projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Automatic date update in version.in
[deliverable/binutils-gdb.git] / opcodes / arc-opc.c
CommitLineData
252b5132 1/* Opcode table for the ARC.
2571583a 2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
886a2506
NC		 3
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
bcee8eb8 5
9b201bb5
NC		 6 This file is part of libopcodes.
7
8 This library is free software; you can redistribute it and/or modify
252b5132 9 it under the terms of the GNU General Public License as published by
9b201bb5 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132
RH		 17
18 You should have received a copy of the GNU General Public License
0d2bcfaf 19 along with this program; if not, write to the Free Software Foundation,
f4321104 20 Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
252b5132 21
5bd67f35 22#include "sysdep.h"
252b5132 23#include <stdio.h>
d943fe33 24#include "bfd.h"
252b5132 25#include "opcode/arc.h"
47b0e7ad 26#include "opintl.h"
886a2506 27#include "libiberty.h"
252b5132 28
e23e8ebe 29/* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom
ce440d63 30 instructions. All NPS400 features are built into all ARC target builds as
e23e8ebe
AB		 31 this reduces the chances that regressions might creep in. */
32
abe7c33b
CZ		 33/* Insert RA register into a 32-bit opcode, with checks. */
34static unsigned long long
35insert_ra_chk (unsigned long long insn,
36 long long int value,
37 const char **errmsg ATTRIBUTE_UNUSED)
38{
39 if (value == 60)
40 *errmsg = _("LP_COUNT register cannot be used as destination register");
41
42 return insn | (value & 0x3F);
43}
886a2506 44/* Insert RB register into a 32-bit opcode. */
bdfe53e3
AB		 45static unsigned long long
46insert_rb (unsigned long long insn,
47 long long int value,
886a2506 48 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 49{
886a2506
NC		 50 return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
51}
0d2bcfaf 52
abe7c33b
CZ		 53/* Insert RB register with checks. */
54static unsigned long long
55insert_rb_chk (unsigned long long insn,
56 long long int value,
57 const char **errmsg ATTRIBUTE_UNUSED)
58{
59 if (value == 60)
60 *errmsg = _("LP_COUNT register cannot be used as destination register");
61
62 return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
63}
64
bdfe53e3
AB		 65static long long int
66extract_rb (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506
NC		 67 bfd_boolean * invalid ATTRIBUTE_UNUSED)
68{
69 int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07);
0d2bcfaf 70
886a2506
NC		 71 if (value == 0x3e && invalid)
72 *invalid = TRUE; /* A limm operand, it should be extracted in a
73 different way. */
252b5132 74
886a2506
NC		 75 return value;
76}
252b5132 77
bdfe53e3
AB		 78static unsigned long long
79insert_rad (unsigned long long insn,
80 long long int value,
886a2506
NC		 81 const char **errmsg ATTRIBUTE_UNUSED)
82{
83 if (value & 0x01)
abe7c33b
CZ		 84 *errmsg = _("cannot use odd number destination register");
85 if (value == 60)
86 *errmsg = _("LP_COUNT register cannot be used as destination register");
0d2bcfaf 87
886a2506
NC		 88 return insn | (value & 0x3F);
89}
0d2bcfaf 90
bdfe53e3
AB		 91static unsigned long long
92insert_rcd (unsigned long long insn,
93 long long int value,
886a2506
NC		 94 const char **errmsg ATTRIBUTE_UNUSED)
95{
96 if (value & 0x01)
abe7c33b 97 *errmsg = _("cannot use odd number source register");
0d2bcfaf 98
886a2506
NC		 99 return insn | ((value & 0x3F) << 6);
100}
252b5132 101
886a2506 102/* Dummy insert ZERO operand function. */
252b5132 103
bdfe53e3
AB		 104static unsigned long long
105insert_za (unsigned long long insn,
106 long long int value,
886a2506
NC		 107 const char **errmsg)
108{
109 if (value)
110 *errmsg = _("operand is not zero");
111 return insn;
112}
252b5132 113
886a2506
NC		 114/* Insert Y-bit in bbit/br instructions. This function is called only
115 when solving fixups. */
252b5132 116
bdfe53e3
AB		 117static unsigned long long
118insert_Ybit (unsigned long long insn,
119 long long int value,
886a2506
NC		 120 const char **errmsg ATTRIBUTE_UNUSED)
121{
122 if (value > 0)
123 insn |= 0x08;
252b5132 124
886a2506
NC		 125 return insn;
126}
252b5132 127
886a2506
NC		 128/* Insert Y-bit in bbit/br instructions. This function is called only
129 when solving fixups. */
252b5132 130
bdfe53e3
AB		 131static unsigned long long
132insert_NYbit (unsigned long long insn,
133 long long int value,
886a2506
NC		 134 const char **errmsg ATTRIBUTE_UNUSED)
135{
136 if (value < 0)
137 insn |= 0x08;
0d2bcfaf 138
886a2506
NC		 139 return insn;
140}
252b5132 141
886a2506 142/* Insert H register into a 16-bit opcode. */
252b5132 143
bdfe53e3
AB		 144static unsigned long long
145insert_rhv1 (unsigned long long insn,
146 long long int value,
886a2506
NC		 147 const char **errmsg ATTRIBUTE_UNUSED)
148{
149 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07);
150}
252b5132 151
bdfe53e3
AB		 152static long long int
153extract_rhv1 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506
NC		 154 bfd_boolean * invalid ATTRIBUTE_UNUSED)
155{
02f3be19 156 int value = ((insn & 0x7) << 3) | ((insn >> 5) & 0x7);
252b5132 157
886a2506
NC		 158 return value;
159}
252b5132 160
886a2506 161/* Insert H register into a 16-bit opcode. */
252b5132 162
bdfe53e3
AB		 163static unsigned long long
164insert_rhv2 (unsigned long long insn,
165 long long int value,
886a2506 166 const char **errmsg)
0d2bcfaf 167{
886a2506
NC		 168 if (value == 0x1E)
169 *errmsg =
abe7c33b 170 _("Register R30 is a limm indicator");
886a2506
NC		 171 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03);
172}
252b5132 173
bdfe53e3
AB		 174static long long int
175extract_rhv2 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506
NC		 176 bfd_boolean * invalid ATTRIBUTE_UNUSED)
177{
178 int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3);
0d2bcfaf 179
886a2506
NC		 180 return value;
181}
0d2bcfaf 182
bdfe53e3
AB		 183static unsigned long long
184insert_r0 (unsigned long long insn,
185 long long int value,
886a2506
NC		 186 const char **errmsg ATTRIBUTE_UNUSED)
187{
188 if (value != 0)
abe7c33b 189 *errmsg = _("Register must be R0");
47b0e7ad
NC		 190 return insn;
191}
252b5132 192
bdfe53e3
AB		 193static long long int
194extract_r0 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 195 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 196{
886a2506 197 return 0;
47b0e7ad 198}
252b5132 199
252b5132 200
bdfe53e3
AB		 201static unsigned long long
202insert_r1 (unsigned long long insn,
203 long long int value,
886a2506 204 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 205{
886a2506 206 if (value != 1)
abe7c33b 207 *errmsg = _("Register must be R1");
47b0e7ad 208 return insn;
252b5132
RH		 209}
210
bdfe53e3
AB		 211static long long int
212extract_r1 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 213 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 214{
886a2506 215 return 1;
252b5132
RH		 216}
217
bdfe53e3
AB		 218static unsigned long long
219insert_r2 (unsigned long long insn,
220 long long int value,
886a2506 221 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 222{
886a2506 223 if (value != 2)
abe7c33b 224 *errmsg = _("Register must be R2");
47b0e7ad 225 return insn;
252b5132
RH		 226}
227
bdfe53e3
AB		 228static long long int
229extract_r2 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 230 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 231{
886a2506 232 return 2;
252b5132
RH		 233}
234
bdfe53e3
AB		 235static unsigned long long
236insert_r3 (unsigned long long insn,
237 long long int value,
886a2506 238 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 239{
886a2506 240 if (value != 3)
abe7c33b 241 *errmsg = _("Register must be R3");
47b0e7ad 242 return insn;
0d2bcfaf
NC		 243}
244
bdfe53e3
AB		 245static long long int
246extract_r3 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 247 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 248{
886a2506 249 return 3;
0d2bcfaf
NC		 250}
251
bdfe53e3
AB		 252static unsigned long long
253insert_sp (unsigned long long insn,
254 long long int value,
886a2506 255 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 256{
886a2506 257 if (value != 28)
abe7c33b 258 *errmsg = _("Register must be SP");
252b5132
RH		 259 return insn;
260}
261
bdfe53e3
AB		 262static long long int
263extract_sp (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 264 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 265{
886a2506 266 return 28;
0d2bcfaf
NC		 267}
268
bdfe53e3
AB		 269static unsigned long long
270insert_gp (unsigned long long insn,
271 long long int value,
886a2506 272 const char **errmsg ATTRIBUTE_UNUSED)
0d2bcfaf 273{
886a2506 274 if (value != 26)
abe7c33b 275 *errmsg = _("Register must be GP");
886a2506 276 return insn;
0d2bcfaf
NC		 277}
278
bdfe53e3
AB		 279static long long int
280extract_gp (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 281 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 282{
886a2506 283 return 26;
0d2bcfaf
NC		 284}
285
bdfe53e3
AB		 286static unsigned long long
287insert_pcl (unsigned long long insn,
288 long long int value,
886a2506 289 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 290{
886a2506 291 if (value != 63)
abe7c33b 292 *errmsg = _("Register must be PCL");
252b5132
RH		 293 return insn;
294}
295
bdfe53e3
AB		 296static long long int
297extract_pcl (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 298 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 299{
886a2506 300 return 63;
0d2bcfaf
NC		 301}
302
bdfe53e3
AB		 303static unsigned long long
304insert_blink (unsigned long long insn,
305 long long int value,
886a2506 306 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 307{
886a2506 308 if (value != 31)
abe7c33b 309 *errmsg = _("Register must be BLINK");
252b5132
RH		 310 return insn;
311}
312
bdfe53e3
AB		 313static long long int
314extract_blink (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 315 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 316{
886a2506 317 return 31;
0d2bcfaf
NC		 318}
319
bdfe53e3
AB		 320static unsigned long long
321insert_ilink1 (unsigned long long insn,
322 long long int value,
886a2506 323 const char **errmsg ATTRIBUTE_UNUSED)
0d2bcfaf 324{
886a2506 325 if (value != 29)
abe7c33b 326 *errmsg = _("Register must be ILINK1");
252b5132
RH		 327 return insn;
328}
329
bdfe53e3
AB		 330static long long int
331extract_ilink1 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 332 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 333{
886a2506 334 return 29;
252b5132
RH		 335}
336
bdfe53e3
AB		 337static unsigned long long
338insert_ilink2 (unsigned long long insn,
339 long long int value,
886a2506 340 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 341{
886a2506 342 if (value != 30)
abe7c33b 343 *errmsg = _("Register must be ILINK2");
252b5132
RH		 344 return insn;
345}
346
bdfe53e3
AB		 347static long long int
348extract_ilink2 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506
NC		 349 bfd_boolean * invalid ATTRIBUTE_UNUSED)
350{
351 return 30;
352}
252b5132 353
bdfe53e3
AB		 354static unsigned long long
355insert_ras (unsigned long long insn,
356 long long int value,
886a2506 357 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 358{
886a2506 359 switch (value)
0d2bcfaf 360 {
886a2506
NC		 361 case 0:
362 case 1:
363 case 2:
364 case 3:
365 insn |= value;
366 break;
367 case 12:
368 case 13:
369 case 14:
370 case 15:
371 insn |= (value - 8);
372 break;
373 default:
abe7c33b 374 *errmsg = _("Register must be either r0-r3 or r12-r15");
886a2506 375 break;
0d2bcfaf 376 }
252b5132
RH		 377 return insn;
378}
252b5132 379
bdfe53e3
AB		 380static long long int
381extract_ras (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 382 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 383{
886a2506
NC		 384 int value = insn & 0x07;
385 if (value > 3)
386 return (value + 8);
387 else
388 return value;
47b0e7ad
NC		 389}
390
bdfe53e3
AB		 391static unsigned long long
392insert_rbs (unsigned long long insn,
393 long long int value,
886a2506 394 const char **errmsg ATTRIBUTE_UNUSED)
252b5132 395{
886a2506 396 switch (value)
47b0e7ad 397 {
886a2506
NC		 398 case 0:
399 case 1:
400 case 2:
401 case 3:
402 insn |= value << 8;
403 break;
404 case 12:
405 case 13:
406 case 14:
407 case 15:
408 insn |= ((value - 8)) << 8;
409 break;
410 default:
abe7c33b 411 *errmsg = _("Register must be either r0-r3 or r12-r15");
886a2506 412 break;
47b0e7ad 413 }
886a2506 414 return insn;
252b5132
RH		 415}
416
bdfe53e3
AB		 417static long long int
418extract_rbs (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 419 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 420{
886a2506
NC		 421 int value = (insn >> 8) & 0x07;
422 if (value > 3)
423 return (value + 8);
424 else
425 return value;
426}
252b5132 427
bdfe53e3
AB		 428static unsigned long long
429insert_rcs (unsigned long long insn,
430 long long int value,
886a2506
NC		 431 const char **errmsg ATTRIBUTE_UNUSED)
432{
433 switch (value)
252b5132 434 {
886a2506
NC		 435 case 0:
436 case 1:
437 case 2:
438 case 3:
439 insn |= value << 5;
440 break;
441 case 12:
442 case 13:
443 case 14:
444 case 15:
445 insn |= ((value - 8)) << 5;
446 break;
447 default:
abe7c33b 448 *errmsg = _("Register must be either r0-r3 or r12-r15");
886a2506 449 break;
252b5132 450 }
886a2506
NC		 451 return insn;
452}
47b0e7ad 453
bdfe53e3
AB		 454static long long int
455extract_rcs (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506
NC		 456 bfd_boolean * invalid ATTRIBUTE_UNUSED)
457{
458 int value = (insn >> 5) & 0x07;
459 if (value > 3)
460 return (value + 8);
252b5132 461 else
886a2506
NC		 462 return value;
463}
47b0e7ad 464
bdfe53e3
AB		 465static unsigned long long
466insert_simm3s (unsigned long long insn,
467 long long int value,
886a2506
NC		 468 const char **errmsg ATTRIBUTE_UNUSED)
469{
470 int tmp = 0;
471 switch (value)
47b0e7ad 472 {
886a2506
NC		 473 case -1:
474 tmp = 0x07;
47b0e7ad 475 break;
886a2506
NC		 476 case 0:
477 tmp = 0x00;
478 break;
479 case 1:
480 tmp = 0x01;
47b0e7ad 481 break;
886a2506
NC		 482 case 2:
483 tmp = 0x02;
47b0e7ad 484 break;
886a2506
NC		 485 case 3:
486 tmp = 0x03;
487 break;
488 case 4:
489 tmp = 0x04;
490 break;
491 case 5:
492 tmp = 0x05;
493 break;
494 case 6:
495 tmp = 0x06;
496 break;
497 default:
abe7c33b 498 *errmsg = _("Accepted values are from -1 to 6");
47b0e7ad
NC		 499 break;
500 }
501
886a2506
NC		 502 insn |= tmp << 8;
503 return insn;
47b0e7ad
NC		 504}
505
bdfe53e3
AB		 506static long long int
507extract_simm3s (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 508 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 509{
886a2506
NC		 510 int value = (insn >> 8) & 0x07;
511 if (value == 7)
512 return -1;
47b0e7ad 513 else
886a2506 514 return value;
47b0e7ad
NC		 515}
516
bdfe53e3
AB		 517static unsigned long long
518insert_rrange (unsigned long long insn,
519 long long int value,
886a2506 520 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 521{
886a2506
NC		 522 int reg1 = (value >> 16) & 0xFFFF;
523 int reg2 = value & 0xFFFF;
524 if (reg1 != 13)
525 {
abe7c33b 526 *errmsg = _("First register of the range should be r13");
886a2506
NC		 527 return insn;
528 }
529 if (reg2 < 13 || reg2 > 26)
530 {
abe7c33b 531 *errmsg = _("Last register of the range doesn't fit");
886a2506
NC		 532 return insn;
533 }
534 insn |= ((reg2 - 12) & 0x0F) << 1;
535 return insn;
47b0e7ad
NC		 536}
537
bdfe53e3
AB		 538static long long int
539extract_rrange (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506
NC		 540 bfd_boolean * invalid ATTRIBUTE_UNUSED)
541{
542 return (insn >> 1) & 0x0F;
543}
47b0e7ad 544
bdfe53e3
AB		 545static unsigned long long
546insert_fpel (unsigned long long insn,
547 long long int value,
886a2506 548 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 549{
886a2506
NC		 550 if (value != 27)
551 {
abe7c33b 552 *errmsg = _("Invalid register number, should be fp");
886a2506
NC		 553 return insn;
554 }
47b0e7ad 555
886a2506
NC		 556 insn |= 0x0100;
557 return insn;
47b0e7ad
NC		 558}
559
bdfe53e3
AB		 560static long long int
561extract_fpel (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 562 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 563{
886a2506 564 return (insn & 0x0100) ? 27 : -1;
47b0e7ad
NC		 565}
566
bdfe53e3
AB		 567static unsigned long long
568insert_blinkel (unsigned long long insn,
569 long long int value,
886a2506 570 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 571{
886a2506 572 if (value != 31)
47b0e7ad 573 {
abe7c33b 574 *errmsg = _("Invalid register number, should be blink");
886a2506 575 return insn;
47b0e7ad 576 }
47b0e7ad 577
886a2506
NC		 578 insn |= 0x0200;
579 return insn;
47b0e7ad
NC		 580}
581
bdfe53e3
AB		 582static long long int
583extract_blinkel (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 584 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 585{
886a2506
NC		 586 return (insn & 0x0200) ? 31 : -1;
587}
47b0e7ad 588
bdfe53e3
AB		 589static unsigned long long
590insert_pclel (unsigned long long insn,
591 long long int value,
886a2506
NC		 592 const char **errmsg ATTRIBUTE_UNUSED)
593{
594 if (value != 63)
47b0e7ad 595 {
abe7c33b 596 *errmsg = _("Invalid register number, should be pcl");
886a2506 597 return insn;
47b0e7ad 598 }
47b0e7ad 599
886a2506
NC		 600 insn |= 0x0400;
601 return insn;
602}
47b0e7ad 603
bdfe53e3
AB		 604static long long int
605extract_pclel (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 606 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 607{
886a2506 608 return (insn & 0x0400) ? 63 : -1;
47b0e7ad 609}
47b0e7ad 610
886a2506
NC		 611#define INSERT_W6
612/* mask = 00000000000000000000111111000000
613 insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */
bdfe53e3
AB		 614static unsigned long long
615insert_w6 (unsigned long long insn ATTRIBUTE_UNUSED,
616 long long int value ATTRIBUTE_UNUSED,
886a2506 617 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 618{
886a2506 619 insn |= ((value >> 0) & 0x003f) << 6;
47b0e7ad 620
886a2506
NC		 621 return insn;
622}
47b0e7ad 623
886a2506
NC		 624#define EXTRACT_W6
625/* mask = 00000000000000000000111111000000. */
bdfe53e3
AB		 626static long long int
627extract_w6 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 628 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 629{
886a2506 630 unsigned value = 0;
47b0e7ad 631
886a2506 632 value |= ((insn >> 6) & 0x003f) << 0;
47b0e7ad 633
886a2506
NC		 634 return value;
635}
47b0e7ad 636
886a2506
NC		 637#define INSERT_G_S
638/* mask = 0000011100022000
639 insn = 01000ggghhhGG0HH. */
bdfe53e3
AB		 640static unsigned long long
641insert_g_s (unsigned long long insn ATTRIBUTE_UNUSED,
642 long long int value ATTRIBUTE_UNUSED,
886a2506 643 const char **errmsg ATTRIBUTE_UNUSED)
47b0e7ad 644{
886a2506
NC		 645 insn |= ((value >> 0) & 0x0007) << 8;
646 insn |= ((value >> 3) & 0x0003) << 3;
252b5132 647
886a2506
NC		 648 return insn;
649}
252b5132 650
886a2506
NC		 651#define EXTRACT_G_S
652/* mask = 0000011100022000. */
bdfe53e3
AB		 653static long long int
654extract_g_s (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506
NC		 655 bfd_boolean * invalid ATTRIBUTE_UNUSED)
656{
657 int value = 0;
252b5132 658
886a2506
NC		 659 value |= ((insn >> 8) & 0x0007) << 0;
660 value |= ((insn >> 3) & 0x0003) << 3;
252b5132 661
886a2506
NC		 662 /* Extend the sign. */
663 int signbit = 1 << (6 - 1);
664 value = (value ^ signbit) - signbit;
252b5132 665
886a2506 666 return value;
252b5132
RH		 667}
668
e23e8ebe 669/* ARC NPS400 Support: See comment near head of file. */
bdfe53e3
AB		 670#define MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(NAME,OFFSET) \
671static unsigned long long \
672insert_nps_3bit_reg_at_##OFFSET##_##NAME \
673 (unsigned long long insn ATTRIBUTE_UNUSED, \
674 long long int value ATTRIBUTE_UNUSED, \
675 const char **errmsg ATTRIBUTE_UNUSED) \
676{ \
677 switch (value) \
678 { \
679 case 0: \
680 case 1: \
681 case 2: \
682 case 3: \
683 insn |= value << (OFFSET); \
684 break; \
685 case 12: \
686 case 13: \
687 case 14: \
688 case 15: \
689 insn |= (value - 8) << (OFFSET); \
690 break; \
691 default: \
abe7c33b 692 *errmsg = _("Register must be either r0-r3 or r12-r15"); \
bdfe53e3
AB		 693 break; \
694 } \
695 return insn; \
696} \
697 \
698static long long int \
699extract_nps_3bit_reg_at_##OFFSET##_##NAME \
700 (unsigned long long insn ATTRIBUTE_UNUSED, \
701 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
702{ \
703 int value = (insn >> (OFFSET)) & 0x07; \
704 if (value > 3) \
705 value += 8; \
706 return value; \
707} \
708
709MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,8)
710MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,24)
711MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,40)
712MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,56)
713
714MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,5)
715MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,21)
716MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,37)
717MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,53)
718
719static unsigned long long
720insert_nps_bitop_size_2b (unsigned long long insn ATTRIBUTE_UNUSED,
721 long long int value ATTRIBUTE_UNUSED,
820f03ff
AB		 722 const char **errmsg ATTRIBUTE_UNUSED)
723{
724 switch (value)
725 {
726 case 1:
727 value = 0;
728 break;
729 case 2:
730 value = 1;
731 break;
732 case 4:
733 value = 2;
734 break;
735 case 8:
736 value = 3;
737 break;
738 default:
739 value = 0;
abe7c33b 740 *errmsg = _("Invalid size, should be 1, 2, 4, or 8");
820f03ff
AB		 741 break;
742 }
743
744 insn |= value << 10;
745 return insn;
746}
747
bdfe53e3
AB		 748static long long int
749extract_nps_bitop_size_2b (unsigned long long insn ATTRIBUTE_UNUSED,
820f03ff
AB		 750 bfd_boolean * invalid ATTRIBUTE_UNUSED)
751{
752 return 1 << ((insn >> 10) & 0x3);
753}
754
bdfe53e3
AB		 755static unsigned long long
756insert_nps_bitop_uimm8 (unsigned long long insn ATTRIBUTE_UNUSED,
757 long long int value ATTRIBUTE_UNUSED,
820f03ff
AB		 758 const char **errmsg ATTRIBUTE_UNUSED)
759{
760 insn |= ((value >> 5) & 7) << 12;
761 insn |= (value & 0x1f);
762 return insn;
763}
764
bdfe53e3
AB		 765static long long int
766extract_nps_bitop_uimm8 (unsigned long long insn ATTRIBUTE_UNUSED,
820f03ff
AB		 767 bfd_boolean * invalid ATTRIBUTE_UNUSED)
768{
769 return (((insn >> 12) & 0x7) << 5) | (insn & 0x1f);
770}
771
bdfe53e3
AB		 772static unsigned long long
773insert_nps_rflt_uimm6 (unsigned long long insn ATTRIBUTE_UNUSED,
774 long long int value ATTRIBUTE_UNUSED,
820f03ff
AB		 775 const char **errmsg ATTRIBUTE_UNUSED)
776{
777 switch (value)
778 {
779 case 1:
780 case 2:
781 case 4:
782 break;
783
784 default:
785 *errmsg = _("invalid immediate, must be 1, 2, or 4");
786 value = 0;
787 }
788
789 insn |= (value << 6);
790 return insn;
791}
792
bdfe53e3
AB		 793static long long int
794extract_nps_rflt_uimm6 (unsigned long long insn ATTRIBUTE_UNUSED,
820f03ff
AB		 795 bfd_boolean * invalid ATTRIBUTE_UNUSED)
796{
797 return (insn >> 6) & 0x3f;
798}
799
bdfe53e3
AB		 800static unsigned long long
801insert_nps_dst_pos_and_size (unsigned long long insn ATTRIBUTE_UNUSED,
802 long long int value ATTRIBUTE_UNUSED,
820f03ff
AB		 803 const char **errmsg ATTRIBUTE_UNUSED)
804{
805 insn |= ((value & 0x1f) | (((32 - value - 1) & 0x1f) << 10));
806 return insn;
807}
808
bdfe53e3
AB		 809static long long int
810extract_nps_dst_pos_and_size (unsigned long long insn ATTRIBUTE_UNUSED,
820f03ff
AB		 811 bfd_boolean * invalid ATTRIBUTE_UNUSED)
812{
813 return (insn & 0x1f);
814}
815
bdfe53e3
AB		 816static unsigned long long
817insert_nps_cmem_uimm16 (unsigned long long insn ATTRIBUTE_UNUSED,
818 long long int value ATTRIBUTE_UNUSED,
4b0c052e
AB		 819 const char **errmsg ATTRIBUTE_UNUSED)
820{
821 int top = (value >> 16) & 0xffff;
822 if (top != 0x0 && top != NPS_CMEM_HIGH_VALUE)
823 *errmsg = _("invalid value for CMEM ld/st immediate");
824 insn |= (value & 0xffff);
825 return insn;
826}
827
bdfe53e3
AB		 828static long long int
829extract_nps_cmem_uimm16 (unsigned long long insn ATTRIBUTE_UNUSED,
4b0c052e
AB		 830 bfd_boolean * invalid ATTRIBUTE_UNUSED)
831{
832 return (NPS_CMEM_HIGH_VALUE << 16) | (insn & 0xffff);
833}
834
645d3342
RZ		 835static unsigned long long int
836insert_nps_imm_offset (unsigned long long insn ATTRIBUTE_UNUSED,
837 long long int value ATTRIBUTE_UNUSED,
838 const char **errmsg ATTRIBUTE_UNUSED)
839{
840 switch (value)
841 {
842 case 0:
843 case 16:
844 case 32:
845 case 48:
846 case 64:
847 value = value >> 4;
848 break;
849 default:
850 *errmsg = _("Invalid position, should be 0, 16, 32, 48 or 64.");
851 value = 0;
852 }
853 insn |= (value << 10);
854 return insn;
855}
856
857static long long int
858extract_nps_imm_offset (unsigned long long insn ATTRIBUTE_UNUSED,
859 bfd_boolean * invalid ATTRIBUTE_UNUSED)
860{
861 return ((insn >> 10) & 0x7) * 16;
862}
863
864static unsigned long long
865insert_nps_imm_entry (unsigned long long insn ATTRIBUTE_UNUSED,
866 long long value ATTRIBUTE_UNUSED,
867 const char **errmsg ATTRIBUTE_UNUSED)
868{
869 switch (value)
870 {
871 case 16:
872 value = 0;
873 break;
874 case 32:
875 value = 1;
876 break;
877 case 64:
878 value = 2;
879 break;
880 case 128:
881 value = 3;
882 break;
883 default:
884 *errmsg = _("Invalid position, should be 16, 32, 64 or 128.");
885 value = 0;
886 }
887 insn |= (value << 2);
888 return insn;
889}
890
891static long long int
892extract_nps_imm_entry (unsigned long long insn ATTRIBUTE_UNUSED,
893 bfd_boolean * invalid ATTRIBUTE_UNUSED)
894{
895 int imm_entry = ((insn >> 2) & 0x7);
896 return (1 << (imm_entry + 4));
897}
898
537aefaf 899#define MAKE_SRC_POS_INSERT_EXTRACT_FUNCS(NAME,SHIFT) \
bdfe53e3
AB		 900static unsigned long long \
901insert_nps_##NAME##_pos (unsigned long long insn ATTRIBUTE_UNUSED, \
902 long long int value ATTRIBUTE_UNUSED, \
537aefaf
AB		 903 const char **errmsg ATTRIBUTE_UNUSED) \
904{ \
905 switch (value) \
906 { \
907 case 0: \
908 case 8: \
909 case 16: \
910 case 24: \
911 value = value / 8; \
912 break; \
913 default: \
abe7c33b 914 *errmsg = _("Invalid position, should be 0, 8, 16, or 24"); \
537aefaf
AB		 915 value = 0; \
916 } \
917 insn |= (value << SHIFT); \
918 return insn; \
919} \
920 \
bdfe53e3
AB		 921static long long int \
922extract_nps_##NAME##_pos (unsigned long long insn ATTRIBUTE_UNUSED, \
537aefaf
AB		 923 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
924{ \
925 return ((insn >> SHIFT) & 0x3) * 8; \
926}
927
928MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src2, 12)
929MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src1, 10)
930
9ba75c88 931#define MAKE_BIAS_INSERT_EXTRACT_FUNCS(NAME,LOWER,UPPER,BITS,BIAS,SHIFT)\
bdfe53e3
AB		 932static unsigned long long \
933insert_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
934 long long int value ATTRIBUTE_UNUSED, \
9ba75c88 935 const char **errmsg ATTRIBUTE_UNUSED) \
537aefaf 936 { \
9ba75c88 937 if (value < LOWER || value > UPPER) \
537aefaf
AB		 938 { \
939 *errmsg = _("Invalid size, value must be " \
940 #LOWER " to " #UPPER "."); \
941 return insn; \
942 } \
943 value -= BIAS; \
944 insn |= (value << SHIFT); \
945 return insn; \
946 } \
947 \
bdfe53e3
AB		 948static long long int \
949extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
9ba75c88 950 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
537aefaf
AB		 951{ \
952 return ((insn >> SHIFT) & ((1 << BITS) - 1)) + BIAS; \
953}
954
db18dbab
GM		 955MAKE_BIAS_INSERT_EXTRACT_FUNCS (addb_size,2,32,5,1,5)
956MAKE_BIAS_INSERT_EXTRACT_FUNCS (andb_size,1,32,5,1,5)
957MAKE_BIAS_INSERT_EXTRACT_FUNCS (fxorb_size,8,32,5,8,5)
958MAKE_BIAS_INSERT_EXTRACT_FUNCS (wxorb_size,16,32,5,16,5)
959MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop_size,1,32,5,1,10)
960MAKE_BIAS_INSERT_EXTRACT_FUNCS (qcmp_size,1,8,3,1,9)
961MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop1_size,1,32,5,1,20)
962MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop2_size,1,32,5,1,25)
963MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_width,1,32,5,1,6)
964MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_len,1,8,3,1,2)
965MAKE_BIAS_INSERT_EXTRACT_FUNCS (index3,4,7,2,4,0)
537aefaf 966
bdfe53e3
AB		 967static long long int
968extract_nps_qcmp_m3 (unsigned long long insn ATTRIBUTE_UNUSED,
537aefaf
AB		 969 bfd_boolean * invalid ATTRIBUTE_UNUSED)
970{
971 int m3 = (insn >> 5) & 0xf;
972 if (m3 == 0xf)
973 *invalid = TRUE;
974 return m3;
975}
976
bdfe53e3
AB		 977static long long int
978extract_nps_qcmp_m2 (unsigned long long insn ATTRIBUTE_UNUSED,
537aefaf
AB		 979 bfd_boolean * invalid ATTRIBUTE_UNUSED)
980{
981 bfd_boolean tmp_invalid = FALSE;
982 int m2 = (insn >> 15) & 0x1;
983 int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
984
985 if (m2 == 0 && m3 == 0xf)
986 *invalid = TRUE;
987 return m2;
988}
989
bdfe53e3
AB		 990static long long int
991extract_nps_qcmp_m1 (unsigned long long insn ATTRIBUTE_UNUSED,
537aefaf
AB		 992 bfd_boolean * invalid ATTRIBUTE_UNUSED)
993{
994 bfd_boolean tmp_invalid = FALSE;
995 int m1 = (insn >> 14) & 0x1;
996 int m2 = extract_nps_qcmp_m2 (insn, &tmp_invalid);
997 int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
998
999 if (m1 == 0 && m2 == 0 && m3 == 0xf)
1000 *invalid = TRUE;
1001 return m1;
1002}
1003
bdfe53e3
AB		 1004static unsigned long long
1005insert_nps_calc_entry_size (unsigned long long insn ATTRIBUTE_UNUSED,
1006 long long int value ATTRIBUTE_UNUSED,
537aefaf
AB		 1007 const char **errmsg ATTRIBUTE_UNUSED)
1008{
1009 unsigned pwr;
1010
1011 if (value < 1 || value > 256)
1012 {
1013 *errmsg = _("value out of range 1 - 256");
1014 return 0;
1015 }
1016
1017 for (pwr = 0; (value & 1) == 0; value >>= 1)
1018 ++pwr;
1019
1020 if (value != 1)
1021 {
1022 *errmsg = _("value must be power of 2");
1023 return 0;
1024 }
1025
1026 return insn | (pwr << 8);
1027}
1028
bdfe53e3
AB		 1029static long long int
1030extract_nps_calc_entry_size (unsigned long long insn ATTRIBUTE_UNUSED,
537aefaf
AB		 1031 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1032{
1033 unsigned entry_size = (insn >> 8) & 0xf;
1034 return 1 << entry_size;
1035}
1036
bdfe53e3
AB		 1037static unsigned long long
1038insert_nps_bitop_mod4 (unsigned long long insn ATTRIBUTE_UNUSED,
1039 long long int value ATTRIBUTE_UNUSED,
4eb6f892
AB		 1040 const char **errmsg ATTRIBUTE_UNUSED)
1041{
bdfe53e3 1042 return insn | ((value & 0x2) << 30) | ((value & 0x1) << 47);
4eb6f892
AB		 1043}
1044
bdfe53e3
AB		 1045static long long int
1046extract_nps_bitop_mod4 (unsigned long long insn ATTRIBUTE_UNUSED,
4eb6f892
AB		 1047 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1048{
bdfe53e3 1049 return ((insn >> 30) & 0x2) | ((insn >> 47) & 0x1);
4eb6f892
AB		 1050}
1051
bdfe53e3
AB		 1052static unsigned long long
1053insert_nps_bitop_dst_pos3_pos4 (unsigned long long insn ATTRIBUTE_UNUSED,
1054 long long int value ATTRIBUTE_UNUSED,
4eb6f892
AB		 1055 const char **errmsg ATTRIBUTE_UNUSED)
1056{
bdfe53e3 1057 return insn | (value << 42) | (value << 37);
4eb6f892
AB		 1058}
1059
bdfe53e3
AB		 1060static long long int
1061extract_nps_bitop_dst_pos3_pos4 (unsigned long long insn ATTRIBUTE_UNUSED,
4eb6f892
AB		 1062 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1063{
bdfe53e3 1064 if (((insn >> 42) & 0x1f) != ((insn >> 37) & 0x1f))
4eb6f892 1065 *invalid = TRUE;
bdfe53e3 1066 return ((insn >> 37) & 0x1f);
4eb6f892
AB		 1067}
1068
bdfe53e3
AB		 1069static unsigned long long
1070insert_nps_bitop_ins_ext (unsigned long long insn ATTRIBUTE_UNUSED,
1071 long long int value ATTRIBUTE_UNUSED,
4eb6f892
AB		 1072 const char **errmsg ATTRIBUTE_UNUSED)
1073{
1074 if (value < 0 || value > 28)
1075 *errmsg = _("Value must be in the range 0 to 28");
1076 return insn | (value << 20);
1077}
1078
bdfe53e3
AB		 1079static long long int
1080extract_nps_bitop_ins_ext (unsigned long long insn ATTRIBUTE_UNUSED,
4eb6f892
AB		 1081 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1082{
1083 int value = (insn >> 20) & 0x1f;
1084 if (value > 28)
1085 *invalid = TRUE;
1086 return value;
1087}
1088
14053c19 1089#define MAKE_1BASED_INSERT_EXTRACT_FUNCS(NAME,SHIFT,UPPER,BITS) \
bdfe53e3
AB		 1090static unsigned long long \
1091insert_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
1092 long long int value ATTRIBUTE_UNUSED, \
14053c19
GM		 1093 const char **errmsg ATTRIBUTE_UNUSED) \
1094{ \
1095 if (value < 1 || value > UPPER) \
1096 *errmsg = _("Value must be in the range 1 to " #UPPER); \
1097 if (value == UPPER) \
1098 value = 0; \
1099 return insn | (value << SHIFT); \
1100} \
1101 \
bdfe53e3
AB		 1102static long long int \
1103extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
14053c19
GM		 1104 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
1105{ \
1106 int value = (insn >> SHIFT) & ((1 << BITS) - 1); \
1107 if (value == 0) \
1108 value = UPPER; \
1109 return value; \
1110}
1111
db18dbab
GM		 1112MAKE_1BASED_INSERT_EXTRACT_FUNCS (field_size, 6, 8, 3)
1113MAKE_1BASED_INSERT_EXTRACT_FUNCS (shift_factor, 9, 8, 3)
1114MAKE_1BASED_INSERT_EXTRACT_FUNCS (bits_to_scramble, 12, 8, 3)
1115MAKE_1BASED_INSERT_EXTRACT_FUNCS (bdlen_max_len, 5, 256, 8)
1116MAKE_1BASED_INSERT_EXTRACT_FUNCS (bd_num_buff, 6, 8, 3)
1117MAKE_1BASED_INSERT_EXTRACT_FUNCS (pmu_num_job, 6, 4, 2)
5a736821 1118MAKE_1BASED_INSERT_EXTRACT_FUNCS (proto_size, 16, 64, 6)
14053c19 1119
bdfe53e3
AB		 1120static unsigned long long
1121insert_nps_min_hofs (unsigned long long insn ATTRIBUTE_UNUSED,
1122 long long int value ATTRIBUTE_UNUSED,
14053c19
GM		 1123 const char **errmsg ATTRIBUTE_UNUSED)
1124{
1125 if (value < 0 || value > 240)
1126 *errmsg = _("Value must be in the range 0 to 240");
1127 if ((value % 16) != 0)
1128 *errmsg = _("Value must be a multiple of 16");
1129 value = value / 16;
1130 return insn | (value << 6);
1131}
1132
bdfe53e3
AB		 1133static long long int
1134extract_nps_min_hofs (unsigned long long insn ATTRIBUTE_UNUSED,
14053c19
GM		 1135 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1136{
1137 int value = (insn >> 6) & 0xF;
1138 return value * 16;
1139}
1140
db18dbab 1141#define MAKE_INSERT_NPS_ADDRTYPE(NAME,VALUE) \
bdfe53e3
AB		 1142static unsigned long long \
1143insert_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
1144 long long int value ATTRIBUTE_UNUSED, \
db18dbab
GM		 1145 const char **errmsg ATTRIBUTE_UNUSED) \
1146{ \
1147 if (value != ARC_NPS400_ADDRTYPE_##VALUE) \
1148 *errmsg = _("Invalid address type for operand"); \
1149 return insn; \
1150} \
1151 \
bdfe53e3
AB		 1152static long long int \
1153extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
db18dbab
GM		 1154 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
1155{ \
1156 return ARC_NPS400_ADDRTYPE_##VALUE; \
1157}
1158
1159MAKE_INSERT_NPS_ADDRTYPE (bd, BD)
1160MAKE_INSERT_NPS_ADDRTYPE (jid, JID)
1161MAKE_INSERT_NPS_ADDRTYPE (lbd, LBD)
1162MAKE_INSERT_NPS_ADDRTYPE (mbd, MBD)
1163MAKE_INSERT_NPS_ADDRTYPE (sd, SD)
1164MAKE_INSERT_NPS_ADDRTYPE (sm, SM)
1165MAKE_INSERT_NPS_ADDRTYPE (xa, XA)
1166MAKE_INSERT_NPS_ADDRTYPE (xd, XD)
1167MAKE_INSERT_NPS_ADDRTYPE (cd, CD)
1168MAKE_INSERT_NPS_ADDRTYPE (cbd, CBD)
1169MAKE_INSERT_NPS_ADDRTYPE (cjid, CJID)
1170MAKE_INSERT_NPS_ADDRTYPE (clbd, CLBD)
1171MAKE_INSERT_NPS_ADDRTYPE (cm, CM)
1172MAKE_INSERT_NPS_ADDRTYPE (csd, CSD)
1173MAKE_INSERT_NPS_ADDRTYPE (cxa, CXA)
1174MAKE_INSERT_NPS_ADDRTYPE (cxd, CXD)
1175
5a736821
GM		 1176static unsigned long long
1177insert_nps_rbdouble_64 (unsigned long long insn ATTRIBUTE_UNUSED,
1178 long long int value ATTRIBUTE_UNUSED,
1179 const char **errmsg ATTRIBUTE_UNUSED)
1180{
1181 if (value < 0 || value > 31)
1182 *errmsg = _("Value must be in the range 0 to 31");
1183 return insn | (value << 43) | (value << 48);
1184}
1185
1186
1187static long long int
1188extract_nps_rbdouble_64 (unsigned long long insn ATTRIBUTE_UNUSED,
1189 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1190{
1191 int value1 = (insn >> 43) & 0x1F;
1192 int value2 = (insn >> 48) & 0x1F;
1193
1194 if (value1 != value2)
1195 *invalid = TRUE;
1196
1197 return value1;
1198}
1199
886a2506
NC		 1200/* Include the generic extract/insert functions. Order is important
1201 as some of the functions present in the .h may be disabled via
1202 defines. */
1203#include "arc-fxi.h"
252b5132 1204
886a2506 1205/* The flag operands table.
252b5132 1206
886a2506
NC		 1207 The format of the table is
1208 NAME CODE BITS SHIFT FAVAIL. */
1209const struct arc_flag_operand arc_flag_operands[] =
1210{
1211#define F_NULL 0
1212 { 0, 0, 0, 0, 0},
1213#define F_ALWAYS (F_NULL + 1)
1214 { "al", 0, 0, 0, 0 },
1215#define F_RA (F_ALWAYS + 1)
1216 { "ra", 0, 0, 0, 0 },
1217#define F_EQUAL (F_RA + 1)
1218 { "eq", 1, 5, 0, 1 },
1219#define F_ZERO (F_EQUAL + 1)
1220 { "z", 1, 5, 0, 0 },
1221#define F_NOTEQUAL (F_ZERO + 1)
1222 { "ne", 2, 5, 0, 1 },
1223#define F_NOTZERO (F_NOTEQUAL + 1)
1224 { "nz", 2, 5, 0, 0 },
1225#define F_POZITIVE (F_NOTZERO + 1)
1226 { "p", 3, 5, 0, 1 },
1227#define F_PL (F_POZITIVE + 1)
1228 { "pl", 3, 5, 0, 0 },
1229#define F_NEGATIVE (F_PL + 1)
1230 { "n", 4, 5, 0, 1 },
1231#define F_MINUS (F_NEGATIVE + 1)
1232 { "mi", 4, 5, 0, 0 },
1233#define F_CARRY (F_MINUS + 1)
1234 { "c", 5, 5, 0, 1 },
1235#define F_CARRYSET (F_CARRY + 1)
1236 { "cs", 5, 5, 0, 0 },
1237#define F_LOWER (F_CARRYSET + 1)
1238 { "lo", 5, 5, 0, 0 },
1239#define F_CARRYCLR (F_LOWER + 1)
1240 { "cc", 6, 5, 0, 0 },
1241#define F_NOTCARRY (F_CARRYCLR + 1)
1242 { "nc", 6, 5, 0, 1 },
1243#define F_HIGHER (F_NOTCARRY + 1)
1244 { "hs", 6, 5, 0, 0 },
1245#define F_OVERFLOWSET (F_HIGHER + 1)
1246 { "vs", 7, 5, 0, 0 },
1247#define F_OVERFLOW (F_OVERFLOWSET + 1)
1248 { "v", 7, 5, 0, 1 },
1249#define F_NOTOVERFLOW (F_OVERFLOW + 1)
1250 { "nv", 8, 5, 0, 1 },
1251#define F_OVERFLOWCLR (F_NOTOVERFLOW + 1)
1252 { "vc", 8, 5, 0, 0 },
1253#define F_GT (F_OVERFLOWCLR + 1)
1254 { "gt", 9, 5, 0, 1 },
1255#define F_GE (F_GT + 1)
1256 { "ge", 10, 5, 0, 1 },
1257#define F_LT (F_GE + 1)
1258 { "lt", 11, 5, 0, 1 },
1259#define F_LE (F_LT + 1)
1260 { "le", 12, 5, 0, 1 },
1261#define F_HI (F_LE + 1)
1262 { "hi", 13, 5, 0, 1 },
1263#define F_LS (F_HI + 1)
1264 { "ls", 14, 5, 0, 1 },
1265#define F_PNZ (F_LS + 1)
1266 { "pnz", 15, 5, 0, 1 },
1267
1268 /* FLAG. */
1269#define F_FLAG (F_PNZ + 1)
1270 { "f", 1, 1, 15, 1 },
1271#define F_FFAKE (F_FLAG + 1)
1272 { "f", 0, 0, 0, 1 },
1273
1274 /* Delay slot. */
1275#define F_ND (F_FFAKE + 1)
1276 { "nd", 0, 1, 5, 0 },
1277#define F_D (F_ND + 1)
1278 { "d", 1, 1, 5, 1 },
1279#define F_DFAKE (F_D + 1)
1280 { "d", 0, 0, 0, 1 },
2b848ebd
CZ		 1281#define F_DNZ_ND (F_DFAKE + 1)
1282 { "nd", 0, 1, 16, 0 },
1283#define F_DNZ_D (F_DNZ_ND + 1)
1284 { "d", 1, 1, 16, 1 },
886a2506
NC		 1285
1286 /* Data size. */
2b848ebd 1287#define F_SIZEB1 (F_DNZ_D + 1)
886a2506
NC		 1288 { "b", 1, 2, 1, 1 },
1289#define F_SIZEB7 (F_SIZEB1 + 1)
1290 { "b", 1, 2, 7, 1 },
1291#define F_SIZEB17 (F_SIZEB7 + 1)
1292 { "b", 1, 2, 17, 1 },
1293#define F_SIZEW1 (F_SIZEB17 + 1)
1294 { "w", 2, 2, 1, 0 },
1295#define F_SIZEW7 (F_SIZEW1 + 1)
1296 { "w", 2, 2, 7, 0 },
1297#define F_SIZEW17 (F_SIZEW7 + 1)
1298 { "w", 2, 2, 17, 0 },
1299
1300 /* Sign extension. */
1301#define F_SIGN6 (F_SIZEW17 + 1)
1302 { "x", 1, 1, 6, 1 },
1303#define F_SIGN16 (F_SIGN6 + 1)
1304 { "x", 1, 1, 16, 1 },
1305#define F_SIGNX (F_SIGN16 + 1)
1306 { "x", 0, 0, 0, 1 },
1307
1308 /* Address write-back modes. */
1309#define F_A3 (F_SIGNX + 1)
1310 { "a", 1, 2, 3, 0 },
1311#define F_A9 (F_A3 + 1)
1312 { "a", 1, 2, 9, 0 },
1313#define F_A22 (F_A9 + 1)
1314 { "a", 1, 2, 22, 0 },
1315#define F_AW3 (F_A22 + 1)
1316 { "aw", 1, 2, 3, 1 },
1317#define F_AW9 (F_AW3 + 1)
1318 { "aw", 1, 2, 9, 1 },
1319#define F_AW22 (F_AW9 + 1)
1320 { "aw", 1, 2, 22, 1 },
1321#define F_AB3 (F_AW22 + 1)
1322 { "ab", 2, 2, 3, 1 },
1323#define F_AB9 (F_AB3 + 1)
1324 { "ab", 2, 2, 9, 1 },
1325#define F_AB22 (F_AB9 + 1)
1326 { "ab", 2, 2, 22, 1 },
1327#define F_AS3 (F_AB22 + 1)
1328 { "as", 3, 2, 3, 1 },
1329#define F_AS9 (F_AS3 + 1)
1330 { "as", 3, 2, 9, 1 },
1331#define F_AS22 (F_AS9 + 1)
1332 { "as", 3, 2, 22, 1 },
1333#define F_ASFAKE (F_AS22 + 1)
1334 { "as", 0, 0, 0, 1 },
1335
1336 /* Cache bypass. */
1337#define F_DI5 (F_ASFAKE + 1)
1338 { "di", 1, 1, 5, 1 },
1339#define F_DI11 (F_DI5 + 1)
1340 { "di", 1, 1, 11, 1 },
b437d035
AB		 1341#define F_DI14 (F_DI11 + 1)
1342 { "di", 1, 1, 14, 1 },
1343#define F_DI15 (F_DI14 + 1)
886a2506
NC		 1344 { "di", 1, 1, 15, 1 },
1345
1346 /* ARCv2 specific. */
1347#define F_NT (F_DI15 + 1)
1348 { "nt", 0, 1, 3, 1},
1349#define F_T (F_NT + 1)
1350 { "t", 1, 1, 3, 1},
1351#define F_H1 (F_T + 1)
1352 { "h", 2, 2, 1, 1 },
1353#define F_H7 (F_H1 + 1)
1354 { "h", 2, 2, 7, 1 },
1355#define F_H17 (F_H7 + 1)
1356 { "h", 2, 2, 17, 1 },
6ec7c1ae
CZ		 1357#define F_SIZED (F_H17 + 1)
1358 { "dd", 8, 0, 0, 0 }, /* Fake. */
886a2506
NC		 1359
1360 /* Fake Flags. */
6ec7c1ae 1361#define F_NE (F_SIZED + 1)
886a2506 1362 { "ne", 0, 0, 0, 1 },
e23e8ebe
AB		 1363
1364 /* ARC NPS400 Support: See comment near head of file. */
1365#define F_NPS_CL (F_NE + 1)
1366 { "cl", 0, 0, 0, 1 },
1367
645d3342
RZ		 1368#define F_NPS_NA (F_NPS_CL + 1)
1369 { "na", 1, 1, 9, 1 },
1370
1371#define F_NPS_FLAG (F_NPS_NA + 1)
e23e8ebe 1372 { "f", 1, 1, 20, 1 },
820f03ff
AB		 1373
1374#define F_NPS_R (F_NPS_FLAG + 1)
1375 { "r", 1, 1, 15, 1 },
a42a4f84
AB		 1376
1377#define F_NPS_RW (F_NPS_R + 1)
1378 { "rw", 0, 1, 7, 1 },
1379
1380#define F_NPS_RD (F_NPS_RW + 1)
1381 { "rd", 1, 1, 7, 1 },
1382
1383#define F_NPS_WFT (F_NPS_RD + 1)
1384 { "wft", 0, 0, 0, 1 },
1385
1386#define F_NPS_IE1 (F_NPS_WFT + 1)
1387 { "ie1", 1, 2, 8, 1 },
1388
1389#define F_NPS_IE2 (F_NPS_IE1 + 1)
1390 { "ie2", 2, 2, 8, 1 },
1391
1392#define F_NPS_IE12 (F_NPS_IE2 + 1)
1393 { "ie12", 3, 2, 8, 1 },
1394
1395#define F_NPS_SYNC_RD (F_NPS_IE12 + 1)
1396 { "rd", 0, 1, 6, 1 },
1397
1398#define F_NPS_SYNC_WR (F_NPS_SYNC_RD + 1)
1399 { "wr", 1, 1, 6, 1 },
1400
1401#define F_NPS_HWS_OFF (F_NPS_SYNC_WR + 1)
1402 { "off", 0, 0, 0, 1 },
1403
1404#define F_NPS_HWS_RESTORE (F_NPS_HWS_OFF + 1)
1405 { "restore", 0, 0, 0, 1 },
1406
537aefaf
AB		 1407#define F_NPS_SX (F_NPS_HWS_RESTORE + 1)
1408 { "sx", 1, 1, 14, 1 },
1409
1410#define F_NPS_AR (F_NPS_SX + 1)
1411 { "ar", 0, 1, 0, 1 },
1412
1413#define F_NPS_AL (F_NPS_AR + 1)
1414 { "al", 1, 1, 0, 1 },
14053c19
GM		 1415
1416#define F_NPS_S (F_NPS_AL + 1)
1417 { "s", 0, 0, 0, 1 },
1418
1419#define F_NPS_ZNCV_RD (F_NPS_S + 1)
1420 { "rd", 0, 1, 15, 1 },
1421
1422#define F_NPS_ZNCV_WR (F_NPS_ZNCV_RD + 1)
1423 { "wr", 1, 1, 15, 1 },
9ba75c88
GM		 1424
1425#define F_NPS_P0 (F_NPS_ZNCV_WR + 1)
1426 { "p0", 0, 0, 0, 1 },
1427
1428#define F_NPS_P1 (F_NPS_P0 + 1)
1429 { "p1", 0, 0, 0, 1 },
1430
1431#define F_NPS_P2 (F_NPS_P1 + 1)
1432 { "p2", 0, 0, 0, 1 },
1433
1434#define F_NPS_P3 (F_NPS_P2 + 1)
1435 { "p3", 0, 0, 0, 1 },
28215275
GM		 1436
1437#define F_NPS_LDBIT_DI (F_NPS_P3 + 1)
1438 { "di", 0, 0, 0, 1 },
1439
1440#define F_NPS_LDBIT_CL1 (F_NPS_LDBIT_DI + 1)
1441 { "cl", 1, 1, 6, 1 },
1442
1443#define F_NPS_LDBIT_CL2 (F_NPS_LDBIT_CL1 + 1)
1444 { "cl", 1, 1, 16, 1 },
1445
1446#define F_NPS_LDBIT_X2_1 (F_NPS_LDBIT_CL2 + 1)
1447 { "x2", 1, 2, 9, 1 },
1448
1449#define F_NPS_LDBIT_X2_2 (F_NPS_LDBIT_X2_1 + 1)
1450 { "x2", 1, 2, 22, 1 },
1451
1452#define F_NPS_LDBIT_X4_1 (F_NPS_LDBIT_X2_2 + 1)
1453 { "x4", 2, 2, 9, 1 },
1454
1455#define F_NPS_LDBIT_X4_2 (F_NPS_LDBIT_X4_1 + 1)
1456 { "x4", 2, 2, 22, 1 },
886a2506 1457};
252b5132 1458
886a2506 1459const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
252b5132 1460
886a2506 1461/* Table of the flag classes.
252b5132 1462
886a2506
NC		 1463 The format of the table is
1464 CLASS {FLAG_CODE}. */
1465const struct arc_flag_class arc_flag_classes[] =
1466{
1467#define C_EMPTY 0
1ae8ab47 1468 { F_CLASS_NONE, { F_NULL } },
886a2506 1469
6ec7c1ae
CZ		 1470#define C_CC_EQ (C_EMPTY + 1)
1471 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_EQUAL, F_NULL} },
1472
1473#define C_CC_GE (C_CC_EQ + 1)
1474 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GE, F_NULL} },
1475
1476#define C_CC_GT (C_CC_GE + 1)
1477 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GT, F_NULL} },
1478
1479#define C_CC_HI (C_CC_GT + 1)
1480 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_HI, F_NULL} },
1481
1482#define C_CC_HS (C_CC_HI + 1)
1483 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTCARRY, F_NULL} },
1484
1485#define C_CC_LE (C_CC_HS + 1)
1486 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LE, F_NULL} },
1487
1488#define C_CC_LO (C_CC_LE + 1)
1489 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_CARRY, F_NULL} },
1490
1491#define C_CC_LS (C_CC_LO + 1)
1492 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LS, F_NULL} },
1493
1494#define C_CC_LT (C_CC_LS + 1)
1495 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LT, F_NULL} },
1496
1497#define C_CC_NE (C_CC_LT + 1)
1498 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTEQUAL, F_NULL} },
1499
1500#define C_AA_AB (C_CC_NE + 1)
1501 {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AB3, F_NULL} },
1502
1503#define C_AA_AW (C_AA_AB + 1)
1504 {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AW3, F_NULL} },
1505
1506#define C_ZZ_D (C_AA_AW + 1)
1507 {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZED, F_NULL} },
1508
1509#define C_ZZ_H (C_ZZ_D + 1)
1510 {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_H1, F_NULL} },
1511
1512#define C_ZZ_B (C_ZZ_H + 1)
1513 {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZEB1, F_NULL} },
1514
1515#define C_CC (C_ZZ_B + 1)
d9eca1df 1516 { F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND,
f36e33da
CZ		 1517 { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL,
1518 F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS,
1519 F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1520 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW,
1521 F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT,
1522 F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
886a2506
NC		 1523
1524#define C_AA_ADDR3 (C_CC + 1)
1525#define C_AA27 (C_CC + 1)
6ec7c1ae 1526 { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } },
886a2506
NC		 1527#define C_AA_ADDR9 (C_AA_ADDR3 + 1)
1528#define C_AA21 (C_AA_ADDR3 + 1)
6ec7c1ae 1529 { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } },
886a2506
NC		 1530#define C_AA_ADDR22 (C_AA_ADDR9 + 1)
1531#define C_AA8 (C_AA_ADDR9 + 1)
6ec7c1ae 1532 { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } },
886a2506
NC		 1533
1534#define C_F (C_AA_ADDR22 + 1)
1ae8ab47 1535 { F_CLASS_OPTIONAL, { F_FLAG, F_NULL } },
886a2506 1536#define C_FHARD (C_F + 1)
1ae8ab47 1537 { F_CLASS_OPTIONAL, { F_FFAKE, F_NULL } },
886a2506
NC		 1538
1539#define C_T (C_FHARD + 1)
1ae8ab47 1540 { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } },
886a2506 1541#define C_D (C_T + 1)
1ae8ab47 1542 { F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL } },
2b848ebd
CZ		 1543#define C_DNZ_D (C_D + 1)
1544 { F_CLASS_OPTIONAL, { F_DNZ_ND, F_DNZ_D, F_NULL } },
886a2506 1545
2b848ebd 1546#define C_DHARD (C_DNZ_D + 1)
1ae8ab47 1547 { F_CLASS_OPTIONAL, { F_DFAKE, F_NULL } },
886a2506
NC		 1548
1549#define C_DI20 (C_DHARD + 1)
1ae8ab47 1550 { F_CLASS_OPTIONAL, { F_DI11, F_NULL }},
b437d035
AB		 1551#define C_DI14 (C_DI20 + 1)
1552 { F_CLASS_OPTIONAL, { F_DI14, F_NULL }},
1553#define C_DI16 (C_DI14 + 1)
1ae8ab47 1554 { F_CLASS_OPTIONAL, { F_DI15, F_NULL }},
886a2506 1555#define C_DI26 (C_DI16 + 1)
1ae8ab47 1556 { F_CLASS_OPTIONAL, { F_DI5, F_NULL }},
886a2506
NC		 1557
1558#define C_X25 (C_DI26 + 1)
1ae8ab47 1559 { F_CLASS_OPTIONAL, { F_SIGN6, F_NULL }},
886a2506 1560#define C_X15 (C_X25 + 1)
1ae8ab47 1561 { F_CLASS_OPTIONAL, { F_SIGN16, F_NULL }},
886a2506
NC		 1562#define C_XHARD (C_X15 + 1)
1563#define C_X (C_X15 + 1)
1ae8ab47 1564 { F_CLASS_OPTIONAL, { F_SIGNX, F_NULL }},
886a2506
NC		 1565
1566#define C_ZZ13 (C_X + 1)
1ae8ab47 1567 { F_CLASS_OPTIONAL, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}},
886a2506 1568#define C_ZZ23 (C_ZZ13 + 1)
1ae8ab47 1569 { F_CLASS_OPTIONAL, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}},
886a2506 1570#define C_ZZ29 (C_ZZ23 + 1)
1ae8ab47 1571 { F_CLASS_OPTIONAL, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}},
886a2506
NC		 1572
1573#define C_AS (C_ZZ29 + 1)
1ae8ab47 1574 { F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}},
886a2506
NC		 1575
1576#define C_NE (C_AS + 1)
1ae8ab47 1577 { F_CLASS_OPTIONAL, { F_NE, F_NULL}},
e23e8ebe
AB		 1578
1579 /* ARC NPS400 Support: See comment near head of file. */
1580#define C_NPS_CL (C_NE + 1)
1581 { F_CLASS_REQUIRED, { F_NPS_CL, F_NULL}},
1582
645d3342
RZ		 1583#define C_NPS_NA (C_NPS_CL + 1)
1584 { F_CLASS_OPTIONAL, { F_NPS_NA, F_NULL}},
1585
1586#define C_NPS_F (C_NPS_NA + 1)
e23e8ebe 1587 { F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}},
820f03ff
AB		 1588
1589#define C_NPS_R (C_NPS_F + 1)
1590 { F_CLASS_OPTIONAL, { F_NPS_R, F_NULL}},
a42a4f84
AB		 1591
1592#define C_NPS_SCHD_RW (C_NPS_R + 1)
1593 { F_CLASS_REQUIRED, { F_NPS_RW, F_NPS_RD, F_NULL}},
1594
1595#define C_NPS_SCHD_TRIG (C_NPS_SCHD_RW + 1)
1596 { F_CLASS_REQUIRED, { F_NPS_WFT, F_NULL}},
1597
1598#define C_NPS_SCHD_IE (C_NPS_SCHD_TRIG + 1)
1599 { F_CLASS_OPTIONAL, { F_NPS_IE1, F_NPS_IE2, F_NPS_IE12, F_NULL}},
1600
1601#define C_NPS_SYNC (C_NPS_SCHD_IE + 1)
1602 { F_CLASS_REQUIRED, { F_NPS_SYNC_RD, F_NPS_SYNC_WR, F_NULL}},
1603
1604#define C_NPS_HWS_OFF (C_NPS_SYNC + 1)
1605 { F_CLASS_REQUIRED, { F_NPS_HWS_OFF, F_NULL}},
1606
1607#define C_NPS_HWS_RESTORE (C_NPS_HWS_OFF + 1)
1608 { F_CLASS_REQUIRED, { F_NPS_HWS_RESTORE, F_NULL}},
1609
537aefaf
AB		 1610#define C_NPS_SX (C_NPS_HWS_RESTORE + 1)
1611 { F_CLASS_OPTIONAL, { F_NPS_SX, F_NULL}},
1612
1613#define C_NPS_AR_AL (C_NPS_SX + 1)
1614 { F_CLASS_REQUIRED, { F_NPS_AR, F_NPS_AL, F_NULL}},
14053c19
GM		 1615
1616#define C_NPS_S (C_NPS_AR_AL + 1)
1617 { F_CLASS_REQUIRED, { F_NPS_S, F_NULL}},
1618
1619#define C_NPS_ZNCV (C_NPS_S + 1)
1620 { F_CLASS_REQUIRED, { F_NPS_ZNCV_RD, F_NPS_ZNCV_WR, F_NULL}},
9ba75c88
GM		 1621
1622#define C_NPS_P0 (C_NPS_ZNCV + 1)
1623 { F_CLASS_REQUIRED, { F_NPS_P0, F_NULL }},
1624
1625#define C_NPS_P1 (C_NPS_P0 + 1)
1626 { F_CLASS_REQUIRED, { F_NPS_P1, F_NULL }},
1627
1628#define C_NPS_P2 (C_NPS_P1 + 1)
1629 { F_CLASS_REQUIRED, { F_NPS_P2, F_NULL }},
1630
1631#define C_NPS_P3 (C_NPS_P2 + 1)
1632 { F_CLASS_REQUIRED, { F_NPS_P3, F_NULL }},
28215275
GM		 1633
1634#define C_NPS_LDBIT_DI (C_NPS_P3 + 1)
1635 { F_CLASS_REQUIRED, { F_NPS_LDBIT_DI, F_NULL }},
1636
1637#define C_NPS_LDBIT_CL1 (C_NPS_LDBIT_DI + 1)
1638 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL1, F_NULL }},
1639
1640#define C_NPS_LDBIT_CL2 (C_NPS_LDBIT_CL1 + 1)
1641 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL2, F_NULL }},
1642
1643#define C_NPS_LDBIT_X_1 (C_NPS_LDBIT_CL2 + 1)
1644 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_1, F_NPS_LDBIT_X4_1, F_NULL }},
1645
1646#define C_NPS_LDBIT_X_2 (C_NPS_LDBIT_X_1 + 1)
1647 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_2, F_NPS_LDBIT_X4_2, F_NULL }},
886a2506 1648};
252b5132 1649
b99747ae
CZ		 1650const unsigned char flags_none[] = { 0 };
1651const unsigned char flags_f[] = { C_F };
1652const unsigned char flags_cc[] = { C_CC };
1653const unsigned char flags_ccf[] = { C_CC, C_F };
1654
886a2506 1655/* The operands table.
252b5132 1656
886a2506 1657 The format of the operands table is:
47b0e7ad 1658
886a2506
NC		 1659 BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN. */
1660const struct arc_operand arc_operands[] =
0d2bcfaf 1661{
886a2506
NC		 1662 /* The fields are bits, shift, insert, extract, flags. The zero
1663 index is used to indicate end-of-list. */
1664#define UNUSED 0
1665 { 0, 0, 0, 0, 0, 0 },
4eb6f892
AB		 1666
1667#define IGNORED (UNUSED + 1)
1668 { 0, 0, 0, ARC_OPERAND_IGNORE | ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 0, 0 },
1669
886a2506
NC		 1670 /* The plain integer register fields. Used by 32 bit
1671 instructions. */
4eb6f892 1672#define RA (IGNORED + 1)
886a2506 1673 { 6, 0, 0, ARC_OPERAND_IR, 0, 0 },
abe7c33b
CZ		 1674#define RA_CHK (RA + 1)
1675 { 6, 0, 0, ARC_OPERAND_IR, insert_ra_chk, 0 },
1676#define RB (RA_CHK + 1)
886a2506 1677 { 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb },
abe7c33b
CZ		 1678#define RB_CHK (RB + 1)
1679 { 6, 12, 0, ARC_OPERAND_IR, insert_rb_chk, extract_rb },
1680#define RC (RB_CHK + 1)
886a2506
NC		 1681 { 6, 6, 0, ARC_OPERAND_IR, 0, 0 },
1682#define RBdup (RC + 1)
1683 { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb },
1684
1685#define RAD (RBdup + 1)
1686 { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 },
1687#define RCD (RAD + 1)
1688 { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 },
1689
1690 /* The plain integer register fields. Used by short
1691 instructions. */
1692#define RA16 (RCD + 1)
1693#define RA_S (RCD + 1)
1694 { 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras },
1695#define RB16 (RA16 + 1)
1696#define RB_S (RA16 + 1)
1697 { 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs },
1698#define RB16dup (RB16 + 1)
1699#define RB_Sdup (RB16 + 1)
1700 { 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs },
1701#define RC16 (RB16dup + 1)
1702#define RC_S (RB16dup + 1)
1703 { 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs },
1704#define R6H (RC16 + 1) /* 6bit register field 'h' used
1705 by V1 cpus. */
1706 { 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1 },
1707#define R5H (R6H + 1) /* 5bit register field 'h' used
1708 by V2 cpus. */
1709#define RH_S (R6H + 1) /* 5bit register field 'h' used
1710 by V2 cpus. */
1711 { 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2 },
1712#define R5Hdup (R5H + 1)
1713#define RH_Sdup (R5H + 1)
1714 { 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE,
1715 insert_rhv2, extract_rhv2 },
1716
1717#define RG (R5Hdup + 1)
1718#define G_S (R5Hdup + 1)
1719 { 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s },
1720
1721 /* Fix registers. */
1722#define R0 (RG + 1)
1723#define R0_S (RG + 1)
1724 { 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0 },
1725#define R1 (R0 + 1)
1726#define R1_S (R0 + 1)
1727 { 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1 },
1728#define R2 (R1 + 1)
1729#define R2_S (R1 + 1)
1730 { 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2 },
1731#define R3 (R2 + 1)
1732#define R3_S (R2 + 1)
1733 { 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3 },
8ddf6b2a 1734#define RSP (R3 + 1)
886a2506
NC		 1735#define SP_S (R3 + 1)
1736 { 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp },
8ddf6b2a
CZ		 1737#define SPdup (RSP + 1)
1738#define SP_Sdup (RSP + 1)
886a2506
NC		 1739 { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp },
1740#define GP (SPdup + 1)
1741#define GP_S (SPdup + 1)
1742 { 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp },
1743
1744#define PCL_S (GP + 1)
1745 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl },
1746
1747#define BLINK (PCL_S + 1)
1748#define BLINK_S (PCL_S + 1)
1749 { 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink },
1750
1751#define ILINK1 (BLINK + 1)
1752 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1 },
1753#define ILINK2 (ILINK1 + 1)
1754 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2 },
1755
1756 /* Long immediate. */
1757#define LIMM (ILINK2 + 1)
1758#define LIMM_S (ILINK2 + 1)
1759 { 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0 },
1760#define LIMMdup (LIMM + 1)
1761 { 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0 },
1762
1763 /* Special operands. */
1764#define ZA (LIMMdup + 1)
1765#define ZB (LIMMdup + 1)
1766#define ZA_S (LIMMdup + 1)
1767#define ZB_S (LIMMdup + 1)
1768#define ZC_S (LIMMdup + 1)
1769 { 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0 },
1770
1771#define RRANGE_EL (ZA + 1)
1772 { 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE,
1773 insert_rrange, extract_rrange},
1774#define FP_EL (RRANGE_EL + 1)
1775 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1776 insert_fpel, extract_fpel },
1777#define BLINK_EL (FP_EL + 1)
1778 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1779 insert_blinkel, extract_blinkel },
1780#define PCL_EL (BLINK_EL + 1)
1781 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1782 insert_pclel, extract_pclel },
1783
1784 /* Fake operand to handle the T flag. */
1785#define BRAKET (PCL_EL + 1)
1786#define BRAKETdup (PCL_EL + 1)
1787 { 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0 },
1788
1789 /* Fake operand to handle the T flag. */
1790#define FKT_T (BRAKET + 1)
1791 { 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0 },
1792 /* Fake operand to handle the T flag. */
1793#define FKT_NT (FKT_T + 1)
1794 { 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0 },
1795
1796 /* UIMM6_20 mask = 00000000000000000000111111000000. */
1797#define UIMM6_20 (FKT_NT + 1)
1798 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20},
1799
cc07cda6
CZ		 1800 /* Exactly like the above but used by relaxation. */
1801#define UIMM6_20R (UIMM6_20 + 1)
1802 {6, 0, -UIMM6_20R, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
1803 insert_uimm6_20, extract_uimm6_20},
1804
886a2506 1805 /* SIMM12_20 mask = 00000000000000000000111111222222. */
cc07cda6 1806#define SIMM12_20 (UIMM6_20R + 1)
886a2506
NC		 1807 {12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20},
1808
cc07cda6
CZ		 1809 /* Exactly like the above but used by relaxation. */
1810#define SIMM12_20R (SIMM12_20 + 1)
1811 {12, 0, -SIMM12_20R, ARC_OPERAND_SIGNED | ARC_OPERAND_PCREL,
1812 insert_simm12_20, extract_simm12_20},
1813
886a2506 1814 /* SIMM3_5_S mask = 0000011100000000. */
cc07cda6 1815#define SIMM3_5_S (SIMM12_20R + 1)
886a2506
NC		 1816 {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK,
1817 insert_simm3s, extract_simm3s},
1818
1819 /* UIMM7_A32_11_S mask = 0000000000011111. */
1820#define UIMM7_A32_11_S (SIMM3_5_S + 1)
1821 {7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1822 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s,
1823 extract_uimm7_a32_11_s},
1824
cc07cda6
CZ		 1825 /* The same as above but used by relaxation. */
1826#define UIMM7_A32_11R_S (UIMM7_A32_11_S + 1)
1827 {7, 0, -UIMM7_A32_11R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1828 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE | ARC_OPERAND_PCREL,
1829 insert_uimm7_a32_11_s, extract_uimm7_a32_11_s},
1830
886a2506 1831 /* UIMM7_9_S mask = 0000000001111111. */
cc07cda6 1832#define UIMM7_9_S (UIMM7_A32_11R_S + 1)
886a2506
NC		 1833 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s},
1834
1835 /* UIMM3_13_S mask = 0000000000000111. */
1836#define UIMM3_13_S (UIMM7_9_S + 1)
1837 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s},
1838
cc07cda6
CZ		 1839 /* Exactly like the above but used for relaxation. */
1840#define UIMM3_13R_S (UIMM3_13_S + 1)
1841 {3, 0, -UIMM3_13R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
1842 insert_uimm3_13_s, extract_uimm3_13_s},
1843
886a2506 1844 /* SIMM11_A32_7_S mask = 0000000111111111. */
cc07cda6 1845#define SIMM11_A32_7_S (UIMM3_13R_S + 1)
886a2506
NC		 1846 {11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1847 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s},
1848
1849 /* UIMM6_13_S mask = 0000000002220111. */
1850#define UIMM6_13_S (SIMM11_A32_7_S + 1)
1851 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s},
1852 /* UIMM5_11_S mask = 0000000000011111. */
1853#define UIMM5_11_S (UIMM6_13_S + 1)
1854 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s,
1855 extract_uimm5_11_s},
1856
1857 /* SIMM9_A16_8 mask = 00000000111111102000000000000000. */
1858#define SIMM9_A16_8 (UIMM5_11_S + 1)
1859 {9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1860 | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8,
1861 extract_simm9_a16_8},
1862
1863 /* UIMM6_8 mask = 00000000000000000000111111000000. */
1864#define UIMM6_8 (SIMM9_A16_8 + 1)
1865 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8},
1866
1867 /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */
1868#define SIMM21_A16_5 (UIMM6_8 + 1)
1869 {21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED
1870 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE,
1871 insert_simm21_a16_5, extract_simm21_a16_5},
1872
1873 /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */
1874#define SIMM25_A16_5 (SIMM21_A16_5 + 1)
1875 {25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED
1876 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL,
1877 insert_simm25_a16_5, extract_simm25_a16_5},
1878
1879 /* SIMM10_A16_7_S mask = 0000000111111111. */
1880#define SIMM10_A16_7_S (SIMM25_A16_5 + 1)
1881 {10, 0, -SIMM10_A16_7_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1882 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s,
1883 extract_simm10_a16_7_s},
1884
1885#define SIMM10_A16_7_Sbis (SIMM10_A16_7_S + 1)
1886 {10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1887 | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s},
1888
1889 /* SIMM7_A16_10_S mask = 0000000000111111. */
1890#define SIMM7_A16_10_S (SIMM10_A16_7_Sbis + 1)
1891 {7, 0, -SIMM7_A16_10_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1892 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s,
1893 extract_simm7_a16_10_s},
1894
1895 /* SIMM21_A32_5 mask = 00000111111111002222222222000000. */
1896#define SIMM21_A32_5 (SIMM7_A16_10_S + 1)
1897 {21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1898 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5,
1899 extract_simm21_a32_5},
1900
1901 /* SIMM25_A32_5 mask = 00000111111111002222222222003333. */
1902#define SIMM25_A32_5 (SIMM21_A32_5 + 1)
1903 {25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1904 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5,
1905 extract_simm25_a32_5},
1906
1907 /* SIMM13_A32_5_S mask = 0000011111111111. */
1908#define SIMM13_A32_5_S (SIMM25_A32_5 + 1)
1909 {13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1910 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s,
1911 extract_simm13_a32_5_s},
1912
1913 /* SIMM8_A16_9_S mask = 0000000001111111. */
1914#define SIMM8_A16_9_S (SIMM13_A32_5_S + 1)
1915 {8, 0, -SIMM8_A16_9_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1916 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s,
1917 extract_simm8_a16_9_s},
1918
1919 /* UIMM3_23 mask = 00000000000000000000000111000000. */
1920#define UIMM3_23 (SIMM8_A16_9_S + 1)
1921 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23},
1922
1923 /* UIMM10_6_S mask = 0000001111111111. */
1924#define UIMM10_6_S (UIMM3_23 + 1)
1925 {10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s},
1926
1927 /* UIMM6_11_S mask = 0000002200011110. */
1928#define UIMM6_11_S (UIMM10_6_S + 1)
1929 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s},
1930
1931 /* SIMM9_8 mask = 00000000111111112000000000000000. */
1932#define SIMM9_8 (UIMM6_11_S + 1)
1933 {9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE,
1934 insert_simm9_8, extract_simm9_8},
1935
cc07cda6
CZ		 1936 /* The same as above but used by relaxation. */
1937#define SIMM9_8R (SIMM9_8 + 1)
1938 {9, 0, -SIMM9_8R, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE
1939 | ARC_OPERAND_PCREL, insert_simm9_8, extract_simm9_8},
1940
886a2506 1941 /* UIMM10_A32_8_S mask = 0000000011111111. */
cc07cda6 1942#define UIMM10_A32_8_S (SIMM9_8R + 1)
886a2506
NC		 1943 {10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1944 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s,
1945 extract_uimm10_a32_8_s},
1946
1947 /* SIMM9_7_S mask = 0000000111111111. */
1948#define SIMM9_7_S (UIMM10_A32_8_S + 1)
1949 {9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s,
1950 extract_simm9_7_s},
1951
1952 /* UIMM6_A16_11_S mask = 0000000000011111. */
1953#define UIMM6_A16_11_S (SIMM9_7_S + 1)
1954 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1955 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s,
1956 extract_uimm6_a16_11_s},
1957
1958 /* UIMM5_A32_11_S mask = 0000020000011000. */
1959#define UIMM5_A32_11_S (UIMM6_A16_11_S + 1)
1960 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1961 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s,
1962 extract_uimm5_a32_11_s},
1963
1964 /* SIMM11_A32_13_S mask = 0000022222200111. */
1965#define SIMM11_A32_13_S (UIMM5_A32_11_S + 1)
1966 {11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1967 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s},
1968
1969 /* UIMM7_13_S mask = 0000000022220111. */
1970#define UIMM7_13_S (SIMM11_A32_13_S + 1)
1971 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s},
1972
1973 /* UIMM6_A16_21 mask = 00000000000000000000011111000000. */
1974#define UIMM6_A16_21 (UIMM7_13_S + 1)
1975 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1976 | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21},
1977
1978 /* UIMM7_11_S mask = 0000022200011110. */
1979#define UIMM7_11_S (UIMM6_A16_21 + 1)
1980 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s},
1981
1982 /* UIMM7_A16_20 mask = 00000000000000000000111111000000. */
1983#define UIMM7_A16_20 (UIMM7_11_S + 1)
1984 {7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1985 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20,
1986 extract_uimm7_a16_20},
1987
1988 /* SIMM13_A16_20 mask = 00000000000000000000111111222222. */
1989#define SIMM13_A16_20 (UIMM7_A16_20 + 1)
1990 {13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1991 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20,
1992 extract_simm13_a16_20},
1993
1994 /* UIMM8_8_S mask = 0000000011111111. */
1995#define UIMM8_8_S (SIMM13_A16_20 + 1)
1996 {8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s},
1997
cc07cda6
CZ		 1998 /* The same as above but used for relaxation. */
1999#define UIMM8_8R_S (UIMM8_8_S + 1)
2000 {8, 0, -UIMM8_8R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
2001 insert_uimm8_8_s, extract_uimm8_8_s},
2002
886a2506 2003 /* W6 mask = 00000000000000000000111111000000. */
cc07cda6 2004#define W6 (UIMM8_8R_S + 1)
886a2506
NC		 2005 {6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6},
2006
2007 /* UIMM6_5_S mask = 0000011111100000. */
2008#define UIMM6_5_S (W6 + 1)
2009 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s},
e23e8ebe
AB		 2010
2011 /* ARC NPS400 Support: See comment near head of file. */
2012#define NPS_R_DST_3B (UIMM6_5_S + 1)
bdfe53e3 2013 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
e23e8ebe
AB		 2014
2015#define NPS_R_SRC1_3B (NPS_R_DST_3B + 1)
bdfe53e3 2016 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
e23e8ebe
AB		 2017
2018#define NPS_R_SRC2_3B (NPS_R_SRC1_3B + 1)
bdfe53e3 2019 { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_21_src2, extract_nps_3bit_reg_at_21_src2 },
e23e8ebe
AB		 2020
2021#define NPS_R_DST (NPS_R_SRC2_3B + 1)
2cce10e7 2022 { 6, 21, 0, ARC_OPERAND_IR, NULL, NULL },
e23e8ebe
AB		 2023
2024#define NPS_R_SRC1 (NPS_R_DST + 1)
2cce10e7 2025 { 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL },
e23e8ebe
AB		 2026
2027#define NPS_BITOP_DST_POS (NPS_R_SRC1 + 1)
2028 { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
2029
2030#define NPS_BITOP_SRC_POS (NPS_BITOP_DST_POS + 1)
2031 { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
2032
2033#define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1)
820f03ff 2034 { 5, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size, extract_nps_bitop_size },
e23e8ebe 2035
820f03ff
AB		 2036#define NPS_BITOP_DST_POS_SZ (NPS_BITOP_SIZE + 1)
2037 { 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_dst_pos_and_size, extract_nps_dst_pos_and_size },
2038
2039#define NPS_BITOP_SIZE_2B (NPS_BITOP_DST_POS_SZ + 1)
2040 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size_2b, extract_nps_bitop_size_2b },
2041
2042#define NPS_BITOP_UIMM8 (NPS_BITOP_SIZE_2B + 1)
2043 { 8, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_uimm8, extract_nps_bitop_uimm8 },
2044
2045#define NPS_UIMM16 (NPS_BITOP_UIMM8 + 1)
e23e8ebe 2046 { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
820f03ff 2047
14053c19
GM		 2048#define NPS_SIMM16 (NPS_UIMM16 + 1)
2049 { 16, 0, 0, ARC_OPERAND_SIGNED, NULL, NULL },
2050
2051#define NPS_RFLT_UIMM6 (NPS_SIMM16 + 1)
820f03ff 2052 { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_rflt_uimm6, extract_nps_rflt_uimm6 },
4b0c052e
AB		 2053
2054#define NPS_XLDST_UIMM16 (NPS_RFLT_UIMM6 + 1)
2055 { 16, 0, BFD_RELOC_ARC_NPS_CMEM16, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_cmem_uimm16, extract_nps_cmem_uimm16 },
537aefaf
AB		 2056
2057#define NPS_SRC2_POS (NPS_XLDST_UIMM16 + 1)
2058 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_src2_pos, extract_nps_src2_pos },
2059
2060#define NPS_SRC1_POS (NPS_SRC2_POS + 1)
2061 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_src1_pos, extract_nps_src1_pos },
2062
2063#define NPS_ADDB_SIZE (NPS_SRC1_POS + 1)
2064 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_addb_size, extract_nps_addb_size },
2065
2066#define NPS_ANDB_SIZE (NPS_ADDB_SIZE + 1)
2067 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_andb_size, extract_nps_andb_size },
2068
2069#define NPS_FXORB_SIZE (NPS_ANDB_SIZE + 1)
2070 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_fxorb_size, extract_nps_fxorb_size },
2071
2072#define NPS_WXORB_SIZE (NPS_FXORB_SIZE + 1)
2073 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_wxorb_size, extract_nps_wxorb_size },
2074
2075#define NPS_R_XLDST (NPS_WXORB_SIZE + 1)
2076 { 6, 5, 0, ARC_OPERAND_IR, NULL, NULL },
2077
2078#define NPS_DIV_UIMM4 (NPS_R_XLDST + 1)
2079 { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2080
2081#define NPS_QCMP_SIZE (NPS_DIV_UIMM4 + 1)
2082 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_qcmp_size, extract_nps_qcmp_size },
2083
2084#define NPS_QCMP_M1 (NPS_QCMP_SIZE + 1)
2085 { 1, 14, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m1 },
2086
2087#define NPS_QCMP_M2 (NPS_QCMP_M1 + 1)
2088 { 1, 15, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m2 },
2089
2090#define NPS_QCMP_M3 (NPS_QCMP_M2 + 1)
2091 { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m3 },
2092
2093#define NPS_CALC_ENTRY_SIZE (NPS_QCMP_M3 + 1)
2094 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_calc_entry_size, extract_nps_calc_entry_size },
4eb6f892
AB		 2095
2096#define NPS_R_DST_3B_SHORT (NPS_CALC_ENTRY_SIZE + 1)
bdfe53e3 2097 { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst },
4eb6f892
AB		 2098
2099#define NPS_R_SRC1_3B_SHORT (NPS_R_DST_3B_SHORT + 1)
bdfe53e3 2100 { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst },
4eb6f892
AB		 2101
2102#define NPS_R_SRC2_3B_SHORT (NPS_R_SRC1_3B_SHORT + 1)
bdfe53e3 2103 { 3, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_5_src2, extract_nps_3bit_reg_at_5_src2 },
4eb6f892
AB		 2104
2105#define NPS_BITOP_SIZE2 (NPS_R_SRC2_3B_SHORT + 1)
2106 { 5, 25, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop2_size, extract_nps_bitop2_size },
2107
2108#define NPS_BITOP_SIZE1 (NPS_BITOP_SIZE2 + 1)
2109 { 5, 20, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop1_size, extract_nps_bitop1_size },
2110
2111#define NPS_BITOP_DST_POS3_POS4 (NPS_BITOP_SIZE1 + 1)
2112 { 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_dst_pos3_pos4, extract_nps_bitop_dst_pos3_pos4 },
2113
2114#define NPS_BITOP_DST_POS4 (NPS_BITOP_DST_POS3_POS4 + 1)
bdfe53e3 2115 { 5, 42, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
4eb6f892
AB		 2116
2117#define NPS_BITOP_DST_POS3 (NPS_BITOP_DST_POS4 + 1)
bdfe53e3 2118 { 5, 37, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
4eb6f892
AB		 2119
2120#define NPS_BITOP_DST_POS2 (NPS_BITOP_DST_POS3 + 1)
2121 { 5, 15, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2122
2123#define NPS_BITOP_DST_POS1 (NPS_BITOP_DST_POS2 + 1)
2124 { 5, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2125
2126#define NPS_BITOP_SRC_POS4 (NPS_BITOP_DST_POS1 + 1)
bdfe53e3 2127 { 5, 32, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
4eb6f892
AB		 2128
2129#define NPS_BITOP_SRC_POS3 (NPS_BITOP_SRC_POS4 + 1)
2130 { 5, 20, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2131
2132#define NPS_BITOP_SRC_POS2 (NPS_BITOP_SRC_POS3 + 1)
2133 { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2134
2135#define NPS_BITOP_SRC_POS1 (NPS_BITOP_SRC_POS2 + 1)
2136 { 5, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2137
bdfe53e3
AB		 2138#define NPS_BITOP_MOD4 (NPS_BITOP_SRC_POS1 + 1)
2139 { 2, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_mod4, extract_nps_bitop_mod4 },
4eb6f892 2140
bdfe53e3 2141#define NPS_BITOP_MOD3 (NPS_BITOP_MOD4 + 1)
4eb6f892
AB		 2142 { 2, 29, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2143
2144#define NPS_BITOP_MOD2 (NPS_BITOP_MOD3 + 1)
2145 { 2, 27, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2146
2147#define NPS_BITOP_MOD1 (NPS_BITOP_MOD2 + 1)
2148 { 2, 25, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2149
2150#define NPS_BITOP_INS_EXT (NPS_BITOP_MOD1 + 1)
2151 { 5, 20, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_ins_ext, extract_nps_bitop_ins_ext },
14053c19
GM		 2152
2153#define NPS_FIELD_START_POS (NPS_BITOP_INS_EXT + 1)
2154 { 3, 3, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2155
2156#define NPS_FIELD_SIZE (NPS_FIELD_START_POS + 1)
2157 { 3, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_field_size, extract_nps_field_size },
2158
2159#define NPS_SHIFT_FACTOR (NPS_FIELD_SIZE + 1)
2160 { 3, 9, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_shift_factor, extract_nps_shift_factor },
2161
2162#define NPS_BITS_TO_SCRAMBLE (NPS_SHIFT_FACTOR + 1)
2163 { 3, 12, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bits_to_scramble, extract_nps_bits_to_scramble },
2164
2165#define NPS_SRC2_POS_5B (NPS_BITS_TO_SCRAMBLE + 1)
2166 { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2167
2168#define NPS_BDLEN_MAX_LEN (NPS_SRC2_POS_5B + 1)
2169 { 8, 5, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bdlen_max_len, extract_nps_bdlen_max_len },
2170
2171#define NPS_MIN_HOFS (NPS_BDLEN_MAX_LEN + 1)
2172 { 4, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_min_hofs, extract_nps_min_hofs },
2173
2174#define NPS_PSBC (NPS_MIN_HOFS + 1)
2175 { 1, 11, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
9ba75c88
GM		 2176
2177#define NPS_DPI_DST (NPS_PSBC + 1)
2178 { 5, 11, 0, ARC_OPERAND_IR, NULL, NULL },
2179
2180 /* NPS_DPI_SRC1_3B is similar to NPS_R_SRC1_3B but doesn't duplicate an operand */
2181#define NPS_DPI_SRC1_3B (NPS_DPI_DST + 1)
bdfe53e3 2182 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
9ba75c88
GM		 2183
2184#define NPS_HASH_WIDTH (NPS_DPI_SRC1_3B + 1)
2185 { 5, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_hash_width, extract_nps_hash_width },
2186
2187#define NPS_HASH_PERM (NPS_HASH_WIDTH + 1)
2188 { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2189
2190#define NPS_HASH_NONLINEAR (NPS_HASH_PERM + 1)
2191 { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2192
2193#define NPS_HASH_BASEMAT (NPS_HASH_NONLINEAR + 1)
2194 { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2195
2196#define NPS_HASH_LEN (NPS_HASH_BASEMAT + 1)
2197 { 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_hash_len, extract_nps_hash_len },
2198
2199#define NPS_HASH_OFS (NPS_HASH_LEN + 1)
2200 { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2201
2202#define NPS_HASH_BASEMAT2 (NPS_HASH_OFS + 1)
2203 { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2204
2205#define NPS_E4BY_INDEX0 (NPS_HASH_BASEMAT2 + 1)
2206 { 3, 8, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2207
2208#define NPS_E4BY_INDEX1 (NPS_E4BY_INDEX0 + 1)
2209 { 3, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2210
2211#define NPS_E4BY_INDEX2 (NPS_E4BY_INDEX1 + 1)
2212 { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2213
2214#define NPS_E4BY_INDEX3 (NPS_E4BY_INDEX2 + 1)
2215 { 2, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_index3, extract_nps_index3 },
db18dbab
GM		 2216
2217#define COLON (NPS_E4BY_INDEX3 + 1)
2218 { 0, 0, 0, ARC_OPERAND_COLON | ARC_OPERAND_FAKE, NULL, NULL },
2219
2220#define NPS_BD (COLON + 1)
2221 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_bd, extract_nps_bd },
2222
2223#define NPS_JID (NPS_BD + 1)
2224 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_jid, extract_nps_jid },
2225
2226#define NPS_LBD (NPS_JID + 1)
2227 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_lbd, extract_nps_lbd },
2228
2229#define NPS_MBD (NPS_LBD + 1)
2230 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_mbd, extract_nps_mbd },
2231
2232#define NPS_SD (NPS_MBD + 1)
2233 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_sd, extract_nps_sd },
2234
2235#define NPS_SM (NPS_SD + 1)
2236 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_sm, extract_nps_sm },
2237
2238#define NPS_XA (NPS_SM + 1)
2239 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_xa, extract_nps_xa },
2240
2241#define NPS_XD (NPS_XA + 1)
2242 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_xd, extract_nps_xd },
2243
2244#define NPS_CD (NPS_XD + 1)
2245 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cd, extract_nps_cd },
2246
2247#define NPS_CBD (NPS_CD + 1)
2248 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cbd, extract_nps_cbd },
2249
2250#define NPS_CJID (NPS_CBD + 1)
2251 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cjid, extract_nps_cjid },
2252
2253#define NPS_CLBD (NPS_CJID + 1)
2254 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_clbd, extract_nps_clbd },
2255
2256#define NPS_CM (NPS_CLBD + 1)
2257 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cm, extract_nps_cm },
2258
2259#define NPS_CSD (NPS_CM + 1)
2260 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_csd, extract_nps_csd },
2261
2262#define NPS_CXA (NPS_CSD + 1)
2263 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cxa, extract_nps_cxa },
2264
2265#define NPS_CXD (NPS_CXA + 1)
2266 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cxd, extract_nps_cxd },
2267
2268#define NPS_BD_TYPE (NPS_CXD + 1)
2269 { 1, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2270
2271#define NPS_BMU_NUM (NPS_BD_TYPE + 1)
2272 { 3, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bd_num_buff, extract_nps_bd_num_buff },
2273
2274#define NPS_PMU_NXT_DST (NPS_BMU_NUM + 1)
2275 { 4, 6, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2276
2277#define NPS_PMU_NUM_JOB (NPS_PMU_NXT_DST + 1)
2278 { 2, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_pmu_num_job, extract_nps_pmu_num_job },
bdfe53e3 2279
645d3342
RZ		 2280#define NPS_DMA_IMM_ENTRY (NPS_PMU_NUM_JOB + 1)
2281 { 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_imm_entry, extract_nps_imm_entry },
2282
2283#define NPS_DMA_IMM_OFFSET (NPS_DMA_IMM_ENTRY + 1)
2284 { 4, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_imm_offset, extract_nps_imm_offset },
2285
2286#define NPS_R_DST_3B_48 (NPS_DMA_IMM_OFFSET + 1)
bdfe53e3
AB		 2287 { 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst },
2288
2289#define NPS_R_SRC1_3B_48 (NPS_R_DST_3B_48 + 1)
2290 { 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst },
2291
2292#define NPS_R_SRC2_3B_48 (NPS_R_SRC1_3B_48 + 1)
2293 { 3, 37, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_37_src2, extract_nps_3bit_reg_at_37_src2 },
2294
2295#define NPS_R_DST_3B_64 (NPS_R_SRC2_3B_48 + 1)
2296 { 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst },
2297
2298#define NPS_R_SRC1_3B_64 (NPS_R_DST_3B_64 + 1)
2299 { 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst },
2300
2301#define NPS_R_SRC2_3B_64 (NPS_R_SRC1_3B_64 + 1)
2302 { 3, 53, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_53_src2, extract_nps_3bit_reg_at_53_src2 },
0d2bcfaf 2303
5a736821
GM		 2304#define NPS_RA_64 (NPS_R_SRC2_3B_64 + 1)
2305 { 6, 53, 0, ARC_OPERAND_IR, NULL, NULL },
2306
2307#define NPS_RB_64 (NPS_RA_64 + 1)
2308 { 5, 48, 0, ARC_OPERAND_IR, NULL, NULL },
2309
2310#define NPS_RBdup_64 (NPS_RB_64 + 1)
2311 { 5, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL },
2312
2313#define NPS_RBdouble_64 (NPS_RBdup_64 + 1)
2314 { 10, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_rbdouble_64, extract_nps_rbdouble_64 },
2315
2316#define NPS_RC_64 (NPS_RBdouble_64 + 1)
2317 { 5, 43, 0, ARC_OPERAND_IR, NULL, NULL },
2318
2319#define NPS_UIMM16_0_64 (NPS_RC_64 + 1)
2320 { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2321
2322#define NPS_PROTO_SIZE (NPS_UIMM16_0_64 + 1)
2323 { 6, 16, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_proto_size, extract_nps_proto_size }
2324};
886a2506 2325const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
0d2bcfaf 2326
886a2506
NC		 2327const unsigned arc_Toperand = FKT_T;
2328const unsigned arc_NToperand = FKT_NT;
47b0e7ad 2329
b99747ae
CZ		 2330const unsigned char arg_none[] = { 0 };
2331const unsigned char arg_32bit_rarbrc[] = { RA, RB, RC };
2332const unsigned char arg_32bit_zarbrc[] = { ZA, RB, RC };
2333const unsigned char arg_32bit_rbrbrc[] = { RB, RBdup, RC };
2334const unsigned char arg_32bit_rarbu6[] = { RA, RB, UIMM6_20 };
2335const unsigned char arg_32bit_zarbu6[] = { ZA, RB, UIMM6_20 };
2336const unsigned char arg_32bit_rbrbu6[] = { RB, RBdup, UIMM6_20 };
2337const unsigned char arg_32bit_rbrbs12[] = { RB, RBdup, SIMM12_20 };
2338const unsigned char arg_32bit_ralimmrc[] = { RA, LIMM, RC };
2339const unsigned char arg_32bit_rarblimm[] = { RA, RB, LIMM };
2340const unsigned char arg_32bit_zalimmrc[] = { ZA, LIMM, RC };
2341const unsigned char arg_32bit_zarblimm[] = { ZA, RB, LIMM };
2342
2343const unsigned char arg_32bit_rbrblimm[] = { RB, RBdup, LIMM };
2344const unsigned char arg_32bit_ralimmu6[] = { RA, LIMM, UIMM6_20 };
2345const unsigned char arg_32bit_zalimmu6[] = { ZA, LIMM, UIMM6_20 };
2346
2347const unsigned char arg_32bit_zalimms12[] = { ZA, LIMM, SIMM12_20 };
2348const unsigned char arg_32bit_ralimmlimm[] = { RA, LIMM, LIMMdup };
2349const unsigned char arg_32bit_zalimmlimm[] = { ZA, LIMM, LIMMdup };
2350
2351const unsigned char arg_32bit_rbrc[] = { RB, RC };
2352const unsigned char arg_32bit_zarc[] = { ZA, RC };
2353const unsigned char arg_32bit_rbu6[] = { RB, UIMM6_20 };
2354const unsigned char arg_32bit_zau6[] = { ZA, UIMM6_20 };
2355const unsigned char arg_32bit_rblimm[] = { RB, LIMM };
2356const unsigned char arg_32bit_zalimm[] = { ZA, LIMM };
2357
2358const unsigned char arg_32bit_limmrc[] = { LIMM, RC };
2359const unsigned char arg_32bit_limmu6[] = { LIMM, UIMM6_20 };
2360const unsigned char arg_32bit_limms12[] = { LIMM, SIMM12_20 };
2361const unsigned char arg_32bit_limmlimm[] = { LIMM, LIMMdup };
2362
945e0f82
CZ		 2363const unsigned char arg_32bit_rc[] = { RC };
2364const unsigned char arg_32bit_u6[] = { UIMM6_20 };
2365const unsigned char arg_32bit_limm[] = { LIMM };
2366
886a2506 2367/* The opcode table.
0d2bcfaf 2368
886a2506 2369 The format of the opcode table is:
0d2bcfaf 2370
1328504b
AB		 2371 NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }.
2372
2373 The table is organised such that, where possible, all instructions with
2374 the same mnemonic are together in a block. When the assembler searches
2375 for a suitable instruction the entries are checked in table order, so
2376 more specific, or specialised cases should appear earlier in the table.
2377
2378 As an example, consider two instructions 'add a,b,u6' and 'add
2379 a,b,limm'. The first takes a 6-bit immediate that is encoded within the
2380 32-bit instruction, while the second takes a 32-bit immediate that is
2381 encoded in a follow-on 32-bit, making the total instruction length
2382 64-bits. In this case the u6 variant must appear first in the table, as
2383 all u6 immediates could also be encoded using the 'limm' extension,
2384 however, we want to use the shorter instruction wherever possible.
2385
2386 It is possible though to split instructions with the same mnemonic into
2387 multiple groups. However, the instructions are still checked in table
2388 order, even across groups. The only time that instructions with the
2389 same mnemonic should be split into different groups is when different
2390 variants of the instruction appear in different architectures, in which
2391 case, grouping all instructions from a particular architecture together
2392 might be preferable to merging the instruction into the main instruction
2393 table.
2394
2395 An example of this split instruction groups can be found with the 'sync'
2396 instruction. The core arc architecture provides a 'sync' instruction,
2397 while the nps instruction set extension provides 'sync.rd' and
2398 'sync.wr'. The rd/wr flags are instruction flags, not part of the
2399 mnemonic, so we end up with two groups for the sync instruction, the
2400 first within the core arc instruction table, and the second within the
2401 nps extension instructions. */
886a2506 2402const struct arc_opcode arc_opcodes[] =
0d2bcfaf 2403{
886a2506 2404#include "arc-tbl.h"
e23e8ebe 2405#include "arc-nps400-tbl.h"
f2dd8838 2406#include "arc-ext-tbl.h"
0d2bcfaf 2407
b99747ae
CZ		 2408 { NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } }
2409};
252b5132 2410
886a2506
NC		 2411/* List with special cases instructions and the applicable flags. */
2412const struct arc_flag_special arc_flag_special_cases[] =
252b5132 2413{
886a2506
NC		 2414 { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2415 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2416 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2417 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2418 { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2419 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2420 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2421 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2422 { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2423 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2424 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2425 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2426 { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2427 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2428 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2429 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2430 { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2431 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2432 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2433 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2434 { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2435 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2436 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2437 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2438 { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2439 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2440 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2441 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2442 { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } },
2443 { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } }
2444};
252b5132 2445
886a2506 2446const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases);
252b5132 2447
886a2506 2448/* Relocations. */
886a2506
NC		 2449const struct arc_reloc_equiv_tab arc_reloc_equiv[] =
2450{
24b368f8
CZ		 2451 { "sda", "ld", { F_ASFAKE, F_H1, F_NULL },
2452 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2453 { "sda", "st", { F_ASFAKE, F_H1, F_NULL },
2454 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2455 { "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL },
2456 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2457 { "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL },
2458 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2459
2460 /* Next two entries will cover the undefined behavior ldb/stb with
2461 address scaling. */
2462 { "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL },
2463 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
2464 { "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL },
2465 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST},
2466
2467 { "sda", "ld", { F_ASFAKE, F_NULL },
2468 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
2469 { "sda", "st", { F_ASFAKE, F_NULL },
2470 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
2471 { "sda", "ldd", { F_ASFAKE, F_NULL },
2472 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
2473 { "sda", "std", { F_ASFAKE, F_NULL },
2474 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
886a2506
NC		 2475
2476 /* Short instructions. */
24b368f8
CZ		 2477 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD },
2478 { "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 },
2479 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 },
2480 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 },
2481
2482 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME },
2483 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
2484
2485 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL,
2486 BFD_RELOC_ARC_S25H_PCREL_PLT },
2487 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL,
2488 BFD_RELOC_ARC_S21H_PCREL_PLT },
2489 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL,
2490 BFD_RELOC_ARC_S25W_PCREL_PLT },
2491 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL,
2492 BFD_RELOC_ARC_S21W_PCREL_PLT },
2493
2494 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 }
886a2506 2495};
252b5132 2496
886a2506 2497const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv);
252b5132 2498
886a2506 2499const struct arc_pseudo_insn arc_pseudo_insns[] =
0d2bcfaf 2500{
886a2506
NC		 2501 { "push", "st", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
2502 { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 },
2503 { BRAKETdup, 1, 0, 4} } },
2504 { "pop", "ld", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
2505 { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 },
2506 { BRAKETdup, 1, 0, 4} } },
2507
2508 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2509 { SIMM9_A16_8, 0, 0, 2 } } },
2510 { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2511 { SIMM9_A16_8, 0, 0, 2 } } },
2512 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2513 { SIMM9_A16_8, 0, 0, 2 } } },
2514 { "brgt", "brlt", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2515 { SIMM9_A16_8, 0, 0, 2 } } },
2516 { "brgt", "brge", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2517 { SIMM9_A16_8, 0, 0, 2 } } },
2518
2519 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2520 { SIMM9_A16_8, 0, 0, 2 } } },
2521 { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2522 { SIMM9_A16_8, 0, 0, 2 } } },
2523 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2524 { SIMM9_A16_8, 0, 0, 2 } } },
2525 { "brhi", "brlo", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2526 { SIMM9_A16_8, 0, 0, 2 } } },
2527 { "brhi", "brhs", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2528 { SIMM9_A16_8, 0, 0, 2 } } },
2529
2530 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2531 { SIMM9_A16_8, 0, 0, 2 } } },
2532 { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2533 { SIMM9_A16_8, 0, 0, 2 } } },
2534 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2535 { SIMM9_A16_8, 0, 0, 2 } } },
2536 { "brle", "brge", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2537 { SIMM9_A16_8, 0, 0, 2 } } },
2538 { "brle", "brlt", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2539 { SIMM9_A16_8, 0, 0, 2 } } },
2540
2541 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2542 { SIMM9_A16_8, 0, 0, 2 } } },
2543 { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2544 { SIMM9_A16_8, 0, 0, 2 } } },
2545 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2546 { SIMM9_A16_8, 0, 0, 2 } } },
2547 { "brls", "brhs", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2548 { SIMM9_A16_8, 0, 0, 2 } } },
2549 { "brls", "brlo", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2550 { SIMM9_A16_8, 0, 0, 2 } } },
2551};
0d2bcfaf 2552
886a2506
NC		 2553const unsigned arc_num_pseudo_insn =
2554 sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns);
0d2bcfaf 2555
886a2506 2556const struct arc_aux_reg arc_aux_regs[] =
0d2bcfaf 2557{
886a2506 2558#undef DEF
f36e33da
CZ		 2559#define DEF(ADDR, CPU, SUBCLASS, NAME) \
2560 { ADDR, CPU, SUBCLASS, #NAME, sizeof (#NAME)-1 },
0d2bcfaf 2561
886a2506 2562#include "arc-regs.h"
0d2bcfaf 2563
886a2506
NC		 2564#undef DEF
2565};
0d2bcfaf 2566
886a2506 2567const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs);
4670103e
CZ		 2568
2569/* NOTE: The order of this array MUST be consistent with 'enum
2570 arc_rlx_types' located in tc-arc.h! */
2571const struct arc_opcode arc_relax_opcodes[] =
2572{
2573 { NULL, 0x0, 0x0, 0x0, ARITH, NONE, { UNUSED }, { 0 } },
2574
2575 /* bl_s s13 11111sssssssssss. */
2576 { "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2577 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2578 { SIMM13_A32_5_S }, { 0 }},
2579
2580 /* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */
2581 { "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2582 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2583 { SIMM25_A32_5 }, { C_D }},
2584
2585 /* b_s s10 1111000sssssssss. */
2586 { "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2587 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2588 { SIMM10_A16_7_S }, { 0 }},
2589
2590 /* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */
2591 { "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2592 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2593 { SIMM25_A16_5 }, { C_D }},
2594
cc07cda6 2595 /* add_s c,b,u3 01101bbbccc00uuu. */
4670103e
CZ		 2596 { "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2597 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
cc07cda6 2598 { RC_S, RB_S, UIMM3_13R_S }, { 0 }},
4670103e 2599
cc07cda6 2600 /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. */
4670103e
CZ		 2601 { "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2602 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
cc07cda6 2603 { RA, RB, UIMM6_20R }, { C_F }},
4670103e
CZ		 2604
2605 /* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */
2606 { "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2607 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2608 { RA, RB, LIMM }, { C_F }},
2609
cc07cda6 2610 /* ld_s c,b,u7 10000bbbcccuuuuu. */
4670103e
CZ		 2611 { "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2612 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
cc07cda6 2613 { RC_S, BRAKET, RB_S, UIMM7_A32_11R_S, BRAKETdup }, { 0 }},
4670103e
CZ		 2614
2615 /* ld<.di><.aa><.x><zz> a,b,s9
cc07cda6 2616 00010bbbssssssssSBBBDaaZZXAAAAAA. */
4670103e
CZ		 2617 { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2618 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
cc07cda6 2619 { RA, BRAKET, RB, SIMM9_8R, BRAKETdup },
4670103e
CZ		 2620 { C_ZZ23, C_DI20, C_AA21, C_X25 }},
2621
2622 /* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */
2623 { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2624 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2625 { RA, BRAKET, RB, LIMM, BRAKETdup },
2626 { C_ZZ13, C_DI16, C_AA8, C_X15 }},
2627
cc07cda6 2628 /* mov_s b,u8 11011bbbuuuuuuuu. */
4670103e
CZ		 2629 { "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2630 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
cc07cda6 2631 { RB_S, UIMM8_8R_S }, { 0 }},
4670103e 2632
cc07cda6 2633 /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. */
4670103e
CZ		 2634 { "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2635 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
cc07cda6 2636 { RB, SIMM12_20R }, { C_F }},
4670103e
CZ		 2637
2638 /* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */
2639 { "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2640 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2641 { RB, LIMM }, { C_F }},
2642
cc07cda6 2643 /* sub_s c,b,u3 01101bbbccc01uuu. */
4670103e
CZ		 2644 { "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2645 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
cc07cda6 2646 { RC_S, RB_S, UIMM3_13R_S }, { 0 }},
4670103e 2647
cc07cda6 2648 /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA. */
4670103e
CZ		 2649 { "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2650 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
cc07cda6 2651 { RA, RB, UIMM6_20R }, { C_F }},
4670103e
CZ		 2652
2653 /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */
2654 { "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2655 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2656 { RA, RB, LIMM }, { C_F }},
2657
cc07cda6 2658 /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA. */
4670103e 2659 { "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
cc07cda6 2660 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20R }, { C_F }},
4670103e
CZ		 2661
2662 /* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */
2663 { "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
2664 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }},
2665
cc07cda6 2666 /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ. */
4670103e
CZ		 2667 { "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2668 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
cc07cda6 2669 { RB, UIMM6_20R }, { C_F, C_CC }},
4670103e
CZ		 2670
2671 /* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */
2672 { "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2673 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2674 { RB, LIMM }, { C_F, C_CC }},
2675
cc07cda6 2676 /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ. */
4670103e
CZ		 2677 { "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2678 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
cc07cda6 2679 { RB, RBdup, UIMM6_20R }, { C_F, C_CC }},
4670103e
CZ		 2680
2681 /* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */
2682 { "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2683 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2684 { RB, RBdup, LIMM }, { C_F, C_CC }}
2685};
2686
2687const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes);
4eb6f892 2688
bdfe53e3 2689/* Return length of an opcode in bytes. */
06fe285f
GM		 2690
2691int
2692arc_opcode_len (const struct arc_opcode *opcode)
2693{
2694 if (opcode->mask < 0x10000ull)
2695 return 2;
bdfe53e3
AB		 2696
2697 if (opcode->mask < 0x100000000ull)
2698 return 4;
2699
2700 if (opcode->mask < 0x1000000000000ull)
2701 return 6;
2702
2703 return 8;
06fe285f 2704}
GDB Binutils - Deliverables
This page took 1.780046 seconds and 4 git commands to generate.