Commit | Line | Data |
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886a2506 | 1 | /* ARC Auxiliary register definitions |
6f2750fe | 2 | Copyright (C) 2015-2016 Free Software Foundation, Inc. |
886a2506 NC |
3 | |
4 | Contributed by Claudiu Zissulescu (claziss@synopsys.com) | |
5 | ||
6 | This file is part of libopcodes. | |
7 | ||
8 | This library is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3, or (at your option) | |
11 | any later version. | |
12 | ||
13 | It is distributed in the hope that it will be useful, but WITHOUT | |
14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software Foundation, | |
20 | Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ | |
21 | ||
22 | DEF (0x0, STATUS) | |
23 | DEF (0x1, SEMAPHORE) | |
24 | DEF (0x2, LP_START) | |
25 | DEF (0x3, LP_END) | |
26 | DEF (0x4, IDENTITY) | |
27 | DEF (0x5, DEBUG) | |
28 | DEF (0x6, PC) | |
29 | DEF (0x7, ADCR) | |
30 | DEF (0x8, APCR) | |
31 | DEF (0x9, ACR) | |
32 | DEF (0xA, STATUS32) | |
33 | DEF (0xB, STATUS32_L1) | |
34 | DEF (0xC, STATUS32_L2) | |
35 | DEF (0xF, BPU_FLUSH) | |
36 | DEF (0x10, IVIC) | |
37 | DEF (0x10, IC_IVIC) | |
38 | DEF (0x11, CHE_MODE) | |
39 | DEF (0x11, IC_CTRL) | |
40 | DEF (0x12, MULHI) | |
41 | DEF (0x13, LOCKLINE) | |
42 | DEF (0x13, IC_LIL) | |
43 | DEF (0x14, DMC_CODE_RAM) | |
44 | DEF (0x15, TAG_ADDR_MASK) | |
45 | DEF (0x16, TAG_DATA_MASK) | |
46 | DEF (0x17, LINE_LENGTH_MASK) | |
47 | DEF (0x18, AUX_LDST_RAM) | |
48 | DEF (0x18, AUX_DCCM) | |
49 | DEF (0x19, UNLOCKLINE) | |
50 | DEF (0x19, IC_IVIL) | |
51 | DEF (0x1A, IC_RAM_ADDRESS) | |
52 | DEF (0x1A, IC_RAM_ADDRESS) | |
53 | DEF (0x1B, IC_TAG) | |
54 | DEF (0x1B, IC_TAG) | |
55 | DEF (0x1C, IC_WP) | |
56 | DEF (0x1C, IC_WP) | |
57 | DEF (0x1D, IC_DATA) | |
58 | DEF (0x1D, IC_DATA) | |
59 | DEF (0x20, SRAM_SEQ) | |
60 | DEF (0x21, COUNT0) | |
61 | DEF (0x22, CONTROL0) | |
62 | DEF (0x22, CONTROL0) | |
63 | DEF (0x23, LIMIT0) | |
64 | DEF (0x24, PCPORT) | |
65 | DEF (0x25, INT_VECTOR_BASE) | |
66 | DEF (0x26, AUX_VBFDW_MODE) | |
67 | DEF (0x26, JLI_BASE) | |
68 | DEF (0x27, AUX_VBFDW_BM0) | |
69 | DEF (0x28, AUX_VBFDW_BM1) | |
70 | DEF (0x29, AUX_VBFDW_ACCU) | |
71 | DEF (0x2A, AUX_VBFDW_OFST) | |
72 | DEF (0x2B, AUX_VBFDW_INTSTAT) | |
73 | DEF (0x2C, AX2 (A4)) | |
74 | DEF (0x2C, AUX_XMAC0_24) | |
75 | DEF (0x2D, AY2 (A4)) | |
76 | DEF (0x2D, AUX_XMAC1_24) | |
77 | DEF (0x2E, MX2 (A4)) | |
78 | DEF (0x2E, AUX_XMAC2_24) | |
79 | DEF (0x2F, MY2 (A4)) | |
80 | DEF (0x2F, AUX_FBF_STORE_16) | |
81 | DEF (0x30, AX0) | |
82 | DEF (0x31, AX1) | |
83 | DEF (0x32, AY0 (A4)) | |
84 | DEF (0x32, AUX_CRC_POLY) | |
85 | DEF (0x33, AY1 (A4)) | |
86 | DEF (0x33, AUX_CRC_MODE) | |
87 | DEF (0x34, MX0) | |
88 | DEF (0x35, MX1) | |
89 | DEF (0x36, MY0) | |
90 | DEF (0x37, MY1) | |
91 | DEF (0x38, XYCONFIG) | |
92 | DEF (0x39, SCRATCH_A) | |
93 | DEF (0x3A, BURSTSYS) | |
94 | DEF (0x3A, TSCH) | |
95 | DEF (0x3B, BURSTXYM) | |
96 | DEF (0x3C, BURSTSZ) | |
97 | DEF (0x3D, BURSTVAL) | |
98 | DEF (0x40, XTP_NEWVAL) | |
99 | DEF (0x41, AUX_MACMODE) | |
100 | DEF (0x42, LSP_NEWVAL) | |
101 | DEF (0x43, AUX_IRQ_LV12) | |
102 | DEF (0x44, AUX_XMAC0) | |
103 | DEF (0x45, AUX_XMAC1) | |
104 | DEF (0x46, AUX_XMAC2) | |
105 | DEF (0x47, DC_IVDC) | |
106 | DEF (0x48, DC_CTRL) | |
107 | DEF (0x49, DC_LDL) | |
108 | DEF (0x4A, DC_IVDL) | |
109 | DEF (0x4B, DC_FLSH) | |
110 | DEF (0x4C, DC_FLDL) | |
111 | DEF (0x50, HEXDATA) | |
112 | DEF (0x51, HEXCTRL) | |
113 | DEF (0x52, LED) | |
114 | DEF (0x53, LCDINSTR (A4)) | |
115 | DEF (0x54, LCDDATA (A4)) | |
116 | DEF (0x55, LCDSTAT (A4)) | |
117 | DEF (0x56, DILSTAT) | |
118 | DEF (0x57, SWSTAT) | |
119 | DEF (0x58, DC_RAM_ADDR) | |
120 | DEF (0x58, DC_RAM_ADDR) | |
121 | DEF (0x59, DC_TAG) | |
122 | DEF (0x59, DC_TAG) | |
123 | DEF (0x5A, DC_WP) | |
124 | DEF (0x5B, DC_DATA) | |
125 | DEF (0x61, DCCM_BASE_BUILD) | |
126 | DEF (0x62, CRC_BUILD) | |
127 | DEF (0x63, BTA_LINK_BUILD) | |
128 | DEF (0x64, VBFDW_BUILD) | |
129 | DEF (0x65, EA_BUILD) | |
130 | DEF (0x66, DATASPACE) | |
131 | DEF (0x67, MEMSUBSYS) | |
132 | DEF (0x68, VECBASE_AC_BUILD) | |
133 | DEF (0x69, P_BASE_ADDR) | |
134 | DEF (0x6A, DATA_UNCACHED_BUILD) | |
135 | DEF (0x6B, FP_BUILD) | |
136 | DEF (0x6C, DPFP_BUILD) | |
137 | DEF (0x6D, MPU_BUILD) | |
138 | DEF (0x6E, RF_BUILD) | |
139 | DEF (0x6F, MMU_BUILD) | |
140 | DEF (0x70, AA2_BUILD) | |
141 | DEF (0x71, VECBASE_BUILD) | |
142 | DEF (0x72, D_CACHE_BUILD) | |
143 | DEF (0x73, MADI_BUILD) | |
144 | DEF (0x74, DCCM_BUILD) | |
145 | DEF (0x75, TIMER_BUILD) | |
146 | DEF (0x76, AP_BUILD) | |
147 | DEF (0x77, I_CACHE_BUILD) | |
148 | DEF (0x78, ICCM_BUILD) | |
149 | DEF (0x79, DSPRAM_BUILD) | |
150 | DEF (0x7A, MAC_BUILD) | |
151 | DEF (0x7B, MULTIPLY_BUILD) | |
152 | DEF (0x7C, SWAP_BUILD) | |
153 | DEF (0x7D, NORM_BUILD) | |
154 | DEF (0x7E, MINMAX_BUILD) | |
155 | DEF (0x7F, BARREL_BUILD) | |
156 | DEF (0x80, AX0) | |
157 | DEF (0x81, AX1) | |
158 | DEF (0x82, AX2) | |
159 | DEF (0x83, AX3) | |
160 | DEF (0x84, AY0) | |
161 | DEF (0x85, AY1) | |
162 | DEF (0x86, AY2) | |
163 | DEF (0x87, AY3) | |
164 | DEF (0x88, MX00) | |
165 | DEF (0x89, MX01) | |
166 | DEF (0x8A, MX10) | |
167 | DEF (0x8B, MX11) | |
168 | DEF (0x8C, MX20) | |
169 | DEF (0x8D, MX21) | |
170 | DEF (0x8E, MX30) | |
171 | DEF (0x8F, MX31) | |
172 | DEF (0x90, MY00) | |
173 | DEF (0x91, MY01) | |
174 | DEF (0x92, MY10) | |
175 | DEF (0x93, MY11) | |
176 | DEF (0x94, MY20) | |
177 | DEF (0x95, MY21) | |
178 | DEF (0x96, MY30) | |
179 | DEF (0x97, MY31) | |
180 | DEF (0x98, XYCONFIG) | |
181 | DEF (0x99, BURSTSYS) | |
182 | DEF (0x9A, BURSTXYM) | |
183 | DEF (0x9B, BURSTSZ) | |
184 | DEF (0x9C, BURSTVAL) | |
185 | DEF (0x9D, XYLSBASEX) | |
186 | DEF (0x9E, XYLSBASEY) | |
187 | DEF (0x9F, AUX_XMACLW_H) | |
188 | DEF (0xA0, AUX_XMACLW_L) | |
189 | DEF (0xA1, SE_CTRL) | |
190 | DEF (0xA2, SE_STAT) | |
191 | DEF (0xA3, SE_ERR) | |
192 | DEF (0xA4, SE_EADR) | |
193 | DEF (0xA5, SE_SPC) | |
194 | DEF (0xA6, SDM_BASE) | |
195 | DEF (0xA7, SCM_BASE) | |
196 | DEF (0xA8, SE_DBG_CTRL) | |
197 | DEF (0xA9, SE_DBG_DATA0) | |
198 | DEF (0xAA, SE_DBG_DATA1) | |
199 | DEF (0xAB, SE_DBG_DATA2) | |
200 | DEF (0xAC, SE_DBG_DATA3) | |
201 | DEF (0xAD, SE_WATCH) | |
202 | DEF (0xC0, BPU_BUILD) | |
203 | DEF (0xC1, ARC600_BUILD_CONFIG) | |
204 | DEF (0xC2, ISA_CONFIG) | |
205 | DEF (0xF4, HWP_BUILD) | |
206 | DEF (0xF5, PCT_BUILD) | |
207 | DEF (0xF6, CC_BUILD) | |
208 | DEF (0xF7, PM_BCR) | |
209 | DEF (0xF8, SCQ_SWITCH_BUILD) | |
210 | DEF (0xF9, VRAPTOR_BUILD) | |
211 | DEF (0xFA, DMA_CONFIG) | |
212 | DEF (0xFB, SIMD_CONFIG) | |
213 | DEF (0xFC, VLC_BUILD) | |
214 | DEF (0xFD, SIMD_DMA_BUILD) | |
215 | DEF (0xFE, IFETCH_QUEUE_BUILD) | |
216 | DEF (0xFF, SMART_BUILD) | |
217 | DEF (0x100, COUNT1) | |
218 | DEF (0x101, CONTROL1) | |
219 | DEF (0x101, CONTROL1) | |
220 | DEF (0x102, LIMIT1) | |
221 | DEF (0x103, TIMER_XX) | |
222 | DEF (0x120, ARCANGEL_PERIPH_XX) | |
223 | DEF (0x140, PERIPH_XX) | |
224 | DEF (0x200, AUX_IRQ_LEV) | |
225 | DEF (0x201, AUX_IRQ_HINT) | |
226 | DEF (0x202, AUX_INTER_CORE_INTERRUPT) | |
227 | DEF (0x210, AES_AUX_0) | |
228 | DEF (0x211, AES_AUX_1) | |
229 | DEF (0x212, AES_AUX_2) | |
230 | DEF (0x213, AES_CRYPT_MODE) | |
231 | DEF (0x214, AES_AUXS) | |
232 | DEF (0x215, AES_AUXI) | |
233 | DEF (0x216, AES_AUX_3) | |
234 | DEF (0x217, AES_AUX_4) | |
235 | DEF (0x218, ARITH_CTL_AUX) | |
236 | DEF (0x219, DES_AUX) | |
237 | DEF (0x220, AP_AMV0) | |
238 | DEF (0x221, AP_AMM0) | |
239 | DEF (0x222, AP_AC0) | |
240 | DEF (0x223, AP_AMV1) | |
241 | DEF (0x224, AP_AMM1) | |
242 | DEF (0x225, AP_AC1) | |
243 | DEF (0x226, AP_AMV2) | |
244 | DEF (0x227, AP_AMM2) | |
245 | DEF (0x228, AP_AC2) | |
246 | DEF (0x229, AP_AMV3) | |
247 | DEF (0x22A, AP_AMM3) | |
248 | DEF (0x22B, AP_AC3) | |
249 | DEF (0x22C, AP_AMV4) | |
250 | DEF (0x22D, AP_AMM4) | |
251 | DEF (0x22E, AP_AC4) | |
252 | DEF (0x22F, AP_AMV5) | |
253 | DEF (0x230, AP_AMM5) | |
254 | DEF (0x231, AP_AC5) | |
255 | DEF (0x232, AP_AMV6) | |
256 | DEF (0x233, AP_AMM6) | |
257 | DEF (0x234, AP_AC6) | |
258 | DEF (0x235, AP_AMV7) | |
259 | DEF (0x236, AP_AMM7) | |
260 | DEF (0x237, AP_AC7) | |
261 | DEF (0x240, CC_*) | |
262 | DEF (0x250, PCT_COUNT*) | |
263 | DEF (0x260, PCT_SNAP*) | |
264 | DEF (0x270, PCT_CONFIG*) | |
265 | DEF (0x278, PCT_CONTROL) | |
266 | DEF (0x279, PCT_BANK) | |
267 | DEF (0x300, FP_STATUS) | |
268 | DEF (0x300, RTT (A5 - A4)) | |
269 | DEF (0x301, AUX_DPFP1L) | |
270 | DEF (0x301, RTT (A5 - A4)) | |
271 | DEF (0x302, AUX_DPFP1H) | |
272 | DEF (0x302, RTT (A5 - A4)) | |
273 | DEF (0x303, AUX_DPFP2L) | |
274 | DEF (0x303, RTT (A5 - A4)) | |
275 | DEF (0x304, AUX_DPFP2H) | |
276 | DEF (0x304, RTT (A5 - A4)) | |
277 | DEF (0x305, DPFP_STATUS) | |
278 | DEF (0x305, RTT (A5 - A4)) | |
279 | DEF (0x306, RTT) | |
280 | DEF (0x400, ERET) | |
281 | DEF (0x401, ERBTA) | |
282 | DEF (0x402, ERSTATUS) | |
283 | DEF (0x403, ECR) | |
284 | DEF (0x404, EFA) | |
285 | DEF (0x405, TLBPD0) | |
286 | DEF (0x406, TLBPD1) | |
287 | DEF (0x407, TLBIndex) | |
288 | DEF (0x408, TLBCommand) | |
289 | DEF (0x409, PID) | |
290 | DEF (0x409, MPUEN) | |
291 | DEF (0x40A, ICAUSE1) | |
292 | DEF (0x40B, ICAUSE2) | |
293 | DEF (0x40C, AUX_IENABLE) | |
294 | DEF (0x40D, AUX_ITRIGGER) | |
295 | DEF (0x410, XPU) | |
296 | DEF (0x412, BTA) | |
297 | DEF (0x413, BTA_L1) | |
298 | DEF (0x414, BTA_L2) | |
299 | DEF (0x415, AUX_IRQ_PULSE_CANCEL) | |
300 | DEF (0x416, AUX_IRQ_PENDING) | |
301 | DEF (0x418, SCRATCH_DATA0) | |
302 | DEF (0x420, MPUIC) | |
303 | DEF (0x421, MPUFA) | |
304 | DEF (0x422, MPURDB0) | |
305 | DEF (0x423, MPURDP0) | |
306 | DEF (0x424, MPURDB1) | |
307 | DEF (0x425, MPURDP1) | |
308 | DEF (0x426, MPURDB2) | |
309 | DEF (0x427, MPURDP2) | |
310 | DEF (0x428, MPURDB3) | |
311 | DEF (0x429, MPURDP3) | |
312 | DEF (0x42A, MPURDB4) | |
313 | DEF (0x42B, MPURDP4) | |
314 | DEF (0x42C, MPURDB5) | |
315 | DEF (0x42D, MPURDP5) | |
316 | DEF (0x42E, MPURDB6) | |
317 | DEF (0x42F, MPURDP6) | |
318 | DEF (0x430, MPURDB7) | |
319 | DEF (0x431, MPURDP7) | |
320 | DEF (0x432, MPURDB8) | |
321 | DEF (0x433, MPURDP8) | |
322 | DEF (0x434, MPURDB9) | |
323 | DEF (0x435, MPURDP9) | |
324 | DEF (0x436, MPURDB10) | |
325 | DEF (0x437, MPURDP10) | |
326 | DEF (0x438, MPURDB11) | |
327 | DEF (0x439, MPURDP11) | |
328 | DEF (0x43A, MPURDB12) | |
329 | DEF (0x43B, MPURDP12) | |
330 | DEF (0x43C, MPURDB13) | |
331 | DEF (0x43D, MPURDP13) | |
332 | DEF (0x43E, MPURDB14) | |
333 | DEF (0x43F, MPURDP14) | |
334 | DEF (0x440, MPURDB15) | |
335 | DEF (0x441, MPURDP15) | |
336 | DEF (0x44F, EIA_FLAGS) | |
337 | DEF (0x450, PM_STATUS) | |
338 | DEF (0x451, WAKE) | |
339 | DEF (0x452, DVFS_PERFORMANCE) | |
340 | DEF (0x453, PWR_CTRL) | |
341 | DEF (0x500, AUX_VLC_BUF_IDX) | |
342 | DEF (0x501, AUX_VLC_READ_BUF) | |
343 | DEF (0x502, AUX_VLC_VALID_BITS) | |
344 | DEF (0x503, AUX_VLC_BUF_IN) | |
345 | DEF (0x504, AUX_VLC_BUF_FREE) | |
346 | DEF (0x505, AUX_VLC_IBUF_STATUS) | |
347 | DEF (0x506, AUX_VLC_SETUP) | |
348 | DEF (0x507, AUX_VLC_BITS) | |
349 | DEF (0x508, AUX_VLC_TABLE) | |
350 | DEF (0x509, AUX_VLC_GET_SYMBOL) | |
351 | DEF (0x50A, AUX_VLC_READ_SYMBOL) | |
352 | DEF (0x510, AUX_UCAVLC_SETUP) | |
353 | DEF (0x511, AUX_UCAVLC_STATE) | |
354 | DEF (0x512, AUX_CAVLC_ZERO_LEFT) | |
355 | DEF (0x514, AUX_UVLC_I_STATE) | |
356 | DEF (0x51C, AUX_VLC_DMA_PTR) | |
357 | DEF (0x51D, AUX_VLC_DMA_END) | |
358 | DEF (0x51E, AUX_VLC_DMA_ESC) | |
359 | DEF (0x51F, AUX_VLC_DMA_CTRL) | |
360 | DEF (0x520, AUX_VLC_GET_0BIT) | |
361 | DEF (0x521, AUX_VLC_GET_1BIT) | |
362 | DEF (0x522, AUX_VLC_GET_2BIT) | |
363 | DEF (0x523, AUX_VLC_GET_3BIT) | |
364 | DEF (0x524, AUX_VLC_GET_4BIT) | |
365 | DEF (0x525, AUX_VLC_GET_5BIT) | |
366 | DEF (0x526, AUX_VLC_GET_6BIT) | |
367 | DEF (0x527, AUX_VLC_GET_7BIT) | |
368 | DEF (0x528, AUX_VLC_GET_8BIT) | |
369 | DEF (0x529, AUX_VLC_GET_9BIT) | |
370 | DEF (0x52A, AUX_VLC_GET_10BIT) | |
371 | DEF (0x52B, AUX_VLC_GET_11BIT) | |
372 | DEF (0x52C, AUX_VLC_GET_12BIT) | |
373 | DEF (0x52D, AUX_VLC_GET_13BIT) | |
374 | DEF (0x52E, AUX_VLC_GET_14BIT) | |
375 | DEF (0x52F, AUX_VLC_GET_15BIT) | |
376 | DEF (0x530, AUX_VLC_GET_16BIT) | |
377 | DEF (0x531, AUX_VLC_GET_17BIT) | |
378 | DEF (0x532, AUX_VLC_GET_18BIT) | |
379 | DEF (0x533, AUX_VLC_GET_19BIT) | |
380 | DEF (0x534, AUX_VLC_GET_20BIT) | |
381 | DEF (0x535, AUX_VLC_GET_21BIT) | |
382 | DEF (0x536, AUX_VLC_GET_22BIT) | |
383 | DEF (0x537, AUX_VLC_GET_23BIT) | |
384 | DEF (0x538, AUX_VLC_GET_24BIT) | |
385 | DEF (0x539, AUX_VLC_GET_25BIT) | |
386 | DEF (0x53A, AUX_VLC_GET_26BIT) | |
387 | DEF (0x53B, AUX_VLC_GET_27BIT) | |
388 | DEF (0x53C, AUX_VLC_GET_28BIT) | |
389 | DEF (0x53D, AUX_VLC_GET_29BIT) | |
390 | DEF (0x53E, AUX_VLC_GET_30BIT) | |
391 | DEF (0x53F, AUX_VLC_GET_31BIT) | |
392 | DEF (0x540, AUX_CABAC_CTRL) | |
393 | DEF (0x541, AUX_CABAC_CTX_STATE) | |
394 | DEF (0x542, AUX_CABAC_COD_PARAM) | |
395 | DEF (0x543, AUX_CABAC_MISC0) | |
396 | DEF (0x544, AUX_CABAC_MISC1) | |
397 | DEF (0x545, AUX_CABAC_MISC2) | |
398 | DEF (0x600, ARC600_BUILD_CONFIG) | |
399 | DEF (0x700, SMART_CONTROL) | |
400 | DEF (0x701, SMART_DATA_0) | |
401 | DEF (0x701, SMART_DATA_1) | |
402 | DEF (0x701, SMART_DATA_2) | |
403 | DEF (0x701, SMART_DATA_3) |