Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* Instruction printing code for the ARM |
060d22b0 NC |
2 | Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 |
3 | Free Software Foundation, Inc. | |
252b5132 RH |
4 | Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) |
5 | Modification by James G. Smith (jsmith@cygnus.co.uk) | |
6 | ||
7 | This file is part of libopcodes. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify it under | |
10 | the terms of the GNU General Public License as published by the Free | |
11 | Software Foundation; either version 2 of the License, or (at your option) | |
12 | any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, but WITHOUT | |
15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
17 | more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program; if not, write to the Free Software | |
21 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
22 | ||
cb6a5892 | 23 | #include "sysdep.h" |
252b5132 RH |
24 | #include "dis-asm.h" |
25 | #define DEFINE_TABLE | |
26 | #include "arm-opc.h" | |
27 | #include "coff/internal.h" | |
28 | #include "libcoff.h" | |
29 | #include "opintl.h" | |
30 | ||
31 | /* FIXME: This shouldn't be done here */ | |
32 | #include "elf-bfd.h" | |
33 | #include "elf/internal.h" | |
34 | #include "elf/arm.h" | |
35 | ||
01c7f630 | 36 | #ifndef streq |
58efb6c0 | 37 | #define streq(a,b) (strcmp ((a), (b)) == 0) |
01c7f630 | 38 | #endif |
58efb6c0 | 39 | |
01c7f630 | 40 | #ifndef strneq |
58efb6c0 NC |
41 | #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0) |
42 | #endif | |
43 | ||
44 | #ifndef NUM_ELEM | |
45 | #define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0]) | |
01c7f630 NC |
46 | #endif |
47 | ||
5876e06d | 48 | static char * arm_conditional[] = |
252b5132 RH |
49 | {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", |
50 | "hi", "ls", "ge", "lt", "gt", "le", "", "nv"}; | |
51 | ||
58efb6c0 NC |
52 | typedef struct |
53 | { | |
54 | const char * name; | |
55 | const char * description; | |
56 | const char * reg_names[16]; | |
57 | } | |
58 | arm_regname; | |
dd92f639 | 59 | |
58efb6c0 NC |
60 | static arm_regname regnames[] = |
61 | { | |
62 | { "raw" , "Select raw register names", | |
63 | { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}}, | |
7c03c75e SB |
64 | { "gcc", "Select register names used by GCC", |
65 | { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }}, | |
58efb6c0 NC |
66 | { "std", "Select register names used in ARM's ISA documentation", |
67 | { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }}, | |
68 | { "apcs", "Select register names used in the APCS", | |
69 | { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }}, | |
70 | { "atpcs", "Select register names used in the ATPCS", | |
71 | { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }}, | |
a7f8487e | 72 | { "special-atpcs", "Select special register names used in the ATPCS", |
58efb6c0 NC |
73 | { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }} |
74 | }; | |
75 | ||
7c03c75e | 76 | /* Default to GCC register name set. */ |
58efb6c0 NC |
77 | static unsigned int regname_selected = 1; |
78 | ||
79 | #define NUM_ARM_REGNAMES NUM_ELEM (regnames) | |
80 | #define arm_regnames regnames[regname_selected].reg_names | |
252b5132 | 81 | |
01c7f630 NC |
82 | static boolean force_thumb = false; |
83 | ||
5876e06d | 84 | static char * arm_fp_const[] = |
252b5132 RH |
85 | {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"}; |
86 | ||
5876e06d | 87 | static char * arm_shift[] = |
252b5132 | 88 | {"lsl", "lsr", "asr", "ror"}; |
01c7f630 NC |
89 | \f |
90 | /* Forward declarations. */ | |
91 | static void arm_decode_shift PARAMS ((long, fprintf_ftype, void *)); | |
92 | static int print_insn_arm PARAMS ((bfd_vma, struct disassemble_info *, long)); | |
93 | static int print_insn_thumb PARAMS ((bfd_vma, struct disassemble_info *, long)); | |
01c7f630 | 94 | static void parse_disassembler_options PARAMS ((char *)); |
58efb6c0 | 95 | static int print_insn PARAMS ((bfd_vma, struct disassemble_info *, boolean)); |
a7f8487e FN |
96 | int get_arm_regname_num_options (void); |
97 | int set_arm_regname_option (int option); | |
98 | int get_arm_regnames (int option, const char **setname, | |
99 | const char **setdescription, | |
100 | const char ***register_names); | |
01c7f630 NC |
101 | \f |
102 | /* Functions. */ | |
a7f8487e FN |
103 | int |
104 | get_arm_regname_num_options (void) | |
105 | { | |
106 | return NUM_ARM_REGNAMES; | |
107 | } | |
108 | ||
109 | int | |
110 | set_arm_regname_option (int option) | |
111 | { | |
112 | int old = regname_selected; | |
113 | regname_selected = option; | |
114 | return old; | |
115 | } | |
116 | ||
117 | int | |
118 | get_arm_regnames (int option, const char **setname, | |
119 | const char **setdescription, | |
120 | const char ***register_names) | |
121 | { | |
122 | *setname = regnames[option].name; | |
123 | *setdescription = regnames[option].description; | |
124 | *register_names = regnames[option].reg_names; | |
125 | return 16; | |
126 | } | |
127 | ||
252b5132 RH |
128 | static void |
129 | arm_decode_shift (given, func, stream) | |
130 | long given; | |
131 | fprintf_ftype func; | |
5876e06d | 132 | void * stream; |
252b5132 RH |
133 | { |
134 | func (stream, "%s", arm_regnames[given & 0xf]); | |
5876e06d | 135 | |
252b5132 RH |
136 | if ((given & 0xff0) != 0) |
137 | { | |
138 | if ((given & 0x10) == 0) | |
139 | { | |
140 | int amount = (given & 0xf80) >> 7; | |
141 | int shift = (given & 0x60) >> 5; | |
5876e06d | 142 | |
252b5132 RH |
143 | if (amount == 0) |
144 | { | |
145 | if (shift == 3) | |
146 | { | |
147 | func (stream, ", rrx"); | |
148 | return; | |
149 | } | |
5876e06d | 150 | |
252b5132 RH |
151 | amount = 32; |
152 | } | |
5876e06d | 153 | |
252b5132 RH |
154 | func (stream, ", %s #%d", arm_shift[shift], amount); |
155 | } | |
156 | else | |
157 | func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5], | |
158 | arm_regnames[(given & 0xf00) >> 8]); | |
159 | } | |
160 | } | |
161 | ||
162 | /* Print one instruction from PC on INFO->STREAM. | |
163 | Return the size of the instruction (always 4 on ARM). */ | |
252b5132 RH |
164 | static int |
165 | print_insn_arm (pc, info, given) | |
5876e06d NC |
166 | bfd_vma pc; |
167 | struct disassemble_info * info; | |
168 | long given; | |
252b5132 RH |
169 | { |
170 | struct arm_opcode * insn; | |
171 | void * stream = info->stream; | |
172 | fprintf_ftype func = info->fprintf_func; | |
173 | ||
174 | for (insn = arm_opcodes; insn->assembler; insn++) | |
175 | { | |
176 | if ((given & insn->mask) == insn->value) | |
177 | { | |
178 | char * c; | |
179 | ||
180 | for (c = insn->assembler; *c; c++) | |
181 | { | |
182 | if (*c == '%') | |
183 | { | |
184 | switch (*++c) | |
185 | { | |
186 | case '%': | |
187 | func (stream, "%%"); | |
188 | break; | |
189 | ||
190 | case 'a': | |
191 | if (((given & 0x000f0000) == 0x000f0000) | |
192 | && ((given & 0x02000000) == 0)) | |
193 | { | |
194 | int offset = given & 0xfff; | |
195 | ||
196 | func (stream, "[pc"); | |
197 | ||
198 | if (given & 0x01000000) | |
199 | { | |
200 | if ((given & 0x00800000) == 0) | |
201 | offset = - offset; | |
202 | ||
203 | /* pre-indexed */ | |
40536497 | 204 | func (stream, ", #%d]", offset); |
252b5132 RH |
205 | |
206 | offset += pc + 8; | |
207 | ||
58efb6c0 NC |
208 | /* Cope with the possibility of write-back |
209 | being used. Probably a very dangerous thing | |
210 | for the programmer to do, but who are we to | |
211 | argue ? */ | |
252b5132 RH |
212 | if (given & 0x00200000) |
213 | func (stream, "!"); | |
214 | } | |
215 | else | |
216 | { | |
58efb6c0 | 217 | /* Post indexed. */ |
40536497 | 218 | func (stream, "], #%d", offset); |
252b5132 | 219 | |
58efb6c0 | 220 | offset = pc + 8; /* ie ignore the offset. */ |
252b5132 RH |
221 | } |
222 | ||
223 | func (stream, "\t; "); | |
224 | info->print_address_func (offset, info); | |
225 | } | |
226 | else | |
227 | { | |
228 | func (stream, "[%s", | |
229 | arm_regnames[(given >> 16) & 0xf]); | |
230 | if ((given & 0x01000000) != 0) | |
231 | { | |
232 | if ((given & 0x02000000) == 0) | |
233 | { | |
234 | int offset = given & 0xfff; | |
235 | if (offset) | |
236 | func (stream, ", %s#%d", | |
237 | (((given & 0x00800000) == 0) | |
238 | ? "-" : ""), offset); | |
239 | } | |
240 | else | |
241 | { | |
242 | func (stream, ", %s", | |
243 | (((given & 0x00800000) == 0) | |
244 | ? "-" : "")); | |
245 | arm_decode_shift (given, func, stream); | |
246 | } | |
247 | ||
248 | func (stream, "]%s", | |
249 | ((given & 0x00200000) != 0) ? "!" : ""); | |
250 | } | |
251 | else | |
252 | { | |
253 | if ((given & 0x02000000) == 0) | |
254 | { | |
255 | int offset = given & 0xfff; | |
256 | if (offset) | |
257 | func (stream, "], %s#%d", | |
258 | (((given & 0x00800000) == 0) | |
259 | ? "-" : ""), offset); | |
260 | else | |
261 | func (stream, "]"); | |
262 | } | |
263 | else | |
264 | { | |
265 | func (stream, "], %s", | |
266 | (((given & 0x00800000) == 0) | |
267 | ? "-" : "")); | |
268 | arm_decode_shift (given, func, stream); | |
269 | } | |
270 | } | |
271 | } | |
272 | break; | |
273 | ||
274 | case 's': | |
275 | if ((given & 0x004f0000) == 0x004f0000) | |
276 | { | |
58efb6c0 | 277 | /* PC relative with immediate offset. */ |
252b5132 | 278 | int offset = ((given & 0xf00) >> 4) | (given & 0xf); |
886796f9 | 279 | |
252b5132 RH |
280 | if ((given & 0x00800000) == 0) |
281 | offset = -offset; | |
886796f9 | 282 | |
40536497 | 283 | func (stream, "[pc, #%d]\t; ", offset); |
886796f9 | 284 | |
252b5132 RH |
285 | (*info->print_address_func) |
286 | (offset + pc + 8, info); | |
287 | } | |
288 | else | |
289 | { | |
290 | func (stream, "[%s", | |
291 | arm_regnames[(given >> 16) & 0xf]); | |
292 | if ((given & 0x01000000) != 0) | |
293 | { | |
58efb6c0 | 294 | /* Pre-indexed. */ |
252b5132 RH |
295 | if ((given & 0x00400000) == 0x00400000) |
296 | { | |
58efb6c0 | 297 | /* Immediate. */ |
252b5132 RH |
298 | int offset = ((given & 0xf00) >> 4) | (given & 0xf); |
299 | if (offset) | |
300 | func (stream, ", %s#%d", | |
301 | (((given & 0x00800000) == 0) | |
302 | ? "-" : ""), offset); | |
303 | } | |
304 | else | |
305 | { | |
58efb6c0 | 306 | /* Register. */ |
252b5132 RH |
307 | func (stream, ", %s%s", |
308 | (((given & 0x00800000) == 0) | |
309 | ? "-" : ""), | |
310 | arm_regnames[given & 0xf]); | |
311 | } | |
312 | ||
313 | func (stream, "]%s", | |
314 | ((given & 0x00200000) != 0) ? "!" : ""); | |
315 | } | |
316 | else | |
317 | { | |
58efb6c0 | 318 | /* Post-indexed. */ |
252b5132 RH |
319 | if ((given & 0x00400000) == 0x00400000) |
320 | { | |
58efb6c0 | 321 | /* Immediate. */ |
252b5132 RH |
322 | int offset = ((given & 0xf00) >> 4) | (given & 0xf); |
323 | if (offset) | |
324 | func (stream, "], %s#%d", | |
325 | (((given & 0x00800000) == 0) | |
326 | ? "-" : ""), offset); | |
327 | else | |
328 | func (stream, "]"); | |
329 | } | |
330 | else | |
331 | { | |
58efb6c0 | 332 | /* Register. */ |
252b5132 RH |
333 | func (stream, "], %s%s", |
334 | (((given & 0x00800000) == 0) | |
335 | ? "-" : ""), | |
336 | arm_regnames[given & 0xf]); | |
337 | } | |
338 | } | |
339 | } | |
340 | break; | |
341 | ||
342 | case 'b': | |
343 | (*info->print_address_func) | |
344 | (BDISP (given) * 4 + pc + 8, info); | |
345 | break; | |
346 | ||
347 | case 'c': | |
348 | func (stream, "%s", | |
349 | arm_conditional [(given >> 28) & 0xf]); | |
350 | break; | |
351 | ||
352 | case 'm': | |
353 | { | |
354 | int started = 0; | |
355 | int reg; | |
356 | ||
357 | func (stream, "{"); | |
358 | for (reg = 0; reg < 16; reg++) | |
359 | if ((given & (1 << reg)) != 0) | |
360 | { | |
361 | if (started) | |
362 | func (stream, ", "); | |
363 | started = 1; | |
364 | func (stream, "%s", arm_regnames[reg]); | |
365 | } | |
366 | func (stream, "}"); | |
367 | } | |
368 | break; | |
369 | ||
370 | case 'o': | |
371 | if ((given & 0x02000000) != 0) | |
372 | { | |
373 | int rotate = (given & 0xf00) >> 7; | |
374 | int immed = (given & 0xff); | |
9f20bbfd NC |
375 | immed = (((immed << (32 - rotate)) |
376 | | (immed >> rotate)) & 0xffffffff); | |
377 | func (stream, "#%d\t; 0x%x", immed, immed); | |
252b5132 RH |
378 | } |
379 | else | |
380 | arm_decode_shift (given, func, stream); | |
381 | break; | |
382 | ||
383 | case 'p': | |
384 | if ((given & 0x0000f000) == 0x0000f000) | |
385 | func (stream, "p"); | |
386 | break; | |
387 | ||
388 | case 't': | |
389 | if ((given & 0x01200000) == 0x00200000) | |
390 | func (stream, "t"); | |
391 | break; | |
392 | ||
393 | case 'h': | |
394 | if ((given & 0x00000020) == 0x00000020) | |
395 | func (stream, "h"); | |
396 | else | |
397 | func (stream, "b"); | |
398 | break; | |
399 | ||
400 | case 'A': | |
401 | func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); | |
402 | if ((given & 0x01000000) != 0) | |
403 | { | |
404 | int offset = given & 0xff; | |
405 | if (offset) | |
406 | func (stream, ", %s#%d]%s", | |
407 | ((given & 0x00800000) == 0 ? "-" : ""), | |
408 | offset * 4, | |
409 | ((given & 0x00200000) != 0 ? "!" : "")); | |
410 | else | |
411 | func (stream, "]"); | |
412 | } | |
413 | else | |
414 | { | |
415 | int offset = given & 0xff; | |
416 | if (offset) | |
417 | func (stream, "], %s#%d", | |
418 | ((given & 0x00800000) == 0 ? "-" : ""), | |
419 | offset * 4); | |
420 | else | |
421 | func (stream, "]"); | |
422 | } | |
423 | break; | |
424 | ||
077b8428 NC |
425 | case 'B': |
426 | /* Print ARM V5 BLX(1) address: pc+25 bits. */ | |
427 | { | |
428 | bfd_vma address; | |
429 | bfd_vma offset = 0; | |
430 | ||
431 | if (given & 0x00800000) | |
432 | /* Is signed, hi bits should be ones. */ | |
433 | offset = (-1) ^ 0x00ffffff; | |
434 | ||
435 | /* Offset is (SignExtend(offset field)<<2). */ | |
436 | offset += given & 0x00ffffff; | |
437 | offset <<= 2; | |
438 | address = offset + pc + 8; | |
439 | ||
440 | if (given & 0x01000000) | |
441 | /* H bit allows addressing to 2-byte boundaries. */ | |
442 | address += 2; | |
443 | ||
444 | info->print_address_func (address, info); | |
445 | } | |
446 | break; | |
447 | ||
b1ee46c5 AH |
448 | case 'I': |
449 | /* Print a Cirrus/DSP shift immediate. */ | |
450 | /* Immediates are 7bit signed ints with bits 0..3 in | |
451 | bits 0..3 of opcode and bits 4..6 in bits 5..7 | |
452 | of opcode. */ | |
453 | { | |
454 | int imm; | |
455 | ||
456 | imm = (given & 0xf) | ((given & 0xe0) >> 1); | |
457 | ||
458 | /* Is ``imm'' a negative number? */ | |
459 | if (imm & 0x40) | |
460 | imm |= (-1 << 7); | |
461 | ||
462 | func (stream, "%d", imm); | |
463 | } | |
464 | ||
465 | break; | |
466 | ||
252b5132 | 467 | case 'C': |
6eeeb4b4 AO |
468 | func (stream, "_"); |
469 | if (given & 0x80000) | |
470 | func (stream, "f"); | |
471 | if (given & 0x40000) | |
472 | func (stream, "s"); | |
473 | if (given & 0x20000) | |
474 | func (stream, "x"); | |
475 | if (given & 0x10000) | |
476 | func (stream, "c"); | |
252b5132 RH |
477 | break; |
478 | ||
479 | case 'F': | |
480 | switch (given & 0x00408000) | |
481 | { | |
482 | case 0: | |
483 | func (stream, "4"); | |
484 | break; | |
485 | case 0x8000: | |
486 | func (stream, "1"); | |
487 | break; | |
488 | case 0x00400000: | |
489 | func (stream, "2"); | |
490 | break; | |
491 | default: | |
492 | func (stream, "3"); | |
493 | } | |
494 | break; | |
495 | ||
496 | case 'P': | |
497 | switch (given & 0x00080080) | |
498 | { | |
499 | case 0: | |
500 | func (stream, "s"); | |
501 | break; | |
502 | case 0x80: | |
503 | func (stream, "d"); | |
504 | break; | |
505 | case 0x00080000: | |
506 | func (stream, "e"); | |
507 | break; | |
508 | default: | |
509 | func (stream, _("<illegal precision>")); | |
510 | break; | |
511 | } | |
512 | break; | |
513 | case 'Q': | |
514 | switch (given & 0x00408000) | |
515 | { | |
516 | case 0: | |
517 | func (stream, "s"); | |
518 | break; | |
519 | case 0x8000: | |
520 | func (stream, "d"); | |
521 | break; | |
522 | case 0x00400000: | |
523 | func (stream, "e"); | |
524 | break; | |
525 | default: | |
526 | func (stream, "p"); | |
527 | break; | |
528 | } | |
529 | break; | |
530 | case 'R': | |
531 | switch (given & 0x60) | |
532 | { | |
533 | case 0: | |
534 | break; | |
535 | case 0x20: | |
536 | func (stream, "p"); | |
537 | break; | |
538 | case 0x40: | |
539 | func (stream, "m"); | |
540 | break; | |
541 | default: | |
542 | func (stream, "z"); | |
543 | break; | |
544 | } | |
545 | break; | |
546 | ||
547 | case '0': case '1': case '2': case '3': case '4': | |
548 | case '5': case '6': case '7': case '8': case '9': | |
549 | { | |
550 | int bitstart = *c++ - '0'; | |
551 | int bitend = 0; | |
552 | while (*c >= '0' && *c <= '9') | |
553 | bitstart = (bitstart * 10) + *c++ - '0'; | |
554 | ||
555 | switch (*c) | |
556 | { | |
557 | case '-': | |
558 | c++; | |
58efb6c0 | 559 | |
252b5132 RH |
560 | while (*c >= '0' && *c <= '9') |
561 | bitend = (bitend * 10) + *c++ - '0'; | |
58efb6c0 | 562 | |
252b5132 RH |
563 | if (!bitend) |
564 | abort (); | |
58efb6c0 | 565 | |
252b5132 RH |
566 | switch (*c) |
567 | { | |
568 | case 'r': | |
569 | { | |
570 | long reg; | |
58efb6c0 | 571 | |
252b5132 RH |
572 | reg = given >> bitstart; |
573 | reg &= (2 << (bitend - bitstart)) - 1; | |
58efb6c0 | 574 | |
252b5132 RH |
575 | func (stream, "%s", arm_regnames[reg]); |
576 | } | |
577 | break; | |
578 | case 'd': | |
579 | { | |
580 | long reg; | |
58efb6c0 | 581 | |
252b5132 RH |
582 | reg = given >> bitstart; |
583 | reg &= (2 << (bitend - bitstart)) - 1; | |
58efb6c0 | 584 | |
252b5132 RH |
585 | func (stream, "%d", reg); |
586 | } | |
587 | break; | |
588 | case 'x': | |
589 | { | |
590 | long reg; | |
58efb6c0 | 591 | |
252b5132 RH |
592 | reg = given >> bitstart; |
593 | reg &= (2 << (bitend - bitstart)) - 1; | |
58efb6c0 | 594 | |
252b5132 | 595 | func (stream, "0x%08x", reg); |
5876e06d | 596 | |
58efb6c0 NC |
597 | /* Some SWI instructions have special |
598 | meanings. */ | |
5876e06d NC |
599 | if ((given & 0x0fffffff) == 0x0FF00000) |
600 | func (stream, "\t; IMB"); | |
601 | else if ((given & 0x0fffffff) == 0x0FF00001) | |
602 | func (stream, "\t; IMBRange"); | |
252b5132 RH |
603 | } |
604 | break; | |
cfbd315c DL |
605 | case 'X': |
606 | { | |
607 | long reg; | |
58efb6c0 | 608 | |
cfbd315c DL |
609 | reg = given >> bitstart; |
610 | reg &= (2 << (bitend - bitstart)) - 1; | |
58efb6c0 | 611 | |
cfbd315c DL |
612 | func (stream, "%01x", reg & 0xf); |
613 | } | |
614 | break; | |
252b5132 RH |
615 | case 'f': |
616 | { | |
617 | long reg; | |
58efb6c0 | 618 | |
252b5132 RH |
619 | reg = given >> bitstart; |
620 | reg &= (2 << (bitend - bitstart)) - 1; | |
58efb6c0 | 621 | |
252b5132 RH |
622 | if (reg > 7) |
623 | func (stream, "#%s", | |
624 | arm_fp_const[reg & 7]); | |
625 | else | |
626 | func (stream, "f%d", reg); | |
627 | } | |
628 | break; | |
629 | default: | |
630 | abort (); | |
631 | } | |
632 | break; | |
58efb6c0 | 633 | |
252b5132 RH |
634 | case '`': |
635 | c++; | |
636 | if ((given & (1 << bitstart)) == 0) | |
637 | func (stream, "%c", *c); | |
638 | break; | |
639 | case '\'': | |
640 | c++; | |
641 | if ((given & (1 << bitstart)) != 0) | |
642 | func (stream, "%c", *c); | |
643 | break; | |
644 | case '?': | |
645 | ++c; | |
646 | if ((given & (1 << bitstart)) != 0) | |
647 | func (stream, "%c", *c++); | |
648 | else | |
649 | func (stream, "%c", *++c); | |
650 | break; | |
651 | default: | |
652 | abort (); | |
653 | } | |
654 | break; | |
655 | ||
656 | default: | |
657 | abort (); | |
658 | } | |
659 | } | |
660 | } | |
661 | else | |
662 | func (stream, "%c", *c); | |
663 | } | |
664 | return 4; | |
665 | } | |
666 | } | |
667 | abort (); | |
668 | } | |
669 | ||
670 | /* Print one instruction from PC on INFO->STREAM. | |
671 | Return the size of the instruction. */ | |
252b5132 RH |
672 | static int |
673 | print_insn_thumb (pc, info, given) | |
5876e06d NC |
674 | bfd_vma pc; |
675 | struct disassemble_info * info; | |
676 | long given; | |
252b5132 | 677 | { |
5876e06d NC |
678 | struct thumb_opcode * insn; |
679 | void * stream = info->stream; | |
680 | fprintf_ftype func = info->fprintf_func; | |
252b5132 RH |
681 | |
682 | for (insn = thumb_opcodes; insn->assembler; insn++) | |
683 | { | |
684 | if ((given & insn->mask) == insn->value) | |
685 | { | |
5876e06d | 686 | char * c = insn->assembler; |
252b5132 | 687 | |
58efb6c0 NC |
688 | /* Special processing for Thumb 2 instruction BL sequence: */ |
689 | if (!*c) /* Check for empty (not NULL) assembler string. */ | |
252b5132 | 690 | { |
4f3c3dbb NC |
691 | long offset; |
692 | ||
252b5132 RH |
693 | info->bytes_per_chunk = 4; |
694 | info->bytes_per_line = 4; | |
4f3c3dbb NC |
695 | |
696 | offset = BDISP23 (given); | |
252b5132 | 697 | |
077b8428 | 698 | if ((given & 0x10000000) == 0) |
4f3c3dbb NC |
699 | { |
700 | func (stream, "blx\t"); | |
701 | ||
702 | /* The spec says that bit 1 of the branch's destination | |
703 | address comes from bit 1 of the instruction's | |
704 | address and not from the offset in the instruction. */ | |
705 | if (offset & 0x1) | |
706 | { | |
707 | /* func (stream, "*malformed!* "); */ | |
708 | offset &= ~ 0x1; | |
709 | } | |
710 | ||
711 | offset |= ((pc & 0x2) >> 1); | |
712 | } | |
077b8428 | 713 | else |
4f3c3dbb NC |
714 | func (stream, "bl\t"); |
715 | ||
716 | info->print_address_func (offset * 2 + pc + 4, info); | |
252b5132 RH |
717 | return 4; |
718 | } | |
719 | else | |
720 | { | |
721 | info->bytes_per_chunk = 2; | |
722 | info->bytes_per_line = 4; | |
723 | ||
724 | given &= 0xffff; | |
58efb6c0 | 725 | |
252b5132 RH |
726 | for (; *c; c++) |
727 | { | |
728 | if (*c == '%') | |
729 | { | |
730 | int domaskpc = 0; | |
731 | int domasklr = 0; | |
5876e06d | 732 | |
252b5132 RH |
733 | switch (*++c) |
734 | { | |
735 | case '%': | |
736 | func (stream, "%%"); | |
737 | break; | |
738 | ||
739 | case 'S': | |
740 | { | |
741 | long reg; | |
58efb6c0 | 742 | |
252b5132 RH |
743 | reg = (given >> 3) & 0x7; |
744 | if (given & (1 << 6)) | |
745 | reg += 8; | |
58efb6c0 | 746 | |
252b5132 RH |
747 | func (stream, "%s", arm_regnames[reg]); |
748 | } | |
749 | break; | |
750 | ||
751 | case 'D': | |
752 | { | |
753 | long reg; | |
5876e06d | 754 | |
252b5132 RH |
755 | reg = given & 0x7; |
756 | if (given & (1 << 7)) | |
757 | reg += 8; | |
58efb6c0 | 758 | |
252b5132 RH |
759 | func (stream, "%s", arm_regnames[reg]); |
760 | } | |
761 | break; | |
762 | ||
763 | case 'T': | |
764 | func (stream, "%s", | |
765 | arm_conditional [(given >> 8) & 0xf]); | |
766 | break; | |
767 | ||
768 | case 'N': | |
769 | if (given & (1 << 8)) | |
770 | domasklr = 1; | |
58efb6c0 | 771 | /* Fall through. */ |
252b5132 RH |
772 | case 'O': |
773 | if (*c == 'O' && (given & (1 << 8))) | |
774 | domaskpc = 1; | |
58efb6c0 | 775 | /* Fall through. */ |
252b5132 RH |
776 | case 'M': |
777 | { | |
778 | int started = 0; | |
779 | int reg; | |
5876e06d | 780 | |
252b5132 | 781 | func (stream, "{"); |
58efb6c0 | 782 | |
252b5132 RH |
783 | /* It would be nice if we could spot |
784 | ranges, and generate the rS-rE format: */ | |
785 | for (reg = 0; (reg < 8); reg++) | |
786 | if ((given & (1 << reg)) != 0) | |
787 | { | |
788 | if (started) | |
789 | func (stream, ", "); | |
790 | started = 1; | |
791 | func (stream, "%s", arm_regnames[reg]); | |
792 | } | |
793 | ||
794 | if (domasklr) | |
795 | { | |
796 | if (started) | |
797 | func (stream, ", "); | |
798 | started = 1; | |
a7f8487e | 799 | func (stream, arm_regnames[14] /* "lr" */); |
252b5132 RH |
800 | } |
801 | ||
802 | if (domaskpc) | |
803 | { | |
804 | if (started) | |
805 | func (stream, ", "); | |
a7f8487e | 806 | func (stream, arm_regnames[15] /* "pc" */); |
252b5132 RH |
807 | } |
808 | ||
809 | func (stream, "}"); | |
810 | } | |
811 | break; | |
812 | ||
813 | ||
814 | case '0': case '1': case '2': case '3': case '4': | |
815 | case '5': case '6': case '7': case '8': case '9': | |
816 | { | |
817 | int bitstart = *c++ - '0'; | |
818 | int bitend = 0; | |
5876e06d | 819 | |
252b5132 RH |
820 | while (*c >= '0' && *c <= '9') |
821 | bitstart = (bitstart * 10) + *c++ - '0'; | |
822 | ||
823 | switch (*c) | |
824 | { | |
825 | case '-': | |
826 | { | |
827 | long reg; | |
5876e06d | 828 | |
252b5132 RH |
829 | c++; |
830 | while (*c >= '0' && *c <= '9') | |
831 | bitend = (bitend * 10) + *c++ - '0'; | |
832 | if (!bitend) | |
833 | abort (); | |
834 | reg = given >> bitstart; | |
835 | reg &= (2 << (bitend - bitstart)) - 1; | |
836 | switch (*c) | |
837 | { | |
838 | case 'r': | |
839 | func (stream, "%s", arm_regnames[reg]); | |
840 | break; | |
841 | ||
842 | case 'd': | |
843 | func (stream, "%d", reg); | |
844 | break; | |
845 | ||
846 | case 'H': | |
847 | func (stream, "%d", reg << 1); | |
848 | break; | |
849 | ||
850 | case 'W': | |
851 | func (stream, "%d", reg << 2); | |
852 | break; | |
853 | ||
854 | case 'a': | |
855 | /* PC-relative address -- the bottom two | |
58efb6c0 NC |
856 | bits of the address are dropped |
857 | before the calculation. */ | |
252b5132 RH |
858 | info->print_address_func |
859 | (((pc + 4) & ~3) + (reg << 2), info); | |
860 | break; | |
861 | ||
862 | case 'x': | |
863 | func (stream, "0x%04x", reg); | |
864 | break; | |
865 | ||
866 | case 'I': | |
867 | reg = ((reg ^ (1 << bitend)) - (1 << bitend)); | |
868 | func (stream, "%d", reg); | |
869 | break; | |
870 | ||
871 | case 'B': | |
872 | reg = ((reg ^ (1 << bitend)) - (1 << bitend)); | |
873 | (*info->print_address_func) | |
874 | (reg * 2 + pc + 4, info); | |
875 | break; | |
876 | ||
877 | default: | |
5876e06d | 878 | abort (); |
252b5132 RH |
879 | } |
880 | } | |
881 | break; | |
882 | ||
883 | case '\'': | |
884 | c++; | |
885 | if ((given & (1 << bitstart)) != 0) | |
886 | func (stream, "%c", *c); | |
887 | break; | |
888 | ||
889 | case '?': | |
890 | ++c; | |
891 | if ((given & (1 << bitstart)) != 0) | |
892 | func (stream, "%c", *c++); | |
893 | else | |
894 | func (stream, "%c", *++c); | |
895 | break; | |
896 | ||
897 | default: | |
5876e06d | 898 | abort (); |
252b5132 RH |
899 | } |
900 | } | |
901 | break; | |
902 | ||
903 | default: | |
904 | abort (); | |
905 | } | |
906 | } | |
907 | else | |
908 | func (stream, "%c", *c); | |
909 | } | |
910 | } | |
911 | return 2; | |
912 | } | |
913 | } | |
914 | ||
58efb6c0 | 915 | /* No match. */ |
252b5132 RH |
916 | abort (); |
917 | } | |
918 | ||
58efb6c0 | 919 | /* Parse an individual disassembler option. */ |
a3d9c82d NC |
920 | void |
921 | parse_arm_disassembler_option (option) | |
01c7f630 | 922 | char * option; |
dd92f639 | 923 | { |
01c7f630 | 924 | if (option == NULL) |
dd92f639 NC |
925 | return; |
926 | ||
01c7f630 | 927 | if (strneq (option, "reg-names-", 10)) |
dd92f639 | 928 | { |
58efb6c0 NC |
929 | int i; |
930 | ||
01c7f630 | 931 | option += 10; |
58efb6c0 NC |
932 | |
933 | for (i = NUM_ARM_REGNAMES; i--;) | |
934 | if (streq (option, regnames[i].name)) | |
935 | { | |
936 | regname_selected = i; | |
937 | break; | |
938 | } | |
dd92f639 | 939 | |
58efb6c0 NC |
940 | if (i < 0) |
941 | fprintf (stderr, _("Unrecognised register name set: %s\n"), option); | |
dd92f639 | 942 | } |
01c7f630 NC |
943 | else if (streq (option, "force-thumb")) |
944 | force_thumb = 1; | |
945 | else if (streq (option, "no-force-thumb")) | |
946 | force_thumb = 0; | |
dd92f639 | 947 | else |
58efb6c0 | 948 | fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option); |
dd92f639 NC |
949 | |
950 | return; | |
951 | } | |
952 | ||
58efb6c0 | 953 | /* Parse the string of disassembler options, spliting it at whitespaces. */ |
01c7f630 NC |
954 | static void |
955 | parse_disassembler_options (options) | |
956 | char * options; | |
957 | { | |
958 | char * space; | |
959 | ||
960 | if (options == NULL) | |
961 | return; | |
962 | ||
963 | do | |
964 | { | |
965 | space = strchr (options, ' '); | |
966 | ||
967 | if (space) | |
968 | { | |
969 | * space = '\0'; | |
a3d9c82d | 970 | parse_arm_disassembler_option (options); |
01c7f630 NC |
971 | * space = ' '; |
972 | options = space + 1; | |
973 | } | |
974 | else | |
a3d9c82d | 975 | parse_arm_disassembler_option (options); |
01c7f630 NC |
976 | } |
977 | while (space); | |
978 | } | |
979 | ||
58efb6c0 NC |
980 | /* NOTE: There are no checks in these routines that |
981 | the relevant number of data bytes exist. */ | |
982 | static int | |
983 | print_insn (pc, info, little) | |
252b5132 | 984 | bfd_vma pc; |
5876e06d | 985 | struct disassemble_info * info; |
58efb6c0 | 986 | boolean little; |
252b5132 RH |
987 | { |
988 | unsigned char b[4]; | |
989 | long given; | |
990 | int status; | |
252b5132 | 991 | int is_thumb; |
58efb6c0 | 992 | |
dd92f639 NC |
993 | if (info->disassembler_options) |
994 | { | |
995 | parse_disassembler_options (info->disassembler_options); | |
996 | ||
58efb6c0 | 997 | /* To avoid repeated parsing of these options, we remove them here. */ |
dd92f639 NC |
998 | info->disassembler_options = NULL; |
999 | } | |
1000 | ||
01c7f630 NC |
1001 | is_thumb = force_thumb; |
1002 | ||
1003 | if (!is_thumb && info->symbols != NULL) | |
252b5132 | 1004 | { |
5876e06d NC |
1005 | if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour) |
1006 | { | |
2f0ca46a NC |
1007 | coff_symbol_type * cs; |
1008 | ||
5876e06d NC |
1009 | cs = coffsymbol (*info->symbols); |
1010 | is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT | |
1011 | || cs->native->u.syment.n_sclass == C_THUMBSTAT | |
1012 | || cs->native->u.syment.n_sclass == C_THUMBLABEL | |
1013 | || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC | |
1014 | || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC); | |
1015 | } | |
1016 | else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour) | |
1017 | { | |
2f0ca46a | 1018 | elf_symbol_type * es; |
58efb6c0 | 1019 | unsigned int type; |
2f0ca46a | 1020 | |
5876e06d | 1021 | es = *(elf_symbol_type **)(info->symbols); |
58efb6c0 NC |
1022 | type = ELF_ST_TYPE (es->internal_elf_sym.st_info); |
1023 | ||
1024 | is_thumb = (type == STT_ARM_TFUNC) || (type == STT_ARM_16BIT); | |
5876e06d NC |
1025 | } |
1026 | } | |
58efb6c0 | 1027 | |
252b5132 | 1028 | info->bytes_per_chunk = 4; |
58efb6c0 | 1029 | info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; |
252b5132 | 1030 | |
58efb6c0 | 1031 | if (little) |
252b5132 | 1032 | { |
58efb6c0 NC |
1033 | status = info->read_memory_func (pc, (bfd_byte *) &b[0], 4, info); |
1034 | if (status != 0 && is_thumb) | |
1035 | { | |
1036 | info->bytes_per_chunk = 2; | |
1037 | ||
1038 | status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); | |
1039 | b[3] = b[2] = 0; | |
1040 | } | |
1041 | ||
1042 | if (status != 0) | |
1043 | { | |
1044 | info->memory_error_func (status, pc, info); | |
1045 | return -1; | |
1046 | } | |
1047 | ||
1048 | given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24); | |
252b5132 | 1049 | } |
58efb6c0 | 1050 | else |
252b5132 | 1051 | { |
58efb6c0 NC |
1052 | status = info->read_memory_func |
1053 | (pc & ~ 0x3, (bfd_byte *) &b[0], 4, info); | |
1054 | if (status != 0) | |
252b5132 | 1055 | { |
58efb6c0 NC |
1056 | info->memory_error_func (status, pc, info); |
1057 | return -1; | |
1058 | } | |
1059 | ||
1060 | if (is_thumb) | |
1061 | { | |
1062 | if (pc & 0x2) | |
252b5132 | 1063 | { |
58efb6c0 NC |
1064 | given = (b[2] << 8) | b[3]; |
1065 | ||
1066 | status = info->read_memory_func | |
1067 | ((pc + 4) & ~ 0x3, (bfd_byte *) b, 4, info); | |
1068 | if (status != 0) | |
1069 | { | |
1070 | info->memory_error_func (status, pc + 4, info); | |
1071 | return -1; | |
1072 | } | |
1073 | ||
1074 | given |= (b[0] << 24) | (b[1] << 16); | |
252b5132 | 1075 | } |
58efb6c0 NC |
1076 | else |
1077 | given = (b[0] << 8) | b[1] | (b[2] << 24) | (b[3] << 16); | |
252b5132 RH |
1078 | } |
1079 | else | |
58efb6c0 | 1080 | given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]); |
252b5132 | 1081 | } |
58efb6c0 | 1082 | |
6a56ec7e NC |
1083 | if (info->flags & INSN_HAS_RELOC) |
1084 | /* If the instruction has a reloc associated with it, then | |
1085 | the offset field in the instruction will actually be the | |
1086 | addend for the reloc. (We are using REL type relocs). | |
1087 | In such cases, we can ignore the pc when computing | |
1088 | addresses, since the addend is not currently pc-relative. */ | |
1089 | pc = 0; | |
1090 | ||
252b5132 | 1091 | if (is_thumb) |
5876e06d | 1092 | status = print_insn_thumb (pc, info, given); |
252b5132 | 1093 | else |
5876e06d | 1094 | status = print_insn_arm (pc, info, given); |
252b5132 RH |
1095 | |
1096 | return status; | |
1097 | } | |
1098 | ||
1099 | int | |
58efb6c0 | 1100 | print_insn_big_arm (pc, info) |
252b5132 RH |
1101 | bfd_vma pc; |
1102 | struct disassemble_info * info; | |
1103 | { | |
58efb6c0 NC |
1104 | return print_insn (pc, info, false); |
1105 | } | |
01c7f630 | 1106 | |
58efb6c0 NC |
1107 | int |
1108 | print_insn_little_arm (pc, info) | |
1109 | bfd_vma pc; | |
1110 | struct disassemble_info * info; | |
1111 | { | |
1112 | return print_insn (pc, info, true); | |
1113 | } | |
252b5132 | 1114 | |
58efb6c0 NC |
1115 | void |
1116 | print_arm_disassembler_options (FILE * stream) | |
1117 | { | |
1118 | int i; | |
252b5132 | 1119 | |
58efb6c0 NC |
1120 | fprintf (stream, _("\n\ |
1121 | The following ARM specific disassembler options are supported for use with\n\ | |
1122 | the -M switch:\n")); | |
01c7f630 | 1123 | |
58efb6c0 NC |
1124 | for (i = NUM_ARM_REGNAMES; i--;) |
1125 | fprintf (stream, " reg-names-%s %*c%s\n", | |
1126 | regnames[i].name, | |
d5b2f4d6 | 1127 | (int)(14 - strlen (regnames[i].name)), ' ', |
58efb6c0 NC |
1128 | regnames[i].description); |
1129 | ||
1130 | fprintf (stream, " force-thumb Assume all insns are Thumb insns\n"); | |
1131 | fprintf (stream, " no-force-thumb Examine preceeding label to determine an insn's type\n\n"); | |
252b5132 | 1132 | } |