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Add some missing xcoff support
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
CommitLineData
252b5132 1/* Instruction printing code for the ARM
2571583a 2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
2fbad815 24
6394c606 25#include "disassemble.h"
2fbad815 26#include "opcode/arm.h"
252b5132 27#include "opintl.h"
31e0f3cd 28#include "safe-ctype.h"
65b48a81 29#include "libiberty.h"
0dbde4cf 30#include "floatformat.h"
252b5132 31
baf0cc5e 32/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 33#include "coff/internal.h"
34#include "libcoff.h"
252b5132
RH		 35#include "elf-bfd.h"
36#include "elf/internal.h"
37#include "elf/arm.h"
e49d43ff 38#include "mach-o.h"
252b5132 39
6b5d3a4d 40/* FIXME: Belongs in global header. */
01c7f630 41#ifndef strneq
58efb6c0
NC		 42#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
43#endif
44
1fbaefec
PB		 45/* Cached mapping symbol state. */
46enum map_type
47{
48 MAP_ARM,
49 MAP_THUMB,
50 MAP_DATA
51};
52
b0e28b39
DJ		 53struct arm_private_data
54{
55 /* The features to use when disassembling optional instructions. */
56 arm_feature_set features;
57
58 /* Whether any mapping symbols are present in the provided symbol
59 table. -1 if we do not know yet, otherwise 0 or 1. */
60 int has_mapping_symbols;
1fbaefec
PB		 61
62 /* Track the last type (although this doesn't seem to be useful) */
63 enum map_type last_type;
64
65 /* Tracking symbol table information */
66 int last_mapping_sym;
67 bfd_vma last_mapping_addr;
b0e28b39
DJ		 68};
69
6b5d3a4d
ZW		 70struct opcode32
71{
823d2571
TG		 72 arm_feature_set arch; /* Architecture defining this insn. */
73 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 74 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 75 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 76};
77
78struct opcode16
79{
823d2571 80 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 81 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 82 const char *assembler; /* How to disassemble this insn. */
83};
b7693d02 84
8f06b2d8 85/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 86
2fbad815 87 %% %
4a5329c6 88
c22aaad1 89 %c print condition code (always bits 28-31 in ARM mode)
37b37b2d 90 %q print shifter argument
e2efe87d
MGD		 91 %u print condition code (unconditional in ARM mode,
92 UNPREDICTABLE if not AL in Thumb)
4a5329c6 93 %A print address for ldc/stc/ldf/stf instruction
16980d0b 94 %B print vstm/vldm register list
4a5329c6 95 %I print cirrus signed shift immediate: bits 0..3|4..6
4a5329c6
ZW		 96 %F print the COUNT field of a LFM/SFM instruction.
97 %P print floating point precision in arithmetic insn
98 %Q print floating point precision in ldf/stf insn
99 %R print floating point rounding mode
100
33399f07 101 %<bitfield>c print as a condition code (for vsel)
4a5329c6 102 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 103 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
104 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 105 %<bitfield>d print the bitfield in decimal
16980d0b 106 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 107 %<bitfield>x print the bitfield in hex
108 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 109 %<bitfield>f print a floating point constant if >7 else a
110 floating point register
4a5329c6
ZW		 111 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
112 %<bitfield>g print as an iWMMXt 64-bit register
113 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 114 %<bitfield>D print as a NEON D register
115 %<bitfield>Q print as a NEON Q register
c28eeff2 116 %<bitfield>V print as a NEON D or Q register
6f1c2142 117 %<bitfield>E print a quarter-float immediate value
4a5329c6 118
16980d0b 119 %y<code> print a single precision VFP reg.
2fbad815 120 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 121 %z<code> print a double precision VFP reg
2fbad815 122 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 123
16980d0b
JB		 124 %<bitfield>'c print specified char iff bitfield is all ones
125 %<bitfield>`c print specified char iff bitfield is all zeroes
126 %<bitfield>?ab... select from array of values in big endian order
43e65147 127
2fbad815 128 %L print as an iWMMXt N/M width field.
4a5329c6 129 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 130 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 131 versions.
132 %i print 5-bit immediate in bits 8,3..0
133 (print "32" when 0)
fe56b6ce 134 %r print register offset address for wldt/wstr instruction. */
2fbad815 135
21d799b5 136enum opcode_sentinel_enum
05413229
NC		 137{
138 SENTINEL_IWMMXT_START = 1,
139 SENTINEL_IWMMXT_END,
140 SENTINEL_GENERIC_START
141} opcode_sentinels;
142
aefd8a40 143#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
c1e26897 144#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 145
8f06b2d8 146/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 147
8f06b2d8 148static const struct opcode32 coprocessor_opcodes[] =
2fbad815 149{
2fbad815 150 /* XScale instructions. */
823d2571
TG		 151 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
152 0x0e200010, 0x0fff0ff0,
153 "mia%c\tacc0, %0-3r, %12-15r"},
154 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
155 0x0e280010, 0x0fff0ff0,
156 "miaph%c\tacc0, %0-3r, %12-15r"},
157 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
158 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
159 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
160 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
161 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
162 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 163
2fbad815 164 /* Intel Wireless MMX technology instructions. */
823d2571
TG		 165 {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
166 {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
167 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
168 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
169 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
170 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
171 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
172 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
173 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
174 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
175 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
176 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
177 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
178 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
179 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
180 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
181 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
182 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
183 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
184 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
185 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
186 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
187 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
188 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
189 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
190 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
191 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
192 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
193 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
194 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
195 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
196 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
197 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
198 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
199 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
200 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
201 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
202 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
203 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
204 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
205 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
206 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
207 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
208 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
209 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
210 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
211 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
212 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
213 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
214 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
215 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
216 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
217 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
218 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
219 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
220 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
221 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
222 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
223 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
224 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
225 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
226 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
227 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
228 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
229 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
230 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
231 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
232 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
233 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
234 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
235 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
236 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
237 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
238 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
239 0x0e800120, 0x0f800ff0,
240 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
241 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
242 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
243 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
244 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
245 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
246 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
247 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
248 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
249 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
250 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
251 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
252 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
253 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
254 0x0e8000a0, 0x0f800ff0,
255 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
256 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
257 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
258 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
259 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
260 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
261 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
262 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
263 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
264 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
265 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
266 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
267 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
268 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
269 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
270 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
271 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
272 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
273 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
274 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
275 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
276 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
277 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
278 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
279 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
280 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
281 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
282 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
283 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
284 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
285 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
286 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
287 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
288 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
289 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
290 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
291 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
292 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
293 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
294 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
295 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
296 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
297 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
298 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
299 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
300 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
301 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
302 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
303 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
304 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
305 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
306 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
307 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
308 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
309 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
310 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
311 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
312 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
313 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
314 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
315 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
316 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
317 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
318 {ARM_FEATURE_CORE_LOW (0),
319 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 320
fe56b6ce 321 /* Floating point coprocessor (FPA) instructions. */
823d2571
TG		 322 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
323 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
324 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
325 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
326 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
327 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
328 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
329 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
330 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
331 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
332 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
333 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
334 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
335 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
336 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
337 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
338 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
339 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
340 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
341 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
342 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
343 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
344 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
345 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
346 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
347 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
348 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
349 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
350 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
351 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
352 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
353 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
354 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
355 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
356 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
357 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
358 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
359 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
360 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
361 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
362 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
363 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
364 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
365 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
366 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
367 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
368 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
369 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
370 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
371 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
372 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
373 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
374 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
375 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
376 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
377 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
378 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
379 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
380 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
381 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
382 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
383 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
384 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
385 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
386 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
387 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
388 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
389 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
390 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
391 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
392 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
393 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
394 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
395 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
396 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
397 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
398 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
399 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
400 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
401 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
402 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
403 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
404 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
405 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
406 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
407 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 408
16a1fa25
TP		 409 /* ARMv8-M Mainline Security Extensions instructions. */
410 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
411 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
412 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
413 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
414
fe56b6ce 415 /* Register load/store. */
823d2571
TG		 416 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
417 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
418 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
419 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
420 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
421 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
422 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
423 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
424 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
425 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
426 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
427 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
428 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
429 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
430 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
431 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
432 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
433 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
434 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
435 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
436 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
437 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
438 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
439 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
440 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
441 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
442 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
443 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
444 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
445 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
446 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
447 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
448
449 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
450 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
451 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
452 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
453 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
454 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
455 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
456 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 457
fe56b6ce 458 /* Data transfer between ARM and NEON registers. */
823d2571
TG		 459 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
460 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
462 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
464 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
466 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
468 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
470 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
472 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
474 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
476 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
478 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
480 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
482 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
484 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
486 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 487 /* Half-precision conversion instructions. */
823d2571
TG		 488 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
489 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
490 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
491 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
492 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
493 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
494 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
495 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 496
fe56b6ce 497 /* Floating point coprocessor (VFP) instructions. */
823d2571
TG		 498 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
499 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
500 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
501 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
502 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
503 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
504 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
505 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
40c7d507
RR		 506 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
507 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
823d2571
TG		 508 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
509 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
510 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
511 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
512 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
513 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
514 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
515 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
516 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
517 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
518 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
519 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
40c7d507
RR		 520 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
521 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
823d2571
TG		 522 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
523 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
524 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
525 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
526 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
527 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
528 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
529 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
530 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
531 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
532 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
533 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
534 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
535 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
536 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
537 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
538 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
539 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
540 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
541 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
542 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
543 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
544 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
545 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
546 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
547 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
548 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
549 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
550 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
551 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
552 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
553 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
554 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
555 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
556 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
557 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
558 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
559 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
560 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
561 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
562 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
563 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
564 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
565 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
566 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
567 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
568 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
569 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
570 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
571 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
572 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
573 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
574 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
575 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
576 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
577 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
578 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
579 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
580 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
581 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
582 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
583 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
584 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
585 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
586 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
587 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
588 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
589 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
590 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6f1c2142 591 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
823d2571 592 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6f1c2142 593 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
823d2571
TG		 594 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
595 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
596 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
597 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
598 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
599 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
600 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
601 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
602 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
603 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
604 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
605 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
606 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
607 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
608 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
609 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
610 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
611 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
612 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
613 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
614 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
615 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
616 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
617 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
618 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
619 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
620 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
621 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
622 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
623 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
624 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
625 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
626 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
627 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
628 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
629 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
630 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
631 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
632 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
633 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
634 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
635 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 636
637 /* Cirrus coprocessor instructions. */
823d2571
TG		 638 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
639 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
640 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
641 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
642 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
643 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
644 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
645 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
646 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
647 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
648 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
649 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
650 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
651 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
652 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
653 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
654 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
655 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
656 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
657 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
658 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
659 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
660 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
661 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
662 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
663 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
664 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
665 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
666 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
667 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
668 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
669 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
670 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
671 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
672 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
673 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
674 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
675 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
676 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
677 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
678 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
679 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
680 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
681 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
682 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
683 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
684 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
685 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
686 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
687 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
688 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
689 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
690 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
691 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
692 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
693 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
694 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
695 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
696 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
697 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
698 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
699 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
700 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
701 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
702 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
703 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
704 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
705 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
706 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
707 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
708 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
709 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
710 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
711 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
712 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
713 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
714 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
715 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
716 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
717 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
718 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
719 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
720 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
721 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
722 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
723 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
724 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
725 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
726 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
727 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
728 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
729 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
730 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
731 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
732 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
733 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
734 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
735 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
736 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
737 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
738 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
739 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
740 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
741 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
742 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
743 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
744 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
745 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
746 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
747 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
748 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
749 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
750 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
751 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
752 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
753 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
754 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
755 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
756 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
757 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
758 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
759 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
760 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
761 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
762 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
763 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
764 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
765 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
766 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
767 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
768 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
769 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
770 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
771 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
772 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
773 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
774 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
775 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
776 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
777 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
778 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
779 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
780 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
781 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
782 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
783 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
784 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
785 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
786 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
787 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
788 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
789 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
790 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
791 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
792 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
793 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
794 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
795 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
796 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
797 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
798 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
799 0x0e000600, 0x0ff00f10,
800 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
801 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
802 0x0e100600, 0x0ff00f10,
803 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
804 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
805 0x0e200600, 0x0ff00f10,
806 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
807 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
808 0x0e300600, 0x0ff00f10,
809 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 810
62f3b8c8 811 /* VFP Fused multiply add instructions. */
823d2571
TG		 812 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
813 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
814 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
815 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
816 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
817 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
818 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
819 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
820 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
821 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
822 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
824 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
825 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
826 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
827 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 828
33399f07 829 /* FP v5. */
823d2571 830 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 831 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
823d2571 832 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 833 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
823d2571 834 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 835 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
823d2571 836 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 837 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
823d2571 838 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 839 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
823d2571 840 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 841 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
823d2571
TG		 842 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
843 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
844 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
845 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
846 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
847 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
848 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
849 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
850 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 851 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
823d2571 852 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 853 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 854
05413229 855 /* Generic coprocessor instructions. */
823d2571
TG		 856 {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
858 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
860 0x0c500000, 0x0ff00000,
861 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
863 0x0e000000, 0x0f000010,
864 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
866 0x0e10f010, 0x0f10f010,
867 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
869 0x0e100010, 0x0f100010,
870 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
872 0x0e000010, 0x0f100010,
873 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
875 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
877 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
2fbad815 878
05413229 879 /* V6 coprocessor instructions. */
823d2571
TG		 880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
881 0xfc500000, 0xfff00000,
882 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
884 0xfc400000, 0xfff00000,
885 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
8f06b2d8 886
c28eeff2
SN		 887 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
888 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
889 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
890 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
891 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
892 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
893 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
894 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
895 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
896 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
897 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
898 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
899 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
900 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 901 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
c28eeff2 902 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 903 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
c28eeff2 904 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 905 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
c28eeff2 906 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 907 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
c28eeff2 908
c604a79a
JW		 909 /* Dot Product instructions in the space of coprocessor 13. */
910 {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
911 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
912 {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
913 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
914
05413229 915 /* V5 coprocessor instructions. */
823d2571
TG		 916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
917 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
919 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
921 0xfe000000, 0xff000010,
922 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
924 0xfe000010, 0xff100010,
925 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
927 0xfe100010, 0xff100010,
928 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
929
b0c11777
RL		 930 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
931 cp_num: bit <11:8> == 0b1001.
932 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
933 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
934 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
935 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
936 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
937 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
938 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
939 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
940 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
941 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
942 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
943 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
944 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
945 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
946 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
947 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
948 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
949 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
950 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
951 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
952 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
953 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
954 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
955 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
956 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
957 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
958 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
959 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
960 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
961 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
962 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
963 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
964 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
965 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
966 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
967 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
968 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
969 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
970 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
971 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
972 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
973 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
974 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
975 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
976 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
977 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
978 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
979 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
980 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
981 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
982 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
983 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
984 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
985 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
986 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
987 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
988 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
989 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
990 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
991 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
992 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
993 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
994 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
995 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
996 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
997 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
998 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
999 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1000 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1001 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1002 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1003
49e8a725
SN		 1004 /* ARMv8.3 javascript conversion instruction. */
1005 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1006 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1007
823d2571 1008 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 1009};
1010
16980d0b
JB		 1011/* Neon opcode table: This does not encode the top byte -- that is
1012 checked by the print_insn_neon routine, as it depends on whether we are
1013 doing thumb32 or arm32 disassembly. */
1014
1015/* print_insn_neon recognizes the following format control codes:
1016
1017 %% %
1018
c22aaad1 1019 %c print condition code
e2efe87d
MGD		 1020 %u print condition code (unconditional in ARM mode,
1021 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 1022 %A print v{st,ld}[1234] operands
1023 %B print v{st,ld}[1234] any one operands
1024 %C print v{st,ld}[1234] single->all operands
1025 %D print scalar
1026 %E print vmov, vmvn, vorr, vbic encoded constant
1027 %F print vtbl,vtbx register list
1028
1029 %<bitfield>r print as an ARM register
1030 %<bitfield>d print the bitfield in decimal
1031 %<bitfield>e print the 2^N - bitfield in decimal
1032 %<bitfield>D print as a NEON D register
1033 %<bitfield>Q print as a NEON Q register
1034 %<bitfield>R print as a NEON D or Q register
1035 %<bitfield>Sn print byte scaled width limited by n
1036 %<bitfield>Tn print short scaled width limited by n
1037 %<bitfield>Un print long scaled width limited by n
43e65147 1038
16980d0b
JB		 1039 %<bitfield>'c print specified char iff bitfield is all ones
1040 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1041 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1042
1043static const struct opcode32 neon_opcodes[] =
1044{
fe56b6ce 1045 /* Extract. */
823d2571
TG		 1046 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1047 0xf2b00840, 0xffb00850,
1048 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1049 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1050 0xf2b00000, 0xffb00810,
1051 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 1052
fe56b6ce 1053 /* Move data element to all lanes. */
823d2571
TG		 1054 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1055 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1056 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1057 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1058 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1059 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 1060
fe56b6ce 1061 /* Table lookup. */
823d2571
TG		 1062 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1063 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1064 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1065 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1066
8e79c3df 1067 /* Half-precision conversions. */
823d2571
TG		 1068 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1069 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1070 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1071 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1072
1073 /* NEON fused multiply add instructions. */
823d2571 1074 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1075 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1076 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1077 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1078 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1079 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1080 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1081 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1082
fe56b6ce 1083 /* Two registers, miscellaneous. */
823d2571
TG		 1084 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1085 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1086 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1087 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1088 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1089 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1090 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1091 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1092 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1093 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1094 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1095 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1096 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1097 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1098 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1099 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1100 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1101 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1102 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1103 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1104 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1105 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1106 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1107 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1108 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1109 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1110 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1111 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1112 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1113 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1114 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1115 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1116 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1117 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1118 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1119 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1120 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1121 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1122 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1123 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1124 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1125 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1126 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1127 0xf3b20300, 0xffb30fd0,
1128 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1129 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1130 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1131 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1132 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1133 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1134 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1135 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1136 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1137 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1138 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1139 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1140 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1141 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1142 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1143 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1144 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1145 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1146 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1147 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1148 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1149 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1150 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1151 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1152 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1153 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1154 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1155 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1156 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1157 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1158 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1159 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1160 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1161 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1162 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1163 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1164 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1165 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1166 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1167 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1168 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1169 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1170 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1171 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1172 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1173 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1174 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1175 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301 1176 0xf3bb0600, 0xffbf0e10,
823d2571 1177 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1178 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1179 0xf3b70600, 0xffbf0e10,
1180 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
16980d0b 1181
fe56b6ce 1182 /* Three registers of the same length. */
823d2571
TG		 1183 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1184 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1185 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1186 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1187 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1188 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1189 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1190 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1191 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1192 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1193 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1194 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1195 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1196 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1197 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1198 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1199 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1200 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1201 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1202 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1203 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1204 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1205 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1206 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1207 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1208 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1209 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1210 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1211 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1212 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1213 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1214 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1215 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1216 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1217 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1218 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1219 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1220 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1221 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1222 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1223 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1224 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1225 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1226 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1227 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1228 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1229 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1230 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1231 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1232 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1233 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1234 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1235 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1236 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1237 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1238 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1239 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1240 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1241 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1242 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1243 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1244 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1245 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1246 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1247 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1248 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1249 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1250 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1251 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1252 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1253 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1254 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1255 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1256 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1257 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1258 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1259 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1260 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1261 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1262 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1263 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1264 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1265 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1266 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1267 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1268 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1269 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1270 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1271 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1272 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1273 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1274 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1275 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1276 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1277 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1278 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1279 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1280 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1281 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1282 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1283 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1284 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1285 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1286 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1287 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1288 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1289 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1290 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1291 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1292 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1293 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1294 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1295 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1296 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1297 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1298 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1299 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1300 0xf2000b00, 0xff800f10,
1301 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1302 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1303 0xf2000b10, 0xff800f10,
1304 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1305 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1306 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1307 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1308 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1309 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1310 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1311 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1312 0xf3000b00, 0xff800f10,
1313 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1314 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1315 0xf2000000, 0xfe800f10,
1316 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1317 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1318 0xf2000010, 0xfe800f10,
1319 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1320 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1321 0xf2000100, 0xfe800f10,
1322 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1323 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1324 0xf2000200, 0xfe800f10,
1325 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1326 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1327 0xf2000210, 0xfe800f10,
1328 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1329 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1330 0xf2000300, 0xfe800f10,
1331 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1332 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1333 0xf2000310, 0xfe800f10,
1334 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1335 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1336 0xf2000400, 0xfe800f10,
1337 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1338 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1339 0xf2000410, 0xfe800f10,
1340 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1341 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1342 0xf2000500, 0xfe800f10,
1343 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1344 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1345 0xf2000510, 0xfe800f10,
1346 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1347 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1348 0xf2000600, 0xfe800f10,
1349 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1350 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1351 0xf2000610, 0xfe800f10,
1352 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1353 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1354 0xf2000700, 0xfe800f10,
1355 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1356 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1357 0xf2000710, 0xfe800f10,
1358 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1359 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1360 0xf2000910, 0xfe800f10,
1361 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1362 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1363 0xf2000a00, 0xfe800f10,
1364 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1365 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1366 0xf2000a10, 0xfe800f10,
1367 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1368 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1369 0xf3000b10, 0xff800f10,
1370 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1371 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1372 0xf3000c10, 0xff800f10,
1373 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1374
fe56b6ce 1375 /* One register and an immediate value. */
823d2571
TG		 1376 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1377 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1378 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1379 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1380 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1381 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1382 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1383 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1384 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1385 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1386 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1387 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1388 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1389 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1390 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1391 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1392 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1393 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1394 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1395 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1396 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1397 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1398 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1399 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1400 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1401 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1402
fe56b6ce 1403 /* Two registers and a shift amount. */
823d2571
TG		 1404 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1405 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1406 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1407 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1408 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1409 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1410 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1411 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1412 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1413 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1414 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1415 0xf2880950, 0xfeb80fd0,
1416 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1417 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1418 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1419 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1420 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1421 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1422 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1423 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1424 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1425 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1426 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1427 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1428 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1429 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1430 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1431 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1432 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1433 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1434 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1435 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1436 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1437 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1438 0xf2900950, 0xfeb00fd0,
1439 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1440 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1441 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1442 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1443 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1444 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1445 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1446 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1447 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1448 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1449 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1450 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1451 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1452 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1453 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1454 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1455 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1456 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1457 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1458 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1459 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1460 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1461 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1462 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1463 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1465 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1466 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1467 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1468 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1469 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1470 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1471 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1473 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1474 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1475 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1477 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1478 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1479 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1481 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1482 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1483 0xf2a00950, 0xfea00fd0,
1484 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1486 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1487 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1488 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1489 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1490 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1492 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1494 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1495 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1496 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1498 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1499 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1500 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1502 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1503 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1504 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1511 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1512 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1515 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1517 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1518 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1519 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1520 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1521 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1522 0xf2a00e10, 0xfea00e90,
1523 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
cc933301
JW		 1524 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1525 0xf2a00c10, 0xfea00e90,
1526 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 1527
fe56b6ce 1528 /* Three registers of different lengths. */
823d2571
TG		 1529 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1530 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1531 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1532 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1533 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1534 0xf2800400, 0xff800f50,
1535 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1536 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1537 0xf2800600, 0xff800f50,
1538 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1539 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1540 0xf2800900, 0xff800f50,
1541 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1542 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1543 0xf2800b00, 0xff800f50,
1544 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1545 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1546 0xf2800d00, 0xff800f50,
1547 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1548 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1549 0xf3800400, 0xff800f50,
1550 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1551 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1552 0xf3800600, 0xff800f50,
1553 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1554 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1555 0xf2800000, 0xfe800f50,
1556 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1557 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1558 0xf2800100, 0xfe800f50,
1559 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1560 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1561 0xf2800200, 0xfe800f50,
1562 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1564 0xf2800300, 0xfe800f50,
1565 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1566 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1567 0xf2800500, 0xfe800f50,
1568 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1569 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1570 0xf2800700, 0xfe800f50,
1571 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1572 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1573 0xf2800800, 0xfe800f50,
1574 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1576 0xf2800a00, 0xfe800f50,
1577 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1578 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1579 0xf2800c00, 0xfe800f50,
1580 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 1581
fe56b6ce 1582 /* Two registers and a scalar. */
823d2571
TG		 1583 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1584 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1585 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1586 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1587 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1588 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1589 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1590 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1591 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1592 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1594 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1595 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1596 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1597 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1598 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1599 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1600 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1601 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1602 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1603 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1604 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1605 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1606 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1607 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1608 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1609 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1610 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1611 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1612 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1613 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1614 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1615 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1616 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1618 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1619 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1620 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1621 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1622 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1623 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1624 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1625 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1626 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1627 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1628 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1630 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1631 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1632 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1633 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1634 0xf2800240, 0xfe800f50,
1635 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1636 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1637 0xf2800640, 0xfe800f50,
1638 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1639 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1640 0xf2800a40, 0xfe800f50,
1641 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 1642 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1643 0xf2800e40, 0xff800f50,
1644 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1646 0xf2800f40, 0xff800f50,
1647 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1648 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1649 0xf3800e40, 0xff800f50,
1650 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1651 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1652 0xf3800f40, 0xff800f50,
1653 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1654 },
16980d0b 1655
fe56b6ce 1656 /* Element and structure load/store. */
823d2571
TG		 1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1658 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1659 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1660 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1661 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1662 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1663 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1664 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1665 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1666 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1667 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1668 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1669 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1670 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1671 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1672 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1673 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1674 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1675 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1676 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1677 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1678 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1679 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1680 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1681 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1682 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1683 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1684 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1685 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1686 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1687 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1688 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1689 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1690 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1691 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1692 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1693 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1694 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1695
1696 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 1697};
1698
8f06b2d8
PB		 1699/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
1700 ordered: they must be searched linearly from the top to obtain a correct
1701 match. */
1702
1703/* print_insn_arm recognizes the following format control codes:
1704
1705 %% %
1706
1707 %a print address for ldr/str instruction
1708 %s print address for ldr/str halfword/signextend instruction
c1e26897 1709 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 1710 %b print branch destination
1711 %c print condition code (always bits 28-31)
1712 %m print register mask for ldm/stm instruction
1713 %o print operand2 (immediate or register + shift)
1714 %p print 'p' iff bits 12-15 are 15
1715 %t print 't' iff bit 21 set and bit 24 clear
1716 %B print arm BLX(1) destination
1717 %C print the PSR sub type.
62b3e311
PB		 1718 %U print barrier type.
1719 %P print address for pli instruction.
8f06b2d8
PB		 1720
1721 %<bitfield>r print as an ARM register
9eb6c0f1 1722 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 1723 %<bitfield>R as %r but r15 is UNPREDICTABLE
1724 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1725 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 1726 %<bitfield>d print the bitfield in decimal
43e65147 1727 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 1728 %<bitfield>x print the bitfield in hex
1729 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 1730
16980d0b
JB		 1731 %<bitfield>'c print specified char iff bitfield is all ones
1732 %<bitfield>`c print specified char iff bitfield is all zeroes
1733 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 1734
8f06b2d8
PB		 1735 %e print arm SMI operand (bits 0..7,8..19).
1736 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 1737 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
1738 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 1739
8f06b2d8
PB		 1740static const struct opcode32 arm_opcodes[] =
1741{
1742 /* ARM instructions. */
823d2571
TG		 1743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1744 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1746 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1747
1748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
1749 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1751 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1753 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
1755 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1757 0x00800090, 0x0fa000f0,
1758 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1760 0x00a00090, 0x0fa000f0,
1761 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 1762
105bde57 1763 /* V8.2 RAS extension instructions. */
4d1464f2 1764 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 1765 0xe320f010, 0xffffffff, "esb"},
1766
53c4b28b 1767 /* V8 instructions. */
823d2571
TG		 1768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1769 0x0320f005, 0x0fffffff, "sevl"},
1770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1771 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
4ed7ed8d 1772 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 1773 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1774 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 1775 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1777 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1779 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 1780 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1781 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1782 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1783 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1784 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1785 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1786 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1787 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1788 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1789 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1790 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1791 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1792 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1793 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1794 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1795 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1796 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1797 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1798 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 1799 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 1800 /* CRC32 instructions. */
823d2571
TG		 1801 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1802 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
1803 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1804 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
1805 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1806 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
1807 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1808 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
1809 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1810 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
1811 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1812 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 1813
ddfded2f
MW		 1814 /* Privileged Access Never extension instructions. */
1815 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
1816 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
1817
90ec0d68 1818 /* Virtualization Extension instructions. */
823d2571
TG		 1819 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
1820 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 1821
eea54501 1822 /* Integer Divide Extension instructions. */
823d2571
TG		 1823 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1824 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1825 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1826 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 1827
60e5ef9f 1828 /* MP Extension instructions. */
823d2571 1829 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 1830
62b3e311 1831 /* V7 instructions. */
823d2571
TG		 1832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
1833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
1835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
1836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a
AV		 1839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
1840 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
62b3e311 1841
c19d1205 1842 /* ARM V6T2 instructions. */
823d2571
TG		 1843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1844 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1846 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1848 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1850 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
1851
1852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1853 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
1854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1855 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1856
ff8646ee 1857 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 1858 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 1859 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 1860 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1862 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1864 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 1865
f4c65163 1866 /* ARM Security extension instructions. */
823d2571
TG		 1867 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
1868 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 1869
8f06b2d8 1870 /* ARM V6K instructions. */
823d2571
TG		 1871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1872 0xf57ff01f, 0xffffffff, "clrex"},
1873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1874 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1876 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1878 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1880 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1882 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1884 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 1885
8f06b2d8 1886 /* ARM V6K NOP hints. */
823d2571
TG		 1887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1888 0x0320f001, 0x0fffffff, "yield%c"},
1889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1890 0x0320f002, 0x0fffffff, "wfe%c"},
1891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1892 0x0320f003, 0x0fffffff, "wfi%c"},
1893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1894 0x0320f004, 0x0fffffff, "sev%c"},
1895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1896 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 1897
fe56b6ce 1898 /* ARM V6 instructions. */
823d2571
TG		 1899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1900 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
1901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1902 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
1903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1904 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
1905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1906 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
1907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1908 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
1909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1910 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
1911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1912 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
1913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1914 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
1915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1916 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
1917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1918 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
1919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1920 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
1921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1922 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
1923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1924 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
1925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1926 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
1927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1928 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
1929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1930 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
1931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1932 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
1933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1934 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
1935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1936 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
1937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1938 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
1939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1940 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
1941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1942 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
1943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1944 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
1945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1946 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
1947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1948 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
1949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1950 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
1951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1952 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
1953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1954 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
1955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1956 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
1957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1958 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
1959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1960 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
1961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1962 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
1963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1964 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
1965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1966 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
1967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1968 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
1969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1970 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
1971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1972 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
1973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1974 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
1975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1976 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
1977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1978 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
1979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1980 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
1981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1982 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
1983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1984 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
1985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1986 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
1987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1988 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
1989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1990 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
1991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1992 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
1993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1994 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
1995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1996 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
1997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1998 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
1999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2000 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
2001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2002 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
2003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2004 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
2005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2006 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
2007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2008 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
2009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2010 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
2011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2012 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
2013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2014 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
2015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2016 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
2017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2018 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
2019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2020 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
2021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2022 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
2023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2024 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
2025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2026 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
2027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2028 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
2029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2030 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
2031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2032 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
2033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2034 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
2035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2036 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
2037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2038 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
2039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2040 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
2041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2042 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
2043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2044 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
2045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2046 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
2047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2048 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
2049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2050 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2052 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2054 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2056 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
2057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2058 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2060 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2062 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2064 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
2065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2066 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2068 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2070 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2072 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
2073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2074 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2076 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2078 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2080 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
2081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2082 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2084 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2086 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
2087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2088 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
2089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2090 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2092 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2094 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2096 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
2097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2098 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
2099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2100 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
2101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2102 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
2103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2104 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2106 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2108 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2110 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2112 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
2113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2114 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2116 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2118 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
2119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2120 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
2121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2122 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
2123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2124 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
2125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2126 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
2127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2128 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
2129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2130 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
2131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2132 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
2133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2134 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2136 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
2137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2138 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
2139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2140 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
2141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2142 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 2143
8f06b2d8 2144 /* V5J instruction. */
823d2571
TG		 2145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
2146 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 2147
8f06b2d8 2148 /* V5 Instructions. */
823d2571
TG		 2149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2150 0xe1200070, 0xfff000f0,
2151 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
2152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2153 0xfa000000, 0xfe000000, "blx\t%B"},
2154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2155 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
2156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2157 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
2158
2159 /* V5E "El Segundo" Instructions. */
2160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2161 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
2162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2163 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
2164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2165 0xf450f000, 0xfc70f000, "pld\t%a"},
2166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2167 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2169 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2171 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2173 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
2174
2175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2176 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2178 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
2179
2180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2181 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2183 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2185 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2187 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2188
2189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2190 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2192 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2194 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2196 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2197
2198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2199 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2201 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2202
2203 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2204 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
2205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2206 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2208 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
2209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2210 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 2211
8f06b2d8 2212 /* ARM Instructions. */
823d2571
TG		 2213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2214 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2215
2216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2217 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2219 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2221 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2223 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2225 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2227 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2228
2229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2230 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2232 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2234 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2236 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2237
2238 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2239 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2240 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2241 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2243 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2245 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2246
2247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2248 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2250 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2252 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2253
2254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2255 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2257 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2259 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2260
2261 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2262 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2263 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2264 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2266 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2267
2268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2269 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2271 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2273 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2274
2275 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2276 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2277 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2278 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2279 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2280 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2281
2282 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2283 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2285 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2287 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2288
2289 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2290 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2292 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2294 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2295
2296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2297 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2299 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2301 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2302
2303 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2304 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2305 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2306 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2307 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2308 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2309
2310 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2311 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2313 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2315 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2316
2317 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2318 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 2319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2320 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 2321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2322 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
823d2571
TG		 2323
2324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2325 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2327 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2329 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2330
2331 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2332 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2334 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2336 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2337
2338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2339 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2341 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2343 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2344
2345 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2346 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2348 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2350 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2352 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2354 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2356 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2358 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2359
2360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2361 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2363 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2365 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2366
2367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2368 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2370 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2372 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2373
2374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2375 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2377 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2378
2379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2380 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2381
2382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2383 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2385 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2386
2387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2388 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2390 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2392 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2394 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2395 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2396 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2397 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2398 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2399 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2400 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2401 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2402 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2403 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2404 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2406 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2408 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2410 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2411 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2412 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2413 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2414 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2415 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2416 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2418 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2419 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2420 0x092d0000, 0x0fff0000, "push%c\t%m"},
2421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2422 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2424 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2425
2426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2427 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2429 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2431 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2433 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2434 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2435 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2437 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2439 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2440 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2441 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2443 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2445 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2447 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2448 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2449 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2451 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2453 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2455 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2457 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2459 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2461 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2463 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2464
2465 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2466 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2467 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2468 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 2469
2470 /* The rest. */
4ab90a7a
AV		 2471 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2472 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 2473 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2474 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2475 {ARM_FEATURE_CORE_LOW (0),
2476 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 2477};
2478
2479/* print_insn_thumb16 recognizes the following format control codes:
2480
2481 %S print Thumb register (bits 3..5 as high number if bit 6 set)
2482 %D print Thumb register (bits 0..2 as high number if bit 7 set)
2483 %<bitfield>I print bitfield as a signed decimal
2484 (top bit of range being the sign bit)
2485 %N print Thumb register mask (with LR)
2486 %O print Thumb register mask (with PC)
2487 %M print Thumb register mask
2488 %b print CZB's 6-bit unsigned branch destination
2489 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 2490 %c print the condition code
2491 %C print the condition code, or "s" if not conditional
2492 %x print warning if conditional an not at end of IT block"
2493 %X print "\t; unpredictable <IT:code>" if conditional
2494 %I print IT instruction suffix and operands
4547cb56 2495 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 2496 %<bitfield>r print bitfield as an ARM register
2497 %<bitfield>d print bitfield as a decimal
2498 %<bitfield>H print (bitfield * 2) as a decimal
2499 %<bitfield>W print (bitfield * 4) as a decimal
2500 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
2501 %<bitfield>B print Thumb branch destination (signed displacement)
2502 %<bitfield>c print bitfield as a condition code
2503 %<bitnum>'c print specified char iff bit is one
2504 %<bitnum>?ab print a if bit is one else print b. */
2505
2506static const struct opcode16 thumb_opcodes[] =
2507{
2508 /* Thumb instructions. */
2509
16a1fa25
TP		 2510 /* ARMv8-M Security Extensions instructions. */
2511 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
2512 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff07, "bxns\t%3-6r"},
2513
53c4b28b 2514 /* ARM V8 instructions. */
823d2571
TG		 2515 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
2516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
ddfded2f 2517 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
53c4b28b 2518
8f06b2d8 2519 /* ARM V6K no-argument instructions. */
823d2571
TG		 2520 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2521 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2522 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2523 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2524 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2525 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 2526
2527 /* ARM V6T2 instructions. */
ff8646ee
TP		 2528 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2529 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2530 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2531 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 2532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 2533
2534 /* ARM V6. */
823d2571
TG		 2535 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2537 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2539 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2541 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2545 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 2546
2547 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 2548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2549 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 2550 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 2551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2552 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 2553 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 2554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2555 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 2556 /* Format 4. */
823d2571
TG		 2557 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2559 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2563 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 2573 /* format 13 */
823d2571
TG		 2574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 2576 /* format 5 */
823d2571
TG		 2577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
2578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
2579 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 2581 /* format 14 */
823d2571
TG		 2582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
2583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 2584 /* format 2 */
823d2571
TG		 2585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2586 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2588 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2590 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2591 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2592 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 2593 /* format 8 */
823d2571
TG		 2594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2595 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2597 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2599 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2600 /* format 7 */
823d2571
TG		 2601 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2602 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2603 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2604 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2605 /* format 1 */
823d2571
TG		 2606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2608 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 2611 /* format 3 */
823d2571
TG		 2612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2613 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2615 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 2616 /* format 6 */
823d2571
TG		 2617 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2619 0x4800, 0xF800,
2620 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 2621 /* format 9 */
823d2571
TG		 2622 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2623 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2625 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2627 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2629 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 2630 /* format 10 */
823d2571
TG		 2631 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2632 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2634 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 2635 /* format 11 */
823d2571
TG		 2636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2637 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2639 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 2640 /* format 12 */
823d2571
TG		 2641 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2642 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2644 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 2645 /* format 15 */
823d2571
TG		 2646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 2648 /* format 17 */
823d2571 2649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 2650 /* format 16 */
823d2571
TG		 2651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2652 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
2653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 2654 /* format 18 */
823d2571 2655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 2656
2657 /* The E800 .. FFFF range is unconditionally redirected to the
2658 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2659 are processed via that table. Thus, we can never encounter a
2660 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 2661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
2662 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 2663};
2664
2665/* Thumb32 opcodes use the same table structure as the ARM opcodes.
2666 We adopt the convention that hw1 is the high 16 bits of .value and
2667 .mask, hw2 the low 16 bits.
2668
2669 print_insn_thumb32 recognizes the following format control codes:
2670
2671 %% %
2672
2673 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2674 %M print a modified 12-bit immediate (same location)
2675 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2676 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 2677 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 2678 %S print a possibly-shifted Rm
2679
32a94698 2680 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 2681 %a print the address of a plain load/store
2682 %w print the width and signedness of a core load/store
2683 %m print register mask for ldm/stm
2684
2685 %E print the lsb and width fields of a bfc/bfi instruction
2686 %F print the lsb and width fields of a sbfx/ubfx instruction
2687 %b print a conditional branch offset
2688 %B print an unconditional branch offset
2689 %s print the shift field of an SSAT instruction
2690 %R print the rotation field of an SXT instruction
62b3e311
PB		 2691 %U print barrier type.
2692 %P print address for pli instruction.
c22aaad1
PB		 2693 %c print the condition code
2694 %x print warning if conditional an not at end of IT block"
2695 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 2696
2697 %<bitfield>d print bitfield in decimal
f0fba320 2698 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 2699 %<bitfield>W print bitfield*4 in decimal
2700 %<bitfield>r print bitfield as an ARM register
dd5181d5
KT		 2701 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
2702 %<bitfield>S as %<>R but r13 is UNPREDICTABLE
8f06b2d8
PB		 2703 %<bitfield>c print bitfield as a condition code
2704
16980d0b
JB		 2705 %<bitfield>'c print specified char iff bitfield is all ones
2706 %<bitfield>`c print specified char iff bitfield is all zeroes
2707 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 2708
2709 With one exception at the bottom (done because BL and BLX(1) need
2710 to come dead last), this table was machine-sorted first in
2711 decreasing order of number of bits set in the mask, then in
2712 increasing numeric order of mask, then in increasing numeric order
2713 of opcode. This order is not the clearest for a human reader, but
2714 is guaranteed never to catch a special-case bit pattern with a more
2715 general mask, which is important, because this instruction encoding
2716 makes heavy use of special-case bit patterns. */
2717static const struct opcode32 thumb32_opcodes[] =
2718{
16a1fa25
TP		 2719 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
2720 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4ed7ed8d
TP		 2721 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2722 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
2723 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2724 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
16a1fa25
TP		 2725 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2726 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
2727 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2728 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4ed7ed8d 2729
105bde57 2730 /* ARM V8.2 RAS extension instructions. */
4d1464f2 2731 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 2732 0xf3af8010, 0xffffffff, "esb"},
2733
53c4b28b 2734 /* V8 instructions. */
823d2571
TG		 2735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2736 0xf3af8005, 0xffffffff, "sevl%c.w"},
2737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2738 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2740 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2742 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
2743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2744 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
2745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2746 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
2747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2748 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
2749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2750 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
2751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2752 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
2753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2754 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2756 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2758 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
2759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2760 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2762 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2764 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2766 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 2767
dd5181d5 2768 /* CRC32 instructions. */
823d2571
TG		 2769 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2770 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"},
2771 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2772 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"},
2773 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2774 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"},
2775 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2776 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"},
2777 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2778 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"},
2779 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2780 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"},
dd5181d5 2781
62b3e311 2782 /* V7 instructions. */
823d2571
TG		 2783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
2784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
2785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
2786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
2787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
2788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
2789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
2790 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2791 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
2792 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2793 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 2794
90ec0d68 2795 /* Virtualization Extension instructions. */
823d2571 2796 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 2797 /* We skip ERET as that is SUBS pc, lr, #0. */
2798
60e5ef9f 2799 /* MP Extension instructions. */
823d2571 2800 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 2801
f4c65163 2802 /* Security extension instructions. */
823d2571 2803 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 2804
8f06b2d8 2805 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 2806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
2807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
2808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
2811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2812 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
2813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
2814
ff8646ee 2815 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2816 0xf3bf8f2f, 0xffffffff, "clrex%c"},
2817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2818 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
2819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2820 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
2821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2822 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
2823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2824 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
2825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2826 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
2827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2828 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
2829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2830 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
2831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2832 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
2833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2834 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
2835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2836 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
2837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2838 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
2839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2840 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
2841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2842 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 2843 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 2844 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 2845 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2846 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
2847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2848 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
2849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2850 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
2851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2852 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
2853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2854 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
2855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2856 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
2857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2858 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
2859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2860 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
2861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2862 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 2863 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2864 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
2865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2866 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
2867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2868 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
2869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2870 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
2871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2872 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
2873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2874 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
2875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2876 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
2877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2878 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
2879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2880 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
2881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2882 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
2883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2884 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
2885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2886 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
2887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2888 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
2889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2890 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
2891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2892 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
2893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2894 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
2895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2896 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
2897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2898 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
2899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2900 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
2901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2902 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
2903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2904 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
2905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2906 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
2907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2908 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
2909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2910 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
2911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2912 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
2913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2914 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
2915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2916 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
2917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2918 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
2919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2920 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
2921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2922 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
2923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2924 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
2925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2926 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
2927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2928 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
2929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2930 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
2931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2932 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
2933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2934 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
2935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2936 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
2937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2938 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
2939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2940 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
2941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2942 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
2943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2944 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
2945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2946 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
2947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2948 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
2949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2950 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
2951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2952 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
2953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2954 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
2955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2956 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
2957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2958 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
2959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2960 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
2961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2962 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
2963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2964 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2966 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2968 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2970 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 2971 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2972 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
2973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 2974 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 2975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2976 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
2977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2978 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
2979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2980 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2982 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
2983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2984 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
2985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2986 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2988 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2990 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2992 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2994 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2996 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2998 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3000 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
3001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3002 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
3003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3004 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
3005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3006 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
3007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3008 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
3009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3010 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
3011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3012 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
3013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3014 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
3015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3016 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
3017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3018 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
3019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3020 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
3021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3022 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
3023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3024 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3026 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3028 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3030 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3032 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3034 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3036 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3038 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 3039 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3040 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
3041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3042 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
3043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3044 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
3045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3046 0xf810f000, 0xff70f000, "pld%c\t%a"},
3047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3048 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3050 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3052 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3054 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3056 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3058 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3060 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3062 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
3063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3064 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
3065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3066 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
3067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3068 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
3069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3070 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
3071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3072 0xfb100000, 0xfff000c0,
3073 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3075 0xfbc00080, 0xfff000c0,
3076 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
3077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3078 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
3079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3080 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
3081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 3082 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 3083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3084 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
3085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3086 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 3087 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3088 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
3089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3090 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 3091 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3092 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
3093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3094 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
3095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3096 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
3097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3098 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
3099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3100 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
3101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3102 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
3103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3104 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
3105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3106 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
3107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3108 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
3109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3110 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
3111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3112 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 3113 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3114 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
3115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3116 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
3117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3118 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
3119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3120 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
3121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3122 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
3123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3124 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
3125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3126 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
3127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3128 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
3129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3130 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
3131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3132 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
3133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3134 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
3135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3136 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
3137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3138 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
3139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3140 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
3141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3142 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
3143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3144 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
3145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3146 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
3147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3148 0xe9400000, 0xff500000,
3149 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3151 0xe9500000, 0xff500000,
3152 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3154 0xe8600000, 0xff700000,
3155 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3157 0xe8700000, 0xff700000,
3158 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3160 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
3161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3162 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 3163
3164 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 3165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3166 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
3167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3168 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
3169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3170 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
3171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3172 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 3173
8f06b2d8 3174 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 3175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3176 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
3177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3178 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 3179
3180 /* Fallback. */
823d2571
TG		 3181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3182 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3183 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 3184};
ff4a8d2b 3185
8f06b2d8
PB		 3186static const char *const arm_conditional[] =
3187{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 3188 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 3189
3190static const char *const arm_fp_const[] =
3191{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3192
3193static const char *const arm_shift[] =
3194{"lsl", "lsr", "asr", "ror"};
3195
3196typedef struct
3197{
3198 const char *name;
3199 const char *description;
3200 const char *reg_names[16];
3201}
3202arm_regname;
3203
3204static const arm_regname regnames[] =
3205{
65b48a81 3206 { "reg-names-raw", N_("Select raw register names"),
8f06b2d8 3207 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
65b48a81 3208 { "reg-names-gcc", N_("Select register names used by GCC"),
8f06b2d8 3209 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 3210 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
8f06b2d8 3211 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65b48a81
PB		 3212 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
3213 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
3214 { "reg-names-apcs", N_("Select register names used in the APCS"),
8f06b2d8 3215 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 3216 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
8f06b2d8 3217 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
65b48a81
PB		 3218 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
3219 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
8f06b2d8
PB		 3220};
3221
3222static const char *const iwmmxt_wwnames[] =
3223{"b", "h", "w", "d"};
3224
3225static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 3226{"b", "bus", "bc", "bss",
3227 "h", "hus", "hc", "hss",
3228 "w", "wus", "wc", "wss",
3229 "d", "dus", "dc", "dss"
8f06b2d8
PB		 3230};
3231
3232static const char *const iwmmxt_regnames[] =
3233{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3234 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3235};
3236
3237static const char *const iwmmxt_cregnames[] =
3238{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3239 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3240};
3241
3242/* Default to GCC register name set. */
3243static unsigned int regname_selected = 1;
3244
65b48a81 3245#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
8f06b2d8
PB		 3246#define arm_regnames regnames[regname_selected].reg_names
3247
3248static bfd_boolean force_thumb = FALSE;
3249
c22aaad1
PB		 3250/* Current IT instruction state. This contains the same state as the IT
3251 bits in the CPSR. */
3252static unsigned int ifthen_state;
3253/* IT state for the next instruction. */
3254static unsigned int ifthen_next_state;
3255/* The address of the insn for which the IT state is valid. */
3256static bfd_vma ifthen_address;
3257#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 3258/* Indicates that the current Conditional state is unconditional or outside
3259 an IT block. */
3260#define COND_UNCOND 16
c22aaad1 3261
8f06b2d8
PB		 3262\f
3263/* Functions. */
8f06b2d8 3264
16980d0b
JB		 3265/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3266 Returns pointer to following character of the format string and
3267 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 3268 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 3269
3270static const char *
fe56b6ce
NC		 3271arm_decode_bitfield (const char *ptr,
3272 unsigned long insn,
3273 unsigned long *valuep,
3274 int *widthp)
16980d0b
JB		 3275{
3276 unsigned long value = 0;
3277 int width = 0;
43e65147
L		 3278
3279 do
16980d0b
JB		 3280 {
3281 int start, end;
3282 int bits;
3283
3284 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3285 start = start * 10 + *ptr - '0';
3286 if (*ptr == '-')
3287 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3288 end = end * 10 + *ptr - '0';
3289 else
3290 end = start;
3291 bits = end - start;
3292 if (bits < 0)
3293 abort ();
3294 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3295 width += bits + 1;
3296 }
3297 while (*ptr++ == ',');
3298 *valuep = value;
3299 if (widthp)
3300 *widthp = width;
3301 return ptr - 1;
3302}
3303
8f06b2d8 3304static void
37b37b2d 3305arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 3306 bfd_boolean print_shift)
8f06b2d8
PB		 3307{
3308 func (stream, "%s", arm_regnames[given & 0xf]);
3309
3310 if ((given & 0xff0) != 0)
3311 {
3312 if ((given & 0x10) == 0)
3313 {
3314 int amount = (given & 0xf80) >> 7;
3315 int shift = (given & 0x60) >> 5;
3316
3317 if (amount == 0)
3318 {
3319 if (shift == 3)
3320 {
3321 func (stream, ", rrx");
3322 return;
3323 }
3324
3325 amount = 32;
3326 }
3327
37b37b2d
RE		 3328 if (print_shift)
3329 func (stream, ", %s #%d", arm_shift[shift], amount);
3330 else
3331 func (stream, ", #%d", amount);
8f06b2d8 3332 }
74bdfecf 3333 else if ((given & 0x80) == 0x80)
aefd8a40 3334 func (stream, "\t; <illegal shifter operand>");
37b37b2d 3335 else if (print_shift)
8f06b2d8
PB		 3336 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3337 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 3338 else
3339 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 3340 }
3341}
3342
c1e26897
NC		 3343#define W_BIT 21
3344#define I_BIT 22
3345#define U_BIT 23
3346#define P_BIT 24
3347
3348#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
3349#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
3350#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
3351#define PRE_BIT_SET (given & (1 << P_BIT))
3352
8f06b2d8
PB		 3353/* Print one coprocessor instruction on INFO->STREAM.
3354 Return TRUE if the instuction matched, FALSE if this is not a
3355 recognised coprocessor instruction. */
3356
3357static bfd_boolean
fe56b6ce
NC		 3358print_insn_coprocessor (bfd_vma pc,
3359 struct disassemble_info *info,
3360 long given,
8f06b2d8
PB		 3361 bfd_boolean thumb)
3362{
3363 const struct opcode32 *insn;
3364 void *stream = info->stream;
3365 fprintf_ftype func = info->fprintf_func;
3366 unsigned long mask;
2edcd244 3367 unsigned long value = 0;
c22aaad1 3368 int cond;
8afc7bea 3369 int cp_num;
823d2571
TG		 3370 struct arm_private_data *private_data = info->private_data;
3371 arm_feature_set allowed_arches = ARM_ARCH_NONE;
3372
3373 ARM_FEATURE_COPY (allowed_arches, private_data->features);
8f06b2d8
PB		 3374
3375 for (insn = coprocessor_opcodes; insn->assembler; insn++)
3376 {
ff4a8d2b
NC		 3377 unsigned long u_reg = 16;
3378 bfd_boolean is_unpredictable = FALSE;
05413229 3379 signed long value_in_comment = 0;
0313a2b8
NC		 3380 const char *c;
3381
823d2571 3382 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 3383 switch (insn->value)
3384 {
3385 case SENTINEL_IWMMXT_START:
3386 if (info->mach != bfd_mach_arm_XScale
3387 && info->mach != bfd_mach_arm_iWMMXt
3388 && info->mach != bfd_mach_arm_iWMMXt2)
3389 do
3390 insn++;
823d2571
TG		 3391 while ((! ARM_FEATURE_ZERO (insn->arch))
3392 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 3393 continue;
3394
3395 case SENTINEL_IWMMXT_END:
3396 continue;
3397
3398 case SENTINEL_GENERIC_START:
823d2571 3399 ARM_FEATURE_COPY (allowed_arches, private_data->features);
05413229
NC		 3400 continue;
3401
3402 default:
3403 abort ();
3404 }
8f06b2d8
PB		 3405
3406 mask = insn->mask;
3407 value = insn->value;
8afc7bea
RL		 3408 cp_num = (given >> 8) & 0xf;
3409
8f06b2d8
PB		 3410 if (thumb)
3411 {
3412 /* The high 4 bits are 0xe for Arm conditional instructions, and
3413 0xe for arm unconditional instructions. The rest of the
3414 encoding is the same. */
3415 mask |= 0xf0000000;
3416 value |= 0xe0000000;
c22aaad1
PB		 3417 if (ifthen_state)
3418 cond = IFTHEN_COND;
3419 else
e2efe87d 3420 cond = COND_UNCOND;
8f06b2d8
PB		 3421 }
3422 else
3423 {
3424 /* Only match unconditional instuctions against unconditional
3425 patterns. */
3426 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 3427 {
3428 mask |= 0xf0000000;
e2efe87d 3429 cond = COND_UNCOND;
c22aaad1
PB		 3430 }
3431 else
3432 {
3433 cond = (given >> 28) & 0xf;
3434 if (cond == 0xe)
e2efe87d 3435 cond = COND_UNCOND;
c22aaad1 3436 }
8f06b2d8 3437 }
823d2571 3438
0313a2b8
NC		 3439 if ((given & mask) != value)
3440 continue;
8f06b2d8 3441
823d2571 3442 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 3443 continue;
3444
8afc7bea
RL		 3445 if (insn->value == 0xfe000010 /* mcr2 */
3446 || insn->value == 0xfe100010 /* mrc2 */
3447 || insn->value == 0xfc100000 /* ldc2 */
3448 || insn->value == 0xfc000000) /* stc2 */
3449 {
b0c11777 3450 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea
RL		 3451 is_unpredictable = TRUE;
3452 }
3453 else if (insn->value == 0x0e000000 /* cdp */
3454 || insn->value == 0xfe000000 /* cdp2 */
3455 || insn->value == 0x0e000010 /* mcr */
3456 || insn->value == 0x0e100010 /* mrc */
3457 || insn->value == 0x0c100000 /* ldc */
3458 || insn->value == 0x0c000000) /* stc */
3459 {
3460 /* Floating-point instructions. */
b0c11777 3461 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea
RL		 3462 continue;
3463 }
3464
0313a2b8
NC		 3465 for (c = insn->assembler; *c; c++)
3466 {
3467 if (*c == '%')
8f06b2d8 3468 {
0313a2b8 3469 switch (*++c)
8f06b2d8 3470 {
0313a2b8
NC		 3471 case '%':
3472 func (stream, "%%");
3473 break;
3474
3475 case 'A':
05413229 3476 {
79862e45 3477 int rn = (given >> 16) & 0xf;
b0c11777 3478 bfd_vma offset = given & 0xff;
0313a2b8 3479
05413229 3480 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 3481
79862e45
DJ		 3482 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
3483 {
3484 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 3485 if (cp_num == 9)
3486 /* vldr.16/vstr.16 will shift the address
3487 left by 1 bit only. */
3488 offset = offset * 2;
3489 else
3490 offset = offset * 4;
3491
79862e45
DJ		 3492 if (NEGATIVE_BIT_SET)
3493 offset = - offset;
3494 if (rn != 15)
3495 value_in_comment = offset;
3496 }
3497
c1e26897 3498 if (PRE_BIT_SET)
05413229
NC		 3499 {
3500 if (offset)
fe56b6ce 3501 func (stream, ", #%d]%s",
d908c8af 3502 (int) offset,
c1e26897 3503 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 3504 else if (NEGATIVE_BIT_SET)
3505 func (stream, ", #-0]");
05413229
NC		 3506 else
3507 func (stream, "]");
3508 }
3509 else
3510 {
0313a2b8 3511 func (stream, "]");
8f06b2d8 3512
c1e26897 3513 if (WRITEBACK_BIT_SET)
05413229
NC		 3514 {
3515 if (offset)
d908c8af 3516 func (stream, ", #%d", (int) offset);
26d97720
NS		 3517 else if (NEGATIVE_BIT_SET)
3518 func (stream, ", #-0");
05413229
NC		 3519 }
3520 else
fe56b6ce 3521 {
26d97720
NS		 3522 func (stream, ", {%s%d}",
3523 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 3524 (int) offset);
fe56b6ce
NC		 3525 value_in_comment = offset;
3526 }
05413229 3527 }
79862e45
DJ		 3528 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
3529 {
3530 func (stream, "\t; ");
6844b2c2
MGD		 3531 /* For unaligned PCs, apply off-by-alignment
3532 correction. */
43e65147 3533 info->print_address_func (offset + pc
6844b2c2
MGD		 3534 + info->bytes_per_chunk * 2
3535 - (pc & 3),
3536 info);
79862e45 3537 }
05413229 3538 }
0313a2b8 3539 break;
8f06b2d8 3540
0313a2b8
NC		 3541 case 'B':
3542 {
3543 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
3544 int offset = (given >> 1) & 0x3f;
3545
3546 if (offset == 1)
3547 func (stream, "{d%d}", regno);
3548 else if (regno + offset > 32)
3549 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
3550 else
3551 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
3552 }
3553 break;
8f06b2d8 3554
e2efe87d
MGD		 3555 case 'u':
3556 if (cond != COND_UNCOND)
3557 is_unpredictable = TRUE;
3558
3559 /* Fall through. */
0313a2b8 3560 case 'c':
b0c11777
RL		 3561 if (cond != COND_UNCOND && cp_num == 9)
3562 is_unpredictable = TRUE;
3563
0313a2b8
NC		 3564 func (stream, "%s", arm_conditional[cond]);
3565 break;
8f06b2d8 3566
0313a2b8
NC		 3567 case 'I':
3568 /* Print a Cirrus/DSP shift immediate. */
3569 /* Immediates are 7bit signed ints with bits 0..3 in
3570 bits 0..3 of opcode and bits 4..6 in bits 5..7
3571 of opcode. */
3572 {
3573 int imm;
8f06b2d8 3574
0313a2b8 3575 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 3576
0313a2b8
NC		 3577 /* Is ``imm'' a negative number? */
3578 if (imm & 0x40)
24b4cf66 3579 imm -= 0x80;
8f06b2d8 3580
0313a2b8
NC		 3581 func (stream, "%d", imm);
3582 }
3583
3584 break;
8f06b2d8 3585
0313a2b8
NC		 3586 case 'F':
3587 switch (given & 0x00408000)
3588 {
3589 case 0:
3590 func (stream, "4");
3591 break;
3592 case 0x8000:
3593 func (stream, "1");
3594 break;
3595 case 0x00400000:
3596 func (stream, "2");
8f06b2d8 3597 break;
0313a2b8
NC		 3598 default:
3599 func (stream, "3");
3600 }
3601 break;
8f06b2d8 3602
0313a2b8
NC		 3603 case 'P':
3604 switch (given & 0x00080080)
3605 {
3606 case 0:
3607 func (stream, "s");
3608 break;
3609 case 0x80:
3610 func (stream, "d");
3611 break;
3612 case 0x00080000:
3613 func (stream, "e");
3614 break;
3615 default:
3616 func (stream, _("<illegal precision>"));
8f06b2d8 3617 break;
0313a2b8
NC		 3618 }
3619 break;
8f06b2d8 3620
0313a2b8
NC		 3621 case 'Q':
3622 switch (given & 0x00408000)
3623 {
3624 case 0:
3625 func (stream, "s");
8f06b2d8 3626 break;
0313a2b8
NC		 3627 case 0x8000:
3628 func (stream, "d");
8f06b2d8 3629 break;
0313a2b8
NC		 3630 case 0x00400000:
3631 func (stream, "e");
3632 break;
3633 default:
3634 func (stream, "p");
8f06b2d8 3635 break;
0313a2b8
NC		 3636 }
3637 break;
8f06b2d8 3638
0313a2b8
NC		 3639 case 'R':
3640 switch (given & 0x60)
3641 {
3642 case 0:
3643 break;
3644 case 0x20:
3645 func (stream, "p");
3646 break;
3647 case 0x40:
3648 func (stream, "m");
3649 break;
3650 default:
3651 func (stream, "z");
3652 break;
3653 }
3654 break;
16980d0b 3655
0313a2b8
NC		 3656 case '0': case '1': case '2': case '3': case '4':
3657 case '5': case '6': case '7': case '8': case '9':
3658 {
3659 int width;
8f06b2d8 3660
0313a2b8 3661 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 3662
0313a2b8
NC		 3663 switch (*c)
3664 {
ff4a8d2b
NC		 3665 case 'R':
3666 if (value == 15)
3667 is_unpredictable = TRUE;
3668 /* Fall through. */
0313a2b8 3669 case 'r':
ff4a8d2b
NC		 3670 if (c[1] == 'u')
3671 {
3672 /* Eat the 'u' character. */
3673 ++ c;
3674
3675 if (u_reg == value)
3676 is_unpredictable = TRUE;
3677 u_reg = value;
3678 }
0313a2b8
NC		 3679 func (stream, "%s", arm_regnames[value]);
3680 break;
c28eeff2
SN		 3681 case 'V':
3682 if (given & (1 << 6))
3683 goto Q;
3684 /* FALLTHROUGH */
0313a2b8
NC		 3685 case 'D':
3686 func (stream, "d%ld", value);
3687 break;
3688 case 'Q':
c28eeff2 3689 Q:
0313a2b8
NC		 3690 if (value & 1)
3691 func (stream, "<illegal reg q%ld.5>", value >> 1);
3692 else
3693 func (stream, "q%ld", value >> 1);
3694 break;
3695 case 'd':
3696 func (stream, "%ld", value);
05413229 3697 value_in_comment = value;
0313a2b8 3698 break;
6f1c2142
AM		 3699 case 'E':
3700 {
3701 /* Converts immediate 8 bit back to float value. */
3702 unsigned floatVal = (value & 0x80) << 24
3703 | (value & 0x3F) << 19
3704 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
3705
3706 /* Quarter float have a maximum value of 31.0.
3707 Get floating point value multiplied by 1e7.
3708 The maximum value stays in limit of a 32-bit int. */
3709 unsigned decVal =
3710 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
3711 (16 + (value & 0xF));
3712
3713 if (!(decVal % 1000000))
3714 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
3715 floatVal, value & 0x80 ? '-' : ' ',
3716 decVal / 10000000,
3717 decVal % 10000000 / 1000000);
3718 else if (!(decVal % 10000))
3719 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
3720 floatVal, value & 0x80 ? '-' : ' ',
3721 decVal / 10000000,
3722 decVal % 10000000 / 10000);
3723 else
3724 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
3725 floatVal, value & 0x80 ? '-' : ' ',
3726 decVal / 10000000, decVal % 10000000);
3727 break;
3728 }
0313a2b8
NC		 3729 case 'k':
3730 {
3731 int from = (given & (1 << 7)) ? 32 : 16;
3732 func (stream, "%ld", from - value);
3733 }
3734 break;
8f06b2d8 3735
0313a2b8
NC		 3736 case 'f':
3737 if (value > 7)
3738 func (stream, "#%s", arm_fp_const[value & 7]);
3739 else
3740 func (stream, "f%ld", value);
3741 break;
4146fd53 3742
0313a2b8
NC		 3743 case 'w':
3744 if (width == 2)
3745 func (stream, "%s", iwmmxt_wwnames[value]);
3746 else
3747 func (stream, "%s", iwmmxt_wwssnames[value]);
3748 break;
4146fd53 3749
0313a2b8
NC		 3750 case 'g':
3751 func (stream, "%s", iwmmxt_regnames[value]);
3752 break;
3753 case 'G':
3754 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 3755 break;
8f06b2d8 3756
0313a2b8 3757 case 'x':
d1aaab3c 3758 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 3759 break;
8f06b2d8 3760
33399f07
MGD		 3761 case 'c':
3762 switch (value)
3763 {
3764 case 0:
3765 func (stream, "eq");
3766 break;
3767
3768 case 1:
3769 func (stream, "vs");
3770 break;
3771
3772 case 2:
3773 func (stream, "ge");
3774 break;
3775
3776 case 3:
3777 func (stream, "gt");
3778 break;
3779
3780 default:
3781 func (stream, "??");
3782 break;
3783 }
3784 break;
3785
0313a2b8
NC		 3786 case '`':
3787 c++;
3788 if (value == 0)
3789 func (stream, "%c", *c);
3790 break;
3791 case '\'':
3792 c++;
3793 if (value == ((1ul << width) - 1))
3794 func (stream, "%c", *c);
3795 break;
3796 case '?':
fe56b6ce 3797 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 3798 c += 1 << width;
3799 break;
3800 default:
3801 abort ();
3802 }
3803 break;
8f06b2d8 3804
0313a2b8
NC		 3805 case 'y':
3806 case 'z':
3807 {
3808 int single = *c++ == 'y';
3809 int regno;
3810
3811 switch (*c)
3812 {
3813 case '4': /* Sm pair */
3814 case '0': /* Sm, Dm */
3815 regno = given & 0x0000000f;
3816 if (single)
3817 {
3818 regno <<= 1;
3819 regno += (given >> 5) & 1;
16980d0b 3820 }
0313a2b8
NC		 3821 else
3822 regno += ((given >> 5) & 1) << 4;
3823 break;
8f06b2d8 3824
0313a2b8
NC		 3825 case '1': /* Sd, Dd */
3826 regno = (given >> 12) & 0x0000000f;
3827 if (single)
3828 {
3829 regno <<= 1;
3830 regno += (given >> 22) & 1;
3831 }
3832 else
3833 regno += ((given >> 22) & 1) << 4;
3834 break;
8f06b2d8 3835
0313a2b8
NC		 3836 case '2': /* Sn, Dn */
3837 regno = (given >> 16) & 0x0000000f;
3838 if (single)
8f06b2d8 3839 {
0313a2b8
NC		 3840 regno <<= 1;
3841 regno += (given >> 7) & 1;
8f06b2d8 3842 }
0313a2b8
NC		 3843 else
3844 regno += ((given >> 7) & 1) << 4;
3845 break;
7df76b80 3846
0313a2b8
NC		 3847 case '3': /* List */
3848 func (stream, "{");
3849 regno = (given >> 12) & 0x0000000f;
3850 if (single)
3851 {
3852 regno <<= 1;
3853 regno += (given >> 22) & 1;
3854 }
3855 else
3856 regno += ((given >> 22) & 1) << 4;
3857 break;
a7f8487e 3858
0313a2b8
NC		 3859 default:
3860 abort ();
8f06b2d8 3861 }
a7f8487e 3862
0313a2b8
NC		 3863 func (stream, "%c%d", single ? 's' : 'd', regno);
3864
3865 if (*c == '3')
8f06b2d8 3866 {
0313a2b8 3867 int count = given & 0xff;
a7f8487e 3868
0313a2b8
NC		 3869 if (single == 0)
3870 count >>= 1;
b34976b6 3871
0313a2b8 3872 if (--count)
8f06b2d8 3873 {
0313a2b8
NC		 3874 func (stream, "-%c%d",
3875 single ? 's' : 'd',
3876 regno + count);
8f06b2d8 3877 }
0313a2b8
NC		 3878
3879 func (stream, "}");
8f06b2d8 3880 }
0313a2b8
NC		 3881 else if (*c == '4')
3882 func (stream, ", %c%d", single ? 's' : 'd',
3883 regno + 1);
3884 }
3885 break;
3886
3887 case 'L':
3888 switch (given & 0x00400100)
3889 {
3890 case 0x00000000: func (stream, "b"); break;
3891 case 0x00400000: func (stream, "h"); break;
3892 case 0x00000100: func (stream, "w"); break;
3893 case 0x00400100: func (stream, "d"); break;
3894 default:
8f06b2d8 3895 break;
0313a2b8
NC		 3896 }
3897 break;
b34976b6 3898
0313a2b8
NC		 3899 case 'Z':
3900 {
0313a2b8
NC		 3901 /* given (20, 23) | given (0, 3) */
3902 value = ((given >> 16) & 0xf0) | (given & 0xf);
d908c8af 3903 func (stream, "%d", (int) value);
0313a2b8
NC		 3904 }
3905 break;
2d447fca 3906
0313a2b8
NC		 3907 case 'l':
3908 /* This is like the 'A' operator, except that if
3909 the width field "M" is zero, then the offset is
3910 *not* multiplied by four. */
3911 {
3912 int offset = given & 0xff;
3913 int multiplier = (given & 0x00000100) ? 4 : 1;
3914
3915 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3916
05413229
NC		 3917 if (multiplier > 1)
3918 {
3919 value_in_comment = offset * multiplier;
c1e26897 3920 if (NEGATIVE_BIT_SET)
05413229
NC		 3921 value_in_comment = - value_in_comment;
3922 }
3923
0313a2b8
NC		 3924 if (offset)
3925 {
c1e26897 3926 if (PRE_BIT_SET)
0313a2b8 3927 func (stream, ", #%s%d]%s",
c1e26897 3928 NEGATIVE_BIT_SET ? "-" : "",
0313a2b8 3929 offset * multiplier,
c1e26897 3930 WRITEBACK_BIT_SET ? "!" : "");
0313a2b8
NC		 3931 else
3932 func (stream, "], #%s%d",
c1e26897 3933 NEGATIVE_BIT_SET ? "-" : "",
0313a2b8 3934 offset * multiplier);
2d447fca 3935 }
0313a2b8
NC		 3936 else
3937 func (stream, "]");
3938 }
3939 break;
3940
3941 case 'r':
3942 {
3943 int imm4 = (given >> 4) & 0xf;
c1e26897
NC		 3944 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
3945 int ubit = ! NEGATIVE_BIT_SET;
0313a2b8
NC		 3946 const char *rm = arm_regnames [given & 0xf];
3947 const char *rn = arm_regnames [(given >> 16) & 0xf];
2d447fca 3948
0313a2b8 3949 switch (puw_bits)
2d447fca 3950 {
0313a2b8
NC		 3951 case 1:
3952 case 3:
3953 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
3954 if (imm4)
3955 func (stream, ", lsl #%d", imm4);
3956 break;
3957
3958 case 4:
3959 case 5:
3960 case 6:
3961 case 7:
3962 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
3963 if (imm4 > 0)
3964 func (stream, ", lsl #%d", imm4);
3965 func (stream, "]");
3966 if (puw_bits == 5 || puw_bits == 7)
3967 func (stream, "!");
3968 break;
3969
3970 default:
3971 func (stream, "INVALID");
2d447fca 3972 }
0313a2b8
NC		 3973 }
3974 break;
2d447fca 3975
0313a2b8
NC		 3976 case 'i':
3977 {
3978 long imm5;
3979 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
3980 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
8f06b2d8 3981 }
0313a2b8
NC		 3982 break;
3983
3984 default:
3985 abort ();
3986 }
252b5132 3987 }
252b5132 3988 }
0313a2b8
NC		 3989 else
3990 func (stream, "%c", *c);
252b5132 3991 }
05413229
NC		 3992
3993 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 3994 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 3995
ff4a8d2b
NC		 3996 if (is_unpredictable)
3997 func (stream, UNPREDICTABLE_INSTRUCTION);
3998
0313a2b8 3999 return TRUE;
252b5132 4000 }
8f06b2d8 4001 return FALSE;
252b5132
RH		 4002}
4003
05413229
NC		 4004/* Decodes and prints ARM addressing modes. Returns the offset
4005 used in the address, if any, if it is worthwhile printing the
4006 offset as a hexadecimal value in a comment at the end of the
4007 line of disassembly. */
4008
4009static signed long
62b3e311
PB		 4010print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
4011{
4012 void *stream = info->stream;
4013 fprintf_ftype func = info->fprintf_func;
f8b960bc 4014 bfd_vma offset = 0;
62b3e311
PB		 4015
4016 if (((given & 0x000f0000) == 0x000f0000)
4017 && ((given & 0x02000000) == 0))
4018 {
05413229 4019 offset = given & 0xfff;
62b3e311
PB		 4020
4021 func (stream, "[pc");
4022
c1e26897 4023 if (PRE_BIT_SET)
62b3e311 4024 {
26d97720
NS		 4025 /* Pre-indexed. Elide offset of positive zero when
4026 non-writeback. */
4027 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 4028 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 4029
4030 if (NEGATIVE_BIT_SET)
4031 offset = -offset;
62b3e311
PB		 4032
4033 offset += pc + 8;
4034
4035 /* Cope with the possibility of write-back
4036 being used. Probably a very dangerous thing
4037 for the programmer to do, but who are we to
4038 argue ? */
26d97720 4039 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 4040 }
c1e26897 4041 else /* Post indexed. */
62b3e311 4042 {
d908c8af 4043 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 4044
c1e26897 4045 /* Ie ignore the offset. */
62b3e311
PB		 4046 offset = pc + 8;
4047 }
4048
4049 func (stream, "\t; ");
4050 info->print_address_func (offset, info);
05413229 4051 offset = 0;
62b3e311
PB		 4052 }
4053 else
4054 {
4055 func (stream, "[%s",
4056 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 4057
4058 if (PRE_BIT_SET)
62b3e311
PB		 4059 {
4060 if ((given & 0x02000000) == 0)
4061 {
26d97720 4062 /* Elide offset of positive zero when non-writeback. */
05413229 4063 offset = given & 0xfff;
26d97720 4064 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 4065 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 4066 }
4067 else
4068 {
26d97720 4069 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 4070 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 4071 }
4072
4073 func (stream, "]%s",
c1e26897 4074 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 4075 }
4076 else
4077 {
4078 if ((given & 0x02000000) == 0)
4079 {
26d97720 4080 /* Always show offset. */
05413229 4081 offset = given & 0xfff;
26d97720 4082 func (stream, "], #%s%d",
d908c8af 4083 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 4084 }
4085 else
4086 {
4087 func (stream, "], %s",
c1e26897 4088 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 4089 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 4090 }
4091 }
84919466
MR		 4092 if (NEGATIVE_BIT_SET)
4093 offset = -offset;
62b3e311 4094 }
05413229
NC		 4095
4096 return (signed long) offset;
62b3e311
PB		 4097}
4098
16980d0b
JB		 4099/* Print one neon instruction on INFO->STREAM.
4100 Return TRUE if the instuction matched, FALSE if this is not a
4101 recognised neon instruction. */
4102
4103static bfd_boolean
4104print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
4105{
4106 const struct opcode32 *insn;
4107 void *stream = info->stream;
4108 fprintf_ftype func = info->fprintf_func;
4109
4110 if (thumb)
4111 {
4112 if ((given & 0xef000000) == 0xef000000)
4113 {
0313a2b8 4114 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 4115 unsigned long bit28 = given & (1 << 28);
4116
4117 given &= 0x00ffffff;
4118 if (bit28)
4119 given |= 0xf3000000;
4120 else
4121 given |= 0xf2000000;
4122 }
4123 else if ((given & 0xff000000) == 0xf9000000)
4124 given ^= 0xf9000000 ^ 0xf4000000;
4125 else
4126 return FALSE;
4127 }
43e65147 4128
16980d0b
JB		 4129 for (insn = neon_opcodes; insn->assembler; insn++)
4130 {
4131 if ((given & insn->mask) == insn->value)
4132 {
05413229 4133 signed long value_in_comment = 0;
e2efe87d 4134 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 4135 const char *c;
4136
4137 for (c = insn->assembler; *c; c++)
4138 {
4139 if (*c == '%')
4140 {
4141 switch (*++c)
4142 {
4143 case '%':
4144 func (stream, "%%");
4145 break;
4146
e2efe87d
MGD		 4147 case 'u':
4148 if (thumb && ifthen_state)
4149 is_unpredictable = TRUE;
4150
4151 /* Fall through. */
c22aaad1
PB		 4152 case 'c':
4153 if (thumb && ifthen_state)
4154 func (stream, "%s", arm_conditional[IFTHEN_COND]);
4155 break;
4156
16980d0b
JB		 4157 case 'A':
4158 {
43e65147 4159 static const unsigned char enc[16] =
16980d0b
JB		 4160 {
4161 0x4, 0x14, /* st4 0,1 */
4162 0x4, /* st1 2 */
4163 0x4, /* st2 3 */
4164 0x3, /* st3 4 */
4165 0x13, /* st3 5 */
4166 0x3, /* st1 6 */
4167 0x1, /* st1 7 */
4168 0x2, /* st2 8 */
4169 0x12, /* st2 9 */
4170 0x2, /* st1 10 */
4171 0, 0, 0, 0, 0
4172 };
4173 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4174 int rn = ((given >> 16) & 0xf);
4175 int rm = ((given >> 0) & 0xf);
4176 int align = ((given >> 4) & 0x3);
4177 int type = ((given >> 8) & 0xf);
4178 int n = enc[type] & 0xf;
4179 int stride = (enc[type] >> 4) + 1;
4180 int ix;
43e65147 4181
16980d0b
JB		 4182 func (stream, "{");
4183 if (stride > 1)
4184 for (ix = 0; ix != n; ix++)
4185 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
4186 else if (n == 1)
4187 func (stream, "d%d", rd);
4188 else
4189 func (stream, "d%d-d%d", rd, rd + n - 1);
4190 func (stream, "}, [%s", arm_regnames[rn]);
4191 if (align)
8e560766 4192 func (stream, " :%d", 32 << align);
16980d0b
JB		 4193 func (stream, "]");
4194 if (rm == 0xd)
4195 func (stream, "!");
4196 else if (rm != 0xf)
4197 func (stream, ", %s", arm_regnames[rm]);
4198 }
4199 break;
43e65147 4200
16980d0b
JB		 4201 case 'B':
4202 {
4203 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4204 int rn = ((given >> 16) & 0xf);
4205 int rm = ((given >> 0) & 0xf);
4206 int idx_align = ((given >> 4) & 0xf);
4207 int align = 0;
4208 int size = ((given >> 10) & 0x3);
4209 int idx = idx_align >> (size + 1);
4210 int length = ((given >> 8) & 3) + 1;
4211 int stride = 1;
4212 int i;
4213
4214 if (length > 1 && size > 0)
4215 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 4216
16980d0b
JB		 4217 switch (length)
4218 {
4219 case 1:
4220 {
4221 int amask = (1 << size) - 1;
4222 if ((idx_align & (1 << size)) != 0)
4223 return FALSE;
4224 if (size > 0)
4225 {
4226 if ((idx_align & amask) == amask)
4227 align = 8 << size;
4228 else if ((idx_align & amask) != 0)
4229 return FALSE;
4230 }
4231 }
4232 break;
43e65147 4233
16980d0b
JB		 4234 case 2:
4235 if (size == 2 && (idx_align & 2) != 0)
4236 return FALSE;
4237 align = (idx_align & 1) ? 16 << size : 0;
4238 break;
43e65147 4239
16980d0b
JB		 4240 case 3:
4241 if ((size == 2 && (idx_align & 3) != 0)
4242 || (idx_align & 1) != 0)
4243 return FALSE;
4244 break;
43e65147 4245
16980d0b
JB		 4246 case 4:
4247 if (size == 2)
4248 {
4249 if ((idx_align & 3) == 3)
4250 return FALSE;
4251 align = (idx_align & 3) * 64;
4252 }
4253 else
4254 align = (idx_align & 1) ? 32 << size : 0;
4255 break;
43e65147 4256
16980d0b
JB		 4257 default:
4258 abort ();
4259 }
43e65147 4260
16980d0b
JB		 4261 func (stream, "{");
4262 for (i = 0; i < length; i++)
4263 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
4264 rd + i * stride, idx);
4265 func (stream, "}, [%s", arm_regnames[rn]);
4266 if (align)
8e560766 4267 func (stream, " :%d", align);
16980d0b
JB		 4268 func (stream, "]");
4269 if (rm == 0xd)
4270 func (stream, "!");
4271 else if (rm != 0xf)
4272 func (stream, ", %s", arm_regnames[rm]);
4273 }
4274 break;
43e65147 4275
16980d0b
JB		 4276 case 'C':
4277 {
4278 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4279 int rn = ((given >> 16) & 0xf);
4280 int rm = ((given >> 0) & 0xf);
4281 int align = ((given >> 4) & 0x1);
4282 int size = ((given >> 6) & 0x3);
4283 int type = ((given >> 8) & 0x3);
4284 int n = type + 1;
4285 int stride = ((given >> 5) & 0x1);
4286 int ix;
43e65147 4287
16980d0b
JB		 4288 if (stride && (n == 1))
4289 n++;
4290 else
4291 stride++;
43e65147 4292
16980d0b
JB		 4293 func (stream, "{");
4294 if (stride > 1)
4295 for (ix = 0; ix != n; ix++)
4296 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
4297 else if (n == 1)
4298 func (stream, "d%d[]", rd);
4299 else
4300 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
4301 func (stream, "}, [%s", arm_regnames[rn]);
4302 if (align)
4303 {
91d6fa6a 4304 align = (8 * (type + 1)) << size;
16980d0b
JB		 4305 if (type == 3)
4306 align = (size > 1) ? align >> 1 : align;
4307 if (type == 2 || (type == 0 && !size))
8e560766 4308 func (stream, " :<bad align %d>", align);
16980d0b 4309 else
8e560766 4310 func (stream, " :%d", align);
16980d0b
JB		 4311 }
4312 func (stream, "]");
4313 if (rm == 0xd)
4314 func (stream, "!");
4315 else if (rm != 0xf)
4316 func (stream, ", %s", arm_regnames[rm]);
4317 }
4318 break;
43e65147 4319
16980d0b
JB		 4320 case 'D':
4321 {
4322 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
4323 int size = (given >> 20) & 3;
4324 int reg = raw_reg & ((4 << size) - 1);
4325 int ix = raw_reg >> size >> 2;
43e65147 4326
16980d0b
JB		 4327 func (stream, "d%d[%d]", reg, ix);
4328 }
4329 break;
43e65147 4330
16980d0b 4331 case 'E':
fe56b6ce 4332 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 4333 {
4334 int bits = 0;
4335 int cmode = (given >> 8) & 0xf;
4336 int op = (given >> 5) & 0x1;
4337 unsigned long value = 0, hival = 0;
4338 unsigned shift;
4339 int size = 0;
0dbde4cf 4340 int isfloat = 0;
43e65147 4341
16980d0b
JB		 4342 bits |= ((given >> 24) & 1) << 7;
4343 bits |= ((given >> 16) & 7) << 4;
4344 bits |= ((given >> 0) & 15) << 0;
43e65147 4345
16980d0b
JB		 4346 if (cmode < 8)
4347 {
4348 shift = (cmode >> 1) & 3;
fe56b6ce 4349 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4350 size = 32;
4351 }
4352 else if (cmode < 12)
4353 {
4354 shift = (cmode >> 1) & 1;
fe56b6ce 4355 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4356 size = 16;
4357 }
4358 else if (cmode < 14)
4359 {
4360 shift = (cmode & 1) + 1;
fe56b6ce 4361 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4362 value |= (1ul << (8 * shift)) - 1;
4363 size = 32;
4364 }
4365 else if (cmode == 14)
4366 {
4367 if (op)
4368 {
fe56b6ce 4369 /* Bit replication into bytes. */
16980d0b
JB		 4370 int ix;
4371 unsigned long mask;
43e65147 4372
16980d0b
JB		 4373 value = 0;
4374 hival = 0;
4375 for (ix = 7; ix >= 0; ix--)
4376 {
4377 mask = ((bits >> ix) & 1) ? 0xff : 0;
4378 if (ix <= 3)
4379 value = (value << 8) | mask;
4380 else
4381 hival = (hival << 8) | mask;
4382 }
4383 size = 64;
4384 }
4385 else
4386 {
fe56b6ce
NC		 4387 /* Byte replication. */
4388 value = (unsigned long) bits;
16980d0b
JB		 4389 size = 8;
4390 }
4391 }
4392 else if (!op)
4393 {
fe56b6ce 4394 /* Floating point encoding. */
16980d0b 4395 int tmp;
43e65147 4396
fe56b6ce
NC		 4397 value = (unsigned long) (bits & 0x7f) << 19;
4398 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 4399 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 4400 value |= (unsigned long) tmp << 24;
16980d0b 4401 size = 32;
0dbde4cf 4402 isfloat = 1;
16980d0b
JB		 4403 }
4404 else
4405 {
4406 func (stream, "<illegal constant %.8x:%x:%x>",
4407 bits, cmode, op);
4408 size = 32;
4409 break;
4410 }
4411 switch (size)
4412 {
4413 case 8:
4414 func (stream, "#%ld\t; 0x%.2lx", value, value);
4415 break;
43e65147 4416
16980d0b
JB		 4417 case 16:
4418 func (stream, "#%ld\t; 0x%.4lx", value, value);
4419 break;
4420
4421 case 32:
0dbde4cf
JB		 4422 if (isfloat)
4423 {
4424 unsigned char valbytes[4];
4425 double fvalue;
43e65147 4426
0dbde4cf
JB		 4427 /* Do this a byte at a time so we don't have to
4428 worry about the host's endianness. */
4429 valbytes[0] = value & 0xff;
4430 valbytes[1] = (value >> 8) & 0xff;
4431 valbytes[2] = (value >> 16) & 0xff;
4432 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 4433
4434 floatformat_to_double
c1e26897
NC		 4435 (& floatformat_ieee_single_little, valbytes,
4436 & fvalue);
43e65147 4437
0dbde4cf
JB		 4438 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
4439 value);
4440 }
4441 else
4e9d3b81 4442 func (stream, "#%ld\t; 0x%.8lx",
43e65147 4443 (long) (((value & 0x80000000L) != 0)
9d82ec38 4444 ? value | ~0xffffffffL : value),
c1e26897 4445 value);
16980d0b
JB		 4446 break;
4447
4448 case 64:
4449 func (stream, "#0x%.8lx%.8lx", hival, value);
4450 break;
43e65147 4451
16980d0b
JB		 4452 default:
4453 abort ();
4454 }
4455 }
4456 break;
43e65147 4457
16980d0b
JB		 4458 case 'F':
4459 {
4460 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
4461 int num = (given >> 8) & 0x3;
43e65147 4462
16980d0b
JB		 4463 if (!num)
4464 func (stream, "{d%d}", regno);
4465 else if (num + regno >= 32)
4466 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
4467 else
4468 func (stream, "{d%d-d%d}", regno, regno + num);
4469 }
4470 break;
7e8e6784 4471
16980d0b
JB		 4472
4473 case '0': case '1': case '2': case '3': case '4':
4474 case '5': case '6': case '7': case '8': case '9':
4475 {
4476 int width;
4477 unsigned long value;
4478
4479 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 4480
16980d0b
JB		 4481 switch (*c)
4482 {
4483 case 'r':
4484 func (stream, "%s", arm_regnames[value]);
4485 break;
4486 case 'd':
4487 func (stream, "%ld", value);
05413229 4488 value_in_comment = value;
16980d0b
JB		 4489 break;
4490 case 'e':
4491 func (stream, "%ld", (1ul << width) - value);
4492 break;
43e65147 4493
16980d0b
JB		 4494 case 'S':
4495 case 'T':
4496 case 'U':
05413229 4497 /* Various width encodings. */
16980d0b
JB		 4498 {
4499 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
4500 int limit;
4501 unsigned low, high;
4502
4503 c++;
4504 if (*c >= '0' && *c <= '9')
4505 limit = *c - '0';
4506 else if (*c >= 'a' && *c <= 'f')
4507 limit = *c - 'a' + 10;
4508 else
4509 abort ();
4510 low = limit >> 2;
4511 high = limit & 3;
4512
4513 if (value < low || value > high)
4514 func (stream, "<illegal width %d>", base << value);
4515 else
4516 func (stream, "%d", base << value);
4517 }
4518 break;
4519 case 'R':
4520 if (given & (1 << 6))
4521 goto Q;
4522 /* FALLTHROUGH */
4523 case 'D':
4524 func (stream, "d%ld", value);
4525 break;
4526 case 'Q':
4527 Q:
4528 if (value & 1)
4529 func (stream, "<illegal reg q%ld.5>", value >> 1);
4530 else
4531 func (stream, "q%ld", value >> 1);
4532 break;
43e65147 4533
16980d0b
JB		 4534 case '`':
4535 c++;
4536 if (value == 0)
4537 func (stream, "%c", *c);
4538 break;
4539 case '\'':
4540 c++;
4541 if (value == ((1ul << width) - 1))
4542 func (stream, "%c", *c);
4543 break;
4544 case '?':
fe56b6ce 4545 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 4546 c += 1 << width;
4547 break;
4548 default:
4549 abort ();
4550 }
4551 break;
4552
4553 default:
4554 abort ();
4555 }
4556 }
4557 }
4558 else
4559 func (stream, "%c", *c);
4560 }
05413229
NC		 4561
4562 if (value_in_comment > 32 || value_in_comment < -16)
4563 func (stream, "\t; 0x%lx", value_in_comment);
4564
e2efe87d
MGD		 4565 if (is_unpredictable)
4566 func (stream, UNPREDICTABLE_INSTRUCTION);
4567
16980d0b
JB		 4568 return TRUE;
4569 }
4570 }
4571 return FALSE;
4572}
4573
90ec0d68
MGD		 4574/* Return the name of a v7A special register. */
4575
43e65147 4576static const char *
90ec0d68
MGD		 4577banked_regname (unsigned reg)
4578{
4579 switch (reg)
4580 {
4581 case 15: return "CPSR";
43e65147 4582 case 32: return "R8_usr";
90ec0d68
MGD		 4583 case 33: return "R9_usr";
4584 case 34: return "R10_usr";
4585 case 35: return "R11_usr";
4586 case 36: return "R12_usr";
4587 case 37: return "SP_usr";
4588 case 38: return "LR_usr";
43e65147 4589 case 40: return "R8_fiq";
90ec0d68
MGD		 4590 case 41: return "R9_fiq";
4591 case 42: return "R10_fiq";
4592 case 43: return "R11_fiq";
4593 case 44: return "R12_fiq";
4594 case 45: return "SP_fiq";
4595 case 46: return "LR_fiq";
4596 case 48: return "LR_irq";
4597 case 49: return "SP_irq";
4598 case 50: return "LR_svc";
4599 case 51: return "SP_svc";
4600 case 52: return "LR_abt";
4601 case 53: return "SP_abt";
4602 case 54: return "LR_und";
4603 case 55: return "SP_und";
4604 case 60: return "LR_mon";
4605 case 61: return "SP_mon";
4606 case 62: return "ELR_hyp";
4607 case 63: return "SP_hyp";
4608 case 79: return "SPSR";
4609 case 110: return "SPSR_fiq";
4610 case 112: return "SPSR_irq";
4611 case 114: return "SPSR_svc";
4612 case 116: return "SPSR_abt";
4613 case 118: return "SPSR_und";
4614 case 124: return "SPSR_mon";
4615 case 126: return "SPSR_hyp";
4616 default: return NULL;
4617 }
4618}
4619
e797f7e0
MGD		 4620/* Return the name of the DMB/DSB option. */
4621static const char *
4622data_barrier_option (unsigned option)
4623{
4624 switch (option & 0xf)
4625 {
4626 case 0xf: return "sy";
4627 case 0xe: return "st";
4628 case 0xd: return "ld";
4629 case 0xb: return "ish";
4630 case 0xa: return "ishst";
4631 case 0x9: return "ishld";
4632 case 0x7: return "un";
4633 case 0x6: return "unst";
4634 case 0x5: return "nshld";
4635 case 0x3: return "osh";
4636 case 0x2: return "oshst";
4637 case 0x1: return "oshld";
4638 default: return NULL;
4639 }
4640}
4641
4a5329c6
ZW		 4642/* Print one ARM instruction from PC on INFO->STREAM. */
4643
4644static void
4645print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 4646{
6b5d3a4d 4647 const struct opcode32 *insn;
6a51a8a8 4648 void *stream = info->stream;
6b5d3a4d 4649 fprintf_ftype func = info->fprintf_func;
b0e28b39 4650 struct arm_private_data *private_data = info->private_data;
252b5132 4651
16980d0b
JB		 4652 if (print_insn_coprocessor (pc, info, given, FALSE))
4653 return;
4654
4655 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 4656 return;
4657
252b5132
RH		 4658 for (insn = arm_opcodes; insn->assembler; insn++)
4659 {
0313a2b8
NC		 4660 if ((given & insn->mask) != insn->value)
4661 continue;
823d2571
TG		 4662
4663 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 4664 continue;
4665
4666 /* Special case: an instruction with all bits set in the condition field
4667 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
4668 or by the catchall at the end of the table. */
4669 if ((given & 0xF0000000) != 0xF0000000
4670 || (insn->mask & 0xF0000000) == 0xF0000000
4671 || (insn->mask == 0 && insn->value == 0))
252b5132 4672 {
ff4a8d2b
NC		 4673 unsigned long u_reg = 16;
4674 unsigned long U_reg = 16;
ab8e2090 4675 bfd_boolean is_unpredictable = FALSE;
05413229 4676 signed long value_in_comment = 0;
6b5d3a4d 4677 const char *c;
b34976b6 4678
252b5132
RH		 4679 for (c = insn->assembler; *c; c++)
4680 {
4681 if (*c == '%')
4682 {
c1e26897
NC		 4683 bfd_boolean allow_unpredictable = FALSE;
4684
252b5132
RH		 4685 switch (*++c)
4686 {
4687 case '%':
4688 func (stream, "%%");
4689 break;
4690
4691 case 'a':
05413229 4692 value_in_comment = print_arm_address (pc, info, given);
62b3e311 4693 break;
252b5132 4694
62b3e311
PB		 4695 case 'P':
4696 /* Set P address bit and use normal address
4697 printing routine. */
c1e26897 4698 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 4699 break;
4700
c1e26897
NC		 4701 case 'S':
4702 allow_unpredictable = TRUE;
1a0670f3 4703 /* Fall through. */
252b5132
RH		 4704 case 's':
4705 if ((given & 0x004f0000) == 0x004f0000)
4706 {
58efb6c0 4707 /* PC relative with immediate offset. */
f8b960bc 4708 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 4709
aefd8a40
NC		 4710 if (PRE_BIT_SET)
4711 {
26d97720
NS		 4712 /* Elide positive zero offset. */
4713 if (offset || NEGATIVE_BIT_SET)
4714 func (stream, "[pc, #%s%d]\t; ",
d908c8af 4715 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 4716 else
26d97720
NS		 4717 func (stream, "[pc]\t; ");
4718 if (NEGATIVE_BIT_SET)
4719 offset = -offset;
aefd8a40
NC		 4720 info->print_address_func (offset + pc + 8, info);
4721 }
4722 else
4723 {
26d97720
NS		 4724 /* Always show the offset. */
4725 func (stream, "[pc], #%s%d",
d908c8af 4726 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 4727 if (! allow_unpredictable)
4728 is_unpredictable = TRUE;
aefd8a40 4729 }
252b5132
RH		 4730 }
4731 else
4732 {
fe56b6ce
NC		 4733 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
4734
b34976b6 4735 func (stream, "[%s",
252b5132 4736 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 4737
c1e26897 4738 if (PRE_BIT_SET)
252b5132 4739 {
c1e26897 4740 if (IMMEDIATE_BIT_SET)
252b5132 4741 {
26d97720
NS		 4742 /* Elide offset for non-writeback
4743 positive zero. */
4744 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
4745 || offset)
4746 func (stream, ", #%s%d",
4747 NEGATIVE_BIT_SET ? "-" : "", offset);
4748
4749 if (NEGATIVE_BIT_SET)
4750 offset = -offset;
945ee430 4751
fe56b6ce 4752 value_in_comment = offset;
252b5132 4753 }
945ee430 4754 else
ff4a8d2b
NC		 4755 {
4756 /* Register Offset or Register Pre-Indexed. */
4757 func (stream, ", %s%s",
4758 NEGATIVE_BIT_SET ? "-" : "",
4759 arm_regnames[given & 0xf]);
4760
4761 /* Writing back to the register that is the source/
4762 destination of the load/store is unpredictable. */
4763 if (! allow_unpredictable
4764 && WRITEBACK_BIT_SET
4765 && ((given & 0xf) == ((given >> 12) & 0xf)))
4766 is_unpredictable = TRUE;
4767 }
252b5132 4768
b34976b6 4769 func (stream, "]%s",
c1e26897 4770 WRITEBACK_BIT_SET ? "!" : "");
252b5132 4771 }
945ee430 4772 else
252b5132 4773 {
c1e26897 4774 if (IMMEDIATE_BIT_SET)
252b5132 4775 {
945ee430 4776 /* Immediate Post-indexed. */
aefd8a40 4777 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 4778 func (stream, "], #%s%d",
4779 NEGATIVE_BIT_SET ? "-" : "", offset);
4780 if (NEGATIVE_BIT_SET)
4781 offset = -offset;
fe56b6ce 4782 value_in_comment = offset;
252b5132 4783 }
945ee430 4784 else
ff4a8d2b
NC		 4785 {
4786 /* Register Post-indexed. */
4787 func (stream, "], %s%s",
4788 NEGATIVE_BIT_SET ? "-" : "",
4789 arm_regnames[given & 0xf]);
4790
4791 /* Writing back to the register that is the source/
4792 destination of the load/store is unpredictable. */
4793 if (! allow_unpredictable
4794 && (given & 0xf) == ((given >> 12) & 0xf))
4795 is_unpredictable = TRUE;
4796 }
c1e26897 4797
07a28fab
NC		 4798 if (! allow_unpredictable)
4799 {
4800 /* Writeback is automatically implied by post- addressing.
4801 Setting the W bit is unnecessary and ARM specify it as
4802 being unpredictable. */
4803 if (WRITEBACK_BIT_SET
4804 /* Specifying the PC register as the post-indexed
4805 registers is also unpredictable. */
ab8e2090
NC		 4806 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
4807 is_unpredictable = TRUE;
07a28fab 4808 }
252b5132
RH		 4809 }
4810 }
4811 break;
b34976b6 4812
252b5132 4813 case 'b':
6b5d3a4d 4814 {
f8b960bc 4815 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
05413229 4816 info->print_address_func (disp * 4 + pc + 8, info);
6b5d3a4d 4817 }
252b5132
RH		 4818 break;
4819
4820 case 'c':
c22aaad1
PB		 4821 if (((given >> 28) & 0xf) != 0xe)
4822 func (stream, "%s",
4823 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 4824 break;
4825
4826 case 'm':
4827 {
4828 int started = 0;
4829 int reg;
4830
4831 func (stream, "{");
4832 for (reg = 0; reg < 16; reg++)
4833 if ((given & (1 << reg)) != 0)
4834 {
4835 if (started)
4836 func (stream, ", ");
4837 started = 1;
4838 func (stream, "%s", arm_regnames[reg]);
4839 }
4840 func (stream, "}");
ab8e2090
NC		 4841 if (! started)
4842 is_unpredictable = TRUE;
252b5132
RH		 4843 }
4844 break;
4845
37b37b2d 4846 case 'q':
78c66db8 4847 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 4848 break;
4849
252b5132
RH		 4850 case 'o':
4851 if ((given & 0x02000000) != 0)
4852 {
a415b1cd
JB		 4853 unsigned int rotate = (given & 0xf00) >> 7;
4854 unsigned int immed = (given & 0xff);
4855 unsigned int a, i;
4856
4857 a = (((immed << (32 - rotate))
4858 | (immed >> rotate)) & 0xffffffff);
4859 /* If there is another encoding with smaller rotate,
4860 the rotate should be specified directly. */
4861 for (i = 0; i < 32; i += 2)
4862 if ((a << i | a >> (32 - i)) <= 0xff)
4863 break;
4864
4865 if (i != rotate)
4866 func (stream, "#%d, %d", immed, rotate);
4867 else
4868 func (stream, "#%d", a);
4869 value_in_comment = a;
252b5132
RH		 4870 }
4871 else
78c66db8 4872 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 4873 break;
4874
4875 case 'p':
4876 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 4877 {
823d2571
TG		 4878 arm_feature_set arm_ext_v6 =
4879 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
4880
aefd8a40
NC		 4881 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
4882 mechanism for setting PSR flag bits. They are
4883 obsolete in V6 onwards. */
823d2571
TG		 4884 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
4885 arm_ext_v6))
aefd8a40 4886 func (stream, "p");
4ab90a7a
AV		 4887 else
4888 is_unpredictable = TRUE;
aefd8a40 4889 }
252b5132
RH		 4890 break;
4891
4892 case 't':
4893 if ((given & 0x01200000) == 0x00200000)
4894 func (stream, "t");
4895 break;
4896
252b5132 4897 case 'A':
05413229
NC		 4898 {
4899 int offset = given & 0xff;
f02232aa 4900
05413229 4901 value_in_comment = offset * 4;
c1e26897 4902 if (NEGATIVE_BIT_SET)
05413229 4903 value_in_comment = - value_in_comment;
f02232aa 4904
05413229 4905 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 4906
c1e26897 4907 if (PRE_BIT_SET)
05413229
NC		 4908 {
4909 if (offset)
fe56b6ce 4910 func (stream, ", #%d]%s",
d908c8af 4911 (int) value_in_comment,
c1e26897 4912 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 4913 else
4914 func (stream, "]");
4915 }
4916 else
4917 {
4918 func (stream, "]");
f02232aa 4919
c1e26897 4920 if (WRITEBACK_BIT_SET)
05413229
NC		 4921 {
4922 if (offset)
d908c8af 4923 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 4924 }
4925 else
fe56b6ce 4926 {
d908c8af 4927 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 4928 value_in_comment = offset;
4929 }
05413229
NC		 4930 }
4931 }
252b5132
RH		 4932 break;
4933
077b8428
NC		 4934 case 'B':
4935 /* Print ARM V5 BLX(1) address: pc+25 bits. */
4936 {
4937 bfd_vma address;
4938 bfd_vma offset = 0;
b34976b6 4939
c1e26897 4940 if (! NEGATIVE_BIT_SET)
077b8428
NC		 4941 /* Is signed, hi bits should be ones. */
4942 offset = (-1) ^ 0x00ffffff;
4943
4944 /* Offset is (SignExtend(offset field)<<2). */
4945 offset += given & 0x00ffffff;
4946 offset <<= 2;
4947 address = offset + pc + 8;
b34976b6 4948
8f06b2d8
PB		 4949 if (given & 0x01000000)
4950 /* H bit allows addressing to 2-byte boundaries. */
4951 address += 2;
b1ee46c5 4952
8f06b2d8 4953 info->print_address_func (address, info);
b1ee46c5 4954 }
b1ee46c5
AH		 4955 break;
4956
252b5132 4957 case 'C':
90ec0d68
MGD		 4958 if ((given & 0x02000200) == 0x200)
4959 {
4960 const char * name;
4961 unsigned sysm = (given & 0x004f0000) >> 16;
4962
4963 sysm |= (given & 0x300) >> 4;
4964 name = banked_regname (sysm);
4965
4966 if (name != NULL)
4967 func (stream, "%s", name);
4968 else
d908c8af 4969 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 4970 }
4971 else
4972 {
43e65147 4973 func (stream, "%cPSR_",
90ec0d68
MGD		 4974 (given & 0x00400000) ? 'S' : 'C');
4975 if (given & 0x80000)
4976 func (stream, "f");
4977 if (given & 0x40000)
4978 func (stream, "s");
4979 if (given & 0x20000)
4980 func (stream, "x");
4981 if (given & 0x10000)
4982 func (stream, "c");
4983 }
252b5132
RH		 4984 break;
4985
62b3e311 4986 case 'U':
43e65147 4987 if ((given & 0xf0) == 0x60)
62b3e311 4988 {
52e7f43d
RE		 4989 switch (given & 0xf)
4990 {
4991 case 0xf: func (stream, "sy"); break;
4992 default:
4993 func (stream, "#%d", (int) given & 0xf);
4994 break;
4995 }
43e65147
L		 4996 }
4997 else
52e7f43d 4998 {
e797f7e0
MGD		 4999 const char * opt = data_barrier_option (given & 0xf);
5000 if (opt != NULL)
5001 func (stream, "%s", opt);
5002 else
52e7f43d 5003 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 5004 }
5005 break;
5006
b34976b6 5007 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 5008 case '5': case '6': case '7': case '8': case '9':
5009 {
16980d0b
JB		 5010 int width;
5011 unsigned long value;
252b5132 5012
16980d0b 5013 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 5014
252b5132
RH		 5015 switch (*c)
5016 {
ab8e2090
NC		 5017 case 'R':
5018 if (value == 15)
5019 is_unpredictable = TRUE;
5020 /* Fall through. */
16980d0b 5021 case 'r':
9eb6c0f1
MGD		 5022 case 'T':
5023 /* We want register + 1 when decoding T. */
5024 if (*c == 'T')
5025 ++value;
5026
ff4a8d2b
NC		 5027 if (c[1] == 'u')
5028 {
5029 /* Eat the 'u' character. */
5030 ++ c;
5031
5032 if (u_reg == value)
5033 is_unpredictable = TRUE;
5034 u_reg = value;
5035 }
5036 if (c[1] == 'U')
5037 {
5038 /* Eat the 'U' character. */
5039 ++ c;
5040
5041 if (U_reg == value)
5042 is_unpredictable = TRUE;
5043 U_reg = value;
5044 }
16980d0b
JB		 5045 func (stream, "%s", arm_regnames[value]);
5046 break;
5047 case 'd':
5048 func (stream, "%ld", value);
05413229 5049 value_in_comment = value;
16980d0b
JB		 5050 break;
5051 case 'b':
5052 func (stream, "%ld", value * 8);
05413229 5053 value_in_comment = value * 8;
16980d0b
JB		 5054 break;
5055 case 'W':
5056 func (stream, "%ld", value + 1);
05413229 5057 value_in_comment = value + 1;
16980d0b
JB		 5058 break;
5059 case 'x':
5060 func (stream, "0x%08lx", value);
5061
5062 /* Some SWI instructions have special
5063 meanings. */
5064 if ((given & 0x0fffffff) == 0x0FF00000)
5065 func (stream, "\t; IMB");
5066 else if ((given & 0x0fffffff) == 0x0FF00001)
5067 func (stream, "\t; IMBRange");
5068 break;
5069 case 'X':
5070 func (stream, "%01lx", value & 0xf);
05413229 5071 value_in_comment = value;
252b5132
RH		 5072 break;
5073 case '`':
5074 c++;
16980d0b 5075 if (value == 0)
252b5132
RH		 5076 func (stream, "%c", *c);
5077 break;
5078 case '\'':
5079 c++;
16980d0b 5080 if (value == ((1ul << width) - 1))
252b5132
RH		 5081 func (stream, "%c", *c);
5082 break;
5083 case '?':
fe56b6ce 5084 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 5085 c += 1 << width;
252b5132
RH		 5086 break;
5087 default:
5088 abort ();
5089 }
5090 break;
5091
0dd132b6
NC		 5092 case 'e':
5093 {
5094 int imm;
5095
5096 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
5097 func (stream, "%d", imm);
fe56b6ce 5098 value_in_comment = imm;
0dd132b6
NC		 5099 }
5100 break;
5101
0a003adc
ZW		 5102 case 'E':
5103 /* LSB and WIDTH fields of BFI or BFC. The machine-
5104 language instruction encodes LSB and MSB. */
5105 {
5106 long msb = (given & 0x001f0000) >> 16;
5107 long lsb = (given & 0x00000f80) >> 7;
91d6fa6a 5108 long w = msb - lsb + 1;
fe56b6ce 5109
91d6fa6a
NC		 5110 if (w > 0)
5111 func (stream, "#%lu, #%lu", lsb, w);
0a003adc
ZW		 5112 else
5113 func (stream, "(invalid: %lu:%lu)", lsb, msb);
5114 }
5115 break;
5116
90ec0d68
MGD		 5117 case 'R':
5118 /* Get the PSR/banked register name. */
5119 {
5120 const char * name;
5121 unsigned sysm = (given & 0x004f0000) >> 16;
5122
5123 sysm |= (given & 0x300) >> 4;
5124 name = banked_regname (sysm);
5125
5126 if (name != NULL)
5127 func (stream, "%s", name);
5128 else
d908c8af 5129 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 5130 }
5131 break;
5132
0a003adc
ZW		 5133 case 'V':
5134 /* 16-bit unsigned immediate from a MOVT or MOVW
5135 instruction, encoded in bits 0:11 and 15:19. */
5136 {
5137 long hi = (given & 0x000f0000) >> 4;
5138 long lo = (given & 0x00000fff);
5139 long imm16 = hi | lo;
fe56b6ce
NC		 5140
5141 func (stream, "#%lu", imm16);
5142 value_in_comment = imm16;
0a003adc
ZW		 5143 }
5144 break;
5145
252b5132
RH		 5146 default:
5147 abort ();
5148 }
5149 }
5150 }
5151 else
5152 func (stream, "%c", *c);
5153 }
05413229
NC		 5154
5155 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 5156 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 5157
5158 if (is_unpredictable)
5159 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 5160
4a5329c6 5161 return;
252b5132
RH		 5162 }
5163 }
5164 abort ();
5165}
5166
4a5329c6 5167/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 5168
4a5329c6
ZW		 5169static void
5170print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 5171{
6b5d3a4d 5172 const struct opcode16 *insn;
6a51a8a8
AM		 5173 void *stream = info->stream;
5174 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 5175
5176 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 5177 if ((given & insn->mask) == insn->value)
5178 {
05413229 5179 signed long value_in_comment = 0;
6b5d3a4d 5180 const char *c = insn->assembler;
05413229 5181
c19d1205
ZW		 5182 for (; *c; c++)
5183 {
5184 int domaskpc = 0;
5185 int domasklr = 0;
5186
5187 if (*c != '%')
5188 {
5189 func (stream, "%c", *c);
5190 continue;
5191 }
252b5132 5192
c19d1205
ZW		 5193 switch (*++c)
5194 {
5195 case '%':
5196 func (stream, "%%");
5197 break;
b34976b6 5198
c22aaad1
PB		 5199 case 'c':
5200 if (ifthen_state)
5201 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5202 break;
5203
5204 case 'C':
5205 if (ifthen_state)
5206 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5207 else
5208 func (stream, "s");
5209 break;
5210
5211 case 'I':
5212 {
5213 unsigned int tmp;
5214
5215 ifthen_next_state = given & 0xff;
5216 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
5217 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
5218 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
5219 }
5220 break;
5221
5222 case 'x':
5223 if (ifthen_next_state)
5224 func (stream, "\t; unpredictable branch in IT block\n");
5225 break;
5226
5227 case 'X':
5228 if (ifthen_state)
5229 func (stream, "\t; unpredictable <IT:%s>",
5230 arm_conditional[IFTHEN_COND]);
5231 break;
5232
c19d1205
ZW		 5233 case 'S':
5234 {
5235 long reg;
5236
5237 reg = (given >> 3) & 0x7;
5238 if (given & (1 << 6))
5239 reg += 8;
4f3c3dbb 5240
c19d1205
ZW		 5241 func (stream, "%s", arm_regnames[reg]);
5242 }
5243 break;
baf0cc5e 5244
c19d1205 5245 case 'D':
4f3c3dbb 5246 {
c19d1205
ZW		 5247 long reg;
5248
5249 reg = given & 0x7;
5250 if (given & (1 << 7))
5251 reg += 8;
5252
5253 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 5254 }
c19d1205
ZW		 5255 break;
5256
5257 case 'N':
5258 if (given & (1 << 8))
5259 domasklr = 1;
5260 /* Fall through. */
5261 case 'O':
5262 if (*c == 'O' && (given & (1 << 8)))
5263 domaskpc = 1;
5264 /* Fall through. */
5265 case 'M':
5266 {
5267 int started = 0;
5268 int reg;
5269
5270 func (stream, "{");
5271
5272 /* It would be nice if we could spot
5273 ranges, and generate the rS-rE format: */
5274 for (reg = 0; (reg < 8); reg++)
5275 if ((given & (1 << reg)) != 0)
5276 {
5277 if (started)
5278 func (stream, ", ");
5279 started = 1;
5280 func (stream, "%s", arm_regnames[reg]);
5281 }
5282
5283 if (domasklr)
5284 {
5285 if (started)
5286 func (stream, ", ");
5287 started = 1;
d908c8af 5288 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 5289 }
5290
5291 if (domaskpc)
5292 {
5293 if (started)
5294 func (stream, ", ");
d908c8af 5295 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 5296 }
5297
5298 func (stream, "}");
5299 }
5300 break;
5301
4547cb56
NC		 5302 case 'W':
5303 /* Print writeback indicator for a LDMIA. We are doing a
5304 writeback if the base register is not in the register
5305 mask. */
5306 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
5307 func (stream, "!");
5308 break;
5309
c19d1205
ZW		 5310 case 'b':
5311 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
5312 {
5313 bfd_vma address = (pc + 4
5314 + ((given & 0x00f8) >> 2)
5315 + ((given & 0x0200) >> 3));
5316 info->print_address_func (address, info);
5317 }
5318 break;
5319
5320 case 's':
5321 /* Right shift immediate -- bits 6..10; 1-31 print
5322 as themselves, 0 prints as 32. */
5323 {
5324 long imm = (given & 0x07c0) >> 6;
5325 if (imm == 0)
5326 imm = 32;
0fd3a477 5327 func (stream, "#%ld", imm);
c19d1205
ZW		 5328 }
5329 break;
5330
5331 case '0': case '1': case '2': case '3': case '4':
5332 case '5': case '6': case '7': case '8': case '9':
5333 {
5334 int bitstart = *c++ - '0';
5335 int bitend = 0;
5336
5337 while (*c >= '0' && *c <= '9')
5338 bitstart = (bitstart * 10) + *c++ - '0';
5339
5340 switch (*c)
5341 {
5342 case '-':
5343 {
f8b960bc 5344 bfd_vma reg;
c19d1205
ZW		 5345
5346 c++;
5347 while (*c >= '0' && *c <= '9')
5348 bitend = (bitend * 10) + *c++ - '0';
5349 if (!bitend)
5350 abort ();
5351 reg = given >> bitstart;
5352 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 5353
c19d1205
ZW		 5354 switch (*c)
5355 {
5356 case 'r':
5357 func (stream, "%s", arm_regnames[reg]);
5358 break;
5359
5360 case 'd':
d908c8af 5361 func (stream, "%ld", (long) reg);
05413229 5362 value_in_comment = reg;
c19d1205
ZW		 5363 break;
5364
5365 case 'H':
d908c8af 5366 func (stream, "%ld", (long) (reg << 1));
05413229 5367 value_in_comment = reg << 1;
c19d1205
ZW		 5368 break;
5369
5370 case 'W':
d908c8af 5371 func (stream, "%ld", (long) (reg << 2));
05413229 5372 value_in_comment = reg << 2;
c19d1205
ZW		 5373 break;
5374
5375 case 'a':
5376 /* PC-relative address -- the bottom two
5377 bits of the address are dropped
5378 before the calculation. */
5379 info->print_address_func
5380 (((pc + 4) & ~3) + (reg << 2), info);
05413229 5381 value_in_comment = 0;
c19d1205
ZW		 5382 break;
5383
5384 case 'x':
d908c8af 5385 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 5386 break;
5387
c19d1205
ZW		 5388 case 'B':
5389 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6b5d3a4d 5390 info->print_address_func (reg * 2 + pc + 4, info);
05413229 5391 value_in_comment = 0;
c19d1205
ZW		 5392 break;
5393
5394 case 'c':
c22aaad1 5395 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 5396 break;
5397
5398 default:
5399 abort ();
5400 }
5401 }
5402 break;
5403
5404 case '\'':
5405 c++;
5406 if ((given & (1 << bitstart)) != 0)
5407 func (stream, "%c", *c);
5408 break;
5409
5410 case '?':
5411 ++c;
5412 if ((given & (1 << bitstart)) != 0)
5413 func (stream, "%c", *c++);
5414 else
5415 func (stream, "%c", *++c);
5416 break;
5417
5418 default:
5419 abort ();
5420 }
5421 }
5422 break;
5423
5424 default:
5425 abort ();
5426 }
5427 }
05413229
NC		 5428
5429 if (value_in_comment > 32 || value_in_comment < -16)
5430 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 5431 return;
c19d1205
ZW		 5432 }
5433
5434 /* No match. */
5435 abort ();
5436}
5437
62b3e311 5438/* Return the name of an V7M special register. */
fe56b6ce 5439
62b3e311
PB		 5440static const char *
5441psr_name (int regno)
5442{
5443 switch (regno)
5444 {
1a336194
TP		 5445 case 0x0: return "APSR";
5446 case 0x1: return "IAPSR";
5447 case 0x2: return "EAPSR";
5448 case 0x3: return "PSR";
5449 case 0x5: return "IPSR";
5450 case 0x6: return "EPSR";
5451 case 0x7: return "IEPSR";
5452 case 0x8: return "MSP";
5453 case 0x9: return "PSP";
5454 case 0xa: return "MSPLIM";
5455 case 0xb: return "PSPLIM";
5456 case 0x10: return "PRIMASK";
5457 case 0x11: return "BASEPRI";
5458 case 0x12: return "BASEPRI_MAX";
5459 case 0x13: return "FAULTMASK";
5460 case 0x14: return "CONTROL";
16a1fa25
TP		 5461 case 0x88: return "MSP_NS";
5462 case 0x89: return "PSP_NS";
1a336194
TP		 5463 case 0x8a: return "MSPLIM_NS";
5464 case 0x8b: return "PSPLIM_NS";
5465 case 0x90: return "PRIMASK_NS";
5466 case 0x91: return "BASEPRI_NS";
5467 case 0x93: return "FAULTMASK_NS";
5468 case 0x94: return "CONTROL_NS";
5469 case 0x98: return "SP_NS";
62b3e311
PB		 5470 default: return "<unknown>";
5471 }
5472}
5473
4a5329c6
ZW		 5474/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
5475
5476static void
5477print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 5478{
6b5d3a4d 5479 const struct opcode32 *insn;
c19d1205
ZW		 5480 void *stream = info->stream;
5481 fprintf_ftype func = info->fprintf_func;
5482
16980d0b
JB		 5483 if (print_insn_coprocessor (pc, info, given, TRUE))
5484 return;
5485
5486 if (print_insn_neon (info, given, TRUE))
8f06b2d8
PB		 5487 return;
5488
c19d1205
ZW		 5489 for (insn = thumb32_opcodes; insn->assembler; insn++)
5490 if ((given & insn->mask) == insn->value)
5491 {
ff4a8d2b 5492 bfd_boolean is_unpredictable = FALSE;
05413229 5493 signed long value_in_comment = 0;
6b5d3a4d 5494 const char *c = insn->assembler;
05413229 5495
c19d1205
ZW		 5496 for (; *c; c++)
5497 {
5498 if (*c != '%')
5499 {
5500 func (stream, "%c", *c);
5501 continue;
5502 }
5503
5504 switch (*++c)
5505 {
5506 case '%':
5507 func (stream, "%%");
5508 break;
5509
c22aaad1
PB		 5510 case 'c':
5511 if (ifthen_state)
5512 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5513 break;
5514
5515 case 'x':
5516 if (ifthen_next_state)
5517 func (stream, "\t; unpredictable branch in IT block\n");
5518 break;
5519
5520 case 'X':
5521 if (ifthen_state)
5522 func (stream, "\t; unpredictable <IT:%s>",
5523 arm_conditional[IFTHEN_COND]);
5524 break;
5525
c19d1205
ZW		 5526 case 'I':
5527 {
5528 unsigned int imm12 = 0;
fe56b6ce 5529
c19d1205
ZW		 5530 imm12 |= (given & 0x000000ffu);
5531 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 5532 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 5533 func (stream, "#%u", imm12);
5534 value_in_comment = imm12;
c19d1205
ZW		 5535 }
5536 break;
5537
5538 case 'M':
5539 {
5540 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 5541
c19d1205
ZW		 5542 bits |= (given & 0x000000ffu);
5543 bits |= (given & 0x00007000u) >> 4;
5544 bits |= (given & 0x04000000u) >> 15;
5545 imm8 = (bits & 0x0ff);
5546 mod = (bits & 0xf00) >> 8;
5547 switch (mod)
5548 {
5549 case 0: imm = imm8; break;
c1e26897
NC		 5550 case 1: imm = ((imm8 << 16) | imm8); break;
5551 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
5552 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 5553 default:
5554 mod = (bits & 0xf80) >> 7;
5555 imm8 = (bits & 0x07f) | 0x80;
5556 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
5557 }
fe56b6ce
NC		 5558 func (stream, "#%u", imm);
5559 value_in_comment = imm;
c19d1205
ZW		 5560 }
5561 break;
43e65147 5562
c19d1205
ZW		 5563 case 'J':
5564 {
5565 unsigned int imm = 0;
fe56b6ce 5566
c19d1205
ZW		 5567 imm |= (given & 0x000000ffu);
5568 imm |= (given & 0x00007000u) >> 4;
5569 imm |= (given & 0x04000000u) >> 15;
5570 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 5571 func (stream, "#%u", imm);
5572 value_in_comment = imm;
c19d1205
ZW		 5573 }
5574 break;
5575
5576 case 'K':
5577 {
5578 unsigned int imm = 0;
fe56b6ce 5579
c19d1205
ZW		 5580 imm |= (given & 0x000f0000u) >> 16;
5581 imm |= (given & 0x00000ff0u) >> 0;
5582 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 5583 func (stream, "#%u", imm);
5584 value_in_comment = imm;
c19d1205
ZW		 5585 }
5586 break;
5587
74db7efb
NC		 5588 case 'H':
5589 {
5590 unsigned int imm = 0;
5591
5592 imm |= (given & 0x000f0000u) >> 4;
5593 imm |= (given & 0x00000fffu) >> 0;
5594 func (stream, "#%u", imm);
5595 value_in_comment = imm;
5596 }
5597 break;
5598
90ec0d68
MGD		 5599 case 'V':
5600 {
5601 unsigned int imm = 0;
5602
5603 imm |= (given & 0x00000fffu);
5604 imm |= (given & 0x000f0000u) >> 4;
5605 func (stream, "#%u", imm);
5606 value_in_comment = imm;
5607 }
5608 break;
5609
c19d1205
ZW		 5610 case 'S':
5611 {
5612 unsigned int reg = (given & 0x0000000fu);
5613 unsigned int stp = (given & 0x00000030u) >> 4;
5614 unsigned int imm = 0;
5615 imm |= (given & 0x000000c0u) >> 6;
5616 imm |= (given & 0x00007000u) >> 10;
5617
5618 func (stream, "%s", arm_regnames[reg]);
5619 switch (stp)
5620 {
5621 case 0:
5622 if (imm > 0)
5623 func (stream, ", lsl #%u", imm);
5624 break;
5625
5626 case 1:
5627 if (imm == 0)
5628 imm = 32;
5629 func (stream, ", lsr #%u", imm);
5630 break;
5631
5632 case 2:
5633 if (imm == 0)
5634 imm = 32;
5635 func (stream, ", asr #%u", imm);
5636 break;
5637
5638 case 3:
5639 if (imm == 0)
5640 func (stream, ", rrx");
5641 else
5642 func (stream, ", ror #%u", imm);
5643 }
5644 }
5645 break;
5646
5647 case 'a':
5648 {
5649 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 5650 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 5651 unsigned int op = (given & 0x00000f00) >> 8;
5652 unsigned int i12 = (given & 0x00000fff);
5653 unsigned int i8 = (given & 0x000000ff);
5654 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 5655 bfd_vma offset = 0;
c19d1205
ZW		 5656
5657 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 5658 if (U) /* 12-bit positive immediate offset. */
5659 {
5660 offset = i12;
5661 if (Rn != 15)
5662 value_in_comment = offset;
5663 }
5664 else if (Rn == 15) /* 12-bit negative immediate offset. */
5665 offset = - (int) i12;
5666 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 5667 {
5668 unsigned int Rm = (i8 & 0x0f);
5669 unsigned int sh = (i8 & 0x30) >> 4;
05413229 5670
c19d1205
ZW		 5671 func (stream, ", %s", arm_regnames[Rm]);
5672 if (sh)
5673 func (stream, ", lsl #%u", sh);
5674 func (stream, "]");
5675 break;
5676 }
5677 else switch (op)
5678 {
05413229 5679 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 5680 offset = i8;
5681 break;
5682
05413229 5683 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 5684 offset = -i8;
5685 break;
5686
05413229 5687 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 5688 offset = i8;
5689 writeback = TRUE;
5690 break;
5691
05413229 5692 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 5693 offset = -i8;
5694 writeback = TRUE;
5695 break;
5696
05413229 5697 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 5698 offset = i8;
5699 postind = TRUE;
5700 break;
5701
05413229 5702 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 5703 offset = -i8;
5704 postind = TRUE;
5705 break;
5706
5707 default:
5708 func (stream, ", <undefined>]");
5709 goto skip;
5710 }
5711
5712 if (postind)
d908c8af 5713 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 5714 else
5715 {
5716 if (offset)
d908c8af 5717 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 5718 func (stream, writeback ? "]!" : "]");
5719 }
5720
5721 if (Rn == 15)
5722 {
5723 func (stream, "\t; ");
5724 info->print_address_func (((pc + 4) & ~3) + offset, info);
5725 }
5726 }
5727 skip:
5728 break;
5729
5730 case 'A':
5731 {
c1e26897
NC		 5732 unsigned int U = ! NEGATIVE_BIT_SET;
5733 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 5734 unsigned int Rn = (given & 0x000f0000) >> 16;
5735 unsigned int off = (given & 0x000000ff);
5736
5737 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 5738
5739 if (PRE_BIT_SET)
c19d1205
ZW		 5740 {
5741 if (off || !U)
05413229
NC		 5742 {
5743 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
fe50e98c 5744 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 5745 }
c19d1205
ZW		 5746 func (stream, "]");
5747 if (W)
5748 func (stream, "!");
5749 }
5750 else
5751 {
5752 func (stream, "], ");
5753 if (W)
05413229
NC		 5754 {
5755 func (stream, "#%c%u", U ? '+' : '-', off * 4);
fe50e98c 5756 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 5757 }
c19d1205 5758 else
fe56b6ce
NC		 5759 {
5760 func (stream, "{%u}", off);
5761 value_in_comment = off;
5762 }
c19d1205
ZW		 5763 }
5764 }
5765 break;
5766
5767 case 'w':
5768 {
5769 unsigned int Sbit = (given & 0x01000000) >> 24;
5770 unsigned int type = (given & 0x00600000) >> 21;
05413229 5771
c19d1205
ZW		 5772 switch (type)
5773 {
5774 case 0: func (stream, Sbit ? "sb" : "b"); break;
5775 case 1: func (stream, Sbit ? "sh" : "h"); break;
5776 case 2:
5777 if (Sbit)
5778 func (stream, "??");
5779 break;
5780 case 3:
5781 func (stream, "??");
5782 break;
5783 }
5784 }
5785 break;
5786
5787 case 'm':
5788 {
5789 int started = 0;
5790 int reg;
5791
5792 func (stream, "{");
5793 for (reg = 0; reg < 16; reg++)
5794 if ((given & (1 << reg)) != 0)
5795 {
5796 if (started)
5797 func (stream, ", ");
5798 started = 1;
5799 func (stream, "%s", arm_regnames[reg]);
5800 }
5801 func (stream, "}");
5802 }
5803 break;
5804
5805 case 'E':
5806 {
5807 unsigned int msb = (given & 0x0000001f);
5808 unsigned int lsb = 0;
fe56b6ce 5809
c19d1205
ZW		 5810 lsb |= (given & 0x000000c0u) >> 6;
5811 lsb |= (given & 0x00007000u) >> 10;
5812 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
5813 }
5814 break;
5815
5816 case 'F':
5817 {
5818 unsigned int width = (given & 0x0000001f) + 1;
5819 unsigned int lsb = 0;
fe56b6ce 5820
c19d1205
ZW		 5821 lsb |= (given & 0x000000c0u) >> 6;
5822 lsb |= (given & 0x00007000u) >> 10;
5823 func (stream, "#%u, #%u", lsb, width);
5824 }
5825 break;
5826
5827 case 'b':
5828 {
5829 unsigned int S = (given & 0x04000000u) >> 26;
5830 unsigned int J1 = (given & 0x00002000u) >> 13;
5831 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 5832 bfd_vma offset = 0;
c19d1205
ZW		 5833
5834 offset |= !S << 20;
5835 offset |= J2 << 19;
5836 offset |= J1 << 18;
5837 offset |= (given & 0x003f0000) >> 4;
5838 offset |= (given & 0x000007ff) << 1;
5839 offset -= (1 << 20);
5840
5841 info->print_address_func (pc + 4 + offset, info);
5842 }
5843 break;
5844
5845 case 'B':
5846 {
5847 unsigned int S = (given & 0x04000000u) >> 26;
5848 unsigned int I1 = (given & 0x00002000u) >> 13;
5849 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 5850 bfd_vma offset = 0;
c19d1205
ZW		 5851
5852 offset |= !S << 24;
5853 offset |= !(I1 ^ S) << 23;
5854 offset |= !(I2 ^ S) << 22;
5855 offset |= (given & 0x03ff0000u) >> 4;
5856 offset |= (given & 0x000007ffu) << 1;
5857 offset -= (1 << 24);
36b0c57d 5858 offset += pc + 4;
c19d1205 5859
36b0c57d
PB		 5860 /* BLX target addresses are always word aligned. */
5861 if ((given & 0x00001000u) == 0)
5862 offset &= ~2u;
5863
5864 info->print_address_func (offset, info);
c19d1205
ZW		 5865 }
5866 break;
5867
5868 case 's':
5869 {
5870 unsigned int shift = 0;
fe56b6ce 5871
c19d1205
ZW		 5872 shift |= (given & 0x000000c0u) >> 6;
5873 shift |= (given & 0x00007000u) >> 10;
c1e26897 5874 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 5875 func (stream, ", asr #%u", shift);
5876 else if (shift)
5877 func (stream, ", lsl #%u", shift);
5878 /* else print nothing - lsl #0 */
5879 }
5880 break;
5881
5882 case 'R':
5883 {
5884 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 5885
c19d1205
ZW		 5886 if (rot)
5887 func (stream, ", ror #%u", rot * 8);
5888 }
5889 break;
5890
62b3e311 5891 case 'U':
43e65147 5892 if ((given & 0xf0) == 0x60)
62b3e311 5893 {
52e7f43d
RE		 5894 switch (given & 0xf)
5895 {
5896 case 0xf: func (stream, "sy"); break;
5897 default:
5898 func (stream, "#%d", (int) given & 0xf);
5899 break;
5900 }
62b3e311 5901 }
43e65147 5902 else
52e7f43d 5903 {
e797f7e0
MGD		 5904 const char * opt = data_barrier_option (given & 0xf);
5905 if (opt != NULL)
5906 func (stream, "%s", opt);
5907 else
5908 func (stream, "#%d", (int) given & 0xf);
52e7f43d 5909 }
62b3e311
PB		 5910 break;
5911
5912 case 'C':
5913 if ((given & 0xff) == 0)
5914 {
5915 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
5916 if (given & 0x800)
5917 func (stream, "f");
5918 if (given & 0x400)
5919 func (stream, "s");
5920 if (given & 0x200)
5921 func (stream, "x");
5922 if (given & 0x100)
5923 func (stream, "c");
5924 }
90ec0d68
MGD		 5925 else if ((given & 0x20) == 0x20)
5926 {
5927 char const* name;
5928 unsigned sysm = (given & 0xf00) >> 8;
5929
5930 sysm |= (given & 0x30);
5931 sysm |= (given & 0x00100000) >> 14;
5932 name = banked_regname (sysm);
43e65147 5933
90ec0d68
MGD		 5934 if (name != NULL)
5935 func (stream, "%s", name);
5936 else
d908c8af 5937 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 5938 }
62b3e311
PB		 5939 else
5940 {
d908c8af 5941 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 5942 }
5943 break;
5944
5945 case 'D':
90ec0d68
MGD		 5946 if (((given & 0xff) == 0)
5947 || ((given & 0x20) == 0x20))
5948 {
5949 char const* name;
5950 unsigned sm = (given & 0xf0000) >> 16;
5951
5952 sm |= (given & 0x30);
5953 sm |= (given & 0x00100000) >> 14;
5954 name = banked_regname (sm);
5955
5956 if (name != NULL)
5957 func (stream, "%s", name);
5958 else
d908c8af 5959 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 5960 }
62b3e311 5961 else
d908c8af 5962 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 5963 break;
5964
c19d1205
ZW		 5965 case '0': case '1': case '2': case '3': case '4':
5966 case '5': case '6': case '7': case '8': case '9':
5967 {
16980d0b
JB		 5968 int width;
5969 unsigned long val;
c19d1205 5970
16980d0b 5971 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 5972
c19d1205
ZW		 5973 switch (*c)
5974 {
05413229
NC		 5975 case 'd':
5976 func (stream, "%lu", val);
5977 value_in_comment = val;
5978 break;
ff4a8d2b 5979
f0fba320
RL		 5980 case 'D':
5981 func (stream, "%lu", val + 1);
5982 value_in_comment = val + 1;
5983 break;
5984
05413229
NC		 5985 case 'W':
5986 func (stream, "%lu", val * 4);
5987 value_in_comment = val * 4;
5988 break;
ff4a8d2b 5989
dd5181d5
KT		 5990 case 'S':
5991 if (val == 13)
5992 is_unpredictable = TRUE;
5993 /* Fall through. */
ff4a8d2b
NC		 5994 case 'R':
5995 if (val == 15)
5996 is_unpredictable = TRUE;
5997 /* Fall through. */
5998 case 'r':
5999 func (stream, "%s", arm_regnames[val]);
6000 break;
c19d1205
ZW		 6001
6002 case 'c':
c22aaad1 6003 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 6004 break;
6005
6006 case '\'':
c19d1205 6007 c++;
16980d0b
JB		 6008 if (val == ((1ul << width) - 1))
6009 func (stream, "%c", *c);
c19d1205 6010 break;
43e65147 6011
c19d1205 6012 case '`':
c19d1205 6013 c++;
16980d0b
JB		 6014 if (val == 0)
6015 func (stream, "%c", *c);
c19d1205
ZW		 6016 break;
6017
6018 case '?':
fe56b6ce 6019 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 6020 c += 1 << width;
c19d1205 6021 break;
43e65147 6022
0bb027fd
RR		 6023 case 'x':
6024 func (stream, "0x%lx", val & 0xffffffffUL);
6025 break;
c19d1205
ZW		 6026
6027 default:
6028 abort ();
6029 }
6030 }
6031 break;
6032
32a94698
NC		 6033 case 'L':
6034 /* PR binutils/12534
6035 If we have a PC relative offset in an LDRD or STRD
6036 instructions then display the decoded address. */
6037 if (((given >> 16) & 0xf) == 0xf)
6038 {
6039 bfd_vma offset = (given & 0xff) * 4;
6040
6041 if ((given & (1 << 23)) == 0)
6042 offset = - offset;
6043 func (stream, "\t; ");
6044 info->print_address_func ((pc & ~3) + 4 + offset, info);
6045 }
6046 break;
6047
c19d1205
ZW		 6048 default:
6049 abort ();
6050 }
6051 }
05413229
NC		 6052
6053 if (value_in_comment > 32 || value_in_comment < -16)
6054 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 6055
6056 if (is_unpredictable)
6057 func (stream, UNPREDICTABLE_INSTRUCTION);
6058
4a5329c6 6059 return;
c19d1205 6060 }
252b5132 6061
58efb6c0 6062 /* No match. */
252b5132
RH		 6063 abort ();
6064}
6065
e821645d
DJ		 6066/* Print data bytes on INFO->STREAM. */
6067
6068static void
fe56b6ce
NC		 6069print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
6070 struct disassemble_info *info,
e821645d
DJ		 6071 long given)
6072{
6073 switch (info->bytes_per_chunk)
6074 {
6075 case 1:
6076 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
6077 break;
6078 case 2:
6079 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
6080 break;
6081 case 4:
6082 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
6083 break;
6084 default:
6085 abort ();
6086 }
6087}
6088
22a398e1 6089/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 6090 being displayed in symbol relative addresses.
6091
6092 Also disallow private symbol, with __tagsym$$ prefix,
6093 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 6094
6095bfd_boolean
6096arm_symbol_is_valid (asymbol * sym,
6097 struct disassemble_info * info ATTRIBUTE_UNUSED)
6098{
6099 const char * name;
43e65147 6100
22a398e1
NC		 6101 if (sym == NULL)
6102 return FALSE;
6103
6104 name = bfd_asymbol_name (sym);
6105
d8282f0e 6106 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 6107}
6108
65b48a81 6109/* Parse the string of disassembler options. */
baf0cc5e 6110
65b48a81 6111static void
f995bbe8 6112parse_arm_disassembler_options (const char *options)
dd92f639 6113{
f995bbe8 6114 const char *opt;
b34976b6 6115
65b48a81 6116 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
dd92f639 6117 {
65b48a81
PB		 6118 if (CONST_STRNEQ (opt, "reg-names-"))
6119 {
6120 unsigned int i;
6121 for (i = 0; i < NUM_ARM_OPTIONS; i++)
6122 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
6123 {
6124 regname_selected = i;
6125 break;
6126 }
b34976b6 6127
65b48a81
PB		 6128 if (i >= NUM_ARM_OPTIONS)
6129 fprintf (stderr, _("Unrecognised register name set: %s\n"), opt);
6130 }
6131 else if (CONST_STRNEQ (opt, "force-thumb"))
6132 force_thumb = 1;
6133 else if (CONST_STRNEQ (opt, "no-force-thumb"))
6134 force_thumb = 0;
6135 else
6136 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), opt);
dd92f639 6137 }
b34976b6 6138
dd92f639
NC		 6139 return;
6140}
6141
5bc5ae88
RL		 6142static bfd_boolean
6143mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6144 enum map_type *map_symbol);
6145
c22aaad1
PB		 6146/* Search back through the insn stream to determine if this instruction is
6147 conditionally executed. */
fe56b6ce 6148
c22aaad1 6149static void
fe56b6ce
NC		 6150find_ifthen_state (bfd_vma pc,
6151 struct disassemble_info *info,
c22aaad1
PB		 6152 bfd_boolean little)
6153{
6154 unsigned char b[2];
6155 unsigned int insn;
6156 int status;
6157 /* COUNT is twice the number of instructions seen. It will be odd if we
6158 just crossed an instruction boundary. */
6159 int count;
6160 int it_count;
6161 unsigned int seen_it;
6162 bfd_vma addr;
6163
6164 ifthen_address = pc;
6165 ifthen_state = 0;
6166
6167 addr = pc;
6168 count = 1;
6169 it_count = 0;
6170 seen_it = 0;
6171 /* Scan backwards looking for IT instructions, keeping track of where
6172 instruction boundaries are. We don't know if something is actually an
6173 IT instruction until we find a definite instruction boundary. */
6174 for (;;)
6175 {
fe56b6ce 6176 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 6177 {
6178 /* A symbol must be on an instruction boundary, and will not
6179 be within an IT block. */
6180 if (seen_it && (count & 1))
6181 break;
6182
6183 return;
6184 }
6185 addr -= 2;
fe56b6ce 6186 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 6187 if (status)
6188 return;
6189
6190 if (little)
6191 insn = (b[0]) | (b[1] << 8);
6192 else
6193 insn = (b[1]) | (b[0] << 8);
6194 if (seen_it)
6195 {
6196 if ((insn & 0xf800) < 0xe800)
6197 {
6198 /* Addr + 2 is an instruction boundary. See if this matches
6199 the expected boundary based on the position of the last
6200 IT candidate. */
6201 if (count & 1)
6202 break;
6203 seen_it = 0;
6204 }
6205 }
6206 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
6207 {
5bc5ae88
RL		 6208 enum map_type type = MAP_ARM;
6209 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
6210
6211 if (!found || (found && type == MAP_THUMB))
6212 {
6213 /* This could be an IT instruction. */
6214 seen_it = insn;
6215 it_count = count >> 1;
6216 }
c22aaad1
PB		 6217 }
6218 if ((insn & 0xf800) >= 0xe800)
6219 count++;
6220 else
6221 count = (count + 2) | 1;
6222 /* IT blocks contain at most 4 instructions. */
6223 if (count >= 8 && !seen_it)
6224 return;
6225 }
6226 /* We found an IT instruction. */
6227 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
6228 if ((ifthen_state & 0xf) == 0)
6229 ifthen_state = 0;
6230}
6231
b0e28b39
DJ		 6232/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
6233 mapping symbol. */
6234
6235static int
6236is_mapping_symbol (struct disassemble_info *info, int n,
6237 enum map_type *map_type)
6238{
6239 const char *name;
6240
6241 name = bfd_asymbol_name (info->symtab[n]);
6242 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
6243 && (name[2] == 0 || name[2] == '.'))
6244 {
6245 *map_type = ((name[1] == 'a') ? MAP_ARM
6246 : (name[1] == 't') ? MAP_THUMB
6247 : MAP_DATA);
6248 return TRUE;
6249 }
6250
6251 return FALSE;
6252}
6253
6254/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
6255 Returns nonzero if *MAP_TYPE was set. */
6256
6257static int
6258get_map_sym_type (struct disassemble_info *info,
6259 int n,
6260 enum map_type *map_type)
6261{
6262 /* If the symbol is in a different section, ignore it. */
6263 if (info->section != NULL && info->section != info->symtab[n]->section)
6264 return FALSE;
6265
6266 return is_mapping_symbol (info, n, map_type);
6267}
6268
6269/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 6270 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 6271
6272static int
fe56b6ce
NC		 6273get_sym_code_type (struct disassemble_info *info,
6274 int n,
e821645d 6275 enum map_type *map_type)
2087ad84
PB		 6276{
6277 elf_symbol_type *es;
6278 unsigned int type;
b0e28b39
DJ		 6279
6280 /* If the symbol is in a different section, ignore it. */
6281 if (info->section != NULL && info->section != info->symtab[n]->section)
6282 return FALSE;
2087ad84 6283
e821645d 6284 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 6285 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6286
6287 /* If the symbol has function type then use that. */
34e77a92 6288 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 6289 {
39d911fc
TP		 6290 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6291 == ST_BRANCH_TO_THUMB)
35fc36a8
RS		 6292 *map_type = MAP_THUMB;
6293 else
6294 *map_type = MAP_ARM;
2087ad84
PB		 6295 return TRUE;
6296 }
6297
2087ad84
PB		 6298 return FALSE;
6299}
6300
5bc5ae88
RL		 6301/* Search the mapping symbol state for instruction at pc. This is only
6302 applicable for elf target.
6303
6304 There is an assumption Here, info->private_data contains the correct AND
6305 up-to-date information about current scan process. The information will be
6306 used to speed this search process.
6307
6308 Return TRUE if the mapping state can be determined, and map_symbol
6309 will be updated accordingly. Otherwise, return FALSE. */
6310
6311static bfd_boolean
6312mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6313 enum map_type *map_symbol)
6314{
6315 bfd_vma addr;
6316 int n, start = 0;
6317 bfd_boolean found = FALSE;
6318 enum map_type type = MAP_ARM;
6319 struct arm_private_data *private_data;
6320
6321 if (info->private_data == NULL || info->symtab_size == 0
6322 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
6323 return FALSE;
6324
6325 private_data = info->private_data;
6326 if (pc == 0)
6327 start = 0;
6328 else
6329 start = private_data->last_mapping_sym;
6330
6331 start = (start == -1)? 0 : start;
6332 addr = bfd_asymbol_value (info->symtab[start]);
6333
6334 if (pc >= addr)
6335 {
6336 if (get_map_sym_type (info, start, &type))
6337 found = TRUE;
6338 }
6339 else
6340 {
6341 for (n = start - 1; n >= 0; n--)
6342 {
6343 if (get_map_sym_type (info, n, &type))
6344 {
6345 found = TRUE;
6346 break;
6347 }
6348 }
6349 }
6350
6351 /* No mapping symbols were found. A leading $d may be
6352 omitted for sections which start with data; but for
6353 compatibility with legacy and stripped binaries, only
6354 assume the leading $d if there is at least one mapping
6355 symbol in the file. */
6356 if (!found && private_data->has_mapping_symbols == 1)
6357 {
6358 type = MAP_DATA;
6359 found = TRUE;
6360 }
6361
6362 *map_symbol = type;
6363 return found;
6364}
6365
0313a2b8
NC		 6366/* Given a bfd_mach_arm_XXX value, this function fills in the fields
6367 of the supplied arm_feature_set structure with bitmasks indicating
6368 the support base architectures and coprocessor extensions.
6369
6370 FIXME: This could more efficiently implemented as a constant array,
6371 although it would also be less robust. */
6372
6373static void
6374select_arm_features (unsigned long mach,
6375 arm_feature_set * features)
6376{
1af1dd51
MW		 6377#undef ARM_SET_FEATURES
6378#define ARM_SET_FEATURES(FSET) \
6379 { \
6380 const arm_feature_set fset = FSET; \
6381 arm_feature_set tmp = ARM_FEATURE (0, 0, FPU_FPA) ; \
6382 ARM_MERGE_FEATURE_SETS (*features, tmp, fset); \
6383 }
823d2571 6384
0313a2b8
NC		 6385 switch (mach)
6386 {
1af1dd51
MW		 6387 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
6388 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
6389 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
6390 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
6391 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
6392 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
6393 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
6394 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
6395 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
6396 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
6397 case bfd_mach_arm_ep9312:
6398 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
6399 ARM_CEXT_MAVERICK | FPU_MAVERICK));
6400 break;
6401 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
6402 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
0313a2b8
NC		 6403 /* If the machine type is unknown allow all
6404 architecture types and all extensions. */
1af1dd51 6405 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
0313a2b8
NC		 6406 default:
6407 abort ();
6408 }
1af1dd51
MW		 6409
6410#undef ARM_SET_FEATURES
0313a2b8
NC		 6411}
6412
6413
58efb6c0
NC		 6414/* NOTE: There are no checks in these routines that
6415 the relevant number of data bytes exist. */
baf0cc5e 6416
58efb6c0 6417static int
4a5329c6 6418print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 6419{
c19d1205
ZW		 6420 unsigned char b[4];
6421 long given;
6422 int status;
e821645d 6423 int is_thumb = FALSE;
b0e28b39 6424 int is_data = FALSE;
bd2e2557 6425 int little_code;
e821645d 6426 unsigned int size = 4;
4a5329c6 6427 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 6428 bfd_boolean found = FALSE;
b0e28b39 6429 struct arm_private_data *private_data;
58efb6c0 6430
dd92f639
NC		 6431 if (info->disassembler_options)
6432 {
65b48a81 6433 parse_arm_disassembler_options (info->disassembler_options);
b34976b6 6434
58efb6c0 6435 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 6436 info->disassembler_options = NULL;
6437 }
b34976b6 6438
0313a2b8
NC		 6439 /* PR 10288: Control which instructions will be disassembled. */
6440 if (info->private_data == NULL)
6441 {
b0e28b39 6442 static struct arm_private_data private;
0313a2b8
NC		 6443
6444 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
6445 /* If the user did not use the -m command line switch then default to
6446 disassembling all types of ARM instruction.
43e65147 6447
0313a2b8
NC		 6448 The info->mach value has to be ignored as this will be based on
6449 the default archictecture for the target and/or hints in the notes
6450 section, but it will never be greater than the current largest arm
6451 machine value (iWMMXt2), which is only equivalent to the V5TE
6452 architecture. ARM architectures have advanced beyond the machine
6453 value encoding, and these newer architectures would be ignored if
6454 the machine value was used.
6455
6456 Ie the -m switch is used to restrict which instructions will be
6457 disassembled. If it is necessary to use the -m switch to tell
6458 objdump that an ARM binary is being disassembled, eg because the
6459 input is a raw binary file, but it is also desired to disassemble
6460 all ARM instructions then use "-marm". This will select the
6461 "unknown" arm architecture which is compatible with any ARM
6462 instruction. */
6463 info->mach = bfd_mach_arm_unknown;
6464
6465 /* Compute the architecture bitmask from the machine number.
6466 Note: This assumes that the machine number will not change
6467 during disassembly.... */
b0e28b39 6468 select_arm_features (info->mach, & private.features);
0313a2b8 6469
b0e28b39 6470 private.has_mapping_symbols = -1;
1fbaefec
PB		 6471 private.last_mapping_sym = -1;
6472 private.last_mapping_addr = 0;
b0e28b39
DJ		 6473
6474 info->private_data = & private;
0313a2b8 6475 }
b0e28b39
DJ		 6476
6477 private_data = info->private_data;
6478
bd2e2557
SS		 6479 /* Decide if our code is going to be little-endian, despite what the
6480 function argument might say. */
6481 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
6482
b0e28b39
DJ		 6483 /* For ELF, consult the symbol table to determine what kind of code
6484 or data we have. */
8977d4b2 6485 if (info->symtab_size != 0
e821645d
DJ		 6486 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
6487 {
6488 bfd_vma addr;
b0e28b39 6489 int n, start;
e821645d 6490 int last_sym = -1;
b0e28b39 6491 enum map_type type = MAP_ARM;
e821645d 6492
e821645d
DJ		 6493 /* Start scanning at the start of the function, or wherever
6494 we finished last time. */
6750a3a7
NC		 6495 /* PR 14006. When the address is 0 we are either at the start of the
6496 very first function, or else the first function in a new, unlinked
838441e4 6497 executable section (eg because of -ffunction-sections). Either way
6750a3a7
NC		 6498 start scanning from the beginning of the symbol table, not where we
6499 left off last time. */
6500 if (pc == 0)
6501 start = 0;
6502 else
6503 {
6504 start = info->symtab_pos + 1;
6505 if (start < private_data->last_mapping_sym)
6506 start = private_data->last_mapping_sym;
6507 }
b0e28b39 6508 found = FALSE;
e821645d 6509
b0e28b39
DJ		 6510 /* First, look for mapping symbols. */
6511 if (private_data->has_mapping_symbols != 0)
e821645d 6512 {
b0e28b39
DJ		 6513 /* Scan up to the location being disassembled. */
6514 for (n = start; n < info->symtab_size; n++)
6515 {
6516 addr = bfd_asymbol_value (info->symtab[n]);
6517 if (addr > pc)
6518 break;
6519 if (get_map_sym_type (info, n, &type))
6520 {
6521 last_sym = n;
6522 found = TRUE;
6523 }
6524 }
6525
6526 if (!found)
6527 {
6528 /* No mapping symbol found at this address. Look backwards
cc643b88 6529 for a preceding one. */
b0e28b39
DJ		 6530 for (n = start - 1; n >= 0; n--)
6531 {
6532 if (get_map_sym_type (info, n, &type))
6533 {
6534 last_sym = n;
6535 found = TRUE;
6536 break;
6537 }
6538 }
6539 }
6540
6541 if (found)
6542 private_data->has_mapping_symbols = 1;
6543
6544 /* No mapping symbols were found. A leading $d may be
6545 omitted for sections which start with data; but for
6546 compatibility with legacy and stripped binaries, only
6547 assume the leading $d if there is at least one mapping
6548 symbol in the file. */
6549 if (!found && private_data->has_mapping_symbols == -1)
e821645d 6550 {
b0e28b39
DJ		 6551 /* Look for mapping symbols, in any section. */
6552 for (n = 0; n < info->symtab_size; n++)
6553 if (is_mapping_symbol (info, n, &type))
6554 {
6555 private_data->has_mapping_symbols = 1;
6556 break;
6557 }
6558 if (private_data->has_mapping_symbols == -1)
6559 private_data->has_mapping_symbols = 0;
6560 }
6561
6562 if (!found && private_data->has_mapping_symbols == 1)
6563 {
6564 type = MAP_DATA;
e821645d
DJ		 6565 found = TRUE;
6566 }
6567 }
6568
b0e28b39
DJ		 6569 /* Next search for function symbols to separate ARM from Thumb
6570 in binaries without mapping symbols. */
e821645d
DJ		 6571 if (!found)
6572 {
b0e28b39
DJ		 6573 /* Scan up to the location being disassembled. */
6574 for (n = start; n < info->symtab_size; n++)
e821645d 6575 {
b0e28b39
DJ		 6576 addr = bfd_asymbol_value (info->symtab[n]);
6577 if (addr > pc)
6578 break;
6579 if (get_sym_code_type (info, n, &type))
e821645d
DJ		 6580 {
6581 last_sym = n;
6582 found = TRUE;
b0e28b39
DJ		 6583 }
6584 }
6585
6586 if (!found)
6587 {
6588 /* No mapping symbol found at this address. Look backwards
cc643b88 6589 for a preceding one. */
b0e28b39
DJ		 6590 for (n = start - 1; n >= 0; n--)
6591 {
6592 if (get_sym_code_type (info, n, &type))
6593 {
6594 last_sym = n;
6595 found = TRUE;
6596 break;
6597 }
e821645d
DJ		 6598 }
6599 }
6600 }
6601
1fbaefec
PB		 6602 private_data->last_mapping_sym = last_sym;
6603 private_data->last_type = type;
6604 is_thumb = (private_data->last_type == MAP_THUMB);
6605 is_data = (private_data->last_type == MAP_DATA);
b34976b6 6606
e821645d
DJ		 6607 /* Look a little bit ahead to see if we should print out
6608 two or four bytes of data. If there's a symbol,
6609 mapping or otherwise, after two bytes then don't
6610 print more. */
6611 if (is_data)
6612 {
6613 size = 4 - (pc & 3);
6614 for (n = last_sym + 1; n < info->symtab_size; n++)
6615 {
6616 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 6617 if (addr > pc
6618 && (info->section == NULL
6619 || info->section == info->symtab[n]->section))
e821645d
DJ		 6620 {
6621 if (addr - pc < size)
6622 size = addr - pc;
6623 break;
6624 }
6625 }
6626 /* If the next symbol is after three bytes, we need to
6627 print only part of the data, so that we can use either
6628 .byte or .short. */
6629 if (size == 3)
6630 size = (pc & 1) ? 1 : 2;
6631 }
6632 }
6633
6634 if (info->symbols != NULL)
252b5132 6635 {
5876e06d
NC		 6636 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
6637 {
2f0ca46a 6638 coff_symbol_type * cs;
b34976b6 6639
5876e06d
NC		 6640 cs = coffsymbol (*info->symbols);
6641 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
6642 || cs->native->u.syment.n_sclass == C_THUMBSTAT
6643 || cs->native->u.syment.n_sclass == C_THUMBLABEL
6644 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
6645 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
6646 }
e821645d
DJ		 6647 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
6648 && !found)
5876e06d 6649 {
2087ad84
PB		 6650 /* If no mapping symbol has been found then fall back to the type
6651 of the function symbol. */
e821645d
DJ		 6652 elf_symbol_type * es;
6653 unsigned int type;
2087ad84 6654
e821645d
DJ		 6655 es = *(elf_symbol_type **)(info->symbols);
6656 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 6657
39d911fc
TP		 6658 is_thumb =
6659 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6660 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
5876e06d 6661 }
e49d43ff
TG		 6662 else if (bfd_asymbol_flavour (*info->symbols)
6663 == bfd_target_mach_o_flavour)
6664 {
6665 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
6666
6667 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
6668 }
5876e06d 6669 }
b34976b6 6670
e821645d
DJ		 6671 if (force_thumb)
6672 is_thumb = TRUE;
6673
b8f9ee44
CL		 6674 if (is_data)
6675 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6676 else
6677 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6678
c19d1205 6679 info->bytes_per_line = 4;
252b5132 6680
1316c8b3
NC		 6681 /* PR 10263: Disassemble data if requested to do so by the user. */
6682 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 6683 {
6684 int i;
6685
1316c8b3 6686 /* Size was already set above. */
e821645d
DJ		 6687 info->bytes_per_chunk = size;
6688 printer = print_insn_data;
6689
fe56b6ce 6690 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 6691 given = 0;
6692 if (little)
6693 for (i = size - 1; i >= 0; i--)
6694 given = b[i] | (given << 8);
6695 else
6696 for (i = 0; i < (int) size; i++)
6697 given = b[i] | (given << 8);
6698 }
6699 else if (!is_thumb)
252b5132 6700 {
c19d1205
ZW		 6701 /* In ARM mode endianness is a straightforward issue: the instruction
6702 is four bytes long and is either ordered 0123 or 3210. */
6703 printer = print_insn_arm;
6704 info->bytes_per_chunk = 4;
4a5329c6 6705 size = 4;
c19d1205 6706
0313a2b8 6707 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 6708 if (little_code)
c19d1205
ZW		 6709 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
6710 else
6711 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
252b5132 6712 }
58efb6c0 6713 else
252b5132 6714 {
c19d1205
ZW		 6715 /* In Thumb mode we have the additional wrinkle of two
6716 instruction lengths. Fortunately, the bits that determine
6717 the length of the current instruction are always to be found
6718 in the first two bytes. */
4a5329c6 6719 printer = print_insn_thumb16;
c19d1205 6720 info->bytes_per_chunk = 2;
4a5329c6
ZW		 6721 size = 2;
6722
fe56b6ce 6723 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 6724 if (little_code)
9a2ff3f5
AM		 6725 given = (b[0]) | (b[1] << 8);
6726 else
6727 given = (b[1]) | (b[0] << 8);
6728
c19d1205 6729 if (!status)
252b5132 6730 {
c19d1205
ZW		 6731 /* These bit patterns signal a four-byte Thumb
6732 instruction. */
6733 if ((given & 0xF800) == 0xF800
6734 || (given & 0xF800) == 0xF000
6735 || (given & 0xF800) == 0xE800)
252b5132 6736 {
0313a2b8 6737 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 6738 if (little_code)
c19d1205 6739 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 6740 else
c19d1205
ZW		 6741 given = (b[1]) | (b[0] << 8) | (given << 16);
6742
6743 printer = print_insn_thumb32;
4a5329c6 6744 size = 4;
252b5132 6745 }
252b5132 6746 }
c22aaad1
PB		 6747
6748 if (ifthen_address != pc)
0313a2b8 6749 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 6750
6751 if (ifthen_state)
6752 {
6753 if ((ifthen_state & 0xf) == 0x8)
6754 ifthen_next_state = 0;
6755 else
6756 ifthen_next_state = (ifthen_state & 0xe0)
6757 | ((ifthen_state & 0xf) << 1);
6758 }
252b5132 6759 }
b34976b6 6760
c19d1205
ZW		 6761 if (status)
6762 {
6763 info->memory_error_func (status, pc, info);
6764 return -1;
6765 }
6a56ec7e
NC		 6766 if (info->flags & INSN_HAS_RELOC)
6767 /* If the instruction has a reloc associated with it, then
6768 the offset field in the instruction will actually be the
6769 addend for the reloc. (We are using REL type relocs).
6770 In such cases, we can ignore the pc when computing
6771 addresses, since the addend is not currently pc-relative. */
6772 pc = 0;
b34976b6 6773
4a5329c6 6774 printer (pc, info, given);
c22aaad1
PB		 6775
6776 if (is_thumb)
6777 {
6778 ifthen_state = ifthen_next_state;
6779 ifthen_address += size;
6780 }
4a5329c6 6781 return size;
252b5132
RH		 6782}
6783
6784int
4a5329c6 6785print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 6786{
bd2e2557
SS		 6787 /* Detect BE8-ness and record it in the disassembler info. */
6788 if (info->flavour == bfd_target_elf_flavour
6789 && info->section != NULL
6790 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
6791 info->endian_code = BFD_ENDIAN_LITTLE;
6792
b34976b6 6793 return print_insn (pc, info, FALSE);
58efb6c0 6794}
01c7f630 6795
58efb6c0 6796int
4a5329c6 6797print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 6798{
b34976b6 6799 return print_insn (pc, info, TRUE);
58efb6c0 6800}
252b5132 6801
65b48a81
PB		 6802const disasm_options_t *
6803disassembler_options_arm (void)
6804{
6805 static disasm_options_t *opts = NULL;
6806
6807 if (opts == NULL)
6808 {
6809 unsigned int i;
6810 opts = XNEW (disasm_options_t);
6811 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
6812 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
6813 for (i = 0; i < NUM_ARM_OPTIONS; i++)
6814 {
6815 opts->name[i] = regnames[i].name;
6816 if (regnames[i].description != NULL)
6817 opts->description[i] = _(regnames[i].description);
6818 else
6819 opts->description[i] = NULL;
6820 }
6821 /* The array we return must be NULL terminated. */
6822 opts->name[i] = NULL;
6823 opts->description[i] = NULL;
6824 }
6825
6826 return opts;
6827}
6828
58efb6c0 6829void
4a5329c6 6830print_arm_disassembler_options (FILE *stream)
58efb6c0 6831{
65b48a81 6832 unsigned int i, max_len = 0;
58efb6c0
NC		 6833 fprintf (stream, _("\n\
6834The following ARM specific disassembler options are supported for use with\n\
6835the -M switch:\n"));
b34976b6 6836
65b48a81
PB		 6837 for (i = 0; i < NUM_ARM_OPTIONS; i++)
6838 {
6839 unsigned int len = strlen (regnames[i].name);
6840 if (max_len < len)
6841 max_len = len;
6842 }
58efb6c0 6843
65b48a81
PB		 6844 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
6845 fprintf (stream, " %s%*c %s\n",
6846 regnames[i].name,
6847 (int)(max_len - strlen (regnames[i].name)), ' ',
6848 _(regnames[i].description));
252b5132 6849}
GDB Binutils - Deliverables
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