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Add support for the GBZ80, Z180, and eZ80 variants of the Z80 architecure. Add an...
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
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252b5132 1/* Instruction printing code for the ARM
b3adc24a 2 Copyright (C) 1994-2020 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
143275ea 24#include <assert.h>
2fbad815 25
6394c606 26#include "disassemble.h"
2fbad815 27#include "opcode/arm.h"
252b5132 28#include "opintl.h"
31e0f3cd 29#include "safe-ctype.h"
65b48a81 30#include "libiberty.h"
0dbde4cf 31#include "floatformat.h"
252b5132 32
baf0cc5e 33/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 34#include "coff/internal.h"
35#include "libcoff.h"
2d5d5a8f 36#include "bfd.h"
252b5132
RH		 37#include "elf-bfd.h"
38#include "elf/internal.h"
39#include "elf/arm.h"
e49d43ff 40#include "mach-o.h"
252b5132 41
6b5d3a4d 42/* FIXME: Belongs in global header. */
01c7f630 43#ifndef strneq
58efb6c0
NC		 44#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
45#endif
46
1fbaefec
PB		 47/* Cached mapping symbol state. */
48enum map_type
49{
50 MAP_ARM,
51 MAP_THUMB,
52 MAP_DATA
53};
54
b0e28b39
DJ		 55struct arm_private_data
56{
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features;
59
1fbaefec
PB		 60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type;
62
63 /* Tracking symbol table information */
64 int last_mapping_sym;
796d6298
TC		 65
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset;
1fbaefec 68 bfd_vma last_mapping_addr;
b0e28b39
DJ		 69};
70
73cd51e5
AV		 71enum mve_instructions
72{
143275ea
AV		 73 MVE_VPST,
74 MVE_VPT_FP_T1,
75 MVE_VPT_FP_T2,
76 MVE_VPT_VEC_T1,
77 MVE_VPT_VEC_T2,
78 MVE_VPT_VEC_T3,
79 MVE_VPT_VEC_T4,
80 MVE_VPT_VEC_T5,
81 MVE_VPT_VEC_T6,
82 MVE_VCMP_FP_T1,
83 MVE_VCMP_FP_T2,
84 MVE_VCMP_VEC_T1,
85 MVE_VCMP_VEC_T2,
86 MVE_VCMP_VEC_T3,
87 MVE_VCMP_VEC_T4,
88 MVE_VCMP_VEC_T5,
89 MVE_VCMP_VEC_T6,
9743db03
AV		 90 MVE_VDUP,
91 MVE_VEOR,
92 MVE_VFMAS_FP_SCALAR,
93 MVE_VFMA_FP_SCALAR,
94 MVE_VFMA_FP,
95 MVE_VFMS_FP,
96 MVE_VHADD_T1,
97 MVE_VHADD_T2,
98 MVE_VHSUB_T1,
99 MVE_VHSUB_T2,
100 MVE_VRHADD,
04d54ace
AV		 101 MVE_VLD2,
102 MVE_VLD4,
103 MVE_VST2,
104 MVE_VST4,
aef6d006
AV		 105 MVE_VLDRB_T1,
106 MVE_VLDRH_T2,
107 MVE_VLDRB_T5,
108 MVE_VLDRH_T6,
109 MVE_VLDRW_T7,
110 MVE_VSTRB_T1,
111 MVE_VSTRH_T2,
112 MVE_VSTRB_T5,
113 MVE_VSTRH_T6,
114 MVE_VSTRW_T7,
ef1576a1
AV		 115 MVE_VLDRB_GATHER_T1,
116 MVE_VLDRH_GATHER_T2,
117 MVE_VLDRW_GATHER_T3,
118 MVE_VLDRD_GATHER_T4,
119 MVE_VLDRW_GATHER_T5,
120 MVE_VLDRD_GATHER_T6,
121 MVE_VSTRB_SCATTER_T1,
122 MVE_VSTRH_SCATTER_T2,
123 MVE_VSTRW_SCATTER_T3,
124 MVE_VSTRD_SCATTER_T4,
125 MVE_VSTRW_SCATTER_T5,
126 MVE_VSTRD_SCATTER_T6,
bf0b396d
AV		 127 MVE_VCVT_FP_FIX_VEC,
128 MVE_VCVT_BETWEEN_FP_INT,
129 MVE_VCVT_FP_HALF_FP,
130 MVE_VCVT_FROM_FP_TO_INT,
131 MVE_VRINT_FP,
c507f10b
AV		 132 MVE_VMOV_HFP_TO_GP,
133 MVE_VMOV_GP_TO_VEC_LANE,
134 MVE_VMOV_IMM_TO_VEC,
135 MVE_VMOV_VEC_TO_VEC,
136 MVE_VMOV2_VEC_LANE_TO_GP,
137 MVE_VMOV2_GP_TO_VEC_LANE,
138 MVE_VMOV_VEC_LANE_TO_GP,
139 MVE_VMVN_IMM,
140 MVE_VMVN_REG,
141 MVE_VORR_IMM,
142 MVE_VORR_REG,
143 MVE_VORN,
144 MVE_VBIC_IMM,
145 MVE_VBIC_REG,
146 MVE_VMOVX,
14925797
AV		 147 MVE_VMOVL,
148 MVE_VMOVN,
149 MVE_VMULL_INT,
150 MVE_VMULL_POLY,
151 MVE_VQDMULL_T1,
152 MVE_VQDMULL_T2,
153 MVE_VQMOVN,
154 MVE_VQMOVUN,
d3b63143
AV		 155 MVE_VADDV,
156 MVE_VMLADAV_T1,
157 MVE_VMLADAV_T2,
158 MVE_VMLALDAV,
159 MVE_VMLAS,
160 MVE_VADDLV,
161 MVE_VMLSDAV_T1,
162 MVE_VMLSDAV_T2,
163 MVE_VMLSLDAV,
164 MVE_VRMLALDAVH,
165 MVE_VRMLSLDAVH,
166 MVE_VQDMLADH,
167 MVE_VQRDMLADH,
168 MVE_VQDMLAH,
169 MVE_VQRDMLAH,
170 MVE_VQDMLASH,
171 MVE_VQRDMLASH,
172 MVE_VQDMLSDH,
173 MVE_VQRDMLSDH,
174 MVE_VQDMULH_T1,
175 MVE_VQRDMULH_T2,
176 MVE_VQDMULH_T3,
177 MVE_VQRDMULH_T4,
1c8f2df8
AV		 178 MVE_VDDUP,
179 MVE_VDWDUP,
180 MVE_VIWDUP,
181 MVE_VIDUP,
897b9bbc
AV		 182 MVE_VCADD_FP,
183 MVE_VCADD_VEC,
184 MVE_VHCADD,
185 MVE_VCMLA_FP,
186 MVE_VCMUL_FP,
ed63aa17
AV		 187 MVE_VQRSHL_T1,
188 MVE_VQRSHL_T2,
189 MVE_VQRSHRN,
190 MVE_VQRSHRUN,
191 MVE_VQSHL_T1,
192 MVE_VQSHL_T2,
193 MVE_VQSHLU_T3,
194 MVE_VQSHL_T4,
195 MVE_VQSHRN,
196 MVE_VQSHRUN,
197 MVE_VRSHL_T1,
198 MVE_VRSHL_T2,
199 MVE_VRSHR,
200 MVE_VRSHRN,
201 MVE_VSHL_T1,
202 MVE_VSHL_T2,
203 MVE_VSHL_T3,
204 MVE_VSHLC,
205 MVE_VSHLL_T1,
206 MVE_VSHLL_T2,
207 MVE_VSHR,
208 MVE_VSHRN,
209 MVE_VSLI,
210 MVE_VSRI,
66dcaa5d
AV		 211 MVE_VADC,
212 MVE_VABAV,
213 MVE_VABD_FP,
214 MVE_VABD_VEC,
215 MVE_VABS_FP,
216 MVE_VABS_VEC,
217 MVE_VADD_FP_T1,
218 MVE_VADD_FP_T2,
219 MVE_VADD_VEC_T1,
220 MVE_VADD_VEC_T2,
221 MVE_VSBC,
222 MVE_VSUB_FP_T1,
223 MVE_VSUB_FP_T2,
224 MVE_VSUB_VEC_T1,
225 MVE_VSUB_VEC_T2,
e523f101
AV		 226 MVE_VAND,
227 MVE_VBRSR,
228 MVE_VCLS,
229 MVE_VCLZ,
230 MVE_VCTP,
56858bea
AV		 231 MVE_VMAX,
232 MVE_VMAXA,
233 MVE_VMAXNM_FP,
234 MVE_VMAXNMA_FP,
235 MVE_VMAXNMV_FP,
236 MVE_VMAXNMAV_FP,
237 MVE_VMAXV,
238 MVE_VMAXAV,
239 MVE_VMIN,
240 MVE_VMINA,
241 MVE_VMINNM_FP,
242 MVE_VMINNMA_FP,
243 MVE_VMINNMV_FP,
244 MVE_VMINNMAV_FP,
245 MVE_VMINV,
246 MVE_VMINAV,
247 MVE_VMLA,
f49bb598
AV		 248 MVE_VMUL_FP_T1,
249 MVE_VMUL_FP_T2,
250 MVE_VMUL_VEC_T1,
251 MVE_VMUL_VEC_T2,
252 MVE_VMULH,
253 MVE_VRMULH,
254 MVE_VNEG_FP,
255 MVE_VNEG_VEC,
14b456f2
AV		 256 MVE_VPNOT,
257 MVE_VPSEL,
258 MVE_VQABS,
259 MVE_VQADD_T1,
260 MVE_VQADD_T2,
261 MVE_VQSUB_T1,
262 MVE_VQSUB_T2,
263 MVE_VQNEG,
264 MVE_VREV16,
265 MVE_VREV32,
266 MVE_VREV64,
23d00a41
SD		 267 MVE_LSLL,
268 MVE_LSLLI,
269 MVE_LSRL,
270 MVE_ASRL,
271 MVE_ASRLI,
272 MVE_SQRSHRL,
273 MVE_SQRSHR,
274 MVE_UQRSHL,
275 MVE_UQRSHLL,
276 MVE_UQSHL,
277 MVE_UQSHLL,
278 MVE_URSHRL,
279 MVE_URSHR,
280 MVE_SRSHRL,
281 MVE_SRSHR,
282 MVE_SQSHLL,
283 MVE_SQSHL,
e39c1607
SD		 284 MVE_CINC,
285 MVE_CINV,
286 MVE_CNEG,
287 MVE_CSINC,
288 MVE_CSINV,
289 MVE_CSET,
290 MVE_CSETM,
291 MVE_CSNEG,
292 MVE_CSEL,
73cd51e5
AV		 293 MVE_NONE
294};
295
296enum mve_unpredictable
297{
298 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
299 */
143275ea
AV		 300 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and
301 fcB = 1 (vpt). */
302 UNPRED_R13, /* Unpredictable because r13 (sp) or
303 r15 (sp) used. */
9743db03 304 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
04d54ace
AV		 305 UNPRED_Q_GT_4, /* Unpredictable because
306 vec reg start > 4 (vld4/st4). */
307 UNPRED_Q_GT_6, /* Unpredictable because
308 vec reg start > 6 (vld2/st2). */
309 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
310 and WB bit = 1. */
ef1576a1
AV		 311 UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are
312 equal. */
313 UNPRED_OS, /* Unpredictable because offset scaled == 1. */
bf0b396d
AV		 314 UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the
315 same. */
c507f10b
AV		 316 UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and
317 size = 1. */
318 UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and
319 size = 2. */
73cd51e5
AV		 320 UNPRED_NONE /* No unpredictable behavior. */
321};
322
323enum mve_undefined
324{
ed63aa17 325 UNDEF_SIZE, /* undefined size. */
bf0b396d 326 UNDEF_SIZE_0, /* undefined because size == 0. */
c507f10b 327 UNDEF_SIZE_2, /* undefined because size == 2. */
aef6d006
AV		 328 UNDEF_SIZE_3, /* undefined because size == 3. */
329 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
14b456f2 330 UNDEF_SIZE_NOT_0, /* undefined because size != 0. */
ef1576a1
AV		 331 UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
332 UNDEF_SIZE_NOT_3, /* undefined because size != 3. */
333 UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and
334 size == 0. */
335 UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and
336 size == 1. */
337 UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
bf0b396d
AV		 338 UNDEF_VCVT_IMM6, /* imm6 < 32. */
339 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
c507f10b
AV		 340 UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and
341 op1 == (0 or 1). */
342 UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and
343 op2 == 0 and op1 == (0 or 1). */
344 UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode
345 in {0xx1, x0x1}. */
d3b63143 346 UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */
73cd51e5
AV		 347 UNDEF_NONE /* no undefined behavior. */
348};
349
6b5d3a4d
ZW		 350struct opcode32
351{
823d2571
TG		 352 arm_feature_set arch; /* Architecture defining this insn. */
353 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 354 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 355 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 356};
357
73cd51e5
AV		 358/* MVE opcodes. */
359
360struct mopcode32
361{
362 arm_feature_set arch; /* Architecture defining this insn. */
363 enum mve_instructions mve_op; /* Specific mve instruction for faster
364 decoding. */
365 unsigned long value; /* If arch is 0 then value is a sentinel. */
366 unsigned long mask; /* Recognise insn if (op & mask) == value. */
367 const char * assembler; /* How to disassemble this insn. */
368};
369
6b0dd094
AV		 370enum isa {
371 ANY,
372 T32,
373 ARM
374};
375
376
377/* Shared (between Arm and Thumb mode) opcode. */
378struct sopcode32
379{
380 enum isa isa; /* Execution mode instruction availability. */
381 arm_feature_set arch; /* Architecture defining this insn. */
382 unsigned long value; /* If arch is 0 then value is a sentinel. */
383 unsigned long mask; /* Recognise insn if (op & mask) == value. */
384 const char * assembler; /* How to disassemble this insn. */
385};
386
6b5d3a4d
ZW		 387struct opcode16
388{
823d2571 389 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 390 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 391 const char *assembler; /* How to disassemble this insn. */
392};
b7693d02 393
8f06b2d8 394/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 395
2fbad815 396 %% %
4a5329c6 397
c22aaad1 398 %c print condition code (always bits 28-31 in ARM mode)
aab2c27d 399 %b print condition code allowing cp_num == 9
37b37b2d 400 %q print shifter argument
e2efe87d
MGD		 401 %u print condition code (unconditional in ARM mode,
402 UNPREDICTABLE if not AL in Thumb)
4a5329c6 403 %A print address for ldc/stc/ldf/stf instruction
16980d0b 404 %B print vstm/vldm register list
efd6b359 405 %C print vscclrm register list
4a5329c6 406 %I print cirrus signed shift immediate: bits 0..3|4..6
32c36c3c
AV		 407 %J print register for VLDR instruction
408 %K print address for VLDR instruction
4a5329c6
ZW		 409 %F print the COUNT field of a LFM/SFM instruction.
410 %P print floating point precision in arithmetic insn
411 %Q print floating point precision in ldf/stf insn
412 %R print floating point rounding mode
413
33399f07 414 %<bitfield>c print as a condition code (for vsel)
4a5329c6 415 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 416 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
417 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 418 %<bitfield>d print the bitfield in decimal
16980d0b 419 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 420 %<bitfield>x print the bitfield in hex
421 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 422 %<bitfield>f print a floating point constant if >7 else a
423 floating point register
4a5329c6
ZW		 424 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
425 %<bitfield>g print as an iWMMXt 64-bit register
426 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 427 %<bitfield>D print as a NEON D register
428 %<bitfield>Q print as a NEON Q register
c28eeff2 429 %<bitfield>V print as a NEON D or Q register
6f1c2142 430 %<bitfield>E print a quarter-float immediate value
4a5329c6 431
16980d0b 432 %y<code> print a single precision VFP reg.
2fbad815 433 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 434 %z<code> print a double precision VFP reg
2fbad815 435 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 436
16980d0b
JB		 437 %<bitfield>'c print specified char iff bitfield is all ones
438 %<bitfield>`c print specified char iff bitfield is all zeroes
439 %<bitfield>?ab... select from array of values in big endian order
43e65147 440
2fbad815 441 %L print as an iWMMXt N/M width field.
4a5329c6 442 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 443 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 444 versions.
445 %i print 5-bit immediate in bits 8,3..0
446 (print "32" when 0)
fe56b6ce 447 %r print register offset address for wldt/wstr instruction. */
2fbad815 448
21d799b5 449enum opcode_sentinel_enum
05413229
NC		 450{
451 SENTINEL_IWMMXT_START = 1,
452 SENTINEL_IWMMXT_END,
453 SENTINEL_GENERIC_START
454} opcode_sentinels;
455
aefd8a40 456#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
0b347048
TC		 457#define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
458#define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
c1e26897 459#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 460
8f06b2d8 461/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 462
6b0dd094 463static const struct sopcode32 coprocessor_opcodes[] =
2fbad815 464{
2fbad815 465 /* XScale instructions. */
6b0dd094 466 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 467 0x0e200010, 0x0fff0ff0,
468 "mia%c\tacc0, %0-3r, %12-15r"},
6b0dd094 469 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 470 0x0e280010, 0x0fff0ff0,
471 "miaph%c\tacc0, %0-3r, %12-15r"},
6b0dd094 472 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 473 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
6b0dd094 474 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 475 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
6b0dd094 476 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 477 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 478
2fbad815 479 /* Intel Wireless MMX technology instructions. */
6b0dd094
AV		 480 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
481 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
823d2571 482 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
6b0dd094 483 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 484 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
6b0dd094 485 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 486 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
6b0dd094 487 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 488 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
6b0dd094 489 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 490 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
6b0dd094 491 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 492 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
6b0dd094 493 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 494 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
6b0dd094 495 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 496 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 497 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 498 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 499 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 500 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 501 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 502 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
6b0dd094 503 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 504 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
6b0dd094 505 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 506 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
6b0dd094 507 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 508 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
6b0dd094 509 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 510 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
6b0dd094 511 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 512 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 513 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 514 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 515 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 516 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 517 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 518 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 519 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 520 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 521 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 522 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
6b0dd094 523 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 524 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 525 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 526 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 527 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 528 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 529 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 530 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 531 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 532 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 533 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 534 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 535 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 536 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
6b0dd094 537 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 538 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
6b0dd094 539 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 540 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
6b0dd094 541 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 542 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 543 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 544 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 545 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 546 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 547 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 548 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 549 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 550 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
6b0dd094 551 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 552 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 553 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 554 0x0e800120, 0x0f800ff0,
555 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 556 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 557 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 558 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 559 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 560 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 561 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 562 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 563 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 564 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 565 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 566 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 567 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 568 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 569 0x0e8000a0, 0x0f800ff0,
570 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 571 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 572 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 573 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 574 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 575 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 576 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 577 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 578 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 579 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 580 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 581 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 582 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 583 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 584 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 585 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 586 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 587 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 588 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
6b0dd094 589 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 590 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 591 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 592 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 593 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 594 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 595 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 596 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 597 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 598 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 599 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 600 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 601 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 602 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 603 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 604 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 605 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 606 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 607 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 608 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
6b0dd094 609 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 610 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
6b0dd094 611 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 612 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
6b0dd094 613 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 614 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 615 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 616 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 617 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 618 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 619 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 620 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
6b0dd094 621 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 622 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
6b0dd094 623 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 624 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
6b0dd094 625 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 626 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 627 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 628 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 629 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 630 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 631 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 632 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 633 {ANY, ARM_FEATURE_CORE_LOW (0),
823d2571 634 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 635
fe56b6ce 636 /* Floating point coprocessor (FPA) instructions. */
6b0dd094 637 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 638 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 639 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 640 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 641 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 642 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 643 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 644 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 645 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 646 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 647 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 648 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 649 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 650 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 651 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 652 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 653 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 654 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 655 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 656 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 657 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 658 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 659 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 660 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 661 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 662 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 663 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 664 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 665 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 666 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 667 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 668 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 669 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 670 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 671 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 672 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
6b0dd094 673 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 674 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
6b0dd094 675 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 676 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 677 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 678 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
6b0dd094 679 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 680 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
6b0dd094 681 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 682 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
6b0dd094 683 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 684 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
6b0dd094 685 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 686 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 687 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 688 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 689 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 690 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 691 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 692 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 693 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 694 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
6b0dd094 695 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 696 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
6b0dd094 697 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 698 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
6b0dd094 699 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 700 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
6b0dd094 701 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 702 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
6b0dd094 703 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 704 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
6b0dd094 705 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 706 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
6b0dd094 707 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 708 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
6b0dd094 709 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 710 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
6b0dd094 711 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 712 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
6b0dd094 713 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 714 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
6b0dd094 715 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 716 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
6b0dd094 717 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 718 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
6b0dd094 719 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 720 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
6b0dd094 721 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 722 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 723
efd6b359
AV		 724 /* Armv8.1-M Mainline instructions. */
725 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
726 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
727 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
728 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
729
16a1fa25 730 /* ARMv8-M Mainline Security Extensions instructions. */
6b0dd094 731 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25 732 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
6b0dd094 733 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25
TP		 734 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
735
fe56b6ce 736 /* Register load/store. */
6b0dd094 737 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 738 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
6b0dd094 739 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 740 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
6b0dd094 741 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 742 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
6b0dd094 743 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 744 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
6b0dd094 745 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 746 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
6b0dd094 747 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 748 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
6b0dd094 749 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 750 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
6b0dd094 751 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 752 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
6b0dd094 753 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 754 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
6b0dd094 755 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 756 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
6b0dd094 757 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 758 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
6b0dd094 759 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 760 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
6b0dd094 761 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 762 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
6b0dd094 763 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 764 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
6b0dd094 765 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 766 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
6b0dd094 767 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 768 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
32c36c3c
AV		 769 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
770 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
771 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
772 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
823d2571 773
6b0dd094 774 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 775 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 776 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 777 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 778 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 779 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
6b0dd094 780 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 781 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 782
fe56b6ce 783 /* Data transfer between ARM and NEON registers. */
6b0dd094 784 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 785 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
6b0dd094 786 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 787 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
6b0dd094 788 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 789 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
6b0dd094 790 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 791 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
6b0dd094 792 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 793 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
6b0dd094 794 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 795 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
6b0dd094 796 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 797 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
6b0dd094 798 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 799 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 800 /* Half-precision conversion instructions. */
6b0dd094 801 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 802 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
6b0dd094 803 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 804 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
6b0dd094 805 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 806 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
6b0dd094 807 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 808 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 809
fe56b6ce 810 /* Floating point coprocessor (VFP) instructions. */
6b0dd094 811 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 812 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
ba6cd17f 813 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_MVE),
823d2571 814 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
ba6cd17f
SD		 815 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
816 0x0ee20a10, 0x0fff0fff, "vmsr%c\tfpscr_nzcvqc, %12-15r"},
6b0dd094 817 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 818 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
6b0dd094 819 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 820 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
6b0dd094 821 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 822 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
6b0dd094 823 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 824 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
6b0dd094 825 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 826 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
6b0dd094 827 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 828 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
ba6cd17f
SD		 829 {ANY, ARM_FEATURE_COPROC (FPU_MVE),
830 0x0eec0a10, 0x0fff0fff, "vmsr%c\tvpr, %12-15r"},
831 {ANY, ARM_FEATURE_COPROC (FPU_MVE),
832 0x0eed0a10, 0x0fff0fff, "vmsr%c\tp0, %12-15r"},
833 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
834 0x0eee0a10, 0x0fff0fff, "vmsr%c\tfpcxt_ns, %12-15r"},
835 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
836 0x0eef0a10, 0x0fff0fff, "vmsr%c\tfpcxt_s, %12-15r"},
6b0dd094 837 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 838 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
6b0dd094 839 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 840 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
ba6cd17f 841 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_MVE),
823d2571 842 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
ba6cd17f
SD		 843 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
844 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr_nzcvqc"},
6b0dd094 845 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 846 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
6b0dd094 847 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 848 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
6b0dd094 849 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 850 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
6b0dd094 851 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 852 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
6b0dd094 853 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 854 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
6b0dd094 855 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 856 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
ba6cd17f
SD		 857 {ANY, ARM_FEATURE_COPROC (FPU_MVE),
858 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, vpr"},
859 {ANY, ARM_FEATURE_COPROC (FPU_MVE),
860 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, p0"},
861 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
862 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_ns"},
863 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
864 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_s"},
6b0dd094 865 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 866 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
6b0dd094 867 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 868 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
6b0dd094 869 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 870 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
6b0dd094 871 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 872 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
6b0dd094 873 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 874 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
6b0dd094 875 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 876 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
6b0dd094 877 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 878 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
6b0dd094 879 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 880 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
6b0dd094 881 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 882 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
6b0dd094 883 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 884 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
6b0dd094 885 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 886 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
6b0dd094 887 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 888 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
6b0dd094 889 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 890 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
6b0dd094 891 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 892 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
6b0dd094 893 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 894 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
6b0dd094 895 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 896 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
6b0dd094 897 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 898 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
6b0dd094 899 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 900 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
6b0dd094 901 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 902 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
6b0dd094 903 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 904 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
6b0dd094 905 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 906 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
6b0dd094 907 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 908 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
6b0dd094 909 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 910 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 911 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 912 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
6b0dd094 913 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 914 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
6b0dd094 915 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 916 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
6b0dd094 917 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 918 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
6b0dd094 919 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 920 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
6b0dd094 921 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 922 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
6b0dd094 923 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6f1c2142 924 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
6b0dd094 925 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6f1c2142 926 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
6b0dd094 927 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 928 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
6b0dd094 929 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 930 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
6b0dd094 931 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 932 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
6b0dd094 933 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 934 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 935 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 936 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 937 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 938 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 939 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 940 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 941 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 942 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 943 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 944 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 945 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 946 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 947 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 948 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 949 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 950 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 951 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 952 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 953 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 954 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 955 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 956 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 957 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 958 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
6b0dd094 959 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 960 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
6b0dd094 961 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 962 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
6b0dd094 963 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 964 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
6b0dd094 965 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 966 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
6b0dd094 967 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 968 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 969
970 /* Cirrus coprocessor instructions. */
6b0dd094 971 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 972 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 973 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 974 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 975 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 976 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 977 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 978 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 979 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 980 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 981 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 982 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 983 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 984 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 985 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 986 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 987 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 988 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 989 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 990 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 991 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 992 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 993 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 994 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 995 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 996 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 997 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 998 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 999 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1000 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 1001 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1002 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 1003 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1004 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
6b0dd094 1005 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1006 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
6b0dd094 1007 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1008 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
6b0dd094 1009 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1010 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
6b0dd094 1011 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1012 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
6b0dd094 1013 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1014 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
6b0dd094 1015 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1016 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 1017 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1018 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
6b0dd094 1019 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1020 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 1021 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1022 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
6b0dd094 1023 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1024 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1025 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1026 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1027 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1028 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1029 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1030 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1031 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1032 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1033 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1034 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1035 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1036 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1037 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1038 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1039 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1040 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
6b0dd094 1041 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1042 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
6b0dd094 1043 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1044 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
6b0dd094 1045 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1046 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
6b0dd094 1047 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1048 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1049 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1050 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1051 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1052 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
6b0dd094 1053 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1054 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
6b0dd094 1055 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1056 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
6b0dd094 1057 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1058 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
6b0dd094 1059 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1060 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
6b0dd094 1061 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1062 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
6b0dd094 1063 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1064 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 1065 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1066 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 1067 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1068 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 1069 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1070 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 1071 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1072 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
6b0dd094 1073 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1074 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
6b0dd094 1075 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1076 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
6b0dd094 1077 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1078 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
6b0dd094 1079 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1080 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
6b0dd094 1081 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1082 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
6b0dd094 1083 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1084 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1085 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1086 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1087 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1088 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1089 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1090 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1091 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1092 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1093 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1094 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1095 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1096 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1097 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1098 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1099 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1100 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1101 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1102 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1103 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1104 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1105 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1106 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1107 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1108 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 1109 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1110 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 1111 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1112 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 1113 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1114 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 1115 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1116 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1117 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1118 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1119 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1120 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1121 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1122 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1123 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1124 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1125 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1126 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1127 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1128 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1129 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1130 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1131 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1132 0x0e000600, 0x0ff00f10,
1133 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1134 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1135 0x0e100600, 0x0ff00f10,
1136 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1137 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1138 0x0e200600, 0x0ff00f10,
1139 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1140 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1141 0x0e300600, 0x0ff00f10,
1142 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 1143
62f3b8c8 1144 /* VFP Fused multiply add instructions. */
6b0dd094 1145 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1146 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1147 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1148 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1149 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1150 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1151 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1152 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
6b0dd094 1153 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1154 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1155 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1156 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1157 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1158 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1159 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1160 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 1161
33399f07 1162 /* FP v5. */
6b0dd094 1163 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1164 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
6b0dd094 1165 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1166 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
6b0dd094 1167 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1168 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1169 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1170 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1171 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1172 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1173 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1174 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1175 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1176 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
6b0dd094 1177 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1178 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
6b0dd094 1179 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1180 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
6b0dd094 1181 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1182 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
6b0dd094 1183 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1184 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
6b0dd094 1185 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1186 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 1187
6b0dd094 1188 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
c28eeff2 1189 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
6b0dd094 1190 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1191 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1192 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1193 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1194 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1195 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1196 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1197 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1198 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1199 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1200 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1201 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1202 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1203 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
6b0dd094 1204 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1205 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
6b0dd094 1206 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1207 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
6b0dd094 1208 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1209 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
c28eeff2 1210
aab2c27d
MM		 1211 /* BFloat16 instructions. */
1212 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1213 0x0eb30940, 0x0fbf0f50, "vcvt%7?tb%b.bf16.f32\t%y1, %y0"},
1214
c604a79a 1215 /* Dot Product instructions in the space of coprocessor 13. */
6b0dd094 1216 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a 1217 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
6b0dd094 1218 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
aab2c27d 1219 0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
c604a79a 1220
dec41383 1221 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
6b0dd094 1222 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1223 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1224 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1225 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1226 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1227 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1228 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1229 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1230 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1231 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1232 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1233 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1234 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1235 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
6b0dd094 1236 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383
JW		 1237 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1238
b0c11777
RL		 1239 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1240 cp_num: bit <11:8> == 0b1001.
1241 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
6b0dd094 1242 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1243 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
6b0dd094 1244 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1245 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
6b0dd094 1246 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1247 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
6b0dd094 1248 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1249 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
6b0dd094 1250 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1251 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 1252 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1253 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
6b0dd094 1254 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1255 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
6b0dd094 1256 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1257 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
6b0dd094 1258 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1259 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
6b0dd094 1260 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1261 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
6b0dd094 1262 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1263 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1264 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1265 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1266 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1267 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1268 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1269 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1270 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1271 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
6b0dd094 1272 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1273 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
6b0dd094 1274 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1275 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
6b0dd094 1276 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1277 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
6b0dd094 1278 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1279 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1280 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1281 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1282 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1283 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1284 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1285 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1286 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1287 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
6b0dd094 1288 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1289 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
6b0dd094 1290 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1291 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
6b0dd094 1292 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1293 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1294 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1295 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
6b0dd094 1296 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1297 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1298 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1299 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1300 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1301 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1302 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1303 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
6b0dd094 1304 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1305 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
6b0dd094 1306 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1307 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
6b0dd094 1308 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1309 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
6b0dd094 1310 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777
RL		 1311 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1312
49e8a725 1313 /* ARMv8.3 javascript conversion instruction. */
6b0dd094 1314 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
49e8a725
SN		 1315 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1316
6b0dd094 1317 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 1318};
1319
33593eaf
MM		 1320/* Generic coprocessor instructions. These are only matched if a more specific
1321 SIMD or co-processor instruction does not match first. */
1322
1323static const struct sopcode32 generic_coprocessor_opcodes[] =
1324{
1325 /* Generic coprocessor instructions. */
1326 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1327 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
1328 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1329 0x0c500000, 0x0ff00000,
1330 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1331 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1332 0x0e000000, 0x0f000010,
1333 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1334 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1335 0x0e10f010, 0x0f10f010,
1336 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
1337 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1338 0x0e100010, 0x0f100010,
1339 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1340 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1341 0x0e000010, 0x0f100010,
1342 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1343 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1344 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
1345 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1346 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
1347
1348 /* V6 coprocessor instructions. */
1349 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1350 0xfc500000, 0xfff00000,
1351 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1352 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1353 0xfc400000, 0xfff00000,
1354 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
1355
1356 /* V5 coprocessor instructions. */
1357 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1358 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1359 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1360 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1361 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1362 0xfe000000, 0xff000010,
1363 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1364 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1365 0xfe000010, 0xff100010,
1366 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1367 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1368 0xfe100010, 0xff100010,
1369 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1370
1371 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1372};
1373
16980d0b
JB		 1374/* Neon opcode table: This does not encode the top byte -- that is
1375 checked by the print_insn_neon routine, as it depends on whether we are
1376 doing thumb32 or arm32 disassembly. */
1377
1378/* print_insn_neon recognizes the following format control codes:
1379
1380 %% %
1381
c22aaad1 1382 %c print condition code
e2efe87d
MGD		 1383 %u print condition code (unconditional in ARM mode,
1384 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 1385 %A print v{st,ld}[1234] operands
1386 %B print v{st,ld}[1234] any one operands
1387 %C print v{st,ld}[1234] single->all operands
1388 %D print scalar
1389 %E print vmov, vmvn, vorr, vbic encoded constant
1390 %F print vtbl,vtbx register list
1391
1392 %<bitfield>r print as an ARM register
1393 %<bitfield>d print the bitfield in decimal
1394 %<bitfield>e print the 2^N - bitfield in decimal
1395 %<bitfield>D print as a NEON D register
1396 %<bitfield>Q print as a NEON Q register
1397 %<bitfield>R print as a NEON D or Q register
1398 %<bitfield>Sn print byte scaled width limited by n
1399 %<bitfield>Tn print short scaled width limited by n
1400 %<bitfield>Un print long scaled width limited by n
43e65147 1401
16980d0b
JB		 1402 %<bitfield>'c print specified char iff bitfield is all ones
1403 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1404 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1405
1406static const struct opcode32 neon_opcodes[] =
1407{
fe56b6ce 1408 /* Extract. */
823d2571
TG		 1409 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1410 0xf2b00840, 0xffb00850,
1411 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1412 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1413 0xf2b00000, 0xffb00810,
1414 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 1415
9743db03
AV		 1416 /* Data transfer between ARM and NEON registers. */
1417 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1418 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1419 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1420 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1421 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1422 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1423 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1424 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1425 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1426 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1427 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1428 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1429
fe56b6ce 1430 /* Move data element to all lanes. */
823d2571
TG		 1431 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1432 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1433 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1434 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1435 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1436 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 1437
fe56b6ce 1438 /* Table lookup. */
823d2571
TG		 1439 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1440 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1441 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1442 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1443
8e79c3df 1444 /* Half-precision conversions. */
823d2571
TG		 1445 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1446 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1447 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1448 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1449
1450 /* NEON fused multiply add instructions. */
823d2571 1451 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1452 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1453 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1454 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1456 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1457 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1458 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1459
aab2c27d
MM		 1460 /* BFloat16 instructions. */
1461 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1462 0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1463 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1464 0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1465 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1466 0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1467 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1468 0xf3b60640, 0xffbf0fd0, "vcvt%c.bf16.f32\t%12-15,22D, %0-3,5Q"},
1469 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1470 0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1471 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1472 0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-2D[%3,5d]"},
1473
616ce08e
MM		 1474 /* Matrix Multiply instructions. */
1475 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1476 0xfc200c40, 0xffb00f50, "vsmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1477 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1478 0xfc200c50, 0xffb00f50, "vummla.u8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1479 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1480 0xfca00c40, 0xffb00f50, "vusmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1481 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1482 0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1483 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1484 0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1485 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1486 0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1487
fe56b6ce 1488 /* Two registers, miscellaneous. */
823d2571
TG		 1489 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1490 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1491 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1492 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1494 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1495 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1496 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1497 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1498 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1499 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1500 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1501 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1502 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1503 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1504 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1505 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1506 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1507 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1508 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1509 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1510 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1511 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1512 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1515 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1517 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1518 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1519 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1520 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1521 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1522 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1523 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1524 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1525 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1526 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1527 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1528 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1530 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1531 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1532 0xf3b20300, 0xffb30fd0,
1533 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1534 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1535 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1536 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1537 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1538 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1539 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1541 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1542 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1543 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1544 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1545 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1546 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1547 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1548 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1549 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1550 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1551 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1552 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1553 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1554 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1555 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1556 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1557 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1558 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1559 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1560 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1561 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1562 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1563 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1564 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1565 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1566 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1567 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1568 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1569 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1570 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1571 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1572 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1573 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1574 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1575 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1576 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1577 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1578 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1579 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1580 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301 1581 0xf3bb0600, 0xffbf0e10,
823d2571 1582 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1583 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1584 0xf3b70600, 0xffbf0e10,
1585 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
16980d0b 1586
fe56b6ce 1587 /* Three registers of the same length. */
823d2571
TG		 1588 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1589 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1590 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1591 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1592 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1593 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1594 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1595 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1596 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1597 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1598 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1599 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1600 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1601 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1602 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1603 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1604 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1605 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1606 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1607 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1608 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1609 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1610 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1611 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1612 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1613 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1614 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1615 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1616 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1617 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1618 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1619 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1621 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1622 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1623 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1624 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1625 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1626 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1627 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1628 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1629 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1630 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1631 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1632 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1633 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1634 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1635 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1636 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1637 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1638 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1639 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1640 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1641 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1642 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1643 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1644 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1645 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1646 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1647 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1648 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1649 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1650 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1651 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1652 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1653 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1654 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1655 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1656 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1657 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1658 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1659 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1660 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1661 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1662 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1663 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1664 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1665 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1666 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1667 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1668 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1669 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1670 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1671 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1672 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1673 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1674 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1675 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1676 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1677 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1678 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1679 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1680 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1681 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1682 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1683 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1684 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1685 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1687 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1688 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1689 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1691 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1692 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1693 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1694 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1695 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1696 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1697 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1698 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1699 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1700 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1701 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1702 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1703 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1704 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1705 0xf2000b00, 0xff800f10,
1706 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1707 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1708 0xf2000b10, 0xff800f10,
1709 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1710 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1711 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1712 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1713 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1714 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1715 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1716 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1717 0xf3000b00, 0xff800f10,
1718 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1719 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1720 0xf2000000, 0xfe800f10,
1721 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1722 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1723 0xf2000010, 0xfe800f10,
1724 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1725 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1726 0xf2000100, 0xfe800f10,
1727 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1728 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1729 0xf2000200, 0xfe800f10,
1730 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1731 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1732 0xf2000210, 0xfe800f10,
1733 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1734 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1735 0xf2000300, 0xfe800f10,
1736 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1737 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1738 0xf2000310, 0xfe800f10,
1739 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1740 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1741 0xf2000400, 0xfe800f10,
1742 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1743 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1744 0xf2000410, 0xfe800f10,
1745 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1746 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1747 0xf2000500, 0xfe800f10,
1748 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1749 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1750 0xf2000510, 0xfe800f10,
1751 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1753 0xf2000600, 0xfe800f10,
1754 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1755 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1756 0xf2000610, 0xfe800f10,
1757 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1758 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1759 0xf2000700, 0xfe800f10,
1760 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1761 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1762 0xf2000710, 0xfe800f10,
1763 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1764 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1765 0xf2000910, 0xfe800f10,
1766 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1767 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1768 0xf2000a00, 0xfe800f10,
1769 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1770 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1771 0xf2000a10, 0xfe800f10,
1772 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1773 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1774 0xf3000b10, 0xff800f10,
1775 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1776 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1777 0xf3000c10, 0xff800f10,
1778 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1779
fe56b6ce 1780 /* One register and an immediate value. */
823d2571
TG		 1781 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1782 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1783 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1784 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1785 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1786 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1787 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1788 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1789 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1790 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1791 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1792 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1793 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1794 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1795 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1796 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1797 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1798 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1799 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1800 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1801 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1802 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1803 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1804 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1805 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1806 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1807
fe56b6ce 1808 /* Two registers and a shift amount. */
823d2571
TG		 1809 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1810 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1811 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1812 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1813 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1814 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1815 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1816 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1817 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1818 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1819 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1820 0xf2880950, 0xfeb80fd0,
1821 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1822 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1823 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1824 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1825 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1826 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1827 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1828 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1829 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1830 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1831 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1832 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1833 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1834 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1835 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1836 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1837 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1838 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1839 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1840 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1841 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1842 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1843 0xf2900950, 0xfeb00fd0,
1844 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1845 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1846 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1847 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1848 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1849 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1850 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1851 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1852 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1853 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1854 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1855 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1856 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1857 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1858 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1859 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1860 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1861 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1862 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1863 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1864 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1865 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1866 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1867 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1868 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1869 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1870 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1871 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1872 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1873 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1874 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1875 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1876 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1877 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1878 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1879 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1880 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1881 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1882 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1883 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1884 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1885 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1886 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1887 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1888 0xf2a00950, 0xfea00fd0,
1889 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1890 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1891 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1892 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1893 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1894 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1895 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1896 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1897 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1898 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1899 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1900 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1901 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1902 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1903 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1904 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1905 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1906 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1907 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1908 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1909 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1910 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1911 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1912 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1913 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1914 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1915 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1916 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1917 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1918 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1919 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1920 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1921 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1922 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1923 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1924 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1925 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1926 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1927 0xf2a00e10, 0xfea00e90,
1928 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
cc933301
JW		 1929 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1930 0xf2a00c10, 0xfea00e90,
1931 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 1932
fe56b6ce 1933 /* Three registers of different lengths. */
823d2571
TG		 1934 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1935 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1936 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1937 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1938 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1939 0xf2800400, 0xff800f50,
1940 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1941 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1942 0xf2800600, 0xff800f50,
1943 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1944 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1945 0xf2800900, 0xff800f50,
1946 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1947 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1948 0xf2800b00, 0xff800f50,
1949 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1950 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1951 0xf2800d00, 0xff800f50,
1952 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1953 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1954 0xf3800400, 0xff800f50,
1955 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1956 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1957 0xf3800600, 0xff800f50,
1958 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1959 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1960 0xf2800000, 0xfe800f50,
1961 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1962 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1963 0xf2800100, 0xfe800f50,
1964 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1965 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1966 0xf2800200, 0xfe800f50,
1967 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1968 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1969 0xf2800300, 0xfe800f50,
1970 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1971 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1972 0xf2800500, 0xfe800f50,
1973 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1974 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1975 0xf2800700, 0xfe800f50,
1976 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1977 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1978 0xf2800800, 0xfe800f50,
1979 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1980 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1981 0xf2800a00, 0xfe800f50,
1982 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1983 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1984 0xf2800c00, 0xfe800f50,
1985 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 1986
fe56b6ce 1987 /* Two registers and a scalar. */
823d2571
TG		 1988 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1989 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1990 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1991 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1992 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1993 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1994 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1995 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1996 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1997 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1998 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1999 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2000 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2001 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 2002 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2003 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2004 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2005 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2006 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2007 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
2008 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2009 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 2010 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2011 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2012 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2013 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2014 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2015 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2016 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2017 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2018 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2019 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2020 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2021 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 2022 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2023 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2024 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2025 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2026 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2027 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 2028 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2029 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2030 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2031 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2032 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2033 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 2034 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2035 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2036 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2037 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2038 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2039 0xf2800240, 0xfe800f50,
2040 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2041 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2042 0xf2800640, 0xfe800f50,
2043 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2044 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2045 0xf2800a40, 0xfe800f50,
2046 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 2047 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2048 0xf2800e40, 0xff800f50,
2049 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2050 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2051 0xf2800f40, 0xff800f50,
2052 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2053 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2054 0xf3800e40, 0xff800f50,
2055 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2056 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2057 0xf3800f40, 0xff800f50,
2058 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
2059 },
16980d0b 2060
fe56b6ce 2061 /* Element and structure load/store. */
823d2571
TG		 2062 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2063 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
2064 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2065 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
2066 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2067 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
2068 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2069 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
2070 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2071 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
2072 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2073 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2074 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2075 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2076 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2077 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2078 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2079 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2080 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2081 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2082 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2083 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2084 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2085 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2086 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2087 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2088 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2089 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2090 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2091 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
2092 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2093 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
2094 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2095 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
2096 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2097 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
2098 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2099 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
2100
2101 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 2102};
2103
73cd51e5
AV		 2104/* mve opcode table. */
2105
2106/* print_insn_mve recognizes the following format control codes:
2107
2108 %% %
2109
ef1576a1
AV		 2110 %a print '+' or '-' or imm offset in vldr[bhwd] and
2111 vstr[bhwd]
9743db03 2112 %c print condition code
aef6d006
AV		 2113 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
2114 %u print 'U' (unsigned) or 'S' for various mve instructions
143275ea 2115 %i print MVE predicate(s) for vpt and vpst
23d00a41 2116 %j print a 5-bit immediate from hw2[14:12,7:6]
08132bdd 2117 %k print 48 if the 7th position bit is set else print 64.
bf0b396d 2118 %m print rounding mode for vcvt and vrint
143275ea 2119 %n print vector comparison code for predicated instruction
bf0b396d 2120 %s print size for various vcvt instructions
143275ea
AV		 2121 %v print vector predicate for instruction in predicated
2122 block
ef1576a1 2123 %o print offset scaled for vldr[hwd] and vstr[hwd]
04d54ace
AV		 2124 %w print writeback mode for MVE v{st,ld}[24]
2125 %B print v{st,ld}[24] any one operands
c507f10b
AV		 2126 %E print vmov, vmvn, vorr, vbic encoded constant
2127 %N print generic index for vmov
14925797 2128 %T print bottom ('b') or top ('t') of source register
d3b63143 2129 %X print exchange field in vmla* instructions
04d54ace 2130
9743db03 2131 %<bitfield>r print as an ARM register
04d54ace 2132 %<bitfield>d print the bitfield in decimal
d3b63143 2133 %<bitfield>A print accumulate or not
e39c1607
SD		 2134 %<bitfield>c print bitfield as a condition code
2135 %<bitfield>C print bitfield as an inverted condition code
143275ea 2136 %<bitfield>Q print as a MVE Q register
c507f10b 2137 %<bitfield>F print as a MVE S register
143275ea
AV		 2138 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
2139 UNPREDICTABLE
23d00a41
SD		 2140
2141 %<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE
143275ea 2142 %<bitfield>s print size for vector predicate & non VMOV instructions
66dcaa5d 2143 %<bitfield>I print carry flag or not
ef1576a1 2144 %<bitfield>i print immediate for vstr/vldr reg +/- imm
1c8f2df8 2145 %<bitfield>h print high half of 64-bit destination reg
bf0b396d 2146 %<bitfield>k print immediate for vector conversion instruction
1c8f2df8 2147 %<bitfield>l print low half of 64-bit destination reg
897b9bbc 2148 %<bitfield>o print rotate value for vcmul
1c8f2df8 2149 %<bitfield>u print immediate value for vddup/vdwdup
c507f10b 2150 %<bitfield>x print the bitfield in hex.
1c8f2df8 2151 */
73cd51e5
AV		 2152
2153static const struct mopcode32 mve_opcodes[] =
2154{
143275ea
AV		 2155 /* MVE. */
2156
2157 {ARM_FEATURE_COPROC (FPU_MVE),
2158 MVE_VPST,
2159 0xfe310f4d, 0xffbf1fff,
2160 "vpst%i"
2161 },
2162
2163 /* Floating point VPT T1. */
2164 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2165 MVE_VPT_FP_T1,
2166 0xee310f00, 0xefb10f50,
2167 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2168 /* Floating point VPT T2. */
2169 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2170 MVE_VPT_FP_T2,
2171 0xee310f40, 0xefb10f50,
2172 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2173
2174 /* Vector VPT T1. */
2175 {ARM_FEATURE_COPROC (FPU_MVE),
2176 MVE_VPT_VEC_T1,
2177 0xfe010f00, 0xff811f51,
2178 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2179 /* Vector VPT T2. */
2180 {ARM_FEATURE_COPROC (FPU_MVE),
2181 MVE_VPT_VEC_T2,
2182 0xfe010f01, 0xff811f51,
2183 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2184 /* Vector VPT T3. */
2185 {ARM_FEATURE_COPROC (FPU_MVE),
2186 MVE_VPT_VEC_T3,
2187 0xfe011f00, 0xff811f50,
2188 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2189 /* Vector VPT T4. */
2190 {ARM_FEATURE_COPROC (FPU_MVE),
2191 MVE_VPT_VEC_T4,
2192 0xfe010f40, 0xff811f70,
2193 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2194 /* Vector VPT T5. */
2195 {ARM_FEATURE_COPROC (FPU_MVE),
2196 MVE_VPT_VEC_T5,
2197 0xfe010f60, 0xff811f70,
2198 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2199 /* Vector VPT T6. */
2200 {ARM_FEATURE_COPROC (FPU_MVE),
2201 MVE_VPT_VEC_T6,
2202 0xfe011f40, 0xff811f50,
2203 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2204
c507f10b
AV		 2205 /* Vector VBIC immediate. */
2206 {ARM_FEATURE_COPROC (FPU_MVE),
2207 MVE_VBIC_IMM,
2208 0xef800070, 0xefb81070,
2209 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2210
2211 /* Vector VBIC register. */
2212 {ARM_FEATURE_COPROC (FPU_MVE),
2213 MVE_VBIC_REG,
2214 0xef100150, 0xffb11f51,
2215 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2216
66dcaa5d
AV		 2217 /* Vector VABAV. */
2218 {ARM_FEATURE_COPROC (FPU_MVE),
2219 MVE_VABAV,
2220 0xee800f01, 0xefc10f51,
2221 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2222
2223 /* Vector VABD floating point. */
2224 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2225 MVE_VABD_FP,
2226 0xff200d40, 0xffa11f51,
2227 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2228
2229 /* Vector VABD. */
2230 {ARM_FEATURE_COPROC (FPU_MVE),
2231 MVE_VABD_VEC,
2232 0xef000740, 0xef811f51,
2233 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2234
2235 /* Vector VABS floating point. */
2236 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2237 MVE_VABS_FP,
2238 0xFFB10740, 0xFFB31FD1,
2239 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2240 /* Vector VABS. */
2241 {ARM_FEATURE_COPROC (FPU_MVE),
2242 MVE_VABS_VEC,
2243 0xffb10340, 0xffb31fd1,
2244 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2245
2246 /* Vector VADD floating point T1. */
2247 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2248 MVE_VADD_FP_T1,
2249 0xef000d40, 0xffa11f51,
2250 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2251 /* Vector VADD floating point T2. */
2252 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2253 MVE_VADD_FP_T2,
2254 0xee300f40, 0xefb11f70,
2255 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2256 /* Vector VADD T1. */
2257 {ARM_FEATURE_COPROC (FPU_MVE),
2258 MVE_VADD_VEC_T1,
2259 0xef000840, 0xff811f51,
2260 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2261 /* Vector VADD T2. */
2262 {ARM_FEATURE_COPROC (FPU_MVE),
2263 MVE_VADD_VEC_T2,
2264 0xee010f40, 0xff811f70,
2265 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2266
d3b63143
AV		 2267 /* Vector VADDLV. */
2268 {ARM_FEATURE_COPROC (FPU_MVE),
2269 MVE_VADDLV,
2270 0xee890f00, 0xef8f1fd1,
2271 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2272
2273 /* Vector VADDV. */
2274 {ARM_FEATURE_COPROC (FPU_MVE),
2275 MVE_VADDV,
2276 0xeef10f00, 0xeff31fd1,
2277 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2278
66dcaa5d
AV		 2279 /* Vector VADC. */
2280 {ARM_FEATURE_COPROC (FPU_MVE),
2281 MVE_VADC,
2282 0xee300f00, 0xffb10f51,
2283 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2284
e523f101
AV		 2285 /* Vector VAND. */
2286 {ARM_FEATURE_COPROC (FPU_MVE),
2287 MVE_VAND,
2288 0xef000150, 0xffb11f51,
2289 "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2290
2291 /* Vector VBRSR register. */
2292 {ARM_FEATURE_COPROC (FPU_MVE),
2293 MVE_VBRSR,
2294 0xfe011e60, 0xff811f70,
2295 "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2296
897b9bbc
AV		 2297 /* Vector VCADD floating point. */
2298 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2299 MVE_VCADD_FP,
2300 0xfc800840, 0xfea11f51,
2301 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2302
2303 /* Vector VCADD. */
2304 {ARM_FEATURE_COPROC (FPU_MVE),
2305 MVE_VCADD_VEC,
2306 0xfe000f00, 0xff810f51,
2307 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2308
e523f101
AV		 2309 /* Vector VCLS. */
2310 {ARM_FEATURE_COPROC (FPU_MVE),
2311 MVE_VCLS,
2312 0xffb00440, 0xffb31fd1,
2313 "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2314
2315 /* Vector VCLZ. */
2316 {ARM_FEATURE_COPROC (FPU_MVE),
2317 MVE_VCLZ,
2318 0xffb004c0, 0xffb31fd1,
2319 "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2320
897b9bbc
AV		 2321 /* Vector VCMLA. */
2322 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2323 MVE_VCMLA_FP,
2324 0xfc200840, 0xfe211f51,
2325 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2326
143275ea
AV		 2327 /* Vector VCMP floating point T1. */
2328 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2329 MVE_VCMP_FP_T1,
2330 0xee310f00, 0xeff1ef50,
2331 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2332
2333 /* Vector VCMP floating point T2. */
2334 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2335 MVE_VCMP_FP_T2,
2336 0xee310f40, 0xeff1ef50,
2337 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2338
2339 /* Vector VCMP T1. */
2340 {ARM_FEATURE_COPROC (FPU_MVE),
2341 MVE_VCMP_VEC_T1,
2342 0xfe010f00, 0xffc1ff51,
2343 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2344 /* Vector VCMP T2. */
2345 {ARM_FEATURE_COPROC (FPU_MVE),
2346 MVE_VCMP_VEC_T2,
2347 0xfe010f01, 0xffc1ff51,
2348 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2349 /* Vector VCMP T3. */
2350 {ARM_FEATURE_COPROC (FPU_MVE),
2351 MVE_VCMP_VEC_T3,
2352 0xfe011f00, 0xffc1ff50,
2353 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2354 /* Vector VCMP T4. */
2355 {ARM_FEATURE_COPROC (FPU_MVE),
2356 MVE_VCMP_VEC_T4,
2357 0xfe010f40, 0xffc1ff70,
2358 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2359 /* Vector VCMP T5. */
2360 {ARM_FEATURE_COPROC (FPU_MVE),
2361 MVE_VCMP_VEC_T5,
2362 0xfe010f60, 0xffc1ff70,
2363 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2364 /* Vector VCMP T6. */
2365 {ARM_FEATURE_COPROC (FPU_MVE),
2366 MVE_VCMP_VEC_T6,
2367 0xfe011f40, 0xffc1ff50,
2368 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2369
9743db03
AV		 2370 /* Vector VDUP. */
2371 {ARM_FEATURE_COPROC (FPU_MVE),
2372 MVE_VDUP,
2373 0xeea00b10, 0xffb10f5f,
2374 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2375
2376 /* Vector VEOR. */
2377 {ARM_FEATURE_COPROC (FPU_MVE),
2378 MVE_VEOR,
2379 0xff000150, 0xffd11f51,
2380 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2381
2382 /* Vector VFMA, vector * scalar. */
2383 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2384 MVE_VFMA_FP_SCALAR,
2385 0xee310e40, 0xefb11f70,
2386 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2387
2388 /* Vector VFMA floating point. */
2389 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2390 MVE_VFMA_FP,
2391 0xef000c50, 0xffa11f51,
2392 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2393
2394 /* Vector VFMS floating point. */
2395 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2396 MVE_VFMS_FP,
2397 0xef200c50, 0xffa11f51,
2398 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2399
2400 /* Vector VFMAS, vector * scalar. */
2401 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2402 MVE_VFMAS_FP_SCALAR,
2403 0xee311e40, 0xefb11f70,
2404 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2405
2406 /* Vector VHADD T1. */
2407 {ARM_FEATURE_COPROC (FPU_MVE),
2408 MVE_VHADD_T1,
2409 0xef000040, 0xef811f51,
2410 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2411
2412 /* Vector VHADD T2. */
2413 {ARM_FEATURE_COPROC (FPU_MVE),
2414 MVE_VHADD_T2,
2415 0xee000f40, 0xef811f70,
2416 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2417
2418 /* Vector VHSUB T1. */
2419 {ARM_FEATURE_COPROC (FPU_MVE),
2420 MVE_VHSUB_T1,
2421 0xef000240, 0xef811f51,
2422 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2423
2424 /* Vector VHSUB T2. */
2425 {ARM_FEATURE_COPROC (FPU_MVE),
2426 MVE_VHSUB_T2,
2427 0xee001f40, 0xef811f70,
2428 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2429
897b9bbc
AV		 2430 /* Vector VCMUL. */
2431 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2432 MVE_VCMUL_FP,
2433 0xee300e00, 0xefb10f50,
2434 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2435
e523f101
AV		 2436 /* Vector VCTP. */
2437 {ARM_FEATURE_COPROC (FPU_MVE),
2438 MVE_VCTP,
2439 0xf000e801, 0xffc0ffff,
2440 "vctp%v.%20-21s\t%16-19r"},
2441
9743db03
AV		 2442 /* Vector VDUP. */
2443 {ARM_FEATURE_COPROC (FPU_MVE),
2444 MVE_VDUP,
2445 0xeea00b10, 0xffb10f5f,
2446 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2447
2448 /* Vector VRHADD. */
2449 {ARM_FEATURE_COPROC (FPU_MVE),
2450 MVE_VRHADD,
2451 0xef000140, 0xef811f51,
2452 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2453
bf0b396d
AV		 2454 /* Vector VCVT. */
2455 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2456 MVE_VCVT_FP_FIX_VEC,
2457 0xef800c50, 0xef801cd1,
2458 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2459
2460 /* Vector VCVT. */
2461 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2462 MVE_VCVT_BETWEEN_FP_INT,
2463 0xffb30640, 0xffb31e51,
2464 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2465
2466 /* Vector VCVT between single and half-precision float, bottom half. */
2467 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2468 MVE_VCVT_FP_HALF_FP,
2469 0xee3f0e01, 0xefbf1fd1,
2470 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2471
2472 /* Vector VCVT between single and half-precision float, top half. */
2473 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2474 MVE_VCVT_FP_HALF_FP,
2475 0xee3f1e01, 0xefbf1fd1,
2476 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2477
2478 /* Vector VCVT. */
2479 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2480 MVE_VCVT_FROM_FP_TO_INT,
2481 0xffb30040, 0xffb31c51,
2482 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2483
1c8f2df8
AV		 2484 /* Vector VDDUP. */
2485 {ARM_FEATURE_COPROC (FPU_MVE),
2486 MVE_VDDUP,
2487 0xee011f6e, 0xff811f7e,
2488 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2489
2490 /* Vector VDWDUP. */
2491 {ARM_FEATURE_COPROC (FPU_MVE),
2492 MVE_VDWDUP,
2493 0xee011f60, 0xff811f70,
2494 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2495
897b9bbc
AV		 2496 /* Vector VHCADD. */
2497 {ARM_FEATURE_COPROC (FPU_MVE),
2498 MVE_VHCADD,
2499 0xee000f00, 0xff810f51,
2500 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2501
1c8f2df8
AV		 2502 /* Vector VIWDUP. */
2503 {ARM_FEATURE_COPROC (FPU_MVE),
2504 MVE_VIWDUP,
2505 0xee010f60, 0xff811f70,
2506 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2507
2508 /* Vector VIDUP. */
2509 {ARM_FEATURE_COPROC (FPU_MVE),
2510 MVE_VIDUP,
2511 0xee010f6e, 0xff811f7e,
2512 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2513
04d54ace
AV		 2514 /* Vector VLD2. */
2515 {ARM_FEATURE_COPROC (FPU_MVE),
2516 MVE_VLD2,
2517 0xfc901e00, 0xff901e5f,
2518 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2519
2520 /* Vector VLD4. */
2521 {ARM_FEATURE_COPROC (FPU_MVE),
2522 MVE_VLD4,
2523 0xfc901e01, 0xff901e1f,
2524 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2525
ef1576a1
AV		 2526 /* Vector VLDRB gather load. */
2527 {ARM_FEATURE_COPROC (FPU_MVE),
2528 MVE_VLDRB_GATHER_T1,
2529 0xec900e00, 0xefb01e50,
2530 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2531
2532 /* Vector VLDRH gather load. */
2533 {ARM_FEATURE_COPROC (FPU_MVE),
2534 MVE_VLDRH_GATHER_T2,
2535 0xec900e10, 0xefb01e50,
2536 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2537
2538 /* Vector VLDRW gather load. */
2539 {ARM_FEATURE_COPROC (FPU_MVE),
2540 MVE_VLDRW_GATHER_T3,
2541 0xfc900f40, 0xffb01fd0,
2542 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2543
2544 /* Vector VLDRD gather load. */
2545 {ARM_FEATURE_COPROC (FPU_MVE),
2546 MVE_VLDRD_GATHER_T4,
2547 0xec900fd0, 0xefb01fd0,
2548 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2549
2550 /* Vector VLDRW gather load. */
2551 {ARM_FEATURE_COPROC (FPU_MVE),
2552 MVE_VLDRW_GATHER_T5,
2553 0xfd101e00, 0xff111f00,
2554 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2555
2556 /* Vector VLDRD gather load, variant T6. */
2557 {ARM_FEATURE_COPROC (FPU_MVE),
2558 MVE_VLDRD_GATHER_T6,
2559 0xfd101f00, 0xff111f00,
2560 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2561
aef6d006
AV		 2562 /* Vector VLDRB. */
2563 {ARM_FEATURE_COPROC (FPU_MVE),
2564 MVE_VLDRB_T1,
2565 0xec100e00, 0xee581e00,
2566 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2567
2568 /* Vector VLDRH. */
2569 {ARM_FEATURE_COPROC (FPU_MVE),
2570 MVE_VLDRH_T2,
2571 0xec180e00, 0xee581e00,
2572 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2573
2574 /* Vector VLDRB unsigned, variant T5. */
2575 {ARM_FEATURE_COPROC (FPU_MVE),
2576 MVE_VLDRB_T5,
2577 0xec101e00, 0xfe101f80,
2578 "vldrb%v.u8\t%13-15,22Q, %d"},
2579
2580 /* Vector VLDRH unsigned, variant T6. */
2581 {ARM_FEATURE_COPROC (FPU_MVE),
2582 MVE_VLDRH_T6,
2583 0xec101e80, 0xfe101f80,
2584 "vldrh%v.u16\t%13-15,22Q, %d"},
2585
2586 /* Vector VLDRW unsigned, variant T7. */
2587 {ARM_FEATURE_COPROC (FPU_MVE),
2588 MVE_VLDRW_T7,
2589 0xec101f00, 0xfe101f80,
2590 "vldrw%v.u32\t%13-15,22Q, %d"},
2591
56858bea
AV		 2592 /* Vector VMAX. */
2593 {ARM_FEATURE_COPROC (FPU_MVE),
2594 MVE_VMAX,
2595 0xef000640, 0xef811f51,
2596 "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2597
2598 /* Vector VMAXA. */
2599 {ARM_FEATURE_COPROC (FPU_MVE),
2600 MVE_VMAXA,
2601 0xee330e81, 0xffb31fd1,
2602 "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2603
2604 /* Vector VMAXNM floating point. */
2605 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2606 MVE_VMAXNM_FP,
2607 0xff000f50, 0xffa11f51,
2608 "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2609
2610 /* Vector VMAXNMA floating point. */
2611 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2612 MVE_VMAXNMA_FP,
2613 0xee3f0e81, 0xefbf1fd1,
2614 "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2615
2616 /* Vector VMAXNMV floating point. */
2617 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2618 MVE_VMAXNMV_FP,
2619 0xeeee0f00, 0xefff0fd1,
2620 "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2621
2622 /* Vector VMAXNMAV floating point. */
2623 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2624 MVE_VMAXNMAV_FP,
2625 0xeeec0f00, 0xefff0fd1,
2626 "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2627
2628 /* Vector VMAXV. */
2629 {ARM_FEATURE_COPROC (FPU_MVE),
2630 MVE_VMAXV,
2631 0xeee20f00, 0xeff30fd1,
2632 "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2633
2634 /* Vector VMAXAV. */
2635 {ARM_FEATURE_COPROC (FPU_MVE),
2636 MVE_VMAXAV,
2637 0xeee00f00, 0xfff30fd1,
2638 "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2639
2640 /* Vector VMIN. */
2641 {ARM_FEATURE_COPROC (FPU_MVE),
2642 MVE_VMIN,
2643 0xef000650, 0xef811f51,
2644 "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2645
2646 /* Vector VMINA. */
2647 {ARM_FEATURE_COPROC (FPU_MVE),
2648 MVE_VMINA,
2649 0xee331e81, 0xffb31fd1,
2650 "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2651
2652 /* Vector VMINNM floating point. */
2653 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2654 MVE_VMINNM_FP,
2655 0xff200f50, 0xffa11f51,
2656 "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2657
2658 /* Vector VMINNMA floating point. */
2659 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2660 MVE_VMINNMA_FP,
2661 0xee3f1e81, 0xefbf1fd1,
2662 "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2663
2664 /* Vector VMINNMV floating point. */
2665 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2666 MVE_VMINNMV_FP,
2667 0xeeee0f80, 0xefff0fd1,
2668 "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2669
2670 /* Vector VMINNMAV floating point. */
2671 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2672 MVE_VMINNMAV_FP,
2673 0xeeec0f80, 0xefff0fd1,
2674 "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2675
2676 /* Vector VMINV. */
2677 {ARM_FEATURE_COPROC (FPU_MVE),
2678 MVE_VMINV,
2679 0xeee20f80, 0xeff30fd1,
2680 "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2681
2682 /* Vector VMINAV. */
2683 {ARM_FEATURE_COPROC (FPU_MVE),
2684 MVE_VMINAV,
2685 0xeee00f80, 0xfff30fd1,
2686 "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2687
2688 /* Vector VMLA. */
2689 {ARM_FEATURE_COPROC (FPU_MVE),
2690 MVE_VMLA,
2691 0xee010e40, 0xef811f70,
2692 "vmla%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2693
d3b63143
AV		 2694 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2695 opcode aliasing. */
2696 {ARM_FEATURE_COPROC (FPU_MVE),
2697 MVE_VMLALDAV,
2698 0xee801e00, 0xef801f51,
2699 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2700
2701 {ARM_FEATURE_COPROC (FPU_MVE),
2702 MVE_VMLALDAV,
2703 0xee800e00, 0xef801f51,
2704 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2705
2706 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2707 {ARM_FEATURE_COPROC (FPU_MVE),
2708 MVE_VMLADAV_T1,
2709 0xeef00e00, 0xeff01f51,
2710 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2711
2712 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2713 {ARM_FEATURE_COPROC (FPU_MVE),
2714 MVE_VMLADAV_T2,
2715 0xeef00f00, 0xeff11f51,
2716 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2717
2718 /* Vector VMLADAV T1 variant. */
2719 {ARM_FEATURE_COPROC (FPU_MVE),
2720 MVE_VMLADAV_T1,
2721 0xeef01e00, 0xeff01f51,
2722 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2723
2724 /* Vector VMLADAV T2 variant. */
2725 {ARM_FEATURE_COPROC (FPU_MVE),
2726 MVE_VMLADAV_T2,
2727 0xeef01f00, 0xeff11f51,
2728 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2729
2730 /* Vector VMLAS. */
2731 {ARM_FEATURE_COPROC (FPU_MVE),
2732 MVE_VMLAS,
2733 0xee011e40, 0xef811f70,
2734 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2735
2736 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2737 opcode aliasing. */
2738 {ARM_FEATURE_COPROC (FPU_MVE),
2739 MVE_VRMLSLDAVH,
2740 0xfe800e01, 0xff810f51,
2741 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2742
2743 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2744 opcdoe aliasing. */
2745 {ARM_FEATURE_COPROC (FPU_MVE),
2746 MVE_VMLSLDAV,
2747 0xee800e01, 0xff800f51,
2748 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2749
2750 /* Vector VMLSDAV T1 Variant. */
2751 {ARM_FEATURE_COPROC (FPU_MVE),
2752 MVE_VMLSDAV_T1,
2753 0xeef00e01, 0xfff00f51,
2754 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2755
2756 /* Vector VMLSDAV T2 Variant. */
2757 {ARM_FEATURE_COPROC (FPU_MVE),
2758 MVE_VMLSDAV_T2,
2759 0xfef00e01, 0xfff10f51,
2760 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2761
c507f10b
AV		 2762 /* Vector VMOV between gpr and half precision register, op == 0. */
2763 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2764 MVE_VMOV_HFP_TO_GP,
2765 0xee000910, 0xfff00f7f,
2766 "vmov.f16\t%7,16-19F, %12-15r"},
2767
2768 /* Vector VMOV between gpr and half precision register, op == 1. */
2769 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2770 MVE_VMOV_HFP_TO_GP,
2771 0xee100910, 0xfff00f7f,
2772 "vmov.f16\t%12-15r, %7,16-19F"},
2773
2774 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2775 MVE_VMOV_GP_TO_VEC_LANE,
2776 0xee000b10, 0xff900f1f,
2777 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2778
2779 /* Vector VORR immediate to vector.
2780 NOTE: MVE_VORR_IMM must appear in the table
2781 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2782 {ARM_FEATURE_COPROC (FPU_MVE),
2783 MVE_VORR_IMM,
2784 0xef800050, 0xefb810f0,
2785 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2786
ed63aa17
AV		 2787 /* Vector VQSHL T2 Variant.
2788 NOTE: MVE_VQSHL_T2 must appear in the table before
2789 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2790 {ARM_FEATURE_COPROC (FPU_MVE),
2791 MVE_VQSHL_T2,
2792 0xef800750, 0xef801fd1,
2793 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2794
2795 /* Vector VQSHLU T3 Variant
2796 NOTE: MVE_VQSHL_T2 must appear in the table before
2797 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2798
2799 {ARM_FEATURE_COPROC (FPU_MVE),
2800 MVE_VQSHLU_T3,
2801 0xff800650, 0xff801fd1,
2802 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2803
2804 /* Vector VRSHR
2805 NOTE: MVE_VRSHR must appear in the table before
2806 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2807 {ARM_FEATURE_COPROC (FPU_MVE),
2808 MVE_VRSHR,
2809 0xef800250, 0xef801fd1,
2810 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2811
2812 /* Vector VSHL.
2813 NOTE: MVE_VSHL must appear in the table before
2814 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2815 {ARM_FEATURE_COPROC (FPU_MVE),
2816 MVE_VSHL_T1,
2817 0xef800550, 0xff801fd1,
2818 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2819
2820 /* Vector VSHR
2821 NOTE: MVE_VSHR must appear in the table before
2822 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2823 {ARM_FEATURE_COPROC (FPU_MVE),
2824 MVE_VSHR,
2825 0xef800050, 0xef801fd1,
2826 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2827
2828 /* Vector VSLI
2829 NOTE: MVE_VSLI must appear in the table before
2830 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2831 {ARM_FEATURE_COPROC (FPU_MVE),
2832 MVE_VSLI,
2833 0xff800550, 0xff801fd1,
2834 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2835
2836 /* Vector VSRI
2837 NOTE: MVE_VSRI must appear in the table before
2838 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2839 {ARM_FEATURE_COPROC (FPU_MVE),
2840 MVE_VSRI,
2841 0xff800450, 0xff801fd1,
2842 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2843
c507f10b 2844 /* Vector VMOV immediate to vector,
ce760a76 2845 undefinded for cmode == 1111 */
c507f10b 2846 {ARM_FEATURE_COPROC (FPU_MVE),
ce760a76
MI		 2847 MVE_VMVN_IMM, 0xef800f70, 0xefb81ff0, UNDEFINED_INSTRUCTION},
2848
2849 /* Vector VMOV immediate to vector,
2850 cmode == 1101 */
2851 {ARM_FEATURE_COPROC (FPU_MVE),
2852 MVE_VMOV_IMM_TO_VEC, 0xef800d50, 0xefb81fd0,
2853 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
c507f10b
AV		 2854
2855 /* Vector VMOV immediate to vector. */
2856 {ARM_FEATURE_COPROC (FPU_MVE),
2857 MVE_VMOV_IMM_TO_VEC,
2858 0xef800050, 0xefb810d0,
2859 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2860
2861 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2862 {ARM_FEATURE_COPROC (FPU_MVE),
2863 MVE_VMOV2_VEC_LANE_TO_GP,
2864 0xec000f00, 0xffb01ff0,
2865 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2866
2867 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2868 {ARM_FEATURE_COPROC (FPU_MVE),
2869 MVE_VMOV2_VEC_LANE_TO_GP,
2870 0xec000f10, 0xffb01ff0,
2871 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2872
2873 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2874 {ARM_FEATURE_COPROC (FPU_MVE),
2875 MVE_VMOV2_GP_TO_VEC_LANE,
2876 0xec100f00, 0xffb01ff0,
2877 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2878
2879 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2880 {ARM_FEATURE_COPROC (FPU_MVE),
2881 MVE_VMOV2_GP_TO_VEC_LANE,
2882 0xec100f10, 0xffb01ff0,
2883 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2884
2885 /* Vector VMOV Vector lane to gpr. */
2886 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2887 MVE_VMOV_VEC_LANE_TO_GP,
2888 0xee100b10, 0xff100f1f,
2889 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2890
ed63aa17
AV		 2891 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
2892 to instruction opcode aliasing. */
2893 {ARM_FEATURE_COPROC (FPU_MVE),
2894 MVE_VSHLL_T1,
2895 0xeea00f40, 0xefa00fd1,
2896 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2897
14925797
AV		 2898 /* Vector VMOVL long. */
2899 {ARM_FEATURE_COPROC (FPU_MVE),
2900 MVE_VMOVL,
2901 0xeea00f40, 0xefa70fd1,
2902 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2903
2904 /* Vector VMOV and narrow. */
2905 {ARM_FEATURE_COPROC (FPU_MVE),
2906 MVE_VMOVN,
2907 0xfe310e81, 0xffb30fd1,
2908 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2909
c507f10b
AV		 2910 /* Floating point move extract. */
2911 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2912 MVE_VMOVX,
2913 0xfeb00a40, 0xffbf0fd0,
2914 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2915
f49bb598
AV		 2916 /* Vector VMUL floating-point T1 variant. */
2917 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2918 MVE_VMUL_FP_T1,
2919 0xff000d50, 0xffa11f51,
2920 "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2921
2922 /* Vector VMUL floating-point T2 variant. */
2923 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2924 MVE_VMUL_FP_T2,
2925 0xee310e60, 0xefb11f70,
2926 "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2927
2928 /* Vector VMUL T1 variant. */
2929 {ARM_FEATURE_COPROC (FPU_MVE),
2930 MVE_VMUL_VEC_T1,
2931 0xef000950, 0xff811f51,
2932 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2933
2934 /* Vector VMUL T2 variant. */
2935 {ARM_FEATURE_COPROC (FPU_MVE),
2936 MVE_VMUL_VEC_T2,
2937 0xee011e60, 0xff811f70,
2938 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2939
2940 /* Vector VMULH. */
2941 {ARM_FEATURE_COPROC (FPU_MVE),
2942 MVE_VMULH,
2943 0xee010e01, 0xef811f51,
2944 "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2945
2946 /* Vector VRMULH. */
2947 {ARM_FEATURE_COPROC (FPU_MVE),
2948 MVE_VRMULH,
2949 0xee011e01, 0xef811f51,
2950 "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2951
14925797
AV		 2952 /* Vector VMULL integer. */
2953 {ARM_FEATURE_COPROC (FPU_MVE),
2954 MVE_VMULL_INT,
2955 0xee010e00, 0xef810f51,
2956 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2957
2958 /* Vector VMULL polynomial. */
2959 {ARM_FEATURE_COPROC (FPU_MVE),
2960 MVE_VMULL_POLY,
2961 0xee310e00, 0xefb10f51,
2962 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2963
c507f10b
AV		 2964 /* Vector VMVN immediate to vector. */
2965 {ARM_FEATURE_COPROC (FPU_MVE),
2966 MVE_VMVN_IMM,
2967 0xef800070, 0xefb810f0,
2968 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2969
2970 /* Vector VMVN register. */
2971 {ARM_FEATURE_COPROC (FPU_MVE),
2972 MVE_VMVN_REG,
2973 0xffb005c0, 0xffbf1fd1,
2974 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2975
f49bb598
AV		 2976 /* Vector VNEG floating point. */
2977 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2978 MVE_VNEG_FP,
2979 0xffb107c0, 0xffb31fd1,
2980 "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2981
2982 /* Vector VNEG. */
2983 {ARM_FEATURE_COPROC (FPU_MVE),
2984 MVE_VNEG_VEC,
2985 0xffb103c0, 0xffb31fd1,
2986 "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2987
c507f10b
AV		 2988 /* Vector VORN, vector bitwise or not. */
2989 {ARM_FEATURE_COPROC (FPU_MVE),
2990 MVE_VORN,
2991 0xef300150, 0xffb11f51,
2992 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2993
2994 /* Vector VORR register. */
2995 {ARM_FEATURE_COPROC (FPU_MVE),
2996 MVE_VORR_REG,
2997 0xef200150, 0xffb11f51,
2998 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2999
c4a23bf8
SP		 3000 /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if
3001 "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen
3002 MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes
3003 array. */
3004
3005 {ARM_FEATURE_COPROC (FPU_MVE),
3006 MVE_VMOV_VEC_TO_VEC,
3007 0xef200150, 0xffb11f51,
3008 "vmov%v\t%13-15,22Q, %17-19,7Q"},
3009
14925797
AV		 3010 /* Vector VQDMULL T1 variant. */
3011 {ARM_FEATURE_COPROC (FPU_MVE),
3012 MVE_VQDMULL_T1,
3013 0xee300f01, 0xefb10f51,
3014 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3015
14b456f2
AV		 3016 /* Vector VPNOT. */
3017 {ARM_FEATURE_COPROC (FPU_MVE),
3018 MVE_VPNOT,
3019 0xfe310f4d, 0xffffffff,
3020 "vpnot%v"},
3021
3022 /* Vector VPSEL. */
3023 {ARM_FEATURE_COPROC (FPU_MVE),
3024 MVE_VPSEL,
3025 0xfe310f01, 0xffb11f51,
3026 "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3027
3028 /* Vector VQABS. */
3029 {ARM_FEATURE_COPROC (FPU_MVE),
3030 MVE_VQABS,
3031 0xffb00740, 0xffb31fd1,
3032 "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3033
3034 /* Vector VQADD T1 variant. */
3035 {ARM_FEATURE_COPROC (FPU_MVE),
3036 MVE_VQADD_T1,
3037 0xef000050, 0xef811f51,
3038 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3039
3040 /* Vector VQADD T2 variant. */
3041 {ARM_FEATURE_COPROC (FPU_MVE),
3042 MVE_VQADD_T2,
3043 0xee000f60, 0xef811f70,
3044 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3045
14925797
AV		 3046 /* Vector VQDMULL T2 variant. */
3047 {ARM_FEATURE_COPROC (FPU_MVE),
3048 MVE_VQDMULL_T2,
3049 0xee300f60, 0xefb10f70,
3050 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3051
3052 /* Vector VQMOVN. */
3053 {ARM_FEATURE_COPROC (FPU_MVE),
3054 MVE_VQMOVN,
3055 0xee330e01, 0xefb30fd1,
3056 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
3057
3058 /* Vector VQMOVUN. */
3059 {ARM_FEATURE_COPROC (FPU_MVE),
3060 MVE_VQMOVUN,
3061 0xee310e81, 0xffb30fd1,
3062 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3063
d3b63143
AV		 3064 /* Vector VQDMLADH. */
3065 {ARM_FEATURE_COPROC (FPU_MVE),
3066 MVE_VQDMLADH,
3067 0xee000e00, 0xff810f51,
3068 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3069
3070 /* Vector VQRDMLADH. */
3071 {ARM_FEATURE_COPROC (FPU_MVE),
3072 MVE_VQRDMLADH,
3073 0xee000e01, 0xff810f51,
3074 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3075
3076 /* Vector VQDMLAH. */
3077 {ARM_FEATURE_COPROC (FPU_MVE),
3078 MVE_VQDMLAH,
23d188c7 3079 0xee000e60, 0xff811f70,
d3b63143
AV		 3080 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3081
3082 /* Vector VQRDMLAH. */
3083 {ARM_FEATURE_COPROC (FPU_MVE),
3084 MVE_VQRDMLAH,
23d188c7 3085 0xee000e40, 0xff811f70,
d3b63143
AV		 3086 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3087
3088 /* Vector VQDMLASH. */
3089 {ARM_FEATURE_COPROC (FPU_MVE),
3090 MVE_VQDMLASH,
23d188c7 3091 0xee001e60, 0xff811f70,
d3b63143
AV		 3092 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3093
3094 /* Vector VQRDMLASH. */
3095 {ARM_FEATURE_COPROC (FPU_MVE),
3096 MVE_VQRDMLASH,
23d188c7 3097 0xee001e40, 0xff811f70,
d3b63143
AV		 3098 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3099
3100 /* Vector VQDMLSDH. */
3101 {ARM_FEATURE_COPROC (FPU_MVE),
3102 MVE_VQDMLSDH,
3103 0xfe000e00, 0xff810f51,
3104 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3105
3106 /* Vector VQRDMLSDH. */
3107 {ARM_FEATURE_COPROC (FPU_MVE),
3108 MVE_VQRDMLSDH,
3109 0xfe000e01, 0xff810f51,
3110 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3111
3112 /* Vector VQDMULH T1 variant. */
3113 {ARM_FEATURE_COPROC (FPU_MVE),
3114 MVE_VQDMULH_T1,
3115 0xef000b40, 0xff811f51,
3116 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3117
3118 /* Vector VQRDMULH T2 variant. */
3119 {ARM_FEATURE_COPROC (FPU_MVE),
3120 MVE_VQRDMULH_T2,
3121 0xff000b40, 0xff811f51,
3122 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3123
3124 /* Vector VQDMULH T3 variant. */
3125 {ARM_FEATURE_COPROC (FPU_MVE),
3126 MVE_VQDMULH_T3,
3127 0xee010e60, 0xff811f70,
3128 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3129
3130 /* Vector VQRDMULH T4 variant. */
3131 {ARM_FEATURE_COPROC (FPU_MVE),
3132 MVE_VQRDMULH_T4,
3133 0xfe010e60, 0xff811f70,
3134 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3135
14b456f2
AV		 3136 /* Vector VQNEG. */
3137 {ARM_FEATURE_COPROC (FPU_MVE),
3138 MVE_VQNEG,
3139 0xffb007c0, 0xffb31fd1,
3140 "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3141
ed63aa17
AV		 3142 /* Vector VQRSHL T1 variant. */
3143 {ARM_FEATURE_COPROC (FPU_MVE),
3144 MVE_VQRSHL_T1,
3145 0xef000550, 0xef811f51,
3146 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3147
3148 /* Vector VQRSHL T2 variant. */
3149 {ARM_FEATURE_COPROC (FPU_MVE),
3150 MVE_VQRSHL_T2,
3151 0xee331ee0, 0xefb31ff0,
3152 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3153
3154 /* Vector VQRSHRN. */
3155 {ARM_FEATURE_COPROC (FPU_MVE),
3156 MVE_VQRSHRN,
3157 0xee800f41, 0xefa00fd1,
3158 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3159
3160 /* Vector VQRSHRUN. */
3161 {ARM_FEATURE_COPROC (FPU_MVE),
3162 MVE_VQRSHRUN,
3163 0xfe800fc0, 0xffa00fd1,
3164 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3165
3166 /* Vector VQSHL T1 Variant. */
3167 {ARM_FEATURE_COPROC (FPU_MVE),
3168 MVE_VQSHL_T1,
3169 0xee311ee0, 0xefb31ff0,
3170 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3171
3172 /* Vector VQSHL T4 Variant. */
3173 {ARM_FEATURE_COPROC (FPU_MVE),
3174 MVE_VQSHL_T4,
3175 0xef000450, 0xef811f51,
3176 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3177
3178 /* Vector VQSHRN. */
3179 {ARM_FEATURE_COPROC (FPU_MVE),
3180 MVE_VQSHRN,
3181 0xee800f40, 0xefa00fd1,
3182 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3183
3184 /* Vector VQSHRUN. */
3185 {ARM_FEATURE_COPROC (FPU_MVE),
3186 MVE_VQSHRUN,
3187 0xee800fc0, 0xffa00fd1,
3188 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3189
14b456f2
AV		 3190 /* Vector VQSUB T1 Variant. */
3191 {ARM_FEATURE_COPROC (FPU_MVE),
3192 MVE_VQSUB_T1,
3193 0xef000250, 0xef811f51,
3194 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3195
3196 /* Vector VQSUB T2 Variant. */
3197 {ARM_FEATURE_COPROC (FPU_MVE),
3198 MVE_VQSUB_T2,
3199 0xee001f60, 0xef811f70,
3200 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3201
3202 /* Vector VREV16. */
3203 {ARM_FEATURE_COPROC (FPU_MVE),
3204 MVE_VREV16,
3205 0xffb00140, 0xffb31fd1,
3206 "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
3207
3208 /* Vector VREV32. */
3209 {ARM_FEATURE_COPROC (FPU_MVE),
3210 MVE_VREV32,
3211 0xffb000c0, 0xffb31fd1,
3212 "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3213
3214 /* Vector VREV64. */
3215 {ARM_FEATURE_COPROC (FPU_MVE),
3216 MVE_VREV64,
3217 0xffb00040, 0xffb31fd1,
3218 "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3219
bf0b396d
AV		 3220 /* Vector VRINT floating point. */
3221 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3222 MVE_VRINT_FP,
3223 0xffb20440, 0xffb31c51,
3224 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3225
d3b63143
AV		 3226 /* Vector VRMLALDAVH. */
3227 {ARM_FEATURE_COPROC (FPU_MVE),
3228 MVE_VRMLALDAVH,
3229 0xee800f00, 0xef811f51,
3230 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3231
3232 /* Vector VRMLALDAVH. */
3233 {ARM_FEATURE_COPROC (FPU_MVE),
3234 MVE_VRMLALDAVH,
3235 0xee801f00, 0xef811f51,
3236 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3237
ed63aa17
AV		 3238 /* Vector VRSHL T1 Variant. */
3239 {ARM_FEATURE_COPROC (FPU_MVE),
3240 MVE_VRSHL_T1,
3241 0xef000540, 0xef811f51,
3242 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3243
3244 /* Vector VRSHL T2 Variant. */
3245 {ARM_FEATURE_COPROC (FPU_MVE),
3246 MVE_VRSHL_T2,
3247 0xee331e60, 0xefb31ff0,
3248 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3249
3250 /* Vector VRSHRN. */
3251 {ARM_FEATURE_COPROC (FPU_MVE),
3252 MVE_VRSHRN,
3253 0xfe800fc1, 0xffa00fd1,
3254 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3255
66dcaa5d
AV		 3256 /* Vector VSBC. */
3257 {ARM_FEATURE_COPROC (FPU_MVE),
3258 MVE_VSBC,
3259 0xfe300f00, 0xffb10f51,
3260 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3261
ed63aa17
AV		 3262 /* Vector VSHL T2 Variant. */
3263 {ARM_FEATURE_COPROC (FPU_MVE),
3264 MVE_VSHL_T2,
3265 0xee311e60, 0xefb31ff0,
3266 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3267
3268 /* Vector VSHL T3 Variant. */
3269 {ARM_FEATURE_COPROC (FPU_MVE),
3270 MVE_VSHL_T3,
3271 0xef000440, 0xef811f51,
3272 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3273
3274 /* Vector VSHLC. */
3275 {ARM_FEATURE_COPROC (FPU_MVE),
3276 MVE_VSHLC,
3277 0xeea00fc0, 0xffa01ff0,
3278 "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
3279
3280 /* Vector VSHLL T2 Variant. */
3281 {ARM_FEATURE_COPROC (FPU_MVE),
3282 MVE_VSHLL_T2,
3283 0xee310e01, 0xefb30fd1,
3284 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
3285
3286 /* Vector VSHRN. */
3287 {ARM_FEATURE_COPROC (FPU_MVE),
3288 MVE_VSHRN,
3289 0xee800fc1, 0xffa00fd1,
3290 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3291
04d54ace
AV		 3292 /* Vector VST2 no writeback. */
3293 {ARM_FEATURE_COPROC (FPU_MVE),
3294 MVE_VST2,
3295 0xfc801e00, 0xffb01e5f,
3296 "vst2%5d.%7-8s\t%B, [%16-19r]"},
3297
3298 /* Vector VST2 writeback. */
3299 {ARM_FEATURE_COPROC (FPU_MVE),
3300 MVE_VST2,
3301 0xfca01e00, 0xffb01e5f,
3302 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3303
3304 /* Vector VST4 no writeback. */
3305 {ARM_FEATURE_COPROC (FPU_MVE),
3306 MVE_VST4,
3307 0xfc801e01, 0xffb01e1f,
3308 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3309
3310 /* Vector VST4 writeback. */
3311 {ARM_FEATURE_COPROC (FPU_MVE),
3312 MVE_VST4,
3313 0xfca01e01, 0xffb01e1f,
3314 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3315
ef1576a1
AV		 3316 /* Vector VSTRB scatter store, T1 variant. */
3317 {ARM_FEATURE_COPROC (FPU_MVE),
3318 MVE_VSTRB_SCATTER_T1,
3319 0xec800e00, 0xffb01e50,
3320 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3321
3322 /* Vector VSTRH scatter store, T2 variant. */
3323 {ARM_FEATURE_COPROC (FPU_MVE),
3324 MVE_VSTRH_SCATTER_T2,
3325 0xec800e10, 0xffb01e50,
3326 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3327
3328 /* Vector VSTRW scatter store, T3 variant. */
3329 {ARM_FEATURE_COPROC (FPU_MVE),
3330 MVE_VSTRW_SCATTER_T3,
3331 0xec800e40, 0xffb01e50,
3332 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3333
3334 /* Vector VSTRD scatter store, T4 variant. */
3335 {ARM_FEATURE_COPROC (FPU_MVE),
3336 MVE_VSTRD_SCATTER_T4,
3337 0xec800fd0, 0xffb01fd0,
3338 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3339
3340 /* Vector VSTRW scatter store, T5 variant. */
3341 {ARM_FEATURE_COPROC (FPU_MVE),
3342 MVE_VSTRW_SCATTER_T5,
3343 0xfd001e00, 0xff111f00,
3344 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3345
3346 /* Vector VSTRD scatter store, T6 variant. */
3347 {ARM_FEATURE_COPROC (FPU_MVE),
3348 MVE_VSTRD_SCATTER_T6,
3349 0xfd001f00, 0xff111f00,
3350 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3351
aef6d006
AV		 3352 /* Vector VSTRB. */
3353 {ARM_FEATURE_COPROC (FPU_MVE),
3354 MVE_VSTRB_T1,
3355 0xec000e00, 0xfe581e00,
3356 "vstrb%v.%7-8s\t%13-15Q, %d"},
3357
3358 /* Vector VSTRH. */
3359 {ARM_FEATURE_COPROC (FPU_MVE),
3360 MVE_VSTRH_T2,
3361 0xec080e00, 0xfe581e00,
3362 "vstrh%v.%7-8s\t%13-15Q, %d"},
3363
3364 /* Vector VSTRB variant T5. */
3365 {ARM_FEATURE_COPROC (FPU_MVE),
3366 MVE_VSTRB_T5,
3367 0xec001e00, 0xfe101f80,
3368 "vstrb%v.8\t%13-15,22Q, %d"},
3369
3370 /* Vector VSTRH variant T6. */
3371 {ARM_FEATURE_COPROC (FPU_MVE),
3372 MVE_VSTRH_T6,
3373 0xec001e80, 0xfe101f80,
3374 "vstrh%v.16\t%13-15,22Q, %d"},
3375
3376 /* Vector VSTRW variant T7. */
3377 {ARM_FEATURE_COPROC (FPU_MVE),
3378 MVE_VSTRW_T7,
3379 0xec001f00, 0xfe101f80,
3380 "vstrw%v.32\t%13-15,22Q, %d"},
3381
66dcaa5d
AV		 3382 /* Vector VSUB floating point T1 variant. */
3383 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3384 MVE_VSUB_FP_T1,
3385 0xef200d40, 0xffa11f51,
3386 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3387
3388 /* Vector VSUB floating point T2 variant. */
3389 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3390 MVE_VSUB_FP_T2,
3391 0xee301f40, 0xefb11f70,
3392 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3393
3394 /* Vector VSUB T1 variant. */
3395 {ARM_FEATURE_COPROC (FPU_MVE),
3396 MVE_VSUB_VEC_T1,
3397 0xff000840, 0xff811f51,
3398 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3399
3400 /* Vector VSUB T2 variant. */
3401 {ARM_FEATURE_COPROC (FPU_MVE),
3402 MVE_VSUB_VEC_T2,
3403 0xee011f40, 0xff811f70,
3404 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3405
23d00a41
SD		 3406 {ARM_FEATURE_COPROC (FPU_MVE),
3407 MVE_ASRLI,
3408 0xea50012f, 0xfff1813f,
3409 "asrl%c\t%17-19l, %9-11h, %j"},
3410
3411 {ARM_FEATURE_COPROC (FPU_MVE),
3412 MVE_ASRL,
3413 0xea50012d, 0xfff101ff,
3414 "asrl%c\t%17-19l, %9-11h, %12-15S"},
3415
3416 {ARM_FEATURE_COPROC (FPU_MVE),
3417 MVE_LSLLI,
3418 0xea50010f, 0xfff1813f,
3419 "lsll%c\t%17-19l, %9-11h, %j"},
3420
3421 {ARM_FEATURE_COPROC (FPU_MVE),
3422 MVE_LSLL,
3423 0xea50010d, 0xfff101ff,
3424 "lsll%c\t%17-19l, %9-11h, %12-15S"},
3425
3426 {ARM_FEATURE_COPROC (FPU_MVE),
3427 MVE_LSRL,
3428 0xea50011f, 0xfff1813f,
3429 "lsrl%c\t%17-19l, %9-11h, %j"},
3430
3431 {ARM_FEATURE_COPROC (FPU_MVE),
3432 MVE_SQRSHRL,
08132bdd
SP		 3433 0xea51012d, 0xfff1017f,
3434 "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"},
23d00a41
SD		 3435
3436 {ARM_FEATURE_COPROC (FPU_MVE),
3437 MVE_SQRSHR,
3438 0xea500f2d, 0xfff00fff,
3439 "sqrshr%c\t%16-19S, %12-15S"},
3440
3441 {ARM_FEATURE_COPROC (FPU_MVE),
3442 MVE_SQSHLL,
3443 0xea51013f, 0xfff1813f,
3444 "sqshll%c\t%17-19l, %9-11h, %j"},
3445
3446 {ARM_FEATURE_COPROC (FPU_MVE),
3447 MVE_SQSHL,
3448 0xea500f3f, 0xfff08f3f,
3449 "sqshl%c\t%16-19S, %j"},
3450
3451 {ARM_FEATURE_COPROC (FPU_MVE),
3452 MVE_SRSHRL,
3453 0xea51012f, 0xfff1813f,
3454 "srshrl%c\t%17-19l, %9-11h, %j"},
3455
3456 {ARM_FEATURE_COPROC (FPU_MVE),
3457 MVE_SRSHR,
3458 0xea500f2f, 0xfff08f3f,
3459 "srshr%c\t%16-19S, %j"},
3460
3461 {ARM_FEATURE_COPROC (FPU_MVE),
3462 MVE_UQRSHLL,
08132bdd
SP		 3463 0xea51010d, 0xfff1017f,
3464 "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"},
23d00a41
SD		 3465
3466 {ARM_FEATURE_COPROC (FPU_MVE),
3467 MVE_UQRSHL,
3468 0xea500f0d, 0xfff00fff,
3469 "uqrshl%c\t%16-19S, %12-15S"},
3470
3471 {ARM_FEATURE_COPROC (FPU_MVE),
3472 MVE_UQSHLL,
3473 0xea51010f, 0xfff1813f,
3474 "uqshll%c\t%17-19l, %9-11h, %j"},
3475
3476 {ARM_FEATURE_COPROC (FPU_MVE),
3477 MVE_UQSHL,
3478 0xea500f0f, 0xfff08f3f,
3479 "uqshl%c\t%16-19S, %j"},
3480
3481 {ARM_FEATURE_COPROC (FPU_MVE),
3482 MVE_URSHRL,
3483 0xea51011f, 0xfff1813f,
3484 "urshrl%c\t%17-19l, %9-11h, %j"},
3485
3486 {ARM_FEATURE_COPROC (FPU_MVE),
3487 MVE_URSHR,
3488 0xea500f1f, 0xfff08f3f,
3489 "urshr%c\t%16-19S, %j"},
3490
e39c1607
SD		 3491 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3492 MVE_CSINC,
3493 0xea509000, 0xfff0f000,
3494 "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3495
3496 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3497 MVE_CSINV,
3498 0xea50a000, 0xfff0f000,
3499 "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3500
3501 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3502 MVE_CSET,
3503 0xea5f900f, 0xfffff00f,
3504 "cset\t%8-11S, %4-7C"},
3505
3506 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3507 MVE_CSETM,
3508 0xea5fa00f, 0xfffff00f,
3509 "csetm\t%8-11S, %4-7C"},
3510
3511 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3512 MVE_CSEL,
3513 0xea508000, 0xfff0f000,
3514 "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3515
3516 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3517 MVE_CSNEG,
3518 0xea50b000, 0xfff0f000,
3519 "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3520
3521 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3522 MVE_CINC,
3523 0xea509000, 0xfff0f000,
3524 "cinc\t%8-11S, %16-19Z, %4-7C"},
3525
3526 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3527 MVE_CINV,
3528 0xea50a000, 0xfff0f000,
3529 "cinv\t%8-11S, %16-19Z, %4-7C"},
3530
3531 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3532 MVE_CNEG,
3533 0xea50b000, 0xfff0f000,
3534 "cneg\t%8-11S, %16-19Z, %4-7C"},
3535
143275ea
AV		 3536 {ARM_FEATURE_CORE_LOW (0),
3537 MVE_NONE,
3538 0x00000000, 0x00000000, 0}
73cd51e5
AV		 3539};
3540
8f06b2d8
PB		 3541/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
3542 ordered: they must be searched linearly from the top to obtain a correct
3543 match. */
3544
3545/* print_insn_arm recognizes the following format control codes:
3546
3547 %% %
3548
3549 %a print address for ldr/str instruction
3550 %s print address for ldr/str halfword/signextend instruction
c1e26897 3551 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 3552 %b print branch destination
3553 %c print condition code (always bits 28-31)
3554 %m print register mask for ldm/stm instruction
3555 %o print operand2 (immediate or register + shift)
3556 %p print 'p' iff bits 12-15 are 15
3557 %t print 't' iff bit 21 set and bit 24 clear
3558 %B print arm BLX(1) destination
3559 %C print the PSR sub type.
62b3e311
PB		 3560 %U print barrier type.
3561 %P print address for pli instruction.
8f06b2d8
PB		 3562
3563 %<bitfield>r print as an ARM register
9eb6c0f1 3564 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 3565 %<bitfield>R as %r but r15 is UNPREDICTABLE
3566 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3567 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 3568 %<bitfield>d print the bitfield in decimal
43e65147 3569 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 3570 %<bitfield>x print the bitfield in hex
3571 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 3572
16980d0b
JB		 3573 %<bitfield>'c print specified char iff bitfield is all ones
3574 %<bitfield>`c print specified char iff bitfield is all zeroes
3575 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 3576
8f06b2d8
PB		 3577 %e print arm SMI operand (bits 0..7,8..19).
3578 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 3579 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
3580 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 3581
8f06b2d8
PB		 3582static const struct opcode32 arm_opcodes[] =
3583{
3584 /* ARM instructions. */
823d2571
TG		 3585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3586 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
3587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3588 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
3589
3590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
3591 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3593 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3595 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
3597 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3599 0x00800090, 0x0fa000f0,
3600 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3601 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3602 0x00a00090, 0x0fa000f0,
3603 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 3604
105bde57 3605 /* V8.2 RAS extension instructions. */
4d1464f2 3606 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 3607 0xe320f010, 0xffffffff, "esb"},
3608
53c4b28b 3609 /* V8 instructions. */
823d2571
TG		 3610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3611 0x0320f005, 0x0fffffff, "sevl"},
f7dd2fb2
TC		 3612 /* Defined in V8 but is in NOP space so available to all arch. */
3613 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
823d2571 3614 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
4ed7ed8d 3615 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 3616 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3617 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 3618 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3619 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3620 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3622 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 3623 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3624 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3625 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3626 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3627 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3628 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3629 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3630 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3631 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3632 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3633 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3634 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3635 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3636 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3637 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3638 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3639 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3640 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3641 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 3642 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 3643 /* CRC32 instructions. */
8b301fbb 3644 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3645 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3646 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3647 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3648 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3649 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3650 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3651 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3652 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3653 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3654 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3655 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 3656
ddfded2f
MW		 3657 /* Privileged Access Never extension instructions. */
3658 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
3659 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
3660
90ec0d68 3661 /* Virtualization Extension instructions. */
823d2571
TG		 3662 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
3663 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 3664
eea54501 3665 /* Integer Divide Extension instructions. */
823d2571
TG		 3666 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3667 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3668 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3669 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 3670
60e5ef9f 3671 /* MP Extension instructions. */
823d2571 3672 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 3673
c597cc3d
SD		 3674 /* Speculation Barriers. */
3675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
3676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
3677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
3678
62b3e311 3679 /* V7 instructions. */
823d2571
TG		 3680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
3681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
3682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3683 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3685 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a
AV		 3687 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3688 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
62b3e311 3689
c19d1205 3690 /* ARM V6T2 instructions. */
823d2571
TG		 3691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3692 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3694 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3695 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3696 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3697 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3698 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3699
3700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3701 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
3702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3703 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3704
ff8646ee 3705 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 3706 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 3707 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3708 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3710 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3711 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3712 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 3713
f4c65163 3714 /* ARM Security extension instructions. */
823d2571
TG		 3715 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
3716 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 3717
8f06b2d8 3718 /* ARM V6K instructions. */
823d2571
TG		 3719 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3720 0xf57ff01f, 0xffffffff, "clrex"},
3721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3722 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3724 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3726 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3728 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3730 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3732 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 3733
7fadb25d
SD		 3734 /* ARMv8.5-A instructions. */
3735 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
3736
8f06b2d8 3737 /* ARM V6K NOP hints. */
823d2571
TG		 3738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3739 0x0320f001, 0x0fffffff, "yield%c"},
3740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3741 0x0320f002, 0x0fffffff, "wfe%c"},
3742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3743 0x0320f003, 0x0fffffff, "wfi%c"},
3744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3745 0x0320f004, 0x0fffffff, "sev%c"},
3746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3747 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 3748
fe56b6ce 3749 /* ARM V6 instructions. */
823d2571
TG		 3750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3751 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
3752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3753 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
3754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3755 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
3756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3757 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
3758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3759 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
3760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3761 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3763 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
3764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3765 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
3766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3767 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
3768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3769 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
3770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3771 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3773 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3775 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3777 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3779 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3781 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3783 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3785 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3787 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3789 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3791 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3793 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3795 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3797 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3799 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3801 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3803 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3805 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3807 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3809 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3811 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3813 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3815 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3817 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3819 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3821 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3823 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3825 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3827 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3829 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3831 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3833 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3835 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3837 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3839 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3841 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3843 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3845 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3847 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3849 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3851 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3853 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3855 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3857 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3859 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3861 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3863 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3865 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3867 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3869 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3871 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3873 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3875 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3877 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3879 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3881 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3883 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3885 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3887 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3889 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3891 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3893 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3895 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3897 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3899 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3901 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3903 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3905 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3907 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3909 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3911 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3913 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3915 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3917 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3919 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3921 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3923 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3925 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3927 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3929 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3931 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3933 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3935 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3937 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
3938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3939 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3941 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3943 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3945 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3947 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
3948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3949 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
3950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3951 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
3952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3953 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
3954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3955 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3957 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3959 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3961 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3963 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
3964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3965 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3967 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3969 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
3970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3971 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
3972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3973 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
3974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3975 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
3976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3977 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
3978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3979 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
3980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3981 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
3982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3983 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
3984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3985 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3987 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
3988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3989 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
3990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3991 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
3992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3993 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 3994
8f06b2d8 3995 /* V5J instruction. */
823d2571
TG		 3996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
3997 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 3998
8f06b2d8 3999 /* V5 Instructions. */
823d2571
TG		 4000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4001 0xe1200070, 0xfff000f0,
4002 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
4003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4004 0xfa000000, 0xfe000000, "blx\t%B"},
4005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4006 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
4007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4008 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
4009
4010 /* V5E "El Segundo" Instructions. */
4011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4012 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
4013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4014 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
4015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4016 0xf450f000, 0xfc70f000, "pld\t%a"},
4017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4018 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4020 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4022 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4024 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
4025
4026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4027 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4029 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
4030
4031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4032 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4034 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4036 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4038 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4039
4040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4041 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
4042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4043 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
4044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4045 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
4046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4047 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
4048
4049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4050 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
4051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4052 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
4053
4054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4055 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
4056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4057 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
4058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4059 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
4060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4061 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 4062
8f06b2d8 4063 /* ARM Instructions. */
823d2571
TG		 4064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4065 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
4066
4067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4068 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
4069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4070 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
4071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4072 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
4073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4074 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
4075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4076 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
4077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4078 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
4079
4080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4081 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
4082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4083 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
4084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4085 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
4086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4087 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
4088
4089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4090 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
4091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4092 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
4093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4094 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
4095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4096 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
4097
4098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4099 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
4100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4101 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
4102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4103 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
4104
4105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4106 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
4107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4108 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
4109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4110 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
4111
4112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4113 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
4114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4115 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
4116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4117 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
4118
4119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4120 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4122 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4124 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
4125
4126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4127 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
4128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4129 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
4130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4131 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
4132
4133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4134 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
4135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4136 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
4137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4138 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
4139
4140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4141 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4143 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4145 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
4146
4147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4148 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4150 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4152 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
4153
4154 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
4155 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
4156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4157 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
4158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4159 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
4160
4161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4162 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
4163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4164 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
4165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4166 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
4167
4168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4169 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 4170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4171 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 4172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4173 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
823d2571
TG		 4174
4175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4176 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
4177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4178 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
4179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4180 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
4181
4182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4183 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
4184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4185 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
4186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4187 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
4188
4189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4190 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
4191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4192 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
4193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4194 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
4195
4196 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4197 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
4198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4199 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
4200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4201 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
4202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4203 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
4204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4205 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
4206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4207 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
4208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4209 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
4210
4211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4212 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
4213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4214 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
4215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4216 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
4217
4218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4219 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
4220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4221 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
4222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4223 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
4224
4225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4226 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
4227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4228 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
4229
4230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4231 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
4232
4233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4234 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
4235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4236 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
4237
4238 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4239 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4240 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4241 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4243 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4245 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4247 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4249 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4251 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4252 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4253 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4255 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4257 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4259 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4261 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4263 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4265 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4266 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4267 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4269 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4271 0x092d0000, 0x0fff0000, "push%c\t%m"},
4272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4273 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
4274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4275 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4276
4277 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4278 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4279 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4280 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4281 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4282 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4283 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4284 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4285 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4286 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4287 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4288 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4289 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4290 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4292 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4294 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4295 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4296 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4297 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4298 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4299 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4300 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4301 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4302 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4304 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4305 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4306 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4307 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4308 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4310 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
4311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4312 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
4313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4314 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4315
4316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4317 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4319 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 4320
4321 /* The rest. */
4ab90a7a
AV		 4322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
4323 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 4324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4325 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4326 {ARM_FEATURE_CORE_LOW (0),
4327 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 4328};
4329
4330/* print_insn_thumb16 recognizes the following format control codes:
4331
4332 %S print Thumb register (bits 3..5 as high number if bit 6 set)
4333 %D print Thumb register (bits 0..2 as high number if bit 7 set)
4334 %<bitfield>I print bitfield as a signed decimal
4335 (top bit of range being the sign bit)
4336 %N print Thumb register mask (with LR)
4337 %O print Thumb register mask (with PC)
4338 %M print Thumb register mask
4339 %b print CZB's 6-bit unsigned branch destination
4340 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 4341 %c print the condition code
4342 %C print the condition code, or "s" if not conditional
4343 %x print warning if conditional an not at end of IT block"
4344 %X print "\t; unpredictable <IT:code>" if conditional
4345 %I print IT instruction suffix and operands
4547cb56 4346 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 4347 %<bitfield>r print bitfield as an ARM register
4348 %<bitfield>d print bitfield as a decimal
4349 %<bitfield>H print (bitfield * 2) as a decimal
4350 %<bitfield>W print (bitfield * 4) as a decimal
4351 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
4352 %<bitfield>B print Thumb branch destination (signed displacement)
4353 %<bitfield>c print bitfield as a condition code
4354 %<bitnum>'c print specified char iff bit is one
4355 %<bitnum>?ab print a if bit is one else print b. */
4356
4357static const struct opcode16 thumb_opcodes[] =
4358{
4359 /* Thumb instructions. */
4360
16a1fa25
TP		 4361 /* ARMv8-M Security Extensions instructions. */
4362 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
e207bc53 4363 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
16a1fa25 4364
53c4b28b 4365 /* ARM V8 instructions. */
823d2571
TG		 4366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
4367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
ddfded2f 4368 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
53c4b28b 4369
8f06b2d8 4370 /* ARM V6K no-argument instructions. */
823d2571
TG		 4371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
4372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
4373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
4374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
4375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
4376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 4377
4378 /* ARM V6T2 instructions. */
ff8646ee
TP		 4379 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4380 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4381 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4382 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 4383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 4384
4385 /* ARM V6. */
823d2571
TG		 4386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
4387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
4388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
4392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
4393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4395 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 4397
4398 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 4399 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4400 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 4401 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 4402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4403 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 4404 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 4405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4406 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 4407 /* Format 4. */
823d2571
TG		 4408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4411 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4413 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4415 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4418 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4419 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 4424 /* format 13 */
823d2571
TG		 4425 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
4426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 4427 /* format 5 */
823d2571
TG		 4428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
4429 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
4430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4431 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 4432 /* format 14 */
823d2571
TG		 4433 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
4434 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 4435 /* format 2 */
823d2571
TG		 4436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4437 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4439 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4440 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4441 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
4442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4443 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 4444 /* format 8 */
823d2571
TG		 4445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4446 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4447 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4448 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4450 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 4451 /* format 7 */
823d2571
TG		 4452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4453 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4455 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 4456 /* format 1 */
823d2571
TG		 4457 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4459 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
4460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4461 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 4462 /* format 3 */
823d2571
TG		 4463 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
4464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
4465 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
4466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 4467 /* format 6 */
823d2571
TG		 4468 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4469 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4470 0x4800, 0xF800,
4471 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 4472 /* format 9 */
823d2571
TG		 4473 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4474 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
4475 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4476 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
4477 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4478 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
4479 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4480 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 4481 /* format 10 */
823d2571
TG		 4482 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4483 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
4484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4485 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 4486 /* format 11 */
823d2571
TG		 4487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4488 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
4489 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4490 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 4491 /* format 12 */
823d2571
TG		 4492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4493 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
4494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4495 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 4496 /* format 15 */
823d2571
TG		 4497 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 4499 /* format 17 */
823d2571 4500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 4501 /* format 16 */
823d2571
TG		 4502 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
4503 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
4504 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 4505 /* format 18 */
823d2571 4506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 4507
4508 /* The E800 .. FFFF range is unconditionally redirected to the
4509 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4510 are processed via that table. Thus, we can never encounter a
4511 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 4512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
4513 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 4514};
4515
4516/* Thumb32 opcodes use the same table structure as the ARM opcodes.
4517 We adopt the convention that hw1 is the high 16 bits of .value and
4518 .mask, hw2 the low 16 bits.
4519
4520 print_insn_thumb32 recognizes the following format control codes:
4521
4522 %% %
4523
4524 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4525 %M print a modified 12-bit immediate (same location)
4526 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4527 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 4528 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 4529 %S print a possibly-shifted Rm
4530
32a94698 4531 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 4532 %a print the address of a plain load/store
4533 %w print the width and signedness of a core load/store
4534 %m print register mask for ldm/stm
4b5a202f 4535 %n print register mask for clrm
8f06b2d8
PB		 4536
4537 %E print the lsb and width fields of a bfc/bfi instruction
4538 %F print the lsb and width fields of a sbfx/ubfx instruction
e12437dc 4539 %G print a fallback offset for Branch Future instructions
e5d6e09e 4540 %W print an offset for BF instruction
1caf72a5 4541 %Y print an offset for BFL instruction
1889da70 4542 %Z print an offset for BFCSEL instruction
60f993ce
AV		 4543 %Q print an offset for Low Overhead Loop instructions
4544 %P print an offset for Low Overhead Loop end instructions
8f06b2d8
PB		 4545 %b print a conditional branch offset
4546 %B print an unconditional branch offset
4547 %s print the shift field of an SSAT instruction
4548 %R print the rotation field of an SXT instruction
62b3e311
PB		 4549 %U print barrier type.
4550 %P print address for pli instruction.
c22aaad1
PB		 4551 %c print the condition code
4552 %x print warning if conditional an not at end of IT block"
4553 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 4554
4555 %<bitfield>d print bitfield in decimal
f0fba320 4556 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 4557 %<bitfield>W print bitfield*4 in decimal
4558 %<bitfield>r print bitfield as an ARM register
dd5181d5 4559 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
f1c7f421 4560 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
8f06b2d8
PB		 4561 %<bitfield>c print bitfield as a condition code
4562
16980d0b
JB		 4563 %<bitfield>'c print specified char iff bitfield is all ones
4564 %<bitfield>`c print specified char iff bitfield is all zeroes
4565 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 4566
4567 With one exception at the bottom (done because BL and BLX(1) need
4568 to come dead last), this table was machine-sorted first in
4569 decreasing order of number of bits set in the mask, then in
4570 increasing numeric order of mask, then in increasing numeric order
4571 of opcode. This order is not the clearest for a human reader, but
4572 is guaranteed never to catch a special-case bit pattern with a more
4573 general mask, which is important, because this instruction encoding
4574 makes heavy use of special-case bit patterns. */
4575static const struct opcode32 thumb32_opcodes[] =
4576{
4b5a202f
AV		 4577 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4578 instructions. */
60f993ce 4579 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
d052b9b7 4580 0xf00fe001, 0xffffffff, "lctp%c"},
60f993ce
AV		 4581 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4582 0xf02fc001, 0xfffff001, "le\t%P"},
4583 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4584 0xf00fc001, 0xfffff001, "le\tlr, %P"},
d052b9b7
AV		 4585 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4586 0xf01fc001, 0xfffff001, "letp\tlr, %P"},
4587 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4588 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
4589 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4590 0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
4591 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4592 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
4593 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4594 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
60f993ce 4595
4389b29a
AV		 4596 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4597 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
f1c7f421
AV		 4598 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4599 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
65d1bc05
AV		 4600 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4601 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
f1c7f421
AV		 4602 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4603 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
f6b2b12d
AV		 4604 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4605 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4389b29a 4606
4b5a202f
AV		 4607 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4608 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4389b29a 4609
16a1fa25
TP		 4610 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
4611 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4ed7ed8d
TP		 4612 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4613 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4614 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4615 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
16a1fa25
TP		 4616 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4617 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4618 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4619 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4ed7ed8d 4620
105bde57 4621 /* ARM V8.2 RAS extension instructions. */
4d1464f2 4622 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 4623 0xf3af8010, 0xffffffff, "esb"},
4624
53c4b28b 4625 /* V8 instructions. */
823d2571
TG		 4626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4627 0xf3af8005, 0xffffffff, "sevl%c.w"},
4628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4629 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4631 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4633 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4635 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4637 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4639 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4641 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4643 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4645 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4647 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4649 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4651 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4652 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4653 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4655 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4657 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 4658
dd5181d5 4659 /* CRC32 instructions. */
8b301fbb 4660 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4661 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4662 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4663 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
8b301fbb 4664 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4665 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4666 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4667 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4668 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4669 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4670 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4671 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
dd5181d5 4672
c597cc3d
SD		 4673 /* Speculation Barriers. */
4674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
4675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
4676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
4677
62b3e311 4678 /* V7 instructions. */
823d2571
TG		 4679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
4681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4683 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4685 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4686 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4687 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4688 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4689 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 4690
90ec0d68 4691 /* Virtualization Extension instructions. */
823d2571 4692 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 4693 /* We skip ERET as that is SUBS pc, lr, #0. */
4694
60e5ef9f 4695 /* MP Extension instructions. */
823d2571 4696 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 4697
f4c65163 4698 /* Security extension instructions. */
823d2571 4699 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 4700
7fadb25d
SD		 4701 /* ARMv8.5-A instructions. */
4702 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
4703
8f06b2d8 4704 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 4705 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
4706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
4707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
4710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4711 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
4712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4713
ff8646ee 4714 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4715 0xf3bf8f2f, 0xffffffff, "clrex%c"},
4716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4717 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
4718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4719 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
4720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4721 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4723 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4725 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4727 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4729 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
4730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4731 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4733 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
4734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4735 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
4736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4737 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
4738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4739 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
4740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4741 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 4742 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 4743 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 4744 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4745 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4747 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
4748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4749 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
4750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4751 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4753 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4755 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4757 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4759 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4761 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 4762 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4763 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4765 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4767 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4769 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4771 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4773 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4775 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4777 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4779 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4781 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4783 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4785 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4787 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4789 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4791 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4793 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4795 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4797 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4799 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4801 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4803 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4805 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4807 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4809 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4811 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4813 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4815 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4817 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4819 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4821 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4823 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4825 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4827 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4829 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4831 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4833 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4835 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4837 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4839 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4841 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4843 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4845 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4847 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4849 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4851 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4853 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4855 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4857 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4859 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4861 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4863 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4865 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4867 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4869 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 4870 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4871 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 4873 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 4874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4875 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4877 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4879 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4881 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4883 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4885 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4887 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4889 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4891 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4893 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4895 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4897 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4899 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4901 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4903 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4905 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4907 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4909 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4911 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4913 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4915 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4917 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4919 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4921 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4923 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4925 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4927 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4929 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4931 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4933 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4935 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4937 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 4938 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4939 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
4940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4941 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
4942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4943 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
4944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4945 0xf810f000, 0xff70f000, "pld%c\t%a"},
4946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4947 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4949 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4951 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4953 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4955 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4957 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4959 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4961 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
4962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4963 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
4964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4965 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
4966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4967 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
4968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4969 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
4970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4971 0xfb100000, 0xfff000c0,
4972 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4974 0xfbc00080, 0xfff000c0,
4975 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
4976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4977 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
4978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4979 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
4980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 4981 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 4982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4983 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
4984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4985 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 4986 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4987 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
4988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4989 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 4990 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4991 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
4992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4993 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
4994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4995 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
4996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4997 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
4998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4999 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
5000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5001 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
5002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5003 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
5004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5005 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
5006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5007 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
5008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5009 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
5010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5011 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 5012 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 5013 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
5014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5015 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
5016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5017 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
5018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5019 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
5020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5021 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
5022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5023 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
5024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5025 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
5026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5027 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
5028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5029 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
5030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5031 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
5032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5033 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
5034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5035 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
5036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5037 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
5038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5039 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
5040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5041 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
5042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5043 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
5044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5045 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
5046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5047 0xe9400000, 0xff500000,
5048 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5050 0xe9500000, 0xff500000,
5051 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5053 0xe8600000, 0xff700000,
5054 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5056 0xe8700000, 0xff700000,
5057 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5059 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
5060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5061 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 5062
5063 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 5064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5065 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
5066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5067 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
5068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5069 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
5070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5071 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 5072
8f06b2d8 5073 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 5074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5075 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
5076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5077 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 5078
5079 /* Fallback. */
823d2571
TG		 5080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
5081 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
5082 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 5083};
ff4a8d2b 5084
8f06b2d8
PB		 5085static const char *const arm_conditional[] =
5086{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 5087 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 5088
5089static const char *const arm_fp_const[] =
5090{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
5091
5092static const char *const arm_shift[] =
5093{"lsl", "lsr", "asr", "ror"};
5094
5095typedef struct
5096{
5097 const char *name;
5098 const char *description;
5099 const char *reg_names[16];
5100}
5101arm_regname;
5102
5103static const arm_regname regnames[] =
5104{
65b48a81 5105 { "reg-names-raw", N_("Select raw register names"),
8f06b2d8 5106 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
65b48a81 5107 { "reg-names-gcc", N_("Select register names used by GCC"),
8f06b2d8 5108 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 5109 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
8f06b2d8 5110 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65b48a81
PB		 5111 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
5112 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
5113 { "reg-names-apcs", N_("Select register names used in the APCS"),
8f06b2d8 5114 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 5115 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
8f06b2d8 5116 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
65b48a81
PB		 5117 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
5118 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
8f06b2d8
PB		 5119};
5120
5121static const char *const iwmmxt_wwnames[] =
5122{"b", "h", "w", "d"};
5123
5124static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 5125{"b", "bus", "bc", "bss",
5126 "h", "hus", "hc", "hss",
5127 "w", "wus", "wc", "wss",
5128 "d", "dus", "dc", "dss"
8f06b2d8
PB		 5129};
5130
5131static const char *const iwmmxt_regnames[] =
5132{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
5133 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
5134};
5135
5136static const char *const iwmmxt_cregnames[] =
5137{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
5138 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
5139};
5140
143275ea
AV		 5141static const char *const vec_condnames[] =
5142{ "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
5143};
5144
5145static const char *const mve_predicatenames[] =
5146{ "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
5147 "eee", "ee", "eet", "e", "ett", "et", "ete"
5148};
5149
5150/* Names for 2-bit size field for mve vector isntructions. */
5151static const char *const mve_vec_sizename[] =
5152 { "8", "16", "32", "64"};
5153
5154/* Indicates whether we are processing a then predicate,
5155 else predicate or none at all. */
5156enum vpt_pred_state
5157{
5158 PRED_NONE,
5159 PRED_THEN,
5160 PRED_ELSE
5161};
5162
5163/* Information used to process a vpt block and subsequent instructions. */
5164struct vpt_block
5165{
5166 /* Are we in a vpt block. */
5167 bfd_boolean in_vpt_block;
5168
5169 /* Next predicate state if in vpt block. */
5170 enum vpt_pred_state next_pred_state;
5171
5172 /* Mask from vpt/vpst instruction. */
5173 long predicate_mask;
5174
5175 /* Instruction number in vpt block. */
5176 long current_insn_num;
5177
5178 /* Number of instructions in vpt block.. */
5179 long num_pred_insn;
5180};
5181
5182static struct vpt_block vpt_block_state =
5183{
5184 FALSE,
5185 PRED_NONE,
5186 0,
5187 0,
5188 0
5189};
5190
8f06b2d8
PB		 5191/* Default to GCC register name set. */
5192static unsigned int regname_selected = 1;
5193
65b48a81 5194#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
8f06b2d8
PB		 5195#define arm_regnames regnames[regname_selected].reg_names
5196
5197static bfd_boolean force_thumb = FALSE;
5198
c22aaad1
PB		 5199/* Current IT instruction state. This contains the same state as the IT
5200 bits in the CPSR. */
5201static unsigned int ifthen_state;
5202/* IT state for the next instruction. */
5203static unsigned int ifthen_next_state;
5204/* The address of the insn for which the IT state is valid. */
5205static bfd_vma ifthen_address;
5206#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 5207/* Indicates that the current Conditional state is unconditional or outside
5208 an IT block. */
5209#define COND_UNCOND 16
c22aaad1 5210
8f06b2d8
PB		 5211\f
5212/* Functions. */
143275ea
AV		 5213/* Extract the predicate mask for a VPT or VPST instruction.
5214 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
5215
5216static long
5217mve_extract_pred_mask (long given)
5218{
5219 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
5220}
5221
5222/* Return the number of instructions in a MVE predicate block. */
5223static long
5224num_instructions_vpt_block (long given)
5225{
5226 long mask = mve_extract_pred_mask (given);
5227 if (mask == 0)
5228 return 0;
5229
5230 if (mask == 8)
5231 return 1;
5232
5233 if ((mask & 7) == 4)
5234 return 2;
5235
5236 if ((mask & 3) == 2)
5237 return 3;
5238
5239 if ((mask & 1) == 1)
5240 return 4;
5241
5242 return 0;
5243}
5244
5245static void
5246mark_outside_vpt_block (void)
5247{
5248 vpt_block_state.in_vpt_block = FALSE;
5249 vpt_block_state.next_pred_state = PRED_NONE;
5250 vpt_block_state.predicate_mask = 0;
5251 vpt_block_state.current_insn_num = 0;
5252 vpt_block_state.num_pred_insn = 0;
5253}
5254
5255static void
5256mark_inside_vpt_block (long given)
5257{
5258 vpt_block_state.in_vpt_block = TRUE;
5259 vpt_block_state.next_pred_state = PRED_THEN;
5260 vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
5261 vpt_block_state.current_insn_num = 0;
5262 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
5263 assert (vpt_block_state.num_pred_insn >= 1);
5264}
5265
5266static enum vpt_pred_state
5267invert_next_predicate_state (enum vpt_pred_state astate)
5268{
5269 if (astate == PRED_THEN)
5270 return PRED_ELSE;
5271 else if (astate == PRED_ELSE)
5272 return PRED_THEN;
5273 else
5274 return PRED_NONE;
5275}
5276
5277static enum vpt_pred_state
5278update_next_predicate_state (void)
5279{
5280 long pred_mask = vpt_block_state.predicate_mask;
5281 long mask_for_insn = 0;
5282
5283 switch (vpt_block_state.current_insn_num)
5284 {
5285 case 1:
5286 mask_for_insn = 8;
5287 break;
5288
5289 case 2:
5290 mask_for_insn = 4;
5291 break;
5292
5293 case 3:
5294 mask_for_insn = 2;
5295 break;
5296
5297 case 4:
5298 return PRED_NONE;
5299 }
5300
5301 if (pred_mask & mask_for_insn)
5302 return invert_next_predicate_state (vpt_block_state.next_pred_state);
5303 else
5304 return vpt_block_state.next_pred_state;
5305}
5306
5307static void
5308update_vpt_block_state (void)
5309{
5310 vpt_block_state.current_insn_num++;
5311 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
5312 {
5313 /* No more instructions to process in vpt block. */
5314 mark_outside_vpt_block ();
5315 return;
5316 }
5317
5318 vpt_block_state.next_pred_state = update_next_predicate_state ();
5319}
8f06b2d8 5320
16980d0b
JB		 5321/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5322 Returns pointer to following character of the format string and
5323 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 5324 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 5325
5326static const char *
fe56b6ce
NC		 5327arm_decode_bitfield (const char *ptr,
5328 unsigned long insn,
5329 unsigned long *valuep,
5330 int *widthp)
16980d0b
JB		 5331{
5332 unsigned long value = 0;
5333 int width = 0;
43e65147
L		 5334
5335 do
16980d0b
JB		 5336 {
5337 int start, end;
5338 int bits;
5339
5340 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
5341 start = start * 10 + *ptr - '0';
5342 if (*ptr == '-')
5343 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
5344 end = end * 10 + *ptr - '0';
5345 else
5346 end = start;
5347 bits = end - start;
5348 if (bits < 0)
5349 abort ();
5350 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
5351 width += bits + 1;
5352 }
5353 while (*ptr++ == ',');
5354 *valuep = value;
5355 if (widthp)
5356 *widthp = width;
5357 return ptr - 1;
5358}
5359
8f06b2d8 5360static void
37b37b2d 5361arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 5362 bfd_boolean print_shift)
8f06b2d8
PB		 5363{
5364 func (stream, "%s", arm_regnames[given & 0xf]);
5365
5366 if ((given & 0xff0) != 0)
5367 {
5368 if ((given & 0x10) == 0)
5369 {
5370 int amount = (given & 0xf80) >> 7;
5371 int shift = (given & 0x60) >> 5;
5372
5373 if (amount == 0)
5374 {
5375 if (shift == 3)
5376 {
5377 func (stream, ", rrx");
5378 return;
5379 }
5380
5381 amount = 32;
5382 }
5383
37b37b2d
RE		 5384 if (print_shift)
5385 func (stream, ", %s #%d", arm_shift[shift], amount);
5386 else
5387 func (stream, ", #%d", amount);
8f06b2d8 5388 }
74bdfecf 5389 else if ((given & 0x80) == 0x80)
aefd8a40 5390 func (stream, "\t; <illegal shifter operand>");
37b37b2d 5391 else if (print_shift)
8f06b2d8
PB		 5392 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
5393 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 5394 else
5395 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 5396 }
5397}
5398
73cd51e5
AV		 5399/* Return TRUE if the MATCHED_INSN can be inside an IT block. */
5400
5401static bfd_boolean
5402is_mve_okay_in_it (enum mve_instructions matched_insn)
5403{
c507f10b
AV		 5404 switch (matched_insn)
5405 {
5406 case MVE_VMOV_GP_TO_VEC_LANE:
5407 case MVE_VMOV2_VEC_LANE_TO_GP:
5408 case MVE_VMOV2_GP_TO_VEC_LANE:
5409 case MVE_VMOV_VEC_LANE_TO_GP:
23d00a41
SD		 5410 case MVE_LSLL:
5411 case MVE_LSLLI:
5412 case MVE_LSRL:
5413 case MVE_ASRL:
5414 case MVE_ASRLI:
5415 case MVE_SQRSHRL:
5416 case MVE_SQRSHR:
5417 case MVE_UQRSHL:
5418 case MVE_UQRSHLL:
5419 case MVE_UQSHL:
5420 case MVE_UQSHLL:
5421 case MVE_URSHRL:
5422 case MVE_URSHR:
5423 case MVE_SRSHRL:
5424 case MVE_SRSHR:
5425 case MVE_SQSHLL:
5426 case MVE_SQSHL:
c507f10b
AV		 5427 return TRUE;
5428 default:
5429 return FALSE;
5430 }
73cd51e5
AV		 5431}
5432
5433static bfd_boolean
5434is_mve_architecture (struct disassemble_info *info)
5435{
5436 struct arm_private_data *private_data = info->private_data;
5437 arm_feature_set allowed_arches = private_data->features;
5438
5439 arm_feature_set arm_ext_v8_1m_main
5440 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
5441
5442 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
5443 && !ARM_CPU_IS_ANY (allowed_arches))
5444 return TRUE;
5445 else
5446 return FALSE;
5447}
5448
143275ea
AV		 5449static bfd_boolean
5450is_vpt_instruction (long given)
5451{
5452
5453 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
5454 if ((given & 0x0040e000) == 0)
5455 return FALSE;
5456
5457 /* VPT floating point T1 variant. */
5458 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
5459 /* VPT floating point T2 variant. */
5460 || ((given & 0xefb10f50) == 0xee310f40)
5461 /* VPT vector T1 variant. */
5462 || ((given & 0xff811f51) == 0xfe010f00)
5463 /* VPT vector T2 variant. */
5464 || ((given & 0xff811f51) == 0xfe010f01
5465 && ((given & 0x300000) != 0x300000))
5466 /* VPT vector T3 variant. */
5467 || ((given & 0xff811f50) == 0xfe011f00)
5468 /* VPT vector T4 variant. */
5469 || ((given & 0xff811f70) == 0xfe010f40)
5470 /* VPT vector T5 variant. */
5471 || ((given & 0xff811f70) == 0xfe010f60)
5472 /* VPT vector T6 variant. */
5473 || ((given & 0xff811f50) == 0xfe011f40)
5474 /* VPST vector T variant. */
5475 || ((given & 0xffbf1fff) == 0xfe310f4d))
5476 return TRUE;
5477 else
5478 return FALSE;
5479}
5480
73cd51e5
AV		 5481/* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5482 and ending bitfield = END. END must be greater than START. */
5483
5484static unsigned long
5485arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
5486{
5487 int bits = end - start;
5488
5489 if (bits < 0)
5490 abort ();
5491
5492 return ((given >> start) & ((2ul << bits) - 1));
5493}
5494
5495/* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5496 START:END and START2:END2. END/END2 must be greater than
5497 START/START2. */
5498
5499static unsigned long
5500arm_decode_field_multiple (unsigned long given, unsigned int start,
5501 unsigned int end, unsigned int start2,
5502 unsigned int end2)
5503{
5504 int bits = end - start;
5505 int bits2 = end2 - start2;
5506 unsigned long value = 0;
5507 int width = 0;
5508
5509 if (bits2 < 0)
5510 abort ();
5511
5512 value = arm_decode_field (given, start, end);
5513 width += bits + 1;
5514
5515 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
5516 return value;
5517}
5518
5519/* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5520 This helps us decode instructions that change mnemonic depending on specific
5521 operand values/encodings. */
5522
5523static bfd_boolean
5524is_mve_encoding_conflict (unsigned long given,
5525 enum mve_instructions matched_insn)
5526{
143275ea
AV		 5527 switch (matched_insn)
5528 {
5529 case MVE_VPST:
5530 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5531 return TRUE;
5532 else
5533 return FALSE;
5534
5535 case MVE_VPT_FP_T1:
5536 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5537 return TRUE;
5538 if ((arm_decode_field (given, 12, 12) == 0)
5539 && (arm_decode_field (given, 0, 0) == 1))
5540 return TRUE;
5541 return FALSE;
5542
5543 case MVE_VPT_FP_T2:
5544 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5545 return TRUE;
5546 if (arm_decode_field (given, 0, 3) == 0xd)
5547 return TRUE;
5548 return FALSE;
5549
5550 case MVE_VPT_VEC_T1:
5551 case MVE_VPT_VEC_T2:
5552 case MVE_VPT_VEC_T3:
5553 case MVE_VPT_VEC_T4:
5554 case MVE_VPT_VEC_T5:
5555 case MVE_VPT_VEC_T6:
5556 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5557 return TRUE;
5558 if (arm_decode_field (given, 20, 21) == 3)
5559 return TRUE;
5560 return FALSE;
5561
5562 case MVE_VCMP_FP_T1:
5563 if ((arm_decode_field (given, 12, 12) == 0)
5564 && (arm_decode_field (given, 0, 0) == 1))
5565 return TRUE;
5566 else
5567 return FALSE;
5568
5569 case MVE_VCMP_FP_T2:
5570 if (arm_decode_field (given, 0, 3) == 0xd)
5571 return TRUE;
5572 else
5573 return FALSE;
5574
14b456f2
AV		 5575 case MVE_VQADD_T2:
5576 case MVE_VQSUB_T2:
f49bb598
AV		 5577 case MVE_VMUL_VEC_T2:
5578 case MVE_VMULH:
5579 case MVE_VRMULH:
56858bea
AV		 5580 case MVE_VMLA:
5581 case MVE_VMAX:
5582 case MVE_VMIN:
e523f101 5583 case MVE_VBRSR:
66dcaa5d
AV		 5584 case MVE_VADD_VEC_T2:
5585 case MVE_VSUB_VEC_T2:
5586 case MVE_VABAV:
ed63aa17
AV		 5587 case MVE_VQRSHL_T1:
5588 case MVE_VQSHL_T4:
5589 case MVE_VRSHL_T1:
5590 case MVE_VSHL_T3:
897b9bbc
AV		 5591 case MVE_VCADD_VEC:
5592 case MVE_VHCADD:
1c8f2df8
AV		 5593 case MVE_VDDUP:
5594 case MVE_VIDUP:
d3b63143
AV		 5595 case MVE_VQRDMLADH:
5596 case MVE_VQDMLAH:
5597 case MVE_VQRDMLAH:
5598 case MVE_VQDMLASH:
5599 case MVE_VQRDMLASH:
5600 case MVE_VQDMLSDH:
5601 case MVE_VQRDMLSDH:
5602 case MVE_VQDMULH_T3:
5603 case MVE_VQRDMULH_T4:
5604 case MVE_VQDMLADH:
5605 case MVE_VMLAS:
14925797 5606 case MVE_VMULL_INT:
9743db03
AV		 5607 case MVE_VHADD_T2:
5608 case MVE_VHSUB_T2:
143275ea
AV		 5609 case MVE_VCMP_VEC_T1:
5610 case MVE_VCMP_VEC_T2:
5611 case MVE_VCMP_VEC_T3:
5612 case MVE_VCMP_VEC_T4:
5613 case MVE_VCMP_VEC_T5:
5614 case MVE_VCMP_VEC_T6:
5615 if (arm_decode_field (given, 20, 21) == 3)
5616 return TRUE;
5617 else
5618 return FALSE;
5619
04d54ace
AV		 5620 case MVE_VLD2:
5621 case MVE_VLD4:
5622 case MVE_VST2:
5623 case MVE_VST4:
5624 if (arm_decode_field (given, 7, 8) == 3)
5625 return TRUE;
5626 else
5627 return FALSE;
5628
aef6d006
AV		 5629 case MVE_VSTRB_T1:
5630 case MVE_VSTRH_T2:
5631 if ((arm_decode_field (given, 24, 24) == 0)
5632 && (arm_decode_field (given, 21, 21) == 0))
5633 {
5634 return TRUE;
5635 }
5636 else if ((arm_decode_field (given, 7, 8) == 3))
5637 return TRUE;
5638 else
5639 return FALSE;
5640
5641 case MVE_VSTRB_T5:
5642 case MVE_VSTRH_T6:
5643 case MVE_VSTRW_T7:
5644 if ((arm_decode_field (given, 24, 24) == 0)
5645 && (arm_decode_field (given, 21, 21) == 0))
5646 {
5647 return TRUE;
5648 }
5649 else
5650 return FALSE;
5651
bf0b396d
AV		 5652 case MVE_VCVT_FP_FIX_VEC:
5653 return (arm_decode_field (given, 16, 21) & 0x38) == 0;
5654
c507f10b
AV		 5655 case MVE_VBIC_IMM:
5656 case MVE_VORR_IMM:
5657 {
5658 unsigned long cmode = arm_decode_field (given, 8, 11);
5659
5660 if ((cmode & 1) == 0)
5661 return TRUE;
5662 else if ((cmode & 0xc) == 0xc)
5663 return TRUE;
5664 else
5665 return FALSE;
5666 }
5667
5668 case MVE_VMVN_IMM:
5669 {
5670 unsigned long cmode = arm_decode_field (given, 8, 11);
5671
ce760a76 5672 if (cmode == 0xe)
c507f10b 5673 return TRUE;
ce760a76 5674 else if ((cmode & 0x9) == 1)
c507f10b 5675 return TRUE;
ce760a76 5676 else if ((cmode & 0xd) == 9)
c507f10b
AV		 5677 return TRUE;
5678 else
5679 return FALSE;
5680 }
5681
5682 case MVE_VMOV_IMM_TO_VEC:
5683 if ((arm_decode_field (given, 5, 5) == 1)
5684 && (arm_decode_field (given, 8, 11) != 0xe))
5685 return TRUE;
5686 else
5687 return FALSE;
5688
14925797
AV		 5689 case MVE_VMOVL:
5690 {
5691 unsigned long size = arm_decode_field (given, 19, 20);
5692 if ((size == 0) || (size == 3))
5693 return TRUE;
5694 else
5695 return FALSE;
5696 }
5697
56858bea
AV		 5698 case MVE_VMAXA:
5699 case MVE_VMINA:
5700 case MVE_VMAXV:
5701 case MVE_VMAXAV:
5702 case MVE_VMINV:
5703 case MVE_VMINAV:
ed63aa17
AV		 5704 case MVE_VQRSHL_T2:
5705 case MVE_VQSHL_T1:
5706 case MVE_VRSHL_T2:
5707 case MVE_VSHL_T2:
5708 case MVE_VSHLL_T2:
d3b63143 5709 case MVE_VADDV:
14925797
AV		 5710 case MVE_VMOVN:
5711 case MVE_VQMOVUN:
5712 case MVE_VQMOVN:
5713 if (arm_decode_field (given, 18, 19) == 3)
5714 return TRUE;
5715 else
5716 return FALSE;
5717
d3b63143
AV		 5718 case MVE_VMLSLDAV:
5719 case MVE_VRMLSLDAVH:
5720 case MVE_VMLALDAV:
5721 case MVE_VADDLV:
5722 if (arm_decode_field (given, 20, 22) == 7)
5723 return TRUE;
5724 else
5725 return FALSE;
5726
5727 case MVE_VRMLALDAVH:
5728 if ((arm_decode_field (given, 20, 22) & 6) == 6)
5729 return TRUE;
5730 else
5731 return FALSE;
5732
1c8f2df8
AV		 5733 case MVE_VDWDUP:
5734 case MVE_VIWDUP:
5735 if ((arm_decode_field (given, 20, 21) == 3)
5736 || (arm_decode_field (given, 1, 3) == 7))
5737 return TRUE;
5738 else
5739 return FALSE;
5740
ed63aa17
AV		 5741
5742 case MVE_VSHLL_T1:
5743 if (arm_decode_field (given, 16, 18) == 0)
5744 {
5745 unsigned long sz = arm_decode_field (given, 19, 20);
5746
5747 if ((sz == 1) || (sz == 2))
5748 return TRUE;
5749 else
5750 return FALSE;
5751 }
5752 else
5753 return FALSE;
5754
5755 case MVE_VQSHL_T2:
5756 case MVE_VQSHLU_T3:
5757 case MVE_VRSHR:
5758 case MVE_VSHL_T1:
5759 case MVE_VSHR:
5760 case MVE_VSLI:
5761 case MVE_VSRI:
5762 if (arm_decode_field (given, 19, 21) == 0)
5763 return TRUE;
5764 else
5765 return FALSE;
5766
e523f101
AV		 5767 case MVE_VCTP:
5768 if (arm_decode_field (given, 16, 19) == 0xf)
5769 return TRUE;
5770 else
5771 return FALSE;
5772
23d00a41
SD		 5773 case MVE_ASRLI:
5774 case MVE_ASRL:
5775 case MVE_LSLLI:
5776 case MVE_LSLL:
5777 case MVE_LSRL:
5778 case MVE_SQRSHRL:
5779 case MVE_SQSHLL:
5780 case MVE_SRSHRL:
5781 case MVE_UQRSHLL:
5782 case MVE_UQSHLL:
5783 case MVE_URSHRL:
5784 if (arm_decode_field (given, 9, 11) == 0x7)
5785 return TRUE;
5786 else
5787 return FALSE;
5788
e39c1607
SD		 5789 case MVE_CSINC:
5790 case MVE_CSINV:
5791 {
5792 unsigned long rm, rn;
5793 rm = arm_decode_field (given, 0, 3);
5794 rn = arm_decode_field (given, 16, 19);
5795 /* CSET/CSETM. */
5796 if (rm == 0xf && rn == 0xf)
5797 return TRUE;
5798 /* CINC/CINV. */
5799 else if (rn == rm && rn != 0xf)
5800 return TRUE;
5801 }
5802 /* Fall through. */
5803 case MVE_CSEL:
5804 case MVE_CSNEG:
5805 if (arm_decode_field (given, 0, 3) == 0xd)
5806 return TRUE;
5807 /* CNEG. */
5808 else if (matched_insn == MVE_CSNEG)
5809 if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19))
5810 return TRUE;
5811 return FALSE;
5812
143275ea 5813 default:
66dcaa5d
AV		 5814 case MVE_VADD_FP_T1:
5815 case MVE_VADD_FP_T2:
5816 case MVE_VADD_VEC_T1:
143275ea
AV		 5817 return FALSE;
5818
5819 }
73cd51e5
AV		 5820}
5821
aef6d006
AV		 5822static void
5823print_mve_vld_str_addr (struct disassemble_info *info,
5824 unsigned long given,
5825 enum mve_instructions matched_insn)
5826{
5827 void *stream = info->stream;
5828 fprintf_ftype func = info->fprintf_func;
5829
5830 unsigned long p, w, gpr, imm, add, mod_imm;
5831
5832 imm = arm_decode_field (given, 0, 6);
5833 mod_imm = imm;
5834
5835 switch (matched_insn)
5836 {
5837 case MVE_VLDRB_T1:
5838 case MVE_VSTRB_T1:
5839 gpr = arm_decode_field (given, 16, 18);
5840 break;
5841
5842 case MVE_VLDRH_T2:
5843 case MVE_VSTRH_T2:
5844 gpr = arm_decode_field (given, 16, 18);
5845 mod_imm = imm << 1;
5846 break;
5847
5848 case MVE_VLDRH_T6:
5849 case MVE_VSTRH_T6:
5850 gpr = arm_decode_field (given, 16, 19);
5851 mod_imm = imm << 1;
5852 break;
5853
5854 case MVE_VLDRW_T7:
5855 case MVE_VSTRW_T7:
5856 gpr = arm_decode_field (given, 16, 19);
5857 mod_imm = imm << 2;
5858 break;
5859
5860 case MVE_VLDRB_T5:
5861 case MVE_VSTRB_T5:
5862 gpr = arm_decode_field (given, 16, 19);
5863 break;
5864
5865 default:
5866 return;
5867 }
5868
5869 p = arm_decode_field (given, 24, 24);
5870 w = arm_decode_field (given, 21, 21);
5871
5872 add = arm_decode_field (given, 23, 23);
5873
5874 char * add_sub;
5875
5876 /* Don't print anything for '+' as it is implied. */
5877 if (add == 1)
5878 add_sub = "";
5879 else
5880 add_sub = "-";
5881
5882 if (p == 1)
5883 {
5884 /* Offset mode. */
5885 if (w == 0)
5886 func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm);
5887 /* Pre-indexed mode. */
5888 else
5889 func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm);
5890 }
5891 else if ((p == 0) && (w == 1))
5892 /* Post-index mode. */
5893 func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm);
5894}
5895
73cd51e5
AV		 5896/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5897 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5898 this encoding is undefined. */
5899
5900static bfd_boolean
5901is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
5902 enum mve_undefined *undefined_code)
5903{
5904 *undefined_code = UNDEF_NONE;
5905
9743db03
AV		 5906 switch (matched_insn)
5907 {
5908 case MVE_VDUP:
5909 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
5910 {
5911 *undefined_code = UNDEF_SIZE_3;
5912 return TRUE;
5913 }
5914 else
5915 return FALSE;
5916
14b456f2
AV		 5917 case MVE_VQADD_T1:
5918 case MVE_VQSUB_T1:
f49bb598 5919 case MVE_VMUL_VEC_T1:
66dcaa5d
AV		 5920 case MVE_VABD_VEC:
5921 case MVE_VADD_VEC_T1:
5922 case MVE_VSUB_VEC_T1:
d3b63143
AV		 5923 case MVE_VQDMULH_T1:
5924 case MVE_VQRDMULH_T2:
9743db03
AV		 5925 case MVE_VRHADD:
5926 case MVE_VHADD_T1:
5927 case MVE_VHSUB_T1:
5928 if (arm_decode_field (given, 20, 21) == 3)
5929 {
5930 *undefined_code = UNDEF_SIZE_3;
5931 return TRUE;
5932 }
5933 else
5934 return FALSE;
5935
aef6d006
AV		 5936 case MVE_VLDRB_T1:
5937 if (arm_decode_field (given, 7, 8) == 3)
5938 {
5939 *undefined_code = UNDEF_SIZE_3;
5940 return TRUE;
5941 }
5942 else
5943 return FALSE;
5944
5945 case MVE_VLDRH_T2:
5946 if (arm_decode_field (given, 7, 8) <= 1)
5947 {
5948 *undefined_code = UNDEF_SIZE_LE_1;
5949 return TRUE;
5950 }
5951 else
5952 return FALSE;
5953
5954 case MVE_VSTRB_T1:
5955 if ((arm_decode_field (given, 7, 8) == 0))
5956 {
5957 *undefined_code = UNDEF_SIZE_0;
5958 return TRUE;
5959 }
5960 else
5961 return FALSE;
5962
5963 case MVE_VSTRH_T2:
5964 if ((arm_decode_field (given, 7, 8) <= 1))
5965 {
5966 *undefined_code = UNDEF_SIZE_LE_1;
5967 return TRUE;
5968 }
5969 else
5970 return FALSE;
5971
ef1576a1
AV		 5972 case MVE_VLDRB_GATHER_T1:
5973 if (arm_decode_field (given, 7, 8) == 3)
5974 {
5975 *undefined_code = UNDEF_SIZE_3;
5976 return TRUE;
5977 }
5978 else if ((arm_decode_field (given, 28, 28) == 0)
5979 && (arm_decode_field (given, 7, 8) == 0))
5980 {
5981 *undefined_code = UNDEF_NOT_UNS_SIZE_0;
5982 return TRUE;
5983 }
5984 else
5985 return FALSE;
5986
5987 case MVE_VLDRH_GATHER_T2:
5988 if (arm_decode_field (given, 7, 8) == 3)
5989 {
5990 *undefined_code = UNDEF_SIZE_3;
5991 return TRUE;
5992 }
5993 else if ((arm_decode_field (given, 28, 28) == 0)
5994 && (arm_decode_field (given, 7, 8) == 1))
5995 {
5996 *undefined_code = UNDEF_NOT_UNS_SIZE_1;
5997 return TRUE;
5998 }
5999 else if (arm_decode_field (given, 7, 8) == 0)
6000 {
6001 *undefined_code = UNDEF_SIZE_0;
6002 return TRUE;
6003 }
6004 else
6005 return FALSE;
6006
6007 case MVE_VLDRW_GATHER_T3:
6008 if (arm_decode_field (given, 7, 8) != 2)
6009 {
6010 *undefined_code = UNDEF_SIZE_NOT_2;
6011 return TRUE;
6012 }
6013 else if (arm_decode_field (given, 28, 28) == 0)
6014 {
6015 *undefined_code = UNDEF_NOT_UNSIGNED;
6016 return TRUE;
6017 }
6018 else
6019 return FALSE;
6020
6021 case MVE_VLDRD_GATHER_T4:
6022 if (arm_decode_field (given, 7, 8) != 3)
6023 {
6024 *undefined_code = UNDEF_SIZE_NOT_3;
6025 return TRUE;
6026 }
6027 else if (arm_decode_field (given, 28, 28) == 0)
6028 {
6029 *undefined_code = UNDEF_NOT_UNSIGNED;
6030 return TRUE;
6031 }
6032 else
6033 return FALSE;
6034
6035 case MVE_VSTRB_SCATTER_T1:
6036 if (arm_decode_field (given, 7, 8) == 3)
6037 {
6038 *undefined_code = UNDEF_SIZE_3;
6039 return TRUE;
6040 }
6041 else
6042 return FALSE;
6043
6044 case MVE_VSTRH_SCATTER_T2:
6045 {
6046 unsigned long size = arm_decode_field (given, 7, 8);
6047 if (size == 3)
6048 {
6049 *undefined_code = UNDEF_SIZE_3;
6050 return TRUE;
6051 }
6052 else if (size == 0)
6053 {
6054 *undefined_code = UNDEF_SIZE_0;
6055 return TRUE;
6056 }
6057 else
6058 return FALSE;
6059 }
6060
6061 case MVE_VSTRW_SCATTER_T3:
6062 if (arm_decode_field (given, 7, 8) != 2)
6063 {
6064 *undefined_code = UNDEF_SIZE_NOT_2;
6065 return TRUE;
6066 }
6067 else
6068 return FALSE;
6069
6070 case MVE_VSTRD_SCATTER_T4:
6071 if (arm_decode_field (given, 7, 8) != 3)
6072 {
6073 *undefined_code = UNDEF_SIZE_NOT_3;
6074 return TRUE;
6075 }
6076 else
6077 return FALSE;
6078
bf0b396d
AV		 6079 case MVE_VCVT_FP_FIX_VEC:
6080 {
6081 unsigned long imm6 = arm_decode_field (given, 16, 21);
6082 if ((imm6 & 0x20) == 0)
6083 {
6084 *undefined_code = UNDEF_VCVT_IMM6;
6085 return TRUE;
6086 }
6087
6088 if ((arm_decode_field (given, 9, 9) == 0)
6089 && ((imm6 & 0x30) == 0x20))
6090 {
6091 *undefined_code = UNDEF_VCVT_FSI_IMM6;
6092 return TRUE;
6093 }
6094
6095 return FALSE;
6096 }
6097
f49bb598 6098 case MVE_VNEG_FP:
66dcaa5d 6099 case MVE_VABS_FP:
bf0b396d
AV		 6100 case MVE_VCVT_BETWEEN_FP_INT:
6101 case MVE_VCVT_FROM_FP_TO_INT:
6102 {
6103 unsigned long size = arm_decode_field (given, 18, 19);
6104 if (size == 0)
6105 {
6106 *undefined_code = UNDEF_SIZE_0;
6107 return TRUE;
6108 }
6109 else if (size == 3)
6110 {
6111 *undefined_code = UNDEF_SIZE_3;
6112 return TRUE;
6113 }
6114 else
6115 return FALSE;
6116 }
6117
c507f10b
AV		 6118 case MVE_VMOV_VEC_LANE_TO_GP:
6119 {
6120 unsigned long op1 = arm_decode_field (given, 21, 22);
6121 unsigned long op2 = arm_decode_field (given, 5, 6);
6122 unsigned long u = arm_decode_field (given, 23, 23);
6123
6124 if ((op2 == 0) && (u == 1))
6125 {
6126 if ((op1 == 0) || (op1 == 1))
6127 {
6128 *undefined_code = UNDEF_BAD_U_OP1_OP2;
6129 return TRUE;
6130 }
6131 else
6132 return FALSE;
6133 }
6134 else if (op2 == 2)
6135 {
6136 if ((op1 == 0) || (op1 == 1))
6137 {
6138 *undefined_code = UNDEF_BAD_OP1_OP2;
6139 return TRUE;
6140 }
6141 else
6142 return FALSE;
6143 }
6144
6145 return FALSE;
6146 }
6147
6148 case MVE_VMOV_GP_TO_VEC_LANE:
6149 if (arm_decode_field (given, 5, 6) == 2)
6150 {
6151 unsigned long op1 = arm_decode_field (given, 21, 22);
6152 if ((op1 == 0) || (op1 == 1))
6153 {
6154 *undefined_code = UNDEF_BAD_OP1_OP2;
6155 return TRUE;
6156 }
6157 else
6158 return FALSE;
6159 }
6160 else
6161 return FALSE;
6162
c4a23bf8
SP		 6163 case MVE_VMOV_VEC_TO_VEC:
6164 if ((arm_decode_field (given, 5, 5) == 1)
6165 || (arm_decode_field (given, 22, 22) == 1))
6166 return TRUE;
6167 return FALSE;
6168
c507f10b
AV		 6169 case MVE_VMOV_IMM_TO_VEC:
6170 if (arm_decode_field (given, 5, 5) == 0)
6171 {
6172 unsigned long cmode = arm_decode_field (given, 8, 11);
6173
6174 if (((cmode & 9) == 1) || ((cmode & 5) == 1))
6175 {
6176 *undefined_code = UNDEF_OP_0_BAD_CMODE;
6177 return TRUE;
6178 }
6179 else
6180 return FALSE;
6181 }
6182 else
6183 return FALSE;
6184
ed63aa17 6185 case MVE_VSHLL_T2:
14925797
AV		 6186 case MVE_VMOVN:
6187 if (arm_decode_field (given, 18, 19) == 2)
6188 {
6189 *undefined_code = UNDEF_SIZE_2;
6190 return TRUE;
6191 }
6192 else
6193 return FALSE;
6194
d3b63143
AV		 6195 case MVE_VRMLALDAVH:
6196 case MVE_VMLADAV_T1:
6197 case MVE_VMLADAV_T2:
6198 case MVE_VMLALDAV:
6199 if ((arm_decode_field (given, 28, 28) == 1)
6200 && (arm_decode_field (given, 12, 12) == 1))
6201 {
6202 *undefined_code = UNDEF_XCHG_UNS;
6203 return TRUE;
6204 }
6205 else
6206 return FALSE;
6207
ed63aa17
AV		 6208 case MVE_VQSHRN:
6209 case MVE_VQSHRUN:
6210 case MVE_VSHLL_T1:
6211 case MVE_VSHRN:
6212 {
6213 unsigned long sz = arm_decode_field (given, 19, 20);
6214 if (sz == 1)
6215 return FALSE;
6216 else if ((sz & 2) == 2)
6217 return FALSE;
6218 else
6219 {
6220 *undefined_code = UNDEF_SIZE;
6221 return TRUE;
6222 }
6223 }
6224 break;
6225
6226 case MVE_VQSHL_T2:
6227 case MVE_VQSHLU_T3:
6228 case MVE_VRSHR:
6229 case MVE_VSHL_T1:
6230 case MVE_VSHR:
6231 case MVE_VSLI:
6232 case MVE_VSRI:
6233 {
6234 unsigned long sz = arm_decode_field (given, 19, 21);
6235 if ((sz & 7) == 1)
6236 return FALSE;
6237 else if ((sz & 6) == 2)
6238 return FALSE;
6239 else if ((sz & 4) == 4)
6240 return FALSE;
6241 else
6242 {
6243 *undefined_code = UNDEF_SIZE;
6244 return TRUE;
6245 }
6246 }
6247
6248 case MVE_VQRSHRN:
6249 case MVE_VQRSHRUN:
6250 if (arm_decode_field (given, 19, 20) == 0)
6251 {
6252 *undefined_code = UNDEF_SIZE_0;
6253 return TRUE;
6254 }
6255 else
6256 return FALSE;
6257
66dcaa5d
AV		 6258 case MVE_VABS_VEC:
6259 if (arm_decode_field (given, 18, 19) == 3)
6260 {
6261 *undefined_code = UNDEF_SIZE_3;
6262 return TRUE;
6263 }
6264 else
6265 return FALSE;
6266
14b456f2
AV		 6267 case MVE_VQNEG:
6268 case MVE_VQABS:
f49bb598 6269 case MVE_VNEG_VEC:
e523f101
AV		 6270 case MVE_VCLS:
6271 case MVE_VCLZ:
6272 if (arm_decode_field (given, 18, 19) == 3)
6273 {
6274 *undefined_code = UNDEF_SIZE_3;
6275 return TRUE;
6276 }
6277 else
6278 return FALSE;
6279
14b456f2
AV		 6280 case MVE_VREV16:
6281 if (arm_decode_field (given, 18, 19) == 0)
6282 return FALSE;
6283 else
6284 {
6285 *undefined_code = UNDEF_SIZE_NOT_0;
6286 return TRUE;
6287 }
6288
6289 case MVE_VREV32:
6290 {
6291 unsigned long size = arm_decode_field (given, 18, 19);
6292 if ((size & 2) == 2)
6293 {
6294 *undefined_code = UNDEF_SIZE_2;
6295 return TRUE;
6296 }
6297 else
6298 return FALSE;
6299 }
6300
6301 case MVE_VREV64:
6302 if (arm_decode_field (given, 18, 19) != 3)
6303 return FALSE;
6304 else
6305 {
6306 *undefined_code = UNDEF_SIZE_3;
6307 return TRUE;
6308 }
6309
9743db03
AV		 6310 default:
6311 return FALSE;
6312 }
73cd51e5
AV		 6313}
6314
6315/* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6316 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
6317 why this encoding is unpredictable. */
6318
6319static bfd_boolean
6320is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
6321 enum mve_unpredictable *unpredictable_code)
6322{
6323 *unpredictable_code = UNPRED_NONE;
6324
143275ea
AV		 6325 switch (matched_insn)
6326 {
6327 case MVE_VCMP_FP_T2:
6328 case MVE_VPT_FP_T2:
6329 if ((arm_decode_field (given, 12, 12) == 0)
6330 && (arm_decode_field (given, 5, 5) == 1))
6331 {
6332 *unpredictable_code = UNPRED_FCA_0_FCB_1;
6333 return TRUE;
6334 }
6335 else
6336 return FALSE;
73cd51e5 6337
143275ea
AV		 6338 case MVE_VPT_VEC_T4:
6339 case MVE_VPT_VEC_T5:
6340 case MVE_VPT_VEC_T6:
6341 case MVE_VCMP_VEC_T4:
6342 case MVE_VCMP_VEC_T5:
6343 case MVE_VCMP_VEC_T6:
6344 if (arm_decode_field (given, 0, 3) == 0xd)
6345 {
6346 *unpredictable_code = UNPRED_R13;
6347 return TRUE;
6348 }
6349 else
6350 return FALSE;
c1e26897 6351
9743db03
AV		 6352 case MVE_VDUP:
6353 {
6354 unsigned long gpr = arm_decode_field (given, 12, 15);
6355 if (gpr == 0xd)
6356 {
6357 *unpredictable_code = UNPRED_R13;
6358 return TRUE;
6359 }
6360 else if (gpr == 0xf)
6361 {
6362 *unpredictable_code = UNPRED_R15;
6363 return TRUE;
6364 }
6365
6366 return FALSE;
6367 }
6368
14b456f2
AV		 6369 case MVE_VQADD_T2:
6370 case MVE_VQSUB_T2:
f49bb598
AV		 6371 case MVE_VMUL_FP_T2:
6372 case MVE_VMUL_VEC_T2:
56858bea 6373 case MVE_VMLA:
e523f101 6374 case MVE_VBRSR:
66dcaa5d
AV		 6375 case MVE_VADD_FP_T2:
6376 case MVE_VSUB_FP_T2:
6377 case MVE_VADD_VEC_T2:
6378 case MVE_VSUB_VEC_T2:
ed63aa17
AV		 6379 case MVE_VQRSHL_T2:
6380 case MVE_VQSHL_T1:
6381 case MVE_VRSHL_T2:
6382 case MVE_VSHL_T2:
6383 case MVE_VSHLC:
d3b63143
AV		 6384 case MVE_VQDMLAH:
6385 case MVE_VQRDMLAH:
6386 case MVE_VQDMLASH:
6387 case MVE_VQRDMLASH:
6388 case MVE_VQDMULH_T3:
6389 case MVE_VQRDMULH_T4:
6390 case MVE_VMLAS:
9743db03
AV		 6391 case MVE_VFMA_FP_SCALAR:
6392 case MVE_VFMAS_FP_SCALAR:
6393 case MVE_VHADD_T2:
6394 case MVE_VHSUB_T2:
6395 {
6396 unsigned long gpr = arm_decode_field (given, 0, 3);
6397 if (gpr == 0xd)
6398 {
6399 *unpredictable_code = UNPRED_R13;
6400 return TRUE;
6401 }
6402 else if (gpr == 0xf)
6403 {
6404 *unpredictable_code = UNPRED_R15;
6405 return TRUE;
6406 }
6407
6408 return FALSE;
6409 }
6410
04d54ace
AV		 6411 case MVE_VLD2:
6412 case MVE_VST2:
6413 {
6414 unsigned long rn = arm_decode_field (given, 16, 19);
6415
6416 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6417 {
6418 *unpredictable_code = UNPRED_R13_AND_WB;
6419 return TRUE;
6420 }
6421
6422 if (rn == 0xf)
6423 {
6424 *unpredictable_code = UNPRED_R15;
6425 return TRUE;
6426 }
6427
6428 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
6429 {
6430 *unpredictable_code = UNPRED_Q_GT_6;
6431 return TRUE;
6432 }
6433 else
6434 return FALSE;
6435 }
6436
6437 case MVE_VLD4:
6438 case MVE_VST4:
6439 {
6440 unsigned long rn = arm_decode_field (given, 16, 19);
6441
6442 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6443 {
6444 *unpredictable_code = UNPRED_R13_AND_WB;
6445 return TRUE;
6446 }
6447
6448 if (rn == 0xf)
6449 {
6450 *unpredictable_code = UNPRED_R15;
6451 return TRUE;
6452 }
6453
6454 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
6455 {
6456 *unpredictable_code = UNPRED_Q_GT_4;
6457 return TRUE;
6458 }
6459 else
6460 return FALSE;
6461 }
6462
aef6d006
AV		 6463 case MVE_VLDRB_T5:
6464 case MVE_VLDRH_T6:
6465 case MVE_VLDRW_T7:
6466 case MVE_VSTRB_T5:
6467 case MVE_VSTRH_T6:
6468 case MVE_VSTRW_T7:
6469 {
6470 unsigned long rn = arm_decode_field (given, 16, 19);
6471
6472 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6473 {
6474 *unpredictable_code = UNPRED_R13_AND_WB;
6475 return TRUE;
6476 }
6477 else if (rn == 0xf)
6478 {
6479 *unpredictable_code = UNPRED_R15;
6480 return TRUE;
6481 }
6482 else
6483 return FALSE;
6484 }
6485
ef1576a1
AV		 6486 case MVE_VLDRB_GATHER_T1:
6487 if (arm_decode_field (given, 0, 0) == 1)
6488 {
6489 *unpredictable_code = UNPRED_OS;
6490 return TRUE;
6491 }
6492
6493 /* fall through. */
6494 /* To handle common code with T2-T4 variants. */
6495 case MVE_VLDRH_GATHER_T2:
6496 case MVE_VLDRW_GATHER_T3:
6497 case MVE_VLDRD_GATHER_T4:
6498 {
6499 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6500 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6501
6502 if (qd == qm)
6503 {
6504 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6505 return TRUE;
6506 }
6507
6508 if (arm_decode_field (given, 16, 19) == 0xf)
6509 {
6510 *unpredictable_code = UNPRED_R15;
6511 return TRUE;
6512 }
6513
6514 return FALSE;
6515 }
6516
6517 case MVE_VLDRW_GATHER_T5:
6518 case MVE_VLDRD_GATHER_T6:
6519 {
6520 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6521 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
6522
6523 if (qd == qm)
6524 {
6525 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6526 return TRUE;
6527 }
6528 else
6529 return FALSE;
6530 }
6531
6532 case MVE_VSTRB_SCATTER_T1:
6533 if (arm_decode_field (given, 16, 19) == 0xf)
6534 {
6535 *unpredictable_code = UNPRED_R15;
6536 return TRUE;
6537 }
6538 else if (arm_decode_field (given, 0, 0) == 1)
6539 {
6540 *unpredictable_code = UNPRED_OS;
6541 return TRUE;
6542 }
6543 else
6544 return FALSE;
6545
6546 case MVE_VSTRH_SCATTER_T2:
6547 case MVE_VSTRW_SCATTER_T3:
6548 case MVE_VSTRD_SCATTER_T4:
6549 if (arm_decode_field (given, 16, 19) == 0xf)
6550 {
6551 *unpredictable_code = UNPRED_R15;
6552 return TRUE;
6553 }
6554 else
6555 return FALSE;
6556
c507f10b
AV		 6557 case MVE_VMOV2_VEC_LANE_TO_GP:
6558 case MVE_VMOV2_GP_TO_VEC_LANE:
bf0b396d
AV		 6559 case MVE_VCVT_BETWEEN_FP_INT:
6560 case MVE_VCVT_FROM_FP_TO_INT:
6561 {
6562 unsigned long rt = arm_decode_field (given, 0, 3);
6563 unsigned long rt2 = arm_decode_field (given, 16, 19);
6564
6565 if ((rt == 0xd) || (rt2 == 0xd))
6566 {
6567 *unpredictable_code = UNPRED_R13;
6568 return TRUE;
6569 }
6570 else if ((rt == 0xf) || (rt2 == 0xf))
6571 {
6572 *unpredictable_code = UNPRED_R15;
6573 return TRUE;
6574 }
6575 else if (rt == rt2)
6576 {
6577 *unpredictable_code = UNPRED_GP_REGS_EQUAL;
6578 return TRUE;
6579 }
6580
6581 return FALSE;
6582 }
6583
56858bea
AV		 6584 case MVE_VMAXV:
6585 case MVE_VMAXAV:
6586 case MVE_VMAXNMV_FP:
6587 case MVE_VMAXNMAV_FP:
6588 case MVE_VMINNMV_FP:
6589 case MVE_VMINNMAV_FP:
6590 case MVE_VMINV:
6591 case MVE_VMINAV:
66dcaa5d 6592 case MVE_VABAV:
c507f10b
AV		 6593 case MVE_VMOV_HFP_TO_GP:
6594 case MVE_VMOV_GP_TO_VEC_LANE:
6595 case MVE_VMOV_VEC_LANE_TO_GP:
6596 {
6597 unsigned long rda = arm_decode_field (given, 12, 15);
6598 if (rda == 0xd)
6599 {
6600 *unpredictable_code = UNPRED_R13;
6601 return TRUE;
6602 }
6603 else if (rda == 0xf)
6604 {
6605 *unpredictable_code = UNPRED_R15;
6606 return TRUE;
6607 }
6608
6609 return FALSE;
6610 }
6611
14925797
AV		 6612 case MVE_VMULL_INT:
6613 {
6614 unsigned long Qd;
6615 unsigned long Qm;
6616 unsigned long Qn;
6617
6618 if (arm_decode_field (given, 20, 21) == 2)
6619 {
6620 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6621 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6622 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6623
6624 if ((Qd == Qn) || (Qd == Qm))
6625 {
6626 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6627 return TRUE;
6628 }
6629 else
6630 return FALSE;
6631 }
6632 else
6633 return FALSE;
6634 }
6635
897b9bbc 6636 case MVE_VCMUL_FP:
14925797
AV		 6637 case MVE_VQDMULL_T1:
6638 {
6639 unsigned long Qd;
6640 unsigned long Qm;
6641 unsigned long Qn;
6642
6643 if (arm_decode_field (given, 28, 28) == 1)
6644 {
6645 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6646 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6647 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6648
6649 if ((Qd == Qn) || (Qd == Qm))
6650 {
6651 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6652 return TRUE;
6653 }
6654 else
6655 return FALSE;
6656 }
6657 else
6658 return FALSE;
6659 }
6660
6661 case MVE_VQDMULL_T2:
6662 {
6663 unsigned long gpr = arm_decode_field (given, 0, 3);
6664 if (gpr == 0xd)
6665 {
6666 *unpredictable_code = UNPRED_R13;
6667 return TRUE;
6668 }
6669 else if (gpr == 0xf)
6670 {
6671 *unpredictable_code = UNPRED_R15;
6672 return TRUE;
6673 }
6674
6675 if (arm_decode_field (given, 28, 28) == 1)
6676 {
6677 unsigned long Qd
6678 = arm_decode_field_multiple (given, 13, 15, 22, 22);
6679 unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6680
a9d96ab9 6681 if (Qd == Qn)
14925797
AV		 6682 {
6683 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6684 return TRUE;
6685 }
6686 else
6687 return FALSE;
6688 }
6689
6690 return FALSE;
6691 }
6692
d3b63143
AV		 6693 case MVE_VMLSLDAV:
6694 case MVE_VRMLSLDAVH:
6695 case MVE_VMLALDAV:
6696 case MVE_VADDLV:
6697 if (arm_decode_field (given, 20, 22) == 6)
6698 {
6699 *unpredictable_code = UNPRED_R13;
6700 return TRUE;
6701 }
6702 else
6703 return FALSE;
6704
1c8f2df8
AV		 6705 case MVE_VDWDUP:
6706 case MVE_VIWDUP:
6707 if (arm_decode_field (given, 1, 3) == 6)
6708 {
6709 *unpredictable_code = UNPRED_R13;
6710 return TRUE;
6711 }
6712 else
6713 return FALSE;
6714
897b9bbc
AV		 6715 case MVE_VCADD_VEC:
6716 case MVE_VHCADD:
6717 {
6718 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6719 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6720 if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
6721 {
6722 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6723 return TRUE;
6724 }
6725 else
6726 return FALSE;
6727 }
6728
6729 case MVE_VCADD_FP:
6730 {
6731 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6732 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6733 if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
6734 {
6735 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6736 return TRUE;
6737 }
6738 else
6739 return FALSE;
6740 }
6741
6742 case MVE_VCMLA_FP:
6743 {
6744 unsigned long Qda;
6745 unsigned long Qm;
6746 unsigned long Qn;
6747
6748 if (arm_decode_field (given, 20, 20) == 1)
6749 {
6750 Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
6751 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6752 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6753
6754 if ((Qda == Qn) || (Qda == Qm))
6755 {
6756 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6757 return TRUE;
6758 }
6759 else
6760 return FALSE;
6761 }
6762 else
6763 return FALSE;
6764
6765 }
6766
e523f101
AV		 6767 case MVE_VCTP:
6768 if (arm_decode_field (given, 16, 19) == 0xd)
6769 {
6770 *unpredictable_code = UNPRED_R13;
6771 return TRUE;
6772 }
6773 else
6774 return FALSE;
6775
14b456f2
AV		 6776 case MVE_VREV64:
6777 {
6778 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6779 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6);
6780
6781 if (qd == qm)
6782 {
6783 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6784 return TRUE;
6785 }
6786 else
6787 return FALSE;
6788 }
6789
23d00a41
SD		 6790 case MVE_LSLL:
6791 case MVE_LSLLI:
6792 case MVE_LSRL:
6793 case MVE_ASRL:
6794 case MVE_ASRLI:
6795 case MVE_UQSHLL:
6796 case MVE_UQRSHLL:
6797 case MVE_URSHRL:
6798 case MVE_SRSHRL:
6799 case MVE_SQSHLL:
6800 case MVE_SQRSHRL:
6801 {
6802 unsigned long gpr = arm_decode_field (given, 9, 11);
6803 gpr = ((gpr << 1) | 1);
6804 if (gpr == 0xd)
6805 {
6806 *unpredictable_code = UNPRED_R13;
6807 return TRUE;
6808 }
6809 else if (gpr == 0xf)
6810 {
6811 *unpredictable_code = UNPRED_R15;
6812 return TRUE;
6813 }
6814
6815 return FALSE;
6816 }
6817
143275ea
AV		 6818 default:
6819 return FALSE;
6820 }
6821}
c1e26897 6822
c507f10b
AV		 6823static void
6824print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
6825{
6826 unsigned long op1 = arm_decode_field (given, 21, 22);
6827 unsigned long op2 = arm_decode_field (given, 5, 6);
6828 unsigned long h = arm_decode_field (given, 16, 16);
43dd7626 6829 unsigned long index_operand, esize, targetBeat, idx;
c507f10b
AV		 6830 void *stream = info->stream;
6831 fprintf_ftype func = info->fprintf_func;
6832
6833 if ((op1 & 0x2) == 0x2)
6834 {
43dd7626 6835 index_operand = op2;
c507f10b
AV		 6836 esize = 8;
6837 }
6838 else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
6839 {
43dd7626 6840 index_operand = op2 >> 1;
c507f10b
AV		 6841 esize = 16;
6842 }
6843 else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
6844 {
43dd7626 6845 index_operand = 0;
c507f10b
AV		 6846 esize = 32;
6847 }
6848 else
6849 {
6850 func (stream, "<undefined index>");
6851 return;
6852 }
6853
6854 targetBeat = (op1 & 0x1) | (h << 1);
43dd7626 6855 idx = index_operand + targetBeat * (32/esize);
c507f10b
AV		 6856
6857 func (stream, "%lu", idx);
6858}
6859
6860/* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6861 in length and integer of floating-point type. */
6862static void
6863print_simd_imm8 (struct disassemble_info *info, unsigned long given,
6864 unsigned int ibit_loc, const struct mopcode32 *insn)
6865{
6866 int bits = 0;
6867 int cmode = (given >> 8) & 0xf;
6868 int op = (given >> 5) & 0x1;
6869 unsigned long value = 0, hival = 0;
6870 unsigned shift;
6871 int size = 0;
6872 int isfloat = 0;
6873 void *stream = info->stream;
6874 fprintf_ftype func = info->fprintf_func;
6875
6876 /* On Neon the 'i' bit is at bit 24, on mve it is
6877 at bit 28. */
6878 bits |= ((given >> ibit_loc) & 1) << 7;
6879 bits |= ((given >> 16) & 7) << 4;
6880 bits |= ((given >> 0) & 15) << 0;
6881
6882 if (cmode < 8)
6883 {
6884 shift = (cmode >> 1) & 3;
6885 value = (unsigned long) bits << (8 * shift);
6886 size = 32;
6887 }
6888 else if (cmode < 12)
6889 {
6890 shift = (cmode >> 1) & 1;
6891 value = (unsigned long) bits << (8 * shift);
6892 size = 16;
6893 }
6894 else if (cmode < 14)
6895 {
6896 shift = (cmode & 1) + 1;
6897 value = (unsigned long) bits << (8 * shift);
6898 value |= (1ul << (8 * shift)) - 1;
6899 size = 32;
6900 }
6901 else if (cmode == 14)
6902 {
6903 if (op)
6904 {
6905 /* Bit replication into bytes. */
6906 int ix;
6907 unsigned long mask;
6908
6909 value = 0;
6910 hival = 0;
6911 for (ix = 7; ix >= 0; ix--)
6912 {
6913 mask = ((bits >> ix) & 1) ? 0xff : 0;
6914 if (ix <= 3)
6915 value = (value << 8) | mask;
6916 else
6917 hival = (hival << 8) | mask;
6918 }
6919 size = 64;
6920 }
6921 else
6922 {
6923 /* Byte replication. */
6924 value = (unsigned long) bits;
6925 size = 8;
6926 }
6927 }
6928 else if (!op)
6929 {
6930 /* Floating point encoding. */
6931 int tmp;
6932
6933 value = (unsigned long) (bits & 0x7f) << 19;
6934 value |= (unsigned long) (bits & 0x80) << 24;
6935 tmp = bits & 0x40 ? 0x3c : 0x40;
6936 value |= (unsigned long) tmp << 24;
6937 size = 32;
6938 isfloat = 1;
6939 }
6940 else
6941 {
6942 func (stream, "<illegal constant %.8x:%x:%x>",
6943 bits, cmode, op);
6944 size = 32;
6945 return;
6946 }
6947
6948 // printU determines whether the immediate value should be printed as
6949 // unsigned.
6950 unsigned printU = 0;
6951 switch (insn->mve_op)
6952 {
6953 default:
6954 break;
6955 // We want this for instructions that don't have a 'signed' type
6956 case MVE_VBIC_IMM:
6957 case MVE_VORR_IMM:
6958 case MVE_VMVN_IMM:
6959 case MVE_VMOV_IMM_TO_VEC:
6960 printU = 1;
6961 break;
6962 }
6963 switch (size)
6964 {
6965 case 8:
6966 func (stream, "#%ld\t; 0x%.2lx", value, value);
6967 break;
6968
6969 case 16:
6970 func (stream,
6971 printU
6972 ? "#%lu\t; 0x%.4lx"
6973 : "#%ld\t; 0x%.4lx", value, value);
6974 break;
6975
6976 case 32:
6977 if (isfloat)
6978 {
6979 unsigned char valbytes[4];
6980 double fvalue;
6981
6982 /* Do this a byte at a time so we don't have to
6983 worry about the host's endianness. */
6984 valbytes[0] = value & 0xff;
6985 valbytes[1] = (value >> 8) & 0xff;
6986 valbytes[2] = (value >> 16) & 0xff;
6987 valbytes[3] = (value >> 24) & 0xff;
6988
6989 floatformat_to_double
6990 (& floatformat_ieee_single_little, valbytes,
6991 & fvalue);
6992
6993 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
6994 value);
6995 }
6996 else
6997 func (stream,
6998 printU
6999 ? "#%lu\t; 0x%.8lx"
7000 : "#%ld\t; 0x%.8lx",
7001 (long) (((value & 0x80000000L) != 0)
7002 && !printU
7003 ? value | ~0xffffffffL : value),
7004 value);
7005 break;
7006
7007 case 64:
7008 func (stream, "#0x%.8lx%.8lx", hival, value);
7009 break;
7010
7011 default:
7012 abort ();
7013 }
7014
7015}
7016
73cd51e5
AV		 7017static void
7018print_mve_undefined (struct disassemble_info *info,
7019 enum mve_undefined undefined_code)
7020{
7021 void *stream = info->stream;
7022 fprintf_ftype func = info->fprintf_func;
7023
7024 func (stream, "\t\tundefined instruction: ");
7025
7026 switch (undefined_code)
7027 {
ed63aa17
AV		 7028 case UNDEF_SIZE:
7029 func (stream, "illegal size");
7030 break;
7031
aef6d006
AV		 7032 case UNDEF_SIZE_0:
7033 func (stream, "size equals zero");
7034 break;
7035
c507f10b
AV		 7036 case UNDEF_SIZE_2:
7037 func (stream, "size equals two");
7038 break;
7039
9743db03
AV		 7040 case UNDEF_SIZE_3:
7041 func (stream, "size equals three");
7042 break;
7043
aef6d006
AV		 7044 case UNDEF_SIZE_LE_1:
7045 func (stream, "size <= 1");
7046 break;
7047
14b456f2
AV		 7048 case UNDEF_SIZE_NOT_0:
7049 func (stream, "size not equal to 0");
7050 break;
7051
ef1576a1
AV		 7052 case UNDEF_SIZE_NOT_2:
7053 func (stream, "size not equal to 2");
7054 break;
7055
7056 case UNDEF_SIZE_NOT_3:
7057 func (stream, "size not equal to 3");
7058 break;
7059
7060 case UNDEF_NOT_UNS_SIZE_0:
7061 func (stream, "not unsigned and size = zero");
7062 break;
7063
7064 case UNDEF_NOT_UNS_SIZE_1:
7065 func (stream, "not unsigned and size = one");
7066 break;
7067
7068 case UNDEF_NOT_UNSIGNED:
7069 func (stream, "not unsigned");
7070 break;
7071
bf0b396d
AV		 7072 case UNDEF_VCVT_IMM6:
7073 func (stream, "invalid imm6");
7074 break;
7075
7076 case UNDEF_VCVT_FSI_IMM6:
7077 func (stream, "fsi = 0 and invalid imm6");
7078 break;
7079
c507f10b
AV		 7080 case UNDEF_BAD_OP1_OP2:
7081 func (stream, "bad size with op2 = 2 and op1 = 0 or 1");
7082 break;
7083
7084 case UNDEF_BAD_U_OP1_OP2:
7085 func (stream, "unsigned with op2 = 0 and op1 = 0 or 1");
7086 break;
7087
7088 case UNDEF_OP_0_BAD_CMODE:
7089 func (stream, "op field equal 0 and bad cmode");
7090 break;
7091
d3b63143
AV		 7092 case UNDEF_XCHG_UNS:
7093 func (stream, "exchange and unsigned together");
7094 break;
7095
73cd51e5
AV		 7096 case UNDEF_NONE:
7097 break;
7098 }
7099
7100}
7101
7102static void
7103print_mve_unpredictable (struct disassemble_info *info,
7104 enum mve_unpredictable unpredict_code)
7105{
7106 void *stream = info->stream;
7107 fprintf_ftype func = info->fprintf_func;
7108
7109 func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
7110
7111 switch (unpredict_code)
7112 {
7113 case UNPRED_IT_BLOCK:
7114 func (stream, "mve instruction in it block");
7115 break;
7116
143275ea
AV		 7117 case UNPRED_FCA_0_FCB_1:
7118 func (stream, "condition bits, fca = 0 and fcb = 1");
7119 break;
7120
7121 case UNPRED_R13:
7122 func (stream, "use of r13 (sp)");
7123 break;
7124
9743db03
AV		 7125 case UNPRED_R15:
7126 func (stream, "use of r15 (pc)");
7127 break;
7128
04d54ace
AV		 7129 case UNPRED_Q_GT_4:
7130 func (stream, "start register block > r4");
7131 break;
7132
7133 case UNPRED_Q_GT_6:
7134 func (stream, "start register block > r6");
7135 break;
7136
7137 case UNPRED_R13_AND_WB:
7138 func (stream, "use of r13 and write back");
7139 break;
7140
ef1576a1
AV		 7141 case UNPRED_Q_REGS_EQUAL:
7142 func (stream,
7143 "same vector register used for destination and other operand");
7144 break;
7145
7146 case UNPRED_OS:
7147 func (stream, "use of offset scaled");
7148 break;
7149
bf0b396d
AV		 7150 case UNPRED_GP_REGS_EQUAL:
7151 func (stream, "same general-purpose register used for both operands");
7152 break;
7153
c507f10b
AV		 7154 case UNPRED_Q_REGS_EQ_AND_SIZE_1:
7155 func (stream, "use of identical q registers and size = 1");
7156 break;
7157
7158 case UNPRED_Q_REGS_EQ_AND_SIZE_2:
7159 func (stream, "use of identical q registers and size = 1");
7160 break;
7161
73cd51e5
AV		 7162 case UNPRED_NONE:
7163 break;
7164 }
7165}
7166
04d54ace
AV		 7167/* Print register block operand for mve vld2/vld4/vst2/vld4. */
7168
7169static void
7170print_mve_register_blocks (struct disassemble_info *info,
7171 unsigned long given,
7172 enum mve_instructions matched_insn)
7173{
7174 void *stream = info->stream;
7175 fprintf_ftype func = info->fprintf_func;
7176
7177 unsigned long q_reg_start = arm_decode_field_multiple (given,
7178 13, 15,
7179 22, 22);
7180 switch (matched_insn)
7181 {
7182 case MVE_VLD2:
7183 case MVE_VST2:
7184 if (q_reg_start <= 6)
7185 func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
7186 else
7187 func (stream, "<illegal reg q%ld>", q_reg_start);
7188 break;
7189
7190 case MVE_VLD4:
7191 case MVE_VST4:
7192 if (q_reg_start <= 4)
7193 func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
7194 q_reg_start + 1, q_reg_start + 2,
7195 q_reg_start + 3);
7196 else
7197 func (stream, "<illegal reg q%ld>", q_reg_start);
7198 break;
7199
7200 default:
7201 break;
7202 }
7203}
7204
bf0b396d
AV		 7205static void
7206print_mve_rounding_mode (struct disassemble_info *info,
7207 unsigned long given,
7208 enum mve_instructions matched_insn)
7209{
7210 void *stream = info->stream;
7211 fprintf_ftype func = info->fprintf_func;
7212
7213 switch (matched_insn)
7214 {
7215 case MVE_VCVT_FROM_FP_TO_INT:
7216 {
7217 switch (arm_decode_field (given, 8, 9))
7218 {
7219 case 0:
7220 func (stream, "a");
7221 break;
7222
7223 case 1:
7224 func (stream, "n");
7225 break;
7226
7227 case 2:
7228 func (stream, "p");
7229 break;
7230
7231 case 3:
7232 func (stream, "m");
7233 break;
7234
7235 default:
7236 break;
7237 }
7238 }
7239 break;
7240
7241 case MVE_VRINT_FP:
7242 {
7243 switch (arm_decode_field (given, 7, 9))
7244 {
7245 case 0:
7246 func (stream, "n");
7247 break;
7248
7249 case 1:
7250 func (stream, "x");
7251 break;
7252
7253 case 2:
7254 func (stream, "a");
7255 break;
7256
7257 case 3:
7258 func (stream, "z");
7259 break;
7260
7261 case 5:
7262 func (stream, "m");
7263 break;
7264
7265 case 7:
7266 func (stream, "p");
7267
7268 case 4:
7269 case 6:
7270 default:
7271 break;
7272 }
7273 }
7274 break;
7275
7276 default:
7277 break;
7278 }
7279}
7280
7281static void
7282print_mve_vcvt_size (struct disassemble_info *info,
7283 unsigned long given,
7284 enum mve_instructions matched_insn)
7285{
7286 unsigned long mode = 0;
7287 void *stream = info->stream;
7288 fprintf_ftype func = info->fprintf_func;
7289
7290 switch (matched_insn)
7291 {
7292 case MVE_VCVT_FP_FIX_VEC:
7293 {
7294 mode = (((given & 0x200) >> 7)
7295 | ((given & 0x10000000) >> 27)
7296 | ((given & 0x100) >> 8));
7297
7298 switch (mode)
7299 {
7300 case 0:
7301 func (stream, "f16.s16");
7302 break;
7303
7304 case 1:
7305 func (stream, "s16.f16");
7306 break;
7307
7308 case 2:
7309 func (stream, "f16.u16");
7310 break;
7311
7312 case 3:
7313 func (stream, "u16.f16");
7314 break;
7315
7316 case 4:
7317 func (stream, "f32.s32");
7318 break;
7319
7320 case 5:
7321 func (stream, "s32.f32");
7322 break;
7323
7324 case 6:
7325 func (stream, "f32.u32");
7326 break;
7327
7328 case 7:
7329 func (stream, "u32.f32");
7330 break;
7331
7332 default:
7333 break;
7334 }
7335 break;
7336 }
7337 case MVE_VCVT_BETWEEN_FP_INT:
7338 {
7339 unsigned long size = arm_decode_field (given, 18, 19);
7340 unsigned long op = arm_decode_field (given, 7, 8);
7341
7342 if (size == 1)
7343 {
7344 switch (op)
7345 {
7346 case 0:
7347 func (stream, "f16.s16");
7348 break;
7349
7350 case 1:
7351 func (stream, "f16.u16");
7352 break;
7353
7354 case 2:
7355 func (stream, "s16.f16");
7356 break;
7357
7358 case 3:
7359 func (stream, "u16.f16");
7360 break;
7361
7362 default:
7363 break;
7364 }
7365 }
7366 else if (size == 2)
7367 {
7368 switch (op)
7369 {
7370 case 0:
7371 func (stream, "f32.s32");
7372 break;
7373
7374 case 1:
7375 func (stream, "f32.u32");
7376 break;
7377
7378 case 2:
7379 func (stream, "s32.f32");
7380 break;
7381
7382 case 3:
7383 func (stream, "u32.f32");
7384 break;
7385 }
7386 }
7387 }
7388 break;
7389
7390 case MVE_VCVT_FP_HALF_FP:
7391 {
7392 unsigned long op = arm_decode_field (given, 28, 28);
7393 if (op == 0)
7394 func (stream, "f16.f32");
7395 else if (op == 1)
7396 func (stream, "f32.f16");
7397 }
7398 break;
7399
7400 case MVE_VCVT_FROM_FP_TO_INT:
7401 {
7402 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
7403
7404 switch (size)
7405 {
7406 case 2:
7407 func (stream, "s16.f16");
7408 break;
7409
7410 case 3:
7411 func (stream, "u16.f16");
7412 break;
7413
7414 case 4:
7415 func (stream, "s32.f32");
7416 break;
7417
7418 case 5:
7419 func (stream, "u32.f32");
7420 break;
7421
7422 default:
7423 break;
7424 }
7425 }
7426 break;
7427
7428 default:
7429 break;
7430 }
7431}
7432
897b9bbc
AV		 7433static void
7434print_mve_rotate (struct disassemble_info *info, unsigned long rot,
7435 unsigned long rot_width)
7436{
7437 void *stream = info->stream;
7438 fprintf_ftype func = info->fprintf_func;
7439
7440 if (rot_width == 1)
7441 {
7442 switch (rot)
7443 {
7444 case 0:
7445 func (stream, "90");
7446 break;
7447 case 1:
7448 func (stream, "270");
7449 break;
7450 default:
7451 break;
7452 }
7453 }
7454 else if (rot_width == 2)
7455 {
7456 switch (rot)
7457 {
7458 case 0:
7459 func (stream, "0");
7460 break;
7461 case 1:
7462 func (stream, "90");
7463 break;
7464 case 2:
7465 func (stream, "180");
7466 break;
7467 case 3:
7468 func (stream, "270");
7469 break;
7470 default:
7471 break;
7472 }
7473 }
7474}
7475
143275ea
AV		 7476static void
7477print_instruction_predicate (struct disassemble_info *info)
7478{
7479 void *stream = info->stream;
7480 fprintf_ftype func = info->fprintf_func;
7481
7482 if (vpt_block_state.next_pred_state == PRED_THEN)
7483 func (stream, "t");
7484 else if (vpt_block_state.next_pred_state == PRED_ELSE)
7485 func (stream, "e");
7486}
7487
7488static void
7489print_mve_size (struct disassemble_info *info,
7490 unsigned long size,
7491 enum mve_instructions matched_insn)
7492{
7493 void *stream = info->stream;
7494 fprintf_ftype func = info->fprintf_func;
7495
7496 switch (matched_insn)
7497 {
66dcaa5d
AV		 7498 case MVE_VABAV:
7499 case MVE_VABD_VEC:
7500 case MVE_VABS_FP:
7501 case MVE_VABS_VEC:
7502 case MVE_VADD_VEC_T1:
7503 case MVE_VADD_VEC_T2:
d3b63143 7504 case MVE_VADDV:
e523f101 7505 case MVE_VBRSR:
897b9bbc 7506 case MVE_VCADD_VEC:
e523f101
AV		 7507 case MVE_VCLS:
7508 case MVE_VCLZ:
143275ea
AV		 7509 case MVE_VCMP_VEC_T1:
7510 case MVE_VCMP_VEC_T2:
7511 case MVE_VCMP_VEC_T3:
7512 case MVE_VCMP_VEC_T4:
7513 case MVE_VCMP_VEC_T5:
7514 case MVE_VCMP_VEC_T6:
e523f101 7515 case MVE_VCTP:
1c8f2df8
AV		 7516 case MVE_VDDUP:
7517 case MVE_VDWDUP:
9743db03
AV		 7518 case MVE_VHADD_T1:
7519 case MVE_VHADD_T2:
897b9bbc 7520 case MVE_VHCADD:
9743db03
AV		 7521 case MVE_VHSUB_T1:
7522 case MVE_VHSUB_T2:
1c8f2df8
AV		 7523 case MVE_VIDUP:
7524 case MVE_VIWDUP:
04d54ace
AV		 7525 case MVE_VLD2:
7526 case MVE_VLD4:
ef1576a1
AV		 7527 case MVE_VLDRB_GATHER_T1:
7528 case MVE_VLDRH_GATHER_T2:
7529 case MVE_VLDRW_GATHER_T3:
7530 case MVE_VLDRD_GATHER_T4:
aef6d006
AV		 7531 case MVE_VLDRB_T1:
7532 case MVE_VLDRH_T2:
56858bea
AV		 7533 case MVE_VMAX:
7534 case MVE_VMAXA:
7535 case MVE_VMAXV:
7536 case MVE_VMAXAV:
7537 case MVE_VMIN:
7538 case MVE_VMINA:
7539 case MVE_VMINV:
7540 case MVE_VMINAV:
7541 case MVE_VMLA:
d3b63143 7542 case MVE_VMLAS:
f49bb598
AV		 7543 case MVE_VMUL_VEC_T1:
7544 case MVE_VMUL_VEC_T2:
7545 case MVE_VMULH:
7546 case MVE_VRMULH:
7547 case MVE_VMULL_INT:
7548 case MVE_VNEG_FP:
7549 case MVE_VNEG_VEC:
143275ea
AV		 7550 case MVE_VPT_VEC_T1:
7551 case MVE_VPT_VEC_T2:
7552 case MVE_VPT_VEC_T3:
7553 case MVE_VPT_VEC_T4:
7554 case MVE_VPT_VEC_T5:
7555 case MVE_VPT_VEC_T6:
14b456f2
AV		 7556 case MVE_VQABS:
7557 case MVE_VQADD_T1:
7558 case MVE_VQADD_T2:
d3b63143
AV		 7559 case MVE_VQDMLADH:
7560 case MVE_VQRDMLADH:
7561 case MVE_VQDMLAH:
7562 case MVE_VQRDMLAH:
7563 case MVE_VQDMLASH:
7564 case MVE_VQRDMLASH:
7565 case MVE_VQDMLSDH:
7566 case MVE_VQRDMLSDH:
7567 case MVE_VQDMULH_T1:
7568 case MVE_VQRDMULH_T2:
7569 case MVE_VQDMULH_T3:
7570 case MVE_VQRDMULH_T4:
14b456f2 7571 case MVE_VQNEG:
ed63aa17
AV		 7572 case MVE_VQRSHL_T1:
7573 case MVE_VQRSHL_T2:
7574 case MVE_VQSHL_T1:
7575 case MVE_VQSHL_T4:
14b456f2
AV		 7576 case MVE_VQSUB_T1:
7577 case MVE_VQSUB_T2:
7578 case MVE_VREV32:
7579 case MVE_VREV64:
9743db03 7580 case MVE_VRHADD:
bf0b396d 7581 case MVE_VRINT_FP:
ed63aa17
AV		 7582 case MVE_VRSHL_T1:
7583 case MVE_VRSHL_T2:
7584 case MVE_VSHL_T2:
7585 case MVE_VSHL_T3:
7586 case MVE_VSHLL_T2:
04d54ace
AV		 7587 case MVE_VST2:
7588 case MVE_VST4:
ef1576a1
AV		 7589 case MVE_VSTRB_SCATTER_T1:
7590 case MVE_VSTRH_SCATTER_T2:
7591 case MVE_VSTRW_SCATTER_T3:
aef6d006
AV		 7592 case MVE_VSTRB_T1:
7593 case MVE_VSTRH_T2:
66dcaa5d
AV		 7594 case MVE_VSUB_VEC_T1:
7595 case MVE_VSUB_VEC_T2:
143275ea
AV		 7596 if (size <= 3)
7597 func (stream, "%s", mve_vec_sizename[size]);
7598 else
7599 func (stream, "<undef size>");
7600 break;
7601
66dcaa5d
AV		 7602 case MVE_VABD_FP:
7603 case MVE_VADD_FP_T1:
7604 case MVE_VADD_FP_T2:
7605 case MVE_VSUB_FP_T1:
7606 case MVE_VSUB_FP_T2:
143275ea
AV		 7607 case MVE_VCMP_FP_T1:
7608 case MVE_VCMP_FP_T2:
9743db03
AV		 7609 case MVE_VFMA_FP_SCALAR:
7610 case MVE_VFMA_FP:
7611 case MVE_VFMS_FP:
7612 case MVE_VFMAS_FP_SCALAR:
56858bea
AV		 7613 case MVE_VMAXNM_FP:
7614 case MVE_VMAXNMA_FP:
7615 case MVE_VMAXNMV_FP:
7616 case MVE_VMAXNMAV_FP:
7617 case MVE_VMINNM_FP:
7618 case MVE_VMINNMA_FP:
7619 case MVE_VMINNMV_FP:
7620 case MVE_VMINNMAV_FP:
f49bb598
AV		 7621 case MVE_VMUL_FP_T1:
7622 case MVE_VMUL_FP_T2:
143275ea
AV		 7623 case MVE_VPT_FP_T1:
7624 case MVE_VPT_FP_T2:
7625 if (size == 0)
7626 func (stream, "32");
7627 else if (size == 1)
7628 func (stream, "16");
7629 break;
7630
897b9bbc
AV		 7631 case MVE_VCADD_FP:
7632 case MVE_VCMLA_FP:
7633 case MVE_VCMUL_FP:
d3b63143
AV		 7634 case MVE_VMLADAV_T1:
7635 case MVE_VMLALDAV:
7636 case MVE_VMLSDAV_T1:
7637 case MVE_VMLSLDAV:
14925797
AV		 7638 case MVE_VMOVN:
7639 case MVE_VQDMULL_T1:
7640 case MVE_VQDMULL_T2:
7641 case MVE_VQMOVN:
7642 case MVE_VQMOVUN:
7643 if (size == 0)
7644 func (stream, "16");
7645 else if (size == 1)
7646 func (stream, "32");
7647 break;
7648
7649 case MVE_VMOVL:
7650 if (size == 1)
7651 func (stream, "8");
7652 else if (size == 2)
7653 func (stream, "16");
7654 break;
7655
9743db03
AV		 7656 case MVE_VDUP:
7657 switch (size)
7658 {
7659 case 0:
7660 func (stream, "32");
7661 break;
7662 case 1:
7663 func (stream, "16");
7664 break;
7665 case 2:
7666 func (stream, "8");
7667 break;
7668 default:
7669 break;
7670 }
7671 break;
7672
c507f10b
AV		 7673 case MVE_VMOV_GP_TO_VEC_LANE:
7674 case MVE_VMOV_VEC_LANE_TO_GP:
7675 switch (size)
7676 {
7677 case 0: case 4:
7678 func (stream, "32");
7679 break;
7680
7681 case 1: case 3:
7682 case 5: case 7:
7683 func (stream, "16");
7684 break;
7685
7686 case 8: case 9: case 10: case 11:
7687 case 12: case 13: case 14: case 15:
7688 func (stream, "8");
7689 break;
7690
7691 default:
7692 break;
7693 }
7694 break;
7695
7696 case MVE_VMOV_IMM_TO_VEC:
7697 switch (size)
7698 {
7699 case 0: case 4: case 8:
7700 case 12: case 24: case 26:
7701 func (stream, "i32");
7702 break;
7703 case 16: case 20:
7704 func (stream, "i16");
7705 break;
7706 case 28:
7707 func (stream, "i8");
7708 break;
7709 case 29:
7710 func (stream, "i64");
7711 break;
7712 case 30:
7713 func (stream, "f32");
7714 break;
7715 default:
7716 break;
7717 }
7718 break;
7719
14925797
AV		 7720 case MVE_VMULL_POLY:
7721 if (size == 0)
7722 func (stream, "p8");
7723 else if (size == 1)
7724 func (stream, "p16");
7725 break;
7726
c507f10b
AV		 7727 case MVE_VMVN_IMM:
7728 switch (size)
7729 {
7730 case 0: case 2: case 4:
7731 case 6: case 12: case 13:
7732 func (stream, "32");
7733 break;
7734
7735 case 8: case 10:
7736 func (stream, "16");
7737 break;
7738
7739 default:
7740 break;
7741 }
7742 break;
7743
7744 case MVE_VBIC_IMM:
7745 case MVE_VORR_IMM:
7746 switch (size)
7747 {
7748 case 1: case 3:
7749 case 5: case 7:
7750 func (stream, "32");
7751 break;
7752
7753 case 9: case 11:
7754 func (stream, "16");
7755 break;
7756
7757 default:
7758 break;
7759 }
7760 break;
7761
ed63aa17
AV		 7762 case MVE_VQSHRN:
7763 case MVE_VQSHRUN:
7764 case MVE_VQRSHRN:
7765 case MVE_VQRSHRUN:
7766 case MVE_VRSHRN:
7767 case MVE_VSHRN:
7768 {
7769 switch (size)
7770 {
7771 case 1:
7772 func (stream, "16");
7773 break;
7774
7775 case 2: case 3:
7776 func (stream, "32");
7777 break;
7778
7779 default:
7780 break;
7781 }
7782 }
7783 break;
7784
7785 case MVE_VQSHL_T2:
7786 case MVE_VQSHLU_T3:
7787 case MVE_VRSHR:
7788 case MVE_VSHL_T1:
7789 case MVE_VSHLL_T1:
7790 case MVE_VSHR:
7791 case MVE_VSLI:
7792 case MVE_VSRI:
7793 {
7794 switch (size)
7795 {
7796 case 1:
7797 func (stream, "8");
7798 break;
7799
7800 case 2: case 3:
7801 func (stream, "16");
7802 break;
7803
7804 case 4: case 5: case 6: case 7:
7805 func (stream, "32");
7806 break;
7807
7808 default:
7809 break;
7810 }
7811 }
7812 break;
7813
143275ea
AV		 7814 default:
7815 break;
7816 }
7817}
7818
ed63aa17
AV		 7819static void
7820print_mve_shift_n (struct disassemble_info *info, long given,
7821 enum mve_instructions matched_insn)
7822{
7823 void *stream = info->stream;
7824 fprintf_ftype func = info->fprintf_func;
7825
7826 int startAt0
7827 = matched_insn == MVE_VQSHL_T2
7828 || matched_insn == MVE_VQSHLU_T3
7829 || matched_insn == MVE_VSHL_T1
7830 || matched_insn == MVE_VSHLL_T1
7831 || matched_insn == MVE_VSLI;
7832
7833 unsigned imm6 = (given & 0x3f0000) >> 16;
7834
7835 if (matched_insn == MVE_VSHLL_T1)
7836 imm6 &= 0x1f;
7837
7838 unsigned shiftAmount = 0;
7839 if ((imm6 & 0x20) != 0)
7840 shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
7841 else if ((imm6 & 0x10) != 0)
7842 shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
7843 else if ((imm6 & 0x08) != 0)
7844 shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
7845 else
7846 print_mve_undefined (info, UNDEF_SIZE_0);
7847
7848 func (stream, "%u", shiftAmount);
7849}
7850
143275ea
AV		 7851static void
7852print_vec_condition (struct disassemble_info *info, long given,
7853 enum mve_instructions matched_insn)
7854{
7855 void *stream = info->stream;
7856 fprintf_ftype func = info->fprintf_func;
7857 long vec_cond = 0;
7858
7859 switch (matched_insn)
7860 {
7861 case MVE_VPT_FP_T1:
7862 case MVE_VCMP_FP_T1:
7863 vec_cond = (((given & 0x1000) >> 10)
7864 | ((given & 1) << 1)
7865 | ((given & 0x0080) >> 7));
7866 func (stream, "%s",vec_condnames[vec_cond]);
7867 break;
7868
7869 case MVE_VPT_FP_T2:
7870 case MVE_VCMP_FP_T2:
7871 vec_cond = (((given & 0x1000) >> 10)
7872 | ((given & 0x0020) >> 4)
7873 | ((given & 0x0080) >> 7));
7874 func (stream, "%s",vec_condnames[vec_cond]);
7875 break;
7876
7877 case MVE_VPT_VEC_T1:
7878 case MVE_VCMP_VEC_T1:
7879 vec_cond = (given & 0x0080) >> 7;
7880 func (stream, "%s",vec_condnames[vec_cond]);
7881 break;
7882
7883 case MVE_VPT_VEC_T2:
7884 case MVE_VCMP_VEC_T2:
7885 vec_cond = 2 | ((given & 0x0080) >> 7);
7886 func (stream, "%s",vec_condnames[vec_cond]);
7887 break;
7888
7889 case MVE_VPT_VEC_T3:
7890 case MVE_VCMP_VEC_T3:
7891 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
7892 func (stream, "%s",vec_condnames[vec_cond]);
7893 break;
7894
7895 case MVE_VPT_VEC_T4:
7896 case MVE_VCMP_VEC_T4:
7897 vec_cond = (given & 0x0080) >> 7;
7898 func (stream, "%s",vec_condnames[vec_cond]);
7899 break;
7900
7901 case MVE_VPT_VEC_T5:
7902 case MVE_VCMP_VEC_T5:
7903 vec_cond = 2 | ((given & 0x0080) >> 7);
7904 func (stream, "%s",vec_condnames[vec_cond]);
7905 break;
7906
7907 case MVE_VPT_VEC_T6:
7908 case MVE_VCMP_VEC_T6:
7909 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
7910 func (stream, "%s",vec_condnames[vec_cond]);
7911 break;
7912
7913 case MVE_NONE:
7914 case MVE_VPST:
7915 default:
7916 break;
7917 }
7918}
7919
7920#define W_BIT 21
7921#define I_BIT 22
7922#define U_BIT 23
7923#define P_BIT 24
7924
7925#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
7926#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
7927#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
7928#define PRE_BIT_SET (given & (1 << P_BIT))
7929
7930
8f06b2d8
PB		 7931/* Print one coprocessor instruction on INFO->STREAM.
7932 Return TRUE if the instuction matched, FALSE if this is not a
7933 recognised coprocessor instruction. */
7934
7935static bfd_boolean
33593eaf
MM		 7936print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
7937 bfd_vma pc,
7938 struct disassemble_info *info,
7939 long given,
7940 bfd_boolean thumb)
8f06b2d8 7941{
6b0dd094 7942 const struct sopcode32 *insn;
8f06b2d8
PB		 7943 void *stream = info->stream;
7944 fprintf_ftype func = info->fprintf_func;
7945 unsigned long mask;
2edcd244 7946 unsigned long value = 0;
c22aaad1 7947 int cond;
8afc7bea 7948 int cp_num;
823d2571
TG		 7949 struct arm_private_data *private_data = info->private_data;
7950 arm_feature_set allowed_arches = ARM_ARCH_NONE;
32c36c3c
AV		 7951 arm_feature_set arm_ext_v8_1m_main =
7952 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
823d2571 7953
5b616bef 7954 allowed_arches = private_data->features;
8f06b2d8 7955
33593eaf 7956 for (insn = opcodes; insn->assembler; insn++)
8f06b2d8 7957 {
ff4a8d2b
NC		 7958 unsigned long u_reg = 16;
7959 bfd_boolean is_unpredictable = FALSE;
05413229 7960 signed long value_in_comment = 0;
0313a2b8
NC		 7961 const char *c;
7962
823d2571 7963 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 7964 switch (insn->value)
7965 {
7966 case SENTINEL_IWMMXT_START:
7967 if (info->mach != bfd_mach_arm_XScale
7968 && info->mach != bfd_mach_arm_iWMMXt
7969 && info->mach != bfd_mach_arm_iWMMXt2)
7970 do
7971 insn++;
823d2571
TG		 7972 while ((! ARM_FEATURE_ZERO (insn->arch))
7973 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 7974 continue;
7975
7976 case SENTINEL_IWMMXT_END:
7977 continue;
7978
7979 case SENTINEL_GENERIC_START:
5b616bef 7980 allowed_arches = private_data->features;
05413229
NC		 7981 continue;
7982
7983 default:
7984 abort ();
7985 }
8f06b2d8
PB		 7986
7987 mask = insn->mask;
7988 value = insn->value;
8afc7bea
RL		 7989 cp_num = (given >> 8) & 0xf;
7990
8f06b2d8
PB		 7991 if (thumb)
7992 {
7993 /* The high 4 bits are 0xe for Arm conditional instructions, and
7994 0xe for arm unconditional instructions. The rest of the
7995 encoding is the same. */
7996 mask |= 0xf0000000;
7997 value |= 0xe0000000;
c22aaad1
PB		 7998 if (ifthen_state)
7999 cond = IFTHEN_COND;
8000 else
e2efe87d 8001 cond = COND_UNCOND;
8f06b2d8
PB		 8002 }
8003 else
8004 {
8005 /* Only match unconditional instuctions against unconditional
8006 patterns. */
8007 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 8008 {
8009 mask |= 0xf0000000;
e2efe87d 8010 cond = COND_UNCOND;
c22aaad1
PB		 8011 }
8012 else
8013 {
8014 cond = (given >> 28) & 0xf;
8015 if (cond == 0xe)
e2efe87d 8016 cond = COND_UNCOND;
c22aaad1 8017 }
8f06b2d8 8018 }
823d2571 8019
6b0dd094
AV		 8020 if ((insn->isa == T32 && !thumb)
8021 || (insn->isa == ARM && thumb))
8022 continue;
8023
0313a2b8
NC		 8024 if ((given & mask) != value)
8025 continue;
8f06b2d8 8026
823d2571 8027 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 8028 continue;
8029
8afc7bea
RL		 8030 if (insn->value == 0xfe000010 /* mcr2 */
8031 || insn->value == 0xfe100010 /* mrc2 */
8032 || insn->value == 0xfc100000 /* ldc2 */
8033 || insn->value == 0xfc000000) /* stc2 */
8034 {
b0c11777 8035 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 8036 is_unpredictable = TRUE;
f08d8ce3
AV		 8037
8038 /* Armv8.1-M Mainline FP & MVE instructions. */
8039 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8040 && !ARM_CPU_IS_ANY (allowed_arches)
8041 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8042 continue;
8043
8afc7bea
RL		 8044 }
8045 else if (insn->value == 0x0e000000 /* cdp */
8046 || insn->value == 0xfe000000 /* cdp2 */
8047 || insn->value == 0x0e000010 /* mcr */
8048 || insn->value == 0x0e100010 /* mrc */
8049 || insn->value == 0x0c100000 /* ldc */
8050 || insn->value == 0x0c000000) /* stc */
8051 {
8052 /* Floating-point instructions. */
b0c11777 8053 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 8054 continue;
32c36c3c
AV		 8055
8056 /* Armv8.1-M Mainline FP & MVE instructions. */
8057 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8058 && !ARM_CPU_IS_ANY (allowed_arches)
8059 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8060 continue;
8afc7bea 8061 }
aef6d006
AV		 8062 else if ((insn->value == 0xec100f80 /* vldr (system register) */
8063 || insn->value == 0xec000f80) /* vstr (system register) */
8064 && arm_decode_field (given, 24, 24) == 0
8065 && arm_decode_field (given, 21, 21) == 0)
8066 /* If the P and W bits are both 0 then these encodings match the MVE
8067 VLDR and VSTR instructions, these are in a different table, so we
8068 don't let it match here. */
8069 continue;
8070
0313a2b8
NC		 8071 for (c = insn->assembler; *c; c++)
8072 {
8073 if (*c == '%')
8f06b2d8 8074 {
32c36c3c
AV		 8075 const char mod = *++c;
8076 switch (mod)
8f06b2d8 8077 {
0313a2b8
NC		 8078 case '%':
8079 func (stream, "%%");
8080 break;
8081
8082 case 'A':
32c36c3c 8083 case 'K':
05413229 8084 {
79862e45 8085 int rn = (given >> 16) & 0xf;
b0c11777 8086 bfd_vma offset = given & 0xff;
0313a2b8 8087
32c36c3c
AV		 8088 if (mod == 'K')
8089 offset = given & 0x7f;
8090
05413229 8091 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 8092
79862e45
DJ		 8093 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
8094 {
8095 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 8096 if (cp_num == 9)
8097 /* vldr.16/vstr.16 will shift the address
8098 left by 1 bit only. */
8099 offset = offset * 2;
8100 else
8101 offset = offset * 4;
8102
79862e45
DJ		 8103 if (NEGATIVE_BIT_SET)
8104 offset = - offset;
8105 if (rn != 15)
8106 value_in_comment = offset;
8107 }
8108
c1e26897 8109 if (PRE_BIT_SET)
05413229
NC		 8110 {
8111 if (offset)
fe56b6ce 8112 func (stream, ", #%d]%s",
d908c8af 8113 (int) offset,
c1e26897 8114 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 8115 else if (NEGATIVE_BIT_SET)
8116 func (stream, ", #-0]");
05413229
NC		 8117 else
8118 func (stream, "]");
8119 }
8120 else
8121 {
0313a2b8 8122 func (stream, "]");
8f06b2d8 8123
c1e26897 8124 if (WRITEBACK_BIT_SET)
05413229
NC		 8125 {
8126 if (offset)
d908c8af 8127 func (stream, ", #%d", (int) offset);
26d97720
NS		 8128 else if (NEGATIVE_BIT_SET)
8129 func (stream, ", #-0");
05413229
NC		 8130 }
8131 else
fe56b6ce 8132 {
26d97720
NS		 8133 func (stream, ", {%s%d}",
8134 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 8135 (int) offset);
fe56b6ce
NC		 8136 value_in_comment = offset;
8137 }
05413229 8138 }
79862e45
DJ		 8139 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
8140 {
8141 func (stream, "\t; ");
6844b2c2
MGD		 8142 /* For unaligned PCs, apply off-by-alignment
8143 correction. */
43e65147 8144 info->print_address_func (offset + pc
6844b2c2
MGD		 8145 + info->bytes_per_chunk * 2
8146 - (pc & 3),
dffaa15c 8147 info);
79862e45 8148 }
05413229 8149 }
0313a2b8 8150 break;
8f06b2d8 8151
0313a2b8
NC		 8152 case 'B':
8153 {
8154 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
8155 int offset = (given >> 1) & 0x3f;
8156
8157 if (offset == 1)
8158 func (stream, "{d%d}", regno);
8159 else if (regno + offset > 32)
8160 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
8161 else
8162 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
8163 }
8164 break;
8f06b2d8 8165
efd6b359
AV		 8166 case 'C':
8167 {
8168 bfd_boolean single = ((given >> 8) & 1) == 0;
8169 char reg_prefix = single ? 's' : 'd';
8170 int Dreg = (given >> 22) & 0x1;
8171 int Vdreg = (given >> 12) & 0xf;
8172 int reg = single ? ((Vdreg << 1) | Dreg)
8173 : ((Dreg << 4) | Vdreg);
8174 int num = (given >> (single ? 0 : 1)) & 0x7f;
8175 int maxreg = single ? 31 : 15;
8176 int topreg = reg + num - 1;
8177
8178 if (!num)
8179 func (stream, "{VPR}");
8180 else if (num == 1)
8181 func (stream, "{%c%d, VPR}", reg_prefix, reg);
8182 else if (topreg > maxreg)
8183 func (stream, "{%c%d-<overflow reg d%d, VPR}",
8184 reg_prefix, reg, single ? topreg >> 1 : topreg);
8185 else
8186 func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
8187 reg_prefix, topreg);
8188 }
8189 break;
8190
e2efe87d
MGD		 8191 case 'u':
8192 if (cond != COND_UNCOND)
8193 is_unpredictable = TRUE;
8194
8195 /* Fall through. */
0313a2b8 8196 case 'c':
b0c11777
RL		 8197 if (cond != COND_UNCOND && cp_num == 9)
8198 is_unpredictable = TRUE;
8199
aab2c27d
MM		 8200 /* Fall through. */
8201 case 'b':
0313a2b8
NC		 8202 func (stream, "%s", arm_conditional[cond]);
8203 break;
8f06b2d8 8204
0313a2b8
NC		 8205 case 'I':
8206 /* Print a Cirrus/DSP shift immediate. */
8207 /* Immediates are 7bit signed ints with bits 0..3 in
8208 bits 0..3 of opcode and bits 4..6 in bits 5..7
8209 of opcode. */
8210 {
8211 int imm;
8f06b2d8 8212
0313a2b8 8213 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 8214
0313a2b8
NC		 8215 /* Is ``imm'' a negative number? */
8216 if (imm & 0x40)
24b4cf66 8217 imm -= 0x80;
8f06b2d8 8218
0313a2b8
NC		 8219 func (stream, "%d", imm);
8220 }
8221
8222 break;
8f06b2d8 8223
32c36c3c
AV		 8224 case 'J':
8225 {
73cd51e5
AV		 8226 unsigned long regno
8227 = arm_decode_field_multiple (given, 13, 15, 22, 22);
32c36c3c
AV		 8228
8229 switch (regno)
8230 {
8231 case 0x1:
8232 func (stream, "FPSCR");
8233 break;
8234 case 0x2:
8235 func (stream, "FPSCR_nzcvqc");
8236 break;
8237 case 0xc:
8238 func (stream, "VPR");
8239 break;
8240 case 0xd:
8241 func (stream, "P0");
8242 break;
8243 case 0xe:
8244 func (stream, "FPCXTNS");
8245 break;
8246 case 0xf:
8247 func (stream, "FPCXTS");
8248 break;
8249 default:
73cd51e5 8250 func (stream, "<invalid reg %lu>", regno);
32c36c3c
AV		 8251 break;
8252 }
8253 }
8254 break;
8255
0313a2b8
NC		 8256 case 'F':
8257 switch (given & 0x00408000)
8258 {
8259 case 0:
8260 func (stream, "4");
8261 break;
8262 case 0x8000:
8263 func (stream, "1");
8264 break;
8265 case 0x00400000:
8266 func (stream, "2");
8f06b2d8 8267 break;
0313a2b8
NC		 8268 default:
8269 func (stream, "3");
8270 }
8271 break;
8f06b2d8 8272
0313a2b8
NC		 8273 case 'P':
8274 switch (given & 0x00080080)
8275 {
8276 case 0:
8277 func (stream, "s");
8278 break;
8279 case 0x80:
8280 func (stream, "d");
8281 break;
8282 case 0x00080000:
8283 func (stream, "e");
8284 break;
8285 default:
8286 func (stream, _("<illegal precision>"));
8f06b2d8 8287 break;
0313a2b8
NC		 8288 }
8289 break;
8f06b2d8 8290
0313a2b8
NC		 8291 case 'Q':
8292 switch (given & 0x00408000)
8293 {
8294 case 0:
8295 func (stream, "s");
8f06b2d8 8296 break;
0313a2b8
NC		 8297 case 0x8000:
8298 func (stream, "d");
8f06b2d8 8299 break;
0313a2b8
NC		 8300 case 0x00400000:
8301 func (stream, "e");
8302 break;
8303 default:
8304 func (stream, "p");
8f06b2d8 8305 break;
0313a2b8
NC		 8306 }
8307 break;
8f06b2d8 8308
0313a2b8
NC		 8309 case 'R':
8310 switch (given & 0x60)
8311 {
8312 case 0:
8313 break;
8314 case 0x20:
8315 func (stream, "p");
8316 break;
8317 case 0x40:
8318 func (stream, "m");
8319 break;
8320 default:
8321 func (stream, "z");
8322 break;
8323 }
8324 break;
16980d0b 8325
0313a2b8
NC		 8326 case '0': case '1': case '2': case '3': case '4':
8327 case '5': case '6': case '7': case '8': case '9':
8328 {
8329 int width;
8f06b2d8 8330
0313a2b8 8331 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 8332
0313a2b8
NC		 8333 switch (*c)
8334 {
ff4a8d2b
NC		 8335 case 'R':
8336 if (value == 15)
8337 is_unpredictable = TRUE;
8338 /* Fall through. */
0313a2b8 8339 case 'r':
ff4a8d2b
NC		 8340 if (c[1] == 'u')
8341 {
8342 /* Eat the 'u' character. */
8343 ++ c;
8344
8345 if (u_reg == value)
8346 is_unpredictable = TRUE;
8347 u_reg = value;
8348 }
0313a2b8
NC		 8349 func (stream, "%s", arm_regnames[value]);
8350 break;
c28eeff2
SN		 8351 case 'V':
8352 if (given & (1 << 6))
8353 goto Q;
8354 /* FALLTHROUGH */
0313a2b8
NC		 8355 case 'D':
8356 func (stream, "d%ld", value);
8357 break;
8358 case 'Q':
c28eeff2 8359 Q:
0313a2b8
NC		 8360 if (value & 1)
8361 func (stream, "<illegal reg q%ld.5>", value >> 1);
8362 else
8363 func (stream, "q%ld", value >> 1);
8364 break;
8365 case 'd':
8366 func (stream, "%ld", value);
05413229 8367 value_in_comment = value;
0313a2b8 8368 break;
6f1c2142
AM		 8369 case 'E':
8370 {
8371 /* Converts immediate 8 bit back to float value. */
8372 unsigned floatVal = (value & 0x80) << 24
8373 | (value & 0x3F) << 19
8374 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
8375
8376 /* Quarter float have a maximum value of 31.0.
8377 Get floating point value multiplied by 1e7.
8378 The maximum value stays in limit of a 32-bit int. */
8379 unsigned decVal =
8380 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
8381 (16 + (value & 0xF));
8382
8383 if (!(decVal % 1000000))
8384 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
8385 floatVal, value & 0x80 ? '-' : ' ',
8386 decVal / 10000000,
8387 decVal % 10000000 / 1000000);
8388 else if (!(decVal % 10000))
8389 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
8390 floatVal, value & 0x80 ? '-' : ' ',
8391 decVal / 10000000,
8392 decVal % 10000000 / 10000);
8393 else
8394 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
8395 floatVal, value & 0x80 ? '-' : ' ',
8396 decVal / 10000000, decVal % 10000000);
8397 break;
8398 }
0313a2b8
NC		 8399 case 'k':
8400 {
8401 int from = (given & (1 << 7)) ? 32 : 16;
8402 func (stream, "%ld", from - value);
8403 }
8404 break;
8f06b2d8 8405
0313a2b8
NC		 8406 case 'f':
8407 if (value > 7)
8408 func (stream, "#%s", arm_fp_const[value & 7]);
8409 else
8410 func (stream, "f%ld", value);
8411 break;
4146fd53 8412
0313a2b8
NC		 8413 case 'w':
8414 if (width == 2)
8415 func (stream, "%s", iwmmxt_wwnames[value]);
8416 else
8417 func (stream, "%s", iwmmxt_wwssnames[value]);
8418 break;
4146fd53 8419
0313a2b8
NC		 8420 case 'g':
8421 func (stream, "%s", iwmmxt_regnames[value]);
8422 break;
8423 case 'G':
8424 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 8425 break;
8f06b2d8 8426
0313a2b8 8427 case 'x':
d1aaab3c 8428 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 8429 break;
8f06b2d8 8430
33399f07
MGD		 8431 case 'c':
8432 switch (value)
8433 {
8434 case 0:
8435 func (stream, "eq");
8436 break;
8437
8438 case 1:
8439 func (stream, "vs");
8440 break;
8441
8442 case 2:
8443 func (stream, "ge");
8444 break;
8445
8446 case 3:
8447 func (stream, "gt");
8448 break;
8449
8450 default:
8451 func (stream, "??");
8452 break;
8453 }
8454 break;
8455
0313a2b8
NC		 8456 case '`':
8457 c++;
8458 if (value == 0)
8459 func (stream, "%c", *c);
8460 break;
8461 case '\'':
8462 c++;
8463 if (value == ((1ul << width) - 1))
8464 func (stream, "%c", *c);
8465 break;
8466 case '?':
fe56b6ce 8467 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 8468 c += 1 << width;
8469 break;
8470 default:
8471 abort ();
8472 }
dffaa15c
AM		 8473 }
8474 break;
0313a2b8 8475
dffaa15c
AM		 8476 case 'y':
8477 case 'z':
8478 {
8479 int single = *c++ == 'y';
8480 int regno;
8f06b2d8 8481
dffaa15c
AM		 8482 switch (*c)
8483 {
8484 case '4': /* Sm pair */
8485 case '0': /* Sm, Dm */
8486 regno = given & 0x0000000f;
8487 if (single)
8488 {
8489 regno <<= 1;
8490 regno += (given >> 5) & 1;
8491 }
8492 else
8493 regno += ((given >> 5) & 1) << 4;
8494 break;
8f06b2d8 8495
dffaa15c
AM		 8496 case '1': /* Sd, Dd */
8497 regno = (given >> 12) & 0x0000000f;
8498 if (single)
8499 {
8500 regno <<= 1;
8501 regno += (given >> 22) & 1;
8502 }
8503 else
8504 regno += ((given >> 22) & 1) << 4;
8505 break;
7df76b80 8506
dffaa15c
AM		 8507 case '2': /* Sn, Dn */
8508 regno = (given >> 16) & 0x0000000f;
8509 if (single)
8510 {
8511 regno <<= 1;
8512 regno += (given >> 7) & 1;
8513 }
8514 else
8515 regno += ((given >> 7) & 1) << 4;
8516 break;
a7f8487e 8517
dffaa15c
AM		 8518 case '3': /* List */
8519 func (stream, "{");
8520 regno = (given >> 12) & 0x0000000f;
8521 if (single)
8522 {
8523 regno <<= 1;
8524 regno += (given >> 22) & 1;
8525 }
8526 else
8527 regno += ((given >> 22) & 1) << 4;
8528 break;
a7f8487e 8529
dffaa15c
AM		 8530 default:
8531 abort ();
8532 }
0313a2b8 8533
dffaa15c 8534 func (stream, "%c%d", single ? 's' : 'd', regno);
a7f8487e 8535
dffaa15c
AM		 8536 if (*c == '3')
8537 {
8538 int count = given & 0xff;
b34976b6 8539
dffaa15c
AM		 8540 if (single == 0)
8541 count >>= 1;
0313a2b8 8542
dffaa15c
AM		 8543 if (--count)
8544 {
8545 func (stream, "-%c%d",
8546 single ? 's' : 'd',
8547 regno + count);
8548 }
0313a2b8 8549
dffaa15c 8550 func (stream, "}");
0313a2b8 8551 }
dffaa15c
AM		 8552 else if (*c == '4')
8553 func (stream, ", %c%d", single ? 's' : 'd',
8554 regno + 1);
8555 }
8556 break;
b34976b6 8557
dffaa15c
AM		 8558 case 'L':
8559 switch (given & 0x00400100)
0313a2b8 8560 {
dffaa15c
AM		 8561 case 0x00000000: func (stream, "b"); break;
8562 case 0x00400000: func (stream, "h"); break;
8563 case 0x00000100: func (stream, "w"); break;
8564 case 0x00400100: func (stream, "d"); break;
8565 default:
8566 break;
0313a2b8 8567 }
dffaa15c 8568 break;
2d447fca 8569
dffaa15c
AM		 8570 case 'Z':
8571 {
8572 /* given (20, 23) | given (0, 3) */
8573 value = ((given >> 16) & 0xf0) | (given & 0xf);
8574 func (stream, "%d", (int) value);
8575 }
8576 break;
0313a2b8 8577
dffaa15c
AM		 8578 case 'l':
8579 /* This is like the 'A' operator, except that if
8580 the width field "M" is zero, then the offset is
8581 *not* multiplied by four. */
8582 {
8583 int offset = given & 0xff;
8584 int multiplier = (given & 0x00000100) ? 4 : 1;
0313a2b8 8585
dffaa15c 8586 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
05413229 8587
dffaa15c
AM		 8588 if (multiplier > 1)
8589 {
8590 value_in_comment = offset * multiplier;
8591 if (NEGATIVE_BIT_SET)
8592 value_in_comment = - value_in_comment;
8593 }
0313a2b8 8594
dffaa15c
AM		 8595 if (offset)
8596 {
8597 if (PRE_BIT_SET)
8598 func (stream, ", #%s%d]%s",
8599 NEGATIVE_BIT_SET ? "-" : "",
8600 offset * multiplier,
8601 WRITEBACK_BIT_SET ? "!" : "");
8602 else
8603 func (stream, "], #%s%d",
8604 NEGATIVE_BIT_SET ? "-" : "",
8605 offset * multiplier);
8606 }
8607 else
8608 func (stream, "]");
8609 }
8610 break;
2d447fca 8611
dffaa15c
AM		 8612 case 'r':
8613 {
8614 int imm4 = (given >> 4) & 0xf;
8615 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
8616 int ubit = ! NEGATIVE_BIT_SET;
8617 const char *rm = arm_regnames [given & 0xf];
8618 const char *rn = arm_regnames [(given >> 16) & 0xf];
0313a2b8 8619
dffaa15c
AM		 8620 switch (puw_bits)
8621 {
8622 case 1:
8623 case 3:
8624 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
8625 if (imm4)
8626 func (stream, ", lsl #%d", imm4);
8627 break;
0313a2b8 8628
dffaa15c
AM		 8629 case 4:
8630 case 5:
8631 case 6:
8632 case 7:
8633 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
8634 if (imm4 > 0)
8635 func (stream, ", lsl #%d", imm4);
8636 func (stream, "]");
8637 if (puw_bits == 5 || puw_bits == 7)
8638 func (stream, "!");
8639 break;
2d447fca 8640
dffaa15c
AM		 8641 default:
8642 func (stream, "INVALID");
8643 }
8644 }
8645 break;
0313a2b8 8646
dffaa15c
AM		 8647 case 'i':
8648 {
8649 long imm5;
8650 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
8651 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
0313a2b8 8652 }
dffaa15c
AM		 8653 break;
8654
8655 default:
8656 abort ();
252b5132 8657 }
252b5132 8658 }
0313a2b8
NC		 8659 else
8660 func (stream, "%c", *c);
252b5132 8661 }
05413229
NC		 8662
8663 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 8664 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 8665
ff4a8d2b
NC		 8666 if (is_unpredictable)
8667 func (stream, UNPREDICTABLE_INSTRUCTION);
8668
0313a2b8 8669 return TRUE;
252b5132 8670 }
8f06b2d8 8671 return FALSE;
252b5132
RH		 8672}
8673
33593eaf
MM		 8674static bfd_boolean
8675print_insn_coprocessor (bfd_vma pc,
8676 struct disassemble_info *info,
8677 long given,
8678 bfd_boolean thumb)
8679{
8680 return print_insn_coprocessor_1 (coprocessor_opcodes,
8681 pc, info, given, thumb);
8682}
8683
8684static bfd_boolean
8685print_insn_generic_coprocessor (bfd_vma pc,
8686 struct disassemble_info *info,
8687 long given,
8688 bfd_boolean thumb)
8689{
8690 return print_insn_coprocessor_1 (generic_coprocessor_opcodes,
8691 pc, info, given, thumb);
8692}
8693
05413229
NC		 8694/* Decodes and prints ARM addressing modes. Returns the offset
8695 used in the address, if any, if it is worthwhile printing the
8696 offset as a hexadecimal value in a comment at the end of the
8697 line of disassembly. */
8698
8699static signed long
62b3e311
PB		 8700print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
8701{
8702 void *stream = info->stream;
8703 fprintf_ftype func = info->fprintf_func;
f8b960bc 8704 bfd_vma offset = 0;
62b3e311
PB		 8705
8706 if (((given & 0x000f0000) == 0x000f0000)
8707 && ((given & 0x02000000) == 0))
8708 {
05413229 8709 offset = given & 0xfff;
62b3e311
PB		 8710
8711 func (stream, "[pc");
8712
c1e26897 8713 if (PRE_BIT_SET)
62b3e311 8714 {
26d97720
NS		 8715 /* Pre-indexed. Elide offset of positive zero when
8716 non-writeback. */
8717 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 8718 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 8719
8720 if (NEGATIVE_BIT_SET)
8721 offset = -offset;
62b3e311
PB		 8722
8723 offset += pc + 8;
8724
8725 /* Cope with the possibility of write-back
8726 being used. Probably a very dangerous thing
8727 for the programmer to do, but who are we to
8728 argue ? */
26d97720 8729 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 8730 }
c1e26897 8731 else /* Post indexed. */
62b3e311 8732 {
d908c8af 8733 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 8734
c1e26897 8735 /* Ie ignore the offset. */
62b3e311
PB		 8736 offset = pc + 8;
8737 }
8738
8739 func (stream, "\t; ");
8740 info->print_address_func (offset, info);
05413229 8741 offset = 0;
62b3e311
PB		 8742 }
8743 else
8744 {
8745 func (stream, "[%s",
8746 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 8747
8748 if (PRE_BIT_SET)
62b3e311
PB		 8749 {
8750 if ((given & 0x02000000) == 0)
8751 {
26d97720 8752 /* Elide offset of positive zero when non-writeback. */
05413229 8753 offset = given & 0xfff;
26d97720 8754 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 8755 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 8756 }
8757 else
8758 {
26d97720 8759 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 8760 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 8761 }
8762
8763 func (stream, "]%s",
c1e26897 8764 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 8765 }
8766 else
8767 {
8768 if ((given & 0x02000000) == 0)
8769 {
26d97720 8770 /* Always show offset. */
05413229 8771 offset = given & 0xfff;
26d97720 8772 func (stream, "], #%s%d",
d908c8af 8773 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 8774 }
8775 else
8776 {
8777 func (stream, "], %s",
c1e26897 8778 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 8779 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 8780 }
8781 }
84919466
MR		 8782 if (NEGATIVE_BIT_SET)
8783 offset = -offset;
62b3e311 8784 }
05413229
NC		 8785
8786 return (signed long) offset;
62b3e311
PB		 8787}
8788
16980d0b
JB		 8789/* Print one neon instruction on INFO->STREAM.
8790 Return TRUE if the instuction matched, FALSE if this is not a
8791 recognised neon instruction. */
8792
8793static bfd_boolean
8794print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
8795{
8796 const struct opcode32 *insn;
8797 void *stream = info->stream;
8798 fprintf_ftype func = info->fprintf_func;
8799
8800 if (thumb)
8801 {
8802 if ((given & 0xef000000) == 0xef000000)
8803 {
0313a2b8 8804 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 8805 unsigned long bit28 = given & (1 << 28);
8806
8807 given &= 0x00ffffff;
8808 if (bit28)
8809 given |= 0xf3000000;
8810 else
8811 given |= 0xf2000000;
8812 }
8813 else if ((given & 0xff000000) == 0xf9000000)
8814 given ^= 0xf9000000 ^ 0xf4000000;
aab2c27d
MM		 8815 /* BFloat16 neon instructions without special top byte handling. */
8816 else if ((given & 0xff000000) == 0xfe000000
8817 || (given & 0xff000000) == 0xfc000000)
8818 ;
9743db03
AV		 8819 /* vdup is also a valid neon instruction. */
8820 else if ((given & 0xff910f5f) != 0xee800b10)
16980d0b
JB		 8821 return FALSE;
8822 }
43e65147 8823
16980d0b
JB		 8824 for (insn = neon_opcodes; insn->assembler; insn++)
8825 {
8826 if ((given & insn->mask) == insn->value)
8827 {
05413229 8828 signed long value_in_comment = 0;
e2efe87d 8829 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 8830 const char *c;
8831
8832 for (c = insn->assembler; *c; c++)
8833 {
8834 if (*c == '%')
8835 {
8836 switch (*++c)
8837 {
8838 case '%':
8839 func (stream, "%%");
8840 break;
8841
e2efe87d
MGD		 8842 case 'u':
8843 if (thumb && ifthen_state)
8844 is_unpredictable = TRUE;
8845
8846 /* Fall through. */
c22aaad1
PB		 8847 case 'c':
8848 if (thumb && ifthen_state)
8849 func (stream, "%s", arm_conditional[IFTHEN_COND]);
8850 break;
8851
16980d0b
JB		 8852 case 'A':
8853 {
43e65147 8854 static const unsigned char enc[16] =
16980d0b
JB		 8855 {
8856 0x4, 0x14, /* st4 0,1 */
8857 0x4, /* st1 2 */
8858 0x4, /* st2 3 */
8859 0x3, /* st3 4 */
8860 0x13, /* st3 5 */
8861 0x3, /* st1 6 */
8862 0x1, /* st1 7 */
8863 0x2, /* st2 8 */
8864 0x12, /* st2 9 */
8865 0x2, /* st1 10 */
8866 0, 0, 0, 0, 0
8867 };
8868 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8869 int rn = ((given >> 16) & 0xf);
8870 int rm = ((given >> 0) & 0xf);
8871 int align = ((given >> 4) & 0x3);
8872 int type = ((given >> 8) & 0xf);
8873 int n = enc[type] & 0xf;
8874 int stride = (enc[type] >> 4) + 1;
8875 int ix;
43e65147 8876
16980d0b
JB		 8877 func (stream, "{");
8878 if (stride > 1)
8879 for (ix = 0; ix != n; ix++)
8880 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
8881 else if (n == 1)
8882 func (stream, "d%d", rd);
8883 else
8884 func (stream, "d%d-d%d", rd, rd + n - 1);
8885 func (stream, "}, [%s", arm_regnames[rn]);
8886 if (align)
8e560766 8887 func (stream, " :%d", 32 << align);
16980d0b
JB		 8888 func (stream, "]");
8889 if (rm == 0xd)
8890 func (stream, "!");
8891 else if (rm != 0xf)
8892 func (stream, ", %s", arm_regnames[rm]);
8893 }
8894 break;
43e65147 8895
16980d0b
JB		 8896 case 'B':
8897 {
8898 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8899 int rn = ((given >> 16) & 0xf);
8900 int rm = ((given >> 0) & 0xf);
8901 int idx_align = ((given >> 4) & 0xf);
8902 int align = 0;
8903 int size = ((given >> 10) & 0x3);
8904 int idx = idx_align >> (size + 1);
8905 int length = ((given >> 8) & 3) + 1;
8906 int stride = 1;
8907 int i;
8908
8909 if (length > 1 && size > 0)
8910 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 8911
16980d0b
JB		 8912 switch (length)
8913 {
8914 case 1:
8915 {
8916 int amask = (1 << size) - 1;
8917 if ((idx_align & (1 << size)) != 0)
8918 return FALSE;
8919 if (size > 0)
8920 {
8921 if ((idx_align & amask) == amask)
8922 align = 8 << size;
8923 else if ((idx_align & amask) != 0)
8924 return FALSE;
8925 }
8926 }
8927 break;
43e65147 8928
16980d0b
JB		 8929 case 2:
8930 if (size == 2 && (idx_align & 2) != 0)
8931 return FALSE;
8932 align = (idx_align & 1) ? 16 << size : 0;
8933 break;
43e65147 8934
16980d0b
JB		 8935 case 3:
8936 if ((size == 2 && (idx_align & 3) != 0)
8937 || (idx_align & 1) != 0)
8938 return FALSE;
8939 break;
43e65147 8940
16980d0b
JB		 8941 case 4:
8942 if (size == 2)
8943 {
8944 if ((idx_align & 3) == 3)
8945 return FALSE;
8946 align = (idx_align & 3) * 64;
8947 }
8948 else
8949 align = (idx_align & 1) ? 32 << size : 0;
8950 break;
43e65147 8951
16980d0b
JB		 8952 default:
8953 abort ();
8954 }
43e65147 8955
16980d0b
JB		 8956 func (stream, "{");
8957 for (i = 0; i < length; i++)
8958 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
8959 rd + i * stride, idx);
8960 func (stream, "}, [%s", arm_regnames[rn]);
8961 if (align)
8e560766 8962 func (stream, " :%d", align);
16980d0b
JB		 8963 func (stream, "]");
8964 if (rm == 0xd)
8965 func (stream, "!");
8966 else if (rm != 0xf)
8967 func (stream, ", %s", arm_regnames[rm]);
8968 }
8969 break;
43e65147 8970
16980d0b
JB		 8971 case 'C':
8972 {
8973 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8974 int rn = ((given >> 16) & 0xf);
8975 int rm = ((given >> 0) & 0xf);
8976 int align = ((given >> 4) & 0x1);
8977 int size = ((given >> 6) & 0x3);
8978 int type = ((given >> 8) & 0x3);
8979 int n = type + 1;
8980 int stride = ((given >> 5) & 0x1);
8981 int ix;
43e65147 8982
16980d0b
JB		 8983 if (stride && (n == 1))
8984 n++;
8985 else
8986 stride++;
43e65147 8987
16980d0b
JB		 8988 func (stream, "{");
8989 if (stride > 1)
8990 for (ix = 0; ix != n; ix++)
8991 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
8992 else if (n == 1)
8993 func (stream, "d%d[]", rd);
8994 else
8995 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
8996 func (stream, "}, [%s", arm_regnames[rn]);
8997 if (align)
8998 {
91d6fa6a 8999 align = (8 * (type + 1)) << size;
16980d0b
JB		 9000 if (type == 3)
9001 align = (size > 1) ? align >> 1 : align;
9002 if (type == 2 || (type == 0 && !size))
8e560766 9003 func (stream, " :<bad align %d>", align);
16980d0b 9004 else
8e560766 9005 func (stream, " :%d", align);
16980d0b
JB		 9006 }
9007 func (stream, "]");
9008 if (rm == 0xd)
9009 func (stream, "!");
9010 else if (rm != 0xf)
9011 func (stream, ", %s", arm_regnames[rm]);
9012 }
9013 break;
43e65147 9014
16980d0b
JB		 9015 case 'D':
9016 {
9017 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
9018 int size = (given >> 20) & 3;
9019 int reg = raw_reg & ((4 << size) - 1);
9020 int ix = raw_reg >> size >> 2;
43e65147 9021
16980d0b
JB		 9022 func (stream, "d%d[%d]", reg, ix);
9023 }
9024 break;
43e65147 9025
16980d0b 9026 case 'E':
fe56b6ce 9027 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 9028 {
9029 int bits = 0;
9030 int cmode = (given >> 8) & 0xf;
9031 int op = (given >> 5) & 0x1;
9032 unsigned long value = 0, hival = 0;
9033 unsigned shift;
9034 int size = 0;
0dbde4cf 9035 int isfloat = 0;
43e65147 9036
16980d0b
JB		 9037 bits |= ((given >> 24) & 1) << 7;
9038 bits |= ((given >> 16) & 7) << 4;
9039 bits |= ((given >> 0) & 15) << 0;
43e65147 9040
16980d0b
JB		 9041 if (cmode < 8)
9042 {
9043 shift = (cmode >> 1) & 3;
fe56b6ce 9044 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 9045 size = 32;
9046 }
9047 else if (cmode < 12)
9048 {
9049 shift = (cmode >> 1) & 1;
fe56b6ce 9050 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 9051 size = 16;
9052 }
9053 else if (cmode < 14)
9054 {
9055 shift = (cmode & 1) + 1;
fe56b6ce 9056 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 9057 value |= (1ul << (8 * shift)) - 1;
9058 size = 32;
9059 }
9060 else if (cmode == 14)
9061 {
9062 if (op)
9063 {
fe56b6ce 9064 /* Bit replication into bytes. */
16980d0b
JB		 9065 int ix;
9066 unsigned long mask;
43e65147 9067
16980d0b
JB		 9068 value = 0;
9069 hival = 0;
9070 for (ix = 7; ix >= 0; ix--)
9071 {
9072 mask = ((bits >> ix) & 1) ? 0xff : 0;
9073 if (ix <= 3)
9074 value = (value << 8) | mask;
9075 else
9076 hival = (hival << 8) | mask;
9077 }
9078 size = 64;
9079 }
9080 else
9081 {
fe56b6ce
NC		 9082 /* Byte replication. */
9083 value = (unsigned long) bits;
16980d0b
JB		 9084 size = 8;
9085 }
9086 }
9087 else if (!op)
9088 {
fe56b6ce 9089 /* Floating point encoding. */
16980d0b 9090 int tmp;
43e65147 9091
fe56b6ce
NC		 9092 value = (unsigned long) (bits & 0x7f) << 19;
9093 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 9094 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 9095 value |= (unsigned long) tmp << 24;
16980d0b 9096 size = 32;
0dbde4cf 9097 isfloat = 1;
16980d0b
JB		 9098 }
9099 else
9100 {
9101 func (stream, "<illegal constant %.8x:%x:%x>",
9102 bits, cmode, op);
9103 size = 32;
9104 break;
9105 }
9106 switch (size)
9107 {
9108 case 8:
9109 func (stream, "#%ld\t; 0x%.2lx", value, value);
9110 break;
43e65147 9111
16980d0b
JB		 9112 case 16:
9113 func (stream, "#%ld\t; 0x%.4lx", value, value);
9114 break;
9115
9116 case 32:
0dbde4cf
JB		 9117 if (isfloat)
9118 {
9119 unsigned char valbytes[4];
9120 double fvalue;
43e65147 9121
0dbde4cf
JB		 9122 /* Do this a byte at a time so we don't have to
9123 worry about the host's endianness. */
9124 valbytes[0] = value & 0xff;
9125 valbytes[1] = (value >> 8) & 0xff;
9126 valbytes[2] = (value >> 16) & 0xff;
9127 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 9128
9129 floatformat_to_double
c1e26897
NC		 9130 (& floatformat_ieee_single_little, valbytes,
9131 & fvalue);
43e65147 9132
0dbde4cf
JB		 9133 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
9134 value);
9135 }
9136 else
4e9d3b81 9137 func (stream, "#%ld\t; 0x%.8lx",
43e65147 9138 (long) (((value & 0x80000000L) != 0)
9d82ec38 9139 ? value | ~0xffffffffL : value),
c1e26897 9140 value);
16980d0b
JB		 9141 break;
9142
9143 case 64:
9144 func (stream, "#0x%.8lx%.8lx", hival, value);
9145 break;
43e65147 9146
16980d0b
JB		 9147 default:
9148 abort ();
9149 }
9150 }
9151 break;
43e65147 9152
16980d0b
JB		 9153 case 'F':
9154 {
9155 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
9156 int num = (given >> 8) & 0x3;
43e65147 9157
16980d0b
JB		 9158 if (!num)
9159 func (stream, "{d%d}", regno);
9160 else if (num + regno >= 32)
9161 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
9162 else
9163 func (stream, "{d%d-d%d}", regno, regno + num);
9164 }
9165 break;
7e8e6784 9166
16980d0b
JB		 9167
9168 case '0': case '1': case '2': case '3': case '4':
9169 case '5': case '6': case '7': case '8': case '9':
9170 {
9171 int width;
9172 unsigned long value;
9173
9174 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 9175
16980d0b
JB		 9176 switch (*c)
9177 {
9178 case 'r':
9179 func (stream, "%s", arm_regnames[value]);
9180 break;
9181 case 'd':
9182 func (stream, "%ld", value);
05413229 9183 value_in_comment = value;
16980d0b
JB		 9184 break;
9185 case 'e':
9186 func (stream, "%ld", (1ul << width) - value);
9187 break;
43e65147 9188
16980d0b
JB		 9189 case 'S':
9190 case 'T':
9191 case 'U':
05413229 9192 /* Various width encodings. */
16980d0b
JB		 9193 {
9194 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
9195 int limit;
9196 unsigned low, high;
9197
9198 c++;
9199 if (*c >= '0' && *c <= '9')
9200 limit = *c - '0';
9201 else if (*c >= 'a' && *c <= 'f')
9202 limit = *c - 'a' + 10;
9203 else
9204 abort ();
9205 low = limit >> 2;
9206 high = limit & 3;
9207
9208 if (value < low || value > high)
9209 func (stream, "<illegal width %d>", base << value);
9210 else
9211 func (stream, "%d", base << value);
9212 }
9213 break;
9214 case 'R':
9215 if (given & (1 << 6))
9216 goto Q;
9217 /* FALLTHROUGH */
9218 case 'D':
9219 func (stream, "d%ld", value);
9220 break;
9221 case 'Q':
9222 Q:
9223 if (value & 1)
9224 func (stream, "<illegal reg q%ld.5>", value >> 1);
9225 else
9226 func (stream, "q%ld", value >> 1);
9227 break;
43e65147 9228
16980d0b
JB		 9229 case '`':
9230 c++;
9231 if (value == 0)
9232 func (stream, "%c", *c);
9233 break;
9234 case '\'':
9235 c++;
9236 if (value == ((1ul << width) - 1))
9237 func (stream, "%c", *c);
9238 break;
9239 case '?':
fe56b6ce 9240 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 9241 c += 1 << width;
9242 break;
9243 default:
9244 abort ();
9245 }
16980d0b 9246 }
dffaa15c
AM		 9247 break;
9248
9249 default:
9250 abort ();
16980d0b
JB		 9251 }
9252 }
9253 else
9254 func (stream, "%c", *c);
9255 }
05413229
NC		 9256
9257 if (value_in_comment > 32 || value_in_comment < -16)
9258 func (stream, "\t; 0x%lx", value_in_comment);
9259
e2efe87d
MGD		 9260 if (is_unpredictable)
9261 func (stream, UNPREDICTABLE_INSTRUCTION);
9262
16980d0b
JB		 9263 return TRUE;
9264 }
9265 }
9266 return FALSE;
9267}
9268
73cd51e5
AV		 9269/* Print one mve instruction on INFO->STREAM.
9270 Return TRUE if the instuction matched, FALSE if this is not a
9271 recognised mve instruction. */
9272
9273static bfd_boolean
9274print_insn_mve (struct disassemble_info *info, long given)
9275{
9276 const struct mopcode32 *insn;
9277 void *stream = info->stream;
9278 fprintf_ftype func = info->fprintf_func;
9279
9280 for (insn = mve_opcodes; insn->assembler; insn++)
9281 {
9282 if (((given & insn->mask) == insn->value)
9283 && !is_mve_encoding_conflict (given, insn->mve_op))
9284 {
9285 signed long value_in_comment = 0;
9286 bfd_boolean is_unpredictable = FALSE;
9287 bfd_boolean is_undefined = FALSE;
9288 const char *c;
9289 enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
9290 enum mve_undefined undefined_cond = UNDEF_NONE;
9291
9292 /* Most vector mve instruction are illegal in a it block.
9293 There are a few exceptions; check for them. */
9294 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
9295 {
9296 is_unpredictable = TRUE;
9297 unpredictable_cond = UNPRED_IT_BLOCK;
9298 }
9299 else if (is_mve_unpredictable (given, insn->mve_op,
9300 &unpredictable_cond))
9301 is_unpredictable = TRUE;
9302
9303 if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
9304 is_undefined = TRUE;
9305
c4a23bf8
SP		 9306 /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV,
9307 i.e "VMOV Qd, Qm". */
9308 if ((insn->mve_op == MVE_VORR_REG)
9309 && (arm_decode_field (given, 1, 3)
9310 == arm_decode_field (given, 17, 19)))
9311 continue;
9312
73cd51e5
AV		 9313 for (c = insn->assembler; *c; c++)
9314 {
9315 if (*c == '%')
9316 {
9317 switch (*++c)
9318 {
9319 case '%':
9320 func (stream, "%%");
9321 break;
9322
ef1576a1
AV		 9323 case 'a':
9324 /* Don't print anything for '+' as it is implied. */
9325 if (arm_decode_field (given, 23, 23) == 0)
9326 func (stream, "-");
9327 break;
9328
143275ea
AV		 9329 case 'c':
9330 if (ifthen_state)
9331 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9332 break;
9333
aef6d006
AV		 9334 case 'd':
9335 print_mve_vld_str_addr (info, given, insn->mve_op);
9336 break;
9337
143275ea
AV		 9338 case 'i':
9339 {
9340 long mve_mask = mve_extract_pred_mask (given);
9341 func (stream, "%s", mve_predicatenames[mve_mask]);
9342 }
9343 break;
9344
23d00a41
SD		 9345 case 'j':
9346 {
9347 unsigned int imm5 = 0;
9348 imm5 |= arm_decode_field (given, 6, 7);
9349 imm5 |= (arm_decode_field (given, 12, 14) << 2);
9350 func (stream, "#%u", (imm5 == 0) ? 32 : imm5);
9351 }
9352 break;
9353
08132bdd
SP		 9354 case 'k':
9355 func (stream, "#%u",
9356 (arm_decode_field (given, 7, 7) == 0) ? 64 : 48);
9357 break;
9358
143275ea
AV		 9359 case 'n':
9360 print_vec_condition (info, given, insn->mve_op);
9361 break;
9362
ef1576a1
AV		 9363 case 'o':
9364 if (arm_decode_field (given, 0, 0) == 1)
9365 {
9366 unsigned long size
9367 = arm_decode_field (given, 4, 4)
9368 | (arm_decode_field (given, 6, 6) << 1);
9369
9370 func (stream, ", uxtw #%lu", size);
9371 }
9372 break;
9373
bf0b396d
AV		 9374 case 'm':
9375 print_mve_rounding_mode (info, given, insn->mve_op);
9376 break;
9377
9378 case 's':
9379 print_mve_vcvt_size (info, given, insn->mve_op);
9380 break;
9381
aef6d006
AV		 9382 case 'u':
9383 {
c507f10b
AV		 9384 unsigned long op1 = arm_decode_field (given, 21, 22);
9385
9386 if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
9387 {
9388 /* Check for signed. */
9389 if (arm_decode_field (given, 23, 23) == 0)
9390 {
9391 /* We don't print 's' for S32. */
9392 if ((arm_decode_field (given, 5, 6) == 0)
9393 && ((op1 == 0) || (op1 == 1)))
9394 ;
9395 else
9396 func (stream, "s");
9397 }
9398 else
9399 func (stream, "u");
9400 }
aef6d006 9401 else
c507f10b
AV		 9402 {
9403 if (arm_decode_field (given, 28, 28) == 0)
9404 func (stream, "s");
9405 else
9406 func (stream, "u");
9407 }
aef6d006 9408 }
ef1576a1 9409 break;
aef6d006 9410
143275ea
AV		 9411 case 'v':
9412 print_instruction_predicate (info);
9413 break;
9414
04d54ace
AV		 9415 case 'w':
9416 if (arm_decode_field (given, 21, 21) == 1)
9417 func (stream, "!");
9418 break;
9419
9420 case 'B':
9421 print_mve_register_blocks (info, given, insn->mve_op);
9422 break;
9423
c507f10b
AV		 9424 case 'E':
9425 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
9426
9427 print_simd_imm8 (info, given, 28, insn);
9428 break;
9429
9430 case 'N':
9431 print_mve_vmov_index (info, given);
9432 break;
9433
14925797
AV		 9434 case 'T':
9435 if (arm_decode_field (given, 12, 12) == 0)
9436 func (stream, "b");
9437 else
9438 func (stream, "t");
9439 break;
9440
d3b63143
AV		 9441 case 'X':
9442 if (arm_decode_field (given, 12, 12) == 1)
9443 func (stream, "x");
9444 break;
9445
143275ea
AV		 9446 case '0': case '1': case '2': case '3': case '4':
9447 case '5': case '6': case '7': case '8': case '9':
9448 {
9449 int width;
9450 unsigned long value;
9451
9452 c = arm_decode_bitfield (c, given, &value, &width);
9453
9454 switch (*c)
9455 {
9456 case 'Z':
9457 if (value == 13)
9458 is_unpredictable = TRUE;
9459 else if (value == 15)
9460 func (stream, "zr");
9461 else
9462 func (stream, "%s", arm_regnames[value]);
9463 break;
23d00a41 9464
e39c1607
SD		 9465 case 'c':
9466 func (stream, "%s", arm_conditional[value]);
9467 break;
9468
9469 case 'C':
9470 value ^= 1;
9471 func (stream, "%s", arm_conditional[value]);
9472 break;
9473
23d00a41
SD		 9474 case 'S':
9475 if (value == 13 || value == 15)
9476 is_unpredictable = TRUE;
9477 else
9478 func (stream, "%s", arm_regnames[value]);
9479 break;
9480
143275ea
AV		 9481 case 's':
9482 print_mve_size (info,
9483 value,
9484 insn->mve_op);
9485 break;
66dcaa5d
AV		 9486 case 'I':
9487 if (value == 1)
9488 func (stream, "i");
9489 break;
d3b63143
AV		 9490 case 'A':
9491 if (value == 1)
9492 func (stream, "a");
9493 break;
1c8f2df8
AV		 9494 case 'h':
9495 {
9496 unsigned int odd_reg = (value << 1) | 1;
9497 func (stream, "%s", arm_regnames[odd_reg]);
9498 }
9499 break;
ef1576a1
AV		 9500 case 'i':
9501 {
9502 unsigned long imm
9503 = arm_decode_field (given, 0, 6);
9504 unsigned long mod_imm = imm;
9505
9506 switch (insn->mve_op)
9507 {
9508 case MVE_VLDRW_GATHER_T5:
9509 case MVE_VSTRW_SCATTER_T5:
9510 mod_imm = mod_imm << 2;
9511 break;
9512 case MVE_VSTRD_SCATTER_T6:
9513 case MVE_VLDRD_GATHER_T6:
9514 mod_imm = mod_imm << 3;
9515 break;
9516
9517 default:
9518 break;
9519 }
9520
9521 func (stream, "%lu", mod_imm);
9522 }
9523 break;
bf0b396d
AV		 9524 case 'k':
9525 func (stream, "%lu", 64 - value);
9526 break;
1c8f2df8
AV		 9527 case 'l':
9528 {
9529 unsigned int even_reg = value << 1;
9530 func (stream, "%s", arm_regnames[even_reg]);
9531 }
9532 break;
9533 case 'u':
9534 switch (value)
9535 {
9536 case 0:
9537 func (stream, "1");
9538 break;
9539 case 1:
9540 func (stream, "2");
9541 break;
9542 case 2:
9543 func (stream, "4");
9544 break;
9545 case 3:
9546 func (stream, "8");
9547 break;
9548 default:
9549 break;
9550 }
9551 break;
897b9bbc
AV		 9552 case 'o':
9553 print_mve_rotate (info, value, width);
9554 break;
9743db03
AV		 9555 case 'r':
9556 func (stream, "%s", arm_regnames[value]);
9557 break;
04d54ace 9558 case 'd':
ed63aa17
AV		 9559 if (insn->mve_op == MVE_VQSHL_T2
9560 || insn->mve_op == MVE_VQSHLU_T3
9561 || insn->mve_op == MVE_VRSHR
9562 || insn->mve_op == MVE_VRSHRN
9563 || insn->mve_op == MVE_VSHL_T1
9564 || insn->mve_op == MVE_VSHLL_T1
9565 || insn->mve_op == MVE_VSHR
9566 || insn->mve_op == MVE_VSHRN
9567 || insn->mve_op == MVE_VSLI
9568 || insn->mve_op == MVE_VSRI)
9569 print_mve_shift_n (info, given, insn->mve_op);
9570 else if (insn->mve_op == MVE_VSHLL_T2)
9571 {
9572 switch (value)
9573 {
9574 case 0x00:
9575 func (stream, "8");
9576 break;
9577 case 0x01:
9578 func (stream, "16");
9579 break;
9580 case 0x10:
9581 print_mve_undefined (info, UNDEF_SIZE_0);
9582 break;
9583 default:
9584 assert (0);
9585 break;
9586 }
9587 }
9588 else
9589 {
9590 if (insn->mve_op == MVE_VSHLC && value == 0)
9591 value = 32;
9592 func (stream, "%ld", value);
9593 value_in_comment = value;
9594 }
04d54ace 9595 break;
c507f10b
AV		 9596 case 'F':
9597 func (stream, "s%ld", value);
9598 break;
143275ea
AV		 9599 case 'Q':
9600 if (value & 0x8)
9601 func (stream, "<illegal reg q%ld.5>", value);
9602 else
9603 func (stream, "q%ld", value);
9604 break;
c507f10b
AV		 9605 case 'x':
9606 func (stream, "0x%08lx", value);
9607 break;
143275ea
AV		 9608 default:
9609 abort ();
9610 }
9611 break;
9612 default:
9613 abort ();
9614 }
73cd51e5
AV		 9615 }
9616 }
9617 else
9618 func (stream, "%c", *c);
9619 }
9620
9621 if (value_in_comment > 32 || value_in_comment < -16)
9622 func (stream, "\t; 0x%lx", value_in_comment);
9623
9624 if (is_unpredictable)
9625 print_mve_unpredictable (info, unpredictable_cond);
9626
9627 if (is_undefined)
9628 print_mve_undefined (info, undefined_cond);
9629
143275ea
AV		 9630 if ((vpt_block_state.in_vpt_block == FALSE)
9631 && !ifthen_state
9632 && (is_vpt_instruction (given) == TRUE))
9633 mark_inside_vpt_block (given);
9634 else if (vpt_block_state.in_vpt_block == TRUE)
9635 update_vpt_block_state ();
9636
73cd51e5
AV		 9637 return TRUE;
9638 }
9639 }
9640 return FALSE;
9641}
9642
9643
90ec0d68
MGD		 9644/* Return the name of a v7A special register. */
9645
43e65147 9646static const char *
90ec0d68
MGD		 9647banked_regname (unsigned reg)
9648{
9649 switch (reg)
9650 {
9651 case 15: return "CPSR";
43e65147 9652 case 32: return "R8_usr";
90ec0d68
MGD		 9653 case 33: return "R9_usr";
9654 case 34: return "R10_usr";
9655 case 35: return "R11_usr";
9656 case 36: return "R12_usr";
9657 case 37: return "SP_usr";
9658 case 38: return "LR_usr";
43e65147 9659 case 40: return "R8_fiq";
90ec0d68
MGD		 9660 case 41: return "R9_fiq";
9661 case 42: return "R10_fiq";
9662 case 43: return "R11_fiq";
9663 case 44: return "R12_fiq";
9664 case 45: return "SP_fiq";
9665 case 46: return "LR_fiq";
9666 case 48: return "LR_irq";
9667 case 49: return "SP_irq";
9668 case 50: return "LR_svc";
9669 case 51: return "SP_svc";
9670 case 52: return "LR_abt";
9671 case 53: return "SP_abt";
9672 case 54: return "LR_und";
9673 case 55: return "SP_und";
9674 case 60: return "LR_mon";
9675 case 61: return "SP_mon";
9676 case 62: return "ELR_hyp";
9677 case 63: return "SP_hyp";
9678 case 79: return "SPSR";
9679 case 110: return "SPSR_fiq";
9680 case 112: return "SPSR_irq";
9681 case 114: return "SPSR_svc";
9682 case 116: return "SPSR_abt";
9683 case 118: return "SPSR_und";
9684 case 124: return "SPSR_mon";
9685 case 126: return "SPSR_hyp";
9686 default: return NULL;
9687 }
9688}
9689
e797f7e0
MGD		 9690/* Return the name of the DMB/DSB option. */
9691static const char *
9692data_barrier_option (unsigned option)
9693{
9694 switch (option & 0xf)
9695 {
9696 case 0xf: return "sy";
9697 case 0xe: return "st";
9698 case 0xd: return "ld";
9699 case 0xb: return "ish";
9700 case 0xa: return "ishst";
9701 case 0x9: return "ishld";
9702 case 0x7: return "un";
9703 case 0x6: return "unst";
9704 case 0x5: return "nshld";
9705 case 0x3: return "osh";
9706 case 0x2: return "oshst";
9707 case 0x1: return "oshld";
9708 default: return NULL;
9709 }
9710}
9711
4a5329c6
ZW		 9712/* Print one ARM instruction from PC on INFO->STREAM. */
9713
9714static void
9715print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 9716{
6b5d3a4d 9717 const struct opcode32 *insn;
6a51a8a8 9718 void *stream = info->stream;
6b5d3a4d 9719 fprintf_ftype func = info->fprintf_func;
b0e28b39 9720 struct arm_private_data *private_data = info->private_data;
252b5132 9721
16980d0b
JB		 9722 if (print_insn_coprocessor (pc, info, given, FALSE))
9723 return;
9724
9725 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 9726 return;
9727
33593eaf
MM		 9728 if (print_insn_generic_coprocessor (pc, info, given, FALSE))
9729 return;
9730
252b5132
RH		 9731 for (insn = arm_opcodes; insn->assembler; insn++)
9732 {
0313a2b8
NC		 9733 if ((given & insn->mask) != insn->value)
9734 continue;
823d2571
TG		 9735
9736 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 9737 continue;
9738
9739 /* Special case: an instruction with all bits set in the condition field
9740 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
9741 or by the catchall at the end of the table. */
9742 if ((given & 0xF0000000) != 0xF0000000
9743 || (insn->mask & 0xF0000000) == 0xF0000000
9744 || (insn->mask == 0 && insn->value == 0))
252b5132 9745 {
ff4a8d2b
NC		 9746 unsigned long u_reg = 16;
9747 unsigned long U_reg = 16;
ab8e2090 9748 bfd_boolean is_unpredictable = FALSE;
05413229 9749 signed long value_in_comment = 0;
6b5d3a4d 9750 const char *c;
b34976b6 9751
252b5132
RH		 9752 for (c = insn->assembler; *c; c++)
9753 {
9754 if (*c == '%')
9755 {
c1e26897
NC		 9756 bfd_boolean allow_unpredictable = FALSE;
9757
252b5132
RH		 9758 switch (*++c)
9759 {
9760 case '%':
9761 func (stream, "%%");
9762 break;
9763
9764 case 'a':
05413229 9765 value_in_comment = print_arm_address (pc, info, given);
62b3e311 9766 break;
252b5132 9767
62b3e311
PB		 9768 case 'P':
9769 /* Set P address bit and use normal address
9770 printing routine. */
c1e26897 9771 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 9772 break;
9773
c1e26897
NC		 9774 case 'S':
9775 allow_unpredictable = TRUE;
1a0670f3 9776 /* Fall through. */
252b5132
RH		 9777 case 's':
9778 if ((given & 0x004f0000) == 0x004f0000)
9779 {
58efb6c0 9780 /* PC relative with immediate offset. */
f8b960bc 9781 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 9782
aefd8a40
NC		 9783 if (PRE_BIT_SET)
9784 {
26d97720
NS		 9785 /* Elide positive zero offset. */
9786 if (offset || NEGATIVE_BIT_SET)
9787 func (stream, "[pc, #%s%d]\t; ",
d908c8af 9788 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 9789 else
26d97720
NS		 9790 func (stream, "[pc]\t; ");
9791 if (NEGATIVE_BIT_SET)
9792 offset = -offset;
aefd8a40
NC		 9793 info->print_address_func (offset + pc + 8, info);
9794 }
9795 else
9796 {
26d97720
NS		 9797 /* Always show the offset. */
9798 func (stream, "[pc], #%s%d",
d908c8af 9799 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 9800 if (! allow_unpredictable)
9801 is_unpredictable = TRUE;
aefd8a40 9802 }
252b5132
RH		 9803 }
9804 else
9805 {
fe56b6ce
NC		 9806 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
9807
b34976b6 9808 func (stream, "[%s",
252b5132 9809 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 9810
c1e26897 9811 if (PRE_BIT_SET)
252b5132 9812 {
c1e26897 9813 if (IMMEDIATE_BIT_SET)
252b5132 9814 {
26d97720
NS		 9815 /* Elide offset for non-writeback
9816 positive zero. */
9817 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
9818 || offset)
9819 func (stream, ", #%s%d",
9820 NEGATIVE_BIT_SET ? "-" : "", offset);
9821
9822 if (NEGATIVE_BIT_SET)
9823 offset = -offset;
945ee430 9824
fe56b6ce 9825 value_in_comment = offset;
252b5132 9826 }
945ee430 9827 else
ff4a8d2b
NC		 9828 {
9829 /* Register Offset or Register Pre-Indexed. */
9830 func (stream, ", %s%s",
9831 NEGATIVE_BIT_SET ? "-" : "",
9832 arm_regnames[given & 0xf]);
9833
9834 /* Writing back to the register that is the source/
9835 destination of the load/store is unpredictable. */
9836 if (! allow_unpredictable
9837 && WRITEBACK_BIT_SET
9838 && ((given & 0xf) == ((given >> 12) & 0xf)))
9839 is_unpredictable = TRUE;
9840 }
252b5132 9841
b34976b6 9842 func (stream, "]%s",
c1e26897 9843 WRITEBACK_BIT_SET ? "!" : "");
252b5132 9844 }
945ee430 9845 else
252b5132 9846 {
c1e26897 9847 if (IMMEDIATE_BIT_SET)
252b5132 9848 {
945ee430 9849 /* Immediate Post-indexed. */
aefd8a40 9850 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 9851 func (stream, "], #%s%d",
9852 NEGATIVE_BIT_SET ? "-" : "", offset);
9853 if (NEGATIVE_BIT_SET)
9854 offset = -offset;
fe56b6ce 9855 value_in_comment = offset;
252b5132 9856 }
945ee430 9857 else
ff4a8d2b
NC		 9858 {
9859 /* Register Post-indexed. */
9860 func (stream, "], %s%s",
9861 NEGATIVE_BIT_SET ? "-" : "",
9862 arm_regnames[given & 0xf]);
9863
9864 /* Writing back to the register that is the source/
9865 destination of the load/store is unpredictable. */
9866 if (! allow_unpredictable
9867 && (given & 0xf) == ((given >> 12) & 0xf))
9868 is_unpredictable = TRUE;
9869 }
c1e26897 9870
07a28fab
NC		 9871 if (! allow_unpredictable)
9872 {
9873 /* Writeback is automatically implied by post- addressing.
9874 Setting the W bit is unnecessary and ARM specify it as
9875 being unpredictable. */
9876 if (WRITEBACK_BIT_SET
9877 /* Specifying the PC register as the post-indexed
9878 registers is also unpredictable. */
ab8e2090
NC		 9879 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
9880 is_unpredictable = TRUE;
07a28fab 9881 }
252b5132
RH		 9882 }
9883 }
9884 break;
b34976b6 9885
252b5132 9886 case 'b':
6b5d3a4d 9887 {
f8b960bc 9888 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
05413229 9889 info->print_address_func (disp * 4 + pc + 8, info);
6b5d3a4d 9890 }
252b5132
RH		 9891 break;
9892
9893 case 'c':
c22aaad1
PB		 9894 if (((given >> 28) & 0xf) != 0xe)
9895 func (stream, "%s",
9896 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 9897 break;
9898
9899 case 'm':
9900 {
9901 int started = 0;
9902 int reg;
9903
9904 func (stream, "{");
9905 for (reg = 0; reg < 16; reg++)
9906 if ((given & (1 << reg)) != 0)
9907 {
9908 if (started)
9909 func (stream, ", ");
9910 started = 1;
9911 func (stream, "%s", arm_regnames[reg]);
9912 }
9913 func (stream, "}");
ab8e2090
NC		 9914 if (! started)
9915 is_unpredictable = TRUE;
252b5132
RH		 9916 }
9917 break;
9918
37b37b2d 9919 case 'q':
78c66db8 9920 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 9921 break;
9922
252b5132
RH		 9923 case 'o':
9924 if ((given & 0x02000000) != 0)
9925 {
a415b1cd
JB		 9926 unsigned int rotate = (given & 0xf00) >> 7;
9927 unsigned int immed = (given & 0xff);
9928 unsigned int a, i;
9929
ebd1c6d1
AM		 9930 a = (immed << ((32 - rotate) & 31)
9931 | immed >> rotate) & 0xffffffff;
a415b1cd
JB		 9932 /* If there is another encoding with smaller rotate,
9933 the rotate should be specified directly. */
9934 for (i = 0; i < 32; i += 2)
ebd1c6d1 9935 if ((a << i | a >> ((32 - i) & 31)) <= 0xff)
a415b1cd
JB		 9936 break;
9937
9938 if (i != rotate)
9939 func (stream, "#%d, %d", immed, rotate);
9940 else
9941 func (stream, "#%d", a);
9942 value_in_comment = a;
252b5132
RH		 9943 }
9944 else
78c66db8 9945 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 9946 break;
9947
9948 case 'p':
9949 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 9950 {
823d2571
TG		 9951 arm_feature_set arm_ext_v6 =
9952 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
9953
aefd8a40
NC		 9954 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
9955 mechanism for setting PSR flag bits. They are
9956 obsolete in V6 onwards. */
823d2571
TG		 9957 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
9958 arm_ext_v6))
aefd8a40 9959 func (stream, "p");
4ab90a7a
AV		 9960 else
9961 is_unpredictable = TRUE;
aefd8a40 9962 }
252b5132
RH		 9963 break;
9964
9965 case 't':
9966 if ((given & 0x01200000) == 0x00200000)
9967 func (stream, "t");
9968 break;
9969
252b5132 9970 case 'A':
05413229
NC		 9971 {
9972 int offset = given & 0xff;
f02232aa 9973
05413229 9974 value_in_comment = offset * 4;
c1e26897 9975 if (NEGATIVE_BIT_SET)
05413229 9976 value_in_comment = - value_in_comment;
f02232aa 9977
05413229 9978 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 9979
c1e26897 9980 if (PRE_BIT_SET)
05413229
NC		 9981 {
9982 if (offset)
fe56b6ce 9983 func (stream, ", #%d]%s",
d908c8af 9984 (int) value_in_comment,
c1e26897 9985 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 9986 else
9987 func (stream, "]");
9988 }
9989 else
9990 {
9991 func (stream, "]");
f02232aa 9992
c1e26897 9993 if (WRITEBACK_BIT_SET)
05413229
NC		 9994 {
9995 if (offset)
d908c8af 9996 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 9997 }
9998 else
fe56b6ce 9999 {
d908c8af 10000 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 10001 value_in_comment = offset;
10002 }
05413229
NC		 10003 }
10004 }
252b5132
RH		 10005 break;
10006
077b8428
NC		 10007 case 'B':
10008 /* Print ARM V5 BLX(1) address: pc+25 bits. */
10009 {
10010 bfd_vma address;
10011 bfd_vma offset = 0;
b34976b6 10012
c1e26897 10013 if (! NEGATIVE_BIT_SET)
077b8428
NC		 10014 /* Is signed, hi bits should be ones. */
10015 offset = (-1) ^ 0x00ffffff;
10016
10017 /* Offset is (SignExtend(offset field)<<2). */
10018 offset += given & 0x00ffffff;
10019 offset <<= 2;
10020 address = offset + pc + 8;
b34976b6 10021
8f06b2d8
PB		 10022 if (given & 0x01000000)
10023 /* H bit allows addressing to 2-byte boundaries. */
10024 address += 2;
b1ee46c5 10025
8f06b2d8 10026 info->print_address_func (address, info);
b1ee46c5 10027 }
b1ee46c5
AH		 10028 break;
10029
252b5132 10030 case 'C':
90ec0d68
MGD		 10031 if ((given & 0x02000200) == 0x200)
10032 {
10033 const char * name;
10034 unsigned sysm = (given & 0x004f0000) >> 16;
10035
10036 sysm |= (given & 0x300) >> 4;
10037 name = banked_regname (sysm);
10038
10039 if (name != NULL)
10040 func (stream, "%s", name);
10041 else
d908c8af 10042 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 10043 }
10044 else
10045 {
43e65147 10046 func (stream, "%cPSR_",
90ec0d68
MGD		 10047 (given & 0x00400000) ? 'S' : 'C');
10048 if (given & 0x80000)
10049 func (stream, "f");
10050 if (given & 0x40000)
10051 func (stream, "s");
10052 if (given & 0x20000)
10053 func (stream, "x");
10054 if (given & 0x10000)
10055 func (stream, "c");
10056 }
252b5132
RH		 10057 break;
10058
62b3e311 10059 case 'U':
43e65147 10060 if ((given & 0xf0) == 0x60)
62b3e311 10061 {
52e7f43d
RE		 10062 switch (given & 0xf)
10063 {
10064 case 0xf: func (stream, "sy"); break;
10065 default:
10066 func (stream, "#%d", (int) given & 0xf);
10067 break;
10068 }
43e65147
L		 10069 }
10070 else
52e7f43d 10071 {
e797f7e0
MGD		 10072 const char * opt = data_barrier_option (given & 0xf);
10073 if (opt != NULL)
10074 func (stream, "%s", opt);
10075 else
52e7f43d 10076 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 10077 }
10078 break;
10079
b34976b6 10080 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 10081 case '5': case '6': case '7': case '8': case '9':
10082 {
16980d0b
JB		 10083 int width;
10084 unsigned long value;
252b5132 10085
16980d0b 10086 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 10087
252b5132
RH		 10088 switch (*c)
10089 {
ab8e2090
NC		 10090 case 'R':
10091 if (value == 15)
10092 is_unpredictable = TRUE;
10093 /* Fall through. */
16980d0b 10094 case 'r':
9eb6c0f1
MGD		 10095 case 'T':
10096 /* We want register + 1 when decoding T. */
10097 if (*c == 'T')
10098 ++value;
10099
ff4a8d2b
NC		 10100 if (c[1] == 'u')
10101 {
10102 /* Eat the 'u' character. */
10103 ++ c;
10104
10105 if (u_reg == value)
10106 is_unpredictable = TRUE;
10107 u_reg = value;
10108 }
10109 if (c[1] == 'U')
10110 {
10111 /* Eat the 'U' character. */
10112 ++ c;
10113
10114 if (U_reg == value)
10115 is_unpredictable = TRUE;
10116 U_reg = value;
10117 }
16980d0b
JB		 10118 func (stream, "%s", arm_regnames[value]);
10119 break;
10120 case 'd':
10121 func (stream, "%ld", value);
05413229 10122 value_in_comment = value;
16980d0b
JB		 10123 break;
10124 case 'b':
10125 func (stream, "%ld", value * 8);
05413229 10126 value_in_comment = value * 8;
16980d0b
JB		 10127 break;
10128 case 'W':
10129 func (stream, "%ld", value + 1);
05413229 10130 value_in_comment = value + 1;
16980d0b
JB		 10131 break;
10132 case 'x':
10133 func (stream, "0x%08lx", value);
10134
10135 /* Some SWI instructions have special
10136 meanings. */
10137 if ((given & 0x0fffffff) == 0x0FF00000)
10138 func (stream, "\t; IMB");
10139 else if ((given & 0x0fffffff) == 0x0FF00001)
10140 func (stream, "\t; IMBRange");
10141 break;
10142 case 'X':
10143 func (stream, "%01lx", value & 0xf);
05413229 10144 value_in_comment = value;
252b5132
RH		 10145 break;
10146 case '`':
10147 c++;
16980d0b 10148 if (value == 0)
252b5132
RH		 10149 func (stream, "%c", *c);
10150 break;
10151 case '\'':
10152 c++;
16980d0b 10153 if (value == ((1ul << width) - 1))
252b5132
RH		 10154 func (stream, "%c", *c);
10155 break;
10156 case '?':
fe56b6ce 10157 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 10158 c += 1 << width;
252b5132
RH		 10159 break;
10160 default:
10161 abort ();
10162 }
dffaa15c
AM		 10163 }
10164 break;
0dd132b6 10165
dffaa15c
AM		 10166 case 'e':
10167 {
10168 int imm;
0dd132b6 10169
dffaa15c
AM		 10170 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
10171 func (stream, "%d", imm);
10172 value_in_comment = imm;
10173 }
10174 break;
fe56b6ce 10175
dffaa15c
AM		 10176 case 'E':
10177 /* LSB and WIDTH fields of BFI or BFC. The machine-
10178 language instruction encodes LSB and MSB. */
10179 {
10180 long msb = (given & 0x001f0000) >> 16;
10181 long lsb = (given & 0x00000f80) >> 7;
10182 long w = msb - lsb + 1;
0a003adc 10183
dffaa15c
AM		 10184 if (w > 0)
10185 func (stream, "#%lu, #%lu", lsb, w);
10186 else
10187 func (stream, "(invalid: %lu:%lu)", lsb, msb);
10188 }
10189 break;
90ec0d68 10190
dffaa15c
AM		 10191 case 'R':
10192 /* Get the PSR/banked register name. */
10193 {
10194 const char * name;
10195 unsigned sysm = (given & 0x004f0000) >> 16;
90ec0d68 10196
dffaa15c
AM		 10197 sysm |= (given & 0x300) >> 4;
10198 name = banked_regname (sysm);
90ec0d68 10199
dffaa15c
AM		 10200 if (name != NULL)
10201 func (stream, "%s", name);
10202 else
10203 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
10204 }
10205 break;
fe56b6ce 10206
dffaa15c
AM		 10207 case 'V':
10208 /* 16-bit unsigned immediate from a MOVT or MOVW
10209 instruction, encoded in bits 0:11 and 15:19. */
10210 {
10211 long hi = (given & 0x000f0000) >> 4;
10212 long lo = (given & 0x00000fff);
10213 long imm16 = hi | lo;
0a003adc 10214
dffaa15c
AM		 10215 func (stream, "#%lu", imm16);
10216 value_in_comment = imm16;
252b5132 10217 }
dffaa15c
AM		 10218 break;
10219
10220 default:
10221 abort ();
252b5132
RH		 10222 }
10223 }
10224 else
10225 func (stream, "%c", *c);
10226 }
05413229
NC		 10227
10228 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 10229 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 10230
10231 if (is_unpredictable)
10232 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 10233
4a5329c6 10234 return;
252b5132
RH		 10235 }
10236 }
0b347048
TC		 10237 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
10238 return;
252b5132
RH		 10239}
10240
4a5329c6 10241/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 10242
4a5329c6
ZW		 10243static void
10244print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 10245{
6b5d3a4d 10246 const struct opcode16 *insn;
6a51a8a8
AM		 10247 void *stream = info->stream;
10248 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 10249
10250 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 10251 if ((given & insn->mask) == insn->value)
10252 {
05413229 10253 signed long value_in_comment = 0;
6b5d3a4d 10254 const char *c = insn->assembler;
05413229 10255
c19d1205
ZW		 10256 for (; *c; c++)
10257 {
10258 int domaskpc = 0;
10259 int domasklr = 0;
10260
10261 if (*c != '%')
10262 {
10263 func (stream, "%c", *c);
10264 continue;
10265 }
252b5132 10266
c19d1205
ZW		 10267 switch (*++c)
10268 {
10269 case '%':
10270 func (stream, "%%");
10271 break;
b34976b6 10272
c22aaad1
PB		 10273 case 'c':
10274 if (ifthen_state)
10275 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10276 break;
10277
10278 case 'C':
10279 if (ifthen_state)
10280 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10281 else
10282 func (stream, "s");
10283 break;
10284
10285 case 'I':
10286 {
10287 unsigned int tmp;
10288
10289 ifthen_next_state = given & 0xff;
10290 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
10291 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
10292 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
10293 }
10294 break;
10295
10296 case 'x':
10297 if (ifthen_next_state)
10298 func (stream, "\t; unpredictable branch in IT block\n");
10299 break;
10300
10301 case 'X':
10302 if (ifthen_state)
10303 func (stream, "\t; unpredictable <IT:%s>",
10304 arm_conditional[IFTHEN_COND]);
10305 break;
10306
c19d1205
ZW		 10307 case 'S':
10308 {
10309 long reg;
10310
10311 reg = (given >> 3) & 0x7;
10312 if (given & (1 << 6))
10313 reg += 8;
4f3c3dbb 10314
c19d1205
ZW		 10315 func (stream, "%s", arm_regnames[reg]);
10316 }
10317 break;
baf0cc5e 10318
c19d1205 10319 case 'D':
4f3c3dbb 10320 {
c19d1205
ZW		 10321 long reg;
10322
10323 reg = given & 0x7;
10324 if (given & (1 << 7))
10325 reg += 8;
10326
10327 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 10328 }
c19d1205
ZW		 10329 break;
10330
10331 case 'N':
10332 if (given & (1 << 8))
10333 domasklr = 1;
10334 /* Fall through. */
10335 case 'O':
10336 if (*c == 'O' && (given & (1 << 8)))
10337 domaskpc = 1;
10338 /* Fall through. */
10339 case 'M':
10340 {
10341 int started = 0;
10342 int reg;
10343
10344 func (stream, "{");
10345
10346 /* It would be nice if we could spot
10347 ranges, and generate the rS-rE format: */
10348 for (reg = 0; (reg < 8); reg++)
10349 if ((given & (1 << reg)) != 0)
10350 {
10351 if (started)
10352 func (stream, ", ");
10353 started = 1;
10354 func (stream, "%s", arm_regnames[reg]);
10355 }
10356
10357 if (domasklr)
10358 {
10359 if (started)
10360 func (stream, ", ");
10361 started = 1;
d908c8af 10362 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 10363 }
10364
10365 if (domaskpc)
10366 {
10367 if (started)
10368 func (stream, ", ");
d908c8af 10369 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 10370 }
10371
10372 func (stream, "}");
10373 }
10374 break;
10375
4547cb56
NC		 10376 case 'W':
10377 /* Print writeback indicator for a LDMIA. We are doing a
10378 writeback if the base register is not in the register
10379 mask. */
10380 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
10381 func (stream, "!");
dffaa15c 10382 break;
4547cb56 10383
c19d1205
ZW		 10384 case 'b':
10385 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
10386 {
10387 bfd_vma address = (pc + 4
10388 + ((given & 0x00f8) >> 2)
10389 + ((given & 0x0200) >> 3));
10390 info->print_address_func (address, info);
10391 }
10392 break;
10393
10394 case 's':
10395 /* Right shift immediate -- bits 6..10; 1-31 print
10396 as themselves, 0 prints as 32. */
10397 {
10398 long imm = (given & 0x07c0) >> 6;
10399 if (imm == 0)
10400 imm = 32;
0fd3a477 10401 func (stream, "#%ld", imm);
c19d1205
ZW		 10402 }
10403 break;
10404
10405 case '0': case '1': case '2': case '3': case '4':
10406 case '5': case '6': case '7': case '8': case '9':
10407 {
10408 int bitstart = *c++ - '0';
10409 int bitend = 0;
10410
10411 while (*c >= '0' && *c <= '9')
10412 bitstart = (bitstart * 10) + *c++ - '0';
10413
10414 switch (*c)
10415 {
10416 case '-':
10417 {
f8b960bc 10418 bfd_vma reg;
c19d1205
ZW		 10419
10420 c++;
10421 while (*c >= '0' && *c <= '9')
10422 bitend = (bitend * 10) + *c++ - '0';
10423 if (!bitend)
10424 abort ();
10425 reg = given >> bitstart;
10426 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 10427
c19d1205
ZW		 10428 switch (*c)
10429 {
10430 case 'r':
10431 func (stream, "%s", arm_regnames[reg]);
10432 break;
10433
10434 case 'd':
d908c8af 10435 func (stream, "%ld", (long) reg);
05413229 10436 value_in_comment = reg;
c19d1205
ZW		 10437 break;
10438
10439 case 'H':
d908c8af 10440 func (stream, "%ld", (long) (reg << 1));
05413229 10441 value_in_comment = reg << 1;
c19d1205
ZW		 10442 break;
10443
10444 case 'W':
d908c8af 10445 func (stream, "%ld", (long) (reg << 2));
05413229 10446 value_in_comment = reg << 2;
c19d1205
ZW		 10447 break;
10448
10449 case 'a':
10450 /* PC-relative address -- the bottom two
10451 bits of the address are dropped
10452 before the calculation. */
10453 info->print_address_func
10454 (((pc + 4) & ~3) + (reg << 2), info);
05413229 10455 value_in_comment = 0;
c19d1205
ZW		 10456 break;
10457
10458 case 'x':
d908c8af 10459 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 10460 break;
10461
c19d1205
ZW		 10462 case 'B':
10463 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6b5d3a4d 10464 info->print_address_func (reg * 2 + pc + 4, info);
05413229 10465 value_in_comment = 0;
c19d1205
ZW		 10466 break;
10467
10468 case 'c':
c22aaad1 10469 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 10470 break;
10471
10472 default:
10473 abort ();
10474 }
10475 }
10476 break;
10477
10478 case '\'':
10479 c++;
10480 if ((given & (1 << bitstart)) != 0)
10481 func (stream, "%c", *c);
10482 break;
10483
10484 case '?':
10485 ++c;
10486 if ((given & (1 << bitstart)) != 0)
10487 func (stream, "%c", *c++);
10488 else
10489 func (stream, "%c", *++c);
10490 break;
10491
10492 default:
10493 abort ();
10494 }
10495 }
10496 break;
10497
10498 default:
10499 abort ();
10500 }
10501 }
05413229
NC		 10502
10503 if (value_in_comment > 32 || value_in_comment < -16)
10504 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 10505 return;
c19d1205
ZW		 10506 }
10507
10508 /* No match. */
0b347048
TC		 10509 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
10510 return;
c19d1205
ZW		 10511}
10512
62b3e311 10513/* Return the name of an V7M special register. */
fe56b6ce 10514
62b3e311
PB		 10515static const char *
10516psr_name (int regno)
10517{
10518 switch (regno)
10519 {
1a336194
TP		 10520 case 0x0: return "APSR";
10521 case 0x1: return "IAPSR";
10522 case 0x2: return "EAPSR";
10523 case 0x3: return "PSR";
10524 case 0x5: return "IPSR";
10525 case 0x6: return "EPSR";
10526 case 0x7: return "IEPSR";
10527 case 0x8: return "MSP";
10528 case 0x9: return "PSP";
10529 case 0xa: return "MSPLIM";
10530 case 0xb: return "PSPLIM";
10531 case 0x10: return "PRIMASK";
10532 case 0x11: return "BASEPRI";
10533 case 0x12: return "BASEPRI_MAX";
10534 case 0x13: return "FAULTMASK";
10535 case 0x14: return "CONTROL";
16a1fa25
TP		 10536 case 0x88: return "MSP_NS";
10537 case 0x89: return "PSP_NS";
1a336194
TP		 10538 case 0x8a: return "MSPLIM_NS";
10539 case 0x8b: return "PSPLIM_NS";
10540 case 0x90: return "PRIMASK_NS";
10541 case 0x91: return "BASEPRI_NS";
10542 case 0x93: return "FAULTMASK_NS";
10543 case 0x94: return "CONTROL_NS";
10544 case 0x98: return "SP_NS";
62b3e311
PB		 10545 default: return "<unknown>";
10546 }
10547}
10548
4a5329c6
ZW		 10549/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
10550
10551static void
10552print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 10553{
6b5d3a4d 10554 const struct opcode32 *insn;
c19d1205
ZW		 10555 void *stream = info->stream;
10556 fprintf_ftype func = info->fprintf_func;
73cd51e5 10557 bfd_boolean is_mve = is_mve_architecture (info);
c19d1205 10558
16980d0b
JB		 10559 if (print_insn_coprocessor (pc, info, given, TRUE))
10560 return;
10561
73cd51e5
AV		 10562 if ((is_mve == FALSE) && print_insn_neon (info, given, TRUE))
10563 return;
10564
10565 if (is_mve && print_insn_mve (info, given))
8f06b2d8
PB		 10566 return;
10567
33593eaf
MM		 10568 if (print_insn_generic_coprocessor (pc, info, given, TRUE))
10569 return;
10570
c19d1205
ZW		 10571 for (insn = thumb32_opcodes; insn->assembler; insn++)
10572 if ((given & insn->mask) == insn->value)
10573 {
4b5a202f 10574 bfd_boolean is_clrm = FALSE;
ff4a8d2b 10575 bfd_boolean is_unpredictable = FALSE;
05413229 10576 signed long value_in_comment = 0;
6b5d3a4d 10577 const char *c = insn->assembler;
05413229 10578
c19d1205
ZW		 10579 for (; *c; c++)
10580 {
10581 if (*c != '%')
10582 {
10583 func (stream, "%c", *c);
10584 continue;
10585 }
10586
10587 switch (*++c)
10588 {
10589 case '%':
10590 func (stream, "%%");
10591 break;
10592
c22aaad1
PB		 10593 case 'c':
10594 if (ifthen_state)
10595 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10596 break;
10597
10598 case 'x':
10599 if (ifthen_next_state)
10600 func (stream, "\t; unpredictable branch in IT block\n");
10601 break;
10602
10603 case 'X':
10604 if (ifthen_state)
10605 func (stream, "\t; unpredictable <IT:%s>",
10606 arm_conditional[IFTHEN_COND]);
10607 break;
10608
c19d1205
ZW		 10609 case 'I':
10610 {
10611 unsigned int imm12 = 0;
fe56b6ce 10612
c19d1205
ZW		 10613 imm12 |= (given & 0x000000ffu);
10614 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 10615 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 10616 func (stream, "#%u", imm12);
10617 value_in_comment = imm12;
c19d1205
ZW		 10618 }
10619 break;
10620
10621 case 'M':
10622 {
10623 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 10624
c19d1205
ZW		 10625 bits |= (given & 0x000000ffu);
10626 bits |= (given & 0x00007000u) >> 4;
10627 bits |= (given & 0x04000000u) >> 15;
10628 imm8 = (bits & 0x0ff);
10629 mod = (bits & 0xf00) >> 8;
10630 switch (mod)
10631 {
10632 case 0: imm = imm8; break;
c1e26897
NC		 10633 case 1: imm = ((imm8 << 16) | imm8); break;
10634 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
10635 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 10636 default:
10637 mod = (bits & 0xf80) >> 7;
10638 imm8 = (bits & 0x07f) | 0x80;
10639 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
10640 }
fe56b6ce
NC		 10641 func (stream, "#%u", imm);
10642 value_in_comment = imm;
c19d1205
ZW		 10643 }
10644 break;
43e65147 10645
c19d1205
ZW		 10646 case 'J':
10647 {
10648 unsigned int imm = 0;
fe56b6ce 10649
c19d1205
ZW		 10650 imm |= (given & 0x000000ffu);
10651 imm |= (given & 0x00007000u) >> 4;
10652 imm |= (given & 0x04000000u) >> 15;
10653 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 10654 func (stream, "#%u", imm);
10655 value_in_comment = imm;
c19d1205
ZW		 10656 }
10657 break;
10658
10659 case 'K':
10660 {
10661 unsigned int imm = 0;
fe56b6ce 10662
c19d1205
ZW		 10663 imm |= (given & 0x000f0000u) >> 16;
10664 imm |= (given & 0x00000ff0u) >> 0;
10665 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 10666 func (stream, "#%u", imm);
10667 value_in_comment = imm;
c19d1205
ZW		 10668 }
10669 break;
10670
74db7efb
NC		 10671 case 'H':
10672 {
10673 unsigned int imm = 0;
10674
10675 imm |= (given & 0x000f0000u) >> 4;
10676 imm |= (given & 0x00000fffu) >> 0;
10677 func (stream, "#%u", imm);
10678 value_in_comment = imm;
10679 }
10680 break;
10681
90ec0d68
MGD		 10682 case 'V':
10683 {
10684 unsigned int imm = 0;
10685
10686 imm |= (given & 0x00000fffu);
10687 imm |= (given & 0x000f0000u) >> 4;
10688 func (stream, "#%u", imm);
10689 value_in_comment = imm;
10690 }
10691 break;
10692
c19d1205
ZW		 10693 case 'S':
10694 {
10695 unsigned int reg = (given & 0x0000000fu);
10696 unsigned int stp = (given & 0x00000030u) >> 4;
10697 unsigned int imm = 0;
10698 imm |= (given & 0x000000c0u) >> 6;
10699 imm |= (given & 0x00007000u) >> 10;
10700
10701 func (stream, "%s", arm_regnames[reg]);
10702 switch (stp)
10703 {
10704 case 0:
10705 if (imm > 0)
10706 func (stream, ", lsl #%u", imm);
10707 break;
10708
10709 case 1:
10710 if (imm == 0)
10711 imm = 32;
10712 func (stream, ", lsr #%u", imm);
10713 break;
10714
10715 case 2:
10716 if (imm == 0)
10717 imm = 32;
10718 func (stream, ", asr #%u", imm);
10719 break;
10720
10721 case 3:
10722 if (imm == 0)
10723 func (stream, ", rrx");
10724 else
10725 func (stream, ", ror #%u", imm);
10726 }
10727 }
10728 break;
10729
10730 case 'a':
10731 {
10732 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 10733 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 10734 unsigned int op = (given & 0x00000f00) >> 8;
10735 unsigned int i12 = (given & 0x00000fff);
10736 unsigned int i8 = (given & 0x000000ff);
10737 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 10738 bfd_vma offset = 0;
c19d1205
ZW		 10739
10740 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 10741 if (U) /* 12-bit positive immediate offset. */
10742 {
10743 offset = i12;
10744 if (Rn != 15)
10745 value_in_comment = offset;
10746 }
10747 else if (Rn == 15) /* 12-bit negative immediate offset. */
10748 offset = - (int) i12;
10749 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 10750 {
10751 unsigned int Rm = (i8 & 0x0f);
10752 unsigned int sh = (i8 & 0x30) >> 4;
05413229 10753
c19d1205
ZW		 10754 func (stream, ", %s", arm_regnames[Rm]);
10755 if (sh)
10756 func (stream, ", lsl #%u", sh);
10757 func (stream, "]");
10758 break;
10759 }
10760 else switch (op)
10761 {
05413229 10762 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 10763 offset = i8;
10764 break;
10765
05413229 10766 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 10767 offset = -i8;
10768 break;
10769
05413229 10770 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 10771 offset = i8;
10772 writeback = TRUE;
10773 break;
10774
05413229 10775 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 10776 offset = -i8;
10777 writeback = TRUE;
10778 break;
10779
05413229 10780 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 10781 offset = i8;
10782 postind = TRUE;
10783 break;
10784
05413229 10785 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 10786 offset = -i8;
10787 postind = TRUE;
10788 break;
10789
10790 default:
10791 func (stream, ", <undefined>]");
10792 goto skip;
10793 }
10794
10795 if (postind)
d908c8af 10796 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 10797 else
10798 {
10799 if (offset)
d908c8af 10800 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 10801 func (stream, writeback ? "]!" : "]");
10802 }
10803
10804 if (Rn == 15)
10805 {
10806 func (stream, "\t; ");
10807 info->print_address_func (((pc + 4) & ~3) + offset, info);
10808 }
10809 }
10810 skip:
10811 break;
10812
10813 case 'A':
10814 {
c1e26897
NC		 10815 unsigned int U = ! NEGATIVE_BIT_SET;
10816 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 10817 unsigned int Rn = (given & 0x000f0000) >> 16;
10818 unsigned int off = (given & 0x000000ff);
10819
10820 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 10821
10822 if (PRE_BIT_SET)
c19d1205
ZW		 10823 {
10824 if (off || !U)
05413229
NC		 10825 {
10826 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
fe50e98c 10827 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 10828 }
c19d1205
ZW		 10829 func (stream, "]");
10830 if (W)
10831 func (stream, "!");
10832 }
10833 else
10834 {
10835 func (stream, "], ");
10836 if (W)
05413229
NC		 10837 {
10838 func (stream, "#%c%u", U ? '+' : '-', off * 4);
fe50e98c 10839 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 10840 }
c19d1205 10841 else
fe56b6ce
NC		 10842 {
10843 func (stream, "{%u}", off);
10844 value_in_comment = off;
10845 }
c19d1205
ZW		 10846 }
10847 }
10848 break;
10849
10850 case 'w':
10851 {
10852 unsigned int Sbit = (given & 0x01000000) >> 24;
10853 unsigned int type = (given & 0x00600000) >> 21;
05413229 10854
c19d1205
ZW		 10855 switch (type)
10856 {
10857 case 0: func (stream, Sbit ? "sb" : "b"); break;
10858 case 1: func (stream, Sbit ? "sh" : "h"); break;
10859 case 2:
10860 if (Sbit)
10861 func (stream, "??");
10862 break;
10863 case 3:
10864 func (stream, "??");
10865 break;
10866 }
10867 }
10868 break;
10869
4b5a202f
AV		 10870 case 'n':
10871 is_clrm = TRUE;
10872 /* Fall through. */
c19d1205
ZW		 10873 case 'm':
10874 {
10875 int started = 0;
10876 int reg;
10877
10878 func (stream, "{");
10879 for (reg = 0; reg < 16; reg++)
10880 if ((given & (1 << reg)) != 0)
10881 {
10882 if (started)
10883 func (stream, ", ");
10884 started = 1;
4b5a202f
AV		 10885 if (is_clrm && reg == 13)
10886 func (stream, "(invalid: %s)", arm_regnames[reg]);
10887 else if (is_clrm && reg == 15)
10888 func (stream, "%s", "APSR");
10889 else
10890 func (stream, "%s", arm_regnames[reg]);
c19d1205
ZW		 10891 }
10892 func (stream, "}");
10893 }
10894 break;
10895
10896 case 'E':
10897 {
10898 unsigned int msb = (given & 0x0000001f);
10899 unsigned int lsb = 0;
fe56b6ce 10900
c19d1205
ZW		 10901 lsb |= (given & 0x000000c0u) >> 6;
10902 lsb |= (given & 0x00007000u) >> 10;
10903 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
10904 }
10905 break;
10906
10907 case 'F':
10908 {
10909 unsigned int width = (given & 0x0000001f) + 1;
10910 unsigned int lsb = 0;
fe56b6ce 10911
c19d1205
ZW		 10912 lsb |= (given & 0x000000c0u) >> 6;
10913 lsb |= (given & 0x00007000u) >> 10;
10914 func (stream, "#%u, #%u", lsb, width);
10915 }
10916 break;
10917
e12437dc
AV		 10918 case 'G':
10919 {
10920 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
10921 func (stream, "%x", boff);
10922 }
10923 break;
10924
e5d6e09e
AV		 10925 case 'W':
10926 {
10927 unsigned int immA = (given & 0x001f0000u) >> 16;
10928 unsigned int immB = (given & 0x000007feu) >> 1;
10929 unsigned int immC = (given & 0x00000800u) >> 11;
10930 bfd_vma offset = 0;
10931
10932 offset |= immA << 12;
10933 offset |= immB << 2;
10934 offset |= immC << 1;
10935 /* Sign extend. */
10936 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
10937
10938 info->print_address_func (pc + 4 + offset, info);
10939 }
10940 break;
10941
1caf72a5
AV		 10942 case 'Y':
10943 {
10944 unsigned int immA = (given & 0x007f0000u) >> 16;
10945 unsigned int immB = (given & 0x000007feu) >> 1;
10946 unsigned int immC = (given & 0x00000800u) >> 11;
10947 bfd_vma offset = 0;
10948
10949 offset |= immA << 12;
10950 offset |= immB << 2;
10951 offset |= immC << 1;
10952 /* Sign extend. */
10953 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
10954
10955 info->print_address_func (pc + 4 + offset, info);
10956 }
10957 break;
10958
1889da70
AV		 10959 case 'Z':
10960 {
10961 unsigned int immA = (given & 0x00010000u) >> 16;
10962 unsigned int immB = (given & 0x000007feu) >> 1;
10963 unsigned int immC = (given & 0x00000800u) >> 11;
10964 bfd_vma offset = 0;
10965
10966 offset |= immA << 12;
10967 offset |= immB << 2;
10968 offset |= immC << 1;
10969 /* Sign extend. */
10970 offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
10971
10972 info->print_address_func (pc + 4 + offset, info);
f6b2b12d
AV		 10973
10974 unsigned int T = (given & 0x00020000u) >> 17;
10975 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
10976 unsigned int boffset = (T == 1) ? 4 : 2;
10977 func (stream, ", ");
10978 func (stream, "%x", endoffset + boffset);
1889da70
AV		 10979 }
10980 break;
10981
60f993ce
AV		 10982 case 'Q':
10983 {
10984 unsigned int immh = (given & 0x000007feu) >> 1;
10985 unsigned int imml = (given & 0x00000800u) >> 11;
10986 bfd_vma imm32 = 0;
10987
10988 imm32 |= immh << 2;
10989 imm32 |= imml << 1;
10990
10991 info->print_address_func (pc + 4 + imm32, info);
10992 }
10993 break;
10994
10995 case 'P':
10996 {
10997 unsigned int immh = (given & 0x000007feu) >> 1;
10998 unsigned int imml = (given & 0x00000800u) >> 11;
10999 bfd_vma imm32 = 0;
11000
11001 imm32 |= immh << 2;
11002 imm32 |= imml << 1;
11003
11004 info->print_address_func (pc + 4 - imm32, info);
11005 }
11006 break;
11007
c19d1205
ZW		 11008 case 'b':
11009 {
11010 unsigned int S = (given & 0x04000000u) >> 26;
11011 unsigned int J1 = (given & 0x00002000u) >> 13;
11012 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 11013 bfd_vma offset = 0;
c19d1205
ZW		 11014
11015 offset |= !S << 20;
11016 offset |= J2 << 19;
11017 offset |= J1 << 18;
11018 offset |= (given & 0x003f0000) >> 4;
11019 offset |= (given & 0x000007ff) << 1;
11020 offset -= (1 << 20);
11021
11022 info->print_address_func (pc + 4 + offset, info);
11023 }
11024 break;
11025
11026 case 'B':
11027 {
11028 unsigned int S = (given & 0x04000000u) >> 26;
11029 unsigned int I1 = (given & 0x00002000u) >> 13;
11030 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 11031 bfd_vma offset = 0;
c19d1205
ZW		 11032
11033 offset |= !S << 24;
11034 offset |= !(I1 ^ S) << 23;
11035 offset |= !(I2 ^ S) << 22;
11036 offset |= (given & 0x03ff0000u) >> 4;
11037 offset |= (given & 0x000007ffu) << 1;
11038 offset -= (1 << 24);
36b0c57d 11039 offset += pc + 4;
c19d1205 11040
36b0c57d
PB		 11041 /* BLX target addresses are always word aligned. */
11042 if ((given & 0x00001000u) == 0)
11043 offset &= ~2u;
11044
11045 info->print_address_func (offset, info);
c19d1205
ZW		 11046 }
11047 break;
11048
11049 case 's':
11050 {
11051 unsigned int shift = 0;
fe56b6ce 11052
c19d1205
ZW		 11053 shift |= (given & 0x000000c0u) >> 6;
11054 shift |= (given & 0x00007000u) >> 10;
c1e26897 11055 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 11056 func (stream, ", asr #%u", shift);
11057 else if (shift)
11058 func (stream, ", lsl #%u", shift);
11059 /* else print nothing - lsl #0 */
11060 }
11061 break;
11062
11063 case 'R':
11064 {
11065 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 11066
c19d1205
ZW		 11067 if (rot)
11068 func (stream, ", ror #%u", rot * 8);
11069 }
11070 break;
11071
62b3e311 11072 case 'U':
43e65147 11073 if ((given & 0xf0) == 0x60)
62b3e311 11074 {
52e7f43d
RE		 11075 switch (given & 0xf)
11076 {
11077 case 0xf: func (stream, "sy"); break;
11078 default:
11079 func (stream, "#%d", (int) given & 0xf);
11080 break;
11081 }
62b3e311 11082 }
43e65147 11083 else
52e7f43d 11084 {
e797f7e0
MGD		 11085 const char * opt = data_barrier_option (given & 0xf);
11086 if (opt != NULL)
11087 func (stream, "%s", opt);
11088 else
11089 func (stream, "#%d", (int) given & 0xf);
52e7f43d 11090 }
62b3e311
PB		 11091 break;
11092
11093 case 'C':
11094 if ((given & 0xff) == 0)
11095 {
11096 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
11097 if (given & 0x800)
11098 func (stream, "f");
11099 if (given & 0x400)
11100 func (stream, "s");
11101 if (given & 0x200)
11102 func (stream, "x");
11103 if (given & 0x100)
11104 func (stream, "c");
11105 }
90ec0d68
MGD		 11106 else if ((given & 0x20) == 0x20)
11107 {
11108 char const* name;
11109 unsigned sysm = (given & 0xf00) >> 8;
11110
11111 sysm |= (given & 0x30);
11112 sysm |= (given & 0x00100000) >> 14;
11113 name = banked_regname (sysm);
43e65147 11114
90ec0d68
MGD		 11115 if (name != NULL)
11116 func (stream, "%s", name);
11117 else
d908c8af 11118 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 11119 }
62b3e311
PB		 11120 else
11121 {
d908c8af 11122 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 11123 }
11124 break;
11125
11126 case 'D':
90ec0d68
MGD		 11127 if (((given & 0xff) == 0)
11128 || ((given & 0x20) == 0x20))
11129 {
11130 char const* name;
11131 unsigned sm = (given & 0xf0000) >> 16;
11132
11133 sm |= (given & 0x30);
11134 sm |= (given & 0x00100000) >> 14;
11135 name = banked_regname (sm);
11136
11137 if (name != NULL)
11138 func (stream, "%s", name);
11139 else
d908c8af 11140 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 11141 }
62b3e311 11142 else
d908c8af 11143 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 11144 break;
11145
c19d1205
ZW		 11146 case '0': case '1': case '2': case '3': case '4':
11147 case '5': case '6': case '7': case '8': case '9':
11148 {
16980d0b
JB		 11149 int width;
11150 unsigned long val;
c19d1205 11151
16980d0b 11152 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 11153
c19d1205
ZW		 11154 switch (*c)
11155 {
d052b9b7
AV		 11156 case 's':
11157 if (val <= 3)
11158 func (stream, "%s", mve_vec_sizename[val]);
11159 else
11160 func (stream, "<undef size>");
11161 break;
11162
05413229
NC		 11163 case 'd':
11164 func (stream, "%lu", val);
11165 value_in_comment = val;
11166 break;
ff4a8d2b 11167
f0fba320
RL		 11168 case 'D':
11169 func (stream, "%lu", val + 1);
11170 value_in_comment = val + 1;
11171 break;
11172
05413229
NC		 11173 case 'W':
11174 func (stream, "%lu", val * 4);
11175 value_in_comment = val * 4;
11176 break;
ff4a8d2b 11177
f1c7f421
AV		 11178 case 'S':
11179 if (val == 13)
11180 is_unpredictable = TRUE;
11181 /* Fall through. */
ff4a8d2b
NC		 11182 case 'R':
11183 if (val == 15)
11184 is_unpredictable = TRUE;
11185 /* Fall through. */
11186 case 'r':
11187 func (stream, "%s", arm_regnames[val]);
11188 break;
c19d1205
ZW		 11189
11190 case 'c':
c22aaad1 11191 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 11192 break;
11193
11194 case '\'':
c19d1205 11195 c++;
16980d0b
JB		 11196 if (val == ((1ul << width) - 1))
11197 func (stream, "%c", *c);
c19d1205 11198 break;
43e65147 11199
c19d1205 11200 case '`':
c19d1205 11201 c++;
16980d0b
JB		 11202 if (val == 0)
11203 func (stream, "%c", *c);
c19d1205
ZW		 11204 break;
11205
11206 case '?':
fe56b6ce 11207 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 11208 c += 1 << width;
c19d1205 11209 break;
43e65147 11210
0bb027fd
RR		 11211 case 'x':
11212 func (stream, "0x%lx", val & 0xffffffffUL);
11213 break;
c19d1205
ZW		 11214
11215 default:
11216 abort ();
11217 }
11218 }
11219 break;
11220
32a94698
NC		 11221 case 'L':
11222 /* PR binutils/12534
11223 If we have a PC relative offset in an LDRD or STRD
11224 instructions then display the decoded address. */
11225 if (((given >> 16) & 0xf) == 0xf)
11226 {
11227 bfd_vma offset = (given & 0xff) * 4;
11228
11229 if ((given & (1 << 23)) == 0)
11230 offset = - offset;
11231 func (stream, "\t; ");
11232 info->print_address_func ((pc & ~3) + 4 + offset, info);
11233 }
11234 break;
11235
c19d1205
ZW		 11236 default:
11237 abort ();
11238 }
11239 }
05413229
NC		 11240
11241 if (value_in_comment > 32 || value_in_comment < -16)
11242 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 11243
11244 if (is_unpredictable)
11245 func (stream, UNPREDICTABLE_INSTRUCTION);
11246
4a5329c6 11247 return;
c19d1205 11248 }
252b5132 11249
58efb6c0 11250 /* No match. */
0b347048
TC		 11251 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
11252 return;
252b5132
RH		 11253}
11254
e821645d
DJ		 11255/* Print data bytes on INFO->STREAM. */
11256
11257static void
fe56b6ce
NC		 11258print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
11259 struct disassemble_info *info,
e821645d
DJ		 11260 long given)
11261{
11262 switch (info->bytes_per_chunk)
11263 {
11264 case 1:
11265 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
11266 break;
11267 case 2:
11268 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
11269 break;
11270 case 4:
11271 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
11272 break;
11273 default:
11274 abort ();
11275 }
11276}
11277
22a398e1 11278/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 11279 being displayed in symbol relative addresses.
11280
11281 Also disallow private symbol, with __tagsym$$ prefix,
11282 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 11283
11284bfd_boolean
11285arm_symbol_is_valid (asymbol * sym,
11286 struct disassemble_info * info ATTRIBUTE_UNUSED)
11287{
11288 const char * name;
43e65147 11289
22a398e1
NC		 11290 if (sym == NULL)
11291 return FALSE;
11292
11293 name = bfd_asymbol_name (sym);
11294
d8282f0e 11295 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 11296}
11297
65b48a81 11298/* Parse the string of disassembler options. */
baf0cc5e 11299
65b48a81 11300static void
f995bbe8 11301parse_arm_disassembler_options (const char *options)
dd92f639 11302{
f995bbe8 11303 const char *opt;
b34976b6 11304
65b48a81 11305 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
dd92f639 11306 {
65b48a81
PB		 11307 if (CONST_STRNEQ (opt, "reg-names-"))
11308 {
11309 unsigned int i;
11310 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11311 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
11312 {
11313 regname_selected = i;
11314 break;
11315 }
b34976b6 11316
65b48a81 11317 if (i >= NUM_ARM_OPTIONS)
a6743a54
AM		 11318 /* xgettext: c-format */
11319 opcodes_error_handler (_("unrecognised register name set: %s"),
11320 opt);
65b48a81
PB		 11321 }
11322 else if (CONST_STRNEQ (opt, "force-thumb"))
11323 force_thumb = 1;
11324 else if (CONST_STRNEQ (opt, "no-force-thumb"))
11325 force_thumb = 0;
11326 else
a6743a54
AM		 11327 /* xgettext: c-format */
11328 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
dd92f639 11329 }
b34976b6 11330
dd92f639
NC		 11331 return;
11332}
11333
5bc5ae88
RL		 11334static bfd_boolean
11335mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11336 enum map_type *map_symbol);
11337
c22aaad1
PB		 11338/* Search back through the insn stream to determine if this instruction is
11339 conditionally executed. */
fe56b6ce 11340
c22aaad1 11341static void
fe56b6ce
NC		 11342find_ifthen_state (bfd_vma pc,
11343 struct disassemble_info *info,
c22aaad1
PB		 11344 bfd_boolean little)
11345{
11346 unsigned char b[2];
11347 unsigned int insn;
11348 int status;
11349 /* COUNT is twice the number of instructions seen. It will be odd if we
11350 just crossed an instruction boundary. */
11351 int count;
11352 int it_count;
11353 unsigned int seen_it;
11354 bfd_vma addr;
11355
11356 ifthen_address = pc;
11357 ifthen_state = 0;
11358
11359 addr = pc;
11360 count = 1;
11361 it_count = 0;
11362 seen_it = 0;
11363 /* Scan backwards looking for IT instructions, keeping track of where
11364 instruction boundaries are. We don't know if something is actually an
11365 IT instruction until we find a definite instruction boundary. */
11366 for (;;)
11367 {
fe56b6ce 11368 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 11369 {
11370 /* A symbol must be on an instruction boundary, and will not
11371 be within an IT block. */
11372 if (seen_it && (count & 1))
11373 break;
11374
11375 return;
11376 }
11377 addr -= 2;
fe56b6ce 11378 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 11379 if (status)
11380 return;
11381
11382 if (little)
11383 insn = (b[0]) | (b[1] << 8);
11384 else
11385 insn = (b[1]) | (b[0] << 8);
11386 if (seen_it)
11387 {
11388 if ((insn & 0xf800) < 0xe800)
11389 {
11390 /* Addr + 2 is an instruction boundary. See if this matches
11391 the expected boundary based on the position of the last
11392 IT candidate. */
11393 if (count & 1)
11394 break;
11395 seen_it = 0;
11396 }
11397 }
11398 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
11399 {
5bc5ae88
RL		 11400 enum map_type type = MAP_ARM;
11401 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
11402
11403 if (!found || (found && type == MAP_THUMB))
11404 {
11405 /* This could be an IT instruction. */
11406 seen_it = insn;
11407 it_count = count >> 1;
11408 }
c22aaad1
PB		 11409 }
11410 if ((insn & 0xf800) >= 0xe800)
11411 count++;
11412 else
11413 count = (count + 2) | 1;
11414 /* IT blocks contain at most 4 instructions. */
11415 if (count >= 8 && !seen_it)
11416 return;
11417 }
11418 /* We found an IT instruction. */
11419 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
11420 if ((ifthen_state & 0xf) == 0)
11421 ifthen_state = 0;
11422}
11423
b0e28b39
DJ		 11424/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
11425 mapping symbol. */
11426
11427static int
11428is_mapping_symbol (struct disassemble_info *info, int n,
11429 enum map_type *map_type)
11430{
11431 const char *name;
11432
11433 name = bfd_asymbol_name (info->symtab[n]);
11434 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
11435 && (name[2] == 0 || name[2] == '.'))
11436 {
11437 *map_type = ((name[1] == 'a') ? MAP_ARM
11438 : (name[1] == 't') ? MAP_THUMB
11439 : MAP_DATA);
11440 return TRUE;
11441 }
11442
11443 return FALSE;
11444}
11445
11446/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
11447 Returns nonzero if *MAP_TYPE was set. */
11448
11449static int
11450get_map_sym_type (struct disassemble_info *info,
11451 int n,
11452 enum map_type *map_type)
11453{
11454 /* If the symbol is in a different section, ignore it. */
11455 if (info->section != NULL && info->section != info->symtab[n]->section)
11456 return FALSE;
11457
11458 return is_mapping_symbol (info, n, map_type);
11459}
11460
11461/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 11462 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 11463
11464static int
fe56b6ce
NC		 11465get_sym_code_type (struct disassemble_info *info,
11466 int n,
e821645d 11467 enum map_type *map_type)
2087ad84
PB		 11468{
11469 elf_symbol_type *es;
11470 unsigned int type;
b0e28b39
DJ		 11471
11472 /* If the symbol is in a different section, ignore it. */
11473 if (info->section != NULL && info->section != info->symtab[n]->section)
11474 return FALSE;
2087ad84 11475
e821645d 11476 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 11477 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
11478
11479 /* If the symbol has function type then use that. */
34e77a92 11480 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 11481 {
39d911fc
TP		 11482 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
11483 == ST_BRANCH_TO_THUMB)
35fc36a8
RS		 11484 *map_type = MAP_THUMB;
11485 else
11486 *map_type = MAP_ARM;
2087ad84
PB		 11487 return TRUE;
11488 }
11489
2087ad84
PB		 11490 return FALSE;
11491}
11492
5bc5ae88
RL		 11493/* Search the mapping symbol state for instruction at pc. This is only
11494 applicable for elf target.
11495
11496 There is an assumption Here, info->private_data contains the correct AND
11497 up-to-date information about current scan process. The information will be
11498 used to speed this search process.
11499
11500 Return TRUE if the mapping state can be determined, and map_symbol
11501 will be updated accordingly. Otherwise, return FALSE. */
11502
11503static bfd_boolean
11504mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11505 enum map_type *map_symbol)
11506{
796d6298
TC		 11507 bfd_vma addr, section_vma = 0;
11508 int n, last_sym = -1;
5bc5ae88 11509 bfd_boolean found = FALSE;
796d6298
TC		 11510 bfd_boolean can_use_search_opt_p = FALSE;
11511
11512 /* Default to DATA. A text section is required by the ABI to contain an
11513 INSN mapping symbol at the start. A data section has no such
11514 requirement, hence if no mapping symbol is found the section must
11515 contain only data. This however isn't very useful if the user has
11516 fully stripped the binaries. If this is the case use the section
11517 attributes to determine the default. If we have no section default to
11518 INSN as well, as we may be disassembling some raw bytes on a baremetal
11519 HEX file or similar. */
11520 enum map_type type = MAP_DATA;
11521 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
11522 type = MAP_ARM;
5bc5ae88
RL		 11523 struct arm_private_data *private_data;
11524
796d6298 11525 if (info->private_data == NULL
5bc5ae88
RL		 11526 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
11527 return FALSE;
11528
11529 private_data = info->private_data;
5bc5ae88 11530
796d6298
TC		 11531 /* First, look for mapping symbols. */
11532 if (info->symtab_size != 0)
11533 {
11534 if (pc <= private_data->last_mapping_addr)
11535 private_data->last_mapping_sym = -1;
11536
11537 /* Start scanning at the start of the function, or wherever
11538 we finished last time. */
11539 n = info->symtab_pos + 1;
11540
11541 /* If the last stop offset is different from the current one it means we
11542 are disassembling a different glob of bytes. As such the optimization
11543 would not be safe and we should start over. */
11544 can_use_search_opt_p
11545 = private_data->last_mapping_sym >= 0
11546 && info->stop_offset == private_data->last_stop_offset;
11547
11548 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11549 n = private_data->last_mapping_sym;
11550
11551 /* Look down while we haven't passed the location being disassembled.
11552 The reason for this is that there's no defined order between a symbol
11553 and an mapping symbol that may be at the same address. We may have to
11554 look at least one position ahead. */
11555 for (; n < info->symtab_size; n++)
11556 {
11557 addr = bfd_asymbol_value (info->symtab[n]);
11558 if (addr > pc)
11559 break;
11560 if (get_map_sym_type (info, n, &type))
11561 {
11562 last_sym = n;
11563 found = TRUE;
11564 }
11565 }
5bc5ae88 11566
796d6298
TC		 11567 if (!found)
11568 {
11569 n = info->symtab_pos;
11570 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11571 n = private_data->last_mapping_sym;
11572
11573 /* No mapping symbol found at this address. Look backwards
11574 for a preceeding one, but don't go pass the section start
11575 otherwise a data section with no mapping symbol can pick up
11576 a text mapping symbol of a preceeding section. The documentation
11577 says section can be NULL, in which case we will seek up all the
11578 way to the top. */
11579 if (info->section)
11580 section_vma = info->section->vma;
11581
11582 for (; n >= 0; n--)
11583 {
11584 addr = bfd_asymbol_value (info->symtab[n]);
11585 if (addr < section_vma)
11586 break;
11587
11588 if (get_map_sym_type (info, n, &type))
11589 {
11590 last_sym = n;
11591 found = TRUE;
11592 break;
11593 }
11594 }
11595 }
11596 }
11597
11598 /* If no mapping symbol was found, try looking up without a mapping
11599 symbol. This is done by walking up from the current PC to the nearest
11600 symbol. We don't actually have to loop here since symtab_pos will
11601 contain the nearest symbol already. */
11602 if (!found)
5bc5ae88 11603 {
796d6298
TC		 11604 n = info->symtab_pos;
11605 if (n >= 0 && get_sym_code_type (info, n, &type))
5bc5ae88 11606 {
796d6298
TC		 11607 last_sym = n;
11608 found = TRUE;
5bc5ae88
RL		 11609 }
11610 }
11611
796d6298
TC		 11612 private_data->last_mapping_sym = last_sym;
11613 private_data->last_type = type;
11614 private_data->last_stop_offset = info->stop_offset;
5bc5ae88
RL		 11615
11616 *map_symbol = type;
11617 return found;
11618}
11619
0313a2b8
NC		 11620/* Given a bfd_mach_arm_XXX value, this function fills in the fields
11621 of the supplied arm_feature_set structure with bitmasks indicating
c0c468d5 11622 the supported base architectures and coprocessor extensions.
0313a2b8
NC		 11623
11624 FIXME: This could more efficiently implemented as a constant array,
11625 although it would also be less robust. */
11626
11627static void
11628select_arm_features (unsigned long mach,
11629 arm_feature_set * features)
11630{
c0c468d5
TP		 11631 arm_feature_set arch_fset;
11632 const arm_feature_set fpu_any = FPU_ANY;
11633
1af1dd51
MW		 11634#undef ARM_SET_FEATURES
11635#define ARM_SET_FEATURES(FSET) \
11636 { \
11637 const arm_feature_set fset = FSET; \
c0c468d5 11638 arch_fset = fset; \
1af1dd51 11639 }
823d2571 11640
c0c468d5
TP		 11641 /* When several architecture versions share the same bfd_mach_arm_XXX value
11642 the most featureful is chosen. */
0313a2b8
NC		 11643 switch (mach)
11644 {
c0c468d5
TP		 11645 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
11646 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
11647 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
11648 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
11649 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
11650 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
11651 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
11652 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
11653 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
11654 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
1af1dd51 11655 case bfd_mach_arm_ep9312:
c0c468d5
TP		 11656 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
11657 ARM_CEXT_MAVERICK | FPU_MAVERICK));
1af1dd51 11658 break;
c0c468d5
TP		 11659 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
11660 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
11661 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
11662 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
11663 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
11664 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
11665 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
11666 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
11667 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
11668 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
11669 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
11670 case bfd_mach_arm_8:
11671 {
aab2c27d
MM		 11672 /* Add bits for extensions that Armv8.6-A recognizes. */
11673 arm_feature_set armv8_6_ext_fset
0632eeea 11674 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
aab2c27d
MM		 11675 ARM_SET_FEATURES (ARM_ARCH_V8_6A);
11676 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_6_ext_fset);
c0c468d5
TP		 11677 break;
11678 }
11679 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
11680 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
11681 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
73cd51e5
AV		 11682 case bfd_mach_arm_8_1M_MAIN:
11683 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
11684 force_thumb = 1;
11685 break;
c0c468d5
TP		 11686 /* If the machine type is unknown allow all architecture types and all
11687 extensions. */
11688 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
0313a2b8
NC		 11689 default:
11690 abort ();
11691 }
1af1dd51 11692#undef ARM_SET_FEATURES
c0c468d5
TP		 11693
11694 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
11695 and thus on bfd_mach_arm_XXX value. Therefore for a given
11696 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
11697 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
0313a2b8
NC		 11698}
11699
11700
58efb6c0
NC		 11701/* NOTE: There are no checks in these routines that
11702 the relevant number of data bytes exist. */
baf0cc5e 11703
58efb6c0 11704static int
4a5329c6 11705print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 11706{
c19d1205 11707 unsigned char b[4];
2480b6fa 11708 unsigned long given;
c19d1205 11709 int status;
e821645d 11710 int is_thumb = FALSE;
b0e28b39 11711 int is_data = FALSE;
bd2e2557 11712 int little_code;
e821645d 11713 unsigned int size = 4;
4a5329c6 11714 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 11715 bfd_boolean found = FALSE;
b0e28b39 11716 struct arm_private_data *private_data;
58efb6c0 11717
dd92f639
NC		 11718 if (info->disassembler_options)
11719 {
65b48a81 11720 parse_arm_disassembler_options (info->disassembler_options);
b34976b6 11721
58efb6c0 11722 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 11723 info->disassembler_options = NULL;
11724 }
b34976b6 11725
0313a2b8
NC		 11726 /* PR 10288: Control which instructions will be disassembled. */
11727 if (info->private_data == NULL)
11728 {
b0e28b39 11729 static struct arm_private_data private;
0313a2b8
NC		 11730
11731 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
11732 /* If the user did not use the -m command line switch then default to
11733 disassembling all types of ARM instruction.
43e65147 11734
0313a2b8
NC		 11735 The info->mach value has to be ignored as this will be based on
11736 the default archictecture for the target and/or hints in the notes
11737 section, but it will never be greater than the current largest arm
11738 machine value (iWMMXt2), which is only equivalent to the V5TE
11739 architecture. ARM architectures have advanced beyond the machine
11740 value encoding, and these newer architectures would be ignored if
11741 the machine value was used.
11742
11743 Ie the -m switch is used to restrict which instructions will be
11744 disassembled. If it is necessary to use the -m switch to tell
11745 objdump that an ARM binary is being disassembled, eg because the
11746 input is a raw binary file, but it is also desired to disassemble
11747 all ARM instructions then use "-marm". This will select the
11748 "unknown" arm architecture which is compatible with any ARM
11749 instruction. */
11750 info->mach = bfd_mach_arm_unknown;
11751
11752 /* Compute the architecture bitmask from the machine number.
11753 Note: This assumes that the machine number will not change
11754 during disassembly.... */
b0e28b39 11755 select_arm_features (info->mach, & private.features);
0313a2b8 11756
1fbaefec
PB		 11757 private.last_mapping_sym = -1;
11758 private.last_mapping_addr = 0;
796d6298 11759 private.last_stop_offset = 0;
b0e28b39
DJ		 11760
11761 info->private_data = & private;
0313a2b8 11762 }
b0e28b39
DJ		 11763
11764 private_data = info->private_data;
11765
bd2e2557
SS		 11766 /* Decide if our code is going to be little-endian, despite what the
11767 function argument might say. */
11768 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
11769
b0e28b39
DJ		 11770 /* For ELF, consult the symbol table to determine what kind of code
11771 or data we have. */
8977d4b2 11772 if (info->symtab_size != 0
e821645d
DJ		 11773 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
11774 {
11775 bfd_vma addr;
796d6298 11776 int n;
e821645d 11777 int last_sym = -1;
b0e28b39 11778 enum map_type type = MAP_ARM;
e821645d 11779
796d6298
TC		 11780 found = mapping_symbol_for_insn (pc, info, &type);
11781 last_sym = private_data->last_mapping_sym;
e821645d 11782
1fbaefec
PB		 11783 is_thumb = (private_data->last_type == MAP_THUMB);
11784 is_data = (private_data->last_type == MAP_DATA);
b34976b6 11785
e821645d
DJ		 11786 /* Look a little bit ahead to see if we should print out
11787 two or four bytes of data. If there's a symbol,
11788 mapping or otherwise, after two bytes then don't
11789 print more. */
11790 if (is_data)
11791 {
11792 size = 4 - (pc & 3);
11793 for (n = last_sym + 1; n < info->symtab_size; n++)
11794 {
11795 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 11796 if (addr > pc
11797 && (info->section == NULL
11798 || info->section == info->symtab[n]->section))
e821645d
DJ		 11799 {
11800 if (addr - pc < size)
11801 size = addr - pc;
11802 break;
11803 }
11804 }
11805 /* If the next symbol is after three bytes, we need to
11806 print only part of the data, so that we can use either
11807 .byte or .short. */
11808 if (size == 3)
11809 size = (pc & 1) ? 1 : 2;
11810 }
11811 }
11812
11813 if (info->symbols != NULL)
252b5132 11814 {
5876e06d
NC		 11815 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
11816 {
2f0ca46a 11817 coff_symbol_type * cs;
b34976b6 11818
5876e06d
NC		 11819 cs = coffsymbol (*info->symbols);
11820 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
11821 || cs->native->u.syment.n_sclass == C_THUMBSTAT
11822 || cs->native->u.syment.n_sclass == C_THUMBLABEL
11823 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
11824 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
11825 }
e821645d
DJ		 11826 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
11827 && !found)
5876e06d 11828 {
2087ad84
PB		 11829 /* If no mapping symbol has been found then fall back to the type
11830 of the function symbol. */
e821645d
DJ		 11831 elf_symbol_type * es;
11832 unsigned int type;
2087ad84 11833
e821645d
DJ		 11834 es = *(elf_symbol_type **)(info->symbols);
11835 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 11836
39d911fc
TP		 11837 is_thumb =
11838 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
11839 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
5876e06d 11840 }
e49d43ff
TG		 11841 else if (bfd_asymbol_flavour (*info->symbols)
11842 == bfd_target_mach_o_flavour)
11843 {
11844 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
11845
11846 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
11847 }
5876e06d 11848 }
b34976b6 11849
e821645d
DJ		 11850 if (force_thumb)
11851 is_thumb = TRUE;
11852
b8f9ee44
CL		 11853 if (is_data)
11854 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
11855 else
11856 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
11857
c19d1205 11858 info->bytes_per_line = 4;
252b5132 11859
1316c8b3
NC		 11860 /* PR 10263: Disassemble data if requested to do so by the user. */
11861 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 11862 {
11863 int i;
11864
1316c8b3 11865 /* Size was already set above. */
e821645d
DJ		 11866 info->bytes_per_chunk = size;
11867 printer = print_insn_data;
11868
fe56b6ce 11869 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 11870 given = 0;
11871 if (little)
11872 for (i = size - 1; i >= 0; i--)
11873 given = b[i] | (given << 8);
11874 else
11875 for (i = 0; i < (int) size; i++)
11876 given = b[i] | (given << 8);
11877 }
11878 else if (!is_thumb)
252b5132 11879 {
c19d1205
ZW		 11880 /* In ARM mode endianness is a straightforward issue: the instruction
11881 is four bytes long and is either ordered 0123 or 3210. */
11882 printer = print_insn_arm;
11883 info->bytes_per_chunk = 4;
4a5329c6 11884 size = 4;
c19d1205 11885
0313a2b8 11886 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 11887 if (little_code)
2480b6fa 11888 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | ((unsigned) b[3] << 24);
c19d1205 11889 else
2480b6fa 11890 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | ((unsigned) b[0] << 24);
252b5132 11891 }
58efb6c0 11892 else
252b5132 11893 {
c19d1205
ZW		 11894 /* In Thumb mode we have the additional wrinkle of two
11895 instruction lengths. Fortunately, the bits that determine
11896 the length of the current instruction are always to be found
11897 in the first two bytes. */
4a5329c6 11898 printer = print_insn_thumb16;
c19d1205 11899 info->bytes_per_chunk = 2;
4a5329c6
ZW		 11900 size = 2;
11901
fe56b6ce 11902 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 11903 if (little_code)
9a2ff3f5
AM		 11904 given = (b[0]) | (b[1] << 8);
11905 else
11906 given = (b[1]) | (b[0] << 8);
11907
c19d1205 11908 if (!status)
252b5132 11909 {
c19d1205
ZW		 11910 /* These bit patterns signal a four-byte Thumb
11911 instruction. */
11912 if ((given & 0xF800) == 0xF800
11913 || (given & 0xF800) == 0xF000
11914 || (given & 0xF800) == 0xE800)
252b5132 11915 {
0313a2b8 11916 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 11917 if (little_code)
c19d1205 11918 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 11919 else
c19d1205
ZW		 11920 given = (b[1]) | (b[0] << 8) | (given << 16);
11921
11922 printer = print_insn_thumb32;
4a5329c6 11923 size = 4;
252b5132 11924 }
252b5132 11925 }
c22aaad1
PB		 11926
11927 if (ifthen_address != pc)
0313a2b8 11928 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 11929
11930 if (ifthen_state)
11931 {
11932 if ((ifthen_state & 0xf) == 0x8)
11933 ifthen_next_state = 0;
11934 else
11935 ifthen_next_state = (ifthen_state & 0xe0)
11936 | ((ifthen_state & 0xf) << 1);
11937 }
252b5132 11938 }
b34976b6 11939
c19d1205
ZW		 11940 if (status)
11941 {
11942 info->memory_error_func (status, pc, info);
11943 return -1;
11944 }
6a56ec7e
NC		 11945 if (info->flags & INSN_HAS_RELOC)
11946 /* If the instruction has a reloc associated with it, then
11947 the offset field in the instruction will actually be the
11948 addend for the reloc. (We are using REL type relocs).
11949 In such cases, we can ignore the pc when computing
11950 addresses, since the addend is not currently pc-relative. */
11951 pc = 0;
b34976b6 11952
4a5329c6 11953 printer (pc, info, given);
c22aaad1
PB		 11954
11955 if (is_thumb)
11956 {
11957 ifthen_state = ifthen_next_state;
11958 ifthen_address += size;
11959 }
4a5329c6 11960 return size;
252b5132
RH		 11961}
11962
11963int
4a5329c6 11964print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 11965{
bd2e2557
SS		 11966 /* Detect BE8-ness and record it in the disassembler info. */
11967 if (info->flavour == bfd_target_elf_flavour
11968 && info->section != NULL
11969 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
11970 info->endian_code = BFD_ENDIAN_LITTLE;
11971
b34976b6 11972 return print_insn (pc, info, FALSE);
58efb6c0 11973}
01c7f630 11974
58efb6c0 11975int
4a5329c6 11976print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 11977{
b34976b6 11978 return print_insn (pc, info, TRUE);
58efb6c0 11979}
252b5132 11980
471b9d15 11981const disasm_options_and_args_t *
65b48a81
PB		 11982disassembler_options_arm (void)
11983{
471b9d15 11984 static disasm_options_and_args_t *opts_and_args;
65b48a81 11985
471b9d15 11986 if (opts_and_args == NULL)
65b48a81 11987 {
471b9d15 11988 disasm_options_t *opts;
65b48a81 11989 unsigned int i;
471b9d15
MR		 11990
11991 opts_and_args = XNEW (disasm_options_and_args_t);
11992 opts_and_args->args = NULL;
11993
11994 opts = &opts_and_args->options;
65b48a81
PB		 11995 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
11996 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
471b9d15 11997 opts->arg = NULL;
65b48a81
PB		 11998 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11999 {
12000 opts->name[i] = regnames[i].name;
12001 if (regnames[i].description != NULL)
12002 opts->description[i] = _(regnames[i].description);
12003 else
12004 opts->description[i] = NULL;
12005 }
12006 /* The array we return must be NULL terminated. */
12007 opts->name[i] = NULL;
12008 opts->description[i] = NULL;
12009 }
12010
471b9d15 12011 return opts_and_args;
65b48a81
PB		 12012}
12013
58efb6c0 12014void
4a5329c6 12015print_arm_disassembler_options (FILE *stream)
58efb6c0 12016{
65b48a81 12017 unsigned int i, max_len = 0;
58efb6c0
NC		 12018 fprintf (stream, _("\n\
12019The following ARM specific disassembler options are supported for use with\n\
12020the -M switch:\n"));
b34976b6 12021
65b48a81
PB		 12022 for (i = 0; i < NUM_ARM_OPTIONS; i++)
12023 {
12024 unsigned int len = strlen (regnames[i].name);
12025 if (max_len < len)
12026 max_len = len;
12027 }
58efb6c0 12028
65b48a81
PB		 12029 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
12030 fprintf (stream, " %s%*c %s\n",
12031 regnames[i].name,
12032 (int)(max_len - strlen (regnames[i].name)), ' ',
12033 _(regnames[i].description));
252b5132 12034}
GDB Binutils - Deliverables
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