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[AArch64] Add ARMv8.3 pointer authentication key registers
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
CommitLineData
252b5132 1/* Instruction printing code for the ARM
6f2750fe 2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
2fbad815 24
252b5132 25#include "dis-asm.h"
2fbad815 26#include "opcode/arm.h"
252b5132 27#include "opintl.h"
31e0f3cd 28#include "safe-ctype.h"
0dbde4cf 29#include "floatformat.h"
252b5132 30
baf0cc5e 31/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 32#include "coff/internal.h"
33#include "libcoff.h"
252b5132
RH		 34#include "elf-bfd.h"
35#include "elf/internal.h"
36#include "elf/arm.h"
e49d43ff 37#include "mach-o.h"
252b5132 38
6b5d3a4d 39/* FIXME: Belongs in global header. */
01c7f630 40#ifndef strneq
58efb6c0
NC		 41#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
42#endif
43
44#ifndef NUM_ELEM
45#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
01c7f630
NC		 46#endif
47
1fbaefec
PB		 48/* Cached mapping symbol state. */
49enum map_type
50{
51 MAP_ARM,
52 MAP_THUMB,
53 MAP_DATA
54};
55
b0e28b39
DJ		 56struct arm_private_data
57{
58 /* The features to use when disassembling optional instructions. */
59 arm_feature_set features;
60
61 /* Whether any mapping symbols are present in the provided symbol
62 table. -1 if we do not know yet, otherwise 0 or 1. */
63 int has_mapping_symbols;
1fbaefec
PB		 64
65 /* Track the last type (although this doesn't seem to be useful) */
66 enum map_type last_type;
67
68 /* Tracking symbol table information */
69 int last_mapping_sym;
70 bfd_vma last_mapping_addr;
b0e28b39
DJ		 71};
72
6b5d3a4d
ZW		 73struct opcode32
74{
823d2571
TG		 75 arm_feature_set arch; /* Architecture defining this insn. */
76 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 77 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 78 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 79};
80
81struct opcode16
82{
823d2571 83 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 84 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 85 const char *assembler; /* How to disassemble this insn. */
86};
b7693d02 87
8f06b2d8 88/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 89
2fbad815 90 %% %
4a5329c6 91
c22aaad1 92 %c print condition code (always bits 28-31 in ARM mode)
37b37b2d 93 %q print shifter argument
e2efe87d
MGD		 94 %u print condition code (unconditional in ARM mode,
95 UNPREDICTABLE if not AL in Thumb)
4a5329c6 96 %A print address for ldc/stc/ldf/stf instruction
16980d0b 97 %B print vstm/vldm register list
4a5329c6 98 %I print cirrus signed shift immediate: bits 0..3|4..6
4a5329c6
ZW		 99 %F print the COUNT field of a LFM/SFM instruction.
100 %P print floating point precision in arithmetic insn
101 %Q print floating point precision in ldf/stf insn
102 %R print floating point rounding mode
103
33399f07 104 %<bitfield>c print as a condition code (for vsel)
4a5329c6 105 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 106 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
107 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 108 %<bitfield>d print the bitfield in decimal
16980d0b 109 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 110 %<bitfield>x print the bitfield in hex
111 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 112 %<bitfield>f print a floating point constant if >7 else a
113 floating point register
4a5329c6
ZW		 114 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
115 %<bitfield>g print as an iWMMXt 64-bit register
116 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 117 %<bitfield>D print as a NEON D register
118 %<bitfield>Q print as a NEON Q register
6f1c2142 119 %<bitfield>E print a quarter-float immediate value
4a5329c6 120
16980d0b 121 %y<code> print a single precision VFP reg.
2fbad815 122 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 123 %z<code> print a double precision VFP reg
2fbad815 124 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 125
16980d0b
JB		 126 %<bitfield>'c print specified char iff bitfield is all ones
127 %<bitfield>`c print specified char iff bitfield is all zeroes
128 %<bitfield>?ab... select from array of values in big endian order
43e65147 129
2fbad815 130 %L print as an iWMMXt N/M width field.
4a5329c6 131 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 132 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 133 versions.
134 %i print 5-bit immediate in bits 8,3..0
135 (print "32" when 0)
fe56b6ce 136 %r print register offset address for wldt/wstr instruction. */
2fbad815 137
21d799b5 138enum opcode_sentinel_enum
05413229
NC		 139{
140 SENTINEL_IWMMXT_START = 1,
141 SENTINEL_IWMMXT_END,
142 SENTINEL_GENERIC_START
143} opcode_sentinels;
144
aefd8a40 145#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
c1e26897 146#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 147
8f06b2d8 148/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 149
8f06b2d8 150static const struct opcode32 coprocessor_opcodes[] =
2fbad815 151{
2fbad815 152 /* XScale instructions. */
823d2571
TG		 153 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
154 0x0e200010, 0x0fff0ff0,
155 "mia%c\tacc0, %0-3r, %12-15r"},
156 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
157 0x0e280010, 0x0fff0ff0,
158 "miaph%c\tacc0, %0-3r, %12-15r"},
159 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
160 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
161 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
162 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
163 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
164 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 165
2fbad815 166 /* Intel Wireless MMX technology instructions. */
823d2571
TG		 167 {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
168 {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
169 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
170 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
171 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
172 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
173 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
174 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
175 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
176 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
177 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
178 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
179 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
180 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
181 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
182 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
183 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
184 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
185 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
186 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
187 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
188 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
189 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
190 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
191 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
192 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
193 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
194 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
195 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
196 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
197 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
198 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
199 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
200 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
201 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
202 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
203 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
204 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
205 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
206 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
207 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
208 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
209 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
210 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
211 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
212 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
213 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
214 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
215 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
216 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
217 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
218 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
219 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
220 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
221 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
222 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
223 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
224 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
225 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
226 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
227 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
228 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
229 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
230 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
231 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
232 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
233 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
234 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
235 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
236 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
237 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
238 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
239 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
240 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
241 0x0e800120, 0x0f800ff0,
242 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
243 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
244 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
245 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
246 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
247 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
248 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
249 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
250 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
251 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
252 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
253 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
254 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
255 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
256 0x0e8000a0, 0x0f800ff0,
257 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
258 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
259 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
260 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
261 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
262 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
263 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
264 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
265 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
266 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
267 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
268 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
269 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
270 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
271 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
272 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
273 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
274 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
275 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
276 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
277 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
278 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
279 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
280 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
281 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
282 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
283 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
284 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
285 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
286 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
287 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
288 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
289 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
290 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
291 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
292 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
293 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
294 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
295 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
296 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
297 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
298 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
299 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
300 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
301 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
302 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
303 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
304 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
305 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
306 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
307 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
308 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
309 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
310 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
311 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
312 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
313 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
314 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
315 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
316 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
317 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
318 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
319 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
320 {ARM_FEATURE_CORE_LOW (0),
321 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 322
fe56b6ce 323 /* Floating point coprocessor (FPA) instructions. */
823d2571
TG		 324 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
325 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
326 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
327 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
328 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
329 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
330 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
331 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
332 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
333 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
334 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
335 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
336 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
337 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
338 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
339 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
340 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
341 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
342 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
343 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
344 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
345 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
346 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
347 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
348 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
349 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
350 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
351 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
352 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
353 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
354 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
355 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
356 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
357 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
358 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
359 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
360 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
361 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
362 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
363 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
364 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
365 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
366 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
367 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
368 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
369 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
370 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
371 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
372 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
373 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
374 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
375 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
376 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
377 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
378 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
379 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
380 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
381 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
382 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
383 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
384 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
385 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
386 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
387 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
388 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
389 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
390 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
391 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
392 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
393 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
394 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
395 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
396 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
397 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
398 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
399 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
400 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
401 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
402 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
403 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
404 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
405 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
406 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
407 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
408 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
409 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 410
16a1fa25
TP		 411 /* ARMv8-M Mainline Security Extensions instructions. */
412 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
413 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
414 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
415 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
416
fe56b6ce 417 /* Register load/store. */
823d2571
TG		 418 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
419 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
420 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
421 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
422 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
423 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
424 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
425 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
426 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
427 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
428 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
429 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
430 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
431 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
432 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
433 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
434 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
435 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
436 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
437 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
438 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
439 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
440 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
441 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
442 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
443 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
444 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
445 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
446 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
447 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
448 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
449 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
450
451 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
452 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
453 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
454 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
455 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
456 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
457 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
458 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 459
fe56b6ce 460 /* Data transfer between ARM and NEON registers. */
823d2571
TG		 461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
462 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
464 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
466 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
468 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
470 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
472 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
474 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
476 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
478 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
480 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
482 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
484 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
486 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
487 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
488 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 489 /* Half-precision conversion instructions. */
823d2571
TG		 490 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
491 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
492 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
493 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
494 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
495 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
496 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
497 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 498
fe56b6ce 499 /* Floating point coprocessor (VFP) instructions. */
823d2571
TG		 500 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
501 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
502 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
503 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
504 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
505 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
506 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
507 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
508 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
509 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
510 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
511 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
512 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
513 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
514 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
515 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
516 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
517 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
518 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
519 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
520 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
521 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
522 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
523 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
524 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
525 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
526 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
527 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
528 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
529 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
530 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
531 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
532 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
533 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
534 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
535 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
536 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
537 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
538 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
539 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
540 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
541 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
542 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
543 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
544 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
545 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
546 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
547 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
548 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
549 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
550 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
551 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
552 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
553 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
554 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
555 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
556 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
557 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
558 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
559 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
560 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
561 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
562 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
563 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
564 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
565 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
566 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
567 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
568 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
569 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
570 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
571 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
572 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
573 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
574 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
575 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
576 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
577 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
578 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
579 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
580 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
581 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
582 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
583 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
584 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
585 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
586 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
587 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
588 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6f1c2142 589 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
823d2571 590 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6f1c2142 591 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
823d2571
TG		 592 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
593 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
594 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
595 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
596 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
597 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
598 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
599 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
600 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
601 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
602 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
603 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
604 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
605 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
606 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
607 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
608 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
609 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
610 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
611 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
612 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
613 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
614 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
615 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
616 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
617 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
618 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
619 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
620 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
621 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
622 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
623 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
624 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
625 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
626 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
627 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
628 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
629 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
630 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
631 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
632 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
633 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 634
635 /* Cirrus coprocessor instructions. */
823d2571
TG		 636 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
637 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
638 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
639 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
640 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
641 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
642 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
643 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
644 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
645 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
646 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
647 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
648 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
649 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
650 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
651 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
652 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
653 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
654 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
655 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
656 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
657 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
658 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
659 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
660 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
661 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
662 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
663 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
664 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
665 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
666 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
667 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
668 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
669 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
670 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
671 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
672 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
673 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
674 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
675 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
676 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
677 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
678 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
679 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
680 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
681 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
682 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
683 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
684 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
685 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
686 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
687 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
688 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
689 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
690 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
691 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
692 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
693 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
694 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
695 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
696 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
697 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
698 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
699 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
700 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
701 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
702 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
703 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
704 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
705 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
706 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
707 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
708 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
709 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
710 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
711 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
712 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
713 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
714 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
715 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
716 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
717 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
718 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
719 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
720 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
721 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
722 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
723 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
724 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
725 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
726 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
727 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
728 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
729 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
730 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
731 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
732 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
733 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
734 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
735 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
736 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
737 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
738 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
739 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
740 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
741 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
742 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
743 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
744 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
745 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
746 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
747 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
748 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
749 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
750 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
751 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
752 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
753 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
754 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
755 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
756 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
757 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
758 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
759 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
760 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
761 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
762 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
763 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
764 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
765 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
766 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
767 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
768 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
769 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
770 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
771 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
772 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
773 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
774 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
775 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
776 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
777 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
778 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
779 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
780 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
781 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
782 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
783 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
784 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
785 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
786 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
787 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
788 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
789 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
790 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
791 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
792 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
793 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
794 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
795 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
796 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
797 0x0e000600, 0x0ff00f10,
798 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
799 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
800 0x0e100600, 0x0ff00f10,
801 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
802 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
803 0x0e200600, 0x0ff00f10,
804 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
805 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
806 0x0e300600, 0x0ff00f10,
807 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 808
62f3b8c8 809 /* VFP Fused multiply add instructions. */
823d2571
TG		 810 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
811 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
812 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
813 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
814 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
815 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
816 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
817 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
818 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
819 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
820 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
821 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
822 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
824 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
825 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 826
33399f07 827 /* FP v5. */
823d2571 828 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 829 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
823d2571 830 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 831 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
823d2571 832 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 833 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
823d2571 834 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 835 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
823d2571 836 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 837 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
823d2571 838 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 839 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
823d2571
TG		 840 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
841 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
842 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
843 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
844 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
845 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
846 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
847 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
848 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 849 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
823d2571 850 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 851 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 852
05413229 853 /* Generic coprocessor instructions. */
823d2571
TG		 854 {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
856 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
858 0x0c500000, 0x0ff00000,
859 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
861 0x0e000000, 0x0f000010,
862 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
864 0x0e10f010, 0x0f10f010,
865 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
867 0x0e100010, 0x0f100010,
868 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
870 0x0e000010, 0x0f100010,
871 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
873 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
875 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
2fbad815 876
05413229 877 /* V6 coprocessor instructions. */
823d2571
TG		 878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
879 0xfc500000, 0xfff00000,
880 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
882 0xfc400000, 0xfff00000,
883 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
8f06b2d8 884
05413229 885 /* V5 coprocessor instructions. */
823d2571
TG		 886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
887 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
889 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
891 0xfe000000, 0xff000010,
892 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
894 0xfe000010, 0xff100010,
895 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
897 0xfe100010, 0xff100010,
898 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
899
b0c11777
RL		 900 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
901 cp_num: bit <11:8> == 0b1001.
902 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
903 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
904 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
905 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
906 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
907 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
908 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
909 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
910 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
911 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
912 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
913 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
914 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
915 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
916 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
917 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
918 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
919 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
920 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
921 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
922 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
923 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
924 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
925 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
926 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
927 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
928 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
929 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
930 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
931 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
932 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
933 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
934 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
935 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
936 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
937 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
938 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
939 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
940 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
941 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
942 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
943 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
944 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
945 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
946 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
947 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
948 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
949 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
950 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
951 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
952 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
953 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
954 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
955 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
956 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
957 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
958 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
959 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
960 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
961 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
962 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
963 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
964 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
965 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
966 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
967 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
968 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
969 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
970 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
971 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
972 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
973
823d2571 974 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 975};
976
16980d0b
JB		 977/* Neon opcode table: This does not encode the top byte -- that is
978 checked by the print_insn_neon routine, as it depends on whether we are
979 doing thumb32 or arm32 disassembly. */
980
981/* print_insn_neon recognizes the following format control codes:
982
983 %% %
984
c22aaad1 985 %c print condition code
e2efe87d
MGD		 986 %u print condition code (unconditional in ARM mode,
987 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 988 %A print v{st,ld}[1234] operands
989 %B print v{st,ld}[1234] any one operands
990 %C print v{st,ld}[1234] single->all operands
991 %D print scalar
992 %E print vmov, vmvn, vorr, vbic encoded constant
993 %F print vtbl,vtbx register list
994
995 %<bitfield>r print as an ARM register
996 %<bitfield>d print the bitfield in decimal
997 %<bitfield>e print the 2^N - bitfield in decimal
998 %<bitfield>D print as a NEON D register
999 %<bitfield>Q print as a NEON Q register
1000 %<bitfield>R print as a NEON D or Q register
1001 %<bitfield>Sn print byte scaled width limited by n
1002 %<bitfield>Tn print short scaled width limited by n
1003 %<bitfield>Un print long scaled width limited by n
43e65147 1004
16980d0b
JB		 1005 %<bitfield>'c print specified char iff bitfield is all ones
1006 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1007 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1008
1009static const struct opcode32 neon_opcodes[] =
1010{
fe56b6ce 1011 /* Extract. */
823d2571
TG		 1012 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1013 0xf2b00840, 0xffb00850,
1014 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1015 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1016 0xf2b00000, 0xffb00810,
1017 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 1018
fe56b6ce 1019 /* Move data element to all lanes. */
823d2571
TG		 1020 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1021 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1022 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1023 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1024 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1025 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 1026
fe56b6ce 1027 /* Table lookup. */
823d2571
TG		 1028 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1029 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1030 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1031 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1032
8e79c3df 1033 /* Half-precision conversions. */
823d2571
TG		 1034 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1035 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1036 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1037 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1038
1039 /* NEON fused multiply add instructions. */
823d2571 1040 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1041 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1042 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1043 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1044 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1045 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1046 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1047 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1048
fe56b6ce 1049 /* Two registers, miscellaneous. */
823d2571
TG		 1050 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1051 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1052 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1053 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1054 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1055 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1056 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1057 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1058 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1059 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1060 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1061 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1062 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1063 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1064 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1065 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1066 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1067 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1068 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1069 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1070 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1071 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1072 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1073 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1074 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1075 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1076 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1077 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1078 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1079 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1080 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1081 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1082 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1083 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1084 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1085 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1086 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1087 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1088 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1089 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1090 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1091 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1092 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1093 0xf3b20300, 0xffb30fd0,
1094 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1095 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1096 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1097 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1098 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1099 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1100 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1101 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1102 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1103 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1104 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1105 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1106 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1107 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1108 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1109 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1110 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1111 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1112 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1113 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1114 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1115 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1116 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1117 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1118 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1119 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1120 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1121 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1122 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1123 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1124 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1125 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1126 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1127 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1128 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1129 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1130 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1131 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1132 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1133 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1134 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1135 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1136 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1137 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1138 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1139 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1140 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1141 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301 1142 0xf3bb0600, 0xffbf0e10,
823d2571 1143 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1144 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1145 0xf3b70600, 0xffbf0e10,
1146 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
16980d0b 1147
fe56b6ce 1148 /* Three registers of the same length. */
823d2571
TG		 1149 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1150 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1151 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1152 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1153 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1154 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1155 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1156 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1157 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1158 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1159 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1160 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1161 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1162 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1163 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1164 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1165 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1166 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1167 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1168 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1169 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1170 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1171 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1172 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1173 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1174 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1175 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1176 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1177 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1178 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1179 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1180 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1181 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1182 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1183 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1184 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1185 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1186 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1187 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1188 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1189 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1190 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1191 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1192 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1193 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1194 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1195 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1196 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1197 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1198 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1199 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1200 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1201 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1202 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1203 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1204 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1205 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1206 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1207 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1208 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1209 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1210 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1211 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1212 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1213 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1214 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1215 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1216 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1217 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1218 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1219 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1220 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1221 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1222 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1223 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1224 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1225 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1226 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1227 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1228 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1229 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1230 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1231 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1232 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1233 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1234 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1235 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1236 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1237 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1238 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1239 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1240 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1241 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1242 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1243 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1244 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1245 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1246 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1247 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1248 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1249 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1250 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1251 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1252 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1253 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1254 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1255 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1256 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1257 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1258 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1259 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1260 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1261 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1262 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1263 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1264 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1265 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1266 0xf2000b00, 0xff800f10,
1267 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1268 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1269 0xf2000b10, 0xff800f10,
1270 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1271 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1272 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1273 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1274 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1275 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1276 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1277 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1278 0xf3000b00, 0xff800f10,
1279 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1280 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1281 0xf2000000, 0xfe800f10,
1282 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1283 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1284 0xf2000010, 0xfe800f10,
1285 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1286 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1287 0xf2000100, 0xfe800f10,
1288 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1289 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1290 0xf2000200, 0xfe800f10,
1291 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1292 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1293 0xf2000210, 0xfe800f10,
1294 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1295 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1296 0xf2000300, 0xfe800f10,
1297 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1298 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1299 0xf2000310, 0xfe800f10,
1300 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1301 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1302 0xf2000400, 0xfe800f10,
1303 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1304 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1305 0xf2000410, 0xfe800f10,
1306 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1307 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1308 0xf2000500, 0xfe800f10,
1309 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1310 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1311 0xf2000510, 0xfe800f10,
1312 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1313 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1314 0xf2000600, 0xfe800f10,
1315 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1316 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1317 0xf2000610, 0xfe800f10,
1318 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1319 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1320 0xf2000700, 0xfe800f10,
1321 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1322 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1323 0xf2000710, 0xfe800f10,
1324 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1325 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1326 0xf2000910, 0xfe800f10,
1327 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1328 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1329 0xf2000a00, 0xfe800f10,
1330 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1331 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1332 0xf2000a10, 0xfe800f10,
1333 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1334 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1335 0xf3000b10, 0xff800f10,
1336 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1337 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1338 0xf3000c10, 0xff800f10,
1339 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1340
fe56b6ce 1341 /* One register and an immediate value. */
823d2571
TG		 1342 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1343 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1344 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1345 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1346 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1347 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1348 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1349 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1350 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1351 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1352 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1353 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1354 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1355 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1356 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1357 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1358 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1359 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1360 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1361 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1362 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1363 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1364 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1365 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1366 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1367 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1368
fe56b6ce 1369 /* Two registers and a shift amount. */
823d2571
TG		 1370 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1371 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1372 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1373 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1374 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1375 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1376 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1377 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1378 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1379 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1380 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1381 0xf2880950, 0xfeb80fd0,
1382 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1383 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1384 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1385 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1386 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1387 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1388 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1389 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1390 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1391 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1392 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1393 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1394 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1395 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1396 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1397 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1398 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1399 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1400 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1401 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1402 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1403 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1404 0xf2900950, 0xfeb00fd0,
1405 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1406 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1407 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1408 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1409 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1410 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1411 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1412 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1413 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1414 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1415 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1416 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1417 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1418 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1419 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1420 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1421 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1422 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1423 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1424 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1425 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1426 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1427 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1428 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1429 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1430 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1431 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1432 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1433 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1434 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1435 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1436 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1437 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1438 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1439 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1440 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1441 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1442 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1443 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1444 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1445 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1446 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1447 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1448 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1449 0xf2a00950, 0xfea00fd0,
1450 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1451 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1452 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1453 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1454 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1456 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1457 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1458 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1459 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1460 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1462 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1464 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1466 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1468 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1470 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1472 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1474 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1476 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1478 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1480 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1482 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1484 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1486 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1487 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1488 0xf2a00e10, 0xfea00e90,
1489 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
cc933301
JW		 1490 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1491 0xf2a00c10, 0xfea00e90,
1492 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 1493
fe56b6ce 1494 /* Three registers of different lengths. */
823d2571
TG		 1495 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1496 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1498 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1499 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1500 0xf2800400, 0xff800f50,
1501 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1502 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1503 0xf2800600, 0xff800f50,
1504 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506 0xf2800900, 0xff800f50,
1507 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1508 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1509 0xf2800b00, 0xff800f50,
1510 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1511 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1512 0xf2800d00, 0xff800f50,
1513 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1514 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1515 0xf3800400, 0xff800f50,
1516 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1517 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1518 0xf3800600, 0xff800f50,
1519 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1520 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1521 0xf2800000, 0xfe800f50,
1522 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1523 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1524 0xf2800100, 0xfe800f50,
1525 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1526 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1527 0xf2800200, 0xfe800f50,
1528 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1530 0xf2800300, 0xfe800f50,
1531 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1532 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1533 0xf2800500, 0xfe800f50,
1534 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1535 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1536 0xf2800700, 0xfe800f50,
1537 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1538 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1539 0xf2800800, 0xfe800f50,
1540 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1541 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1542 0xf2800a00, 0xfe800f50,
1543 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1544 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1545 0xf2800c00, 0xfe800f50,
1546 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 1547
fe56b6ce 1548 /* Two registers and a scalar. */
823d2571
TG		 1549 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1550 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1551 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1552 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1553 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1554 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1555 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1556 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1557 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1558 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1559 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1560 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1561 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1562 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1564 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1565 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1566 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1567 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1568 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1569 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1570 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1571 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1572 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1573 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1574 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1576 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1577 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1578 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1579 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1580 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1581 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1582 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1583 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1584 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1585 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1586 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1587 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1588 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1589 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1590 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1591 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1592 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1593 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1594 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1595 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1596 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1597 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1598 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1599 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1600 0xf2800240, 0xfe800f50,
1601 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1602 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1603 0xf2800640, 0xfe800f50,
1604 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1605 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1606 0xf2800a40, 0xfe800f50,
1607 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 1608 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1609 0xf2800e40, 0xff800f50,
1610 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1611 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1612 0xf2800f40, 0xff800f50,
1613 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1614 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1615 0xf3800e40, 0xff800f50,
1616 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1618 0xf3800f40, 0xff800f50,
1619 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1620 },
16980d0b 1621
fe56b6ce 1622 /* Element and structure load/store. */
823d2571
TG		 1623 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1624 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1625 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1626 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1627 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1628 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1630 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1631 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1632 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1633 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1634 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1635 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1636 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1638 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1639 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1640 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1642 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1643 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1644 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1646 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1647 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1648 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1650 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1651 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1652 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1653 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1654 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1655 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1656 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1658 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1659 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1660 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1661
1662 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 1663};
1664
8f06b2d8
PB		 1665/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
1666 ordered: they must be searched linearly from the top to obtain a correct
1667 match. */
1668
1669/* print_insn_arm recognizes the following format control codes:
1670
1671 %% %
1672
1673 %a print address for ldr/str instruction
1674 %s print address for ldr/str halfword/signextend instruction
c1e26897 1675 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 1676 %b print branch destination
1677 %c print condition code (always bits 28-31)
1678 %m print register mask for ldm/stm instruction
1679 %o print operand2 (immediate or register + shift)
1680 %p print 'p' iff bits 12-15 are 15
1681 %t print 't' iff bit 21 set and bit 24 clear
1682 %B print arm BLX(1) destination
1683 %C print the PSR sub type.
62b3e311
PB		 1684 %U print barrier type.
1685 %P print address for pli instruction.
8f06b2d8
PB		 1686
1687 %<bitfield>r print as an ARM register
9eb6c0f1 1688 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 1689 %<bitfield>R as %r but r15 is UNPREDICTABLE
1690 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1691 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 1692 %<bitfield>d print the bitfield in decimal
43e65147 1693 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 1694 %<bitfield>x print the bitfield in hex
1695 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 1696
16980d0b
JB		 1697 %<bitfield>'c print specified char iff bitfield is all ones
1698 %<bitfield>`c print specified char iff bitfield is all zeroes
1699 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 1700
8f06b2d8
PB		 1701 %e print arm SMI operand (bits 0..7,8..19).
1702 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 1703 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
1704 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 1705
8f06b2d8
PB		 1706static const struct opcode32 arm_opcodes[] =
1707{
1708 /* ARM instructions. */
823d2571
TG		 1709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1710 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1711 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1712 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1713
1714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
1715 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1717 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1719 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
1721 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1723 0x00800090, 0x0fa000f0,
1724 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1726 0x00a00090, 0x0fa000f0,
1727 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 1728
105bde57 1729 /* V8.2 RAS extension instructions. */
4d1464f2 1730 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 1731 0xe320f010, 0xffffffff, "esb"},
1732
53c4b28b 1733 /* V8 instructions. */
823d2571
TG		 1734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1735 0x0320f005, 0x0fffffff, "sevl"},
1736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1737 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
4ed7ed8d 1738 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 1739 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1740 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 1741 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1743 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1745 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 1746 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1747 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1748 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1749 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1750 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1751 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1752 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1753 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1754 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1755 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1756 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1757 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1758 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1759 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1760 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1761 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1762 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1763 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1764 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 1765 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 1766 /* CRC32 instructions. */
823d2571
TG		 1767 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1768 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
1769 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1770 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
1771 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1772 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
1773 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1774 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
1775 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1776 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
1777 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1778 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 1779
ddfded2f
MW		 1780 /* Privileged Access Never extension instructions. */
1781 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
1782 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
1783
90ec0d68 1784 /* Virtualization Extension instructions. */
823d2571
TG		 1785 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
1786 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 1787
eea54501 1788 /* Integer Divide Extension instructions. */
823d2571
TG		 1789 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1790 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1791 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1792 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 1793
60e5ef9f 1794 /* MP Extension instructions. */
823d2571 1795 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 1796
62b3e311 1797 /* V7 instructions. */
823d2571
TG		 1798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
1799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
1801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
1802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a
AV		 1805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
1806 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
62b3e311 1807
c19d1205 1808 /* ARM V6T2 instructions. */
823d2571
TG		 1809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1810 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1812 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1814 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1816 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
1817
1818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1819 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
1820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1821 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1822
ff8646ee 1823 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 1824 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 1825 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 1826 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1828 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1830 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 1831
f4c65163 1832 /* ARM Security extension instructions. */
823d2571
TG		 1833 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
1834 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 1835
8f06b2d8 1836 /* ARM V6K instructions. */
823d2571
TG		 1837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1838 0xf57ff01f, 0xffffffff, "clrex"},
1839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1840 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1842 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1844 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1846 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1848 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1850 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 1851
8f06b2d8 1852 /* ARM V6K NOP hints. */
823d2571
TG		 1853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1854 0x0320f001, 0x0fffffff, "yield%c"},
1855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1856 0x0320f002, 0x0fffffff, "wfe%c"},
1857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1858 0x0320f003, 0x0fffffff, "wfi%c"},
1859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1860 0x0320f004, 0x0fffffff, "sev%c"},
1861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1862 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 1863
fe56b6ce 1864 /* ARM V6 instructions. */
823d2571
TG		 1865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1866 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
1867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1868 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
1869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1870 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
1871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1872 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
1873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1874 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
1875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1876 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
1877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1878 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
1879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1880 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
1881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1882 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
1883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1884 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
1885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1886 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
1887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1888 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
1889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1890 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
1891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1892 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
1893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1894 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
1895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1896 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
1897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1898 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
1899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1900 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
1901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1902 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
1903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1904 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
1905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1906 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
1907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1908 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
1909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1910 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
1911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1912 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
1913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1914 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
1915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1916 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
1917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1918 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
1919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1920 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
1921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1922 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
1923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1924 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
1925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1926 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
1927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1928 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
1929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1930 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
1931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1932 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
1933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1934 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
1935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1936 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
1937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1938 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
1939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1940 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
1941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1942 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
1943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1944 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
1945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1946 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
1947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1948 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
1949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1950 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
1951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1952 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
1953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1954 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
1955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1956 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
1957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1958 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
1959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1960 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
1961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1962 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
1963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1964 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
1965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1966 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
1967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1968 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
1969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1970 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
1971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1972 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
1973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1974 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
1975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1976 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
1977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1978 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
1979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1980 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
1981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1982 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
1983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1984 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
1985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1986 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
1987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1988 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
1989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1990 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
1991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1992 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
1993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1994 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
1995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1996 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
1997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1998 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
1999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2000 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
2001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2002 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
2003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2004 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
2005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2006 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
2007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2008 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
2009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2010 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
2011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2012 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
2013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2014 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
2015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2016 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2018 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2020 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2022 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
2023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2024 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2026 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2028 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2030 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
2031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2032 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2034 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2036 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2038 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
2039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2040 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2042 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2044 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2046 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
2047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2048 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2050 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2052 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
2053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2054 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
2055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2056 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2058 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2060 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2062 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
2063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2064 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
2065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2066 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
2067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2068 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
2069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2070 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2072 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2074 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2076 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2078 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
2079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2080 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2082 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2084 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
2085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2086 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
2087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2088 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
2089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2090 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
2091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2092 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
2093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2094 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
2095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2096 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
2097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2098 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
2099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2100 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2102 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
2103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2104 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
2105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2106 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
2107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2108 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 2109
8f06b2d8 2110 /* V5J instruction. */
823d2571
TG		 2111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
2112 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 2113
8f06b2d8 2114 /* V5 Instructions. */
823d2571
TG		 2115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2116 0xe1200070, 0xfff000f0,
2117 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
2118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2119 0xfa000000, 0xfe000000, "blx\t%B"},
2120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2121 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
2122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2123 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
2124
2125 /* V5E "El Segundo" Instructions. */
2126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2127 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
2128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2129 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
2130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2131 0xf450f000, 0xfc70f000, "pld\t%a"},
2132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2133 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2135 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2137 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2139 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
2140
2141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2142 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2144 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
2145
2146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2147 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2149 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2151 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2153 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2154
2155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2156 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2158 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2160 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2162 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2163
2164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2165 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2167 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2168
2169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2170 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
2171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2172 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2174 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
2175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2176 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 2177
8f06b2d8 2178 /* ARM Instructions. */
823d2571
TG		 2179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2180 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2181
2182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2183 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2185 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2187 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2189 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2191 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2193 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2194
2195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2196 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2198 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2200 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2202 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2203
2204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2205 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2207 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2209 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2210 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2211 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2212
2213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2214 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2216 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2217 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2218 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2219
2220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2221 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2223 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2225 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2226
2227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2228 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2230 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2232 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2233
2234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2235 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2237 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2238 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2239 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2240
2241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2242 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2244 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2246 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2247
2248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2249 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2251 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2252 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2253 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2254
2255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2256 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2257 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2258 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2259 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2260 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2261
2262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2263 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2265 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2266 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2267 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2268
2269 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2270 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2272 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2273 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2274 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2275
2276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2277 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2279 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2281 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2282
2283 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2284 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 2285 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2286 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 2287 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a
AV		 2288 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
2289 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2290 0x0130f000, 0x0ff0f010, "bx%c\t%0-3r"},
823d2571
TG		 2291
2292 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2293 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2294 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2295 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2297 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2298
2299 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2300 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2301 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2302 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2304 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2305
2306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2307 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2309 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2310 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2311 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2312
2313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2314 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2315 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2316 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2317 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2318 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2320 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2322 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2323 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2324 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2325 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2326 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2327
2328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2329 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2331 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2333 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2334
2335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2336 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2338 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2339 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2340 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2341
2342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2343 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2345 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2346
2347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2348 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2349
2350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2351 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2353 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2354
2355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2356 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2358 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2360 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2362 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2364 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2366 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2368 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2370 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2372 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2374 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2376 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2378 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2380 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2382 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2384 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2386 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2388 0x092d0000, 0x0fff0000, "push%c\t%m"},
2389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2390 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2392 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2393
2394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2395 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2397 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2399 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2401 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2403 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2405 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2407 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2409 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2411 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2413 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2415 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2417 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2418 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2419 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2421 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2423 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2425 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2427 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2429 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2431 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2432
2433 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2434 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2435 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2436 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 2437
2438 /* The rest. */
4ab90a7a
AV		 2439 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2440 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 2441 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2442 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2443 {ARM_FEATURE_CORE_LOW (0),
2444 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 2445};
2446
2447/* print_insn_thumb16 recognizes the following format control codes:
2448
2449 %S print Thumb register (bits 3..5 as high number if bit 6 set)
2450 %D print Thumb register (bits 0..2 as high number if bit 7 set)
2451 %<bitfield>I print bitfield as a signed decimal
2452 (top bit of range being the sign bit)
2453 %N print Thumb register mask (with LR)
2454 %O print Thumb register mask (with PC)
2455 %M print Thumb register mask
2456 %b print CZB's 6-bit unsigned branch destination
2457 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 2458 %c print the condition code
2459 %C print the condition code, or "s" if not conditional
2460 %x print warning if conditional an not at end of IT block"
2461 %X print "\t; unpredictable <IT:code>" if conditional
2462 %I print IT instruction suffix and operands
4547cb56 2463 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 2464 %<bitfield>r print bitfield as an ARM register
2465 %<bitfield>d print bitfield as a decimal
2466 %<bitfield>H print (bitfield * 2) as a decimal
2467 %<bitfield>W print (bitfield * 4) as a decimal
2468 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
2469 %<bitfield>B print Thumb branch destination (signed displacement)
2470 %<bitfield>c print bitfield as a condition code
2471 %<bitnum>'c print specified char iff bit is one
2472 %<bitnum>?ab print a if bit is one else print b. */
2473
2474static const struct opcode16 thumb_opcodes[] =
2475{
2476 /* Thumb instructions. */
2477
16a1fa25
TP		 2478 /* ARMv8-M Security Extensions instructions. */
2479 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
2480 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff07, "bxns\t%3-6r"},
2481
53c4b28b 2482 /* ARM V8 instructions. */
823d2571
TG		 2483 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
2484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
ddfded2f 2485 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
53c4b28b 2486
8f06b2d8 2487 /* ARM V6K no-argument instructions. */
823d2571
TG		 2488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2489 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2490 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 2494
2495 /* ARM V6T2 instructions. */
ff8646ee
TP		 2496 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2497 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2498 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2499 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 2500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 2501
2502 /* ARM V6. */
823d2571
TG		 2503 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2504 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2505 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2507 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2509 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2510 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2511 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2513 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 2514
2515 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 2516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2517 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 2518 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 2519 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2520 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 2521 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 2522 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2523 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 2524 /* Format 4. */
823d2571
TG		 2525 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2526 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2527 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2528 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2529 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2531 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2533 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2534 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2535 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2537 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2539 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 2541 /* format 13 */
823d2571
TG		 2542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 2544 /* format 5 */
823d2571
TG		 2545 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
2546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
2547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 2549 /* format 14 */
823d2571
TG		 2550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
2551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 2552 /* format 2 */
823d2571
TG		 2553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2554 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2555 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2556 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2557 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2558 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2559 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2560 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 2561 /* format 8 */
823d2571
TG		 2562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2563 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2565 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2567 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2568 /* format 7 */
823d2571
TG		 2569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2570 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2572 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2573 /* format 1 */
823d2571
TG		 2574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2576 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 2579 /* format 3 */
823d2571
TG		 2580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 2584 /* format 6 */
823d2571
TG		 2585 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2587 0x4800, 0xF800,
2588 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 2589 /* format 9 */
823d2571
TG		 2590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2591 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2593 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2595 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2597 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 2598 /* format 10 */
823d2571
TG		 2599 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2600 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2601 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2602 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 2603 /* format 11 */
823d2571
TG		 2604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2605 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2607 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 2608 /* format 12 */
823d2571
TG		 2609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2610 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2611 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2612 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 2613 /* format 15 */
823d2571
TG		 2614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2615 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 2616 /* format 17 */
823d2571 2617 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 2618 /* format 16 */
823d2571
TG		 2619 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
2621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 2622 /* format 18 */
823d2571 2623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 2624
2625 /* The E800 .. FFFF range is unconditionally redirected to the
2626 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2627 are processed via that table. Thus, we can never encounter a
2628 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 2629 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
2630 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 2631};
2632
2633/* Thumb32 opcodes use the same table structure as the ARM opcodes.
2634 We adopt the convention that hw1 is the high 16 bits of .value and
2635 .mask, hw2 the low 16 bits.
2636
2637 print_insn_thumb32 recognizes the following format control codes:
2638
2639 %% %
2640
2641 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2642 %M print a modified 12-bit immediate (same location)
2643 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2644 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 2645 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 2646 %S print a possibly-shifted Rm
2647
32a94698 2648 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 2649 %a print the address of a plain load/store
2650 %w print the width and signedness of a core load/store
2651 %m print register mask for ldm/stm
2652
2653 %E print the lsb and width fields of a bfc/bfi instruction
2654 %F print the lsb and width fields of a sbfx/ubfx instruction
2655 %b print a conditional branch offset
2656 %B print an unconditional branch offset
2657 %s print the shift field of an SSAT instruction
2658 %R print the rotation field of an SXT instruction
62b3e311
PB		 2659 %U print barrier type.
2660 %P print address for pli instruction.
c22aaad1
PB		 2661 %c print the condition code
2662 %x print warning if conditional an not at end of IT block"
2663 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 2664
2665 %<bitfield>d print bitfield in decimal
f0fba320 2666 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 2667 %<bitfield>W print bitfield*4 in decimal
2668 %<bitfield>r print bitfield as an ARM register
dd5181d5
KT		 2669 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
2670 %<bitfield>S as %<>R but r13 is UNPREDICTABLE
8f06b2d8
PB		 2671 %<bitfield>c print bitfield as a condition code
2672
16980d0b
JB		 2673 %<bitfield>'c print specified char iff bitfield is all ones
2674 %<bitfield>`c print specified char iff bitfield is all zeroes
2675 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 2676
2677 With one exception at the bottom (done because BL and BLX(1) need
2678 to come dead last), this table was machine-sorted first in
2679 decreasing order of number of bits set in the mask, then in
2680 increasing numeric order of mask, then in increasing numeric order
2681 of opcode. This order is not the clearest for a human reader, but
2682 is guaranteed never to catch a special-case bit pattern with a more
2683 general mask, which is important, because this instruction encoding
2684 makes heavy use of special-case bit patterns. */
2685static const struct opcode32 thumb32_opcodes[] =
2686{
16a1fa25
TP		 2687 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
2688 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4ed7ed8d
TP		 2689 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2690 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
2691 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2692 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
16a1fa25
TP		 2693 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2694 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
2695 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2696 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4ed7ed8d 2697
105bde57 2698 /* ARM V8.2 RAS extension instructions. */
4d1464f2 2699 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 2700 0xf3af8010, 0xffffffff, "esb"},
2701
53c4b28b 2702 /* V8 instructions. */
823d2571
TG		 2703 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2704 0xf3af8005, 0xffffffff, "sevl%c.w"},
2705 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2706 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2708 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2710 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
2711 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2712 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
2713 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2714 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
2715 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2716 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
2717 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2718 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
2719 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2720 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
2721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2722 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2724 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2726 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
2727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2728 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2730 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2732 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2734 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 2735
dd5181d5 2736 /* CRC32 instructions. */
823d2571
TG		 2737 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2738 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"},
2739 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2740 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"},
2741 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2742 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"},
2743 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2744 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"},
2745 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2746 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"},
2747 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2748 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"},
dd5181d5 2749
62b3e311 2750 /* V7 instructions. */
823d2571
TG		 2751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
2752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
2753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
2754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
2755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
2756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
2757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
2758 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2759 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
2760 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2761 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 2762
90ec0d68 2763 /* Virtualization Extension instructions. */
823d2571 2764 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 2765 /* We skip ERET as that is SUBS pc, lr, #0. */
2766
60e5ef9f 2767 /* MP Extension instructions. */
823d2571 2768 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 2769
f4c65163 2770 /* Security extension instructions. */
823d2571 2771 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 2772
8f06b2d8 2773 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 2774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
2775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
2776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
2779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2780 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
2781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
2782
ff8646ee 2783 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2784 0xf3bf8f2f, 0xffffffff, "clrex%c"},
2785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2786 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
2787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2788 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
2789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2790 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
2791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2792 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
2793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2794 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
2795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2796 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
2797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2798 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
2799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2800 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
2801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2802 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
2803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2804 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
2805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2806 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
2807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2808 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
2809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2810 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 2811 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 2812 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 2813 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2814 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
2815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2816 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
2817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2818 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
2819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2820 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
2821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2822 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
2823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2824 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
2825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2826 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
2827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2828 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
2829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2830 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 2831 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2832 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
2833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2834 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
2835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2836 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
2837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2838 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
2839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2840 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
2841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2842 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
2843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2844 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
2845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2846 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
2847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2848 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
2849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2850 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
2851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2852 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
2853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2854 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
2855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2856 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
2857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2858 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
2859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2860 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
2861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2862 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
2863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2864 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
2865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2866 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
2867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2868 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
2869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2870 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
2871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2872 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
2873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2874 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
2875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2876 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
2877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2878 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
2879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2880 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
2881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2882 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
2883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2884 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
2885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2886 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
2887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2888 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
2889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2890 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
2891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2892 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
2893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2894 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
2895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2896 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
2897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2898 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
2899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2900 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
2901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2902 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
2903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2904 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
2905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2906 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
2907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2908 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
2909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2910 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
2911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2912 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
2913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2914 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
2915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2916 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
2917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2918 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
2919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2920 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
2921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2922 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
2923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2924 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
2925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2926 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
2927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2928 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
2929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2930 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
2931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2932 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2934 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2936 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2938 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 2939 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2940 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
2941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 2942 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 2943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2944 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
2945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2946 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
2947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2948 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2950 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
2951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2952 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
2953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2954 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2956 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2958 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2960 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2962 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2964 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2966 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2968 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
2969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2970 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
2971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2972 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
2973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2974 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
2975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2976 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
2977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2978 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
2979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2980 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
2981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2982 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
2983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2984 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
2985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2986 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
2987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2988 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
2989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2990 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
2991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2992 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2994 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2996 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2998 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3000 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3002 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3004 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3006 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 3007 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3008 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
3009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3010 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
3011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3012 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
3013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3014 0xf810f000, 0xff70f000, "pld%c\t%a"},
3015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3016 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3018 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3020 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3022 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3024 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3026 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3028 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3030 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
3031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3032 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
3033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3034 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
3035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3036 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
3037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3038 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
3039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3040 0xfb100000, 0xfff000c0,
3041 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3043 0xfbc00080, 0xfff000c0,
3044 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
3045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3046 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
3047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3048 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
3049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 3050 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 3051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3052 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
3053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3054 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 3055 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3056 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
3057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3058 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 3059 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3060 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
3061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3062 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
3063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3064 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
3065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3066 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
3067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3068 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
3069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3070 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
3071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3072 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
3073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3074 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
3075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3076 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
3077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3078 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
3079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3080 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 3081 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3082 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
3083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3084 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
3085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3086 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
3087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3088 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
3089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3090 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
3091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3092 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
3093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3094 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
3095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3096 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
3097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3098 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
3099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3100 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
3101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3102 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
3103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3104 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
3105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3106 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
3107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3108 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
3109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3110 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
3111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3112 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
3113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3114 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
3115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3116 0xe9400000, 0xff500000,
3117 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3119 0xe9500000, 0xff500000,
3120 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3122 0xe8600000, 0xff700000,
3123 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3125 0xe8700000, 0xff700000,
3126 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3128 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
3129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3130 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 3131
3132 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 3133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3134 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
3135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3136 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
3137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3138 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
3139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3140 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 3141
8f06b2d8 3142 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 3143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3144 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
3145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3146 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 3147
3148 /* Fallback. */
823d2571
TG		 3149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3150 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3151 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 3152};
ff4a8d2b 3153
8f06b2d8
PB		 3154static const char *const arm_conditional[] =
3155{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 3156 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 3157
3158static const char *const arm_fp_const[] =
3159{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3160
3161static const char *const arm_shift[] =
3162{"lsl", "lsr", "asr", "ror"};
3163
3164typedef struct
3165{
3166 const char *name;
3167 const char *description;
3168 const char *reg_names[16];
3169}
3170arm_regname;
3171
3172static const arm_regname regnames[] =
3173{
3174 { "raw" , "Select raw register names",
3175 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
3176 { "gcc", "Select register names used by GCC",
3177 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
3178 { "std", "Select register names used in ARM's ISA documentation",
3179 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
3180 { "apcs", "Select register names used in the APCS",
3181 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
3182 { "atpcs", "Select register names used in the ATPCS",
3183 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
3184 { "special-atpcs", "Select special register names used in the ATPCS",
3185 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
3186};
3187
3188static const char *const iwmmxt_wwnames[] =
3189{"b", "h", "w", "d"};
3190
3191static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 3192{"b", "bus", "bc", "bss",
3193 "h", "hus", "hc", "hss",
3194 "w", "wus", "wc", "wss",
3195 "d", "dus", "dc", "dss"
8f06b2d8
PB		 3196};
3197
3198static const char *const iwmmxt_regnames[] =
3199{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3200 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3201};
3202
3203static const char *const iwmmxt_cregnames[] =
3204{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3205 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3206};
3207
3208/* Default to GCC register name set. */
3209static unsigned int regname_selected = 1;
3210
3211#define NUM_ARM_REGNAMES NUM_ELEM (regnames)
3212#define arm_regnames regnames[regname_selected].reg_names
3213
3214static bfd_boolean force_thumb = FALSE;
3215
c22aaad1
PB		 3216/* Current IT instruction state. This contains the same state as the IT
3217 bits in the CPSR. */
3218static unsigned int ifthen_state;
3219/* IT state for the next instruction. */
3220static unsigned int ifthen_next_state;
3221/* The address of the insn for which the IT state is valid. */
3222static bfd_vma ifthen_address;
3223#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 3224/* Indicates that the current Conditional state is unconditional or outside
3225 an IT block. */
3226#define COND_UNCOND 16
c22aaad1 3227
8f06b2d8
PB		 3228\f
3229/* Functions. */
3230int
3231get_arm_regname_num_options (void)
3232{
3233 return NUM_ARM_REGNAMES;
3234}
3235
3236int
3237set_arm_regname_option (int option)
3238{
3239 int old = regname_selected;
3240 regname_selected = option;
3241 return old;
3242}
3243
3244int
fe56b6ce
NC		 3245get_arm_regnames (int option,
3246 const char **setname,
3247 const char **setdescription,
8f06b2d8
PB		 3248 const char *const **register_names)
3249{
3250 *setname = regnames[option].name;
3251 *setdescription = regnames[option].description;
3252 *register_names = regnames[option].reg_names;
3253 return 16;
3254}
3255
16980d0b
JB		 3256/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3257 Returns pointer to following character of the format string and
3258 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 3259 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 3260
3261static const char *
fe56b6ce
NC		 3262arm_decode_bitfield (const char *ptr,
3263 unsigned long insn,
3264 unsigned long *valuep,
3265 int *widthp)
16980d0b
JB		 3266{
3267 unsigned long value = 0;
3268 int width = 0;
43e65147
L		 3269
3270 do
16980d0b
JB		 3271 {
3272 int start, end;
3273 int bits;
3274
3275 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3276 start = start * 10 + *ptr - '0';
3277 if (*ptr == '-')
3278 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3279 end = end * 10 + *ptr - '0';
3280 else
3281 end = start;
3282 bits = end - start;
3283 if (bits < 0)
3284 abort ();
3285 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3286 width += bits + 1;
3287 }
3288 while (*ptr++ == ',');
3289 *valuep = value;
3290 if (widthp)
3291 *widthp = width;
3292 return ptr - 1;
3293}
3294
8f06b2d8 3295static void
37b37b2d 3296arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 3297 bfd_boolean print_shift)
8f06b2d8
PB		 3298{
3299 func (stream, "%s", arm_regnames[given & 0xf]);
3300
3301 if ((given & 0xff0) != 0)
3302 {
3303 if ((given & 0x10) == 0)
3304 {
3305 int amount = (given & 0xf80) >> 7;
3306 int shift = (given & 0x60) >> 5;
3307
3308 if (amount == 0)
3309 {
3310 if (shift == 3)
3311 {
3312 func (stream, ", rrx");
3313 return;
3314 }
3315
3316 amount = 32;
3317 }
3318
37b37b2d
RE		 3319 if (print_shift)
3320 func (stream, ", %s #%d", arm_shift[shift], amount);
3321 else
3322 func (stream, ", #%d", amount);
8f06b2d8 3323 }
74bdfecf 3324 else if ((given & 0x80) == 0x80)
aefd8a40 3325 func (stream, "\t; <illegal shifter operand>");
37b37b2d 3326 else if (print_shift)
8f06b2d8
PB		 3327 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3328 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 3329 else
3330 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 3331 }
3332}
3333
c1e26897
NC		 3334#define W_BIT 21
3335#define I_BIT 22
3336#define U_BIT 23
3337#define P_BIT 24
3338
3339#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
3340#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
3341#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
3342#define PRE_BIT_SET (given & (1 << P_BIT))
3343
8f06b2d8
PB		 3344/* Print one coprocessor instruction on INFO->STREAM.
3345 Return TRUE if the instuction matched, FALSE if this is not a
3346 recognised coprocessor instruction. */
3347
3348static bfd_boolean
fe56b6ce
NC		 3349print_insn_coprocessor (bfd_vma pc,
3350 struct disassemble_info *info,
3351 long given,
8f06b2d8
PB		 3352 bfd_boolean thumb)
3353{
3354 const struct opcode32 *insn;
3355 void *stream = info->stream;
3356 fprintf_ftype func = info->fprintf_func;
3357 unsigned long mask;
2edcd244 3358 unsigned long value = 0;
c22aaad1 3359 int cond;
8afc7bea 3360 int cp_num;
823d2571
TG		 3361 struct arm_private_data *private_data = info->private_data;
3362 arm_feature_set allowed_arches = ARM_ARCH_NONE;
3363
3364 ARM_FEATURE_COPY (allowed_arches, private_data->features);
8f06b2d8
PB		 3365
3366 for (insn = coprocessor_opcodes; insn->assembler; insn++)
3367 {
ff4a8d2b
NC		 3368 unsigned long u_reg = 16;
3369 bfd_boolean is_unpredictable = FALSE;
05413229 3370 signed long value_in_comment = 0;
0313a2b8
NC		 3371 const char *c;
3372
823d2571 3373 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 3374 switch (insn->value)
3375 {
3376 case SENTINEL_IWMMXT_START:
3377 if (info->mach != bfd_mach_arm_XScale
3378 && info->mach != bfd_mach_arm_iWMMXt
3379 && info->mach != bfd_mach_arm_iWMMXt2)
3380 do
3381 insn++;
823d2571
TG		 3382 while ((! ARM_FEATURE_ZERO (insn->arch))
3383 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 3384 continue;
3385
3386 case SENTINEL_IWMMXT_END:
3387 continue;
3388
3389 case SENTINEL_GENERIC_START:
823d2571 3390 ARM_FEATURE_COPY (allowed_arches, private_data->features);
05413229
NC		 3391 continue;
3392
3393 default:
3394 abort ();
3395 }
8f06b2d8
PB		 3396
3397 mask = insn->mask;
3398 value = insn->value;
8afc7bea
RL		 3399 cp_num = (given >> 8) & 0xf;
3400
8f06b2d8
PB		 3401 if (thumb)
3402 {
3403 /* The high 4 bits are 0xe for Arm conditional instructions, and
3404 0xe for arm unconditional instructions. The rest of the
3405 encoding is the same. */
3406 mask |= 0xf0000000;
3407 value |= 0xe0000000;
c22aaad1
PB		 3408 if (ifthen_state)
3409 cond = IFTHEN_COND;
3410 else
e2efe87d 3411 cond = COND_UNCOND;
8f06b2d8
PB		 3412 }
3413 else
3414 {
3415 /* Only match unconditional instuctions against unconditional
3416 patterns. */
3417 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 3418 {
3419 mask |= 0xf0000000;
e2efe87d 3420 cond = COND_UNCOND;
c22aaad1
PB		 3421 }
3422 else
3423 {
3424 cond = (given >> 28) & 0xf;
3425 if (cond == 0xe)
e2efe87d 3426 cond = COND_UNCOND;
c22aaad1 3427 }
8f06b2d8 3428 }
823d2571 3429
0313a2b8
NC		 3430 if ((given & mask) != value)
3431 continue;
8f06b2d8 3432
823d2571 3433 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 3434 continue;
3435
8afc7bea
RL		 3436 if (insn->value == 0xfe000010 /* mcr2 */
3437 || insn->value == 0xfe100010 /* mrc2 */
3438 || insn->value == 0xfc100000 /* ldc2 */
3439 || insn->value == 0xfc000000) /* stc2 */
3440 {
b0c11777 3441 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea
RL		 3442 is_unpredictable = TRUE;
3443 }
3444 else if (insn->value == 0x0e000000 /* cdp */
3445 || insn->value == 0xfe000000 /* cdp2 */
3446 || insn->value == 0x0e000010 /* mcr */
3447 || insn->value == 0x0e100010 /* mrc */
3448 || insn->value == 0x0c100000 /* ldc */
3449 || insn->value == 0x0c000000) /* stc */
3450 {
3451 /* Floating-point instructions. */
b0c11777 3452 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea
RL		 3453 continue;
3454 }
3455
0313a2b8
NC		 3456 for (c = insn->assembler; *c; c++)
3457 {
3458 if (*c == '%')
8f06b2d8 3459 {
0313a2b8 3460 switch (*++c)
8f06b2d8 3461 {
0313a2b8
NC		 3462 case '%':
3463 func (stream, "%%");
3464 break;
3465
3466 case 'A':
05413229 3467 {
79862e45 3468 int rn = (given >> 16) & 0xf;
b0c11777 3469 bfd_vma offset = given & 0xff;
0313a2b8 3470
05413229 3471 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 3472
79862e45
DJ		 3473 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
3474 {
3475 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 3476 if (cp_num == 9)
3477 /* vldr.16/vstr.16 will shift the address
3478 left by 1 bit only. */
3479 offset = offset * 2;
3480 else
3481 offset = offset * 4;
3482
79862e45
DJ		 3483 if (NEGATIVE_BIT_SET)
3484 offset = - offset;
3485 if (rn != 15)
3486 value_in_comment = offset;
3487 }
3488
c1e26897 3489 if (PRE_BIT_SET)
05413229
NC		 3490 {
3491 if (offset)
fe56b6ce 3492 func (stream, ", #%d]%s",
d908c8af 3493 (int) offset,
c1e26897 3494 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 3495 else if (NEGATIVE_BIT_SET)
3496 func (stream, ", #-0]");
05413229
NC		 3497 else
3498 func (stream, "]");
3499 }
3500 else
3501 {
0313a2b8 3502 func (stream, "]");
8f06b2d8 3503
c1e26897 3504 if (WRITEBACK_BIT_SET)
05413229
NC		 3505 {
3506 if (offset)
d908c8af 3507 func (stream, ", #%d", (int) offset);
26d97720
NS		 3508 else if (NEGATIVE_BIT_SET)
3509 func (stream, ", #-0");
05413229
NC		 3510 }
3511 else
fe56b6ce 3512 {
26d97720
NS		 3513 func (stream, ", {%s%d}",
3514 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 3515 (int) offset);
fe56b6ce
NC		 3516 value_in_comment = offset;
3517 }
05413229 3518 }
79862e45
DJ		 3519 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
3520 {
3521 func (stream, "\t; ");
6844b2c2
MGD		 3522 /* For unaligned PCs, apply off-by-alignment
3523 correction. */
43e65147 3524 info->print_address_func (offset + pc
6844b2c2
MGD		 3525 + info->bytes_per_chunk * 2
3526 - (pc & 3),
3527 info);
79862e45 3528 }
05413229 3529 }
0313a2b8 3530 break;
8f06b2d8 3531
0313a2b8
NC		 3532 case 'B':
3533 {
3534 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
3535 int offset = (given >> 1) & 0x3f;
3536
3537 if (offset == 1)
3538 func (stream, "{d%d}", regno);
3539 else if (regno + offset > 32)
3540 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
3541 else
3542 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
3543 }
3544 break;
8f06b2d8 3545
e2efe87d
MGD		 3546 case 'u':
3547 if (cond != COND_UNCOND)
3548 is_unpredictable = TRUE;
3549
3550 /* Fall through. */
0313a2b8 3551 case 'c':
b0c11777
RL		 3552 if (cond != COND_UNCOND && cp_num == 9)
3553 is_unpredictable = TRUE;
3554
0313a2b8
NC		 3555 func (stream, "%s", arm_conditional[cond]);
3556 break;
8f06b2d8 3557
0313a2b8
NC		 3558 case 'I':
3559 /* Print a Cirrus/DSP shift immediate. */
3560 /* Immediates are 7bit signed ints with bits 0..3 in
3561 bits 0..3 of opcode and bits 4..6 in bits 5..7
3562 of opcode. */
3563 {
3564 int imm;
8f06b2d8 3565
0313a2b8 3566 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 3567
0313a2b8
NC		 3568 /* Is ``imm'' a negative number? */
3569 if (imm & 0x40)
24b4cf66 3570 imm -= 0x80;
8f06b2d8 3571
0313a2b8
NC		 3572 func (stream, "%d", imm);
3573 }
3574
3575 break;
8f06b2d8 3576
0313a2b8
NC		 3577 case 'F':
3578 switch (given & 0x00408000)
3579 {
3580 case 0:
3581 func (stream, "4");
3582 break;
3583 case 0x8000:
3584 func (stream, "1");
3585 break;
3586 case 0x00400000:
3587 func (stream, "2");
8f06b2d8 3588 break;
0313a2b8
NC		 3589 default:
3590 func (stream, "3");
3591 }
3592 break;
8f06b2d8 3593
0313a2b8
NC		 3594 case 'P':
3595 switch (given & 0x00080080)
3596 {
3597 case 0:
3598 func (stream, "s");
3599 break;
3600 case 0x80:
3601 func (stream, "d");
3602 break;
3603 case 0x00080000:
3604 func (stream, "e");
3605 break;
3606 default:
3607 func (stream, _("<illegal precision>"));
8f06b2d8 3608 break;
0313a2b8
NC		 3609 }
3610 break;
8f06b2d8 3611
0313a2b8
NC		 3612 case 'Q':
3613 switch (given & 0x00408000)
3614 {
3615 case 0:
3616 func (stream, "s");
8f06b2d8 3617 break;
0313a2b8
NC		 3618 case 0x8000:
3619 func (stream, "d");
8f06b2d8 3620 break;
0313a2b8
NC		 3621 case 0x00400000:
3622 func (stream, "e");
3623 break;
3624 default:
3625 func (stream, "p");
8f06b2d8 3626 break;
0313a2b8
NC		 3627 }
3628 break;
8f06b2d8 3629
0313a2b8
NC		 3630 case 'R':
3631 switch (given & 0x60)
3632 {
3633 case 0:
3634 break;
3635 case 0x20:
3636 func (stream, "p");
3637 break;
3638 case 0x40:
3639 func (stream, "m");
3640 break;
3641 default:
3642 func (stream, "z");
3643 break;
3644 }
3645 break;
16980d0b 3646
0313a2b8
NC		 3647 case '0': case '1': case '2': case '3': case '4':
3648 case '5': case '6': case '7': case '8': case '9':
3649 {
3650 int width;
8f06b2d8 3651
0313a2b8 3652 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 3653
0313a2b8
NC		 3654 switch (*c)
3655 {
ff4a8d2b
NC		 3656 case 'R':
3657 if (value == 15)
3658 is_unpredictable = TRUE;
3659 /* Fall through. */
0313a2b8 3660 case 'r':
ff4a8d2b
NC		 3661 if (c[1] == 'u')
3662 {
3663 /* Eat the 'u' character. */
3664 ++ c;
3665
3666 if (u_reg == value)
3667 is_unpredictable = TRUE;
3668 u_reg = value;
3669 }
0313a2b8
NC		 3670 func (stream, "%s", arm_regnames[value]);
3671 break;
3672 case 'D':
3673 func (stream, "d%ld", value);
3674 break;
3675 case 'Q':
3676 if (value & 1)
3677 func (stream, "<illegal reg q%ld.5>", value >> 1);
3678 else
3679 func (stream, "q%ld", value >> 1);
3680 break;
3681 case 'd':
3682 func (stream, "%ld", value);
05413229 3683 value_in_comment = value;
0313a2b8 3684 break;
6f1c2142
AM		 3685 case 'E':
3686 {
3687 /* Converts immediate 8 bit back to float value. */
3688 unsigned floatVal = (value & 0x80) << 24
3689 | (value & 0x3F) << 19
3690 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
3691
3692 /* Quarter float have a maximum value of 31.0.
3693 Get floating point value multiplied by 1e7.
3694 The maximum value stays in limit of a 32-bit int. */
3695 unsigned decVal =
3696 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
3697 (16 + (value & 0xF));
3698
3699 if (!(decVal % 1000000))
3700 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
3701 floatVal, value & 0x80 ? '-' : ' ',
3702 decVal / 10000000,
3703 decVal % 10000000 / 1000000);
3704 else if (!(decVal % 10000))
3705 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
3706 floatVal, value & 0x80 ? '-' : ' ',
3707 decVal / 10000000,
3708 decVal % 10000000 / 10000);
3709 else
3710 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
3711 floatVal, value & 0x80 ? '-' : ' ',
3712 decVal / 10000000, decVal % 10000000);
3713 break;
3714 }
0313a2b8
NC		 3715 case 'k':
3716 {
3717 int from = (given & (1 << 7)) ? 32 : 16;
3718 func (stream, "%ld", from - value);
3719 }
3720 break;
8f06b2d8 3721
0313a2b8
NC		 3722 case 'f':
3723 if (value > 7)
3724 func (stream, "#%s", arm_fp_const[value & 7]);
3725 else
3726 func (stream, "f%ld", value);
3727 break;
4146fd53 3728
0313a2b8
NC		 3729 case 'w':
3730 if (width == 2)
3731 func (stream, "%s", iwmmxt_wwnames[value]);
3732 else
3733 func (stream, "%s", iwmmxt_wwssnames[value]);
3734 break;
4146fd53 3735
0313a2b8
NC		 3736 case 'g':
3737 func (stream, "%s", iwmmxt_regnames[value]);
3738 break;
3739 case 'G':
3740 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 3741 break;
8f06b2d8 3742
0313a2b8 3743 case 'x':
d1aaab3c 3744 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 3745 break;
8f06b2d8 3746
33399f07
MGD		 3747 case 'c':
3748 switch (value)
3749 {
3750 case 0:
3751 func (stream, "eq");
3752 break;
3753
3754 case 1:
3755 func (stream, "vs");
3756 break;
3757
3758 case 2:
3759 func (stream, "ge");
3760 break;
3761
3762 case 3:
3763 func (stream, "gt");
3764 break;
3765
3766 default:
3767 func (stream, "??");
3768 break;
3769 }
3770 break;
3771
0313a2b8
NC		 3772 case '`':
3773 c++;
3774 if (value == 0)
3775 func (stream, "%c", *c);
3776 break;
3777 case '\'':
3778 c++;
3779 if (value == ((1ul << width) - 1))
3780 func (stream, "%c", *c);
3781 break;
3782 case '?':
fe56b6ce 3783 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 3784 c += 1 << width;
3785 break;
3786 default:
3787 abort ();
3788 }
3789 break;
8f06b2d8 3790
0313a2b8
NC		 3791 case 'y':
3792 case 'z':
3793 {
3794 int single = *c++ == 'y';
3795 int regno;
3796
3797 switch (*c)
3798 {
3799 case '4': /* Sm pair */
3800 case '0': /* Sm, Dm */
3801 regno = given & 0x0000000f;
3802 if (single)
3803 {
3804 regno <<= 1;
3805 regno += (given >> 5) & 1;
16980d0b 3806 }
0313a2b8
NC		 3807 else
3808 regno += ((given >> 5) & 1) << 4;
3809 break;
8f06b2d8 3810
0313a2b8
NC		 3811 case '1': /* Sd, Dd */
3812 regno = (given >> 12) & 0x0000000f;
3813 if (single)
3814 {
3815 regno <<= 1;
3816 regno += (given >> 22) & 1;
3817 }
3818 else
3819 regno += ((given >> 22) & 1) << 4;
3820 break;
8f06b2d8 3821
0313a2b8
NC		 3822 case '2': /* Sn, Dn */
3823 regno = (given >> 16) & 0x0000000f;
3824 if (single)
8f06b2d8 3825 {
0313a2b8
NC		 3826 regno <<= 1;
3827 regno += (given >> 7) & 1;
8f06b2d8 3828 }
0313a2b8
NC		 3829 else
3830 regno += ((given >> 7) & 1) << 4;
3831 break;
7df76b80 3832
0313a2b8
NC		 3833 case '3': /* List */
3834 func (stream, "{");
3835 regno = (given >> 12) & 0x0000000f;
3836 if (single)
3837 {
3838 regno <<= 1;
3839 regno += (given >> 22) & 1;
3840 }
3841 else
3842 regno += ((given >> 22) & 1) << 4;
3843 break;
a7f8487e 3844
0313a2b8
NC		 3845 default:
3846 abort ();
8f06b2d8 3847 }
a7f8487e 3848
0313a2b8
NC		 3849 func (stream, "%c%d", single ? 's' : 'd', regno);
3850
3851 if (*c == '3')
8f06b2d8 3852 {
0313a2b8 3853 int count = given & 0xff;
a7f8487e 3854
0313a2b8
NC		 3855 if (single == 0)
3856 count >>= 1;
b34976b6 3857
0313a2b8 3858 if (--count)
8f06b2d8 3859 {
0313a2b8
NC		 3860 func (stream, "-%c%d",
3861 single ? 's' : 'd',
3862 regno + count);
8f06b2d8 3863 }
0313a2b8
NC		 3864
3865 func (stream, "}");
8f06b2d8 3866 }
0313a2b8
NC		 3867 else if (*c == '4')
3868 func (stream, ", %c%d", single ? 's' : 'd',
3869 regno + 1);
3870 }
3871 break;
3872
3873 case 'L':
3874 switch (given & 0x00400100)
3875 {
3876 case 0x00000000: func (stream, "b"); break;
3877 case 0x00400000: func (stream, "h"); break;
3878 case 0x00000100: func (stream, "w"); break;
3879 case 0x00400100: func (stream, "d"); break;
3880 default:
8f06b2d8 3881 break;
0313a2b8
NC		 3882 }
3883 break;
b34976b6 3884
0313a2b8
NC		 3885 case 'Z':
3886 {
0313a2b8
NC		 3887 /* given (20, 23) | given (0, 3) */
3888 value = ((given >> 16) & 0xf0) | (given & 0xf);
d908c8af 3889 func (stream, "%d", (int) value);
0313a2b8
NC		 3890 }
3891 break;
2d447fca 3892
0313a2b8
NC		 3893 case 'l':
3894 /* This is like the 'A' operator, except that if
3895 the width field "M" is zero, then the offset is
3896 *not* multiplied by four. */
3897 {
3898 int offset = given & 0xff;
3899 int multiplier = (given & 0x00000100) ? 4 : 1;
3900
3901 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3902
05413229
NC		 3903 if (multiplier > 1)
3904 {
3905 value_in_comment = offset * multiplier;
c1e26897 3906 if (NEGATIVE_BIT_SET)
05413229
NC		 3907 value_in_comment = - value_in_comment;
3908 }
3909
0313a2b8
NC		 3910 if (offset)
3911 {
c1e26897 3912 if (PRE_BIT_SET)
0313a2b8 3913 func (stream, ", #%s%d]%s",
c1e26897 3914 NEGATIVE_BIT_SET ? "-" : "",
0313a2b8 3915 offset * multiplier,
c1e26897 3916 WRITEBACK_BIT_SET ? "!" : "");
0313a2b8
NC		 3917 else
3918 func (stream, "], #%s%d",
c1e26897 3919 NEGATIVE_BIT_SET ? "-" : "",
0313a2b8 3920 offset * multiplier);
2d447fca 3921 }
0313a2b8
NC		 3922 else
3923 func (stream, "]");
3924 }
3925 break;
3926
3927 case 'r':
3928 {
3929 int imm4 = (given >> 4) & 0xf;
c1e26897
NC		 3930 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
3931 int ubit = ! NEGATIVE_BIT_SET;
0313a2b8
NC		 3932 const char *rm = arm_regnames [given & 0xf];
3933 const char *rn = arm_regnames [(given >> 16) & 0xf];
2d447fca 3934
0313a2b8 3935 switch (puw_bits)
2d447fca 3936 {
0313a2b8
NC		 3937 case 1:
3938 case 3:
3939 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
3940 if (imm4)
3941 func (stream, ", lsl #%d", imm4);
3942 break;
3943
3944 case 4:
3945 case 5:
3946 case 6:
3947 case 7:
3948 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
3949 if (imm4 > 0)
3950 func (stream, ", lsl #%d", imm4);
3951 func (stream, "]");
3952 if (puw_bits == 5 || puw_bits == 7)
3953 func (stream, "!");
3954 break;
3955
3956 default:
3957 func (stream, "INVALID");
2d447fca 3958 }
0313a2b8
NC		 3959 }
3960 break;
2d447fca 3961
0313a2b8
NC		 3962 case 'i':
3963 {
3964 long imm5;
3965 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
3966 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
8f06b2d8 3967 }
0313a2b8
NC		 3968 break;
3969
3970 default:
3971 abort ();
3972 }
252b5132 3973 }
252b5132 3974 }
0313a2b8
NC		 3975 else
3976 func (stream, "%c", *c);
252b5132 3977 }
05413229
NC		 3978
3979 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 3980 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 3981
ff4a8d2b
NC		 3982 if (is_unpredictable)
3983 func (stream, UNPREDICTABLE_INSTRUCTION);
3984
0313a2b8 3985 return TRUE;
252b5132 3986 }
8f06b2d8 3987 return FALSE;
252b5132
RH		 3988}
3989
05413229
NC		 3990/* Decodes and prints ARM addressing modes. Returns the offset
3991 used in the address, if any, if it is worthwhile printing the
3992 offset as a hexadecimal value in a comment at the end of the
3993 line of disassembly. */
3994
3995static signed long
62b3e311
PB		 3996print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
3997{
3998 void *stream = info->stream;
3999 fprintf_ftype func = info->fprintf_func;
f8b960bc 4000 bfd_vma offset = 0;
62b3e311
PB		 4001
4002 if (((given & 0x000f0000) == 0x000f0000)
4003 && ((given & 0x02000000) == 0))
4004 {
05413229 4005 offset = given & 0xfff;
62b3e311
PB		 4006
4007 func (stream, "[pc");
4008
c1e26897 4009 if (PRE_BIT_SET)
62b3e311 4010 {
26d97720
NS		 4011 /* Pre-indexed. Elide offset of positive zero when
4012 non-writeback. */
4013 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 4014 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 4015
4016 if (NEGATIVE_BIT_SET)
4017 offset = -offset;
62b3e311
PB		 4018
4019 offset += pc + 8;
4020
4021 /* Cope with the possibility of write-back
4022 being used. Probably a very dangerous thing
4023 for the programmer to do, but who are we to
4024 argue ? */
26d97720 4025 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 4026 }
c1e26897 4027 else /* Post indexed. */
62b3e311 4028 {
d908c8af 4029 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 4030
c1e26897 4031 /* Ie ignore the offset. */
62b3e311
PB		 4032 offset = pc + 8;
4033 }
4034
4035 func (stream, "\t; ");
4036 info->print_address_func (offset, info);
05413229 4037 offset = 0;
62b3e311
PB		 4038 }
4039 else
4040 {
4041 func (stream, "[%s",
4042 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 4043
4044 if (PRE_BIT_SET)
62b3e311
PB		 4045 {
4046 if ((given & 0x02000000) == 0)
4047 {
26d97720 4048 /* Elide offset of positive zero when non-writeback. */
05413229 4049 offset = given & 0xfff;
26d97720 4050 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 4051 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 4052 }
4053 else
4054 {
26d97720 4055 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 4056 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 4057 }
4058
4059 func (stream, "]%s",
c1e26897 4060 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 4061 }
4062 else
4063 {
4064 if ((given & 0x02000000) == 0)
4065 {
26d97720 4066 /* Always show offset. */
05413229 4067 offset = given & 0xfff;
26d97720 4068 func (stream, "], #%s%d",
d908c8af 4069 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 4070 }
4071 else
4072 {
4073 func (stream, "], %s",
c1e26897 4074 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 4075 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 4076 }
4077 }
84919466
MR		 4078 if (NEGATIVE_BIT_SET)
4079 offset = -offset;
62b3e311 4080 }
05413229
NC		 4081
4082 return (signed long) offset;
62b3e311
PB		 4083}
4084
16980d0b
JB		 4085/* Print one neon instruction on INFO->STREAM.
4086 Return TRUE if the instuction matched, FALSE if this is not a
4087 recognised neon instruction. */
4088
4089static bfd_boolean
4090print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
4091{
4092 const struct opcode32 *insn;
4093 void *stream = info->stream;
4094 fprintf_ftype func = info->fprintf_func;
4095
4096 if (thumb)
4097 {
4098 if ((given & 0xef000000) == 0xef000000)
4099 {
0313a2b8 4100 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 4101 unsigned long bit28 = given & (1 << 28);
4102
4103 given &= 0x00ffffff;
4104 if (bit28)
4105 given |= 0xf3000000;
4106 else
4107 given |= 0xf2000000;
4108 }
4109 else if ((given & 0xff000000) == 0xf9000000)
4110 given ^= 0xf9000000 ^ 0xf4000000;
4111 else
4112 return FALSE;
4113 }
43e65147 4114
16980d0b
JB		 4115 for (insn = neon_opcodes; insn->assembler; insn++)
4116 {
4117 if ((given & insn->mask) == insn->value)
4118 {
05413229 4119 signed long value_in_comment = 0;
e2efe87d 4120 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 4121 const char *c;
4122
4123 for (c = insn->assembler; *c; c++)
4124 {
4125 if (*c == '%')
4126 {
4127 switch (*++c)
4128 {
4129 case '%':
4130 func (stream, "%%");
4131 break;
4132
e2efe87d
MGD		 4133 case 'u':
4134 if (thumb && ifthen_state)
4135 is_unpredictable = TRUE;
4136
4137 /* Fall through. */
c22aaad1
PB		 4138 case 'c':
4139 if (thumb && ifthen_state)
4140 func (stream, "%s", arm_conditional[IFTHEN_COND]);
4141 break;
4142
16980d0b
JB		 4143 case 'A':
4144 {
43e65147 4145 static const unsigned char enc[16] =
16980d0b
JB		 4146 {
4147 0x4, 0x14, /* st4 0,1 */
4148 0x4, /* st1 2 */
4149 0x4, /* st2 3 */
4150 0x3, /* st3 4 */
4151 0x13, /* st3 5 */
4152 0x3, /* st1 6 */
4153 0x1, /* st1 7 */
4154 0x2, /* st2 8 */
4155 0x12, /* st2 9 */
4156 0x2, /* st1 10 */
4157 0, 0, 0, 0, 0
4158 };
4159 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4160 int rn = ((given >> 16) & 0xf);
4161 int rm = ((given >> 0) & 0xf);
4162 int align = ((given >> 4) & 0x3);
4163 int type = ((given >> 8) & 0xf);
4164 int n = enc[type] & 0xf;
4165 int stride = (enc[type] >> 4) + 1;
4166 int ix;
43e65147 4167
16980d0b
JB		 4168 func (stream, "{");
4169 if (stride > 1)
4170 for (ix = 0; ix != n; ix++)
4171 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
4172 else if (n == 1)
4173 func (stream, "d%d", rd);
4174 else
4175 func (stream, "d%d-d%d", rd, rd + n - 1);
4176 func (stream, "}, [%s", arm_regnames[rn]);
4177 if (align)
8e560766 4178 func (stream, " :%d", 32 << align);
16980d0b
JB		 4179 func (stream, "]");
4180 if (rm == 0xd)
4181 func (stream, "!");
4182 else if (rm != 0xf)
4183 func (stream, ", %s", arm_regnames[rm]);
4184 }
4185 break;
43e65147 4186
16980d0b
JB		 4187 case 'B':
4188 {
4189 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4190 int rn = ((given >> 16) & 0xf);
4191 int rm = ((given >> 0) & 0xf);
4192 int idx_align = ((given >> 4) & 0xf);
4193 int align = 0;
4194 int size = ((given >> 10) & 0x3);
4195 int idx = idx_align >> (size + 1);
4196 int length = ((given >> 8) & 3) + 1;
4197 int stride = 1;
4198 int i;
4199
4200 if (length > 1 && size > 0)
4201 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 4202
16980d0b
JB		 4203 switch (length)
4204 {
4205 case 1:
4206 {
4207 int amask = (1 << size) - 1;
4208 if ((idx_align & (1 << size)) != 0)
4209 return FALSE;
4210 if (size > 0)
4211 {
4212 if ((idx_align & amask) == amask)
4213 align = 8 << size;
4214 else if ((idx_align & amask) != 0)
4215 return FALSE;
4216 }
4217 }
4218 break;
43e65147 4219
16980d0b
JB		 4220 case 2:
4221 if (size == 2 && (idx_align & 2) != 0)
4222 return FALSE;
4223 align = (idx_align & 1) ? 16 << size : 0;
4224 break;
43e65147 4225
16980d0b
JB		 4226 case 3:
4227 if ((size == 2 && (idx_align & 3) != 0)
4228 || (idx_align & 1) != 0)
4229 return FALSE;
4230 break;
43e65147 4231
16980d0b
JB		 4232 case 4:
4233 if (size == 2)
4234 {
4235 if ((idx_align & 3) == 3)
4236 return FALSE;
4237 align = (idx_align & 3) * 64;
4238 }
4239 else
4240 align = (idx_align & 1) ? 32 << size : 0;
4241 break;
43e65147 4242
16980d0b
JB		 4243 default:
4244 abort ();
4245 }
43e65147 4246
16980d0b
JB		 4247 func (stream, "{");
4248 for (i = 0; i < length; i++)
4249 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
4250 rd + i * stride, idx);
4251 func (stream, "}, [%s", arm_regnames[rn]);
4252 if (align)
8e560766 4253 func (stream, " :%d", align);
16980d0b
JB		 4254 func (stream, "]");
4255 if (rm == 0xd)
4256 func (stream, "!");
4257 else if (rm != 0xf)
4258 func (stream, ", %s", arm_regnames[rm]);
4259 }
4260 break;
43e65147 4261
16980d0b
JB		 4262 case 'C':
4263 {
4264 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4265 int rn = ((given >> 16) & 0xf);
4266 int rm = ((given >> 0) & 0xf);
4267 int align = ((given >> 4) & 0x1);
4268 int size = ((given >> 6) & 0x3);
4269 int type = ((given >> 8) & 0x3);
4270 int n = type + 1;
4271 int stride = ((given >> 5) & 0x1);
4272 int ix;
43e65147 4273
16980d0b
JB		 4274 if (stride && (n == 1))
4275 n++;
4276 else
4277 stride++;
43e65147 4278
16980d0b
JB		 4279 func (stream, "{");
4280 if (stride > 1)
4281 for (ix = 0; ix != n; ix++)
4282 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
4283 else if (n == 1)
4284 func (stream, "d%d[]", rd);
4285 else
4286 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
4287 func (stream, "}, [%s", arm_regnames[rn]);
4288 if (align)
4289 {
91d6fa6a 4290 align = (8 * (type + 1)) << size;
16980d0b
JB		 4291 if (type == 3)
4292 align = (size > 1) ? align >> 1 : align;
4293 if (type == 2 || (type == 0 && !size))
8e560766 4294 func (stream, " :<bad align %d>", align);
16980d0b 4295 else
8e560766 4296 func (stream, " :%d", align);
16980d0b
JB		 4297 }
4298 func (stream, "]");
4299 if (rm == 0xd)
4300 func (stream, "!");
4301 else if (rm != 0xf)
4302 func (stream, ", %s", arm_regnames[rm]);
4303 }
4304 break;
43e65147 4305
16980d0b
JB		 4306 case 'D':
4307 {
4308 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
4309 int size = (given >> 20) & 3;
4310 int reg = raw_reg & ((4 << size) - 1);
4311 int ix = raw_reg >> size >> 2;
43e65147 4312
16980d0b
JB		 4313 func (stream, "d%d[%d]", reg, ix);
4314 }
4315 break;
43e65147 4316
16980d0b 4317 case 'E':
fe56b6ce 4318 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 4319 {
4320 int bits = 0;
4321 int cmode = (given >> 8) & 0xf;
4322 int op = (given >> 5) & 0x1;
4323 unsigned long value = 0, hival = 0;
4324 unsigned shift;
4325 int size = 0;
0dbde4cf 4326 int isfloat = 0;
43e65147 4327
16980d0b
JB		 4328 bits |= ((given >> 24) & 1) << 7;
4329 bits |= ((given >> 16) & 7) << 4;
4330 bits |= ((given >> 0) & 15) << 0;
43e65147 4331
16980d0b
JB		 4332 if (cmode < 8)
4333 {
4334 shift = (cmode >> 1) & 3;
fe56b6ce 4335 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4336 size = 32;
4337 }
4338 else if (cmode < 12)
4339 {
4340 shift = (cmode >> 1) & 1;
fe56b6ce 4341 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4342 size = 16;
4343 }
4344 else if (cmode < 14)
4345 {
4346 shift = (cmode & 1) + 1;
fe56b6ce 4347 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4348 value |= (1ul << (8 * shift)) - 1;
4349 size = 32;
4350 }
4351 else if (cmode == 14)
4352 {
4353 if (op)
4354 {
fe56b6ce 4355 /* Bit replication into bytes. */
16980d0b
JB		 4356 int ix;
4357 unsigned long mask;
43e65147 4358
16980d0b
JB		 4359 value = 0;
4360 hival = 0;
4361 for (ix = 7; ix >= 0; ix--)
4362 {
4363 mask = ((bits >> ix) & 1) ? 0xff : 0;
4364 if (ix <= 3)
4365 value = (value << 8) | mask;
4366 else
4367 hival = (hival << 8) | mask;
4368 }
4369 size = 64;
4370 }
4371 else
4372 {
fe56b6ce
NC		 4373 /* Byte replication. */
4374 value = (unsigned long) bits;
16980d0b
JB		 4375 size = 8;
4376 }
4377 }
4378 else if (!op)
4379 {
fe56b6ce 4380 /* Floating point encoding. */
16980d0b 4381 int tmp;
43e65147 4382
fe56b6ce
NC		 4383 value = (unsigned long) (bits & 0x7f) << 19;
4384 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 4385 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 4386 value |= (unsigned long) tmp << 24;
16980d0b 4387 size = 32;
0dbde4cf 4388 isfloat = 1;
16980d0b
JB		 4389 }
4390 else
4391 {
4392 func (stream, "<illegal constant %.8x:%x:%x>",
4393 bits, cmode, op);
4394 size = 32;
4395 break;
4396 }
4397 switch (size)
4398 {
4399 case 8:
4400 func (stream, "#%ld\t; 0x%.2lx", value, value);
4401 break;
43e65147 4402
16980d0b
JB		 4403 case 16:
4404 func (stream, "#%ld\t; 0x%.4lx", value, value);
4405 break;
4406
4407 case 32:
0dbde4cf
JB		 4408 if (isfloat)
4409 {
4410 unsigned char valbytes[4];
4411 double fvalue;
43e65147 4412
0dbde4cf
JB		 4413 /* Do this a byte at a time so we don't have to
4414 worry about the host's endianness. */
4415 valbytes[0] = value & 0xff;
4416 valbytes[1] = (value >> 8) & 0xff;
4417 valbytes[2] = (value >> 16) & 0xff;
4418 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 4419
4420 floatformat_to_double
c1e26897
NC		 4421 (& floatformat_ieee_single_little, valbytes,
4422 & fvalue);
43e65147 4423
0dbde4cf
JB		 4424 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
4425 value);
4426 }
4427 else
4e9d3b81 4428 func (stream, "#%ld\t; 0x%.8lx",
43e65147 4429 (long) (((value & 0x80000000L) != 0)
9d82ec38 4430 ? value | ~0xffffffffL : value),
c1e26897 4431 value);
16980d0b
JB		 4432 break;
4433
4434 case 64:
4435 func (stream, "#0x%.8lx%.8lx", hival, value);
4436 break;
43e65147 4437
16980d0b
JB		 4438 default:
4439 abort ();
4440 }
4441 }
4442 break;
43e65147 4443
16980d0b
JB		 4444 case 'F':
4445 {
4446 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
4447 int num = (given >> 8) & 0x3;
43e65147 4448
16980d0b
JB		 4449 if (!num)
4450 func (stream, "{d%d}", regno);
4451 else if (num + regno >= 32)
4452 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
4453 else
4454 func (stream, "{d%d-d%d}", regno, regno + num);
4455 }
4456 break;
7e8e6784 4457
16980d0b
JB		 4458
4459 case '0': case '1': case '2': case '3': case '4':
4460 case '5': case '6': case '7': case '8': case '9':
4461 {
4462 int width;
4463 unsigned long value;
4464
4465 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 4466
16980d0b
JB		 4467 switch (*c)
4468 {
4469 case 'r':
4470 func (stream, "%s", arm_regnames[value]);
4471 break;
4472 case 'd':
4473 func (stream, "%ld", value);
05413229 4474 value_in_comment = value;
16980d0b
JB		 4475 break;
4476 case 'e':
4477 func (stream, "%ld", (1ul << width) - value);
4478 break;
43e65147 4479
16980d0b
JB		 4480 case 'S':
4481 case 'T':
4482 case 'U':
05413229 4483 /* Various width encodings. */
16980d0b
JB		 4484 {
4485 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
4486 int limit;
4487 unsigned low, high;
4488
4489 c++;
4490 if (*c >= '0' && *c <= '9')
4491 limit = *c - '0';
4492 else if (*c >= 'a' && *c <= 'f')
4493 limit = *c - 'a' + 10;
4494 else
4495 abort ();
4496 low = limit >> 2;
4497 high = limit & 3;
4498
4499 if (value < low || value > high)
4500 func (stream, "<illegal width %d>", base << value);
4501 else
4502 func (stream, "%d", base << value);
4503 }
4504 break;
4505 case 'R':
4506 if (given & (1 << 6))
4507 goto Q;
4508 /* FALLTHROUGH */
4509 case 'D':
4510 func (stream, "d%ld", value);
4511 break;
4512 case 'Q':
4513 Q:
4514 if (value & 1)
4515 func (stream, "<illegal reg q%ld.5>", value >> 1);
4516 else
4517 func (stream, "q%ld", value >> 1);
4518 break;
43e65147 4519
16980d0b
JB		 4520 case '`':
4521 c++;
4522 if (value == 0)
4523 func (stream, "%c", *c);
4524 break;
4525 case '\'':
4526 c++;
4527 if (value == ((1ul << width) - 1))
4528 func (stream, "%c", *c);
4529 break;
4530 case '?':
fe56b6ce 4531 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 4532 c += 1 << width;
4533 break;
4534 default:
4535 abort ();
4536 }
4537 break;
4538
4539 default:
4540 abort ();
4541 }
4542 }
4543 }
4544 else
4545 func (stream, "%c", *c);
4546 }
05413229
NC		 4547
4548 if (value_in_comment > 32 || value_in_comment < -16)
4549 func (stream, "\t; 0x%lx", value_in_comment);
4550
e2efe87d
MGD		 4551 if (is_unpredictable)
4552 func (stream, UNPREDICTABLE_INSTRUCTION);
4553
16980d0b
JB		 4554 return TRUE;
4555 }
4556 }
4557 return FALSE;
4558}
4559
90ec0d68
MGD		 4560/* Return the name of a v7A special register. */
4561
43e65147 4562static const char *
90ec0d68
MGD		 4563banked_regname (unsigned reg)
4564{
4565 switch (reg)
4566 {
4567 case 15: return "CPSR";
43e65147 4568 case 32: return "R8_usr";
90ec0d68
MGD		 4569 case 33: return "R9_usr";
4570 case 34: return "R10_usr";
4571 case 35: return "R11_usr";
4572 case 36: return "R12_usr";
4573 case 37: return "SP_usr";
4574 case 38: return "LR_usr";
43e65147 4575 case 40: return "R8_fiq";
90ec0d68
MGD		 4576 case 41: return "R9_fiq";
4577 case 42: return "R10_fiq";
4578 case 43: return "R11_fiq";
4579 case 44: return "R12_fiq";
4580 case 45: return "SP_fiq";
4581 case 46: return "LR_fiq";
4582 case 48: return "LR_irq";
4583 case 49: return "SP_irq";
4584 case 50: return "LR_svc";
4585 case 51: return "SP_svc";
4586 case 52: return "LR_abt";
4587 case 53: return "SP_abt";
4588 case 54: return "LR_und";
4589 case 55: return "SP_und";
4590 case 60: return "LR_mon";
4591 case 61: return "SP_mon";
4592 case 62: return "ELR_hyp";
4593 case 63: return "SP_hyp";
4594 case 79: return "SPSR";
4595 case 110: return "SPSR_fiq";
4596 case 112: return "SPSR_irq";
4597 case 114: return "SPSR_svc";
4598 case 116: return "SPSR_abt";
4599 case 118: return "SPSR_und";
4600 case 124: return "SPSR_mon";
4601 case 126: return "SPSR_hyp";
4602 default: return NULL;
4603 }
4604}
4605
e797f7e0
MGD		 4606/* Return the name of the DMB/DSB option. */
4607static const char *
4608data_barrier_option (unsigned option)
4609{
4610 switch (option & 0xf)
4611 {
4612 case 0xf: return "sy";
4613 case 0xe: return "st";
4614 case 0xd: return "ld";
4615 case 0xb: return "ish";
4616 case 0xa: return "ishst";
4617 case 0x9: return "ishld";
4618 case 0x7: return "un";
4619 case 0x6: return "unst";
4620 case 0x5: return "nshld";
4621 case 0x3: return "osh";
4622 case 0x2: return "oshst";
4623 case 0x1: return "oshld";
4624 default: return NULL;
4625 }
4626}
4627
4a5329c6
ZW		 4628/* Print one ARM instruction from PC on INFO->STREAM. */
4629
4630static void
4631print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 4632{
6b5d3a4d 4633 const struct opcode32 *insn;
6a51a8a8 4634 void *stream = info->stream;
6b5d3a4d 4635 fprintf_ftype func = info->fprintf_func;
b0e28b39 4636 struct arm_private_data *private_data = info->private_data;
252b5132 4637
16980d0b
JB		 4638 if (print_insn_coprocessor (pc, info, given, FALSE))
4639 return;
4640
4641 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 4642 return;
4643
252b5132
RH		 4644 for (insn = arm_opcodes; insn->assembler; insn++)
4645 {
0313a2b8
NC		 4646 if ((given & insn->mask) != insn->value)
4647 continue;
823d2571
TG		 4648
4649 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 4650 continue;
4651
4652 /* Special case: an instruction with all bits set in the condition field
4653 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
4654 or by the catchall at the end of the table. */
4655 if ((given & 0xF0000000) != 0xF0000000
4656 || (insn->mask & 0xF0000000) == 0xF0000000
4657 || (insn->mask == 0 && insn->value == 0))
252b5132 4658 {
ff4a8d2b
NC		 4659 unsigned long u_reg = 16;
4660 unsigned long U_reg = 16;
ab8e2090 4661 bfd_boolean is_unpredictable = FALSE;
05413229 4662 signed long value_in_comment = 0;
6b5d3a4d 4663 const char *c;
b34976b6 4664
252b5132
RH		 4665 for (c = insn->assembler; *c; c++)
4666 {
4667 if (*c == '%')
4668 {
c1e26897
NC		 4669 bfd_boolean allow_unpredictable = FALSE;
4670
252b5132
RH		 4671 switch (*++c)
4672 {
4673 case '%':
4674 func (stream, "%%");
4675 break;
4676
4677 case 'a':
05413229 4678 value_in_comment = print_arm_address (pc, info, given);
62b3e311 4679 break;
252b5132 4680
62b3e311
PB		 4681 case 'P':
4682 /* Set P address bit and use normal address
4683 printing routine. */
c1e26897 4684 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 4685 break;
4686
c1e26897
NC		 4687 case 'S':
4688 allow_unpredictable = TRUE;
1a0670f3 4689 /* Fall through. */
252b5132
RH		 4690 case 's':
4691 if ((given & 0x004f0000) == 0x004f0000)
4692 {
58efb6c0 4693 /* PC relative with immediate offset. */
f8b960bc 4694 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 4695
aefd8a40
NC		 4696 if (PRE_BIT_SET)
4697 {
26d97720
NS		 4698 /* Elide positive zero offset. */
4699 if (offset || NEGATIVE_BIT_SET)
4700 func (stream, "[pc, #%s%d]\t; ",
d908c8af 4701 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 4702 else
26d97720
NS		 4703 func (stream, "[pc]\t; ");
4704 if (NEGATIVE_BIT_SET)
4705 offset = -offset;
aefd8a40
NC		 4706 info->print_address_func (offset + pc + 8, info);
4707 }
4708 else
4709 {
26d97720
NS		 4710 /* Always show the offset. */
4711 func (stream, "[pc], #%s%d",
d908c8af 4712 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 4713 if (! allow_unpredictable)
4714 is_unpredictable = TRUE;
aefd8a40 4715 }
252b5132
RH		 4716 }
4717 else
4718 {
fe56b6ce
NC		 4719 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
4720
b34976b6 4721 func (stream, "[%s",
252b5132 4722 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 4723
c1e26897 4724 if (PRE_BIT_SET)
252b5132 4725 {
c1e26897 4726 if (IMMEDIATE_BIT_SET)
252b5132 4727 {
26d97720
NS		 4728 /* Elide offset for non-writeback
4729 positive zero. */
4730 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
4731 || offset)
4732 func (stream, ", #%s%d",
4733 NEGATIVE_BIT_SET ? "-" : "", offset);
4734
4735 if (NEGATIVE_BIT_SET)
4736 offset = -offset;
945ee430 4737
fe56b6ce 4738 value_in_comment = offset;
252b5132 4739 }
945ee430 4740 else
ff4a8d2b
NC		 4741 {
4742 /* Register Offset or Register Pre-Indexed. */
4743 func (stream, ", %s%s",
4744 NEGATIVE_BIT_SET ? "-" : "",
4745 arm_regnames[given & 0xf]);
4746
4747 /* Writing back to the register that is the source/
4748 destination of the load/store is unpredictable. */
4749 if (! allow_unpredictable
4750 && WRITEBACK_BIT_SET
4751 && ((given & 0xf) == ((given >> 12) & 0xf)))
4752 is_unpredictable = TRUE;
4753 }
252b5132 4754
b34976b6 4755 func (stream, "]%s",
c1e26897 4756 WRITEBACK_BIT_SET ? "!" : "");
252b5132 4757 }
945ee430 4758 else
252b5132 4759 {
c1e26897 4760 if (IMMEDIATE_BIT_SET)
252b5132 4761 {
945ee430 4762 /* Immediate Post-indexed. */
aefd8a40 4763 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 4764 func (stream, "], #%s%d",
4765 NEGATIVE_BIT_SET ? "-" : "", offset);
4766 if (NEGATIVE_BIT_SET)
4767 offset = -offset;
fe56b6ce 4768 value_in_comment = offset;
252b5132 4769 }
945ee430 4770 else
ff4a8d2b
NC		 4771 {
4772 /* Register Post-indexed. */
4773 func (stream, "], %s%s",
4774 NEGATIVE_BIT_SET ? "-" : "",
4775 arm_regnames[given & 0xf]);
4776
4777 /* Writing back to the register that is the source/
4778 destination of the load/store is unpredictable. */
4779 if (! allow_unpredictable
4780 && (given & 0xf) == ((given >> 12) & 0xf))
4781 is_unpredictable = TRUE;
4782 }
c1e26897 4783
07a28fab
NC		 4784 if (! allow_unpredictable)
4785 {
4786 /* Writeback is automatically implied by post- addressing.
4787 Setting the W bit is unnecessary and ARM specify it as
4788 being unpredictable. */
4789 if (WRITEBACK_BIT_SET
4790 /* Specifying the PC register as the post-indexed
4791 registers is also unpredictable. */
ab8e2090
NC		 4792 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
4793 is_unpredictable = TRUE;
07a28fab 4794 }
252b5132
RH		 4795 }
4796 }
4797 break;
b34976b6 4798
252b5132 4799 case 'b':
6b5d3a4d 4800 {
f8b960bc 4801 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
05413229 4802 info->print_address_func (disp * 4 + pc + 8, info);
6b5d3a4d 4803 }
252b5132
RH		 4804 break;
4805
4806 case 'c':
c22aaad1
PB		 4807 if (((given >> 28) & 0xf) != 0xe)
4808 func (stream, "%s",
4809 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 4810 break;
4811
4812 case 'm':
4813 {
4814 int started = 0;
4815 int reg;
4816
4817 func (stream, "{");
4818 for (reg = 0; reg < 16; reg++)
4819 if ((given & (1 << reg)) != 0)
4820 {
4821 if (started)
4822 func (stream, ", ");
4823 started = 1;
4824 func (stream, "%s", arm_regnames[reg]);
4825 }
4826 func (stream, "}");
ab8e2090
NC		 4827 if (! started)
4828 is_unpredictable = TRUE;
252b5132
RH		 4829 }
4830 break;
4831
37b37b2d 4832 case 'q':
78c66db8 4833 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 4834 break;
4835
252b5132
RH		 4836 case 'o':
4837 if ((given & 0x02000000) != 0)
4838 {
a415b1cd
JB		 4839 unsigned int rotate = (given & 0xf00) >> 7;
4840 unsigned int immed = (given & 0xff);
4841 unsigned int a, i;
4842
4843 a = (((immed << (32 - rotate))
4844 | (immed >> rotate)) & 0xffffffff);
4845 /* If there is another encoding with smaller rotate,
4846 the rotate should be specified directly. */
4847 for (i = 0; i < 32; i += 2)
4848 if ((a << i | a >> (32 - i)) <= 0xff)
4849 break;
4850
4851 if (i != rotate)
4852 func (stream, "#%d, %d", immed, rotate);
4853 else
4854 func (stream, "#%d", a);
4855 value_in_comment = a;
252b5132
RH		 4856 }
4857 else
78c66db8 4858 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 4859 break;
4860
4861 case 'p':
4862 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 4863 {
823d2571
TG		 4864 arm_feature_set arm_ext_v6 =
4865 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
4866
aefd8a40
NC		 4867 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
4868 mechanism for setting PSR flag bits. They are
4869 obsolete in V6 onwards. */
823d2571
TG		 4870 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
4871 arm_ext_v6))
aefd8a40 4872 func (stream, "p");
4ab90a7a
AV		 4873 else
4874 is_unpredictable = TRUE;
aefd8a40 4875 }
252b5132
RH		 4876 break;
4877
4878 case 't':
4879 if ((given & 0x01200000) == 0x00200000)
4880 func (stream, "t");
4881 break;
4882
252b5132 4883 case 'A':
05413229
NC		 4884 {
4885 int offset = given & 0xff;
f02232aa 4886
05413229 4887 value_in_comment = offset * 4;
c1e26897 4888 if (NEGATIVE_BIT_SET)
05413229 4889 value_in_comment = - value_in_comment;
f02232aa 4890
05413229 4891 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 4892
c1e26897 4893 if (PRE_BIT_SET)
05413229
NC		 4894 {
4895 if (offset)
fe56b6ce 4896 func (stream, ", #%d]%s",
d908c8af 4897 (int) value_in_comment,
c1e26897 4898 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 4899 else
4900 func (stream, "]");
4901 }
4902 else
4903 {
4904 func (stream, "]");
f02232aa 4905
c1e26897 4906 if (WRITEBACK_BIT_SET)
05413229
NC		 4907 {
4908 if (offset)
d908c8af 4909 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 4910 }
4911 else
fe56b6ce 4912 {
d908c8af 4913 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 4914 value_in_comment = offset;
4915 }
05413229
NC		 4916 }
4917 }
252b5132
RH		 4918 break;
4919
077b8428
NC		 4920 case 'B':
4921 /* Print ARM V5 BLX(1) address: pc+25 bits. */
4922 {
4923 bfd_vma address;
4924 bfd_vma offset = 0;
b34976b6 4925
c1e26897 4926 if (! NEGATIVE_BIT_SET)
077b8428
NC		 4927 /* Is signed, hi bits should be ones. */
4928 offset = (-1) ^ 0x00ffffff;
4929
4930 /* Offset is (SignExtend(offset field)<<2). */
4931 offset += given & 0x00ffffff;
4932 offset <<= 2;
4933 address = offset + pc + 8;
b34976b6 4934
8f06b2d8
PB		 4935 if (given & 0x01000000)
4936 /* H bit allows addressing to 2-byte boundaries. */
4937 address += 2;
b1ee46c5 4938
8f06b2d8 4939 info->print_address_func (address, info);
b1ee46c5 4940 }
b1ee46c5
AH		 4941 break;
4942
252b5132 4943 case 'C':
90ec0d68
MGD		 4944 if ((given & 0x02000200) == 0x200)
4945 {
4946 const char * name;
4947 unsigned sysm = (given & 0x004f0000) >> 16;
4948
4949 sysm |= (given & 0x300) >> 4;
4950 name = banked_regname (sysm);
4951
4952 if (name != NULL)
4953 func (stream, "%s", name);
4954 else
d908c8af 4955 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 4956 }
4957 else
4958 {
43e65147 4959 func (stream, "%cPSR_",
90ec0d68
MGD		 4960 (given & 0x00400000) ? 'S' : 'C');
4961 if (given & 0x80000)
4962 func (stream, "f");
4963 if (given & 0x40000)
4964 func (stream, "s");
4965 if (given & 0x20000)
4966 func (stream, "x");
4967 if (given & 0x10000)
4968 func (stream, "c");
4969 }
252b5132
RH		 4970 break;
4971
62b3e311 4972 case 'U':
43e65147 4973 if ((given & 0xf0) == 0x60)
62b3e311 4974 {
52e7f43d
RE		 4975 switch (given & 0xf)
4976 {
4977 case 0xf: func (stream, "sy"); break;
4978 default:
4979 func (stream, "#%d", (int) given & 0xf);
4980 break;
4981 }
43e65147
L		 4982 }
4983 else
52e7f43d 4984 {
e797f7e0
MGD		 4985 const char * opt = data_barrier_option (given & 0xf);
4986 if (opt != NULL)
4987 func (stream, "%s", opt);
4988 else
52e7f43d 4989 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 4990 }
4991 break;
4992
b34976b6 4993 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 4994 case '5': case '6': case '7': case '8': case '9':
4995 {
16980d0b
JB		 4996 int width;
4997 unsigned long value;
252b5132 4998
16980d0b 4999 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 5000
252b5132
RH		 5001 switch (*c)
5002 {
ab8e2090
NC		 5003 case 'R':
5004 if (value == 15)
5005 is_unpredictable = TRUE;
5006 /* Fall through. */
16980d0b 5007 case 'r':
9eb6c0f1
MGD		 5008 case 'T':
5009 /* We want register + 1 when decoding T. */
5010 if (*c == 'T')
5011 ++value;
5012
ff4a8d2b
NC		 5013 if (c[1] == 'u')
5014 {
5015 /* Eat the 'u' character. */
5016 ++ c;
5017
5018 if (u_reg == value)
5019 is_unpredictable = TRUE;
5020 u_reg = value;
5021 }
5022 if (c[1] == 'U')
5023 {
5024 /* Eat the 'U' character. */
5025 ++ c;
5026
5027 if (U_reg == value)
5028 is_unpredictable = TRUE;
5029 U_reg = value;
5030 }
16980d0b
JB		 5031 func (stream, "%s", arm_regnames[value]);
5032 break;
5033 case 'd':
5034 func (stream, "%ld", value);
05413229 5035 value_in_comment = value;
16980d0b
JB		 5036 break;
5037 case 'b':
5038 func (stream, "%ld", value * 8);
05413229 5039 value_in_comment = value * 8;
16980d0b
JB		 5040 break;
5041 case 'W':
5042 func (stream, "%ld", value + 1);
05413229 5043 value_in_comment = value + 1;
16980d0b
JB		 5044 break;
5045 case 'x':
5046 func (stream, "0x%08lx", value);
5047
5048 /* Some SWI instructions have special
5049 meanings. */
5050 if ((given & 0x0fffffff) == 0x0FF00000)
5051 func (stream, "\t; IMB");
5052 else if ((given & 0x0fffffff) == 0x0FF00001)
5053 func (stream, "\t; IMBRange");
5054 break;
5055 case 'X':
5056 func (stream, "%01lx", value & 0xf);
05413229 5057 value_in_comment = value;
252b5132
RH		 5058 break;
5059 case '`':
5060 c++;
16980d0b 5061 if (value == 0)
252b5132
RH		 5062 func (stream, "%c", *c);
5063 break;
5064 case '\'':
5065 c++;
16980d0b 5066 if (value == ((1ul << width) - 1))
252b5132
RH		 5067 func (stream, "%c", *c);
5068 break;
5069 case '?':
fe56b6ce 5070 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 5071 c += 1 << width;
252b5132
RH		 5072 break;
5073 default:
5074 abort ();
5075 }
5076 break;
5077
0dd132b6
NC		 5078 case 'e':
5079 {
5080 int imm;
5081
5082 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
5083 func (stream, "%d", imm);
fe56b6ce 5084 value_in_comment = imm;
0dd132b6
NC		 5085 }
5086 break;
5087
0a003adc
ZW		 5088 case 'E':
5089 /* LSB and WIDTH fields of BFI or BFC. The machine-
5090 language instruction encodes LSB and MSB. */
5091 {
5092 long msb = (given & 0x001f0000) >> 16;
5093 long lsb = (given & 0x00000f80) >> 7;
91d6fa6a 5094 long w = msb - lsb + 1;
fe56b6ce 5095
91d6fa6a
NC		 5096 if (w > 0)
5097 func (stream, "#%lu, #%lu", lsb, w);
0a003adc
ZW		 5098 else
5099 func (stream, "(invalid: %lu:%lu)", lsb, msb);
5100 }
5101 break;
5102
90ec0d68
MGD		 5103 case 'R':
5104 /* Get the PSR/banked register name. */
5105 {
5106 const char * name;
5107 unsigned sysm = (given & 0x004f0000) >> 16;
5108
5109 sysm |= (given & 0x300) >> 4;
5110 name = banked_regname (sysm);
5111
5112 if (name != NULL)
5113 func (stream, "%s", name);
5114 else
d908c8af 5115 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 5116 }
5117 break;
5118
0a003adc
ZW		 5119 case 'V':
5120 /* 16-bit unsigned immediate from a MOVT or MOVW
5121 instruction, encoded in bits 0:11 and 15:19. */
5122 {
5123 long hi = (given & 0x000f0000) >> 4;
5124 long lo = (given & 0x00000fff);
5125 long imm16 = hi | lo;
fe56b6ce
NC		 5126
5127 func (stream, "#%lu", imm16);
5128 value_in_comment = imm16;
0a003adc
ZW		 5129 }
5130 break;
5131
252b5132
RH		 5132 default:
5133 abort ();
5134 }
5135 }
5136 }
5137 else
5138 func (stream, "%c", *c);
5139 }
05413229
NC		 5140
5141 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 5142 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 5143
5144 if (is_unpredictable)
5145 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 5146
4a5329c6 5147 return;
252b5132
RH		 5148 }
5149 }
5150 abort ();
5151}
5152
4a5329c6 5153/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 5154
4a5329c6
ZW		 5155static void
5156print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 5157{
6b5d3a4d 5158 const struct opcode16 *insn;
6a51a8a8
AM		 5159 void *stream = info->stream;
5160 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 5161
5162 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 5163 if ((given & insn->mask) == insn->value)
5164 {
05413229 5165 signed long value_in_comment = 0;
6b5d3a4d 5166 const char *c = insn->assembler;
05413229 5167
c19d1205
ZW		 5168 for (; *c; c++)
5169 {
5170 int domaskpc = 0;
5171 int domasklr = 0;
5172
5173 if (*c != '%')
5174 {
5175 func (stream, "%c", *c);
5176 continue;
5177 }
252b5132 5178
c19d1205
ZW		 5179 switch (*++c)
5180 {
5181 case '%':
5182 func (stream, "%%");
5183 break;
b34976b6 5184
c22aaad1
PB		 5185 case 'c':
5186 if (ifthen_state)
5187 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5188 break;
5189
5190 case 'C':
5191 if (ifthen_state)
5192 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5193 else
5194 func (stream, "s");
5195 break;
5196
5197 case 'I':
5198 {
5199 unsigned int tmp;
5200
5201 ifthen_next_state = given & 0xff;
5202 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
5203 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
5204 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
5205 }
5206 break;
5207
5208 case 'x':
5209 if (ifthen_next_state)
5210 func (stream, "\t; unpredictable branch in IT block\n");
5211 break;
5212
5213 case 'X':
5214 if (ifthen_state)
5215 func (stream, "\t; unpredictable <IT:%s>",
5216 arm_conditional[IFTHEN_COND]);
5217 break;
5218
c19d1205
ZW		 5219 case 'S':
5220 {
5221 long reg;
5222
5223 reg = (given >> 3) & 0x7;
5224 if (given & (1 << 6))
5225 reg += 8;
4f3c3dbb 5226
c19d1205
ZW		 5227 func (stream, "%s", arm_regnames[reg]);
5228 }
5229 break;
baf0cc5e 5230
c19d1205 5231 case 'D':
4f3c3dbb 5232 {
c19d1205
ZW		 5233 long reg;
5234
5235 reg = given & 0x7;
5236 if (given & (1 << 7))
5237 reg += 8;
5238
5239 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 5240 }
c19d1205
ZW		 5241 break;
5242
5243 case 'N':
5244 if (given & (1 << 8))
5245 domasklr = 1;
5246 /* Fall through. */
5247 case 'O':
5248 if (*c == 'O' && (given & (1 << 8)))
5249 domaskpc = 1;
5250 /* Fall through. */
5251 case 'M':
5252 {
5253 int started = 0;
5254 int reg;
5255
5256 func (stream, "{");
5257
5258 /* It would be nice if we could spot
5259 ranges, and generate the rS-rE format: */
5260 for (reg = 0; (reg < 8); reg++)
5261 if ((given & (1 << reg)) != 0)
5262 {
5263 if (started)
5264 func (stream, ", ");
5265 started = 1;
5266 func (stream, "%s", arm_regnames[reg]);
5267 }
5268
5269 if (domasklr)
5270 {
5271 if (started)
5272 func (stream, ", ");
5273 started = 1;
d908c8af 5274 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 5275 }
5276
5277 if (domaskpc)
5278 {
5279 if (started)
5280 func (stream, ", ");
d908c8af 5281 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 5282 }
5283
5284 func (stream, "}");
5285 }
5286 break;
5287
4547cb56
NC		 5288 case 'W':
5289 /* Print writeback indicator for a LDMIA. We are doing a
5290 writeback if the base register is not in the register
5291 mask. */
5292 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
5293 func (stream, "!");
5294 break;
5295
c19d1205
ZW		 5296 case 'b':
5297 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
5298 {
5299 bfd_vma address = (pc + 4
5300 + ((given & 0x00f8) >> 2)
5301 + ((given & 0x0200) >> 3));
5302 info->print_address_func (address, info);
5303 }
5304 break;
5305
5306 case 's':
5307 /* Right shift immediate -- bits 6..10; 1-31 print
5308 as themselves, 0 prints as 32. */
5309 {
5310 long imm = (given & 0x07c0) >> 6;
5311 if (imm == 0)
5312 imm = 32;
0fd3a477 5313 func (stream, "#%ld", imm);
c19d1205
ZW		 5314 }
5315 break;
5316
5317 case '0': case '1': case '2': case '3': case '4':
5318 case '5': case '6': case '7': case '8': case '9':
5319 {
5320 int bitstart = *c++ - '0';
5321 int bitend = 0;
5322
5323 while (*c >= '0' && *c <= '9')
5324 bitstart = (bitstart * 10) + *c++ - '0';
5325
5326 switch (*c)
5327 {
5328 case '-':
5329 {
f8b960bc 5330 bfd_vma reg;
c19d1205
ZW		 5331
5332 c++;
5333 while (*c >= '0' && *c <= '9')
5334 bitend = (bitend * 10) + *c++ - '0';
5335 if (!bitend)
5336 abort ();
5337 reg = given >> bitstart;
5338 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 5339
c19d1205
ZW		 5340 switch (*c)
5341 {
5342 case 'r':
5343 func (stream, "%s", arm_regnames[reg]);
5344 break;
5345
5346 case 'd':
d908c8af 5347 func (stream, "%ld", (long) reg);
05413229 5348 value_in_comment = reg;
c19d1205
ZW		 5349 break;
5350
5351 case 'H':
d908c8af 5352 func (stream, "%ld", (long) (reg << 1));
05413229 5353 value_in_comment = reg << 1;
c19d1205
ZW		 5354 break;
5355
5356 case 'W':
d908c8af 5357 func (stream, "%ld", (long) (reg << 2));
05413229 5358 value_in_comment = reg << 2;
c19d1205
ZW		 5359 break;
5360
5361 case 'a':
5362 /* PC-relative address -- the bottom two
5363 bits of the address are dropped
5364 before the calculation. */
5365 info->print_address_func
5366 (((pc + 4) & ~3) + (reg << 2), info);
05413229 5367 value_in_comment = 0;
c19d1205
ZW		 5368 break;
5369
5370 case 'x':
d908c8af 5371 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 5372 break;
5373
c19d1205
ZW		 5374 case 'B':
5375 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6b5d3a4d 5376 info->print_address_func (reg * 2 + pc + 4, info);
05413229 5377 value_in_comment = 0;
c19d1205
ZW		 5378 break;
5379
5380 case 'c':
c22aaad1 5381 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 5382 break;
5383
5384 default:
5385 abort ();
5386 }
5387 }
5388 break;
5389
5390 case '\'':
5391 c++;
5392 if ((given & (1 << bitstart)) != 0)
5393 func (stream, "%c", *c);
5394 break;
5395
5396 case '?':
5397 ++c;
5398 if ((given & (1 << bitstart)) != 0)
5399 func (stream, "%c", *c++);
5400 else
5401 func (stream, "%c", *++c);
5402 break;
5403
5404 default:
5405 abort ();
5406 }
5407 }
5408 break;
5409
5410 default:
5411 abort ();
5412 }
5413 }
05413229
NC		 5414
5415 if (value_in_comment > 32 || value_in_comment < -16)
5416 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 5417 return;
c19d1205
ZW		 5418 }
5419
5420 /* No match. */
5421 abort ();
5422}
5423
62b3e311 5424/* Return the name of an V7M special register. */
fe56b6ce 5425
62b3e311
PB		 5426static const char *
5427psr_name (int regno)
5428{
5429 switch (regno)
5430 {
1a336194
TP		 5431 case 0x0: return "APSR";
5432 case 0x1: return "IAPSR";
5433 case 0x2: return "EAPSR";
5434 case 0x3: return "PSR";
5435 case 0x5: return "IPSR";
5436 case 0x6: return "EPSR";
5437 case 0x7: return "IEPSR";
5438 case 0x8: return "MSP";
5439 case 0x9: return "PSP";
5440 case 0xa: return "MSPLIM";
5441 case 0xb: return "PSPLIM";
5442 case 0x10: return "PRIMASK";
5443 case 0x11: return "BASEPRI";
5444 case 0x12: return "BASEPRI_MAX";
5445 case 0x13: return "FAULTMASK";
5446 case 0x14: return "CONTROL";
16a1fa25
TP		 5447 case 0x88: return "MSP_NS";
5448 case 0x89: return "PSP_NS";
1a336194
TP		 5449 case 0x8a: return "MSPLIM_NS";
5450 case 0x8b: return "PSPLIM_NS";
5451 case 0x90: return "PRIMASK_NS";
5452 case 0x91: return "BASEPRI_NS";
5453 case 0x93: return "FAULTMASK_NS";
5454 case 0x94: return "CONTROL_NS";
5455 case 0x98: return "SP_NS";
62b3e311
PB		 5456 default: return "<unknown>";
5457 }
5458}
5459
4a5329c6
ZW		 5460/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
5461
5462static void
5463print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 5464{
6b5d3a4d 5465 const struct opcode32 *insn;
c19d1205
ZW		 5466 void *stream = info->stream;
5467 fprintf_ftype func = info->fprintf_func;
5468
16980d0b
JB		 5469 if (print_insn_coprocessor (pc, info, given, TRUE))
5470 return;
5471
5472 if (print_insn_neon (info, given, TRUE))
8f06b2d8
PB		 5473 return;
5474
c19d1205
ZW		 5475 for (insn = thumb32_opcodes; insn->assembler; insn++)
5476 if ((given & insn->mask) == insn->value)
5477 {
ff4a8d2b 5478 bfd_boolean is_unpredictable = FALSE;
05413229 5479 signed long value_in_comment = 0;
6b5d3a4d 5480 const char *c = insn->assembler;
05413229 5481
c19d1205
ZW		 5482 for (; *c; c++)
5483 {
5484 if (*c != '%')
5485 {
5486 func (stream, "%c", *c);
5487 continue;
5488 }
5489
5490 switch (*++c)
5491 {
5492 case '%':
5493 func (stream, "%%");
5494 break;
5495
c22aaad1
PB		 5496 case 'c':
5497 if (ifthen_state)
5498 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5499 break;
5500
5501 case 'x':
5502 if (ifthen_next_state)
5503 func (stream, "\t; unpredictable branch in IT block\n");
5504 break;
5505
5506 case 'X':
5507 if (ifthen_state)
5508 func (stream, "\t; unpredictable <IT:%s>",
5509 arm_conditional[IFTHEN_COND]);
5510 break;
5511
c19d1205
ZW		 5512 case 'I':
5513 {
5514 unsigned int imm12 = 0;
fe56b6ce 5515
c19d1205
ZW		 5516 imm12 |= (given & 0x000000ffu);
5517 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 5518 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 5519 func (stream, "#%u", imm12);
5520 value_in_comment = imm12;
c19d1205
ZW		 5521 }
5522 break;
5523
5524 case 'M':
5525 {
5526 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 5527
c19d1205
ZW		 5528 bits |= (given & 0x000000ffu);
5529 bits |= (given & 0x00007000u) >> 4;
5530 bits |= (given & 0x04000000u) >> 15;
5531 imm8 = (bits & 0x0ff);
5532 mod = (bits & 0xf00) >> 8;
5533 switch (mod)
5534 {
5535 case 0: imm = imm8; break;
c1e26897
NC		 5536 case 1: imm = ((imm8 << 16) | imm8); break;
5537 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
5538 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 5539 default:
5540 mod = (bits & 0xf80) >> 7;
5541 imm8 = (bits & 0x07f) | 0x80;
5542 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
5543 }
fe56b6ce
NC		 5544 func (stream, "#%u", imm);
5545 value_in_comment = imm;
c19d1205
ZW		 5546 }
5547 break;
43e65147 5548
c19d1205
ZW		 5549 case 'J':
5550 {
5551 unsigned int imm = 0;
fe56b6ce 5552
c19d1205
ZW		 5553 imm |= (given & 0x000000ffu);
5554 imm |= (given & 0x00007000u) >> 4;
5555 imm |= (given & 0x04000000u) >> 15;
5556 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 5557 func (stream, "#%u", imm);
5558 value_in_comment = imm;
c19d1205
ZW		 5559 }
5560 break;
5561
5562 case 'K':
5563 {
5564 unsigned int imm = 0;
fe56b6ce 5565
c19d1205
ZW		 5566 imm |= (given & 0x000f0000u) >> 16;
5567 imm |= (given & 0x00000ff0u) >> 0;
5568 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 5569 func (stream, "#%u", imm);
5570 value_in_comment = imm;
c19d1205
ZW		 5571 }
5572 break;
5573
74db7efb
NC		 5574 case 'H':
5575 {
5576 unsigned int imm = 0;
5577
5578 imm |= (given & 0x000f0000u) >> 4;
5579 imm |= (given & 0x00000fffu) >> 0;
5580 func (stream, "#%u", imm);
5581 value_in_comment = imm;
5582 }
5583 break;
5584
90ec0d68
MGD		 5585 case 'V':
5586 {
5587 unsigned int imm = 0;
5588
5589 imm |= (given & 0x00000fffu);
5590 imm |= (given & 0x000f0000u) >> 4;
5591 func (stream, "#%u", imm);
5592 value_in_comment = imm;
5593 }
5594 break;
5595
c19d1205
ZW		 5596 case 'S':
5597 {
5598 unsigned int reg = (given & 0x0000000fu);
5599 unsigned int stp = (given & 0x00000030u) >> 4;
5600 unsigned int imm = 0;
5601 imm |= (given & 0x000000c0u) >> 6;
5602 imm |= (given & 0x00007000u) >> 10;
5603
5604 func (stream, "%s", arm_regnames[reg]);
5605 switch (stp)
5606 {
5607 case 0:
5608 if (imm > 0)
5609 func (stream, ", lsl #%u", imm);
5610 break;
5611
5612 case 1:
5613 if (imm == 0)
5614 imm = 32;
5615 func (stream, ", lsr #%u", imm);
5616 break;
5617
5618 case 2:
5619 if (imm == 0)
5620 imm = 32;
5621 func (stream, ", asr #%u", imm);
5622 break;
5623
5624 case 3:
5625 if (imm == 0)
5626 func (stream, ", rrx");
5627 else
5628 func (stream, ", ror #%u", imm);
5629 }
5630 }
5631 break;
5632
5633 case 'a':
5634 {
5635 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 5636 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 5637 unsigned int op = (given & 0x00000f00) >> 8;
5638 unsigned int i12 = (given & 0x00000fff);
5639 unsigned int i8 = (given & 0x000000ff);
5640 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 5641 bfd_vma offset = 0;
c19d1205
ZW		 5642
5643 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 5644 if (U) /* 12-bit positive immediate offset. */
5645 {
5646 offset = i12;
5647 if (Rn != 15)
5648 value_in_comment = offset;
5649 }
5650 else if (Rn == 15) /* 12-bit negative immediate offset. */
5651 offset = - (int) i12;
5652 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 5653 {
5654 unsigned int Rm = (i8 & 0x0f);
5655 unsigned int sh = (i8 & 0x30) >> 4;
05413229 5656
c19d1205
ZW		 5657 func (stream, ", %s", arm_regnames[Rm]);
5658 if (sh)
5659 func (stream, ", lsl #%u", sh);
5660 func (stream, "]");
5661 break;
5662 }
5663 else switch (op)
5664 {
05413229 5665 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 5666 offset = i8;
5667 break;
5668
05413229 5669 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 5670 offset = -i8;
5671 break;
5672
05413229 5673 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 5674 offset = i8;
5675 writeback = TRUE;
5676 break;
5677
05413229 5678 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 5679 offset = -i8;
5680 writeback = TRUE;
5681 break;
5682
05413229 5683 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 5684 offset = i8;
5685 postind = TRUE;
5686 break;
5687
05413229 5688 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 5689 offset = -i8;
5690 postind = TRUE;
5691 break;
5692
5693 default:
5694 func (stream, ", <undefined>]");
5695 goto skip;
5696 }
5697
5698 if (postind)
d908c8af 5699 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 5700 else
5701 {
5702 if (offset)
d908c8af 5703 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 5704 func (stream, writeback ? "]!" : "]");
5705 }
5706
5707 if (Rn == 15)
5708 {
5709 func (stream, "\t; ");
5710 info->print_address_func (((pc + 4) & ~3) + offset, info);
5711 }
5712 }
5713 skip:
5714 break;
5715
5716 case 'A':
5717 {
c1e26897
NC		 5718 unsigned int U = ! NEGATIVE_BIT_SET;
5719 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 5720 unsigned int Rn = (given & 0x000f0000) >> 16;
5721 unsigned int off = (given & 0x000000ff);
5722
5723 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 5724
5725 if (PRE_BIT_SET)
c19d1205
ZW		 5726 {
5727 if (off || !U)
05413229
NC		 5728 {
5729 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
5730 value_in_comment = off * 4 * U ? 1 : -1;
5731 }
c19d1205
ZW		 5732 func (stream, "]");
5733 if (W)
5734 func (stream, "!");
5735 }
5736 else
5737 {
5738 func (stream, "], ");
5739 if (W)
05413229
NC		 5740 {
5741 func (stream, "#%c%u", U ? '+' : '-', off * 4);
5742 value_in_comment = off * 4 * U ? 1 : -1;
5743 }
c19d1205 5744 else
fe56b6ce
NC		 5745 {
5746 func (stream, "{%u}", off);
5747 value_in_comment = off;
5748 }
c19d1205
ZW		 5749 }
5750 }
5751 break;
5752
5753 case 'w':
5754 {
5755 unsigned int Sbit = (given & 0x01000000) >> 24;
5756 unsigned int type = (given & 0x00600000) >> 21;
05413229 5757
c19d1205
ZW		 5758 switch (type)
5759 {
5760 case 0: func (stream, Sbit ? "sb" : "b"); break;
5761 case 1: func (stream, Sbit ? "sh" : "h"); break;
5762 case 2:
5763 if (Sbit)
5764 func (stream, "??");
5765 break;
5766 case 3:
5767 func (stream, "??");
5768 break;
5769 }
5770 }
5771 break;
5772
5773 case 'm':
5774 {
5775 int started = 0;
5776 int reg;
5777
5778 func (stream, "{");
5779 for (reg = 0; reg < 16; reg++)
5780 if ((given & (1 << reg)) != 0)
5781 {
5782 if (started)
5783 func (stream, ", ");
5784 started = 1;
5785 func (stream, "%s", arm_regnames[reg]);
5786 }
5787 func (stream, "}");
5788 }
5789 break;
5790
5791 case 'E':
5792 {
5793 unsigned int msb = (given & 0x0000001f);
5794 unsigned int lsb = 0;
fe56b6ce 5795
c19d1205
ZW		 5796 lsb |= (given & 0x000000c0u) >> 6;
5797 lsb |= (given & 0x00007000u) >> 10;
5798 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
5799 }
5800 break;
5801
5802 case 'F':
5803 {
5804 unsigned int width = (given & 0x0000001f) + 1;
5805 unsigned int lsb = 0;
fe56b6ce 5806
c19d1205
ZW		 5807 lsb |= (given & 0x000000c0u) >> 6;
5808 lsb |= (given & 0x00007000u) >> 10;
5809 func (stream, "#%u, #%u", lsb, width);
5810 }
5811 break;
5812
5813 case 'b':
5814 {
5815 unsigned int S = (given & 0x04000000u) >> 26;
5816 unsigned int J1 = (given & 0x00002000u) >> 13;
5817 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 5818 bfd_vma offset = 0;
c19d1205
ZW		 5819
5820 offset |= !S << 20;
5821 offset |= J2 << 19;
5822 offset |= J1 << 18;
5823 offset |= (given & 0x003f0000) >> 4;
5824 offset |= (given & 0x000007ff) << 1;
5825 offset -= (1 << 20);
5826
5827 info->print_address_func (pc + 4 + offset, info);
5828 }
5829 break;
5830
5831 case 'B':
5832 {
5833 unsigned int S = (given & 0x04000000u) >> 26;
5834 unsigned int I1 = (given & 0x00002000u) >> 13;
5835 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 5836 bfd_vma offset = 0;
c19d1205
ZW		 5837
5838 offset |= !S << 24;
5839 offset |= !(I1 ^ S) << 23;
5840 offset |= !(I2 ^ S) << 22;
5841 offset |= (given & 0x03ff0000u) >> 4;
5842 offset |= (given & 0x000007ffu) << 1;
5843 offset -= (1 << 24);
36b0c57d 5844 offset += pc + 4;
c19d1205 5845
36b0c57d
PB		 5846 /* BLX target addresses are always word aligned. */
5847 if ((given & 0x00001000u) == 0)
5848 offset &= ~2u;
5849
5850 info->print_address_func (offset, info);
c19d1205
ZW		 5851 }
5852 break;
5853
5854 case 's':
5855 {
5856 unsigned int shift = 0;
fe56b6ce 5857
c19d1205
ZW		 5858 shift |= (given & 0x000000c0u) >> 6;
5859 shift |= (given & 0x00007000u) >> 10;
c1e26897 5860 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 5861 func (stream, ", asr #%u", shift);
5862 else if (shift)
5863 func (stream, ", lsl #%u", shift);
5864 /* else print nothing - lsl #0 */
5865 }
5866 break;
5867
5868 case 'R':
5869 {
5870 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 5871
c19d1205
ZW		 5872 if (rot)
5873 func (stream, ", ror #%u", rot * 8);
5874 }
5875 break;
5876
62b3e311 5877 case 'U':
43e65147 5878 if ((given & 0xf0) == 0x60)
62b3e311 5879 {
52e7f43d
RE		 5880 switch (given & 0xf)
5881 {
5882 case 0xf: func (stream, "sy"); break;
5883 default:
5884 func (stream, "#%d", (int) given & 0xf);
5885 break;
5886 }
62b3e311 5887 }
43e65147 5888 else
52e7f43d 5889 {
e797f7e0
MGD		 5890 const char * opt = data_barrier_option (given & 0xf);
5891 if (opt != NULL)
5892 func (stream, "%s", opt);
5893 else
5894 func (stream, "#%d", (int) given & 0xf);
52e7f43d 5895 }
62b3e311
PB		 5896 break;
5897
5898 case 'C':
5899 if ((given & 0xff) == 0)
5900 {
5901 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
5902 if (given & 0x800)
5903 func (stream, "f");
5904 if (given & 0x400)
5905 func (stream, "s");
5906 if (given & 0x200)
5907 func (stream, "x");
5908 if (given & 0x100)
5909 func (stream, "c");
5910 }
90ec0d68
MGD		 5911 else if ((given & 0x20) == 0x20)
5912 {
5913 char const* name;
5914 unsigned sysm = (given & 0xf00) >> 8;
5915
5916 sysm |= (given & 0x30);
5917 sysm |= (given & 0x00100000) >> 14;
5918 name = banked_regname (sysm);
43e65147 5919
90ec0d68
MGD		 5920 if (name != NULL)
5921 func (stream, "%s", name);
5922 else
d908c8af 5923 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 5924 }
62b3e311
PB		 5925 else
5926 {
d908c8af 5927 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 5928 }
5929 break;
5930
5931 case 'D':
90ec0d68
MGD		 5932 if (((given & 0xff) == 0)
5933 || ((given & 0x20) == 0x20))
5934 {
5935 char const* name;
5936 unsigned sm = (given & 0xf0000) >> 16;
5937
5938 sm |= (given & 0x30);
5939 sm |= (given & 0x00100000) >> 14;
5940 name = banked_regname (sm);
5941
5942 if (name != NULL)
5943 func (stream, "%s", name);
5944 else
d908c8af 5945 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 5946 }
62b3e311 5947 else
d908c8af 5948 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 5949 break;
5950
c19d1205
ZW		 5951 case '0': case '1': case '2': case '3': case '4':
5952 case '5': case '6': case '7': case '8': case '9':
5953 {
16980d0b
JB		 5954 int width;
5955 unsigned long val;
c19d1205 5956
16980d0b 5957 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 5958
c19d1205
ZW		 5959 switch (*c)
5960 {
05413229
NC		 5961 case 'd':
5962 func (stream, "%lu", val);
5963 value_in_comment = val;
5964 break;
ff4a8d2b 5965
f0fba320
RL		 5966 case 'D':
5967 func (stream, "%lu", val + 1);
5968 value_in_comment = val + 1;
5969 break;
5970
05413229
NC		 5971 case 'W':
5972 func (stream, "%lu", val * 4);
5973 value_in_comment = val * 4;
5974 break;
ff4a8d2b 5975
dd5181d5
KT		 5976 case 'S':
5977 if (val == 13)
5978 is_unpredictable = TRUE;
5979 /* Fall through. */
ff4a8d2b
NC		 5980 case 'R':
5981 if (val == 15)
5982 is_unpredictable = TRUE;
5983 /* Fall through. */
5984 case 'r':
5985 func (stream, "%s", arm_regnames[val]);
5986 break;
c19d1205
ZW		 5987
5988 case 'c':
c22aaad1 5989 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 5990 break;
5991
5992 case '\'':
c19d1205 5993 c++;
16980d0b
JB		 5994 if (val == ((1ul << width) - 1))
5995 func (stream, "%c", *c);
c19d1205 5996 break;
43e65147 5997
c19d1205 5998 case '`':
c19d1205 5999 c++;
16980d0b
JB		 6000 if (val == 0)
6001 func (stream, "%c", *c);
c19d1205
ZW		 6002 break;
6003
6004 case '?':
fe56b6ce 6005 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 6006 c += 1 << width;
c19d1205 6007 break;
43e65147 6008
0bb027fd
RR		 6009 case 'x':
6010 func (stream, "0x%lx", val & 0xffffffffUL);
6011 break;
c19d1205
ZW		 6012
6013 default:
6014 abort ();
6015 }
6016 }
6017 break;
6018
32a94698
NC		 6019 case 'L':
6020 /* PR binutils/12534
6021 If we have a PC relative offset in an LDRD or STRD
6022 instructions then display the decoded address. */
6023 if (((given >> 16) & 0xf) == 0xf)
6024 {
6025 bfd_vma offset = (given & 0xff) * 4;
6026
6027 if ((given & (1 << 23)) == 0)
6028 offset = - offset;
6029 func (stream, "\t; ");
6030 info->print_address_func ((pc & ~3) + 4 + offset, info);
6031 }
6032 break;
6033
c19d1205
ZW		 6034 default:
6035 abort ();
6036 }
6037 }
05413229
NC		 6038
6039 if (value_in_comment > 32 || value_in_comment < -16)
6040 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 6041
6042 if (is_unpredictable)
6043 func (stream, UNPREDICTABLE_INSTRUCTION);
6044
4a5329c6 6045 return;
c19d1205 6046 }
252b5132 6047
58efb6c0 6048 /* No match. */
252b5132
RH		 6049 abort ();
6050}
6051
e821645d
DJ		 6052/* Print data bytes on INFO->STREAM. */
6053
6054static void
fe56b6ce
NC		 6055print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
6056 struct disassemble_info *info,
e821645d
DJ		 6057 long given)
6058{
6059 switch (info->bytes_per_chunk)
6060 {
6061 case 1:
6062 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
6063 break;
6064 case 2:
6065 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
6066 break;
6067 case 4:
6068 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
6069 break;
6070 default:
6071 abort ();
6072 }
6073}
6074
22a398e1 6075/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 6076 being displayed in symbol relative addresses.
6077
6078 Also disallow private symbol, with __tagsym$$ prefix,
6079 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 6080
6081bfd_boolean
6082arm_symbol_is_valid (asymbol * sym,
6083 struct disassemble_info * info ATTRIBUTE_UNUSED)
6084{
6085 const char * name;
43e65147 6086
22a398e1
NC		 6087 if (sym == NULL)
6088 return FALSE;
6089
6090 name = bfd_asymbol_name (sym);
6091
d8282f0e 6092 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 6093}
6094
58efb6c0 6095/* Parse an individual disassembler option. */
baf0cc5e 6096
a3d9c82d 6097void
4a5329c6 6098parse_arm_disassembler_option (char *option)
dd92f639 6099{
01c7f630 6100 if (option == NULL)
dd92f639 6101 return;
b34976b6 6102
0112cd26 6103 if (CONST_STRNEQ (option, "reg-names-"))
dd92f639 6104 {
58efb6c0 6105 int i;
b34976b6 6106
01c7f630 6107 option += 10;
58efb6c0
NC		 6108
6109 for (i = NUM_ARM_REGNAMES; i--;)
31e0f3cd 6110 if (strneq (option, regnames[i].name, strlen (regnames[i].name)))
58efb6c0
NC		 6111 {
6112 regname_selected = i;
6113 break;
6114 }
b34976b6 6115
58efb6c0 6116 if (i < 0)
31e0f3cd 6117 /* XXX - should break 'option' at following delimiter. */
58efb6c0 6118 fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
dd92f639 6119 }
0112cd26 6120 else if (CONST_STRNEQ (option, "force-thumb"))
01c7f630 6121 force_thumb = 1;
0112cd26 6122 else if (CONST_STRNEQ (option, "no-force-thumb"))
01c7f630 6123 force_thumb = 0;
dd92f639 6124 else
31e0f3cd 6125 /* XXX - should break 'option' at following delimiter. */
58efb6c0 6126 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
b34976b6 6127
dd92f639
NC		 6128 return;
6129}
6130
31e0f3cd
NC		 6131/* Parse the string of disassembler options, spliting it at whitespaces
6132 or commas. (Whitespace separators supported for backwards compatibility). */
baf0cc5e 6133
01c7f630 6134static void
4a5329c6 6135parse_disassembler_options (char *options)
01c7f630 6136{
01c7f630
NC		 6137 if (options == NULL)
6138 return;
6139
31e0f3cd 6140 while (*options)
01c7f630 6141 {
31e0f3cd
NC		 6142 parse_arm_disassembler_option (options);
6143
6144 /* Skip forward to next seperator. */
6145 while ((*options) && (! ISSPACE (*options)) && (*options != ','))
6146 ++ options;
6147 /* Skip forward past seperators. */
6148 while (ISSPACE (*options) || (*options == ','))
43e65147 6149 ++ options;
01c7f630 6150 }
01c7f630
NC		 6151}
6152
5bc5ae88
RL		 6153static bfd_boolean
6154mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6155 enum map_type *map_symbol);
6156
c22aaad1
PB		 6157/* Search back through the insn stream to determine if this instruction is
6158 conditionally executed. */
fe56b6ce 6159
c22aaad1 6160static void
fe56b6ce
NC		 6161find_ifthen_state (bfd_vma pc,
6162 struct disassemble_info *info,
c22aaad1
PB		 6163 bfd_boolean little)
6164{
6165 unsigned char b[2];
6166 unsigned int insn;
6167 int status;
6168 /* COUNT is twice the number of instructions seen. It will be odd if we
6169 just crossed an instruction boundary. */
6170 int count;
6171 int it_count;
6172 unsigned int seen_it;
6173 bfd_vma addr;
6174
6175 ifthen_address = pc;
6176 ifthen_state = 0;
6177
6178 addr = pc;
6179 count = 1;
6180 it_count = 0;
6181 seen_it = 0;
6182 /* Scan backwards looking for IT instructions, keeping track of where
6183 instruction boundaries are. We don't know if something is actually an
6184 IT instruction until we find a definite instruction boundary. */
6185 for (;;)
6186 {
fe56b6ce 6187 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 6188 {
6189 /* A symbol must be on an instruction boundary, and will not
6190 be within an IT block. */
6191 if (seen_it && (count & 1))
6192 break;
6193
6194 return;
6195 }
6196 addr -= 2;
fe56b6ce 6197 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 6198 if (status)
6199 return;
6200
6201 if (little)
6202 insn = (b[0]) | (b[1] << 8);
6203 else
6204 insn = (b[1]) | (b[0] << 8);
6205 if (seen_it)
6206 {
6207 if ((insn & 0xf800) < 0xe800)
6208 {
6209 /* Addr + 2 is an instruction boundary. See if this matches
6210 the expected boundary based on the position of the last
6211 IT candidate. */
6212 if (count & 1)
6213 break;
6214 seen_it = 0;
6215 }
6216 }
6217 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
6218 {
5bc5ae88
RL		 6219 enum map_type type = MAP_ARM;
6220 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
6221
6222 if (!found || (found && type == MAP_THUMB))
6223 {
6224 /* This could be an IT instruction. */
6225 seen_it = insn;
6226 it_count = count >> 1;
6227 }
c22aaad1
PB		 6228 }
6229 if ((insn & 0xf800) >= 0xe800)
6230 count++;
6231 else
6232 count = (count + 2) | 1;
6233 /* IT blocks contain at most 4 instructions. */
6234 if (count >= 8 && !seen_it)
6235 return;
6236 }
6237 /* We found an IT instruction. */
6238 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
6239 if ((ifthen_state & 0xf) == 0)
6240 ifthen_state = 0;
6241}
6242
b0e28b39
DJ		 6243/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
6244 mapping symbol. */
6245
6246static int
6247is_mapping_symbol (struct disassemble_info *info, int n,
6248 enum map_type *map_type)
6249{
6250 const char *name;
6251
6252 name = bfd_asymbol_name (info->symtab[n]);
6253 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
6254 && (name[2] == 0 || name[2] == '.'))
6255 {
6256 *map_type = ((name[1] == 'a') ? MAP_ARM
6257 : (name[1] == 't') ? MAP_THUMB
6258 : MAP_DATA);
6259 return TRUE;
6260 }
6261
6262 return FALSE;
6263}
6264
6265/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
6266 Returns nonzero if *MAP_TYPE was set. */
6267
6268static int
6269get_map_sym_type (struct disassemble_info *info,
6270 int n,
6271 enum map_type *map_type)
6272{
6273 /* If the symbol is in a different section, ignore it. */
6274 if (info->section != NULL && info->section != info->symtab[n]->section)
6275 return FALSE;
6276
6277 return is_mapping_symbol (info, n, map_type);
6278}
6279
6280/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 6281 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 6282
6283static int
fe56b6ce
NC		 6284get_sym_code_type (struct disassemble_info *info,
6285 int n,
e821645d 6286 enum map_type *map_type)
2087ad84
PB		 6287{
6288 elf_symbol_type *es;
6289 unsigned int type;
b0e28b39
DJ		 6290
6291 /* If the symbol is in a different section, ignore it. */
6292 if (info->section != NULL && info->section != info->symtab[n]->section)
6293 return FALSE;
2087ad84 6294
e821645d 6295 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 6296 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6297
6298 /* If the symbol has function type then use that. */
34e77a92 6299 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 6300 {
39d911fc
TP		 6301 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6302 == ST_BRANCH_TO_THUMB)
35fc36a8
RS		 6303 *map_type = MAP_THUMB;
6304 else
6305 *map_type = MAP_ARM;
2087ad84
PB		 6306 return TRUE;
6307 }
6308
2087ad84
PB		 6309 return FALSE;
6310}
6311
5bc5ae88
RL		 6312/* Search the mapping symbol state for instruction at pc. This is only
6313 applicable for elf target.
6314
6315 There is an assumption Here, info->private_data contains the correct AND
6316 up-to-date information about current scan process. The information will be
6317 used to speed this search process.
6318
6319 Return TRUE if the mapping state can be determined, and map_symbol
6320 will be updated accordingly. Otherwise, return FALSE. */
6321
6322static bfd_boolean
6323mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6324 enum map_type *map_symbol)
6325{
6326 bfd_vma addr;
6327 int n, start = 0;
6328 bfd_boolean found = FALSE;
6329 enum map_type type = MAP_ARM;
6330 struct arm_private_data *private_data;
6331
6332 if (info->private_data == NULL || info->symtab_size == 0
6333 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
6334 return FALSE;
6335
6336 private_data = info->private_data;
6337 if (pc == 0)
6338 start = 0;
6339 else
6340 start = private_data->last_mapping_sym;
6341
6342 start = (start == -1)? 0 : start;
6343 addr = bfd_asymbol_value (info->symtab[start]);
6344
6345 if (pc >= addr)
6346 {
6347 if (get_map_sym_type (info, start, &type))
6348 found = TRUE;
6349 }
6350 else
6351 {
6352 for (n = start - 1; n >= 0; n--)
6353 {
6354 if (get_map_sym_type (info, n, &type))
6355 {
6356 found = TRUE;
6357 break;
6358 }
6359 }
6360 }
6361
6362 /* No mapping symbols were found. A leading $d may be
6363 omitted for sections which start with data; but for
6364 compatibility with legacy and stripped binaries, only
6365 assume the leading $d if there is at least one mapping
6366 symbol in the file. */
6367 if (!found && private_data->has_mapping_symbols == 1)
6368 {
6369 type = MAP_DATA;
6370 found = TRUE;
6371 }
6372
6373 *map_symbol = type;
6374 return found;
6375}
6376
0313a2b8
NC		 6377/* Given a bfd_mach_arm_XXX value, this function fills in the fields
6378 of the supplied arm_feature_set structure with bitmasks indicating
6379 the support base architectures and coprocessor extensions.
6380
6381 FIXME: This could more efficiently implemented as a constant array,
6382 although it would also be less robust. */
6383
6384static void
6385select_arm_features (unsigned long mach,
6386 arm_feature_set * features)
6387{
1af1dd51
MW		 6388#undef ARM_SET_FEATURES
6389#define ARM_SET_FEATURES(FSET) \
6390 { \
6391 const arm_feature_set fset = FSET; \
6392 arm_feature_set tmp = ARM_FEATURE (0, 0, FPU_FPA) ; \
6393 ARM_MERGE_FEATURE_SETS (*features, tmp, fset); \
6394 }
823d2571 6395
0313a2b8
NC		 6396 switch (mach)
6397 {
1af1dd51
MW		 6398 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
6399 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
6400 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
6401 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
6402 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
6403 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
6404 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
6405 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
6406 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
6407 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
6408 case bfd_mach_arm_ep9312:
6409 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
6410 ARM_CEXT_MAVERICK | FPU_MAVERICK));
6411 break;
6412 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
6413 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
0313a2b8
NC		 6414 /* If the machine type is unknown allow all
6415 architecture types and all extensions. */
1af1dd51 6416 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
0313a2b8
NC		 6417 default:
6418 abort ();
6419 }
1af1dd51
MW		 6420
6421#undef ARM_SET_FEATURES
0313a2b8
NC		 6422}
6423
6424
58efb6c0
NC		 6425/* NOTE: There are no checks in these routines that
6426 the relevant number of data bytes exist. */
baf0cc5e 6427
58efb6c0 6428static int
4a5329c6 6429print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 6430{
c19d1205
ZW		 6431 unsigned char b[4];
6432 long given;
6433 int status;
e821645d 6434 int is_thumb = FALSE;
b0e28b39 6435 int is_data = FALSE;
bd2e2557 6436 int little_code;
e821645d 6437 unsigned int size = 4;
4a5329c6 6438 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 6439 bfd_boolean found = FALSE;
b0e28b39 6440 struct arm_private_data *private_data;
58efb6c0 6441
dd92f639
NC		 6442 if (info->disassembler_options)
6443 {
6444 parse_disassembler_options (info->disassembler_options);
b34976b6 6445
58efb6c0 6446 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 6447 info->disassembler_options = NULL;
6448 }
b34976b6 6449
0313a2b8
NC		 6450 /* PR 10288: Control which instructions will be disassembled. */
6451 if (info->private_data == NULL)
6452 {
b0e28b39 6453 static struct arm_private_data private;
0313a2b8
NC		 6454
6455 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
6456 /* If the user did not use the -m command line switch then default to
6457 disassembling all types of ARM instruction.
43e65147 6458
0313a2b8
NC		 6459 The info->mach value has to be ignored as this will be based on
6460 the default archictecture for the target and/or hints in the notes
6461 section, but it will never be greater than the current largest arm
6462 machine value (iWMMXt2), which is only equivalent to the V5TE
6463 architecture. ARM architectures have advanced beyond the machine
6464 value encoding, and these newer architectures would be ignored if
6465 the machine value was used.
6466
6467 Ie the -m switch is used to restrict which instructions will be
6468 disassembled. If it is necessary to use the -m switch to tell
6469 objdump that an ARM binary is being disassembled, eg because the
6470 input is a raw binary file, but it is also desired to disassemble
6471 all ARM instructions then use "-marm". This will select the
6472 "unknown" arm architecture which is compatible with any ARM
6473 instruction. */
6474 info->mach = bfd_mach_arm_unknown;
6475
6476 /* Compute the architecture bitmask from the machine number.
6477 Note: This assumes that the machine number will not change
6478 during disassembly.... */
b0e28b39 6479 select_arm_features (info->mach, & private.features);
0313a2b8 6480
b0e28b39 6481 private.has_mapping_symbols = -1;
1fbaefec
PB		 6482 private.last_mapping_sym = -1;
6483 private.last_mapping_addr = 0;
b0e28b39
DJ		 6484
6485 info->private_data = & private;
0313a2b8 6486 }
b0e28b39
DJ		 6487
6488 private_data = info->private_data;
6489
bd2e2557
SS		 6490 /* Decide if our code is going to be little-endian, despite what the
6491 function argument might say. */
6492 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
6493
b0e28b39
DJ		 6494 /* For ELF, consult the symbol table to determine what kind of code
6495 or data we have. */
8977d4b2 6496 if (info->symtab_size != 0
e821645d
DJ		 6497 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
6498 {
6499 bfd_vma addr;
b0e28b39 6500 int n, start;
e821645d 6501 int last_sym = -1;
b0e28b39 6502 enum map_type type = MAP_ARM;
e821645d 6503
e821645d
DJ		 6504 /* Start scanning at the start of the function, or wherever
6505 we finished last time. */
6750a3a7
NC		 6506 /* PR 14006. When the address is 0 we are either at the start of the
6507 very first function, or else the first function in a new, unlinked
838441e4 6508 executable section (eg because of -ffunction-sections). Either way
6750a3a7
NC		 6509 start scanning from the beginning of the symbol table, not where we
6510 left off last time. */
6511 if (pc == 0)
6512 start = 0;
6513 else
6514 {
6515 start = info->symtab_pos + 1;
6516 if (start < private_data->last_mapping_sym)
6517 start = private_data->last_mapping_sym;
6518 }
b0e28b39 6519 found = FALSE;
e821645d 6520
b0e28b39
DJ		 6521 /* First, look for mapping symbols. */
6522 if (private_data->has_mapping_symbols != 0)
e821645d 6523 {
b0e28b39
DJ		 6524 /* Scan up to the location being disassembled. */
6525 for (n = start; n < info->symtab_size; n++)
6526 {
6527 addr = bfd_asymbol_value (info->symtab[n]);
6528 if (addr > pc)
6529 break;
6530 if (get_map_sym_type (info, n, &type))
6531 {
6532 last_sym = n;
6533 found = TRUE;
6534 }
6535 }
6536
6537 if (!found)
6538 {
6539 /* No mapping symbol found at this address. Look backwards
cc643b88 6540 for a preceding one. */
b0e28b39
DJ		 6541 for (n = start - 1; n >= 0; n--)
6542 {
6543 if (get_map_sym_type (info, n, &type))
6544 {
6545 last_sym = n;
6546 found = TRUE;
6547 break;
6548 }
6549 }
6550 }
6551
6552 if (found)
6553 private_data->has_mapping_symbols = 1;
6554
6555 /* No mapping symbols were found. A leading $d may be
6556 omitted for sections which start with data; but for
6557 compatibility with legacy and stripped binaries, only
6558 assume the leading $d if there is at least one mapping
6559 symbol in the file. */
6560 if (!found && private_data->has_mapping_symbols == -1)
e821645d 6561 {
b0e28b39
DJ		 6562 /* Look for mapping symbols, in any section. */
6563 for (n = 0; n < info->symtab_size; n++)
6564 if (is_mapping_symbol (info, n, &type))
6565 {
6566 private_data->has_mapping_symbols = 1;
6567 break;
6568 }
6569 if (private_data->has_mapping_symbols == -1)
6570 private_data->has_mapping_symbols = 0;
6571 }
6572
6573 if (!found && private_data->has_mapping_symbols == 1)
6574 {
6575 type = MAP_DATA;
e821645d
DJ		 6576 found = TRUE;
6577 }
6578 }
6579
b0e28b39
DJ		 6580 /* Next search for function symbols to separate ARM from Thumb
6581 in binaries without mapping symbols. */
e821645d
DJ		 6582 if (!found)
6583 {
b0e28b39
DJ		 6584 /* Scan up to the location being disassembled. */
6585 for (n = start; n < info->symtab_size; n++)
e821645d 6586 {
b0e28b39
DJ		 6587 addr = bfd_asymbol_value (info->symtab[n]);
6588 if (addr > pc)
6589 break;
6590 if (get_sym_code_type (info, n, &type))
e821645d
DJ		 6591 {
6592 last_sym = n;
6593 found = TRUE;
b0e28b39
DJ		 6594 }
6595 }
6596
6597 if (!found)
6598 {
6599 /* No mapping symbol found at this address. Look backwards
cc643b88 6600 for a preceding one. */
b0e28b39
DJ		 6601 for (n = start - 1; n >= 0; n--)
6602 {
6603 if (get_sym_code_type (info, n, &type))
6604 {
6605 last_sym = n;
6606 found = TRUE;
6607 break;
6608 }
e821645d
DJ		 6609 }
6610 }
6611 }
6612
1fbaefec
PB		 6613 private_data->last_mapping_sym = last_sym;
6614 private_data->last_type = type;
6615 is_thumb = (private_data->last_type == MAP_THUMB);
6616 is_data = (private_data->last_type == MAP_DATA);
b34976b6 6617
e821645d
DJ		 6618 /* Look a little bit ahead to see if we should print out
6619 two or four bytes of data. If there's a symbol,
6620 mapping or otherwise, after two bytes then don't
6621 print more. */
6622 if (is_data)
6623 {
6624 size = 4 - (pc & 3);
6625 for (n = last_sym + 1; n < info->symtab_size; n++)
6626 {
6627 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 6628 if (addr > pc
6629 && (info->section == NULL
6630 || info->section == info->symtab[n]->section))
e821645d
DJ		 6631 {
6632 if (addr - pc < size)
6633 size = addr - pc;
6634 break;
6635 }
6636 }
6637 /* If the next symbol is after three bytes, we need to
6638 print only part of the data, so that we can use either
6639 .byte or .short. */
6640 if (size == 3)
6641 size = (pc & 1) ? 1 : 2;
6642 }
6643 }
6644
6645 if (info->symbols != NULL)
252b5132 6646 {
5876e06d
NC		 6647 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
6648 {
2f0ca46a 6649 coff_symbol_type * cs;
b34976b6 6650
5876e06d
NC		 6651 cs = coffsymbol (*info->symbols);
6652 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
6653 || cs->native->u.syment.n_sclass == C_THUMBSTAT
6654 || cs->native->u.syment.n_sclass == C_THUMBLABEL
6655 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
6656 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
6657 }
e821645d
DJ		 6658 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
6659 && !found)
5876e06d 6660 {
2087ad84
PB		 6661 /* If no mapping symbol has been found then fall back to the type
6662 of the function symbol. */
e821645d
DJ		 6663 elf_symbol_type * es;
6664 unsigned int type;
2087ad84 6665
e821645d
DJ		 6666 es = *(elf_symbol_type **)(info->symbols);
6667 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 6668
39d911fc
TP		 6669 is_thumb =
6670 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6671 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
5876e06d 6672 }
e49d43ff
TG		 6673 else if (bfd_asymbol_flavour (*info->symbols)
6674 == bfd_target_mach_o_flavour)
6675 {
6676 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
6677
6678 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
6679 }
5876e06d 6680 }
b34976b6 6681
e821645d
DJ		 6682 if (force_thumb)
6683 is_thumb = TRUE;
6684
b8f9ee44
CL		 6685 if (is_data)
6686 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6687 else
6688 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6689
c19d1205 6690 info->bytes_per_line = 4;
252b5132 6691
1316c8b3
NC		 6692 /* PR 10263: Disassemble data if requested to do so by the user. */
6693 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 6694 {
6695 int i;
6696
1316c8b3 6697 /* Size was already set above. */
e821645d
DJ		 6698 info->bytes_per_chunk = size;
6699 printer = print_insn_data;
6700
fe56b6ce 6701 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 6702 given = 0;
6703 if (little)
6704 for (i = size - 1; i >= 0; i--)
6705 given = b[i] | (given << 8);
6706 else
6707 for (i = 0; i < (int) size; i++)
6708 given = b[i] | (given << 8);
6709 }
6710 else if (!is_thumb)
252b5132 6711 {
c19d1205
ZW		 6712 /* In ARM mode endianness is a straightforward issue: the instruction
6713 is four bytes long and is either ordered 0123 or 3210. */
6714 printer = print_insn_arm;
6715 info->bytes_per_chunk = 4;
4a5329c6 6716 size = 4;
c19d1205 6717
0313a2b8 6718 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 6719 if (little_code)
c19d1205
ZW		 6720 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
6721 else
6722 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
252b5132 6723 }
58efb6c0 6724 else
252b5132 6725 {
c19d1205
ZW		 6726 /* In Thumb mode we have the additional wrinkle of two
6727 instruction lengths. Fortunately, the bits that determine
6728 the length of the current instruction are always to be found
6729 in the first two bytes. */
4a5329c6 6730 printer = print_insn_thumb16;
c19d1205 6731 info->bytes_per_chunk = 2;
4a5329c6
ZW		 6732 size = 2;
6733
fe56b6ce 6734 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 6735 if (little_code)
9a2ff3f5
AM		 6736 given = (b[0]) | (b[1] << 8);
6737 else
6738 given = (b[1]) | (b[0] << 8);
6739
c19d1205 6740 if (!status)
252b5132 6741 {
c19d1205
ZW		 6742 /* These bit patterns signal a four-byte Thumb
6743 instruction. */
6744 if ((given & 0xF800) == 0xF800
6745 || (given & 0xF800) == 0xF000
6746 || (given & 0xF800) == 0xE800)
252b5132 6747 {
0313a2b8 6748 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 6749 if (little_code)
c19d1205 6750 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 6751 else
c19d1205
ZW		 6752 given = (b[1]) | (b[0] << 8) | (given << 16);
6753
6754 printer = print_insn_thumb32;
4a5329c6 6755 size = 4;
252b5132 6756 }
252b5132 6757 }
c22aaad1
PB		 6758
6759 if (ifthen_address != pc)
0313a2b8 6760 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 6761
6762 if (ifthen_state)
6763 {
6764 if ((ifthen_state & 0xf) == 0x8)
6765 ifthen_next_state = 0;
6766 else
6767 ifthen_next_state = (ifthen_state & 0xe0)
6768 | ((ifthen_state & 0xf) << 1);
6769 }
252b5132 6770 }
b34976b6 6771
c19d1205
ZW		 6772 if (status)
6773 {
6774 info->memory_error_func (status, pc, info);
6775 return -1;
6776 }
6a56ec7e
NC		 6777 if (info->flags & INSN_HAS_RELOC)
6778 /* If the instruction has a reloc associated with it, then
6779 the offset field in the instruction will actually be the
6780 addend for the reloc. (We are using REL type relocs).
6781 In such cases, we can ignore the pc when computing
6782 addresses, since the addend is not currently pc-relative. */
6783 pc = 0;
b34976b6 6784
4a5329c6 6785 printer (pc, info, given);
c22aaad1
PB		 6786
6787 if (is_thumb)
6788 {
6789 ifthen_state = ifthen_next_state;
6790 ifthen_address += size;
6791 }
4a5329c6 6792 return size;
252b5132
RH		 6793}
6794
6795int
4a5329c6 6796print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 6797{
bd2e2557
SS		 6798 /* Detect BE8-ness and record it in the disassembler info. */
6799 if (info->flavour == bfd_target_elf_flavour
6800 && info->section != NULL
6801 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
6802 info->endian_code = BFD_ENDIAN_LITTLE;
6803
b34976b6 6804 return print_insn (pc, info, FALSE);
58efb6c0 6805}
01c7f630 6806
58efb6c0 6807int
4a5329c6 6808print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 6809{
b34976b6 6810 return print_insn (pc, info, TRUE);
58efb6c0 6811}
252b5132 6812
58efb6c0 6813void
4a5329c6 6814print_arm_disassembler_options (FILE *stream)
58efb6c0
NC		 6815{
6816 int i;
252b5132 6817
58efb6c0
NC		 6818 fprintf (stream, _("\n\
6819The following ARM specific disassembler options are supported for use with\n\
6820the -M switch:\n"));
b34976b6 6821
58efb6c0
NC		 6822 for (i = NUM_ARM_REGNAMES; i--;)
6823 fprintf (stream, " reg-names-%s %*c%s\n",
6824 regnames[i].name,
d5b2f4d6 6825 (int)(14 - strlen (regnames[i].name)), ' ',
58efb6c0
NC		 6826 regnames[i].description);
6827
6828 fprintf (stream, " force-thumb Assume all insns are Thumb insns\n");
cc643b88 6829 fprintf (stream, " no-force-thumb Examine preceding label to determine an insn's type\n\n");
252b5132 6830}
GDB Binutils - Deliverables
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