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x86: correct UDn
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
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252b5132 1/* Instruction printing code for the ARM
2571583a 2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
2fbad815 24
6394c606 25#include "disassemble.h"
2fbad815 26#include "opcode/arm.h"
252b5132 27#include "opintl.h"
31e0f3cd 28#include "safe-ctype.h"
65b48a81 29#include "libiberty.h"
0dbde4cf 30#include "floatformat.h"
252b5132 31
baf0cc5e 32/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 33#include "coff/internal.h"
34#include "libcoff.h"
252b5132
RH		 35#include "elf-bfd.h"
36#include "elf/internal.h"
37#include "elf/arm.h"
e49d43ff 38#include "mach-o.h"
252b5132 39
6b5d3a4d 40/* FIXME: Belongs in global header. */
01c7f630 41#ifndef strneq
58efb6c0
NC		 42#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
43#endif
44
1fbaefec
PB		 45/* Cached mapping symbol state. */
46enum map_type
47{
48 MAP_ARM,
49 MAP_THUMB,
50 MAP_DATA
51};
52
b0e28b39
DJ		 53struct arm_private_data
54{
55 /* The features to use when disassembling optional instructions. */
56 arm_feature_set features;
57
58 /* Whether any mapping symbols are present in the provided symbol
59 table. -1 if we do not know yet, otherwise 0 or 1. */
60 int has_mapping_symbols;
1fbaefec
PB		 61
62 /* Track the last type (although this doesn't seem to be useful) */
63 enum map_type last_type;
64
65 /* Tracking symbol table information */
66 int last_mapping_sym;
67 bfd_vma last_mapping_addr;
b0e28b39
DJ		 68};
69
6b5d3a4d
ZW		 70struct opcode32
71{
823d2571
TG		 72 arm_feature_set arch; /* Architecture defining this insn. */
73 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 74 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 75 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 76};
77
78struct opcode16
79{
823d2571 80 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 81 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 82 const char *assembler; /* How to disassemble this insn. */
83};
b7693d02 84
8f06b2d8 85/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 86
2fbad815 87 %% %
4a5329c6 88
c22aaad1 89 %c print condition code (always bits 28-31 in ARM mode)
37b37b2d 90 %q print shifter argument
e2efe87d
MGD		 91 %u print condition code (unconditional in ARM mode,
92 UNPREDICTABLE if not AL in Thumb)
4a5329c6 93 %A print address for ldc/stc/ldf/stf instruction
16980d0b 94 %B print vstm/vldm register list
4a5329c6 95 %I print cirrus signed shift immediate: bits 0..3|4..6
4a5329c6
ZW		 96 %F print the COUNT field of a LFM/SFM instruction.
97 %P print floating point precision in arithmetic insn
98 %Q print floating point precision in ldf/stf insn
99 %R print floating point rounding mode
100
33399f07 101 %<bitfield>c print as a condition code (for vsel)
4a5329c6 102 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 103 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
104 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 105 %<bitfield>d print the bitfield in decimal
16980d0b 106 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 107 %<bitfield>x print the bitfield in hex
108 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 109 %<bitfield>f print a floating point constant if >7 else a
110 floating point register
4a5329c6
ZW		 111 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
112 %<bitfield>g print as an iWMMXt 64-bit register
113 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 114 %<bitfield>D print as a NEON D register
115 %<bitfield>Q print as a NEON Q register
c28eeff2 116 %<bitfield>V print as a NEON D or Q register
6f1c2142 117 %<bitfield>E print a quarter-float immediate value
4a5329c6 118
16980d0b 119 %y<code> print a single precision VFP reg.
2fbad815 120 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 121 %z<code> print a double precision VFP reg
2fbad815 122 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 123
16980d0b
JB		 124 %<bitfield>'c print specified char iff bitfield is all ones
125 %<bitfield>`c print specified char iff bitfield is all zeroes
126 %<bitfield>?ab... select from array of values in big endian order
43e65147 127
2fbad815 128 %L print as an iWMMXt N/M width field.
4a5329c6 129 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 130 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 131 versions.
132 %i print 5-bit immediate in bits 8,3..0
133 (print "32" when 0)
fe56b6ce 134 %r print register offset address for wldt/wstr instruction. */
2fbad815 135
21d799b5 136enum opcode_sentinel_enum
05413229
NC		 137{
138 SENTINEL_IWMMXT_START = 1,
139 SENTINEL_IWMMXT_END,
140 SENTINEL_GENERIC_START
141} opcode_sentinels;
142
aefd8a40 143#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
c1e26897 144#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 145
8f06b2d8 146/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 147
8f06b2d8 148static const struct opcode32 coprocessor_opcodes[] =
2fbad815 149{
2fbad815 150 /* XScale instructions. */
823d2571
TG		 151 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
152 0x0e200010, 0x0fff0ff0,
153 "mia%c\tacc0, %0-3r, %12-15r"},
154 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
155 0x0e280010, 0x0fff0ff0,
156 "miaph%c\tacc0, %0-3r, %12-15r"},
157 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
158 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
159 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
160 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
161 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
162 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 163
2fbad815 164 /* Intel Wireless MMX technology instructions. */
823d2571
TG		 165 {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
166 {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
167 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
168 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
169 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
170 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
171 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
172 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
173 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
174 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
175 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
176 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
177 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
178 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
179 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
180 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
181 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
182 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
183 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
184 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
185 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
186 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
187 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
188 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
189 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
190 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
191 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
192 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
193 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
194 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
195 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
196 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
197 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
198 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
199 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
200 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
201 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
202 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
203 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
204 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
205 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
206 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
207 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
208 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
209 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
210 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
211 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
212 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
213 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
214 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
215 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
216 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
217 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
218 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
219 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
220 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
221 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
222 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
223 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
224 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
225 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
226 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
227 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
228 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
229 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
230 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
231 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
232 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
233 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
234 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
235 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
236 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
237 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
238 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
239 0x0e800120, 0x0f800ff0,
240 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
241 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
242 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
243 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
244 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
245 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
246 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
247 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
248 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
249 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
250 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
251 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
252 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
253 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
254 0x0e8000a0, 0x0f800ff0,
255 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
256 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
257 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
258 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
259 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
260 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
261 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
262 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
263 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
264 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
265 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
266 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
267 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
268 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
269 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
270 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
271 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
272 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
273 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
274 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
275 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
276 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
277 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
278 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
279 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
280 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
281 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
282 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
283 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
284 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
285 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
286 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
287 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
288 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
289 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
290 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
291 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
292 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
293 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
294 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
295 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
296 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
297 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
298 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
299 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
300 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
301 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
302 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
303 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
304 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
305 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
306 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
307 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
308 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
309 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
310 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
311 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
312 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
313 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
314 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
315 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
316 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
317 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
318 {ARM_FEATURE_CORE_LOW (0),
319 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 320
fe56b6ce 321 /* Floating point coprocessor (FPA) instructions. */
823d2571
TG		 322 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
323 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
324 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
325 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
326 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
327 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
328 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
329 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
330 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
331 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
332 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
333 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
334 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
335 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
336 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
337 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
338 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
339 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
340 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
341 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
342 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
343 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
344 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
345 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
346 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
347 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
348 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
349 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
350 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
351 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
352 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
353 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
354 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
355 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
356 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
357 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
358 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
359 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
360 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
361 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
362 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
363 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
364 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
365 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
366 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
367 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
368 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
369 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
370 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
371 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
372 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
373 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
374 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
375 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
376 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
377 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
378 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
379 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
380 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
381 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
382 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
383 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
384 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
385 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
386 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
387 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
388 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
389 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
390 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
391 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
392 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
393 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
394 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
395 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
396 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
397 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
398 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
399 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
400 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
401 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
402 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
403 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
404 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
405 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
406 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
407 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 408
16a1fa25
TP		 409 /* ARMv8-M Mainline Security Extensions instructions. */
410 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
411 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
412 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
413 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
414
fe56b6ce 415 /* Register load/store. */
823d2571
TG		 416 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
417 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
418 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
419 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
420 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
421 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
422 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
423 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
424 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
425 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
426 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
427 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
428 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
429 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
430 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
431 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
432 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
433 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
434 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
435 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
436 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
437 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
438 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
439 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
440 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
441 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
442 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
443 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
444 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
445 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
446 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
447 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
448
449 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
450 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
451 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
452 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
453 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
454 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
455 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
456 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 457
fe56b6ce 458 /* Data transfer between ARM and NEON registers. */
823d2571
TG		 459 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
460 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
462 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
464 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
466 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
468 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
470 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
472 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
474 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
476 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
478 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
480 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
482 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
484 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
486 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 487 /* Half-precision conversion instructions. */
823d2571
TG		 488 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
489 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
490 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
491 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
492 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
493 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
494 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
495 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 496
fe56b6ce 497 /* Floating point coprocessor (VFP) instructions. */
823d2571
TG		 498 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
499 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
500 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
501 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
502 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
503 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
504 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
505 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
40c7d507
RR		 506 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
507 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
823d2571
TG		 508 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
509 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
510 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
511 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
512 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
513 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
514 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
515 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
516 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
517 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
518 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
519 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
40c7d507
RR		 520 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
521 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
823d2571
TG		 522 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
523 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
524 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
525 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
526 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
527 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
528 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
529 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
530 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
531 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
532 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
533 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
534 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
535 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
536 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
537 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
538 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
539 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
540 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
541 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
542 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
543 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
544 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
545 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
546 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
547 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
548 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
549 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
550 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
551 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
552 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
553 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
554 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
555 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
556 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
557 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
558 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
559 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
560 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
561 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
562 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
563 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
564 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
565 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
566 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
567 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
568 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
569 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
570 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
571 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
572 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
573 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
574 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
575 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
576 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
577 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
578 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
579 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
580 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
581 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
582 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
583 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
584 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
585 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
586 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
587 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
588 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
589 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
590 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6f1c2142 591 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
823d2571 592 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6f1c2142 593 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
823d2571
TG		 594 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
595 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
596 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
597 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
598 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
599 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
600 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
601 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
602 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
603 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
604 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
605 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
606 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
607 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
608 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
609 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
610 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
611 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
612 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
613 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
614 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
615 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
616 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
617 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
618 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
619 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
620 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
621 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
622 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
623 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
624 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
625 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
626 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
627 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
628 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
629 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
630 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
631 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
632 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
633 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
634 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
635 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 636
637 /* Cirrus coprocessor instructions. */
823d2571
TG		 638 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
639 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
640 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
641 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
642 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
643 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
644 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
645 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
646 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
647 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
648 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
649 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
650 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
651 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
652 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
653 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
654 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
655 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
656 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
657 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
658 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
659 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
660 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
661 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
662 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
663 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
664 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
665 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
666 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
667 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
668 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
669 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
670 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
671 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
672 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
673 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
674 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
675 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
676 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
677 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
678 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
679 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
680 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
681 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
682 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
683 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
684 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
685 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
686 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
687 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
688 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
689 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
690 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
691 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
692 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
693 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
694 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
695 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
696 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
697 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
698 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
699 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
700 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
701 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
702 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
703 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
704 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
705 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
706 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
707 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
708 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
709 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
710 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
711 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
712 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
713 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
714 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
715 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
716 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
717 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
718 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
719 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
720 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
721 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
722 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
723 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
724 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
725 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
726 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
727 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
728 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
729 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
730 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
731 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
732 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
733 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
734 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
735 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
736 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
737 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
738 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
739 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
740 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
741 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
742 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
743 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
744 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
745 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
746 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
747 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
748 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
749 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
750 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
751 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
752 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
753 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
754 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
755 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
756 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
757 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
758 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
759 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
760 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
761 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
762 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
763 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
764 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
765 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
766 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
767 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
768 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
769 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
770 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
771 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
772 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
773 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
774 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
775 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
776 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
777 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
778 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
779 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
780 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
781 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
782 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
783 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
784 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
785 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
786 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
787 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
788 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
789 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
790 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
791 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
792 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
793 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
794 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
795 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
796 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
797 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
798 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
799 0x0e000600, 0x0ff00f10,
800 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
801 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
802 0x0e100600, 0x0ff00f10,
803 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
804 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
805 0x0e200600, 0x0ff00f10,
806 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
807 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
808 0x0e300600, 0x0ff00f10,
809 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 810
62f3b8c8 811 /* VFP Fused multiply add instructions. */
823d2571
TG		 812 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
813 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
814 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
815 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
816 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
817 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
818 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
819 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
820 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
821 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
822 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
824 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
825 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
826 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
827 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 828
33399f07 829 /* FP v5. */
823d2571 830 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 831 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
823d2571 832 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 833 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
823d2571 834 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 835 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
823d2571 836 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 837 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
823d2571 838 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 839 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
823d2571 840 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 841 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
823d2571
TG		 842 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
843 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
844 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
845 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
846 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
847 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
848 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
849 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
850 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 851 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
823d2571 852 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 853 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 854
05413229 855 /* Generic coprocessor instructions. */
823d2571
TG		 856 {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
858 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
860 0x0c500000, 0x0ff00000,
861 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
863 0x0e000000, 0x0f000010,
864 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
866 0x0e10f010, 0x0f10f010,
867 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
869 0x0e100010, 0x0f100010,
870 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
872 0x0e000010, 0x0f100010,
873 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
875 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
877 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
2fbad815 878
05413229 879 /* V6 coprocessor instructions. */
823d2571
TG		 880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
881 0xfc500000, 0xfff00000,
882 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
884 0xfc400000, 0xfff00000,
885 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
8f06b2d8 886
c28eeff2
SN		 887 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
888 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
889 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
890 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
891 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
892 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
893 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
894 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
895 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
896 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
897 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
898 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
899 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
900 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 901 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
c28eeff2 902 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 903 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
c28eeff2 904 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 905 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
c28eeff2 906 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 907 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
c28eeff2 908
c604a79a
JW		 909 /* Dot Product instructions in the space of coprocessor 13. */
910 {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
911 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
912 {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
913 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
914
dec41383
JW		 915 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
916 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
917 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
918 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
919 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
920 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
921 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
922 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
923 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
924 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
925 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
926 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
927 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
928 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
929 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
930 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
931 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
932
05413229 933 /* V5 coprocessor instructions. */
823d2571
TG		 934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
935 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
937 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
939 0xfe000000, 0xff000010,
940 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
942 0xfe000010, 0xff100010,
943 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
945 0xfe100010, 0xff100010,
946 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
947
b0c11777
RL		 948 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
949 cp_num: bit <11:8> == 0b1001.
950 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
951 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
952 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
953 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
954 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
955 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
956 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
957 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
958 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
959 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
960 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
961 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
962 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
963 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
964 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
965 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
966 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
967 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
968 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
969 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
970 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
971 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
972 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
973 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
974 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
975 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
976 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
977 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
978 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
979 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
980 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
981 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
982 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
983 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
984 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
985 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
986 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
987 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
988 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
989 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
990 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
991 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
992 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
993 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
994 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
995 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
996 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
997 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
998 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
999 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1000 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1001 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1002 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1003 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1004 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1005 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1006 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1007 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1008 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1009 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1010 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1011 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1012 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1013 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1014 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1015 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1016 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1017 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1018 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1019 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1020 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1021
49e8a725
SN		 1022 /* ARMv8.3 javascript conversion instruction. */
1023 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1024 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1025
823d2571 1026 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 1027};
1028
16980d0b
JB		 1029/* Neon opcode table: This does not encode the top byte -- that is
1030 checked by the print_insn_neon routine, as it depends on whether we are
1031 doing thumb32 or arm32 disassembly. */
1032
1033/* print_insn_neon recognizes the following format control codes:
1034
1035 %% %
1036
c22aaad1 1037 %c print condition code
e2efe87d
MGD		 1038 %u print condition code (unconditional in ARM mode,
1039 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 1040 %A print v{st,ld}[1234] operands
1041 %B print v{st,ld}[1234] any one operands
1042 %C print v{st,ld}[1234] single->all operands
1043 %D print scalar
1044 %E print vmov, vmvn, vorr, vbic encoded constant
1045 %F print vtbl,vtbx register list
1046
1047 %<bitfield>r print as an ARM register
1048 %<bitfield>d print the bitfield in decimal
1049 %<bitfield>e print the 2^N - bitfield in decimal
1050 %<bitfield>D print as a NEON D register
1051 %<bitfield>Q print as a NEON Q register
1052 %<bitfield>R print as a NEON D or Q register
1053 %<bitfield>Sn print byte scaled width limited by n
1054 %<bitfield>Tn print short scaled width limited by n
1055 %<bitfield>Un print long scaled width limited by n
43e65147 1056
16980d0b
JB		 1057 %<bitfield>'c print specified char iff bitfield is all ones
1058 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1059 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1060
1061static const struct opcode32 neon_opcodes[] =
1062{
fe56b6ce 1063 /* Extract. */
823d2571
TG		 1064 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1065 0xf2b00840, 0xffb00850,
1066 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1067 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1068 0xf2b00000, 0xffb00810,
1069 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 1070
fe56b6ce 1071 /* Move data element to all lanes. */
823d2571
TG		 1072 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1073 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1074 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1075 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1076 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1077 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 1078
fe56b6ce 1079 /* Table lookup. */
823d2571
TG		 1080 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1081 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1082 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1083 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1084
8e79c3df 1085 /* Half-precision conversions. */
823d2571
TG		 1086 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1087 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1088 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1089 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1090
1091 /* NEON fused multiply add instructions. */
823d2571 1092 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1093 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1094 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1095 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1096 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1097 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1098 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1099 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1100
fe56b6ce 1101 /* Two registers, miscellaneous. */
823d2571
TG		 1102 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1103 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1104 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1105 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1106 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1107 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1108 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1109 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1110 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1111 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1112 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1113 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1114 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1115 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1116 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1117 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1118 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1119 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1120 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1121 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1122 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1123 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1124 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1125 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1126 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1127 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1128 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1129 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1130 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1131 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1132 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1133 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1134 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1135 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1136 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1137 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1138 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1139 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1140 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1141 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1142 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1143 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1144 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1145 0xf3b20300, 0xffb30fd0,
1146 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1147 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1148 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1149 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1150 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1151 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1152 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1153 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1154 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1155 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1156 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1157 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1158 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1159 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1160 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1161 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1162 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1163 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1164 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1165 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1166 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1167 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1168 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1169 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1170 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1171 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1172 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1173 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1174 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1175 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1176 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1177 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1178 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1179 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1180 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1181 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1182 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1183 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1184 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1185 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1186 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1187 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1188 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1189 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1190 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1191 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1192 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1193 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301 1194 0xf3bb0600, 0xffbf0e10,
823d2571 1195 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1196 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1197 0xf3b70600, 0xffbf0e10,
1198 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
16980d0b 1199
fe56b6ce 1200 /* Three registers of the same length. */
823d2571
TG		 1201 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1202 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1203 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1204 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1205 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1206 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1207 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1208 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1209 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1210 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1211 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1212 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1213 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1214 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1215 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1216 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1217 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1218 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1219 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1220 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1221 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1222 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1223 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1224 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1225 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1226 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1227 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1228 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1229 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1230 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1231 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1232 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1233 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1234 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1235 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1236 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1237 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1238 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1239 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1240 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1241 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1242 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1243 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1244 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1245 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1246 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1247 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1248 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1249 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1250 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1251 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1252 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1253 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1254 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1255 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1256 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1257 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1258 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1259 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1260 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1261 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1262 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1263 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1264 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1265 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1266 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1267 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1268 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1269 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1270 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1271 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1272 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1273 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1274 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1275 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1276 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1277 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1278 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1279 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1280 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1281 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1282 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1283 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1284 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1285 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1286 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1287 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1288 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1289 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1290 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1291 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1292 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1293 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1294 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1295 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1296 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1297 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1298 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1299 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1300 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1301 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1302 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1303 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1304 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1305 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1306 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1307 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1308 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1309 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1310 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1311 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1312 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1313 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1314 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1315 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1316 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1317 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1318 0xf2000b00, 0xff800f10,
1319 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1320 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1321 0xf2000b10, 0xff800f10,
1322 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1323 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1324 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1325 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1326 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1327 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1328 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1329 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1330 0xf3000b00, 0xff800f10,
1331 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1332 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1333 0xf2000000, 0xfe800f10,
1334 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1335 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1336 0xf2000010, 0xfe800f10,
1337 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1338 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1339 0xf2000100, 0xfe800f10,
1340 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1341 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1342 0xf2000200, 0xfe800f10,
1343 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1344 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1345 0xf2000210, 0xfe800f10,
1346 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1347 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1348 0xf2000300, 0xfe800f10,
1349 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1350 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1351 0xf2000310, 0xfe800f10,
1352 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1353 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1354 0xf2000400, 0xfe800f10,
1355 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1356 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1357 0xf2000410, 0xfe800f10,
1358 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1359 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1360 0xf2000500, 0xfe800f10,
1361 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1362 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1363 0xf2000510, 0xfe800f10,
1364 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1365 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1366 0xf2000600, 0xfe800f10,
1367 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1368 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1369 0xf2000610, 0xfe800f10,
1370 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1371 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1372 0xf2000700, 0xfe800f10,
1373 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1374 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1375 0xf2000710, 0xfe800f10,
1376 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1377 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1378 0xf2000910, 0xfe800f10,
1379 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1380 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1381 0xf2000a00, 0xfe800f10,
1382 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1383 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1384 0xf2000a10, 0xfe800f10,
1385 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1386 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1387 0xf3000b10, 0xff800f10,
1388 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1389 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1390 0xf3000c10, 0xff800f10,
1391 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1392
fe56b6ce 1393 /* One register and an immediate value. */
823d2571
TG		 1394 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1395 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1396 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1397 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1398 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1399 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1400 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1401 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1402 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1403 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1404 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1405 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1406 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1407 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1408 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1409 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1410 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1411 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1412 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1413 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1414 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1415 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1416 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1417 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1418 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1419 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1420
fe56b6ce 1421 /* Two registers and a shift amount. */
823d2571
TG		 1422 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1423 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1424 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1425 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1426 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1427 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1428 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1429 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1430 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1431 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1432 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1433 0xf2880950, 0xfeb80fd0,
1434 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1435 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1436 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1437 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1438 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1439 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1440 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1441 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1442 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1443 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1444 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1445 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1446 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1447 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1448 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1449 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1450 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1451 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1452 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1453 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1454 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1456 0xf2900950, 0xfeb00fd0,
1457 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1458 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1459 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1460 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1461 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1462 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1463 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1465 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1466 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1467 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1468 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1469 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1470 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1471 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1473 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1474 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1475 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1477 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1478 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1479 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1481 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1482 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1483 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1484 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1485 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1487 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1489 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1490 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1491 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1492 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1493 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1494 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1495 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1496 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1497 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1498 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1499 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1500 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1501 0xf2a00950, 0xfea00fd0,
1502 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1503 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1504 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1511 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1512 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1515 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1517 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1518 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1519 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1520 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1521 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1522 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1523 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1524 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1525 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1526 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1527 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1528 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1530 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1531 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1532 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1533 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1534 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1535 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1536 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1537 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1538 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1539 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1540 0xf2a00e10, 0xfea00e90,
1541 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
cc933301
JW		 1542 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1543 0xf2a00c10, 0xfea00e90,
1544 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 1545
fe56b6ce 1546 /* Three registers of different lengths. */
823d2571
TG		 1547 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1548 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1549 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1550 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1551 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1552 0xf2800400, 0xff800f50,
1553 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1554 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1555 0xf2800600, 0xff800f50,
1556 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1557 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1558 0xf2800900, 0xff800f50,
1559 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1560 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1561 0xf2800b00, 0xff800f50,
1562 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1564 0xf2800d00, 0xff800f50,
1565 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1566 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1567 0xf3800400, 0xff800f50,
1568 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1569 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1570 0xf3800600, 0xff800f50,
1571 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1572 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1573 0xf2800000, 0xfe800f50,
1574 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1576 0xf2800100, 0xfe800f50,
1577 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1578 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1579 0xf2800200, 0xfe800f50,
1580 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1581 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1582 0xf2800300, 0xfe800f50,
1583 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1584 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1585 0xf2800500, 0xfe800f50,
1586 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1587 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1588 0xf2800700, 0xfe800f50,
1589 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1590 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1591 0xf2800800, 0xfe800f50,
1592 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1594 0xf2800a00, 0xfe800f50,
1595 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1596 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1597 0xf2800c00, 0xfe800f50,
1598 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 1599
fe56b6ce 1600 /* Two registers and a scalar. */
823d2571
TG		 1601 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1602 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1603 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1604 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1605 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1606 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1607 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1608 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1609 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1610 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1611 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1612 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1613 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1614 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1615 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1616 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1618 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1619 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1620 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1621 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1622 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1623 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1624 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1625 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1626 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1627 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1628 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1630 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1631 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1632 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1633 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1634 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1635 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1636 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1638 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1639 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1640 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1642 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1643 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1644 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1645 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1646 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1647 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1648 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1650 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1651 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1652 0xf2800240, 0xfe800f50,
1653 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1654 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1655 0xf2800640, 0xfe800f50,
1656 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1658 0xf2800a40, 0xfe800f50,
1659 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 1660 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1661 0xf2800e40, 0xff800f50,
1662 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1663 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1664 0xf2800f40, 0xff800f50,
1665 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1666 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1667 0xf3800e40, 0xff800f50,
1668 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1669 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1670 0xf3800f40, 0xff800f50,
1671 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1672 },
16980d0b 1673
fe56b6ce 1674 /* Element and structure load/store. */
823d2571
TG		 1675 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1676 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1677 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1678 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1679 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1680 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1681 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1682 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1683 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1684 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1685 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1686 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1687 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1688 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1689 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1690 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1691 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1692 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1693 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1694 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1695 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1696 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1697 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1698 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1699 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1700 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1701 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1702 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1703 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1704 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1705 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1706 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1707 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1708 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1709 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1710 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1711 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1712 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1713
1714 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 1715};
1716
8f06b2d8
PB		 1717/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
1718 ordered: they must be searched linearly from the top to obtain a correct
1719 match. */
1720
1721/* print_insn_arm recognizes the following format control codes:
1722
1723 %% %
1724
1725 %a print address for ldr/str instruction
1726 %s print address for ldr/str halfword/signextend instruction
c1e26897 1727 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 1728 %b print branch destination
1729 %c print condition code (always bits 28-31)
1730 %m print register mask for ldm/stm instruction
1731 %o print operand2 (immediate or register + shift)
1732 %p print 'p' iff bits 12-15 are 15
1733 %t print 't' iff bit 21 set and bit 24 clear
1734 %B print arm BLX(1) destination
1735 %C print the PSR sub type.
62b3e311
PB		 1736 %U print barrier type.
1737 %P print address for pli instruction.
8f06b2d8
PB		 1738
1739 %<bitfield>r print as an ARM register
9eb6c0f1 1740 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 1741 %<bitfield>R as %r but r15 is UNPREDICTABLE
1742 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1743 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 1744 %<bitfield>d print the bitfield in decimal
43e65147 1745 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 1746 %<bitfield>x print the bitfield in hex
1747 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 1748
16980d0b
JB		 1749 %<bitfield>'c print specified char iff bitfield is all ones
1750 %<bitfield>`c print specified char iff bitfield is all zeroes
1751 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 1752
8f06b2d8
PB		 1753 %e print arm SMI operand (bits 0..7,8..19).
1754 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 1755 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
1756 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 1757
8f06b2d8
PB		 1758static const struct opcode32 arm_opcodes[] =
1759{
1760 /* ARM instructions. */
823d2571
TG		 1761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1762 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1764 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1765
1766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
1767 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1769 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1771 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
1773 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1775 0x00800090, 0x0fa000f0,
1776 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1778 0x00a00090, 0x0fa000f0,
1779 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 1780
105bde57 1781 /* V8.2 RAS extension instructions. */
4d1464f2 1782 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 1783 0xe320f010, 0xffffffff, "esb"},
1784
53c4b28b 1785 /* V8 instructions. */
823d2571
TG		 1786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1787 0x0320f005, 0x0fffffff, "sevl"},
1788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1789 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
4ed7ed8d 1790 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 1791 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1792 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 1793 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1795 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1797 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 1798 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1799 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1800 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1801 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1802 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1803 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1804 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1805 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1806 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1807 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1808 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1809 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1810 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1811 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1812 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1813 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1814 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1815 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1816 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 1817 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 1818 /* CRC32 instructions. */
823d2571
TG		 1819 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1820 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
1821 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1822 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
1823 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1824 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
1825 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1826 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
1827 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1828 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
1829 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1830 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 1831
ddfded2f
MW		 1832 /* Privileged Access Never extension instructions. */
1833 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
1834 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
1835
90ec0d68 1836 /* Virtualization Extension instructions. */
823d2571
TG		 1837 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
1838 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 1839
eea54501 1840 /* Integer Divide Extension instructions. */
823d2571
TG		 1841 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1842 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1843 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1844 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 1845
60e5ef9f 1846 /* MP Extension instructions. */
823d2571 1847 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 1848
62b3e311 1849 /* V7 instructions. */
823d2571
TG		 1850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
1851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
1853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
1854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a
AV		 1857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
1858 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
62b3e311 1859
c19d1205 1860 /* ARM V6T2 instructions. */
823d2571
TG		 1861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1862 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1864 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1866 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1868 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
1869
1870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1871 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
1872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1873 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1874
ff8646ee 1875 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 1876 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 1877 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 1878 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1880 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1882 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 1883
f4c65163 1884 /* ARM Security extension instructions. */
823d2571
TG		 1885 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
1886 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 1887
8f06b2d8 1888 /* ARM V6K instructions. */
823d2571
TG		 1889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1890 0xf57ff01f, 0xffffffff, "clrex"},
1891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1892 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1894 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1896 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1898 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1900 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1902 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 1903
8f06b2d8 1904 /* ARM V6K NOP hints. */
823d2571
TG		 1905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1906 0x0320f001, 0x0fffffff, "yield%c"},
1907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1908 0x0320f002, 0x0fffffff, "wfe%c"},
1909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1910 0x0320f003, 0x0fffffff, "wfi%c"},
1911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1912 0x0320f004, 0x0fffffff, "sev%c"},
1913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1914 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 1915
fe56b6ce 1916 /* ARM V6 instructions. */
823d2571
TG		 1917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1918 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
1919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1920 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
1921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1922 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
1923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1924 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
1925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1926 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
1927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1928 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
1929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1930 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
1931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1932 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
1933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1934 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
1935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1936 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
1937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1938 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
1939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1940 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
1941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1942 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
1943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1944 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
1945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1946 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
1947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1948 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
1949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1950 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
1951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1952 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
1953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1954 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
1955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1956 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
1957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1958 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
1959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1960 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
1961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1962 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
1963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1964 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
1965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1966 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
1967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1968 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
1969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1970 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
1971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1972 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
1973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1974 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
1975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1976 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
1977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1978 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
1979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1980 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
1981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1982 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
1983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1984 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
1985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1986 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
1987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1988 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
1989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1990 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
1991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1992 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
1993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1994 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
1995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1996 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
1997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1998 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
1999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2000 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
2001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2002 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
2003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2004 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
2005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2006 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
2007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2008 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
2009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2010 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
2011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2012 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
2013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2014 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
2015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2016 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
2017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2018 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
2019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2020 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
2021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2022 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
2023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2024 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
2025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2026 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
2027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2028 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
2029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2030 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
2031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2032 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
2033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2034 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
2035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2036 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
2037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2038 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
2039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2040 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
2041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2042 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
2043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2044 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
2045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2046 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
2047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2048 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
2049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2050 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
2051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2052 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
2053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2054 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
2055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2056 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
2057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2058 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
2059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2060 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
2061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2062 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
2063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2064 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
2065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2066 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
2067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2068 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2070 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2072 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2074 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
2075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2076 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2078 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2080 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2082 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
2083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2084 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2086 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2088 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2090 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
2091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2092 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2094 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2096 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2098 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
2099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2100 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2102 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2104 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
2105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2106 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
2107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2108 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2110 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2112 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2114 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
2115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2116 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
2117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2118 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
2119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2120 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
2121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2122 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2124 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2126 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2128 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2130 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
2131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2132 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2134 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2136 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
2137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2138 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
2139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2140 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
2141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2142 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
2143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2144 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
2145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2146 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
2147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2148 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
2149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2150 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
2151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2152 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2154 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
2155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2156 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
2157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2158 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
2159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2160 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 2161
8f06b2d8 2162 /* V5J instruction. */
823d2571
TG		 2163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
2164 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 2165
8f06b2d8 2166 /* V5 Instructions. */
823d2571
TG		 2167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2168 0xe1200070, 0xfff000f0,
2169 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
2170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2171 0xfa000000, 0xfe000000, "blx\t%B"},
2172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2173 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
2174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2175 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
2176
2177 /* V5E "El Segundo" Instructions. */
2178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2179 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
2180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2181 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
2182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2183 0xf450f000, 0xfc70f000, "pld\t%a"},
2184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2185 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2187 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2189 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2191 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
2192
2193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2194 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2196 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
2197
2198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2199 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2201 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2203 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2205 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2206
2207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2208 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2210 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2212 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2214 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2215
2216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2217 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2219 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2220
2221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2222 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
2223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2224 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2226 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
2227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2228 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 2229
8f06b2d8 2230 /* ARM Instructions. */
823d2571
TG		 2231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2232 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2233
2234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2235 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2237 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2238 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2239 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2240 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2241 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2243 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2245 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2246
2247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2248 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2250 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2252 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2254 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2255
2256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2257 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2259 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2261 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2263 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2264
2265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2266 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2268 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2270 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2271
2272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2273 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2275 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2277 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2278
2279 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2280 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2281 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2282 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2283 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2284 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2285
2286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2287 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2289 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2291 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2292
2293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2294 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2295 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2296 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2297 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2298 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2299
2300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2301 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2302 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2303 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2304 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2305 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2306
2307 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2308 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2310 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2312 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2313
2314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2315 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2317 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2319 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2320
2321 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2322 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2323 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2324 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2325 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2326 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2327
2328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2329 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2331 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2333 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2334
2335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2336 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 2337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2338 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 2339 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2340 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
823d2571
TG		 2341
2342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2343 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2345 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2347 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2348
2349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2350 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2352 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2354 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2355
2356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2357 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2359 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2361 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2362
2363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2364 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2366 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2368 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2370 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2372 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2374 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2376 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2377
2378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2379 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2381 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2383 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2384
2385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2386 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2388 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2390 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2391
2392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2393 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2395 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2396
2397 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2398 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2399
2400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2401 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2403 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2404
2405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2406 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2408 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2410 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2411 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2412 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2413 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2414 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2415 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2416 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2418 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2419 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2420 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2422 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2424 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2425 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2426 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2427 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2428 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2429 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2430 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2431 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2432 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2433 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2434 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2435 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2436 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2437 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2438 0x092d0000, 0x0fff0000, "push%c\t%m"},
2439 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2440 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2441 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2442 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2443
2444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2445 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2447 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2448 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2449 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2451 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2453 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2455 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2457 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2459 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2461 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2463 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2465 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2467 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2469 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2471 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2473 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2475 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2476 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2477 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2478 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2479 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2480 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2481 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2482
2483 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2484 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2485 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2486 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 2487
2488 /* The rest. */
4ab90a7a
AV		 2489 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2490 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 2491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2492 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2493 {ARM_FEATURE_CORE_LOW (0),
2494 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 2495};
2496
2497/* print_insn_thumb16 recognizes the following format control codes:
2498
2499 %S print Thumb register (bits 3..5 as high number if bit 6 set)
2500 %D print Thumb register (bits 0..2 as high number if bit 7 set)
2501 %<bitfield>I print bitfield as a signed decimal
2502 (top bit of range being the sign bit)
2503 %N print Thumb register mask (with LR)
2504 %O print Thumb register mask (with PC)
2505 %M print Thumb register mask
2506 %b print CZB's 6-bit unsigned branch destination
2507 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 2508 %c print the condition code
2509 %C print the condition code, or "s" if not conditional
2510 %x print warning if conditional an not at end of IT block"
2511 %X print "\t; unpredictable <IT:code>" if conditional
2512 %I print IT instruction suffix and operands
4547cb56 2513 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 2514 %<bitfield>r print bitfield as an ARM register
2515 %<bitfield>d print bitfield as a decimal
2516 %<bitfield>H print (bitfield * 2) as a decimal
2517 %<bitfield>W print (bitfield * 4) as a decimal
2518 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
2519 %<bitfield>B print Thumb branch destination (signed displacement)
2520 %<bitfield>c print bitfield as a condition code
2521 %<bitnum>'c print specified char iff bit is one
2522 %<bitnum>?ab print a if bit is one else print b. */
2523
2524static const struct opcode16 thumb_opcodes[] =
2525{
2526 /* Thumb instructions. */
2527
16a1fa25
TP		 2528 /* ARMv8-M Security Extensions instructions. */
2529 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
2530 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff07, "bxns\t%3-6r"},
2531
53c4b28b 2532 /* ARM V8 instructions. */
823d2571
TG		 2533 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
2534 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
ddfded2f 2535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
53c4b28b 2536
8f06b2d8 2537 /* ARM V6K no-argument instructions. */
823d2571
TG		 2538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2539 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2541 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 2544
2545 /* ARM V6T2 instructions. */
ff8646ee
TP		 2546 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2547 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2548 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2549 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 2550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 2551
2552 /* ARM V6. */
823d2571
TG		 2553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2555 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2557 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2559 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2563 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 2564
2565 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 2566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2567 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 2568 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 2569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2570 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 2571 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 2572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2573 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 2574 /* Format 4. */
823d2571
TG		 2575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2579 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 2591 /* format 13 */
823d2571
TG		 2592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 2594 /* format 5 */
823d2571
TG		 2595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
2596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
2597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 2599 /* format 14 */
823d2571
TG		 2600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
2601 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 2602 /* format 2 */
823d2571
TG		 2603 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2604 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2606 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2608 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2610 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 2611 /* format 8 */
823d2571
TG		 2612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2613 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2615 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2617 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2618 /* format 7 */
823d2571
TG		 2619 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2620 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2622 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2623 /* format 1 */
823d2571
TG		 2624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2626 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2627 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 2629 /* format 3 */
823d2571
TG		 2630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2631 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 2634 /* format 6 */
823d2571
TG		 2635 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2637 0x4800, 0xF800,
2638 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 2639 /* format 9 */
823d2571
TG		 2640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2641 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2643 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2645 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2647 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 2648 /* format 10 */
823d2571
TG		 2649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2650 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2652 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 2653 /* format 11 */
823d2571
TG		 2654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2655 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2657 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 2658 /* format 12 */
823d2571
TG		 2659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2660 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2662 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 2663 /* format 15 */
823d2571
TG		 2664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 2666 /* format 17 */
823d2571 2667 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 2668 /* format 16 */
823d2571
TG		 2669 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
2671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 2672 /* format 18 */
823d2571 2673 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 2674
2675 /* The E800 .. FFFF range is unconditionally redirected to the
2676 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2677 are processed via that table. Thus, we can never encounter a
2678 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 2679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
2680 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 2681};
2682
2683/* Thumb32 opcodes use the same table structure as the ARM opcodes.
2684 We adopt the convention that hw1 is the high 16 bits of .value and
2685 .mask, hw2 the low 16 bits.
2686
2687 print_insn_thumb32 recognizes the following format control codes:
2688
2689 %% %
2690
2691 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2692 %M print a modified 12-bit immediate (same location)
2693 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2694 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 2695 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 2696 %S print a possibly-shifted Rm
2697
32a94698 2698 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 2699 %a print the address of a plain load/store
2700 %w print the width and signedness of a core load/store
2701 %m print register mask for ldm/stm
2702
2703 %E print the lsb and width fields of a bfc/bfi instruction
2704 %F print the lsb and width fields of a sbfx/ubfx instruction
2705 %b print a conditional branch offset
2706 %B print an unconditional branch offset
2707 %s print the shift field of an SSAT instruction
2708 %R print the rotation field of an SXT instruction
62b3e311
PB		 2709 %U print barrier type.
2710 %P print address for pli instruction.
c22aaad1
PB		 2711 %c print the condition code
2712 %x print warning if conditional an not at end of IT block"
2713 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 2714
2715 %<bitfield>d print bitfield in decimal
f0fba320 2716 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 2717 %<bitfield>W print bitfield*4 in decimal
2718 %<bitfield>r print bitfield as an ARM register
dd5181d5 2719 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
8f06b2d8
PB		 2720 %<bitfield>c print bitfield as a condition code
2721
16980d0b
JB		 2722 %<bitfield>'c print specified char iff bitfield is all ones
2723 %<bitfield>`c print specified char iff bitfield is all zeroes
2724 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 2725
2726 With one exception at the bottom (done because BL and BLX(1) need
2727 to come dead last), this table was machine-sorted first in
2728 decreasing order of number of bits set in the mask, then in
2729 increasing numeric order of mask, then in increasing numeric order
2730 of opcode. This order is not the clearest for a human reader, but
2731 is guaranteed never to catch a special-case bit pattern with a more
2732 general mask, which is important, because this instruction encoding
2733 makes heavy use of special-case bit patterns. */
2734static const struct opcode32 thumb32_opcodes[] =
2735{
16a1fa25
TP		 2736 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
2737 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4ed7ed8d
TP		 2738 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2739 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
2740 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2741 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
16a1fa25
TP		 2742 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2743 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
2744 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2745 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4ed7ed8d 2746
105bde57 2747 /* ARM V8.2 RAS extension instructions. */
4d1464f2 2748 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 2749 0xf3af8010, 0xffffffff, "esb"},
2750
53c4b28b 2751 /* V8 instructions. */
823d2571
TG		 2752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2753 0xf3af8005, 0xffffffff, "sevl%c.w"},
2754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2755 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2757 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2759 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
2760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2761 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
2762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2763 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
2764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2765 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
2766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2767 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
2768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2769 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
2770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2771 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2773 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2775 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
2776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2777 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2779 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2781 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2783 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 2784
dd5181d5 2785 /* CRC32 instructions. */
823d2571 2786 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2787 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
823d2571 2788 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2789 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
823d2571 2790 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2791 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
823d2571 2792 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2793 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
823d2571 2794 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2795 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
823d2571 2796 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2797 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
dd5181d5 2798
62b3e311 2799 /* V7 instructions. */
823d2571
TG		 2800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
2801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
2802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
2803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
2804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
2805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
2806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
2807 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2808 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
2809 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2810 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 2811
90ec0d68 2812 /* Virtualization Extension instructions. */
823d2571 2813 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 2814 /* We skip ERET as that is SUBS pc, lr, #0. */
2815
60e5ef9f 2816 /* MP Extension instructions. */
823d2571 2817 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 2818
f4c65163 2819 /* Security extension instructions. */
823d2571 2820 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 2821
8f06b2d8 2822 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 2823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
2824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
2825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
2828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2829 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
2830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
2831
ff8646ee 2832 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2833 0xf3bf8f2f, 0xffffffff, "clrex%c"},
2834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2835 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
2836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2837 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
2838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2839 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
2840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2841 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
2842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2843 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
2844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2845 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
2846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2847 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
2848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2849 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
2850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2851 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
2852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2853 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
2854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2855 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
2856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2857 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
2858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2859 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 2860 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 2861 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 2862 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2863 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
2864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2865 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
2866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2867 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
2868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2869 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
2870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2871 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
2872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2873 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
2874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2875 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
2876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2877 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
2878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2879 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 2880 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2881 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
2882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2883 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
2884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2885 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
2886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2887 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
2888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2889 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
2890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2891 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
2892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2893 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
2894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2895 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
2896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2897 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
2898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2899 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
2900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2901 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
2902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2903 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
2904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2905 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
2906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2907 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
2908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2909 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
2910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2911 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
2912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2913 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
2914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2915 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
2916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2917 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
2918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2919 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
2920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2921 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
2922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2923 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
2924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2925 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
2926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2927 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
2928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2929 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
2930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2931 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
2932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2933 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
2934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2935 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
2936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2937 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
2938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2939 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
2940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2941 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
2942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2943 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
2944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2945 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
2946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2947 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
2948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2949 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
2950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2951 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
2952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2953 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
2954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2955 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
2956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2957 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
2958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2959 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
2960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2961 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
2962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2963 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
2964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2965 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
2966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2967 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
2968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2969 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
2970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2971 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
2972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2973 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
2974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2975 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
2976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2977 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
2978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2979 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
2980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2981 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2983 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2985 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2987 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 2988 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2989 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
2990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 2991 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 2992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2993 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
2994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2995 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
2996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2997 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2999 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
3000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3001 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
3002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3003 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3005 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3007 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3009 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3011 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3013 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3015 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3017 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
3018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3019 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
3020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3021 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
3022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3023 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
3024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3025 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
3026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3027 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
3028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3029 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
3030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3031 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
3032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3033 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
3034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3035 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
3036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3037 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
3038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3039 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
3040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3041 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3043 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3045 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3047 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3049 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3051 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3053 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3055 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 3056 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3057 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
3058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3059 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
3060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3061 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
3062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3063 0xf810f000, 0xff70f000, "pld%c\t%a"},
3064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3065 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3067 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3069 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3071 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3073 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3075 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3077 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3079 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
3080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3081 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
3082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3083 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
3084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3085 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
3086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3087 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
3088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3089 0xfb100000, 0xfff000c0,
3090 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3092 0xfbc00080, 0xfff000c0,
3093 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
3094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3095 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
3096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3097 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
3098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 3099 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 3100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3101 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
3102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3103 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 3104 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3105 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
3106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3107 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 3108 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3109 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
3110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3111 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
3112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3113 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
3114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3115 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
3116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3117 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
3118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3119 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
3120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3121 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
3122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3123 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
3124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3125 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
3126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3127 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
3128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3129 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 3130 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3131 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
3132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3133 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
3134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3135 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
3136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3137 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
3138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3139 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
3140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3141 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
3142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3143 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
3144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3145 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
3146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3147 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
3148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3149 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
3150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3151 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
3152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3153 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
3154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3155 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
3156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3157 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
3158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3159 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
3160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3161 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
3162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3163 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
3164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3165 0xe9400000, 0xff500000,
3166 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3168 0xe9500000, 0xff500000,
3169 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3171 0xe8600000, 0xff700000,
3172 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3174 0xe8700000, 0xff700000,
3175 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3177 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
3178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3179 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 3180
3181 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 3182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3183 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
3184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3185 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
3186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3187 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
3188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3189 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 3190
8f06b2d8 3191 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 3192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3193 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
3194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3195 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 3196
3197 /* Fallback. */
823d2571
TG		 3198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3199 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3200 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 3201};
ff4a8d2b 3202
8f06b2d8
PB		 3203static const char *const arm_conditional[] =
3204{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 3205 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 3206
3207static const char *const arm_fp_const[] =
3208{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3209
3210static const char *const arm_shift[] =
3211{"lsl", "lsr", "asr", "ror"};
3212
3213typedef struct
3214{
3215 const char *name;
3216 const char *description;
3217 const char *reg_names[16];
3218}
3219arm_regname;
3220
3221static const arm_regname regnames[] =
3222{
65b48a81 3223 { "reg-names-raw", N_("Select raw register names"),
8f06b2d8 3224 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
65b48a81 3225 { "reg-names-gcc", N_("Select register names used by GCC"),
8f06b2d8 3226 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 3227 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
8f06b2d8 3228 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65b48a81
PB		 3229 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
3230 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
3231 { "reg-names-apcs", N_("Select register names used in the APCS"),
8f06b2d8 3232 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 3233 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
8f06b2d8 3234 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
65b48a81
PB		 3235 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
3236 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
8f06b2d8
PB		 3237};
3238
3239static const char *const iwmmxt_wwnames[] =
3240{"b", "h", "w", "d"};
3241
3242static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 3243{"b", "bus", "bc", "bss",
3244 "h", "hus", "hc", "hss",
3245 "w", "wus", "wc", "wss",
3246 "d", "dus", "dc", "dss"
8f06b2d8
PB		 3247};
3248
3249static const char *const iwmmxt_regnames[] =
3250{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3251 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3252};
3253
3254static const char *const iwmmxt_cregnames[] =
3255{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3256 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3257};
3258
3259/* Default to GCC register name set. */
3260static unsigned int regname_selected = 1;
3261
65b48a81 3262#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
8f06b2d8
PB		 3263#define arm_regnames regnames[regname_selected].reg_names
3264
3265static bfd_boolean force_thumb = FALSE;
3266
c22aaad1
PB		 3267/* Current IT instruction state. This contains the same state as the IT
3268 bits in the CPSR. */
3269static unsigned int ifthen_state;
3270/* IT state for the next instruction. */
3271static unsigned int ifthen_next_state;
3272/* The address of the insn for which the IT state is valid. */
3273static bfd_vma ifthen_address;
3274#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 3275/* Indicates that the current Conditional state is unconditional or outside
3276 an IT block. */
3277#define COND_UNCOND 16
c22aaad1 3278
8f06b2d8
PB		 3279\f
3280/* Functions. */
8f06b2d8 3281
16980d0b
JB		 3282/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3283 Returns pointer to following character of the format string and
3284 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 3285 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 3286
3287static const char *
fe56b6ce
NC		 3288arm_decode_bitfield (const char *ptr,
3289 unsigned long insn,
3290 unsigned long *valuep,
3291 int *widthp)
16980d0b
JB		 3292{
3293 unsigned long value = 0;
3294 int width = 0;
43e65147
L		 3295
3296 do
16980d0b
JB		 3297 {
3298 int start, end;
3299 int bits;
3300
3301 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3302 start = start * 10 + *ptr - '0';
3303 if (*ptr == '-')
3304 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3305 end = end * 10 + *ptr - '0';
3306 else
3307 end = start;
3308 bits = end - start;
3309 if (bits < 0)
3310 abort ();
3311 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3312 width += bits + 1;
3313 }
3314 while (*ptr++ == ',');
3315 *valuep = value;
3316 if (widthp)
3317 *widthp = width;
3318 return ptr - 1;
3319}
3320
8f06b2d8 3321static void
37b37b2d 3322arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 3323 bfd_boolean print_shift)
8f06b2d8
PB		 3324{
3325 func (stream, "%s", arm_regnames[given & 0xf]);
3326
3327 if ((given & 0xff0) != 0)
3328 {
3329 if ((given & 0x10) == 0)
3330 {
3331 int amount = (given & 0xf80) >> 7;
3332 int shift = (given & 0x60) >> 5;
3333
3334 if (amount == 0)
3335 {
3336 if (shift == 3)
3337 {
3338 func (stream, ", rrx");
3339 return;
3340 }
3341
3342 amount = 32;
3343 }
3344
37b37b2d
RE		 3345 if (print_shift)
3346 func (stream, ", %s #%d", arm_shift[shift], amount);
3347 else
3348 func (stream, ", #%d", amount);
8f06b2d8 3349 }
74bdfecf 3350 else if ((given & 0x80) == 0x80)
aefd8a40 3351 func (stream, "\t; <illegal shifter operand>");
37b37b2d 3352 else if (print_shift)
8f06b2d8
PB		 3353 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3354 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 3355 else
3356 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 3357 }
3358}
3359
c1e26897
NC		 3360#define W_BIT 21
3361#define I_BIT 22
3362#define U_BIT 23
3363#define P_BIT 24
3364
3365#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
3366#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
3367#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
3368#define PRE_BIT_SET (given & (1 << P_BIT))
3369
8f06b2d8
PB		 3370/* Print one coprocessor instruction on INFO->STREAM.
3371 Return TRUE if the instuction matched, FALSE if this is not a
3372 recognised coprocessor instruction. */
3373
3374static bfd_boolean
fe56b6ce
NC		 3375print_insn_coprocessor (bfd_vma pc,
3376 struct disassemble_info *info,
3377 long given,
8f06b2d8
PB		 3378 bfd_boolean thumb)
3379{
3380 const struct opcode32 *insn;
3381 void *stream = info->stream;
3382 fprintf_ftype func = info->fprintf_func;
3383 unsigned long mask;
2edcd244 3384 unsigned long value = 0;
c22aaad1 3385 int cond;
8afc7bea 3386 int cp_num;
823d2571
TG		 3387 struct arm_private_data *private_data = info->private_data;
3388 arm_feature_set allowed_arches = ARM_ARCH_NONE;
3389
3390 ARM_FEATURE_COPY (allowed_arches, private_data->features);
8f06b2d8
PB		 3391
3392 for (insn = coprocessor_opcodes; insn->assembler; insn++)
3393 {
ff4a8d2b
NC		 3394 unsigned long u_reg = 16;
3395 bfd_boolean is_unpredictable = FALSE;
05413229 3396 signed long value_in_comment = 0;
0313a2b8
NC		 3397 const char *c;
3398
823d2571 3399 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 3400 switch (insn->value)
3401 {
3402 case SENTINEL_IWMMXT_START:
3403 if (info->mach != bfd_mach_arm_XScale
3404 && info->mach != bfd_mach_arm_iWMMXt
3405 && info->mach != bfd_mach_arm_iWMMXt2)
3406 do
3407 insn++;
823d2571
TG		 3408 while ((! ARM_FEATURE_ZERO (insn->arch))
3409 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 3410 continue;
3411
3412 case SENTINEL_IWMMXT_END:
3413 continue;
3414
3415 case SENTINEL_GENERIC_START:
823d2571 3416 ARM_FEATURE_COPY (allowed_arches, private_data->features);
05413229
NC		 3417 continue;
3418
3419 default:
3420 abort ();
3421 }
8f06b2d8
PB		 3422
3423 mask = insn->mask;
3424 value = insn->value;
8afc7bea
RL		 3425 cp_num = (given >> 8) & 0xf;
3426
8f06b2d8
PB		 3427 if (thumb)
3428 {
3429 /* The high 4 bits are 0xe for Arm conditional instructions, and
3430 0xe for arm unconditional instructions. The rest of the
3431 encoding is the same. */
3432 mask |= 0xf0000000;
3433 value |= 0xe0000000;
c22aaad1
PB		 3434 if (ifthen_state)
3435 cond = IFTHEN_COND;
3436 else
e2efe87d 3437 cond = COND_UNCOND;
8f06b2d8
PB		 3438 }
3439 else
3440 {
3441 /* Only match unconditional instuctions against unconditional
3442 patterns. */
3443 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 3444 {
3445 mask |= 0xf0000000;
e2efe87d 3446 cond = COND_UNCOND;
c22aaad1
PB		 3447 }
3448 else
3449 {
3450 cond = (given >> 28) & 0xf;
3451 if (cond == 0xe)
e2efe87d 3452 cond = COND_UNCOND;
c22aaad1 3453 }
8f06b2d8 3454 }
823d2571 3455
0313a2b8
NC		 3456 if ((given & mask) != value)
3457 continue;
8f06b2d8 3458
823d2571 3459 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 3460 continue;
3461
8afc7bea
RL		 3462 if (insn->value == 0xfe000010 /* mcr2 */
3463 || insn->value == 0xfe100010 /* mrc2 */
3464 || insn->value == 0xfc100000 /* ldc2 */
3465 || insn->value == 0xfc000000) /* stc2 */
3466 {
b0c11777 3467 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea
RL		 3468 is_unpredictable = TRUE;
3469 }
3470 else if (insn->value == 0x0e000000 /* cdp */
3471 || insn->value == 0xfe000000 /* cdp2 */
3472 || insn->value == 0x0e000010 /* mcr */
3473 || insn->value == 0x0e100010 /* mrc */
3474 || insn->value == 0x0c100000 /* ldc */
3475 || insn->value == 0x0c000000) /* stc */
3476 {
3477 /* Floating-point instructions. */
b0c11777 3478 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea
RL		 3479 continue;
3480 }
3481
0313a2b8
NC		 3482 for (c = insn->assembler; *c; c++)
3483 {
3484 if (*c == '%')
8f06b2d8 3485 {
0313a2b8 3486 switch (*++c)
8f06b2d8 3487 {
0313a2b8
NC		 3488 case '%':
3489 func (stream, "%%");
3490 break;
3491
3492 case 'A':
05413229 3493 {
79862e45 3494 int rn = (given >> 16) & 0xf;
b0c11777 3495 bfd_vma offset = given & 0xff;
0313a2b8 3496
05413229 3497 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 3498
79862e45
DJ		 3499 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
3500 {
3501 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 3502 if (cp_num == 9)
3503 /* vldr.16/vstr.16 will shift the address
3504 left by 1 bit only. */
3505 offset = offset * 2;
3506 else
3507 offset = offset * 4;
3508
79862e45
DJ		 3509 if (NEGATIVE_BIT_SET)
3510 offset = - offset;
3511 if (rn != 15)
3512 value_in_comment = offset;
3513 }
3514
c1e26897 3515 if (PRE_BIT_SET)
05413229
NC		 3516 {
3517 if (offset)
fe56b6ce 3518 func (stream, ", #%d]%s",
d908c8af 3519 (int) offset,
c1e26897 3520 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 3521 else if (NEGATIVE_BIT_SET)
3522 func (stream, ", #-0]");
05413229
NC		 3523 else
3524 func (stream, "]");
3525 }
3526 else
3527 {
0313a2b8 3528 func (stream, "]");
8f06b2d8 3529
c1e26897 3530 if (WRITEBACK_BIT_SET)
05413229
NC		 3531 {
3532 if (offset)
d908c8af 3533 func (stream, ", #%d", (int) offset);
26d97720
NS		 3534 else if (NEGATIVE_BIT_SET)
3535 func (stream, ", #-0");
05413229
NC		 3536 }
3537 else
fe56b6ce 3538 {
26d97720
NS		 3539 func (stream, ", {%s%d}",
3540 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 3541 (int) offset);
fe56b6ce
NC		 3542 value_in_comment = offset;
3543 }
05413229 3544 }
79862e45
DJ		 3545 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
3546 {
3547 func (stream, "\t; ");
6844b2c2
MGD		 3548 /* For unaligned PCs, apply off-by-alignment
3549 correction. */
43e65147 3550 info->print_address_func (offset + pc
6844b2c2
MGD		 3551 + info->bytes_per_chunk * 2
3552 - (pc & 3),
3553 info);
79862e45 3554 }
05413229 3555 }
0313a2b8 3556 break;
8f06b2d8 3557
0313a2b8
NC		 3558 case 'B':
3559 {
3560 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
3561 int offset = (given >> 1) & 0x3f;
3562
3563 if (offset == 1)
3564 func (stream, "{d%d}", regno);
3565 else if (regno + offset > 32)
3566 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
3567 else
3568 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
3569 }
3570 break;
8f06b2d8 3571
e2efe87d
MGD		 3572 case 'u':
3573 if (cond != COND_UNCOND)
3574 is_unpredictable = TRUE;
3575
3576 /* Fall through. */
0313a2b8 3577 case 'c':
b0c11777
RL		 3578 if (cond != COND_UNCOND && cp_num == 9)
3579 is_unpredictable = TRUE;
3580
0313a2b8
NC		 3581 func (stream, "%s", arm_conditional[cond]);
3582 break;
8f06b2d8 3583
0313a2b8
NC		 3584 case 'I':
3585 /* Print a Cirrus/DSP shift immediate. */
3586 /* Immediates are 7bit signed ints with bits 0..3 in
3587 bits 0..3 of opcode and bits 4..6 in bits 5..7
3588 of opcode. */
3589 {
3590 int imm;
8f06b2d8 3591
0313a2b8 3592 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 3593
0313a2b8
NC		 3594 /* Is ``imm'' a negative number? */
3595 if (imm & 0x40)
24b4cf66 3596 imm -= 0x80;
8f06b2d8 3597
0313a2b8
NC		 3598 func (stream, "%d", imm);
3599 }
3600
3601 break;
8f06b2d8 3602
0313a2b8
NC		 3603 case 'F':
3604 switch (given & 0x00408000)
3605 {
3606 case 0:
3607 func (stream, "4");
3608 break;
3609 case 0x8000:
3610 func (stream, "1");
3611 break;
3612 case 0x00400000:
3613 func (stream, "2");
8f06b2d8 3614 break;
0313a2b8
NC		 3615 default:
3616 func (stream, "3");
3617 }
3618 break;
8f06b2d8 3619
0313a2b8
NC		 3620 case 'P':
3621 switch (given & 0x00080080)
3622 {
3623 case 0:
3624 func (stream, "s");
3625 break;
3626 case 0x80:
3627 func (stream, "d");
3628 break;
3629 case 0x00080000:
3630 func (stream, "e");
3631 break;
3632 default:
3633 func (stream, _("<illegal precision>"));
8f06b2d8 3634 break;
0313a2b8
NC		 3635 }
3636 break;
8f06b2d8 3637
0313a2b8
NC		 3638 case 'Q':
3639 switch (given & 0x00408000)
3640 {
3641 case 0:
3642 func (stream, "s");
8f06b2d8 3643 break;
0313a2b8
NC		 3644 case 0x8000:
3645 func (stream, "d");
8f06b2d8 3646 break;
0313a2b8
NC		 3647 case 0x00400000:
3648 func (stream, "e");
3649 break;
3650 default:
3651 func (stream, "p");
8f06b2d8 3652 break;
0313a2b8
NC		 3653 }
3654 break;
8f06b2d8 3655
0313a2b8
NC		 3656 case 'R':
3657 switch (given & 0x60)
3658 {
3659 case 0:
3660 break;
3661 case 0x20:
3662 func (stream, "p");
3663 break;
3664 case 0x40:
3665 func (stream, "m");
3666 break;
3667 default:
3668 func (stream, "z");
3669 break;
3670 }
3671 break;
16980d0b 3672
0313a2b8
NC		 3673 case '0': case '1': case '2': case '3': case '4':
3674 case '5': case '6': case '7': case '8': case '9':
3675 {
3676 int width;
8f06b2d8 3677
0313a2b8 3678 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 3679
0313a2b8
NC		 3680 switch (*c)
3681 {
ff4a8d2b
NC		 3682 case 'R':
3683 if (value == 15)
3684 is_unpredictable = TRUE;
3685 /* Fall through. */
0313a2b8 3686 case 'r':
ff4a8d2b
NC		 3687 if (c[1] == 'u')
3688 {
3689 /* Eat the 'u' character. */
3690 ++ c;
3691
3692 if (u_reg == value)
3693 is_unpredictable = TRUE;
3694 u_reg = value;
3695 }
0313a2b8
NC		 3696 func (stream, "%s", arm_regnames[value]);
3697 break;
c28eeff2
SN		 3698 case 'V':
3699 if (given & (1 << 6))
3700 goto Q;
3701 /* FALLTHROUGH */
0313a2b8
NC		 3702 case 'D':
3703 func (stream, "d%ld", value);
3704 break;
3705 case 'Q':
c28eeff2 3706 Q:
0313a2b8
NC		 3707 if (value & 1)
3708 func (stream, "<illegal reg q%ld.5>", value >> 1);
3709 else
3710 func (stream, "q%ld", value >> 1);
3711 break;
3712 case 'd':
3713 func (stream, "%ld", value);
05413229 3714 value_in_comment = value;
0313a2b8 3715 break;
6f1c2142
AM		 3716 case 'E':
3717 {
3718 /* Converts immediate 8 bit back to float value. */
3719 unsigned floatVal = (value & 0x80) << 24
3720 | (value & 0x3F) << 19
3721 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
3722
3723 /* Quarter float have a maximum value of 31.0.
3724 Get floating point value multiplied by 1e7.
3725 The maximum value stays in limit of a 32-bit int. */
3726 unsigned decVal =
3727 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
3728 (16 + (value & 0xF));
3729
3730 if (!(decVal % 1000000))
3731 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
3732 floatVal, value & 0x80 ? '-' : ' ',
3733 decVal / 10000000,
3734 decVal % 10000000 / 1000000);
3735 else if (!(decVal % 10000))
3736 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
3737 floatVal, value & 0x80 ? '-' : ' ',
3738 decVal / 10000000,
3739 decVal % 10000000 / 10000);
3740 else
3741 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
3742 floatVal, value & 0x80 ? '-' : ' ',
3743 decVal / 10000000, decVal % 10000000);
3744 break;
3745 }
0313a2b8
NC		 3746 case 'k':
3747 {
3748 int from = (given & (1 << 7)) ? 32 : 16;
3749 func (stream, "%ld", from - value);
3750 }
3751 break;
8f06b2d8 3752
0313a2b8
NC		 3753 case 'f':
3754 if (value > 7)
3755 func (stream, "#%s", arm_fp_const[value & 7]);
3756 else
3757 func (stream, "f%ld", value);
3758 break;
4146fd53 3759
0313a2b8
NC		 3760 case 'w':
3761 if (width == 2)
3762 func (stream, "%s", iwmmxt_wwnames[value]);
3763 else
3764 func (stream, "%s", iwmmxt_wwssnames[value]);
3765 break;
4146fd53 3766
0313a2b8
NC		 3767 case 'g':
3768 func (stream, "%s", iwmmxt_regnames[value]);
3769 break;
3770 case 'G':
3771 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 3772 break;
8f06b2d8 3773
0313a2b8 3774 case 'x':
d1aaab3c 3775 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 3776 break;
8f06b2d8 3777
33399f07
MGD		 3778 case 'c':
3779 switch (value)
3780 {
3781 case 0:
3782 func (stream, "eq");
3783 break;
3784
3785 case 1:
3786 func (stream, "vs");
3787 break;
3788
3789 case 2:
3790 func (stream, "ge");
3791 break;
3792
3793 case 3:
3794 func (stream, "gt");
3795 break;
3796
3797 default:
3798 func (stream, "??");
3799 break;
3800 }
3801 break;
3802
0313a2b8
NC		 3803 case '`':
3804 c++;
3805 if (value == 0)
3806 func (stream, "%c", *c);
3807 break;
3808 case '\'':
3809 c++;
3810 if (value == ((1ul << width) - 1))
3811 func (stream, "%c", *c);
3812 break;
3813 case '?':
fe56b6ce 3814 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 3815 c += 1 << width;
3816 break;
3817 default:
3818 abort ();
3819 }
3820 break;
8f06b2d8 3821
0313a2b8
NC		 3822 case 'y':
3823 case 'z':
3824 {
3825 int single = *c++ == 'y';
3826 int regno;
3827
3828 switch (*c)
3829 {
3830 case '4': /* Sm pair */
3831 case '0': /* Sm, Dm */
3832 regno = given & 0x0000000f;
3833 if (single)
3834 {
3835 regno <<= 1;
3836 regno += (given >> 5) & 1;
16980d0b 3837 }
0313a2b8
NC		 3838 else
3839 regno += ((given >> 5) & 1) << 4;
3840 break;
8f06b2d8 3841
0313a2b8
NC		 3842 case '1': /* Sd, Dd */
3843 regno = (given >> 12) & 0x0000000f;
3844 if (single)
3845 {
3846 regno <<= 1;
3847 regno += (given >> 22) & 1;
3848 }
3849 else
3850 regno += ((given >> 22) & 1) << 4;
3851 break;
8f06b2d8 3852
0313a2b8
NC		 3853 case '2': /* Sn, Dn */
3854 regno = (given >> 16) & 0x0000000f;
3855 if (single)
8f06b2d8 3856 {
0313a2b8
NC		 3857 regno <<= 1;
3858 regno += (given >> 7) & 1;
8f06b2d8 3859 }
0313a2b8
NC		 3860 else
3861 regno += ((given >> 7) & 1) << 4;
3862 break;
7df76b80 3863
0313a2b8
NC		 3864 case '3': /* List */
3865 func (stream, "{");
3866 regno = (given >> 12) & 0x0000000f;
3867 if (single)
3868 {
3869 regno <<= 1;
3870 regno += (given >> 22) & 1;
3871 }
3872 else
3873 regno += ((given >> 22) & 1) << 4;
3874 break;
a7f8487e 3875
0313a2b8
NC		 3876 default:
3877 abort ();
8f06b2d8 3878 }
a7f8487e 3879
0313a2b8
NC		 3880 func (stream, "%c%d", single ? 's' : 'd', regno);
3881
3882 if (*c == '3')
8f06b2d8 3883 {
0313a2b8 3884 int count = given & 0xff;
a7f8487e 3885
0313a2b8
NC		 3886 if (single == 0)
3887 count >>= 1;
b34976b6 3888
0313a2b8 3889 if (--count)
8f06b2d8 3890 {
0313a2b8
NC		 3891 func (stream, "-%c%d",
3892 single ? 's' : 'd',
3893 regno + count);
8f06b2d8 3894 }
0313a2b8
NC		 3895
3896 func (stream, "}");
8f06b2d8 3897 }
0313a2b8
NC		 3898 else if (*c == '4')
3899 func (stream, ", %c%d", single ? 's' : 'd',
3900 regno + 1);
3901 }
3902 break;
3903
3904 case 'L':
3905 switch (given & 0x00400100)
3906 {
3907 case 0x00000000: func (stream, "b"); break;
3908 case 0x00400000: func (stream, "h"); break;
3909 case 0x00000100: func (stream, "w"); break;
3910 case 0x00400100: func (stream, "d"); break;
3911 default:
8f06b2d8 3912 break;
0313a2b8
NC		 3913 }
3914 break;
b34976b6 3915
0313a2b8
NC		 3916 case 'Z':
3917 {
0313a2b8
NC		 3918 /* given (20, 23) | given (0, 3) */
3919 value = ((given >> 16) & 0xf0) | (given & 0xf);
d908c8af 3920 func (stream, "%d", (int) value);
0313a2b8
NC		 3921 }
3922 break;
2d447fca 3923
0313a2b8
NC		 3924 case 'l':
3925 /* This is like the 'A' operator, except that if
3926 the width field "M" is zero, then the offset is
3927 *not* multiplied by four. */
3928 {
3929 int offset = given & 0xff;
3930 int multiplier = (given & 0x00000100) ? 4 : 1;
3931
3932 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3933
05413229
NC		 3934 if (multiplier > 1)
3935 {
3936 value_in_comment = offset * multiplier;
c1e26897 3937 if (NEGATIVE_BIT_SET)
05413229
NC		 3938 value_in_comment = - value_in_comment;
3939 }
3940
0313a2b8
NC		 3941 if (offset)
3942 {
c1e26897 3943 if (PRE_BIT_SET)
0313a2b8 3944 func (stream, ", #%s%d]%s",
c1e26897 3945 NEGATIVE_BIT_SET ? "-" : "",
0313a2b8 3946 offset * multiplier,
c1e26897 3947 WRITEBACK_BIT_SET ? "!" : "");
0313a2b8
NC		 3948 else
3949 func (stream, "], #%s%d",
c1e26897 3950 NEGATIVE_BIT_SET ? "-" : "",
0313a2b8 3951 offset * multiplier);
2d447fca 3952 }
0313a2b8
NC		 3953 else
3954 func (stream, "]");
3955 }
3956 break;
3957
3958 case 'r':
3959 {
3960 int imm4 = (given >> 4) & 0xf;
c1e26897
NC		 3961 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
3962 int ubit = ! NEGATIVE_BIT_SET;
0313a2b8
NC		 3963 const char *rm = arm_regnames [given & 0xf];
3964 const char *rn = arm_regnames [(given >> 16) & 0xf];
2d447fca 3965
0313a2b8 3966 switch (puw_bits)
2d447fca 3967 {
0313a2b8
NC		 3968 case 1:
3969 case 3:
3970 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
3971 if (imm4)
3972 func (stream, ", lsl #%d", imm4);
3973 break;
3974
3975 case 4:
3976 case 5:
3977 case 6:
3978 case 7:
3979 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
3980 if (imm4 > 0)
3981 func (stream, ", lsl #%d", imm4);
3982 func (stream, "]");
3983 if (puw_bits == 5 || puw_bits == 7)
3984 func (stream, "!");
3985 break;
3986
3987 default:
3988 func (stream, "INVALID");
2d447fca 3989 }
0313a2b8
NC		 3990 }
3991 break;
2d447fca 3992
0313a2b8
NC		 3993 case 'i':
3994 {
3995 long imm5;
3996 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
3997 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
8f06b2d8 3998 }
0313a2b8
NC		 3999 break;
4000
4001 default:
4002 abort ();
4003 }
252b5132 4004 }
252b5132 4005 }
0313a2b8
NC		 4006 else
4007 func (stream, "%c", *c);
252b5132 4008 }
05413229
NC		 4009
4010 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 4011 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 4012
ff4a8d2b
NC		 4013 if (is_unpredictable)
4014 func (stream, UNPREDICTABLE_INSTRUCTION);
4015
0313a2b8 4016 return TRUE;
252b5132 4017 }
8f06b2d8 4018 return FALSE;
252b5132
RH		 4019}
4020
05413229
NC		 4021/* Decodes and prints ARM addressing modes. Returns the offset
4022 used in the address, if any, if it is worthwhile printing the
4023 offset as a hexadecimal value in a comment at the end of the
4024 line of disassembly. */
4025
4026static signed long
62b3e311
PB		 4027print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
4028{
4029 void *stream = info->stream;
4030 fprintf_ftype func = info->fprintf_func;
f8b960bc 4031 bfd_vma offset = 0;
62b3e311
PB		 4032
4033 if (((given & 0x000f0000) == 0x000f0000)
4034 && ((given & 0x02000000) == 0))
4035 {
05413229 4036 offset = given & 0xfff;
62b3e311
PB		 4037
4038 func (stream, "[pc");
4039
c1e26897 4040 if (PRE_BIT_SET)
62b3e311 4041 {
26d97720
NS		 4042 /* Pre-indexed. Elide offset of positive zero when
4043 non-writeback. */
4044 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 4045 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 4046
4047 if (NEGATIVE_BIT_SET)
4048 offset = -offset;
62b3e311
PB		 4049
4050 offset += pc + 8;
4051
4052 /* Cope with the possibility of write-back
4053 being used. Probably a very dangerous thing
4054 for the programmer to do, but who are we to
4055 argue ? */
26d97720 4056 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 4057 }
c1e26897 4058 else /* Post indexed. */
62b3e311 4059 {
d908c8af 4060 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 4061
c1e26897 4062 /* Ie ignore the offset. */
62b3e311
PB		 4063 offset = pc + 8;
4064 }
4065
4066 func (stream, "\t; ");
4067 info->print_address_func (offset, info);
05413229 4068 offset = 0;
62b3e311
PB		 4069 }
4070 else
4071 {
4072 func (stream, "[%s",
4073 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 4074
4075 if (PRE_BIT_SET)
62b3e311
PB		 4076 {
4077 if ((given & 0x02000000) == 0)
4078 {
26d97720 4079 /* Elide offset of positive zero when non-writeback. */
05413229 4080 offset = given & 0xfff;
26d97720 4081 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 4082 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 4083 }
4084 else
4085 {
26d97720 4086 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 4087 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 4088 }
4089
4090 func (stream, "]%s",
c1e26897 4091 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 4092 }
4093 else
4094 {
4095 if ((given & 0x02000000) == 0)
4096 {
26d97720 4097 /* Always show offset. */
05413229 4098 offset = given & 0xfff;
26d97720 4099 func (stream, "], #%s%d",
d908c8af 4100 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 4101 }
4102 else
4103 {
4104 func (stream, "], %s",
c1e26897 4105 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 4106 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 4107 }
4108 }
84919466
MR		 4109 if (NEGATIVE_BIT_SET)
4110 offset = -offset;
62b3e311 4111 }
05413229
NC		 4112
4113 return (signed long) offset;
62b3e311
PB		 4114}
4115
16980d0b
JB		 4116/* Print one neon instruction on INFO->STREAM.
4117 Return TRUE if the instuction matched, FALSE if this is not a
4118 recognised neon instruction. */
4119
4120static bfd_boolean
4121print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
4122{
4123 const struct opcode32 *insn;
4124 void *stream = info->stream;
4125 fprintf_ftype func = info->fprintf_func;
4126
4127 if (thumb)
4128 {
4129 if ((given & 0xef000000) == 0xef000000)
4130 {
0313a2b8 4131 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 4132 unsigned long bit28 = given & (1 << 28);
4133
4134 given &= 0x00ffffff;
4135 if (bit28)
4136 given |= 0xf3000000;
4137 else
4138 given |= 0xf2000000;
4139 }
4140 else if ((given & 0xff000000) == 0xf9000000)
4141 given ^= 0xf9000000 ^ 0xf4000000;
4142 else
4143 return FALSE;
4144 }
43e65147 4145
16980d0b
JB		 4146 for (insn = neon_opcodes; insn->assembler; insn++)
4147 {
4148 if ((given & insn->mask) == insn->value)
4149 {
05413229 4150 signed long value_in_comment = 0;
e2efe87d 4151 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 4152 const char *c;
4153
4154 for (c = insn->assembler; *c; c++)
4155 {
4156 if (*c == '%')
4157 {
4158 switch (*++c)
4159 {
4160 case '%':
4161 func (stream, "%%");
4162 break;
4163
e2efe87d
MGD		 4164 case 'u':
4165 if (thumb && ifthen_state)
4166 is_unpredictable = TRUE;
4167
4168 /* Fall through. */
c22aaad1
PB		 4169 case 'c':
4170 if (thumb && ifthen_state)
4171 func (stream, "%s", arm_conditional[IFTHEN_COND]);
4172 break;
4173
16980d0b
JB		 4174 case 'A':
4175 {
43e65147 4176 static const unsigned char enc[16] =
16980d0b
JB		 4177 {
4178 0x4, 0x14, /* st4 0,1 */
4179 0x4, /* st1 2 */
4180 0x4, /* st2 3 */
4181 0x3, /* st3 4 */
4182 0x13, /* st3 5 */
4183 0x3, /* st1 6 */
4184 0x1, /* st1 7 */
4185 0x2, /* st2 8 */
4186 0x12, /* st2 9 */
4187 0x2, /* st1 10 */
4188 0, 0, 0, 0, 0
4189 };
4190 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4191 int rn = ((given >> 16) & 0xf);
4192 int rm = ((given >> 0) & 0xf);
4193 int align = ((given >> 4) & 0x3);
4194 int type = ((given >> 8) & 0xf);
4195 int n = enc[type] & 0xf;
4196 int stride = (enc[type] >> 4) + 1;
4197 int ix;
43e65147 4198
16980d0b
JB		 4199 func (stream, "{");
4200 if (stride > 1)
4201 for (ix = 0; ix != n; ix++)
4202 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
4203 else if (n == 1)
4204 func (stream, "d%d", rd);
4205 else
4206 func (stream, "d%d-d%d", rd, rd + n - 1);
4207 func (stream, "}, [%s", arm_regnames[rn]);
4208 if (align)
8e560766 4209 func (stream, " :%d", 32 << align);
16980d0b
JB		 4210 func (stream, "]");
4211 if (rm == 0xd)
4212 func (stream, "!");
4213 else if (rm != 0xf)
4214 func (stream, ", %s", arm_regnames[rm]);
4215 }
4216 break;
43e65147 4217
16980d0b
JB		 4218 case 'B':
4219 {
4220 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4221 int rn = ((given >> 16) & 0xf);
4222 int rm = ((given >> 0) & 0xf);
4223 int idx_align = ((given >> 4) & 0xf);
4224 int align = 0;
4225 int size = ((given >> 10) & 0x3);
4226 int idx = idx_align >> (size + 1);
4227 int length = ((given >> 8) & 3) + 1;
4228 int stride = 1;
4229 int i;
4230
4231 if (length > 1 && size > 0)
4232 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 4233
16980d0b
JB		 4234 switch (length)
4235 {
4236 case 1:
4237 {
4238 int amask = (1 << size) - 1;
4239 if ((idx_align & (1 << size)) != 0)
4240 return FALSE;
4241 if (size > 0)
4242 {
4243 if ((idx_align & amask) == amask)
4244 align = 8 << size;
4245 else if ((idx_align & amask) != 0)
4246 return FALSE;
4247 }
4248 }
4249 break;
43e65147 4250
16980d0b
JB		 4251 case 2:
4252 if (size == 2 && (idx_align & 2) != 0)
4253 return FALSE;
4254 align = (idx_align & 1) ? 16 << size : 0;
4255 break;
43e65147 4256
16980d0b
JB		 4257 case 3:
4258 if ((size == 2 && (idx_align & 3) != 0)
4259 || (idx_align & 1) != 0)
4260 return FALSE;
4261 break;
43e65147 4262
16980d0b
JB		 4263 case 4:
4264 if (size == 2)
4265 {
4266 if ((idx_align & 3) == 3)
4267 return FALSE;
4268 align = (idx_align & 3) * 64;
4269 }
4270 else
4271 align = (idx_align & 1) ? 32 << size : 0;
4272 break;
43e65147 4273
16980d0b
JB		 4274 default:
4275 abort ();
4276 }
43e65147 4277
16980d0b
JB		 4278 func (stream, "{");
4279 for (i = 0; i < length; i++)
4280 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
4281 rd + i * stride, idx);
4282 func (stream, "}, [%s", arm_regnames[rn]);
4283 if (align)
8e560766 4284 func (stream, " :%d", align);
16980d0b
JB		 4285 func (stream, "]");
4286 if (rm == 0xd)
4287 func (stream, "!");
4288 else if (rm != 0xf)
4289 func (stream, ", %s", arm_regnames[rm]);
4290 }
4291 break;
43e65147 4292
16980d0b
JB		 4293 case 'C':
4294 {
4295 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4296 int rn = ((given >> 16) & 0xf);
4297 int rm = ((given >> 0) & 0xf);
4298 int align = ((given >> 4) & 0x1);
4299 int size = ((given >> 6) & 0x3);
4300 int type = ((given >> 8) & 0x3);
4301 int n = type + 1;
4302 int stride = ((given >> 5) & 0x1);
4303 int ix;
43e65147 4304
16980d0b
JB		 4305 if (stride && (n == 1))
4306 n++;
4307 else
4308 stride++;
43e65147 4309
16980d0b
JB		 4310 func (stream, "{");
4311 if (stride > 1)
4312 for (ix = 0; ix != n; ix++)
4313 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
4314 else if (n == 1)
4315 func (stream, "d%d[]", rd);
4316 else
4317 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
4318 func (stream, "}, [%s", arm_regnames[rn]);
4319 if (align)
4320 {
91d6fa6a 4321 align = (8 * (type + 1)) << size;
16980d0b
JB		 4322 if (type == 3)
4323 align = (size > 1) ? align >> 1 : align;
4324 if (type == 2 || (type == 0 && !size))
8e560766 4325 func (stream, " :<bad align %d>", align);
16980d0b 4326 else
8e560766 4327 func (stream, " :%d", align);
16980d0b
JB		 4328 }
4329 func (stream, "]");
4330 if (rm == 0xd)
4331 func (stream, "!");
4332 else if (rm != 0xf)
4333 func (stream, ", %s", arm_regnames[rm]);
4334 }
4335 break;
43e65147 4336
16980d0b
JB		 4337 case 'D':
4338 {
4339 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
4340 int size = (given >> 20) & 3;
4341 int reg = raw_reg & ((4 << size) - 1);
4342 int ix = raw_reg >> size >> 2;
43e65147 4343
16980d0b
JB		 4344 func (stream, "d%d[%d]", reg, ix);
4345 }
4346 break;
43e65147 4347
16980d0b 4348 case 'E':
fe56b6ce 4349 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 4350 {
4351 int bits = 0;
4352 int cmode = (given >> 8) & 0xf;
4353 int op = (given >> 5) & 0x1;
4354 unsigned long value = 0, hival = 0;
4355 unsigned shift;
4356 int size = 0;
0dbde4cf 4357 int isfloat = 0;
43e65147 4358
16980d0b
JB		 4359 bits |= ((given >> 24) & 1) << 7;
4360 bits |= ((given >> 16) & 7) << 4;
4361 bits |= ((given >> 0) & 15) << 0;
43e65147 4362
16980d0b
JB		 4363 if (cmode < 8)
4364 {
4365 shift = (cmode >> 1) & 3;
fe56b6ce 4366 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4367 size = 32;
4368 }
4369 else if (cmode < 12)
4370 {
4371 shift = (cmode >> 1) & 1;
fe56b6ce 4372 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4373 size = 16;
4374 }
4375 else if (cmode < 14)
4376 {
4377 shift = (cmode & 1) + 1;
fe56b6ce 4378 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4379 value |= (1ul << (8 * shift)) - 1;
4380 size = 32;
4381 }
4382 else if (cmode == 14)
4383 {
4384 if (op)
4385 {
fe56b6ce 4386 /* Bit replication into bytes. */
16980d0b
JB		 4387 int ix;
4388 unsigned long mask;
43e65147 4389
16980d0b
JB		 4390 value = 0;
4391 hival = 0;
4392 for (ix = 7; ix >= 0; ix--)
4393 {
4394 mask = ((bits >> ix) & 1) ? 0xff : 0;
4395 if (ix <= 3)
4396 value = (value << 8) | mask;
4397 else
4398 hival = (hival << 8) | mask;
4399 }
4400 size = 64;
4401 }
4402 else
4403 {
fe56b6ce
NC		 4404 /* Byte replication. */
4405 value = (unsigned long) bits;
16980d0b
JB		 4406 size = 8;
4407 }
4408 }
4409 else if (!op)
4410 {
fe56b6ce 4411 /* Floating point encoding. */
16980d0b 4412 int tmp;
43e65147 4413
fe56b6ce
NC		 4414 value = (unsigned long) (bits & 0x7f) << 19;
4415 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 4416 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 4417 value |= (unsigned long) tmp << 24;
16980d0b 4418 size = 32;
0dbde4cf 4419 isfloat = 1;
16980d0b
JB		 4420 }
4421 else
4422 {
4423 func (stream, "<illegal constant %.8x:%x:%x>",
4424 bits, cmode, op);
4425 size = 32;
4426 break;
4427 }
4428 switch (size)
4429 {
4430 case 8:
4431 func (stream, "#%ld\t; 0x%.2lx", value, value);
4432 break;
43e65147 4433
16980d0b
JB		 4434 case 16:
4435 func (stream, "#%ld\t; 0x%.4lx", value, value);
4436 break;
4437
4438 case 32:
0dbde4cf
JB		 4439 if (isfloat)
4440 {
4441 unsigned char valbytes[4];
4442 double fvalue;
43e65147 4443
0dbde4cf
JB		 4444 /* Do this a byte at a time so we don't have to
4445 worry about the host's endianness. */
4446 valbytes[0] = value & 0xff;
4447 valbytes[1] = (value >> 8) & 0xff;
4448 valbytes[2] = (value >> 16) & 0xff;
4449 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 4450
4451 floatformat_to_double
c1e26897
NC		 4452 (& floatformat_ieee_single_little, valbytes,
4453 & fvalue);
43e65147 4454
0dbde4cf
JB		 4455 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
4456 value);
4457 }
4458 else
4e9d3b81 4459 func (stream, "#%ld\t; 0x%.8lx",
43e65147 4460 (long) (((value & 0x80000000L) != 0)
9d82ec38 4461 ? value | ~0xffffffffL : value),
c1e26897 4462 value);
16980d0b
JB		 4463 break;
4464
4465 case 64:
4466 func (stream, "#0x%.8lx%.8lx", hival, value);
4467 break;
43e65147 4468
16980d0b
JB		 4469 default:
4470 abort ();
4471 }
4472 }
4473 break;
43e65147 4474
16980d0b
JB		 4475 case 'F':
4476 {
4477 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
4478 int num = (given >> 8) & 0x3;
43e65147 4479
16980d0b
JB		 4480 if (!num)
4481 func (stream, "{d%d}", regno);
4482 else if (num + regno >= 32)
4483 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
4484 else
4485 func (stream, "{d%d-d%d}", regno, regno + num);
4486 }
4487 break;
7e8e6784 4488
16980d0b
JB		 4489
4490 case '0': case '1': case '2': case '3': case '4':
4491 case '5': case '6': case '7': case '8': case '9':
4492 {
4493 int width;
4494 unsigned long value;
4495
4496 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 4497
16980d0b
JB		 4498 switch (*c)
4499 {
4500 case 'r':
4501 func (stream, "%s", arm_regnames[value]);
4502 break;
4503 case 'd':
4504 func (stream, "%ld", value);
05413229 4505 value_in_comment = value;
16980d0b
JB		 4506 break;
4507 case 'e':
4508 func (stream, "%ld", (1ul << width) - value);
4509 break;
43e65147 4510
16980d0b
JB		 4511 case 'S':
4512 case 'T':
4513 case 'U':
05413229 4514 /* Various width encodings. */
16980d0b
JB		 4515 {
4516 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
4517 int limit;
4518 unsigned low, high;
4519
4520 c++;
4521 if (*c >= '0' && *c <= '9')
4522 limit = *c - '0';
4523 else if (*c >= 'a' && *c <= 'f')
4524 limit = *c - 'a' + 10;
4525 else
4526 abort ();
4527 low = limit >> 2;
4528 high = limit & 3;
4529
4530 if (value < low || value > high)
4531 func (stream, "<illegal width %d>", base << value);
4532 else
4533 func (stream, "%d", base << value);
4534 }
4535 break;
4536 case 'R':
4537 if (given & (1 << 6))
4538 goto Q;
4539 /* FALLTHROUGH */
4540 case 'D':
4541 func (stream, "d%ld", value);
4542 break;
4543 case 'Q':
4544 Q:
4545 if (value & 1)
4546 func (stream, "<illegal reg q%ld.5>", value >> 1);
4547 else
4548 func (stream, "q%ld", value >> 1);
4549 break;
43e65147 4550
16980d0b
JB		 4551 case '`':
4552 c++;
4553 if (value == 0)
4554 func (stream, "%c", *c);
4555 break;
4556 case '\'':
4557 c++;
4558 if (value == ((1ul << width) - 1))
4559 func (stream, "%c", *c);
4560 break;
4561 case '?':
fe56b6ce 4562 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 4563 c += 1 << width;
4564 break;
4565 default:
4566 abort ();
4567 }
4568 break;
4569
4570 default:
4571 abort ();
4572 }
4573 }
4574 }
4575 else
4576 func (stream, "%c", *c);
4577 }
05413229
NC		 4578
4579 if (value_in_comment > 32 || value_in_comment < -16)
4580 func (stream, "\t; 0x%lx", value_in_comment);
4581
e2efe87d
MGD		 4582 if (is_unpredictable)
4583 func (stream, UNPREDICTABLE_INSTRUCTION);
4584
16980d0b
JB		 4585 return TRUE;
4586 }
4587 }
4588 return FALSE;
4589}
4590
90ec0d68
MGD		 4591/* Return the name of a v7A special register. */
4592
43e65147 4593static const char *
90ec0d68
MGD		 4594banked_regname (unsigned reg)
4595{
4596 switch (reg)
4597 {
4598 case 15: return "CPSR";
43e65147 4599 case 32: return "R8_usr";
90ec0d68
MGD		 4600 case 33: return "R9_usr";
4601 case 34: return "R10_usr";
4602 case 35: return "R11_usr";
4603 case 36: return "R12_usr";
4604 case 37: return "SP_usr";
4605 case 38: return "LR_usr";
43e65147 4606 case 40: return "R8_fiq";
90ec0d68
MGD		 4607 case 41: return "R9_fiq";
4608 case 42: return "R10_fiq";
4609 case 43: return "R11_fiq";
4610 case 44: return "R12_fiq";
4611 case 45: return "SP_fiq";
4612 case 46: return "LR_fiq";
4613 case 48: return "LR_irq";
4614 case 49: return "SP_irq";
4615 case 50: return "LR_svc";
4616 case 51: return "SP_svc";
4617 case 52: return "LR_abt";
4618 case 53: return "SP_abt";
4619 case 54: return "LR_und";
4620 case 55: return "SP_und";
4621 case 60: return "LR_mon";
4622 case 61: return "SP_mon";
4623 case 62: return "ELR_hyp";
4624 case 63: return "SP_hyp";
4625 case 79: return "SPSR";
4626 case 110: return "SPSR_fiq";
4627 case 112: return "SPSR_irq";
4628 case 114: return "SPSR_svc";
4629 case 116: return "SPSR_abt";
4630 case 118: return "SPSR_und";
4631 case 124: return "SPSR_mon";
4632 case 126: return "SPSR_hyp";
4633 default: return NULL;
4634 }
4635}
4636
e797f7e0
MGD		 4637/* Return the name of the DMB/DSB option. */
4638static const char *
4639data_barrier_option (unsigned option)
4640{
4641 switch (option & 0xf)
4642 {
4643 case 0xf: return "sy";
4644 case 0xe: return "st";
4645 case 0xd: return "ld";
4646 case 0xb: return "ish";
4647 case 0xa: return "ishst";
4648 case 0x9: return "ishld";
4649 case 0x7: return "un";
4650 case 0x6: return "unst";
4651 case 0x5: return "nshld";
4652 case 0x3: return "osh";
4653 case 0x2: return "oshst";
4654 case 0x1: return "oshld";
4655 default: return NULL;
4656 }
4657}
4658
4a5329c6
ZW		 4659/* Print one ARM instruction from PC on INFO->STREAM. */
4660
4661static void
4662print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 4663{
6b5d3a4d 4664 const struct opcode32 *insn;
6a51a8a8 4665 void *stream = info->stream;
6b5d3a4d 4666 fprintf_ftype func = info->fprintf_func;
b0e28b39 4667 struct arm_private_data *private_data = info->private_data;
252b5132 4668
16980d0b
JB		 4669 if (print_insn_coprocessor (pc, info, given, FALSE))
4670 return;
4671
4672 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 4673 return;
4674
252b5132
RH		 4675 for (insn = arm_opcodes; insn->assembler; insn++)
4676 {
0313a2b8
NC		 4677 if ((given & insn->mask) != insn->value)
4678 continue;
823d2571
TG		 4679
4680 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 4681 continue;
4682
4683 /* Special case: an instruction with all bits set in the condition field
4684 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
4685 or by the catchall at the end of the table. */
4686 if ((given & 0xF0000000) != 0xF0000000
4687 || (insn->mask & 0xF0000000) == 0xF0000000
4688 || (insn->mask == 0 && insn->value == 0))
252b5132 4689 {
ff4a8d2b
NC		 4690 unsigned long u_reg = 16;
4691 unsigned long U_reg = 16;
ab8e2090 4692 bfd_boolean is_unpredictable = FALSE;
05413229 4693 signed long value_in_comment = 0;
6b5d3a4d 4694 const char *c;
b34976b6 4695
252b5132
RH		 4696 for (c = insn->assembler; *c; c++)
4697 {
4698 if (*c == '%')
4699 {
c1e26897
NC		 4700 bfd_boolean allow_unpredictable = FALSE;
4701
252b5132
RH		 4702 switch (*++c)
4703 {
4704 case '%':
4705 func (stream, "%%");
4706 break;
4707
4708 case 'a':
05413229 4709 value_in_comment = print_arm_address (pc, info, given);
62b3e311 4710 break;
252b5132 4711
62b3e311
PB		 4712 case 'P':
4713 /* Set P address bit and use normal address
4714 printing routine. */
c1e26897 4715 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 4716 break;
4717
c1e26897
NC		 4718 case 'S':
4719 allow_unpredictable = TRUE;
1a0670f3 4720 /* Fall through. */
252b5132
RH		 4721 case 's':
4722 if ((given & 0x004f0000) == 0x004f0000)
4723 {
58efb6c0 4724 /* PC relative with immediate offset. */
f8b960bc 4725 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 4726
aefd8a40
NC		 4727 if (PRE_BIT_SET)
4728 {
26d97720
NS		 4729 /* Elide positive zero offset. */
4730 if (offset || NEGATIVE_BIT_SET)
4731 func (stream, "[pc, #%s%d]\t; ",
d908c8af 4732 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 4733 else
26d97720
NS		 4734 func (stream, "[pc]\t; ");
4735 if (NEGATIVE_BIT_SET)
4736 offset = -offset;
aefd8a40
NC		 4737 info->print_address_func (offset + pc + 8, info);
4738 }
4739 else
4740 {
26d97720
NS		 4741 /* Always show the offset. */
4742 func (stream, "[pc], #%s%d",
d908c8af 4743 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 4744 if (! allow_unpredictable)
4745 is_unpredictable = TRUE;
aefd8a40 4746 }
252b5132
RH		 4747 }
4748 else
4749 {
fe56b6ce
NC		 4750 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
4751
b34976b6 4752 func (stream, "[%s",
252b5132 4753 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 4754
c1e26897 4755 if (PRE_BIT_SET)
252b5132 4756 {
c1e26897 4757 if (IMMEDIATE_BIT_SET)
252b5132 4758 {
26d97720
NS		 4759 /* Elide offset for non-writeback
4760 positive zero. */
4761 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
4762 || offset)
4763 func (stream, ", #%s%d",
4764 NEGATIVE_BIT_SET ? "-" : "", offset);
4765
4766 if (NEGATIVE_BIT_SET)
4767 offset = -offset;
945ee430 4768
fe56b6ce 4769 value_in_comment = offset;
252b5132 4770 }
945ee430 4771 else
ff4a8d2b
NC		 4772 {
4773 /* Register Offset or Register Pre-Indexed. */
4774 func (stream, ", %s%s",
4775 NEGATIVE_BIT_SET ? "-" : "",
4776 arm_regnames[given & 0xf]);
4777
4778 /* Writing back to the register that is the source/
4779 destination of the load/store is unpredictable. */
4780 if (! allow_unpredictable
4781 && WRITEBACK_BIT_SET
4782 && ((given & 0xf) == ((given >> 12) & 0xf)))
4783 is_unpredictable = TRUE;
4784 }
252b5132 4785
b34976b6 4786 func (stream, "]%s",
c1e26897 4787 WRITEBACK_BIT_SET ? "!" : "");
252b5132 4788 }
945ee430 4789 else
252b5132 4790 {
c1e26897 4791 if (IMMEDIATE_BIT_SET)
252b5132 4792 {
945ee430 4793 /* Immediate Post-indexed. */
aefd8a40 4794 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 4795 func (stream, "], #%s%d",
4796 NEGATIVE_BIT_SET ? "-" : "", offset);
4797 if (NEGATIVE_BIT_SET)
4798 offset = -offset;
fe56b6ce 4799 value_in_comment = offset;
252b5132 4800 }
945ee430 4801 else
ff4a8d2b
NC		 4802 {
4803 /* Register Post-indexed. */
4804 func (stream, "], %s%s",
4805 NEGATIVE_BIT_SET ? "-" : "",
4806 arm_regnames[given & 0xf]);
4807
4808 /* Writing back to the register that is the source/
4809 destination of the load/store is unpredictable. */
4810 if (! allow_unpredictable
4811 && (given & 0xf) == ((given >> 12) & 0xf))
4812 is_unpredictable = TRUE;
4813 }
c1e26897 4814
07a28fab
NC		 4815 if (! allow_unpredictable)
4816 {
4817 /* Writeback is automatically implied by post- addressing.
4818 Setting the W bit is unnecessary and ARM specify it as
4819 being unpredictable. */
4820 if (WRITEBACK_BIT_SET
4821 /* Specifying the PC register as the post-indexed
4822 registers is also unpredictable. */
ab8e2090
NC		 4823 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
4824 is_unpredictable = TRUE;
07a28fab 4825 }
252b5132
RH		 4826 }
4827 }
4828 break;
b34976b6 4829
252b5132 4830 case 'b':
6b5d3a4d 4831 {
f8b960bc 4832 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
05413229 4833 info->print_address_func (disp * 4 + pc + 8, info);
6b5d3a4d 4834 }
252b5132
RH		 4835 break;
4836
4837 case 'c':
c22aaad1
PB		 4838 if (((given >> 28) & 0xf) != 0xe)
4839 func (stream, "%s",
4840 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 4841 break;
4842
4843 case 'm':
4844 {
4845 int started = 0;
4846 int reg;
4847
4848 func (stream, "{");
4849 for (reg = 0; reg < 16; reg++)
4850 if ((given & (1 << reg)) != 0)
4851 {
4852 if (started)
4853 func (stream, ", ");
4854 started = 1;
4855 func (stream, "%s", arm_regnames[reg]);
4856 }
4857 func (stream, "}");
ab8e2090
NC		 4858 if (! started)
4859 is_unpredictable = TRUE;
252b5132
RH		 4860 }
4861 break;
4862
37b37b2d 4863 case 'q':
78c66db8 4864 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 4865 break;
4866
252b5132
RH		 4867 case 'o':
4868 if ((given & 0x02000000) != 0)
4869 {
a415b1cd
JB		 4870 unsigned int rotate = (given & 0xf00) >> 7;
4871 unsigned int immed = (given & 0xff);
4872 unsigned int a, i;
4873
4874 a = (((immed << (32 - rotate))
4875 | (immed >> rotate)) & 0xffffffff);
4876 /* If there is another encoding with smaller rotate,
4877 the rotate should be specified directly. */
4878 for (i = 0; i < 32; i += 2)
4879 if ((a << i | a >> (32 - i)) <= 0xff)
4880 break;
4881
4882 if (i != rotate)
4883 func (stream, "#%d, %d", immed, rotate);
4884 else
4885 func (stream, "#%d", a);
4886 value_in_comment = a;
252b5132
RH		 4887 }
4888 else
78c66db8 4889 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 4890 break;
4891
4892 case 'p':
4893 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 4894 {
823d2571
TG		 4895 arm_feature_set arm_ext_v6 =
4896 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
4897
aefd8a40
NC		 4898 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
4899 mechanism for setting PSR flag bits. They are
4900 obsolete in V6 onwards. */
823d2571
TG		 4901 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
4902 arm_ext_v6))
aefd8a40 4903 func (stream, "p");
4ab90a7a
AV		 4904 else
4905 is_unpredictable = TRUE;
aefd8a40 4906 }
252b5132
RH		 4907 break;
4908
4909 case 't':
4910 if ((given & 0x01200000) == 0x00200000)
4911 func (stream, "t");
4912 break;
4913
252b5132 4914 case 'A':
05413229
NC		 4915 {
4916 int offset = given & 0xff;
f02232aa 4917
05413229 4918 value_in_comment = offset * 4;
c1e26897 4919 if (NEGATIVE_BIT_SET)
05413229 4920 value_in_comment = - value_in_comment;
f02232aa 4921
05413229 4922 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 4923
c1e26897 4924 if (PRE_BIT_SET)
05413229
NC		 4925 {
4926 if (offset)
fe56b6ce 4927 func (stream, ", #%d]%s",
d908c8af 4928 (int) value_in_comment,
c1e26897 4929 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 4930 else
4931 func (stream, "]");
4932 }
4933 else
4934 {
4935 func (stream, "]");
f02232aa 4936
c1e26897 4937 if (WRITEBACK_BIT_SET)
05413229
NC		 4938 {
4939 if (offset)
d908c8af 4940 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 4941 }
4942 else
fe56b6ce 4943 {
d908c8af 4944 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 4945 value_in_comment = offset;
4946 }
05413229
NC		 4947 }
4948 }
252b5132
RH		 4949 break;
4950
077b8428
NC		 4951 case 'B':
4952 /* Print ARM V5 BLX(1) address: pc+25 bits. */
4953 {
4954 bfd_vma address;
4955 bfd_vma offset = 0;
b34976b6 4956
c1e26897 4957 if (! NEGATIVE_BIT_SET)
077b8428
NC		 4958 /* Is signed, hi bits should be ones. */
4959 offset = (-1) ^ 0x00ffffff;
4960
4961 /* Offset is (SignExtend(offset field)<<2). */
4962 offset += given & 0x00ffffff;
4963 offset <<= 2;
4964 address = offset + pc + 8;
b34976b6 4965
8f06b2d8
PB		 4966 if (given & 0x01000000)
4967 /* H bit allows addressing to 2-byte boundaries. */
4968 address += 2;
b1ee46c5 4969
8f06b2d8 4970 info->print_address_func (address, info);
b1ee46c5 4971 }
b1ee46c5
AH		 4972 break;
4973
252b5132 4974 case 'C':
90ec0d68
MGD		 4975 if ((given & 0x02000200) == 0x200)
4976 {
4977 const char * name;
4978 unsigned sysm = (given & 0x004f0000) >> 16;
4979
4980 sysm |= (given & 0x300) >> 4;
4981 name = banked_regname (sysm);
4982
4983 if (name != NULL)
4984 func (stream, "%s", name);
4985 else
d908c8af 4986 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 4987 }
4988 else
4989 {
43e65147 4990 func (stream, "%cPSR_",
90ec0d68
MGD		 4991 (given & 0x00400000) ? 'S' : 'C');
4992 if (given & 0x80000)
4993 func (stream, "f");
4994 if (given & 0x40000)
4995 func (stream, "s");
4996 if (given & 0x20000)
4997 func (stream, "x");
4998 if (given & 0x10000)
4999 func (stream, "c");
5000 }
252b5132
RH		 5001 break;
5002
62b3e311 5003 case 'U':
43e65147 5004 if ((given & 0xf0) == 0x60)
62b3e311 5005 {
52e7f43d
RE		 5006 switch (given & 0xf)
5007 {
5008 case 0xf: func (stream, "sy"); break;
5009 default:
5010 func (stream, "#%d", (int) given & 0xf);
5011 break;
5012 }
43e65147
L		 5013 }
5014 else
52e7f43d 5015 {
e797f7e0
MGD		 5016 const char * opt = data_barrier_option (given & 0xf);
5017 if (opt != NULL)
5018 func (stream, "%s", opt);
5019 else
52e7f43d 5020 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 5021 }
5022 break;
5023
b34976b6 5024 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 5025 case '5': case '6': case '7': case '8': case '9':
5026 {
16980d0b
JB		 5027 int width;
5028 unsigned long value;
252b5132 5029
16980d0b 5030 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 5031
252b5132
RH		 5032 switch (*c)
5033 {
ab8e2090
NC		 5034 case 'R':
5035 if (value == 15)
5036 is_unpredictable = TRUE;
5037 /* Fall through. */
16980d0b 5038 case 'r':
9eb6c0f1
MGD		 5039 case 'T':
5040 /* We want register + 1 when decoding T. */
5041 if (*c == 'T')
5042 ++value;
5043
ff4a8d2b
NC		 5044 if (c[1] == 'u')
5045 {
5046 /* Eat the 'u' character. */
5047 ++ c;
5048
5049 if (u_reg == value)
5050 is_unpredictable = TRUE;
5051 u_reg = value;
5052 }
5053 if (c[1] == 'U')
5054 {
5055 /* Eat the 'U' character. */
5056 ++ c;
5057
5058 if (U_reg == value)
5059 is_unpredictable = TRUE;
5060 U_reg = value;
5061 }
16980d0b
JB		 5062 func (stream, "%s", arm_regnames[value]);
5063 break;
5064 case 'd':
5065 func (stream, "%ld", value);
05413229 5066 value_in_comment = value;
16980d0b
JB		 5067 break;
5068 case 'b':
5069 func (stream, "%ld", value * 8);
05413229 5070 value_in_comment = value * 8;
16980d0b
JB		 5071 break;
5072 case 'W':
5073 func (stream, "%ld", value + 1);
05413229 5074 value_in_comment = value + 1;
16980d0b
JB		 5075 break;
5076 case 'x':
5077 func (stream, "0x%08lx", value);
5078
5079 /* Some SWI instructions have special
5080 meanings. */
5081 if ((given & 0x0fffffff) == 0x0FF00000)
5082 func (stream, "\t; IMB");
5083 else if ((given & 0x0fffffff) == 0x0FF00001)
5084 func (stream, "\t; IMBRange");
5085 break;
5086 case 'X':
5087 func (stream, "%01lx", value & 0xf);
05413229 5088 value_in_comment = value;
252b5132
RH		 5089 break;
5090 case '`':
5091 c++;
16980d0b 5092 if (value == 0)
252b5132
RH		 5093 func (stream, "%c", *c);
5094 break;
5095 case '\'':
5096 c++;
16980d0b 5097 if (value == ((1ul << width) - 1))
252b5132
RH		 5098 func (stream, "%c", *c);
5099 break;
5100 case '?':
fe56b6ce 5101 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 5102 c += 1 << width;
252b5132
RH		 5103 break;
5104 default:
5105 abort ();
5106 }
5107 break;
5108
0dd132b6
NC		 5109 case 'e':
5110 {
5111 int imm;
5112
5113 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
5114 func (stream, "%d", imm);
fe56b6ce 5115 value_in_comment = imm;
0dd132b6
NC		 5116 }
5117 break;
5118
0a003adc
ZW		 5119 case 'E':
5120 /* LSB and WIDTH fields of BFI or BFC. The machine-
5121 language instruction encodes LSB and MSB. */
5122 {
5123 long msb = (given & 0x001f0000) >> 16;
5124 long lsb = (given & 0x00000f80) >> 7;
91d6fa6a 5125 long w = msb - lsb + 1;
fe56b6ce 5126
91d6fa6a
NC		 5127 if (w > 0)
5128 func (stream, "#%lu, #%lu", lsb, w);
0a003adc
ZW		 5129 else
5130 func (stream, "(invalid: %lu:%lu)", lsb, msb);
5131 }
5132 break;
5133
90ec0d68
MGD		 5134 case 'R':
5135 /* Get the PSR/banked register name. */
5136 {
5137 const char * name;
5138 unsigned sysm = (given & 0x004f0000) >> 16;
5139
5140 sysm |= (given & 0x300) >> 4;
5141 name = banked_regname (sysm);
5142
5143 if (name != NULL)
5144 func (stream, "%s", name);
5145 else
d908c8af 5146 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 5147 }
5148 break;
5149
0a003adc
ZW		 5150 case 'V':
5151 /* 16-bit unsigned immediate from a MOVT or MOVW
5152 instruction, encoded in bits 0:11 and 15:19. */
5153 {
5154 long hi = (given & 0x000f0000) >> 4;
5155 long lo = (given & 0x00000fff);
5156 long imm16 = hi | lo;
fe56b6ce
NC		 5157
5158 func (stream, "#%lu", imm16);
5159 value_in_comment = imm16;
0a003adc
ZW		 5160 }
5161 break;
5162
252b5132
RH		 5163 default:
5164 abort ();
5165 }
5166 }
5167 }
5168 else
5169 func (stream, "%c", *c);
5170 }
05413229
NC		 5171
5172 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 5173 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 5174
5175 if (is_unpredictable)
5176 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 5177
4a5329c6 5178 return;
252b5132
RH		 5179 }
5180 }
5181 abort ();
5182}
5183
4a5329c6 5184/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 5185
4a5329c6
ZW		 5186static void
5187print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 5188{
6b5d3a4d 5189 const struct opcode16 *insn;
6a51a8a8
AM		 5190 void *stream = info->stream;
5191 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 5192
5193 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 5194 if ((given & insn->mask) == insn->value)
5195 {
05413229 5196 signed long value_in_comment = 0;
6b5d3a4d 5197 const char *c = insn->assembler;
05413229 5198
c19d1205
ZW		 5199 for (; *c; c++)
5200 {
5201 int domaskpc = 0;
5202 int domasklr = 0;
5203
5204 if (*c != '%')
5205 {
5206 func (stream, "%c", *c);
5207 continue;
5208 }
252b5132 5209
c19d1205
ZW		 5210 switch (*++c)
5211 {
5212 case '%':
5213 func (stream, "%%");
5214 break;
b34976b6 5215
c22aaad1
PB		 5216 case 'c':
5217 if (ifthen_state)
5218 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5219 break;
5220
5221 case 'C':
5222 if (ifthen_state)
5223 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5224 else
5225 func (stream, "s");
5226 break;
5227
5228 case 'I':
5229 {
5230 unsigned int tmp;
5231
5232 ifthen_next_state = given & 0xff;
5233 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
5234 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
5235 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
5236 }
5237 break;
5238
5239 case 'x':
5240 if (ifthen_next_state)
5241 func (stream, "\t; unpredictable branch in IT block\n");
5242 break;
5243
5244 case 'X':
5245 if (ifthen_state)
5246 func (stream, "\t; unpredictable <IT:%s>",
5247 arm_conditional[IFTHEN_COND]);
5248 break;
5249
c19d1205
ZW		 5250 case 'S':
5251 {
5252 long reg;
5253
5254 reg = (given >> 3) & 0x7;
5255 if (given & (1 << 6))
5256 reg += 8;
4f3c3dbb 5257
c19d1205
ZW		 5258 func (stream, "%s", arm_regnames[reg]);
5259 }
5260 break;
baf0cc5e 5261
c19d1205 5262 case 'D':
4f3c3dbb 5263 {
c19d1205
ZW		 5264 long reg;
5265
5266 reg = given & 0x7;
5267 if (given & (1 << 7))
5268 reg += 8;
5269
5270 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 5271 }
c19d1205
ZW		 5272 break;
5273
5274 case 'N':
5275 if (given & (1 << 8))
5276 domasklr = 1;
5277 /* Fall through. */
5278 case 'O':
5279 if (*c == 'O' && (given & (1 << 8)))
5280 domaskpc = 1;
5281 /* Fall through. */
5282 case 'M':
5283 {
5284 int started = 0;
5285 int reg;
5286
5287 func (stream, "{");
5288
5289 /* It would be nice if we could spot
5290 ranges, and generate the rS-rE format: */
5291 for (reg = 0; (reg < 8); reg++)
5292 if ((given & (1 << reg)) != 0)
5293 {
5294 if (started)
5295 func (stream, ", ");
5296 started = 1;
5297 func (stream, "%s", arm_regnames[reg]);
5298 }
5299
5300 if (domasklr)
5301 {
5302 if (started)
5303 func (stream, ", ");
5304 started = 1;
d908c8af 5305 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 5306 }
5307
5308 if (domaskpc)
5309 {
5310 if (started)
5311 func (stream, ", ");
d908c8af 5312 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 5313 }
5314
5315 func (stream, "}");
5316 }
5317 break;
5318
4547cb56
NC		 5319 case 'W':
5320 /* Print writeback indicator for a LDMIA. We are doing a
5321 writeback if the base register is not in the register
5322 mask. */
5323 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
5324 func (stream, "!");
5325 break;
5326
c19d1205
ZW		 5327 case 'b':
5328 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
5329 {
5330 bfd_vma address = (pc + 4
5331 + ((given & 0x00f8) >> 2)
5332 + ((given & 0x0200) >> 3));
5333 info->print_address_func (address, info);
5334 }
5335 break;
5336
5337 case 's':
5338 /* Right shift immediate -- bits 6..10; 1-31 print
5339 as themselves, 0 prints as 32. */
5340 {
5341 long imm = (given & 0x07c0) >> 6;
5342 if (imm == 0)
5343 imm = 32;
0fd3a477 5344 func (stream, "#%ld", imm);
c19d1205
ZW		 5345 }
5346 break;
5347
5348 case '0': case '1': case '2': case '3': case '4':
5349 case '5': case '6': case '7': case '8': case '9':
5350 {
5351 int bitstart = *c++ - '0';
5352 int bitend = 0;
5353
5354 while (*c >= '0' && *c <= '9')
5355 bitstart = (bitstart * 10) + *c++ - '0';
5356
5357 switch (*c)
5358 {
5359 case '-':
5360 {
f8b960bc 5361 bfd_vma reg;
c19d1205
ZW		 5362
5363 c++;
5364 while (*c >= '0' && *c <= '9')
5365 bitend = (bitend * 10) + *c++ - '0';
5366 if (!bitend)
5367 abort ();
5368 reg = given >> bitstart;
5369 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 5370
c19d1205
ZW		 5371 switch (*c)
5372 {
5373 case 'r':
5374 func (stream, "%s", arm_regnames[reg]);
5375 break;
5376
5377 case 'd':
d908c8af 5378 func (stream, "%ld", (long) reg);
05413229 5379 value_in_comment = reg;
c19d1205
ZW		 5380 break;
5381
5382 case 'H':
d908c8af 5383 func (stream, "%ld", (long) (reg << 1));
05413229 5384 value_in_comment = reg << 1;
c19d1205
ZW		 5385 break;
5386
5387 case 'W':
d908c8af 5388 func (stream, "%ld", (long) (reg << 2));
05413229 5389 value_in_comment = reg << 2;
c19d1205
ZW		 5390 break;
5391
5392 case 'a':
5393 /* PC-relative address -- the bottom two
5394 bits of the address are dropped
5395 before the calculation. */
5396 info->print_address_func
5397 (((pc + 4) & ~3) + (reg << 2), info);
05413229 5398 value_in_comment = 0;
c19d1205
ZW		 5399 break;
5400
5401 case 'x':
d908c8af 5402 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 5403 break;
5404
c19d1205
ZW		 5405 case 'B':
5406 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6b5d3a4d 5407 info->print_address_func (reg * 2 + pc + 4, info);
05413229 5408 value_in_comment = 0;
c19d1205
ZW		 5409 break;
5410
5411 case 'c':
c22aaad1 5412 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 5413 break;
5414
5415 default:
5416 abort ();
5417 }
5418 }
5419 break;
5420
5421 case '\'':
5422 c++;
5423 if ((given & (1 << bitstart)) != 0)
5424 func (stream, "%c", *c);
5425 break;
5426
5427 case '?':
5428 ++c;
5429 if ((given & (1 << bitstart)) != 0)
5430 func (stream, "%c", *c++);
5431 else
5432 func (stream, "%c", *++c);
5433 break;
5434
5435 default:
5436 abort ();
5437 }
5438 }
5439 break;
5440
5441 default:
5442 abort ();
5443 }
5444 }
05413229
NC		 5445
5446 if (value_in_comment > 32 || value_in_comment < -16)
5447 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 5448 return;
c19d1205
ZW		 5449 }
5450
5451 /* No match. */
5452 abort ();
5453}
5454
62b3e311 5455/* Return the name of an V7M special register. */
fe56b6ce 5456
62b3e311
PB		 5457static const char *
5458psr_name (int regno)
5459{
5460 switch (regno)
5461 {
1a336194
TP		 5462 case 0x0: return "APSR";
5463 case 0x1: return "IAPSR";
5464 case 0x2: return "EAPSR";
5465 case 0x3: return "PSR";
5466 case 0x5: return "IPSR";
5467 case 0x6: return "EPSR";
5468 case 0x7: return "IEPSR";
5469 case 0x8: return "MSP";
5470 case 0x9: return "PSP";
5471 case 0xa: return "MSPLIM";
5472 case 0xb: return "PSPLIM";
5473 case 0x10: return "PRIMASK";
5474 case 0x11: return "BASEPRI";
5475 case 0x12: return "BASEPRI_MAX";
5476 case 0x13: return "FAULTMASK";
5477 case 0x14: return "CONTROL";
16a1fa25
TP		 5478 case 0x88: return "MSP_NS";
5479 case 0x89: return "PSP_NS";
1a336194
TP		 5480 case 0x8a: return "MSPLIM_NS";
5481 case 0x8b: return "PSPLIM_NS";
5482 case 0x90: return "PRIMASK_NS";
5483 case 0x91: return "BASEPRI_NS";
5484 case 0x93: return "FAULTMASK_NS";
5485 case 0x94: return "CONTROL_NS";
5486 case 0x98: return "SP_NS";
62b3e311
PB		 5487 default: return "<unknown>";
5488 }
5489}
5490
4a5329c6
ZW		 5491/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
5492
5493static void
5494print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 5495{
6b5d3a4d 5496 const struct opcode32 *insn;
c19d1205
ZW		 5497 void *stream = info->stream;
5498 fprintf_ftype func = info->fprintf_func;
5499
16980d0b
JB		 5500 if (print_insn_coprocessor (pc, info, given, TRUE))
5501 return;
5502
5503 if (print_insn_neon (info, given, TRUE))
8f06b2d8
PB		 5504 return;
5505
c19d1205
ZW		 5506 for (insn = thumb32_opcodes; insn->assembler; insn++)
5507 if ((given & insn->mask) == insn->value)
5508 {
ff4a8d2b 5509 bfd_boolean is_unpredictable = FALSE;
05413229 5510 signed long value_in_comment = 0;
6b5d3a4d 5511 const char *c = insn->assembler;
05413229 5512
c19d1205
ZW		 5513 for (; *c; c++)
5514 {
5515 if (*c != '%')
5516 {
5517 func (stream, "%c", *c);
5518 continue;
5519 }
5520
5521 switch (*++c)
5522 {
5523 case '%':
5524 func (stream, "%%");
5525 break;
5526
c22aaad1
PB		 5527 case 'c':
5528 if (ifthen_state)
5529 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5530 break;
5531
5532 case 'x':
5533 if (ifthen_next_state)
5534 func (stream, "\t; unpredictable branch in IT block\n");
5535 break;
5536
5537 case 'X':
5538 if (ifthen_state)
5539 func (stream, "\t; unpredictable <IT:%s>",
5540 arm_conditional[IFTHEN_COND]);
5541 break;
5542
c19d1205
ZW		 5543 case 'I':
5544 {
5545 unsigned int imm12 = 0;
fe56b6ce 5546
c19d1205
ZW		 5547 imm12 |= (given & 0x000000ffu);
5548 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 5549 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 5550 func (stream, "#%u", imm12);
5551 value_in_comment = imm12;
c19d1205
ZW		 5552 }
5553 break;
5554
5555 case 'M':
5556 {
5557 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 5558
c19d1205
ZW		 5559 bits |= (given & 0x000000ffu);
5560 bits |= (given & 0x00007000u) >> 4;
5561 bits |= (given & 0x04000000u) >> 15;
5562 imm8 = (bits & 0x0ff);
5563 mod = (bits & 0xf00) >> 8;
5564 switch (mod)
5565 {
5566 case 0: imm = imm8; break;
c1e26897
NC		 5567 case 1: imm = ((imm8 << 16) | imm8); break;
5568 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
5569 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 5570 default:
5571 mod = (bits & 0xf80) >> 7;
5572 imm8 = (bits & 0x07f) | 0x80;
5573 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
5574 }
fe56b6ce
NC		 5575 func (stream, "#%u", imm);
5576 value_in_comment = imm;
c19d1205
ZW		 5577 }
5578 break;
43e65147 5579
c19d1205
ZW		 5580 case 'J':
5581 {
5582 unsigned int imm = 0;
fe56b6ce 5583
c19d1205
ZW		 5584 imm |= (given & 0x000000ffu);
5585 imm |= (given & 0x00007000u) >> 4;
5586 imm |= (given & 0x04000000u) >> 15;
5587 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 5588 func (stream, "#%u", imm);
5589 value_in_comment = imm;
c19d1205
ZW		 5590 }
5591 break;
5592
5593 case 'K':
5594 {
5595 unsigned int imm = 0;
fe56b6ce 5596
c19d1205
ZW		 5597 imm |= (given & 0x000f0000u) >> 16;
5598 imm |= (given & 0x00000ff0u) >> 0;
5599 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 5600 func (stream, "#%u", imm);
5601 value_in_comment = imm;
c19d1205
ZW		 5602 }
5603 break;
5604
74db7efb
NC		 5605 case 'H':
5606 {
5607 unsigned int imm = 0;
5608
5609 imm |= (given & 0x000f0000u) >> 4;
5610 imm |= (given & 0x00000fffu) >> 0;
5611 func (stream, "#%u", imm);
5612 value_in_comment = imm;
5613 }
5614 break;
5615
90ec0d68
MGD		 5616 case 'V':
5617 {
5618 unsigned int imm = 0;
5619
5620 imm |= (given & 0x00000fffu);
5621 imm |= (given & 0x000f0000u) >> 4;
5622 func (stream, "#%u", imm);
5623 value_in_comment = imm;
5624 }
5625 break;
5626
c19d1205
ZW		 5627 case 'S':
5628 {
5629 unsigned int reg = (given & 0x0000000fu);
5630 unsigned int stp = (given & 0x00000030u) >> 4;
5631 unsigned int imm = 0;
5632 imm |= (given & 0x000000c0u) >> 6;
5633 imm |= (given & 0x00007000u) >> 10;
5634
5635 func (stream, "%s", arm_regnames[reg]);
5636 switch (stp)
5637 {
5638 case 0:
5639 if (imm > 0)
5640 func (stream, ", lsl #%u", imm);
5641 break;
5642
5643 case 1:
5644 if (imm == 0)
5645 imm = 32;
5646 func (stream, ", lsr #%u", imm);
5647 break;
5648
5649 case 2:
5650 if (imm == 0)
5651 imm = 32;
5652 func (stream, ", asr #%u", imm);
5653 break;
5654
5655 case 3:
5656 if (imm == 0)
5657 func (stream, ", rrx");
5658 else
5659 func (stream, ", ror #%u", imm);
5660 }
5661 }
5662 break;
5663
5664 case 'a':
5665 {
5666 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 5667 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 5668 unsigned int op = (given & 0x00000f00) >> 8;
5669 unsigned int i12 = (given & 0x00000fff);
5670 unsigned int i8 = (given & 0x000000ff);
5671 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 5672 bfd_vma offset = 0;
c19d1205
ZW		 5673
5674 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 5675 if (U) /* 12-bit positive immediate offset. */
5676 {
5677 offset = i12;
5678 if (Rn != 15)
5679 value_in_comment = offset;
5680 }
5681 else if (Rn == 15) /* 12-bit negative immediate offset. */
5682 offset = - (int) i12;
5683 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 5684 {
5685 unsigned int Rm = (i8 & 0x0f);
5686 unsigned int sh = (i8 & 0x30) >> 4;
05413229 5687
c19d1205
ZW		 5688 func (stream, ", %s", arm_regnames[Rm]);
5689 if (sh)
5690 func (stream, ", lsl #%u", sh);
5691 func (stream, "]");
5692 break;
5693 }
5694 else switch (op)
5695 {
05413229 5696 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 5697 offset = i8;
5698 break;
5699
05413229 5700 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 5701 offset = -i8;
5702 break;
5703
05413229 5704 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 5705 offset = i8;
5706 writeback = TRUE;
5707 break;
5708
05413229 5709 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 5710 offset = -i8;
5711 writeback = TRUE;
5712 break;
5713
05413229 5714 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 5715 offset = i8;
5716 postind = TRUE;
5717 break;
5718
05413229 5719 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 5720 offset = -i8;
5721 postind = TRUE;
5722 break;
5723
5724 default:
5725 func (stream, ", <undefined>]");
5726 goto skip;
5727 }
5728
5729 if (postind)
d908c8af 5730 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 5731 else
5732 {
5733 if (offset)
d908c8af 5734 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 5735 func (stream, writeback ? "]!" : "]");
5736 }
5737
5738 if (Rn == 15)
5739 {
5740 func (stream, "\t; ");
5741 info->print_address_func (((pc + 4) & ~3) + offset, info);
5742 }
5743 }
5744 skip:
5745 break;
5746
5747 case 'A':
5748 {
c1e26897
NC		 5749 unsigned int U = ! NEGATIVE_BIT_SET;
5750 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 5751 unsigned int Rn = (given & 0x000f0000) >> 16;
5752 unsigned int off = (given & 0x000000ff);
5753
5754 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 5755
5756 if (PRE_BIT_SET)
c19d1205
ZW		 5757 {
5758 if (off || !U)
05413229
NC		 5759 {
5760 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
fe50e98c 5761 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 5762 }
c19d1205
ZW		 5763 func (stream, "]");
5764 if (W)
5765 func (stream, "!");
5766 }
5767 else
5768 {
5769 func (stream, "], ");
5770 if (W)
05413229
NC		 5771 {
5772 func (stream, "#%c%u", U ? '+' : '-', off * 4);
fe50e98c 5773 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 5774 }
c19d1205 5775 else
fe56b6ce
NC		 5776 {
5777 func (stream, "{%u}", off);
5778 value_in_comment = off;
5779 }
c19d1205
ZW		 5780 }
5781 }
5782 break;
5783
5784 case 'w':
5785 {
5786 unsigned int Sbit = (given & 0x01000000) >> 24;
5787 unsigned int type = (given & 0x00600000) >> 21;
05413229 5788
c19d1205
ZW		 5789 switch (type)
5790 {
5791 case 0: func (stream, Sbit ? "sb" : "b"); break;
5792 case 1: func (stream, Sbit ? "sh" : "h"); break;
5793 case 2:
5794 if (Sbit)
5795 func (stream, "??");
5796 break;
5797 case 3:
5798 func (stream, "??");
5799 break;
5800 }
5801 }
5802 break;
5803
5804 case 'm':
5805 {
5806 int started = 0;
5807 int reg;
5808
5809 func (stream, "{");
5810 for (reg = 0; reg < 16; reg++)
5811 if ((given & (1 << reg)) != 0)
5812 {
5813 if (started)
5814 func (stream, ", ");
5815 started = 1;
5816 func (stream, "%s", arm_regnames[reg]);
5817 }
5818 func (stream, "}");
5819 }
5820 break;
5821
5822 case 'E':
5823 {
5824 unsigned int msb = (given & 0x0000001f);
5825 unsigned int lsb = 0;
fe56b6ce 5826
c19d1205
ZW		 5827 lsb |= (given & 0x000000c0u) >> 6;
5828 lsb |= (given & 0x00007000u) >> 10;
5829 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
5830 }
5831 break;
5832
5833 case 'F':
5834 {
5835 unsigned int width = (given & 0x0000001f) + 1;
5836 unsigned int lsb = 0;
fe56b6ce 5837
c19d1205
ZW		 5838 lsb |= (given & 0x000000c0u) >> 6;
5839 lsb |= (given & 0x00007000u) >> 10;
5840 func (stream, "#%u, #%u", lsb, width);
5841 }
5842 break;
5843
5844 case 'b':
5845 {
5846 unsigned int S = (given & 0x04000000u) >> 26;
5847 unsigned int J1 = (given & 0x00002000u) >> 13;
5848 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 5849 bfd_vma offset = 0;
c19d1205
ZW		 5850
5851 offset |= !S << 20;
5852 offset |= J2 << 19;
5853 offset |= J1 << 18;
5854 offset |= (given & 0x003f0000) >> 4;
5855 offset |= (given & 0x000007ff) << 1;
5856 offset -= (1 << 20);
5857
5858 info->print_address_func (pc + 4 + offset, info);
5859 }
5860 break;
5861
5862 case 'B':
5863 {
5864 unsigned int S = (given & 0x04000000u) >> 26;
5865 unsigned int I1 = (given & 0x00002000u) >> 13;
5866 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 5867 bfd_vma offset = 0;
c19d1205
ZW		 5868
5869 offset |= !S << 24;
5870 offset |= !(I1 ^ S) << 23;
5871 offset |= !(I2 ^ S) << 22;
5872 offset |= (given & 0x03ff0000u) >> 4;
5873 offset |= (given & 0x000007ffu) << 1;
5874 offset -= (1 << 24);
36b0c57d 5875 offset += pc + 4;
c19d1205 5876
36b0c57d
PB		 5877 /* BLX target addresses are always word aligned. */
5878 if ((given & 0x00001000u) == 0)
5879 offset &= ~2u;
5880
5881 info->print_address_func (offset, info);
c19d1205
ZW		 5882 }
5883 break;
5884
5885 case 's':
5886 {
5887 unsigned int shift = 0;
fe56b6ce 5888
c19d1205
ZW		 5889 shift |= (given & 0x000000c0u) >> 6;
5890 shift |= (given & 0x00007000u) >> 10;
c1e26897 5891 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 5892 func (stream, ", asr #%u", shift);
5893 else if (shift)
5894 func (stream, ", lsl #%u", shift);
5895 /* else print nothing - lsl #0 */
5896 }
5897 break;
5898
5899 case 'R':
5900 {
5901 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 5902
c19d1205
ZW		 5903 if (rot)
5904 func (stream, ", ror #%u", rot * 8);
5905 }
5906 break;
5907
62b3e311 5908 case 'U':
43e65147 5909 if ((given & 0xf0) == 0x60)
62b3e311 5910 {
52e7f43d
RE		 5911 switch (given & 0xf)
5912 {
5913 case 0xf: func (stream, "sy"); break;
5914 default:
5915 func (stream, "#%d", (int) given & 0xf);
5916 break;
5917 }
62b3e311 5918 }
43e65147 5919 else
52e7f43d 5920 {
e797f7e0
MGD		 5921 const char * opt = data_barrier_option (given & 0xf);
5922 if (opt != NULL)
5923 func (stream, "%s", opt);
5924 else
5925 func (stream, "#%d", (int) given & 0xf);
52e7f43d 5926 }
62b3e311
PB		 5927 break;
5928
5929 case 'C':
5930 if ((given & 0xff) == 0)
5931 {
5932 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
5933 if (given & 0x800)
5934 func (stream, "f");
5935 if (given & 0x400)
5936 func (stream, "s");
5937 if (given & 0x200)
5938 func (stream, "x");
5939 if (given & 0x100)
5940 func (stream, "c");
5941 }
90ec0d68
MGD		 5942 else if ((given & 0x20) == 0x20)
5943 {
5944 char const* name;
5945 unsigned sysm = (given & 0xf00) >> 8;
5946
5947 sysm |= (given & 0x30);
5948 sysm |= (given & 0x00100000) >> 14;
5949 name = banked_regname (sysm);
43e65147 5950
90ec0d68
MGD		 5951 if (name != NULL)
5952 func (stream, "%s", name);
5953 else
d908c8af 5954 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 5955 }
62b3e311
PB		 5956 else
5957 {
d908c8af 5958 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 5959 }
5960 break;
5961
5962 case 'D':
90ec0d68
MGD		 5963 if (((given & 0xff) == 0)
5964 || ((given & 0x20) == 0x20))
5965 {
5966 char const* name;
5967 unsigned sm = (given & 0xf0000) >> 16;
5968
5969 sm |= (given & 0x30);
5970 sm |= (given & 0x00100000) >> 14;
5971 name = banked_regname (sm);
5972
5973 if (name != NULL)
5974 func (stream, "%s", name);
5975 else
d908c8af 5976 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 5977 }
62b3e311 5978 else
d908c8af 5979 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 5980 break;
5981
c19d1205
ZW		 5982 case '0': case '1': case '2': case '3': case '4':
5983 case '5': case '6': case '7': case '8': case '9':
5984 {
16980d0b
JB		 5985 int width;
5986 unsigned long val;
c19d1205 5987
16980d0b 5988 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 5989
c19d1205
ZW		 5990 switch (*c)
5991 {
05413229
NC		 5992 case 'd':
5993 func (stream, "%lu", val);
5994 value_in_comment = val;
5995 break;
ff4a8d2b 5996
f0fba320
RL		 5997 case 'D':
5998 func (stream, "%lu", val + 1);
5999 value_in_comment = val + 1;
6000 break;
6001
05413229
NC		 6002 case 'W':
6003 func (stream, "%lu", val * 4);
6004 value_in_comment = val * 4;
6005 break;
ff4a8d2b
NC		 6006
6007 case 'R':
6008 if (val == 15)
6009 is_unpredictable = TRUE;
6010 /* Fall through. */
6011 case 'r':
6012 func (stream, "%s", arm_regnames[val]);
6013 break;
c19d1205
ZW		 6014
6015 case 'c':
c22aaad1 6016 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 6017 break;
6018
6019 case '\'':
c19d1205 6020 c++;
16980d0b
JB		 6021 if (val == ((1ul << width) - 1))
6022 func (stream, "%c", *c);
c19d1205 6023 break;
43e65147 6024
c19d1205 6025 case '`':
c19d1205 6026 c++;
16980d0b
JB		 6027 if (val == 0)
6028 func (stream, "%c", *c);
c19d1205
ZW		 6029 break;
6030
6031 case '?':
fe56b6ce 6032 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 6033 c += 1 << width;
c19d1205 6034 break;
43e65147 6035
0bb027fd
RR		 6036 case 'x':
6037 func (stream, "0x%lx", val & 0xffffffffUL);
6038 break;
c19d1205
ZW		 6039
6040 default:
6041 abort ();
6042 }
6043 }
6044 break;
6045
32a94698
NC		 6046 case 'L':
6047 /* PR binutils/12534
6048 If we have a PC relative offset in an LDRD or STRD
6049 instructions then display the decoded address. */
6050 if (((given >> 16) & 0xf) == 0xf)
6051 {
6052 bfd_vma offset = (given & 0xff) * 4;
6053
6054 if ((given & (1 << 23)) == 0)
6055 offset = - offset;
6056 func (stream, "\t; ");
6057 info->print_address_func ((pc & ~3) + 4 + offset, info);
6058 }
6059 break;
6060
c19d1205
ZW		 6061 default:
6062 abort ();
6063 }
6064 }
05413229
NC		 6065
6066 if (value_in_comment > 32 || value_in_comment < -16)
6067 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 6068
6069 if (is_unpredictable)
6070 func (stream, UNPREDICTABLE_INSTRUCTION);
6071
4a5329c6 6072 return;
c19d1205 6073 }
252b5132 6074
58efb6c0 6075 /* No match. */
252b5132
RH		 6076 abort ();
6077}
6078
e821645d
DJ		 6079/* Print data bytes on INFO->STREAM. */
6080
6081static void
fe56b6ce
NC		 6082print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
6083 struct disassemble_info *info,
e821645d
DJ		 6084 long given)
6085{
6086 switch (info->bytes_per_chunk)
6087 {
6088 case 1:
6089 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
6090 break;
6091 case 2:
6092 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
6093 break;
6094 case 4:
6095 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
6096 break;
6097 default:
6098 abort ();
6099 }
6100}
6101
22a398e1 6102/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 6103 being displayed in symbol relative addresses.
6104
6105 Also disallow private symbol, with __tagsym$$ prefix,
6106 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 6107
6108bfd_boolean
6109arm_symbol_is_valid (asymbol * sym,
6110 struct disassemble_info * info ATTRIBUTE_UNUSED)
6111{
6112 const char * name;
43e65147 6113
22a398e1
NC		 6114 if (sym == NULL)
6115 return FALSE;
6116
6117 name = bfd_asymbol_name (sym);
6118
d8282f0e 6119 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 6120}
6121
65b48a81 6122/* Parse the string of disassembler options. */
baf0cc5e 6123
65b48a81 6124static void
f995bbe8 6125parse_arm_disassembler_options (const char *options)
dd92f639 6126{
f995bbe8 6127 const char *opt;
b34976b6 6128
65b48a81 6129 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
dd92f639 6130 {
65b48a81
PB		 6131 if (CONST_STRNEQ (opt, "reg-names-"))
6132 {
6133 unsigned int i;
6134 for (i = 0; i < NUM_ARM_OPTIONS; i++)
6135 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
6136 {
6137 regname_selected = i;
6138 break;
6139 }
b34976b6 6140
65b48a81
PB		 6141 if (i >= NUM_ARM_OPTIONS)
6142 fprintf (stderr, _("Unrecognised register name set: %s\n"), opt);
6143 }
6144 else if (CONST_STRNEQ (opt, "force-thumb"))
6145 force_thumb = 1;
6146 else if (CONST_STRNEQ (opt, "no-force-thumb"))
6147 force_thumb = 0;
6148 else
6149 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), opt);
dd92f639 6150 }
b34976b6 6151
dd92f639
NC		 6152 return;
6153}
6154
5bc5ae88
RL		 6155static bfd_boolean
6156mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6157 enum map_type *map_symbol);
6158
c22aaad1
PB		 6159/* Search back through the insn stream to determine if this instruction is
6160 conditionally executed. */
fe56b6ce 6161
c22aaad1 6162static void
fe56b6ce
NC		 6163find_ifthen_state (bfd_vma pc,
6164 struct disassemble_info *info,
c22aaad1
PB		 6165 bfd_boolean little)
6166{
6167 unsigned char b[2];
6168 unsigned int insn;
6169 int status;
6170 /* COUNT is twice the number of instructions seen. It will be odd if we
6171 just crossed an instruction boundary. */
6172 int count;
6173 int it_count;
6174 unsigned int seen_it;
6175 bfd_vma addr;
6176
6177 ifthen_address = pc;
6178 ifthen_state = 0;
6179
6180 addr = pc;
6181 count = 1;
6182 it_count = 0;
6183 seen_it = 0;
6184 /* Scan backwards looking for IT instructions, keeping track of where
6185 instruction boundaries are. We don't know if something is actually an
6186 IT instruction until we find a definite instruction boundary. */
6187 for (;;)
6188 {
fe56b6ce 6189 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 6190 {
6191 /* A symbol must be on an instruction boundary, and will not
6192 be within an IT block. */
6193 if (seen_it && (count & 1))
6194 break;
6195
6196 return;
6197 }
6198 addr -= 2;
fe56b6ce 6199 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 6200 if (status)
6201 return;
6202
6203 if (little)
6204 insn = (b[0]) | (b[1] << 8);
6205 else
6206 insn = (b[1]) | (b[0] << 8);
6207 if (seen_it)
6208 {
6209 if ((insn & 0xf800) < 0xe800)
6210 {
6211 /* Addr + 2 is an instruction boundary. See if this matches
6212 the expected boundary based on the position of the last
6213 IT candidate. */
6214 if (count & 1)
6215 break;
6216 seen_it = 0;
6217 }
6218 }
6219 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
6220 {
5bc5ae88
RL		 6221 enum map_type type = MAP_ARM;
6222 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
6223
6224 if (!found || (found && type == MAP_THUMB))
6225 {
6226 /* This could be an IT instruction. */
6227 seen_it = insn;
6228 it_count = count >> 1;
6229 }
c22aaad1
PB		 6230 }
6231 if ((insn & 0xf800) >= 0xe800)
6232 count++;
6233 else
6234 count = (count + 2) | 1;
6235 /* IT blocks contain at most 4 instructions. */
6236 if (count >= 8 && !seen_it)
6237 return;
6238 }
6239 /* We found an IT instruction. */
6240 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
6241 if ((ifthen_state & 0xf) == 0)
6242 ifthen_state = 0;
6243}
6244
b0e28b39
DJ		 6245/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
6246 mapping symbol. */
6247
6248static int
6249is_mapping_symbol (struct disassemble_info *info, int n,
6250 enum map_type *map_type)
6251{
6252 const char *name;
6253
6254 name = bfd_asymbol_name (info->symtab[n]);
6255 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
6256 && (name[2] == 0 || name[2] == '.'))
6257 {
6258 *map_type = ((name[1] == 'a') ? MAP_ARM
6259 : (name[1] == 't') ? MAP_THUMB
6260 : MAP_DATA);
6261 return TRUE;
6262 }
6263
6264 return FALSE;
6265}
6266
6267/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
6268 Returns nonzero if *MAP_TYPE was set. */
6269
6270static int
6271get_map_sym_type (struct disassemble_info *info,
6272 int n,
6273 enum map_type *map_type)
6274{
6275 /* If the symbol is in a different section, ignore it. */
6276 if (info->section != NULL && info->section != info->symtab[n]->section)
6277 return FALSE;
6278
6279 return is_mapping_symbol (info, n, map_type);
6280}
6281
6282/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 6283 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 6284
6285static int
fe56b6ce
NC		 6286get_sym_code_type (struct disassemble_info *info,
6287 int n,
e821645d 6288 enum map_type *map_type)
2087ad84
PB		 6289{
6290 elf_symbol_type *es;
6291 unsigned int type;
b0e28b39
DJ		 6292
6293 /* If the symbol is in a different section, ignore it. */
6294 if (info->section != NULL && info->section != info->symtab[n]->section)
6295 return FALSE;
2087ad84 6296
e821645d 6297 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 6298 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6299
6300 /* If the symbol has function type then use that. */
34e77a92 6301 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 6302 {
39d911fc
TP		 6303 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6304 == ST_BRANCH_TO_THUMB)
35fc36a8
RS		 6305 *map_type = MAP_THUMB;
6306 else
6307 *map_type = MAP_ARM;
2087ad84
PB		 6308 return TRUE;
6309 }
6310
2087ad84
PB		 6311 return FALSE;
6312}
6313
5bc5ae88
RL		 6314/* Search the mapping symbol state for instruction at pc. This is only
6315 applicable for elf target.
6316
6317 There is an assumption Here, info->private_data contains the correct AND
6318 up-to-date information about current scan process. The information will be
6319 used to speed this search process.
6320
6321 Return TRUE if the mapping state can be determined, and map_symbol
6322 will be updated accordingly. Otherwise, return FALSE. */
6323
6324static bfd_boolean
6325mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6326 enum map_type *map_symbol)
6327{
6328 bfd_vma addr;
6329 int n, start = 0;
6330 bfd_boolean found = FALSE;
6331 enum map_type type = MAP_ARM;
6332 struct arm_private_data *private_data;
6333
6334 if (info->private_data == NULL || info->symtab_size == 0
6335 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
6336 return FALSE;
6337
6338 private_data = info->private_data;
6339 if (pc == 0)
6340 start = 0;
6341 else
6342 start = private_data->last_mapping_sym;
6343
6344 start = (start == -1)? 0 : start;
6345 addr = bfd_asymbol_value (info->symtab[start]);
6346
6347 if (pc >= addr)
6348 {
6349 if (get_map_sym_type (info, start, &type))
6350 found = TRUE;
6351 }
6352 else
6353 {
6354 for (n = start - 1; n >= 0; n--)
6355 {
6356 if (get_map_sym_type (info, n, &type))
6357 {
6358 found = TRUE;
6359 break;
6360 }
6361 }
6362 }
6363
6364 /* No mapping symbols were found. A leading $d may be
6365 omitted for sections which start with data; but for
6366 compatibility with legacy and stripped binaries, only
6367 assume the leading $d if there is at least one mapping
6368 symbol in the file. */
6369 if (!found && private_data->has_mapping_symbols == 1)
6370 {
6371 type = MAP_DATA;
6372 found = TRUE;
6373 }
6374
6375 *map_symbol = type;
6376 return found;
6377}
6378
0313a2b8
NC		 6379/* Given a bfd_mach_arm_XXX value, this function fills in the fields
6380 of the supplied arm_feature_set structure with bitmasks indicating
6381 the support base architectures and coprocessor extensions.
6382
6383 FIXME: This could more efficiently implemented as a constant array,
6384 although it would also be less robust. */
6385
6386static void
6387select_arm_features (unsigned long mach,
6388 arm_feature_set * features)
6389{
1af1dd51
MW		 6390#undef ARM_SET_FEATURES
6391#define ARM_SET_FEATURES(FSET) \
6392 { \
6393 const arm_feature_set fset = FSET; \
6394 arm_feature_set tmp = ARM_FEATURE (0, 0, FPU_FPA) ; \
6395 ARM_MERGE_FEATURE_SETS (*features, tmp, fset); \
6396 }
823d2571 6397
0313a2b8
NC		 6398 switch (mach)
6399 {
1af1dd51
MW		 6400 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
6401 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
6402 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
6403 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
6404 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
6405 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
6406 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
6407 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
6408 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
6409 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
6410 case bfd_mach_arm_ep9312:
6411 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
6412 ARM_CEXT_MAVERICK | FPU_MAVERICK));
6413 break;
6414 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
6415 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
0313a2b8
NC		 6416 /* If the machine type is unknown allow all
6417 architecture types and all extensions. */
1af1dd51 6418 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
0313a2b8
NC		 6419 default:
6420 abort ();
6421 }
1af1dd51
MW		 6422
6423#undef ARM_SET_FEATURES
0313a2b8
NC		 6424}
6425
6426
58efb6c0
NC		 6427/* NOTE: There are no checks in these routines that
6428 the relevant number of data bytes exist. */
baf0cc5e 6429
58efb6c0 6430static int
4a5329c6 6431print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 6432{
c19d1205
ZW		 6433 unsigned char b[4];
6434 long given;
6435 int status;
e821645d 6436 int is_thumb = FALSE;
b0e28b39 6437 int is_data = FALSE;
bd2e2557 6438 int little_code;
e821645d 6439 unsigned int size = 4;
4a5329c6 6440 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 6441 bfd_boolean found = FALSE;
b0e28b39 6442 struct arm_private_data *private_data;
58efb6c0 6443
dd92f639
NC		 6444 if (info->disassembler_options)
6445 {
65b48a81 6446 parse_arm_disassembler_options (info->disassembler_options);
b34976b6 6447
58efb6c0 6448 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 6449 info->disassembler_options = NULL;
6450 }
b34976b6 6451
0313a2b8
NC		 6452 /* PR 10288: Control which instructions will be disassembled. */
6453 if (info->private_data == NULL)
6454 {
b0e28b39 6455 static struct arm_private_data private;
0313a2b8
NC		 6456
6457 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
6458 /* If the user did not use the -m command line switch then default to
6459 disassembling all types of ARM instruction.
43e65147 6460
0313a2b8
NC		 6461 The info->mach value has to be ignored as this will be based on
6462 the default archictecture for the target and/or hints in the notes
6463 section, but it will never be greater than the current largest arm
6464 machine value (iWMMXt2), which is only equivalent to the V5TE
6465 architecture. ARM architectures have advanced beyond the machine
6466 value encoding, and these newer architectures would be ignored if
6467 the machine value was used.
6468
6469 Ie the -m switch is used to restrict which instructions will be
6470 disassembled. If it is necessary to use the -m switch to tell
6471 objdump that an ARM binary is being disassembled, eg because the
6472 input is a raw binary file, but it is also desired to disassemble
6473 all ARM instructions then use "-marm". This will select the
6474 "unknown" arm architecture which is compatible with any ARM
6475 instruction. */
6476 info->mach = bfd_mach_arm_unknown;
6477
6478 /* Compute the architecture bitmask from the machine number.
6479 Note: This assumes that the machine number will not change
6480 during disassembly.... */
b0e28b39 6481 select_arm_features (info->mach, & private.features);
0313a2b8 6482
b0e28b39 6483 private.has_mapping_symbols = -1;
1fbaefec
PB		 6484 private.last_mapping_sym = -1;
6485 private.last_mapping_addr = 0;
b0e28b39
DJ		 6486
6487 info->private_data = & private;
0313a2b8 6488 }
b0e28b39
DJ		 6489
6490 private_data = info->private_data;
6491
bd2e2557
SS		 6492 /* Decide if our code is going to be little-endian, despite what the
6493 function argument might say. */
6494 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
6495
b0e28b39
DJ		 6496 /* For ELF, consult the symbol table to determine what kind of code
6497 or data we have. */
8977d4b2 6498 if (info->symtab_size != 0
e821645d
DJ		 6499 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
6500 {
6501 bfd_vma addr;
b0e28b39 6502 int n, start;
e821645d 6503 int last_sym = -1;
b0e28b39 6504 enum map_type type = MAP_ARM;
e821645d 6505
e821645d
DJ		 6506 /* Start scanning at the start of the function, or wherever
6507 we finished last time. */
6750a3a7
NC		 6508 /* PR 14006. When the address is 0 we are either at the start of the
6509 very first function, or else the first function in a new, unlinked
838441e4 6510 executable section (eg because of -ffunction-sections). Either way
6750a3a7
NC		 6511 start scanning from the beginning of the symbol table, not where we
6512 left off last time. */
6513 if (pc == 0)
6514 start = 0;
6515 else
6516 {
6517 start = info->symtab_pos + 1;
6518 if (start < private_data->last_mapping_sym)
6519 start = private_data->last_mapping_sym;
6520 }
b0e28b39 6521 found = FALSE;
e821645d 6522
b0e28b39
DJ		 6523 /* First, look for mapping symbols. */
6524 if (private_data->has_mapping_symbols != 0)
e821645d 6525 {
b0e28b39
DJ		 6526 /* Scan up to the location being disassembled. */
6527 for (n = start; n < info->symtab_size; n++)
6528 {
6529 addr = bfd_asymbol_value (info->symtab[n]);
6530 if (addr > pc)
6531 break;
6532 if (get_map_sym_type (info, n, &type))
6533 {
6534 last_sym = n;
6535 found = TRUE;
6536 }
6537 }
6538
6539 if (!found)
6540 {
6541 /* No mapping symbol found at this address. Look backwards
cc643b88 6542 for a preceding one. */
b0e28b39
DJ		 6543 for (n = start - 1; n >= 0; n--)
6544 {
6545 if (get_map_sym_type (info, n, &type))
6546 {
6547 last_sym = n;
6548 found = TRUE;
6549 break;
6550 }
6551 }
6552 }
6553
6554 if (found)
6555 private_data->has_mapping_symbols = 1;
6556
6557 /* No mapping symbols were found. A leading $d may be
6558 omitted for sections which start with data; but for
6559 compatibility with legacy and stripped binaries, only
6560 assume the leading $d if there is at least one mapping
6561 symbol in the file. */
6562 if (!found && private_data->has_mapping_symbols == -1)
e821645d 6563 {
b0e28b39
DJ		 6564 /* Look for mapping symbols, in any section. */
6565 for (n = 0; n < info->symtab_size; n++)
6566 if (is_mapping_symbol (info, n, &type))
6567 {
6568 private_data->has_mapping_symbols = 1;
6569 break;
6570 }
6571 if (private_data->has_mapping_symbols == -1)
6572 private_data->has_mapping_symbols = 0;
6573 }
6574
6575 if (!found && private_data->has_mapping_symbols == 1)
6576 {
6577 type = MAP_DATA;
e821645d
DJ		 6578 found = TRUE;
6579 }
6580 }
6581
b0e28b39
DJ		 6582 /* Next search for function symbols to separate ARM from Thumb
6583 in binaries without mapping symbols. */
e821645d
DJ		 6584 if (!found)
6585 {
b0e28b39
DJ		 6586 /* Scan up to the location being disassembled. */
6587 for (n = start; n < info->symtab_size; n++)
e821645d 6588 {
b0e28b39
DJ		 6589 addr = bfd_asymbol_value (info->symtab[n]);
6590 if (addr > pc)
6591 break;
6592 if (get_sym_code_type (info, n, &type))
e821645d
DJ		 6593 {
6594 last_sym = n;
6595 found = TRUE;
b0e28b39
DJ		 6596 }
6597 }
6598
6599 if (!found)
6600 {
6601 /* No mapping symbol found at this address. Look backwards
cc643b88 6602 for a preceding one. */
b0e28b39
DJ		 6603 for (n = start - 1; n >= 0; n--)
6604 {
6605 if (get_sym_code_type (info, n, &type))
6606 {
6607 last_sym = n;
6608 found = TRUE;
6609 break;
6610 }
e821645d
DJ		 6611 }
6612 }
6613 }
6614
1fbaefec
PB		 6615 private_data->last_mapping_sym = last_sym;
6616 private_data->last_type = type;
6617 is_thumb = (private_data->last_type == MAP_THUMB);
6618 is_data = (private_data->last_type == MAP_DATA);
b34976b6 6619
e821645d
DJ		 6620 /* Look a little bit ahead to see if we should print out
6621 two or four bytes of data. If there's a symbol,
6622 mapping or otherwise, after two bytes then don't
6623 print more. */
6624 if (is_data)
6625 {
6626 size = 4 - (pc & 3);
6627 for (n = last_sym + 1; n < info->symtab_size; n++)
6628 {
6629 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 6630 if (addr > pc
6631 && (info->section == NULL
6632 || info->section == info->symtab[n]->section))
e821645d
DJ		 6633 {
6634 if (addr - pc < size)
6635 size = addr - pc;
6636 break;
6637 }
6638 }
6639 /* If the next symbol is after three bytes, we need to
6640 print only part of the data, so that we can use either
6641 .byte or .short. */
6642 if (size == 3)
6643 size = (pc & 1) ? 1 : 2;
6644 }
6645 }
6646
6647 if (info->symbols != NULL)
252b5132 6648 {
5876e06d
NC		 6649 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
6650 {
2f0ca46a 6651 coff_symbol_type * cs;
b34976b6 6652
5876e06d
NC		 6653 cs = coffsymbol (*info->symbols);
6654 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
6655 || cs->native->u.syment.n_sclass == C_THUMBSTAT
6656 || cs->native->u.syment.n_sclass == C_THUMBLABEL
6657 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
6658 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
6659 }
e821645d
DJ		 6660 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
6661 && !found)
5876e06d 6662 {
2087ad84
PB		 6663 /* If no mapping symbol has been found then fall back to the type
6664 of the function symbol. */
e821645d
DJ		 6665 elf_symbol_type * es;
6666 unsigned int type;
2087ad84 6667
e821645d
DJ		 6668 es = *(elf_symbol_type **)(info->symbols);
6669 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 6670
39d911fc
TP		 6671 is_thumb =
6672 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6673 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
5876e06d 6674 }
e49d43ff
TG		 6675 else if (bfd_asymbol_flavour (*info->symbols)
6676 == bfd_target_mach_o_flavour)
6677 {
6678 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
6679
6680 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
6681 }
5876e06d 6682 }
b34976b6 6683
e821645d
DJ		 6684 if (force_thumb)
6685 is_thumb = TRUE;
6686
b8f9ee44
CL		 6687 if (is_data)
6688 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6689 else
6690 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6691
c19d1205 6692 info->bytes_per_line = 4;
252b5132 6693
1316c8b3
NC		 6694 /* PR 10263: Disassemble data if requested to do so by the user. */
6695 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 6696 {
6697 int i;
6698
1316c8b3 6699 /* Size was already set above. */
e821645d
DJ		 6700 info->bytes_per_chunk = size;
6701 printer = print_insn_data;
6702
fe56b6ce 6703 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 6704 given = 0;
6705 if (little)
6706 for (i = size - 1; i >= 0; i--)
6707 given = b[i] | (given << 8);
6708 else
6709 for (i = 0; i < (int) size; i++)
6710 given = b[i] | (given << 8);
6711 }
6712 else if (!is_thumb)
252b5132 6713 {
c19d1205
ZW		 6714 /* In ARM mode endianness is a straightforward issue: the instruction
6715 is four bytes long and is either ordered 0123 or 3210. */
6716 printer = print_insn_arm;
6717 info->bytes_per_chunk = 4;
4a5329c6 6718 size = 4;
c19d1205 6719
0313a2b8 6720 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 6721 if (little_code)
c19d1205
ZW		 6722 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
6723 else
6724 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
252b5132 6725 }
58efb6c0 6726 else
252b5132 6727 {
c19d1205
ZW		 6728 /* In Thumb mode we have the additional wrinkle of two
6729 instruction lengths. Fortunately, the bits that determine
6730 the length of the current instruction are always to be found
6731 in the first two bytes. */
4a5329c6 6732 printer = print_insn_thumb16;
c19d1205 6733 info->bytes_per_chunk = 2;
4a5329c6
ZW		 6734 size = 2;
6735
fe56b6ce 6736 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 6737 if (little_code)
9a2ff3f5
AM		 6738 given = (b[0]) | (b[1] << 8);
6739 else
6740 given = (b[1]) | (b[0] << 8);
6741
c19d1205 6742 if (!status)
252b5132 6743 {
c19d1205
ZW		 6744 /* These bit patterns signal a four-byte Thumb
6745 instruction. */
6746 if ((given & 0xF800) == 0xF800
6747 || (given & 0xF800) == 0xF000
6748 || (given & 0xF800) == 0xE800)
252b5132 6749 {
0313a2b8 6750 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 6751 if (little_code)
c19d1205 6752 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 6753 else
c19d1205
ZW		 6754 given = (b[1]) | (b[0] << 8) | (given << 16);
6755
6756 printer = print_insn_thumb32;
4a5329c6 6757 size = 4;
252b5132 6758 }
252b5132 6759 }
c22aaad1
PB		 6760
6761 if (ifthen_address != pc)
0313a2b8 6762 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 6763
6764 if (ifthen_state)
6765 {
6766 if ((ifthen_state & 0xf) == 0x8)
6767 ifthen_next_state = 0;
6768 else
6769 ifthen_next_state = (ifthen_state & 0xe0)
6770 | ((ifthen_state & 0xf) << 1);
6771 }
252b5132 6772 }
b34976b6 6773
c19d1205
ZW		 6774 if (status)
6775 {
6776 info->memory_error_func (status, pc, info);
6777 return -1;
6778 }
6a56ec7e
NC		 6779 if (info->flags & INSN_HAS_RELOC)
6780 /* If the instruction has a reloc associated with it, then
6781 the offset field in the instruction will actually be the
6782 addend for the reloc. (We are using REL type relocs).
6783 In such cases, we can ignore the pc when computing
6784 addresses, since the addend is not currently pc-relative. */
6785 pc = 0;
b34976b6 6786
4a5329c6 6787 printer (pc, info, given);
c22aaad1
PB		 6788
6789 if (is_thumb)
6790 {
6791 ifthen_state = ifthen_next_state;
6792 ifthen_address += size;
6793 }
4a5329c6 6794 return size;
252b5132
RH		 6795}
6796
6797int
4a5329c6 6798print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 6799{
bd2e2557
SS		 6800 /* Detect BE8-ness and record it in the disassembler info. */
6801 if (info->flavour == bfd_target_elf_flavour
6802 && info->section != NULL
6803 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
6804 info->endian_code = BFD_ENDIAN_LITTLE;
6805
b34976b6 6806 return print_insn (pc, info, FALSE);
58efb6c0 6807}
01c7f630 6808
58efb6c0 6809int
4a5329c6 6810print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 6811{
b34976b6 6812 return print_insn (pc, info, TRUE);
58efb6c0 6813}
252b5132 6814
65b48a81
PB		 6815const disasm_options_t *
6816disassembler_options_arm (void)
6817{
6818 static disasm_options_t *opts = NULL;
6819
6820 if (opts == NULL)
6821 {
6822 unsigned int i;
6823 opts = XNEW (disasm_options_t);
6824 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
6825 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
6826 for (i = 0; i < NUM_ARM_OPTIONS; i++)
6827 {
6828 opts->name[i] = regnames[i].name;
6829 if (regnames[i].description != NULL)
6830 opts->description[i] = _(regnames[i].description);
6831 else
6832 opts->description[i] = NULL;
6833 }
6834 /* The array we return must be NULL terminated. */
6835 opts->name[i] = NULL;
6836 opts->description[i] = NULL;
6837 }
6838
6839 return opts;
6840}
6841
58efb6c0 6842void
4a5329c6 6843print_arm_disassembler_options (FILE *stream)
58efb6c0 6844{
65b48a81 6845 unsigned int i, max_len = 0;
58efb6c0
NC		 6846 fprintf (stream, _("\n\
6847The following ARM specific disassembler options are supported for use with\n\
6848the -M switch:\n"));
b34976b6 6849
65b48a81
PB		 6850 for (i = 0; i < NUM_ARM_OPTIONS; i++)
6851 {
6852 unsigned int len = strlen (regnames[i].name);
6853 if (max_len < len)
6854 max_len = len;
6855 }
58efb6c0 6856
65b48a81
PB		 6857 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
6858 fprintf (stream, " %s%*c %s\n",
6859 regnames[i].name,
6860 (int)(max_len - strlen (regnames[i].name)), ' ',
6861 _(regnames[i].description));
252b5132 6862}
GDB Binutils - Deliverables
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