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Use p_vaddr_offset to set p_vaddr on segments without sections
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
CommitLineData
252b5132 1/* Instruction printing code for the ARM
219d1afa 2 Copyright (C) 1994-2018 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
2fbad815 24
6394c606 25#include "disassemble.h"
2fbad815 26#include "opcode/arm.h"
252b5132 27#include "opintl.h"
31e0f3cd 28#include "safe-ctype.h"
65b48a81 29#include "libiberty.h"
0dbde4cf 30#include "floatformat.h"
252b5132 31
baf0cc5e 32/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 33#include "coff/internal.h"
34#include "libcoff.h"
252b5132
RH		 35#include "elf-bfd.h"
36#include "elf/internal.h"
37#include "elf/arm.h"
e49d43ff 38#include "mach-o.h"
252b5132 39
6b5d3a4d 40/* FIXME: Belongs in global header. */
01c7f630 41#ifndef strneq
58efb6c0
NC		 42#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
43#endif
44
1fbaefec
PB		 45/* Cached mapping symbol state. */
46enum map_type
47{
48 MAP_ARM,
49 MAP_THUMB,
50 MAP_DATA
51};
52
b0e28b39
DJ		 53struct arm_private_data
54{
55 /* The features to use when disassembling optional instructions. */
56 arm_feature_set features;
57
58 /* Whether any mapping symbols are present in the provided symbol
59 table. -1 if we do not know yet, otherwise 0 or 1. */
60 int has_mapping_symbols;
1fbaefec
PB		 61
62 /* Track the last type (although this doesn't seem to be useful) */
63 enum map_type last_type;
64
65 /* Tracking symbol table information */
66 int last_mapping_sym;
67 bfd_vma last_mapping_addr;
b0e28b39
DJ		 68};
69
6b5d3a4d
ZW		 70struct opcode32
71{
823d2571
TG		 72 arm_feature_set arch; /* Architecture defining this insn. */
73 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 74 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 75 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 76};
77
78struct opcode16
79{
823d2571 80 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 81 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 82 const char *assembler; /* How to disassemble this insn. */
83};
b7693d02 84
8f06b2d8 85/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 86
2fbad815 87 %% %
4a5329c6 88
c22aaad1 89 %c print condition code (always bits 28-31 in ARM mode)
37b37b2d 90 %q print shifter argument
e2efe87d
MGD		 91 %u print condition code (unconditional in ARM mode,
92 UNPREDICTABLE if not AL in Thumb)
4a5329c6 93 %A print address for ldc/stc/ldf/stf instruction
16980d0b 94 %B print vstm/vldm register list
4a5329c6 95 %I print cirrus signed shift immediate: bits 0..3|4..6
4a5329c6
ZW		 96 %F print the COUNT field of a LFM/SFM instruction.
97 %P print floating point precision in arithmetic insn
98 %Q print floating point precision in ldf/stf insn
99 %R print floating point rounding mode
100
33399f07 101 %<bitfield>c print as a condition code (for vsel)
4a5329c6 102 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 103 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
104 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 105 %<bitfield>d print the bitfield in decimal
16980d0b 106 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 107 %<bitfield>x print the bitfield in hex
108 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 109 %<bitfield>f print a floating point constant if >7 else a
110 floating point register
4a5329c6
ZW		 111 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
112 %<bitfield>g print as an iWMMXt 64-bit register
113 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 114 %<bitfield>D print as a NEON D register
115 %<bitfield>Q print as a NEON Q register
c28eeff2 116 %<bitfield>V print as a NEON D or Q register
6f1c2142 117 %<bitfield>E print a quarter-float immediate value
4a5329c6 118
16980d0b 119 %y<code> print a single precision VFP reg.
2fbad815 120 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 121 %z<code> print a double precision VFP reg
2fbad815 122 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 123
16980d0b
JB		 124 %<bitfield>'c print specified char iff bitfield is all ones
125 %<bitfield>`c print specified char iff bitfield is all zeroes
126 %<bitfield>?ab... select from array of values in big endian order
43e65147 127
2fbad815 128 %L print as an iWMMXt N/M width field.
4a5329c6 129 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 130 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 131 versions.
132 %i print 5-bit immediate in bits 8,3..0
133 (print "32" when 0)
fe56b6ce 134 %r print register offset address for wldt/wstr instruction. */
2fbad815 135
21d799b5 136enum opcode_sentinel_enum
05413229
NC		 137{
138 SENTINEL_IWMMXT_START = 1,
139 SENTINEL_IWMMXT_END,
140 SENTINEL_GENERIC_START
141} opcode_sentinels;
142
aefd8a40 143#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
c1e26897 144#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 145
8f06b2d8 146/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 147
8f06b2d8 148static const struct opcode32 coprocessor_opcodes[] =
2fbad815 149{
2fbad815 150 /* XScale instructions. */
823d2571
TG		 151 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
152 0x0e200010, 0x0fff0ff0,
153 "mia%c\tacc0, %0-3r, %12-15r"},
154 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
155 0x0e280010, 0x0fff0ff0,
156 "miaph%c\tacc0, %0-3r, %12-15r"},
157 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
158 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
159 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
160 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
161 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
162 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 163
2fbad815 164 /* Intel Wireless MMX technology instructions. */
823d2571
TG		 165 {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
166 {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
167 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
168 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
169 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
170 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
171 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
172 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
173 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
174 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
175 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
176 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
177 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
178 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
179 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
180 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
181 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
182 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
183 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
184 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
185 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
186 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
187 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
188 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
189 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
190 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
191 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
192 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
193 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
194 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
195 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
196 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
197 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
198 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
199 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
200 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
201 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
202 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
203 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
204 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
205 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
206 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
207 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
208 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
209 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
210 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
211 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
212 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
213 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
214 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
215 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
216 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
217 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
218 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
219 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
220 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
221 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
222 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
223 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
224 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
225 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
226 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
227 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
228 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
229 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
230 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
231 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
232 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
233 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
234 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
235 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
236 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
237 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
238 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
239 0x0e800120, 0x0f800ff0,
240 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
241 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
242 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
243 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
244 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
245 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
246 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
247 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
248 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
249 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
250 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
251 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
252 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
253 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
254 0x0e8000a0, 0x0f800ff0,
255 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
256 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
257 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
258 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
259 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
260 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
261 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
262 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
263 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
264 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
265 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
266 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
267 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
268 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
269 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
270 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
271 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
272 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
273 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
274 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
275 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
276 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
277 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
278 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
279 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
280 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
281 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
282 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
283 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
284 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
285 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
286 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
287 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
288 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
289 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
290 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
291 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
292 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
293 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
294 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
295 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
296 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
297 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
298 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
299 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
300 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
301 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
302 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
303 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
304 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
305 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
306 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
307 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
308 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
309 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
310 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
311 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
312 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
313 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
314 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
315 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
316 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
317 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
318 {ARM_FEATURE_CORE_LOW (0),
319 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 320
fe56b6ce 321 /* Floating point coprocessor (FPA) instructions. */
823d2571
TG		 322 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
323 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
324 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
325 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
326 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
327 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
328 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
329 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
330 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
331 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
332 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
333 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
334 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
335 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
336 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
337 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
338 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
339 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
340 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
341 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
342 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
343 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
344 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
345 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
346 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
347 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
348 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
349 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
350 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
351 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
352 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
353 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
354 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
355 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
356 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
357 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
358 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
359 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
360 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
361 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
362 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
363 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
364 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
365 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
366 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
367 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
368 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
369 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
370 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
371 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
372 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
373 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
374 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
375 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
376 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
377 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
378 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
379 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
380 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
381 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
382 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
383 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
384 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
385 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
386 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
387 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
388 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
389 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
390 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
391 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
392 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
393 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
394 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
395 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
396 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
397 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
398 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
399 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
400 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
401 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
402 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
403 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
404 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
405 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
406 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
407 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 408
16a1fa25
TP		 409 /* ARMv8-M Mainline Security Extensions instructions. */
410 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
411 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
412 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
413 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
414
fe56b6ce 415 /* Register load/store. */
823d2571
TG		 416 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
417 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
418 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
419 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
420 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
421 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
422 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
423 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
424 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
425 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
426 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
427 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
428 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
429 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
430 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
431 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
432 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
433 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
434 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
435 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
436 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
437 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
438 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
439 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
440 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
441 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
442 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
443 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
444 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
445 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
446 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
447 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
448
449 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
450 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
451 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
452 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
453 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
454 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
455 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
456 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 457
fe56b6ce 458 /* Data transfer between ARM and NEON registers. */
823d2571
TG		 459 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
460 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
462 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
464 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
466 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
468 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
470 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
472 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
474 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
476 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
478 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
480 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
482 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
484 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
486 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 487 /* Half-precision conversion instructions. */
823d2571
TG		 488 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
489 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
490 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
491 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
492 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
493 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
494 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
495 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 496
fe56b6ce 497 /* Floating point coprocessor (VFP) instructions. */
823d2571
TG		 498 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
499 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
500 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
501 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
502 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
503 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
504 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
505 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
40c7d507
RR		 506 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
507 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
823d2571
TG		 508 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
509 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
510 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
511 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
512 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
513 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
514 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
515 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
516 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
517 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
518 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
519 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
40c7d507
RR		 520 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
521 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
823d2571
TG		 522 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
523 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
524 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
525 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
526 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
527 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
528 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
529 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
530 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
531 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
532 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
533 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
534 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
535 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
536 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
537 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
538 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
539 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
540 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
541 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
542 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
543 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
544 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
545 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
546 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
547 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
548 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
549 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
550 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
551 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
552 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
553 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
554 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
555 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
556 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
557 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
558 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
559 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
560 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
561 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
562 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
563 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
564 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
565 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
566 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
567 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
568 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
569 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
570 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
571 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
572 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
573 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
574 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
575 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
576 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
577 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
578 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
579 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
580 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
581 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
582 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
583 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
584 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
585 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
586 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
587 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
588 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
589 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
590 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6f1c2142 591 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
823d2571 592 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6f1c2142 593 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
823d2571
TG		 594 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
595 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
596 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
597 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
598 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
599 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
600 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
601 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
602 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
603 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
604 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
605 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
606 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
607 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
608 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
609 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
610 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
611 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
612 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
613 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
614 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
615 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
616 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
617 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
618 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
619 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
620 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
621 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
622 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
623 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
624 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
625 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
626 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
627 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
628 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
629 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
630 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
631 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
632 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
633 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
634 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
635 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 636
637 /* Cirrus coprocessor instructions. */
823d2571
TG		 638 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
639 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
640 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
641 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
642 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
643 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
644 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
645 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
646 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
647 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
648 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
649 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
650 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
651 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
652 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
653 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
654 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
655 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
656 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
657 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
658 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
659 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
660 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
661 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
662 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
663 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
664 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
665 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
666 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
667 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
668 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
669 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
670 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
671 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
672 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
673 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
674 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
675 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
676 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
677 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
678 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
679 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
680 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
681 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
682 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
683 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
684 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
685 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
686 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
687 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
688 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
689 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
690 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
691 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
692 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
693 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
694 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
695 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
696 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
697 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
698 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
699 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
700 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
701 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
702 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
703 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
704 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
705 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
706 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
707 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
708 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
709 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
710 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
711 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
712 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
713 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
714 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
715 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
716 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
717 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
718 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
719 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
720 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
721 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
722 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
723 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
724 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
725 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
726 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
727 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
728 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
729 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
730 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
731 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
732 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
733 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
734 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
735 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
736 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
737 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
738 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
739 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
740 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
741 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
742 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
743 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
744 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
745 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
746 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
747 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
748 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
749 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
750 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
751 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
752 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
753 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
754 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
755 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
756 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
757 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
758 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
759 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
760 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
761 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
762 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
763 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
764 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
765 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
766 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
767 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
768 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
769 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
770 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
771 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
772 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
773 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
774 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
775 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
776 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
777 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
778 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
779 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
780 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
781 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
782 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
783 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
784 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
785 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
786 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
787 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
788 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
789 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
790 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
791 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
792 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
793 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
794 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
795 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
796 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
797 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
798 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
799 0x0e000600, 0x0ff00f10,
800 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
801 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
802 0x0e100600, 0x0ff00f10,
803 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
804 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
805 0x0e200600, 0x0ff00f10,
806 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
807 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
808 0x0e300600, 0x0ff00f10,
809 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 810
62f3b8c8 811 /* VFP Fused multiply add instructions. */
823d2571
TG		 812 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
813 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
814 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
815 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
816 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
817 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
818 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
819 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
820 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
821 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
822 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
824 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
825 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
826 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
827 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 828
33399f07 829 /* FP v5. */
823d2571 830 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 831 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
823d2571 832 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 833 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
823d2571 834 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 835 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
823d2571 836 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 837 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
823d2571 838 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 839 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
823d2571 840 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 841 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
823d2571
TG		 842 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
843 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
844 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
845 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
846 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
847 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
848 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
849 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
850 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 851 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
823d2571 852 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 853 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 854
05413229 855 /* Generic coprocessor instructions. */
823d2571
TG		 856 {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
858 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
860 0x0c500000, 0x0ff00000,
861 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
863 0x0e000000, 0x0f000010,
864 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
866 0x0e10f010, 0x0f10f010,
867 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
869 0x0e100010, 0x0f100010,
870 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
872 0x0e000010, 0x0f100010,
873 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
875 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
877 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
2fbad815 878
05413229 879 /* V6 coprocessor instructions. */
823d2571
TG		 880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
881 0xfc500000, 0xfff00000,
882 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
884 0xfc400000, 0xfff00000,
885 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
8f06b2d8 886
c28eeff2
SN		 887 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
888 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
889 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
890 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
891 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
892 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
893 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
894 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
895 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
896 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
897 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
898 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
899 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
900 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 901 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
c28eeff2 902 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 903 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
c28eeff2 904 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 905 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
c28eeff2 906 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 907 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
c28eeff2 908
c604a79a
JW		 909 /* Dot Product instructions in the space of coprocessor 13. */
910 {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
911 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
912 {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
913 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
914
dec41383
JW		 915 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
916 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
917 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
918 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
919 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
920 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
921 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
922 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
923 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
924 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
925 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
926 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
927 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
928 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
929 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
930 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
931 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
932
05413229 933 /* V5 coprocessor instructions. */
823d2571
TG		 934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
935 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
937 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
939 0xfe000000, 0xff000010,
940 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
942 0xfe000010, 0xff100010,
943 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
945 0xfe100010, 0xff100010,
946 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
947
b0c11777
RL		 948 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
949 cp_num: bit <11:8> == 0b1001.
950 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
951 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
952 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
953 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
954 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
955 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
956 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
957 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
958 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
959 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
960 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
961 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
962 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
963 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
964 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
965 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
966 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
967 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
968 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
969 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
970 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
971 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
972 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
973 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
974 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
975 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
976 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
977 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
978 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
979 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
980 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
981 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
982 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
983 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
984 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
985 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
986 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
987 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
988 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
989 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
990 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
991 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
992 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
993 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
994 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
995 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
996 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
997 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
998 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
999 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1000 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1001 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1002 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1003 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1004 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1005 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1006 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1007 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1008 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1009 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1010 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1011 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1012 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1013 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1014 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1015 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1016 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1017 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1018 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1019 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1020 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1021
49e8a725
SN		 1022 /* ARMv8.3 javascript conversion instruction. */
1023 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1024 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1025
823d2571 1026 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 1027};
1028
16980d0b
JB		 1029/* Neon opcode table: This does not encode the top byte -- that is
1030 checked by the print_insn_neon routine, as it depends on whether we are
1031 doing thumb32 or arm32 disassembly. */
1032
1033/* print_insn_neon recognizes the following format control codes:
1034
1035 %% %
1036
c22aaad1 1037 %c print condition code
e2efe87d
MGD		 1038 %u print condition code (unconditional in ARM mode,
1039 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 1040 %A print v{st,ld}[1234] operands
1041 %B print v{st,ld}[1234] any one operands
1042 %C print v{st,ld}[1234] single->all operands
1043 %D print scalar
1044 %E print vmov, vmvn, vorr, vbic encoded constant
1045 %F print vtbl,vtbx register list
1046
1047 %<bitfield>r print as an ARM register
1048 %<bitfield>d print the bitfield in decimal
1049 %<bitfield>e print the 2^N - bitfield in decimal
1050 %<bitfield>D print as a NEON D register
1051 %<bitfield>Q print as a NEON Q register
1052 %<bitfield>R print as a NEON D or Q register
1053 %<bitfield>Sn print byte scaled width limited by n
1054 %<bitfield>Tn print short scaled width limited by n
1055 %<bitfield>Un print long scaled width limited by n
43e65147 1056
16980d0b
JB		 1057 %<bitfield>'c print specified char iff bitfield is all ones
1058 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1059 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1060
1061static const struct opcode32 neon_opcodes[] =
1062{
fe56b6ce 1063 /* Extract. */
823d2571
TG		 1064 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1065 0xf2b00840, 0xffb00850,
1066 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1067 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1068 0xf2b00000, 0xffb00810,
1069 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 1070
fe56b6ce 1071 /* Move data element to all lanes. */
823d2571
TG		 1072 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1073 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1074 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1075 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1076 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1077 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 1078
fe56b6ce 1079 /* Table lookup. */
823d2571
TG		 1080 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1081 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1082 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1083 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1084
8e79c3df 1085 /* Half-precision conversions. */
823d2571
TG		 1086 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1087 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1088 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1089 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1090
1091 /* NEON fused multiply add instructions. */
823d2571 1092 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1093 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1094 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1095 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1096 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1097 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1098 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1099 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1100
fe56b6ce 1101 /* Two registers, miscellaneous. */
823d2571
TG		 1102 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1103 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1104 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1105 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1106 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1107 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1108 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1109 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1110 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1111 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1112 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1113 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1114 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1115 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1116 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1117 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1118 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1119 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1120 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1121 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1122 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1123 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1124 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1125 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1126 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1127 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1128 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1129 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1130 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1131 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1132 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1133 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1134 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1135 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1136 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1137 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1138 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1139 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1140 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1141 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1142 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1143 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1144 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1145 0xf3b20300, 0xffb30fd0,
1146 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1147 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1148 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1149 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1150 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1151 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1152 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1153 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1154 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1155 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1156 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1157 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1158 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1159 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1160 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1161 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1162 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1163 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1164 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1165 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1166 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1167 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1168 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1169 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1170 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1171 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1172 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1173 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1174 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1175 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1176 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1177 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1178 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1179 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1180 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1181 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1182 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1183 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1184 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1185 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1186 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1187 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1188 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1189 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1190 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1191 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1192 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1193 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301 1194 0xf3bb0600, 0xffbf0e10,
823d2571 1195 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1196 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1197 0xf3b70600, 0xffbf0e10,
1198 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
16980d0b 1199
fe56b6ce 1200 /* Three registers of the same length. */
823d2571
TG		 1201 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1202 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1203 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1204 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1205 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1206 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1207 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1208 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1209 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1210 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1211 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1212 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1213 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1214 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1215 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1216 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1217 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1218 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1219 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1220 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1221 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1222 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1223 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1224 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1225 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1226 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1227 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1228 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1229 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1230 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1231 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1232 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1233 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1234 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1235 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1236 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1237 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1238 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1239 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1240 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1241 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1242 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1243 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1244 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1245 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1246 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1247 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1248 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1249 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1250 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1251 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1252 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1253 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1254 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1255 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1256 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1257 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1258 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1259 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1260 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1261 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1262 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1263 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1264 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1265 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1266 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1267 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1268 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1269 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1270 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1271 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1272 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1273 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1274 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1275 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1276 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1277 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1278 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1279 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1280 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1281 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1282 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1283 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1284 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1285 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1286 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1287 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1288 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1289 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1290 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1291 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1292 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1293 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1294 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1295 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1296 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1297 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1298 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1299 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1300 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1301 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1302 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1303 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1304 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1305 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1306 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1307 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1308 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1309 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1310 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1311 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1312 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1313 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1314 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1315 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1316 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1317 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1318 0xf2000b00, 0xff800f10,
1319 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1320 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1321 0xf2000b10, 0xff800f10,
1322 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1323 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1324 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1325 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1326 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1327 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1328 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1329 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1330 0xf3000b00, 0xff800f10,
1331 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1332 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1333 0xf2000000, 0xfe800f10,
1334 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1335 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1336 0xf2000010, 0xfe800f10,
1337 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1338 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1339 0xf2000100, 0xfe800f10,
1340 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1341 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1342 0xf2000200, 0xfe800f10,
1343 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1344 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1345 0xf2000210, 0xfe800f10,
1346 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1347 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1348 0xf2000300, 0xfe800f10,
1349 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1350 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1351 0xf2000310, 0xfe800f10,
1352 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1353 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1354 0xf2000400, 0xfe800f10,
1355 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1356 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1357 0xf2000410, 0xfe800f10,
1358 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1359 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1360 0xf2000500, 0xfe800f10,
1361 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1362 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1363 0xf2000510, 0xfe800f10,
1364 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1365 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1366 0xf2000600, 0xfe800f10,
1367 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1368 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1369 0xf2000610, 0xfe800f10,
1370 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1371 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1372 0xf2000700, 0xfe800f10,
1373 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1374 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1375 0xf2000710, 0xfe800f10,
1376 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1377 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1378 0xf2000910, 0xfe800f10,
1379 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1380 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1381 0xf2000a00, 0xfe800f10,
1382 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1383 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1384 0xf2000a10, 0xfe800f10,
1385 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1386 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1387 0xf3000b10, 0xff800f10,
1388 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1389 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1390 0xf3000c10, 0xff800f10,
1391 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1392
fe56b6ce 1393 /* One register and an immediate value. */
823d2571
TG		 1394 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1395 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1396 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1397 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1398 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1399 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1400 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1401 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1402 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1403 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1404 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1405 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1406 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1407 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1408 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1409 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1410 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1411 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1412 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1413 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1414 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1415 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1416 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1417 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1418 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1419 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1420
fe56b6ce 1421 /* Two registers and a shift amount. */
823d2571
TG		 1422 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1423 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1424 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1425 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1426 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1427 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1428 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1429 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1430 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1431 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1432 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1433 0xf2880950, 0xfeb80fd0,
1434 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1435 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1436 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1437 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1438 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1439 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1440 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1441 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1442 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1443 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1444 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1445 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1446 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1447 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1448 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1449 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1450 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1451 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1452 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1453 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1454 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1456 0xf2900950, 0xfeb00fd0,
1457 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1458 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1459 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1460 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1461 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1462 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1463 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1465 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1466 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1467 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1468 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1469 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1470 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1471 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1473 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1474 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1475 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1477 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1478 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1479 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1481 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1482 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1483 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1484 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1485 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1487 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1489 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1490 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1491 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1492 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1493 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1494 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1495 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1496 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1497 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1498 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1499 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1500 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1501 0xf2a00950, 0xfea00fd0,
1502 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1503 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1504 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1511 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1512 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1515 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1517 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1518 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1519 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1520 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1521 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1522 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1523 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1524 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1525 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1526 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1527 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1528 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1530 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1531 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1532 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1533 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1534 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1535 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1536 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1537 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1538 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1539 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1540 0xf2a00e10, 0xfea00e90,
1541 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
cc933301
JW		 1542 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1543 0xf2a00c10, 0xfea00e90,
1544 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 1545
fe56b6ce 1546 /* Three registers of different lengths. */
823d2571
TG		 1547 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1548 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1549 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1550 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1551 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1552 0xf2800400, 0xff800f50,
1553 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1554 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1555 0xf2800600, 0xff800f50,
1556 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1557 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1558 0xf2800900, 0xff800f50,
1559 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1560 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1561 0xf2800b00, 0xff800f50,
1562 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1564 0xf2800d00, 0xff800f50,
1565 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1566 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1567 0xf3800400, 0xff800f50,
1568 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1569 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1570 0xf3800600, 0xff800f50,
1571 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1572 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1573 0xf2800000, 0xfe800f50,
1574 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1576 0xf2800100, 0xfe800f50,
1577 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1578 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1579 0xf2800200, 0xfe800f50,
1580 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1581 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1582 0xf2800300, 0xfe800f50,
1583 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1584 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1585 0xf2800500, 0xfe800f50,
1586 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1587 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1588 0xf2800700, 0xfe800f50,
1589 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1590 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1591 0xf2800800, 0xfe800f50,
1592 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1594 0xf2800a00, 0xfe800f50,
1595 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1596 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1597 0xf2800c00, 0xfe800f50,
1598 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 1599
fe56b6ce 1600 /* Two registers and a scalar. */
823d2571
TG		 1601 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1602 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1603 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1604 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1605 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1606 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1607 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1608 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1609 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1610 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1611 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1612 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1613 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1614 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1615 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1616 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1618 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1619 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1620 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1621 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1622 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1623 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1624 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1625 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1626 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1627 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1628 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1630 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1631 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1632 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1633 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1634 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1635 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1636 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1638 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1639 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1640 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1642 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1643 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1644 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1645 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1646 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1647 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1648 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1650 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1651 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1652 0xf2800240, 0xfe800f50,
1653 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1654 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1655 0xf2800640, 0xfe800f50,
1656 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1658 0xf2800a40, 0xfe800f50,
1659 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 1660 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1661 0xf2800e40, 0xff800f50,
1662 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1663 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1664 0xf2800f40, 0xff800f50,
1665 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1666 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1667 0xf3800e40, 0xff800f50,
1668 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1669 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1670 0xf3800f40, 0xff800f50,
1671 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1672 },
16980d0b 1673
fe56b6ce 1674 /* Element and structure load/store. */
823d2571
TG		 1675 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1676 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1677 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1678 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1679 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1680 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1681 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1682 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1683 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1684 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1685 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1686 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1687 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1688 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1689 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1690 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1691 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1692 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1693 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1694 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1695 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1696 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1697 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1698 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1699 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1700 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1701 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1702 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1703 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1704 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1705 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1706 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1707 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1708 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1709 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1710 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1711 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1712 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1713
1714 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 1715};
1716
8f06b2d8
PB		 1717/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
1718 ordered: they must be searched linearly from the top to obtain a correct
1719 match. */
1720
1721/* print_insn_arm recognizes the following format control codes:
1722
1723 %% %
1724
1725 %a print address for ldr/str instruction
1726 %s print address for ldr/str halfword/signextend instruction
c1e26897 1727 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 1728 %b print branch destination
1729 %c print condition code (always bits 28-31)
1730 %m print register mask for ldm/stm instruction
1731 %o print operand2 (immediate or register + shift)
1732 %p print 'p' iff bits 12-15 are 15
1733 %t print 't' iff bit 21 set and bit 24 clear
1734 %B print arm BLX(1) destination
1735 %C print the PSR sub type.
62b3e311
PB		 1736 %U print barrier type.
1737 %P print address for pli instruction.
8f06b2d8
PB		 1738
1739 %<bitfield>r print as an ARM register
9eb6c0f1 1740 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 1741 %<bitfield>R as %r but r15 is UNPREDICTABLE
1742 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1743 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 1744 %<bitfield>d print the bitfield in decimal
43e65147 1745 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 1746 %<bitfield>x print the bitfield in hex
1747 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 1748
16980d0b
JB		 1749 %<bitfield>'c print specified char iff bitfield is all ones
1750 %<bitfield>`c print specified char iff bitfield is all zeroes
1751 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 1752
8f06b2d8
PB		 1753 %e print arm SMI operand (bits 0..7,8..19).
1754 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 1755 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
1756 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 1757
8f06b2d8
PB		 1758static const struct opcode32 arm_opcodes[] =
1759{
1760 /* ARM instructions. */
823d2571
TG		 1761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1762 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1764 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1765
1766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
1767 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1769 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1771 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
1773 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1775 0x00800090, 0x0fa000f0,
1776 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1778 0x00a00090, 0x0fa000f0,
1779 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 1780
105bde57 1781 /* V8.2 RAS extension instructions. */
4d1464f2 1782 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 1783 0xe320f010, 0xffffffff, "esb"},
1784
53c4b28b 1785 /* V8 instructions. */
823d2571
TG		 1786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1787 0x0320f005, 0x0fffffff, "sevl"},
1788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1789 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
4ed7ed8d 1790 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 1791 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1792 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 1793 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1795 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1797 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 1798 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1799 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1800 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1801 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1802 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1803 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1804 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1805 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1806 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1807 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1808 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1809 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1810 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1811 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1812 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1813 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1814 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1815 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1816 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 1817 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 1818 /* CRC32 instructions. */
823d2571
TG		 1819 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1820 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
1821 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1822 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
1823 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1824 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
1825 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1826 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
1827 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1828 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
1829 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1830 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 1831
ddfded2f
MW		 1832 /* Privileged Access Never extension instructions. */
1833 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
1834 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
1835
90ec0d68 1836 /* Virtualization Extension instructions. */
823d2571
TG		 1837 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
1838 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 1839
eea54501 1840 /* Integer Divide Extension instructions. */
823d2571
TG		 1841 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1842 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1843 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1844 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 1845
60e5ef9f 1846 /* MP Extension instructions. */
823d2571 1847 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 1848
c597cc3d
SD		 1849 /* Speculation Barriers. */
1850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
1851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
1852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
1853
62b3e311 1854 /* V7 instructions. */
823d2571
TG		 1855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
1856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
1858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
1859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a
AV		 1862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
1863 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
62b3e311 1864
c19d1205 1865 /* ARM V6T2 instructions. */
823d2571
TG		 1866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1867 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1869 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1871 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1873 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
1874
1875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1876 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
1877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1878 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1879
ff8646ee 1880 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 1881 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 1882 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 1883 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1885 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1887 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 1888
f4c65163 1889 /* ARM Security extension instructions. */
823d2571
TG		 1890 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
1891 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 1892
8f06b2d8 1893 /* ARM V6K instructions. */
823d2571
TG		 1894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1895 0xf57ff01f, 0xffffffff, "clrex"},
1896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1897 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1899 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1901 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1903 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1905 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1907 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 1908
7fadb25d
SD		 1909 /* ARMv8.5-A instructions. */
1910 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
1911
8f06b2d8 1912 /* ARM V6K NOP hints. */
823d2571
TG		 1913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1914 0x0320f001, 0x0fffffff, "yield%c"},
1915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1916 0x0320f002, 0x0fffffff, "wfe%c"},
1917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1918 0x0320f003, 0x0fffffff, "wfi%c"},
1919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1920 0x0320f004, 0x0fffffff, "sev%c"},
1921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1922 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 1923
fe56b6ce 1924 /* ARM V6 instructions. */
823d2571
TG		 1925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1926 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
1927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1928 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
1929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1930 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
1931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1932 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
1933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1934 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
1935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1936 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
1937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1938 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
1939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1940 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
1941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1942 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
1943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1944 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
1945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1946 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
1947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1948 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
1949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1950 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
1951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1952 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
1953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1954 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
1955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1956 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
1957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1958 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
1959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1960 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
1961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1962 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
1963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1964 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
1965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1966 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
1967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1968 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
1969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1970 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
1971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1972 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
1973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1974 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
1975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1976 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
1977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1978 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
1979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1980 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
1981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1982 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
1983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1984 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
1985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1986 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
1987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1988 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
1989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1990 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
1991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1992 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
1993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1994 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
1995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1996 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
1997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1998 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
1999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2000 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
2001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2002 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
2003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2004 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
2005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2006 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
2007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2008 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
2009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2010 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
2011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2012 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
2013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2014 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
2015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2016 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
2017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2018 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
2019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2020 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
2021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2022 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
2023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2024 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
2025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2026 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
2027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2028 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
2029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2030 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
2031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2032 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
2033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2034 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
2035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2036 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
2037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2038 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
2039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2040 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
2041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2042 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
2043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2044 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
2045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2046 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
2047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2048 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
2049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2050 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
2051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2052 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
2053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2054 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
2055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2056 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
2057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2058 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
2059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2060 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
2061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2062 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
2063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2064 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
2065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2066 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
2067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2068 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
2069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2070 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
2071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2072 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
2073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2074 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
2075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2076 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2078 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2080 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2082 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
2083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2084 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2086 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2088 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2090 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
2091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2092 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2094 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2096 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2098 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
2099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2100 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2102 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2104 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2106 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
2107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2108 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2110 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2112 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
2113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2114 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
2115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2116 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2118 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2120 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2122 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
2123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2124 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
2125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2126 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
2127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2128 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
2129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2130 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2132 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2134 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2136 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2138 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
2139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2140 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2142 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2144 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
2145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2146 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
2147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2148 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
2149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2150 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
2151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2152 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
2153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2154 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
2155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2156 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
2157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2158 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
2159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2160 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2162 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
2163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2164 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
2165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2166 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
2167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2168 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 2169
8f06b2d8 2170 /* V5J instruction. */
823d2571
TG		 2171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
2172 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 2173
8f06b2d8 2174 /* V5 Instructions. */
823d2571
TG		 2175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2176 0xe1200070, 0xfff000f0,
2177 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
2178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2179 0xfa000000, 0xfe000000, "blx\t%B"},
2180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2181 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
2182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2183 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
2184
2185 /* V5E "El Segundo" Instructions. */
2186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2187 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
2188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2189 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
2190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2191 0xf450f000, 0xfc70f000, "pld\t%a"},
2192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2193 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2195 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2196 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2197 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2199 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
2200
2201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2202 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2203 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2204 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
2205
2206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2207 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2209 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2210 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2211 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2212 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2213 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2214
2215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2216 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2217 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2218 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2220 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2222 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2223
2224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2225 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2227 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2228
2229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2230 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
2231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2232 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2234 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
2235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2236 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 2237
8f06b2d8 2238 /* ARM Instructions. */
823d2571
TG		 2239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2240 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2241
2242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2243 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2245 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2247 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2249 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2251 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2252 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2253 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2254
2255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2256 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2257 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2258 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2259 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2260 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2261 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2262 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2263
2264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2265 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2266 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2267 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2269 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2271 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2272
2273 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2274 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2275 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2276 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2277 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2278 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2279
2280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2281 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2282 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2283 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2285 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2286
2287 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2288 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2289 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2290 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2292 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2293
2294 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2295 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2297 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2299 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2300
2301 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2302 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2304 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2305 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2306 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2307
2308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2309 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2310 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2311 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2313 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2314
2315 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2316 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2317 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2318 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2320 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2321
2322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2323 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2325 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2327 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2328
2329 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2330 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2331 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2332 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2334 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2335
2336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2337 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2339 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2341 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2342
2343 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2344 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 2345 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2346 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 2347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2348 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
823d2571
TG		 2349
2350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2351 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2353 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2355 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2356
2357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2358 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2360 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2362 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2363
2364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2365 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2367 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2369 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2370
2371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2372 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2374 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2376 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2378 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2380 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2382 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2384 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2385
2386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2387 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2389 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2391 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2392
2393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2394 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2395 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2396 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2397 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2398 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2399
2400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2401 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2403 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2404
2405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2406 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2407
2408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2409 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2411 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2412
2413 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2414 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2415 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2416 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2418 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2419 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2420 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2422 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2424 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2425 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2426 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2427 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2428 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2429 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2430 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2431 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2432 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2433 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2434 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2435 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2436 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2437 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2438 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2439 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2440 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2441 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2442 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2443 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2444 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2446 0x092d0000, 0x0fff0000, "push%c\t%m"},
2447 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2448 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2450 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2451
2452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2453 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2455 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2457 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2459 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2461 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2463 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2465 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2467 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2469 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2471 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2473 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2475 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2476 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2477 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2478 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2479 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2480 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2481 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2482 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2483 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2485 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2487 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2489 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2490
2491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2492 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2494 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 2495
2496 /* The rest. */
4ab90a7a
AV		 2497 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2498 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 2499 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2500 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2501 {ARM_FEATURE_CORE_LOW (0),
2502 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 2503};
2504
2505/* print_insn_thumb16 recognizes the following format control codes:
2506
2507 %S print Thumb register (bits 3..5 as high number if bit 6 set)
2508 %D print Thumb register (bits 0..2 as high number if bit 7 set)
2509 %<bitfield>I print bitfield as a signed decimal
2510 (top bit of range being the sign bit)
2511 %N print Thumb register mask (with LR)
2512 %O print Thumb register mask (with PC)
2513 %M print Thumb register mask
2514 %b print CZB's 6-bit unsigned branch destination
2515 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 2516 %c print the condition code
2517 %C print the condition code, or "s" if not conditional
2518 %x print warning if conditional an not at end of IT block"
2519 %X print "\t; unpredictable <IT:code>" if conditional
2520 %I print IT instruction suffix and operands
4547cb56 2521 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 2522 %<bitfield>r print bitfield as an ARM register
2523 %<bitfield>d print bitfield as a decimal
2524 %<bitfield>H print (bitfield * 2) as a decimal
2525 %<bitfield>W print (bitfield * 4) as a decimal
2526 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
2527 %<bitfield>B print Thumb branch destination (signed displacement)
2528 %<bitfield>c print bitfield as a condition code
2529 %<bitnum>'c print specified char iff bit is one
2530 %<bitnum>?ab print a if bit is one else print b. */
2531
2532static const struct opcode16 thumb_opcodes[] =
2533{
2534 /* Thumb instructions. */
2535
16a1fa25
TP		 2536 /* ARMv8-M Security Extensions instructions. */
2537 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
e207bc53 2538 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
16a1fa25 2539
53c4b28b 2540 /* ARM V8 instructions. */
823d2571
TG		 2541 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
2542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
ddfded2f 2543 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
53c4b28b 2544
8f06b2d8 2545 /* ARM V6K no-argument instructions. */
823d2571
TG		 2546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 2552
2553 /* ARM V6T2 instructions. */
ff8646ee
TP		 2554 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2555 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2556 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2557 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 2558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 2559
2560 /* ARM V6. */
823d2571
TG		 2561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2563 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 2572
2573 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 2574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2575 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 2576 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 2577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2578 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 2579 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 2580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2581 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 2582 /* Format 4. */
823d2571
TG		 2583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2591 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 2599 /* format 13 */
823d2571
TG		 2600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2601 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 2602 /* format 5 */
823d2571
TG		 2603 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
2604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
2605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 2607 /* format 14 */
823d2571
TG		 2608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
2609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 2610 /* format 2 */
823d2571
TG		 2611 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2612 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2613 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2614 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2615 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2616 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2617 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2618 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 2619 /* format 8 */
823d2571
TG		 2620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2621 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2622 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2623 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2625 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2626 /* format 7 */
823d2571
TG		 2627 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2628 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2629 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2630 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2631 /* format 1 */
823d2571
TG		 2632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2634 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 2637 /* format 3 */
823d2571
TG		 2638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2641 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 2642 /* format 6 */
823d2571
TG		 2643 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2645 0x4800, 0xF800,
2646 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 2647 /* format 9 */
823d2571
TG		 2648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2649 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2651 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2652 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2653 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2655 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 2656 /* format 10 */
823d2571
TG		 2657 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2658 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2660 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 2661 /* format 11 */
823d2571
TG		 2662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2663 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2665 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 2666 /* format 12 */
823d2571
TG		 2667 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2668 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2669 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2670 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 2671 /* format 15 */
823d2571
TG		 2672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2673 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 2674 /* format 17 */
823d2571 2675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 2676 /* format 16 */
823d2571
TG		 2677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
2679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 2680 /* format 18 */
823d2571 2681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 2682
2683 /* The E800 .. FFFF range is unconditionally redirected to the
2684 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2685 are processed via that table. Thus, we can never encounter a
2686 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 2687 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
2688 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 2689};
2690
2691/* Thumb32 opcodes use the same table structure as the ARM opcodes.
2692 We adopt the convention that hw1 is the high 16 bits of .value and
2693 .mask, hw2 the low 16 bits.
2694
2695 print_insn_thumb32 recognizes the following format control codes:
2696
2697 %% %
2698
2699 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2700 %M print a modified 12-bit immediate (same location)
2701 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2702 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 2703 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 2704 %S print a possibly-shifted Rm
2705
32a94698 2706 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 2707 %a print the address of a plain load/store
2708 %w print the width and signedness of a core load/store
2709 %m print register mask for ldm/stm
2710
2711 %E print the lsb and width fields of a bfc/bfi instruction
2712 %F print the lsb and width fields of a sbfx/ubfx instruction
2713 %b print a conditional branch offset
2714 %B print an unconditional branch offset
2715 %s print the shift field of an SSAT instruction
2716 %R print the rotation field of an SXT instruction
62b3e311
PB		 2717 %U print barrier type.
2718 %P print address for pli instruction.
c22aaad1
PB		 2719 %c print the condition code
2720 %x print warning if conditional an not at end of IT block"
2721 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 2722
2723 %<bitfield>d print bitfield in decimal
f0fba320 2724 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 2725 %<bitfield>W print bitfield*4 in decimal
2726 %<bitfield>r print bitfield as an ARM register
dd5181d5 2727 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
8f06b2d8
PB		 2728 %<bitfield>c print bitfield as a condition code
2729
16980d0b
JB		 2730 %<bitfield>'c print specified char iff bitfield is all ones
2731 %<bitfield>`c print specified char iff bitfield is all zeroes
2732 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 2733
2734 With one exception at the bottom (done because BL and BLX(1) need
2735 to come dead last), this table was machine-sorted first in
2736 decreasing order of number of bits set in the mask, then in
2737 increasing numeric order of mask, then in increasing numeric order
2738 of opcode. This order is not the clearest for a human reader, but
2739 is guaranteed never to catch a special-case bit pattern with a more
2740 general mask, which is important, because this instruction encoding
2741 makes heavy use of special-case bit patterns. */
2742static const struct opcode32 thumb32_opcodes[] =
2743{
16a1fa25
TP		 2744 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
2745 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4ed7ed8d
TP		 2746 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2747 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
2748 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2749 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
16a1fa25
TP		 2750 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2751 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
2752 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2753 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4ed7ed8d 2754
105bde57 2755 /* ARM V8.2 RAS extension instructions. */
4d1464f2 2756 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 2757 0xf3af8010, 0xffffffff, "esb"},
2758
53c4b28b 2759 /* V8 instructions. */
823d2571
TG		 2760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2761 0xf3af8005, 0xffffffff, "sevl%c.w"},
2762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2763 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2765 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2767 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
2768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2769 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
2770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2771 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
2772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2773 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
2774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2775 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
2776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2777 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
2778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2779 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2781 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2783 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
2784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2785 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2787 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2789 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2791 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 2792
dd5181d5 2793 /* CRC32 instructions. */
823d2571 2794 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2795 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
823d2571 2796 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2797 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
823d2571 2798 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2799 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
823d2571 2800 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2801 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
823d2571 2802 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2803 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
823d2571 2804 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2805 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
dd5181d5 2806
c597cc3d
SD		 2807 /* Speculation Barriers. */
2808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
2809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
2810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
2811
62b3e311 2812 /* V7 instructions. */
823d2571
TG		 2813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
2814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
2815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
2816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
2817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
2818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
2819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
2820 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2821 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
2822 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2823 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 2824
90ec0d68 2825 /* Virtualization Extension instructions. */
823d2571 2826 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 2827 /* We skip ERET as that is SUBS pc, lr, #0. */
2828
60e5ef9f 2829 /* MP Extension instructions. */
823d2571 2830 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 2831
f4c65163 2832 /* Security extension instructions. */
823d2571 2833 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 2834
7fadb25d
SD		 2835 /* ARMv8.5-A instructions. */
2836 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
2837
8f06b2d8 2838 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 2839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
2840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
2841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
2844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2845 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
2846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
2847
ff8646ee 2848 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2849 0xf3bf8f2f, 0xffffffff, "clrex%c"},
2850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2851 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
2852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2853 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
2854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2855 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
2856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2857 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
2858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2859 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
2860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2861 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
2862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2863 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
2864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2865 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
2866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2867 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
2868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2869 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
2870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2871 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
2872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2873 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
2874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2875 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 2876 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 2877 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 2878 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2879 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
2880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2881 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
2882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2883 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
2884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2885 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
2886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2887 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
2888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2889 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
2890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2891 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
2892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2893 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
2894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2895 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 2896 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2897 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
2898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2899 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
2900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2901 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
2902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2903 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
2904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2905 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
2906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2907 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
2908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2909 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
2910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2911 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
2912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2913 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
2914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2915 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
2916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2917 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
2918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2919 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
2920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2921 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
2922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2923 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
2924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2925 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
2926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2927 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
2928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2929 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
2930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2931 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
2932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2933 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
2934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2935 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
2936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2937 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
2938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2939 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
2940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2941 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
2942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2943 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
2944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2945 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
2946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2947 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
2948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2949 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
2950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2951 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
2952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2953 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
2954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2955 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
2956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2957 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
2958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2959 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
2960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2961 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
2962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2963 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
2964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2965 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
2966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2967 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
2968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2969 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
2970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2971 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
2972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2973 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
2974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2975 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
2976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2977 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
2978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2979 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
2980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2981 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
2982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2983 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
2984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2985 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
2986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2987 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
2988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2989 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
2990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2991 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
2992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2993 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
2994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2995 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
2996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2997 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2999 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3001 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3003 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 3004 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3005 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
3006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 3007 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 3008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3009 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
3010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3011 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
3012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3013 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3015 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
3016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3017 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
3018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3019 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3021 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3023 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3025 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3027 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3029 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3031 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3033 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
3034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3035 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
3036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3037 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
3038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3039 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
3040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3041 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
3042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3043 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
3044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3045 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
3046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3047 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
3048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3049 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
3050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3051 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
3052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3053 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
3054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3055 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
3056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3057 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3059 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3061 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3063 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3065 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3067 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3069 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3071 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 3072 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3073 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
3074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3075 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
3076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3077 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
3078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3079 0xf810f000, 0xff70f000, "pld%c\t%a"},
3080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3081 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3083 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3085 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3087 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3089 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3091 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3093 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3095 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
3096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3097 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
3098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3099 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
3100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3101 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
3102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3103 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
3104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3105 0xfb100000, 0xfff000c0,
3106 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3108 0xfbc00080, 0xfff000c0,
3109 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
3110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3111 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
3112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3113 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
3114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 3115 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 3116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3117 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
3118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3119 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 3120 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3121 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
3122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3123 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 3124 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3125 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
3126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3127 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
3128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3129 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
3130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3131 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
3132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3133 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
3134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3135 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
3136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3137 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
3138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3139 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
3140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3141 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
3142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3143 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
3144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3145 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 3146 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3147 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
3148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3149 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
3150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3151 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
3152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3153 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
3154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3155 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
3156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3157 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
3158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3159 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
3160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3161 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
3162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3163 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
3164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3165 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
3166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3167 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
3168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3169 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
3170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3171 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
3172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3173 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
3174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3175 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
3176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3177 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
3178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3179 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
3180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3181 0xe9400000, 0xff500000,
3182 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3184 0xe9500000, 0xff500000,
3185 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3187 0xe8600000, 0xff700000,
3188 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3190 0xe8700000, 0xff700000,
3191 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3193 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
3194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3195 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 3196
3197 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 3198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3199 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
3200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3201 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
3202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3203 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
3204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3205 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 3206
8f06b2d8 3207 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 3208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3209 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
3210 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3211 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 3212
3213 /* Fallback. */
823d2571
TG		 3214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3215 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3216 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 3217};
ff4a8d2b 3218
8f06b2d8
PB		 3219static const char *const arm_conditional[] =
3220{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 3221 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 3222
3223static const char *const arm_fp_const[] =
3224{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3225
3226static const char *const arm_shift[] =
3227{"lsl", "lsr", "asr", "ror"};
3228
3229typedef struct
3230{
3231 const char *name;
3232 const char *description;
3233 const char *reg_names[16];
3234}
3235arm_regname;
3236
3237static const arm_regname regnames[] =
3238{
65b48a81 3239 { "reg-names-raw", N_("Select raw register names"),
8f06b2d8 3240 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
65b48a81 3241 { "reg-names-gcc", N_("Select register names used by GCC"),
8f06b2d8 3242 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 3243 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
8f06b2d8 3244 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65b48a81
PB		 3245 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
3246 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
3247 { "reg-names-apcs", N_("Select register names used in the APCS"),
8f06b2d8 3248 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 3249 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
8f06b2d8 3250 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
65b48a81
PB		 3251 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
3252 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
8f06b2d8
PB		 3253};
3254
3255static const char *const iwmmxt_wwnames[] =
3256{"b", "h", "w", "d"};
3257
3258static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 3259{"b", "bus", "bc", "bss",
3260 "h", "hus", "hc", "hss",
3261 "w", "wus", "wc", "wss",
3262 "d", "dus", "dc", "dss"
8f06b2d8
PB		 3263};
3264
3265static const char *const iwmmxt_regnames[] =
3266{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3267 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3268};
3269
3270static const char *const iwmmxt_cregnames[] =
3271{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3272 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3273};
3274
3275/* Default to GCC register name set. */
3276static unsigned int regname_selected = 1;
3277
65b48a81 3278#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
8f06b2d8
PB		 3279#define arm_regnames regnames[regname_selected].reg_names
3280
3281static bfd_boolean force_thumb = FALSE;
3282
c22aaad1
PB		 3283/* Current IT instruction state. This contains the same state as the IT
3284 bits in the CPSR. */
3285static unsigned int ifthen_state;
3286/* IT state for the next instruction. */
3287static unsigned int ifthen_next_state;
3288/* The address of the insn for which the IT state is valid. */
3289static bfd_vma ifthen_address;
3290#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 3291/* Indicates that the current Conditional state is unconditional or outside
3292 an IT block. */
3293#define COND_UNCOND 16
c22aaad1 3294
8f06b2d8
PB		 3295\f
3296/* Functions. */
8f06b2d8 3297
16980d0b
JB		 3298/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3299 Returns pointer to following character of the format string and
3300 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 3301 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 3302
3303static const char *
fe56b6ce
NC		 3304arm_decode_bitfield (const char *ptr,
3305 unsigned long insn,
3306 unsigned long *valuep,
3307 int *widthp)
16980d0b
JB		 3308{
3309 unsigned long value = 0;
3310 int width = 0;
43e65147
L		 3311
3312 do
16980d0b
JB		 3313 {
3314 int start, end;
3315 int bits;
3316
3317 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3318 start = start * 10 + *ptr - '0';
3319 if (*ptr == '-')
3320 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3321 end = end * 10 + *ptr - '0';
3322 else
3323 end = start;
3324 bits = end - start;
3325 if (bits < 0)
3326 abort ();
3327 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3328 width += bits + 1;
3329 }
3330 while (*ptr++ == ',');
3331 *valuep = value;
3332 if (widthp)
3333 *widthp = width;
3334 return ptr - 1;
3335}
3336
8f06b2d8 3337static void
37b37b2d 3338arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 3339 bfd_boolean print_shift)
8f06b2d8
PB		 3340{
3341 func (stream, "%s", arm_regnames[given & 0xf]);
3342
3343 if ((given & 0xff0) != 0)
3344 {
3345 if ((given & 0x10) == 0)
3346 {
3347 int amount = (given & 0xf80) >> 7;
3348 int shift = (given & 0x60) >> 5;
3349
3350 if (amount == 0)
3351 {
3352 if (shift == 3)
3353 {
3354 func (stream, ", rrx");
3355 return;
3356 }
3357
3358 amount = 32;
3359 }
3360
37b37b2d
RE		 3361 if (print_shift)
3362 func (stream, ", %s #%d", arm_shift[shift], amount);
3363 else
3364 func (stream, ", #%d", amount);
8f06b2d8 3365 }
74bdfecf 3366 else if ((given & 0x80) == 0x80)
aefd8a40 3367 func (stream, "\t; <illegal shifter operand>");
37b37b2d 3368 else if (print_shift)
8f06b2d8
PB		 3369 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3370 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 3371 else
3372 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 3373 }
3374}
3375
c1e26897
NC		 3376#define W_BIT 21
3377#define I_BIT 22
3378#define U_BIT 23
3379#define P_BIT 24
3380
3381#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
3382#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
3383#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
3384#define PRE_BIT_SET (given & (1 << P_BIT))
3385
8f06b2d8
PB		 3386/* Print one coprocessor instruction on INFO->STREAM.
3387 Return TRUE if the instuction matched, FALSE if this is not a
3388 recognised coprocessor instruction. */
3389
3390static bfd_boolean
fe56b6ce
NC		 3391print_insn_coprocessor (bfd_vma pc,
3392 struct disassemble_info *info,
3393 long given,
8f06b2d8
PB		 3394 bfd_boolean thumb)
3395{
3396 const struct opcode32 *insn;
3397 void *stream = info->stream;
3398 fprintf_ftype func = info->fprintf_func;
3399 unsigned long mask;
2edcd244 3400 unsigned long value = 0;
c22aaad1 3401 int cond;
8afc7bea 3402 int cp_num;
823d2571
TG		 3403 struct arm_private_data *private_data = info->private_data;
3404 arm_feature_set allowed_arches = ARM_ARCH_NONE;
3405
5b616bef 3406 allowed_arches = private_data->features;
8f06b2d8
PB		 3407
3408 for (insn = coprocessor_opcodes; insn->assembler; insn++)
3409 {
ff4a8d2b
NC		 3410 unsigned long u_reg = 16;
3411 bfd_boolean is_unpredictable = FALSE;
05413229 3412 signed long value_in_comment = 0;
0313a2b8
NC		 3413 const char *c;
3414
823d2571 3415 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 3416 switch (insn->value)
3417 {
3418 case SENTINEL_IWMMXT_START:
3419 if (info->mach != bfd_mach_arm_XScale
3420 && info->mach != bfd_mach_arm_iWMMXt
3421 && info->mach != bfd_mach_arm_iWMMXt2)
3422 do
3423 insn++;
823d2571
TG		 3424 while ((! ARM_FEATURE_ZERO (insn->arch))
3425 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 3426 continue;
3427
3428 case SENTINEL_IWMMXT_END:
3429 continue;
3430
3431 case SENTINEL_GENERIC_START:
5b616bef 3432 allowed_arches = private_data->features;
05413229
NC		 3433 continue;
3434
3435 default:
3436 abort ();
3437 }
8f06b2d8
PB		 3438
3439 mask = insn->mask;
3440 value = insn->value;
8afc7bea
RL		 3441 cp_num = (given >> 8) & 0xf;
3442
8f06b2d8
PB		 3443 if (thumb)
3444 {
3445 /* The high 4 bits are 0xe for Arm conditional instructions, and
3446 0xe for arm unconditional instructions. The rest of the
3447 encoding is the same. */
3448 mask |= 0xf0000000;
3449 value |= 0xe0000000;
c22aaad1
PB		 3450 if (ifthen_state)
3451 cond = IFTHEN_COND;
3452 else
e2efe87d 3453 cond = COND_UNCOND;
8f06b2d8
PB		 3454 }
3455 else
3456 {
3457 /* Only match unconditional instuctions against unconditional
3458 patterns. */
3459 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 3460 {
3461 mask |= 0xf0000000;
e2efe87d 3462 cond = COND_UNCOND;
c22aaad1
PB		 3463 }
3464 else
3465 {
3466 cond = (given >> 28) & 0xf;
3467 if (cond == 0xe)
e2efe87d 3468 cond = COND_UNCOND;
c22aaad1 3469 }
8f06b2d8 3470 }
823d2571 3471
0313a2b8
NC		 3472 if ((given & mask) != value)
3473 continue;
8f06b2d8 3474
823d2571 3475 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 3476 continue;
3477
8afc7bea
RL		 3478 if (insn->value == 0xfe000010 /* mcr2 */
3479 || insn->value == 0xfe100010 /* mrc2 */
3480 || insn->value == 0xfc100000 /* ldc2 */
3481 || insn->value == 0xfc000000) /* stc2 */
3482 {
b0c11777 3483 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea
RL		 3484 is_unpredictable = TRUE;
3485 }
3486 else if (insn->value == 0x0e000000 /* cdp */
3487 || insn->value == 0xfe000000 /* cdp2 */
3488 || insn->value == 0x0e000010 /* mcr */
3489 || insn->value == 0x0e100010 /* mrc */
3490 || insn->value == 0x0c100000 /* ldc */
3491 || insn->value == 0x0c000000) /* stc */
3492 {
3493 /* Floating-point instructions. */
b0c11777 3494 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea
RL		 3495 continue;
3496 }
3497
0313a2b8
NC		 3498 for (c = insn->assembler; *c; c++)
3499 {
3500 if (*c == '%')
8f06b2d8 3501 {
0313a2b8 3502 switch (*++c)
8f06b2d8 3503 {
0313a2b8
NC		 3504 case '%':
3505 func (stream, "%%");
3506 break;
3507
3508 case 'A':
05413229 3509 {
79862e45 3510 int rn = (given >> 16) & 0xf;
b0c11777 3511 bfd_vma offset = given & 0xff;
0313a2b8 3512
05413229 3513 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 3514
79862e45
DJ		 3515 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
3516 {
3517 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 3518 if (cp_num == 9)
3519 /* vldr.16/vstr.16 will shift the address
3520 left by 1 bit only. */
3521 offset = offset * 2;
3522 else
3523 offset = offset * 4;
3524
79862e45
DJ		 3525 if (NEGATIVE_BIT_SET)
3526 offset = - offset;
3527 if (rn != 15)
3528 value_in_comment = offset;
3529 }
3530
c1e26897 3531 if (PRE_BIT_SET)
05413229
NC		 3532 {
3533 if (offset)
fe56b6ce 3534 func (stream, ", #%d]%s",
d908c8af 3535 (int) offset,
c1e26897 3536 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 3537 else if (NEGATIVE_BIT_SET)
3538 func (stream, ", #-0]");
05413229
NC		 3539 else
3540 func (stream, "]");
3541 }
3542 else
3543 {
0313a2b8 3544 func (stream, "]");
8f06b2d8 3545
c1e26897 3546 if (WRITEBACK_BIT_SET)
05413229
NC		 3547 {
3548 if (offset)
d908c8af 3549 func (stream, ", #%d", (int) offset);
26d97720
NS		 3550 else if (NEGATIVE_BIT_SET)
3551 func (stream, ", #-0");
05413229
NC		 3552 }
3553 else
fe56b6ce 3554 {
26d97720
NS		 3555 func (stream, ", {%s%d}",
3556 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 3557 (int) offset);
fe56b6ce
NC		 3558 value_in_comment = offset;
3559 }
05413229 3560 }
79862e45
DJ		 3561 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
3562 {
3563 func (stream, "\t; ");
6844b2c2
MGD		 3564 /* For unaligned PCs, apply off-by-alignment
3565 correction. */
43e65147 3566 info->print_address_func (offset + pc
6844b2c2
MGD		 3567 + info->bytes_per_chunk * 2
3568 - (pc & 3),
3569 info);
79862e45 3570 }
05413229 3571 }
0313a2b8 3572 break;
8f06b2d8 3573
0313a2b8
NC		 3574 case 'B':
3575 {
3576 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
3577 int offset = (given >> 1) & 0x3f;
3578
3579 if (offset == 1)
3580 func (stream, "{d%d}", regno);
3581 else if (regno + offset > 32)
3582 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
3583 else
3584 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
3585 }
3586 break;
8f06b2d8 3587
e2efe87d
MGD		 3588 case 'u':
3589 if (cond != COND_UNCOND)
3590 is_unpredictable = TRUE;
3591
3592 /* Fall through. */
0313a2b8 3593 case 'c':
b0c11777
RL		 3594 if (cond != COND_UNCOND && cp_num == 9)
3595 is_unpredictable = TRUE;
3596
0313a2b8
NC		 3597 func (stream, "%s", arm_conditional[cond]);
3598 break;
8f06b2d8 3599
0313a2b8
NC		 3600 case 'I':
3601 /* Print a Cirrus/DSP shift immediate. */
3602 /* Immediates are 7bit signed ints with bits 0..3 in
3603 bits 0..3 of opcode and bits 4..6 in bits 5..7
3604 of opcode. */
3605 {
3606 int imm;
8f06b2d8 3607
0313a2b8 3608 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 3609
0313a2b8
NC		 3610 /* Is ``imm'' a negative number? */
3611 if (imm & 0x40)
24b4cf66 3612 imm -= 0x80;
8f06b2d8 3613
0313a2b8
NC		 3614 func (stream, "%d", imm);
3615 }
3616
3617 break;
8f06b2d8 3618
0313a2b8
NC		 3619 case 'F':
3620 switch (given & 0x00408000)
3621 {
3622 case 0:
3623 func (stream, "4");
3624 break;
3625 case 0x8000:
3626 func (stream, "1");
3627 break;
3628 case 0x00400000:
3629 func (stream, "2");
8f06b2d8 3630 break;
0313a2b8
NC		 3631 default:
3632 func (stream, "3");
3633 }
3634 break;
8f06b2d8 3635
0313a2b8
NC		 3636 case 'P':
3637 switch (given & 0x00080080)
3638 {
3639 case 0:
3640 func (stream, "s");
3641 break;
3642 case 0x80:
3643 func (stream, "d");
3644 break;
3645 case 0x00080000:
3646 func (stream, "e");
3647 break;
3648 default:
3649 func (stream, _("<illegal precision>"));
8f06b2d8 3650 break;
0313a2b8
NC		 3651 }
3652 break;
8f06b2d8 3653
0313a2b8
NC		 3654 case 'Q':
3655 switch (given & 0x00408000)
3656 {
3657 case 0:
3658 func (stream, "s");
8f06b2d8 3659 break;
0313a2b8
NC		 3660 case 0x8000:
3661 func (stream, "d");
8f06b2d8 3662 break;
0313a2b8
NC		 3663 case 0x00400000:
3664 func (stream, "e");
3665 break;
3666 default:
3667 func (stream, "p");
8f06b2d8 3668 break;
0313a2b8
NC		 3669 }
3670 break;
8f06b2d8 3671
0313a2b8
NC		 3672 case 'R':
3673 switch (given & 0x60)
3674 {
3675 case 0:
3676 break;
3677 case 0x20:
3678 func (stream, "p");
3679 break;
3680 case 0x40:
3681 func (stream, "m");
3682 break;
3683 default:
3684 func (stream, "z");
3685 break;
3686 }
3687 break;
16980d0b 3688
0313a2b8
NC		 3689 case '0': case '1': case '2': case '3': case '4':
3690 case '5': case '6': case '7': case '8': case '9':
3691 {
3692 int width;
8f06b2d8 3693
0313a2b8 3694 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 3695
0313a2b8
NC		 3696 switch (*c)
3697 {
ff4a8d2b
NC		 3698 case 'R':
3699 if (value == 15)
3700 is_unpredictable = TRUE;
3701 /* Fall through. */
0313a2b8 3702 case 'r':
ff4a8d2b
NC		 3703 if (c[1] == 'u')
3704 {
3705 /* Eat the 'u' character. */
3706 ++ c;
3707
3708 if (u_reg == value)
3709 is_unpredictable = TRUE;
3710 u_reg = value;
3711 }
0313a2b8
NC		 3712 func (stream, "%s", arm_regnames[value]);
3713 break;
c28eeff2
SN		 3714 case 'V':
3715 if (given & (1 << 6))
3716 goto Q;
3717 /* FALLTHROUGH */
0313a2b8
NC		 3718 case 'D':
3719 func (stream, "d%ld", value);
3720 break;
3721 case 'Q':
c28eeff2 3722 Q:
0313a2b8
NC		 3723 if (value & 1)
3724 func (stream, "<illegal reg q%ld.5>", value >> 1);
3725 else
3726 func (stream, "q%ld", value >> 1);
3727 break;
3728 case 'd':
3729 func (stream, "%ld", value);
05413229 3730 value_in_comment = value;
0313a2b8 3731 break;
6f1c2142
AM		 3732 case 'E':
3733 {
3734 /* Converts immediate 8 bit back to float value. */
3735 unsigned floatVal = (value & 0x80) << 24
3736 | (value & 0x3F) << 19
3737 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
3738
3739 /* Quarter float have a maximum value of 31.0.
3740 Get floating point value multiplied by 1e7.
3741 The maximum value stays in limit of a 32-bit int. */
3742 unsigned decVal =
3743 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
3744 (16 + (value & 0xF));
3745
3746 if (!(decVal % 1000000))
3747 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
3748 floatVal, value & 0x80 ? '-' : ' ',
3749 decVal / 10000000,
3750 decVal % 10000000 / 1000000);
3751 else if (!(decVal % 10000))
3752 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
3753 floatVal, value & 0x80 ? '-' : ' ',
3754 decVal / 10000000,
3755 decVal % 10000000 / 10000);
3756 else
3757 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
3758 floatVal, value & 0x80 ? '-' : ' ',
3759 decVal / 10000000, decVal % 10000000);
3760 break;
3761 }
0313a2b8
NC		 3762 case 'k':
3763 {
3764 int from = (given & (1 << 7)) ? 32 : 16;
3765 func (stream, "%ld", from - value);
3766 }
3767 break;
8f06b2d8 3768
0313a2b8
NC		 3769 case 'f':
3770 if (value > 7)
3771 func (stream, "#%s", arm_fp_const[value & 7]);
3772 else
3773 func (stream, "f%ld", value);
3774 break;
4146fd53 3775
0313a2b8
NC		 3776 case 'w':
3777 if (width == 2)
3778 func (stream, "%s", iwmmxt_wwnames[value]);
3779 else
3780 func (stream, "%s", iwmmxt_wwssnames[value]);
3781 break;
4146fd53 3782
0313a2b8
NC		 3783 case 'g':
3784 func (stream, "%s", iwmmxt_regnames[value]);
3785 break;
3786 case 'G':
3787 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 3788 break;
8f06b2d8 3789
0313a2b8 3790 case 'x':
d1aaab3c 3791 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 3792 break;
8f06b2d8 3793
33399f07
MGD		 3794 case 'c':
3795 switch (value)
3796 {
3797 case 0:
3798 func (stream, "eq");
3799 break;
3800
3801 case 1:
3802 func (stream, "vs");
3803 break;
3804
3805 case 2:
3806 func (stream, "ge");
3807 break;
3808
3809 case 3:
3810 func (stream, "gt");
3811 break;
3812
3813 default:
3814 func (stream, "??");
3815 break;
3816 }
3817 break;
3818
0313a2b8
NC		 3819 case '`':
3820 c++;
3821 if (value == 0)
3822 func (stream, "%c", *c);
3823 break;
3824 case '\'':
3825 c++;
3826 if (value == ((1ul << width) - 1))
3827 func (stream, "%c", *c);
3828 break;
3829 case '?':
fe56b6ce 3830 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 3831 c += 1 << width;
3832 break;
3833 default:
3834 abort ();
3835 }
3836 break;
8f06b2d8 3837
0313a2b8
NC		 3838 case 'y':
3839 case 'z':
3840 {
3841 int single = *c++ == 'y';
3842 int regno;
3843
3844 switch (*c)
3845 {
3846 case '4': /* Sm pair */
3847 case '0': /* Sm, Dm */
3848 regno = given & 0x0000000f;
3849 if (single)
3850 {
3851 regno <<= 1;
3852 regno += (given >> 5) & 1;
16980d0b 3853 }
0313a2b8
NC		 3854 else
3855 regno += ((given >> 5) & 1) << 4;
3856 break;
8f06b2d8 3857
0313a2b8
NC		 3858 case '1': /* Sd, Dd */
3859 regno = (given >> 12) & 0x0000000f;
3860 if (single)
3861 {
3862 regno <<= 1;
3863 regno += (given >> 22) & 1;
3864 }
3865 else
3866 regno += ((given >> 22) & 1) << 4;
3867 break;
8f06b2d8 3868
0313a2b8
NC		 3869 case '2': /* Sn, Dn */
3870 regno = (given >> 16) & 0x0000000f;
3871 if (single)
8f06b2d8 3872 {
0313a2b8
NC		 3873 regno <<= 1;
3874 regno += (given >> 7) & 1;
8f06b2d8 3875 }
0313a2b8
NC		 3876 else
3877 regno += ((given >> 7) & 1) << 4;
3878 break;
7df76b80 3879
0313a2b8
NC		 3880 case '3': /* List */
3881 func (stream, "{");
3882 regno = (given >> 12) & 0x0000000f;
3883 if (single)
3884 {
3885 regno <<= 1;
3886 regno += (given >> 22) & 1;
3887 }
3888 else
3889 regno += ((given >> 22) & 1) << 4;
3890 break;
a7f8487e 3891
0313a2b8
NC		 3892 default:
3893 abort ();
8f06b2d8 3894 }
a7f8487e 3895
0313a2b8
NC		 3896 func (stream, "%c%d", single ? 's' : 'd', regno);
3897
3898 if (*c == '3')
8f06b2d8 3899 {
0313a2b8 3900 int count = given & 0xff;
a7f8487e 3901
0313a2b8
NC		 3902 if (single == 0)
3903 count >>= 1;
b34976b6 3904
0313a2b8 3905 if (--count)
8f06b2d8 3906 {
0313a2b8
NC		 3907 func (stream, "-%c%d",
3908 single ? 's' : 'd',
3909 regno + count);
8f06b2d8 3910 }
0313a2b8
NC		 3911
3912 func (stream, "}");
8f06b2d8 3913 }
0313a2b8
NC		 3914 else if (*c == '4')
3915 func (stream, ", %c%d", single ? 's' : 'd',
3916 regno + 1);
3917 }
3918 break;
3919
3920 case 'L':
3921 switch (given & 0x00400100)
3922 {
3923 case 0x00000000: func (stream, "b"); break;
3924 case 0x00400000: func (stream, "h"); break;
3925 case 0x00000100: func (stream, "w"); break;
3926 case 0x00400100: func (stream, "d"); break;
3927 default:
8f06b2d8 3928 break;
0313a2b8
NC		 3929 }
3930 break;
b34976b6 3931
0313a2b8
NC		 3932 case 'Z':
3933 {
0313a2b8
NC		 3934 /* given (20, 23) | given (0, 3) */
3935 value = ((given >> 16) & 0xf0) | (given & 0xf);
d908c8af 3936 func (stream, "%d", (int) value);
0313a2b8
NC		 3937 }
3938 break;
2d447fca 3939
0313a2b8
NC		 3940 case 'l':
3941 /* This is like the 'A' operator, except that if
3942 the width field "M" is zero, then the offset is
3943 *not* multiplied by four. */
3944 {
3945 int offset = given & 0xff;
3946 int multiplier = (given & 0x00000100) ? 4 : 1;
3947
3948 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3949
05413229
NC		 3950 if (multiplier > 1)
3951 {
3952 value_in_comment = offset * multiplier;
c1e26897 3953 if (NEGATIVE_BIT_SET)
05413229
NC		 3954 value_in_comment = - value_in_comment;
3955 }
3956
0313a2b8
NC		 3957 if (offset)
3958 {
c1e26897 3959 if (PRE_BIT_SET)
0313a2b8 3960 func (stream, ", #%s%d]%s",
c1e26897 3961 NEGATIVE_BIT_SET ? "-" : "",
0313a2b8 3962 offset * multiplier,
c1e26897 3963 WRITEBACK_BIT_SET ? "!" : "");
0313a2b8
NC		 3964 else
3965 func (stream, "], #%s%d",
c1e26897 3966 NEGATIVE_BIT_SET ? "-" : "",
0313a2b8 3967 offset * multiplier);
2d447fca 3968 }
0313a2b8
NC		 3969 else
3970 func (stream, "]");
3971 }
3972 break;
3973
3974 case 'r':
3975 {
3976 int imm4 = (given >> 4) & 0xf;
c1e26897
NC		 3977 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
3978 int ubit = ! NEGATIVE_BIT_SET;
0313a2b8
NC		 3979 const char *rm = arm_regnames [given & 0xf];
3980 const char *rn = arm_regnames [(given >> 16) & 0xf];
2d447fca 3981
0313a2b8 3982 switch (puw_bits)
2d447fca 3983 {
0313a2b8
NC		 3984 case 1:
3985 case 3:
3986 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
3987 if (imm4)
3988 func (stream, ", lsl #%d", imm4);
3989 break;
3990
3991 case 4:
3992 case 5:
3993 case 6:
3994 case 7:
3995 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
3996 if (imm4 > 0)
3997 func (stream, ", lsl #%d", imm4);
3998 func (stream, "]");
3999 if (puw_bits == 5 || puw_bits == 7)
4000 func (stream, "!");
4001 break;
4002
4003 default:
4004 func (stream, "INVALID");
2d447fca 4005 }
0313a2b8
NC		 4006 }
4007 break;
2d447fca 4008
0313a2b8
NC		 4009 case 'i':
4010 {
4011 long imm5;
4012 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
4013 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
8f06b2d8 4014 }
0313a2b8
NC		 4015 break;
4016
4017 default:
4018 abort ();
4019 }
252b5132 4020 }
252b5132 4021 }
0313a2b8
NC		 4022 else
4023 func (stream, "%c", *c);
252b5132 4024 }
05413229
NC		 4025
4026 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 4027 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 4028
ff4a8d2b
NC		 4029 if (is_unpredictable)
4030 func (stream, UNPREDICTABLE_INSTRUCTION);
4031
0313a2b8 4032 return TRUE;
252b5132 4033 }
8f06b2d8 4034 return FALSE;
252b5132
RH		 4035}
4036
05413229
NC		 4037/* Decodes and prints ARM addressing modes. Returns the offset
4038 used in the address, if any, if it is worthwhile printing the
4039 offset as a hexadecimal value in a comment at the end of the
4040 line of disassembly. */
4041
4042static signed long
62b3e311
PB		 4043print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
4044{
4045 void *stream = info->stream;
4046 fprintf_ftype func = info->fprintf_func;
f8b960bc 4047 bfd_vma offset = 0;
62b3e311
PB		 4048
4049 if (((given & 0x000f0000) == 0x000f0000)
4050 && ((given & 0x02000000) == 0))
4051 {
05413229 4052 offset = given & 0xfff;
62b3e311
PB		 4053
4054 func (stream, "[pc");
4055
c1e26897 4056 if (PRE_BIT_SET)
62b3e311 4057 {
26d97720
NS		 4058 /* Pre-indexed. Elide offset of positive zero when
4059 non-writeback. */
4060 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 4061 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 4062
4063 if (NEGATIVE_BIT_SET)
4064 offset = -offset;
62b3e311
PB		 4065
4066 offset += pc + 8;
4067
4068 /* Cope with the possibility of write-back
4069 being used. Probably a very dangerous thing
4070 for the programmer to do, but who are we to
4071 argue ? */
26d97720 4072 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 4073 }
c1e26897 4074 else /* Post indexed. */
62b3e311 4075 {
d908c8af 4076 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 4077
c1e26897 4078 /* Ie ignore the offset. */
62b3e311
PB		 4079 offset = pc + 8;
4080 }
4081
4082 func (stream, "\t; ");
4083 info->print_address_func (offset, info);
05413229 4084 offset = 0;
62b3e311
PB		 4085 }
4086 else
4087 {
4088 func (stream, "[%s",
4089 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 4090
4091 if (PRE_BIT_SET)
62b3e311
PB		 4092 {
4093 if ((given & 0x02000000) == 0)
4094 {
26d97720 4095 /* Elide offset of positive zero when non-writeback. */
05413229 4096 offset = given & 0xfff;
26d97720 4097 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 4098 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 4099 }
4100 else
4101 {
26d97720 4102 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 4103 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 4104 }
4105
4106 func (stream, "]%s",
c1e26897 4107 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 4108 }
4109 else
4110 {
4111 if ((given & 0x02000000) == 0)
4112 {
26d97720 4113 /* Always show offset. */
05413229 4114 offset = given & 0xfff;
26d97720 4115 func (stream, "], #%s%d",
d908c8af 4116 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 4117 }
4118 else
4119 {
4120 func (stream, "], %s",
c1e26897 4121 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 4122 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 4123 }
4124 }
84919466
MR		 4125 if (NEGATIVE_BIT_SET)
4126 offset = -offset;
62b3e311 4127 }
05413229
NC		 4128
4129 return (signed long) offset;
62b3e311
PB		 4130}
4131
16980d0b
JB		 4132/* Print one neon instruction on INFO->STREAM.
4133 Return TRUE if the instuction matched, FALSE if this is not a
4134 recognised neon instruction. */
4135
4136static bfd_boolean
4137print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
4138{
4139 const struct opcode32 *insn;
4140 void *stream = info->stream;
4141 fprintf_ftype func = info->fprintf_func;
4142
4143 if (thumb)
4144 {
4145 if ((given & 0xef000000) == 0xef000000)
4146 {
0313a2b8 4147 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 4148 unsigned long bit28 = given & (1 << 28);
4149
4150 given &= 0x00ffffff;
4151 if (bit28)
4152 given |= 0xf3000000;
4153 else
4154 given |= 0xf2000000;
4155 }
4156 else if ((given & 0xff000000) == 0xf9000000)
4157 given ^= 0xf9000000 ^ 0xf4000000;
4158 else
4159 return FALSE;
4160 }
43e65147 4161
16980d0b
JB		 4162 for (insn = neon_opcodes; insn->assembler; insn++)
4163 {
4164 if ((given & insn->mask) == insn->value)
4165 {
05413229 4166 signed long value_in_comment = 0;
e2efe87d 4167 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 4168 const char *c;
4169
4170 for (c = insn->assembler; *c; c++)
4171 {
4172 if (*c == '%')
4173 {
4174 switch (*++c)
4175 {
4176 case '%':
4177 func (stream, "%%");
4178 break;
4179
e2efe87d
MGD		 4180 case 'u':
4181 if (thumb && ifthen_state)
4182 is_unpredictable = TRUE;
4183
4184 /* Fall through. */
c22aaad1
PB		 4185 case 'c':
4186 if (thumb && ifthen_state)
4187 func (stream, "%s", arm_conditional[IFTHEN_COND]);
4188 break;
4189
16980d0b
JB		 4190 case 'A':
4191 {
43e65147 4192 static const unsigned char enc[16] =
16980d0b
JB		 4193 {
4194 0x4, 0x14, /* st4 0,1 */
4195 0x4, /* st1 2 */
4196 0x4, /* st2 3 */
4197 0x3, /* st3 4 */
4198 0x13, /* st3 5 */
4199 0x3, /* st1 6 */
4200 0x1, /* st1 7 */
4201 0x2, /* st2 8 */
4202 0x12, /* st2 9 */
4203 0x2, /* st1 10 */
4204 0, 0, 0, 0, 0
4205 };
4206 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4207 int rn = ((given >> 16) & 0xf);
4208 int rm = ((given >> 0) & 0xf);
4209 int align = ((given >> 4) & 0x3);
4210 int type = ((given >> 8) & 0xf);
4211 int n = enc[type] & 0xf;
4212 int stride = (enc[type] >> 4) + 1;
4213 int ix;
43e65147 4214
16980d0b
JB		 4215 func (stream, "{");
4216 if (stride > 1)
4217 for (ix = 0; ix != n; ix++)
4218 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
4219 else if (n == 1)
4220 func (stream, "d%d", rd);
4221 else
4222 func (stream, "d%d-d%d", rd, rd + n - 1);
4223 func (stream, "}, [%s", arm_regnames[rn]);
4224 if (align)
8e560766 4225 func (stream, " :%d", 32 << align);
16980d0b
JB		 4226 func (stream, "]");
4227 if (rm == 0xd)
4228 func (stream, "!");
4229 else if (rm != 0xf)
4230 func (stream, ", %s", arm_regnames[rm]);
4231 }
4232 break;
43e65147 4233
16980d0b
JB		 4234 case 'B':
4235 {
4236 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4237 int rn = ((given >> 16) & 0xf);
4238 int rm = ((given >> 0) & 0xf);
4239 int idx_align = ((given >> 4) & 0xf);
4240 int align = 0;
4241 int size = ((given >> 10) & 0x3);
4242 int idx = idx_align >> (size + 1);
4243 int length = ((given >> 8) & 3) + 1;
4244 int stride = 1;
4245 int i;
4246
4247 if (length > 1 && size > 0)
4248 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 4249
16980d0b
JB		 4250 switch (length)
4251 {
4252 case 1:
4253 {
4254 int amask = (1 << size) - 1;
4255 if ((idx_align & (1 << size)) != 0)
4256 return FALSE;
4257 if (size > 0)
4258 {
4259 if ((idx_align & amask) == amask)
4260 align = 8 << size;
4261 else if ((idx_align & amask) != 0)
4262 return FALSE;
4263 }
4264 }
4265 break;
43e65147 4266
16980d0b
JB		 4267 case 2:
4268 if (size == 2 && (idx_align & 2) != 0)
4269 return FALSE;
4270 align = (idx_align & 1) ? 16 << size : 0;
4271 break;
43e65147 4272
16980d0b
JB		 4273 case 3:
4274 if ((size == 2 && (idx_align & 3) != 0)
4275 || (idx_align & 1) != 0)
4276 return FALSE;
4277 break;
43e65147 4278
16980d0b
JB		 4279 case 4:
4280 if (size == 2)
4281 {
4282 if ((idx_align & 3) == 3)
4283 return FALSE;
4284 align = (idx_align & 3) * 64;
4285 }
4286 else
4287 align = (idx_align & 1) ? 32 << size : 0;
4288 break;
43e65147 4289
16980d0b
JB		 4290 default:
4291 abort ();
4292 }
43e65147 4293
16980d0b
JB		 4294 func (stream, "{");
4295 for (i = 0; i < length; i++)
4296 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
4297 rd + i * stride, idx);
4298 func (stream, "}, [%s", arm_regnames[rn]);
4299 if (align)
8e560766 4300 func (stream, " :%d", align);
16980d0b
JB		 4301 func (stream, "]");
4302 if (rm == 0xd)
4303 func (stream, "!");
4304 else if (rm != 0xf)
4305 func (stream, ", %s", arm_regnames[rm]);
4306 }
4307 break;
43e65147 4308
16980d0b
JB		 4309 case 'C':
4310 {
4311 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4312 int rn = ((given >> 16) & 0xf);
4313 int rm = ((given >> 0) & 0xf);
4314 int align = ((given >> 4) & 0x1);
4315 int size = ((given >> 6) & 0x3);
4316 int type = ((given >> 8) & 0x3);
4317 int n = type + 1;
4318 int stride = ((given >> 5) & 0x1);
4319 int ix;
43e65147 4320
16980d0b
JB		 4321 if (stride && (n == 1))
4322 n++;
4323 else
4324 stride++;
43e65147 4325
16980d0b
JB		 4326 func (stream, "{");
4327 if (stride > 1)
4328 for (ix = 0; ix != n; ix++)
4329 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
4330 else if (n == 1)
4331 func (stream, "d%d[]", rd);
4332 else
4333 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
4334 func (stream, "}, [%s", arm_regnames[rn]);
4335 if (align)
4336 {
91d6fa6a 4337 align = (8 * (type + 1)) << size;
16980d0b
JB		 4338 if (type == 3)
4339 align = (size > 1) ? align >> 1 : align;
4340 if (type == 2 || (type == 0 && !size))
8e560766 4341 func (stream, " :<bad align %d>", align);
16980d0b 4342 else
8e560766 4343 func (stream, " :%d", align);
16980d0b
JB		 4344 }
4345 func (stream, "]");
4346 if (rm == 0xd)
4347 func (stream, "!");
4348 else if (rm != 0xf)
4349 func (stream, ", %s", arm_regnames[rm]);
4350 }
4351 break;
43e65147 4352
16980d0b
JB		 4353 case 'D':
4354 {
4355 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
4356 int size = (given >> 20) & 3;
4357 int reg = raw_reg & ((4 << size) - 1);
4358 int ix = raw_reg >> size >> 2;
43e65147 4359
16980d0b
JB		 4360 func (stream, "d%d[%d]", reg, ix);
4361 }
4362 break;
43e65147 4363
16980d0b 4364 case 'E':
fe56b6ce 4365 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 4366 {
4367 int bits = 0;
4368 int cmode = (given >> 8) & 0xf;
4369 int op = (given >> 5) & 0x1;
4370 unsigned long value = 0, hival = 0;
4371 unsigned shift;
4372 int size = 0;
0dbde4cf 4373 int isfloat = 0;
43e65147 4374
16980d0b
JB		 4375 bits |= ((given >> 24) & 1) << 7;
4376 bits |= ((given >> 16) & 7) << 4;
4377 bits |= ((given >> 0) & 15) << 0;
43e65147 4378
16980d0b
JB		 4379 if (cmode < 8)
4380 {
4381 shift = (cmode >> 1) & 3;
fe56b6ce 4382 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4383 size = 32;
4384 }
4385 else if (cmode < 12)
4386 {
4387 shift = (cmode >> 1) & 1;
fe56b6ce 4388 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4389 size = 16;
4390 }
4391 else if (cmode < 14)
4392 {
4393 shift = (cmode & 1) + 1;
fe56b6ce 4394 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4395 value |= (1ul << (8 * shift)) - 1;
4396 size = 32;
4397 }
4398 else if (cmode == 14)
4399 {
4400 if (op)
4401 {
fe56b6ce 4402 /* Bit replication into bytes. */
16980d0b
JB		 4403 int ix;
4404 unsigned long mask;
43e65147 4405
16980d0b
JB		 4406 value = 0;
4407 hival = 0;
4408 for (ix = 7; ix >= 0; ix--)
4409 {
4410 mask = ((bits >> ix) & 1) ? 0xff : 0;
4411 if (ix <= 3)
4412 value = (value << 8) | mask;
4413 else
4414 hival = (hival << 8) | mask;
4415 }
4416 size = 64;
4417 }
4418 else
4419 {
fe56b6ce
NC		 4420 /* Byte replication. */
4421 value = (unsigned long) bits;
16980d0b
JB		 4422 size = 8;
4423 }
4424 }
4425 else if (!op)
4426 {
fe56b6ce 4427 /* Floating point encoding. */
16980d0b 4428 int tmp;
43e65147 4429
fe56b6ce
NC		 4430 value = (unsigned long) (bits & 0x7f) << 19;
4431 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 4432 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 4433 value |= (unsigned long) tmp << 24;
16980d0b 4434 size = 32;
0dbde4cf 4435 isfloat = 1;
16980d0b
JB		 4436 }
4437 else
4438 {
4439 func (stream, "<illegal constant %.8x:%x:%x>",
4440 bits, cmode, op);
4441 size = 32;
4442 break;
4443 }
4444 switch (size)
4445 {
4446 case 8:
4447 func (stream, "#%ld\t; 0x%.2lx", value, value);
4448 break;
43e65147 4449
16980d0b
JB		 4450 case 16:
4451 func (stream, "#%ld\t; 0x%.4lx", value, value);
4452 break;
4453
4454 case 32:
0dbde4cf
JB		 4455 if (isfloat)
4456 {
4457 unsigned char valbytes[4];
4458 double fvalue;
43e65147 4459
0dbde4cf
JB		 4460 /* Do this a byte at a time so we don't have to
4461 worry about the host's endianness. */
4462 valbytes[0] = value & 0xff;
4463 valbytes[1] = (value >> 8) & 0xff;
4464 valbytes[2] = (value >> 16) & 0xff;
4465 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 4466
4467 floatformat_to_double
c1e26897
NC		 4468 (& floatformat_ieee_single_little, valbytes,
4469 & fvalue);
43e65147 4470
0dbde4cf
JB		 4471 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
4472 value);
4473 }
4474 else
4e9d3b81 4475 func (stream, "#%ld\t; 0x%.8lx",
43e65147 4476 (long) (((value & 0x80000000L) != 0)
9d82ec38 4477 ? value | ~0xffffffffL : value),
c1e26897 4478 value);
16980d0b
JB		 4479 break;
4480
4481 case 64:
4482 func (stream, "#0x%.8lx%.8lx", hival, value);
4483 break;
43e65147 4484
16980d0b
JB		 4485 default:
4486 abort ();
4487 }
4488 }
4489 break;
43e65147 4490
16980d0b
JB		 4491 case 'F':
4492 {
4493 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
4494 int num = (given >> 8) & 0x3;
43e65147 4495
16980d0b
JB		 4496 if (!num)
4497 func (stream, "{d%d}", regno);
4498 else if (num + regno >= 32)
4499 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
4500 else
4501 func (stream, "{d%d-d%d}", regno, regno + num);
4502 }
4503 break;
7e8e6784 4504
16980d0b
JB		 4505
4506 case '0': case '1': case '2': case '3': case '4':
4507 case '5': case '6': case '7': case '8': case '9':
4508 {
4509 int width;
4510 unsigned long value;
4511
4512 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 4513
16980d0b
JB		 4514 switch (*c)
4515 {
4516 case 'r':
4517 func (stream, "%s", arm_regnames[value]);
4518 break;
4519 case 'd':
4520 func (stream, "%ld", value);
05413229 4521 value_in_comment = value;
16980d0b
JB		 4522 break;
4523 case 'e':
4524 func (stream, "%ld", (1ul << width) - value);
4525 break;
43e65147 4526
16980d0b
JB		 4527 case 'S':
4528 case 'T':
4529 case 'U':
05413229 4530 /* Various width encodings. */
16980d0b
JB		 4531 {
4532 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
4533 int limit;
4534 unsigned low, high;
4535
4536 c++;
4537 if (*c >= '0' && *c <= '9')
4538 limit = *c - '0';
4539 else if (*c >= 'a' && *c <= 'f')
4540 limit = *c - 'a' + 10;
4541 else
4542 abort ();
4543 low = limit >> 2;
4544 high = limit & 3;
4545
4546 if (value < low || value > high)
4547 func (stream, "<illegal width %d>", base << value);
4548 else
4549 func (stream, "%d", base << value);
4550 }
4551 break;
4552 case 'R':
4553 if (given & (1 << 6))
4554 goto Q;
4555 /* FALLTHROUGH */
4556 case 'D':
4557 func (stream, "d%ld", value);
4558 break;
4559 case 'Q':
4560 Q:
4561 if (value & 1)
4562 func (stream, "<illegal reg q%ld.5>", value >> 1);
4563 else
4564 func (stream, "q%ld", value >> 1);
4565 break;
43e65147 4566
16980d0b
JB		 4567 case '`':
4568 c++;
4569 if (value == 0)
4570 func (stream, "%c", *c);
4571 break;
4572 case '\'':
4573 c++;
4574 if (value == ((1ul << width) - 1))
4575 func (stream, "%c", *c);
4576 break;
4577 case '?':
fe56b6ce 4578 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 4579 c += 1 << width;
4580 break;
4581 default:
4582 abort ();
4583 }
4584 break;
4585
4586 default:
4587 abort ();
4588 }
4589 }
4590 }
4591 else
4592 func (stream, "%c", *c);
4593 }
05413229
NC		 4594
4595 if (value_in_comment > 32 || value_in_comment < -16)
4596 func (stream, "\t; 0x%lx", value_in_comment);
4597
e2efe87d
MGD		 4598 if (is_unpredictable)
4599 func (stream, UNPREDICTABLE_INSTRUCTION);
4600
16980d0b
JB		 4601 return TRUE;
4602 }
4603 }
4604 return FALSE;
4605}
4606
90ec0d68
MGD		 4607/* Return the name of a v7A special register. */
4608
43e65147 4609static const char *
90ec0d68
MGD		 4610banked_regname (unsigned reg)
4611{
4612 switch (reg)
4613 {
4614 case 15: return "CPSR";
43e65147 4615 case 32: return "R8_usr";
90ec0d68
MGD		 4616 case 33: return "R9_usr";
4617 case 34: return "R10_usr";
4618 case 35: return "R11_usr";
4619 case 36: return "R12_usr";
4620 case 37: return "SP_usr";
4621 case 38: return "LR_usr";
43e65147 4622 case 40: return "R8_fiq";
90ec0d68
MGD		 4623 case 41: return "R9_fiq";
4624 case 42: return "R10_fiq";
4625 case 43: return "R11_fiq";
4626 case 44: return "R12_fiq";
4627 case 45: return "SP_fiq";
4628 case 46: return "LR_fiq";
4629 case 48: return "LR_irq";
4630 case 49: return "SP_irq";
4631 case 50: return "LR_svc";
4632 case 51: return "SP_svc";
4633 case 52: return "LR_abt";
4634 case 53: return "SP_abt";
4635 case 54: return "LR_und";
4636 case 55: return "SP_und";
4637 case 60: return "LR_mon";
4638 case 61: return "SP_mon";
4639 case 62: return "ELR_hyp";
4640 case 63: return "SP_hyp";
4641 case 79: return "SPSR";
4642 case 110: return "SPSR_fiq";
4643 case 112: return "SPSR_irq";
4644 case 114: return "SPSR_svc";
4645 case 116: return "SPSR_abt";
4646 case 118: return "SPSR_und";
4647 case 124: return "SPSR_mon";
4648 case 126: return "SPSR_hyp";
4649 default: return NULL;
4650 }
4651}
4652
e797f7e0
MGD		 4653/* Return the name of the DMB/DSB option. */
4654static const char *
4655data_barrier_option (unsigned option)
4656{
4657 switch (option & 0xf)
4658 {
4659 case 0xf: return "sy";
4660 case 0xe: return "st";
4661 case 0xd: return "ld";
4662 case 0xb: return "ish";
4663 case 0xa: return "ishst";
4664 case 0x9: return "ishld";
4665 case 0x7: return "un";
4666 case 0x6: return "unst";
4667 case 0x5: return "nshld";
4668 case 0x3: return "osh";
4669 case 0x2: return "oshst";
4670 case 0x1: return "oshld";
4671 default: return NULL;
4672 }
4673}
4674
4a5329c6
ZW		 4675/* Print one ARM instruction from PC on INFO->STREAM. */
4676
4677static void
4678print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 4679{
6b5d3a4d 4680 const struct opcode32 *insn;
6a51a8a8 4681 void *stream = info->stream;
6b5d3a4d 4682 fprintf_ftype func = info->fprintf_func;
b0e28b39 4683 struct arm_private_data *private_data = info->private_data;
252b5132 4684
16980d0b
JB		 4685 if (print_insn_coprocessor (pc, info, given, FALSE))
4686 return;
4687
4688 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 4689 return;
4690
252b5132
RH		 4691 for (insn = arm_opcodes; insn->assembler; insn++)
4692 {
0313a2b8
NC		 4693 if ((given & insn->mask) != insn->value)
4694 continue;
823d2571
TG		 4695
4696 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 4697 continue;
4698
4699 /* Special case: an instruction with all bits set in the condition field
4700 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
4701 or by the catchall at the end of the table. */
4702 if ((given & 0xF0000000) != 0xF0000000
4703 || (insn->mask & 0xF0000000) == 0xF0000000
4704 || (insn->mask == 0 && insn->value == 0))
252b5132 4705 {
ff4a8d2b
NC		 4706 unsigned long u_reg = 16;
4707 unsigned long U_reg = 16;
ab8e2090 4708 bfd_boolean is_unpredictable = FALSE;
05413229 4709 signed long value_in_comment = 0;
6b5d3a4d 4710 const char *c;
b34976b6 4711
252b5132
RH		 4712 for (c = insn->assembler; *c; c++)
4713 {
4714 if (*c == '%')
4715 {
c1e26897
NC		 4716 bfd_boolean allow_unpredictable = FALSE;
4717
252b5132
RH		 4718 switch (*++c)
4719 {
4720 case '%':
4721 func (stream, "%%");
4722 break;
4723
4724 case 'a':
05413229 4725 value_in_comment = print_arm_address (pc, info, given);
62b3e311 4726 break;
252b5132 4727
62b3e311
PB		 4728 case 'P':
4729 /* Set P address bit and use normal address
4730 printing routine. */
c1e26897 4731 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 4732 break;
4733
c1e26897
NC		 4734 case 'S':
4735 allow_unpredictable = TRUE;
1a0670f3 4736 /* Fall through. */
252b5132
RH		 4737 case 's':
4738 if ((given & 0x004f0000) == 0x004f0000)
4739 {
58efb6c0 4740 /* PC relative with immediate offset. */
f8b960bc 4741 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 4742
aefd8a40
NC		 4743 if (PRE_BIT_SET)
4744 {
26d97720
NS		 4745 /* Elide positive zero offset. */
4746 if (offset || NEGATIVE_BIT_SET)
4747 func (stream, "[pc, #%s%d]\t; ",
d908c8af 4748 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 4749 else
26d97720
NS		 4750 func (stream, "[pc]\t; ");
4751 if (NEGATIVE_BIT_SET)
4752 offset = -offset;
aefd8a40
NC		 4753 info->print_address_func (offset + pc + 8, info);
4754 }
4755 else
4756 {
26d97720
NS		 4757 /* Always show the offset. */
4758 func (stream, "[pc], #%s%d",
d908c8af 4759 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 4760 if (! allow_unpredictable)
4761 is_unpredictable = TRUE;
aefd8a40 4762 }
252b5132
RH		 4763 }
4764 else
4765 {
fe56b6ce
NC		 4766 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
4767
b34976b6 4768 func (stream, "[%s",
252b5132 4769 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 4770
c1e26897 4771 if (PRE_BIT_SET)
252b5132 4772 {
c1e26897 4773 if (IMMEDIATE_BIT_SET)
252b5132 4774 {
26d97720
NS		 4775 /* Elide offset for non-writeback
4776 positive zero. */
4777 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
4778 || offset)
4779 func (stream, ", #%s%d",
4780 NEGATIVE_BIT_SET ? "-" : "", offset);
4781
4782 if (NEGATIVE_BIT_SET)
4783 offset = -offset;
945ee430 4784
fe56b6ce 4785 value_in_comment = offset;
252b5132 4786 }
945ee430 4787 else
ff4a8d2b
NC		 4788 {
4789 /* Register Offset or Register Pre-Indexed. */
4790 func (stream, ", %s%s",
4791 NEGATIVE_BIT_SET ? "-" : "",
4792 arm_regnames[given & 0xf]);
4793
4794 /* Writing back to the register that is the source/
4795 destination of the load/store is unpredictable. */
4796 if (! allow_unpredictable
4797 && WRITEBACK_BIT_SET
4798 && ((given & 0xf) == ((given >> 12) & 0xf)))
4799 is_unpredictable = TRUE;
4800 }
252b5132 4801
b34976b6 4802 func (stream, "]%s",
c1e26897 4803 WRITEBACK_BIT_SET ? "!" : "");
252b5132 4804 }
945ee430 4805 else
252b5132 4806 {
c1e26897 4807 if (IMMEDIATE_BIT_SET)
252b5132 4808 {
945ee430 4809 /* Immediate Post-indexed. */
aefd8a40 4810 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 4811 func (stream, "], #%s%d",
4812 NEGATIVE_BIT_SET ? "-" : "", offset);
4813 if (NEGATIVE_BIT_SET)
4814 offset = -offset;
fe56b6ce 4815 value_in_comment = offset;
252b5132 4816 }
945ee430 4817 else
ff4a8d2b
NC		 4818 {
4819 /* Register Post-indexed. */
4820 func (stream, "], %s%s",
4821 NEGATIVE_BIT_SET ? "-" : "",
4822 arm_regnames[given & 0xf]);
4823
4824 /* Writing back to the register that is the source/
4825 destination of the load/store is unpredictable. */
4826 if (! allow_unpredictable
4827 && (given & 0xf) == ((given >> 12) & 0xf))
4828 is_unpredictable = TRUE;
4829 }
c1e26897 4830
07a28fab
NC		 4831 if (! allow_unpredictable)
4832 {
4833 /* Writeback is automatically implied by post- addressing.
4834 Setting the W bit is unnecessary and ARM specify it as
4835 being unpredictable. */
4836 if (WRITEBACK_BIT_SET
4837 /* Specifying the PC register as the post-indexed
4838 registers is also unpredictable. */
ab8e2090
NC		 4839 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
4840 is_unpredictable = TRUE;
07a28fab 4841 }
252b5132
RH		 4842 }
4843 }
4844 break;
b34976b6 4845
252b5132 4846 case 'b':
6b5d3a4d 4847 {
f8b960bc 4848 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
05413229 4849 info->print_address_func (disp * 4 + pc + 8, info);
6b5d3a4d 4850 }
252b5132
RH		 4851 break;
4852
4853 case 'c':
c22aaad1
PB		 4854 if (((given >> 28) & 0xf) != 0xe)
4855 func (stream, "%s",
4856 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 4857 break;
4858
4859 case 'm':
4860 {
4861 int started = 0;
4862 int reg;
4863
4864 func (stream, "{");
4865 for (reg = 0; reg < 16; reg++)
4866 if ((given & (1 << reg)) != 0)
4867 {
4868 if (started)
4869 func (stream, ", ");
4870 started = 1;
4871 func (stream, "%s", arm_regnames[reg]);
4872 }
4873 func (stream, "}");
ab8e2090
NC		 4874 if (! started)
4875 is_unpredictable = TRUE;
252b5132
RH		 4876 }
4877 break;
4878
37b37b2d 4879 case 'q':
78c66db8 4880 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 4881 break;
4882
252b5132
RH		 4883 case 'o':
4884 if ((given & 0x02000000) != 0)
4885 {
a415b1cd
JB		 4886 unsigned int rotate = (given & 0xf00) >> 7;
4887 unsigned int immed = (given & 0xff);
4888 unsigned int a, i;
4889
4890 a = (((immed << (32 - rotate))
4891 | (immed >> rotate)) & 0xffffffff);
4892 /* If there is another encoding with smaller rotate,
4893 the rotate should be specified directly. */
4894 for (i = 0; i < 32; i += 2)
4895 if ((a << i | a >> (32 - i)) <= 0xff)
4896 break;
4897
4898 if (i != rotate)
4899 func (stream, "#%d, %d", immed, rotate);
4900 else
4901 func (stream, "#%d", a);
4902 value_in_comment = a;
252b5132
RH		 4903 }
4904 else
78c66db8 4905 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 4906 break;
4907
4908 case 'p':
4909 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 4910 {
823d2571
TG		 4911 arm_feature_set arm_ext_v6 =
4912 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
4913
aefd8a40
NC		 4914 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
4915 mechanism for setting PSR flag bits. They are
4916 obsolete in V6 onwards. */
823d2571
TG		 4917 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
4918 arm_ext_v6))
aefd8a40 4919 func (stream, "p");
4ab90a7a
AV		 4920 else
4921 is_unpredictable = TRUE;
aefd8a40 4922 }
252b5132
RH		 4923 break;
4924
4925 case 't':
4926 if ((given & 0x01200000) == 0x00200000)
4927 func (stream, "t");
4928 break;
4929
252b5132 4930 case 'A':
05413229
NC		 4931 {
4932 int offset = given & 0xff;
f02232aa 4933
05413229 4934 value_in_comment = offset * 4;
c1e26897 4935 if (NEGATIVE_BIT_SET)
05413229 4936 value_in_comment = - value_in_comment;
f02232aa 4937
05413229 4938 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 4939
c1e26897 4940 if (PRE_BIT_SET)
05413229
NC		 4941 {
4942 if (offset)
fe56b6ce 4943 func (stream, ", #%d]%s",
d908c8af 4944 (int) value_in_comment,
c1e26897 4945 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 4946 else
4947 func (stream, "]");
4948 }
4949 else
4950 {
4951 func (stream, "]");
f02232aa 4952
c1e26897 4953 if (WRITEBACK_BIT_SET)
05413229
NC		 4954 {
4955 if (offset)
d908c8af 4956 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 4957 }
4958 else
fe56b6ce 4959 {
d908c8af 4960 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 4961 value_in_comment = offset;
4962 }
05413229
NC		 4963 }
4964 }
252b5132
RH		 4965 break;
4966
077b8428
NC		 4967 case 'B':
4968 /* Print ARM V5 BLX(1) address: pc+25 bits. */
4969 {
4970 bfd_vma address;
4971 bfd_vma offset = 0;
b34976b6 4972
c1e26897 4973 if (! NEGATIVE_BIT_SET)
077b8428
NC		 4974 /* Is signed, hi bits should be ones. */
4975 offset = (-1) ^ 0x00ffffff;
4976
4977 /* Offset is (SignExtend(offset field)<<2). */
4978 offset += given & 0x00ffffff;
4979 offset <<= 2;
4980 address = offset + pc + 8;
b34976b6 4981
8f06b2d8
PB		 4982 if (given & 0x01000000)
4983 /* H bit allows addressing to 2-byte boundaries. */
4984 address += 2;
b1ee46c5 4985
8f06b2d8 4986 info->print_address_func (address, info);
b1ee46c5 4987 }
b1ee46c5
AH		 4988 break;
4989
252b5132 4990 case 'C':
90ec0d68
MGD		 4991 if ((given & 0x02000200) == 0x200)
4992 {
4993 const char * name;
4994 unsigned sysm = (given & 0x004f0000) >> 16;
4995
4996 sysm |= (given & 0x300) >> 4;
4997 name = banked_regname (sysm);
4998
4999 if (name != NULL)
5000 func (stream, "%s", name);
5001 else
d908c8af 5002 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 5003 }
5004 else
5005 {
43e65147 5006 func (stream, "%cPSR_",
90ec0d68
MGD		 5007 (given & 0x00400000) ? 'S' : 'C');
5008 if (given & 0x80000)
5009 func (stream, "f");
5010 if (given & 0x40000)
5011 func (stream, "s");
5012 if (given & 0x20000)
5013 func (stream, "x");
5014 if (given & 0x10000)
5015 func (stream, "c");
5016 }
252b5132
RH		 5017 break;
5018
62b3e311 5019 case 'U':
43e65147 5020 if ((given & 0xf0) == 0x60)
62b3e311 5021 {
52e7f43d
RE		 5022 switch (given & 0xf)
5023 {
5024 case 0xf: func (stream, "sy"); break;
5025 default:
5026 func (stream, "#%d", (int) given & 0xf);
5027 break;
5028 }
43e65147
L		 5029 }
5030 else
52e7f43d 5031 {
e797f7e0
MGD		 5032 const char * opt = data_barrier_option (given & 0xf);
5033 if (opt != NULL)
5034 func (stream, "%s", opt);
5035 else
52e7f43d 5036 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 5037 }
5038 break;
5039
b34976b6 5040 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 5041 case '5': case '6': case '7': case '8': case '9':
5042 {
16980d0b
JB		 5043 int width;
5044 unsigned long value;
252b5132 5045
16980d0b 5046 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 5047
252b5132
RH		 5048 switch (*c)
5049 {
ab8e2090
NC		 5050 case 'R':
5051 if (value == 15)
5052 is_unpredictable = TRUE;
5053 /* Fall through. */
16980d0b 5054 case 'r':
9eb6c0f1
MGD		 5055 case 'T':
5056 /* We want register + 1 when decoding T. */
5057 if (*c == 'T')
5058 ++value;
5059
ff4a8d2b
NC		 5060 if (c[1] == 'u')
5061 {
5062 /* Eat the 'u' character. */
5063 ++ c;
5064
5065 if (u_reg == value)
5066 is_unpredictable = TRUE;
5067 u_reg = value;
5068 }
5069 if (c[1] == 'U')
5070 {
5071 /* Eat the 'U' character. */
5072 ++ c;
5073
5074 if (U_reg == value)
5075 is_unpredictable = TRUE;
5076 U_reg = value;
5077 }
16980d0b
JB		 5078 func (stream, "%s", arm_regnames[value]);
5079 break;
5080 case 'd':
5081 func (stream, "%ld", value);
05413229 5082 value_in_comment = value;
16980d0b
JB		 5083 break;
5084 case 'b':
5085 func (stream, "%ld", value * 8);
05413229 5086 value_in_comment = value * 8;
16980d0b
JB		 5087 break;
5088 case 'W':
5089 func (stream, "%ld", value + 1);
05413229 5090 value_in_comment = value + 1;
16980d0b
JB		 5091 break;
5092 case 'x':
5093 func (stream, "0x%08lx", value);
5094
5095 /* Some SWI instructions have special
5096 meanings. */
5097 if ((given & 0x0fffffff) == 0x0FF00000)
5098 func (stream, "\t; IMB");
5099 else if ((given & 0x0fffffff) == 0x0FF00001)
5100 func (stream, "\t; IMBRange");
5101 break;
5102 case 'X':
5103 func (stream, "%01lx", value & 0xf);
05413229 5104 value_in_comment = value;
252b5132
RH		 5105 break;
5106 case '`':
5107 c++;
16980d0b 5108 if (value == 0)
252b5132
RH		 5109 func (stream, "%c", *c);
5110 break;
5111 case '\'':
5112 c++;
16980d0b 5113 if (value == ((1ul << width) - 1))
252b5132
RH		 5114 func (stream, "%c", *c);
5115 break;
5116 case '?':
fe56b6ce 5117 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 5118 c += 1 << width;
252b5132
RH		 5119 break;
5120 default:
5121 abort ();
5122 }
5123 break;
5124
0dd132b6
NC		 5125 case 'e':
5126 {
5127 int imm;
5128
5129 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
5130 func (stream, "%d", imm);
fe56b6ce 5131 value_in_comment = imm;
0dd132b6
NC		 5132 }
5133 break;
5134
0a003adc
ZW		 5135 case 'E':
5136 /* LSB and WIDTH fields of BFI or BFC. The machine-
5137 language instruction encodes LSB and MSB. */
5138 {
5139 long msb = (given & 0x001f0000) >> 16;
5140 long lsb = (given & 0x00000f80) >> 7;
91d6fa6a 5141 long w = msb - lsb + 1;
fe56b6ce 5142
91d6fa6a
NC		 5143 if (w > 0)
5144 func (stream, "#%lu, #%lu", lsb, w);
0a003adc
ZW		 5145 else
5146 func (stream, "(invalid: %lu:%lu)", lsb, msb);
5147 }
5148 break;
5149
90ec0d68
MGD		 5150 case 'R':
5151 /* Get the PSR/banked register name. */
5152 {
5153 const char * name;
5154 unsigned sysm = (given & 0x004f0000) >> 16;
5155
5156 sysm |= (given & 0x300) >> 4;
5157 name = banked_regname (sysm);
5158
5159 if (name != NULL)
5160 func (stream, "%s", name);
5161 else
d908c8af 5162 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 5163 }
5164 break;
5165
0a003adc
ZW		 5166 case 'V':
5167 /* 16-bit unsigned immediate from a MOVT or MOVW
5168 instruction, encoded in bits 0:11 and 15:19. */
5169 {
5170 long hi = (given & 0x000f0000) >> 4;
5171 long lo = (given & 0x00000fff);
5172 long imm16 = hi | lo;
fe56b6ce
NC		 5173
5174 func (stream, "#%lu", imm16);
5175 value_in_comment = imm16;
0a003adc
ZW		 5176 }
5177 break;
5178
252b5132
RH		 5179 default:
5180 abort ();
5181 }
5182 }
5183 }
5184 else
5185 func (stream, "%c", *c);
5186 }
05413229
NC		 5187
5188 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 5189 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 5190
5191 if (is_unpredictable)
5192 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 5193
4a5329c6 5194 return;
252b5132
RH		 5195 }
5196 }
5197 abort ();
5198}
5199
4a5329c6 5200/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 5201
4a5329c6
ZW		 5202static void
5203print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 5204{
6b5d3a4d 5205 const struct opcode16 *insn;
6a51a8a8
AM		 5206 void *stream = info->stream;
5207 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 5208
5209 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 5210 if ((given & insn->mask) == insn->value)
5211 {
05413229 5212 signed long value_in_comment = 0;
6b5d3a4d 5213 const char *c = insn->assembler;
05413229 5214
c19d1205
ZW		 5215 for (; *c; c++)
5216 {
5217 int domaskpc = 0;
5218 int domasklr = 0;
5219
5220 if (*c != '%')
5221 {
5222 func (stream, "%c", *c);
5223 continue;
5224 }
252b5132 5225
c19d1205
ZW		 5226 switch (*++c)
5227 {
5228 case '%':
5229 func (stream, "%%");
5230 break;
b34976b6 5231
c22aaad1
PB		 5232 case 'c':
5233 if (ifthen_state)
5234 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5235 break;
5236
5237 case 'C':
5238 if (ifthen_state)
5239 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5240 else
5241 func (stream, "s");
5242 break;
5243
5244 case 'I':
5245 {
5246 unsigned int tmp;
5247
5248 ifthen_next_state = given & 0xff;
5249 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
5250 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
5251 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
5252 }
5253 break;
5254
5255 case 'x':
5256 if (ifthen_next_state)
5257 func (stream, "\t; unpredictable branch in IT block\n");
5258 break;
5259
5260 case 'X':
5261 if (ifthen_state)
5262 func (stream, "\t; unpredictable <IT:%s>",
5263 arm_conditional[IFTHEN_COND]);
5264 break;
5265
c19d1205
ZW		 5266 case 'S':
5267 {
5268 long reg;
5269
5270 reg = (given >> 3) & 0x7;
5271 if (given & (1 << 6))
5272 reg += 8;
4f3c3dbb 5273
c19d1205
ZW		 5274 func (stream, "%s", arm_regnames[reg]);
5275 }
5276 break;
baf0cc5e 5277
c19d1205 5278 case 'D':
4f3c3dbb 5279 {
c19d1205
ZW		 5280 long reg;
5281
5282 reg = given & 0x7;
5283 if (given & (1 << 7))
5284 reg += 8;
5285
5286 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 5287 }
c19d1205
ZW		 5288 break;
5289
5290 case 'N':
5291 if (given & (1 << 8))
5292 domasklr = 1;
5293 /* Fall through. */
5294 case 'O':
5295 if (*c == 'O' && (given & (1 << 8)))
5296 domaskpc = 1;
5297 /* Fall through. */
5298 case 'M':
5299 {
5300 int started = 0;
5301 int reg;
5302
5303 func (stream, "{");
5304
5305 /* It would be nice if we could spot
5306 ranges, and generate the rS-rE format: */
5307 for (reg = 0; (reg < 8); reg++)
5308 if ((given & (1 << reg)) != 0)
5309 {
5310 if (started)
5311 func (stream, ", ");
5312 started = 1;
5313 func (stream, "%s", arm_regnames[reg]);
5314 }
5315
5316 if (domasklr)
5317 {
5318 if (started)
5319 func (stream, ", ");
5320 started = 1;
d908c8af 5321 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 5322 }
5323
5324 if (domaskpc)
5325 {
5326 if (started)
5327 func (stream, ", ");
d908c8af 5328 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 5329 }
5330
5331 func (stream, "}");
5332 }
5333 break;
5334
4547cb56
NC		 5335 case 'W':
5336 /* Print writeback indicator for a LDMIA. We are doing a
5337 writeback if the base register is not in the register
5338 mask. */
5339 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
5340 func (stream, "!");
5341 break;
5342
c19d1205
ZW		 5343 case 'b':
5344 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
5345 {
5346 bfd_vma address = (pc + 4
5347 + ((given & 0x00f8) >> 2)
5348 + ((given & 0x0200) >> 3));
5349 info->print_address_func (address, info);
5350 }
5351 break;
5352
5353 case 's':
5354 /* Right shift immediate -- bits 6..10; 1-31 print
5355 as themselves, 0 prints as 32. */
5356 {
5357 long imm = (given & 0x07c0) >> 6;
5358 if (imm == 0)
5359 imm = 32;
0fd3a477 5360 func (stream, "#%ld", imm);
c19d1205
ZW		 5361 }
5362 break;
5363
5364 case '0': case '1': case '2': case '3': case '4':
5365 case '5': case '6': case '7': case '8': case '9':
5366 {
5367 int bitstart = *c++ - '0';
5368 int bitend = 0;
5369
5370 while (*c >= '0' && *c <= '9')
5371 bitstart = (bitstart * 10) + *c++ - '0';
5372
5373 switch (*c)
5374 {
5375 case '-':
5376 {
f8b960bc 5377 bfd_vma reg;
c19d1205
ZW		 5378
5379 c++;
5380 while (*c >= '0' && *c <= '9')
5381 bitend = (bitend * 10) + *c++ - '0';
5382 if (!bitend)
5383 abort ();
5384 reg = given >> bitstart;
5385 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 5386
c19d1205
ZW		 5387 switch (*c)
5388 {
5389 case 'r':
5390 func (stream, "%s", arm_regnames[reg]);
5391 break;
5392
5393 case 'd':
d908c8af 5394 func (stream, "%ld", (long) reg);
05413229 5395 value_in_comment = reg;
c19d1205
ZW		 5396 break;
5397
5398 case 'H':
d908c8af 5399 func (stream, "%ld", (long) (reg << 1));
05413229 5400 value_in_comment = reg << 1;
c19d1205
ZW		 5401 break;
5402
5403 case 'W':
d908c8af 5404 func (stream, "%ld", (long) (reg << 2));
05413229 5405 value_in_comment = reg << 2;
c19d1205
ZW		 5406 break;
5407
5408 case 'a':
5409 /* PC-relative address -- the bottom two
5410 bits of the address are dropped
5411 before the calculation. */
5412 info->print_address_func
5413 (((pc + 4) & ~3) + (reg << 2), info);
05413229 5414 value_in_comment = 0;
c19d1205
ZW		 5415 break;
5416
5417 case 'x':
d908c8af 5418 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 5419 break;
5420
c19d1205
ZW		 5421 case 'B':
5422 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6b5d3a4d 5423 info->print_address_func (reg * 2 + pc + 4, info);
05413229 5424 value_in_comment = 0;
c19d1205
ZW		 5425 break;
5426
5427 case 'c':
c22aaad1 5428 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 5429 break;
5430
5431 default:
5432 abort ();
5433 }
5434 }
5435 break;
5436
5437 case '\'':
5438 c++;
5439 if ((given & (1 << bitstart)) != 0)
5440 func (stream, "%c", *c);
5441 break;
5442
5443 case '?':
5444 ++c;
5445 if ((given & (1 << bitstart)) != 0)
5446 func (stream, "%c", *c++);
5447 else
5448 func (stream, "%c", *++c);
5449 break;
5450
5451 default:
5452 abort ();
5453 }
5454 }
5455 break;
5456
5457 default:
5458 abort ();
5459 }
5460 }
05413229
NC		 5461
5462 if (value_in_comment > 32 || value_in_comment < -16)
5463 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 5464 return;
c19d1205
ZW		 5465 }
5466
5467 /* No match. */
5468 abort ();
5469}
5470
62b3e311 5471/* Return the name of an V7M special register. */
fe56b6ce 5472
62b3e311
PB		 5473static const char *
5474psr_name (int regno)
5475{
5476 switch (regno)
5477 {
1a336194
TP		 5478 case 0x0: return "APSR";
5479 case 0x1: return "IAPSR";
5480 case 0x2: return "EAPSR";
5481 case 0x3: return "PSR";
5482 case 0x5: return "IPSR";
5483 case 0x6: return "EPSR";
5484 case 0x7: return "IEPSR";
5485 case 0x8: return "MSP";
5486 case 0x9: return "PSP";
5487 case 0xa: return "MSPLIM";
5488 case 0xb: return "PSPLIM";
5489 case 0x10: return "PRIMASK";
5490 case 0x11: return "BASEPRI";
5491 case 0x12: return "BASEPRI_MAX";
5492 case 0x13: return "FAULTMASK";
5493 case 0x14: return "CONTROL";
16a1fa25
TP		 5494 case 0x88: return "MSP_NS";
5495 case 0x89: return "PSP_NS";
1a336194
TP		 5496 case 0x8a: return "MSPLIM_NS";
5497 case 0x8b: return "PSPLIM_NS";
5498 case 0x90: return "PRIMASK_NS";
5499 case 0x91: return "BASEPRI_NS";
5500 case 0x93: return "FAULTMASK_NS";
5501 case 0x94: return "CONTROL_NS";
5502 case 0x98: return "SP_NS";
62b3e311
PB		 5503 default: return "<unknown>";
5504 }
5505}
5506
4a5329c6
ZW		 5507/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
5508
5509static void
5510print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 5511{
6b5d3a4d 5512 const struct opcode32 *insn;
c19d1205
ZW		 5513 void *stream = info->stream;
5514 fprintf_ftype func = info->fprintf_func;
5515
16980d0b
JB		 5516 if (print_insn_coprocessor (pc, info, given, TRUE))
5517 return;
5518
5519 if (print_insn_neon (info, given, TRUE))
8f06b2d8
PB		 5520 return;
5521
c19d1205
ZW		 5522 for (insn = thumb32_opcodes; insn->assembler; insn++)
5523 if ((given & insn->mask) == insn->value)
5524 {
ff4a8d2b 5525 bfd_boolean is_unpredictable = FALSE;
05413229 5526 signed long value_in_comment = 0;
6b5d3a4d 5527 const char *c = insn->assembler;
05413229 5528
c19d1205
ZW		 5529 for (; *c; c++)
5530 {
5531 if (*c != '%')
5532 {
5533 func (stream, "%c", *c);
5534 continue;
5535 }
5536
5537 switch (*++c)
5538 {
5539 case '%':
5540 func (stream, "%%");
5541 break;
5542
c22aaad1
PB		 5543 case 'c':
5544 if (ifthen_state)
5545 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5546 break;
5547
5548 case 'x':
5549 if (ifthen_next_state)
5550 func (stream, "\t; unpredictable branch in IT block\n");
5551 break;
5552
5553 case 'X':
5554 if (ifthen_state)
5555 func (stream, "\t; unpredictable <IT:%s>",
5556 arm_conditional[IFTHEN_COND]);
5557 break;
5558
c19d1205
ZW		 5559 case 'I':
5560 {
5561 unsigned int imm12 = 0;
fe56b6ce 5562
c19d1205
ZW		 5563 imm12 |= (given & 0x000000ffu);
5564 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 5565 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 5566 func (stream, "#%u", imm12);
5567 value_in_comment = imm12;
c19d1205
ZW		 5568 }
5569 break;
5570
5571 case 'M':
5572 {
5573 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 5574
c19d1205
ZW		 5575 bits |= (given & 0x000000ffu);
5576 bits |= (given & 0x00007000u) >> 4;
5577 bits |= (given & 0x04000000u) >> 15;
5578 imm8 = (bits & 0x0ff);
5579 mod = (bits & 0xf00) >> 8;
5580 switch (mod)
5581 {
5582 case 0: imm = imm8; break;
c1e26897
NC		 5583 case 1: imm = ((imm8 << 16) | imm8); break;
5584 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
5585 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 5586 default:
5587 mod = (bits & 0xf80) >> 7;
5588 imm8 = (bits & 0x07f) | 0x80;
5589 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
5590 }
fe56b6ce
NC		 5591 func (stream, "#%u", imm);
5592 value_in_comment = imm;
c19d1205
ZW		 5593 }
5594 break;
43e65147 5595
c19d1205
ZW		 5596 case 'J':
5597 {
5598 unsigned int imm = 0;
fe56b6ce 5599
c19d1205
ZW		 5600 imm |= (given & 0x000000ffu);
5601 imm |= (given & 0x00007000u) >> 4;
5602 imm |= (given & 0x04000000u) >> 15;
5603 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 5604 func (stream, "#%u", imm);
5605 value_in_comment = imm;
c19d1205
ZW		 5606 }
5607 break;
5608
5609 case 'K':
5610 {
5611 unsigned int imm = 0;
fe56b6ce 5612
c19d1205
ZW		 5613 imm |= (given & 0x000f0000u) >> 16;
5614 imm |= (given & 0x00000ff0u) >> 0;
5615 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 5616 func (stream, "#%u", imm);
5617 value_in_comment = imm;
c19d1205
ZW		 5618 }
5619 break;
5620
74db7efb
NC		 5621 case 'H':
5622 {
5623 unsigned int imm = 0;
5624
5625 imm |= (given & 0x000f0000u) >> 4;
5626 imm |= (given & 0x00000fffu) >> 0;
5627 func (stream, "#%u", imm);
5628 value_in_comment = imm;
5629 }
5630 break;
5631
90ec0d68
MGD		 5632 case 'V':
5633 {
5634 unsigned int imm = 0;
5635
5636 imm |= (given & 0x00000fffu);
5637 imm |= (given & 0x000f0000u) >> 4;
5638 func (stream, "#%u", imm);
5639 value_in_comment = imm;
5640 }
5641 break;
5642
c19d1205
ZW		 5643 case 'S':
5644 {
5645 unsigned int reg = (given & 0x0000000fu);
5646 unsigned int stp = (given & 0x00000030u) >> 4;
5647 unsigned int imm = 0;
5648 imm |= (given & 0x000000c0u) >> 6;
5649 imm |= (given & 0x00007000u) >> 10;
5650
5651 func (stream, "%s", arm_regnames[reg]);
5652 switch (stp)
5653 {
5654 case 0:
5655 if (imm > 0)
5656 func (stream, ", lsl #%u", imm);
5657 break;
5658
5659 case 1:
5660 if (imm == 0)
5661 imm = 32;
5662 func (stream, ", lsr #%u", imm);
5663 break;
5664
5665 case 2:
5666 if (imm == 0)
5667 imm = 32;
5668 func (stream, ", asr #%u", imm);
5669 break;
5670
5671 case 3:
5672 if (imm == 0)
5673 func (stream, ", rrx");
5674 else
5675 func (stream, ", ror #%u", imm);
5676 }
5677 }
5678 break;
5679
5680 case 'a':
5681 {
5682 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 5683 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 5684 unsigned int op = (given & 0x00000f00) >> 8;
5685 unsigned int i12 = (given & 0x00000fff);
5686 unsigned int i8 = (given & 0x000000ff);
5687 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 5688 bfd_vma offset = 0;
c19d1205
ZW		 5689
5690 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 5691 if (U) /* 12-bit positive immediate offset. */
5692 {
5693 offset = i12;
5694 if (Rn != 15)
5695 value_in_comment = offset;
5696 }
5697 else if (Rn == 15) /* 12-bit negative immediate offset. */
5698 offset = - (int) i12;
5699 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 5700 {
5701 unsigned int Rm = (i8 & 0x0f);
5702 unsigned int sh = (i8 & 0x30) >> 4;
05413229 5703
c19d1205
ZW		 5704 func (stream, ", %s", arm_regnames[Rm]);
5705 if (sh)
5706 func (stream, ", lsl #%u", sh);
5707 func (stream, "]");
5708 break;
5709 }
5710 else switch (op)
5711 {
05413229 5712 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 5713 offset = i8;
5714 break;
5715
05413229 5716 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 5717 offset = -i8;
5718 break;
5719
05413229 5720 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 5721 offset = i8;
5722 writeback = TRUE;
5723 break;
5724
05413229 5725 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 5726 offset = -i8;
5727 writeback = TRUE;
5728 break;
5729
05413229 5730 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 5731 offset = i8;
5732 postind = TRUE;
5733 break;
5734
05413229 5735 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 5736 offset = -i8;
5737 postind = TRUE;
5738 break;
5739
5740 default:
5741 func (stream, ", <undefined>]");
5742 goto skip;
5743 }
5744
5745 if (postind)
d908c8af 5746 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 5747 else
5748 {
5749 if (offset)
d908c8af 5750 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 5751 func (stream, writeback ? "]!" : "]");
5752 }
5753
5754 if (Rn == 15)
5755 {
5756 func (stream, "\t; ");
5757 info->print_address_func (((pc + 4) & ~3) + offset, info);
5758 }
5759 }
5760 skip:
5761 break;
5762
5763 case 'A':
5764 {
c1e26897
NC		 5765 unsigned int U = ! NEGATIVE_BIT_SET;
5766 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 5767 unsigned int Rn = (given & 0x000f0000) >> 16;
5768 unsigned int off = (given & 0x000000ff);
5769
5770 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 5771
5772 if (PRE_BIT_SET)
c19d1205
ZW		 5773 {
5774 if (off || !U)
05413229
NC		 5775 {
5776 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
fe50e98c 5777 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 5778 }
c19d1205
ZW		 5779 func (stream, "]");
5780 if (W)
5781 func (stream, "!");
5782 }
5783 else
5784 {
5785 func (stream, "], ");
5786 if (W)
05413229
NC		 5787 {
5788 func (stream, "#%c%u", U ? '+' : '-', off * 4);
fe50e98c 5789 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 5790 }
c19d1205 5791 else
fe56b6ce
NC		 5792 {
5793 func (stream, "{%u}", off);
5794 value_in_comment = off;
5795 }
c19d1205
ZW		 5796 }
5797 }
5798 break;
5799
5800 case 'w':
5801 {
5802 unsigned int Sbit = (given & 0x01000000) >> 24;
5803 unsigned int type = (given & 0x00600000) >> 21;
05413229 5804
c19d1205
ZW		 5805 switch (type)
5806 {
5807 case 0: func (stream, Sbit ? "sb" : "b"); break;
5808 case 1: func (stream, Sbit ? "sh" : "h"); break;
5809 case 2:
5810 if (Sbit)
5811 func (stream, "??");
5812 break;
5813 case 3:
5814 func (stream, "??");
5815 break;
5816 }
5817 }
5818 break;
5819
5820 case 'm':
5821 {
5822 int started = 0;
5823 int reg;
5824
5825 func (stream, "{");
5826 for (reg = 0; reg < 16; reg++)
5827 if ((given & (1 << reg)) != 0)
5828 {
5829 if (started)
5830 func (stream, ", ");
5831 started = 1;
5832 func (stream, "%s", arm_regnames[reg]);
5833 }
5834 func (stream, "}");
5835 }
5836 break;
5837
5838 case 'E':
5839 {
5840 unsigned int msb = (given & 0x0000001f);
5841 unsigned int lsb = 0;
fe56b6ce 5842
c19d1205
ZW		 5843 lsb |= (given & 0x000000c0u) >> 6;
5844 lsb |= (given & 0x00007000u) >> 10;
5845 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
5846 }
5847 break;
5848
5849 case 'F':
5850 {
5851 unsigned int width = (given & 0x0000001f) + 1;
5852 unsigned int lsb = 0;
fe56b6ce 5853
c19d1205
ZW		 5854 lsb |= (given & 0x000000c0u) >> 6;
5855 lsb |= (given & 0x00007000u) >> 10;
5856 func (stream, "#%u, #%u", lsb, width);
5857 }
5858 break;
5859
5860 case 'b':
5861 {
5862 unsigned int S = (given & 0x04000000u) >> 26;
5863 unsigned int J1 = (given & 0x00002000u) >> 13;
5864 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 5865 bfd_vma offset = 0;
c19d1205
ZW		 5866
5867 offset |= !S << 20;
5868 offset |= J2 << 19;
5869 offset |= J1 << 18;
5870 offset |= (given & 0x003f0000) >> 4;
5871 offset |= (given & 0x000007ff) << 1;
5872 offset -= (1 << 20);
5873
5874 info->print_address_func (pc + 4 + offset, info);
5875 }
5876 break;
5877
5878 case 'B':
5879 {
5880 unsigned int S = (given & 0x04000000u) >> 26;
5881 unsigned int I1 = (given & 0x00002000u) >> 13;
5882 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 5883 bfd_vma offset = 0;
c19d1205
ZW		 5884
5885 offset |= !S << 24;
5886 offset |= !(I1 ^ S) << 23;
5887 offset |= !(I2 ^ S) << 22;
5888 offset |= (given & 0x03ff0000u) >> 4;
5889 offset |= (given & 0x000007ffu) << 1;
5890 offset -= (1 << 24);
36b0c57d 5891 offset += pc + 4;
c19d1205 5892
36b0c57d
PB		 5893 /* BLX target addresses are always word aligned. */
5894 if ((given & 0x00001000u) == 0)
5895 offset &= ~2u;
5896
5897 info->print_address_func (offset, info);
c19d1205
ZW		 5898 }
5899 break;
5900
5901 case 's':
5902 {
5903 unsigned int shift = 0;
fe56b6ce 5904
c19d1205
ZW		 5905 shift |= (given & 0x000000c0u) >> 6;
5906 shift |= (given & 0x00007000u) >> 10;
c1e26897 5907 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 5908 func (stream, ", asr #%u", shift);
5909 else if (shift)
5910 func (stream, ", lsl #%u", shift);
5911 /* else print nothing - lsl #0 */
5912 }
5913 break;
5914
5915 case 'R':
5916 {
5917 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 5918
c19d1205
ZW		 5919 if (rot)
5920 func (stream, ", ror #%u", rot * 8);
5921 }
5922 break;
5923
62b3e311 5924 case 'U':
43e65147 5925 if ((given & 0xf0) == 0x60)
62b3e311 5926 {
52e7f43d
RE		 5927 switch (given & 0xf)
5928 {
5929 case 0xf: func (stream, "sy"); break;
5930 default:
5931 func (stream, "#%d", (int) given & 0xf);
5932 break;
5933 }
62b3e311 5934 }
43e65147 5935 else
52e7f43d 5936 {
e797f7e0
MGD		 5937 const char * opt = data_barrier_option (given & 0xf);
5938 if (opt != NULL)
5939 func (stream, "%s", opt);
5940 else
5941 func (stream, "#%d", (int) given & 0xf);
52e7f43d 5942 }
62b3e311
PB		 5943 break;
5944
5945 case 'C':
5946 if ((given & 0xff) == 0)
5947 {
5948 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
5949 if (given & 0x800)
5950 func (stream, "f");
5951 if (given & 0x400)
5952 func (stream, "s");
5953 if (given & 0x200)
5954 func (stream, "x");
5955 if (given & 0x100)
5956 func (stream, "c");
5957 }
90ec0d68
MGD		 5958 else if ((given & 0x20) == 0x20)
5959 {
5960 char const* name;
5961 unsigned sysm = (given & 0xf00) >> 8;
5962
5963 sysm |= (given & 0x30);
5964 sysm |= (given & 0x00100000) >> 14;
5965 name = banked_regname (sysm);
43e65147 5966
90ec0d68
MGD		 5967 if (name != NULL)
5968 func (stream, "%s", name);
5969 else
d908c8af 5970 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 5971 }
62b3e311
PB		 5972 else
5973 {
d908c8af 5974 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 5975 }
5976 break;
5977
5978 case 'D':
90ec0d68
MGD		 5979 if (((given & 0xff) == 0)
5980 || ((given & 0x20) == 0x20))
5981 {
5982 char const* name;
5983 unsigned sm = (given & 0xf0000) >> 16;
5984
5985 sm |= (given & 0x30);
5986 sm |= (given & 0x00100000) >> 14;
5987 name = banked_regname (sm);
5988
5989 if (name != NULL)
5990 func (stream, "%s", name);
5991 else
d908c8af 5992 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 5993 }
62b3e311 5994 else
d908c8af 5995 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 5996 break;
5997
c19d1205
ZW		 5998 case '0': case '1': case '2': case '3': case '4':
5999 case '5': case '6': case '7': case '8': case '9':
6000 {
16980d0b
JB		 6001 int width;
6002 unsigned long val;
c19d1205 6003
16980d0b 6004 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 6005
c19d1205
ZW		 6006 switch (*c)
6007 {
05413229
NC		 6008 case 'd':
6009 func (stream, "%lu", val);
6010 value_in_comment = val;
6011 break;
ff4a8d2b 6012
f0fba320
RL		 6013 case 'D':
6014 func (stream, "%lu", val + 1);
6015 value_in_comment = val + 1;
6016 break;
6017
05413229
NC		 6018 case 'W':
6019 func (stream, "%lu", val * 4);
6020 value_in_comment = val * 4;
6021 break;
ff4a8d2b
NC		 6022
6023 case 'R':
6024 if (val == 15)
6025 is_unpredictable = TRUE;
6026 /* Fall through. */
6027 case 'r':
6028 func (stream, "%s", arm_regnames[val]);
6029 break;
c19d1205
ZW		 6030
6031 case 'c':
c22aaad1 6032 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 6033 break;
6034
6035 case '\'':
c19d1205 6036 c++;
16980d0b
JB		 6037 if (val == ((1ul << width) - 1))
6038 func (stream, "%c", *c);
c19d1205 6039 break;
43e65147 6040
c19d1205 6041 case '`':
c19d1205 6042 c++;
16980d0b
JB		 6043 if (val == 0)
6044 func (stream, "%c", *c);
c19d1205
ZW		 6045 break;
6046
6047 case '?':
fe56b6ce 6048 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 6049 c += 1 << width;
c19d1205 6050 break;
43e65147 6051
0bb027fd
RR		 6052 case 'x':
6053 func (stream, "0x%lx", val & 0xffffffffUL);
6054 break;
c19d1205
ZW		 6055
6056 default:
6057 abort ();
6058 }
6059 }
6060 break;
6061
32a94698
NC		 6062 case 'L':
6063 /* PR binutils/12534
6064 If we have a PC relative offset in an LDRD or STRD
6065 instructions then display the decoded address. */
6066 if (((given >> 16) & 0xf) == 0xf)
6067 {
6068 bfd_vma offset = (given & 0xff) * 4;
6069
6070 if ((given & (1 << 23)) == 0)
6071 offset = - offset;
6072 func (stream, "\t; ");
6073 info->print_address_func ((pc & ~3) + 4 + offset, info);
6074 }
6075 break;
6076
c19d1205
ZW		 6077 default:
6078 abort ();
6079 }
6080 }
05413229
NC		 6081
6082 if (value_in_comment > 32 || value_in_comment < -16)
6083 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 6084
6085 if (is_unpredictable)
6086 func (stream, UNPREDICTABLE_INSTRUCTION);
6087
4a5329c6 6088 return;
c19d1205 6089 }
252b5132 6090
58efb6c0 6091 /* No match. */
252b5132
RH		 6092 abort ();
6093}
6094
e821645d
DJ		 6095/* Print data bytes on INFO->STREAM. */
6096
6097static void
fe56b6ce
NC		 6098print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
6099 struct disassemble_info *info,
e821645d
DJ		 6100 long given)
6101{
6102 switch (info->bytes_per_chunk)
6103 {
6104 case 1:
6105 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
6106 break;
6107 case 2:
6108 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
6109 break;
6110 case 4:
6111 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
6112 break;
6113 default:
6114 abort ();
6115 }
6116}
6117
22a398e1 6118/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 6119 being displayed in symbol relative addresses.
6120
6121 Also disallow private symbol, with __tagsym$$ prefix,
6122 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 6123
6124bfd_boolean
6125arm_symbol_is_valid (asymbol * sym,
6126 struct disassemble_info * info ATTRIBUTE_UNUSED)
6127{
6128 const char * name;
43e65147 6129
22a398e1
NC		 6130 if (sym == NULL)
6131 return FALSE;
6132
6133 name = bfd_asymbol_name (sym);
6134
d8282f0e 6135 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 6136}
6137
65b48a81 6138/* Parse the string of disassembler options. */
baf0cc5e 6139
65b48a81 6140static void
f995bbe8 6141parse_arm_disassembler_options (const char *options)
dd92f639 6142{
f995bbe8 6143 const char *opt;
b34976b6 6144
65b48a81 6145 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
dd92f639 6146 {
65b48a81
PB		 6147 if (CONST_STRNEQ (opt, "reg-names-"))
6148 {
6149 unsigned int i;
6150 for (i = 0; i < NUM_ARM_OPTIONS; i++)
6151 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
6152 {
6153 regname_selected = i;
6154 break;
6155 }
b34976b6 6156
65b48a81 6157 if (i >= NUM_ARM_OPTIONS)
a6743a54
AM		 6158 /* xgettext: c-format */
6159 opcodes_error_handler (_("unrecognised register name set: %s"),
6160 opt);
65b48a81
PB		 6161 }
6162 else if (CONST_STRNEQ (opt, "force-thumb"))
6163 force_thumb = 1;
6164 else if (CONST_STRNEQ (opt, "no-force-thumb"))
6165 force_thumb = 0;
6166 else
a6743a54
AM		 6167 /* xgettext: c-format */
6168 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
dd92f639 6169 }
b34976b6 6170
dd92f639
NC		 6171 return;
6172}
6173
5bc5ae88
RL		 6174static bfd_boolean
6175mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6176 enum map_type *map_symbol);
6177
c22aaad1
PB		 6178/* Search back through the insn stream to determine if this instruction is
6179 conditionally executed. */
fe56b6ce 6180
c22aaad1 6181static void
fe56b6ce
NC		 6182find_ifthen_state (bfd_vma pc,
6183 struct disassemble_info *info,
c22aaad1
PB		 6184 bfd_boolean little)
6185{
6186 unsigned char b[2];
6187 unsigned int insn;
6188 int status;
6189 /* COUNT is twice the number of instructions seen. It will be odd if we
6190 just crossed an instruction boundary. */
6191 int count;
6192 int it_count;
6193 unsigned int seen_it;
6194 bfd_vma addr;
6195
6196 ifthen_address = pc;
6197 ifthen_state = 0;
6198
6199 addr = pc;
6200 count = 1;
6201 it_count = 0;
6202 seen_it = 0;
6203 /* Scan backwards looking for IT instructions, keeping track of where
6204 instruction boundaries are. We don't know if something is actually an
6205 IT instruction until we find a definite instruction boundary. */
6206 for (;;)
6207 {
fe56b6ce 6208 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 6209 {
6210 /* A symbol must be on an instruction boundary, and will not
6211 be within an IT block. */
6212 if (seen_it && (count & 1))
6213 break;
6214
6215 return;
6216 }
6217 addr -= 2;
fe56b6ce 6218 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 6219 if (status)
6220 return;
6221
6222 if (little)
6223 insn = (b[0]) | (b[1] << 8);
6224 else
6225 insn = (b[1]) | (b[0] << 8);
6226 if (seen_it)
6227 {
6228 if ((insn & 0xf800) < 0xe800)
6229 {
6230 /* Addr + 2 is an instruction boundary. See if this matches
6231 the expected boundary based on the position of the last
6232 IT candidate. */
6233 if (count & 1)
6234 break;
6235 seen_it = 0;
6236 }
6237 }
6238 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
6239 {
5bc5ae88
RL		 6240 enum map_type type = MAP_ARM;
6241 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
6242
6243 if (!found || (found && type == MAP_THUMB))
6244 {
6245 /* This could be an IT instruction. */
6246 seen_it = insn;
6247 it_count = count >> 1;
6248 }
c22aaad1
PB		 6249 }
6250 if ((insn & 0xf800) >= 0xe800)
6251 count++;
6252 else
6253 count = (count + 2) | 1;
6254 /* IT blocks contain at most 4 instructions. */
6255 if (count >= 8 && !seen_it)
6256 return;
6257 }
6258 /* We found an IT instruction. */
6259 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
6260 if ((ifthen_state & 0xf) == 0)
6261 ifthen_state = 0;
6262}
6263
b0e28b39
DJ		 6264/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
6265 mapping symbol. */
6266
6267static int
6268is_mapping_symbol (struct disassemble_info *info, int n,
6269 enum map_type *map_type)
6270{
6271 const char *name;
6272
6273 name = bfd_asymbol_name (info->symtab[n]);
6274 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
6275 && (name[2] == 0 || name[2] == '.'))
6276 {
6277 *map_type = ((name[1] == 'a') ? MAP_ARM
6278 : (name[1] == 't') ? MAP_THUMB
6279 : MAP_DATA);
6280 return TRUE;
6281 }
6282
6283 return FALSE;
6284}
6285
6286/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
6287 Returns nonzero if *MAP_TYPE was set. */
6288
6289static int
6290get_map_sym_type (struct disassemble_info *info,
6291 int n,
6292 enum map_type *map_type)
6293{
6294 /* If the symbol is in a different section, ignore it. */
6295 if (info->section != NULL && info->section != info->symtab[n]->section)
6296 return FALSE;
6297
6298 return is_mapping_symbol (info, n, map_type);
6299}
6300
6301/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 6302 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 6303
6304static int
fe56b6ce
NC		 6305get_sym_code_type (struct disassemble_info *info,
6306 int n,
e821645d 6307 enum map_type *map_type)
2087ad84
PB		 6308{
6309 elf_symbol_type *es;
6310 unsigned int type;
b0e28b39
DJ		 6311
6312 /* If the symbol is in a different section, ignore it. */
6313 if (info->section != NULL && info->section != info->symtab[n]->section)
6314 return FALSE;
2087ad84 6315
e821645d 6316 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 6317 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6318
6319 /* If the symbol has function type then use that. */
34e77a92 6320 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 6321 {
39d911fc
TP		 6322 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6323 == ST_BRANCH_TO_THUMB)
35fc36a8
RS		 6324 *map_type = MAP_THUMB;
6325 else
6326 *map_type = MAP_ARM;
2087ad84
PB		 6327 return TRUE;
6328 }
6329
2087ad84
PB		 6330 return FALSE;
6331}
6332
5bc5ae88
RL		 6333/* Search the mapping symbol state for instruction at pc. This is only
6334 applicable for elf target.
6335
6336 There is an assumption Here, info->private_data contains the correct AND
6337 up-to-date information about current scan process. The information will be
6338 used to speed this search process.
6339
6340 Return TRUE if the mapping state can be determined, and map_symbol
6341 will be updated accordingly. Otherwise, return FALSE. */
6342
6343static bfd_boolean
6344mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6345 enum map_type *map_symbol)
6346{
6347 bfd_vma addr;
6348 int n, start = 0;
6349 bfd_boolean found = FALSE;
6350 enum map_type type = MAP_ARM;
6351 struct arm_private_data *private_data;
6352
6353 if (info->private_data == NULL || info->symtab_size == 0
6354 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
6355 return FALSE;
6356
6357 private_data = info->private_data;
6358 if (pc == 0)
6359 start = 0;
6360 else
6361 start = private_data->last_mapping_sym;
6362
6363 start = (start == -1)? 0 : start;
6364 addr = bfd_asymbol_value (info->symtab[start]);
6365
6366 if (pc >= addr)
6367 {
6368 if (get_map_sym_type (info, start, &type))
6369 found = TRUE;
6370 }
6371 else
6372 {
6373 for (n = start - 1; n >= 0; n--)
6374 {
6375 if (get_map_sym_type (info, n, &type))
6376 {
6377 found = TRUE;
6378 break;
6379 }
6380 }
6381 }
6382
6383 /* No mapping symbols were found. A leading $d may be
6384 omitted for sections which start with data; but for
6385 compatibility with legacy and stripped binaries, only
6386 assume the leading $d if there is at least one mapping
6387 symbol in the file. */
6388 if (!found && private_data->has_mapping_symbols == 1)
6389 {
6390 type = MAP_DATA;
6391 found = TRUE;
6392 }
6393
6394 *map_symbol = type;
6395 return found;
6396}
6397
0313a2b8
NC		 6398/* Given a bfd_mach_arm_XXX value, this function fills in the fields
6399 of the supplied arm_feature_set structure with bitmasks indicating
c0c468d5 6400 the supported base architectures and coprocessor extensions.
0313a2b8
NC		 6401
6402 FIXME: This could more efficiently implemented as a constant array,
6403 although it would also be less robust. */
6404
6405static void
6406select_arm_features (unsigned long mach,
6407 arm_feature_set * features)
6408{
c0c468d5
TP		 6409 arm_feature_set arch_fset;
6410 const arm_feature_set fpu_any = FPU_ANY;
6411
1af1dd51
MW		 6412#undef ARM_SET_FEATURES
6413#define ARM_SET_FEATURES(FSET) \
6414 { \
6415 const arm_feature_set fset = FSET; \
c0c468d5 6416 arch_fset = fset; \
1af1dd51 6417 }
823d2571 6418
c0c468d5
TP		 6419 /* When several architecture versions share the same bfd_mach_arm_XXX value
6420 the most featureful is chosen. */
0313a2b8
NC		 6421 switch (mach)
6422 {
c0c468d5
TP		 6423 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
6424 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
6425 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
6426 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
6427 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
6428 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
6429 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
6430 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
6431 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
6432 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
1af1dd51 6433 case bfd_mach_arm_ep9312:
c0c468d5
TP		 6434 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
6435 ARM_CEXT_MAVERICK | FPU_MAVERICK));
1af1dd51 6436 break;
c0c468d5
TP		 6437 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
6438 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
6439 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
6440 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
6441 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
6442 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
6443 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
6444 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
6445 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
6446 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
6447 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
6448 case bfd_mach_arm_8:
6449 {
6450 /* Add bits for extensions that Armv8.4-A recognizes. */
6451 arm_feature_set armv8_4_ext_fset
6452 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML);
6453 ARM_SET_FEATURES (ARM_ARCH_V8_4A);
6454 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_4_ext_fset);
6455 break;
6456 }
6457 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
6458 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
6459 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
6460 /* If the machine type is unknown allow all architecture types and all
6461 extensions. */
6462 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
0313a2b8
NC		 6463 default:
6464 abort ();
6465 }
1af1dd51 6466#undef ARM_SET_FEATURES
c0c468d5
TP		 6467
6468 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
6469 and thus on bfd_mach_arm_XXX value. Therefore for a given
6470 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
6471 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
0313a2b8
NC		 6472}
6473
6474
58efb6c0
NC		 6475/* NOTE: There are no checks in these routines that
6476 the relevant number of data bytes exist. */
baf0cc5e 6477
58efb6c0 6478static int
4a5329c6 6479print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 6480{
c19d1205
ZW		 6481 unsigned char b[4];
6482 long given;
6483 int status;
e821645d 6484 int is_thumb = FALSE;
b0e28b39 6485 int is_data = FALSE;
bd2e2557 6486 int little_code;
e821645d 6487 unsigned int size = 4;
4a5329c6 6488 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 6489 bfd_boolean found = FALSE;
b0e28b39 6490 struct arm_private_data *private_data;
58efb6c0 6491
dd92f639
NC		 6492 if (info->disassembler_options)
6493 {
65b48a81 6494 parse_arm_disassembler_options (info->disassembler_options);
b34976b6 6495
58efb6c0 6496 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 6497 info->disassembler_options = NULL;
6498 }
b34976b6 6499
0313a2b8
NC		 6500 /* PR 10288: Control which instructions will be disassembled. */
6501 if (info->private_data == NULL)
6502 {
b0e28b39 6503 static struct arm_private_data private;
0313a2b8
NC		 6504
6505 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
6506 /* If the user did not use the -m command line switch then default to
6507 disassembling all types of ARM instruction.
43e65147 6508
0313a2b8
NC		 6509 The info->mach value has to be ignored as this will be based on
6510 the default archictecture for the target and/or hints in the notes
6511 section, but it will never be greater than the current largest arm
6512 machine value (iWMMXt2), which is only equivalent to the V5TE
6513 architecture. ARM architectures have advanced beyond the machine
6514 value encoding, and these newer architectures would be ignored if
6515 the machine value was used.
6516
6517 Ie the -m switch is used to restrict which instructions will be
6518 disassembled. If it is necessary to use the -m switch to tell
6519 objdump that an ARM binary is being disassembled, eg because the
6520 input is a raw binary file, but it is also desired to disassemble
6521 all ARM instructions then use "-marm". This will select the
6522 "unknown" arm architecture which is compatible with any ARM
6523 instruction. */
6524 info->mach = bfd_mach_arm_unknown;
6525
6526 /* Compute the architecture bitmask from the machine number.
6527 Note: This assumes that the machine number will not change
6528 during disassembly.... */
b0e28b39 6529 select_arm_features (info->mach, & private.features);
0313a2b8 6530
b0e28b39 6531 private.has_mapping_symbols = -1;
1fbaefec
PB		 6532 private.last_mapping_sym = -1;
6533 private.last_mapping_addr = 0;
b0e28b39
DJ		 6534
6535 info->private_data = & private;
0313a2b8 6536 }
b0e28b39
DJ		 6537
6538 private_data = info->private_data;
6539
bd2e2557
SS		 6540 /* Decide if our code is going to be little-endian, despite what the
6541 function argument might say. */
6542 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
6543
b0e28b39
DJ		 6544 /* For ELF, consult the symbol table to determine what kind of code
6545 or data we have. */
8977d4b2 6546 if (info->symtab_size != 0
e821645d
DJ		 6547 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
6548 {
6549 bfd_vma addr;
b0e28b39 6550 int n, start;
e821645d 6551 int last_sym = -1;
b0e28b39 6552 enum map_type type = MAP_ARM;
e821645d 6553
e821645d
DJ		 6554 /* Start scanning at the start of the function, or wherever
6555 we finished last time. */
6750a3a7
NC		 6556 /* PR 14006. When the address is 0 we are either at the start of the
6557 very first function, or else the first function in a new, unlinked
838441e4 6558 executable section (eg because of -ffunction-sections). Either way
6750a3a7
NC		 6559 start scanning from the beginning of the symbol table, not where we
6560 left off last time. */
6561 if (pc == 0)
6562 start = 0;
6563 else
6564 {
6565 start = info->symtab_pos + 1;
6566 if (start < private_data->last_mapping_sym)
6567 start = private_data->last_mapping_sym;
6568 }
b0e28b39 6569 found = FALSE;
e821645d 6570
b0e28b39
DJ		 6571 /* First, look for mapping symbols. */
6572 if (private_data->has_mapping_symbols != 0)
e821645d 6573 {
b0e28b39
DJ		 6574 /* Scan up to the location being disassembled. */
6575 for (n = start; n < info->symtab_size; n++)
6576 {
6577 addr = bfd_asymbol_value (info->symtab[n]);
6578 if (addr > pc)
6579 break;
6580 if (get_map_sym_type (info, n, &type))
6581 {
6582 last_sym = n;
6583 found = TRUE;
6584 }
6585 }
6586
6587 if (!found)
6588 {
6589 /* No mapping symbol found at this address. Look backwards
cc643b88 6590 for a preceding one. */
b0e28b39
DJ		 6591 for (n = start - 1; n >= 0; n--)
6592 {
6593 if (get_map_sym_type (info, n, &type))
6594 {
6595 last_sym = n;
6596 found = TRUE;
6597 break;
6598 }
6599 }
6600 }
6601
6602 if (found)
6603 private_data->has_mapping_symbols = 1;
6604
6605 /* No mapping symbols were found. A leading $d may be
6606 omitted for sections which start with data; but for
6607 compatibility with legacy and stripped binaries, only
6608 assume the leading $d if there is at least one mapping
6609 symbol in the file. */
6610 if (!found && private_data->has_mapping_symbols == -1)
e821645d 6611 {
b0e28b39
DJ		 6612 /* Look for mapping symbols, in any section. */
6613 for (n = 0; n < info->symtab_size; n++)
6614 if (is_mapping_symbol (info, n, &type))
6615 {
6616 private_data->has_mapping_symbols = 1;
6617 break;
6618 }
6619 if (private_data->has_mapping_symbols == -1)
6620 private_data->has_mapping_symbols = 0;
6621 }
6622
6623 if (!found && private_data->has_mapping_symbols == 1)
6624 {
6625 type = MAP_DATA;
e821645d
DJ		 6626 found = TRUE;
6627 }
6628 }
6629
b0e28b39
DJ		 6630 /* Next search for function symbols to separate ARM from Thumb
6631 in binaries without mapping symbols. */
e821645d
DJ		 6632 if (!found)
6633 {
b0e28b39
DJ		 6634 /* Scan up to the location being disassembled. */
6635 for (n = start; n < info->symtab_size; n++)
e821645d 6636 {
b0e28b39
DJ		 6637 addr = bfd_asymbol_value (info->symtab[n]);
6638 if (addr > pc)
6639 break;
6640 if (get_sym_code_type (info, n, &type))
e821645d
DJ		 6641 {
6642 last_sym = n;
6643 found = TRUE;
b0e28b39
DJ		 6644 }
6645 }
6646
6647 if (!found)
6648 {
6649 /* No mapping symbol found at this address. Look backwards
cc643b88 6650 for a preceding one. */
b0e28b39
DJ		 6651 for (n = start - 1; n >= 0; n--)
6652 {
6653 if (get_sym_code_type (info, n, &type))
6654 {
6655 last_sym = n;
6656 found = TRUE;
6657 break;
6658 }
e821645d
DJ		 6659 }
6660 }
6661 }
6662
1fbaefec
PB		 6663 private_data->last_mapping_sym = last_sym;
6664 private_data->last_type = type;
6665 is_thumb = (private_data->last_type == MAP_THUMB);
6666 is_data = (private_data->last_type == MAP_DATA);
b34976b6 6667
e821645d
DJ		 6668 /* Look a little bit ahead to see if we should print out
6669 two or four bytes of data. If there's a symbol,
6670 mapping or otherwise, after two bytes then don't
6671 print more. */
6672 if (is_data)
6673 {
6674 size = 4 - (pc & 3);
6675 for (n = last_sym + 1; n < info->symtab_size; n++)
6676 {
6677 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 6678 if (addr > pc
6679 && (info->section == NULL
6680 || info->section == info->symtab[n]->section))
e821645d
DJ		 6681 {
6682 if (addr - pc < size)
6683 size = addr - pc;
6684 break;
6685 }
6686 }
6687 /* If the next symbol is after three bytes, we need to
6688 print only part of the data, so that we can use either
6689 .byte or .short. */
6690 if (size == 3)
6691 size = (pc & 1) ? 1 : 2;
6692 }
6693 }
6694
6695 if (info->symbols != NULL)
252b5132 6696 {
5876e06d
NC		 6697 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
6698 {
2f0ca46a 6699 coff_symbol_type * cs;
b34976b6 6700
5876e06d
NC		 6701 cs = coffsymbol (*info->symbols);
6702 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
6703 || cs->native->u.syment.n_sclass == C_THUMBSTAT
6704 || cs->native->u.syment.n_sclass == C_THUMBLABEL
6705 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
6706 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
6707 }
e821645d
DJ		 6708 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
6709 && !found)
5876e06d 6710 {
2087ad84
PB		 6711 /* If no mapping symbol has been found then fall back to the type
6712 of the function symbol. */
e821645d
DJ		 6713 elf_symbol_type * es;
6714 unsigned int type;
2087ad84 6715
e821645d
DJ		 6716 es = *(elf_symbol_type **)(info->symbols);
6717 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 6718
39d911fc
TP		 6719 is_thumb =
6720 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6721 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
5876e06d 6722 }
e49d43ff
TG		 6723 else if (bfd_asymbol_flavour (*info->symbols)
6724 == bfd_target_mach_o_flavour)
6725 {
6726 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
6727
6728 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
6729 }
5876e06d 6730 }
b34976b6 6731
e821645d
DJ		 6732 if (force_thumb)
6733 is_thumb = TRUE;
6734
b8f9ee44
CL		 6735 if (is_data)
6736 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6737 else
6738 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6739
c19d1205 6740 info->bytes_per_line = 4;
252b5132 6741
1316c8b3
NC		 6742 /* PR 10263: Disassemble data if requested to do so by the user. */
6743 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 6744 {
6745 int i;
6746
1316c8b3 6747 /* Size was already set above. */
e821645d
DJ		 6748 info->bytes_per_chunk = size;
6749 printer = print_insn_data;
6750
fe56b6ce 6751 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 6752 given = 0;
6753 if (little)
6754 for (i = size - 1; i >= 0; i--)
6755 given = b[i] | (given << 8);
6756 else
6757 for (i = 0; i < (int) size; i++)
6758 given = b[i] | (given << 8);
6759 }
6760 else if (!is_thumb)
252b5132 6761 {
c19d1205
ZW		 6762 /* In ARM mode endianness is a straightforward issue: the instruction
6763 is four bytes long and is either ordered 0123 or 3210. */
6764 printer = print_insn_arm;
6765 info->bytes_per_chunk = 4;
4a5329c6 6766 size = 4;
c19d1205 6767
0313a2b8 6768 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 6769 if (little_code)
c19d1205
ZW		 6770 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
6771 else
6772 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
252b5132 6773 }
58efb6c0 6774 else
252b5132 6775 {
c19d1205
ZW		 6776 /* In Thumb mode we have the additional wrinkle of two
6777 instruction lengths. Fortunately, the bits that determine
6778 the length of the current instruction are always to be found
6779 in the first two bytes. */
4a5329c6 6780 printer = print_insn_thumb16;
c19d1205 6781 info->bytes_per_chunk = 2;
4a5329c6
ZW		 6782 size = 2;
6783
fe56b6ce 6784 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 6785 if (little_code)
9a2ff3f5
AM		 6786 given = (b[0]) | (b[1] << 8);
6787 else
6788 given = (b[1]) | (b[0] << 8);
6789
c19d1205 6790 if (!status)
252b5132 6791 {
c19d1205
ZW		 6792 /* These bit patterns signal a four-byte Thumb
6793 instruction. */
6794 if ((given & 0xF800) == 0xF800
6795 || (given & 0xF800) == 0xF000
6796 || (given & 0xF800) == 0xE800)
252b5132 6797 {
0313a2b8 6798 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 6799 if (little_code)
c19d1205 6800 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 6801 else
c19d1205
ZW		 6802 given = (b[1]) | (b[0] << 8) | (given << 16);
6803
6804 printer = print_insn_thumb32;
4a5329c6 6805 size = 4;
252b5132 6806 }
252b5132 6807 }
c22aaad1
PB		 6808
6809 if (ifthen_address != pc)
0313a2b8 6810 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 6811
6812 if (ifthen_state)
6813 {
6814 if ((ifthen_state & 0xf) == 0x8)
6815 ifthen_next_state = 0;
6816 else
6817 ifthen_next_state = (ifthen_state & 0xe0)
6818 | ((ifthen_state & 0xf) << 1);
6819 }
252b5132 6820 }
b34976b6 6821
c19d1205
ZW		 6822 if (status)
6823 {
6824 info->memory_error_func (status, pc, info);
6825 return -1;
6826 }
6a56ec7e
NC		 6827 if (info->flags & INSN_HAS_RELOC)
6828 /* If the instruction has a reloc associated with it, then
6829 the offset field in the instruction will actually be the
6830 addend for the reloc. (We are using REL type relocs).
6831 In such cases, we can ignore the pc when computing
6832 addresses, since the addend is not currently pc-relative. */
6833 pc = 0;
b34976b6 6834
4a5329c6 6835 printer (pc, info, given);
c22aaad1
PB		 6836
6837 if (is_thumb)
6838 {
6839 ifthen_state = ifthen_next_state;
6840 ifthen_address += size;
6841 }
4a5329c6 6842 return size;
252b5132
RH		 6843}
6844
6845int
4a5329c6 6846print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 6847{
bd2e2557
SS		 6848 /* Detect BE8-ness and record it in the disassembler info. */
6849 if (info->flavour == bfd_target_elf_flavour
6850 && info->section != NULL
6851 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
6852 info->endian_code = BFD_ENDIAN_LITTLE;
6853
b34976b6 6854 return print_insn (pc, info, FALSE);
58efb6c0 6855}
01c7f630 6856
58efb6c0 6857int
4a5329c6 6858print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 6859{
b34976b6 6860 return print_insn (pc, info, TRUE);
58efb6c0 6861}
252b5132 6862
471b9d15 6863const disasm_options_and_args_t *
65b48a81
PB		 6864disassembler_options_arm (void)
6865{
471b9d15 6866 static disasm_options_and_args_t *opts_and_args;
65b48a81 6867
471b9d15 6868 if (opts_and_args == NULL)
65b48a81 6869 {
471b9d15 6870 disasm_options_t *opts;
65b48a81 6871 unsigned int i;
471b9d15
MR		 6872
6873 opts_and_args = XNEW (disasm_options_and_args_t);
6874 opts_and_args->args = NULL;
6875
6876 opts = &opts_and_args->options;
65b48a81
PB		 6877 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
6878 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
471b9d15 6879 opts->arg = NULL;
65b48a81
PB		 6880 for (i = 0; i < NUM_ARM_OPTIONS; i++)
6881 {
6882 opts->name[i] = regnames[i].name;
6883 if (regnames[i].description != NULL)
6884 opts->description[i] = _(regnames[i].description);
6885 else
6886 opts->description[i] = NULL;
6887 }
6888 /* The array we return must be NULL terminated. */
6889 opts->name[i] = NULL;
6890 opts->description[i] = NULL;
6891 }
6892
471b9d15 6893 return opts_and_args;
65b48a81
PB		 6894}
6895
58efb6c0 6896void
4a5329c6 6897print_arm_disassembler_options (FILE *stream)
58efb6c0 6898{
65b48a81 6899 unsigned int i, max_len = 0;
58efb6c0
NC		 6900 fprintf (stream, _("\n\
6901The following ARM specific disassembler options are supported for use with\n\
6902the -M switch:\n"));
b34976b6 6903
65b48a81
PB		 6904 for (i = 0; i < NUM_ARM_OPTIONS; i++)
6905 {
6906 unsigned int len = strlen (regnames[i].name);
6907 if (max_len < len)
6908 max_len = len;
6909 }
58efb6c0 6910
65b48a81
PB		 6911 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
6912 fprintf (stream, " %s%*c %s\n",
6913 regnames[i].name,
6914 (int)(max_len - strlen (regnames[i].name)), ' ',
6915 _(regnames[i].description));
252b5132 6916}
GDB Binutils - Deliverables
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