projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH 46/57][Arm][OBJDUMP] Add support for MVE instructions: vmovl, vmull, vqdmull...
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
CommitLineData
252b5132 1/* Instruction printing code for the ARM
82704155 2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
143275ea 24#include <assert.h>
2fbad815 25
6394c606 26#include "disassemble.h"
2fbad815 27#include "opcode/arm.h"
252b5132 28#include "opintl.h"
31e0f3cd 29#include "safe-ctype.h"
65b48a81 30#include "libiberty.h"
0dbde4cf 31#include "floatformat.h"
252b5132 32
baf0cc5e 33/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 34#include "coff/internal.h"
35#include "libcoff.h"
2d5d5a8f 36#include "bfd.h"
252b5132
RH		 37#include "elf-bfd.h"
38#include "elf/internal.h"
39#include "elf/arm.h"
e49d43ff 40#include "mach-o.h"
252b5132 41
6b5d3a4d 42/* FIXME: Belongs in global header. */
01c7f630 43#ifndef strneq
58efb6c0
NC		 44#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
45#endif
46
1fbaefec
PB		 47/* Cached mapping symbol state. */
48enum map_type
49{
50 MAP_ARM,
51 MAP_THUMB,
52 MAP_DATA
53};
54
b0e28b39
DJ		 55struct arm_private_data
56{
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features;
59
1fbaefec
PB		 60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type;
62
63 /* Tracking symbol table information */
64 int last_mapping_sym;
796d6298
TC		 65
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset;
1fbaefec 68 bfd_vma last_mapping_addr;
b0e28b39
DJ		 69};
70
73cd51e5
AV		 71enum mve_instructions
72{
143275ea
AV		 73 MVE_VPST,
74 MVE_VPT_FP_T1,
75 MVE_VPT_FP_T2,
76 MVE_VPT_VEC_T1,
77 MVE_VPT_VEC_T2,
78 MVE_VPT_VEC_T3,
79 MVE_VPT_VEC_T4,
80 MVE_VPT_VEC_T5,
81 MVE_VPT_VEC_T6,
82 MVE_VCMP_FP_T1,
83 MVE_VCMP_FP_T2,
84 MVE_VCMP_VEC_T1,
85 MVE_VCMP_VEC_T2,
86 MVE_VCMP_VEC_T3,
87 MVE_VCMP_VEC_T4,
88 MVE_VCMP_VEC_T5,
89 MVE_VCMP_VEC_T6,
9743db03
AV		 90 MVE_VDUP,
91 MVE_VEOR,
92 MVE_VFMAS_FP_SCALAR,
93 MVE_VFMA_FP_SCALAR,
94 MVE_VFMA_FP,
95 MVE_VFMS_FP,
96 MVE_VHADD_T1,
97 MVE_VHADD_T2,
98 MVE_VHSUB_T1,
99 MVE_VHSUB_T2,
100 MVE_VRHADD,
04d54ace
AV		 101 MVE_VLD2,
102 MVE_VLD4,
103 MVE_VST2,
104 MVE_VST4,
aef6d006
AV		 105 MVE_VLDRB_T1,
106 MVE_VLDRH_T2,
107 MVE_VLDRB_T5,
108 MVE_VLDRH_T6,
109 MVE_VLDRW_T7,
110 MVE_VSTRB_T1,
111 MVE_VSTRH_T2,
112 MVE_VSTRB_T5,
113 MVE_VSTRH_T6,
114 MVE_VSTRW_T7,
ef1576a1
AV		 115 MVE_VLDRB_GATHER_T1,
116 MVE_VLDRH_GATHER_T2,
117 MVE_VLDRW_GATHER_T3,
118 MVE_VLDRD_GATHER_T4,
119 MVE_VLDRW_GATHER_T5,
120 MVE_VLDRD_GATHER_T6,
121 MVE_VSTRB_SCATTER_T1,
122 MVE_VSTRH_SCATTER_T2,
123 MVE_VSTRW_SCATTER_T3,
124 MVE_VSTRD_SCATTER_T4,
125 MVE_VSTRW_SCATTER_T5,
126 MVE_VSTRD_SCATTER_T6,
bf0b396d
AV		 127 MVE_VCVT_FP_FIX_VEC,
128 MVE_VCVT_BETWEEN_FP_INT,
129 MVE_VCVT_FP_HALF_FP,
130 MVE_VCVT_FROM_FP_TO_INT,
131 MVE_VRINT_FP,
c507f10b
AV		 132 MVE_VMOV_HFP_TO_GP,
133 MVE_VMOV_GP_TO_VEC_LANE,
134 MVE_VMOV_IMM_TO_VEC,
135 MVE_VMOV_VEC_TO_VEC,
136 MVE_VMOV2_VEC_LANE_TO_GP,
137 MVE_VMOV2_GP_TO_VEC_LANE,
138 MVE_VMOV_VEC_LANE_TO_GP,
139 MVE_VMVN_IMM,
140 MVE_VMVN_REG,
141 MVE_VORR_IMM,
142 MVE_VORR_REG,
143 MVE_VORN,
144 MVE_VBIC_IMM,
145 MVE_VBIC_REG,
146 MVE_VMOVX,
14925797
AV		 147 MVE_VMOVL,
148 MVE_VMOVN,
149 MVE_VMULL_INT,
150 MVE_VMULL_POLY,
151 MVE_VQDMULL_T1,
152 MVE_VQDMULL_T2,
153 MVE_VQMOVN,
154 MVE_VQMOVUN,
73cd51e5
AV		 155 MVE_NONE
156};
157
158enum mve_unpredictable
159{
160 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
161 */
143275ea
AV		 162 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and
163 fcB = 1 (vpt). */
164 UNPRED_R13, /* Unpredictable because r13 (sp) or
165 r15 (sp) used. */
9743db03 166 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
04d54ace
AV		 167 UNPRED_Q_GT_4, /* Unpredictable because
168 vec reg start > 4 (vld4/st4). */
169 UNPRED_Q_GT_6, /* Unpredictable because
170 vec reg start > 6 (vld2/st2). */
171 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
172 and WB bit = 1. */
ef1576a1
AV		 173 UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are
174 equal. */
175 UNPRED_OS, /* Unpredictable because offset scaled == 1. */
bf0b396d
AV		 176 UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the
177 same. */
c507f10b
AV		 178 UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and
179 size = 1. */
180 UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and
181 size = 2. */
73cd51e5
AV		 182 UNPRED_NONE /* No unpredictable behavior. */
183};
184
185enum mve_undefined
186{
bf0b396d 187 UNDEF_SIZE_0, /* undefined because size == 0. */
c507f10b 188 UNDEF_SIZE_2, /* undefined because size == 2. */
aef6d006
AV		 189 UNDEF_SIZE_3, /* undefined because size == 3. */
190 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
ef1576a1
AV		 191 UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
192 UNDEF_SIZE_NOT_3, /* undefined because size != 3. */
193 UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and
194 size == 0. */
195 UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and
196 size == 1. */
197 UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
bf0b396d
AV		 198 UNDEF_VCVT_IMM6, /* imm6 < 32. */
199 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
c507f10b
AV		 200 UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and
201 op1 == (0 or 1). */
202 UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and
203 op2 == 0 and op1 == (0 or 1). */
204 UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode
205 in {0xx1, x0x1}. */
73cd51e5
AV		 206 UNDEF_NONE /* no undefined behavior. */
207};
208
6b5d3a4d
ZW		 209struct opcode32
210{
823d2571
TG		 211 arm_feature_set arch; /* Architecture defining this insn. */
212 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 213 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 214 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 215};
216
73cd51e5
AV		 217/* MVE opcodes. */
218
219struct mopcode32
220{
221 arm_feature_set arch; /* Architecture defining this insn. */
222 enum mve_instructions mve_op; /* Specific mve instruction for faster
223 decoding. */
224 unsigned long value; /* If arch is 0 then value is a sentinel. */
225 unsigned long mask; /* Recognise insn if (op & mask) == value. */
226 const char * assembler; /* How to disassemble this insn. */
227};
228
6b0dd094
AV		 229enum isa {
230 ANY,
231 T32,
232 ARM
233};
234
235
236/* Shared (between Arm and Thumb mode) opcode. */
237struct sopcode32
238{
239 enum isa isa; /* Execution mode instruction availability. */
240 arm_feature_set arch; /* Architecture defining this insn. */
241 unsigned long value; /* If arch is 0 then value is a sentinel. */
242 unsigned long mask; /* Recognise insn if (op & mask) == value. */
243 const char * assembler; /* How to disassemble this insn. */
244};
245
6b5d3a4d
ZW		 246struct opcode16
247{
823d2571 248 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 249 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 250 const char *assembler; /* How to disassemble this insn. */
251};
b7693d02 252
8f06b2d8 253/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 254
2fbad815 255 %% %
4a5329c6 256
c22aaad1 257 %c print condition code (always bits 28-31 in ARM mode)
37b37b2d 258 %q print shifter argument
e2efe87d
MGD		 259 %u print condition code (unconditional in ARM mode,
260 UNPREDICTABLE if not AL in Thumb)
4a5329c6 261 %A print address for ldc/stc/ldf/stf instruction
16980d0b 262 %B print vstm/vldm register list
efd6b359 263 %C print vscclrm register list
4a5329c6 264 %I print cirrus signed shift immediate: bits 0..3|4..6
32c36c3c
AV		 265 %J print register for VLDR instruction
266 %K print address for VLDR instruction
4a5329c6
ZW		 267 %F print the COUNT field of a LFM/SFM instruction.
268 %P print floating point precision in arithmetic insn
269 %Q print floating point precision in ldf/stf insn
270 %R print floating point rounding mode
271
33399f07 272 %<bitfield>c print as a condition code (for vsel)
4a5329c6 273 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 274 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
275 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 276 %<bitfield>d print the bitfield in decimal
16980d0b 277 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 278 %<bitfield>x print the bitfield in hex
279 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 280 %<bitfield>f print a floating point constant if >7 else a
281 floating point register
4a5329c6
ZW		 282 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
283 %<bitfield>g print as an iWMMXt 64-bit register
284 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 285 %<bitfield>D print as a NEON D register
286 %<bitfield>Q print as a NEON Q register
c28eeff2 287 %<bitfield>V print as a NEON D or Q register
6f1c2142 288 %<bitfield>E print a quarter-float immediate value
4a5329c6 289
16980d0b 290 %y<code> print a single precision VFP reg.
2fbad815 291 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 292 %z<code> print a double precision VFP reg
2fbad815 293 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 294
16980d0b
JB		 295 %<bitfield>'c print specified char iff bitfield is all ones
296 %<bitfield>`c print specified char iff bitfield is all zeroes
297 %<bitfield>?ab... select from array of values in big endian order
43e65147 298
2fbad815 299 %L print as an iWMMXt N/M width field.
4a5329c6 300 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 301 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 302 versions.
303 %i print 5-bit immediate in bits 8,3..0
304 (print "32" when 0)
fe56b6ce 305 %r print register offset address for wldt/wstr instruction. */
2fbad815 306
21d799b5 307enum opcode_sentinel_enum
05413229
NC		 308{
309 SENTINEL_IWMMXT_START = 1,
310 SENTINEL_IWMMXT_END,
311 SENTINEL_GENERIC_START
312} opcode_sentinels;
313
aefd8a40 314#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
0b347048
TC		 315#define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
316#define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
c1e26897 317#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 318
8f06b2d8 319/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 320
6b0dd094 321static const struct sopcode32 coprocessor_opcodes[] =
2fbad815 322{
2fbad815 323 /* XScale instructions. */
6b0dd094 324 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 325 0x0e200010, 0x0fff0ff0,
326 "mia%c\tacc0, %0-3r, %12-15r"},
6b0dd094 327 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 328 0x0e280010, 0x0fff0ff0,
329 "miaph%c\tacc0, %0-3r, %12-15r"},
6b0dd094 330 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 331 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
6b0dd094 332 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 333 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
6b0dd094 334 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 335 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 336
2fbad815 337 /* Intel Wireless MMX technology instructions. */
6b0dd094
AV		 338 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
339 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
823d2571 340 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
6b0dd094 341 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 342 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
6b0dd094 343 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 344 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
6b0dd094 345 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 346 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
6b0dd094 347 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 348 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
6b0dd094 349 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 350 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
6b0dd094 351 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 352 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
6b0dd094 353 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 354 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 355 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 356 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 357 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 358 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 359 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 360 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
6b0dd094 361 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 362 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
6b0dd094 363 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 364 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
6b0dd094 365 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 366 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
6b0dd094 367 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 368 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
6b0dd094 369 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 370 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 371 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 372 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 373 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 374 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 375 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 376 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 377 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 378 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 379 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 380 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
6b0dd094 381 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 382 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 383 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 384 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 385 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 386 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 387 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 388 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 389 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 390 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 391 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 392 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 393 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 394 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
6b0dd094 395 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 396 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
6b0dd094 397 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 398 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
6b0dd094 399 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 400 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 401 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 402 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 403 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 404 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 405 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 406 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 407 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 408 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
6b0dd094 409 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 410 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 411 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 412 0x0e800120, 0x0f800ff0,
413 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 414 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 415 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 416 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 417 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 418 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 419 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 420 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 421 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 422 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 423 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 424 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 425 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 426 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 427 0x0e8000a0, 0x0f800ff0,
428 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 429 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 430 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 431 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 432 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 433 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 434 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 435 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 436 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 437 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 438 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 439 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 440 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 441 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 442 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 443 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 444 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 445 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 446 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
6b0dd094 447 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 448 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 449 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 450 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 451 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 452 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 453 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 454 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 455 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 456 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 457 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 458 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 459 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 460 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 461 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 462 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 463 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 464 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 465 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 466 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
6b0dd094 467 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 468 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
6b0dd094 469 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 470 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
6b0dd094 471 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 472 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 473 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 474 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 475 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 476 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 477 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 478 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
6b0dd094 479 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 480 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
6b0dd094 481 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 482 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
6b0dd094 483 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 484 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 485 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 486 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 487 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 488 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 489 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 490 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 491 {ANY, ARM_FEATURE_CORE_LOW (0),
823d2571 492 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 493
fe56b6ce 494 /* Floating point coprocessor (FPA) instructions. */
6b0dd094 495 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 496 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 497 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 498 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 499 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 500 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 501 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 502 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 503 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 504 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 505 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 506 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 507 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 508 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 509 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 510 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 511 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 512 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 513 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 514 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 515 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 516 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 517 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 518 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 519 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 520 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 521 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 522 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 523 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 524 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 525 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 526 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 527 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 528 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 529 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 530 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
6b0dd094 531 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 532 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
6b0dd094 533 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 534 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 535 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 536 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
6b0dd094 537 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 538 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
6b0dd094 539 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 540 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
6b0dd094 541 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 542 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
6b0dd094 543 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 544 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 545 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 546 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 547 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 548 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 549 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 550 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 551 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 552 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
6b0dd094 553 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 554 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
6b0dd094 555 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 556 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
6b0dd094 557 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 558 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
6b0dd094 559 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 560 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
6b0dd094 561 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 562 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
6b0dd094 563 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 564 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
6b0dd094 565 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 566 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
6b0dd094 567 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 568 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
6b0dd094 569 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 570 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
6b0dd094 571 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 572 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
6b0dd094 573 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 574 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
6b0dd094 575 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 576 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
6b0dd094 577 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 578 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
6b0dd094 579 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 580 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 581
efd6b359
AV		 582 /* Armv8.1-M Mainline instructions. */
583 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
584 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
585 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
586 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
587
16a1fa25 588 /* ARMv8-M Mainline Security Extensions instructions. */
6b0dd094 589 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25 590 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
6b0dd094 591 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25
TP		 592 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
593
fe56b6ce 594 /* Register load/store. */
6b0dd094 595 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 596 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
6b0dd094 597 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 598 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
6b0dd094 599 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 600 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
6b0dd094 601 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 602 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
6b0dd094 603 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 604 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
6b0dd094 605 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 606 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
6b0dd094 607 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 608 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
6b0dd094 609 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 610 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
6b0dd094 611 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 612 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
6b0dd094 613 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 614 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
6b0dd094 615 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 616 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
6b0dd094 617 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 618 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
6b0dd094 619 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 620 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
6b0dd094 621 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 622 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
6b0dd094 623 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 624 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
6b0dd094 625 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 626 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
32c36c3c
AV		 627 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
628 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
629 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
630 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
823d2571 631
6b0dd094 632 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 633 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 634 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 635 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 636 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 637 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
6b0dd094 638 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 639 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 640
fe56b6ce 641 /* Data transfer between ARM and NEON registers. */
6b0dd094 642 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 643 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
6b0dd094 644 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 645 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
6b0dd094 646 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 647 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
6b0dd094 648 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 649 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
6b0dd094 650 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 651 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
6b0dd094 652 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 653 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
6b0dd094 654 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 655 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
6b0dd094 656 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 657 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 658 /* Half-precision conversion instructions. */
6b0dd094 659 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 660 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
6b0dd094 661 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 662 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
6b0dd094 663 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 664 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
6b0dd094 665 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 666 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 667
fe56b6ce 668 /* Floating point coprocessor (VFP) instructions. */
6b0dd094 669 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 670 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
6b0dd094 671 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 672 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
6b0dd094 673 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 674 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
6b0dd094 675 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 676 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
6b0dd094 677 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 678 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
6b0dd094 679 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 680 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
6b0dd094 681 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 682 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
6b0dd094 683 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 684 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
6b0dd094 685 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 686 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
6b0dd094 687 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 688 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
6b0dd094 689 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 690 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
6b0dd094 691 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 692 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
6b0dd094 693 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 694 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
6b0dd094 695 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 696 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
6b0dd094 697 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 698 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
6b0dd094 699 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 700 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
6b0dd094 701 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 702 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
6b0dd094 703 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 704 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
6b0dd094 705 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 706 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
6b0dd094 707 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 708 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
6b0dd094 709 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 710 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
6b0dd094 711 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 712 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
6b0dd094 713 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 714 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
6b0dd094 715 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 716 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
6b0dd094 717 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 718 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
6b0dd094 719 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 720 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
6b0dd094 721 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 722 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
6b0dd094 723 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 724 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
6b0dd094 725 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 726 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
6b0dd094 727 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 728 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
6b0dd094 729 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 730 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
6b0dd094 731 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 732 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
6b0dd094 733 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 734 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
6b0dd094 735 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 736 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
6b0dd094 737 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 738 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
6b0dd094 739 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 740 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
6b0dd094 741 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 742 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
6b0dd094 743 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 744 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
6b0dd094 745 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 746 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
6b0dd094 747 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 748 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 749 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 750 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
6b0dd094 751 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 752 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
6b0dd094 753 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 754 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
6b0dd094 755 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 756 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
6b0dd094 757 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 758 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
6b0dd094 759 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 760 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
6b0dd094 761 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6f1c2142 762 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
6b0dd094 763 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6f1c2142 764 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
6b0dd094 765 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 766 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
6b0dd094 767 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 768 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
6b0dd094 769 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 770 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
6b0dd094 771 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 772 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 773 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 774 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 775 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 776 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 777 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 778 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 779 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 780 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 781 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 782 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 783 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 784 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 785 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 786 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 787 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 788 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 789 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 790 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 791 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 792 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 793 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 794 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 795 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 796 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
6b0dd094 797 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 798 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
6b0dd094 799 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 800 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
6b0dd094 801 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 802 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
6b0dd094 803 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 804 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
6b0dd094 805 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 806 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 807
808 /* Cirrus coprocessor instructions. */
6b0dd094 809 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 810 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 811 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 812 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 813 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 814 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 815 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 816 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 817 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 818 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 819 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 820 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 821 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 822 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 823 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 824 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 825 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 826 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 827 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 828 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 829 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 830 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 831 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 832 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 833 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 834 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 835 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 836 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 837 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 838 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 839 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 840 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 841 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 842 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
6b0dd094 843 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 844 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
6b0dd094 845 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 846 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
6b0dd094 847 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 848 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
6b0dd094 849 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 850 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
6b0dd094 851 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 852 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
6b0dd094 853 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 854 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 855 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 856 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
6b0dd094 857 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 858 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 859 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 860 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
6b0dd094 861 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 862 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 863 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 864 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 865 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 866 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 867 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 868 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 869 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 870 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 871 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 872 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 873 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 874 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 875 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 876 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 877 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 878 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
6b0dd094 879 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 880 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
6b0dd094 881 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 882 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
6b0dd094 883 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 884 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
6b0dd094 885 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 886 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 887 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 888 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 889 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 890 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
6b0dd094 891 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 892 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
6b0dd094 893 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 894 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
6b0dd094 895 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 896 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
6b0dd094 897 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 898 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
6b0dd094 899 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 900 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
6b0dd094 901 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 902 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 903 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 904 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 905 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 906 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 907 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 908 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 909 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 910 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
6b0dd094 911 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 912 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
6b0dd094 913 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 914 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
6b0dd094 915 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 916 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
6b0dd094 917 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 918 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
6b0dd094 919 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 920 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
6b0dd094 921 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 922 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 923 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 924 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 925 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 926 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 927 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 928 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 929 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 930 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 931 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 932 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 933 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 934 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 935 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 936 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 937 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 938 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 939 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 940 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 941 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 942 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 943 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 944 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 945 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 946 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 947 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 948 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 949 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 950 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 951 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 952 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 953 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 954 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 955 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 956 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 957 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 958 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 959 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 960 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 961 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 962 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 963 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 964 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 965 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 966 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 967 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 968 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 969 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 970 0x0e000600, 0x0ff00f10,
971 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 972 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 973 0x0e100600, 0x0ff00f10,
974 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 975 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 976 0x0e200600, 0x0ff00f10,
977 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 978 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 979 0x0e300600, 0x0ff00f10,
980 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 981
62f3b8c8 982 /* VFP Fused multiply add instructions. */
6b0dd094 983 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 984 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
6b0dd094 985 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 986 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
6b0dd094 987 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 988 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
6b0dd094 989 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 990 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
6b0dd094 991 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 992 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
6b0dd094 993 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 994 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
6b0dd094 995 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 996 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
6b0dd094 997 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 998 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 999
33399f07 1000 /* FP v5. */
6b0dd094 1001 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1002 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
6b0dd094 1003 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1004 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
6b0dd094 1005 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1006 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1007 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1008 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1009 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1010 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1011 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1012 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1013 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1014 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
6b0dd094 1015 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1016 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
6b0dd094 1017 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1018 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
6b0dd094 1019 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1020 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
6b0dd094 1021 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1022 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
6b0dd094 1023 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1024 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 1025
05413229 1026 /* Generic coprocessor instructions. */
6b0dd094
AV		 1027 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
1028 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
823d2571 1029 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
6b0dd094 1030 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
823d2571
TG		 1031 0x0c500000, 0x0ff00000,
1032 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
6b0dd094 1033 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1034 0x0e000000, 0x0f000010,
1035 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1036 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1037 0x0e10f010, 0x0f10f010,
1038 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1039 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1040 0x0e100010, 0x0f100010,
1041 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1042 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1043 0x0e000010, 0x0f100010,
1044 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1045 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571 1046 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 1047 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571 1048 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
2fbad815 1049
05413229 1050 /* V6 coprocessor instructions. */
6b0dd094 1051 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
823d2571
TG		 1052 0xfc500000, 0xfff00000,
1053 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
6b0dd094 1054 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
823d2571
TG		 1055 0xfc400000, 0xfff00000,
1056 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
8f06b2d8 1057
c28eeff2 1058 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
6b0dd094 1059 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1060 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1061 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1062 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1063 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1064 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1065 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1066 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1067 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1068 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1069 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1070 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1071 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1072 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
6b0dd094 1073 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1074 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
6b0dd094 1075 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1076 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
6b0dd094 1077 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1078 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
c28eeff2 1079
c604a79a 1080 /* Dot Product instructions in the space of coprocessor 13. */
6b0dd094 1081 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a 1082 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
6b0dd094 1083 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a
JW		 1084 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1085
dec41383 1086 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
6b0dd094 1087 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1088 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1089 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1090 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1091 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1092 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1093 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1094 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1095 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1096 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1097 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1098 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1099 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1100 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
6b0dd094 1101 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383
JW		 1102 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1103
05413229 1104 /* V5 coprocessor instructions. */
6b0dd094 1105 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571 1106 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 1107 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571 1108 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 1109 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1110 0xfe000000, 0xff000010,
1111 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1112 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1113 0xfe000010, 0xff100010,
1114 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1115 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1116 0xfe100010, 0xff100010,
1117 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1118
b0c11777
RL		 1119 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1120 cp_num: bit <11:8> == 0b1001.
1121 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
6b0dd094 1122 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1123 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
6b0dd094 1124 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1125 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
6b0dd094 1126 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1127 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
6b0dd094 1128 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1129 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
6b0dd094 1130 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1131 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 1132 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1133 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
6b0dd094 1134 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1135 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
6b0dd094 1136 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1137 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
6b0dd094 1138 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1139 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
6b0dd094 1140 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1141 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
6b0dd094 1142 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1143 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1144 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1145 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1146 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1147 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1148 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1149 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1150 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1151 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
6b0dd094 1152 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1153 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
6b0dd094 1154 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1155 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
6b0dd094 1156 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1157 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
6b0dd094 1158 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1159 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1160 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1161 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1162 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1163 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1164 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1165 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1166 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1167 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
6b0dd094 1168 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1169 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
6b0dd094 1170 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1171 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
6b0dd094 1172 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1173 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1174 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1175 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
6b0dd094 1176 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1177 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1178 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1179 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1180 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1181 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1182 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1183 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
6b0dd094 1184 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1185 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
6b0dd094 1186 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1187 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
6b0dd094 1188 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1189 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
6b0dd094 1190 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777
RL		 1191 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1192
49e8a725 1193 /* ARMv8.3 javascript conversion instruction. */
6b0dd094 1194 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
49e8a725
SN		 1195 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1196
6b0dd094 1197 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 1198};
1199
16980d0b
JB		 1200/* Neon opcode table: This does not encode the top byte -- that is
1201 checked by the print_insn_neon routine, as it depends on whether we are
1202 doing thumb32 or arm32 disassembly. */
1203
1204/* print_insn_neon recognizes the following format control codes:
1205
1206 %% %
1207
c22aaad1 1208 %c print condition code
e2efe87d
MGD		 1209 %u print condition code (unconditional in ARM mode,
1210 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 1211 %A print v{st,ld}[1234] operands
1212 %B print v{st,ld}[1234] any one operands
1213 %C print v{st,ld}[1234] single->all operands
1214 %D print scalar
1215 %E print vmov, vmvn, vorr, vbic encoded constant
1216 %F print vtbl,vtbx register list
1217
1218 %<bitfield>r print as an ARM register
1219 %<bitfield>d print the bitfield in decimal
1220 %<bitfield>e print the 2^N - bitfield in decimal
1221 %<bitfield>D print as a NEON D register
1222 %<bitfield>Q print as a NEON Q register
1223 %<bitfield>R print as a NEON D or Q register
1224 %<bitfield>Sn print byte scaled width limited by n
1225 %<bitfield>Tn print short scaled width limited by n
1226 %<bitfield>Un print long scaled width limited by n
43e65147 1227
16980d0b
JB		 1228 %<bitfield>'c print specified char iff bitfield is all ones
1229 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1230 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1231
1232static const struct opcode32 neon_opcodes[] =
1233{
fe56b6ce 1234 /* Extract. */
823d2571
TG		 1235 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1236 0xf2b00840, 0xffb00850,
1237 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1238 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1239 0xf2b00000, 0xffb00810,
1240 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 1241
9743db03
AV		 1242 /* Data transfer between ARM and NEON registers. */
1243 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1244 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1245 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1246 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1247 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1248 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1249 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1250 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1251 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1252 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1253 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1254 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1255
fe56b6ce 1256 /* Move data element to all lanes. */
823d2571
TG		 1257 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1258 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1259 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1260 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1261 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1262 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 1263
fe56b6ce 1264 /* Table lookup. */
823d2571
TG		 1265 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1266 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1267 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1268 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1269
8e79c3df 1270 /* Half-precision conversions. */
823d2571
TG		 1271 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1272 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1273 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1274 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1275
1276 /* NEON fused multiply add instructions. */
823d2571 1277 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1278 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1279 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1280 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1281 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1282 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1283 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1284 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1285
fe56b6ce 1286 /* Two registers, miscellaneous. */
823d2571
TG		 1287 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1288 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1289 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1290 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1291 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1292 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1293 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1294 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1295 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1296 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1297 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1298 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1299 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1300 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1301 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1302 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1303 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1304 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1305 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1306 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1307 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1308 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1309 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1310 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1311 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1312 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1313 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1314 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1315 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1316 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1317 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1318 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1319 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1320 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1321 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1322 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1323 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1324 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1325 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1326 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1327 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1328 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1329 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1330 0xf3b20300, 0xffb30fd0,
1331 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1332 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1333 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1334 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1335 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1336 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1337 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1338 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1339 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1340 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1341 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1342 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1343 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1344 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1345 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1346 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1347 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1348 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1349 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1350 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1351 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1352 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1353 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1354 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1355 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1356 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1357 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1358 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1359 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1360 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1361 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1362 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1363 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1364 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1365 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1366 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1367 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1368 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1369 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1370 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1371 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1372 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1373 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1374 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1375 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1376 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1377 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1378 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301 1379 0xf3bb0600, 0xffbf0e10,
823d2571 1380 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1381 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1382 0xf3b70600, 0xffbf0e10,
1383 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
16980d0b 1384
fe56b6ce 1385 /* Three registers of the same length. */
823d2571
TG		 1386 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1387 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1388 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1389 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1390 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1391 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1392 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1393 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1394 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1395 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1396 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1397 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1398 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1399 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1400 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1401 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1402 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1403 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1404 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1405 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1406 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1407 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1408 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1409 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1410 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1411 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1412 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1413 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1414 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1415 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1416 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1417 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1418 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1419 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1420 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1421 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1422 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1423 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1424 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1425 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1426 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1427 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1428 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1429 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1430 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1431 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1432 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1433 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1434 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1435 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1436 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1437 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1438 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1439 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1440 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1441 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1442 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1443 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1444 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1445 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1446 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1447 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1448 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1449 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1450 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1451 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1452 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1453 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1454 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1455 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1456 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1457 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1458 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1459 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1460 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1461 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1462 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1463 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1465 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1466 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1467 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1468 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1469 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1470 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1471 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1473 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1474 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1475 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1477 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1478 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1479 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1481 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1482 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1483 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1484 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1485 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1486 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1487 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1489 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1490 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1491 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1492 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1493 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1494 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1495 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1496 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1497 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1498 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1499 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1500 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1501 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1502 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1503 0xf2000b00, 0xff800f10,
1504 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506 0xf2000b10, 0xff800f10,
1507 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1508 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1509 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1510 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1511 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1512 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1513 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1514 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1515 0xf3000b00, 0xff800f10,
1516 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1517 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1518 0xf2000000, 0xfe800f10,
1519 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1520 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1521 0xf2000010, 0xfe800f10,
1522 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1523 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1524 0xf2000100, 0xfe800f10,
1525 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1526 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1527 0xf2000200, 0xfe800f10,
1528 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1530 0xf2000210, 0xfe800f10,
1531 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1532 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1533 0xf2000300, 0xfe800f10,
1534 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1535 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1536 0xf2000310, 0xfe800f10,
1537 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1538 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1539 0xf2000400, 0xfe800f10,
1540 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1541 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1542 0xf2000410, 0xfe800f10,
1543 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1544 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1545 0xf2000500, 0xfe800f10,
1546 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1547 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1548 0xf2000510, 0xfe800f10,
1549 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1550 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1551 0xf2000600, 0xfe800f10,
1552 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1553 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1554 0xf2000610, 0xfe800f10,
1555 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1556 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1557 0xf2000700, 0xfe800f10,
1558 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1559 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1560 0xf2000710, 0xfe800f10,
1561 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1562 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1563 0xf2000910, 0xfe800f10,
1564 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1565 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1566 0xf2000a00, 0xfe800f10,
1567 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1568 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1569 0xf2000a10, 0xfe800f10,
1570 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1571 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1572 0xf3000b10, 0xff800f10,
1573 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1574 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1575 0xf3000c10, 0xff800f10,
1576 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1577
fe56b6ce 1578 /* One register and an immediate value. */
823d2571
TG		 1579 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1580 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1581 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1582 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1583 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1584 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1585 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1586 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1587 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1588 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1589 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1590 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1591 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1592 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1594 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1595 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1596 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1597 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1598 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1599 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1600 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1601 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1602 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1603 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1604 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1605
fe56b6ce 1606 /* Two registers and a shift amount. */
823d2571
TG		 1607 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1608 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1609 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1610 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1611 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1612 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1613 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1614 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1615 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1616 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1618 0xf2880950, 0xfeb80fd0,
1619 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1621 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1622 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1623 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1624 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1625 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1626 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1627 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1628 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1629 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1630 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1631 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1632 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1633 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1634 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1635 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1636 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1637 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1638 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1639 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1640 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1641 0xf2900950, 0xfeb00fd0,
1642 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1643 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1644 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1646 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1647 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1648 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1650 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1651 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1652 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1653 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1654 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1655 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1656 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1658 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1659 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1660 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1661 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1662 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1663 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1664 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1665 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1666 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1667 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1668 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1669 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1670 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1671 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1672 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1673 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1674 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1675 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1676 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1677 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1678 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1679 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1680 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1681 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1682 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1683 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1684 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1685 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1686 0xf2a00950, 0xfea00fd0,
1687 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1688 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1689 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1691 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1692 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1693 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1694 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1695 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1696 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1697 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1698 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1699 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1700 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1701 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1702 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1703 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1704 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1705 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1706 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1707 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1708 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1709 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1710 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1711 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1712 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1713 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1714 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1715 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1716 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1717 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1718 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1719 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1720 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1721 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1722 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1723 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1724 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1725 0xf2a00e10, 0xfea00e90,
1726 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
cc933301
JW		 1727 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1728 0xf2a00c10, 0xfea00e90,
1729 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 1730
fe56b6ce 1731 /* Three registers of different lengths. */
823d2571
TG		 1732 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1733 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1734 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1735 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1736 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1737 0xf2800400, 0xff800f50,
1738 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1739 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1740 0xf2800600, 0xff800f50,
1741 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1742 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1743 0xf2800900, 0xff800f50,
1744 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1745 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1746 0xf2800b00, 0xff800f50,
1747 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1748 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1749 0xf2800d00, 0xff800f50,
1750 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1751 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1752 0xf3800400, 0xff800f50,
1753 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1754 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1755 0xf3800600, 0xff800f50,
1756 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1757 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1758 0xf2800000, 0xfe800f50,
1759 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1760 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1761 0xf2800100, 0xfe800f50,
1762 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1763 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1764 0xf2800200, 0xfe800f50,
1765 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1766 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1767 0xf2800300, 0xfe800f50,
1768 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1769 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1770 0xf2800500, 0xfe800f50,
1771 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1772 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1773 0xf2800700, 0xfe800f50,
1774 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1775 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1776 0xf2800800, 0xfe800f50,
1777 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1778 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1779 0xf2800a00, 0xfe800f50,
1780 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1781 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1782 0xf2800c00, 0xfe800f50,
1783 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 1784
fe56b6ce 1785 /* Two registers and a scalar. */
823d2571
TG		 1786 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1787 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1788 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1789 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1790 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1791 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1792 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1793 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1794 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1795 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1796 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1797 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1798 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1799 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1800 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1801 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1802 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1803 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1804 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1805 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1806 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1807 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1808 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1809 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1810 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1811 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1812 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1813 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1814 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1815 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1816 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1817 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1818 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1819 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1820 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1821 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1822 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1823 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1824 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1825 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1826 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1827 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1828 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1829 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1830 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1831 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1832 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1833 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1834 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1835 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1836 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1837 0xf2800240, 0xfe800f50,
1838 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1839 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1840 0xf2800640, 0xfe800f50,
1841 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1842 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1843 0xf2800a40, 0xfe800f50,
1844 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 1845 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1846 0xf2800e40, 0xff800f50,
1847 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1848 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1849 0xf2800f40, 0xff800f50,
1850 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1851 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1852 0xf3800e40, 0xff800f50,
1853 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1854 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1855 0xf3800f40, 0xff800f50,
1856 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1857 },
16980d0b 1858
fe56b6ce 1859 /* Element and structure load/store. */
823d2571
TG		 1860 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1861 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1862 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1863 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1864 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1865 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1866 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1867 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1868 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1869 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1870 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1871 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1872 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1873 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1874 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1875 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1876 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1877 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1878 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1879 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1880 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1881 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1882 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1883 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1884 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1885 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1886 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1887 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1888 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1889 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1890 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1891 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1892 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1893 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1894 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1895 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1896 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1897 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1898
1899 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 1900};
1901
73cd51e5
AV		 1902/* mve opcode table. */
1903
1904/* print_insn_mve recognizes the following format control codes:
1905
1906 %% %
1907
ef1576a1
AV		 1908 %a print '+' or '-' or imm offset in vldr[bhwd] and
1909 vstr[bhwd]
9743db03 1910 %c print condition code
aef6d006
AV		 1911 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
1912 %u print 'U' (unsigned) or 'S' for various mve instructions
143275ea 1913 %i print MVE predicate(s) for vpt and vpst
bf0b396d 1914 %m print rounding mode for vcvt and vrint
143275ea 1915 %n print vector comparison code for predicated instruction
bf0b396d 1916 %s print size for various vcvt instructions
143275ea
AV		 1917 %v print vector predicate for instruction in predicated
1918 block
ef1576a1 1919 %o print offset scaled for vldr[hwd] and vstr[hwd]
04d54ace
AV		 1920 %w print writeback mode for MVE v{st,ld}[24]
1921 %B print v{st,ld}[24] any one operands
c507f10b
AV		 1922 %E print vmov, vmvn, vorr, vbic encoded constant
1923 %N print generic index for vmov
14925797 1924 %T print bottom ('b') or top ('t') of source register
04d54ace 1925
9743db03 1926 %<bitfield>r print as an ARM register
04d54ace 1927 %<bitfield>d print the bitfield in decimal
143275ea 1928 %<bitfield>Q print as a MVE Q register
c507f10b 1929 %<bitfield>F print as a MVE S register
143275ea
AV		 1930 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
1931 UNPREDICTABLE
1932 %<bitfield>s print size for vector predicate & non VMOV instructions
ef1576a1 1933 %<bitfield>i print immediate for vstr/vldr reg +/- imm
bf0b396d 1934 %<bitfield>k print immediate for vector conversion instruction
c507f10b 1935 %<bitfield>x print the bitfield in hex.
bf0b396d 1936 */
73cd51e5
AV		 1937
1938static const struct mopcode32 mve_opcodes[] =
1939{
143275ea
AV		 1940 /* MVE. */
1941
1942 {ARM_FEATURE_COPROC (FPU_MVE),
1943 MVE_VPST,
1944 0xfe310f4d, 0xffbf1fff,
1945 "vpst%i"
1946 },
1947
1948 /* Floating point VPT T1. */
1949 {ARM_FEATURE_COPROC (FPU_MVE_FP),
1950 MVE_VPT_FP_T1,
1951 0xee310f00, 0xefb10f50,
1952 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
1953 /* Floating point VPT T2. */
1954 {ARM_FEATURE_COPROC (FPU_MVE_FP),
1955 MVE_VPT_FP_T2,
1956 0xee310f40, 0xefb10f50,
1957 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
1958
1959 /* Vector VPT T1. */
1960 {ARM_FEATURE_COPROC (FPU_MVE),
1961 MVE_VPT_VEC_T1,
1962 0xfe010f00, 0xff811f51,
1963 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
1964 /* Vector VPT T2. */
1965 {ARM_FEATURE_COPROC (FPU_MVE),
1966 MVE_VPT_VEC_T2,
1967 0xfe010f01, 0xff811f51,
1968 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
1969 /* Vector VPT T3. */
1970 {ARM_FEATURE_COPROC (FPU_MVE),
1971 MVE_VPT_VEC_T3,
1972 0xfe011f00, 0xff811f50,
1973 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
1974 /* Vector VPT T4. */
1975 {ARM_FEATURE_COPROC (FPU_MVE),
1976 MVE_VPT_VEC_T4,
1977 0xfe010f40, 0xff811f70,
1978 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
1979 /* Vector VPT T5. */
1980 {ARM_FEATURE_COPROC (FPU_MVE),
1981 MVE_VPT_VEC_T5,
1982 0xfe010f60, 0xff811f70,
1983 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
1984 /* Vector VPT T6. */
1985 {ARM_FEATURE_COPROC (FPU_MVE),
1986 MVE_VPT_VEC_T6,
1987 0xfe011f40, 0xff811f50,
1988 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
1989
c507f10b
AV		 1990 /* Vector VBIC immediate. */
1991 {ARM_FEATURE_COPROC (FPU_MVE),
1992 MVE_VBIC_IMM,
1993 0xef800070, 0xefb81070,
1994 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
1995
1996 /* Vector VBIC register. */
1997 {ARM_FEATURE_COPROC (FPU_MVE),
1998 MVE_VBIC_REG,
1999 0xef100150, 0xffb11f51,
2000 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2001
143275ea
AV		 2002 /* Vector VCMP floating point T1. */
2003 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2004 MVE_VCMP_FP_T1,
2005 0xee310f00, 0xeff1ef50,
2006 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2007
2008 /* Vector VCMP floating point T2. */
2009 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2010 MVE_VCMP_FP_T2,
2011 0xee310f40, 0xeff1ef50,
2012 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2013
2014 /* Vector VCMP T1. */
2015 {ARM_FEATURE_COPROC (FPU_MVE),
2016 MVE_VCMP_VEC_T1,
2017 0xfe010f00, 0xffc1ff51,
2018 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2019 /* Vector VCMP T2. */
2020 {ARM_FEATURE_COPROC (FPU_MVE),
2021 MVE_VCMP_VEC_T2,
2022 0xfe010f01, 0xffc1ff51,
2023 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2024 /* Vector VCMP T3. */
2025 {ARM_FEATURE_COPROC (FPU_MVE),
2026 MVE_VCMP_VEC_T3,
2027 0xfe011f00, 0xffc1ff50,
2028 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2029 /* Vector VCMP T4. */
2030 {ARM_FEATURE_COPROC (FPU_MVE),
2031 MVE_VCMP_VEC_T4,
2032 0xfe010f40, 0xffc1ff70,
2033 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2034 /* Vector VCMP T5. */
2035 {ARM_FEATURE_COPROC (FPU_MVE),
2036 MVE_VCMP_VEC_T5,
2037 0xfe010f60, 0xffc1ff70,
2038 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2039 /* Vector VCMP T6. */
2040 {ARM_FEATURE_COPROC (FPU_MVE),
2041 MVE_VCMP_VEC_T6,
2042 0xfe011f40, 0xffc1ff50,
2043 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2044
9743db03
AV		 2045 /* Vector VDUP. */
2046 {ARM_FEATURE_COPROC (FPU_MVE),
2047 MVE_VDUP,
2048 0xeea00b10, 0xffb10f5f,
2049 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2050
2051 /* Vector VEOR. */
2052 {ARM_FEATURE_COPROC (FPU_MVE),
2053 MVE_VEOR,
2054 0xff000150, 0xffd11f51,
2055 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2056
2057 /* Vector VFMA, vector * scalar. */
2058 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2059 MVE_VFMA_FP_SCALAR,
2060 0xee310e40, 0xefb11f70,
2061 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2062
2063 /* Vector VFMA floating point. */
2064 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2065 MVE_VFMA_FP,
2066 0xef000c50, 0xffa11f51,
2067 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2068
2069 /* Vector VFMS floating point. */
2070 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2071 MVE_VFMS_FP,
2072 0xef200c50, 0xffa11f51,
2073 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2074
2075 /* Vector VFMAS, vector * scalar. */
2076 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2077 MVE_VFMAS_FP_SCALAR,
2078 0xee311e40, 0xefb11f70,
2079 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2080
2081 /* Vector VHADD T1. */
2082 {ARM_FEATURE_COPROC (FPU_MVE),
2083 MVE_VHADD_T1,
2084 0xef000040, 0xef811f51,
2085 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2086
2087 /* Vector VHADD T2. */
2088 {ARM_FEATURE_COPROC (FPU_MVE),
2089 MVE_VHADD_T2,
2090 0xee000f40, 0xef811f70,
2091 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2092
2093 /* Vector VHSUB T1. */
2094 {ARM_FEATURE_COPROC (FPU_MVE),
2095 MVE_VHSUB_T1,
2096 0xef000240, 0xef811f51,
2097 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2098
2099 /* Vector VHSUB T2. */
2100 {ARM_FEATURE_COPROC (FPU_MVE),
2101 MVE_VHSUB_T2,
2102 0xee001f40, 0xef811f70,
2103 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2104
2105 /* Vector VDUP. */
2106 {ARM_FEATURE_COPROC (FPU_MVE),
2107 MVE_VDUP,
2108 0xeea00b10, 0xffb10f5f,
2109 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2110
2111 /* Vector VRHADD. */
2112 {ARM_FEATURE_COPROC (FPU_MVE),
2113 MVE_VRHADD,
2114 0xef000140, 0xef811f51,
2115 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2116
bf0b396d
AV		 2117 /* Vector VCVT. */
2118 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2119 MVE_VCVT_FP_FIX_VEC,
2120 0xef800c50, 0xef801cd1,
2121 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2122
2123 /* Vector VCVT. */
2124 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2125 MVE_VCVT_BETWEEN_FP_INT,
2126 0xffb30640, 0xffb31e51,
2127 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2128
2129 /* Vector VCVT between single and half-precision float, bottom half. */
2130 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2131 MVE_VCVT_FP_HALF_FP,
2132 0xee3f0e01, 0xefbf1fd1,
2133 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2134
2135 /* Vector VCVT between single and half-precision float, top half. */
2136 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2137 MVE_VCVT_FP_HALF_FP,
2138 0xee3f1e01, 0xefbf1fd1,
2139 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2140
2141 /* Vector VCVT. */
2142 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2143 MVE_VCVT_FROM_FP_TO_INT,
2144 0xffb30040, 0xffb31c51,
2145 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2146
04d54ace
AV		 2147 /* Vector VLD2. */
2148 {ARM_FEATURE_COPROC (FPU_MVE),
2149 MVE_VLD2,
2150 0xfc901e00, 0xff901e5f,
2151 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2152
2153 /* Vector VLD4. */
2154 {ARM_FEATURE_COPROC (FPU_MVE),
2155 MVE_VLD4,
2156 0xfc901e01, 0xff901e1f,
2157 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2158
ef1576a1
AV		 2159 /* Vector VLDRB gather load. */
2160 {ARM_FEATURE_COPROC (FPU_MVE),
2161 MVE_VLDRB_GATHER_T1,
2162 0xec900e00, 0xefb01e50,
2163 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2164
2165 /* Vector VLDRH gather load. */
2166 {ARM_FEATURE_COPROC (FPU_MVE),
2167 MVE_VLDRH_GATHER_T2,
2168 0xec900e10, 0xefb01e50,
2169 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2170
2171 /* Vector VLDRW gather load. */
2172 {ARM_FEATURE_COPROC (FPU_MVE),
2173 MVE_VLDRW_GATHER_T3,
2174 0xfc900f40, 0xffb01fd0,
2175 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2176
2177 /* Vector VLDRD gather load. */
2178 {ARM_FEATURE_COPROC (FPU_MVE),
2179 MVE_VLDRD_GATHER_T4,
2180 0xec900fd0, 0xefb01fd0,
2181 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2182
2183 /* Vector VLDRW gather load. */
2184 {ARM_FEATURE_COPROC (FPU_MVE),
2185 MVE_VLDRW_GATHER_T5,
2186 0xfd101e00, 0xff111f00,
2187 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2188
2189 /* Vector VLDRD gather load, variant T6. */
2190 {ARM_FEATURE_COPROC (FPU_MVE),
2191 MVE_VLDRD_GATHER_T6,
2192 0xfd101f00, 0xff111f00,
2193 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2194
aef6d006
AV		 2195 /* Vector VLDRB. */
2196 {ARM_FEATURE_COPROC (FPU_MVE),
2197 MVE_VLDRB_T1,
2198 0xec100e00, 0xee581e00,
2199 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2200
2201 /* Vector VLDRH. */
2202 {ARM_FEATURE_COPROC (FPU_MVE),
2203 MVE_VLDRH_T2,
2204 0xec180e00, 0xee581e00,
2205 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2206
2207 /* Vector VLDRB unsigned, variant T5. */
2208 {ARM_FEATURE_COPROC (FPU_MVE),
2209 MVE_VLDRB_T5,
2210 0xec101e00, 0xfe101f80,
2211 "vldrb%v.u8\t%13-15,22Q, %d"},
2212
2213 /* Vector VLDRH unsigned, variant T6. */
2214 {ARM_FEATURE_COPROC (FPU_MVE),
2215 MVE_VLDRH_T6,
2216 0xec101e80, 0xfe101f80,
2217 "vldrh%v.u16\t%13-15,22Q, %d"},
2218
2219 /* Vector VLDRW unsigned, variant T7. */
2220 {ARM_FEATURE_COPROC (FPU_MVE),
2221 MVE_VLDRW_T7,
2222 0xec101f00, 0xfe101f80,
2223 "vldrw%v.u32\t%13-15,22Q, %d"},
2224
c507f10b
AV		 2225 /* Vector VMOV between gpr and half precision register, op == 0. */
2226 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2227 MVE_VMOV_HFP_TO_GP,
2228 0xee000910, 0xfff00f7f,
2229 "vmov.f16\t%7,16-19F, %12-15r"},
2230
2231 /* Vector VMOV between gpr and half precision register, op == 1. */
2232 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2233 MVE_VMOV_HFP_TO_GP,
2234 0xee100910, 0xfff00f7f,
2235 "vmov.f16\t%12-15r, %7,16-19F"},
2236
2237 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2238 MVE_VMOV_GP_TO_VEC_LANE,
2239 0xee000b10, 0xff900f1f,
2240 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2241
2242 /* Vector VORR immediate to vector.
2243 NOTE: MVE_VORR_IMM must appear in the table
2244 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2245 {ARM_FEATURE_COPROC (FPU_MVE),
2246 MVE_VORR_IMM,
2247 0xef800050, 0xefb810f0,
2248 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2249
2250 /* Vector VMOV immediate to vector,
2251 cmode == 11x1 -> VMVN which is UNDEFINED
2252 for such a cmode. */
2253 {ARM_FEATURE_COPROC (FPU_MVE),
2254 MVE_VMVN_IMM, 0xef800d50, 0xefb81dd0, UNDEFINED_INSTRUCTION},
2255
2256 /* Vector VMOV immediate to vector. */
2257 {ARM_FEATURE_COPROC (FPU_MVE),
2258 MVE_VMOV_IMM_TO_VEC,
2259 0xef800050, 0xefb810d0,
2260 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2261
2262 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2263 {ARM_FEATURE_COPROC (FPU_MVE),
2264 MVE_VMOV2_VEC_LANE_TO_GP,
2265 0xec000f00, 0xffb01ff0,
2266 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2267
2268 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2269 {ARM_FEATURE_COPROC (FPU_MVE),
2270 MVE_VMOV2_VEC_LANE_TO_GP,
2271 0xec000f10, 0xffb01ff0,
2272 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2273
2274 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2275 {ARM_FEATURE_COPROC (FPU_MVE),
2276 MVE_VMOV2_GP_TO_VEC_LANE,
2277 0xec100f00, 0xffb01ff0,
2278 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2279
2280 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2281 {ARM_FEATURE_COPROC (FPU_MVE),
2282 MVE_VMOV2_GP_TO_VEC_LANE,
2283 0xec100f10, 0xffb01ff0,
2284 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2285
2286 /* Vector VMOV Vector lane to gpr. */
2287 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2288 MVE_VMOV_VEC_LANE_TO_GP,
2289 0xee100b10, 0xff100f1f,
2290 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2291
14925797
AV		 2292 /* Vector VMOVL long. */
2293 {ARM_FEATURE_COPROC (FPU_MVE),
2294 MVE_VMOVL,
2295 0xeea00f40, 0xefa70fd1,
2296 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2297
2298 /* Vector VMOV and narrow. */
2299 {ARM_FEATURE_COPROC (FPU_MVE),
2300 MVE_VMOVN,
2301 0xfe310e81, 0xffb30fd1,
2302 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2303
c507f10b
AV		 2304 /* Floating point move extract. */
2305 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2306 MVE_VMOVX,
2307 0xfeb00a40, 0xffbf0fd0,
2308 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2309
14925797
AV		 2310 /* Vector VMULL integer. */
2311 {ARM_FEATURE_COPROC (FPU_MVE),
2312 MVE_VMULL_INT,
2313 0xee010e00, 0xef810f51,
2314 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2315
2316 /* Vector VMULL polynomial. */
2317 {ARM_FEATURE_COPROC (FPU_MVE),
2318 MVE_VMULL_POLY,
2319 0xee310e00, 0xefb10f51,
2320 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2321
c507f10b
AV		 2322 /* Vector VMVN immediate to vector. */
2323 {ARM_FEATURE_COPROC (FPU_MVE),
2324 MVE_VMVN_IMM,
2325 0xef800070, 0xefb810f0,
2326 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2327
2328 /* Vector VMVN register. */
2329 {ARM_FEATURE_COPROC (FPU_MVE),
2330 MVE_VMVN_REG,
2331 0xffb005c0, 0xffbf1fd1,
2332 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2333
2334 /* Vector VORN, vector bitwise or not. */
2335 {ARM_FEATURE_COPROC (FPU_MVE),
2336 MVE_VORN,
2337 0xef300150, 0xffb11f51,
2338 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2339
2340 /* Vector VORR register. */
2341 {ARM_FEATURE_COPROC (FPU_MVE),
2342 MVE_VORR_REG,
2343 0xef200150, 0xffb11f51,
2344 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2345
14925797
AV		 2346 /* Vector VQDMULL T1 variant. */
2347 {ARM_FEATURE_COPROC (FPU_MVE),
2348 MVE_VQDMULL_T1,
2349 0xee300f01, 0xefb10f51,
2350 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2351
2352 /* Vector VQDMULL T2 variant. */
2353 {ARM_FEATURE_COPROC (FPU_MVE),
2354 MVE_VQDMULL_T2,
2355 0xee300f60, 0xefb10f70,
2356 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2357
2358 /* Vector VQMOVN. */
2359 {ARM_FEATURE_COPROC (FPU_MVE),
2360 MVE_VQMOVN,
2361 0xee330e01, 0xefb30fd1,
2362 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
2363
2364 /* Vector VQMOVUN. */
2365 {ARM_FEATURE_COPROC (FPU_MVE),
2366 MVE_VQMOVUN,
2367 0xee310e81, 0xffb30fd1,
2368 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2369
bf0b396d
AV		 2370 /* Vector VRINT floating point. */
2371 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2372 MVE_VRINT_FP,
2373 0xffb20440, 0xffb31c51,
2374 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2375
04d54ace
AV		 2376 /* Vector VST2 no writeback. */
2377 {ARM_FEATURE_COPROC (FPU_MVE),
2378 MVE_VST2,
2379 0xfc801e00, 0xffb01e5f,
2380 "vst2%5d.%7-8s\t%B, [%16-19r]"},
2381
2382 /* Vector VST2 writeback. */
2383 {ARM_FEATURE_COPROC (FPU_MVE),
2384 MVE_VST2,
2385 0xfca01e00, 0xffb01e5f,
2386 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
2387
2388 /* Vector VST4 no writeback. */
2389 {ARM_FEATURE_COPROC (FPU_MVE),
2390 MVE_VST4,
2391 0xfc801e01, 0xffb01e1f,
2392 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
2393
2394 /* Vector VST4 writeback. */
2395 {ARM_FEATURE_COPROC (FPU_MVE),
2396 MVE_VST4,
2397 0xfca01e01, 0xffb01e1f,
2398 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
2399
ef1576a1
AV		 2400 /* Vector VSTRB scatter store, T1 variant. */
2401 {ARM_FEATURE_COPROC (FPU_MVE),
2402 MVE_VSTRB_SCATTER_T1,
2403 0xec800e00, 0xffb01e50,
2404 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2405
2406 /* Vector VSTRH scatter store, T2 variant. */
2407 {ARM_FEATURE_COPROC (FPU_MVE),
2408 MVE_VSTRH_SCATTER_T2,
2409 0xec800e10, 0xffb01e50,
2410 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2411
2412 /* Vector VSTRW scatter store, T3 variant. */
2413 {ARM_FEATURE_COPROC (FPU_MVE),
2414 MVE_VSTRW_SCATTER_T3,
2415 0xec800e40, 0xffb01e50,
2416 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2417
2418 /* Vector VSTRD scatter store, T4 variant. */
2419 {ARM_FEATURE_COPROC (FPU_MVE),
2420 MVE_VSTRD_SCATTER_T4,
2421 0xec800fd0, 0xffb01fd0,
2422 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2423
2424 /* Vector VSTRW scatter store, T5 variant. */
2425 {ARM_FEATURE_COPROC (FPU_MVE),
2426 MVE_VSTRW_SCATTER_T5,
2427 0xfd001e00, 0xff111f00,
2428 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2429
2430 /* Vector VSTRD scatter store, T6 variant. */
2431 {ARM_FEATURE_COPROC (FPU_MVE),
2432 MVE_VSTRD_SCATTER_T6,
2433 0xfd001f00, 0xff111f00,
2434 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2435
aef6d006
AV		 2436 /* Vector VSTRB. */
2437 {ARM_FEATURE_COPROC (FPU_MVE),
2438 MVE_VSTRB_T1,
2439 0xec000e00, 0xfe581e00,
2440 "vstrb%v.%7-8s\t%13-15Q, %d"},
2441
2442 /* Vector VSTRH. */
2443 {ARM_FEATURE_COPROC (FPU_MVE),
2444 MVE_VSTRH_T2,
2445 0xec080e00, 0xfe581e00,
2446 "vstrh%v.%7-8s\t%13-15Q, %d"},
2447
2448 /* Vector VSTRB variant T5. */
2449 {ARM_FEATURE_COPROC (FPU_MVE),
2450 MVE_VSTRB_T5,
2451 0xec001e00, 0xfe101f80,
2452 "vstrb%v.8\t%13-15,22Q, %d"},
2453
2454 /* Vector VSTRH variant T6. */
2455 {ARM_FEATURE_COPROC (FPU_MVE),
2456 MVE_VSTRH_T6,
2457 0xec001e80, 0xfe101f80,
2458 "vstrh%v.16\t%13-15,22Q, %d"},
2459
2460 /* Vector VSTRW variant T7. */
2461 {ARM_FEATURE_COPROC (FPU_MVE),
2462 MVE_VSTRW_T7,
2463 0xec001f00, 0xfe101f80,
2464 "vstrw%v.32\t%13-15,22Q, %d"},
2465
143275ea
AV		 2466 {ARM_FEATURE_CORE_LOW (0),
2467 MVE_NONE,
2468 0x00000000, 0x00000000, 0}
73cd51e5
AV		 2469};
2470
8f06b2d8
PB		 2471/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
2472 ordered: they must be searched linearly from the top to obtain a correct
2473 match. */
2474
2475/* print_insn_arm recognizes the following format control codes:
2476
2477 %% %
2478
2479 %a print address for ldr/str instruction
2480 %s print address for ldr/str halfword/signextend instruction
c1e26897 2481 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 2482 %b print branch destination
2483 %c print condition code (always bits 28-31)
2484 %m print register mask for ldm/stm instruction
2485 %o print operand2 (immediate or register + shift)
2486 %p print 'p' iff bits 12-15 are 15
2487 %t print 't' iff bit 21 set and bit 24 clear
2488 %B print arm BLX(1) destination
2489 %C print the PSR sub type.
62b3e311
PB		 2490 %U print barrier type.
2491 %P print address for pli instruction.
8f06b2d8
PB		 2492
2493 %<bitfield>r print as an ARM register
9eb6c0f1 2494 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 2495 %<bitfield>R as %r but r15 is UNPREDICTABLE
2496 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
2497 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 2498 %<bitfield>d print the bitfield in decimal
43e65147 2499 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 2500 %<bitfield>x print the bitfield in hex
2501 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 2502
16980d0b
JB		 2503 %<bitfield>'c print specified char iff bitfield is all ones
2504 %<bitfield>`c print specified char iff bitfield is all zeroes
2505 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 2506
8f06b2d8
PB		 2507 %e print arm SMI operand (bits 0..7,8..19).
2508 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 2509 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
2510 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 2511
8f06b2d8
PB		 2512static const struct opcode32 arm_opcodes[] =
2513{
2514 /* ARM instructions. */
823d2571
TG		 2515 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2516 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
2517 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2518 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
2519
2520 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
2521 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
2522 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
2523 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
2524 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
2525 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2526 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
2527 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
2528 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
2529 0x00800090, 0x0fa000f0,
2530 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2531 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
2532 0x00a00090, 0x0fa000f0,
2533 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 2534
105bde57 2535 /* V8.2 RAS extension instructions. */
4d1464f2 2536 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 2537 0xe320f010, 0xffffffff, "esb"},
2538
53c4b28b 2539 /* V8 instructions. */
823d2571
TG		 2540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2541 0x0320f005, 0x0fffffff, "sevl"},
f7dd2fb2
TC		 2542 /* Defined in V8 but is in NOP space so available to all arch. */
2543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
823d2571 2544 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
4ed7ed8d 2545 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 2546 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 2547 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 2548 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2550 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
2551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2552 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 2553 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2554 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 2555 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2556 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 2557 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2558 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 2559 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2560 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 2561 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2562 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 2563 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2564 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 2565 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2566 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 2567 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2568 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 2569 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2570 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 2571 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 2572 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 2573 /* CRC32 instructions. */
823d2571
TG		 2574 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2575 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
2576 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2577 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
2578 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2579 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
2580 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2581 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
2582 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2583 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
2584 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2585 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 2586
ddfded2f
MW		 2587 /* Privileged Access Never extension instructions. */
2588 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
2589 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
2590
90ec0d68 2591 /* Virtualization Extension instructions. */
823d2571
TG		 2592 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
2593 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 2594
eea54501 2595 /* Integer Divide Extension instructions. */
823d2571
TG		 2596 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
2597 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
2598 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
2599 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 2600
60e5ef9f 2601 /* MP Extension instructions. */
823d2571 2602 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 2603
c597cc3d
SD		 2604 /* Speculation Barriers. */
2605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
2606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
2607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
2608
62b3e311 2609 /* V7 instructions. */
823d2571
TG		 2610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
2611 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
2612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
2613 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
2614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
2615 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
2616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a
AV		 2617 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2618 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
62b3e311 2619
c19d1205 2620 /* ARM V6T2 instructions. */
823d2571
TG		 2621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2622 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
2623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2624 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
2625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2626 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2627 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2628 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
2629
2630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2631 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
2632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2633 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
2634
ff8646ee 2635 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 2636 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 2637 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2638 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
2639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2640 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
2641 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2642 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 2643
f4c65163 2644 /* ARM Security extension instructions. */
823d2571
TG		 2645 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
2646 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 2647
8f06b2d8 2648 /* ARM V6K instructions. */
823d2571
TG		 2649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2650 0xf57ff01f, 0xffffffff, "clrex"},
2651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2652 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
2653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2654 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
2655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2656 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
2657 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2658 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
2659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2660 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
2661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2662 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 2663
7fadb25d
SD		 2664 /* ARMv8.5-A instructions. */
2665 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
2666
8f06b2d8 2667 /* ARM V6K NOP hints. */
823d2571
TG		 2668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2669 0x0320f001, 0x0fffffff, "yield%c"},
2670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2671 0x0320f002, 0x0fffffff, "wfe%c"},
2672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2673 0x0320f003, 0x0fffffff, "wfi%c"},
2674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2675 0x0320f004, 0x0fffffff, "sev%c"},
2676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2677 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 2678
fe56b6ce 2679 /* ARM V6 instructions. */
823d2571
TG		 2680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2681 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
2682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2683 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
2684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2685 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
2686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2687 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
2688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2689 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
2690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2691 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
2692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2693 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
2694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2695 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
2696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2697 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
2698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2699 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
2700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2701 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
2702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2703 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
2704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2705 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
2706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2707 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
2708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2709 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
2710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2711 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
2712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2713 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
2714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2715 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
2716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2717 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
2718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2719 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
2720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2721 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
2722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2723 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
2724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2725 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
2726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2727 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
2728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2729 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
2730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2731 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
2732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2733 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
2734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2735 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
2736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2737 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
2738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2739 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
2740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2741 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
2742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2743 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
2744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2745 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
2746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2747 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
2748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2749 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
2750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2751 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
2752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2753 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
2754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2755 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
2756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2757 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
2758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2759 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
2760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2761 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
2762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2763 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
2764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2765 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
2766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2767 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
2768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2769 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
2770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2771 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
2772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2773 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
2774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2775 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
2776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2777 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
2778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2779 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
2780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2781 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
2782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2783 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
2784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2785 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
2786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2787 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
2788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2789 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
2790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2791 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
2792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2793 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
2794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2795 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
2796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2797 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
2798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2799 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
2800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2801 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
2802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2803 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
2804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2805 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
2806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2807 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
2808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2809 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
2810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2811 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
2812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2813 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
2814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2815 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
2816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2817 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
2818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2819 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
2820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2821 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
2822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2823 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
2824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2825 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
2826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2827 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
2828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2829 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
2830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2831 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2833 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2835 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2837 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
2838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2839 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2841 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2843 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2845 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
2846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2847 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2849 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2851 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2853 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
2854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2855 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2857 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2859 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2861 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
2862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2863 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2865 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2867 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
2868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2869 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
2870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2871 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2873 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2875 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2877 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
2878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2879 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
2880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2881 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
2882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2883 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
2884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2885 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2887 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2889 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2891 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2893 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
2894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2895 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2897 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2899 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
2900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2901 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
2902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2903 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
2904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2905 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
2906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2907 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
2908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2909 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
2910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2911 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
2912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2913 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
2914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2915 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2917 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
2918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2919 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
2920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2921 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
2922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2923 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 2924
8f06b2d8 2925 /* V5J instruction. */
823d2571
TG		 2926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
2927 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 2928
8f06b2d8 2929 /* V5 Instructions. */
823d2571
TG		 2930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2931 0xe1200070, 0xfff000f0,
2932 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
2933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2934 0xfa000000, 0xfe000000, "blx\t%B"},
2935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2936 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
2937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2938 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
2939
2940 /* V5E "El Segundo" Instructions. */
2941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2942 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
2943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2944 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
2945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2946 0xf450f000, 0xfc70f000, "pld\t%a"},
2947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2948 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2950 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2952 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2954 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
2955
2956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2957 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2959 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
2960
2961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2962 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2964 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2966 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2968 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2969
2970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2971 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2973 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2975 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2977 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2978
2979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2980 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2982 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2983
2984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2985 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
2986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2987 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2989 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
2990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2991 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 2992
8f06b2d8 2993 /* ARM Instructions. */
823d2571
TG		 2994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2995 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2996
2997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2998 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3000 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
3001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3002 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
3003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3004 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
3005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3006 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
3007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3008 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
3009
3010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3011 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
3012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3013 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
3014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3015 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
3016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3017 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
3018
3019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3020 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
3021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3022 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
3023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3024 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
3025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3026 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
3027
3028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3029 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
3030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3031 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
3032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3033 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
3034
3035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3036 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
3037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3038 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
3039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3040 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
3041
3042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3043 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
3044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3045 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
3046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3047 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
3048
3049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3050 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3052 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3054 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
3055
3056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3057 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
3058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3059 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
3060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3061 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
3062
3063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3064 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
3065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3066 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
3067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3068 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
3069
3070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3071 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3073 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3075 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
3076
3077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3078 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3080 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3082 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
3083
3084 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
3085 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
3086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
3087 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
3088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
3089 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
3090
3091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3092 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
3093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3094 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
3095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3096 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
3097
3098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 3099 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 3100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 3101 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 3102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 3103 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
823d2571
TG		 3104
3105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3106 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
3107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3108 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
3109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3110 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
3111
3112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3113 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
3114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3115 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
3116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3117 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
3118
3119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3120 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
3121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3122 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
3123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3124 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
3125
3126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3127 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
3128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3129 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
3130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3131 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
3132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3133 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
3134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3135 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
3136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3137 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
3138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3139 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
3140
3141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3142 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
3143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3144 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
3145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3146 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
3147
3148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3149 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
3150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3151 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
3152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3153 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
3154
3155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3156 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
3157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3158 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
3159
3160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3161 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
3162
3163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3164 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
3165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3166 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
3167
3168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3169 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3171 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3173 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3175 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3177 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3179 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3181 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3183 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3185 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3187 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3189 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3191 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3193 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3195 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3196 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3197 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3199 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3201 0x092d0000, 0x0fff0000, "push%c\t%m"},
3202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3203 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
3204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3205 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3206
3207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3208 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3210 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3212 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3214 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3216 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3217 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3218 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3220 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3222 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3224 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3226 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3228 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3230 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3232 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3234 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3236 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3238 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3240 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
3241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3242 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
3243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3244 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3245
3246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3247 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
3248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3249 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 3250
3251 /* The rest. */
4ab90a7a
AV		 3252 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3253 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 3254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3255 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3256 {ARM_FEATURE_CORE_LOW (0),
3257 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 3258};
3259
3260/* print_insn_thumb16 recognizes the following format control codes:
3261
3262 %S print Thumb register (bits 3..5 as high number if bit 6 set)
3263 %D print Thumb register (bits 0..2 as high number if bit 7 set)
3264 %<bitfield>I print bitfield as a signed decimal
3265 (top bit of range being the sign bit)
3266 %N print Thumb register mask (with LR)
3267 %O print Thumb register mask (with PC)
3268 %M print Thumb register mask
3269 %b print CZB's 6-bit unsigned branch destination
3270 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 3271 %c print the condition code
3272 %C print the condition code, or "s" if not conditional
3273 %x print warning if conditional an not at end of IT block"
3274 %X print "\t; unpredictable <IT:code>" if conditional
3275 %I print IT instruction suffix and operands
4547cb56 3276 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 3277 %<bitfield>r print bitfield as an ARM register
3278 %<bitfield>d print bitfield as a decimal
3279 %<bitfield>H print (bitfield * 2) as a decimal
3280 %<bitfield>W print (bitfield * 4) as a decimal
3281 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
3282 %<bitfield>B print Thumb branch destination (signed displacement)
3283 %<bitfield>c print bitfield as a condition code
3284 %<bitnum>'c print specified char iff bit is one
3285 %<bitnum>?ab print a if bit is one else print b. */
3286
3287static const struct opcode16 thumb_opcodes[] =
3288{
3289 /* Thumb instructions. */
3290
16a1fa25
TP		 3291 /* ARMv8-M Security Extensions instructions. */
3292 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
e207bc53 3293 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
16a1fa25 3294
53c4b28b 3295 /* ARM V8 instructions. */
823d2571
TG		 3296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
3297 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
ddfded2f 3298 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
53c4b28b 3299
8f06b2d8 3300 /* ARM V6K no-argument instructions. */
823d2571
TG		 3301 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
3302 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
3303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
3304 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
3305 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
3306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 3307
3308 /* ARM V6T2 instructions. */
ff8646ee
TP		 3309 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3310 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
3311 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3312 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 3313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 3314
3315 /* ARM V6. */
823d2571
TG		 3316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
3317 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
3318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
3319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
3320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
3321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
3322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
3323 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
3324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
3325 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
3326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 3327
3328 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 3329 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
3330 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 3331 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 3332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
3333 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 3334 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 3335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3336 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 3337 /* Format 4. */
823d2571
TG		 3338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
3339 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
3340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
3341 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
3342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
3343 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
3344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
3345 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
3346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
3347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
3348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
3349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
3350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
3351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
3352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
3353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 3354 /* format 13 */
823d2571
TG		 3355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
3356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 3357 /* format 5 */
823d2571
TG		 3358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
3359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
3360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
3361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 3362 /* format 14 */
823d2571
TG		 3363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
3364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 3365 /* format 2 */
823d2571
TG		 3366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3367 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
3368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3369 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
3370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3371 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
3372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3373 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 3374 /* format 8 */
823d2571
TG		 3375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3376 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
3377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3378 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
3379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3380 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 3381 /* format 7 */
823d2571
TG		 3382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3383 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
3384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3385 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 3386 /* format 1 */
823d2571
TG		 3387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
3388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3389 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
3390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
3391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 3392 /* format 3 */
823d2571
TG		 3393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
3394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
3395 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
3396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 3397 /* format 6 */
823d2571
TG		 3398 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
3399 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3400 0x4800, 0xF800,
3401 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 3402 /* format 9 */
823d2571
TG		 3403 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3404 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
3405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3406 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
3407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3408 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
3409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3410 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 3411 /* format 10 */
823d2571
TG		 3412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3413 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
3414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3415 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 3416 /* format 11 */
823d2571
TG		 3417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3418 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
3419 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3420 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 3421 /* format 12 */
823d2571
TG		 3422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3423 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
3424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3425 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 3426 /* format 15 */
823d2571
TG		 3427 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
3428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 3429 /* format 17 */
823d2571 3430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 3431 /* format 16 */
823d2571
TG		 3432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
3433 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
3434 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 3435 /* format 18 */
823d2571 3436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 3437
3438 /* The E800 .. FFFF range is unconditionally redirected to the
3439 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
3440 are processed via that table. Thus, we can never encounter a
3441 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 3442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
3443 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 3444};
3445
3446/* Thumb32 opcodes use the same table structure as the ARM opcodes.
3447 We adopt the convention that hw1 is the high 16 bits of .value and
3448 .mask, hw2 the low 16 bits.
3449
3450 print_insn_thumb32 recognizes the following format control codes:
3451
3452 %% %
3453
3454 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
3455 %M print a modified 12-bit immediate (same location)
3456 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
3457 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 3458 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 3459 %S print a possibly-shifted Rm
3460
32a94698 3461 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 3462 %a print the address of a plain load/store
3463 %w print the width and signedness of a core load/store
3464 %m print register mask for ldm/stm
4b5a202f 3465 %n print register mask for clrm
8f06b2d8
PB		 3466
3467 %E print the lsb and width fields of a bfc/bfi instruction
3468 %F print the lsb and width fields of a sbfx/ubfx instruction
e12437dc 3469 %G print a fallback offset for Branch Future instructions
e5d6e09e 3470 %W print an offset for BF instruction
1caf72a5 3471 %Y print an offset for BFL instruction
1889da70 3472 %Z print an offset for BFCSEL instruction
60f993ce
AV		 3473 %Q print an offset for Low Overhead Loop instructions
3474 %P print an offset for Low Overhead Loop end instructions
8f06b2d8
PB		 3475 %b print a conditional branch offset
3476 %B print an unconditional branch offset
3477 %s print the shift field of an SSAT instruction
3478 %R print the rotation field of an SXT instruction
62b3e311
PB		 3479 %U print barrier type.
3480 %P print address for pli instruction.
c22aaad1
PB		 3481 %c print the condition code
3482 %x print warning if conditional an not at end of IT block"
3483 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 3484
3485 %<bitfield>d print bitfield in decimal
f0fba320 3486 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 3487 %<bitfield>W print bitfield*4 in decimal
3488 %<bitfield>r print bitfield as an ARM register
dd5181d5 3489 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
f1c7f421 3490 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
8f06b2d8
PB		 3491 %<bitfield>c print bitfield as a condition code
3492
16980d0b
JB		 3493 %<bitfield>'c print specified char iff bitfield is all ones
3494 %<bitfield>`c print specified char iff bitfield is all zeroes
3495 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 3496
3497 With one exception at the bottom (done because BL and BLX(1) need
3498 to come dead last), this table was machine-sorted first in
3499 decreasing order of number of bits set in the mask, then in
3500 increasing numeric order of mask, then in increasing numeric order
3501 of opcode. This order is not the clearest for a human reader, but
3502 is guaranteed never to catch a special-case bit pattern with a more
3503 general mask, which is important, because this instruction encoding
3504 makes heavy use of special-case bit patterns. */
3505static const struct opcode32 thumb32_opcodes[] =
3506{
4b5a202f
AV		 3507 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
3508 instructions. */
60f993ce
AV		 3509 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3510 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
3511 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3512 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
3513 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3514 0xf02fc001, 0xfffff001, "le\t%P"},
3515 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3516 0xf00fc001, 0xfffff001, "le\tlr, %P"},
3517
4389b29a
AV		 3518 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3519 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
f1c7f421
AV		 3520 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3521 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
65d1bc05
AV		 3522 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3523 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
f1c7f421
AV		 3524 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3525 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
f6b2b12d
AV		 3526 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3527 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4389b29a 3528
4b5a202f
AV		 3529 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3530 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4389b29a 3531
16a1fa25
TP		 3532 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
3533 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4ed7ed8d
TP		 3534 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3535 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
3536 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3537 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
16a1fa25
TP		 3538 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3539 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
3540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3541 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4ed7ed8d 3542
105bde57 3543 /* ARM V8.2 RAS extension instructions. */
4d1464f2 3544 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 3545 0xf3af8010, 0xffffffff, "esb"},
3546
53c4b28b 3547 /* V8 instructions. */
823d2571
TG		 3548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3549 0xf3af8005, 0xffffffff, "sevl%c.w"},
3550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3551 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
3552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3553 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
3554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3555 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
3556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3557 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
3558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3559 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
3560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3561 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
3562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3563 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
3564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3565 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
3566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3567 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3569 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3571 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
3572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3573 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3575 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3577 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3579 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 3580
dd5181d5 3581 /* CRC32 instructions. */
823d2571 3582 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 3583 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
823d2571 3584 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 3585 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
823d2571 3586 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 3587 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
823d2571 3588 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 3589 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
823d2571 3590 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 3591 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
823d2571 3592 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 3593 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
dd5181d5 3594
c597cc3d
SD		 3595 /* Speculation Barriers. */
3596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
3597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
3598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
3599
62b3e311 3600 /* V7 instructions. */
823d2571
TG		 3601 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
3602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
3603 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
3604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
3605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
3606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
3607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
3608 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
3609 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
3610 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
3611 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 3612
90ec0d68 3613 /* Virtualization Extension instructions. */
823d2571 3614 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 3615 /* We skip ERET as that is SUBS pc, lr, #0. */
3616
60e5ef9f 3617 /* MP Extension instructions. */
823d2571 3618 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 3619
f4c65163 3620 /* Security extension instructions. */
823d2571 3621 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 3622
7fadb25d
SD		 3623 /* ARMv8.5-A instructions. */
3624 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
3625
8f06b2d8 3626 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 3627 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
3628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
3629 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
3630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
3631 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
3632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3633 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
3634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
3635
ff8646ee 3636 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3637 0xf3bf8f2f, 0xffffffff, "clrex%c"},
3638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3639 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
3640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3641 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
3642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3643 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
3644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3645 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
3646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3647 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
3648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3649 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
3650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3651 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
3652 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3653 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
3654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3655 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
3656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3657 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
3658 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3659 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
3660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3661 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
3662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3663 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 3664 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 3665 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 3666 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3667 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
3668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3669 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
3670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3671 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
3672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3673 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
3674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3675 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
3676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3677 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
3678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3679 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
3680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3681 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
3682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3683 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 3684 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3685 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
3686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3687 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
3688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3689 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
3690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3691 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
3692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3693 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
3694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3695 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
3696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3697 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
3698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3699 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
3700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3701 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
3702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3703 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
3704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3705 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
3706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3707 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
3708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3709 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
3710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3711 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
3712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3713 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
3714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3715 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
3716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3717 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
3718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3719 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
3720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3721 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
3722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3723 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
3724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3725 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
3726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3727 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
3728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3729 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
3730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3731 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
3732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3733 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
3734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3735 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
3736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3737 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
3738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3739 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
3740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3741 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
3742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3743 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
3744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3745 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
3746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3747 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
3748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3749 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
3750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3751 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
3752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3753 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
3754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3755 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
3756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3757 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
3758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3759 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
3760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3761 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
3762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3763 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
3764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3765 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
3766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3767 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
3768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3769 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
3770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3771 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
3772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3773 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
3774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3775 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
3776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3777 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
3778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3779 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
3780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3781 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
3782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3783 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
3784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3785 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3787 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3789 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3791 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 3792 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3793 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
3794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 3795 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 3796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3797 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
3798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3799 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
3800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3801 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3803 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
3804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3805 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
3806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3807 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3809 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3811 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3813 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3815 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3817 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3819 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3821 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
3822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3823 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
3824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3825 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
3826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3827 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
3828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3829 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
3830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3831 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
3832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3833 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
3834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3835 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
3836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3837 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
3838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3839 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
3840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3841 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
3842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3843 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
3844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3845 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3847 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3849 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3851 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3853 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3855 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3857 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3859 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 3860 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3861 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
3862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3863 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
3864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3865 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
3866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3867 0xf810f000, 0xff70f000, "pld%c\t%a"},
3868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3869 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3871 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3873 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3875 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3877 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3879 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3881 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3883 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
3884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3885 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
3886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3887 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
3888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3889 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
3890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3891 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
3892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3893 0xfb100000, 0xfff000c0,
3894 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3896 0xfbc00080, 0xfff000c0,
3897 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
3898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3899 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
3900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3901 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
3902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 3903 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 3904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3905 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
3906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3907 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 3908 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3909 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
3910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3911 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 3912 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3913 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
3914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3915 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
3916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3917 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
3918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3919 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
3920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3921 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
3922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3923 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
3924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3925 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
3926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3927 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
3928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3929 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
3930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3931 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
3932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3933 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 3934 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3935 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
3936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3937 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
3938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3939 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
3940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3941 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
3942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3943 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
3944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3945 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
3946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3947 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
3948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3949 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
3950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3951 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
3952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3953 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
3954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3955 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
3956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3957 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
3958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3959 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
3960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3961 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
3962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3963 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
3964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3965 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
3966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3967 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
3968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3969 0xe9400000, 0xff500000,
3970 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3972 0xe9500000, 0xff500000,
3973 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3975 0xe8600000, 0xff700000,
3976 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3978 0xe8700000, 0xff700000,
3979 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3981 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
3982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3983 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 3984
3985 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 3986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3987 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
3988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3989 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
3990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3991 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
3992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3993 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 3994
8f06b2d8 3995 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 3996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3997 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
3998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3999 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 4000
4001 /* Fallback. */
823d2571
TG		 4002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4003 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4004 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 4005};
ff4a8d2b 4006
8f06b2d8
PB		 4007static const char *const arm_conditional[] =
4008{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 4009 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 4010
4011static const char *const arm_fp_const[] =
4012{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
4013
4014static const char *const arm_shift[] =
4015{"lsl", "lsr", "asr", "ror"};
4016
4017typedef struct
4018{
4019 const char *name;
4020 const char *description;
4021 const char *reg_names[16];
4022}
4023arm_regname;
4024
4025static const arm_regname regnames[] =
4026{
65b48a81 4027 { "reg-names-raw", N_("Select raw register names"),
8f06b2d8 4028 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
65b48a81 4029 { "reg-names-gcc", N_("Select register names used by GCC"),
8f06b2d8 4030 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 4031 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
8f06b2d8 4032 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65b48a81
PB		 4033 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
4034 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
4035 { "reg-names-apcs", N_("Select register names used in the APCS"),
8f06b2d8 4036 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 4037 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
8f06b2d8 4038 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
65b48a81
PB		 4039 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
4040 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
8f06b2d8
PB		 4041};
4042
4043static const char *const iwmmxt_wwnames[] =
4044{"b", "h", "w", "d"};
4045
4046static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 4047{"b", "bus", "bc", "bss",
4048 "h", "hus", "hc", "hss",
4049 "w", "wus", "wc", "wss",
4050 "d", "dus", "dc", "dss"
8f06b2d8
PB		 4051};
4052
4053static const char *const iwmmxt_regnames[] =
4054{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
4055 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
4056};
4057
4058static const char *const iwmmxt_cregnames[] =
4059{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
4060 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
4061};
4062
143275ea
AV		 4063static const char *const vec_condnames[] =
4064{ "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
4065};
4066
4067static const char *const mve_predicatenames[] =
4068{ "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
4069 "eee", "ee", "eet", "e", "ett", "et", "ete"
4070};
4071
4072/* Names for 2-bit size field for mve vector isntructions. */
4073static const char *const mve_vec_sizename[] =
4074 { "8", "16", "32", "64"};
4075
4076/* Indicates whether we are processing a then predicate,
4077 else predicate or none at all. */
4078enum vpt_pred_state
4079{
4080 PRED_NONE,
4081 PRED_THEN,
4082 PRED_ELSE
4083};
4084
4085/* Information used to process a vpt block and subsequent instructions. */
4086struct vpt_block
4087{
4088 /* Are we in a vpt block. */
4089 bfd_boolean in_vpt_block;
4090
4091 /* Next predicate state if in vpt block. */
4092 enum vpt_pred_state next_pred_state;
4093
4094 /* Mask from vpt/vpst instruction. */
4095 long predicate_mask;
4096
4097 /* Instruction number in vpt block. */
4098 long current_insn_num;
4099
4100 /* Number of instructions in vpt block.. */
4101 long num_pred_insn;
4102};
4103
4104static struct vpt_block vpt_block_state =
4105{
4106 FALSE,
4107 PRED_NONE,
4108 0,
4109 0,
4110 0
4111};
4112
8f06b2d8
PB		 4113/* Default to GCC register name set. */
4114static unsigned int regname_selected = 1;
4115
65b48a81 4116#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
8f06b2d8
PB		 4117#define arm_regnames regnames[regname_selected].reg_names
4118
4119static bfd_boolean force_thumb = FALSE;
4120
c22aaad1
PB		 4121/* Current IT instruction state. This contains the same state as the IT
4122 bits in the CPSR. */
4123static unsigned int ifthen_state;
4124/* IT state for the next instruction. */
4125static unsigned int ifthen_next_state;
4126/* The address of the insn for which the IT state is valid. */
4127static bfd_vma ifthen_address;
4128#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 4129/* Indicates that the current Conditional state is unconditional or outside
4130 an IT block. */
4131#define COND_UNCOND 16
c22aaad1 4132
8f06b2d8
PB		 4133\f
4134/* Functions. */
143275ea
AV		 4135/* Extract the predicate mask for a VPT or VPST instruction.
4136 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
4137
4138static long
4139mve_extract_pred_mask (long given)
4140{
4141 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
4142}
4143
4144/* Return the number of instructions in a MVE predicate block. */
4145static long
4146num_instructions_vpt_block (long given)
4147{
4148 long mask = mve_extract_pred_mask (given);
4149 if (mask == 0)
4150 return 0;
4151
4152 if (mask == 8)
4153 return 1;
4154
4155 if ((mask & 7) == 4)
4156 return 2;
4157
4158 if ((mask & 3) == 2)
4159 return 3;
4160
4161 if ((mask & 1) == 1)
4162 return 4;
4163
4164 return 0;
4165}
4166
4167static void
4168mark_outside_vpt_block (void)
4169{
4170 vpt_block_state.in_vpt_block = FALSE;
4171 vpt_block_state.next_pred_state = PRED_NONE;
4172 vpt_block_state.predicate_mask = 0;
4173 vpt_block_state.current_insn_num = 0;
4174 vpt_block_state.num_pred_insn = 0;
4175}
4176
4177static void
4178mark_inside_vpt_block (long given)
4179{
4180 vpt_block_state.in_vpt_block = TRUE;
4181 vpt_block_state.next_pred_state = PRED_THEN;
4182 vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
4183 vpt_block_state.current_insn_num = 0;
4184 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
4185 assert (vpt_block_state.num_pred_insn >= 1);
4186}
4187
4188static enum vpt_pred_state
4189invert_next_predicate_state (enum vpt_pred_state astate)
4190{
4191 if (astate == PRED_THEN)
4192 return PRED_ELSE;
4193 else if (astate == PRED_ELSE)
4194 return PRED_THEN;
4195 else
4196 return PRED_NONE;
4197}
4198
4199static enum vpt_pred_state
4200update_next_predicate_state (void)
4201{
4202 long pred_mask = vpt_block_state.predicate_mask;
4203 long mask_for_insn = 0;
4204
4205 switch (vpt_block_state.current_insn_num)
4206 {
4207 case 1:
4208 mask_for_insn = 8;
4209 break;
4210
4211 case 2:
4212 mask_for_insn = 4;
4213 break;
4214
4215 case 3:
4216 mask_for_insn = 2;
4217 break;
4218
4219 case 4:
4220 return PRED_NONE;
4221 }
4222
4223 if (pred_mask & mask_for_insn)
4224 return invert_next_predicate_state (vpt_block_state.next_pred_state);
4225 else
4226 return vpt_block_state.next_pred_state;
4227}
4228
4229static void
4230update_vpt_block_state (void)
4231{
4232 vpt_block_state.current_insn_num++;
4233 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
4234 {
4235 /* No more instructions to process in vpt block. */
4236 mark_outside_vpt_block ();
4237 return;
4238 }
4239
4240 vpt_block_state.next_pred_state = update_next_predicate_state ();
4241}
8f06b2d8 4242
16980d0b
JB		 4243/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
4244 Returns pointer to following character of the format string and
4245 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 4246 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 4247
4248static const char *
fe56b6ce
NC		 4249arm_decode_bitfield (const char *ptr,
4250 unsigned long insn,
4251 unsigned long *valuep,
4252 int *widthp)
16980d0b
JB		 4253{
4254 unsigned long value = 0;
4255 int width = 0;
43e65147
L		 4256
4257 do
16980d0b
JB		 4258 {
4259 int start, end;
4260 int bits;
4261
4262 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
4263 start = start * 10 + *ptr - '0';
4264 if (*ptr == '-')
4265 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
4266 end = end * 10 + *ptr - '0';
4267 else
4268 end = start;
4269 bits = end - start;
4270 if (bits < 0)
4271 abort ();
4272 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
4273 width += bits + 1;
4274 }
4275 while (*ptr++ == ',');
4276 *valuep = value;
4277 if (widthp)
4278 *widthp = width;
4279 return ptr - 1;
4280}
4281
8f06b2d8 4282static void
37b37b2d 4283arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 4284 bfd_boolean print_shift)
8f06b2d8
PB		 4285{
4286 func (stream, "%s", arm_regnames[given & 0xf]);
4287
4288 if ((given & 0xff0) != 0)
4289 {
4290 if ((given & 0x10) == 0)
4291 {
4292 int amount = (given & 0xf80) >> 7;
4293 int shift = (given & 0x60) >> 5;
4294
4295 if (amount == 0)
4296 {
4297 if (shift == 3)
4298 {
4299 func (stream, ", rrx");
4300 return;
4301 }
4302
4303 amount = 32;
4304 }
4305
37b37b2d
RE		 4306 if (print_shift)
4307 func (stream, ", %s #%d", arm_shift[shift], amount);
4308 else
4309 func (stream, ", #%d", amount);
8f06b2d8 4310 }
74bdfecf 4311 else if ((given & 0x80) == 0x80)
aefd8a40 4312 func (stream, "\t; <illegal shifter operand>");
37b37b2d 4313 else if (print_shift)
8f06b2d8
PB		 4314 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
4315 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 4316 else
4317 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 4318 }
4319}
4320
73cd51e5
AV		 4321/* Return TRUE if the MATCHED_INSN can be inside an IT block. */
4322
4323static bfd_boolean
4324is_mve_okay_in_it (enum mve_instructions matched_insn)
4325{
c507f10b
AV		 4326 switch (matched_insn)
4327 {
4328 case MVE_VMOV_GP_TO_VEC_LANE:
4329 case MVE_VMOV2_VEC_LANE_TO_GP:
4330 case MVE_VMOV2_GP_TO_VEC_LANE:
4331 case MVE_VMOV_VEC_LANE_TO_GP:
4332 return TRUE;
4333 default:
4334 return FALSE;
4335 }
73cd51e5
AV		 4336}
4337
4338static bfd_boolean
4339is_mve_architecture (struct disassemble_info *info)
4340{
4341 struct arm_private_data *private_data = info->private_data;
4342 arm_feature_set allowed_arches = private_data->features;
4343
4344 arm_feature_set arm_ext_v8_1m_main
4345 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
4346
4347 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
4348 && !ARM_CPU_IS_ANY (allowed_arches))
4349 return TRUE;
4350 else
4351 return FALSE;
4352}
4353
143275ea
AV		 4354static bfd_boolean
4355is_vpt_instruction (long given)
4356{
4357
4358 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
4359 if ((given & 0x0040e000) == 0)
4360 return FALSE;
4361
4362 /* VPT floating point T1 variant. */
4363 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
4364 /* VPT floating point T2 variant. */
4365 || ((given & 0xefb10f50) == 0xee310f40)
4366 /* VPT vector T1 variant. */
4367 || ((given & 0xff811f51) == 0xfe010f00)
4368 /* VPT vector T2 variant. */
4369 || ((given & 0xff811f51) == 0xfe010f01
4370 && ((given & 0x300000) != 0x300000))
4371 /* VPT vector T3 variant. */
4372 || ((given & 0xff811f50) == 0xfe011f00)
4373 /* VPT vector T4 variant. */
4374 || ((given & 0xff811f70) == 0xfe010f40)
4375 /* VPT vector T5 variant. */
4376 || ((given & 0xff811f70) == 0xfe010f60)
4377 /* VPT vector T6 variant. */
4378 || ((given & 0xff811f50) == 0xfe011f40)
4379 /* VPST vector T variant. */
4380 || ((given & 0xffbf1fff) == 0xfe310f4d))
4381 return TRUE;
4382 else
4383 return FALSE;
4384}
4385
73cd51e5
AV		 4386/* Decode a bitfield from opcode GIVEN, with starting bitfield = START
4387 and ending bitfield = END. END must be greater than START. */
4388
4389static unsigned long
4390arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
4391{
4392 int bits = end - start;
4393
4394 if (bits < 0)
4395 abort ();
4396
4397 return ((given >> start) & ((2ul << bits) - 1));
4398}
4399
4400/* Decode a bitfield from opcode GIVEN, with multiple bitfields:
4401 START:END and START2:END2. END/END2 must be greater than
4402 START/START2. */
4403
4404static unsigned long
4405arm_decode_field_multiple (unsigned long given, unsigned int start,
4406 unsigned int end, unsigned int start2,
4407 unsigned int end2)
4408{
4409 int bits = end - start;
4410 int bits2 = end2 - start2;
4411 unsigned long value = 0;
4412 int width = 0;
4413
4414 if (bits2 < 0)
4415 abort ();
4416
4417 value = arm_decode_field (given, start, end);
4418 width += bits + 1;
4419
4420 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
4421 return value;
4422}
4423
4424/* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
4425 This helps us decode instructions that change mnemonic depending on specific
4426 operand values/encodings. */
4427
4428static bfd_boolean
4429is_mve_encoding_conflict (unsigned long given,
4430 enum mve_instructions matched_insn)
4431{
143275ea
AV		 4432 switch (matched_insn)
4433 {
4434 case MVE_VPST:
4435 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4436 return TRUE;
4437 else
4438 return FALSE;
4439
4440 case MVE_VPT_FP_T1:
4441 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4442 return TRUE;
4443 if ((arm_decode_field (given, 12, 12) == 0)
4444 && (arm_decode_field (given, 0, 0) == 1))
4445 return TRUE;
4446 return FALSE;
4447
4448 case MVE_VPT_FP_T2:
4449 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4450 return TRUE;
4451 if (arm_decode_field (given, 0, 3) == 0xd)
4452 return TRUE;
4453 return FALSE;
4454
4455 case MVE_VPT_VEC_T1:
4456 case MVE_VPT_VEC_T2:
4457 case MVE_VPT_VEC_T3:
4458 case MVE_VPT_VEC_T4:
4459 case MVE_VPT_VEC_T5:
4460 case MVE_VPT_VEC_T6:
4461 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4462 return TRUE;
4463 if (arm_decode_field (given, 20, 21) == 3)
4464 return TRUE;
4465 return FALSE;
4466
4467 case MVE_VCMP_FP_T1:
4468 if ((arm_decode_field (given, 12, 12) == 0)
4469 && (arm_decode_field (given, 0, 0) == 1))
4470 return TRUE;
4471 else
4472 return FALSE;
4473
4474 case MVE_VCMP_FP_T2:
4475 if (arm_decode_field (given, 0, 3) == 0xd)
4476 return TRUE;
4477 else
4478 return FALSE;
4479
14925797 4480 case MVE_VMULL_INT:
9743db03
AV		 4481 case MVE_VHADD_T2:
4482 case MVE_VHSUB_T2:
143275ea
AV		 4483 case MVE_VCMP_VEC_T1:
4484 case MVE_VCMP_VEC_T2:
4485 case MVE_VCMP_VEC_T3:
4486 case MVE_VCMP_VEC_T4:
4487 case MVE_VCMP_VEC_T5:
4488 case MVE_VCMP_VEC_T6:
4489 if (arm_decode_field (given, 20, 21) == 3)
4490 return TRUE;
4491 else
4492 return FALSE;
4493
04d54ace
AV		 4494 case MVE_VLD2:
4495 case MVE_VLD4:
4496 case MVE_VST2:
4497 case MVE_VST4:
4498 if (arm_decode_field (given, 7, 8) == 3)
4499 return TRUE;
4500 else
4501 return FALSE;
4502
aef6d006
AV		 4503 case MVE_VSTRB_T1:
4504 case MVE_VSTRH_T2:
4505 if ((arm_decode_field (given, 24, 24) == 0)
4506 && (arm_decode_field (given, 21, 21) == 0))
4507 {
4508 return TRUE;
4509 }
4510 else if ((arm_decode_field (given, 7, 8) == 3))
4511 return TRUE;
4512 else
4513 return FALSE;
4514
4515 case MVE_VSTRB_T5:
4516 case MVE_VSTRH_T6:
4517 case MVE_VSTRW_T7:
4518 if ((arm_decode_field (given, 24, 24) == 0)
4519 && (arm_decode_field (given, 21, 21) == 0))
4520 {
4521 return TRUE;
4522 }
4523 else
4524 return FALSE;
4525
bf0b396d
AV		 4526 case MVE_VCVT_FP_FIX_VEC:
4527 return (arm_decode_field (given, 16, 21) & 0x38) == 0;
4528
c507f10b
AV		 4529 case MVE_VBIC_IMM:
4530 case MVE_VORR_IMM:
4531 {
4532 unsigned long cmode = arm_decode_field (given, 8, 11);
4533
4534 if ((cmode & 1) == 0)
4535 return TRUE;
4536 else if ((cmode & 0xc) == 0xc)
4537 return TRUE;
4538 else
4539 return FALSE;
4540 }
4541
4542 case MVE_VMVN_IMM:
4543 {
4544 unsigned long cmode = arm_decode_field (given, 8, 11);
4545
4546 if ((cmode & 9) == 1)
4547 return TRUE;
4548 else if ((cmode & 5) == 1)
4549 return TRUE;
4550 else if ((cmode & 0xe) == 0xe)
4551 return TRUE;
4552 else
4553 return FALSE;
4554 }
4555
4556 case MVE_VMOV_IMM_TO_VEC:
4557 if ((arm_decode_field (given, 5, 5) == 1)
4558 && (arm_decode_field (given, 8, 11) != 0xe))
4559 return TRUE;
4560 else
4561 return FALSE;
4562
14925797
AV		 4563 case MVE_VMOVL:
4564 {
4565 unsigned long size = arm_decode_field (given, 19, 20);
4566 if ((size == 0) || (size == 3))
4567 return TRUE;
4568 else
4569 return FALSE;
4570 }
4571
4572 case MVE_VMOVN:
4573 case MVE_VQMOVUN:
4574 case MVE_VQMOVN:
4575 if (arm_decode_field (given, 18, 19) == 3)
4576 return TRUE;
4577 else
4578 return FALSE;
4579
143275ea
AV		 4580 default:
4581 return FALSE;
4582
4583 }
73cd51e5
AV		 4584}
4585
aef6d006
AV		 4586static void
4587print_mve_vld_str_addr (struct disassemble_info *info,
4588 unsigned long given,
4589 enum mve_instructions matched_insn)
4590{
4591 void *stream = info->stream;
4592 fprintf_ftype func = info->fprintf_func;
4593
4594 unsigned long p, w, gpr, imm, add, mod_imm;
4595
4596 imm = arm_decode_field (given, 0, 6);
4597 mod_imm = imm;
4598
4599 switch (matched_insn)
4600 {
4601 case MVE_VLDRB_T1:
4602 case MVE_VSTRB_T1:
4603 gpr = arm_decode_field (given, 16, 18);
4604 break;
4605
4606 case MVE_VLDRH_T2:
4607 case MVE_VSTRH_T2:
4608 gpr = arm_decode_field (given, 16, 18);
4609 mod_imm = imm << 1;
4610 break;
4611
4612 case MVE_VLDRH_T6:
4613 case MVE_VSTRH_T6:
4614 gpr = arm_decode_field (given, 16, 19);
4615 mod_imm = imm << 1;
4616 break;
4617
4618 case MVE_VLDRW_T7:
4619 case MVE_VSTRW_T7:
4620 gpr = arm_decode_field (given, 16, 19);
4621 mod_imm = imm << 2;
4622 break;
4623
4624 case MVE_VLDRB_T5:
4625 case MVE_VSTRB_T5:
4626 gpr = arm_decode_field (given, 16, 19);
4627 break;
4628
4629 default:
4630 return;
4631 }
4632
4633 p = arm_decode_field (given, 24, 24);
4634 w = arm_decode_field (given, 21, 21);
4635
4636 add = arm_decode_field (given, 23, 23);
4637
4638 char * add_sub;
4639
4640 /* Don't print anything for '+' as it is implied. */
4641 if (add == 1)
4642 add_sub = "";
4643 else
4644 add_sub = "-";
4645
4646 if (p == 1)
4647 {
4648 /* Offset mode. */
4649 if (w == 0)
4650 func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm);
4651 /* Pre-indexed mode. */
4652 else
4653 func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm);
4654 }
4655 else if ((p == 0) && (w == 1))
4656 /* Post-index mode. */
4657 func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm);
4658}
4659
73cd51e5
AV		 4660/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
4661 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
4662 this encoding is undefined. */
4663
4664static bfd_boolean
4665is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
4666 enum mve_undefined *undefined_code)
4667{
4668 *undefined_code = UNDEF_NONE;
4669
9743db03
AV		 4670 switch (matched_insn)
4671 {
4672 case MVE_VDUP:
4673 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
4674 {
4675 *undefined_code = UNDEF_SIZE_3;
4676 return TRUE;
4677 }
4678 else
4679 return FALSE;
4680
4681 case MVE_VRHADD:
4682 case MVE_VHADD_T1:
4683 case MVE_VHSUB_T1:
4684 if (arm_decode_field (given, 20, 21) == 3)
4685 {
4686 *undefined_code = UNDEF_SIZE_3;
4687 return TRUE;
4688 }
4689 else
4690 return FALSE;
4691
aef6d006
AV		 4692 case MVE_VLDRB_T1:
4693 if (arm_decode_field (given, 7, 8) == 3)
4694 {
4695 *undefined_code = UNDEF_SIZE_3;
4696 return TRUE;
4697 }
4698 else
4699 return FALSE;
4700
4701 case MVE_VLDRH_T2:
4702 if (arm_decode_field (given, 7, 8) <= 1)
4703 {
4704 *undefined_code = UNDEF_SIZE_LE_1;
4705 return TRUE;
4706 }
4707 else
4708 return FALSE;
4709
4710 case MVE_VSTRB_T1:
4711 if ((arm_decode_field (given, 7, 8) == 0))
4712 {
4713 *undefined_code = UNDEF_SIZE_0;
4714 return TRUE;
4715 }
4716 else
4717 return FALSE;
4718
4719 case MVE_VSTRH_T2:
4720 if ((arm_decode_field (given, 7, 8) <= 1))
4721 {
4722 *undefined_code = UNDEF_SIZE_LE_1;
4723 return TRUE;
4724 }
4725 else
4726 return FALSE;
4727
ef1576a1
AV		 4728 case MVE_VLDRB_GATHER_T1:
4729 if (arm_decode_field (given, 7, 8) == 3)
4730 {
4731 *undefined_code = UNDEF_SIZE_3;
4732 return TRUE;
4733 }
4734 else if ((arm_decode_field (given, 28, 28) == 0)
4735 && (arm_decode_field (given, 7, 8) == 0))
4736 {
4737 *undefined_code = UNDEF_NOT_UNS_SIZE_0;
4738 return TRUE;
4739 }
4740 else
4741 return FALSE;
4742
4743 case MVE_VLDRH_GATHER_T2:
4744 if (arm_decode_field (given, 7, 8) == 3)
4745 {
4746 *undefined_code = UNDEF_SIZE_3;
4747 return TRUE;
4748 }
4749 else if ((arm_decode_field (given, 28, 28) == 0)
4750 && (arm_decode_field (given, 7, 8) == 1))
4751 {
4752 *undefined_code = UNDEF_NOT_UNS_SIZE_1;
4753 return TRUE;
4754 }
4755 else if (arm_decode_field (given, 7, 8) == 0)
4756 {
4757 *undefined_code = UNDEF_SIZE_0;
4758 return TRUE;
4759 }
4760 else
4761 return FALSE;
4762
4763 case MVE_VLDRW_GATHER_T3:
4764 if (arm_decode_field (given, 7, 8) != 2)
4765 {
4766 *undefined_code = UNDEF_SIZE_NOT_2;
4767 return TRUE;
4768 }
4769 else if (arm_decode_field (given, 28, 28) == 0)
4770 {
4771 *undefined_code = UNDEF_NOT_UNSIGNED;
4772 return TRUE;
4773 }
4774 else
4775 return FALSE;
4776
4777 case MVE_VLDRD_GATHER_T4:
4778 if (arm_decode_field (given, 7, 8) != 3)
4779 {
4780 *undefined_code = UNDEF_SIZE_NOT_3;
4781 return TRUE;
4782 }
4783 else if (arm_decode_field (given, 28, 28) == 0)
4784 {
4785 *undefined_code = UNDEF_NOT_UNSIGNED;
4786 return TRUE;
4787 }
4788 else
4789 return FALSE;
4790
4791 case MVE_VSTRB_SCATTER_T1:
4792 if (arm_decode_field (given, 7, 8) == 3)
4793 {
4794 *undefined_code = UNDEF_SIZE_3;
4795 return TRUE;
4796 }
4797 else
4798 return FALSE;
4799
4800 case MVE_VSTRH_SCATTER_T2:
4801 {
4802 unsigned long size = arm_decode_field (given, 7, 8);
4803 if (size == 3)
4804 {
4805 *undefined_code = UNDEF_SIZE_3;
4806 return TRUE;
4807 }
4808 else if (size == 0)
4809 {
4810 *undefined_code = UNDEF_SIZE_0;
4811 return TRUE;
4812 }
4813 else
4814 return FALSE;
4815 }
4816
4817 case MVE_VSTRW_SCATTER_T3:
4818 if (arm_decode_field (given, 7, 8) != 2)
4819 {
4820 *undefined_code = UNDEF_SIZE_NOT_2;
4821 return TRUE;
4822 }
4823 else
4824 return FALSE;
4825
4826 case MVE_VSTRD_SCATTER_T4:
4827 if (arm_decode_field (given, 7, 8) != 3)
4828 {
4829 *undefined_code = UNDEF_SIZE_NOT_3;
4830 return TRUE;
4831 }
4832 else
4833 return FALSE;
4834
bf0b396d
AV		 4835 case MVE_VCVT_FP_FIX_VEC:
4836 {
4837 unsigned long imm6 = arm_decode_field (given, 16, 21);
4838 if ((imm6 & 0x20) == 0)
4839 {
4840 *undefined_code = UNDEF_VCVT_IMM6;
4841 return TRUE;
4842 }
4843
4844 if ((arm_decode_field (given, 9, 9) == 0)
4845 && ((imm6 & 0x30) == 0x20))
4846 {
4847 *undefined_code = UNDEF_VCVT_FSI_IMM6;
4848 return TRUE;
4849 }
4850
4851 return FALSE;
4852 }
4853
4854 case MVE_VCVT_BETWEEN_FP_INT:
4855 case MVE_VCVT_FROM_FP_TO_INT:
4856 {
4857 unsigned long size = arm_decode_field (given, 18, 19);
4858 if (size == 0)
4859 {
4860 *undefined_code = UNDEF_SIZE_0;
4861 return TRUE;
4862 }
4863 else if (size == 3)
4864 {
4865 *undefined_code = UNDEF_SIZE_3;
4866 return TRUE;
4867 }
4868 else
4869 return FALSE;
4870 }
4871
c507f10b
AV		 4872 case MVE_VMOV_VEC_LANE_TO_GP:
4873 {
4874 unsigned long op1 = arm_decode_field (given, 21, 22);
4875 unsigned long op2 = arm_decode_field (given, 5, 6);
4876 unsigned long u = arm_decode_field (given, 23, 23);
4877
4878 if ((op2 == 0) && (u == 1))
4879 {
4880 if ((op1 == 0) || (op1 == 1))
4881 {
4882 *undefined_code = UNDEF_BAD_U_OP1_OP2;
4883 return TRUE;
4884 }
4885 else
4886 return FALSE;
4887 }
4888 else if (op2 == 2)
4889 {
4890 if ((op1 == 0) || (op1 == 1))
4891 {
4892 *undefined_code = UNDEF_BAD_OP1_OP2;
4893 return TRUE;
4894 }
4895 else
4896 return FALSE;
4897 }
4898
4899 return FALSE;
4900 }
4901
4902 case MVE_VMOV_GP_TO_VEC_LANE:
4903 if (arm_decode_field (given, 5, 6) == 2)
4904 {
4905 unsigned long op1 = arm_decode_field (given, 21, 22);
4906 if ((op1 == 0) || (op1 == 1))
4907 {
4908 *undefined_code = UNDEF_BAD_OP1_OP2;
4909 return TRUE;
4910 }
4911 else
4912 return FALSE;
4913 }
4914 else
4915 return FALSE;
4916
4917 case MVE_VMOV_IMM_TO_VEC:
4918 if (arm_decode_field (given, 5, 5) == 0)
4919 {
4920 unsigned long cmode = arm_decode_field (given, 8, 11);
4921
4922 if (((cmode & 9) == 1) || ((cmode & 5) == 1))
4923 {
4924 *undefined_code = UNDEF_OP_0_BAD_CMODE;
4925 return TRUE;
4926 }
4927 else
4928 return FALSE;
4929 }
4930 else
4931 return FALSE;
4932
14925797
AV		 4933 case MVE_VMOVN:
4934 if (arm_decode_field (given, 18, 19) == 2)
4935 {
4936 *undefined_code = UNDEF_SIZE_2;
4937 return TRUE;
4938 }
4939 else
4940 return FALSE;
4941
9743db03
AV		 4942 default:
4943 return FALSE;
4944 }
73cd51e5
AV		 4945}
4946
4947/* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
4948 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
4949 why this encoding is unpredictable. */
4950
4951static bfd_boolean
4952is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
4953 enum mve_unpredictable *unpredictable_code)
4954{
4955 *unpredictable_code = UNPRED_NONE;
4956
143275ea
AV		 4957 switch (matched_insn)
4958 {
4959 case MVE_VCMP_FP_T2:
4960 case MVE_VPT_FP_T2:
4961 if ((arm_decode_field (given, 12, 12) == 0)
4962 && (arm_decode_field (given, 5, 5) == 1))
4963 {
4964 *unpredictable_code = UNPRED_FCA_0_FCB_1;
4965 return TRUE;
4966 }
4967 else
4968 return FALSE;
73cd51e5 4969
143275ea
AV		 4970 case MVE_VPT_VEC_T4:
4971 case MVE_VPT_VEC_T5:
4972 case MVE_VPT_VEC_T6:
4973 case MVE_VCMP_VEC_T4:
4974 case MVE_VCMP_VEC_T5:
4975 case MVE_VCMP_VEC_T6:
4976 if (arm_decode_field (given, 0, 3) == 0xd)
4977 {
4978 *unpredictable_code = UNPRED_R13;
4979 return TRUE;
4980 }
4981 else
4982 return FALSE;
c1e26897 4983
9743db03
AV		 4984 case MVE_VDUP:
4985 {
4986 unsigned long gpr = arm_decode_field (given, 12, 15);
4987 if (gpr == 0xd)
4988 {
4989 *unpredictable_code = UNPRED_R13;
4990 return TRUE;
4991 }
4992 else if (gpr == 0xf)
4993 {
4994 *unpredictable_code = UNPRED_R15;
4995 return TRUE;
4996 }
4997
4998 return FALSE;
4999 }
5000
5001 case MVE_VFMA_FP_SCALAR:
5002 case MVE_VFMAS_FP_SCALAR:
5003 case MVE_VHADD_T2:
5004 case MVE_VHSUB_T2:
5005 {
5006 unsigned long gpr = arm_decode_field (given, 0, 3);
5007 if (gpr == 0xd)
5008 {
5009 *unpredictable_code = UNPRED_R13;
5010 return TRUE;
5011 }
5012 else if (gpr == 0xf)
5013 {
5014 *unpredictable_code = UNPRED_R15;
5015 return TRUE;
5016 }
5017
5018 return FALSE;
5019 }
5020
04d54ace
AV		 5021 case MVE_VLD2:
5022 case MVE_VST2:
5023 {
5024 unsigned long rn = arm_decode_field (given, 16, 19);
5025
5026 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
5027 {
5028 *unpredictable_code = UNPRED_R13_AND_WB;
5029 return TRUE;
5030 }
5031
5032 if (rn == 0xf)
5033 {
5034 *unpredictable_code = UNPRED_R15;
5035 return TRUE;
5036 }
5037
5038 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
5039 {
5040 *unpredictable_code = UNPRED_Q_GT_6;
5041 return TRUE;
5042 }
5043 else
5044 return FALSE;
5045 }
5046
5047 case MVE_VLD4:
5048 case MVE_VST4:
5049 {
5050 unsigned long rn = arm_decode_field (given, 16, 19);
5051
5052 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
5053 {
5054 *unpredictable_code = UNPRED_R13_AND_WB;
5055 return TRUE;
5056 }
5057
5058 if (rn == 0xf)
5059 {
5060 *unpredictable_code = UNPRED_R15;
5061 return TRUE;
5062 }
5063
5064 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
5065 {
5066 *unpredictable_code = UNPRED_Q_GT_4;
5067 return TRUE;
5068 }
5069 else
5070 return FALSE;
5071 }
5072
aef6d006
AV		 5073 case MVE_VLDRB_T5:
5074 case MVE_VLDRH_T6:
5075 case MVE_VLDRW_T7:
5076 case MVE_VSTRB_T5:
5077 case MVE_VSTRH_T6:
5078 case MVE_VSTRW_T7:
5079 {
5080 unsigned long rn = arm_decode_field (given, 16, 19);
5081
5082 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
5083 {
5084 *unpredictable_code = UNPRED_R13_AND_WB;
5085 return TRUE;
5086 }
5087 else if (rn == 0xf)
5088 {
5089 *unpredictable_code = UNPRED_R15;
5090 return TRUE;
5091 }
5092 else
5093 return FALSE;
5094 }
5095
ef1576a1
AV		 5096 case MVE_VLDRB_GATHER_T1:
5097 if (arm_decode_field (given, 0, 0) == 1)
5098 {
5099 *unpredictable_code = UNPRED_OS;
5100 return TRUE;
5101 }
5102
5103 /* fall through. */
5104 /* To handle common code with T2-T4 variants. */
5105 case MVE_VLDRH_GATHER_T2:
5106 case MVE_VLDRW_GATHER_T3:
5107 case MVE_VLDRD_GATHER_T4:
5108 {
5109 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5110 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
5111
5112 if (qd == qm)
5113 {
5114 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
5115 return TRUE;
5116 }
5117
5118 if (arm_decode_field (given, 16, 19) == 0xf)
5119 {
5120 *unpredictable_code = UNPRED_R15;
5121 return TRUE;
5122 }
5123
5124 return FALSE;
5125 }
5126
5127 case MVE_VLDRW_GATHER_T5:
5128 case MVE_VLDRD_GATHER_T6:
5129 {
5130 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5131 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
5132
5133 if (qd == qm)
5134 {
5135 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
5136 return TRUE;
5137 }
5138 else
5139 return FALSE;
5140 }
5141
5142 case MVE_VSTRB_SCATTER_T1:
5143 if (arm_decode_field (given, 16, 19) == 0xf)
5144 {
5145 *unpredictable_code = UNPRED_R15;
5146 return TRUE;
5147 }
5148 else if (arm_decode_field (given, 0, 0) == 1)
5149 {
5150 *unpredictable_code = UNPRED_OS;
5151 return TRUE;
5152 }
5153 else
5154 return FALSE;
5155
5156 case MVE_VSTRH_SCATTER_T2:
5157 case MVE_VSTRW_SCATTER_T3:
5158 case MVE_VSTRD_SCATTER_T4:
5159 if (arm_decode_field (given, 16, 19) == 0xf)
5160 {
5161 *unpredictable_code = UNPRED_R15;
5162 return TRUE;
5163 }
5164 else
5165 return FALSE;
5166
c507f10b
AV		 5167 case MVE_VMOV2_VEC_LANE_TO_GP:
5168 case MVE_VMOV2_GP_TO_VEC_LANE:
bf0b396d
AV		 5169 case MVE_VCVT_BETWEEN_FP_INT:
5170 case MVE_VCVT_FROM_FP_TO_INT:
5171 {
5172 unsigned long rt = arm_decode_field (given, 0, 3);
5173 unsigned long rt2 = arm_decode_field (given, 16, 19);
5174
5175 if ((rt == 0xd) || (rt2 == 0xd))
5176 {
5177 *unpredictable_code = UNPRED_R13;
5178 return TRUE;
5179 }
5180 else if ((rt == 0xf) || (rt2 == 0xf))
5181 {
5182 *unpredictable_code = UNPRED_R15;
5183 return TRUE;
5184 }
5185 else if (rt == rt2)
5186 {
5187 *unpredictable_code = UNPRED_GP_REGS_EQUAL;
5188 return TRUE;
5189 }
5190
5191 return FALSE;
5192 }
5193
c507f10b
AV		 5194 case MVE_VMOV_HFP_TO_GP:
5195 case MVE_VMOV_GP_TO_VEC_LANE:
5196 case MVE_VMOV_VEC_LANE_TO_GP:
5197 {
5198 unsigned long rda = arm_decode_field (given, 12, 15);
5199 if (rda == 0xd)
5200 {
5201 *unpredictable_code = UNPRED_R13;
5202 return TRUE;
5203 }
5204 else if (rda == 0xf)
5205 {
5206 *unpredictable_code = UNPRED_R15;
5207 return TRUE;
5208 }
5209
5210 return FALSE;
5211 }
5212
14925797
AV		 5213 case MVE_VMULL_INT:
5214 {
5215 unsigned long Qd;
5216 unsigned long Qm;
5217 unsigned long Qn;
5218
5219 if (arm_decode_field (given, 20, 21) == 2)
5220 {
5221 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5222 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
5223 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
5224
5225 if ((Qd == Qn) || (Qd == Qm))
5226 {
5227 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
5228 return TRUE;
5229 }
5230 else
5231 return FALSE;
5232 }
5233 else
5234 return FALSE;
5235 }
5236
5237 case MVE_VQDMULL_T1:
5238 {
5239 unsigned long Qd;
5240 unsigned long Qm;
5241 unsigned long Qn;
5242
5243 if (arm_decode_field (given, 28, 28) == 1)
5244 {
5245 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5246 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
5247 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
5248
5249 if ((Qd == Qn) || (Qd == Qm))
5250 {
5251 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
5252 return TRUE;
5253 }
5254 else
5255 return FALSE;
5256 }
5257 else
5258 return FALSE;
5259 }
5260
5261 case MVE_VQDMULL_T2:
5262 {
5263 unsigned long gpr = arm_decode_field (given, 0, 3);
5264 if (gpr == 0xd)
5265 {
5266 *unpredictable_code = UNPRED_R13;
5267 return TRUE;
5268 }
5269 else if (gpr == 0xf)
5270 {
5271 *unpredictable_code = UNPRED_R15;
5272 return TRUE;
5273 }
5274
5275 if (arm_decode_field (given, 28, 28) == 1)
5276 {
5277 unsigned long Qd
5278 = arm_decode_field_multiple (given, 13, 15, 22, 22);
5279 unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
5280
5281 if ((Qd == Qn))
5282 {
5283 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
5284 return TRUE;
5285 }
5286 else
5287 return FALSE;
5288 }
5289
5290 return FALSE;
5291 }
5292
143275ea
AV		 5293 default:
5294 return FALSE;
5295 }
5296}
c1e26897 5297
c507f10b
AV		 5298static void
5299print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
5300{
5301 unsigned long op1 = arm_decode_field (given, 21, 22);
5302 unsigned long op2 = arm_decode_field (given, 5, 6);
5303 unsigned long h = arm_decode_field (given, 16, 16);
5304 unsigned long index, esize, targetBeat, idx;
5305 void *stream = info->stream;
5306 fprintf_ftype func = info->fprintf_func;
5307
5308 if ((op1 & 0x2) == 0x2)
5309 {
5310 index = op2;
5311 esize = 8;
5312 }
5313 else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
5314 {
5315 index = op2 >> 1;
5316 esize = 16;
5317 }
5318 else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
5319 {
5320 index = 0;
5321 esize = 32;
5322 }
5323 else
5324 {
5325 func (stream, "<undefined index>");
5326 return;
5327 }
5328
5329 targetBeat = (op1 & 0x1) | (h << 1);
5330 idx = index + targetBeat * (32/esize);
5331
5332 func (stream, "%lu", idx);
5333}
5334
5335/* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
5336 in length and integer of floating-point type. */
5337static void
5338print_simd_imm8 (struct disassemble_info *info, unsigned long given,
5339 unsigned int ibit_loc, const struct mopcode32 *insn)
5340{
5341 int bits = 0;
5342 int cmode = (given >> 8) & 0xf;
5343 int op = (given >> 5) & 0x1;
5344 unsigned long value = 0, hival = 0;
5345 unsigned shift;
5346 int size = 0;
5347 int isfloat = 0;
5348 void *stream = info->stream;
5349 fprintf_ftype func = info->fprintf_func;
5350
5351 /* On Neon the 'i' bit is at bit 24, on mve it is
5352 at bit 28. */
5353 bits |= ((given >> ibit_loc) & 1) << 7;
5354 bits |= ((given >> 16) & 7) << 4;
5355 bits |= ((given >> 0) & 15) << 0;
5356
5357 if (cmode < 8)
5358 {
5359 shift = (cmode >> 1) & 3;
5360 value = (unsigned long) bits << (8 * shift);
5361 size = 32;
5362 }
5363 else if (cmode < 12)
5364 {
5365 shift = (cmode >> 1) & 1;
5366 value = (unsigned long) bits << (8 * shift);
5367 size = 16;
5368 }
5369 else if (cmode < 14)
5370 {
5371 shift = (cmode & 1) + 1;
5372 value = (unsigned long) bits << (8 * shift);
5373 value |= (1ul << (8 * shift)) - 1;
5374 size = 32;
5375 }
5376 else if (cmode == 14)
5377 {
5378 if (op)
5379 {
5380 /* Bit replication into bytes. */
5381 int ix;
5382 unsigned long mask;
5383
5384 value = 0;
5385 hival = 0;
5386 for (ix = 7; ix >= 0; ix--)
5387 {
5388 mask = ((bits >> ix) & 1) ? 0xff : 0;
5389 if (ix <= 3)
5390 value = (value << 8) | mask;
5391 else
5392 hival = (hival << 8) | mask;
5393 }
5394 size = 64;
5395 }
5396 else
5397 {
5398 /* Byte replication. */
5399 value = (unsigned long) bits;
5400 size = 8;
5401 }
5402 }
5403 else if (!op)
5404 {
5405 /* Floating point encoding. */
5406 int tmp;
5407
5408 value = (unsigned long) (bits & 0x7f) << 19;
5409 value |= (unsigned long) (bits & 0x80) << 24;
5410 tmp = bits & 0x40 ? 0x3c : 0x40;
5411 value |= (unsigned long) tmp << 24;
5412 size = 32;
5413 isfloat = 1;
5414 }
5415 else
5416 {
5417 func (stream, "<illegal constant %.8x:%x:%x>",
5418 bits, cmode, op);
5419 size = 32;
5420 return;
5421 }
5422
5423 // printU determines whether the immediate value should be printed as
5424 // unsigned.
5425 unsigned printU = 0;
5426 switch (insn->mve_op)
5427 {
5428 default:
5429 break;
5430 // We want this for instructions that don't have a 'signed' type
5431 case MVE_VBIC_IMM:
5432 case MVE_VORR_IMM:
5433 case MVE_VMVN_IMM:
5434 case MVE_VMOV_IMM_TO_VEC:
5435 printU = 1;
5436 break;
5437 }
5438 switch (size)
5439 {
5440 case 8:
5441 func (stream, "#%ld\t; 0x%.2lx", value, value);
5442 break;
5443
5444 case 16:
5445 func (stream,
5446 printU
5447 ? "#%lu\t; 0x%.4lx"
5448 : "#%ld\t; 0x%.4lx", value, value);
5449 break;
5450
5451 case 32:
5452 if (isfloat)
5453 {
5454 unsigned char valbytes[4];
5455 double fvalue;
5456
5457 /* Do this a byte at a time so we don't have to
5458 worry about the host's endianness. */
5459 valbytes[0] = value & 0xff;
5460 valbytes[1] = (value >> 8) & 0xff;
5461 valbytes[2] = (value >> 16) & 0xff;
5462 valbytes[3] = (value >> 24) & 0xff;
5463
5464 floatformat_to_double
5465 (& floatformat_ieee_single_little, valbytes,
5466 & fvalue);
5467
5468 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
5469 value);
5470 }
5471 else
5472 func (stream,
5473 printU
5474 ? "#%lu\t; 0x%.8lx"
5475 : "#%ld\t; 0x%.8lx",
5476 (long) (((value & 0x80000000L) != 0)
5477 && !printU
5478 ? value | ~0xffffffffL : value),
5479 value);
5480 break;
5481
5482 case 64:
5483 func (stream, "#0x%.8lx%.8lx", hival, value);
5484 break;
5485
5486 default:
5487 abort ();
5488 }
5489
5490}
5491
73cd51e5
AV		 5492static void
5493print_mve_undefined (struct disassemble_info *info,
5494 enum mve_undefined undefined_code)
5495{
5496 void *stream = info->stream;
5497 fprintf_ftype func = info->fprintf_func;
5498
5499 func (stream, "\t\tundefined instruction: ");
5500
5501 switch (undefined_code)
5502 {
aef6d006
AV		 5503 case UNDEF_SIZE_0:
5504 func (stream, "size equals zero");
5505 break;
5506
c507f10b
AV		 5507 case UNDEF_SIZE_2:
5508 func (stream, "size equals two");
5509 break;
5510
9743db03
AV		 5511 case UNDEF_SIZE_3:
5512 func (stream, "size equals three");
5513 break;
5514
aef6d006
AV		 5515 case UNDEF_SIZE_LE_1:
5516 func (stream, "size <= 1");
5517 break;
5518
ef1576a1
AV		 5519 case UNDEF_SIZE_NOT_2:
5520 func (stream, "size not equal to 2");
5521 break;
5522
5523 case UNDEF_SIZE_NOT_3:
5524 func (stream, "size not equal to 3");
5525 break;
5526
5527 case UNDEF_NOT_UNS_SIZE_0:
5528 func (stream, "not unsigned and size = zero");
5529 break;
5530
5531 case UNDEF_NOT_UNS_SIZE_1:
5532 func (stream, "not unsigned and size = one");
5533 break;
5534
5535 case UNDEF_NOT_UNSIGNED:
5536 func (stream, "not unsigned");
5537 break;
5538
bf0b396d
AV		 5539 case UNDEF_VCVT_IMM6:
5540 func (stream, "invalid imm6");
5541 break;
5542
5543 case UNDEF_VCVT_FSI_IMM6:
5544 func (stream, "fsi = 0 and invalid imm6");
5545 break;
5546
c507f10b
AV		 5547 case UNDEF_BAD_OP1_OP2:
5548 func (stream, "bad size with op2 = 2 and op1 = 0 or 1");
5549 break;
5550
5551 case UNDEF_BAD_U_OP1_OP2:
5552 func (stream, "unsigned with op2 = 0 and op1 = 0 or 1");
5553 break;
5554
5555 case UNDEF_OP_0_BAD_CMODE:
5556 func (stream, "op field equal 0 and bad cmode");
5557 break;
5558
73cd51e5
AV		 5559 case UNDEF_NONE:
5560 break;
5561 }
5562
5563}
5564
5565static void
5566print_mve_unpredictable (struct disassemble_info *info,
5567 enum mve_unpredictable unpredict_code)
5568{
5569 void *stream = info->stream;
5570 fprintf_ftype func = info->fprintf_func;
5571
5572 func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
5573
5574 switch (unpredict_code)
5575 {
5576 case UNPRED_IT_BLOCK:
5577 func (stream, "mve instruction in it block");
5578 break;
5579
143275ea
AV		 5580 case UNPRED_FCA_0_FCB_1:
5581 func (stream, "condition bits, fca = 0 and fcb = 1");
5582 break;
5583
5584 case UNPRED_R13:
5585 func (stream, "use of r13 (sp)");
5586 break;
5587
9743db03
AV		 5588 case UNPRED_R15:
5589 func (stream, "use of r15 (pc)");
5590 break;
5591
04d54ace
AV		 5592 case UNPRED_Q_GT_4:
5593 func (stream, "start register block > r4");
5594 break;
5595
5596 case UNPRED_Q_GT_6:
5597 func (stream, "start register block > r6");
5598 break;
5599
5600 case UNPRED_R13_AND_WB:
5601 func (stream, "use of r13 and write back");
5602 break;
5603
ef1576a1
AV		 5604 case UNPRED_Q_REGS_EQUAL:
5605 func (stream,
5606 "same vector register used for destination and other operand");
5607 break;
5608
5609 case UNPRED_OS:
5610 func (stream, "use of offset scaled");
5611 break;
5612
bf0b396d
AV		 5613 case UNPRED_GP_REGS_EQUAL:
5614 func (stream, "same general-purpose register used for both operands");
5615 break;
5616
c507f10b
AV		 5617 case UNPRED_Q_REGS_EQ_AND_SIZE_1:
5618 func (stream, "use of identical q registers and size = 1");
5619 break;
5620
5621 case UNPRED_Q_REGS_EQ_AND_SIZE_2:
5622 func (stream, "use of identical q registers and size = 1");
5623 break;
5624
73cd51e5
AV		 5625 case UNPRED_NONE:
5626 break;
5627 }
5628}
5629
04d54ace
AV		 5630/* Print register block operand for mve vld2/vld4/vst2/vld4. */
5631
5632static void
5633print_mve_register_blocks (struct disassemble_info *info,
5634 unsigned long given,
5635 enum mve_instructions matched_insn)
5636{
5637 void *stream = info->stream;
5638 fprintf_ftype func = info->fprintf_func;
5639
5640 unsigned long q_reg_start = arm_decode_field_multiple (given,
5641 13, 15,
5642 22, 22);
5643 switch (matched_insn)
5644 {
5645 case MVE_VLD2:
5646 case MVE_VST2:
5647 if (q_reg_start <= 6)
5648 func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
5649 else
5650 func (stream, "<illegal reg q%ld>", q_reg_start);
5651 break;
5652
5653 case MVE_VLD4:
5654 case MVE_VST4:
5655 if (q_reg_start <= 4)
5656 func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
5657 q_reg_start + 1, q_reg_start + 2,
5658 q_reg_start + 3);
5659 else
5660 func (stream, "<illegal reg q%ld>", q_reg_start);
5661 break;
5662
5663 default:
5664 break;
5665 }
5666}
5667
bf0b396d
AV		 5668static void
5669print_mve_rounding_mode (struct disassemble_info *info,
5670 unsigned long given,
5671 enum mve_instructions matched_insn)
5672{
5673 void *stream = info->stream;
5674 fprintf_ftype func = info->fprintf_func;
5675
5676 switch (matched_insn)
5677 {
5678 case MVE_VCVT_FROM_FP_TO_INT:
5679 {
5680 switch (arm_decode_field (given, 8, 9))
5681 {
5682 case 0:
5683 func (stream, "a");
5684 break;
5685
5686 case 1:
5687 func (stream, "n");
5688 break;
5689
5690 case 2:
5691 func (stream, "p");
5692 break;
5693
5694 case 3:
5695 func (stream, "m");
5696 break;
5697
5698 default:
5699 break;
5700 }
5701 }
5702 break;
5703
5704 case MVE_VRINT_FP:
5705 {
5706 switch (arm_decode_field (given, 7, 9))
5707 {
5708 case 0:
5709 func (stream, "n");
5710 break;
5711
5712 case 1:
5713 func (stream, "x");
5714 break;
5715
5716 case 2:
5717 func (stream, "a");
5718 break;
5719
5720 case 3:
5721 func (stream, "z");
5722 break;
5723
5724 case 5:
5725 func (stream, "m");
5726 break;
5727
5728 case 7:
5729 func (stream, "p");
5730
5731 case 4:
5732 case 6:
5733 default:
5734 break;
5735 }
5736 }
5737 break;
5738
5739 default:
5740 break;
5741 }
5742}
5743
5744static void
5745print_mve_vcvt_size (struct disassemble_info *info,
5746 unsigned long given,
5747 enum mve_instructions matched_insn)
5748{
5749 unsigned long mode = 0;
5750 void *stream = info->stream;
5751 fprintf_ftype func = info->fprintf_func;
5752
5753 switch (matched_insn)
5754 {
5755 case MVE_VCVT_FP_FIX_VEC:
5756 {
5757 mode = (((given & 0x200) >> 7)
5758 | ((given & 0x10000000) >> 27)
5759 | ((given & 0x100) >> 8));
5760
5761 switch (mode)
5762 {
5763 case 0:
5764 func (stream, "f16.s16");
5765 break;
5766
5767 case 1:
5768 func (stream, "s16.f16");
5769 break;
5770
5771 case 2:
5772 func (stream, "f16.u16");
5773 break;
5774
5775 case 3:
5776 func (stream, "u16.f16");
5777 break;
5778
5779 case 4:
5780 func (stream, "f32.s32");
5781 break;
5782
5783 case 5:
5784 func (stream, "s32.f32");
5785 break;
5786
5787 case 6:
5788 func (stream, "f32.u32");
5789 break;
5790
5791 case 7:
5792 func (stream, "u32.f32");
5793 break;
5794
5795 default:
5796 break;
5797 }
5798 break;
5799 }
5800 case MVE_VCVT_BETWEEN_FP_INT:
5801 {
5802 unsigned long size = arm_decode_field (given, 18, 19);
5803 unsigned long op = arm_decode_field (given, 7, 8);
5804
5805 if (size == 1)
5806 {
5807 switch (op)
5808 {
5809 case 0:
5810 func (stream, "f16.s16");
5811 break;
5812
5813 case 1:
5814 func (stream, "f16.u16");
5815 break;
5816
5817 case 2:
5818 func (stream, "s16.f16");
5819 break;
5820
5821 case 3:
5822 func (stream, "u16.f16");
5823 break;
5824
5825 default:
5826 break;
5827 }
5828 }
5829 else if (size == 2)
5830 {
5831 switch (op)
5832 {
5833 case 0:
5834 func (stream, "f32.s32");
5835 break;
5836
5837 case 1:
5838 func (stream, "f32.u32");
5839 break;
5840
5841 case 2:
5842 func (stream, "s32.f32");
5843 break;
5844
5845 case 3:
5846 func (stream, "u32.f32");
5847 break;
5848 }
5849 }
5850 }
5851 break;
5852
5853 case MVE_VCVT_FP_HALF_FP:
5854 {
5855 unsigned long op = arm_decode_field (given, 28, 28);
5856 if (op == 0)
5857 func (stream, "f16.f32");
5858 else if (op == 1)
5859 func (stream, "f32.f16");
5860 }
5861 break;
5862
5863 case MVE_VCVT_FROM_FP_TO_INT:
5864 {
5865 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
5866
5867 switch (size)
5868 {
5869 case 2:
5870 func (stream, "s16.f16");
5871 break;
5872
5873 case 3:
5874 func (stream, "u16.f16");
5875 break;
5876
5877 case 4:
5878 func (stream, "s32.f32");
5879 break;
5880
5881 case 5:
5882 func (stream, "u32.f32");
5883 break;
5884
5885 default:
5886 break;
5887 }
5888 }
5889 break;
5890
5891 default:
5892 break;
5893 }
5894}
5895
143275ea
AV		 5896static void
5897print_instruction_predicate (struct disassemble_info *info)
5898{
5899 void *stream = info->stream;
5900 fprintf_ftype func = info->fprintf_func;
5901
5902 if (vpt_block_state.next_pred_state == PRED_THEN)
5903 func (stream, "t");
5904 else if (vpt_block_state.next_pred_state == PRED_ELSE)
5905 func (stream, "e");
5906}
5907
5908static void
5909print_mve_size (struct disassemble_info *info,
5910 unsigned long size,
5911 enum mve_instructions matched_insn)
5912{
5913 void *stream = info->stream;
5914 fprintf_ftype func = info->fprintf_func;
5915
5916 switch (matched_insn)
5917 {
5918 case MVE_VCMP_VEC_T1:
5919 case MVE_VCMP_VEC_T2:
5920 case MVE_VCMP_VEC_T3:
5921 case MVE_VCMP_VEC_T4:
5922 case MVE_VCMP_VEC_T5:
5923 case MVE_VCMP_VEC_T6:
9743db03
AV		 5924 case MVE_VHADD_T1:
5925 case MVE_VHADD_T2:
5926 case MVE_VHSUB_T1:
5927 case MVE_VHSUB_T2:
04d54ace
AV		 5928 case MVE_VLD2:
5929 case MVE_VLD4:
ef1576a1
AV		 5930 case MVE_VLDRB_GATHER_T1:
5931 case MVE_VLDRH_GATHER_T2:
5932 case MVE_VLDRW_GATHER_T3:
5933 case MVE_VLDRD_GATHER_T4:
aef6d006
AV		 5934 case MVE_VLDRB_T1:
5935 case MVE_VLDRH_T2:
143275ea
AV		 5936 case MVE_VPT_VEC_T1:
5937 case MVE_VPT_VEC_T2:
5938 case MVE_VPT_VEC_T3:
5939 case MVE_VPT_VEC_T4:
5940 case MVE_VPT_VEC_T5:
5941 case MVE_VPT_VEC_T6:
9743db03 5942 case MVE_VRHADD:
bf0b396d 5943 case MVE_VRINT_FP:
04d54ace
AV		 5944 case MVE_VST2:
5945 case MVE_VST4:
ef1576a1
AV		 5946 case MVE_VSTRB_SCATTER_T1:
5947 case MVE_VSTRH_SCATTER_T2:
5948 case MVE_VSTRW_SCATTER_T3:
aef6d006
AV		 5949 case MVE_VSTRB_T1:
5950 case MVE_VSTRH_T2:
143275ea
AV		 5951 if (size <= 3)
5952 func (stream, "%s", mve_vec_sizename[size]);
5953 else
5954 func (stream, "<undef size>");
5955 break;
5956
5957 case MVE_VCMP_FP_T1:
5958 case MVE_VCMP_FP_T2:
9743db03
AV		 5959 case MVE_VFMA_FP_SCALAR:
5960 case MVE_VFMA_FP:
5961 case MVE_VFMS_FP:
5962 case MVE_VFMAS_FP_SCALAR:
143275ea
AV		 5963 case MVE_VPT_FP_T1:
5964 case MVE_VPT_FP_T2:
5965 if (size == 0)
5966 func (stream, "32");
5967 else if (size == 1)
5968 func (stream, "16");
5969 break;
5970
14925797
AV		 5971 case MVE_VMOVN:
5972 case MVE_VQDMULL_T1:
5973 case MVE_VQDMULL_T2:
5974 case MVE_VQMOVN:
5975 case MVE_VQMOVUN:
5976 if (size == 0)
5977 func (stream, "16");
5978 else if (size == 1)
5979 func (stream, "32");
5980 break;
5981
5982 case MVE_VMOVL:
5983 if (size == 1)
5984 func (stream, "8");
5985 else if (size == 2)
5986 func (stream, "16");
5987 break;
5988
9743db03
AV		 5989 case MVE_VDUP:
5990 switch (size)
5991 {
5992 case 0:
5993 func (stream, "32");
5994 break;
5995 case 1:
5996 func (stream, "16");
5997 break;
5998 case 2:
5999 func (stream, "8");
6000 break;
6001 default:
6002 break;
6003 }
6004 break;
6005
c507f10b
AV		 6006 case MVE_VMOV_GP_TO_VEC_LANE:
6007 case MVE_VMOV_VEC_LANE_TO_GP:
6008 switch (size)
6009 {
6010 case 0: case 4:
6011 func (stream, "32");
6012 break;
6013
6014 case 1: case 3:
6015 case 5: case 7:
6016 func (stream, "16");
6017 break;
6018
6019 case 8: case 9: case 10: case 11:
6020 case 12: case 13: case 14: case 15:
6021 func (stream, "8");
6022 break;
6023
6024 default:
6025 break;
6026 }
6027 break;
6028
6029 case MVE_VMOV_IMM_TO_VEC:
6030 switch (size)
6031 {
6032 case 0: case 4: case 8:
6033 case 12: case 24: case 26:
6034 func (stream, "i32");
6035 break;
6036 case 16: case 20:
6037 func (stream, "i16");
6038 break;
6039 case 28:
6040 func (stream, "i8");
6041 break;
6042 case 29:
6043 func (stream, "i64");
6044 break;
6045 case 30:
6046 func (stream, "f32");
6047 break;
6048 default:
6049 break;
6050 }
6051 break;
6052
14925797
AV		 6053 case MVE_VMULL_POLY:
6054 if (size == 0)
6055 func (stream, "p8");
6056 else if (size == 1)
6057 func (stream, "p16");
6058 break;
6059
c507f10b
AV		 6060 case MVE_VMVN_IMM:
6061 switch (size)
6062 {
6063 case 0: case 2: case 4:
6064 case 6: case 12: case 13:
6065 func (stream, "32");
6066 break;
6067
6068 case 8: case 10:
6069 func (stream, "16");
6070 break;
6071
6072 default:
6073 break;
6074 }
6075 break;
6076
6077 case MVE_VBIC_IMM:
6078 case MVE_VORR_IMM:
6079 switch (size)
6080 {
6081 case 1: case 3:
6082 case 5: case 7:
6083 func (stream, "32");
6084 break;
6085
6086 case 9: case 11:
6087 func (stream, "16");
6088 break;
6089
6090 default:
6091 break;
6092 }
6093 break;
6094
143275ea
AV		 6095 default:
6096 break;
6097 }
6098}
6099
6100static void
6101print_vec_condition (struct disassemble_info *info, long given,
6102 enum mve_instructions matched_insn)
6103{
6104 void *stream = info->stream;
6105 fprintf_ftype func = info->fprintf_func;
6106 long vec_cond = 0;
6107
6108 switch (matched_insn)
6109 {
6110 case MVE_VPT_FP_T1:
6111 case MVE_VCMP_FP_T1:
6112 vec_cond = (((given & 0x1000) >> 10)
6113 | ((given & 1) << 1)
6114 | ((given & 0x0080) >> 7));
6115 func (stream, "%s",vec_condnames[vec_cond]);
6116 break;
6117
6118 case MVE_VPT_FP_T2:
6119 case MVE_VCMP_FP_T2:
6120 vec_cond = (((given & 0x1000) >> 10)
6121 | ((given & 0x0020) >> 4)
6122 | ((given & 0x0080) >> 7));
6123 func (stream, "%s",vec_condnames[vec_cond]);
6124 break;
6125
6126 case MVE_VPT_VEC_T1:
6127 case MVE_VCMP_VEC_T1:
6128 vec_cond = (given & 0x0080) >> 7;
6129 func (stream, "%s",vec_condnames[vec_cond]);
6130 break;
6131
6132 case MVE_VPT_VEC_T2:
6133 case MVE_VCMP_VEC_T2:
6134 vec_cond = 2 | ((given & 0x0080) >> 7);
6135 func (stream, "%s",vec_condnames[vec_cond]);
6136 break;
6137
6138 case MVE_VPT_VEC_T3:
6139 case MVE_VCMP_VEC_T3:
6140 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
6141 func (stream, "%s",vec_condnames[vec_cond]);
6142 break;
6143
6144 case MVE_VPT_VEC_T4:
6145 case MVE_VCMP_VEC_T4:
6146 vec_cond = (given & 0x0080) >> 7;
6147 func (stream, "%s",vec_condnames[vec_cond]);
6148 break;
6149
6150 case MVE_VPT_VEC_T5:
6151 case MVE_VCMP_VEC_T5:
6152 vec_cond = 2 | ((given & 0x0080) >> 7);
6153 func (stream, "%s",vec_condnames[vec_cond]);
6154 break;
6155
6156 case MVE_VPT_VEC_T6:
6157 case MVE_VCMP_VEC_T6:
6158 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
6159 func (stream, "%s",vec_condnames[vec_cond]);
6160 break;
6161
6162 case MVE_NONE:
6163 case MVE_VPST:
6164 default:
6165 break;
6166 }
6167}
6168
6169#define W_BIT 21
6170#define I_BIT 22
6171#define U_BIT 23
6172#define P_BIT 24
6173
6174#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
6175#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
6176#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
6177#define PRE_BIT_SET (given & (1 << P_BIT))
6178
6179
8f06b2d8
PB		 6180/* Print one coprocessor instruction on INFO->STREAM.
6181 Return TRUE if the instuction matched, FALSE if this is not a
6182 recognised coprocessor instruction. */
6183
6184static bfd_boolean
fe56b6ce
NC		 6185print_insn_coprocessor (bfd_vma pc,
6186 struct disassemble_info *info,
6187 long given,
8f06b2d8
PB		 6188 bfd_boolean thumb)
6189{
6b0dd094 6190 const struct sopcode32 *insn;
8f06b2d8
PB		 6191 void *stream = info->stream;
6192 fprintf_ftype func = info->fprintf_func;
6193 unsigned long mask;
2edcd244 6194 unsigned long value = 0;
c22aaad1 6195 int cond;
8afc7bea 6196 int cp_num;
823d2571
TG		 6197 struct arm_private_data *private_data = info->private_data;
6198 arm_feature_set allowed_arches = ARM_ARCH_NONE;
32c36c3c
AV		 6199 arm_feature_set arm_ext_v8_1m_main =
6200 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
823d2571 6201
5b616bef 6202 allowed_arches = private_data->features;
8f06b2d8
PB		 6203
6204 for (insn = coprocessor_opcodes; insn->assembler; insn++)
6205 {
ff4a8d2b
NC		 6206 unsigned long u_reg = 16;
6207 bfd_boolean is_unpredictable = FALSE;
05413229 6208 signed long value_in_comment = 0;
0313a2b8
NC		 6209 const char *c;
6210
823d2571 6211 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 6212 switch (insn->value)
6213 {
6214 case SENTINEL_IWMMXT_START:
6215 if (info->mach != bfd_mach_arm_XScale
6216 && info->mach != bfd_mach_arm_iWMMXt
6217 && info->mach != bfd_mach_arm_iWMMXt2)
6218 do
6219 insn++;
823d2571
TG		 6220 while ((! ARM_FEATURE_ZERO (insn->arch))
6221 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 6222 continue;
6223
6224 case SENTINEL_IWMMXT_END:
6225 continue;
6226
6227 case SENTINEL_GENERIC_START:
5b616bef 6228 allowed_arches = private_data->features;
05413229
NC		 6229 continue;
6230
6231 default:
6232 abort ();
6233 }
8f06b2d8
PB		 6234
6235 mask = insn->mask;
6236 value = insn->value;
8afc7bea
RL		 6237 cp_num = (given >> 8) & 0xf;
6238
8f06b2d8
PB		 6239 if (thumb)
6240 {
6241 /* The high 4 bits are 0xe for Arm conditional instructions, and
6242 0xe for arm unconditional instructions. The rest of the
6243 encoding is the same. */
6244 mask |= 0xf0000000;
6245 value |= 0xe0000000;
c22aaad1
PB		 6246 if (ifthen_state)
6247 cond = IFTHEN_COND;
6248 else
e2efe87d 6249 cond = COND_UNCOND;
8f06b2d8
PB		 6250 }
6251 else
6252 {
6253 /* Only match unconditional instuctions against unconditional
6254 patterns. */
6255 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 6256 {
6257 mask |= 0xf0000000;
e2efe87d 6258 cond = COND_UNCOND;
c22aaad1
PB		 6259 }
6260 else
6261 {
6262 cond = (given >> 28) & 0xf;
6263 if (cond == 0xe)
e2efe87d 6264 cond = COND_UNCOND;
c22aaad1 6265 }
8f06b2d8 6266 }
823d2571 6267
6b0dd094
AV		 6268 if ((insn->isa == T32 && !thumb)
6269 || (insn->isa == ARM && thumb))
6270 continue;
6271
0313a2b8
NC		 6272 if ((given & mask) != value)
6273 continue;
8f06b2d8 6274
823d2571 6275 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 6276 continue;
6277
8afc7bea
RL		 6278 if (insn->value == 0xfe000010 /* mcr2 */
6279 || insn->value == 0xfe100010 /* mrc2 */
6280 || insn->value == 0xfc100000 /* ldc2 */
6281 || insn->value == 0xfc000000) /* stc2 */
6282 {
b0c11777 6283 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 6284 is_unpredictable = TRUE;
f08d8ce3
AV		 6285
6286 /* Armv8.1-M Mainline FP & MVE instructions. */
6287 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
6288 && !ARM_CPU_IS_ANY (allowed_arches)
6289 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
6290 continue;
6291
8afc7bea
RL		 6292 }
6293 else if (insn->value == 0x0e000000 /* cdp */
6294 || insn->value == 0xfe000000 /* cdp2 */
6295 || insn->value == 0x0e000010 /* mcr */
6296 || insn->value == 0x0e100010 /* mrc */
6297 || insn->value == 0x0c100000 /* ldc */
6298 || insn->value == 0x0c000000) /* stc */
6299 {
6300 /* Floating-point instructions. */
b0c11777 6301 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 6302 continue;
32c36c3c
AV		 6303
6304 /* Armv8.1-M Mainline FP & MVE instructions. */
6305 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
6306 && !ARM_CPU_IS_ANY (allowed_arches)
6307 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
6308 continue;
8afc7bea 6309 }
aef6d006
AV		 6310 else if ((insn->value == 0xec100f80 /* vldr (system register) */
6311 || insn->value == 0xec000f80) /* vstr (system register) */
6312 && arm_decode_field (given, 24, 24) == 0
6313 && arm_decode_field (given, 21, 21) == 0)
6314 /* If the P and W bits are both 0 then these encodings match the MVE
6315 VLDR and VSTR instructions, these are in a different table, so we
6316 don't let it match here. */
6317 continue;
6318
0313a2b8
NC		 6319 for (c = insn->assembler; *c; c++)
6320 {
6321 if (*c == '%')
8f06b2d8 6322 {
32c36c3c
AV		 6323 const char mod = *++c;
6324 switch (mod)
8f06b2d8 6325 {
0313a2b8
NC		 6326 case '%':
6327 func (stream, "%%");
6328 break;
6329
6330 case 'A':
32c36c3c 6331 case 'K':
05413229 6332 {
79862e45 6333 int rn = (given >> 16) & 0xf;
b0c11777 6334 bfd_vma offset = given & 0xff;
0313a2b8 6335
32c36c3c
AV		 6336 if (mod == 'K')
6337 offset = given & 0x7f;
6338
05413229 6339 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 6340
79862e45
DJ		 6341 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
6342 {
6343 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 6344 if (cp_num == 9)
6345 /* vldr.16/vstr.16 will shift the address
6346 left by 1 bit only. */
6347 offset = offset * 2;
6348 else
6349 offset = offset * 4;
6350
79862e45
DJ		 6351 if (NEGATIVE_BIT_SET)
6352 offset = - offset;
6353 if (rn != 15)
6354 value_in_comment = offset;
6355 }
6356
c1e26897 6357 if (PRE_BIT_SET)
05413229
NC		 6358 {
6359 if (offset)
fe56b6ce 6360 func (stream, ", #%d]%s",
d908c8af 6361 (int) offset,
c1e26897 6362 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 6363 else if (NEGATIVE_BIT_SET)
6364 func (stream, ", #-0]");
05413229
NC		 6365 else
6366 func (stream, "]");
6367 }
6368 else
6369 {
0313a2b8 6370 func (stream, "]");
8f06b2d8 6371
c1e26897 6372 if (WRITEBACK_BIT_SET)
05413229
NC		 6373 {
6374 if (offset)
d908c8af 6375 func (stream, ", #%d", (int) offset);
26d97720
NS		 6376 else if (NEGATIVE_BIT_SET)
6377 func (stream, ", #-0");
05413229
NC		 6378 }
6379 else
fe56b6ce 6380 {
26d97720
NS		 6381 func (stream, ", {%s%d}",
6382 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 6383 (int) offset);
fe56b6ce
NC		 6384 value_in_comment = offset;
6385 }
05413229 6386 }
79862e45
DJ		 6387 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
6388 {
6389 func (stream, "\t; ");
6844b2c2
MGD		 6390 /* For unaligned PCs, apply off-by-alignment
6391 correction. */
43e65147 6392 info->print_address_func (offset + pc
6844b2c2
MGD		 6393 + info->bytes_per_chunk * 2
6394 - (pc & 3),
dffaa15c 6395 info);
79862e45 6396 }
05413229 6397 }
0313a2b8 6398 break;
8f06b2d8 6399
0313a2b8
NC		 6400 case 'B':
6401 {
6402 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
6403 int offset = (given >> 1) & 0x3f;
6404
6405 if (offset == 1)
6406 func (stream, "{d%d}", regno);
6407 else if (regno + offset > 32)
6408 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
6409 else
6410 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
6411 }
6412 break;
8f06b2d8 6413
efd6b359
AV		 6414 case 'C':
6415 {
6416 bfd_boolean single = ((given >> 8) & 1) == 0;
6417 char reg_prefix = single ? 's' : 'd';
6418 int Dreg = (given >> 22) & 0x1;
6419 int Vdreg = (given >> 12) & 0xf;
6420 int reg = single ? ((Vdreg << 1) | Dreg)
6421 : ((Dreg << 4) | Vdreg);
6422 int num = (given >> (single ? 0 : 1)) & 0x7f;
6423 int maxreg = single ? 31 : 15;
6424 int topreg = reg + num - 1;
6425
6426 if (!num)
6427 func (stream, "{VPR}");
6428 else if (num == 1)
6429 func (stream, "{%c%d, VPR}", reg_prefix, reg);
6430 else if (topreg > maxreg)
6431 func (stream, "{%c%d-<overflow reg d%d, VPR}",
6432 reg_prefix, reg, single ? topreg >> 1 : topreg);
6433 else
6434 func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
6435 reg_prefix, topreg);
6436 }
6437 break;
6438
e2efe87d
MGD		 6439 case 'u':
6440 if (cond != COND_UNCOND)
6441 is_unpredictable = TRUE;
6442
6443 /* Fall through. */
0313a2b8 6444 case 'c':
b0c11777
RL		 6445 if (cond != COND_UNCOND && cp_num == 9)
6446 is_unpredictable = TRUE;
6447
0313a2b8
NC		 6448 func (stream, "%s", arm_conditional[cond]);
6449 break;
8f06b2d8 6450
0313a2b8
NC		 6451 case 'I':
6452 /* Print a Cirrus/DSP shift immediate. */
6453 /* Immediates are 7bit signed ints with bits 0..3 in
6454 bits 0..3 of opcode and bits 4..6 in bits 5..7
6455 of opcode. */
6456 {
6457 int imm;
8f06b2d8 6458
0313a2b8 6459 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 6460
0313a2b8
NC		 6461 /* Is ``imm'' a negative number? */
6462 if (imm & 0x40)
24b4cf66 6463 imm -= 0x80;
8f06b2d8 6464
0313a2b8
NC		 6465 func (stream, "%d", imm);
6466 }
6467
6468 break;
8f06b2d8 6469
32c36c3c
AV		 6470 case 'J':
6471 {
73cd51e5
AV		 6472 unsigned long regno
6473 = arm_decode_field_multiple (given, 13, 15, 22, 22);
32c36c3c
AV		 6474
6475 switch (regno)
6476 {
6477 case 0x1:
6478 func (stream, "FPSCR");
6479 break;
6480 case 0x2:
6481 func (stream, "FPSCR_nzcvqc");
6482 break;
6483 case 0xc:
6484 func (stream, "VPR");
6485 break;
6486 case 0xd:
6487 func (stream, "P0");
6488 break;
6489 case 0xe:
6490 func (stream, "FPCXTNS");
6491 break;
6492 case 0xf:
6493 func (stream, "FPCXTS");
6494 break;
6495 default:
73cd51e5 6496 func (stream, "<invalid reg %lu>", regno);
32c36c3c
AV		 6497 break;
6498 }
6499 }
6500 break;
6501
0313a2b8
NC		 6502 case 'F':
6503 switch (given & 0x00408000)
6504 {
6505 case 0:
6506 func (stream, "4");
6507 break;
6508 case 0x8000:
6509 func (stream, "1");
6510 break;
6511 case 0x00400000:
6512 func (stream, "2");
8f06b2d8 6513 break;
0313a2b8
NC		 6514 default:
6515 func (stream, "3");
6516 }
6517 break;
8f06b2d8 6518
0313a2b8
NC		 6519 case 'P':
6520 switch (given & 0x00080080)
6521 {
6522 case 0:
6523 func (stream, "s");
6524 break;
6525 case 0x80:
6526 func (stream, "d");
6527 break;
6528 case 0x00080000:
6529 func (stream, "e");
6530 break;
6531 default:
6532 func (stream, _("<illegal precision>"));
8f06b2d8 6533 break;
0313a2b8
NC		 6534 }
6535 break;
8f06b2d8 6536
0313a2b8
NC		 6537 case 'Q':
6538 switch (given & 0x00408000)
6539 {
6540 case 0:
6541 func (stream, "s");
8f06b2d8 6542 break;
0313a2b8
NC		 6543 case 0x8000:
6544 func (stream, "d");
8f06b2d8 6545 break;
0313a2b8
NC		 6546 case 0x00400000:
6547 func (stream, "e");
6548 break;
6549 default:
6550 func (stream, "p");
8f06b2d8 6551 break;
0313a2b8
NC		 6552 }
6553 break;
8f06b2d8 6554
0313a2b8
NC		 6555 case 'R':
6556 switch (given & 0x60)
6557 {
6558 case 0:
6559 break;
6560 case 0x20:
6561 func (stream, "p");
6562 break;
6563 case 0x40:
6564 func (stream, "m");
6565 break;
6566 default:
6567 func (stream, "z");
6568 break;
6569 }
6570 break;
16980d0b 6571
0313a2b8
NC		 6572 case '0': case '1': case '2': case '3': case '4':
6573 case '5': case '6': case '7': case '8': case '9':
6574 {
6575 int width;
8f06b2d8 6576
0313a2b8 6577 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 6578
0313a2b8
NC		 6579 switch (*c)
6580 {
ff4a8d2b
NC		 6581 case 'R':
6582 if (value == 15)
6583 is_unpredictable = TRUE;
6584 /* Fall through. */
0313a2b8 6585 case 'r':
ff4a8d2b
NC		 6586 if (c[1] == 'u')
6587 {
6588 /* Eat the 'u' character. */
6589 ++ c;
6590
6591 if (u_reg == value)
6592 is_unpredictable = TRUE;
6593 u_reg = value;
6594 }
0313a2b8
NC		 6595 func (stream, "%s", arm_regnames[value]);
6596 break;
c28eeff2
SN		 6597 case 'V':
6598 if (given & (1 << 6))
6599 goto Q;
6600 /* FALLTHROUGH */
0313a2b8
NC		 6601 case 'D':
6602 func (stream, "d%ld", value);
6603 break;
6604 case 'Q':
c28eeff2 6605 Q:
0313a2b8
NC		 6606 if (value & 1)
6607 func (stream, "<illegal reg q%ld.5>", value >> 1);
6608 else
6609 func (stream, "q%ld", value >> 1);
6610 break;
6611 case 'd':
6612 func (stream, "%ld", value);
05413229 6613 value_in_comment = value;
0313a2b8 6614 break;
6f1c2142
AM		 6615 case 'E':
6616 {
6617 /* Converts immediate 8 bit back to float value. */
6618 unsigned floatVal = (value & 0x80) << 24
6619 | (value & 0x3F) << 19
6620 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
6621
6622 /* Quarter float have a maximum value of 31.0.
6623 Get floating point value multiplied by 1e7.
6624 The maximum value stays in limit of a 32-bit int. */
6625 unsigned decVal =
6626 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
6627 (16 + (value & 0xF));
6628
6629 if (!(decVal % 1000000))
6630 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
6631 floatVal, value & 0x80 ? '-' : ' ',
6632 decVal / 10000000,
6633 decVal % 10000000 / 1000000);
6634 else if (!(decVal % 10000))
6635 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
6636 floatVal, value & 0x80 ? '-' : ' ',
6637 decVal / 10000000,
6638 decVal % 10000000 / 10000);
6639 else
6640 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
6641 floatVal, value & 0x80 ? '-' : ' ',
6642 decVal / 10000000, decVal % 10000000);
6643 break;
6644 }
0313a2b8
NC		 6645 case 'k':
6646 {
6647 int from = (given & (1 << 7)) ? 32 : 16;
6648 func (stream, "%ld", from - value);
6649 }
6650 break;
8f06b2d8 6651
0313a2b8
NC		 6652 case 'f':
6653 if (value > 7)
6654 func (stream, "#%s", arm_fp_const[value & 7]);
6655 else
6656 func (stream, "f%ld", value);
6657 break;
4146fd53 6658
0313a2b8
NC		 6659 case 'w':
6660 if (width == 2)
6661 func (stream, "%s", iwmmxt_wwnames[value]);
6662 else
6663 func (stream, "%s", iwmmxt_wwssnames[value]);
6664 break;
4146fd53 6665
0313a2b8
NC		 6666 case 'g':
6667 func (stream, "%s", iwmmxt_regnames[value]);
6668 break;
6669 case 'G':
6670 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 6671 break;
8f06b2d8 6672
0313a2b8 6673 case 'x':
d1aaab3c 6674 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 6675 break;
8f06b2d8 6676
33399f07
MGD		 6677 case 'c':
6678 switch (value)
6679 {
6680 case 0:
6681 func (stream, "eq");
6682 break;
6683
6684 case 1:
6685 func (stream, "vs");
6686 break;
6687
6688 case 2:
6689 func (stream, "ge");
6690 break;
6691
6692 case 3:
6693 func (stream, "gt");
6694 break;
6695
6696 default:
6697 func (stream, "??");
6698 break;
6699 }
6700 break;
6701
0313a2b8
NC		 6702 case '`':
6703 c++;
6704 if (value == 0)
6705 func (stream, "%c", *c);
6706 break;
6707 case '\'':
6708 c++;
6709 if (value == ((1ul << width) - 1))
6710 func (stream, "%c", *c);
6711 break;
6712 case '?':
fe56b6ce 6713 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 6714 c += 1 << width;
6715 break;
6716 default:
6717 abort ();
6718 }
dffaa15c
AM		 6719 }
6720 break;
0313a2b8 6721
dffaa15c
AM		 6722 case 'y':
6723 case 'z':
6724 {
6725 int single = *c++ == 'y';
6726 int regno;
8f06b2d8 6727
dffaa15c
AM		 6728 switch (*c)
6729 {
6730 case '4': /* Sm pair */
6731 case '0': /* Sm, Dm */
6732 regno = given & 0x0000000f;
6733 if (single)
6734 {
6735 regno <<= 1;
6736 regno += (given >> 5) & 1;
6737 }
6738 else
6739 regno += ((given >> 5) & 1) << 4;
6740 break;
8f06b2d8 6741
dffaa15c
AM		 6742 case '1': /* Sd, Dd */
6743 regno = (given >> 12) & 0x0000000f;
6744 if (single)
6745 {
6746 regno <<= 1;
6747 regno += (given >> 22) & 1;
6748 }
6749 else
6750 regno += ((given >> 22) & 1) << 4;
6751 break;
7df76b80 6752
dffaa15c
AM		 6753 case '2': /* Sn, Dn */
6754 regno = (given >> 16) & 0x0000000f;
6755 if (single)
6756 {
6757 regno <<= 1;
6758 regno += (given >> 7) & 1;
6759 }
6760 else
6761 regno += ((given >> 7) & 1) << 4;
6762 break;
a7f8487e 6763
dffaa15c
AM		 6764 case '3': /* List */
6765 func (stream, "{");
6766 regno = (given >> 12) & 0x0000000f;
6767 if (single)
6768 {
6769 regno <<= 1;
6770 regno += (given >> 22) & 1;
6771 }
6772 else
6773 regno += ((given >> 22) & 1) << 4;
6774 break;
a7f8487e 6775
dffaa15c
AM		 6776 default:
6777 abort ();
6778 }
0313a2b8 6779
dffaa15c 6780 func (stream, "%c%d", single ? 's' : 'd', regno);
a7f8487e 6781
dffaa15c
AM		 6782 if (*c == '3')
6783 {
6784 int count = given & 0xff;
b34976b6 6785
dffaa15c
AM		 6786 if (single == 0)
6787 count >>= 1;
0313a2b8 6788
dffaa15c
AM		 6789 if (--count)
6790 {
6791 func (stream, "-%c%d",
6792 single ? 's' : 'd',
6793 regno + count);
6794 }
0313a2b8 6795
dffaa15c 6796 func (stream, "}");
0313a2b8 6797 }
dffaa15c
AM		 6798 else if (*c == '4')
6799 func (stream, ", %c%d", single ? 's' : 'd',
6800 regno + 1);
6801 }
6802 break;
b34976b6 6803
dffaa15c
AM		 6804 case 'L':
6805 switch (given & 0x00400100)
0313a2b8 6806 {
dffaa15c
AM		 6807 case 0x00000000: func (stream, "b"); break;
6808 case 0x00400000: func (stream, "h"); break;
6809 case 0x00000100: func (stream, "w"); break;
6810 case 0x00400100: func (stream, "d"); break;
6811 default:
6812 break;
0313a2b8 6813 }
dffaa15c 6814 break;
2d447fca 6815
dffaa15c
AM		 6816 case 'Z':
6817 {
6818 /* given (20, 23) | given (0, 3) */
6819 value = ((given >> 16) & 0xf0) | (given & 0xf);
6820 func (stream, "%d", (int) value);
6821 }
6822 break;
0313a2b8 6823
dffaa15c
AM		 6824 case 'l':
6825 /* This is like the 'A' operator, except that if
6826 the width field "M" is zero, then the offset is
6827 *not* multiplied by four. */
6828 {
6829 int offset = given & 0xff;
6830 int multiplier = (given & 0x00000100) ? 4 : 1;
0313a2b8 6831
dffaa15c 6832 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
05413229 6833
dffaa15c
AM		 6834 if (multiplier > 1)
6835 {
6836 value_in_comment = offset * multiplier;
6837 if (NEGATIVE_BIT_SET)
6838 value_in_comment = - value_in_comment;
6839 }
0313a2b8 6840
dffaa15c
AM		 6841 if (offset)
6842 {
6843 if (PRE_BIT_SET)
6844 func (stream, ", #%s%d]%s",
6845 NEGATIVE_BIT_SET ? "-" : "",
6846 offset * multiplier,
6847 WRITEBACK_BIT_SET ? "!" : "");
6848 else
6849 func (stream, "], #%s%d",
6850 NEGATIVE_BIT_SET ? "-" : "",
6851 offset * multiplier);
6852 }
6853 else
6854 func (stream, "]");
6855 }
6856 break;
2d447fca 6857
dffaa15c
AM		 6858 case 'r':
6859 {
6860 int imm4 = (given >> 4) & 0xf;
6861 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
6862 int ubit = ! NEGATIVE_BIT_SET;
6863 const char *rm = arm_regnames [given & 0xf];
6864 const char *rn = arm_regnames [(given >> 16) & 0xf];
0313a2b8 6865
dffaa15c
AM		 6866 switch (puw_bits)
6867 {
6868 case 1:
6869 case 3:
6870 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
6871 if (imm4)
6872 func (stream, ", lsl #%d", imm4);
6873 break;
0313a2b8 6874
dffaa15c
AM		 6875 case 4:
6876 case 5:
6877 case 6:
6878 case 7:
6879 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
6880 if (imm4 > 0)
6881 func (stream, ", lsl #%d", imm4);
6882 func (stream, "]");
6883 if (puw_bits == 5 || puw_bits == 7)
6884 func (stream, "!");
6885 break;
2d447fca 6886
dffaa15c
AM		 6887 default:
6888 func (stream, "INVALID");
6889 }
6890 }
6891 break;
0313a2b8 6892
dffaa15c
AM		 6893 case 'i':
6894 {
6895 long imm5;
6896 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
6897 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
0313a2b8 6898 }
dffaa15c
AM		 6899 break;
6900
6901 default:
6902 abort ();
252b5132 6903 }
252b5132 6904 }
0313a2b8
NC		 6905 else
6906 func (stream, "%c", *c);
252b5132 6907 }
05413229
NC		 6908
6909 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 6910 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 6911
ff4a8d2b
NC		 6912 if (is_unpredictable)
6913 func (stream, UNPREDICTABLE_INSTRUCTION);
6914
0313a2b8 6915 return TRUE;
252b5132 6916 }
8f06b2d8 6917 return FALSE;
252b5132
RH		 6918}
6919
05413229
NC		 6920/* Decodes and prints ARM addressing modes. Returns the offset
6921 used in the address, if any, if it is worthwhile printing the
6922 offset as a hexadecimal value in a comment at the end of the
6923 line of disassembly. */
6924
6925static signed long
62b3e311
PB		 6926print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
6927{
6928 void *stream = info->stream;
6929 fprintf_ftype func = info->fprintf_func;
f8b960bc 6930 bfd_vma offset = 0;
62b3e311
PB		 6931
6932 if (((given & 0x000f0000) == 0x000f0000)
6933 && ((given & 0x02000000) == 0))
6934 {
05413229 6935 offset = given & 0xfff;
62b3e311
PB		 6936
6937 func (stream, "[pc");
6938
c1e26897 6939 if (PRE_BIT_SET)
62b3e311 6940 {
26d97720
NS		 6941 /* Pre-indexed. Elide offset of positive zero when
6942 non-writeback. */
6943 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 6944 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 6945
6946 if (NEGATIVE_BIT_SET)
6947 offset = -offset;
62b3e311
PB		 6948
6949 offset += pc + 8;
6950
6951 /* Cope with the possibility of write-back
6952 being used. Probably a very dangerous thing
6953 for the programmer to do, but who are we to
6954 argue ? */
26d97720 6955 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 6956 }
c1e26897 6957 else /* Post indexed. */
62b3e311 6958 {
d908c8af 6959 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 6960
c1e26897 6961 /* Ie ignore the offset. */
62b3e311
PB		 6962 offset = pc + 8;
6963 }
6964
6965 func (stream, "\t; ");
6966 info->print_address_func (offset, info);
05413229 6967 offset = 0;
62b3e311
PB		 6968 }
6969 else
6970 {
6971 func (stream, "[%s",
6972 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 6973
6974 if (PRE_BIT_SET)
62b3e311
PB		 6975 {
6976 if ((given & 0x02000000) == 0)
6977 {
26d97720 6978 /* Elide offset of positive zero when non-writeback. */
05413229 6979 offset = given & 0xfff;
26d97720 6980 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 6981 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 6982 }
6983 else
6984 {
26d97720 6985 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 6986 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 6987 }
6988
6989 func (stream, "]%s",
c1e26897 6990 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 6991 }
6992 else
6993 {
6994 if ((given & 0x02000000) == 0)
6995 {
26d97720 6996 /* Always show offset. */
05413229 6997 offset = given & 0xfff;
26d97720 6998 func (stream, "], #%s%d",
d908c8af 6999 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 7000 }
7001 else
7002 {
7003 func (stream, "], %s",
c1e26897 7004 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 7005 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 7006 }
7007 }
84919466
MR		 7008 if (NEGATIVE_BIT_SET)
7009 offset = -offset;
62b3e311 7010 }
05413229
NC		 7011
7012 return (signed long) offset;
62b3e311
PB		 7013}
7014
16980d0b
JB		 7015/* Print one neon instruction on INFO->STREAM.
7016 Return TRUE if the instuction matched, FALSE if this is not a
7017 recognised neon instruction. */
7018
7019static bfd_boolean
7020print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
7021{
7022 const struct opcode32 *insn;
7023 void *stream = info->stream;
7024 fprintf_ftype func = info->fprintf_func;
7025
7026 if (thumb)
7027 {
7028 if ((given & 0xef000000) == 0xef000000)
7029 {
0313a2b8 7030 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 7031 unsigned long bit28 = given & (1 << 28);
7032
7033 given &= 0x00ffffff;
7034 if (bit28)
7035 given |= 0xf3000000;
7036 else
7037 given |= 0xf2000000;
7038 }
7039 else if ((given & 0xff000000) == 0xf9000000)
7040 given ^= 0xf9000000 ^ 0xf4000000;
9743db03
AV		 7041 /* vdup is also a valid neon instruction. */
7042 else if ((given & 0xff910f5f) != 0xee800b10)
16980d0b
JB		 7043 return FALSE;
7044 }
43e65147 7045
16980d0b
JB		 7046 for (insn = neon_opcodes; insn->assembler; insn++)
7047 {
7048 if ((given & insn->mask) == insn->value)
7049 {
05413229 7050 signed long value_in_comment = 0;
e2efe87d 7051 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 7052 const char *c;
7053
7054 for (c = insn->assembler; *c; c++)
7055 {
7056 if (*c == '%')
7057 {
7058 switch (*++c)
7059 {
7060 case '%':
7061 func (stream, "%%");
7062 break;
7063
e2efe87d
MGD		 7064 case 'u':
7065 if (thumb && ifthen_state)
7066 is_unpredictable = TRUE;
7067
7068 /* Fall through. */
c22aaad1
PB		 7069 case 'c':
7070 if (thumb && ifthen_state)
7071 func (stream, "%s", arm_conditional[IFTHEN_COND]);
7072 break;
7073
16980d0b
JB		 7074 case 'A':
7075 {
43e65147 7076 static const unsigned char enc[16] =
16980d0b
JB		 7077 {
7078 0x4, 0x14, /* st4 0,1 */
7079 0x4, /* st1 2 */
7080 0x4, /* st2 3 */
7081 0x3, /* st3 4 */
7082 0x13, /* st3 5 */
7083 0x3, /* st1 6 */
7084 0x1, /* st1 7 */
7085 0x2, /* st2 8 */
7086 0x12, /* st2 9 */
7087 0x2, /* st1 10 */
7088 0, 0, 0, 0, 0
7089 };
7090 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
7091 int rn = ((given >> 16) & 0xf);
7092 int rm = ((given >> 0) & 0xf);
7093 int align = ((given >> 4) & 0x3);
7094 int type = ((given >> 8) & 0xf);
7095 int n = enc[type] & 0xf;
7096 int stride = (enc[type] >> 4) + 1;
7097 int ix;
43e65147 7098
16980d0b
JB		 7099 func (stream, "{");
7100 if (stride > 1)
7101 for (ix = 0; ix != n; ix++)
7102 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
7103 else if (n == 1)
7104 func (stream, "d%d", rd);
7105 else
7106 func (stream, "d%d-d%d", rd, rd + n - 1);
7107 func (stream, "}, [%s", arm_regnames[rn]);
7108 if (align)
8e560766 7109 func (stream, " :%d", 32 << align);
16980d0b
JB		 7110 func (stream, "]");
7111 if (rm == 0xd)
7112 func (stream, "!");
7113 else if (rm != 0xf)
7114 func (stream, ", %s", arm_regnames[rm]);
7115 }
7116 break;
43e65147 7117
16980d0b
JB		 7118 case 'B':
7119 {
7120 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
7121 int rn = ((given >> 16) & 0xf);
7122 int rm = ((given >> 0) & 0xf);
7123 int idx_align = ((given >> 4) & 0xf);
7124 int align = 0;
7125 int size = ((given >> 10) & 0x3);
7126 int idx = idx_align >> (size + 1);
7127 int length = ((given >> 8) & 3) + 1;
7128 int stride = 1;
7129 int i;
7130
7131 if (length > 1 && size > 0)
7132 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 7133
16980d0b
JB		 7134 switch (length)
7135 {
7136 case 1:
7137 {
7138 int amask = (1 << size) - 1;
7139 if ((idx_align & (1 << size)) != 0)
7140 return FALSE;
7141 if (size > 0)
7142 {
7143 if ((idx_align & amask) == amask)
7144 align = 8 << size;
7145 else if ((idx_align & amask) != 0)
7146 return FALSE;
7147 }
7148 }
7149 break;
43e65147 7150
16980d0b
JB		 7151 case 2:
7152 if (size == 2 && (idx_align & 2) != 0)
7153 return FALSE;
7154 align = (idx_align & 1) ? 16 << size : 0;
7155 break;
43e65147 7156
16980d0b
JB		 7157 case 3:
7158 if ((size == 2 && (idx_align & 3) != 0)
7159 || (idx_align & 1) != 0)
7160 return FALSE;
7161 break;
43e65147 7162
16980d0b
JB		 7163 case 4:
7164 if (size == 2)
7165 {
7166 if ((idx_align & 3) == 3)
7167 return FALSE;
7168 align = (idx_align & 3) * 64;
7169 }
7170 else
7171 align = (idx_align & 1) ? 32 << size : 0;
7172 break;
43e65147 7173
16980d0b
JB		 7174 default:
7175 abort ();
7176 }
43e65147 7177
16980d0b
JB		 7178 func (stream, "{");
7179 for (i = 0; i < length; i++)
7180 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
7181 rd + i * stride, idx);
7182 func (stream, "}, [%s", arm_regnames[rn]);
7183 if (align)
8e560766 7184 func (stream, " :%d", align);
16980d0b
JB		 7185 func (stream, "]");
7186 if (rm == 0xd)
7187 func (stream, "!");
7188 else if (rm != 0xf)
7189 func (stream, ", %s", arm_regnames[rm]);
7190 }
7191 break;
43e65147 7192
16980d0b
JB		 7193 case 'C':
7194 {
7195 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
7196 int rn = ((given >> 16) & 0xf);
7197 int rm = ((given >> 0) & 0xf);
7198 int align = ((given >> 4) & 0x1);
7199 int size = ((given >> 6) & 0x3);
7200 int type = ((given >> 8) & 0x3);
7201 int n = type + 1;
7202 int stride = ((given >> 5) & 0x1);
7203 int ix;
43e65147 7204
16980d0b
JB		 7205 if (stride && (n == 1))
7206 n++;
7207 else
7208 stride++;
43e65147 7209
16980d0b
JB		 7210 func (stream, "{");
7211 if (stride > 1)
7212 for (ix = 0; ix != n; ix++)
7213 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
7214 else if (n == 1)
7215 func (stream, "d%d[]", rd);
7216 else
7217 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
7218 func (stream, "}, [%s", arm_regnames[rn]);
7219 if (align)
7220 {
91d6fa6a 7221 align = (8 * (type + 1)) << size;
16980d0b
JB		 7222 if (type == 3)
7223 align = (size > 1) ? align >> 1 : align;
7224 if (type == 2 || (type == 0 && !size))
8e560766 7225 func (stream, " :<bad align %d>", align);
16980d0b 7226 else
8e560766 7227 func (stream, " :%d", align);
16980d0b
JB		 7228 }
7229 func (stream, "]");
7230 if (rm == 0xd)
7231 func (stream, "!");
7232 else if (rm != 0xf)
7233 func (stream, ", %s", arm_regnames[rm]);
7234 }
7235 break;
43e65147 7236
16980d0b
JB		 7237 case 'D':
7238 {
7239 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
7240 int size = (given >> 20) & 3;
7241 int reg = raw_reg & ((4 << size) - 1);
7242 int ix = raw_reg >> size >> 2;
43e65147 7243
16980d0b
JB		 7244 func (stream, "d%d[%d]", reg, ix);
7245 }
7246 break;
43e65147 7247
16980d0b 7248 case 'E':
fe56b6ce 7249 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 7250 {
7251 int bits = 0;
7252 int cmode = (given >> 8) & 0xf;
7253 int op = (given >> 5) & 0x1;
7254 unsigned long value = 0, hival = 0;
7255 unsigned shift;
7256 int size = 0;
0dbde4cf 7257 int isfloat = 0;
43e65147 7258
16980d0b
JB		 7259 bits |= ((given >> 24) & 1) << 7;
7260 bits |= ((given >> 16) & 7) << 4;
7261 bits |= ((given >> 0) & 15) << 0;
43e65147 7262
16980d0b
JB		 7263 if (cmode < 8)
7264 {
7265 shift = (cmode >> 1) & 3;
fe56b6ce 7266 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 7267 size = 32;
7268 }
7269 else if (cmode < 12)
7270 {
7271 shift = (cmode >> 1) & 1;
fe56b6ce 7272 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 7273 size = 16;
7274 }
7275 else if (cmode < 14)
7276 {
7277 shift = (cmode & 1) + 1;
fe56b6ce 7278 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 7279 value |= (1ul << (8 * shift)) - 1;
7280 size = 32;
7281 }
7282 else if (cmode == 14)
7283 {
7284 if (op)
7285 {
fe56b6ce 7286 /* Bit replication into bytes. */
16980d0b
JB		 7287 int ix;
7288 unsigned long mask;
43e65147 7289
16980d0b
JB		 7290 value = 0;
7291 hival = 0;
7292 for (ix = 7; ix >= 0; ix--)
7293 {
7294 mask = ((bits >> ix) & 1) ? 0xff : 0;
7295 if (ix <= 3)
7296 value = (value << 8) | mask;
7297 else
7298 hival = (hival << 8) | mask;
7299 }
7300 size = 64;
7301 }
7302 else
7303 {
fe56b6ce
NC		 7304 /* Byte replication. */
7305 value = (unsigned long) bits;
16980d0b
JB		 7306 size = 8;
7307 }
7308 }
7309 else if (!op)
7310 {
fe56b6ce 7311 /* Floating point encoding. */
16980d0b 7312 int tmp;
43e65147 7313
fe56b6ce
NC		 7314 value = (unsigned long) (bits & 0x7f) << 19;
7315 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 7316 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 7317 value |= (unsigned long) tmp << 24;
16980d0b 7318 size = 32;
0dbde4cf 7319 isfloat = 1;
16980d0b
JB		 7320 }
7321 else
7322 {
7323 func (stream, "<illegal constant %.8x:%x:%x>",
7324 bits, cmode, op);
7325 size = 32;
7326 break;
7327 }
7328 switch (size)
7329 {
7330 case 8:
7331 func (stream, "#%ld\t; 0x%.2lx", value, value);
7332 break;
43e65147 7333
16980d0b
JB		 7334 case 16:
7335 func (stream, "#%ld\t; 0x%.4lx", value, value);
7336 break;
7337
7338 case 32:
0dbde4cf
JB		 7339 if (isfloat)
7340 {
7341 unsigned char valbytes[4];
7342 double fvalue;
43e65147 7343
0dbde4cf
JB		 7344 /* Do this a byte at a time so we don't have to
7345 worry about the host's endianness. */
7346 valbytes[0] = value & 0xff;
7347 valbytes[1] = (value >> 8) & 0xff;
7348 valbytes[2] = (value >> 16) & 0xff;
7349 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 7350
7351 floatformat_to_double
c1e26897
NC		 7352 (& floatformat_ieee_single_little, valbytes,
7353 & fvalue);
43e65147 7354
0dbde4cf
JB		 7355 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
7356 value);
7357 }
7358 else
4e9d3b81 7359 func (stream, "#%ld\t; 0x%.8lx",
43e65147 7360 (long) (((value & 0x80000000L) != 0)
9d82ec38 7361 ? value | ~0xffffffffL : value),
c1e26897 7362 value);
16980d0b
JB		 7363 break;
7364
7365 case 64:
7366 func (stream, "#0x%.8lx%.8lx", hival, value);
7367 break;
43e65147 7368
16980d0b
JB		 7369 default:
7370 abort ();
7371 }
7372 }
7373 break;
43e65147 7374
16980d0b
JB		 7375 case 'F':
7376 {
7377 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
7378 int num = (given >> 8) & 0x3;
43e65147 7379
16980d0b
JB		 7380 if (!num)
7381 func (stream, "{d%d}", regno);
7382 else if (num + regno >= 32)
7383 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
7384 else
7385 func (stream, "{d%d-d%d}", regno, regno + num);
7386 }
7387 break;
7e8e6784 7388
16980d0b
JB		 7389
7390 case '0': case '1': case '2': case '3': case '4':
7391 case '5': case '6': case '7': case '8': case '9':
7392 {
7393 int width;
7394 unsigned long value;
7395
7396 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 7397
16980d0b
JB		 7398 switch (*c)
7399 {
7400 case 'r':
7401 func (stream, "%s", arm_regnames[value]);
7402 break;
7403 case 'd':
7404 func (stream, "%ld", value);
05413229 7405 value_in_comment = value;
16980d0b
JB		 7406 break;
7407 case 'e':
7408 func (stream, "%ld", (1ul << width) - value);
7409 break;
43e65147 7410
16980d0b
JB		 7411 case 'S':
7412 case 'T':
7413 case 'U':
05413229 7414 /* Various width encodings. */
16980d0b
JB		 7415 {
7416 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
7417 int limit;
7418 unsigned low, high;
7419
7420 c++;
7421 if (*c >= '0' && *c <= '9')
7422 limit = *c - '0';
7423 else if (*c >= 'a' && *c <= 'f')
7424 limit = *c - 'a' + 10;
7425 else
7426 abort ();
7427 low = limit >> 2;
7428 high = limit & 3;
7429
7430 if (value < low || value > high)
7431 func (stream, "<illegal width %d>", base << value);
7432 else
7433 func (stream, "%d", base << value);
7434 }
7435 break;
7436 case 'R':
7437 if (given & (1 << 6))
7438 goto Q;
7439 /* FALLTHROUGH */
7440 case 'D':
7441 func (stream, "d%ld", value);
7442 break;
7443 case 'Q':
7444 Q:
7445 if (value & 1)
7446 func (stream, "<illegal reg q%ld.5>", value >> 1);
7447 else
7448 func (stream, "q%ld", value >> 1);
7449 break;
43e65147 7450
16980d0b
JB		 7451 case '`':
7452 c++;
7453 if (value == 0)
7454 func (stream, "%c", *c);
7455 break;
7456 case '\'':
7457 c++;
7458 if (value == ((1ul << width) - 1))
7459 func (stream, "%c", *c);
7460 break;
7461 case '?':
fe56b6ce 7462 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 7463 c += 1 << width;
7464 break;
7465 default:
7466 abort ();
7467 }
16980d0b 7468 }
dffaa15c
AM		 7469 break;
7470
7471 default:
7472 abort ();
16980d0b
JB		 7473 }
7474 }
7475 else
7476 func (stream, "%c", *c);
7477 }
05413229
NC		 7478
7479 if (value_in_comment > 32 || value_in_comment < -16)
7480 func (stream, "\t; 0x%lx", value_in_comment);
7481
e2efe87d
MGD		 7482 if (is_unpredictable)
7483 func (stream, UNPREDICTABLE_INSTRUCTION);
7484
16980d0b
JB		 7485 return TRUE;
7486 }
7487 }
7488 return FALSE;
7489}
7490
73cd51e5
AV		 7491/* Print one mve instruction on INFO->STREAM.
7492 Return TRUE if the instuction matched, FALSE if this is not a
7493 recognised mve instruction. */
7494
7495static bfd_boolean
7496print_insn_mve (struct disassemble_info *info, long given)
7497{
7498 const struct mopcode32 *insn;
7499 void *stream = info->stream;
7500 fprintf_ftype func = info->fprintf_func;
7501
7502 for (insn = mve_opcodes; insn->assembler; insn++)
7503 {
7504 if (((given & insn->mask) == insn->value)
7505 && !is_mve_encoding_conflict (given, insn->mve_op))
7506 {
7507 signed long value_in_comment = 0;
7508 bfd_boolean is_unpredictable = FALSE;
7509 bfd_boolean is_undefined = FALSE;
7510 const char *c;
7511 enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
7512 enum mve_undefined undefined_cond = UNDEF_NONE;
7513
7514 /* Most vector mve instruction are illegal in a it block.
7515 There are a few exceptions; check for them. */
7516 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
7517 {
7518 is_unpredictable = TRUE;
7519 unpredictable_cond = UNPRED_IT_BLOCK;
7520 }
7521 else if (is_mve_unpredictable (given, insn->mve_op,
7522 &unpredictable_cond))
7523 is_unpredictable = TRUE;
7524
7525 if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
7526 is_undefined = TRUE;
7527
7528 for (c = insn->assembler; *c; c++)
7529 {
7530 if (*c == '%')
7531 {
7532 switch (*++c)
7533 {
7534 case '%':
7535 func (stream, "%%");
7536 break;
7537
ef1576a1
AV		 7538 case 'a':
7539 /* Don't print anything for '+' as it is implied. */
7540 if (arm_decode_field (given, 23, 23) == 0)
7541 func (stream, "-");
7542 break;
7543
143275ea
AV		 7544 case 'c':
7545 if (ifthen_state)
7546 func (stream, "%s", arm_conditional[IFTHEN_COND]);
7547 break;
7548
aef6d006
AV		 7549 case 'd':
7550 print_mve_vld_str_addr (info, given, insn->mve_op);
7551 break;
7552
143275ea
AV		 7553 case 'i':
7554 {
7555 long mve_mask = mve_extract_pred_mask (given);
7556 func (stream, "%s", mve_predicatenames[mve_mask]);
7557 }
7558 break;
7559
7560 case 'n':
7561 print_vec_condition (info, given, insn->mve_op);
7562 break;
7563
ef1576a1
AV		 7564 case 'o':
7565 if (arm_decode_field (given, 0, 0) == 1)
7566 {
7567 unsigned long size
7568 = arm_decode_field (given, 4, 4)
7569 | (arm_decode_field (given, 6, 6) << 1);
7570
7571 func (stream, ", uxtw #%lu", size);
7572 }
7573 break;
7574
bf0b396d
AV		 7575 case 'm':
7576 print_mve_rounding_mode (info, given, insn->mve_op);
7577 break;
7578
7579 case 's':
7580 print_mve_vcvt_size (info, given, insn->mve_op);
7581 break;
7582
aef6d006
AV		 7583 case 'u':
7584 {
c507f10b
AV		 7585 unsigned long op1 = arm_decode_field (given, 21, 22);
7586
7587 if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
7588 {
7589 /* Check for signed. */
7590 if (arm_decode_field (given, 23, 23) == 0)
7591 {
7592 /* We don't print 's' for S32. */
7593 if ((arm_decode_field (given, 5, 6) == 0)
7594 && ((op1 == 0) || (op1 == 1)))
7595 ;
7596 else
7597 func (stream, "s");
7598 }
7599 else
7600 func (stream, "u");
7601 }
aef6d006 7602 else
c507f10b
AV		 7603 {
7604 if (arm_decode_field (given, 28, 28) == 0)
7605 func (stream, "s");
7606 else
7607 func (stream, "u");
7608 }
aef6d006 7609 }
ef1576a1 7610 break;
aef6d006 7611
143275ea
AV		 7612 case 'v':
7613 print_instruction_predicate (info);
7614 break;
7615
04d54ace
AV		 7616 case 'w':
7617 if (arm_decode_field (given, 21, 21) == 1)
7618 func (stream, "!");
7619 break;
7620
7621 case 'B':
7622 print_mve_register_blocks (info, given, insn->mve_op);
7623 break;
7624
c507f10b
AV		 7625 case 'E':
7626 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
7627
7628 print_simd_imm8 (info, given, 28, insn);
7629 break;
7630
7631 case 'N':
7632 print_mve_vmov_index (info, given);
7633 break;
7634
14925797
AV		 7635 case 'T':
7636 if (arm_decode_field (given, 12, 12) == 0)
7637 func (stream, "b");
7638 else
7639 func (stream, "t");
7640 break;
7641
143275ea
AV		 7642 case '0': case '1': case '2': case '3': case '4':
7643 case '5': case '6': case '7': case '8': case '9':
7644 {
7645 int width;
7646 unsigned long value;
7647
7648 c = arm_decode_bitfield (c, given, &value, &width);
7649
7650 switch (*c)
7651 {
7652 case 'Z':
7653 if (value == 13)
7654 is_unpredictable = TRUE;
7655 else if (value == 15)
7656 func (stream, "zr");
7657 else
7658 func (stream, "%s", arm_regnames[value]);
7659 break;
7660 case 's':
7661 print_mve_size (info,
7662 value,
7663 insn->mve_op);
7664 break;
ef1576a1
AV		 7665 case 'i':
7666 {
7667 unsigned long imm
7668 = arm_decode_field (given, 0, 6);
7669 unsigned long mod_imm = imm;
7670
7671 switch (insn->mve_op)
7672 {
7673 case MVE_VLDRW_GATHER_T5:
7674 case MVE_VSTRW_SCATTER_T5:
7675 mod_imm = mod_imm << 2;
7676 break;
7677 case MVE_VSTRD_SCATTER_T6:
7678 case MVE_VLDRD_GATHER_T6:
7679 mod_imm = mod_imm << 3;
7680 break;
7681
7682 default:
7683 break;
7684 }
7685
7686 func (stream, "%lu", mod_imm);
7687 }
7688 break;
bf0b396d
AV		 7689 case 'k':
7690 func (stream, "%lu", 64 - value);
7691 break;
9743db03
AV		 7692 case 'r':
7693 func (stream, "%s", arm_regnames[value]);
7694 break;
04d54ace
AV		 7695 case 'd':
7696 func (stream, "%ld", value);
7697 value_in_comment = value;
7698 break;
c507f10b
AV		 7699 case 'F':
7700 func (stream, "s%ld", value);
7701 break;
143275ea
AV		 7702 case 'Q':
7703 if (value & 0x8)
7704 func (stream, "<illegal reg q%ld.5>", value);
7705 else
7706 func (stream, "q%ld", value);
7707 break;
c507f10b
AV		 7708 case 'x':
7709 func (stream, "0x%08lx", value);
7710 break;
143275ea
AV		 7711 default:
7712 abort ();
7713 }
7714 break;
7715 default:
7716 abort ();
7717 }
73cd51e5
AV		 7718 }
7719 }
7720 else
7721 func (stream, "%c", *c);
7722 }
7723
7724 if (value_in_comment > 32 || value_in_comment < -16)
7725 func (stream, "\t; 0x%lx", value_in_comment);
7726
7727 if (is_unpredictable)
7728 print_mve_unpredictable (info, unpredictable_cond);
7729
7730 if (is_undefined)
7731 print_mve_undefined (info, undefined_cond);
7732
143275ea
AV		 7733 if ((vpt_block_state.in_vpt_block == FALSE)
7734 && !ifthen_state
7735 && (is_vpt_instruction (given) == TRUE))
7736 mark_inside_vpt_block (given);
7737 else if (vpt_block_state.in_vpt_block == TRUE)
7738 update_vpt_block_state ();
7739
73cd51e5
AV		 7740 return TRUE;
7741 }
7742 }
7743 return FALSE;
7744}
7745
7746
90ec0d68
MGD		 7747/* Return the name of a v7A special register. */
7748
43e65147 7749static const char *
90ec0d68
MGD		 7750banked_regname (unsigned reg)
7751{
7752 switch (reg)
7753 {
7754 case 15: return "CPSR";
43e65147 7755 case 32: return "R8_usr";
90ec0d68
MGD		 7756 case 33: return "R9_usr";
7757 case 34: return "R10_usr";
7758 case 35: return "R11_usr";
7759 case 36: return "R12_usr";
7760 case 37: return "SP_usr";
7761 case 38: return "LR_usr";
43e65147 7762 case 40: return "R8_fiq";
90ec0d68
MGD		 7763 case 41: return "R9_fiq";
7764 case 42: return "R10_fiq";
7765 case 43: return "R11_fiq";
7766 case 44: return "R12_fiq";
7767 case 45: return "SP_fiq";
7768 case 46: return "LR_fiq";
7769 case 48: return "LR_irq";
7770 case 49: return "SP_irq";
7771 case 50: return "LR_svc";
7772 case 51: return "SP_svc";
7773 case 52: return "LR_abt";
7774 case 53: return "SP_abt";
7775 case 54: return "LR_und";
7776 case 55: return "SP_und";
7777 case 60: return "LR_mon";
7778 case 61: return "SP_mon";
7779 case 62: return "ELR_hyp";
7780 case 63: return "SP_hyp";
7781 case 79: return "SPSR";
7782 case 110: return "SPSR_fiq";
7783 case 112: return "SPSR_irq";
7784 case 114: return "SPSR_svc";
7785 case 116: return "SPSR_abt";
7786 case 118: return "SPSR_und";
7787 case 124: return "SPSR_mon";
7788 case 126: return "SPSR_hyp";
7789 default: return NULL;
7790 }
7791}
7792
e797f7e0
MGD		 7793/* Return the name of the DMB/DSB option. */
7794static const char *
7795data_barrier_option (unsigned option)
7796{
7797 switch (option & 0xf)
7798 {
7799 case 0xf: return "sy";
7800 case 0xe: return "st";
7801 case 0xd: return "ld";
7802 case 0xb: return "ish";
7803 case 0xa: return "ishst";
7804 case 0x9: return "ishld";
7805 case 0x7: return "un";
7806 case 0x6: return "unst";
7807 case 0x5: return "nshld";
7808 case 0x3: return "osh";
7809 case 0x2: return "oshst";
7810 case 0x1: return "oshld";
7811 default: return NULL;
7812 }
7813}
7814
4a5329c6
ZW		 7815/* Print one ARM instruction from PC on INFO->STREAM. */
7816
7817static void
7818print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 7819{
6b5d3a4d 7820 const struct opcode32 *insn;
6a51a8a8 7821 void *stream = info->stream;
6b5d3a4d 7822 fprintf_ftype func = info->fprintf_func;
b0e28b39 7823 struct arm_private_data *private_data = info->private_data;
252b5132 7824
16980d0b
JB		 7825 if (print_insn_coprocessor (pc, info, given, FALSE))
7826 return;
7827
7828 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 7829 return;
7830
252b5132
RH		 7831 for (insn = arm_opcodes; insn->assembler; insn++)
7832 {
0313a2b8
NC		 7833 if ((given & insn->mask) != insn->value)
7834 continue;
823d2571
TG		 7835
7836 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 7837 continue;
7838
7839 /* Special case: an instruction with all bits set in the condition field
7840 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
7841 or by the catchall at the end of the table. */
7842 if ((given & 0xF0000000) != 0xF0000000
7843 || (insn->mask & 0xF0000000) == 0xF0000000
7844 || (insn->mask == 0 && insn->value == 0))
252b5132 7845 {
ff4a8d2b
NC		 7846 unsigned long u_reg = 16;
7847 unsigned long U_reg = 16;
ab8e2090 7848 bfd_boolean is_unpredictable = FALSE;
05413229 7849 signed long value_in_comment = 0;
6b5d3a4d 7850 const char *c;
b34976b6 7851
252b5132
RH		 7852 for (c = insn->assembler; *c; c++)
7853 {
7854 if (*c == '%')
7855 {
c1e26897
NC		 7856 bfd_boolean allow_unpredictable = FALSE;
7857
252b5132
RH		 7858 switch (*++c)
7859 {
7860 case '%':
7861 func (stream, "%%");
7862 break;
7863
7864 case 'a':
05413229 7865 value_in_comment = print_arm_address (pc, info, given);
62b3e311 7866 break;
252b5132 7867
62b3e311
PB		 7868 case 'P':
7869 /* Set P address bit and use normal address
7870 printing routine. */
c1e26897 7871 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 7872 break;
7873
c1e26897
NC		 7874 case 'S':
7875 allow_unpredictable = TRUE;
1a0670f3 7876 /* Fall through. */
252b5132
RH		 7877 case 's':
7878 if ((given & 0x004f0000) == 0x004f0000)
7879 {
58efb6c0 7880 /* PC relative with immediate offset. */
f8b960bc 7881 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 7882
aefd8a40
NC		 7883 if (PRE_BIT_SET)
7884 {
26d97720
NS		 7885 /* Elide positive zero offset. */
7886 if (offset || NEGATIVE_BIT_SET)
7887 func (stream, "[pc, #%s%d]\t; ",
d908c8af 7888 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 7889 else
26d97720
NS		 7890 func (stream, "[pc]\t; ");
7891 if (NEGATIVE_BIT_SET)
7892 offset = -offset;
aefd8a40
NC		 7893 info->print_address_func (offset + pc + 8, info);
7894 }
7895 else
7896 {
26d97720
NS		 7897 /* Always show the offset. */
7898 func (stream, "[pc], #%s%d",
d908c8af 7899 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 7900 if (! allow_unpredictable)
7901 is_unpredictable = TRUE;
aefd8a40 7902 }
252b5132
RH		 7903 }
7904 else
7905 {
fe56b6ce
NC		 7906 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
7907
b34976b6 7908 func (stream, "[%s",
252b5132 7909 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 7910
c1e26897 7911 if (PRE_BIT_SET)
252b5132 7912 {
c1e26897 7913 if (IMMEDIATE_BIT_SET)
252b5132 7914 {
26d97720
NS		 7915 /* Elide offset for non-writeback
7916 positive zero. */
7917 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
7918 || offset)
7919 func (stream, ", #%s%d",
7920 NEGATIVE_BIT_SET ? "-" : "", offset);
7921
7922 if (NEGATIVE_BIT_SET)
7923 offset = -offset;
945ee430 7924
fe56b6ce 7925 value_in_comment = offset;
252b5132 7926 }
945ee430 7927 else
ff4a8d2b
NC		 7928 {
7929 /* Register Offset or Register Pre-Indexed. */
7930 func (stream, ", %s%s",
7931 NEGATIVE_BIT_SET ? "-" : "",
7932 arm_regnames[given & 0xf]);
7933
7934 /* Writing back to the register that is the source/
7935 destination of the load/store is unpredictable. */
7936 if (! allow_unpredictable
7937 && WRITEBACK_BIT_SET
7938 && ((given & 0xf) == ((given >> 12) & 0xf)))
7939 is_unpredictable = TRUE;
7940 }
252b5132 7941
b34976b6 7942 func (stream, "]%s",
c1e26897 7943 WRITEBACK_BIT_SET ? "!" : "");
252b5132 7944 }
945ee430 7945 else
252b5132 7946 {
c1e26897 7947 if (IMMEDIATE_BIT_SET)
252b5132 7948 {
945ee430 7949 /* Immediate Post-indexed. */
aefd8a40 7950 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 7951 func (stream, "], #%s%d",
7952 NEGATIVE_BIT_SET ? "-" : "", offset);
7953 if (NEGATIVE_BIT_SET)
7954 offset = -offset;
fe56b6ce 7955 value_in_comment = offset;
252b5132 7956 }
945ee430 7957 else
ff4a8d2b
NC		 7958 {
7959 /* Register Post-indexed. */
7960 func (stream, "], %s%s",
7961 NEGATIVE_BIT_SET ? "-" : "",
7962 arm_regnames[given & 0xf]);
7963
7964 /* Writing back to the register that is the source/
7965 destination of the load/store is unpredictable. */
7966 if (! allow_unpredictable
7967 && (given & 0xf) == ((given >> 12) & 0xf))
7968 is_unpredictable = TRUE;
7969 }
c1e26897 7970
07a28fab
NC		 7971 if (! allow_unpredictable)
7972 {
7973 /* Writeback is automatically implied by post- addressing.
7974 Setting the W bit is unnecessary and ARM specify it as
7975 being unpredictable. */
7976 if (WRITEBACK_BIT_SET
7977 /* Specifying the PC register as the post-indexed
7978 registers is also unpredictable. */
ab8e2090
NC		 7979 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
7980 is_unpredictable = TRUE;
07a28fab 7981 }
252b5132
RH		 7982 }
7983 }
7984 break;
b34976b6 7985
252b5132 7986 case 'b':
6b5d3a4d 7987 {
f8b960bc 7988 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
05413229 7989 info->print_address_func (disp * 4 + pc + 8, info);
6b5d3a4d 7990 }
252b5132
RH		 7991 break;
7992
7993 case 'c':
c22aaad1
PB		 7994 if (((given >> 28) & 0xf) != 0xe)
7995 func (stream, "%s",
7996 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 7997 break;
7998
7999 case 'm':
8000 {
8001 int started = 0;
8002 int reg;
8003
8004 func (stream, "{");
8005 for (reg = 0; reg < 16; reg++)
8006 if ((given & (1 << reg)) != 0)
8007 {
8008 if (started)
8009 func (stream, ", ");
8010 started = 1;
8011 func (stream, "%s", arm_regnames[reg]);
8012 }
8013 func (stream, "}");
ab8e2090
NC		 8014 if (! started)
8015 is_unpredictable = TRUE;
252b5132
RH		 8016 }
8017 break;
8018
37b37b2d 8019 case 'q':
78c66db8 8020 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 8021 break;
8022
252b5132
RH		 8023 case 'o':
8024 if ((given & 0x02000000) != 0)
8025 {
a415b1cd
JB		 8026 unsigned int rotate = (given & 0xf00) >> 7;
8027 unsigned int immed = (given & 0xff);
8028 unsigned int a, i;
8029
8030 a = (((immed << (32 - rotate))
8031 | (immed >> rotate)) & 0xffffffff);
8032 /* If there is another encoding with smaller rotate,
8033 the rotate should be specified directly. */
8034 for (i = 0; i < 32; i += 2)
8035 if ((a << i | a >> (32 - i)) <= 0xff)
8036 break;
8037
8038 if (i != rotate)
8039 func (stream, "#%d, %d", immed, rotate);
8040 else
8041 func (stream, "#%d", a);
8042 value_in_comment = a;
252b5132
RH		 8043 }
8044 else
78c66db8 8045 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 8046 break;
8047
8048 case 'p':
8049 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 8050 {
823d2571
TG		 8051 arm_feature_set arm_ext_v6 =
8052 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
8053
aefd8a40
NC		 8054 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
8055 mechanism for setting PSR flag bits. They are
8056 obsolete in V6 onwards. */
823d2571
TG		 8057 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
8058 arm_ext_v6))
aefd8a40 8059 func (stream, "p");
4ab90a7a
AV		 8060 else
8061 is_unpredictable = TRUE;
aefd8a40 8062 }
252b5132
RH		 8063 break;
8064
8065 case 't':
8066 if ((given & 0x01200000) == 0x00200000)
8067 func (stream, "t");
8068 break;
8069
252b5132 8070 case 'A':
05413229
NC		 8071 {
8072 int offset = given & 0xff;
f02232aa 8073
05413229 8074 value_in_comment = offset * 4;
c1e26897 8075 if (NEGATIVE_BIT_SET)
05413229 8076 value_in_comment = - value_in_comment;
f02232aa 8077
05413229 8078 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 8079
c1e26897 8080 if (PRE_BIT_SET)
05413229
NC		 8081 {
8082 if (offset)
fe56b6ce 8083 func (stream, ", #%d]%s",
d908c8af 8084 (int) value_in_comment,
c1e26897 8085 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 8086 else
8087 func (stream, "]");
8088 }
8089 else
8090 {
8091 func (stream, "]");
f02232aa 8092
c1e26897 8093 if (WRITEBACK_BIT_SET)
05413229
NC		 8094 {
8095 if (offset)
d908c8af 8096 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 8097 }
8098 else
fe56b6ce 8099 {
d908c8af 8100 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 8101 value_in_comment = offset;
8102 }
05413229
NC		 8103 }
8104 }
252b5132
RH		 8105 break;
8106
077b8428
NC		 8107 case 'B':
8108 /* Print ARM V5 BLX(1) address: pc+25 bits. */
8109 {
8110 bfd_vma address;
8111 bfd_vma offset = 0;
b34976b6 8112
c1e26897 8113 if (! NEGATIVE_BIT_SET)
077b8428
NC		 8114 /* Is signed, hi bits should be ones. */
8115 offset = (-1) ^ 0x00ffffff;
8116
8117 /* Offset is (SignExtend(offset field)<<2). */
8118 offset += given & 0x00ffffff;
8119 offset <<= 2;
8120 address = offset + pc + 8;
b34976b6 8121
8f06b2d8
PB		 8122 if (given & 0x01000000)
8123 /* H bit allows addressing to 2-byte boundaries. */
8124 address += 2;
b1ee46c5 8125
8f06b2d8 8126 info->print_address_func (address, info);
b1ee46c5 8127 }
b1ee46c5
AH		 8128 break;
8129
252b5132 8130 case 'C':
90ec0d68
MGD		 8131 if ((given & 0x02000200) == 0x200)
8132 {
8133 const char * name;
8134 unsigned sysm = (given & 0x004f0000) >> 16;
8135
8136 sysm |= (given & 0x300) >> 4;
8137 name = banked_regname (sysm);
8138
8139 if (name != NULL)
8140 func (stream, "%s", name);
8141 else
d908c8af 8142 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 8143 }
8144 else
8145 {
43e65147 8146 func (stream, "%cPSR_",
90ec0d68
MGD		 8147 (given & 0x00400000) ? 'S' : 'C');
8148 if (given & 0x80000)
8149 func (stream, "f");
8150 if (given & 0x40000)
8151 func (stream, "s");
8152 if (given & 0x20000)
8153 func (stream, "x");
8154 if (given & 0x10000)
8155 func (stream, "c");
8156 }
252b5132
RH		 8157 break;
8158
62b3e311 8159 case 'U':
43e65147 8160 if ((given & 0xf0) == 0x60)
62b3e311 8161 {
52e7f43d
RE		 8162 switch (given & 0xf)
8163 {
8164 case 0xf: func (stream, "sy"); break;
8165 default:
8166 func (stream, "#%d", (int) given & 0xf);
8167 break;
8168 }
43e65147
L		 8169 }
8170 else
52e7f43d 8171 {
e797f7e0
MGD		 8172 const char * opt = data_barrier_option (given & 0xf);
8173 if (opt != NULL)
8174 func (stream, "%s", opt);
8175 else
52e7f43d 8176 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 8177 }
8178 break;
8179
b34976b6 8180 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 8181 case '5': case '6': case '7': case '8': case '9':
8182 {
16980d0b
JB		 8183 int width;
8184 unsigned long value;
252b5132 8185
16980d0b 8186 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 8187
252b5132
RH		 8188 switch (*c)
8189 {
ab8e2090
NC		 8190 case 'R':
8191 if (value == 15)
8192 is_unpredictable = TRUE;
8193 /* Fall through. */
16980d0b 8194 case 'r':
9eb6c0f1
MGD		 8195 case 'T':
8196 /* We want register + 1 when decoding T. */
8197 if (*c == 'T')
8198 ++value;
8199
ff4a8d2b
NC		 8200 if (c[1] == 'u')
8201 {
8202 /* Eat the 'u' character. */
8203 ++ c;
8204
8205 if (u_reg == value)
8206 is_unpredictable = TRUE;
8207 u_reg = value;
8208 }
8209 if (c[1] == 'U')
8210 {
8211 /* Eat the 'U' character. */
8212 ++ c;
8213
8214 if (U_reg == value)
8215 is_unpredictable = TRUE;
8216 U_reg = value;
8217 }
16980d0b
JB		 8218 func (stream, "%s", arm_regnames[value]);
8219 break;
8220 case 'd':
8221 func (stream, "%ld", value);
05413229 8222 value_in_comment = value;
16980d0b
JB		 8223 break;
8224 case 'b':
8225 func (stream, "%ld", value * 8);
05413229 8226 value_in_comment = value * 8;
16980d0b
JB		 8227 break;
8228 case 'W':
8229 func (stream, "%ld", value + 1);
05413229 8230 value_in_comment = value + 1;
16980d0b
JB		 8231 break;
8232 case 'x':
8233 func (stream, "0x%08lx", value);
8234
8235 /* Some SWI instructions have special
8236 meanings. */
8237 if ((given & 0x0fffffff) == 0x0FF00000)
8238 func (stream, "\t; IMB");
8239 else if ((given & 0x0fffffff) == 0x0FF00001)
8240 func (stream, "\t; IMBRange");
8241 break;
8242 case 'X':
8243 func (stream, "%01lx", value & 0xf);
05413229 8244 value_in_comment = value;
252b5132
RH		 8245 break;
8246 case '`':
8247 c++;
16980d0b 8248 if (value == 0)
252b5132
RH		 8249 func (stream, "%c", *c);
8250 break;
8251 case '\'':
8252 c++;
16980d0b 8253 if (value == ((1ul << width) - 1))
252b5132
RH		 8254 func (stream, "%c", *c);
8255 break;
8256 case '?':
fe56b6ce 8257 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 8258 c += 1 << width;
252b5132
RH		 8259 break;
8260 default:
8261 abort ();
8262 }
dffaa15c
AM		 8263 }
8264 break;
0dd132b6 8265
dffaa15c
AM		 8266 case 'e':
8267 {
8268 int imm;
0dd132b6 8269
dffaa15c
AM		 8270 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
8271 func (stream, "%d", imm);
8272 value_in_comment = imm;
8273 }
8274 break;
fe56b6ce 8275
dffaa15c
AM		 8276 case 'E':
8277 /* LSB and WIDTH fields of BFI or BFC. The machine-
8278 language instruction encodes LSB and MSB. */
8279 {
8280 long msb = (given & 0x001f0000) >> 16;
8281 long lsb = (given & 0x00000f80) >> 7;
8282 long w = msb - lsb + 1;
0a003adc 8283
dffaa15c
AM		 8284 if (w > 0)
8285 func (stream, "#%lu, #%lu", lsb, w);
8286 else
8287 func (stream, "(invalid: %lu:%lu)", lsb, msb);
8288 }
8289 break;
90ec0d68 8290
dffaa15c
AM		 8291 case 'R':
8292 /* Get the PSR/banked register name. */
8293 {
8294 const char * name;
8295 unsigned sysm = (given & 0x004f0000) >> 16;
90ec0d68 8296
dffaa15c
AM		 8297 sysm |= (given & 0x300) >> 4;
8298 name = banked_regname (sysm);
90ec0d68 8299
dffaa15c
AM		 8300 if (name != NULL)
8301 func (stream, "%s", name);
8302 else
8303 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
8304 }
8305 break;
fe56b6ce 8306
dffaa15c
AM		 8307 case 'V':
8308 /* 16-bit unsigned immediate from a MOVT or MOVW
8309 instruction, encoded in bits 0:11 and 15:19. */
8310 {
8311 long hi = (given & 0x000f0000) >> 4;
8312 long lo = (given & 0x00000fff);
8313 long imm16 = hi | lo;
0a003adc 8314
dffaa15c
AM		 8315 func (stream, "#%lu", imm16);
8316 value_in_comment = imm16;
252b5132 8317 }
dffaa15c
AM		 8318 break;
8319
8320 default:
8321 abort ();
252b5132
RH		 8322 }
8323 }
8324 else
8325 func (stream, "%c", *c);
8326 }
05413229
NC		 8327
8328 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 8329 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 8330
8331 if (is_unpredictable)
8332 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 8333
4a5329c6 8334 return;
252b5132
RH		 8335 }
8336 }
0b347048
TC		 8337 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
8338 return;
252b5132
RH		 8339}
8340
4a5329c6 8341/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 8342
4a5329c6
ZW		 8343static void
8344print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 8345{
6b5d3a4d 8346 const struct opcode16 *insn;
6a51a8a8
AM		 8347 void *stream = info->stream;
8348 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 8349
8350 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 8351 if ((given & insn->mask) == insn->value)
8352 {
05413229 8353 signed long value_in_comment = 0;
6b5d3a4d 8354 const char *c = insn->assembler;
05413229 8355
c19d1205
ZW		 8356 for (; *c; c++)
8357 {
8358 int domaskpc = 0;
8359 int domasklr = 0;
8360
8361 if (*c != '%')
8362 {
8363 func (stream, "%c", *c);
8364 continue;
8365 }
252b5132 8366
c19d1205
ZW		 8367 switch (*++c)
8368 {
8369 case '%':
8370 func (stream, "%%");
8371 break;
b34976b6 8372
c22aaad1
PB		 8373 case 'c':
8374 if (ifthen_state)
8375 func (stream, "%s", arm_conditional[IFTHEN_COND]);
8376 break;
8377
8378 case 'C':
8379 if (ifthen_state)
8380 func (stream, "%s", arm_conditional[IFTHEN_COND]);
8381 else
8382 func (stream, "s");
8383 break;
8384
8385 case 'I':
8386 {
8387 unsigned int tmp;
8388
8389 ifthen_next_state = given & 0xff;
8390 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
8391 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
8392 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
8393 }
8394 break;
8395
8396 case 'x':
8397 if (ifthen_next_state)
8398 func (stream, "\t; unpredictable branch in IT block\n");
8399 break;
8400
8401 case 'X':
8402 if (ifthen_state)
8403 func (stream, "\t; unpredictable <IT:%s>",
8404 arm_conditional[IFTHEN_COND]);
8405 break;
8406
c19d1205
ZW		 8407 case 'S':
8408 {
8409 long reg;
8410
8411 reg = (given >> 3) & 0x7;
8412 if (given & (1 << 6))
8413 reg += 8;
4f3c3dbb 8414
c19d1205
ZW		 8415 func (stream, "%s", arm_regnames[reg]);
8416 }
8417 break;
baf0cc5e 8418
c19d1205 8419 case 'D':
4f3c3dbb 8420 {
c19d1205
ZW		 8421 long reg;
8422
8423 reg = given & 0x7;
8424 if (given & (1 << 7))
8425 reg += 8;
8426
8427 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 8428 }
c19d1205
ZW		 8429 break;
8430
8431 case 'N':
8432 if (given & (1 << 8))
8433 domasklr = 1;
8434 /* Fall through. */
8435 case 'O':
8436 if (*c == 'O' && (given & (1 << 8)))
8437 domaskpc = 1;
8438 /* Fall through. */
8439 case 'M':
8440 {
8441 int started = 0;
8442 int reg;
8443
8444 func (stream, "{");
8445
8446 /* It would be nice if we could spot
8447 ranges, and generate the rS-rE format: */
8448 for (reg = 0; (reg < 8); reg++)
8449 if ((given & (1 << reg)) != 0)
8450 {
8451 if (started)
8452 func (stream, ", ");
8453 started = 1;
8454 func (stream, "%s", arm_regnames[reg]);
8455 }
8456
8457 if (domasklr)
8458 {
8459 if (started)
8460 func (stream, ", ");
8461 started = 1;
d908c8af 8462 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 8463 }
8464
8465 if (domaskpc)
8466 {
8467 if (started)
8468 func (stream, ", ");
d908c8af 8469 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 8470 }
8471
8472 func (stream, "}");
8473 }
8474 break;
8475
4547cb56
NC		 8476 case 'W':
8477 /* Print writeback indicator for a LDMIA. We are doing a
8478 writeback if the base register is not in the register
8479 mask. */
8480 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
8481 func (stream, "!");
dffaa15c 8482 break;
4547cb56 8483
c19d1205
ZW		 8484 case 'b':
8485 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
8486 {
8487 bfd_vma address = (pc + 4
8488 + ((given & 0x00f8) >> 2)
8489 + ((given & 0x0200) >> 3));
8490 info->print_address_func (address, info);
8491 }
8492 break;
8493
8494 case 's':
8495 /* Right shift immediate -- bits 6..10; 1-31 print
8496 as themselves, 0 prints as 32. */
8497 {
8498 long imm = (given & 0x07c0) >> 6;
8499 if (imm == 0)
8500 imm = 32;
0fd3a477 8501 func (stream, "#%ld", imm);
c19d1205
ZW		 8502 }
8503 break;
8504
8505 case '0': case '1': case '2': case '3': case '4':
8506 case '5': case '6': case '7': case '8': case '9':
8507 {
8508 int bitstart = *c++ - '0';
8509 int bitend = 0;
8510
8511 while (*c >= '0' && *c <= '9')
8512 bitstart = (bitstart * 10) + *c++ - '0';
8513
8514 switch (*c)
8515 {
8516 case '-':
8517 {
f8b960bc 8518 bfd_vma reg;
c19d1205
ZW		 8519
8520 c++;
8521 while (*c >= '0' && *c <= '9')
8522 bitend = (bitend * 10) + *c++ - '0';
8523 if (!bitend)
8524 abort ();
8525 reg = given >> bitstart;
8526 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 8527
c19d1205
ZW		 8528 switch (*c)
8529 {
8530 case 'r':
8531 func (stream, "%s", arm_regnames[reg]);
8532 break;
8533
8534 case 'd':
d908c8af 8535 func (stream, "%ld", (long) reg);
05413229 8536 value_in_comment = reg;
c19d1205
ZW		 8537 break;
8538
8539 case 'H':
d908c8af 8540 func (stream, "%ld", (long) (reg << 1));
05413229 8541 value_in_comment = reg << 1;
c19d1205
ZW		 8542 break;
8543
8544 case 'W':
d908c8af 8545 func (stream, "%ld", (long) (reg << 2));
05413229 8546 value_in_comment = reg << 2;
c19d1205
ZW		 8547 break;
8548
8549 case 'a':
8550 /* PC-relative address -- the bottom two
8551 bits of the address are dropped
8552 before the calculation. */
8553 info->print_address_func
8554 (((pc + 4) & ~3) + (reg << 2), info);
05413229 8555 value_in_comment = 0;
c19d1205
ZW		 8556 break;
8557
8558 case 'x':
d908c8af 8559 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 8560 break;
8561
c19d1205
ZW		 8562 case 'B':
8563 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6b5d3a4d 8564 info->print_address_func (reg * 2 + pc + 4, info);
05413229 8565 value_in_comment = 0;
c19d1205
ZW		 8566 break;
8567
8568 case 'c':
c22aaad1 8569 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 8570 break;
8571
8572 default:
8573 abort ();
8574 }
8575 }
8576 break;
8577
8578 case '\'':
8579 c++;
8580 if ((given & (1 << bitstart)) != 0)
8581 func (stream, "%c", *c);
8582 break;
8583
8584 case '?':
8585 ++c;
8586 if ((given & (1 << bitstart)) != 0)
8587 func (stream, "%c", *c++);
8588 else
8589 func (stream, "%c", *++c);
8590 break;
8591
8592 default:
8593 abort ();
8594 }
8595 }
8596 break;
8597
8598 default:
8599 abort ();
8600 }
8601 }
05413229
NC		 8602
8603 if (value_in_comment > 32 || value_in_comment < -16)
8604 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 8605 return;
c19d1205
ZW		 8606 }
8607
8608 /* No match. */
0b347048
TC		 8609 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
8610 return;
c19d1205
ZW		 8611}
8612
62b3e311 8613/* Return the name of an V7M special register. */
fe56b6ce 8614
62b3e311
PB		 8615static const char *
8616psr_name (int regno)
8617{
8618 switch (regno)
8619 {
1a336194
TP		 8620 case 0x0: return "APSR";
8621 case 0x1: return "IAPSR";
8622 case 0x2: return "EAPSR";
8623 case 0x3: return "PSR";
8624 case 0x5: return "IPSR";
8625 case 0x6: return "EPSR";
8626 case 0x7: return "IEPSR";
8627 case 0x8: return "MSP";
8628 case 0x9: return "PSP";
8629 case 0xa: return "MSPLIM";
8630 case 0xb: return "PSPLIM";
8631 case 0x10: return "PRIMASK";
8632 case 0x11: return "BASEPRI";
8633 case 0x12: return "BASEPRI_MAX";
8634 case 0x13: return "FAULTMASK";
8635 case 0x14: return "CONTROL";
16a1fa25
TP		 8636 case 0x88: return "MSP_NS";
8637 case 0x89: return "PSP_NS";
1a336194
TP		 8638 case 0x8a: return "MSPLIM_NS";
8639 case 0x8b: return "PSPLIM_NS";
8640 case 0x90: return "PRIMASK_NS";
8641 case 0x91: return "BASEPRI_NS";
8642 case 0x93: return "FAULTMASK_NS";
8643 case 0x94: return "CONTROL_NS";
8644 case 0x98: return "SP_NS";
62b3e311
PB		 8645 default: return "<unknown>";
8646 }
8647}
8648
4a5329c6
ZW		 8649/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
8650
8651static void
8652print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 8653{
6b5d3a4d 8654 const struct opcode32 *insn;
c19d1205
ZW		 8655 void *stream = info->stream;
8656 fprintf_ftype func = info->fprintf_func;
73cd51e5 8657 bfd_boolean is_mve = is_mve_architecture (info);
c19d1205 8658
16980d0b
JB		 8659 if (print_insn_coprocessor (pc, info, given, TRUE))
8660 return;
8661
73cd51e5
AV		 8662 if ((is_mve == FALSE) && print_insn_neon (info, given, TRUE))
8663 return;
8664
8665 if (is_mve && print_insn_mve (info, given))
8f06b2d8
PB		 8666 return;
8667
c19d1205
ZW		 8668 for (insn = thumb32_opcodes; insn->assembler; insn++)
8669 if ((given & insn->mask) == insn->value)
8670 {
4b5a202f 8671 bfd_boolean is_clrm = FALSE;
ff4a8d2b 8672 bfd_boolean is_unpredictable = FALSE;
05413229 8673 signed long value_in_comment = 0;
6b5d3a4d 8674 const char *c = insn->assembler;
05413229 8675
c19d1205
ZW		 8676 for (; *c; c++)
8677 {
8678 if (*c != '%')
8679 {
8680 func (stream, "%c", *c);
8681 continue;
8682 }
8683
8684 switch (*++c)
8685 {
8686 case '%':
8687 func (stream, "%%");
8688 break;
8689
c22aaad1
PB		 8690 case 'c':
8691 if (ifthen_state)
8692 func (stream, "%s", arm_conditional[IFTHEN_COND]);
8693 break;
8694
8695 case 'x':
8696 if (ifthen_next_state)
8697 func (stream, "\t; unpredictable branch in IT block\n");
8698 break;
8699
8700 case 'X':
8701 if (ifthen_state)
8702 func (stream, "\t; unpredictable <IT:%s>",
8703 arm_conditional[IFTHEN_COND]);
8704 break;
8705
c19d1205
ZW		 8706 case 'I':
8707 {
8708 unsigned int imm12 = 0;
fe56b6ce 8709
c19d1205
ZW		 8710 imm12 |= (given & 0x000000ffu);
8711 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 8712 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 8713 func (stream, "#%u", imm12);
8714 value_in_comment = imm12;
c19d1205
ZW		 8715 }
8716 break;
8717
8718 case 'M':
8719 {
8720 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 8721
c19d1205
ZW		 8722 bits |= (given & 0x000000ffu);
8723 bits |= (given & 0x00007000u) >> 4;
8724 bits |= (given & 0x04000000u) >> 15;
8725 imm8 = (bits & 0x0ff);
8726 mod = (bits & 0xf00) >> 8;
8727 switch (mod)
8728 {
8729 case 0: imm = imm8; break;
c1e26897
NC		 8730 case 1: imm = ((imm8 << 16) | imm8); break;
8731 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
8732 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 8733 default:
8734 mod = (bits & 0xf80) >> 7;
8735 imm8 = (bits & 0x07f) | 0x80;
8736 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
8737 }
fe56b6ce
NC		 8738 func (stream, "#%u", imm);
8739 value_in_comment = imm;
c19d1205
ZW		 8740 }
8741 break;
43e65147 8742
c19d1205
ZW		 8743 case 'J':
8744 {
8745 unsigned int imm = 0;
fe56b6ce 8746
c19d1205
ZW		 8747 imm |= (given & 0x000000ffu);
8748 imm |= (given & 0x00007000u) >> 4;
8749 imm |= (given & 0x04000000u) >> 15;
8750 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 8751 func (stream, "#%u", imm);
8752 value_in_comment = imm;
c19d1205
ZW		 8753 }
8754 break;
8755
8756 case 'K':
8757 {
8758 unsigned int imm = 0;
fe56b6ce 8759
c19d1205
ZW		 8760 imm |= (given & 0x000f0000u) >> 16;
8761 imm |= (given & 0x00000ff0u) >> 0;
8762 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 8763 func (stream, "#%u", imm);
8764 value_in_comment = imm;
c19d1205
ZW		 8765 }
8766 break;
8767
74db7efb
NC		 8768 case 'H':
8769 {
8770 unsigned int imm = 0;
8771
8772 imm |= (given & 0x000f0000u) >> 4;
8773 imm |= (given & 0x00000fffu) >> 0;
8774 func (stream, "#%u", imm);
8775 value_in_comment = imm;
8776 }
8777 break;
8778
90ec0d68
MGD		 8779 case 'V':
8780 {
8781 unsigned int imm = 0;
8782
8783 imm |= (given & 0x00000fffu);
8784 imm |= (given & 0x000f0000u) >> 4;
8785 func (stream, "#%u", imm);
8786 value_in_comment = imm;
8787 }
8788 break;
8789
c19d1205
ZW		 8790 case 'S':
8791 {
8792 unsigned int reg = (given & 0x0000000fu);
8793 unsigned int stp = (given & 0x00000030u) >> 4;
8794 unsigned int imm = 0;
8795 imm |= (given & 0x000000c0u) >> 6;
8796 imm |= (given & 0x00007000u) >> 10;
8797
8798 func (stream, "%s", arm_regnames[reg]);
8799 switch (stp)
8800 {
8801 case 0:
8802 if (imm > 0)
8803 func (stream, ", lsl #%u", imm);
8804 break;
8805
8806 case 1:
8807 if (imm == 0)
8808 imm = 32;
8809 func (stream, ", lsr #%u", imm);
8810 break;
8811
8812 case 2:
8813 if (imm == 0)
8814 imm = 32;
8815 func (stream, ", asr #%u", imm);
8816 break;
8817
8818 case 3:
8819 if (imm == 0)
8820 func (stream, ", rrx");
8821 else
8822 func (stream, ", ror #%u", imm);
8823 }
8824 }
8825 break;
8826
8827 case 'a':
8828 {
8829 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 8830 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 8831 unsigned int op = (given & 0x00000f00) >> 8;
8832 unsigned int i12 = (given & 0x00000fff);
8833 unsigned int i8 = (given & 0x000000ff);
8834 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 8835 bfd_vma offset = 0;
c19d1205
ZW		 8836
8837 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 8838 if (U) /* 12-bit positive immediate offset. */
8839 {
8840 offset = i12;
8841 if (Rn != 15)
8842 value_in_comment = offset;
8843 }
8844 else if (Rn == 15) /* 12-bit negative immediate offset. */
8845 offset = - (int) i12;
8846 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 8847 {
8848 unsigned int Rm = (i8 & 0x0f);
8849 unsigned int sh = (i8 & 0x30) >> 4;
05413229 8850
c19d1205
ZW		 8851 func (stream, ", %s", arm_regnames[Rm]);
8852 if (sh)
8853 func (stream, ", lsl #%u", sh);
8854 func (stream, "]");
8855 break;
8856 }
8857 else switch (op)
8858 {
05413229 8859 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 8860 offset = i8;
8861 break;
8862
05413229 8863 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 8864 offset = -i8;
8865 break;
8866
05413229 8867 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 8868 offset = i8;
8869 writeback = TRUE;
8870 break;
8871
05413229 8872 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 8873 offset = -i8;
8874 writeback = TRUE;
8875 break;
8876
05413229 8877 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 8878 offset = i8;
8879 postind = TRUE;
8880 break;
8881
05413229 8882 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 8883 offset = -i8;
8884 postind = TRUE;
8885 break;
8886
8887 default:
8888 func (stream, ", <undefined>]");
8889 goto skip;
8890 }
8891
8892 if (postind)
d908c8af 8893 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 8894 else
8895 {
8896 if (offset)
d908c8af 8897 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 8898 func (stream, writeback ? "]!" : "]");
8899 }
8900
8901 if (Rn == 15)
8902 {
8903 func (stream, "\t; ");
8904 info->print_address_func (((pc + 4) & ~3) + offset, info);
8905 }
8906 }
8907 skip:
8908 break;
8909
8910 case 'A':
8911 {
c1e26897
NC		 8912 unsigned int U = ! NEGATIVE_BIT_SET;
8913 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 8914 unsigned int Rn = (given & 0x000f0000) >> 16;
8915 unsigned int off = (given & 0x000000ff);
8916
8917 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 8918
8919 if (PRE_BIT_SET)
c19d1205
ZW		 8920 {
8921 if (off || !U)
05413229
NC		 8922 {
8923 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
fe50e98c 8924 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 8925 }
c19d1205
ZW		 8926 func (stream, "]");
8927 if (W)
8928 func (stream, "!");
8929 }
8930 else
8931 {
8932 func (stream, "], ");
8933 if (W)
05413229
NC		 8934 {
8935 func (stream, "#%c%u", U ? '+' : '-', off * 4);
fe50e98c 8936 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 8937 }
c19d1205 8938 else
fe56b6ce
NC		 8939 {
8940 func (stream, "{%u}", off);
8941 value_in_comment = off;
8942 }
c19d1205
ZW		 8943 }
8944 }
8945 break;
8946
8947 case 'w':
8948 {
8949 unsigned int Sbit = (given & 0x01000000) >> 24;
8950 unsigned int type = (given & 0x00600000) >> 21;
05413229 8951
c19d1205
ZW		 8952 switch (type)
8953 {
8954 case 0: func (stream, Sbit ? "sb" : "b"); break;
8955 case 1: func (stream, Sbit ? "sh" : "h"); break;
8956 case 2:
8957 if (Sbit)
8958 func (stream, "??");
8959 break;
8960 case 3:
8961 func (stream, "??");
8962 break;
8963 }
8964 }
8965 break;
8966
4b5a202f
AV		 8967 case 'n':
8968 is_clrm = TRUE;
8969 /* Fall through. */
c19d1205
ZW		 8970 case 'm':
8971 {
8972 int started = 0;
8973 int reg;
8974
8975 func (stream, "{");
8976 for (reg = 0; reg < 16; reg++)
8977 if ((given & (1 << reg)) != 0)
8978 {
8979 if (started)
8980 func (stream, ", ");
8981 started = 1;
4b5a202f
AV		 8982 if (is_clrm && reg == 13)
8983 func (stream, "(invalid: %s)", arm_regnames[reg]);
8984 else if (is_clrm && reg == 15)
8985 func (stream, "%s", "APSR");
8986 else
8987 func (stream, "%s", arm_regnames[reg]);
c19d1205
ZW		 8988 }
8989 func (stream, "}");
8990 }
8991 break;
8992
8993 case 'E':
8994 {
8995 unsigned int msb = (given & 0x0000001f);
8996 unsigned int lsb = 0;
fe56b6ce 8997
c19d1205
ZW		 8998 lsb |= (given & 0x000000c0u) >> 6;
8999 lsb |= (given & 0x00007000u) >> 10;
9000 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
9001 }
9002 break;
9003
9004 case 'F':
9005 {
9006 unsigned int width = (given & 0x0000001f) + 1;
9007 unsigned int lsb = 0;
fe56b6ce 9008
c19d1205
ZW		 9009 lsb |= (given & 0x000000c0u) >> 6;
9010 lsb |= (given & 0x00007000u) >> 10;
9011 func (stream, "#%u, #%u", lsb, width);
9012 }
9013 break;
9014
e12437dc
AV		 9015 case 'G':
9016 {
9017 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
9018 func (stream, "%x", boff);
9019 }
9020 break;
9021
e5d6e09e
AV		 9022 case 'W':
9023 {
9024 unsigned int immA = (given & 0x001f0000u) >> 16;
9025 unsigned int immB = (given & 0x000007feu) >> 1;
9026 unsigned int immC = (given & 0x00000800u) >> 11;
9027 bfd_vma offset = 0;
9028
9029 offset |= immA << 12;
9030 offset |= immB << 2;
9031 offset |= immC << 1;
9032 /* Sign extend. */
9033 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
9034
9035 info->print_address_func (pc + 4 + offset, info);
9036 }
9037 break;
9038
1caf72a5
AV		 9039 case 'Y':
9040 {
9041 unsigned int immA = (given & 0x007f0000u) >> 16;
9042 unsigned int immB = (given & 0x000007feu) >> 1;
9043 unsigned int immC = (given & 0x00000800u) >> 11;
9044 bfd_vma offset = 0;
9045
9046 offset |= immA << 12;
9047 offset |= immB << 2;
9048 offset |= immC << 1;
9049 /* Sign extend. */
9050 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
9051
9052 info->print_address_func (pc + 4 + offset, info);
9053 }
9054 break;
9055
1889da70
AV		 9056 case 'Z':
9057 {
9058 unsigned int immA = (given & 0x00010000u) >> 16;
9059 unsigned int immB = (given & 0x000007feu) >> 1;
9060 unsigned int immC = (given & 0x00000800u) >> 11;
9061 bfd_vma offset = 0;
9062
9063 offset |= immA << 12;
9064 offset |= immB << 2;
9065 offset |= immC << 1;
9066 /* Sign extend. */
9067 offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
9068
9069 info->print_address_func (pc + 4 + offset, info);
f6b2b12d
AV		 9070
9071 unsigned int T = (given & 0x00020000u) >> 17;
9072 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
9073 unsigned int boffset = (T == 1) ? 4 : 2;
9074 func (stream, ", ");
9075 func (stream, "%x", endoffset + boffset);
1889da70
AV		 9076 }
9077 break;
9078
60f993ce
AV		 9079 case 'Q':
9080 {
9081 unsigned int immh = (given & 0x000007feu) >> 1;
9082 unsigned int imml = (given & 0x00000800u) >> 11;
9083 bfd_vma imm32 = 0;
9084
9085 imm32 |= immh << 2;
9086 imm32 |= imml << 1;
9087
9088 info->print_address_func (pc + 4 + imm32, info);
9089 }
9090 break;
9091
9092 case 'P':
9093 {
9094 unsigned int immh = (given & 0x000007feu) >> 1;
9095 unsigned int imml = (given & 0x00000800u) >> 11;
9096 bfd_vma imm32 = 0;
9097
9098 imm32 |= immh << 2;
9099 imm32 |= imml << 1;
9100
9101 info->print_address_func (pc + 4 - imm32, info);
9102 }
9103 break;
9104
c19d1205
ZW		 9105 case 'b':
9106 {
9107 unsigned int S = (given & 0x04000000u) >> 26;
9108 unsigned int J1 = (given & 0x00002000u) >> 13;
9109 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 9110 bfd_vma offset = 0;
c19d1205
ZW		 9111
9112 offset |= !S << 20;
9113 offset |= J2 << 19;
9114 offset |= J1 << 18;
9115 offset |= (given & 0x003f0000) >> 4;
9116 offset |= (given & 0x000007ff) << 1;
9117 offset -= (1 << 20);
9118
9119 info->print_address_func (pc + 4 + offset, info);
9120 }
9121 break;
9122
9123 case 'B':
9124 {
9125 unsigned int S = (given & 0x04000000u) >> 26;
9126 unsigned int I1 = (given & 0x00002000u) >> 13;
9127 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 9128 bfd_vma offset = 0;
c19d1205
ZW		 9129
9130 offset |= !S << 24;
9131 offset |= !(I1 ^ S) << 23;
9132 offset |= !(I2 ^ S) << 22;
9133 offset |= (given & 0x03ff0000u) >> 4;
9134 offset |= (given & 0x000007ffu) << 1;
9135 offset -= (1 << 24);
36b0c57d 9136 offset += pc + 4;
c19d1205 9137
36b0c57d
PB		 9138 /* BLX target addresses are always word aligned. */
9139 if ((given & 0x00001000u) == 0)
9140 offset &= ~2u;
9141
9142 info->print_address_func (offset, info);
c19d1205
ZW		 9143 }
9144 break;
9145
9146 case 's':
9147 {
9148 unsigned int shift = 0;
fe56b6ce 9149
c19d1205
ZW		 9150 shift |= (given & 0x000000c0u) >> 6;
9151 shift |= (given & 0x00007000u) >> 10;
c1e26897 9152 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 9153 func (stream, ", asr #%u", shift);
9154 else if (shift)
9155 func (stream, ", lsl #%u", shift);
9156 /* else print nothing - lsl #0 */
9157 }
9158 break;
9159
9160 case 'R':
9161 {
9162 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 9163
c19d1205
ZW		 9164 if (rot)
9165 func (stream, ", ror #%u", rot * 8);
9166 }
9167 break;
9168
62b3e311 9169 case 'U':
43e65147 9170 if ((given & 0xf0) == 0x60)
62b3e311 9171 {
52e7f43d
RE		 9172 switch (given & 0xf)
9173 {
9174 case 0xf: func (stream, "sy"); break;
9175 default:
9176 func (stream, "#%d", (int) given & 0xf);
9177 break;
9178 }
62b3e311 9179 }
43e65147 9180 else
52e7f43d 9181 {
e797f7e0
MGD		 9182 const char * opt = data_barrier_option (given & 0xf);
9183 if (opt != NULL)
9184 func (stream, "%s", opt);
9185 else
9186 func (stream, "#%d", (int) given & 0xf);
52e7f43d 9187 }
62b3e311
PB		 9188 break;
9189
9190 case 'C':
9191 if ((given & 0xff) == 0)
9192 {
9193 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
9194 if (given & 0x800)
9195 func (stream, "f");
9196 if (given & 0x400)
9197 func (stream, "s");
9198 if (given & 0x200)
9199 func (stream, "x");
9200 if (given & 0x100)
9201 func (stream, "c");
9202 }
90ec0d68
MGD		 9203 else if ((given & 0x20) == 0x20)
9204 {
9205 char const* name;
9206 unsigned sysm = (given & 0xf00) >> 8;
9207
9208 sysm |= (given & 0x30);
9209 sysm |= (given & 0x00100000) >> 14;
9210 name = banked_regname (sysm);
43e65147 9211
90ec0d68
MGD		 9212 if (name != NULL)
9213 func (stream, "%s", name);
9214 else
d908c8af 9215 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 9216 }
62b3e311
PB		 9217 else
9218 {
d908c8af 9219 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 9220 }
9221 break;
9222
9223 case 'D':
90ec0d68
MGD		 9224 if (((given & 0xff) == 0)
9225 || ((given & 0x20) == 0x20))
9226 {
9227 char const* name;
9228 unsigned sm = (given & 0xf0000) >> 16;
9229
9230 sm |= (given & 0x30);
9231 sm |= (given & 0x00100000) >> 14;
9232 name = banked_regname (sm);
9233
9234 if (name != NULL)
9235 func (stream, "%s", name);
9236 else
d908c8af 9237 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 9238 }
62b3e311 9239 else
d908c8af 9240 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 9241 break;
9242
c19d1205
ZW		 9243 case '0': case '1': case '2': case '3': case '4':
9244 case '5': case '6': case '7': case '8': case '9':
9245 {
16980d0b
JB		 9246 int width;
9247 unsigned long val;
c19d1205 9248
16980d0b 9249 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 9250
c19d1205
ZW		 9251 switch (*c)
9252 {
05413229
NC		 9253 case 'd':
9254 func (stream, "%lu", val);
9255 value_in_comment = val;
9256 break;
ff4a8d2b 9257
f0fba320
RL		 9258 case 'D':
9259 func (stream, "%lu", val + 1);
9260 value_in_comment = val + 1;
9261 break;
9262
05413229
NC		 9263 case 'W':
9264 func (stream, "%lu", val * 4);
9265 value_in_comment = val * 4;
9266 break;
ff4a8d2b 9267
f1c7f421
AV		 9268 case 'S':
9269 if (val == 13)
9270 is_unpredictable = TRUE;
9271 /* Fall through. */
ff4a8d2b
NC		 9272 case 'R':
9273 if (val == 15)
9274 is_unpredictable = TRUE;
9275 /* Fall through. */
9276 case 'r':
9277 func (stream, "%s", arm_regnames[val]);
9278 break;
c19d1205
ZW		 9279
9280 case 'c':
c22aaad1 9281 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 9282 break;
9283
9284 case '\'':
c19d1205 9285 c++;
16980d0b
JB		 9286 if (val == ((1ul << width) - 1))
9287 func (stream, "%c", *c);
c19d1205 9288 break;
43e65147 9289
c19d1205 9290 case '`':
c19d1205 9291 c++;
16980d0b
JB		 9292 if (val == 0)
9293 func (stream, "%c", *c);
c19d1205
ZW		 9294 break;
9295
9296 case '?':
fe56b6ce 9297 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 9298 c += 1 << width;
c19d1205 9299 break;
43e65147 9300
0bb027fd
RR		 9301 case 'x':
9302 func (stream, "0x%lx", val & 0xffffffffUL);
9303 break;
c19d1205
ZW		 9304
9305 default:
9306 abort ();
9307 }
9308 }
9309 break;
9310
32a94698
NC		 9311 case 'L':
9312 /* PR binutils/12534
9313 If we have a PC relative offset in an LDRD or STRD
9314 instructions then display the decoded address. */
9315 if (((given >> 16) & 0xf) == 0xf)
9316 {
9317 bfd_vma offset = (given & 0xff) * 4;
9318
9319 if ((given & (1 << 23)) == 0)
9320 offset = - offset;
9321 func (stream, "\t; ");
9322 info->print_address_func ((pc & ~3) + 4 + offset, info);
9323 }
9324 break;
9325
c19d1205
ZW		 9326 default:
9327 abort ();
9328 }
9329 }
05413229
NC		 9330
9331 if (value_in_comment > 32 || value_in_comment < -16)
9332 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 9333
9334 if (is_unpredictable)
9335 func (stream, UNPREDICTABLE_INSTRUCTION);
9336
4a5329c6 9337 return;
c19d1205 9338 }
252b5132 9339
58efb6c0 9340 /* No match. */
0b347048
TC		 9341 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
9342 return;
252b5132
RH		 9343}
9344
e821645d
DJ		 9345/* Print data bytes on INFO->STREAM. */
9346
9347static void
fe56b6ce
NC		 9348print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
9349 struct disassemble_info *info,
e821645d
DJ		 9350 long given)
9351{
9352 switch (info->bytes_per_chunk)
9353 {
9354 case 1:
9355 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
9356 break;
9357 case 2:
9358 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
9359 break;
9360 case 4:
9361 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
9362 break;
9363 default:
9364 abort ();
9365 }
9366}
9367
22a398e1 9368/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 9369 being displayed in symbol relative addresses.
9370
9371 Also disallow private symbol, with __tagsym$$ prefix,
9372 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 9373
9374bfd_boolean
9375arm_symbol_is_valid (asymbol * sym,
9376 struct disassemble_info * info ATTRIBUTE_UNUSED)
9377{
9378 const char * name;
43e65147 9379
22a398e1
NC		 9380 if (sym == NULL)
9381 return FALSE;
9382
9383 name = bfd_asymbol_name (sym);
9384
d8282f0e 9385 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 9386}
9387
65b48a81 9388/* Parse the string of disassembler options. */
baf0cc5e 9389
65b48a81 9390static void
f995bbe8 9391parse_arm_disassembler_options (const char *options)
dd92f639 9392{
f995bbe8 9393 const char *opt;
b34976b6 9394
65b48a81 9395 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
dd92f639 9396 {
65b48a81
PB		 9397 if (CONST_STRNEQ (opt, "reg-names-"))
9398 {
9399 unsigned int i;
9400 for (i = 0; i < NUM_ARM_OPTIONS; i++)
9401 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
9402 {
9403 regname_selected = i;
9404 break;
9405 }
b34976b6 9406
65b48a81 9407 if (i >= NUM_ARM_OPTIONS)
a6743a54
AM		 9408 /* xgettext: c-format */
9409 opcodes_error_handler (_("unrecognised register name set: %s"),
9410 opt);
65b48a81
PB		 9411 }
9412 else if (CONST_STRNEQ (opt, "force-thumb"))
9413 force_thumb = 1;
9414 else if (CONST_STRNEQ (opt, "no-force-thumb"))
9415 force_thumb = 0;
9416 else
a6743a54
AM		 9417 /* xgettext: c-format */
9418 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
dd92f639 9419 }
b34976b6 9420
dd92f639
NC		 9421 return;
9422}
9423
5bc5ae88
RL		 9424static bfd_boolean
9425mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
9426 enum map_type *map_symbol);
9427
c22aaad1
PB		 9428/* Search back through the insn stream to determine if this instruction is
9429 conditionally executed. */
fe56b6ce 9430
c22aaad1 9431static void
fe56b6ce
NC		 9432find_ifthen_state (bfd_vma pc,
9433 struct disassemble_info *info,
c22aaad1
PB		 9434 bfd_boolean little)
9435{
9436 unsigned char b[2];
9437 unsigned int insn;
9438 int status;
9439 /* COUNT is twice the number of instructions seen. It will be odd if we
9440 just crossed an instruction boundary. */
9441 int count;
9442 int it_count;
9443 unsigned int seen_it;
9444 bfd_vma addr;
9445
9446 ifthen_address = pc;
9447 ifthen_state = 0;
9448
9449 addr = pc;
9450 count = 1;
9451 it_count = 0;
9452 seen_it = 0;
9453 /* Scan backwards looking for IT instructions, keeping track of where
9454 instruction boundaries are. We don't know if something is actually an
9455 IT instruction until we find a definite instruction boundary. */
9456 for (;;)
9457 {
fe56b6ce 9458 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 9459 {
9460 /* A symbol must be on an instruction boundary, and will not
9461 be within an IT block. */
9462 if (seen_it && (count & 1))
9463 break;
9464
9465 return;
9466 }
9467 addr -= 2;
fe56b6ce 9468 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 9469 if (status)
9470 return;
9471
9472 if (little)
9473 insn = (b[0]) | (b[1] << 8);
9474 else
9475 insn = (b[1]) | (b[0] << 8);
9476 if (seen_it)
9477 {
9478 if ((insn & 0xf800) < 0xe800)
9479 {
9480 /* Addr + 2 is an instruction boundary. See if this matches
9481 the expected boundary based on the position of the last
9482 IT candidate. */
9483 if (count & 1)
9484 break;
9485 seen_it = 0;
9486 }
9487 }
9488 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
9489 {
5bc5ae88
RL		 9490 enum map_type type = MAP_ARM;
9491 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
9492
9493 if (!found || (found && type == MAP_THUMB))
9494 {
9495 /* This could be an IT instruction. */
9496 seen_it = insn;
9497 it_count = count >> 1;
9498 }
c22aaad1
PB		 9499 }
9500 if ((insn & 0xf800) >= 0xe800)
9501 count++;
9502 else
9503 count = (count + 2) | 1;
9504 /* IT blocks contain at most 4 instructions. */
9505 if (count >= 8 && !seen_it)
9506 return;
9507 }
9508 /* We found an IT instruction. */
9509 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
9510 if ((ifthen_state & 0xf) == 0)
9511 ifthen_state = 0;
9512}
9513
b0e28b39
DJ		 9514/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
9515 mapping symbol. */
9516
9517static int
9518is_mapping_symbol (struct disassemble_info *info, int n,
9519 enum map_type *map_type)
9520{
9521 const char *name;
9522
9523 name = bfd_asymbol_name (info->symtab[n]);
9524 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
9525 && (name[2] == 0 || name[2] == '.'))
9526 {
9527 *map_type = ((name[1] == 'a') ? MAP_ARM
9528 : (name[1] == 't') ? MAP_THUMB
9529 : MAP_DATA);
9530 return TRUE;
9531 }
9532
9533 return FALSE;
9534}
9535
9536/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
9537 Returns nonzero if *MAP_TYPE was set. */
9538
9539static int
9540get_map_sym_type (struct disassemble_info *info,
9541 int n,
9542 enum map_type *map_type)
9543{
9544 /* If the symbol is in a different section, ignore it. */
9545 if (info->section != NULL && info->section != info->symtab[n]->section)
9546 return FALSE;
9547
9548 return is_mapping_symbol (info, n, map_type);
9549}
9550
9551/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 9552 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 9553
9554static int
fe56b6ce
NC		 9555get_sym_code_type (struct disassemble_info *info,
9556 int n,
e821645d 9557 enum map_type *map_type)
2087ad84
PB		 9558{
9559 elf_symbol_type *es;
9560 unsigned int type;
b0e28b39
DJ		 9561
9562 /* If the symbol is in a different section, ignore it. */
9563 if (info->section != NULL && info->section != info->symtab[n]->section)
9564 return FALSE;
2087ad84 9565
e821645d 9566 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 9567 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
9568
9569 /* If the symbol has function type then use that. */
34e77a92 9570 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 9571 {
39d911fc
TP		 9572 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
9573 == ST_BRANCH_TO_THUMB)
35fc36a8
RS		 9574 *map_type = MAP_THUMB;
9575 else
9576 *map_type = MAP_ARM;
2087ad84
PB		 9577 return TRUE;
9578 }
9579
2087ad84
PB		 9580 return FALSE;
9581}
9582
5bc5ae88
RL		 9583/* Search the mapping symbol state for instruction at pc. This is only
9584 applicable for elf target.
9585
9586 There is an assumption Here, info->private_data contains the correct AND
9587 up-to-date information about current scan process. The information will be
9588 used to speed this search process.
9589
9590 Return TRUE if the mapping state can be determined, and map_symbol
9591 will be updated accordingly. Otherwise, return FALSE. */
9592
9593static bfd_boolean
9594mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
9595 enum map_type *map_symbol)
9596{
796d6298
TC		 9597 bfd_vma addr, section_vma = 0;
9598 int n, last_sym = -1;
5bc5ae88 9599 bfd_boolean found = FALSE;
796d6298
TC		 9600 bfd_boolean can_use_search_opt_p = FALSE;
9601
9602 /* Default to DATA. A text section is required by the ABI to contain an
9603 INSN mapping symbol at the start. A data section has no such
9604 requirement, hence if no mapping symbol is found the section must
9605 contain only data. This however isn't very useful if the user has
9606 fully stripped the binaries. If this is the case use the section
9607 attributes to determine the default. If we have no section default to
9608 INSN as well, as we may be disassembling some raw bytes on a baremetal
9609 HEX file or similar. */
9610 enum map_type type = MAP_DATA;
9611 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
9612 type = MAP_ARM;
5bc5ae88
RL		 9613 struct arm_private_data *private_data;
9614
796d6298 9615 if (info->private_data == NULL
5bc5ae88
RL		 9616 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
9617 return FALSE;
9618
9619 private_data = info->private_data;
5bc5ae88 9620
796d6298
TC		 9621 /* First, look for mapping symbols. */
9622 if (info->symtab_size != 0)
9623 {
9624 if (pc <= private_data->last_mapping_addr)
9625 private_data->last_mapping_sym = -1;
9626
9627 /* Start scanning at the start of the function, or wherever
9628 we finished last time. */
9629 n = info->symtab_pos + 1;
9630
9631 /* If the last stop offset is different from the current one it means we
9632 are disassembling a different glob of bytes. As such the optimization
9633 would not be safe and we should start over. */
9634 can_use_search_opt_p
9635 = private_data->last_mapping_sym >= 0
9636 && info->stop_offset == private_data->last_stop_offset;
9637
9638 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
9639 n = private_data->last_mapping_sym;
9640
9641 /* Look down while we haven't passed the location being disassembled.
9642 The reason for this is that there's no defined order between a symbol
9643 and an mapping symbol that may be at the same address. We may have to
9644 look at least one position ahead. */
9645 for (; n < info->symtab_size; n++)
9646 {
9647 addr = bfd_asymbol_value (info->symtab[n]);
9648 if (addr > pc)
9649 break;
9650 if (get_map_sym_type (info, n, &type))
9651 {
9652 last_sym = n;
9653 found = TRUE;
9654 }
9655 }
5bc5ae88 9656
796d6298
TC		 9657 if (!found)
9658 {
9659 n = info->symtab_pos;
9660 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
9661 n = private_data->last_mapping_sym;
9662
9663 /* No mapping symbol found at this address. Look backwards
9664 for a preceeding one, but don't go pass the section start
9665 otherwise a data section with no mapping symbol can pick up
9666 a text mapping symbol of a preceeding section. The documentation
9667 says section can be NULL, in which case we will seek up all the
9668 way to the top. */
9669 if (info->section)
9670 section_vma = info->section->vma;
9671
9672 for (; n >= 0; n--)
9673 {
9674 addr = bfd_asymbol_value (info->symtab[n]);
9675 if (addr < section_vma)
9676 break;
9677
9678 if (get_map_sym_type (info, n, &type))
9679 {
9680 last_sym = n;
9681 found = TRUE;
9682 break;
9683 }
9684 }
9685 }
9686 }
9687
9688 /* If no mapping symbol was found, try looking up without a mapping
9689 symbol. This is done by walking up from the current PC to the nearest
9690 symbol. We don't actually have to loop here since symtab_pos will
9691 contain the nearest symbol already. */
9692 if (!found)
5bc5ae88 9693 {
796d6298
TC		 9694 n = info->symtab_pos;
9695 if (n >= 0 && get_sym_code_type (info, n, &type))
5bc5ae88 9696 {
796d6298
TC		 9697 last_sym = n;
9698 found = TRUE;
5bc5ae88
RL		 9699 }
9700 }
9701
796d6298
TC		 9702 private_data->last_mapping_sym = last_sym;
9703 private_data->last_type = type;
9704 private_data->last_stop_offset = info->stop_offset;
5bc5ae88
RL		 9705
9706 *map_symbol = type;
9707 return found;
9708}
9709
0313a2b8
NC		 9710/* Given a bfd_mach_arm_XXX value, this function fills in the fields
9711 of the supplied arm_feature_set structure with bitmasks indicating
c0c468d5 9712 the supported base architectures and coprocessor extensions.
0313a2b8
NC		 9713
9714 FIXME: This could more efficiently implemented as a constant array,
9715 although it would also be less robust. */
9716
9717static void
9718select_arm_features (unsigned long mach,
9719 arm_feature_set * features)
9720{
c0c468d5
TP		 9721 arm_feature_set arch_fset;
9722 const arm_feature_set fpu_any = FPU_ANY;
9723
1af1dd51
MW		 9724#undef ARM_SET_FEATURES
9725#define ARM_SET_FEATURES(FSET) \
9726 { \
9727 const arm_feature_set fset = FSET; \
c0c468d5 9728 arch_fset = fset; \
1af1dd51 9729 }
823d2571 9730
c0c468d5
TP		 9731 /* When several architecture versions share the same bfd_mach_arm_XXX value
9732 the most featureful is chosen. */
0313a2b8
NC		 9733 switch (mach)
9734 {
c0c468d5
TP		 9735 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
9736 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
9737 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
9738 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
9739 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
9740 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
9741 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
9742 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
9743 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
9744 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
1af1dd51 9745 case bfd_mach_arm_ep9312:
c0c468d5
TP		 9746 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
9747 ARM_CEXT_MAVERICK | FPU_MAVERICK));
1af1dd51 9748 break;
c0c468d5
TP		 9749 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
9750 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
9751 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
9752 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
9753 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
9754 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
9755 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
9756 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
9757 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
9758 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
9759 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
9760 case bfd_mach_arm_8:
9761 {
0632eeea
SD		 9762 /* Add bits for extensions that Armv8.5-A recognizes. */
9763 arm_feature_set armv8_5_ext_fset
9764 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
9765 ARM_SET_FEATURES (ARM_ARCH_V8_5A);
9766 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset);
c0c468d5
TP		 9767 break;
9768 }
9769 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
9770 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
9771 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
73cd51e5
AV		 9772 case bfd_mach_arm_8_1M_MAIN:
9773 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
9774 force_thumb = 1;
9775 break;
c0c468d5
TP		 9776 /* If the machine type is unknown allow all architecture types and all
9777 extensions. */
9778 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
0313a2b8
NC		 9779 default:
9780 abort ();
9781 }
1af1dd51 9782#undef ARM_SET_FEATURES
c0c468d5
TP		 9783
9784 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
9785 and thus on bfd_mach_arm_XXX value. Therefore for a given
9786 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
9787 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
0313a2b8
NC		 9788}
9789
9790
58efb6c0
NC		 9791/* NOTE: There are no checks in these routines that
9792 the relevant number of data bytes exist. */
baf0cc5e 9793
58efb6c0 9794static int
4a5329c6 9795print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 9796{
c19d1205
ZW		 9797 unsigned char b[4];
9798 long given;
9799 int status;
e821645d 9800 int is_thumb = FALSE;
b0e28b39 9801 int is_data = FALSE;
bd2e2557 9802 int little_code;
e821645d 9803 unsigned int size = 4;
4a5329c6 9804 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 9805 bfd_boolean found = FALSE;
b0e28b39 9806 struct arm_private_data *private_data;
58efb6c0 9807
dd92f639
NC		 9808 if (info->disassembler_options)
9809 {
65b48a81 9810 parse_arm_disassembler_options (info->disassembler_options);
b34976b6 9811
58efb6c0 9812 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 9813 info->disassembler_options = NULL;
9814 }
b34976b6 9815
0313a2b8
NC		 9816 /* PR 10288: Control which instructions will be disassembled. */
9817 if (info->private_data == NULL)
9818 {
b0e28b39 9819 static struct arm_private_data private;
0313a2b8
NC		 9820
9821 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
9822 /* If the user did not use the -m command line switch then default to
9823 disassembling all types of ARM instruction.
43e65147 9824
0313a2b8
NC		 9825 The info->mach value has to be ignored as this will be based on
9826 the default archictecture for the target and/or hints in the notes
9827 section, but it will never be greater than the current largest arm
9828 machine value (iWMMXt2), which is only equivalent to the V5TE
9829 architecture. ARM architectures have advanced beyond the machine
9830 value encoding, and these newer architectures would be ignored if
9831 the machine value was used.
9832
9833 Ie the -m switch is used to restrict which instructions will be
9834 disassembled. If it is necessary to use the -m switch to tell
9835 objdump that an ARM binary is being disassembled, eg because the
9836 input is a raw binary file, but it is also desired to disassemble
9837 all ARM instructions then use "-marm". This will select the
9838 "unknown" arm architecture which is compatible with any ARM
9839 instruction. */
9840 info->mach = bfd_mach_arm_unknown;
9841
9842 /* Compute the architecture bitmask from the machine number.
9843 Note: This assumes that the machine number will not change
9844 during disassembly.... */
b0e28b39 9845 select_arm_features (info->mach, & private.features);
0313a2b8 9846
1fbaefec
PB		 9847 private.last_mapping_sym = -1;
9848 private.last_mapping_addr = 0;
796d6298 9849 private.last_stop_offset = 0;
b0e28b39
DJ		 9850
9851 info->private_data = & private;
0313a2b8 9852 }
b0e28b39
DJ		 9853
9854 private_data = info->private_data;
9855
bd2e2557
SS		 9856 /* Decide if our code is going to be little-endian, despite what the
9857 function argument might say. */
9858 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
9859
b0e28b39
DJ		 9860 /* For ELF, consult the symbol table to determine what kind of code
9861 or data we have. */
8977d4b2 9862 if (info->symtab_size != 0
e821645d
DJ		 9863 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
9864 {
9865 bfd_vma addr;
796d6298 9866 int n;
e821645d 9867 int last_sym = -1;
b0e28b39 9868 enum map_type type = MAP_ARM;
e821645d 9869
796d6298
TC		 9870 found = mapping_symbol_for_insn (pc, info, &type);
9871 last_sym = private_data->last_mapping_sym;
e821645d 9872
1fbaefec
PB		 9873 is_thumb = (private_data->last_type == MAP_THUMB);
9874 is_data = (private_data->last_type == MAP_DATA);
b34976b6 9875
e821645d
DJ		 9876 /* Look a little bit ahead to see if we should print out
9877 two or four bytes of data. If there's a symbol,
9878 mapping or otherwise, after two bytes then don't
9879 print more. */
9880 if (is_data)
9881 {
9882 size = 4 - (pc & 3);
9883 for (n = last_sym + 1; n < info->symtab_size; n++)
9884 {
9885 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 9886 if (addr > pc
9887 && (info->section == NULL
9888 || info->section == info->symtab[n]->section))
e821645d
DJ		 9889 {
9890 if (addr - pc < size)
9891 size = addr - pc;
9892 break;
9893 }
9894 }
9895 /* If the next symbol is after three bytes, we need to
9896 print only part of the data, so that we can use either
9897 .byte or .short. */
9898 if (size == 3)
9899 size = (pc & 1) ? 1 : 2;
9900 }
9901 }
9902
9903 if (info->symbols != NULL)
252b5132 9904 {
5876e06d
NC		 9905 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
9906 {
2f0ca46a 9907 coff_symbol_type * cs;
b34976b6 9908
5876e06d
NC		 9909 cs = coffsymbol (*info->symbols);
9910 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
9911 || cs->native->u.syment.n_sclass == C_THUMBSTAT
9912 || cs->native->u.syment.n_sclass == C_THUMBLABEL
9913 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
9914 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
9915 }
e821645d
DJ		 9916 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
9917 && !found)
5876e06d 9918 {
2087ad84
PB		 9919 /* If no mapping symbol has been found then fall back to the type
9920 of the function symbol. */
e821645d
DJ		 9921 elf_symbol_type * es;
9922 unsigned int type;
2087ad84 9923
e821645d
DJ		 9924 es = *(elf_symbol_type **)(info->symbols);
9925 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 9926
39d911fc
TP		 9927 is_thumb =
9928 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
9929 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
5876e06d 9930 }
e49d43ff
TG		 9931 else if (bfd_asymbol_flavour (*info->symbols)
9932 == bfd_target_mach_o_flavour)
9933 {
9934 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
9935
9936 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
9937 }
5876e06d 9938 }
b34976b6 9939
e821645d
DJ		 9940 if (force_thumb)
9941 is_thumb = TRUE;
9942
b8f9ee44
CL		 9943 if (is_data)
9944 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
9945 else
9946 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
9947
c19d1205 9948 info->bytes_per_line = 4;
252b5132 9949
1316c8b3
NC		 9950 /* PR 10263: Disassemble data if requested to do so by the user. */
9951 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 9952 {
9953 int i;
9954
1316c8b3 9955 /* Size was already set above. */
e821645d
DJ		 9956 info->bytes_per_chunk = size;
9957 printer = print_insn_data;
9958
fe56b6ce 9959 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 9960 given = 0;
9961 if (little)
9962 for (i = size - 1; i >= 0; i--)
9963 given = b[i] | (given << 8);
9964 else
9965 for (i = 0; i < (int) size; i++)
9966 given = b[i] | (given << 8);
9967 }
9968 else if (!is_thumb)
252b5132 9969 {
c19d1205
ZW		 9970 /* In ARM mode endianness is a straightforward issue: the instruction
9971 is four bytes long and is either ordered 0123 or 3210. */
9972 printer = print_insn_arm;
9973 info->bytes_per_chunk = 4;
4a5329c6 9974 size = 4;
c19d1205 9975
0313a2b8 9976 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 9977 if (little_code)
c19d1205
ZW		 9978 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
9979 else
9980 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
252b5132 9981 }
58efb6c0 9982 else
252b5132 9983 {
c19d1205
ZW		 9984 /* In Thumb mode we have the additional wrinkle of two
9985 instruction lengths. Fortunately, the bits that determine
9986 the length of the current instruction are always to be found
9987 in the first two bytes. */
4a5329c6 9988 printer = print_insn_thumb16;
c19d1205 9989 info->bytes_per_chunk = 2;
4a5329c6
ZW		 9990 size = 2;
9991
fe56b6ce 9992 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 9993 if (little_code)
9a2ff3f5
AM		 9994 given = (b[0]) | (b[1] << 8);
9995 else
9996 given = (b[1]) | (b[0] << 8);
9997
c19d1205 9998 if (!status)
252b5132 9999 {
c19d1205
ZW		 10000 /* These bit patterns signal a four-byte Thumb
10001 instruction. */
10002 if ((given & 0xF800) == 0xF800
10003 || (given & 0xF800) == 0xF000
10004 || (given & 0xF800) == 0xE800)
252b5132 10005 {
0313a2b8 10006 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 10007 if (little_code)
c19d1205 10008 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 10009 else
c19d1205
ZW		 10010 given = (b[1]) | (b[0] << 8) | (given << 16);
10011
10012 printer = print_insn_thumb32;
4a5329c6 10013 size = 4;
252b5132 10014 }
252b5132 10015 }
c22aaad1
PB		 10016
10017 if (ifthen_address != pc)
0313a2b8 10018 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 10019
10020 if (ifthen_state)
10021 {
10022 if ((ifthen_state & 0xf) == 0x8)
10023 ifthen_next_state = 0;
10024 else
10025 ifthen_next_state = (ifthen_state & 0xe0)
10026 | ((ifthen_state & 0xf) << 1);
10027 }
252b5132 10028 }
b34976b6 10029
c19d1205
ZW		 10030 if (status)
10031 {
10032 info->memory_error_func (status, pc, info);
10033 return -1;
10034 }
6a56ec7e
NC		 10035 if (info->flags & INSN_HAS_RELOC)
10036 /* If the instruction has a reloc associated with it, then
10037 the offset field in the instruction will actually be the
10038 addend for the reloc. (We are using REL type relocs).
10039 In such cases, we can ignore the pc when computing
10040 addresses, since the addend is not currently pc-relative. */
10041 pc = 0;
b34976b6 10042
4a5329c6 10043 printer (pc, info, given);
c22aaad1
PB		 10044
10045 if (is_thumb)
10046 {
10047 ifthen_state = ifthen_next_state;
10048 ifthen_address += size;
10049 }
4a5329c6 10050 return size;
252b5132
RH		 10051}
10052
10053int
4a5329c6 10054print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 10055{
bd2e2557
SS		 10056 /* Detect BE8-ness and record it in the disassembler info. */
10057 if (info->flavour == bfd_target_elf_flavour
10058 && info->section != NULL
10059 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
10060 info->endian_code = BFD_ENDIAN_LITTLE;
10061
b34976b6 10062 return print_insn (pc, info, FALSE);
58efb6c0 10063}
01c7f630 10064
58efb6c0 10065int
4a5329c6 10066print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 10067{
b34976b6 10068 return print_insn (pc, info, TRUE);
58efb6c0 10069}
252b5132 10070
471b9d15 10071const disasm_options_and_args_t *
65b48a81
PB		 10072disassembler_options_arm (void)
10073{
471b9d15 10074 static disasm_options_and_args_t *opts_and_args;
65b48a81 10075
471b9d15 10076 if (opts_and_args == NULL)
65b48a81 10077 {
471b9d15 10078 disasm_options_t *opts;
65b48a81 10079 unsigned int i;
471b9d15
MR		 10080
10081 opts_and_args = XNEW (disasm_options_and_args_t);
10082 opts_and_args->args = NULL;
10083
10084 opts = &opts_and_args->options;
65b48a81
PB		 10085 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
10086 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
471b9d15 10087 opts->arg = NULL;
65b48a81
PB		 10088 for (i = 0; i < NUM_ARM_OPTIONS; i++)
10089 {
10090 opts->name[i] = regnames[i].name;
10091 if (regnames[i].description != NULL)
10092 opts->description[i] = _(regnames[i].description);
10093 else
10094 opts->description[i] = NULL;
10095 }
10096 /* The array we return must be NULL terminated. */
10097 opts->name[i] = NULL;
10098 opts->description[i] = NULL;
10099 }
10100
471b9d15 10101 return opts_and_args;
65b48a81
PB		 10102}
10103
58efb6c0 10104void
4a5329c6 10105print_arm_disassembler_options (FILE *stream)
58efb6c0 10106{
65b48a81 10107 unsigned int i, max_len = 0;
58efb6c0
NC		 10108 fprintf (stream, _("\n\
10109The following ARM specific disassembler options are supported for use with\n\
10110the -M switch:\n"));
b34976b6 10111
65b48a81
PB		 10112 for (i = 0; i < NUM_ARM_OPTIONS; i++)
10113 {
10114 unsigned int len = strlen (regnames[i].name);
10115 if (max_len < len)
10116 max_len = len;
10117 }
58efb6c0 10118
65b48a81
PB		 10119 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
10120 fprintf (stream, " %s%*c %s\n",
10121 regnames[i].name,
10122 (int)(max_len - strlen (regnames[i].name)), ' ',
10123 _(regnames[i].description));
252b5132 10124}
GDB Binutils - Deliverables
This page took 3.692125 seconds and 4 git commands to generate.