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[PATCH 48/57][Arm][OBJDUMP] Add support for MVE instructions: vddup, vdwdup, vidup...
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
CommitLineData
252b5132 1/* Instruction printing code for the ARM
82704155 2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
143275ea 24#include <assert.h>
2fbad815 25
6394c606 26#include "disassemble.h"
2fbad815 27#include "opcode/arm.h"
252b5132 28#include "opintl.h"
31e0f3cd 29#include "safe-ctype.h"
65b48a81 30#include "libiberty.h"
0dbde4cf 31#include "floatformat.h"
252b5132 32
baf0cc5e 33/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 34#include "coff/internal.h"
35#include "libcoff.h"
2d5d5a8f 36#include "bfd.h"
252b5132
RH		 37#include "elf-bfd.h"
38#include "elf/internal.h"
39#include "elf/arm.h"
e49d43ff 40#include "mach-o.h"
252b5132 41
6b5d3a4d 42/* FIXME: Belongs in global header. */
01c7f630 43#ifndef strneq
58efb6c0
NC		 44#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
45#endif
46
1fbaefec
PB		 47/* Cached mapping symbol state. */
48enum map_type
49{
50 MAP_ARM,
51 MAP_THUMB,
52 MAP_DATA
53};
54
b0e28b39
DJ		 55struct arm_private_data
56{
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features;
59
1fbaefec
PB		 60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type;
62
63 /* Tracking symbol table information */
64 int last_mapping_sym;
796d6298
TC		 65
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset;
1fbaefec 68 bfd_vma last_mapping_addr;
b0e28b39
DJ		 69};
70
73cd51e5
AV		 71enum mve_instructions
72{
143275ea
AV		 73 MVE_VPST,
74 MVE_VPT_FP_T1,
75 MVE_VPT_FP_T2,
76 MVE_VPT_VEC_T1,
77 MVE_VPT_VEC_T2,
78 MVE_VPT_VEC_T3,
79 MVE_VPT_VEC_T4,
80 MVE_VPT_VEC_T5,
81 MVE_VPT_VEC_T6,
82 MVE_VCMP_FP_T1,
83 MVE_VCMP_FP_T2,
84 MVE_VCMP_VEC_T1,
85 MVE_VCMP_VEC_T2,
86 MVE_VCMP_VEC_T3,
87 MVE_VCMP_VEC_T4,
88 MVE_VCMP_VEC_T5,
89 MVE_VCMP_VEC_T6,
9743db03
AV		 90 MVE_VDUP,
91 MVE_VEOR,
92 MVE_VFMAS_FP_SCALAR,
93 MVE_VFMA_FP_SCALAR,
94 MVE_VFMA_FP,
95 MVE_VFMS_FP,
96 MVE_VHADD_T1,
97 MVE_VHADD_T2,
98 MVE_VHSUB_T1,
99 MVE_VHSUB_T2,
100 MVE_VRHADD,
04d54ace
AV		 101 MVE_VLD2,
102 MVE_VLD4,
103 MVE_VST2,
104 MVE_VST4,
aef6d006
AV		 105 MVE_VLDRB_T1,
106 MVE_VLDRH_T2,
107 MVE_VLDRB_T5,
108 MVE_VLDRH_T6,
109 MVE_VLDRW_T7,
110 MVE_VSTRB_T1,
111 MVE_VSTRH_T2,
112 MVE_VSTRB_T5,
113 MVE_VSTRH_T6,
114 MVE_VSTRW_T7,
ef1576a1
AV		 115 MVE_VLDRB_GATHER_T1,
116 MVE_VLDRH_GATHER_T2,
117 MVE_VLDRW_GATHER_T3,
118 MVE_VLDRD_GATHER_T4,
119 MVE_VLDRW_GATHER_T5,
120 MVE_VLDRD_GATHER_T6,
121 MVE_VSTRB_SCATTER_T1,
122 MVE_VSTRH_SCATTER_T2,
123 MVE_VSTRW_SCATTER_T3,
124 MVE_VSTRD_SCATTER_T4,
125 MVE_VSTRW_SCATTER_T5,
126 MVE_VSTRD_SCATTER_T6,
bf0b396d
AV		 127 MVE_VCVT_FP_FIX_VEC,
128 MVE_VCVT_BETWEEN_FP_INT,
129 MVE_VCVT_FP_HALF_FP,
130 MVE_VCVT_FROM_FP_TO_INT,
131 MVE_VRINT_FP,
c507f10b
AV		 132 MVE_VMOV_HFP_TO_GP,
133 MVE_VMOV_GP_TO_VEC_LANE,
134 MVE_VMOV_IMM_TO_VEC,
135 MVE_VMOV_VEC_TO_VEC,
136 MVE_VMOV2_VEC_LANE_TO_GP,
137 MVE_VMOV2_GP_TO_VEC_LANE,
138 MVE_VMOV_VEC_LANE_TO_GP,
139 MVE_VMVN_IMM,
140 MVE_VMVN_REG,
141 MVE_VORR_IMM,
142 MVE_VORR_REG,
143 MVE_VORN,
144 MVE_VBIC_IMM,
145 MVE_VBIC_REG,
146 MVE_VMOVX,
14925797
AV		 147 MVE_VMOVL,
148 MVE_VMOVN,
149 MVE_VMULL_INT,
150 MVE_VMULL_POLY,
151 MVE_VQDMULL_T1,
152 MVE_VQDMULL_T2,
153 MVE_VQMOVN,
154 MVE_VQMOVUN,
d3b63143
AV		 155 MVE_VADDV,
156 MVE_VMLADAV_T1,
157 MVE_VMLADAV_T2,
158 MVE_VMLALDAV,
159 MVE_VMLAS,
160 MVE_VADDLV,
161 MVE_VMLSDAV_T1,
162 MVE_VMLSDAV_T2,
163 MVE_VMLSLDAV,
164 MVE_VRMLALDAVH,
165 MVE_VRMLSLDAVH,
166 MVE_VQDMLADH,
167 MVE_VQRDMLADH,
168 MVE_VQDMLAH,
169 MVE_VQRDMLAH,
170 MVE_VQDMLASH,
171 MVE_VQRDMLASH,
172 MVE_VQDMLSDH,
173 MVE_VQRDMLSDH,
174 MVE_VQDMULH_T1,
175 MVE_VQRDMULH_T2,
176 MVE_VQDMULH_T3,
177 MVE_VQRDMULH_T4,
1c8f2df8
AV		 178 MVE_VDDUP,
179 MVE_VDWDUP,
180 MVE_VIWDUP,
181 MVE_VIDUP,
73cd51e5
AV		 182 MVE_NONE
183};
184
185enum mve_unpredictable
186{
187 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
188 */
143275ea
AV		 189 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and
190 fcB = 1 (vpt). */
191 UNPRED_R13, /* Unpredictable because r13 (sp) or
192 r15 (sp) used. */
9743db03 193 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
04d54ace
AV		 194 UNPRED_Q_GT_4, /* Unpredictable because
195 vec reg start > 4 (vld4/st4). */
196 UNPRED_Q_GT_6, /* Unpredictable because
197 vec reg start > 6 (vld2/st2). */
198 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
199 and WB bit = 1. */
ef1576a1
AV		 200 UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are
201 equal. */
202 UNPRED_OS, /* Unpredictable because offset scaled == 1. */
bf0b396d
AV		 203 UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the
204 same. */
c507f10b
AV		 205 UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and
206 size = 1. */
207 UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and
208 size = 2. */
73cd51e5
AV		 209 UNPRED_NONE /* No unpredictable behavior. */
210};
211
212enum mve_undefined
213{
bf0b396d 214 UNDEF_SIZE_0, /* undefined because size == 0. */
c507f10b 215 UNDEF_SIZE_2, /* undefined because size == 2. */
aef6d006
AV		 216 UNDEF_SIZE_3, /* undefined because size == 3. */
217 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
ef1576a1
AV		 218 UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
219 UNDEF_SIZE_NOT_3, /* undefined because size != 3. */
220 UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and
221 size == 0. */
222 UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and
223 size == 1. */
224 UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
bf0b396d
AV		 225 UNDEF_VCVT_IMM6, /* imm6 < 32. */
226 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
c507f10b
AV		 227 UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and
228 op1 == (0 or 1). */
229 UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and
230 op2 == 0 and op1 == (0 or 1). */
231 UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode
232 in {0xx1, x0x1}. */
d3b63143 233 UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */
73cd51e5
AV		 234 UNDEF_NONE /* no undefined behavior. */
235};
236
6b5d3a4d
ZW		 237struct opcode32
238{
823d2571
TG		 239 arm_feature_set arch; /* Architecture defining this insn. */
240 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 241 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 242 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 243};
244
73cd51e5
AV		 245/* MVE opcodes. */
246
247struct mopcode32
248{
249 arm_feature_set arch; /* Architecture defining this insn. */
250 enum mve_instructions mve_op; /* Specific mve instruction for faster
251 decoding. */
252 unsigned long value; /* If arch is 0 then value is a sentinel. */
253 unsigned long mask; /* Recognise insn if (op & mask) == value. */
254 const char * assembler; /* How to disassemble this insn. */
255};
256
6b0dd094
AV		 257enum isa {
258 ANY,
259 T32,
260 ARM
261};
262
263
264/* Shared (between Arm and Thumb mode) opcode. */
265struct sopcode32
266{
267 enum isa isa; /* Execution mode instruction availability. */
268 arm_feature_set arch; /* Architecture defining this insn. */
269 unsigned long value; /* If arch is 0 then value is a sentinel. */
270 unsigned long mask; /* Recognise insn if (op & mask) == value. */
271 const char * assembler; /* How to disassemble this insn. */
272};
273
6b5d3a4d
ZW		 274struct opcode16
275{
823d2571 276 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 277 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 278 const char *assembler; /* How to disassemble this insn. */
279};
b7693d02 280
8f06b2d8 281/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 282
2fbad815 283 %% %
4a5329c6 284
c22aaad1 285 %c print condition code (always bits 28-31 in ARM mode)
37b37b2d 286 %q print shifter argument
e2efe87d
MGD		 287 %u print condition code (unconditional in ARM mode,
288 UNPREDICTABLE if not AL in Thumb)
4a5329c6 289 %A print address for ldc/stc/ldf/stf instruction
16980d0b 290 %B print vstm/vldm register list
efd6b359 291 %C print vscclrm register list
4a5329c6 292 %I print cirrus signed shift immediate: bits 0..3|4..6
32c36c3c
AV		 293 %J print register for VLDR instruction
294 %K print address for VLDR instruction
4a5329c6
ZW		 295 %F print the COUNT field of a LFM/SFM instruction.
296 %P print floating point precision in arithmetic insn
297 %Q print floating point precision in ldf/stf insn
298 %R print floating point rounding mode
299
33399f07 300 %<bitfield>c print as a condition code (for vsel)
4a5329c6 301 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 302 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
303 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 304 %<bitfield>d print the bitfield in decimal
16980d0b 305 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 306 %<bitfield>x print the bitfield in hex
307 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 308 %<bitfield>f print a floating point constant if >7 else a
309 floating point register
4a5329c6
ZW		 310 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
311 %<bitfield>g print as an iWMMXt 64-bit register
312 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 313 %<bitfield>D print as a NEON D register
314 %<bitfield>Q print as a NEON Q register
c28eeff2 315 %<bitfield>V print as a NEON D or Q register
6f1c2142 316 %<bitfield>E print a quarter-float immediate value
4a5329c6 317
16980d0b 318 %y<code> print a single precision VFP reg.
2fbad815 319 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 320 %z<code> print a double precision VFP reg
2fbad815 321 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 322
16980d0b
JB		 323 %<bitfield>'c print specified char iff bitfield is all ones
324 %<bitfield>`c print specified char iff bitfield is all zeroes
325 %<bitfield>?ab... select from array of values in big endian order
43e65147 326
2fbad815 327 %L print as an iWMMXt N/M width field.
4a5329c6 328 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 329 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 330 versions.
331 %i print 5-bit immediate in bits 8,3..0
332 (print "32" when 0)
fe56b6ce 333 %r print register offset address for wldt/wstr instruction. */
2fbad815 334
21d799b5 335enum opcode_sentinel_enum
05413229
NC		 336{
337 SENTINEL_IWMMXT_START = 1,
338 SENTINEL_IWMMXT_END,
339 SENTINEL_GENERIC_START
340} opcode_sentinels;
341
aefd8a40 342#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
0b347048
TC		 343#define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
344#define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
c1e26897 345#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 346
8f06b2d8 347/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 348
6b0dd094 349static const struct sopcode32 coprocessor_opcodes[] =
2fbad815 350{
2fbad815 351 /* XScale instructions. */
6b0dd094 352 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 353 0x0e200010, 0x0fff0ff0,
354 "mia%c\tacc0, %0-3r, %12-15r"},
6b0dd094 355 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 356 0x0e280010, 0x0fff0ff0,
357 "miaph%c\tacc0, %0-3r, %12-15r"},
6b0dd094 358 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 359 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
6b0dd094 360 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 361 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
6b0dd094 362 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 363 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 364
2fbad815 365 /* Intel Wireless MMX technology instructions. */
6b0dd094
AV		 366 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
367 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
823d2571 368 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
6b0dd094 369 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 370 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
6b0dd094 371 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 372 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
6b0dd094 373 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 374 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
6b0dd094 375 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 376 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
6b0dd094 377 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 378 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
6b0dd094 379 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 380 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
6b0dd094 381 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 382 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 383 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 384 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 385 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 386 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 387 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 388 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
6b0dd094 389 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 390 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
6b0dd094 391 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 392 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
6b0dd094 393 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 394 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
6b0dd094 395 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 396 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
6b0dd094 397 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 398 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 399 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 400 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 401 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 402 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 403 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 404 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 405 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 406 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 407 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 408 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
6b0dd094 409 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 410 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 411 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 412 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 413 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 414 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 415 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 416 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 417 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 418 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 419 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 420 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 421 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 422 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
6b0dd094 423 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 424 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
6b0dd094 425 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 426 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
6b0dd094 427 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 428 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 429 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 430 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 431 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 432 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 433 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 434 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 435 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 436 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
6b0dd094 437 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 438 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 439 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 440 0x0e800120, 0x0f800ff0,
441 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 442 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 443 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 444 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 445 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 446 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 447 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 448 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 449 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 450 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 451 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 452 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 453 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 454 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 455 0x0e8000a0, 0x0f800ff0,
456 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 457 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 458 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 459 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 460 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 461 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 462 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 463 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 464 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 465 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 466 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 467 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 468 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 469 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 470 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 471 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 472 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 473 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 474 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
6b0dd094 475 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 476 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 477 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 478 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 479 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 480 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 481 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 482 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 483 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 484 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 485 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 486 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 487 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 488 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 489 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 490 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 491 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 492 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 493 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 494 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
6b0dd094 495 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 496 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
6b0dd094 497 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 498 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
6b0dd094 499 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 500 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 501 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 502 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 503 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 504 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 505 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 506 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
6b0dd094 507 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 508 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
6b0dd094 509 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 510 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
6b0dd094 511 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 512 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 513 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 514 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 515 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 516 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 517 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 518 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 519 {ANY, ARM_FEATURE_CORE_LOW (0),
823d2571 520 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 521
fe56b6ce 522 /* Floating point coprocessor (FPA) instructions. */
6b0dd094 523 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 524 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 525 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 526 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 527 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 528 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 529 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 530 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 531 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 532 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 533 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 534 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 535 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 536 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 537 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 538 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 539 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 540 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 541 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 542 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 543 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 544 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 545 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 546 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 547 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 548 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 549 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 550 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 551 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 552 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 553 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 554 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 555 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 556 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 557 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 558 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
6b0dd094 559 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 560 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
6b0dd094 561 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 562 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 563 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 564 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
6b0dd094 565 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 566 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
6b0dd094 567 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 568 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
6b0dd094 569 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 570 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
6b0dd094 571 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 572 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 573 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 574 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 575 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 576 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 577 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 578 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 579 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 580 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
6b0dd094 581 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 582 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
6b0dd094 583 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 584 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
6b0dd094 585 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 586 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
6b0dd094 587 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 588 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
6b0dd094 589 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 590 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
6b0dd094 591 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 592 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
6b0dd094 593 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 594 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
6b0dd094 595 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 596 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
6b0dd094 597 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 598 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
6b0dd094 599 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 600 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
6b0dd094 601 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 602 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
6b0dd094 603 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 604 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
6b0dd094 605 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 606 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
6b0dd094 607 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 608 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 609
efd6b359
AV		 610 /* Armv8.1-M Mainline instructions. */
611 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
612 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
613 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
614 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
615
16a1fa25 616 /* ARMv8-M Mainline Security Extensions instructions. */
6b0dd094 617 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25 618 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
6b0dd094 619 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25
TP		 620 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
621
fe56b6ce 622 /* Register load/store. */
6b0dd094 623 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 624 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
6b0dd094 625 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 626 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
6b0dd094 627 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 628 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
6b0dd094 629 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 630 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
6b0dd094 631 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 632 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
6b0dd094 633 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 634 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
6b0dd094 635 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 636 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
6b0dd094 637 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 638 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
6b0dd094 639 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 640 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
6b0dd094 641 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 642 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
6b0dd094 643 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 644 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
6b0dd094 645 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 646 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
6b0dd094 647 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 648 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
6b0dd094 649 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 650 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
6b0dd094 651 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 652 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
6b0dd094 653 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 654 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
32c36c3c
AV		 655 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
656 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
657 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
658 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
823d2571 659
6b0dd094 660 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 661 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 662 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 663 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 664 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 665 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
6b0dd094 666 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 667 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 668
fe56b6ce 669 /* Data transfer between ARM and NEON registers. */
6b0dd094 670 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 671 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
6b0dd094 672 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 673 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
6b0dd094 674 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 675 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
6b0dd094 676 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 677 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
6b0dd094 678 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 679 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
6b0dd094 680 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 681 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
6b0dd094 682 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 683 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
6b0dd094 684 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 685 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 686 /* Half-precision conversion instructions. */
6b0dd094 687 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 688 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
6b0dd094 689 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 690 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
6b0dd094 691 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 692 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
6b0dd094 693 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 694 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 695
fe56b6ce 696 /* Floating point coprocessor (VFP) instructions. */
6b0dd094 697 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 698 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
6b0dd094 699 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 700 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
6b0dd094 701 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 702 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
6b0dd094 703 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 704 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
6b0dd094 705 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 706 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
6b0dd094 707 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 708 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
6b0dd094 709 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 710 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
6b0dd094 711 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 712 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
6b0dd094 713 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 714 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
6b0dd094 715 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 716 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
6b0dd094 717 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 718 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
6b0dd094 719 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 720 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
6b0dd094 721 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 722 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
6b0dd094 723 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 724 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
6b0dd094 725 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 726 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
6b0dd094 727 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 728 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
6b0dd094 729 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 730 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
6b0dd094 731 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 732 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
6b0dd094 733 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 734 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
6b0dd094 735 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 736 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
6b0dd094 737 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 738 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
6b0dd094 739 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 740 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
6b0dd094 741 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 742 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
6b0dd094 743 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 744 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
6b0dd094 745 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 746 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
6b0dd094 747 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 748 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
6b0dd094 749 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 750 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
6b0dd094 751 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 752 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
6b0dd094 753 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 754 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
6b0dd094 755 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 756 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
6b0dd094 757 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 758 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
6b0dd094 759 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 760 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
6b0dd094 761 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 762 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
6b0dd094 763 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 764 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
6b0dd094 765 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 766 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
6b0dd094 767 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 768 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
6b0dd094 769 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 770 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
6b0dd094 771 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 772 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
6b0dd094 773 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 774 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
6b0dd094 775 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 776 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 777 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 778 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
6b0dd094 779 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 780 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
6b0dd094 781 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 782 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
6b0dd094 783 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 784 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
6b0dd094 785 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 786 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
6b0dd094 787 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 788 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
6b0dd094 789 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6f1c2142 790 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
6b0dd094 791 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6f1c2142 792 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
6b0dd094 793 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 794 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
6b0dd094 795 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 796 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
6b0dd094 797 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 798 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
6b0dd094 799 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 800 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 801 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 802 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 803 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 804 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 805 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 806 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 807 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 808 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 809 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 810 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 811 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 812 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 813 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 814 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 815 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 816 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 817 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 818 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 819 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 820 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 821 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 822 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 823 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 824 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
6b0dd094 825 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 826 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
6b0dd094 827 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 828 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
6b0dd094 829 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 830 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
6b0dd094 831 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 832 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
6b0dd094 833 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 834 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 835
836 /* Cirrus coprocessor instructions. */
6b0dd094 837 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 838 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 839 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 840 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 841 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 842 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 843 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 844 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 845 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 846 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 847 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 848 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 849 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 850 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 851 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 852 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 853 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 854 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 855 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 856 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 857 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 858 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 859 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 860 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 861 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 862 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 863 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 864 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 865 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 866 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 867 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 868 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 869 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 870 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
6b0dd094 871 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 872 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
6b0dd094 873 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 874 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
6b0dd094 875 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 876 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
6b0dd094 877 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 878 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
6b0dd094 879 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 880 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
6b0dd094 881 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 882 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 883 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 884 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
6b0dd094 885 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 886 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 887 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 888 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
6b0dd094 889 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 890 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 891 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 892 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 893 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 894 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 895 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 896 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 897 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 898 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 899 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 900 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 901 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 902 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 903 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 904 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 905 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 906 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
6b0dd094 907 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 908 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
6b0dd094 909 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 910 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
6b0dd094 911 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 912 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
6b0dd094 913 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 914 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 915 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 916 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 917 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 918 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
6b0dd094 919 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 920 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
6b0dd094 921 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 922 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
6b0dd094 923 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 924 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
6b0dd094 925 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 926 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
6b0dd094 927 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 928 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
6b0dd094 929 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 930 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 931 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 932 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 933 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 934 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 935 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 936 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 937 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 938 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
6b0dd094 939 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 940 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
6b0dd094 941 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 942 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
6b0dd094 943 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 944 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
6b0dd094 945 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 946 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
6b0dd094 947 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 948 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
6b0dd094 949 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 950 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 951 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 952 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 953 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 954 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 955 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 956 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 957 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 958 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 959 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 960 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 961 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 962 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 963 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 964 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 965 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 966 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 967 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 968 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 969 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 970 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 971 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 972 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 973 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 974 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 975 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 976 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 977 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 978 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 979 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 980 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 981 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 982 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 983 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 984 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 985 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 986 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 987 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 988 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 989 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 990 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 991 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 992 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 993 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 994 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 995 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 996 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 997 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 998 0x0e000600, 0x0ff00f10,
999 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1000 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1001 0x0e100600, 0x0ff00f10,
1002 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1003 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1004 0x0e200600, 0x0ff00f10,
1005 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1006 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1007 0x0e300600, 0x0ff00f10,
1008 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 1009
62f3b8c8 1010 /* VFP Fused multiply add instructions. */
6b0dd094 1011 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1012 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1013 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1014 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1015 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1016 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1017 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1018 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
6b0dd094 1019 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1020 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1021 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1022 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1023 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1024 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1025 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1026 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 1027
33399f07 1028 /* FP v5. */
6b0dd094 1029 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1030 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
6b0dd094 1031 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1032 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
6b0dd094 1033 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1034 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1035 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1036 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1037 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1038 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1039 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1040 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1041 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1042 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
6b0dd094 1043 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1044 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
6b0dd094 1045 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1046 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
6b0dd094 1047 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1048 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
6b0dd094 1049 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1050 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
6b0dd094 1051 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1052 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 1053
05413229 1054 /* Generic coprocessor instructions. */
6b0dd094
AV		 1055 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
1056 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
823d2571 1057 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
6b0dd094 1058 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
823d2571
TG		 1059 0x0c500000, 0x0ff00000,
1060 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
6b0dd094 1061 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1062 0x0e000000, 0x0f000010,
1063 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1064 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1065 0x0e10f010, 0x0f10f010,
1066 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1067 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1068 0x0e100010, 0x0f100010,
1069 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1070 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1071 0x0e000010, 0x0f100010,
1072 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1073 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571 1074 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 1075 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571 1076 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
2fbad815 1077
05413229 1078 /* V6 coprocessor instructions. */
6b0dd094 1079 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
823d2571
TG		 1080 0xfc500000, 0xfff00000,
1081 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
6b0dd094 1082 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
823d2571
TG		 1083 0xfc400000, 0xfff00000,
1084 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
8f06b2d8 1085
c28eeff2 1086 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
6b0dd094 1087 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1088 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1089 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1090 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1091 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1092 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1093 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1094 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1095 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1096 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1097 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1098 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1099 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1100 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
6b0dd094 1101 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1102 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
6b0dd094 1103 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1104 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
6b0dd094 1105 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1106 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
c28eeff2 1107
c604a79a 1108 /* Dot Product instructions in the space of coprocessor 13. */
6b0dd094 1109 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a 1110 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
6b0dd094 1111 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a
JW		 1112 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1113
dec41383 1114 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
6b0dd094 1115 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1116 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1117 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1118 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1119 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1120 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1121 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1122 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1123 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1124 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1125 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1126 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1127 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1128 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
6b0dd094 1129 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383
JW		 1130 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1131
05413229 1132 /* V5 coprocessor instructions. */
6b0dd094 1133 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571 1134 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 1135 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571 1136 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 1137 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1138 0xfe000000, 0xff000010,
1139 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1140 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1141 0xfe000010, 0xff100010,
1142 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1143 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1144 0xfe100010, 0xff100010,
1145 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1146
b0c11777
RL		 1147 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1148 cp_num: bit <11:8> == 0b1001.
1149 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
6b0dd094 1150 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1151 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
6b0dd094 1152 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1153 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
6b0dd094 1154 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1155 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
6b0dd094 1156 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1157 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
6b0dd094 1158 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1159 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 1160 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1161 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
6b0dd094 1162 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1163 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
6b0dd094 1164 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1165 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
6b0dd094 1166 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1167 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
6b0dd094 1168 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1169 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
6b0dd094 1170 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1171 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1172 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1173 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1174 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1175 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1176 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1177 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1178 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1179 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
6b0dd094 1180 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1181 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
6b0dd094 1182 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1183 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
6b0dd094 1184 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1185 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
6b0dd094 1186 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1187 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1188 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1189 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1190 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1191 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1192 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1193 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1194 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1195 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
6b0dd094 1196 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1197 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
6b0dd094 1198 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1199 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
6b0dd094 1200 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1201 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1202 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1203 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
6b0dd094 1204 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1205 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1206 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1207 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1208 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1209 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1210 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1211 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
6b0dd094 1212 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1213 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
6b0dd094 1214 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1215 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
6b0dd094 1216 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1217 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
6b0dd094 1218 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777
RL		 1219 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1220
49e8a725 1221 /* ARMv8.3 javascript conversion instruction. */
6b0dd094 1222 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
49e8a725
SN		 1223 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1224
6b0dd094 1225 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 1226};
1227
16980d0b
JB		 1228/* Neon opcode table: This does not encode the top byte -- that is
1229 checked by the print_insn_neon routine, as it depends on whether we are
1230 doing thumb32 or arm32 disassembly. */
1231
1232/* print_insn_neon recognizes the following format control codes:
1233
1234 %% %
1235
c22aaad1 1236 %c print condition code
e2efe87d
MGD		 1237 %u print condition code (unconditional in ARM mode,
1238 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 1239 %A print v{st,ld}[1234] operands
1240 %B print v{st,ld}[1234] any one operands
1241 %C print v{st,ld}[1234] single->all operands
1242 %D print scalar
1243 %E print vmov, vmvn, vorr, vbic encoded constant
1244 %F print vtbl,vtbx register list
1245
1246 %<bitfield>r print as an ARM register
1247 %<bitfield>d print the bitfield in decimal
1248 %<bitfield>e print the 2^N - bitfield in decimal
1249 %<bitfield>D print as a NEON D register
1250 %<bitfield>Q print as a NEON Q register
1251 %<bitfield>R print as a NEON D or Q register
1252 %<bitfield>Sn print byte scaled width limited by n
1253 %<bitfield>Tn print short scaled width limited by n
1254 %<bitfield>Un print long scaled width limited by n
43e65147 1255
16980d0b
JB		 1256 %<bitfield>'c print specified char iff bitfield is all ones
1257 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1258 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1259
1260static const struct opcode32 neon_opcodes[] =
1261{
fe56b6ce 1262 /* Extract. */
823d2571
TG		 1263 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1264 0xf2b00840, 0xffb00850,
1265 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1266 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1267 0xf2b00000, 0xffb00810,
1268 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 1269
9743db03
AV		 1270 /* Data transfer between ARM and NEON registers. */
1271 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1272 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1273 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1274 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1275 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1276 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1277 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1278 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1279 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1280 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1281 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1282 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1283
fe56b6ce 1284 /* Move data element to all lanes. */
823d2571
TG		 1285 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1286 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1287 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1288 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1289 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1290 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 1291
fe56b6ce 1292 /* Table lookup. */
823d2571
TG		 1293 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1294 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1295 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1296 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1297
8e79c3df 1298 /* Half-precision conversions. */
823d2571
TG		 1299 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1300 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1301 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1302 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1303
1304 /* NEON fused multiply add instructions. */
823d2571 1305 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1306 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1307 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1308 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1309 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1310 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1311 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1312 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1313
fe56b6ce 1314 /* Two registers, miscellaneous. */
823d2571
TG		 1315 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1316 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1317 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1318 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1319 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1320 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1321 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1322 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1323 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1324 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1325 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1326 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1327 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1328 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1329 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1330 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1331 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1332 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1333 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1334 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1335 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1336 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1337 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1338 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1339 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1340 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1341 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1342 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1343 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1344 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1345 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1346 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1347 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1348 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1349 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1350 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1351 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1352 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1353 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1354 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1355 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1356 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1357 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1358 0xf3b20300, 0xffb30fd0,
1359 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1360 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1361 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1362 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1363 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1364 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1365 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1366 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1367 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1368 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1369 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1370 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1371 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1372 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1373 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1374 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1375 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1376 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1377 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1378 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1379 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1380 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1381 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1382 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1383 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1384 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1385 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1386 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1387 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1388 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1389 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1390 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1391 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1392 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1393 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1394 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1395 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1396 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1397 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1398 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1399 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1400 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1401 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1402 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1403 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1404 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1405 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1406 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301 1407 0xf3bb0600, 0xffbf0e10,
823d2571 1408 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1409 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1410 0xf3b70600, 0xffbf0e10,
1411 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
16980d0b 1412
fe56b6ce 1413 /* Three registers of the same length. */
823d2571
TG		 1414 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1415 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1416 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1417 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1418 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1419 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1420 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1421 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1422 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1423 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1424 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1425 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1426 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1427 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1428 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1429 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1430 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1431 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1432 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1433 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1434 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1435 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1436 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1437 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1438 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1439 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1440 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1441 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1442 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1443 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1444 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1445 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1446 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1447 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1448 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1449 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1450 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1451 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1452 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1453 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1454 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1455 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1456 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1457 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1458 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1459 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1460 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1461 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1462 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1463 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1465 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1466 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1467 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1468 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1469 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1470 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1471 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1473 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1474 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1475 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1477 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1478 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1479 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1481 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1482 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1483 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1484 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1485 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1486 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1487 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1489 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1490 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1491 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1492 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1493 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1494 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1495 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1496 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1497 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1498 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1499 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1500 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1501 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1502 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1503 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1504 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1505 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1506 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1507 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1508 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1509 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1510 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1511 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1512 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1513 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1514 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1515 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1516 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1517 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1518 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1519 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1520 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1521 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1522 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1523 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1524 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1525 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1526 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1527 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1528 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1529 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1530 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1531 0xf2000b00, 0xff800f10,
1532 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1533 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1534 0xf2000b10, 0xff800f10,
1535 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1536 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1537 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1538 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1539 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1540 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1541 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1542 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1543 0xf3000b00, 0xff800f10,
1544 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1545 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1546 0xf2000000, 0xfe800f10,
1547 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1548 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1549 0xf2000010, 0xfe800f10,
1550 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1551 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1552 0xf2000100, 0xfe800f10,
1553 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1554 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1555 0xf2000200, 0xfe800f10,
1556 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1557 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1558 0xf2000210, 0xfe800f10,
1559 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1560 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1561 0xf2000300, 0xfe800f10,
1562 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1564 0xf2000310, 0xfe800f10,
1565 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1566 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1567 0xf2000400, 0xfe800f10,
1568 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1569 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1570 0xf2000410, 0xfe800f10,
1571 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1572 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1573 0xf2000500, 0xfe800f10,
1574 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1576 0xf2000510, 0xfe800f10,
1577 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1578 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1579 0xf2000600, 0xfe800f10,
1580 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1581 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1582 0xf2000610, 0xfe800f10,
1583 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1584 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1585 0xf2000700, 0xfe800f10,
1586 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1587 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1588 0xf2000710, 0xfe800f10,
1589 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1590 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1591 0xf2000910, 0xfe800f10,
1592 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1594 0xf2000a00, 0xfe800f10,
1595 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1596 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1597 0xf2000a10, 0xfe800f10,
1598 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1599 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1600 0xf3000b10, 0xff800f10,
1601 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1602 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1603 0xf3000c10, 0xff800f10,
1604 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1605
fe56b6ce 1606 /* One register and an immediate value. */
823d2571
TG		 1607 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1608 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1609 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1610 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1611 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1612 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1613 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1614 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1615 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1616 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1618 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1619 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1620 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1621 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1622 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1623 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1624 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1625 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1626 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1627 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1628 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1630 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1631 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1632 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1633
fe56b6ce 1634 /* Two registers and a shift amount. */
823d2571
TG		 1635 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1636 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1638 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1639 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1640 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1642 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1643 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1644 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1646 0xf2880950, 0xfeb80fd0,
1647 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1648 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1649 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1650 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1651 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1652 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1653 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1654 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1655 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1656 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1657 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1658 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1659 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1660 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1661 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1662 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1663 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1664 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1665 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1666 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1667 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1668 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1669 0xf2900950, 0xfeb00fd0,
1670 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1671 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1672 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1673 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1674 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1675 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1676 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1677 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1678 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1679 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1680 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1681 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1682 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1683 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1684 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1685 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1686 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1687 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1688 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1689 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1690 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1691 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1692 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1693 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1694 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1695 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1696 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1697 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1698 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1699 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1700 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1701 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1702 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1703 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1704 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1705 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1706 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1707 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1708 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1709 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1710 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1711 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1712 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1713 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1714 0xf2a00950, 0xfea00fd0,
1715 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1716 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1717 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1718 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1719 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1720 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1721 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1722 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1723 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1724 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1725 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1726 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1727 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1728 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1729 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1730 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1731 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1732 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1733 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1734 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1735 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1736 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1737 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1738 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1739 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1740 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1741 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1742 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1743 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1744 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1745 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1746 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1747 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1748 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1749 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1750 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1751 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1753 0xf2a00e10, 0xfea00e90,
1754 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
cc933301
JW		 1755 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1756 0xf2a00c10, 0xfea00e90,
1757 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 1758
fe56b6ce 1759 /* Three registers of different lengths. */
823d2571
TG		 1760 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1761 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1762 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1763 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1764 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1765 0xf2800400, 0xff800f50,
1766 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1767 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1768 0xf2800600, 0xff800f50,
1769 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1770 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1771 0xf2800900, 0xff800f50,
1772 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1773 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1774 0xf2800b00, 0xff800f50,
1775 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1776 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1777 0xf2800d00, 0xff800f50,
1778 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1779 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1780 0xf3800400, 0xff800f50,
1781 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1782 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1783 0xf3800600, 0xff800f50,
1784 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1785 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1786 0xf2800000, 0xfe800f50,
1787 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1788 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1789 0xf2800100, 0xfe800f50,
1790 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1791 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1792 0xf2800200, 0xfe800f50,
1793 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1794 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1795 0xf2800300, 0xfe800f50,
1796 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1797 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1798 0xf2800500, 0xfe800f50,
1799 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1800 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1801 0xf2800700, 0xfe800f50,
1802 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1803 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1804 0xf2800800, 0xfe800f50,
1805 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1806 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1807 0xf2800a00, 0xfe800f50,
1808 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1809 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1810 0xf2800c00, 0xfe800f50,
1811 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 1812
fe56b6ce 1813 /* Two registers and a scalar. */
823d2571
TG		 1814 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1815 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1816 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1817 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1818 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1819 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1820 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1821 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1822 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1823 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1824 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1825 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1826 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1827 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1828 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1829 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1830 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1831 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1832 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1833 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1834 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1835 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1836 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1837 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1838 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1839 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1840 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1841 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1842 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1843 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1844 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1845 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1846 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1847 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1848 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1849 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1850 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1851 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1852 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1853 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1854 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1855 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1856 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1857 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1858 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1859 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1860 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1861 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1862 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1863 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1864 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1865 0xf2800240, 0xfe800f50,
1866 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1867 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1868 0xf2800640, 0xfe800f50,
1869 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1870 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1871 0xf2800a40, 0xfe800f50,
1872 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 1873 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1874 0xf2800e40, 0xff800f50,
1875 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1876 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1877 0xf2800f40, 0xff800f50,
1878 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1879 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1880 0xf3800e40, 0xff800f50,
1881 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1882 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1883 0xf3800f40, 0xff800f50,
1884 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1885 },
16980d0b 1886
fe56b6ce 1887 /* Element and structure load/store. */
823d2571
TG		 1888 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1889 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1890 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1891 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1892 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1893 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1894 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1895 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1896 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1897 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1898 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1899 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1900 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1901 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1902 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1903 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1904 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1905 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1906 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1907 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1908 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1909 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1910 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1911 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1912 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1913 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1914 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1915 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1916 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1917 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1918 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1919 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1920 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1921 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1922 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1923 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1924 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1925 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1926
1927 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 1928};
1929
73cd51e5
AV		 1930/* mve opcode table. */
1931
1932/* print_insn_mve recognizes the following format control codes:
1933
1934 %% %
1935
ef1576a1
AV		 1936 %a print '+' or '-' or imm offset in vldr[bhwd] and
1937 vstr[bhwd]
9743db03 1938 %c print condition code
aef6d006
AV		 1939 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
1940 %u print 'U' (unsigned) or 'S' for various mve instructions
143275ea 1941 %i print MVE predicate(s) for vpt and vpst
bf0b396d 1942 %m print rounding mode for vcvt and vrint
143275ea 1943 %n print vector comparison code for predicated instruction
bf0b396d 1944 %s print size for various vcvt instructions
143275ea
AV		 1945 %v print vector predicate for instruction in predicated
1946 block
ef1576a1 1947 %o print offset scaled for vldr[hwd] and vstr[hwd]
04d54ace
AV		 1948 %w print writeback mode for MVE v{st,ld}[24]
1949 %B print v{st,ld}[24] any one operands
c507f10b
AV		 1950 %E print vmov, vmvn, vorr, vbic encoded constant
1951 %N print generic index for vmov
14925797 1952 %T print bottom ('b') or top ('t') of source register
d3b63143 1953 %X print exchange field in vmla* instructions
04d54ace 1954
9743db03 1955 %<bitfield>r print as an ARM register
04d54ace 1956 %<bitfield>d print the bitfield in decimal
d3b63143 1957 %<bitfield>A print accumulate or not
143275ea 1958 %<bitfield>Q print as a MVE Q register
c507f10b 1959 %<bitfield>F print as a MVE S register
143275ea
AV		 1960 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
1961 UNPREDICTABLE
1962 %<bitfield>s print size for vector predicate & non VMOV instructions
ef1576a1 1963 %<bitfield>i print immediate for vstr/vldr reg +/- imm
1c8f2df8 1964 %<bitfield>h print high half of 64-bit destination reg
bf0b396d 1965 %<bitfield>k print immediate for vector conversion instruction
1c8f2df8
AV		 1966 %<bitfield>l print low half of 64-bit destination reg
1967 %<bitfield>u print immediate value for vddup/vdwdup
c507f10b 1968 %<bitfield>x print the bitfield in hex.
1c8f2df8 1969 */
73cd51e5
AV		 1970
1971static const struct mopcode32 mve_opcodes[] =
1972{
143275ea
AV		 1973 /* MVE. */
1974
1975 {ARM_FEATURE_COPROC (FPU_MVE),
1976 MVE_VPST,
1977 0xfe310f4d, 0xffbf1fff,
1978 "vpst%i"
1979 },
1980
1981 /* Floating point VPT T1. */
1982 {ARM_FEATURE_COPROC (FPU_MVE_FP),
1983 MVE_VPT_FP_T1,
1984 0xee310f00, 0xefb10f50,
1985 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
1986 /* Floating point VPT T2. */
1987 {ARM_FEATURE_COPROC (FPU_MVE_FP),
1988 MVE_VPT_FP_T2,
1989 0xee310f40, 0xefb10f50,
1990 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
1991
1992 /* Vector VPT T1. */
1993 {ARM_FEATURE_COPROC (FPU_MVE),
1994 MVE_VPT_VEC_T1,
1995 0xfe010f00, 0xff811f51,
1996 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
1997 /* Vector VPT T2. */
1998 {ARM_FEATURE_COPROC (FPU_MVE),
1999 MVE_VPT_VEC_T2,
2000 0xfe010f01, 0xff811f51,
2001 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2002 /* Vector VPT T3. */
2003 {ARM_FEATURE_COPROC (FPU_MVE),
2004 MVE_VPT_VEC_T3,
2005 0xfe011f00, 0xff811f50,
2006 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2007 /* Vector VPT T4. */
2008 {ARM_FEATURE_COPROC (FPU_MVE),
2009 MVE_VPT_VEC_T4,
2010 0xfe010f40, 0xff811f70,
2011 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2012 /* Vector VPT T5. */
2013 {ARM_FEATURE_COPROC (FPU_MVE),
2014 MVE_VPT_VEC_T5,
2015 0xfe010f60, 0xff811f70,
2016 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2017 /* Vector VPT T6. */
2018 {ARM_FEATURE_COPROC (FPU_MVE),
2019 MVE_VPT_VEC_T6,
2020 0xfe011f40, 0xff811f50,
2021 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2022
c507f10b
AV		 2023 /* Vector VBIC immediate. */
2024 {ARM_FEATURE_COPROC (FPU_MVE),
2025 MVE_VBIC_IMM,
2026 0xef800070, 0xefb81070,
2027 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2028
2029 /* Vector VBIC register. */
2030 {ARM_FEATURE_COPROC (FPU_MVE),
2031 MVE_VBIC_REG,
2032 0xef100150, 0xffb11f51,
2033 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2034
d3b63143
AV		 2035 /* Vector VADDLV. */
2036 {ARM_FEATURE_COPROC (FPU_MVE),
2037 MVE_VADDLV,
2038 0xee890f00, 0xef8f1fd1,
2039 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2040
2041 /* Vector VADDV. */
2042 {ARM_FEATURE_COPROC (FPU_MVE),
2043 MVE_VADDV,
2044 0xeef10f00, 0xeff31fd1,
2045 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2046
143275ea
AV		 2047 /* Vector VCMP floating point T1. */
2048 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2049 MVE_VCMP_FP_T1,
2050 0xee310f00, 0xeff1ef50,
2051 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2052
2053 /* Vector VCMP floating point T2. */
2054 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2055 MVE_VCMP_FP_T2,
2056 0xee310f40, 0xeff1ef50,
2057 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2058
2059 /* Vector VCMP T1. */
2060 {ARM_FEATURE_COPROC (FPU_MVE),
2061 MVE_VCMP_VEC_T1,
2062 0xfe010f00, 0xffc1ff51,
2063 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2064 /* Vector VCMP T2. */
2065 {ARM_FEATURE_COPROC (FPU_MVE),
2066 MVE_VCMP_VEC_T2,
2067 0xfe010f01, 0xffc1ff51,
2068 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2069 /* Vector VCMP T3. */
2070 {ARM_FEATURE_COPROC (FPU_MVE),
2071 MVE_VCMP_VEC_T3,
2072 0xfe011f00, 0xffc1ff50,
2073 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2074 /* Vector VCMP T4. */
2075 {ARM_FEATURE_COPROC (FPU_MVE),
2076 MVE_VCMP_VEC_T4,
2077 0xfe010f40, 0xffc1ff70,
2078 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2079 /* Vector VCMP T5. */
2080 {ARM_FEATURE_COPROC (FPU_MVE),
2081 MVE_VCMP_VEC_T5,
2082 0xfe010f60, 0xffc1ff70,
2083 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2084 /* Vector VCMP T6. */
2085 {ARM_FEATURE_COPROC (FPU_MVE),
2086 MVE_VCMP_VEC_T6,
2087 0xfe011f40, 0xffc1ff50,
2088 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2089
9743db03
AV		 2090 /* Vector VDUP. */
2091 {ARM_FEATURE_COPROC (FPU_MVE),
2092 MVE_VDUP,
2093 0xeea00b10, 0xffb10f5f,
2094 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2095
2096 /* Vector VEOR. */
2097 {ARM_FEATURE_COPROC (FPU_MVE),
2098 MVE_VEOR,
2099 0xff000150, 0xffd11f51,
2100 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2101
2102 /* Vector VFMA, vector * scalar. */
2103 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2104 MVE_VFMA_FP_SCALAR,
2105 0xee310e40, 0xefb11f70,
2106 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2107
2108 /* Vector VFMA floating point. */
2109 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2110 MVE_VFMA_FP,
2111 0xef000c50, 0xffa11f51,
2112 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2113
2114 /* Vector VFMS floating point. */
2115 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2116 MVE_VFMS_FP,
2117 0xef200c50, 0xffa11f51,
2118 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2119
2120 /* Vector VFMAS, vector * scalar. */
2121 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2122 MVE_VFMAS_FP_SCALAR,
2123 0xee311e40, 0xefb11f70,
2124 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2125
2126 /* Vector VHADD T1. */
2127 {ARM_FEATURE_COPROC (FPU_MVE),
2128 MVE_VHADD_T1,
2129 0xef000040, 0xef811f51,
2130 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2131
2132 /* Vector VHADD T2. */
2133 {ARM_FEATURE_COPROC (FPU_MVE),
2134 MVE_VHADD_T2,
2135 0xee000f40, 0xef811f70,
2136 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2137
2138 /* Vector VHSUB T1. */
2139 {ARM_FEATURE_COPROC (FPU_MVE),
2140 MVE_VHSUB_T1,
2141 0xef000240, 0xef811f51,
2142 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2143
2144 /* Vector VHSUB T2. */
2145 {ARM_FEATURE_COPROC (FPU_MVE),
2146 MVE_VHSUB_T2,
2147 0xee001f40, 0xef811f70,
2148 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2149
2150 /* Vector VDUP. */
2151 {ARM_FEATURE_COPROC (FPU_MVE),
2152 MVE_VDUP,
2153 0xeea00b10, 0xffb10f5f,
2154 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2155
2156 /* Vector VRHADD. */
2157 {ARM_FEATURE_COPROC (FPU_MVE),
2158 MVE_VRHADD,
2159 0xef000140, 0xef811f51,
2160 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2161
bf0b396d
AV		 2162 /* Vector VCVT. */
2163 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2164 MVE_VCVT_FP_FIX_VEC,
2165 0xef800c50, 0xef801cd1,
2166 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2167
2168 /* Vector VCVT. */
2169 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2170 MVE_VCVT_BETWEEN_FP_INT,
2171 0xffb30640, 0xffb31e51,
2172 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2173
2174 /* Vector VCVT between single and half-precision float, bottom half. */
2175 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2176 MVE_VCVT_FP_HALF_FP,
2177 0xee3f0e01, 0xefbf1fd1,
2178 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2179
2180 /* Vector VCVT between single and half-precision float, top half. */
2181 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2182 MVE_VCVT_FP_HALF_FP,
2183 0xee3f1e01, 0xefbf1fd1,
2184 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2185
2186 /* Vector VCVT. */
2187 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2188 MVE_VCVT_FROM_FP_TO_INT,
2189 0xffb30040, 0xffb31c51,
2190 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2191
1c8f2df8
AV		 2192 /* Vector VDDUP. */
2193 {ARM_FEATURE_COPROC (FPU_MVE),
2194 MVE_VDDUP,
2195 0xee011f6e, 0xff811f7e,
2196 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2197
2198 /* Vector VDWDUP. */
2199 {ARM_FEATURE_COPROC (FPU_MVE),
2200 MVE_VDWDUP,
2201 0xee011f60, 0xff811f70,
2202 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2203
2204 /* Vector VIWDUP. */
2205 {ARM_FEATURE_COPROC (FPU_MVE),
2206 MVE_VIWDUP,
2207 0xee010f60, 0xff811f70,
2208 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2209
2210 /* Vector VIDUP. */
2211 {ARM_FEATURE_COPROC (FPU_MVE),
2212 MVE_VIDUP,
2213 0xee010f6e, 0xff811f7e,
2214 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2215
04d54ace
AV		 2216 /* Vector VLD2. */
2217 {ARM_FEATURE_COPROC (FPU_MVE),
2218 MVE_VLD2,
2219 0xfc901e00, 0xff901e5f,
2220 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2221
2222 /* Vector VLD4. */
2223 {ARM_FEATURE_COPROC (FPU_MVE),
2224 MVE_VLD4,
2225 0xfc901e01, 0xff901e1f,
2226 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2227
ef1576a1
AV		 2228 /* Vector VLDRB gather load. */
2229 {ARM_FEATURE_COPROC (FPU_MVE),
2230 MVE_VLDRB_GATHER_T1,
2231 0xec900e00, 0xefb01e50,
2232 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2233
2234 /* Vector VLDRH gather load. */
2235 {ARM_FEATURE_COPROC (FPU_MVE),
2236 MVE_VLDRH_GATHER_T2,
2237 0xec900e10, 0xefb01e50,
2238 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2239
2240 /* Vector VLDRW gather load. */
2241 {ARM_FEATURE_COPROC (FPU_MVE),
2242 MVE_VLDRW_GATHER_T3,
2243 0xfc900f40, 0xffb01fd0,
2244 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2245
2246 /* Vector VLDRD gather load. */
2247 {ARM_FEATURE_COPROC (FPU_MVE),
2248 MVE_VLDRD_GATHER_T4,
2249 0xec900fd0, 0xefb01fd0,
2250 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2251
2252 /* Vector VLDRW gather load. */
2253 {ARM_FEATURE_COPROC (FPU_MVE),
2254 MVE_VLDRW_GATHER_T5,
2255 0xfd101e00, 0xff111f00,
2256 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2257
2258 /* Vector VLDRD gather load, variant T6. */
2259 {ARM_FEATURE_COPROC (FPU_MVE),
2260 MVE_VLDRD_GATHER_T6,
2261 0xfd101f00, 0xff111f00,
2262 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2263
aef6d006
AV		 2264 /* Vector VLDRB. */
2265 {ARM_FEATURE_COPROC (FPU_MVE),
2266 MVE_VLDRB_T1,
2267 0xec100e00, 0xee581e00,
2268 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2269
2270 /* Vector VLDRH. */
2271 {ARM_FEATURE_COPROC (FPU_MVE),
2272 MVE_VLDRH_T2,
2273 0xec180e00, 0xee581e00,
2274 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2275
2276 /* Vector VLDRB unsigned, variant T5. */
2277 {ARM_FEATURE_COPROC (FPU_MVE),
2278 MVE_VLDRB_T5,
2279 0xec101e00, 0xfe101f80,
2280 "vldrb%v.u8\t%13-15,22Q, %d"},
2281
2282 /* Vector VLDRH unsigned, variant T6. */
2283 {ARM_FEATURE_COPROC (FPU_MVE),
2284 MVE_VLDRH_T6,
2285 0xec101e80, 0xfe101f80,
2286 "vldrh%v.u16\t%13-15,22Q, %d"},
2287
2288 /* Vector VLDRW unsigned, variant T7. */
2289 {ARM_FEATURE_COPROC (FPU_MVE),
2290 MVE_VLDRW_T7,
2291 0xec101f00, 0xfe101f80,
2292 "vldrw%v.u32\t%13-15,22Q, %d"},
2293
d3b63143
AV		 2294 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2295 opcode aliasing. */
2296 {ARM_FEATURE_COPROC (FPU_MVE),
2297 MVE_VMLALDAV,
2298 0xee801e00, 0xef801f51,
2299 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2300
2301 {ARM_FEATURE_COPROC (FPU_MVE),
2302 MVE_VMLALDAV,
2303 0xee800e00, 0xef801f51,
2304 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2305
2306 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2307 {ARM_FEATURE_COPROC (FPU_MVE),
2308 MVE_VMLADAV_T1,
2309 0xeef00e00, 0xeff01f51,
2310 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2311
2312 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2313 {ARM_FEATURE_COPROC (FPU_MVE),
2314 MVE_VMLADAV_T2,
2315 0xeef00f00, 0xeff11f51,
2316 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2317
2318 /* Vector VMLADAV T1 variant. */
2319 {ARM_FEATURE_COPROC (FPU_MVE),
2320 MVE_VMLADAV_T1,
2321 0xeef01e00, 0xeff01f51,
2322 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2323
2324 /* Vector VMLADAV T2 variant. */
2325 {ARM_FEATURE_COPROC (FPU_MVE),
2326 MVE_VMLADAV_T2,
2327 0xeef01f00, 0xeff11f51,
2328 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2329
2330 /* Vector VMLAS. */
2331 {ARM_FEATURE_COPROC (FPU_MVE),
2332 MVE_VMLAS,
2333 0xee011e40, 0xef811f70,
2334 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2335
2336 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2337 opcode aliasing. */
2338 {ARM_FEATURE_COPROC (FPU_MVE),
2339 MVE_VRMLSLDAVH,
2340 0xfe800e01, 0xff810f51,
2341 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2342
2343 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2344 opcdoe aliasing. */
2345 {ARM_FEATURE_COPROC (FPU_MVE),
2346 MVE_VMLSLDAV,
2347 0xee800e01, 0xff800f51,
2348 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2349
2350 /* Vector VMLSDAV T1 Variant. */
2351 {ARM_FEATURE_COPROC (FPU_MVE),
2352 MVE_VMLSDAV_T1,
2353 0xeef00e01, 0xfff00f51,
2354 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2355
2356 /* Vector VMLSDAV T2 Variant. */
2357 {ARM_FEATURE_COPROC (FPU_MVE),
2358 MVE_VMLSDAV_T2,
2359 0xfef00e01, 0xfff10f51,
2360 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2361
c507f10b
AV		 2362 /* Vector VMOV between gpr and half precision register, op == 0. */
2363 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2364 MVE_VMOV_HFP_TO_GP,
2365 0xee000910, 0xfff00f7f,
2366 "vmov.f16\t%7,16-19F, %12-15r"},
2367
2368 /* Vector VMOV between gpr and half precision register, op == 1. */
2369 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2370 MVE_VMOV_HFP_TO_GP,
2371 0xee100910, 0xfff00f7f,
2372 "vmov.f16\t%12-15r, %7,16-19F"},
2373
2374 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2375 MVE_VMOV_GP_TO_VEC_LANE,
2376 0xee000b10, 0xff900f1f,
2377 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2378
2379 /* Vector VORR immediate to vector.
2380 NOTE: MVE_VORR_IMM must appear in the table
2381 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2382 {ARM_FEATURE_COPROC (FPU_MVE),
2383 MVE_VORR_IMM,
2384 0xef800050, 0xefb810f0,
2385 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2386
2387 /* Vector VMOV immediate to vector,
2388 cmode == 11x1 -> VMVN which is UNDEFINED
2389 for such a cmode. */
2390 {ARM_FEATURE_COPROC (FPU_MVE),
2391 MVE_VMVN_IMM, 0xef800d50, 0xefb81dd0, UNDEFINED_INSTRUCTION},
2392
2393 /* Vector VMOV immediate to vector. */
2394 {ARM_FEATURE_COPROC (FPU_MVE),
2395 MVE_VMOV_IMM_TO_VEC,
2396 0xef800050, 0xefb810d0,
2397 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2398
2399 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2400 {ARM_FEATURE_COPROC (FPU_MVE),
2401 MVE_VMOV2_VEC_LANE_TO_GP,
2402 0xec000f00, 0xffb01ff0,
2403 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2404
2405 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2406 {ARM_FEATURE_COPROC (FPU_MVE),
2407 MVE_VMOV2_VEC_LANE_TO_GP,
2408 0xec000f10, 0xffb01ff0,
2409 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2410
2411 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2412 {ARM_FEATURE_COPROC (FPU_MVE),
2413 MVE_VMOV2_GP_TO_VEC_LANE,
2414 0xec100f00, 0xffb01ff0,
2415 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2416
2417 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2418 {ARM_FEATURE_COPROC (FPU_MVE),
2419 MVE_VMOV2_GP_TO_VEC_LANE,
2420 0xec100f10, 0xffb01ff0,
2421 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2422
2423 /* Vector VMOV Vector lane to gpr. */
2424 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2425 MVE_VMOV_VEC_LANE_TO_GP,
2426 0xee100b10, 0xff100f1f,
2427 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2428
14925797
AV		 2429 /* Vector VMOVL long. */
2430 {ARM_FEATURE_COPROC (FPU_MVE),
2431 MVE_VMOVL,
2432 0xeea00f40, 0xefa70fd1,
2433 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2434
2435 /* Vector VMOV and narrow. */
2436 {ARM_FEATURE_COPROC (FPU_MVE),
2437 MVE_VMOVN,
2438 0xfe310e81, 0xffb30fd1,
2439 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2440
c507f10b
AV		 2441 /* Floating point move extract. */
2442 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2443 MVE_VMOVX,
2444 0xfeb00a40, 0xffbf0fd0,
2445 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2446
14925797
AV		 2447 /* Vector VMULL integer. */
2448 {ARM_FEATURE_COPROC (FPU_MVE),
2449 MVE_VMULL_INT,
2450 0xee010e00, 0xef810f51,
2451 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2452
2453 /* Vector VMULL polynomial. */
2454 {ARM_FEATURE_COPROC (FPU_MVE),
2455 MVE_VMULL_POLY,
2456 0xee310e00, 0xefb10f51,
2457 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2458
c507f10b
AV		 2459 /* Vector VMVN immediate to vector. */
2460 {ARM_FEATURE_COPROC (FPU_MVE),
2461 MVE_VMVN_IMM,
2462 0xef800070, 0xefb810f0,
2463 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2464
2465 /* Vector VMVN register. */
2466 {ARM_FEATURE_COPROC (FPU_MVE),
2467 MVE_VMVN_REG,
2468 0xffb005c0, 0xffbf1fd1,
2469 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2470
2471 /* Vector VORN, vector bitwise or not. */
2472 {ARM_FEATURE_COPROC (FPU_MVE),
2473 MVE_VORN,
2474 0xef300150, 0xffb11f51,
2475 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2476
2477 /* Vector VORR register. */
2478 {ARM_FEATURE_COPROC (FPU_MVE),
2479 MVE_VORR_REG,
2480 0xef200150, 0xffb11f51,
2481 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2482
14925797
AV		 2483 /* Vector VQDMULL T1 variant. */
2484 {ARM_FEATURE_COPROC (FPU_MVE),
2485 MVE_VQDMULL_T1,
2486 0xee300f01, 0xefb10f51,
2487 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2488
2489 /* Vector VQDMULL T2 variant. */
2490 {ARM_FEATURE_COPROC (FPU_MVE),
2491 MVE_VQDMULL_T2,
2492 0xee300f60, 0xefb10f70,
2493 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2494
2495 /* Vector VQMOVN. */
2496 {ARM_FEATURE_COPROC (FPU_MVE),
2497 MVE_VQMOVN,
2498 0xee330e01, 0xefb30fd1,
2499 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
2500
2501 /* Vector VQMOVUN. */
2502 {ARM_FEATURE_COPROC (FPU_MVE),
2503 MVE_VQMOVUN,
2504 0xee310e81, 0xffb30fd1,
2505 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2506
d3b63143
AV		 2507 /* Vector VQDMLADH. */
2508 {ARM_FEATURE_COPROC (FPU_MVE),
2509 MVE_VQDMLADH,
2510 0xee000e00, 0xff810f51,
2511 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2512
2513 /* Vector VQRDMLADH. */
2514 {ARM_FEATURE_COPROC (FPU_MVE),
2515 MVE_VQRDMLADH,
2516 0xee000e01, 0xff810f51,
2517 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2518
2519 /* Vector VQDMLAH. */
2520 {ARM_FEATURE_COPROC (FPU_MVE),
2521 MVE_VQDMLAH,
2522 0xee000e60, 0xef811f70,
2523 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2524
2525 /* Vector VQRDMLAH. */
2526 {ARM_FEATURE_COPROC (FPU_MVE),
2527 MVE_VQRDMLAH,
2528 0xee000e40, 0xef811f70,
2529 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2530
2531 /* Vector VQDMLASH. */
2532 {ARM_FEATURE_COPROC (FPU_MVE),
2533 MVE_VQDMLASH,
2534 0xee001e60, 0xef811f70,
2535 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2536
2537 /* Vector VQRDMLASH. */
2538 {ARM_FEATURE_COPROC (FPU_MVE),
2539 MVE_VQRDMLASH,
2540 0xee001e40, 0xef811f70,
2541 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2542
2543 /* Vector VQDMLSDH. */
2544 {ARM_FEATURE_COPROC (FPU_MVE),
2545 MVE_VQDMLSDH,
2546 0xfe000e00, 0xff810f51,
2547 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2548
2549 /* Vector VQRDMLSDH. */
2550 {ARM_FEATURE_COPROC (FPU_MVE),
2551 MVE_VQRDMLSDH,
2552 0xfe000e01, 0xff810f51,
2553 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2554
2555 /* Vector VQDMULH T1 variant. */
2556 {ARM_FEATURE_COPROC (FPU_MVE),
2557 MVE_VQDMULH_T1,
2558 0xef000b40, 0xff811f51,
2559 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2560
2561 /* Vector VQRDMULH T2 variant. */
2562 {ARM_FEATURE_COPROC (FPU_MVE),
2563 MVE_VQRDMULH_T2,
2564 0xff000b40, 0xff811f51,
2565 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2566
2567 /* Vector VQDMULH T3 variant. */
2568 {ARM_FEATURE_COPROC (FPU_MVE),
2569 MVE_VQDMULH_T3,
2570 0xee010e60, 0xff811f70,
2571 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2572
2573 /* Vector VQRDMULH T4 variant. */
2574 {ARM_FEATURE_COPROC (FPU_MVE),
2575 MVE_VQRDMULH_T4,
2576 0xfe010e60, 0xff811f70,
2577 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2578
bf0b396d
AV		 2579 /* Vector VRINT floating point. */
2580 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2581 MVE_VRINT_FP,
2582 0xffb20440, 0xffb31c51,
2583 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2584
d3b63143
AV		 2585 /* Vector VRMLALDAVH. */
2586 {ARM_FEATURE_COPROC (FPU_MVE),
2587 MVE_VRMLALDAVH,
2588 0xee800f00, 0xef811f51,
2589 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2590
2591 /* Vector VRMLALDAVH. */
2592 {ARM_FEATURE_COPROC (FPU_MVE),
2593 MVE_VRMLALDAVH,
2594 0xee801f00, 0xef811f51,
2595 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2596
04d54ace
AV		 2597 /* Vector VST2 no writeback. */
2598 {ARM_FEATURE_COPROC (FPU_MVE),
2599 MVE_VST2,
2600 0xfc801e00, 0xffb01e5f,
2601 "vst2%5d.%7-8s\t%B, [%16-19r]"},
2602
2603 /* Vector VST2 writeback. */
2604 {ARM_FEATURE_COPROC (FPU_MVE),
2605 MVE_VST2,
2606 0xfca01e00, 0xffb01e5f,
2607 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
2608
2609 /* Vector VST4 no writeback. */
2610 {ARM_FEATURE_COPROC (FPU_MVE),
2611 MVE_VST4,
2612 0xfc801e01, 0xffb01e1f,
2613 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
2614
2615 /* Vector VST4 writeback. */
2616 {ARM_FEATURE_COPROC (FPU_MVE),
2617 MVE_VST4,
2618 0xfca01e01, 0xffb01e1f,
2619 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
2620
ef1576a1
AV		 2621 /* Vector VSTRB scatter store, T1 variant. */
2622 {ARM_FEATURE_COPROC (FPU_MVE),
2623 MVE_VSTRB_SCATTER_T1,
2624 0xec800e00, 0xffb01e50,
2625 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2626
2627 /* Vector VSTRH scatter store, T2 variant. */
2628 {ARM_FEATURE_COPROC (FPU_MVE),
2629 MVE_VSTRH_SCATTER_T2,
2630 0xec800e10, 0xffb01e50,
2631 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2632
2633 /* Vector VSTRW scatter store, T3 variant. */
2634 {ARM_FEATURE_COPROC (FPU_MVE),
2635 MVE_VSTRW_SCATTER_T3,
2636 0xec800e40, 0xffb01e50,
2637 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2638
2639 /* Vector VSTRD scatter store, T4 variant. */
2640 {ARM_FEATURE_COPROC (FPU_MVE),
2641 MVE_VSTRD_SCATTER_T4,
2642 0xec800fd0, 0xffb01fd0,
2643 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2644
2645 /* Vector VSTRW scatter store, T5 variant. */
2646 {ARM_FEATURE_COPROC (FPU_MVE),
2647 MVE_VSTRW_SCATTER_T5,
2648 0xfd001e00, 0xff111f00,
2649 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2650
2651 /* Vector VSTRD scatter store, T6 variant. */
2652 {ARM_FEATURE_COPROC (FPU_MVE),
2653 MVE_VSTRD_SCATTER_T6,
2654 0xfd001f00, 0xff111f00,
2655 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2656
aef6d006
AV		 2657 /* Vector VSTRB. */
2658 {ARM_FEATURE_COPROC (FPU_MVE),
2659 MVE_VSTRB_T1,
2660 0xec000e00, 0xfe581e00,
2661 "vstrb%v.%7-8s\t%13-15Q, %d"},
2662
2663 /* Vector VSTRH. */
2664 {ARM_FEATURE_COPROC (FPU_MVE),
2665 MVE_VSTRH_T2,
2666 0xec080e00, 0xfe581e00,
2667 "vstrh%v.%7-8s\t%13-15Q, %d"},
2668
2669 /* Vector VSTRB variant T5. */
2670 {ARM_FEATURE_COPROC (FPU_MVE),
2671 MVE_VSTRB_T5,
2672 0xec001e00, 0xfe101f80,
2673 "vstrb%v.8\t%13-15,22Q, %d"},
2674
2675 /* Vector VSTRH variant T6. */
2676 {ARM_FEATURE_COPROC (FPU_MVE),
2677 MVE_VSTRH_T6,
2678 0xec001e80, 0xfe101f80,
2679 "vstrh%v.16\t%13-15,22Q, %d"},
2680
2681 /* Vector VSTRW variant T7. */
2682 {ARM_FEATURE_COPROC (FPU_MVE),
2683 MVE_VSTRW_T7,
2684 0xec001f00, 0xfe101f80,
2685 "vstrw%v.32\t%13-15,22Q, %d"},
2686
143275ea
AV		 2687 {ARM_FEATURE_CORE_LOW (0),
2688 MVE_NONE,
2689 0x00000000, 0x00000000, 0}
73cd51e5
AV		 2690};
2691
8f06b2d8
PB		 2692/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
2693 ordered: they must be searched linearly from the top to obtain a correct
2694 match. */
2695
2696/* print_insn_arm recognizes the following format control codes:
2697
2698 %% %
2699
2700 %a print address for ldr/str instruction
2701 %s print address for ldr/str halfword/signextend instruction
c1e26897 2702 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 2703 %b print branch destination
2704 %c print condition code (always bits 28-31)
2705 %m print register mask for ldm/stm instruction
2706 %o print operand2 (immediate or register + shift)
2707 %p print 'p' iff bits 12-15 are 15
2708 %t print 't' iff bit 21 set and bit 24 clear
2709 %B print arm BLX(1) destination
2710 %C print the PSR sub type.
62b3e311
PB		 2711 %U print barrier type.
2712 %P print address for pli instruction.
8f06b2d8
PB		 2713
2714 %<bitfield>r print as an ARM register
9eb6c0f1 2715 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 2716 %<bitfield>R as %r but r15 is UNPREDICTABLE
2717 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
2718 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 2719 %<bitfield>d print the bitfield in decimal
43e65147 2720 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 2721 %<bitfield>x print the bitfield in hex
2722 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 2723
16980d0b
JB		 2724 %<bitfield>'c print specified char iff bitfield is all ones
2725 %<bitfield>`c print specified char iff bitfield is all zeroes
2726 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 2727
8f06b2d8
PB		 2728 %e print arm SMI operand (bits 0..7,8..19).
2729 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 2730 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
2731 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 2732
8f06b2d8
PB		 2733static const struct opcode32 arm_opcodes[] =
2734{
2735 /* ARM instructions. */
823d2571
TG		 2736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2737 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
2738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2739 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
2740
2741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
2742 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
2743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
2744 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
2745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
2746 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
2748 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
2749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
2750 0x00800090, 0x0fa000f0,
2751 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
2753 0x00a00090, 0x0fa000f0,
2754 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 2755
105bde57 2756 /* V8.2 RAS extension instructions. */
4d1464f2 2757 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 2758 0xe320f010, 0xffffffff, "esb"},
2759
53c4b28b 2760 /* V8 instructions. */
823d2571
TG		 2761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2762 0x0320f005, 0x0fffffff, "sevl"},
f7dd2fb2
TC		 2763 /* Defined in V8 but is in NOP space so available to all arch. */
2764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
823d2571 2765 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
4ed7ed8d 2766 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 2767 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 2768 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 2769 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2771 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
2772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2773 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 2774 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2775 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 2776 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2777 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 2778 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2779 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 2780 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2781 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 2782 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2783 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 2784 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2785 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 2786 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2787 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 2788 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2789 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 2790 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2791 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 2792 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 2793 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 2794 /* CRC32 instructions. */
823d2571
TG		 2795 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2796 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
2797 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2798 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
2799 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2800 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
2801 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2802 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
2803 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2804 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
2805 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2806 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 2807
ddfded2f
MW		 2808 /* Privileged Access Never extension instructions. */
2809 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
2810 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
2811
90ec0d68 2812 /* Virtualization Extension instructions. */
823d2571
TG		 2813 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
2814 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 2815
eea54501 2816 /* Integer Divide Extension instructions. */
823d2571
TG		 2817 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
2818 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
2819 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
2820 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 2821
60e5ef9f 2822 /* MP Extension instructions. */
823d2571 2823 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 2824
c597cc3d
SD		 2825 /* Speculation Barriers. */
2826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
2827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
2828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
2829
62b3e311 2830 /* V7 instructions. */
823d2571
TG		 2831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
2832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
2833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
2834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
2835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
2836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
2837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a
AV		 2838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2839 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
62b3e311 2840
c19d1205 2841 /* ARM V6T2 instructions. */
823d2571
TG		 2842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2843 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
2844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2845 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
2846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2847 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2849 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
2850
2851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2852 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
2853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2854 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
2855
ff8646ee 2856 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 2857 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 2858 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2859 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
2860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2861 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
2862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2863 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 2864
f4c65163 2865 /* ARM Security extension instructions. */
823d2571
TG		 2866 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
2867 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 2868
8f06b2d8 2869 /* ARM V6K instructions. */
823d2571
TG		 2870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2871 0xf57ff01f, 0xffffffff, "clrex"},
2872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2873 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
2874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2875 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
2876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2877 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
2878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2879 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
2880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2881 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
2882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2883 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 2884
7fadb25d
SD		 2885 /* ARMv8.5-A instructions. */
2886 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
2887
8f06b2d8 2888 /* ARM V6K NOP hints. */
823d2571
TG		 2889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2890 0x0320f001, 0x0fffffff, "yield%c"},
2891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2892 0x0320f002, 0x0fffffff, "wfe%c"},
2893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2894 0x0320f003, 0x0fffffff, "wfi%c"},
2895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2896 0x0320f004, 0x0fffffff, "sev%c"},
2897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2898 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 2899
fe56b6ce 2900 /* ARM V6 instructions. */
823d2571
TG		 2901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2902 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
2903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2904 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
2905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2906 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
2907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2908 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
2909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2910 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
2911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2912 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
2913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2914 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
2915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2916 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
2917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2918 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
2919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2920 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
2921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2922 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
2923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2924 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
2925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2926 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
2927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2928 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
2929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2930 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
2931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2932 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
2933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2934 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
2935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2936 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
2937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2938 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
2939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2940 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
2941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2942 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
2943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2944 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
2945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2946 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
2947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2948 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
2949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2950 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
2951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2952 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
2953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2954 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
2955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2956 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
2957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2958 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
2959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2960 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
2961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2962 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
2963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2964 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
2965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2966 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
2967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2968 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
2969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2970 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
2971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2972 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
2973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2974 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
2975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2976 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
2977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2978 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
2979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2980 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
2981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2982 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
2983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2984 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
2985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2986 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
2987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2988 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
2989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2990 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
2991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2992 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
2993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2994 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
2995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2996 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
2997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2998 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
2999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3000 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3002 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3004 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3006 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3008 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3010 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3012 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3014 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3016 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3018 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3020 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3022 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3024 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3026 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3028 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3030 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3032 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3034 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3036 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3038 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3040 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3042 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3044 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3046 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3048 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3050 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3052 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3054 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3056 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3058 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3060 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3062 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3064 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3066 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3068 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3070 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3072 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3074 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3076 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3078 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3080 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3082 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3084 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3086 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3088 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
3089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3090 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3092 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3094 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3096 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3098 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
3099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3100 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
3101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3102 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
3103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3104 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
3105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3106 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3108 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3110 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3112 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3114 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
3115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3116 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3118 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3120 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
3121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3122 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
3123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3124 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
3125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3126 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
3127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3128 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
3129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3130 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
3131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3132 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
3133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3134 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
3135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3136 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3138 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
3139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3140 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
3141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3142 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
3143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3144 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 3145
8f06b2d8 3146 /* V5J instruction. */
823d2571
TG		 3147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
3148 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 3149
8f06b2d8 3150 /* V5 Instructions. */
823d2571
TG		 3151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3152 0xe1200070, 0xfff000f0,
3153 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
3154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3155 0xfa000000, 0xfe000000, "blx\t%B"},
3156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3157 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
3158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3159 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
3160
3161 /* V5E "El Segundo" Instructions. */
3162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3163 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
3164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3165 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
3166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3167 0xf450f000, 0xfc70f000, "pld\t%a"},
3168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3169 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3171 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3173 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3175 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
3176
3177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3178 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3180 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
3181
3182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3183 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3185 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3187 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3189 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3190
3191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3192 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
3193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3194 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
3195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3196 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
3197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3198 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
3199
3200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3201 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
3202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3203 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
3204
3205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3206 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
3207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3208 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
3209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3210 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
3211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3212 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 3213
8f06b2d8 3214 /* ARM Instructions. */
823d2571
TG		 3215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3216 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
3217
3218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3219 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
3220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3221 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
3222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3223 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
3224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3225 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
3226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3227 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
3228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3229 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
3230
3231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3232 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
3233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3234 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
3235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3236 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
3237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3238 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
3239
3240 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3241 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
3242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3243 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
3244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3245 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
3246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3247 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
3248
3249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3250 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
3251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3252 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
3253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3254 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
3255
3256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3257 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
3258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3259 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
3260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3261 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
3262
3263 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3264 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
3265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3266 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
3267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3268 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
3269
3270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3271 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3273 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3275 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
3276
3277 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3278 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
3279 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3280 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
3281 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3282 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
3283
3284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3285 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
3286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3287 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
3288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3289 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
3290
3291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3292 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3294 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3295 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3296 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
3297
3298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3299 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3301 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3302 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3303 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
3304
3305 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
3306 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
3307 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
3308 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
3309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
3310 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
3311
3312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3313 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
3314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3315 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
3316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3317 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
3318
3319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 3320 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 3321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 3322 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 3323 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 3324 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
823d2571
TG		 3325
3326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3327 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
3328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3329 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
3330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3331 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
3332
3333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3334 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
3335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3336 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
3337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3338 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
3339
3340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3341 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
3342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3343 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
3344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3345 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
3346
3347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3348 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
3349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3350 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
3351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3352 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
3353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3354 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
3355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3356 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
3357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3358 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
3359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3360 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
3361
3362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3363 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
3364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3365 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
3366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3367 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
3368
3369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3370 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
3371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3372 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
3373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3374 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
3375
3376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3377 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
3378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3379 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
3380
3381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3382 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
3383
3384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3385 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
3386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3387 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
3388
3389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3390 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3392 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3394 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3395 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3396 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3397 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3398 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3399 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3400 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3401 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3402 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3403 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3404 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3406 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3408 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3410 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3411 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3412 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3413 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3414 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3415 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3416 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3418 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3419 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3420 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3422 0x092d0000, 0x0fff0000, "push%c\t%m"},
3423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3424 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
3425 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3426 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3427
3428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3429 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3431 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3433 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3434 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3435 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3437 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3439 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3440 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3441 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3443 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3445 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3447 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3448 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3449 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3451 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3453 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3455 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3457 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3459 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3461 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
3462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3463 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
3464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3465 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3466
3467 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3468 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
3469 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3470 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 3471
3472 /* The rest. */
4ab90a7a
AV		 3473 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3474 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 3475 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3476 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3477 {ARM_FEATURE_CORE_LOW (0),
3478 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 3479};
3480
3481/* print_insn_thumb16 recognizes the following format control codes:
3482
3483 %S print Thumb register (bits 3..5 as high number if bit 6 set)
3484 %D print Thumb register (bits 0..2 as high number if bit 7 set)
3485 %<bitfield>I print bitfield as a signed decimal
3486 (top bit of range being the sign bit)
3487 %N print Thumb register mask (with LR)
3488 %O print Thumb register mask (with PC)
3489 %M print Thumb register mask
3490 %b print CZB's 6-bit unsigned branch destination
3491 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 3492 %c print the condition code
3493 %C print the condition code, or "s" if not conditional
3494 %x print warning if conditional an not at end of IT block"
3495 %X print "\t; unpredictable <IT:code>" if conditional
3496 %I print IT instruction suffix and operands
4547cb56 3497 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 3498 %<bitfield>r print bitfield as an ARM register
3499 %<bitfield>d print bitfield as a decimal
3500 %<bitfield>H print (bitfield * 2) as a decimal
3501 %<bitfield>W print (bitfield * 4) as a decimal
3502 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
3503 %<bitfield>B print Thumb branch destination (signed displacement)
3504 %<bitfield>c print bitfield as a condition code
3505 %<bitnum>'c print specified char iff bit is one
3506 %<bitnum>?ab print a if bit is one else print b. */
3507
3508static const struct opcode16 thumb_opcodes[] =
3509{
3510 /* Thumb instructions. */
3511
16a1fa25
TP		 3512 /* ARMv8-M Security Extensions instructions. */
3513 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
e207bc53 3514 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
16a1fa25 3515
53c4b28b 3516 /* ARM V8 instructions. */
823d2571
TG		 3517 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
3518 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
ddfded2f 3519 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
53c4b28b 3520
8f06b2d8 3521 /* ARM V6K no-argument instructions. */
823d2571
TG		 3522 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
3523 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
3524 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
3525 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
3526 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
3527 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 3528
3529 /* ARM V6T2 instructions. */
ff8646ee
TP		 3530 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3531 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
3532 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3533 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 3534 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 3535
3536 /* ARM V6. */
823d2571
TG		 3537 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
3538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
3539 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
3540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
3541 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
3542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
3543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
3544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
3545 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
3546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
3547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 3548
3549 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 3550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
3551 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 3552 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 3553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
3554 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 3555 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 3556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3557 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 3558 /* Format 4. */
823d2571
TG		 3559 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
3560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
3561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
3562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
3563 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
3564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
3565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
3566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
3567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
3568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
3569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
3570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
3571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
3572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
3573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
3574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 3575 /* format 13 */
823d2571
TG		 3576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
3577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 3578 /* format 5 */
823d2571
TG		 3579 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
3580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
3581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
3582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 3583 /* format 14 */
823d2571
TG		 3584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
3585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 3586 /* format 2 */
823d2571
TG		 3587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3588 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
3589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3590 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
3591 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3592 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
3593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3594 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 3595 /* format 8 */
823d2571
TG		 3596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3597 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
3598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3599 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
3600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3601 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 3602 /* format 7 */
823d2571
TG		 3603 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3604 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
3605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3606 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 3607 /* format 1 */
823d2571
TG		 3608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
3609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3610 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
3611 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
3612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 3613 /* format 3 */
823d2571
TG		 3614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
3615 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
3616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
3617 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 3618 /* format 6 */
823d2571
TG		 3619 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
3620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3621 0x4800, 0xF800,
3622 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 3623 /* format 9 */
823d2571
TG		 3624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3625 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
3626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3627 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
3628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3629 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
3630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3631 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 3632 /* format 10 */
823d2571
TG		 3633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3634 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
3635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3636 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 3637 /* format 11 */
823d2571
TG		 3638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3639 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
3640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3641 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 3642 /* format 12 */
823d2571
TG		 3643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3644 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
3645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3646 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 3647 /* format 15 */
823d2571
TG		 3648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
3649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 3650 /* format 17 */
823d2571 3651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 3652 /* format 16 */
823d2571
TG		 3653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
3654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
3655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 3656 /* format 18 */
823d2571 3657 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 3658
3659 /* The E800 .. FFFF range is unconditionally redirected to the
3660 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
3661 are processed via that table. Thus, we can never encounter a
3662 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 3663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
3664 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 3665};
3666
3667/* Thumb32 opcodes use the same table structure as the ARM opcodes.
3668 We adopt the convention that hw1 is the high 16 bits of .value and
3669 .mask, hw2 the low 16 bits.
3670
3671 print_insn_thumb32 recognizes the following format control codes:
3672
3673 %% %
3674
3675 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
3676 %M print a modified 12-bit immediate (same location)
3677 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
3678 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 3679 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 3680 %S print a possibly-shifted Rm
3681
32a94698 3682 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 3683 %a print the address of a plain load/store
3684 %w print the width and signedness of a core load/store
3685 %m print register mask for ldm/stm
4b5a202f 3686 %n print register mask for clrm
8f06b2d8
PB		 3687
3688 %E print the lsb and width fields of a bfc/bfi instruction
3689 %F print the lsb and width fields of a sbfx/ubfx instruction
e12437dc 3690 %G print a fallback offset for Branch Future instructions
e5d6e09e 3691 %W print an offset for BF instruction
1caf72a5 3692 %Y print an offset for BFL instruction
1889da70 3693 %Z print an offset for BFCSEL instruction
60f993ce
AV		 3694 %Q print an offset for Low Overhead Loop instructions
3695 %P print an offset for Low Overhead Loop end instructions
8f06b2d8
PB		 3696 %b print a conditional branch offset
3697 %B print an unconditional branch offset
3698 %s print the shift field of an SSAT instruction
3699 %R print the rotation field of an SXT instruction
62b3e311
PB		 3700 %U print barrier type.
3701 %P print address for pli instruction.
c22aaad1
PB		 3702 %c print the condition code
3703 %x print warning if conditional an not at end of IT block"
3704 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 3705
3706 %<bitfield>d print bitfield in decimal
f0fba320 3707 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 3708 %<bitfield>W print bitfield*4 in decimal
3709 %<bitfield>r print bitfield as an ARM register
dd5181d5 3710 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
f1c7f421 3711 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
8f06b2d8
PB		 3712 %<bitfield>c print bitfield as a condition code
3713
16980d0b
JB		 3714 %<bitfield>'c print specified char iff bitfield is all ones
3715 %<bitfield>`c print specified char iff bitfield is all zeroes
3716 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 3717
3718 With one exception at the bottom (done because BL and BLX(1) need
3719 to come dead last), this table was machine-sorted first in
3720 decreasing order of number of bits set in the mask, then in
3721 increasing numeric order of mask, then in increasing numeric order
3722 of opcode. This order is not the clearest for a human reader, but
3723 is guaranteed never to catch a special-case bit pattern with a more
3724 general mask, which is important, because this instruction encoding
3725 makes heavy use of special-case bit patterns. */
3726static const struct opcode32 thumb32_opcodes[] =
3727{
4b5a202f
AV		 3728 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
3729 instructions. */
60f993ce
AV		 3730 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3731 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
3732 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3733 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
3734 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3735 0xf02fc001, 0xfffff001, "le\t%P"},
3736 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3737 0xf00fc001, 0xfffff001, "le\tlr, %P"},
3738
4389b29a
AV		 3739 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3740 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
f1c7f421
AV		 3741 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3742 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
65d1bc05
AV		 3743 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3744 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
f1c7f421
AV		 3745 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3746 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
f6b2b12d
AV		 3747 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3748 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4389b29a 3749
4b5a202f
AV		 3750 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3751 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4389b29a 3752
16a1fa25
TP		 3753 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
3754 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4ed7ed8d
TP		 3755 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3756 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
3757 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3758 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
16a1fa25
TP		 3759 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3760 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
3761 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3762 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4ed7ed8d 3763
105bde57 3764 /* ARM V8.2 RAS extension instructions. */
4d1464f2 3765 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 3766 0xf3af8010, 0xffffffff, "esb"},
3767
53c4b28b 3768 /* V8 instructions. */
823d2571
TG		 3769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3770 0xf3af8005, 0xffffffff, "sevl%c.w"},
3771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3772 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
3773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3774 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
3775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3776 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
3777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3778 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
3779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3780 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
3781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3782 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
3783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3784 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
3785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3786 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
3787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3788 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3790 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3792 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
3793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3794 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3796 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3798 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3800 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 3801
dd5181d5 3802 /* CRC32 instructions. */
823d2571 3803 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 3804 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
823d2571 3805 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 3806 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
823d2571 3807 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 3808 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
823d2571 3809 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 3810 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
823d2571 3811 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 3812 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
823d2571 3813 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 3814 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
dd5181d5 3815
c597cc3d
SD		 3816 /* Speculation Barriers. */
3817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
3818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
3819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
3820
62b3e311 3821 /* V7 instructions. */
823d2571
TG		 3822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
3823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
3824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
3825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
3826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
3827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
3828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
3829 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
3830 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
3831 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
3832 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 3833
90ec0d68 3834 /* Virtualization Extension instructions. */
823d2571 3835 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 3836 /* We skip ERET as that is SUBS pc, lr, #0. */
3837
60e5ef9f 3838 /* MP Extension instructions. */
823d2571 3839 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 3840
f4c65163 3841 /* Security extension instructions. */
823d2571 3842 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 3843
7fadb25d
SD		 3844 /* ARMv8.5-A instructions. */
3845 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
3846
8f06b2d8 3847 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 3848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
3849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
3850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
3851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
3852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
3853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3854 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
3855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
3856
ff8646ee 3857 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3858 0xf3bf8f2f, 0xffffffff, "clrex%c"},
3859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3860 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
3861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3862 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
3863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3864 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
3865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3866 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
3867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3868 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
3869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3870 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
3871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3872 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
3873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3874 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
3875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3876 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
3877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3878 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
3879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3880 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
3881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3882 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
3883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3884 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 3885 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 3886 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 3887 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3888 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
3889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3890 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
3891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3892 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
3893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3894 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
3895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3896 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
3897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3898 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
3899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3900 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
3901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3902 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
3903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3904 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 3905 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3906 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
3907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3908 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
3909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3910 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
3911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3912 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
3913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3914 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
3915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3916 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
3917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3918 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
3919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3920 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
3921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3922 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
3923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3924 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
3925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3926 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
3927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3928 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
3929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3930 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
3931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3932 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
3933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3934 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
3935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3936 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
3937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3938 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
3939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3940 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
3941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3942 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
3943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3944 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
3945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3946 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
3947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3948 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
3949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3950 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
3951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3952 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
3953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3954 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
3955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3956 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
3957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3958 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
3959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3960 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
3961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3962 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
3963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3964 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
3965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3966 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
3967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3968 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
3969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3970 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
3971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3972 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
3973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3974 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
3975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3976 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
3977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3978 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
3979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3980 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
3981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3982 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
3983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3984 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
3985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3986 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
3987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3988 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
3989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3990 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
3991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3992 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
3993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3994 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
3995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3996 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
3997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3998 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
3999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4000 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4002 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4004 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4006 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4008 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4010 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4012 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 4013 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4014 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 4016 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 4017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4018 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4020 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4022 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4024 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4026 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4028 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4030 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4032 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4034 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4036 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4038 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4040 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4042 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4044 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4046 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4048 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4050 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4052 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4054 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4056 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4058 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4060 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4062 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4064 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4066 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4068 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4070 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4072 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4074 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4076 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4078 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4080 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 4081 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4082 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
4083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4084 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
4085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4086 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
4087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4088 0xf810f000, 0xff70f000, "pld%c\t%a"},
4089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4090 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4092 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4094 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4096 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4098 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4100 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4102 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4104 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
4105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4106 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
4107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4108 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
4109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4110 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
4111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4112 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
4113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4114 0xfb100000, 0xfff000c0,
4115 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4117 0xfbc00080, 0xfff000c0,
4118 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
4119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4120 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
4121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4122 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
4123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 4124 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 4125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4126 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
4127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4128 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 4129 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4130 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
4131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4132 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 4133 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4134 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
4135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4136 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
4137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4138 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
4139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4140 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
4141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4142 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
4143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4144 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
4145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4146 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
4147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4148 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
4149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4150 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
4151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4152 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
4153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4154 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 4155 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4156 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
4157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4158 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
4159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4160 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
4161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4162 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
4163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4164 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
4165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4166 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
4167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4168 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
4169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4170 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
4171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4172 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
4173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4174 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
4175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4176 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
4177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4178 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
4179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4180 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
4181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4182 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
4183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4184 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
4185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4186 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
4187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4188 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
4189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4190 0xe9400000, 0xff500000,
4191 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4193 0xe9500000, 0xff500000,
4194 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4196 0xe8600000, 0xff700000,
4197 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4199 0xe8700000, 0xff700000,
4200 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4202 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
4203 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4204 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 4205
4206 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 4207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4208 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
4209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4210 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
4211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4212 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
4213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4214 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 4215
8f06b2d8 4216 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 4217 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4218 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
4219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4220 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 4221
4222 /* Fallback. */
823d2571
TG		 4223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4224 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4225 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 4226};
ff4a8d2b 4227
8f06b2d8
PB		 4228static const char *const arm_conditional[] =
4229{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 4230 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 4231
4232static const char *const arm_fp_const[] =
4233{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
4234
4235static const char *const arm_shift[] =
4236{"lsl", "lsr", "asr", "ror"};
4237
4238typedef struct
4239{
4240 const char *name;
4241 const char *description;
4242 const char *reg_names[16];
4243}
4244arm_regname;
4245
4246static const arm_regname regnames[] =
4247{
65b48a81 4248 { "reg-names-raw", N_("Select raw register names"),
8f06b2d8 4249 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
65b48a81 4250 { "reg-names-gcc", N_("Select register names used by GCC"),
8f06b2d8 4251 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 4252 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
8f06b2d8 4253 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65b48a81
PB		 4254 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
4255 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
4256 { "reg-names-apcs", N_("Select register names used in the APCS"),
8f06b2d8 4257 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 4258 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
8f06b2d8 4259 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
65b48a81
PB		 4260 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
4261 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
8f06b2d8
PB		 4262};
4263
4264static const char *const iwmmxt_wwnames[] =
4265{"b", "h", "w", "d"};
4266
4267static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 4268{"b", "bus", "bc", "bss",
4269 "h", "hus", "hc", "hss",
4270 "w", "wus", "wc", "wss",
4271 "d", "dus", "dc", "dss"
8f06b2d8
PB		 4272};
4273
4274static const char *const iwmmxt_regnames[] =
4275{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
4276 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
4277};
4278
4279static const char *const iwmmxt_cregnames[] =
4280{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
4281 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
4282};
4283
143275ea
AV		 4284static const char *const vec_condnames[] =
4285{ "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
4286};
4287
4288static const char *const mve_predicatenames[] =
4289{ "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
4290 "eee", "ee", "eet", "e", "ett", "et", "ete"
4291};
4292
4293/* Names for 2-bit size field for mve vector isntructions. */
4294static const char *const mve_vec_sizename[] =
4295 { "8", "16", "32", "64"};
4296
4297/* Indicates whether we are processing a then predicate,
4298 else predicate or none at all. */
4299enum vpt_pred_state
4300{
4301 PRED_NONE,
4302 PRED_THEN,
4303 PRED_ELSE
4304};
4305
4306/* Information used to process a vpt block and subsequent instructions. */
4307struct vpt_block
4308{
4309 /* Are we in a vpt block. */
4310 bfd_boolean in_vpt_block;
4311
4312 /* Next predicate state if in vpt block. */
4313 enum vpt_pred_state next_pred_state;
4314
4315 /* Mask from vpt/vpst instruction. */
4316 long predicate_mask;
4317
4318 /* Instruction number in vpt block. */
4319 long current_insn_num;
4320
4321 /* Number of instructions in vpt block.. */
4322 long num_pred_insn;
4323};
4324
4325static struct vpt_block vpt_block_state =
4326{
4327 FALSE,
4328 PRED_NONE,
4329 0,
4330 0,
4331 0
4332};
4333
8f06b2d8
PB		 4334/* Default to GCC register name set. */
4335static unsigned int regname_selected = 1;
4336
65b48a81 4337#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
8f06b2d8
PB		 4338#define arm_regnames regnames[regname_selected].reg_names
4339
4340static bfd_boolean force_thumb = FALSE;
4341
c22aaad1
PB		 4342/* Current IT instruction state. This contains the same state as the IT
4343 bits in the CPSR. */
4344static unsigned int ifthen_state;
4345/* IT state for the next instruction. */
4346static unsigned int ifthen_next_state;
4347/* The address of the insn for which the IT state is valid. */
4348static bfd_vma ifthen_address;
4349#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 4350/* Indicates that the current Conditional state is unconditional or outside
4351 an IT block. */
4352#define COND_UNCOND 16
c22aaad1 4353
8f06b2d8
PB		 4354\f
4355/* Functions. */
143275ea
AV		 4356/* Extract the predicate mask for a VPT or VPST instruction.
4357 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
4358
4359static long
4360mve_extract_pred_mask (long given)
4361{
4362 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
4363}
4364
4365/* Return the number of instructions in a MVE predicate block. */
4366static long
4367num_instructions_vpt_block (long given)
4368{
4369 long mask = mve_extract_pred_mask (given);
4370 if (mask == 0)
4371 return 0;
4372
4373 if (mask == 8)
4374 return 1;
4375
4376 if ((mask & 7) == 4)
4377 return 2;
4378
4379 if ((mask & 3) == 2)
4380 return 3;
4381
4382 if ((mask & 1) == 1)
4383 return 4;
4384
4385 return 0;
4386}
4387
4388static void
4389mark_outside_vpt_block (void)
4390{
4391 vpt_block_state.in_vpt_block = FALSE;
4392 vpt_block_state.next_pred_state = PRED_NONE;
4393 vpt_block_state.predicate_mask = 0;
4394 vpt_block_state.current_insn_num = 0;
4395 vpt_block_state.num_pred_insn = 0;
4396}
4397
4398static void
4399mark_inside_vpt_block (long given)
4400{
4401 vpt_block_state.in_vpt_block = TRUE;
4402 vpt_block_state.next_pred_state = PRED_THEN;
4403 vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
4404 vpt_block_state.current_insn_num = 0;
4405 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
4406 assert (vpt_block_state.num_pred_insn >= 1);
4407}
4408
4409static enum vpt_pred_state
4410invert_next_predicate_state (enum vpt_pred_state astate)
4411{
4412 if (astate == PRED_THEN)
4413 return PRED_ELSE;
4414 else if (astate == PRED_ELSE)
4415 return PRED_THEN;
4416 else
4417 return PRED_NONE;
4418}
4419
4420static enum vpt_pred_state
4421update_next_predicate_state (void)
4422{
4423 long pred_mask = vpt_block_state.predicate_mask;
4424 long mask_for_insn = 0;
4425
4426 switch (vpt_block_state.current_insn_num)
4427 {
4428 case 1:
4429 mask_for_insn = 8;
4430 break;
4431
4432 case 2:
4433 mask_for_insn = 4;
4434 break;
4435
4436 case 3:
4437 mask_for_insn = 2;
4438 break;
4439
4440 case 4:
4441 return PRED_NONE;
4442 }
4443
4444 if (pred_mask & mask_for_insn)
4445 return invert_next_predicate_state (vpt_block_state.next_pred_state);
4446 else
4447 return vpt_block_state.next_pred_state;
4448}
4449
4450static void
4451update_vpt_block_state (void)
4452{
4453 vpt_block_state.current_insn_num++;
4454 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
4455 {
4456 /* No more instructions to process in vpt block. */
4457 mark_outside_vpt_block ();
4458 return;
4459 }
4460
4461 vpt_block_state.next_pred_state = update_next_predicate_state ();
4462}
8f06b2d8 4463
16980d0b
JB		 4464/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
4465 Returns pointer to following character of the format string and
4466 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 4467 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 4468
4469static const char *
fe56b6ce
NC		 4470arm_decode_bitfield (const char *ptr,
4471 unsigned long insn,
4472 unsigned long *valuep,
4473 int *widthp)
16980d0b
JB		 4474{
4475 unsigned long value = 0;
4476 int width = 0;
43e65147
L		 4477
4478 do
16980d0b
JB		 4479 {
4480 int start, end;
4481 int bits;
4482
4483 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
4484 start = start * 10 + *ptr - '0';
4485 if (*ptr == '-')
4486 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
4487 end = end * 10 + *ptr - '0';
4488 else
4489 end = start;
4490 bits = end - start;
4491 if (bits < 0)
4492 abort ();
4493 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
4494 width += bits + 1;
4495 }
4496 while (*ptr++ == ',');
4497 *valuep = value;
4498 if (widthp)
4499 *widthp = width;
4500 return ptr - 1;
4501}
4502
8f06b2d8 4503static void
37b37b2d 4504arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 4505 bfd_boolean print_shift)
8f06b2d8
PB		 4506{
4507 func (stream, "%s", arm_regnames[given & 0xf]);
4508
4509 if ((given & 0xff0) != 0)
4510 {
4511 if ((given & 0x10) == 0)
4512 {
4513 int amount = (given & 0xf80) >> 7;
4514 int shift = (given & 0x60) >> 5;
4515
4516 if (amount == 0)
4517 {
4518 if (shift == 3)
4519 {
4520 func (stream, ", rrx");
4521 return;
4522 }
4523
4524 amount = 32;
4525 }
4526
37b37b2d
RE		 4527 if (print_shift)
4528 func (stream, ", %s #%d", arm_shift[shift], amount);
4529 else
4530 func (stream, ", #%d", amount);
8f06b2d8 4531 }
74bdfecf 4532 else if ((given & 0x80) == 0x80)
aefd8a40 4533 func (stream, "\t; <illegal shifter operand>");
37b37b2d 4534 else if (print_shift)
8f06b2d8
PB		 4535 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
4536 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 4537 else
4538 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 4539 }
4540}
4541
73cd51e5
AV		 4542/* Return TRUE if the MATCHED_INSN can be inside an IT block. */
4543
4544static bfd_boolean
4545is_mve_okay_in_it (enum mve_instructions matched_insn)
4546{
c507f10b
AV		 4547 switch (matched_insn)
4548 {
4549 case MVE_VMOV_GP_TO_VEC_LANE:
4550 case MVE_VMOV2_VEC_LANE_TO_GP:
4551 case MVE_VMOV2_GP_TO_VEC_LANE:
4552 case MVE_VMOV_VEC_LANE_TO_GP:
4553 return TRUE;
4554 default:
4555 return FALSE;
4556 }
73cd51e5
AV		 4557}
4558
4559static bfd_boolean
4560is_mve_architecture (struct disassemble_info *info)
4561{
4562 struct arm_private_data *private_data = info->private_data;
4563 arm_feature_set allowed_arches = private_data->features;
4564
4565 arm_feature_set arm_ext_v8_1m_main
4566 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
4567
4568 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
4569 && !ARM_CPU_IS_ANY (allowed_arches))
4570 return TRUE;
4571 else
4572 return FALSE;
4573}
4574
143275ea
AV		 4575static bfd_boolean
4576is_vpt_instruction (long given)
4577{
4578
4579 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
4580 if ((given & 0x0040e000) == 0)
4581 return FALSE;
4582
4583 /* VPT floating point T1 variant. */
4584 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
4585 /* VPT floating point T2 variant. */
4586 || ((given & 0xefb10f50) == 0xee310f40)
4587 /* VPT vector T1 variant. */
4588 || ((given & 0xff811f51) == 0xfe010f00)
4589 /* VPT vector T2 variant. */
4590 || ((given & 0xff811f51) == 0xfe010f01
4591 && ((given & 0x300000) != 0x300000))
4592 /* VPT vector T3 variant. */
4593 || ((given & 0xff811f50) == 0xfe011f00)
4594 /* VPT vector T4 variant. */
4595 || ((given & 0xff811f70) == 0xfe010f40)
4596 /* VPT vector T5 variant. */
4597 || ((given & 0xff811f70) == 0xfe010f60)
4598 /* VPT vector T6 variant. */
4599 || ((given & 0xff811f50) == 0xfe011f40)
4600 /* VPST vector T variant. */
4601 || ((given & 0xffbf1fff) == 0xfe310f4d))
4602 return TRUE;
4603 else
4604 return FALSE;
4605}
4606
73cd51e5
AV		 4607/* Decode a bitfield from opcode GIVEN, with starting bitfield = START
4608 and ending bitfield = END. END must be greater than START. */
4609
4610static unsigned long
4611arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
4612{
4613 int bits = end - start;
4614
4615 if (bits < 0)
4616 abort ();
4617
4618 return ((given >> start) & ((2ul << bits) - 1));
4619}
4620
4621/* Decode a bitfield from opcode GIVEN, with multiple bitfields:
4622 START:END and START2:END2. END/END2 must be greater than
4623 START/START2. */
4624
4625static unsigned long
4626arm_decode_field_multiple (unsigned long given, unsigned int start,
4627 unsigned int end, unsigned int start2,
4628 unsigned int end2)
4629{
4630 int bits = end - start;
4631 int bits2 = end2 - start2;
4632 unsigned long value = 0;
4633 int width = 0;
4634
4635 if (bits2 < 0)
4636 abort ();
4637
4638 value = arm_decode_field (given, start, end);
4639 width += bits + 1;
4640
4641 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
4642 return value;
4643}
4644
4645/* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
4646 This helps us decode instructions that change mnemonic depending on specific
4647 operand values/encodings. */
4648
4649static bfd_boolean
4650is_mve_encoding_conflict (unsigned long given,
4651 enum mve_instructions matched_insn)
4652{
143275ea
AV		 4653 switch (matched_insn)
4654 {
4655 case MVE_VPST:
4656 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4657 return TRUE;
4658 else
4659 return FALSE;
4660
4661 case MVE_VPT_FP_T1:
4662 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4663 return TRUE;
4664 if ((arm_decode_field (given, 12, 12) == 0)
4665 && (arm_decode_field (given, 0, 0) == 1))
4666 return TRUE;
4667 return FALSE;
4668
4669 case MVE_VPT_FP_T2:
4670 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4671 return TRUE;
4672 if (arm_decode_field (given, 0, 3) == 0xd)
4673 return TRUE;
4674 return FALSE;
4675
4676 case MVE_VPT_VEC_T1:
4677 case MVE_VPT_VEC_T2:
4678 case MVE_VPT_VEC_T3:
4679 case MVE_VPT_VEC_T4:
4680 case MVE_VPT_VEC_T5:
4681 case MVE_VPT_VEC_T6:
4682 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4683 return TRUE;
4684 if (arm_decode_field (given, 20, 21) == 3)
4685 return TRUE;
4686 return FALSE;
4687
4688 case MVE_VCMP_FP_T1:
4689 if ((arm_decode_field (given, 12, 12) == 0)
4690 && (arm_decode_field (given, 0, 0) == 1))
4691 return TRUE;
4692 else
4693 return FALSE;
4694
4695 case MVE_VCMP_FP_T2:
4696 if (arm_decode_field (given, 0, 3) == 0xd)
4697 return TRUE;
4698 else
4699 return FALSE;
4700
1c8f2df8
AV		 4701 case MVE_VDDUP:
4702 case MVE_VIDUP:
d3b63143
AV		 4703 case MVE_VQRDMLADH:
4704 case MVE_VQDMLAH:
4705 case MVE_VQRDMLAH:
4706 case MVE_VQDMLASH:
4707 case MVE_VQRDMLASH:
4708 case MVE_VQDMLSDH:
4709 case MVE_VQRDMLSDH:
4710 case MVE_VQDMULH_T3:
4711 case MVE_VQRDMULH_T4:
4712 case MVE_VQDMLADH:
4713 case MVE_VMLAS:
14925797 4714 case MVE_VMULL_INT:
9743db03
AV		 4715 case MVE_VHADD_T2:
4716 case MVE_VHSUB_T2:
143275ea
AV		 4717 case MVE_VCMP_VEC_T1:
4718 case MVE_VCMP_VEC_T2:
4719 case MVE_VCMP_VEC_T3:
4720 case MVE_VCMP_VEC_T4:
4721 case MVE_VCMP_VEC_T5:
4722 case MVE_VCMP_VEC_T6:
4723 if (arm_decode_field (given, 20, 21) == 3)
4724 return TRUE;
4725 else
4726 return FALSE;
4727
04d54ace
AV		 4728 case MVE_VLD2:
4729 case MVE_VLD4:
4730 case MVE_VST2:
4731 case MVE_VST4:
4732 if (arm_decode_field (given, 7, 8) == 3)
4733 return TRUE;
4734 else
4735 return FALSE;
4736
aef6d006
AV		 4737 case MVE_VSTRB_T1:
4738 case MVE_VSTRH_T2:
4739 if ((arm_decode_field (given, 24, 24) == 0)
4740 && (arm_decode_field (given, 21, 21) == 0))
4741 {
4742 return TRUE;
4743 }
4744 else if ((arm_decode_field (given, 7, 8) == 3))
4745 return TRUE;
4746 else
4747 return FALSE;
4748
4749 case MVE_VSTRB_T5:
4750 case MVE_VSTRH_T6:
4751 case MVE_VSTRW_T7:
4752 if ((arm_decode_field (given, 24, 24) == 0)
4753 && (arm_decode_field (given, 21, 21) == 0))
4754 {
4755 return TRUE;
4756 }
4757 else
4758 return FALSE;
4759
bf0b396d
AV		 4760 case MVE_VCVT_FP_FIX_VEC:
4761 return (arm_decode_field (given, 16, 21) & 0x38) == 0;
4762
c507f10b
AV		 4763 case MVE_VBIC_IMM:
4764 case MVE_VORR_IMM:
4765 {
4766 unsigned long cmode = arm_decode_field (given, 8, 11);
4767
4768 if ((cmode & 1) == 0)
4769 return TRUE;
4770 else if ((cmode & 0xc) == 0xc)
4771 return TRUE;
4772 else
4773 return FALSE;
4774 }
4775
4776 case MVE_VMVN_IMM:
4777 {
4778 unsigned long cmode = arm_decode_field (given, 8, 11);
4779
4780 if ((cmode & 9) == 1)
4781 return TRUE;
4782 else if ((cmode & 5) == 1)
4783 return TRUE;
4784 else if ((cmode & 0xe) == 0xe)
4785 return TRUE;
4786 else
4787 return FALSE;
4788 }
4789
4790 case MVE_VMOV_IMM_TO_VEC:
4791 if ((arm_decode_field (given, 5, 5) == 1)
4792 && (arm_decode_field (given, 8, 11) != 0xe))
4793 return TRUE;
4794 else
4795 return FALSE;
4796
14925797
AV		 4797 case MVE_VMOVL:
4798 {
4799 unsigned long size = arm_decode_field (given, 19, 20);
4800 if ((size == 0) || (size == 3))
4801 return TRUE;
4802 else
4803 return FALSE;
4804 }
4805
d3b63143 4806 case MVE_VADDV:
14925797
AV		 4807 case MVE_VMOVN:
4808 case MVE_VQMOVUN:
4809 case MVE_VQMOVN:
4810 if (arm_decode_field (given, 18, 19) == 3)
4811 return TRUE;
4812 else
4813 return FALSE;
4814
d3b63143
AV		 4815 case MVE_VMLSLDAV:
4816 case MVE_VRMLSLDAVH:
4817 case MVE_VMLALDAV:
4818 case MVE_VADDLV:
4819 if (arm_decode_field (given, 20, 22) == 7)
4820 return TRUE;
4821 else
4822 return FALSE;
4823
4824 case MVE_VRMLALDAVH:
4825 if ((arm_decode_field (given, 20, 22) & 6) == 6)
4826 return TRUE;
4827 else
4828 return FALSE;
4829
1c8f2df8
AV		 4830 case MVE_VDWDUP:
4831 case MVE_VIWDUP:
4832 if ((arm_decode_field (given, 20, 21) == 3)
4833 || (arm_decode_field (given, 1, 3) == 7))
4834 return TRUE;
4835 else
4836 return FALSE;
4837
143275ea
AV		 4838 default:
4839 return FALSE;
4840
4841 }
73cd51e5
AV		 4842}
4843
aef6d006
AV		 4844static void
4845print_mve_vld_str_addr (struct disassemble_info *info,
4846 unsigned long given,
4847 enum mve_instructions matched_insn)
4848{
4849 void *stream = info->stream;
4850 fprintf_ftype func = info->fprintf_func;
4851
4852 unsigned long p, w, gpr, imm, add, mod_imm;
4853
4854 imm = arm_decode_field (given, 0, 6);
4855 mod_imm = imm;
4856
4857 switch (matched_insn)
4858 {
4859 case MVE_VLDRB_T1:
4860 case MVE_VSTRB_T1:
4861 gpr = arm_decode_field (given, 16, 18);
4862 break;
4863
4864 case MVE_VLDRH_T2:
4865 case MVE_VSTRH_T2:
4866 gpr = arm_decode_field (given, 16, 18);
4867 mod_imm = imm << 1;
4868 break;
4869
4870 case MVE_VLDRH_T6:
4871 case MVE_VSTRH_T6:
4872 gpr = arm_decode_field (given, 16, 19);
4873 mod_imm = imm << 1;
4874 break;
4875
4876 case MVE_VLDRW_T7:
4877 case MVE_VSTRW_T7:
4878 gpr = arm_decode_field (given, 16, 19);
4879 mod_imm = imm << 2;
4880 break;
4881
4882 case MVE_VLDRB_T5:
4883 case MVE_VSTRB_T5:
4884 gpr = arm_decode_field (given, 16, 19);
4885 break;
4886
4887 default:
4888 return;
4889 }
4890
4891 p = arm_decode_field (given, 24, 24);
4892 w = arm_decode_field (given, 21, 21);
4893
4894 add = arm_decode_field (given, 23, 23);
4895
4896 char * add_sub;
4897
4898 /* Don't print anything for '+' as it is implied. */
4899 if (add == 1)
4900 add_sub = "";
4901 else
4902 add_sub = "-";
4903
4904 if (p == 1)
4905 {
4906 /* Offset mode. */
4907 if (w == 0)
4908 func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm);
4909 /* Pre-indexed mode. */
4910 else
4911 func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm);
4912 }
4913 else if ((p == 0) && (w == 1))
4914 /* Post-index mode. */
4915 func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm);
4916}
4917
73cd51e5
AV		 4918/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
4919 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
4920 this encoding is undefined. */
4921
4922static bfd_boolean
4923is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
4924 enum mve_undefined *undefined_code)
4925{
4926 *undefined_code = UNDEF_NONE;
4927
9743db03
AV		 4928 switch (matched_insn)
4929 {
4930 case MVE_VDUP:
4931 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
4932 {
4933 *undefined_code = UNDEF_SIZE_3;
4934 return TRUE;
4935 }
4936 else
4937 return FALSE;
4938
d3b63143
AV		 4939 case MVE_VQDMULH_T1:
4940 case MVE_VQRDMULH_T2:
9743db03
AV		 4941 case MVE_VRHADD:
4942 case MVE_VHADD_T1:
4943 case MVE_VHSUB_T1:
4944 if (arm_decode_field (given, 20, 21) == 3)
4945 {
4946 *undefined_code = UNDEF_SIZE_3;
4947 return TRUE;
4948 }
4949 else
4950 return FALSE;
4951
aef6d006
AV		 4952 case MVE_VLDRB_T1:
4953 if (arm_decode_field (given, 7, 8) == 3)
4954 {
4955 *undefined_code = UNDEF_SIZE_3;
4956 return TRUE;
4957 }
4958 else
4959 return FALSE;
4960
4961 case MVE_VLDRH_T2:
4962 if (arm_decode_field (given, 7, 8) <= 1)
4963 {
4964 *undefined_code = UNDEF_SIZE_LE_1;
4965 return TRUE;
4966 }
4967 else
4968 return FALSE;
4969
4970 case MVE_VSTRB_T1:
4971 if ((arm_decode_field (given, 7, 8) == 0))
4972 {
4973 *undefined_code = UNDEF_SIZE_0;
4974 return TRUE;
4975 }
4976 else
4977 return FALSE;
4978
4979 case MVE_VSTRH_T2:
4980 if ((arm_decode_field (given, 7, 8) <= 1))
4981 {
4982 *undefined_code = UNDEF_SIZE_LE_1;
4983 return TRUE;
4984 }
4985 else
4986 return FALSE;
4987
ef1576a1
AV		 4988 case MVE_VLDRB_GATHER_T1:
4989 if (arm_decode_field (given, 7, 8) == 3)
4990 {
4991 *undefined_code = UNDEF_SIZE_3;
4992 return TRUE;
4993 }
4994 else if ((arm_decode_field (given, 28, 28) == 0)
4995 && (arm_decode_field (given, 7, 8) == 0))
4996 {
4997 *undefined_code = UNDEF_NOT_UNS_SIZE_0;
4998 return TRUE;
4999 }
5000 else
5001 return FALSE;
5002
5003 case MVE_VLDRH_GATHER_T2:
5004 if (arm_decode_field (given, 7, 8) == 3)
5005 {
5006 *undefined_code = UNDEF_SIZE_3;
5007 return TRUE;
5008 }
5009 else if ((arm_decode_field (given, 28, 28) == 0)
5010 && (arm_decode_field (given, 7, 8) == 1))
5011 {
5012 *undefined_code = UNDEF_NOT_UNS_SIZE_1;
5013 return TRUE;
5014 }
5015 else if (arm_decode_field (given, 7, 8) == 0)
5016 {
5017 *undefined_code = UNDEF_SIZE_0;
5018 return TRUE;
5019 }
5020 else
5021 return FALSE;
5022
5023 case MVE_VLDRW_GATHER_T3:
5024 if (arm_decode_field (given, 7, 8) != 2)
5025 {
5026 *undefined_code = UNDEF_SIZE_NOT_2;
5027 return TRUE;
5028 }
5029 else if (arm_decode_field (given, 28, 28) == 0)
5030 {
5031 *undefined_code = UNDEF_NOT_UNSIGNED;
5032 return TRUE;
5033 }
5034 else
5035 return FALSE;
5036
5037 case MVE_VLDRD_GATHER_T4:
5038 if (arm_decode_field (given, 7, 8) != 3)
5039 {
5040 *undefined_code = UNDEF_SIZE_NOT_3;
5041 return TRUE;
5042 }
5043 else if (arm_decode_field (given, 28, 28) == 0)
5044 {
5045 *undefined_code = UNDEF_NOT_UNSIGNED;
5046 return TRUE;
5047 }
5048 else
5049 return FALSE;
5050
5051 case MVE_VSTRB_SCATTER_T1:
5052 if (arm_decode_field (given, 7, 8) == 3)
5053 {
5054 *undefined_code = UNDEF_SIZE_3;
5055 return TRUE;
5056 }
5057 else
5058 return FALSE;
5059
5060 case MVE_VSTRH_SCATTER_T2:
5061 {
5062 unsigned long size = arm_decode_field (given, 7, 8);
5063 if (size == 3)
5064 {
5065 *undefined_code = UNDEF_SIZE_3;
5066 return TRUE;
5067 }
5068 else if (size == 0)
5069 {
5070 *undefined_code = UNDEF_SIZE_0;
5071 return TRUE;
5072 }
5073 else
5074 return FALSE;
5075 }
5076
5077 case MVE_VSTRW_SCATTER_T3:
5078 if (arm_decode_field (given, 7, 8) != 2)
5079 {
5080 *undefined_code = UNDEF_SIZE_NOT_2;
5081 return TRUE;
5082 }
5083 else
5084 return FALSE;
5085
5086 case MVE_VSTRD_SCATTER_T4:
5087 if (arm_decode_field (given, 7, 8) != 3)
5088 {
5089 *undefined_code = UNDEF_SIZE_NOT_3;
5090 return TRUE;
5091 }
5092 else
5093 return FALSE;
5094
bf0b396d
AV		 5095 case MVE_VCVT_FP_FIX_VEC:
5096 {
5097 unsigned long imm6 = arm_decode_field (given, 16, 21);
5098 if ((imm6 & 0x20) == 0)
5099 {
5100 *undefined_code = UNDEF_VCVT_IMM6;
5101 return TRUE;
5102 }
5103
5104 if ((arm_decode_field (given, 9, 9) == 0)
5105 && ((imm6 & 0x30) == 0x20))
5106 {
5107 *undefined_code = UNDEF_VCVT_FSI_IMM6;
5108 return TRUE;
5109 }
5110
5111 return FALSE;
5112 }
5113
5114 case MVE_VCVT_BETWEEN_FP_INT:
5115 case MVE_VCVT_FROM_FP_TO_INT:
5116 {
5117 unsigned long size = arm_decode_field (given, 18, 19);
5118 if (size == 0)
5119 {
5120 *undefined_code = UNDEF_SIZE_0;
5121 return TRUE;
5122 }
5123 else if (size == 3)
5124 {
5125 *undefined_code = UNDEF_SIZE_3;
5126 return TRUE;
5127 }
5128 else
5129 return FALSE;
5130 }
5131
c507f10b
AV		 5132 case MVE_VMOV_VEC_LANE_TO_GP:
5133 {
5134 unsigned long op1 = arm_decode_field (given, 21, 22);
5135 unsigned long op2 = arm_decode_field (given, 5, 6);
5136 unsigned long u = arm_decode_field (given, 23, 23);
5137
5138 if ((op2 == 0) && (u == 1))
5139 {
5140 if ((op1 == 0) || (op1 == 1))
5141 {
5142 *undefined_code = UNDEF_BAD_U_OP1_OP2;
5143 return TRUE;
5144 }
5145 else
5146 return FALSE;
5147 }
5148 else if (op2 == 2)
5149 {
5150 if ((op1 == 0) || (op1 == 1))
5151 {
5152 *undefined_code = UNDEF_BAD_OP1_OP2;
5153 return TRUE;
5154 }
5155 else
5156 return FALSE;
5157 }
5158
5159 return FALSE;
5160 }
5161
5162 case MVE_VMOV_GP_TO_VEC_LANE:
5163 if (arm_decode_field (given, 5, 6) == 2)
5164 {
5165 unsigned long op1 = arm_decode_field (given, 21, 22);
5166 if ((op1 == 0) || (op1 == 1))
5167 {
5168 *undefined_code = UNDEF_BAD_OP1_OP2;
5169 return TRUE;
5170 }
5171 else
5172 return FALSE;
5173 }
5174 else
5175 return FALSE;
5176
5177 case MVE_VMOV_IMM_TO_VEC:
5178 if (arm_decode_field (given, 5, 5) == 0)
5179 {
5180 unsigned long cmode = arm_decode_field (given, 8, 11);
5181
5182 if (((cmode & 9) == 1) || ((cmode & 5) == 1))
5183 {
5184 *undefined_code = UNDEF_OP_0_BAD_CMODE;
5185 return TRUE;
5186 }
5187 else
5188 return FALSE;
5189 }
5190 else
5191 return FALSE;
5192
14925797
AV		 5193 case MVE_VMOVN:
5194 if (arm_decode_field (given, 18, 19) == 2)
5195 {
5196 *undefined_code = UNDEF_SIZE_2;
5197 return TRUE;
5198 }
5199 else
5200 return FALSE;
5201
d3b63143
AV		 5202 case MVE_VRMLALDAVH:
5203 case MVE_VMLADAV_T1:
5204 case MVE_VMLADAV_T2:
5205 case MVE_VMLALDAV:
5206 if ((arm_decode_field (given, 28, 28) == 1)
5207 && (arm_decode_field (given, 12, 12) == 1))
5208 {
5209 *undefined_code = UNDEF_XCHG_UNS;
5210 return TRUE;
5211 }
5212 else
5213 return FALSE;
5214
9743db03
AV		 5215 default:
5216 return FALSE;
5217 }
73cd51e5
AV		 5218}
5219
5220/* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
5221 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
5222 why this encoding is unpredictable. */
5223
5224static bfd_boolean
5225is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
5226 enum mve_unpredictable *unpredictable_code)
5227{
5228 *unpredictable_code = UNPRED_NONE;
5229
143275ea
AV		 5230 switch (matched_insn)
5231 {
5232 case MVE_VCMP_FP_T2:
5233 case MVE_VPT_FP_T2:
5234 if ((arm_decode_field (given, 12, 12) == 0)
5235 && (arm_decode_field (given, 5, 5) == 1))
5236 {
5237 *unpredictable_code = UNPRED_FCA_0_FCB_1;
5238 return TRUE;
5239 }
5240 else
5241 return FALSE;
73cd51e5 5242
143275ea
AV		 5243 case MVE_VPT_VEC_T4:
5244 case MVE_VPT_VEC_T5:
5245 case MVE_VPT_VEC_T6:
5246 case MVE_VCMP_VEC_T4:
5247 case MVE_VCMP_VEC_T5:
5248 case MVE_VCMP_VEC_T6:
5249 if (arm_decode_field (given, 0, 3) == 0xd)
5250 {
5251 *unpredictable_code = UNPRED_R13;
5252 return TRUE;
5253 }
5254 else
5255 return FALSE;
c1e26897 5256
9743db03
AV		 5257 case MVE_VDUP:
5258 {
5259 unsigned long gpr = arm_decode_field (given, 12, 15);
5260 if (gpr == 0xd)
5261 {
5262 *unpredictable_code = UNPRED_R13;
5263 return TRUE;
5264 }
5265 else if (gpr == 0xf)
5266 {
5267 *unpredictable_code = UNPRED_R15;
5268 return TRUE;
5269 }
5270
5271 return FALSE;
5272 }
5273
d3b63143
AV		 5274 case MVE_VQDMLAH:
5275 case MVE_VQRDMLAH:
5276 case MVE_VQDMLASH:
5277 case MVE_VQRDMLASH:
5278 case MVE_VQDMULH_T3:
5279 case MVE_VQRDMULH_T4:
5280 case MVE_VMLAS:
9743db03
AV		 5281 case MVE_VFMA_FP_SCALAR:
5282 case MVE_VFMAS_FP_SCALAR:
5283 case MVE_VHADD_T2:
5284 case MVE_VHSUB_T2:
5285 {
5286 unsigned long gpr = arm_decode_field (given, 0, 3);
5287 if (gpr == 0xd)
5288 {
5289 *unpredictable_code = UNPRED_R13;
5290 return TRUE;
5291 }
5292 else if (gpr == 0xf)
5293 {
5294 *unpredictable_code = UNPRED_R15;
5295 return TRUE;
5296 }
5297
5298 return FALSE;
5299 }
5300
04d54ace
AV		 5301 case MVE_VLD2:
5302 case MVE_VST2:
5303 {
5304 unsigned long rn = arm_decode_field (given, 16, 19);
5305
5306 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
5307 {
5308 *unpredictable_code = UNPRED_R13_AND_WB;
5309 return TRUE;
5310 }
5311
5312 if (rn == 0xf)
5313 {
5314 *unpredictable_code = UNPRED_R15;
5315 return TRUE;
5316 }
5317
5318 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
5319 {
5320 *unpredictable_code = UNPRED_Q_GT_6;
5321 return TRUE;
5322 }
5323 else
5324 return FALSE;
5325 }
5326
5327 case MVE_VLD4:
5328 case MVE_VST4:
5329 {
5330 unsigned long rn = arm_decode_field (given, 16, 19);
5331
5332 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
5333 {
5334 *unpredictable_code = UNPRED_R13_AND_WB;
5335 return TRUE;
5336 }
5337
5338 if (rn == 0xf)
5339 {
5340 *unpredictable_code = UNPRED_R15;
5341 return TRUE;
5342 }
5343
5344 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
5345 {
5346 *unpredictable_code = UNPRED_Q_GT_4;
5347 return TRUE;
5348 }
5349 else
5350 return FALSE;
5351 }
5352
aef6d006
AV		 5353 case MVE_VLDRB_T5:
5354 case MVE_VLDRH_T6:
5355 case MVE_VLDRW_T7:
5356 case MVE_VSTRB_T5:
5357 case MVE_VSTRH_T6:
5358 case MVE_VSTRW_T7:
5359 {
5360 unsigned long rn = arm_decode_field (given, 16, 19);
5361
5362 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
5363 {
5364 *unpredictable_code = UNPRED_R13_AND_WB;
5365 return TRUE;
5366 }
5367 else if (rn == 0xf)
5368 {
5369 *unpredictable_code = UNPRED_R15;
5370 return TRUE;
5371 }
5372 else
5373 return FALSE;
5374 }
5375
ef1576a1
AV		 5376 case MVE_VLDRB_GATHER_T1:
5377 if (arm_decode_field (given, 0, 0) == 1)
5378 {
5379 *unpredictable_code = UNPRED_OS;
5380 return TRUE;
5381 }
5382
5383 /* fall through. */
5384 /* To handle common code with T2-T4 variants. */
5385 case MVE_VLDRH_GATHER_T2:
5386 case MVE_VLDRW_GATHER_T3:
5387 case MVE_VLDRD_GATHER_T4:
5388 {
5389 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5390 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
5391
5392 if (qd == qm)
5393 {
5394 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
5395 return TRUE;
5396 }
5397
5398 if (arm_decode_field (given, 16, 19) == 0xf)
5399 {
5400 *unpredictable_code = UNPRED_R15;
5401 return TRUE;
5402 }
5403
5404 return FALSE;
5405 }
5406
5407 case MVE_VLDRW_GATHER_T5:
5408 case MVE_VLDRD_GATHER_T6:
5409 {
5410 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5411 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
5412
5413 if (qd == qm)
5414 {
5415 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
5416 return TRUE;
5417 }
5418 else
5419 return FALSE;
5420 }
5421
5422 case MVE_VSTRB_SCATTER_T1:
5423 if (arm_decode_field (given, 16, 19) == 0xf)
5424 {
5425 *unpredictable_code = UNPRED_R15;
5426 return TRUE;
5427 }
5428 else if (arm_decode_field (given, 0, 0) == 1)
5429 {
5430 *unpredictable_code = UNPRED_OS;
5431 return TRUE;
5432 }
5433 else
5434 return FALSE;
5435
5436 case MVE_VSTRH_SCATTER_T2:
5437 case MVE_VSTRW_SCATTER_T3:
5438 case MVE_VSTRD_SCATTER_T4:
5439 if (arm_decode_field (given, 16, 19) == 0xf)
5440 {
5441 *unpredictable_code = UNPRED_R15;
5442 return TRUE;
5443 }
5444 else
5445 return FALSE;
5446
c507f10b
AV		 5447 case MVE_VMOV2_VEC_LANE_TO_GP:
5448 case MVE_VMOV2_GP_TO_VEC_LANE:
bf0b396d
AV		 5449 case MVE_VCVT_BETWEEN_FP_INT:
5450 case MVE_VCVT_FROM_FP_TO_INT:
5451 {
5452 unsigned long rt = arm_decode_field (given, 0, 3);
5453 unsigned long rt2 = arm_decode_field (given, 16, 19);
5454
5455 if ((rt == 0xd) || (rt2 == 0xd))
5456 {
5457 *unpredictable_code = UNPRED_R13;
5458 return TRUE;
5459 }
5460 else if ((rt == 0xf) || (rt2 == 0xf))
5461 {
5462 *unpredictable_code = UNPRED_R15;
5463 return TRUE;
5464 }
5465 else if (rt == rt2)
5466 {
5467 *unpredictable_code = UNPRED_GP_REGS_EQUAL;
5468 return TRUE;
5469 }
5470
5471 return FALSE;
5472 }
5473
c507f10b
AV		 5474 case MVE_VMOV_HFP_TO_GP:
5475 case MVE_VMOV_GP_TO_VEC_LANE:
5476 case MVE_VMOV_VEC_LANE_TO_GP:
5477 {
5478 unsigned long rda = arm_decode_field (given, 12, 15);
5479 if (rda == 0xd)
5480 {
5481 *unpredictable_code = UNPRED_R13;
5482 return TRUE;
5483 }
5484 else if (rda == 0xf)
5485 {
5486 *unpredictable_code = UNPRED_R15;
5487 return TRUE;
5488 }
5489
5490 return FALSE;
5491 }
5492
d3b63143
AV		 5493 case MVE_VQRDMLADH:
5494 case MVE_VQDMLSDH:
5495 case MVE_VQRDMLSDH:
5496 case MVE_VQDMLADH:
14925797
AV		 5497 case MVE_VMULL_INT:
5498 {
5499 unsigned long Qd;
5500 unsigned long Qm;
5501 unsigned long Qn;
5502
5503 if (arm_decode_field (given, 20, 21) == 2)
5504 {
5505 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5506 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
5507 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
5508
5509 if ((Qd == Qn) || (Qd == Qm))
5510 {
5511 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
5512 return TRUE;
5513 }
5514 else
5515 return FALSE;
5516 }
5517 else
5518 return FALSE;
5519 }
5520
5521 case MVE_VQDMULL_T1:
5522 {
5523 unsigned long Qd;
5524 unsigned long Qm;
5525 unsigned long Qn;
5526
5527 if (arm_decode_field (given, 28, 28) == 1)
5528 {
5529 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5530 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
5531 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
5532
5533 if ((Qd == Qn) || (Qd == Qm))
5534 {
5535 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
5536 return TRUE;
5537 }
5538 else
5539 return FALSE;
5540 }
5541 else
5542 return FALSE;
5543 }
5544
5545 case MVE_VQDMULL_T2:
5546 {
5547 unsigned long gpr = arm_decode_field (given, 0, 3);
5548 if (gpr == 0xd)
5549 {
5550 *unpredictable_code = UNPRED_R13;
5551 return TRUE;
5552 }
5553 else if (gpr == 0xf)
5554 {
5555 *unpredictable_code = UNPRED_R15;
5556 return TRUE;
5557 }
5558
5559 if (arm_decode_field (given, 28, 28) == 1)
5560 {
5561 unsigned long Qd
5562 = arm_decode_field_multiple (given, 13, 15, 22, 22);
5563 unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
5564
5565 if ((Qd == Qn))
5566 {
5567 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
5568 return TRUE;
5569 }
5570 else
5571 return FALSE;
5572 }
5573
5574 return FALSE;
5575 }
5576
d3b63143
AV		 5577 case MVE_VMLSLDAV:
5578 case MVE_VRMLSLDAVH:
5579 case MVE_VMLALDAV:
5580 case MVE_VADDLV:
5581 if (arm_decode_field (given, 20, 22) == 6)
5582 {
5583 *unpredictable_code = UNPRED_R13;
5584 return TRUE;
5585 }
5586 else
5587 return FALSE;
5588
1c8f2df8
AV		 5589 case MVE_VDWDUP:
5590 case MVE_VIWDUP:
5591 if (arm_decode_field (given, 1, 3) == 6)
5592 {
5593 *unpredictable_code = UNPRED_R13;
5594 return TRUE;
5595 }
5596 else
5597 return FALSE;
5598
143275ea
AV		 5599 default:
5600 return FALSE;
5601 }
5602}
c1e26897 5603
c507f10b
AV		 5604static void
5605print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
5606{
5607 unsigned long op1 = arm_decode_field (given, 21, 22);
5608 unsigned long op2 = arm_decode_field (given, 5, 6);
5609 unsigned long h = arm_decode_field (given, 16, 16);
5610 unsigned long index, esize, targetBeat, idx;
5611 void *stream = info->stream;
5612 fprintf_ftype func = info->fprintf_func;
5613
5614 if ((op1 & 0x2) == 0x2)
5615 {
5616 index = op2;
5617 esize = 8;
5618 }
5619 else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
5620 {
5621 index = op2 >> 1;
5622 esize = 16;
5623 }
5624 else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
5625 {
5626 index = 0;
5627 esize = 32;
5628 }
5629 else
5630 {
5631 func (stream, "<undefined index>");
5632 return;
5633 }
5634
5635 targetBeat = (op1 & 0x1) | (h << 1);
5636 idx = index + targetBeat * (32/esize);
5637
5638 func (stream, "%lu", idx);
5639}
5640
5641/* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
5642 in length and integer of floating-point type. */
5643static void
5644print_simd_imm8 (struct disassemble_info *info, unsigned long given,
5645 unsigned int ibit_loc, const struct mopcode32 *insn)
5646{
5647 int bits = 0;
5648 int cmode = (given >> 8) & 0xf;
5649 int op = (given >> 5) & 0x1;
5650 unsigned long value = 0, hival = 0;
5651 unsigned shift;
5652 int size = 0;
5653 int isfloat = 0;
5654 void *stream = info->stream;
5655 fprintf_ftype func = info->fprintf_func;
5656
5657 /* On Neon the 'i' bit is at bit 24, on mve it is
5658 at bit 28. */
5659 bits |= ((given >> ibit_loc) & 1) << 7;
5660 bits |= ((given >> 16) & 7) << 4;
5661 bits |= ((given >> 0) & 15) << 0;
5662
5663 if (cmode < 8)
5664 {
5665 shift = (cmode >> 1) & 3;
5666 value = (unsigned long) bits << (8 * shift);
5667 size = 32;
5668 }
5669 else if (cmode < 12)
5670 {
5671 shift = (cmode >> 1) & 1;
5672 value = (unsigned long) bits << (8 * shift);
5673 size = 16;
5674 }
5675 else if (cmode < 14)
5676 {
5677 shift = (cmode & 1) + 1;
5678 value = (unsigned long) bits << (8 * shift);
5679 value |= (1ul << (8 * shift)) - 1;
5680 size = 32;
5681 }
5682 else if (cmode == 14)
5683 {
5684 if (op)
5685 {
5686 /* Bit replication into bytes. */
5687 int ix;
5688 unsigned long mask;
5689
5690 value = 0;
5691 hival = 0;
5692 for (ix = 7; ix >= 0; ix--)
5693 {
5694 mask = ((bits >> ix) & 1) ? 0xff : 0;
5695 if (ix <= 3)
5696 value = (value << 8) | mask;
5697 else
5698 hival = (hival << 8) | mask;
5699 }
5700 size = 64;
5701 }
5702 else
5703 {
5704 /* Byte replication. */
5705 value = (unsigned long) bits;
5706 size = 8;
5707 }
5708 }
5709 else if (!op)
5710 {
5711 /* Floating point encoding. */
5712 int tmp;
5713
5714 value = (unsigned long) (bits & 0x7f) << 19;
5715 value |= (unsigned long) (bits & 0x80) << 24;
5716 tmp = bits & 0x40 ? 0x3c : 0x40;
5717 value |= (unsigned long) tmp << 24;
5718 size = 32;
5719 isfloat = 1;
5720 }
5721 else
5722 {
5723 func (stream, "<illegal constant %.8x:%x:%x>",
5724 bits, cmode, op);
5725 size = 32;
5726 return;
5727 }
5728
5729 // printU determines whether the immediate value should be printed as
5730 // unsigned.
5731 unsigned printU = 0;
5732 switch (insn->mve_op)
5733 {
5734 default:
5735 break;
5736 // We want this for instructions that don't have a 'signed' type
5737 case MVE_VBIC_IMM:
5738 case MVE_VORR_IMM:
5739 case MVE_VMVN_IMM:
5740 case MVE_VMOV_IMM_TO_VEC:
5741 printU = 1;
5742 break;
5743 }
5744 switch (size)
5745 {
5746 case 8:
5747 func (stream, "#%ld\t; 0x%.2lx", value, value);
5748 break;
5749
5750 case 16:
5751 func (stream,
5752 printU
5753 ? "#%lu\t; 0x%.4lx"
5754 : "#%ld\t; 0x%.4lx", value, value);
5755 break;
5756
5757 case 32:
5758 if (isfloat)
5759 {
5760 unsigned char valbytes[4];
5761 double fvalue;
5762
5763 /* Do this a byte at a time so we don't have to
5764 worry about the host's endianness. */
5765 valbytes[0] = value & 0xff;
5766 valbytes[1] = (value >> 8) & 0xff;
5767 valbytes[2] = (value >> 16) & 0xff;
5768 valbytes[3] = (value >> 24) & 0xff;
5769
5770 floatformat_to_double
5771 (& floatformat_ieee_single_little, valbytes,
5772 & fvalue);
5773
5774 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
5775 value);
5776 }
5777 else
5778 func (stream,
5779 printU
5780 ? "#%lu\t; 0x%.8lx"
5781 : "#%ld\t; 0x%.8lx",
5782 (long) (((value & 0x80000000L) != 0)
5783 && !printU
5784 ? value | ~0xffffffffL : value),
5785 value);
5786 break;
5787
5788 case 64:
5789 func (stream, "#0x%.8lx%.8lx", hival, value);
5790 break;
5791
5792 default:
5793 abort ();
5794 }
5795
5796}
5797
73cd51e5
AV		 5798static void
5799print_mve_undefined (struct disassemble_info *info,
5800 enum mve_undefined undefined_code)
5801{
5802 void *stream = info->stream;
5803 fprintf_ftype func = info->fprintf_func;
5804
5805 func (stream, "\t\tundefined instruction: ");
5806
5807 switch (undefined_code)
5808 {
aef6d006
AV		 5809 case UNDEF_SIZE_0:
5810 func (stream, "size equals zero");
5811 break;
5812
c507f10b
AV		 5813 case UNDEF_SIZE_2:
5814 func (stream, "size equals two");
5815 break;
5816
9743db03
AV		 5817 case UNDEF_SIZE_3:
5818 func (stream, "size equals three");
5819 break;
5820
aef6d006
AV		 5821 case UNDEF_SIZE_LE_1:
5822 func (stream, "size <= 1");
5823 break;
5824
ef1576a1
AV		 5825 case UNDEF_SIZE_NOT_2:
5826 func (stream, "size not equal to 2");
5827 break;
5828
5829 case UNDEF_SIZE_NOT_3:
5830 func (stream, "size not equal to 3");
5831 break;
5832
5833 case UNDEF_NOT_UNS_SIZE_0:
5834 func (stream, "not unsigned and size = zero");
5835 break;
5836
5837 case UNDEF_NOT_UNS_SIZE_1:
5838 func (stream, "not unsigned and size = one");
5839 break;
5840
5841 case UNDEF_NOT_UNSIGNED:
5842 func (stream, "not unsigned");
5843 break;
5844
bf0b396d
AV		 5845 case UNDEF_VCVT_IMM6:
5846 func (stream, "invalid imm6");
5847 break;
5848
5849 case UNDEF_VCVT_FSI_IMM6:
5850 func (stream, "fsi = 0 and invalid imm6");
5851 break;
5852
c507f10b
AV		 5853 case UNDEF_BAD_OP1_OP2:
5854 func (stream, "bad size with op2 = 2 and op1 = 0 or 1");
5855 break;
5856
5857 case UNDEF_BAD_U_OP1_OP2:
5858 func (stream, "unsigned with op2 = 0 and op1 = 0 or 1");
5859 break;
5860
5861 case UNDEF_OP_0_BAD_CMODE:
5862 func (stream, "op field equal 0 and bad cmode");
5863 break;
5864
d3b63143
AV		 5865 case UNDEF_XCHG_UNS:
5866 func (stream, "exchange and unsigned together");
5867 break;
5868
73cd51e5
AV		 5869 case UNDEF_NONE:
5870 break;
5871 }
5872
5873}
5874
5875static void
5876print_mve_unpredictable (struct disassemble_info *info,
5877 enum mve_unpredictable unpredict_code)
5878{
5879 void *stream = info->stream;
5880 fprintf_ftype func = info->fprintf_func;
5881
5882 func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
5883
5884 switch (unpredict_code)
5885 {
5886 case UNPRED_IT_BLOCK:
5887 func (stream, "mve instruction in it block");
5888 break;
5889
143275ea
AV		 5890 case UNPRED_FCA_0_FCB_1:
5891 func (stream, "condition bits, fca = 0 and fcb = 1");
5892 break;
5893
5894 case UNPRED_R13:
5895 func (stream, "use of r13 (sp)");
5896 break;
5897
9743db03
AV		 5898 case UNPRED_R15:
5899 func (stream, "use of r15 (pc)");
5900 break;
5901
04d54ace
AV		 5902 case UNPRED_Q_GT_4:
5903 func (stream, "start register block > r4");
5904 break;
5905
5906 case UNPRED_Q_GT_6:
5907 func (stream, "start register block > r6");
5908 break;
5909
5910 case UNPRED_R13_AND_WB:
5911 func (stream, "use of r13 and write back");
5912 break;
5913
ef1576a1
AV		 5914 case UNPRED_Q_REGS_EQUAL:
5915 func (stream,
5916 "same vector register used for destination and other operand");
5917 break;
5918
5919 case UNPRED_OS:
5920 func (stream, "use of offset scaled");
5921 break;
5922
bf0b396d
AV		 5923 case UNPRED_GP_REGS_EQUAL:
5924 func (stream, "same general-purpose register used for both operands");
5925 break;
5926
c507f10b
AV		 5927 case UNPRED_Q_REGS_EQ_AND_SIZE_1:
5928 func (stream, "use of identical q registers and size = 1");
5929 break;
5930
5931 case UNPRED_Q_REGS_EQ_AND_SIZE_2:
5932 func (stream, "use of identical q registers and size = 1");
5933 break;
5934
73cd51e5
AV		 5935 case UNPRED_NONE:
5936 break;
5937 }
5938}
5939
04d54ace
AV		 5940/* Print register block operand for mve vld2/vld4/vst2/vld4. */
5941
5942static void
5943print_mve_register_blocks (struct disassemble_info *info,
5944 unsigned long given,
5945 enum mve_instructions matched_insn)
5946{
5947 void *stream = info->stream;
5948 fprintf_ftype func = info->fprintf_func;
5949
5950 unsigned long q_reg_start = arm_decode_field_multiple (given,
5951 13, 15,
5952 22, 22);
5953 switch (matched_insn)
5954 {
5955 case MVE_VLD2:
5956 case MVE_VST2:
5957 if (q_reg_start <= 6)
5958 func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
5959 else
5960 func (stream, "<illegal reg q%ld>", q_reg_start);
5961 break;
5962
5963 case MVE_VLD4:
5964 case MVE_VST4:
5965 if (q_reg_start <= 4)
5966 func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
5967 q_reg_start + 1, q_reg_start + 2,
5968 q_reg_start + 3);
5969 else
5970 func (stream, "<illegal reg q%ld>", q_reg_start);
5971 break;
5972
5973 default:
5974 break;
5975 }
5976}
5977
bf0b396d
AV		 5978static void
5979print_mve_rounding_mode (struct disassemble_info *info,
5980 unsigned long given,
5981 enum mve_instructions matched_insn)
5982{
5983 void *stream = info->stream;
5984 fprintf_ftype func = info->fprintf_func;
5985
5986 switch (matched_insn)
5987 {
5988 case MVE_VCVT_FROM_FP_TO_INT:
5989 {
5990 switch (arm_decode_field (given, 8, 9))
5991 {
5992 case 0:
5993 func (stream, "a");
5994 break;
5995
5996 case 1:
5997 func (stream, "n");
5998 break;
5999
6000 case 2:
6001 func (stream, "p");
6002 break;
6003
6004 case 3:
6005 func (stream, "m");
6006 break;
6007
6008 default:
6009 break;
6010 }
6011 }
6012 break;
6013
6014 case MVE_VRINT_FP:
6015 {
6016 switch (arm_decode_field (given, 7, 9))
6017 {
6018 case 0:
6019 func (stream, "n");
6020 break;
6021
6022 case 1:
6023 func (stream, "x");
6024 break;
6025
6026 case 2:
6027 func (stream, "a");
6028 break;
6029
6030 case 3:
6031 func (stream, "z");
6032 break;
6033
6034 case 5:
6035 func (stream, "m");
6036 break;
6037
6038 case 7:
6039 func (stream, "p");
6040
6041 case 4:
6042 case 6:
6043 default:
6044 break;
6045 }
6046 }
6047 break;
6048
6049 default:
6050 break;
6051 }
6052}
6053
6054static void
6055print_mve_vcvt_size (struct disassemble_info *info,
6056 unsigned long given,
6057 enum mve_instructions matched_insn)
6058{
6059 unsigned long mode = 0;
6060 void *stream = info->stream;
6061 fprintf_ftype func = info->fprintf_func;
6062
6063 switch (matched_insn)
6064 {
6065 case MVE_VCVT_FP_FIX_VEC:
6066 {
6067 mode = (((given & 0x200) >> 7)
6068 | ((given & 0x10000000) >> 27)
6069 | ((given & 0x100) >> 8));
6070
6071 switch (mode)
6072 {
6073 case 0:
6074 func (stream, "f16.s16");
6075 break;
6076
6077 case 1:
6078 func (stream, "s16.f16");
6079 break;
6080
6081 case 2:
6082 func (stream, "f16.u16");
6083 break;
6084
6085 case 3:
6086 func (stream, "u16.f16");
6087 break;
6088
6089 case 4:
6090 func (stream, "f32.s32");
6091 break;
6092
6093 case 5:
6094 func (stream, "s32.f32");
6095 break;
6096
6097 case 6:
6098 func (stream, "f32.u32");
6099 break;
6100
6101 case 7:
6102 func (stream, "u32.f32");
6103 break;
6104
6105 default:
6106 break;
6107 }
6108 break;
6109 }
6110 case MVE_VCVT_BETWEEN_FP_INT:
6111 {
6112 unsigned long size = arm_decode_field (given, 18, 19);
6113 unsigned long op = arm_decode_field (given, 7, 8);
6114
6115 if (size == 1)
6116 {
6117 switch (op)
6118 {
6119 case 0:
6120 func (stream, "f16.s16");
6121 break;
6122
6123 case 1:
6124 func (stream, "f16.u16");
6125 break;
6126
6127 case 2:
6128 func (stream, "s16.f16");
6129 break;
6130
6131 case 3:
6132 func (stream, "u16.f16");
6133 break;
6134
6135 default:
6136 break;
6137 }
6138 }
6139 else if (size == 2)
6140 {
6141 switch (op)
6142 {
6143 case 0:
6144 func (stream, "f32.s32");
6145 break;
6146
6147 case 1:
6148 func (stream, "f32.u32");
6149 break;
6150
6151 case 2:
6152 func (stream, "s32.f32");
6153 break;
6154
6155 case 3:
6156 func (stream, "u32.f32");
6157 break;
6158 }
6159 }
6160 }
6161 break;
6162
6163 case MVE_VCVT_FP_HALF_FP:
6164 {
6165 unsigned long op = arm_decode_field (given, 28, 28);
6166 if (op == 0)
6167 func (stream, "f16.f32");
6168 else if (op == 1)
6169 func (stream, "f32.f16");
6170 }
6171 break;
6172
6173 case MVE_VCVT_FROM_FP_TO_INT:
6174 {
6175 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
6176
6177 switch (size)
6178 {
6179 case 2:
6180 func (stream, "s16.f16");
6181 break;
6182
6183 case 3:
6184 func (stream, "u16.f16");
6185 break;
6186
6187 case 4:
6188 func (stream, "s32.f32");
6189 break;
6190
6191 case 5:
6192 func (stream, "u32.f32");
6193 break;
6194
6195 default:
6196 break;
6197 }
6198 }
6199 break;
6200
6201 default:
6202 break;
6203 }
6204}
6205
143275ea
AV		 6206static void
6207print_instruction_predicate (struct disassemble_info *info)
6208{
6209 void *stream = info->stream;
6210 fprintf_ftype func = info->fprintf_func;
6211
6212 if (vpt_block_state.next_pred_state == PRED_THEN)
6213 func (stream, "t");
6214 else if (vpt_block_state.next_pred_state == PRED_ELSE)
6215 func (stream, "e");
6216}
6217
6218static void
6219print_mve_size (struct disassemble_info *info,
6220 unsigned long size,
6221 enum mve_instructions matched_insn)
6222{
6223 void *stream = info->stream;
6224 fprintf_ftype func = info->fprintf_func;
6225
6226 switch (matched_insn)
6227 {
d3b63143 6228 case MVE_VADDV:
143275ea
AV		 6229 case MVE_VCMP_VEC_T1:
6230 case MVE_VCMP_VEC_T2:
6231 case MVE_VCMP_VEC_T3:
6232 case MVE_VCMP_VEC_T4:
6233 case MVE_VCMP_VEC_T5:
6234 case MVE_VCMP_VEC_T6:
1c8f2df8
AV		 6235 case MVE_VDDUP:
6236 case MVE_VDWDUP:
9743db03
AV		 6237 case MVE_VHADD_T1:
6238 case MVE_VHADD_T2:
6239 case MVE_VHSUB_T1:
6240 case MVE_VHSUB_T2:
1c8f2df8
AV		 6241 case MVE_VIDUP:
6242 case MVE_VIWDUP:
04d54ace
AV		 6243 case MVE_VLD2:
6244 case MVE_VLD4:
ef1576a1
AV		 6245 case MVE_VLDRB_GATHER_T1:
6246 case MVE_VLDRH_GATHER_T2:
6247 case MVE_VLDRW_GATHER_T3:
6248 case MVE_VLDRD_GATHER_T4:
aef6d006
AV		 6249 case MVE_VLDRB_T1:
6250 case MVE_VLDRH_T2:
d3b63143 6251 case MVE_VMLAS:
143275ea
AV		 6252 case MVE_VPT_VEC_T1:
6253 case MVE_VPT_VEC_T2:
6254 case MVE_VPT_VEC_T3:
6255 case MVE_VPT_VEC_T4:
6256 case MVE_VPT_VEC_T5:
6257 case MVE_VPT_VEC_T6:
d3b63143
AV		 6258 case MVE_VQDMLADH:
6259 case MVE_VQRDMLADH:
6260 case MVE_VQDMLAH:
6261 case MVE_VQRDMLAH:
6262 case MVE_VQDMLASH:
6263 case MVE_VQRDMLASH:
6264 case MVE_VQDMLSDH:
6265 case MVE_VQRDMLSDH:
6266 case MVE_VQDMULH_T1:
6267 case MVE_VQRDMULH_T2:
6268 case MVE_VQDMULH_T3:
6269 case MVE_VQRDMULH_T4:
9743db03 6270 case MVE_VRHADD:
bf0b396d 6271 case MVE_VRINT_FP:
04d54ace
AV		 6272 case MVE_VST2:
6273 case MVE_VST4:
ef1576a1
AV		 6274 case MVE_VSTRB_SCATTER_T1:
6275 case MVE_VSTRH_SCATTER_T2:
6276 case MVE_VSTRW_SCATTER_T3:
aef6d006
AV		 6277 case MVE_VSTRB_T1:
6278 case MVE_VSTRH_T2:
143275ea
AV		 6279 if (size <= 3)
6280 func (stream, "%s", mve_vec_sizename[size]);
6281 else
6282 func (stream, "<undef size>");
6283 break;
6284
6285 case MVE_VCMP_FP_T1:
6286 case MVE_VCMP_FP_T2:
9743db03
AV		 6287 case MVE_VFMA_FP_SCALAR:
6288 case MVE_VFMA_FP:
6289 case MVE_VFMS_FP:
6290 case MVE_VFMAS_FP_SCALAR:
143275ea
AV		 6291 case MVE_VPT_FP_T1:
6292 case MVE_VPT_FP_T2:
6293 if (size == 0)
6294 func (stream, "32");
6295 else if (size == 1)
6296 func (stream, "16");
6297 break;
6298
d3b63143
AV		 6299 case MVE_VMLADAV_T1:
6300 case MVE_VMLALDAV:
6301 case MVE_VMLSDAV_T1:
6302 case MVE_VMLSLDAV:
14925797
AV		 6303 case MVE_VMOVN:
6304 case MVE_VQDMULL_T1:
6305 case MVE_VQDMULL_T2:
6306 case MVE_VQMOVN:
6307 case MVE_VQMOVUN:
6308 if (size == 0)
6309 func (stream, "16");
6310 else if (size == 1)
6311 func (stream, "32");
6312 break;
6313
6314 case MVE_VMOVL:
6315 if (size == 1)
6316 func (stream, "8");
6317 else if (size == 2)
6318 func (stream, "16");
6319 break;
6320
9743db03
AV		 6321 case MVE_VDUP:
6322 switch (size)
6323 {
6324 case 0:
6325 func (stream, "32");
6326 break;
6327 case 1:
6328 func (stream, "16");
6329 break;
6330 case 2:
6331 func (stream, "8");
6332 break;
6333 default:
6334 break;
6335 }
6336 break;
6337
c507f10b
AV		 6338 case MVE_VMOV_GP_TO_VEC_LANE:
6339 case MVE_VMOV_VEC_LANE_TO_GP:
6340 switch (size)
6341 {
6342 case 0: case 4:
6343 func (stream, "32");
6344 break;
6345
6346 case 1: case 3:
6347 case 5: case 7:
6348 func (stream, "16");
6349 break;
6350
6351 case 8: case 9: case 10: case 11:
6352 case 12: case 13: case 14: case 15:
6353 func (stream, "8");
6354 break;
6355
6356 default:
6357 break;
6358 }
6359 break;
6360
6361 case MVE_VMOV_IMM_TO_VEC:
6362 switch (size)
6363 {
6364 case 0: case 4: case 8:
6365 case 12: case 24: case 26:
6366 func (stream, "i32");
6367 break;
6368 case 16: case 20:
6369 func (stream, "i16");
6370 break;
6371 case 28:
6372 func (stream, "i8");
6373 break;
6374 case 29:
6375 func (stream, "i64");
6376 break;
6377 case 30:
6378 func (stream, "f32");
6379 break;
6380 default:
6381 break;
6382 }
6383 break;
6384
14925797
AV		 6385 case MVE_VMULL_POLY:
6386 if (size == 0)
6387 func (stream, "p8");
6388 else if (size == 1)
6389 func (stream, "p16");
6390 break;
6391
c507f10b
AV		 6392 case MVE_VMVN_IMM:
6393 switch (size)
6394 {
6395 case 0: case 2: case 4:
6396 case 6: case 12: case 13:
6397 func (stream, "32");
6398 break;
6399
6400 case 8: case 10:
6401 func (stream, "16");
6402 break;
6403
6404 default:
6405 break;
6406 }
6407 break;
6408
6409 case MVE_VBIC_IMM:
6410 case MVE_VORR_IMM:
6411 switch (size)
6412 {
6413 case 1: case 3:
6414 case 5: case 7:
6415 func (stream, "32");
6416 break;
6417
6418 case 9: case 11:
6419 func (stream, "16");
6420 break;
6421
6422 default:
6423 break;
6424 }
6425 break;
6426
143275ea
AV		 6427 default:
6428 break;
6429 }
6430}
6431
6432static void
6433print_vec_condition (struct disassemble_info *info, long given,
6434 enum mve_instructions matched_insn)
6435{
6436 void *stream = info->stream;
6437 fprintf_ftype func = info->fprintf_func;
6438 long vec_cond = 0;
6439
6440 switch (matched_insn)
6441 {
6442 case MVE_VPT_FP_T1:
6443 case MVE_VCMP_FP_T1:
6444 vec_cond = (((given & 0x1000) >> 10)
6445 | ((given & 1) << 1)
6446 | ((given & 0x0080) >> 7));
6447 func (stream, "%s",vec_condnames[vec_cond]);
6448 break;
6449
6450 case MVE_VPT_FP_T2:
6451 case MVE_VCMP_FP_T2:
6452 vec_cond = (((given & 0x1000) >> 10)
6453 | ((given & 0x0020) >> 4)
6454 | ((given & 0x0080) >> 7));
6455 func (stream, "%s",vec_condnames[vec_cond]);
6456 break;
6457
6458 case MVE_VPT_VEC_T1:
6459 case MVE_VCMP_VEC_T1:
6460 vec_cond = (given & 0x0080) >> 7;
6461 func (stream, "%s",vec_condnames[vec_cond]);
6462 break;
6463
6464 case MVE_VPT_VEC_T2:
6465 case MVE_VCMP_VEC_T2:
6466 vec_cond = 2 | ((given & 0x0080) >> 7);
6467 func (stream, "%s",vec_condnames[vec_cond]);
6468 break;
6469
6470 case MVE_VPT_VEC_T3:
6471 case MVE_VCMP_VEC_T3:
6472 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
6473 func (stream, "%s",vec_condnames[vec_cond]);
6474 break;
6475
6476 case MVE_VPT_VEC_T4:
6477 case MVE_VCMP_VEC_T4:
6478 vec_cond = (given & 0x0080) >> 7;
6479 func (stream, "%s",vec_condnames[vec_cond]);
6480 break;
6481
6482 case MVE_VPT_VEC_T5:
6483 case MVE_VCMP_VEC_T5:
6484 vec_cond = 2 | ((given & 0x0080) >> 7);
6485 func (stream, "%s",vec_condnames[vec_cond]);
6486 break;
6487
6488 case MVE_VPT_VEC_T6:
6489 case MVE_VCMP_VEC_T6:
6490 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
6491 func (stream, "%s",vec_condnames[vec_cond]);
6492 break;
6493
6494 case MVE_NONE:
6495 case MVE_VPST:
6496 default:
6497 break;
6498 }
6499}
6500
6501#define W_BIT 21
6502#define I_BIT 22
6503#define U_BIT 23
6504#define P_BIT 24
6505
6506#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
6507#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
6508#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
6509#define PRE_BIT_SET (given & (1 << P_BIT))
6510
6511
8f06b2d8
PB		 6512/* Print one coprocessor instruction on INFO->STREAM.
6513 Return TRUE if the instuction matched, FALSE if this is not a
6514 recognised coprocessor instruction. */
6515
6516static bfd_boolean
fe56b6ce
NC		 6517print_insn_coprocessor (bfd_vma pc,
6518 struct disassemble_info *info,
6519 long given,
8f06b2d8
PB		 6520 bfd_boolean thumb)
6521{
6b0dd094 6522 const struct sopcode32 *insn;
8f06b2d8
PB		 6523 void *stream = info->stream;
6524 fprintf_ftype func = info->fprintf_func;
6525 unsigned long mask;
2edcd244 6526 unsigned long value = 0;
c22aaad1 6527 int cond;
8afc7bea 6528 int cp_num;
823d2571
TG		 6529 struct arm_private_data *private_data = info->private_data;
6530 arm_feature_set allowed_arches = ARM_ARCH_NONE;
32c36c3c
AV		 6531 arm_feature_set arm_ext_v8_1m_main =
6532 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
823d2571 6533
5b616bef 6534 allowed_arches = private_data->features;
8f06b2d8
PB		 6535
6536 for (insn = coprocessor_opcodes; insn->assembler; insn++)
6537 {
ff4a8d2b
NC		 6538 unsigned long u_reg = 16;
6539 bfd_boolean is_unpredictable = FALSE;
05413229 6540 signed long value_in_comment = 0;
0313a2b8
NC		 6541 const char *c;
6542
823d2571 6543 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 6544 switch (insn->value)
6545 {
6546 case SENTINEL_IWMMXT_START:
6547 if (info->mach != bfd_mach_arm_XScale
6548 && info->mach != bfd_mach_arm_iWMMXt
6549 && info->mach != bfd_mach_arm_iWMMXt2)
6550 do
6551 insn++;
823d2571
TG		 6552 while ((! ARM_FEATURE_ZERO (insn->arch))
6553 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 6554 continue;
6555
6556 case SENTINEL_IWMMXT_END:
6557 continue;
6558
6559 case SENTINEL_GENERIC_START:
5b616bef 6560 allowed_arches = private_data->features;
05413229
NC		 6561 continue;
6562
6563 default:
6564 abort ();
6565 }
8f06b2d8
PB		 6566
6567 mask = insn->mask;
6568 value = insn->value;
8afc7bea
RL		 6569 cp_num = (given >> 8) & 0xf;
6570
8f06b2d8
PB		 6571 if (thumb)
6572 {
6573 /* The high 4 bits are 0xe for Arm conditional instructions, and
6574 0xe for arm unconditional instructions. The rest of the
6575 encoding is the same. */
6576 mask |= 0xf0000000;
6577 value |= 0xe0000000;
c22aaad1
PB		 6578 if (ifthen_state)
6579 cond = IFTHEN_COND;
6580 else
e2efe87d 6581 cond = COND_UNCOND;
8f06b2d8
PB		 6582 }
6583 else
6584 {
6585 /* Only match unconditional instuctions against unconditional
6586 patterns. */
6587 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 6588 {
6589 mask |= 0xf0000000;
e2efe87d 6590 cond = COND_UNCOND;
c22aaad1
PB		 6591 }
6592 else
6593 {
6594 cond = (given >> 28) & 0xf;
6595 if (cond == 0xe)
e2efe87d 6596 cond = COND_UNCOND;
c22aaad1 6597 }
8f06b2d8 6598 }
823d2571 6599
6b0dd094
AV		 6600 if ((insn->isa == T32 && !thumb)
6601 || (insn->isa == ARM && thumb))
6602 continue;
6603
0313a2b8
NC		 6604 if ((given & mask) != value)
6605 continue;
8f06b2d8 6606
823d2571 6607 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 6608 continue;
6609
8afc7bea
RL		 6610 if (insn->value == 0xfe000010 /* mcr2 */
6611 || insn->value == 0xfe100010 /* mrc2 */
6612 || insn->value == 0xfc100000 /* ldc2 */
6613 || insn->value == 0xfc000000) /* stc2 */
6614 {
b0c11777 6615 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 6616 is_unpredictable = TRUE;
f08d8ce3
AV		 6617
6618 /* Armv8.1-M Mainline FP & MVE instructions. */
6619 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
6620 && !ARM_CPU_IS_ANY (allowed_arches)
6621 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
6622 continue;
6623
8afc7bea
RL		 6624 }
6625 else if (insn->value == 0x0e000000 /* cdp */
6626 || insn->value == 0xfe000000 /* cdp2 */
6627 || insn->value == 0x0e000010 /* mcr */
6628 || insn->value == 0x0e100010 /* mrc */
6629 || insn->value == 0x0c100000 /* ldc */
6630 || insn->value == 0x0c000000) /* stc */
6631 {
6632 /* Floating-point instructions. */
b0c11777 6633 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 6634 continue;
32c36c3c
AV		 6635
6636 /* Armv8.1-M Mainline FP & MVE instructions. */
6637 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
6638 && !ARM_CPU_IS_ANY (allowed_arches)
6639 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
6640 continue;
8afc7bea 6641 }
aef6d006
AV		 6642 else if ((insn->value == 0xec100f80 /* vldr (system register) */
6643 || insn->value == 0xec000f80) /* vstr (system register) */
6644 && arm_decode_field (given, 24, 24) == 0
6645 && arm_decode_field (given, 21, 21) == 0)
6646 /* If the P and W bits are both 0 then these encodings match the MVE
6647 VLDR and VSTR instructions, these are in a different table, so we
6648 don't let it match here. */
6649 continue;
6650
0313a2b8
NC		 6651 for (c = insn->assembler; *c; c++)
6652 {
6653 if (*c == '%')
8f06b2d8 6654 {
32c36c3c
AV		 6655 const char mod = *++c;
6656 switch (mod)
8f06b2d8 6657 {
0313a2b8
NC		 6658 case '%':
6659 func (stream, "%%");
6660 break;
6661
6662 case 'A':
32c36c3c 6663 case 'K':
05413229 6664 {
79862e45 6665 int rn = (given >> 16) & 0xf;
b0c11777 6666 bfd_vma offset = given & 0xff;
0313a2b8 6667
32c36c3c
AV		 6668 if (mod == 'K')
6669 offset = given & 0x7f;
6670
05413229 6671 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 6672
79862e45
DJ		 6673 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
6674 {
6675 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 6676 if (cp_num == 9)
6677 /* vldr.16/vstr.16 will shift the address
6678 left by 1 bit only. */
6679 offset = offset * 2;
6680 else
6681 offset = offset * 4;
6682
79862e45
DJ		 6683 if (NEGATIVE_BIT_SET)
6684 offset = - offset;
6685 if (rn != 15)
6686 value_in_comment = offset;
6687 }
6688
c1e26897 6689 if (PRE_BIT_SET)
05413229
NC		 6690 {
6691 if (offset)
fe56b6ce 6692 func (stream, ", #%d]%s",
d908c8af 6693 (int) offset,
c1e26897 6694 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 6695 else if (NEGATIVE_BIT_SET)
6696 func (stream, ", #-0]");
05413229
NC		 6697 else
6698 func (stream, "]");
6699 }
6700 else
6701 {
0313a2b8 6702 func (stream, "]");
8f06b2d8 6703
c1e26897 6704 if (WRITEBACK_BIT_SET)
05413229
NC		 6705 {
6706 if (offset)
d908c8af 6707 func (stream, ", #%d", (int) offset);
26d97720
NS		 6708 else if (NEGATIVE_BIT_SET)
6709 func (stream, ", #-0");
05413229
NC		 6710 }
6711 else
fe56b6ce 6712 {
26d97720
NS		 6713 func (stream, ", {%s%d}",
6714 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 6715 (int) offset);
fe56b6ce
NC		 6716 value_in_comment = offset;
6717 }
05413229 6718 }
79862e45
DJ		 6719 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
6720 {
6721 func (stream, "\t; ");
6844b2c2
MGD		 6722 /* For unaligned PCs, apply off-by-alignment
6723 correction. */
43e65147 6724 info->print_address_func (offset + pc
6844b2c2
MGD		 6725 + info->bytes_per_chunk * 2
6726 - (pc & 3),
dffaa15c 6727 info);
79862e45 6728 }
05413229 6729 }
0313a2b8 6730 break;
8f06b2d8 6731
0313a2b8
NC		 6732 case 'B':
6733 {
6734 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
6735 int offset = (given >> 1) & 0x3f;
6736
6737 if (offset == 1)
6738 func (stream, "{d%d}", regno);
6739 else if (regno + offset > 32)
6740 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
6741 else
6742 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
6743 }
6744 break;
8f06b2d8 6745
efd6b359
AV		 6746 case 'C':
6747 {
6748 bfd_boolean single = ((given >> 8) & 1) == 0;
6749 char reg_prefix = single ? 's' : 'd';
6750 int Dreg = (given >> 22) & 0x1;
6751 int Vdreg = (given >> 12) & 0xf;
6752 int reg = single ? ((Vdreg << 1) | Dreg)
6753 : ((Dreg << 4) | Vdreg);
6754 int num = (given >> (single ? 0 : 1)) & 0x7f;
6755 int maxreg = single ? 31 : 15;
6756 int topreg = reg + num - 1;
6757
6758 if (!num)
6759 func (stream, "{VPR}");
6760 else if (num == 1)
6761 func (stream, "{%c%d, VPR}", reg_prefix, reg);
6762 else if (topreg > maxreg)
6763 func (stream, "{%c%d-<overflow reg d%d, VPR}",
6764 reg_prefix, reg, single ? topreg >> 1 : topreg);
6765 else
6766 func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
6767 reg_prefix, topreg);
6768 }
6769 break;
6770
e2efe87d
MGD		 6771 case 'u':
6772 if (cond != COND_UNCOND)
6773 is_unpredictable = TRUE;
6774
6775 /* Fall through. */
0313a2b8 6776 case 'c':
b0c11777
RL		 6777 if (cond != COND_UNCOND && cp_num == 9)
6778 is_unpredictable = TRUE;
6779
0313a2b8
NC		 6780 func (stream, "%s", arm_conditional[cond]);
6781 break;
8f06b2d8 6782
0313a2b8
NC		 6783 case 'I':
6784 /* Print a Cirrus/DSP shift immediate. */
6785 /* Immediates are 7bit signed ints with bits 0..3 in
6786 bits 0..3 of opcode and bits 4..6 in bits 5..7
6787 of opcode. */
6788 {
6789 int imm;
8f06b2d8 6790
0313a2b8 6791 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 6792
0313a2b8
NC		 6793 /* Is ``imm'' a negative number? */
6794 if (imm & 0x40)
24b4cf66 6795 imm -= 0x80;
8f06b2d8 6796
0313a2b8
NC		 6797 func (stream, "%d", imm);
6798 }
6799
6800 break;
8f06b2d8 6801
32c36c3c
AV		 6802 case 'J':
6803 {
73cd51e5
AV		 6804 unsigned long regno
6805 = arm_decode_field_multiple (given, 13, 15, 22, 22);
32c36c3c
AV		 6806
6807 switch (regno)
6808 {
6809 case 0x1:
6810 func (stream, "FPSCR");
6811 break;
6812 case 0x2:
6813 func (stream, "FPSCR_nzcvqc");
6814 break;
6815 case 0xc:
6816 func (stream, "VPR");
6817 break;
6818 case 0xd:
6819 func (stream, "P0");
6820 break;
6821 case 0xe:
6822 func (stream, "FPCXTNS");
6823 break;
6824 case 0xf:
6825 func (stream, "FPCXTS");
6826 break;
6827 default:
73cd51e5 6828 func (stream, "<invalid reg %lu>", regno);
32c36c3c
AV		 6829 break;
6830 }
6831 }
6832 break;
6833
0313a2b8
NC		 6834 case 'F':
6835 switch (given & 0x00408000)
6836 {
6837 case 0:
6838 func (stream, "4");
6839 break;
6840 case 0x8000:
6841 func (stream, "1");
6842 break;
6843 case 0x00400000:
6844 func (stream, "2");
8f06b2d8 6845 break;
0313a2b8
NC		 6846 default:
6847 func (stream, "3");
6848 }
6849 break;
8f06b2d8 6850
0313a2b8
NC		 6851 case 'P':
6852 switch (given & 0x00080080)
6853 {
6854 case 0:
6855 func (stream, "s");
6856 break;
6857 case 0x80:
6858 func (stream, "d");
6859 break;
6860 case 0x00080000:
6861 func (stream, "e");
6862 break;
6863 default:
6864 func (stream, _("<illegal precision>"));
8f06b2d8 6865 break;
0313a2b8
NC		 6866 }
6867 break;
8f06b2d8 6868
0313a2b8
NC		 6869 case 'Q':
6870 switch (given & 0x00408000)
6871 {
6872 case 0:
6873 func (stream, "s");
8f06b2d8 6874 break;
0313a2b8
NC		 6875 case 0x8000:
6876 func (stream, "d");
8f06b2d8 6877 break;
0313a2b8
NC		 6878 case 0x00400000:
6879 func (stream, "e");
6880 break;
6881 default:
6882 func (stream, "p");
8f06b2d8 6883 break;
0313a2b8
NC		 6884 }
6885 break;
8f06b2d8 6886
0313a2b8
NC		 6887 case 'R':
6888 switch (given & 0x60)
6889 {
6890 case 0:
6891 break;
6892 case 0x20:
6893 func (stream, "p");
6894 break;
6895 case 0x40:
6896 func (stream, "m");
6897 break;
6898 default:
6899 func (stream, "z");
6900 break;
6901 }
6902 break;
16980d0b 6903
0313a2b8
NC		 6904 case '0': case '1': case '2': case '3': case '4':
6905 case '5': case '6': case '7': case '8': case '9':
6906 {
6907 int width;
8f06b2d8 6908
0313a2b8 6909 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 6910
0313a2b8
NC		 6911 switch (*c)
6912 {
ff4a8d2b
NC		 6913 case 'R':
6914 if (value == 15)
6915 is_unpredictable = TRUE;
6916 /* Fall through. */
0313a2b8 6917 case 'r':
ff4a8d2b
NC		 6918 if (c[1] == 'u')
6919 {
6920 /* Eat the 'u' character. */
6921 ++ c;
6922
6923 if (u_reg == value)
6924 is_unpredictable = TRUE;
6925 u_reg = value;
6926 }
0313a2b8
NC		 6927 func (stream, "%s", arm_regnames[value]);
6928 break;
c28eeff2
SN		 6929 case 'V':
6930 if (given & (1 << 6))
6931 goto Q;
6932 /* FALLTHROUGH */
0313a2b8
NC		 6933 case 'D':
6934 func (stream, "d%ld", value);
6935 break;
6936 case 'Q':
c28eeff2 6937 Q:
0313a2b8
NC		 6938 if (value & 1)
6939 func (stream, "<illegal reg q%ld.5>", value >> 1);
6940 else
6941 func (stream, "q%ld", value >> 1);
6942 break;
6943 case 'd':
6944 func (stream, "%ld", value);
05413229 6945 value_in_comment = value;
0313a2b8 6946 break;
6f1c2142
AM		 6947 case 'E':
6948 {
6949 /* Converts immediate 8 bit back to float value. */
6950 unsigned floatVal = (value & 0x80) << 24
6951 | (value & 0x3F) << 19
6952 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
6953
6954 /* Quarter float have a maximum value of 31.0.
6955 Get floating point value multiplied by 1e7.
6956 The maximum value stays in limit of a 32-bit int. */
6957 unsigned decVal =
6958 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
6959 (16 + (value & 0xF));
6960
6961 if (!(decVal % 1000000))
6962 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
6963 floatVal, value & 0x80 ? '-' : ' ',
6964 decVal / 10000000,
6965 decVal % 10000000 / 1000000);
6966 else if (!(decVal % 10000))
6967 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
6968 floatVal, value & 0x80 ? '-' : ' ',
6969 decVal / 10000000,
6970 decVal % 10000000 / 10000);
6971 else
6972 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
6973 floatVal, value & 0x80 ? '-' : ' ',
6974 decVal / 10000000, decVal % 10000000);
6975 break;
6976 }
0313a2b8
NC		 6977 case 'k':
6978 {
6979 int from = (given & (1 << 7)) ? 32 : 16;
6980 func (stream, "%ld", from - value);
6981 }
6982 break;
8f06b2d8 6983
0313a2b8
NC		 6984 case 'f':
6985 if (value > 7)
6986 func (stream, "#%s", arm_fp_const[value & 7]);
6987 else
6988 func (stream, "f%ld", value);
6989 break;
4146fd53 6990
0313a2b8
NC		 6991 case 'w':
6992 if (width == 2)
6993 func (stream, "%s", iwmmxt_wwnames[value]);
6994 else
6995 func (stream, "%s", iwmmxt_wwssnames[value]);
6996 break;
4146fd53 6997
0313a2b8
NC		 6998 case 'g':
6999 func (stream, "%s", iwmmxt_regnames[value]);
7000 break;
7001 case 'G':
7002 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 7003 break;
8f06b2d8 7004
0313a2b8 7005 case 'x':
d1aaab3c 7006 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 7007 break;
8f06b2d8 7008
33399f07
MGD		 7009 case 'c':
7010 switch (value)
7011 {
7012 case 0:
7013 func (stream, "eq");
7014 break;
7015
7016 case 1:
7017 func (stream, "vs");
7018 break;
7019
7020 case 2:
7021 func (stream, "ge");
7022 break;
7023
7024 case 3:
7025 func (stream, "gt");
7026 break;
7027
7028 default:
7029 func (stream, "??");
7030 break;
7031 }
7032 break;
7033
0313a2b8
NC		 7034 case '`':
7035 c++;
7036 if (value == 0)
7037 func (stream, "%c", *c);
7038 break;
7039 case '\'':
7040 c++;
7041 if (value == ((1ul << width) - 1))
7042 func (stream, "%c", *c);
7043 break;
7044 case '?':
fe56b6ce 7045 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 7046 c += 1 << width;
7047 break;
7048 default:
7049 abort ();
7050 }
dffaa15c
AM		 7051 }
7052 break;
0313a2b8 7053
dffaa15c
AM		 7054 case 'y':
7055 case 'z':
7056 {
7057 int single = *c++ == 'y';
7058 int regno;
8f06b2d8 7059
dffaa15c
AM		 7060 switch (*c)
7061 {
7062 case '4': /* Sm pair */
7063 case '0': /* Sm, Dm */
7064 regno = given & 0x0000000f;
7065 if (single)
7066 {
7067 regno <<= 1;
7068 regno += (given >> 5) & 1;
7069 }
7070 else
7071 regno += ((given >> 5) & 1) << 4;
7072 break;
8f06b2d8 7073
dffaa15c
AM		 7074 case '1': /* Sd, Dd */
7075 regno = (given >> 12) & 0x0000000f;
7076 if (single)
7077 {
7078 regno <<= 1;
7079 regno += (given >> 22) & 1;
7080 }
7081 else
7082 regno += ((given >> 22) & 1) << 4;
7083 break;
7df76b80 7084
dffaa15c
AM		 7085 case '2': /* Sn, Dn */
7086 regno = (given >> 16) & 0x0000000f;
7087 if (single)
7088 {
7089 regno <<= 1;
7090 regno += (given >> 7) & 1;
7091 }
7092 else
7093 regno += ((given >> 7) & 1) << 4;
7094 break;
a7f8487e 7095
dffaa15c
AM		 7096 case '3': /* List */
7097 func (stream, "{");
7098 regno = (given >> 12) & 0x0000000f;
7099 if (single)
7100 {
7101 regno <<= 1;
7102 regno += (given >> 22) & 1;
7103 }
7104 else
7105 regno += ((given >> 22) & 1) << 4;
7106 break;
a7f8487e 7107
dffaa15c
AM		 7108 default:
7109 abort ();
7110 }
0313a2b8 7111
dffaa15c 7112 func (stream, "%c%d", single ? 's' : 'd', regno);
a7f8487e 7113
dffaa15c
AM		 7114 if (*c == '3')
7115 {
7116 int count = given & 0xff;
b34976b6 7117
dffaa15c
AM		 7118 if (single == 0)
7119 count >>= 1;
0313a2b8 7120
dffaa15c
AM		 7121 if (--count)
7122 {
7123 func (stream, "-%c%d",
7124 single ? 's' : 'd',
7125 regno + count);
7126 }
0313a2b8 7127
dffaa15c 7128 func (stream, "}");
0313a2b8 7129 }
dffaa15c
AM		 7130 else if (*c == '4')
7131 func (stream, ", %c%d", single ? 's' : 'd',
7132 regno + 1);
7133 }
7134 break;
b34976b6 7135
dffaa15c
AM		 7136 case 'L':
7137 switch (given & 0x00400100)
0313a2b8 7138 {
dffaa15c
AM		 7139 case 0x00000000: func (stream, "b"); break;
7140 case 0x00400000: func (stream, "h"); break;
7141 case 0x00000100: func (stream, "w"); break;
7142 case 0x00400100: func (stream, "d"); break;
7143 default:
7144 break;
0313a2b8 7145 }
dffaa15c 7146 break;
2d447fca 7147
dffaa15c
AM		 7148 case 'Z':
7149 {
7150 /* given (20, 23) | given (0, 3) */
7151 value = ((given >> 16) & 0xf0) | (given & 0xf);
7152 func (stream, "%d", (int) value);
7153 }
7154 break;
0313a2b8 7155
dffaa15c
AM		 7156 case 'l':
7157 /* This is like the 'A' operator, except that if
7158 the width field "M" is zero, then the offset is
7159 *not* multiplied by four. */
7160 {
7161 int offset = given & 0xff;
7162 int multiplier = (given & 0x00000100) ? 4 : 1;
0313a2b8 7163
dffaa15c 7164 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
05413229 7165
dffaa15c
AM		 7166 if (multiplier > 1)
7167 {
7168 value_in_comment = offset * multiplier;
7169 if (NEGATIVE_BIT_SET)
7170 value_in_comment = - value_in_comment;
7171 }
0313a2b8 7172
dffaa15c
AM		 7173 if (offset)
7174 {
7175 if (PRE_BIT_SET)
7176 func (stream, ", #%s%d]%s",
7177 NEGATIVE_BIT_SET ? "-" : "",
7178 offset * multiplier,
7179 WRITEBACK_BIT_SET ? "!" : "");
7180 else
7181 func (stream, "], #%s%d",
7182 NEGATIVE_BIT_SET ? "-" : "",
7183 offset * multiplier);
7184 }
7185 else
7186 func (stream, "]");
7187 }
7188 break;
2d447fca 7189
dffaa15c
AM		 7190 case 'r':
7191 {
7192 int imm4 = (given >> 4) & 0xf;
7193 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
7194 int ubit = ! NEGATIVE_BIT_SET;
7195 const char *rm = arm_regnames [given & 0xf];
7196 const char *rn = arm_regnames [(given >> 16) & 0xf];
0313a2b8 7197
dffaa15c
AM		 7198 switch (puw_bits)
7199 {
7200 case 1:
7201 case 3:
7202 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
7203 if (imm4)
7204 func (stream, ", lsl #%d", imm4);
7205 break;
0313a2b8 7206
dffaa15c
AM		 7207 case 4:
7208 case 5:
7209 case 6:
7210 case 7:
7211 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
7212 if (imm4 > 0)
7213 func (stream, ", lsl #%d", imm4);
7214 func (stream, "]");
7215 if (puw_bits == 5 || puw_bits == 7)
7216 func (stream, "!");
7217 break;
2d447fca 7218
dffaa15c
AM		 7219 default:
7220 func (stream, "INVALID");
7221 }
7222 }
7223 break;
0313a2b8 7224
dffaa15c
AM		 7225 case 'i':
7226 {
7227 long imm5;
7228 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
7229 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
0313a2b8 7230 }
dffaa15c
AM		 7231 break;
7232
7233 default:
7234 abort ();
252b5132 7235 }
252b5132 7236 }
0313a2b8
NC		 7237 else
7238 func (stream, "%c", *c);
252b5132 7239 }
05413229
NC		 7240
7241 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 7242 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 7243
ff4a8d2b
NC		 7244 if (is_unpredictable)
7245 func (stream, UNPREDICTABLE_INSTRUCTION);
7246
0313a2b8 7247 return TRUE;
252b5132 7248 }
8f06b2d8 7249 return FALSE;
252b5132
RH		 7250}
7251
05413229
NC		 7252/* Decodes and prints ARM addressing modes. Returns the offset
7253 used in the address, if any, if it is worthwhile printing the
7254 offset as a hexadecimal value in a comment at the end of the
7255 line of disassembly. */
7256
7257static signed long
62b3e311
PB		 7258print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
7259{
7260 void *stream = info->stream;
7261 fprintf_ftype func = info->fprintf_func;
f8b960bc 7262 bfd_vma offset = 0;
62b3e311
PB		 7263
7264 if (((given & 0x000f0000) == 0x000f0000)
7265 && ((given & 0x02000000) == 0))
7266 {
05413229 7267 offset = given & 0xfff;
62b3e311
PB		 7268
7269 func (stream, "[pc");
7270
c1e26897 7271 if (PRE_BIT_SET)
62b3e311 7272 {
26d97720
NS		 7273 /* Pre-indexed. Elide offset of positive zero when
7274 non-writeback. */
7275 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 7276 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 7277
7278 if (NEGATIVE_BIT_SET)
7279 offset = -offset;
62b3e311
PB		 7280
7281 offset += pc + 8;
7282
7283 /* Cope with the possibility of write-back
7284 being used. Probably a very dangerous thing
7285 for the programmer to do, but who are we to
7286 argue ? */
26d97720 7287 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 7288 }
c1e26897 7289 else /* Post indexed. */
62b3e311 7290 {
d908c8af 7291 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 7292
c1e26897 7293 /* Ie ignore the offset. */
62b3e311
PB		 7294 offset = pc + 8;
7295 }
7296
7297 func (stream, "\t; ");
7298 info->print_address_func (offset, info);
05413229 7299 offset = 0;
62b3e311
PB		 7300 }
7301 else
7302 {
7303 func (stream, "[%s",
7304 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 7305
7306 if (PRE_BIT_SET)
62b3e311
PB		 7307 {
7308 if ((given & 0x02000000) == 0)
7309 {
26d97720 7310 /* Elide offset of positive zero when non-writeback. */
05413229 7311 offset = given & 0xfff;
26d97720 7312 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 7313 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 7314 }
7315 else
7316 {
26d97720 7317 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 7318 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 7319 }
7320
7321 func (stream, "]%s",
c1e26897 7322 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 7323 }
7324 else
7325 {
7326 if ((given & 0x02000000) == 0)
7327 {
26d97720 7328 /* Always show offset. */
05413229 7329 offset = given & 0xfff;
26d97720 7330 func (stream, "], #%s%d",
d908c8af 7331 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 7332 }
7333 else
7334 {
7335 func (stream, "], %s",
c1e26897 7336 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 7337 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 7338 }
7339 }
84919466
MR		 7340 if (NEGATIVE_BIT_SET)
7341 offset = -offset;
62b3e311 7342 }
05413229
NC		 7343
7344 return (signed long) offset;
62b3e311
PB		 7345}
7346
16980d0b
JB		 7347/* Print one neon instruction on INFO->STREAM.
7348 Return TRUE if the instuction matched, FALSE if this is not a
7349 recognised neon instruction. */
7350
7351static bfd_boolean
7352print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
7353{
7354 const struct opcode32 *insn;
7355 void *stream = info->stream;
7356 fprintf_ftype func = info->fprintf_func;
7357
7358 if (thumb)
7359 {
7360 if ((given & 0xef000000) == 0xef000000)
7361 {
0313a2b8 7362 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 7363 unsigned long bit28 = given & (1 << 28);
7364
7365 given &= 0x00ffffff;
7366 if (bit28)
7367 given |= 0xf3000000;
7368 else
7369 given |= 0xf2000000;
7370 }
7371 else if ((given & 0xff000000) == 0xf9000000)
7372 given ^= 0xf9000000 ^ 0xf4000000;
9743db03
AV		 7373 /* vdup is also a valid neon instruction. */
7374 else if ((given & 0xff910f5f) != 0xee800b10)
16980d0b
JB		 7375 return FALSE;
7376 }
43e65147 7377
16980d0b
JB		 7378 for (insn = neon_opcodes; insn->assembler; insn++)
7379 {
7380 if ((given & insn->mask) == insn->value)
7381 {
05413229 7382 signed long value_in_comment = 0;
e2efe87d 7383 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 7384 const char *c;
7385
7386 for (c = insn->assembler; *c; c++)
7387 {
7388 if (*c == '%')
7389 {
7390 switch (*++c)
7391 {
7392 case '%':
7393 func (stream, "%%");
7394 break;
7395
e2efe87d
MGD		 7396 case 'u':
7397 if (thumb && ifthen_state)
7398 is_unpredictable = TRUE;
7399
7400 /* Fall through. */
c22aaad1
PB		 7401 case 'c':
7402 if (thumb && ifthen_state)
7403 func (stream, "%s", arm_conditional[IFTHEN_COND]);
7404 break;
7405
16980d0b
JB		 7406 case 'A':
7407 {
43e65147 7408 static const unsigned char enc[16] =
16980d0b
JB		 7409 {
7410 0x4, 0x14, /* st4 0,1 */
7411 0x4, /* st1 2 */
7412 0x4, /* st2 3 */
7413 0x3, /* st3 4 */
7414 0x13, /* st3 5 */
7415 0x3, /* st1 6 */
7416 0x1, /* st1 7 */
7417 0x2, /* st2 8 */
7418 0x12, /* st2 9 */
7419 0x2, /* st1 10 */
7420 0, 0, 0, 0, 0
7421 };
7422 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
7423 int rn = ((given >> 16) & 0xf);
7424 int rm = ((given >> 0) & 0xf);
7425 int align = ((given >> 4) & 0x3);
7426 int type = ((given >> 8) & 0xf);
7427 int n = enc[type] & 0xf;
7428 int stride = (enc[type] >> 4) + 1;
7429 int ix;
43e65147 7430
16980d0b
JB		 7431 func (stream, "{");
7432 if (stride > 1)
7433 for (ix = 0; ix != n; ix++)
7434 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
7435 else if (n == 1)
7436 func (stream, "d%d", rd);
7437 else
7438 func (stream, "d%d-d%d", rd, rd + n - 1);
7439 func (stream, "}, [%s", arm_regnames[rn]);
7440 if (align)
8e560766 7441 func (stream, " :%d", 32 << align);
16980d0b
JB		 7442 func (stream, "]");
7443 if (rm == 0xd)
7444 func (stream, "!");
7445 else if (rm != 0xf)
7446 func (stream, ", %s", arm_regnames[rm]);
7447 }
7448 break;
43e65147 7449
16980d0b
JB		 7450 case 'B':
7451 {
7452 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
7453 int rn = ((given >> 16) & 0xf);
7454 int rm = ((given >> 0) & 0xf);
7455 int idx_align = ((given >> 4) & 0xf);
7456 int align = 0;
7457 int size = ((given >> 10) & 0x3);
7458 int idx = idx_align >> (size + 1);
7459 int length = ((given >> 8) & 3) + 1;
7460 int stride = 1;
7461 int i;
7462
7463 if (length > 1 && size > 0)
7464 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 7465
16980d0b
JB		 7466 switch (length)
7467 {
7468 case 1:
7469 {
7470 int amask = (1 << size) - 1;
7471 if ((idx_align & (1 << size)) != 0)
7472 return FALSE;
7473 if (size > 0)
7474 {
7475 if ((idx_align & amask) == amask)
7476 align = 8 << size;
7477 else if ((idx_align & amask) != 0)
7478 return FALSE;
7479 }
7480 }
7481 break;
43e65147 7482
16980d0b
JB		 7483 case 2:
7484 if (size == 2 && (idx_align & 2) != 0)
7485 return FALSE;
7486 align = (idx_align & 1) ? 16 << size : 0;
7487 break;
43e65147 7488
16980d0b
JB		 7489 case 3:
7490 if ((size == 2 && (idx_align & 3) != 0)
7491 || (idx_align & 1) != 0)
7492 return FALSE;
7493 break;
43e65147 7494
16980d0b
JB		 7495 case 4:
7496 if (size == 2)
7497 {
7498 if ((idx_align & 3) == 3)
7499 return FALSE;
7500 align = (idx_align & 3) * 64;
7501 }
7502 else
7503 align = (idx_align & 1) ? 32 << size : 0;
7504 break;
43e65147 7505
16980d0b
JB		 7506 default:
7507 abort ();
7508 }
43e65147 7509
16980d0b
JB		 7510 func (stream, "{");
7511 for (i = 0; i < length; i++)
7512 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
7513 rd + i * stride, idx);
7514 func (stream, "}, [%s", arm_regnames[rn]);
7515 if (align)
8e560766 7516 func (stream, " :%d", align);
16980d0b
JB		 7517 func (stream, "]");
7518 if (rm == 0xd)
7519 func (stream, "!");
7520 else if (rm != 0xf)
7521 func (stream, ", %s", arm_regnames[rm]);
7522 }
7523 break;
43e65147 7524
16980d0b
JB		 7525 case 'C':
7526 {
7527 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
7528 int rn = ((given >> 16) & 0xf);
7529 int rm = ((given >> 0) & 0xf);
7530 int align = ((given >> 4) & 0x1);
7531 int size = ((given >> 6) & 0x3);
7532 int type = ((given >> 8) & 0x3);
7533 int n = type + 1;
7534 int stride = ((given >> 5) & 0x1);
7535 int ix;
43e65147 7536
16980d0b
JB		 7537 if (stride && (n == 1))
7538 n++;
7539 else
7540 stride++;
43e65147 7541
16980d0b
JB		 7542 func (stream, "{");
7543 if (stride > 1)
7544 for (ix = 0; ix != n; ix++)
7545 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
7546 else if (n == 1)
7547 func (stream, "d%d[]", rd);
7548 else
7549 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
7550 func (stream, "}, [%s", arm_regnames[rn]);
7551 if (align)
7552 {
91d6fa6a 7553 align = (8 * (type + 1)) << size;
16980d0b
JB		 7554 if (type == 3)
7555 align = (size > 1) ? align >> 1 : align;
7556 if (type == 2 || (type == 0 && !size))
8e560766 7557 func (stream, " :<bad align %d>", align);
16980d0b 7558 else
8e560766 7559 func (stream, " :%d", align);
16980d0b
JB		 7560 }
7561 func (stream, "]");
7562 if (rm == 0xd)
7563 func (stream, "!");
7564 else if (rm != 0xf)
7565 func (stream, ", %s", arm_regnames[rm]);
7566 }
7567 break;
43e65147 7568
16980d0b
JB		 7569 case 'D':
7570 {
7571 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
7572 int size = (given >> 20) & 3;
7573 int reg = raw_reg & ((4 << size) - 1);
7574 int ix = raw_reg >> size >> 2;
43e65147 7575
16980d0b
JB		 7576 func (stream, "d%d[%d]", reg, ix);
7577 }
7578 break;
43e65147 7579
16980d0b 7580 case 'E':
fe56b6ce 7581 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 7582 {
7583 int bits = 0;
7584 int cmode = (given >> 8) & 0xf;
7585 int op = (given >> 5) & 0x1;
7586 unsigned long value = 0, hival = 0;
7587 unsigned shift;
7588 int size = 0;
0dbde4cf 7589 int isfloat = 0;
43e65147 7590
16980d0b
JB		 7591 bits |= ((given >> 24) & 1) << 7;
7592 bits |= ((given >> 16) & 7) << 4;
7593 bits |= ((given >> 0) & 15) << 0;
43e65147 7594
16980d0b
JB		 7595 if (cmode < 8)
7596 {
7597 shift = (cmode >> 1) & 3;
fe56b6ce 7598 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 7599 size = 32;
7600 }
7601 else if (cmode < 12)
7602 {
7603 shift = (cmode >> 1) & 1;
fe56b6ce 7604 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 7605 size = 16;
7606 }
7607 else if (cmode < 14)
7608 {
7609 shift = (cmode & 1) + 1;
fe56b6ce 7610 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 7611 value |= (1ul << (8 * shift)) - 1;
7612 size = 32;
7613 }
7614 else if (cmode == 14)
7615 {
7616 if (op)
7617 {
fe56b6ce 7618 /* Bit replication into bytes. */
16980d0b
JB		 7619 int ix;
7620 unsigned long mask;
43e65147 7621
16980d0b
JB		 7622 value = 0;
7623 hival = 0;
7624 for (ix = 7; ix >= 0; ix--)
7625 {
7626 mask = ((bits >> ix) & 1) ? 0xff : 0;
7627 if (ix <= 3)
7628 value = (value << 8) | mask;
7629 else
7630 hival = (hival << 8) | mask;
7631 }
7632 size = 64;
7633 }
7634 else
7635 {
fe56b6ce
NC		 7636 /* Byte replication. */
7637 value = (unsigned long) bits;
16980d0b
JB		 7638 size = 8;
7639 }
7640 }
7641 else if (!op)
7642 {
fe56b6ce 7643 /* Floating point encoding. */
16980d0b 7644 int tmp;
43e65147 7645
fe56b6ce
NC		 7646 value = (unsigned long) (bits & 0x7f) << 19;
7647 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 7648 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 7649 value |= (unsigned long) tmp << 24;
16980d0b 7650 size = 32;
0dbde4cf 7651 isfloat = 1;
16980d0b
JB		 7652 }
7653 else
7654 {
7655 func (stream, "<illegal constant %.8x:%x:%x>",
7656 bits, cmode, op);
7657 size = 32;
7658 break;
7659 }
7660 switch (size)
7661 {
7662 case 8:
7663 func (stream, "#%ld\t; 0x%.2lx", value, value);
7664 break;
43e65147 7665
16980d0b
JB		 7666 case 16:
7667 func (stream, "#%ld\t; 0x%.4lx", value, value);
7668 break;
7669
7670 case 32:
0dbde4cf
JB		 7671 if (isfloat)
7672 {
7673 unsigned char valbytes[4];
7674 double fvalue;
43e65147 7675
0dbde4cf
JB		 7676 /* Do this a byte at a time so we don't have to
7677 worry about the host's endianness. */
7678 valbytes[0] = value & 0xff;
7679 valbytes[1] = (value >> 8) & 0xff;
7680 valbytes[2] = (value >> 16) & 0xff;
7681 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 7682
7683 floatformat_to_double
c1e26897
NC		 7684 (& floatformat_ieee_single_little, valbytes,
7685 & fvalue);
43e65147 7686
0dbde4cf
JB		 7687 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
7688 value);
7689 }
7690 else
4e9d3b81 7691 func (stream, "#%ld\t; 0x%.8lx",
43e65147 7692 (long) (((value & 0x80000000L) != 0)
9d82ec38 7693 ? value | ~0xffffffffL : value),
c1e26897 7694 value);
16980d0b
JB		 7695 break;
7696
7697 case 64:
7698 func (stream, "#0x%.8lx%.8lx", hival, value);
7699 break;
43e65147 7700
16980d0b
JB		 7701 default:
7702 abort ();
7703 }
7704 }
7705 break;
43e65147 7706
16980d0b
JB		 7707 case 'F':
7708 {
7709 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
7710 int num = (given >> 8) & 0x3;
43e65147 7711
16980d0b
JB		 7712 if (!num)
7713 func (stream, "{d%d}", regno);
7714 else if (num + regno >= 32)
7715 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
7716 else
7717 func (stream, "{d%d-d%d}", regno, regno + num);
7718 }
7719 break;
7e8e6784 7720
16980d0b
JB		 7721
7722 case '0': case '1': case '2': case '3': case '4':
7723 case '5': case '6': case '7': case '8': case '9':
7724 {
7725 int width;
7726 unsigned long value;
7727
7728 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 7729
16980d0b
JB		 7730 switch (*c)
7731 {
7732 case 'r':
7733 func (stream, "%s", arm_regnames[value]);
7734 break;
7735 case 'd':
7736 func (stream, "%ld", value);
05413229 7737 value_in_comment = value;
16980d0b
JB		 7738 break;
7739 case 'e':
7740 func (stream, "%ld", (1ul << width) - value);
7741 break;
43e65147 7742
16980d0b
JB		 7743 case 'S':
7744 case 'T':
7745 case 'U':
05413229 7746 /* Various width encodings. */
16980d0b
JB		 7747 {
7748 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
7749 int limit;
7750 unsigned low, high;
7751
7752 c++;
7753 if (*c >= '0' && *c <= '9')
7754 limit = *c - '0';
7755 else if (*c >= 'a' && *c <= 'f')
7756 limit = *c - 'a' + 10;
7757 else
7758 abort ();
7759 low = limit >> 2;
7760 high = limit & 3;
7761
7762 if (value < low || value > high)
7763 func (stream, "<illegal width %d>", base << value);
7764 else
7765 func (stream, "%d", base << value);
7766 }
7767 break;
7768 case 'R':
7769 if (given & (1 << 6))
7770 goto Q;
7771 /* FALLTHROUGH */
7772 case 'D':
7773 func (stream, "d%ld", value);
7774 break;
7775 case 'Q':
7776 Q:
7777 if (value & 1)
7778 func (stream, "<illegal reg q%ld.5>", value >> 1);
7779 else
7780 func (stream, "q%ld", value >> 1);
7781 break;
43e65147 7782
16980d0b
JB		 7783 case '`':
7784 c++;
7785 if (value == 0)
7786 func (stream, "%c", *c);
7787 break;
7788 case '\'':
7789 c++;
7790 if (value == ((1ul << width) - 1))
7791 func (stream, "%c", *c);
7792 break;
7793 case '?':
fe56b6ce 7794 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 7795 c += 1 << width;
7796 break;
7797 default:
7798 abort ();
7799 }
16980d0b 7800 }
dffaa15c
AM		 7801 break;
7802
7803 default:
7804 abort ();
16980d0b
JB		 7805 }
7806 }
7807 else
7808 func (stream, "%c", *c);
7809 }
05413229
NC		 7810
7811 if (value_in_comment > 32 || value_in_comment < -16)
7812 func (stream, "\t; 0x%lx", value_in_comment);
7813
e2efe87d
MGD		 7814 if (is_unpredictable)
7815 func (stream, UNPREDICTABLE_INSTRUCTION);
7816
16980d0b
JB		 7817 return TRUE;
7818 }
7819 }
7820 return FALSE;
7821}
7822
73cd51e5
AV		 7823/* Print one mve instruction on INFO->STREAM.
7824 Return TRUE if the instuction matched, FALSE if this is not a
7825 recognised mve instruction. */
7826
7827static bfd_boolean
7828print_insn_mve (struct disassemble_info *info, long given)
7829{
7830 const struct mopcode32 *insn;
7831 void *stream = info->stream;
7832 fprintf_ftype func = info->fprintf_func;
7833
7834 for (insn = mve_opcodes; insn->assembler; insn++)
7835 {
7836 if (((given & insn->mask) == insn->value)
7837 && !is_mve_encoding_conflict (given, insn->mve_op))
7838 {
7839 signed long value_in_comment = 0;
7840 bfd_boolean is_unpredictable = FALSE;
7841 bfd_boolean is_undefined = FALSE;
7842 const char *c;
7843 enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
7844 enum mve_undefined undefined_cond = UNDEF_NONE;
7845
7846 /* Most vector mve instruction are illegal in a it block.
7847 There are a few exceptions; check for them. */
7848 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
7849 {
7850 is_unpredictable = TRUE;
7851 unpredictable_cond = UNPRED_IT_BLOCK;
7852 }
7853 else if (is_mve_unpredictable (given, insn->mve_op,
7854 &unpredictable_cond))
7855 is_unpredictable = TRUE;
7856
7857 if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
7858 is_undefined = TRUE;
7859
7860 for (c = insn->assembler; *c; c++)
7861 {
7862 if (*c == '%')
7863 {
7864 switch (*++c)
7865 {
7866 case '%':
7867 func (stream, "%%");
7868 break;
7869
ef1576a1
AV		 7870 case 'a':
7871 /* Don't print anything for '+' as it is implied. */
7872 if (arm_decode_field (given, 23, 23) == 0)
7873 func (stream, "-");
7874 break;
7875
143275ea
AV		 7876 case 'c':
7877 if (ifthen_state)
7878 func (stream, "%s", arm_conditional[IFTHEN_COND]);
7879 break;
7880
aef6d006
AV		 7881 case 'd':
7882 print_mve_vld_str_addr (info, given, insn->mve_op);
7883 break;
7884
143275ea
AV		 7885 case 'i':
7886 {
7887 long mve_mask = mve_extract_pred_mask (given);
7888 func (stream, "%s", mve_predicatenames[mve_mask]);
7889 }
7890 break;
7891
7892 case 'n':
7893 print_vec_condition (info, given, insn->mve_op);
7894 break;
7895
ef1576a1
AV		 7896 case 'o':
7897 if (arm_decode_field (given, 0, 0) == 1)
7898 {
7899 unsigned long size
7900 = arm_decode_field (given, 4, 4)
7901 | (arm_decode_field (given, 6, 6) << 1);
7902
7903 func (stream, ", uxtw #%lu", size);
7904 }
7905 break;
7906
bf0b396d
AV		 7907 case 'm':
7908 print_mve_rounding_mode (info, given, insn->mve_op);
7909 break;
7910
7911 case 's':
7912 print_mve_vcvt_size (info, given, insn->mve_op);
7913 break;
7914
aef6d006
AV		 7915 case 'u':
7916 {
c507f10b
AV		 7917 unsigned long op1 = arm_decode_field (given, 21, 22);
7918
7919 if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
7920 {
7921 /* Check for signed. */
7922 if (arm_decode_field (given, 23, 23) == 0)
7923 {
7924 /* We don't print 's' for S32. */
7925 if ((arm_decode_field (given, 5, 6) == 0)
7926 && ((op1 == 0) || (op1 == 1)))
7927 ;
7928 else
7929 func (stream, "s");
7930 }
7931 else
7932 func (stream, "u");
7933 }
aef6d006 7934 else
c507f10b
AV		 7935 {
7936 if (arm_decode_field (given, 28, 28) == 0)
7937 func (stream, "s");
7938 else
7939 func (stream, "u");
7940 }
aef6d006 7941 }
ef1576a1 7942 break;
aef6d006 7943
143275ea
AV		 7944 case 'v':
7945 print_instruction_predicate (info);
7946 break;
7947
04d54ace
AV		 7948 case 'w':
7949 if (arm_decode_field (given, 21, 21) == 1)
7950 func (stream, "!");
7951 break;
7952
7953 case 'B':
7954 print_mve_register_blocks (info, given, insn->mve_op);
7955 break;
7956
c507f10b
AV		 7957 case 'E':
7958 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
7959
7960 print_simd_imm8 (info, given, 28, insn);
7961 break;
7962
7963 case 'N':
7964 print_mve_vmov_index (info, given);
7965 break;
7966
14925797
AV		 7967 case 'T':
7968 if (arm_decode_field (given, 12, 12) == 0)
7969 func (stream, "b");
7970 else
7971 func (stream, "t");
7972 break;
7973
d3b63143
AV		 7974 case 'X':
7975 if (arm_decode_field (given, 12, 12) == 1)
7976 func (stream, "x");
7977 break;
7978
143275ea
AV		 7979 case '0': case '1': case '2': case '3': case '4':
7980 case '5': case '6': case '7': case '8': case '9':
7981 {
7982 int width;
7983 unsigned long value;
7984
7985 c = arm_decode_bitfield (c, given, &value, &width);
7986
7987 switch (*c)
7988 {
7989 case 'Z':
7990 if (value == 13)
7991 is_unpredictable = TRUE;
7992 else if (value == 15)
7993 func (stream, "zr");
7994 else
7995 func (stream, "%s", arm_regnames[value]);
7996 break;
7997 case 's':
7998 print_mve_size (info,
7999 value,
8000 insn->mve_op);
8001 break;
d3b63143
AV		 8002 case 'A':
8003 if (value == 1)
8004 func (stream, "a");
8005 break;
1c8f2df8
AV		 8006 case 'h':
8007 {
8008 unsigned int odd_reg = (value << 1) | 1;
8009 func (stream, "%s", arm_regnames[odd_reg]);
8010 }
8011 break;
ef1576a1
AV		 8012 case 'i':
8013 {
8014 unsigned long imm
8015 = arm_decode_field (given, 0, 6);
8016 unsigned long mod_imm = imm;
8017
8018 switch (insn->mve_op)
8019 {
8020 case MVE_VLDRW_GATHER_T5:
8021 case MVE_VSTRW_SCATTER_T5:
8022 mod_imm = mod_imm << 2;
8023 break;
8024 case MVE_VSTRD_SCATTER_T6:
8025 case MVE_VLDRD_GATHER_T6:
8026 mod_imm = mod_imm << 3;
8027 break;
8028
8029 default:
8030 break;
8031 }
8032
8033 func (stream, "%lu", mod_imm);
8034 }
8035 break;
bf0b396d
AV		 8036 case 'k':
8037 func (stream, "%lu", 64 - value);
8038 break;
1c8f2df8
AV		 8039 case 'l':
8040 {
8041 unsigned int even_reg = value << 1;
8042 func (stream, "%s", arm_regnames[even_reg]);
8043 }
8044 break;
8045 case 'u':
8046 switch (value)
8047 {
8048 case 0:
8049 func (stream, "1");
8050 break;
8051 case 1:
8052 func (stream, "2");
8053 break;
8054 case 2:
8055 func (stream, "4");
8056 break;
8057 case 3:
8058 func (stream, "8");
8059 break;
8060 default:
8061 break;
8062 }
8063 break;
9743db03
AV		 8064 case 'r':
8065 func (stream, "%s", arm_regnames[value]);
8066 break;
04d54ace
AV		 8067 case 'd':
8068 func (stream, "%ld", value);
8069 value_in_comment = value;
8070 break;
c507f10b
AV		 8071 case 'F':
8072 func (stream, "s%ld", value);
8073 break;
143275ea
AV		 8074 case 'Q':
8075 if (value & 0x8)
8076 func (stream, "<illegal reg q%ld.5>", value);
8077 else
8078 func (stream, "q%ld", value);
8079 break;
c507f10b
AV		 8080 case 'x':
8081 func (stream, "0x%08lx", value);
8082 break;
143275ea
AV		 8083 default:
8084 abort ();
8085 }
8086 break;
8087 default:
8088 abort ();
8089 }
73cd51e5
AV		 8090 }
8091 }
8092 else
8093 func (stream, "%c", *c);
8094 }
8095
8096 if (value_in_comment > 32 || value_in_comment < -16)
8097 func (stream, "\t; 0x%lx", value_in_comment);
8098
8099 if (is_unpredictable)
8100 print_mve_unpredictable (info, unpredictable_cond);
8101
8102 if (is_undefined)
8103 print_mve_undefined (info, undefined_cond);
8104
143275ea
AV		 8105 if ((vpt_block_state.in_vpt_block == FALSE)
8106 && !ifthen_state
8107 && (is_vpt_instruction (given) == TRUE))
8108 mark_inside_vpt_block (given);
8109 else if (vpt_block_state.in_vpt_block == TRUE)
8110 update_vpt_block_state ();
8111
73cd51e5
AV		 8112 return TRUE;
8113 }
8114 }
8115 return FALSE;
8116}
8117
8118
90ec0d68
MGD		 8119/* Return the name of a v7A special register. */
8120
43e65147 8121static const char *
90ec0d68
MGD		 8122banked_regname (unsigned reg)
8123{
8124 switch (reg)
8125 {
8126 case 15: return "CPSR";
43e65147 8127 case 32: return "R8_usr";
90ec0d68
MGD		 8128 case 33: return "R9_usr";
8129 case 34: return "R10_usr";
8130 case 35: return "R11_usr";
8131 case 36: return "R12_usr";
8132 case 37: return "SP_usr";
8133 case 38: return "LR_usr";
43e65147 8134 case 40: return "R8_fiq";
90ec0d68
MGD		 8135 case 41: return "R9_fiq";
8136 case 42: return "R10_fiq";
8137 case 43: return "R11_fiq";
8138 case 44: return "R12_fiq";
8139 case 45: return "SP_fiq";
8140 case 46: return "LR_fiq";
8141 case 48: return "LR_irq";
8142 case 49: return "SP_irq";
8143 case 50: return "LR_svc";
8144 case 51: return "SP_svc";
8145 case 52: return "LR_abt";
8146 case 53: return "SP_abt";
8147 case 54: return "LR_und";
8148 case 55: return "SP_und";
8149 case 60: return "LR_mon";
8150 case 61: return "SP_mon";
8151 case 62: return "ELR_hyp";
8152 case 63: return "SP_hyp";
8153 case 79: return "SPSR";
8154 case 110: return "SPSR_fiq";
8155 case 112: return "SPSR_irq";
8156 case 114: return "SPSR_svc";
8157 case 116: return "SPSR_abt";
8158 case 118: return "SPSR_und";
8159 case 124: return "SPSR_mon";
8160 case 126: return "SPSR_hyp";
8161 default: return NULL;
8162 }
8163}
8164
e797f7e0
MGD		 8165/* Return the name of the DMB/DSB option. */
8166static const char *
8167data_barrier_option (unsigned option)
8168{
8169 switch (option & 0xf)
8170 {
8171 case 0xf: return "sy";
8172 case 0xe: return "st";
8173 case 0xd: return "ld";
8174 case 0xb: return "ish";
8175 case 0xa: return "ishst";
8176 case 0x9: return "ishld";
8177 case 0x7: return "un";
8178 case 0x6: return "unst";
8179 case 0x5: return "nshld";
8180 case 0x3: return "osh";
8181 case 0x2: return "oshst";
8182 case 0x1: return "oshld";
8183 default: return NULL;
8184 }
8185}
8186
4a5329c6
ZW		 8187/* Print one ARM instruction from PC on INFO->STREAM. */
8188
8189static void
8190print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 8191{
6b5d3a4d 8192 const struct opcode32 *insn;
6a51a8a8 8193 void *stream = info->stream;
6b5d3a4d 8194 fprintf_ftype func = info->fprintf_func;
b0e28b39 8195 struct arm_private_data *private_data = info->private_data;
252b5132 8196
16980d0b
JB		 8197 if (print_insn_coprocessor (pc, info, given, FALSE))
8198 return;
8199
8200 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 8201 return;
8202
252b5132
RH		 8203 for (insn = arm_opcodes; insn->assembler; insn++)
8204 {
0313a2b8
NC		 8205 if ((given & insn->mask) != insn->value)
8206 continue;
823d2571
TG		 8207
8208 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 8209 continue;
8210
8211 /* Special case: an instruction with all bits set in the condition field
8212 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
8213 or by the catchall at the end of the table. */
8214 if ((given & 0xF0000000) != 0xF0000000
8215 || (insn->mask & 0xF0000000) == 0xF0000000
8216 || (insn->mask == 0 && insn->value == 0))
252b5132 8217 {
ff4a8d2b
NC		 8218 unsigned long u_reg = 16;
8219 unsigned long U_reg = 16;
ab8e2090 8220 bfd_boolean is_unpredictable = FALSE;
05413229 8221 signed long value_in_comment = 0;
6b5d3a4d 8222 const char *c;
b34976b6 8223
252b5132
RH		 8224 for (c = insn->assembler; *c; c++)
8225 {
8226 if (*c == '%')
8227 {
c1e26897
NC		 8228 bfd_boolean allow_unpredictable = FALSE;
8229
252b5132
RH		 8230 switch (*++c)
8231 {
8232 case '%':
8233 func (stream, "%%");
8234 break;
8235
8236 case 'a':
05413229 8237 value_in_comment = print_arm_address (pc, info, given);
62b3e311 8238 break;
252b5132 8239
62b3e311
PB		 8240 case 'P':
8241 /* Set P address bit and use normal address
8242 printing routine. */
c1e26897 8243 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 8244 break;
8245
c1e26897
NC		 8246 case 'S':
8247 allow_unpredictable = TRUE;
1a0670f3 8248 /* Fall through. */
252b5132
RH		 8249 case 's':
8250 if ((given & 0x004f0000) == 0x004f0000)
8251 {
58efb6c0 8252 /* PC relative with immediate offset. */
f8b960bc 8253 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 8254
aefd8a40
NC		 8255 if (PRE_BIT_SET)
8256 {
26d97720
NS		 8257 /* Elide positive zero offset. */
8258 if (offset || NEGATIVE_BIT_SET)
8259 func (stream, "[pc, #%s%d]\t; ",
d908c8af 8260 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 8261 else
26d97720
NS		 8262 func (stream, "[pc]\t; ");
8263 if (NEGATIVE_BIT_SET)
8264 offset = -offset;
aefd8a40
NC		 8265 info->print_address_func (offset + pc + 8, info);
8266 }
8267 else
8268 {
26d97720
NS		 8269 /* Always show the offset. */
8270 func (stream, "[pc], #%s%d",
d908c8af 8271 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 8272 if (! allow_unpredictable)
8273 is_unpredictable = TRUE;
aefd8a40 8274 }
252b5132
RH		 8275 }
8276 else
8277 {
fe56b6ce
NC		 8278 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
8279
b34976b6 8280 func (stream, "[%s",
252b5132 8281 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 8282
c1e26897 8283 if (PRE_BIT_SET)
252b5132 8284 {
c1e26897 8285 if (IMMEDIATE_BIT_SET)
252b5132 8286 {
26d97720
NS		 8287 /* Elide offset for non-writeback
8288 positive zero. */
8289 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
8290 || offset)
8291 func (stream, ", #%s%d",
8292 NEGATIVE_BIT_SET ? "-" : "", offset);
8293
8294 if (NEGATIVE_BIT_SET)
8295 offset = -offset;
945ee430 8296
fe56b6ce 8297 value_in_comment = offset;
252b5132 8298 }
945ee430 8299 else
ff4a8d2b
NC		 8300 {
8301 /* Register Offset or Register Pre-Indexed. */
8302 func (stream, ", %s%s",
8303 NEGATIVE_BIT_SET ? "-" : "",
8304 arm_regnames[given & 0xf]);
8305
8306 /* Writing back to the register that is the source/
8307 destination of the load/store is unpredictable. */
8308 if (! allow_unpredictable
8309 && WRITEBACK_BIT_SET
8310 && ((given & 0xf) == ((given >> 12) & 0xf)))
8311 is_unpredictable = TRUE;
8312 }
252b5132 8313
b34976b6 8314 func (stream, "]%s",
c1e26897 8315 WRITEBACK_BIT_SET ? "!" : "");
252b5132 8316 }
945ee430 8317 else
252b5132 8318 {
c1e26897 8319 if (IMMEDIATE_BIT_SET)
252b5132 8320 {
945ee430 8321 /* Immediate Post-indexed. */
aefd8a40 8322 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 8323 func (stream, "], #%s%d",
8324 NEGATIVE_BIT_SET ? "-" : "", offset);
8325 if (NEGATIVE_BIT_SET)
8326 offset = -offset;
fe56b6ce 8327 value_in_comment = offset;
252b5132 8328 }
945ee430 8329 else
ff4a8d2b
NC		 8330 {
8331 /* Register Post-indexed. */
8332 func (stream, "], %s%s",
8333 NEGATIVE_BIT_SET ? "-" : "",
8334 arm_regnames[given & 0xf]);
8335
8336 /* Writing back to the register that is the source/
8337 destination of the load/store is unpredictable. */
8338 if (! allow_unpredictable
8339 && (given & 0xf) == ((given >> 12) & 0xf))
8340 is_unpredictable = TRUE;
8341 }
c1e26897 8342
07a28fab
NC		 8343 if (! allow_unpredictable)
8344 {
8345 /* Writeback is automatically implied by post- addressing.
8346 Setting the W bit is unnecessary and ARM specify it as
8347 being unpredictable. */
8348 if (WRITEBACK_BIT_SET
8349 /* Specifying the PC register as the post-indexed
8350 registers is also unpredictable. */
ab8e2090
NC		 8351 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
8352 is_unpredictable = TRUE;
07a28fab 8353 }
252b5132
RH		 8354 }
8355 }
8356 break;
b34976b6 8357
252b5132 8358 case 'b':
6b5d3a4d 8359 {
f8b960bc 8360 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
05413229 8361 info->print_address_func (disp * 4 + pc + 8, info);
6b5d3a4d 8362 }
252b5132
RH		 8363 break;
8364
8365 case 'c':
c22aaad1
PB		 8366 if (((given >> 28) & 0xf) != 0xe)
8367 func (stream, "%s",
8368 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 8369 break;
8370
8371 case 'm':
8372 {
8373 int started = 0;
8374 int reg;
8375
8376 func (stream, "{");
8377 for (reg = 0; reg < 16; reg++)
8378 if ((given & (1 << reg)) != 0)
8379 {
8380 if (started)
8381 func (stream, ", ");
8382 started = 1;
8383 func (stream, "%s", arm_regnames[reg]);
8384 }
8385 func (stream, "}");
ab8e2090
NC		 8386 if (! started)
8387 is_unpredictable = TRUE;
252b5132
RH		 8388 }
8389 break;
8390
37b37b2d 8391 case 'q':
78c66db8 8392 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 8393 break;
8394
252b5132
RH		 8395 case 'o':
8396 if ((given & 0x02000000) != 0)
8397 {
a415b1cd
JB		 8398 unsigned int rotate = (given & 0xf00) >> 7;
8399 unsigned int immed = (given & 0xff);
8400 unsigned int a, i;
8401
8402 a = (((immed << (32 - rotate))
8403 | (immed >> rotate)) & 0xffffffff);
8404 /* If there is another encoding with smaller rotate,
8405 the rotate should be specified directly. */
8406 for (i = 0; i < 32; i += 2)
8407 if ((a << i | a >> (32 - i)) <= 0xff)
8408 break;
8409
8410 if (i != rotate)
8411 func (stream, "#%d, %d", immed, rotate);
8412 else
8413 func (stream, "#%d", a);
8414 value_in_comment = a;
252b5132
RH		 8415 }
8416 else
78c66db8 8417 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 8418 break;
8419
8420 case 'p':
8421 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 8422 {
823d2571
TG		 8423 arm_feature_set arm_ext_v6 =
8424 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
8425
aefd8a40
NC		 8426 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
8427 mechanism for setting PSR flag bits. They are
8428 obsolete in V6 onwards. */
823d2571
TG		 8429 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
8430 arm_ext_v6))
aefd8a40 8431 func (stream, "p");
4ab90a7a
AV		 8432 else
8433 is_unpredictable = TRUE;
aefd8a40 8434 }
252b5132
RH		 8435 break;
8436
8437 case 't':
8438 if ((given & 0x01200000) == 0x00200000)
8439 func (stream, "t");
8440 break;
8441
252b5132 8442 case 'A':
05413229
NC		 8443 {
8444 int offset = given & 0xff;
f02232aa 8445
05413229 8446 value_in_comment = offset * 4;
c1e26897 8447 if (NEGATIVE_BIT_SET)
05413229 8448 value_in_comment = - value_in_comment;
f02232aa 8449
05413229 8450 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 8451
c1e26897 8452 if (PRE_BIT_SET)
05413229
NC		 8453 {
8454 if (offset)
fe56b6ce 8455 func (stream, ", #%d]%s",
d908c8af 8456 (int) value_in_comment,
c1e26897 8457 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 8458 else
8459 func (stream, "]");
8460 }
8461 else
8462 {
8463 func (stream, "]");
f02232aa 8464
c1e26897 8465 if (WRITEBACK_BIT_SET)
05413229
NC		 8466 {
8467 if (offset)
d908c8af 8468 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 8469 }
8470 else
fe56b6ce 8471 {
d908c8af 8472 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 8473 value_in_comment = offset;
8474 }
05413229
NC		 8475 }
8476 }
252b5132
RH		 8477 break;
8478
077b8428
NC		 8479 case 'B':
8480 /* Print ARM V5 BLX(1) address: pc+25 bits. */
8481 {
8482 bfd_vma address;
8483 bfd_vma offset = 0;
b34976b6 8484
c1e26897 8485 if (! NEGATIVE_BIT_SET)
077b8428
NC		 8486 /* Is signed, hi bits should be ones. */
8487 offset = (-1) ^ 0x00ffffff;
8488
8489 /* Offset is (SignExtend(offset field)<<2). */
8490 offset += given & 0x00ffffff;
8491 offset <<= 2;
8492 address = offset + pc + 8;
b34976b6 8493
8f06b2d8
PB		 8494 if (given & 0x01000000)
8495 /* H bit allows addressing to 2-byte boundaries. */
8496 address += 2;
b1ee46c5 8497
8f06b2d8 8498 info->print_address_func (address, info);
b1ee46c5 8499 }
b1ee46c5
AH		 8500 break;
8501
252b5132 8502 case 'C':
90ec0d68
MGD		 8503 if ((given & 0x02000200) == 0x200)
8504 {
8505 const char * name;
8506 unsigned sysm = (given & 0x004f0000) >> 16;
8507
8508 sysm |= (given & 0x300) >> 4;
8509 name = banked_regname (sysm);
8510
8511 if (name != NULL)
8512 func (stream, "%s", name);
8513 else
d908c8af 8514 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 8515 }
8516 else
8517 {
43e65147 8518 func (stream, "%cPSR_",
90ec0d68
MGD		 8519 (given & 0x00400000) ? 'S' : 'C');
8520 if (given & 0x80000)
8521 func (stream, "f");
8522 if (given & 0x40000)
8523 func (stream, "s");
8524 if (given & 0x20000)
8525 func (stream, "x");
8526 if (given & 0x10000)
8527 func (stream, "c");
8528 }
252b5132
RH		 8529 break;
8530
62b3e311 8531 case 'U':
43e65147 8532 if ((given & 0xf0) == 0x60)
62b3e311 8533 {
52e7f43d
RE		 8534 switch (given & 0xf)
8535 {
8536 case 0xf: func (stream, "sy"); break;
8537 default:
8538 func (stream, "#%d", (int) given & 0xf);
8539 break;
8540 }
43e65147
L		 8541 }
8542 else
52e7f43d 8543 {
e797f7e0
MGD		 8544 const char * opt = data_barrier_option (given & 0xf);
8545 if (opt != NULL)
8546 func (stream, "%s", opt);
8547 else
52e7f43d 8548 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 8549 }
8550 break;
8551
b34976b6 8552 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 8553 case '5': case '6': case '7': case '8': case '9':
8554 {
16980d0b
JB		 8555 int width;
8556 unsigned long value;
252b5132 8557
16980d0b 8558 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 8559
252b5132
RH		 8560 switch (*c)
8561 {
ab8e2090
NC		 8562 case 'R':
8563 if (value == 15)
8564 is_unpredictable = TRUE;
8565 /* Fall through. */
16980d0b 8566 case 'r':
9eb6c0f1
MGD		 8567 case 'T':
8568 /* We want register + 1 when decoding T. */
8569 if (*c == 'T')
8570 ++value;
8571
ff4a8d2b
NC		 8572 if (c[1] == 'u')
8573 {
8574 /* Eat the 'u' character. */
8575 ++ c;
8576
8577 if (u_reg == value)
8578 is_unpredictable = TRUE;
8579 u_reg = value;
8580 }
8581 if (c[1] == 'U')
8582 {
8583 /* Eat the 'U' character. */
8584 ++ c;
8585
8586 if (U_reg == value)
8587 is_unpredictable = TRUE;
8588 U_reg = value;
8589 }
16980d0b
JB		 8590 func (stream, "%s", arm_regnames[value]);
8591 break;
8592 case 'd':
8593 func (stream, "%ld", value);
05413229 8594 value_in_comment = value;
16980d0b
JB		 8595 break;
8596 case 'b':
8597 func (stream, "%ld", value * 8);
05413229 8598 value_in_comment = value * 8;
16980d0b
JB		 8599 break;
8600 case 'W':
8601 func (stream, "%ld", value + 1);
05413229 8602 value_in_comment = value + 1;
16980d0b
JB		 8603 break;
8604 case 'x':
8605 func (stream, "0x%08lx", value);
8606
8607 /* Some SWI instructions have special
8608 meanings. */
8609 if ((given & 0x0fffffff) == 0x0FF00000)
8610 func (stream, "\t; IMB");
8611 else if ((given & 0x0fffffff) == 0x0FF00001)
8612 func (stream, "\t; IMBRange");
8613 break;
8614 case 'X':
8615 func (stream, "%01lx", value & 0xf);
05413229 8616 value_in_comment = value;
252b5132
RH		 8617 break;
8618 case '`':
8619 c++;
16980d0b 8620 if (value == 0)
252b5132
RH		 8621 func (stream, "%c", *c);
8622 break;
8623 case '\'':
8624 c++;
16980d0b 8625 if (value == ((1ul << width) - 1))
252b5132
RH		 8626 func (stream, "%c", *c);
8627 break;
8628 case '?':
fe56b6ce 8629 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 8630 c += 1 << width;
252b5132
RH		 8631 break;
8632 default:
8633 abort ();
8634 }
dffaa15c
AM		 8635 }
8636 break;
0dd132b6 8637
dffaa15c
AM		 8638 case 'e':
8639 {
8640 int imm;
0dd132b6 8641
dffaa15c
AM		 8642 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
8643 func (stream, "%d", imm);
8644 value_in_comment = imm;
8645 }
8646 break;
fe56b6ce 8647
dffaa15c
AM		 8648 case 'E':
8649 /* LSB and WIDTH fields of BFI or BFC. The machine-
8650 language instruction encodes LSB and MSB. */
8651 {
8652 long msb = (given & 0x001f0000) >> 16;
8653 long lsb = (given & 0x00000f80) >> 7;
8654 long w = msb - lsb + 1;
0a003adc 8655
dffaa15c
AM		 8656 if (w > 0)
8657 func (stream, "#%lu, #%lu", lsb, w);
8658 else
8659 func (stream, "(invalid: %lu:%lu)", lsb, msb);
8660 }
8661 break;
90ec0d68 8662
dffaa15c
AM		 8663 case 'R':
8664 /* Get the PSR/banked register name. */
8665 {
8666 const char * name;
8667 unsigned sysm = (given & 0x004f0000) >> 16;
90ec0d68 8668
dffaa15c
AM		 8669 sysm |= (given & 0x300) >> 4;
8670 name = banked_regname (sysm);
90ec0d68 8671
dffaa15c
AM		 8672 if (name != NULL)
8673 func (stream, "%s", name);
8674 else
8675 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
8676 }
8677 break;
fe56b6ce 8678
dffaa15c
AM		 8679 case 'V':
8680 /* 16-bit unsigned immediate from a MOVT or MOVW
8681 instruction, encoded in bits 0:11 and 15:19. */
8682 {
8683 long hi = (given & 0x000f0000) >> 4;
8684 long lo = (given & 0x00000fff);
8685 long imm16 = hi | lo;
0a003adc 8686
dffaa15c
AM		 8687 func (stream, "#%lu", imm16);
8688 value_in_comment = imm16;
252b5132 8689 }
dffaa15c
AM		 8690 break;
8691
8692 default:
8693 abort ();
252b5132
RH		 8694 }
8695 }
8696 else
8697 func (stream, "%c", *c);
8698 }
05413229
NC		 8699
8700 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 8701 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 8702
8703 if (is_unpredictable)
8704 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 8705
4a5329c6 8706 return;
252b5132
RH		 8707 }
8708 }
0b347048
TC		 8709 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
8710 return;
252b5132
RH		 8711}
8712
4a5329c6 8713/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 8714
4a5329c6
ZW		 8715static void
8716print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 8717{
6b5d3a4d 8718 const struct opcode16 *insn;
6a51a8a8
AM		 8719 void *stream = info->stream;
8720 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 8721
8722 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 8723 if ((given & insn->mask) == insn->value)
8724 {
05413229 8725 signed long value_in_comment = 0;
6b5d3a4d 8726 const char *c = insn->assembler;
05413229 8727
c19d1205
ZW		 8728 for (; *c; c++)
8729 {
8730 int domaskpc = 0;
8731 int domasklr = 0;
8732
8733 if (*c != '%')
8734 {
8735 func (stream, "%c", *c);
8736 continue;
8737 }
252b5132 8738
c19d1205
ZW		 8739 switch (*++c)
8740 {
8741 case '%':
8742 func (stream, "%%");
8743 break;
b34976b6 8744
c22aaad1
PB		 8745 case 'c':
8746 if (ifthen_state)
8747 func (stream, "%s", arm_conditional[IFTHEN_COND]);
8748 break;
8749
8750 case 'C':
8751 if (ifthen_state)
8752 func (stream, "%s", arm_conditional[IFTHEN_COND]);
8753 else
8754 func (stream, "s");
8755 break;
8756
8757 case 'I':
8758 {
8759 unsigned int tmp;
8760
8761 ifthen_next_state = given & 0xff;
8762 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
8763 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
8764 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
8765 }
8766 break;
8767
8768 case 'x':
8769 if (ifthen_next_state)
8770 func (stream, "\t; unpredictable branch in IT block\n");
8771 break;
8772
8773 case 'X':
8774 if (ifthen_state)
8775 func (stream, "\t; unpredictable <IT:%s>",
8776 arm_conditional[IFTHEN_COND]);
8777 break;
8778
c19d1205
ZW		 8779 case 'S':
8780 {
8781 long reg;
8782
8783 reg = (given >> 3) & 0x7;
8784 if (given & (1 << 6))
8785 reg += 8;
4f3c3dbb 8786
c19d1205
ZW		 8787 func (stream, "%s", arm_regnames[reg]);
8788 }
8789 break;
baf0cc5e 8790
c19d1205 8791 case 'D':
4f3c3dbb 8792 {
c19d1205
ZW		 8793 long reg;
8794
8795 reg = given & 0x7;
8796 if (given & (1 << 7))
8797 reg += 8;
8798
8799 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 8800 }
c19d1205
ZW		 8801 break;
8802
8803 case 'N':
8804 if (given & (1 << 8))
8805 domasklr = 1;
8806 /* Fall through. */
8807 case 'O':
8808 if (*c == 'O' && (given & (1 << 8)))
8809 domaskpc = 1;
8810 /* Fall through. */
8811 case 'M':
8812 {
8813 int started = 0;
8814 int reg;
8815
8816 func (stream, "{");
8817
8818 /* It would be nice if we could spot
8819 ranges, and generate the rS-rE format: */
8820 for (reg = 0; (reg < 8); reg++)
8821 if ((given & (1 << reg)) != 0)
8822 {
8823 if (started)
8824 func (stream, ", ");
8825 started = 1;
8826 func (stream, "%s", arm_regnames[reg]);
8827 }
8828
8829 if (domasklr)
8830 {
8831 if (started)
8832 func (stream, ", ");
8833 started = 1;
d908c8af 8834 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 8835 }
8836
8837 if (domaskpc)
8838 {
8839 if (started)
8840 func (stream, ", ");
d908c8af 8841 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 8842 }
8843
8844 func (stream, "}");
8845 }
8846 break;
8847
4547cb56
NC		 8848 case 'W':
8849 /* Print writeback indicator for a LDMIA. We are doing a
8850 writeback if the base register is not in the register
8851 mask. */
8852 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
8853 func (stream, "!");
dffaa15c 8854 break;
4547cb56 8855
c19d1205
ZW		 8856 case 'b':
8857 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
8858 {
8859 bfd_vma address = (pc + 4
8860 + ((given & 0x00f8) >> 2)
8861 + ((given & 0x0200) >> 3));
8862 info->print_address_func (address, info);
8863 }
8864 break;
8865
8866 case 's':
8867 /* Right shift immediate -- bits 6..10; 1-31 print
8868 as themselves, 0 prints as 32. */
8869 {
8870 long imm = (given & 0x07c0) >> 6;
8871 if (imm == 0)
8872 imm = 32;
0fd3a477 8873 func (stream, "#%ld", imm);
c19d1205
ZW		 8874 }
8875 break;
8876
8877 case '0': case '1': case '2': case '3': case '4':
8878 case '5': case '6': case '7': case '8': case '9':
8879 {
8880 int bitstart = *c++ - '0';
8881 int bitend = 0;
8882
8883 while (*c >= '0' && *c <= '9')
8884 bitstart = (bitstart * 10) + *c++ - '0';
8885
8886 switch (*c)
8887 {
8888 case '-':
8889 {
f8b960bc 8890 bfd_vma reg;
c19d1205
ZW		 8891
8892 c++;
8893 while (*c >= '0' && *c <= '9')
8894 bitend = (bitend * 10) + *c++ - '0';
8895 if (!bitend)
8896 abort ();
8897 reg = given >> bitstart;
8898 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 8899
c19d1205
ZW		 8900 switch (*c)
8901 {
8902 case 'r':
8903 func (stream, "%s", arm_regnames[reg]);
8904 break;
8905
8906 case 'd':
d908c8af 8907 func (stream, "%ld", (long) reg);
05413229 8908 value_in_comment = reg;
c19d1205
ZW		 8909 break;
8910
8911 case 'H':
d908c8af 8912 func (stream, "%ld", (long) (reg << 1));
05413229 8913 value_in_comment = reg << 1;
c19d1205
ZW		 8914 break;
8915
8916 case 'W':
d908c8af 8917 func (stream, "%ld", (long) (reg << 2));
05413229 8918 value_in_comment = reg << 2;
c19d1205
ZW		 8919 break;
8920
8921 case 'a':
8922 /* PC-relative address -- the bottom two
8923 bits of the address are dropped
8924 before the calculation. */
8925 info->print_address_func
8926 (((pc + 4) & ~3) + (reg << 2), info);
05413229 8927 value_in_comment = 0;
c19d1205
ZW		 8928 break;
8929
8930 case 'x':
d908c8af 8931 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 8932 break;
8933
c19d1205
ZW		 8934 case 'B':
8935 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6b5d3a4d 8936 info->print_address_func (reg * 2 + pc + 4, info);
05413229 8937 value_in_comment = 0;
c19d1205
ZW		 8938 break;
8939
8940 case 'c':
c22aaad1 8941 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 8942 break;
8943
8944 default:
8945 abort ();
8946 }
8947 }
8948 break;
8949
8950 case '\'':
8951 c++;
8952 if ((given & (1 << bitstart)) != 0)
8953 func (stream, "%c", *c);
8954 break;
8955
8956 case '?':
8957 ++c;
8958 if ((given & (1 << bitstart)) != 0)
8959 func (stream, "%c", *c++);
8960 else
8961 func (stream, "%c", *++c);
8962 break;
8963
8964 default:
8965 abort ();
8966 }
8967 }
8968 break;
8969
8970 default:
8971 abort ();
8972 }
8973 }
05413229
NC		 8974
8975 if (value_in_comment > 32 || value_in_comment < -16)
8976 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 8977 return;
c19d1205
ZW		 8978 }
8979
8980 /* No match. */
0b347048
TC		 8981 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
8982 return;
c19d1205
ZW		 8983}
8984
62b3e311 8985/* Return the name of an V7M special register. */
fe56b6ce 8986
62b3e311
PB		 8987static const char *
8988psr_name (int regno)
8989{
8990 switch (regno)
8991 {
1a336194
TP		 8992 case 0x0: return "APSR";
8993 case 0x1: return "IAPSR";
8994 case 0x2: return "EAPSR";
8995 case 0x3: return "PSR";
8996 case 0x5: return "IPSR";
8997 case 0x6: return "EPSR";
8998 case 0x7: return "IEPSR";
8999 case 0x8: return "MSP";
9000 case 0x9: return "PSP";
9001 case 0xa: return "MSPLIM";
9002 case 0xb: return "PSPLIM";
9003 case 0x10: return "PRIMASK";
9004 case 0x11: return "BASEPRI";
9005 case 0x12: return "BASEPRI_MAX";
9006 case 0x13: return "FAULTMASK";
9007 case 0x14: return "CONTROL";
16a1fa25
TP		 9008 case 0x88: return "MSP_NS";
9009 case 0x89: return "PSP_NS";
1a336194
TP		 9010 case 0x8a: return "MSPLIM_NS";
9011 case 0x8b: return "PSPLIM_NS";
9012 case 0x90: return "PRIMASK_NS";
9013 case 0x91: return "BASEPRI_NS";
9014 case 0x93: return "FAULTMASK_NS";
9015 case 0x94: return "CONTROL_NS";
9016 case 0x98: return "SP_NS";
62b3e311
PB		 9017 default: return "<unknown>";
9018 }
9019}
9020
4a5329c6
ZW		 9021/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
9022
9023static void
9024print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 9025{
6b5d3a4d 9026 const struct opcode32 *insn;
c19d1205
ZW		 9027 void *stream = info->stream;
9028 fprintf_ftype func = info->fprintf_func;
73cd51e5 9029 bfd_boolean is_mve = is_mve_architecture (info);
c19d1205 9030
16980d0b
JB		 9031 if (print_insn_coprocessor (pc, info, given, TRUE))
9032 return;
9033
73cd51e5
AV		 9034 if ((is_mve == FALSE) && print_insn_neon (info, given, TRUE))
9035 return;
9036
9037 if (is_mve && print_insn_mve (info, given))
8f06b2d8
PB		 9038 return;
9039
c19d1205
ZW		 9040 for (insn = thumb32_opcodes; insn->assembler; insn++)
9041 if ((given & insn->mask) == insn->value)
9042 {
4b5a202f 9043 bfd_boolean is_clrm = FALSE;
ff4a8d2b 9044 bfd_boolean is_unpredictable = FALSE;
05413229 9045 signed long value_in_comment = 0;
6b5d3a4d 9046 const char *c = insn->assembler;
05413229 9047
c19d1205
ZW		 9048 for (; *c; c++)
9049 {
9050 if (*c != '%')
9051 {
9052 func (stream, "%c", *c);
9053 continue;
9054 }
9055
9056 switch (*++c)
9057 {
9058 case '%':
9059 func (stream, "%%");
9060 break;
9061
c22aaad1
PB		 9062 case 'c':
9063 if (ifthen_state)
9064 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9065 break;
9066
9067 case 'x':
9068 if (ifthen_next_state)
9069 func (stream, "\t; unpredictable branch in IT block\n");
9070 break;
9071
9072 case 'X':
9073 if (ifthen_state)
9074 func (stream, "\t; unpredictable <IT:%s>",
9075 arm_conditional[IFTHEN_COND]);
9076 break;
9077
c19d1205
ZW		 9078 case 'I':
9079 {
9080 unsigned int imm12 = 0;
fe56b6ce 9081
c19d1205
ZW		 9082 imm12 |= (given & 0x000000ffu);
9083 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 9084 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 9085 func (stream, "#%u", imm12);
9086 value_in_comment = imm12;
c19d1205
ZW		 9087 }
9088 break;
9089
9090 case 'M':
9091 {
9092 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 9093
c19d1205
ZW		 9094 bits |= (given & 0x000000ffu);
9095 bits |= (given & 0x00007000u) >> 4;
9096 bits |= (given & 0x04000000u) >> 15;
9097 imm8 = (bits & 0x0ff);
9098 mod = (bits & 0xf00) >> 8;
9099 switch (mod)
9100 {
9101 case 0: imm = imm8; break;
c1e26897
NC		 9102 case 1: imm = ((imm8 << 16) | imm8); break;
9103 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
9104 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 9105 default:
9106 mod = (bits & 0xf80) >> 7;
9107 imm8 = (bits & 0x07f) | 0x80;
9108 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
9109 }
fe56b6ce
NC		 9110 func (stream, "#%u", imm);
9111 value_in_comment = imm;
c19d1205
ZW		 9112 }
9113 break;
43e65147 9114
c19d1205
ZW		 9115 case 'J':
9116 {
9117 unsigned int imm = 0;
fe56b6ce 9118
c19d1205
ZW		 9119 imm |= (given & 0x000000ffu);
9120 imm |= (given & 0x00007000u) >> 4;
9121 imm |= (given & 0x04000000u) >> 15;
9122 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 9123 func (stream, "#%u", imm);
9124 value_in_comment = imm;
c19d1205
ZW		 9125 }
9126 break;
9127
9128 case 'K':
9129 {
9130 unsigned int imm = 0;
fe56b6ce 9131
c19d1205
ZW		 9132 imm |= (given & 0x000f0000u) >> 16;
9133 imm |= (given & 0x00000ff0u) >> 0;
9134 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 9135 func (stream, "#%u", imm);
9136 value_in_comment = imm;
c19d1205
ZW		 9137 }
9138 break;
9139
74db7efb
NC		 9140 case 'H':
9141 {
9142 unsigned int imm = 0;
9143
9144 imm |= (given & 0x000f0000u) >> 4;
9145 imm |= (given & 0x00000fffu) >> 0;
9146 func (stream, "#%u", imm);
9147 value_in_comment = imm;
9148 }
9149 break;
9150
90ec0d68
MGD		 9151 case 'V':
9152 {
9153 unsigned int imm = 0;
9154
9155 imm |= (given & 0x00000fffu);
9156 imm |= (given & 0x000f0000u) >> 4;
9157 func (stream, "#%u", imm);
9158 value_in_comment = imm;
9159 }
9160 break;
9161
c19d1205
ZW		 9162 case 'S':
9163 {
9164 unsigned int reg = (given & 0x0000000fu);
9165 unsigned int stp = (given & 0x00000030u) >> 4;
9166 unsigned int imm = 0;
9167 imm |= (given & 0x000000c0u) >> 6;
9168 imm |= (given & 0x00007000u) >> 10;
9169
9170 func (stream, "%s", arm_regnames[reg]);
9171 switch (stp)
9172 {
9173 case 0:
9174 if (imm > 0)
9175 func (stream, ", lsl #%u", imm);
9176 break;
9177
9178 case 1:
9179 if (imm == 0)
9180 imm = 32;
9181 func (stream, ", lsr #%u", imm);
9182 break;
9183
9184 case 2:
9185 if (imm == 0)
9186 imm = 32;
9187 func (stream, ", asr #%u", imm);
9188 break;
9189
9190 case 3:
9191 if (imm == 0)
9192 func (stream, ", rrx");
9193 else
9194 func (stream, ", ror #%u", imm);
9195 }
9196 }
9197 break;
9198
9199 case 'a':
9200 {
9201 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 9202 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 9203 unsigned int op = (given & 0x00000f00) >> 8;
9204 unsigned int i12 = (given & 0x00000fff);
9205 unsigned int i8 = (given & 0x000000ff);
9206 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 9207 bfd_vma offset = 0;
c19d1205
ZW		 9208
9209 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 9210 if (U) /* 12-bit positive immediate offset. */
9211 {
9212 offset = i12;
9213 if (Rn != 15)
9214 value_in_comment = offset;
9215 }
9216 else if (Rn == 15) /* 12-bit negative immediate offset. */
9217 offset = - (int) i12;
9218 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 9219 {
9220 unsigned int Rm = (i8 & 0x0f);
9221 unsigned int sh = (i8 & 0x30) >> 4;
05413229 9222
c19d1205
ZW		 9223 func (stream, ", %s", arm_regnames[Rm]);
9224 if (sh)
9225 func (stream, ", lsl #%u", sh);
9226 func (stream, "]");
9227 break;
9228 }
9229 else switch (op)
9230 {
05413229 9231 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 9232 offset = i8;
9233 break;
9234
05413229 9235 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 9236 offset = -i8;
9237 break;
9238
05413229 9239 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 9240 offset = i8;
9241 writeback = TRUE;
9242 break;
9243
05413229 9244 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 9245 offset = -i8;
9246 writeback = TRUE;
9247 break;
9248
05413229 9249 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 9250 offset = i8;
9251 postind = TRUE;
9252 break;
9253
05413229 9254 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 9255 offset = -i8;
9256 postind = TRUE;
9257 break;
9258
9259 default:
9260 func (stream, ", <undefined>]");
9261 goto skip;
9262 }
9263
9264 if (postind)
d908c8af 9265 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 9266 else
9267 {
9268 if (offset)
d908c8af 9269 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 9270 func (stream, writeback ? "]!" : "]");
9271 }
9272
9273 if (Rn == 15)
9274 {
9275 func (stream, "\t; ");
9276 info->print_address_func (((pc + 4) & ~3) + offset, info);
9277 }
9278 }
9279 skip:
9280 break;
9281
9282 case 'A':
9283 {
c1e26897
NC		 9284 unsigned int U = ! NEGATIVE_BIT_SET;
9285 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 9286 unsigned int Rn = (given & 0x000f0000) >> 16;
9287 unsigned int off = (given & 0x000000ff);
9288
9289 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 9290
9291 if (PRE_BIT_SET)
c19d1205
ZW		 9292 {
9293 if (off || !U)
05413229
NC		 9294 {
9295 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
fe50e98c 9296 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 9297 }
c19d1205
ZW		 9298 func (stream, "]");
9299 if (W)
9300 func (stream, "!");
9301 }
9302 else
9303 {
9304 func (stream, "], ");
9305 if (W)
05413229
NC		 9306 {
9307 func (stream, "#%c%u", U ? '+' : '-', off * 4);
fe50e98c 9308 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 9309 }
c19d1205 9310 else
fe56b6ce
NC		 9311 {
9312 func (stream, "{%u}", off);
9313 value_in_comment = off;
9314 }
c19d1205
ZW		 9315 }
9316 }
9317 break;
9318
9319 case 'w':
9320 {
9321 unsigned int Sbit = (given & 0x01000000) >> 24;
9322 unsigned int type = (given & 0x00600000) >> 21;
05413229 9323
c19d1205
ZW		 9324 switch (type)
9325 {
9326 case 0: func (stream, Sbit ? "sb" : "b"); break;
9327 case 1: func (stream, Sbit ? "sh" : "h"); break;
9328 case 2:
9329 if (Sbit)
9330 func (stream, "??");
9331 break;
9332 case 3:
9333 func (stream, "??");
9334 break;
9335 }
9336 }
9337 break;
9338
4b5a202f
AV		 9339 case 'n':
9340 is_clrm = TRUE;
9341 /* Fall through. */
c19d1205
ZW		 9342 case 'm':
9343 {
9344 int started = 0;
9345 int reg;
9346
9347 func (stream, "{");
9348 for (reg = 0; reg < 16; reg++)
9349 if ((given & (1 << reg)) != 0)
9350 {
9351 if (started)
9352 func (stream, ", ");
9353 started = 1;
4b5a202f
AV		 9354 if (is_clrm && reg == 13)
9355 func (stream, "(invalid: %s)", arm_regnames[reg]);
9356 else if (is_clrm && reg == 15)
9357 func (stream, "%s", "APSR");
9358 else
9359 func (stream, "%s", arm_regnames[reg]);
c19d1205
ZW		 9360 }
9361 func (stream, "}");
9362 }
9363 break;
9364
9365 case 'E':
9366 {
9367 unsigned int msb = (given & 0x0000001f);
9368 unsigned int lsb = 0;
fe56b6ce 9369
c19d1205
ZW		 9370 lsb |= (given & 0x000000c0u) >> 6;
9371 lsb |= (given & 0x00007000u) >> 10;
9372 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
9373 }
9374 break;
9375
9376 case 'F':
9377 {
9378 unsigned int width = (given & 0x0000001f) + 1;
9379 unsigned int lsb = 0;
fe56b6ce 9380
c19d1205
ZW		 9381 lsb |= (given & 0x000000c0u) >> 6;
9382 lsb |= (given & 0x00007000u) >> 10;
9383 func (stream, "#%u, #%u", lsb, width);
9384 }
9385 break;
9386
e12437dc
AV		 9387 case 'G':
9388 {
9389 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
9390 func (stream, "%x", boff);
9391 }
9392 break;
9393
e5d6e09e
AV		 9394 case 'W':
9395 {
9396 unsigned int immA = (given & 0x001f0000u) >> 16;
9397 unsigned int immB = (given & 0x000007feu) >> 1;
9398 unsigned int immC = (given & 0x00000800u) >> 11;
9399 bfd_vma offset = 0;
9400
9401 offset |= immA << 12;
9402 offset |= immB << 2;
9403 offset |= immC << 1;
9404 /* Sign extend. */
9405 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
9406
9407 info->print_address_func (pc + 4 + offset, info);
9408 }
9409 break;
9410
1caf72a5
AV		 9411 case 'Y':
9412 {
9413 unsigned int immA = (given & 0x007f0000u) >> 16;
9414 unsigned int immB = (given & 0x000007feu) >> 1;
9415 unsigned int immC = (given & 0x00000800u) >> 11;
9416 bfd_vma offset = 0;
9417
9418 offset |= immA << 12;
9419 offset |= immB << 2;
9420 offset |= immC << 1;
9421 /* Sign extend. */
9422 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
9423
9424 info->print_address_func (pc + 4 + offset, info);
9425 }
9426 break;
9427
1889da70
AV		 9428 case 'Z':
9429 {
9430 unsigned int immA = (given & 0x00010000u) >> 16;
9431 unsigned int immB = (given & 0x000007feu) >> 1;
9432 unsigned int immC = (given & 0x00000800u) >> 11;
9433 bfd_vma offset = 0;
9434
9435 offset |= immA << 12;
9436 offset |= immB << 2;
9437 offset |= immC << 1;
9438 /* Sign extend. */
9439 offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
9440
9441 info->print_address_func (pc + 4 + offset, info);
f6b2b12d
AV		 9442
9443 unsigned int T = (given & 0x00020000u) >> 17;
9444 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
9445 unsigned int boffset = (T == 1) ? 4 : 2;
9446 func (stream, ", ");
9447 func (stream, "%x", endoffset + boffset);
1889da70
AV		 9448 }
9449 break;
9450
60f993ce
AV		 9451 case 'Q':
9452 {
9453 unsigned int immh = (given & 0x000007feu) >> 1;
9454 unsigned int imml = (given & 0x00000800u) >> 11;
9455 bfd_vma imm32 = 0;
9456
9457 imm32 |= immh << 2;
9458 imm32 |= imml << 1;
9459
9460 info->print_address_func (pc + 4 + imm32, info);
9461 }
9462 break;
9463
9464 case 'P':
9465 {
9466 unsigned int immh = (given & 0x000007feu) >> 1;
9467 unsigned int imml = (given & 0x00000800u) >> 11;
9468 bfd_vma imm32 = 0;
9469
9470 imm32 |= immh << 2;
9471 imm32 |= imml << 1;
9472
9473 info->print_address_func (pc + 4 - imm32, info);
9474 }
9475 break;
9476
c19d1205
ZW		 9477 case 'b':
9478 {
9479 unsigned int S = (given & 0x04000000u) >> 26;
9480 unsigned int J1 = (given & 0x00002000u) >> 13;
9481 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 9482 bfd_vma offset = 0;
c19d1205
ZW		 9483
9484 offset |= !S << 20;
9485 offset |= J2 << 19;
9486 offset |= J1 << 18;
9487 offset |= (given & 0x003f0000) >> 4;
9488 offset |= (given & 0x000007ff) << 1;
9489 offset -= (1 << 20);
9490
9491 info->print_address_func (pc + 4 + offset, info);
9492 }
9493 break;
9494
9495 case 'B':
9496 {
9497 unsigned int S = (given & 0x04000000u) >> 26;
9498 unsigned int I1 = (given & 0x00002000u) >> 13;
9499 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 9500 bfd_vma offset = 0;
c19d1205
ZW		 9501
9502 offset |= !S << 24;
9503 offset |= !(I1 ^ S) << 23;
9504 offset |= !(I2 ^ S) << 22;
9505 offset |= (given & 0x03ff0000u) >> 4;
9506 offset |= (given & 0x000007ffu) << 1;
9507 offset -= (1 << 24);
36b0c57d 9508 offset += pc + 4;
c19d1205 9509
36b0c57d
PB		 9510 /* BLX target addresses are always word aligned. */
9511 if ((given & 0x00001000u) == 0)
9512 offset &= ~2u;
9513
9514 info->print_address_func (offset, info);
c19d1205
ZW		 9515 }
9516 break;
9517
9518 case 's':
9519 {
9520 unsigned int shift = 0;
fe56b6ce 9521
c19d1205
ZW		 9522 shift |= (given & 0x000000c0u) >> 6;
9523 shift |= (given & 0x00007000u) >> 10;
c1e26897 9524 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 9525 func (stream, ", asr #%u", shift);
9526 else if (shift)
9527 func (stream, ", lsl #%u", shift);
9528 /* else print nothing - lsl #0 */
9529 }
9530 break;
9531
9532 case 'R':
9533 {
9534 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 9535
c19d1205
ZW		 9536 if (rot)
9537 func (stream, ", ror #%u", rot * 8);
9538 }
9539 break;
9540
62b3e311 9541 case 'U':
43e65147 9542 if ((given & 0xf0) == 0x60)
62b3e311 9543 {
52e7f43d
RE		 9544 switch (given & 0xf)
9545 {
9546 case 0xf: func (stream, "sy"); break;
9547 default:
9548 func (stream, "#%d", (int) given & 0xf);
9549 break;
9550 }
62b3e311 9551 }
43e65147 9552 else
52e7f43d 9553 {
e797f7e0
MGD		 9554 const char * opt = data_barrier_option (given & 0xf);
9555 if (opt != NULL)
9556 func (stream, "%s", opt);
9557 else
9558 func (stream, "#%d", (int) given & 0xf);
52e7f43d 9559 }
62b3e311
PB		 9560 break;
9561
9562 case 'C':
9563 if ((given & 0xff) == 0)
9564 {
9565 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
9566 if (given & 0x800)
9567 func (stream, "f");
9568 if (given & 0x400)
9569 func (stream, "s");
9570 if (given & 0x200)
9571 func (stream, "x");
9572 if (given & 0x100)
9573 func (stream, "c");
9574 }
90ec0d68
MGD		 9575 else if ((given & 0x20) == 0x20)
9576 {
9577 char const* name;
9578 unsigned sysm = (given & 0xf00) >> 8;
9579
9580 sysm |= (given & 0x30);
9581 sysm |= (given & 0x00100000) >> 14;
9582 name = banked_regname (sysm);
43e65147 9583
90ec0d68
MGD		 9584 if (name != NULL)
9585 func (stream, "%s", name);
9586 else
d908c8af 9587 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 9588 }
62b3e311
PB		 9589 else
9590 {
d908c8af 9591 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 9592 }
9593 break;
9594
9595 case 'D':
90ec0d68
MGD		 9596 if (((given & 0xff) == 0)
9597 || ((given & 0x20) == 0x20))
9598 {
9599 char const* name;
9600 unsigned sm = (given & 0xf0000) >> 16;
9601
9602 sm |= (given & 0x30);
9603 sm |= (given & 0x00100000) >> 14;
9604 name = banked_regname (sm);
9605
9606 if (name != NULL)
9607 func (stream, "%s", name);
9608 else
d908c8af 9609 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 9610 }
62b3e311 9611 else
d908c8af 9612 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 9613 break;
9614
c19d1205
ZW		 9615 case '0': case '1': case '2': case '3': case '4':
9616 case '5': case '6': case '7': case '8': case '9':
9617 {
16980d0b
JB		 9618 int width;
9619 unsigned long val;
c19d1205 9620
16980d0b 9621 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 9622
c19d1205
ZW		 9623 switch (*c)
9624 {
05413229
NC		 9625 case 'd':
9626 func (stream, "%lu", val);
9627 value_in_comment = val;
9628 break;
ff4a8d2b 9629
f0fba320
RL		 9630 case 'D':
9631 func (stream, "%lu", val + 1);
9632 value_in_comment = val + 1;
9633 break;
9634
05413229
NC		 9635 case 'W':
9636 func (stream, "%lu", val * 4);
9637 value_in_comment = val * 4;
9638 break;
ff4a8d2b 9639
f1c7f421
AV		 9640 case 'S':
9641 if (val == 13)
9642 is_unpredictable = TRUE;
9643 /* Fall through. */
ff4a8d2b
NC		 9644 case 'R':
9645 if (val == 15)
9646 is_unpredictable = TRUE;
9647 /* Fall through. */
9648 case 'r':
9649 func (stream, "%s", arm_regnames[val]);
9650 break;
c19d1205
ZW		 9651
9652 case 'c':
c22aaad1 9653 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 9654 break;
9655
9656 case '\'':
c19d1205 9657 c++;
16980d0b
JB		 9658 if (val == ((1ul << width) - 1))
9659 func (stream, "%c", *c);
c19d1205 9660 break;
43e65147 9661
c19d1205 9662 case '`':
c19d1205 9663 c++;
16980d0b
JB		 9664 if (val == 0)
9665 func (stream, "%c", *c);
c19d1205
ZW		 9666 break;
9667
9668 case '?':
fe56b6ce 9669 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 9670 c += 1 << width;
c19d1205 9671 break;
43e65147 9672
0bb027fd
RR		 9673 case 'x':
9674 func (stream, "0x%lx", val & 0xffffffffUL);
9675 break;
c19d1205
ZW		 9676
9677 default:
9678 abort ();
9679 }
9680 }
9681 break;
9682
32a94698
NC		 9683 case 'L':
9684 /* PR binutils/12534
9685 If we have a PC relative offset in an LDRD or STRD
9686 instructions then display the decoded address. */
9687 if (((given >> 16) & 0xf) == 0xf)
9688 {
9689 bfd_vma offset = (given & 0xff) * 4;
9690
9691 if ((given & (1 << 23)) == 0)
9692 offset = - offset;
9693 func (stream, "\t; ");
9694 info->print_address_func ((pc & ~3) + 4 + offset, info);
9695 }
9696 break;
9697
c19d1205
ZW		 9698 default:
9699 abort ();
9700 }
9701 }
05413229
NC		 9702
9703 if (value_in_comment > 32 || value_in_comment < -16)
9704 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 9705
9706 if (is_unpredictable)
9707 func (stream, UNPREDICTABLE_INSTRUCTION);
9708
4a5329c6 9709 return;
c19d1205 9710 }
252b5132 9711
58efb6c0 9712 /* No match. */
0b347048
TC		 9713 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
9714 return;
252b5132
RH		 9715}
9716
e821645d
DJ		 9717/* Print data bytes on INFO->STREAM. */
9718
9719static void
fe56b6ce
NC		 9720print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
9721 struct disassemble_info *info,
e821645d
DJ		 9722 long given)
9723{
9724 switch (info->bytes_per_chunk)
9725 {
9726 case 1:
9727 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
9728 break;
9729 case 2:
9730 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
9731 break;
9732 case 4:
9733 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
9734 break;
9735 default:
9736 abort ();
9737 }
9738}
9739
22a398e1 9740/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 9741 being displayed in symbol relative addresses.
9742
9743 Also disallow private symbol, with __tagsym$$ prefix,
9744 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 9745
9746bfd_boolean
9747arm_symbol_is_valid (asymbol * sym,
9748 struct disassemble_info * info ATTRIBUTE_UNUSED)
9749{
9750 const char * name;
43e65147 9751
22a398e1
NC		 9752 if (sym == NULL)
9753 return FALSE;
9754
9755 name = bfd_asymbol_name (sym);
9756
d8282f0e 9757 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 9758}
9759
65b48a81 9760/* Parse the string of disassembler options. */
baf0cc5e 9761
65b48a81 9762static void
f995bbe8 9763parse_arm_disassembler_options (const char *options)
dd92f639 9764{
f995bbe8 9765 const char *opt;
b34976b6 9766
65b48a81 9767 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
dd92f639 9768 {
65b48a81
PB		 9769 if (CONST_STRNEQ (opt, "reg-names-"))
9770 {
9771 unsigned int i;
9772 for (i = 0; i < NUM_ARM_OPTIONS; i++)
9773 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
9774 {
9775 regname_selected = i;
9776 break;
9777 }
b34976b6 9778
65b48a81 9779 if (i >= NUM_ARM_OPTIONS)
a6743a54
AM		 9780 /* xgettext: c-format */
9781 opcodes_error_handler (_("unrecognised register name set: %s"),
9782 opt);
65b48a81
PB		 9783 }
9784 else if (CONST_STRNEQ (opt, "force-thumb"))
9785 force_thumb = 1;
9786 else if (CONST_STRNEQ (opt, "no-force-thumb"))
9787 force_thumb = 0;
9788 else
a6743a54
AM		 9789 /* xgettext: c-format */
9790 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
dd92f639 9791 }
b34976b6 9792
dd92f639
NC		 9793 return;
9794}
9795
5bc5ae88
RL		 9796static bfd_boolean
9797mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
9798 enum map_type *map_symbol);
9799
c22aaad1
PB		 9800/* Search back through the insn stream to determine if this instruction is
9801 conditionally executed. */
fe56b6ce 9802
c22aaad1 9803static void
fe56b6ce
NC		 9804find_ifthen_state (bfd_vma pc,
9805 struct disassemble_info *info,
c22aaad1
PB		 9806 bfd_boolean little)
9807{
9808 unsigned char b[2];
9809 unsigned int insn;
9810 int status;
9811 /* COUNT is twice the number of instructions seen. It will be odd if we
9812 just crossed an instruction boundary. */
9813 int count;
9814 int it_count;
9815 unsigned int seen_it;
9816 bfd_vma addr;
9817
9818 ifthen_address = pc;
9819 ifthen_state = 0;
9820
9821 addr = pc;
9822 count = 1;
9823 it_count = 0;
9824 seen_it = 0;
9825 /* Scan backwards looking for IT instructions, keeping track of where
9826 instruction boundaries are. We don't know if something is actually an
9827 IT instruction until we find a definite instruction boundary. */
9828 for (;;)
9829 {
fe56b6ce 9830 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 9831 {
9832 /* A symbol must be on an instruction boundary, and will not
9833 be within an IT block. */
9834 if (seen_it && (count & 1))
9835 break;
9836
9837 return;
9838 }
9839 addr -= 2;
fe56b6ce 9840 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 9841 if (status)
9842 return;
9843
9844 if (little)
9845 insn = (b[0]) | (b[1] << 8);
9846 else
9847 insn = (b[1]) | (b[0] << 8);
9848 if (seen_it)
9849 {
9850 if ((insn & 0xf800) < 0xe800)
9851 {
9852 /* Addr + 2 is an instruction boundary. See if this matches
9853 the expected boundary based on the position of the last
9854 IT candidate. */
9855 if (count & 1)
9856 break;
9857 seen_it = 0;
9858 }
9859 }
9860 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
9861 {
5bc5ae88
RL		 9862 enum map_type type = MAP_ARM;
9863 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
9864
9865 if (!found || (found && type == MAP_THUMB))
9866 {
9867 /* This could be an IT instruction. */
9868 seen_it = insn;
9869 it_count = count >> 1;
9870 }
c22aaad1
PB		 9871 }
9872 if ((insn & 0xf800) >= 0xe800)
9873 count++;
9874 else
9875 count = (count + 2) | 1;
9876 /* IT blocks contain at most 4 instructions. */
9877 if (count >= 8 && !seen_it)
9878 return;
9879 }
9880 /* We found an IT instruction. */
9881 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
9882 if ((ifthen_state & 0xf) == 0)
9883 ifthen_state = 0;
9884}
9885
b0e28b39
DJ		 9886/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
9887 mapping symbol. */
9888
9889static int
9890is_mapping_symbol (struct disassemble_info *info, int n,
9891 enum map_type *map_type)
9892{
9893 const char *name;
9894
9895 name = bfd_asymbol_name (info->symtab[n]);
9896 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
9897 && (name[2] == 0 || name[2] == '.'))
9898 {
9899 *map_type = ((name[1] == 'a') ? MAP_ARM
9900 : (name[1] == 't') ? MAP_THUMB
9901 : MAP_DATA);
9902 return TRUE;
9903 }
9904
9905 return FALSE;
9906}
9907
9908/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
9909 Returns nonzero if *MAP_TYPE was set. */
9910
9911static int
9912get_map_sym_type (struct disassemble_info *info,
9913 int n,
9914 enum map_type *map_type)
9915{
9916 /* If the symbol is in a different section, ignore it. */
9917 if (info->section != NULL && info->section != info->symtab[n]->section)
9918 return FALSE;
9919
9920 return is_mapping_symbol (info, n, map_type);
9921}
9922
9923/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 9924 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 9925
9926static int
fe56b6ce
NC		 9927get_sym_code_type (struct disassemble_info *info,
9928 int n,
e821645d 9929 enum map_type *map_type)
2087ad84
PB		 9930{
9931 elf_symbol_type *es;
9932 unsigned int type;
b0e28b39
DJ		 9933
9934 /* If the symbol is in a different section, ignore it. */
9935 if (info->section != NULL && info->section != info->symtab[n]->section)
9936 return FALSE;
2087ad84 9937
e821645d 9938 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 9939 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
9940
9941 /* If the symbol has function type then use that. */
34e77a92 9942 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 9943 {
39d911fc
TP		 9944 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
9945 == ST_BRANCH_TO_THUMB)
35fc36a8
RS		 9946 *map_type = MAP_THUMB;
9947 else
9948 *map_type = MAP_ARM;
2087ad84
PB		 9949 return TRUE;
9950 }
9951
2087ad84
PB		 9952 return FALSE;
9953}
9954
5bc5ae88
RL		 9955/* Search the mapping symbol state for instruction at pc. This is only
9956 applicable for elf target.
9957
9958 There is an assumption Here, info->private_data contains the correct AND
9959 up-to-date information about current scan process. The information will be
9960 used to speed this search process.
9961
9962 Return TRUE if the mapping state can be determined, and map_symbol
9963 will be updated accordingly. Otherwise, return FALSE. */
9964
9965static bfd_boolean
9966mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
9967 enum map_type *map_symbol)
9968{
796d6298
TC		 9969 bfd_vma addr, section_vma = 0;
9970 int n, last_sym = -1;
5bc5ae88 9971 bfd_boolean found = FALSE;
796d6298
TC		 9972 bfd_boolean can_use_search_opt_p = FALSE;
9973
9974 /* Default to DATA. A text section is required by the ABI to contain an
9975 INSN mapping symbol at the start. A data section has no such
9976 requirement, hence if no mapping symbol is found the section must
9977 contain only data. This however isn't very useful if the user has
9978 fully stripped the binaries. If this is the case use the section
9979 attributes to determine the default. If we have no section default to
9980 INSN as well, as we may be disassembling some raw bytes on a baremetal
9981 HEX file or similar. */
9982 enum map_type type = MAP_DATA;
9983 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
9984 type = MAP_ARM;
5bc5ae88
RL		 9985 struct arm_private_data *private_data;
9986
796d6298 9987 if (info->private_data == NULL
5bc5ae88
RL		 9988 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
9989 return FALSE;
9990
9991 private_data = info->private_data;
5bc5ae88 9992
796d6298
TC		 9993 /* First, look for mapping symbols. */
9994 if (info->symtab_size != 0)
9995 {
9996 if (pc <= private_data->last_mapping_addr)
9997 private_data->last_mapping_sym = -1;
9998
9999 /* Start scanning at the start of the function, or wherever
10000 we finished last time. */
10001 n = info->symtab_pos + 1;
10002
10003 /* If the last stop offset is different from the current one it means we
10004 are disassembling a different glob of bytes. As such the optimization
10005 would not be safe and we should start over. */
10006 can_use_search_opt_p
10007 = private_data->last_mapping_sym >= 0
10008 && info->stop_offset == private_data->last_stop_offset;
10009
10010 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
10011 n = private_data->last_mapping_sym;
10012
10013 /* Look down while we haven't passed the location being disassembled.
10014 The reason for this is that there's no defined order between a symbol
10015 and an mapping symbol that may be at the same address. We may have to
10016 look at least one position ahead. */
10017 for (; n < info->symtab_size; n++)
10018 {
10019 addr = bfd_asymbol_value (info->symtab[n]);
10020 if (addr > pc)
10021 break;
10022 if (get_map_sym_type (info, n, &type))
10023 {
10024 last_sym = n;
10025 found = TRUE;
10026 }
10027 }
5bc5ae88 10028
796d6298
TC		 10029 if (!found)
10030 {
10031 n = info->symtab_pos;
10032 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
10033 n = private_data->last_mapping_sym;
10034
10035 /* No mapping symbol found at this address. Look backwards
10036 for a preceeding one, but don't go pass the section start
10037 otherwise a data section with no mapping symbol can pick up
10038 a text mapping symbol of a preceeding section. The documentation
10039 says section can be NULL, in which case we will seek up all the
10040 way to the top. */
10041 if (info->section)
10042 section_vma = info->section->vma;
10043
10044 for (; n >= 0; n--)
10045 {
10046 addr = bfd_asymbol_value (info->symtab[n]);
10047 if (addr < section_vma)
10048 break;
10049
10050 if (get_map_sym_type (info, n, &type))
10051 {
10052 last_sym = n;
10053 found = TRUE;
10054 break;
10055 }
10056 }
10057 }
10058 }
10059
10060 /* If no mapping symbol was found, try looking up without a mapping
10061 symbol. This is done by walking up from the current PC to the nearest
10062 symbol. We don't actually have to loop here since symtab_pos will
10063 contain the nearest symbol already. */
10064 if (!found)
5bc5ae88 10065 {
796d6298
TC		 10066 n = info->symtab_pos;
10067 if (n >= 0 && get_sym_code_type (info, n, &type))
5bc5ae88 10068 {
796d6298
TC		 10069 last_sym = n;
10070 found = TRUE;
5bc5ae88
RL		 10071 }
10072 }
10073
796d6298
TC		 10074 private_data->last_mapping_sym = last_sym;
10075 private_data->last_type = type;
10076 private_data->last_stop_offset = info->stop_offset;
5bc5ae88
RL		 10077
10078 *map_symbol = type;
10079 return found;
10080}
10081
0313a2b8
NC		 10082/* Given a bfd_mach_arm_XXX value, this function fills in the fields
10083 of the supplied arm_feature_set structure with bitmasks indicating
c0c468d5 10084 the supported base architectures and coprocessor extensions.
0313a2b8
NC		 10085
10086 FIXME: This could more efficiently implemented as a constant array,
10087 although it would also be less robust. */
10088
10089static void
10090select_arm_features (unsigned long mach,
10091 arm_feature_set * features)
10092{
c0c468d5
TP		 10093 arm_feature_set arch_fset;
10094 const arm_feature_set fpu_any = FPU_ANY;
10095
1af1dd51
MW		 10096#undef ARM_SET_FEATURES
10097#define ARM_SET_FEATURES(FSET) \
10098 { \
10099 const arm_feature_set fset = FSET; \
c0c468d5 10100 arch_fset = fset; \
1af1dd51 10101 }
823d2571 10102
c0c468d5
TP		 10103 /* When several architecture versions share the same bfd_mach_arm_XXX value
10104 the most featureful is chosen. */
0313a2b8
NC		 10105 switch (mach)
10106 {
c0c468d5
TP		 10107 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
10108 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
10109 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
10110 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
10111 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
10112 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
10113 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
10114 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
10115 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
10116 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
1af1dd51 10117 case bfd_mach_arm_ep9312:
c0c468d5
TP		 10118 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
10119 ARM_CEXT_MAVERICK | FPU_MAVERICK));
1af1dd51 10120 break;
c0c468d5
TP		 10121 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
10122 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
10123 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
10124 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
10125 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
10126 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
10127 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
10128 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
10129 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
10130 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
10131 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
10132 case bfd_mach_arm_8:
10133 {
0632eeea
SD		 10134 /* Add bits for extensions that Armv8.5-A recognizes. */
10135 arm_feature_set armv8_5_ext_fset
10136 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
10137 ARM_SET_FEATURES (ARM_ARCH_V8_5A);
10138 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset);
c0c468d5
TP		 10139 break;
10140 }
10141 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
10142 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
10143 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
73cd51e5
AV		 10144 case bfd_mach_arm_8_1M_MAIN:
10145 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
10146 force_thumb = 1;
10147 break;
c0c468d5
TP		 10148 /* If the machine type is unknown allow all architecture types and all
10149 extensions. */
10150 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
0313a2b8
NC		 10151 default:
10152 abort ();
10153 }
1af1dd51 10154#undef ARM_SET_FEATURES
c0c468d5
TP		 10155
10156 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
10157 and thus on bfd_mach_arm_XXX value. Therefore for a given
10158 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
10159 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
0313a2b8
NC		 10160}
10161
10162
58efb6c0
NC		 10163/* NOTE: There are no checks in these routines that
10164 the relevant number of data bytes exist. */
baf0cc5e 10165
58efb6c0 10166static int
4a5329c6 10167print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 10168{
c19d1205
ZW		 10169 unsigned char b[4];
10170 long given;
10171 int status;
e821645d 10172 int is_thumb = FALSE;
b0e28b39 10173 int is_data = FALSE;
bd2e2557 10174 int little_code;
e821645d 10175 unsigned int size = 4;
4a5329c6 10176 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 10177 bfd_boolean found = FALSE;
b0e28b39 10178 struct arm_private_data *private_data;
58efb6c0 10179
dd92f639
NC		 10180 if (info->disassembler_options)
10181 {
65b48a81 10182 parse_arm_disassembler_options (info->disassembler_options);
b34976b6 10183
58efb6c0 10184 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 10185 info->disassembler_options = NULL;
10186 }
b34976b6 10187
0313a2b8
NC		 10188 /* PR 10288: Control which instructions will be disassembled. */
10189 if (info->private_data == NULL)
10190 {
b0e28b39 10191 static struct arm_private_data private;
0313a2b8
NC		 10192
10193 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
10194 /* If the user did not use the -m command line switch then default to
10195 disassembling all types of ARM instruction.
43e65147 10196
0313a2b8
NC		 10197 The info->mach value has to be ignored as this will be based on
10198 the default archictecture for the target and/or hints in the notes
10199 section, but it will never be greater than the current largest arm
10200 machine value (iWMMXt2), which is only equivalent to the V5TE
10201 architecture. ARM architectures have advanced beyond the machine
10202 value encoding, and these newer architectures would be ignored if
10203 the machine value was used.
10204
10205 Ie the -m switch is used to restrict which instructions will be
10206 disassembled. If it is necessary to use the -m switch to tell
10207 objdump that an ARM binary is being disassembled, eg because the
10208 input is a raw binary file, but it is also desired to disassemble
10209 all ARM instructions then use "-marm". This will select the
10210 "unknown" arm architecture which is compatible with any ARM
10211 instruction. */
10212 info->mach = bfd_mach_arm_unknown;
10213
10214 /* Compute the architecture bitmask from the machine number.
10215 Note: This assumes that the machine number will not change
10216 during disassembly.... */
b0e28b39 10217 select_arm_features (info->mach, & private.features);
0313a2b8 10218
1fbaefec
PB		 10219 private.last_mapping_sym = -1;
10220 private.last_mapping_addr = 0;
796d6298 10221 private.last_stop_offset = 0;
b0e28b39
DJ		 10222
10223 info->private_data = & private;
0313a2b8 10224 }
b0e28b39
DJ		 10225
10226 private_data = info->private_data;
10227
bd2e2557
SS		 10228 /* Decide if our code is going to be little-endian, despite what the
10229 function argument might say. */
10230 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
10231
b0e28b39
DJ		 10232 /* For ELF, consult the symbol table to determine what kind of code
10233 or data we have. */
8977d4b2 10234 if (info->symtab_size != 0
e821645d
DJ		 10235 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
10236 {
10237 bfd_vma addr;
796d6298 10238 int n;
e821645d 10239 int last_sym = -1;
b0e28b39 10240 enum map_type type = MAP_ARM;
e821645d 10241
796d6298
TC		 10242 found = mapping_symbol_for_insn (pc, info, &type);
10243 last_sym = private_data->last_mapping_sym;
e821645d 10244
1fbaefec
PB		 10245 is_thumb = (private_data->last_type == MAP_THUMB);
10246 is_data = (private_data->last_type == MAP_DATA);
b34976b6 10247
e821645d
DJ		 10248 /* Look a little bit ahead to see if we should print out
10249 two or four bytes of data. If there's a symbol,
10250 mapping or otherwise, after two bytes then don't
10251 print more. */
10252 if (is_data)
10253 {
10254 size = 4 - (pc & 3);
10255 for (n = last_sym + 1; n < info->symtab_size; n++)
10256 {
10257 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 10258 if (addr > pc
10259 && (info->section == NULL
10260 || info->section == info->symtab[n]->section))
e821645d
DJ		 10261 {
10262 if (addr - pc < size)
10263 size = addr - pc;
10264 break;
10265 }
10266 }
10267 /* If the next symbol is after three bytes, we need to
10268 print only part of the data, so that we can use either
10269 .byte or .short. */
10270 if (size == 3)
10271 size = (pc & 1) ? 1 : 2;
10272 }
10273 }
10274
10275 if (info->symbols != NULL)
252b5132 10276 {
5876e06d
NC		 10277 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
10278 {
2f0ca46a 10279 coff_symbol_type * cs;
b34976b6 10280
5876e06d
NC		 10281 cs = coffsymbol (*info->symbols);
10282 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
10283 || cs->native->u.syment.n_sclass == C_THUMBSTAT
10284 || cs->native->u.syment.n_sclass == C_THUMBLABEL
10285 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
10286 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
10287 }
e821645d
DJ		 10288 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
10289 && !found)
5876e06d 10290 {
2087ad84
PB		 10291 /* If no mapping symbol has been found then fall back to the type
10292 of the function symbol. */
e821645d
DJ		 10293 elf_symbol_type * es;
10294 unsigned int type;
2087ad84 10295
e821645d
DJ		 10296 es = *(elf_symbol_type **)(info->symbols);
10297 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 10298
39d911fc
TP		 10299 is_thumb =
10300 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
10301 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
5876e06d 10302 }
e49d43ff
TG		 10303 else if (bfd_asymbol_flavour (*info->symbols)
10304 == bfd_target_mach_o_flavour)
10305 {
10306 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
10307
10308 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
10309 }
5876e06d 10310 }
b34976b6 10311
e821645d
DJ		 10312 if (force_thumb)
10313 is_thumb = TRUE;
10314
b8f9ee44
CL		 10315 if (is_data)
10316 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
10317 else
10318 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
10319
c19d1205 10320 info->bytes_per_line = 4;
252b5132 10321
1316c8b3
NC		 10322 /* PR 10263: Disassemble data if requested to do so by the user. */
10323 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 10324 {
10325 int i;
10326
1316c8b3 10327 /* Size was already set above. */
e821645d
DJ		 10328 info->bytes_per_chunk = size;
10329 printer = print_insn_data;
10330
fe56b6ce 10331 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 10332 given = 0;
10333 if (little)
10334 for (i = size - 1; i >= 0; i--)
10335 given = b[i] | (given << 8);
10336 else
10337 for (i = 0; i < (int) size; i++)
10338 given = b[i] | (given << 8);
10339 }
10340 else if (!is_thumb)
252b5132 10341 {
c19d1205
ZW		 10342 /* In ARM mode endianness is a straightforward issue: the instruction
10343 is four bytes long and is either ordered 0123 or 3210. */
10344 printer = print_insn_arm;
10345 info->bytes_per_chunk = 4;
4a5329c6 10346 size = 4;
c19d1205 10347
0313a2b8 10348 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 10349 if (little_code)
c19d1205
ZW		 10350 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
10351 else
10352 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
252b5132 10353 }
58efb6c0 10354 else
252b5132 10355 {
c19d1205
ZW		 10356 /* In Thumb mode we have the additional wrinkle of two
10357 instruction lengths. Fortunately, the bits that determine
10358 the length of the current instruction are always to be found
10359 in the first two bytes. */
4a5329c6 10360 printer = print_insn_thumb16;
c19d1205 10361 info->bytes_per_chunk = 2;
4a5329c6
ZW		 10362 size = 2;
10363
fe56b6ce 10364 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 10365 if (little_code)
9a2ff3f5
AM		 10366 given = (b[0]) | (b[1] << 8);
10367 else
10368 given = (b[1]) | (b[0] << 8);
10369
c19d1205 10370 if (!status)
252b5132 10371 {
c19d1205
ZW		 10372 /* These bit patterns signal a four-byte Thumb
10373 instruction. */
10374 if ((given & 0xF800) == 0xF800
10375 || (given & 0xF800) == 0xF000
10376 || (given & 0xF800) == 0xE800)
252b5132 10377 {
0313a2b8 10378 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 10379 if (little_code)
c19d1205 10380 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 10381 else
c19d1205
ZW		 10382 given = (b[1]) | (b[0] << 8) | (given << 16);
10383
10384 printer = print_insn_thumb32;
4a5329c6 10385 size = 4;
252b5132 10386 }
252b5132 10387 }
c22aaad1
PB		 10388
10389 if (ifthen_address != pc)
0313a2b8 10390 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 10391
10392 if (ifthen_state)
10393 {
10394 if ((ifthen_state & 0xf) == 0x8)
10395 ifthen_next_state = 0;
10396 else
10397 ifthen_next_state = (ifthen_state & 0xe0)
10398 | ((ifthen_state & 0xf) << 1);
10399 }
252b5132 10400 }
b34976b6 10401
c19d1205
ZW		 10402 if (status)
10403 {
10404 info->memory_error_func (status, pc, info);
10405 return -1;
10406 }
6a56ec7e
NC		 10407 if (info->flags & INSN_HAS_RELOC)
10408 /* If the instruction has a reloc associated with it, then
10409 the offset field in the instruction will actually be the
10410 addend for the reloc. (We are using REL type relocs).
10411 In such cases, we can ignore the pc when computing
10412 addresses, since the addend is not currently pc-relative. */
10413 pc = 0;
b34976b6 10414
4a5329c6 10415 printer (pc, info, given);
c22aaad1
PB		 10416
10417 if (is_thumb)
10418 {
10419 ifthen_state = ifthen_next_state;
10420 ifthen_address += size;
10421 }
4a5329c6 10422 return size;
252b5132
RH		 10423}
10424
10425int
4a5329c6 10426print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 10427{
bd2e2557
SS		 10428 /* Detect BE8-ness and record it in the disassembler info. */
10429 if (info->flavour == bfd_target_elf_flavour
10430 && info->section != NULL
10431 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
10432 info->endian_code = BFD_ENDIAN_LITTLE;
10433
b34976b6 10434 return print_insn (pc, info, FALSE);
58efb6c0 10435}
01c7f630 10436
58efb6c0 10437int
4a5329c6 10438print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 10439{
b34976b6 10440 return print_insn (pc, info, TRUE);
58efb6c0 10441}
252b5132 10442
471b9d15 10443const disasm_options_and_args_t *
65b48a81
PB		 10444disassembler_options_arm (void)
10445{
471b9d15 10446 static disasm_options_and_args_t *opts_and_args;
65b48a81 10447
471b9d15 10448 if (opts_and_args == NULL)
65b48a81 10449 {
471b9d15 10450 disasm_options_t *opts;
65b48a81 10451 unsigned int i;
471b9d15
MR		 10452
10453 opts_and_args = XNEW (disasm_options_and_args_t);
10454 opts_and_args->args = NULL;
10455
10456 opts = &opts_and_args->options;
65b48a81
PB		 10457 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
10458 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
471b9d15 10459 opts->arg = NULL;
65b48a81
PB		 10460 for (i = 0; i < NUM_ARM_OPTIONS; i++)
10461 {
10462 opts->name[i] = regnames[i].name;
10463 if (regnames[i].description != NULL)
10464 opts->description[i] = _(regnames[i].description);
10465 else
10466 opts->description[i] = NULL;
10467 }
10468 /* The array we return must be NULL terminated. */
10469 opts->name[i] = NULL;
10470 opts->description[i] = NULL;
10471 }
10472
471b9d15 10473 return opts_and_args;
65b48a81
PB		 10474}
10475
58efb6c0 10476void
4a5329c6 10477print_arm_disassembler_options (FILE *stream)
58efb6c0 10478{
65b48a81 10479 unsigned int i, max_len = 0;
58efb6c0
NC		 10480 fprintf (stream, _("\n\
10481The following ARM specific disassembler options are supported for use with\n\
10482the -M switch:\n"));
b34976b6 10483
65b48a81
PB		 10484 for (i = 0; i < NUM_ARM_OPTIONS; i++)
10485 {
10486 unsigned int len = strlen (regnames[i].name);
10487 if (max_len < len)
10488 max_len = len;
10489 }
58efb6c0 10490
65b48a81
PB		 10491 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
10492 fprintf (stream, " %s%*c %s\n",
10493 regnames[i].name,
10494 (int)(max_len - strlen (regnames[i].name)), ' ',
10495 _(regnames[i].description));
252b5132 10496}
GDB Binutils - Deliverables
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