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[binutils, ARM, 8/16] BFL infrastructure with new global reloc R_ARM_THM_BF18
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
CommitLineData
252b5132 1/* Instruction printing code for the ARM
82704155 2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
2fbad815 24
6394c606 25#include "disassemble.h"
2fbad815 26#include "opcode/arm.h"
252b5132 27#include "opintl.h"
31e0f3cd 28#include "safe-ctype.h"
65b48a81 29#include "libiberty.h"
0dbde4cf 30#include "floatformat.h"
252b5132 31
baf0cc5e 32/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 33#include "coff/internal.h"
34#include "libcoff.h"
2d5d5a8f 35#include "bfd.h"
252b5132
RH		 36#include "elf-bfd.h"
37#include "elf/internal.h"
38#include "elf/arm.h"
e49d43ff 39#include "mach-o.h"
252b5132 40
6b5d3a4d 41/* FIXME: Belongs in global header. */
01c7f630 42#ifndef strneq
58efb6c0
NC		 43#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
44#endif
45
1fbaefec
PB		 46/* Cached mapping symbol state. */
47enum map_type
48{
49 MAP_ARM,
50 MAP_THUMB,
51 MAP_DATA
52};
53
b0e28b39
DJ		 54struct arm_private_data
55{
56 /* The features to use when disassembling optional instructions. */
57 arm_feature_set features;
58
1fbaefec
PB		 59 /* Track the last type (although this doesn't seem to be useful) */
60 enum map_type last_type;
61
62 /* Tracking symbol table information */
63 int last_mapping_sym;
796d6298
TC		 64
65 /* The end range of the current range being disassembled. */
66 bfd_vma last_stop_offset;
1fbaefec 67 bfd_vma last_mapping_addr;
b0e28b39
DJ		 68};
69
6b5d3a4d
ZW		 70struct opcode32
71{
823d2571
TG		 72 arm_feature_set arch; /* Architecture defining this insn. */
73 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 74 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 75 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 76};
77
78struct opcode16
79{
823d2571 80 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 81 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 82 const char *assembler; /* How to disassemble this insn. */
83};
b7693d02 84
8f06b2d8 85/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 86
2fbad815 87 %% %
4a5329c6 88
c22aaad1 89 %c print condition code (always bits 28-31 in ARM mode)
37b37b2d 90 %q print shifter argument
e2efe87d
MGD		 91 %u print condition code (unconditional in ARM mode,
92 UNPREDICTABLE if not AL in Thumb)
4a5329c6 93 %A print address for ldc/stc/ldf/stf instruction
16980d0b 94 %B print vstm/vldm register list
4a5329c6 95 %I print cirrus signed shift immediate: bits 0..3|4..6
4a5329c6
ZW		 96 %F print the COUNT field of a LFM/SFM instruction.
97 %P print floating point precision in arithmetic insn
98 %Q print floating point precision in ldf/stf insn
99 %R print floating point rounding mode
100
33399f07 101 %<bitfield>c print as a condition code (for vsel)
4a5329c6 102 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 103 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
104 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 105 %<bitfield>d print the bitfield in decimal
16980d0b 106 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 107 %<bitfield>x print the bitfield in hex
108 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 109 %<bitfield>f print a floating point constant if >7 else a
110 floating point register
4a5329c6
ZW		 111 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
112 %<bitfield>g print as an iWMMXt 64-bit register
113 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 114 %<bitfield>D print as a NEON D register
115 %<bitfield>Q print as a NEON Q register
c28eeff2 116 %<bitfield>V print as a NEON D or Q register
6f1c2142 117 %<bitfield>E print a quarter-float immediate value
4a5329c6 118
16980d0b 119 %y<code> print a single precision VFP reg.
2fbad815 120 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 121 %z<code> print a double precision VFP reg
2fbad815 122 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 123
16980d0b
JB		 124 %<bitfield>'c print specified char iff bitfield is all ones
125 %<bitfield>`c print specified char iff bitfield is all zeroes
126 %<bitfield>?ab... select from array of values in big endian order
43e65147 127
2fbad815 128 %L print as an iWMMXt N/M width field.
4a5329c6 129 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 130 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 131 versions.
132 %i print 5-bit immediate in bits 8,3..0
133 (print "32" when 0)
fe56b6ce 134 %r print register offset address for wldt/wstr instruction. */
2fbad815 135
21d799b5 136enum opcode_sentinel_enum
05413229
NC		 137{
138 SENTINEL_IWMMXT_START = 1,
139 SENTINEL_IWMMXT_END,
140 SENTINEL_GENERIC_START
141} opcode_sentinels;
142
aefd8a40 143#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
0b347048
TC		 144#define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
145#define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
c1e26897 146#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 147
8f06b2d8 148/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 149
8f06b2d8 150static const struct opcode32 coprocessor_opcodes[] =
2fbad815 151{
2fbad815 152 /* XScale instructions. */
823d2571
TG		 153 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
154 0x0e200010, 0x0fff0ff0,
155 "mia%c\tacc0, %0-3r, %12-15r"},
156 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
157 0x0e280010, 0x0fff0ff0,
158 "miaph%c\tacc0, %0-3r, %12-15r"},
159 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
160 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
161 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
162 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
163 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
164 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 165
2fbad815 166 /* Intel Wireless MMX technology instructions. */
823d2571
TG		 167 {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
168 {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
169 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
170 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
171 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
172 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
173 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
174 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
175 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
176 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
177 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
178 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
179 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
180 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
181 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
182 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
183 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
184 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
185 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
186 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
187 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
188 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
189 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
190 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
191 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
192 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
193 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
194 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
195 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
196 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
197 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
198 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
199 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
200 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
201 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
202 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
203 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
204 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
205 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
206 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
207 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
208 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
209 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
210 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
211 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
212 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
213 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
214 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
215 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
216 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
217 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
218 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
219 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
220 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
221 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
222 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
223 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
224 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
225 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
226 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
227 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
228 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
229 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
230 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
231 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
232 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
233 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
234 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
235 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
236 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
237 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
238 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
239 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
240 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
241 0x0e800120, 0x0f800ff0,
242 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
243 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
244 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
245 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
246 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
247 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
248 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
249 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
250 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
251 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
252 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
253 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
254 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
255 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
256 0x0e8000a0, 0x0f800ff0,
257 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
258 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
259 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
260 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
261 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
262 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
263 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
264 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
265 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
266 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
267 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
268 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
269 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
270 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
271 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
272 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
273 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
274 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
275 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
276 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
277 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
278 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
279 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
280 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
281 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
282 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
283 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
284 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
285 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
286 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
287 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
288 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
289 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
290 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
291 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
292 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
293 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
294 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
295 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
296 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
297 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
298 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
299 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
300 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
301 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
302 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
303 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
304 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
305 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
306 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
307 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
308 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
309 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
310 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
311 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
312 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
313 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
314 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
315 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
316 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
317 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
318 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
319 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
320 {ARM_FEATURE_CORE_LOW (0),
321 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 322
fe56b6ce 323 /* Floating point coprocessor (FPA) instructions. */
823d2571
TG		 324 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
325 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
326 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
327 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
328 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
329 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
330 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
331 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
332 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
333 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
334 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
335 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
336 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
337 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
338 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
339 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
340 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
341 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
342 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
343 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
344 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
345 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
346 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
347 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
348 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
349 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
350 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
351 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
352 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
353 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
354 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
355 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
356 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
357 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
358 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
359 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
360 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
361 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
362 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
363 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
364 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
365 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
366 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
367 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
368 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
369 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
370 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
371 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
372 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
373 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
374 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
375 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
376 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
377 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
378 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
379 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
380 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
381 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
382 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
383 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
384 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
385 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
386 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
387 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
388 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
389 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
390 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
391 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
392 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
393 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
394 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
395 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
396 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
397 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
398 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
399 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
400 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
401 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
402 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
403 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
404 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
405 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
406 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
407 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
408 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
409 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 410
16a1fa25
TP		 411 /* ARMv8-M Mainline Security Extensions instructions. */
412 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
413 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
414 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
415 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
416
fe56b6ce 417 /* Register load/store. */
823d2571
TG		 418 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
419 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
420 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
421 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
422 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
423 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
424 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
425 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
426 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
427 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
428 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
429 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
430 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
431 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
432 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
433 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
434 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
435 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
436 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
437 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
438 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
439 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
440 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
441 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
442 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
443 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
444 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
445 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
446 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
447 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
448 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
449 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
450
451 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
452 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
453 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
454 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
455 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
456 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
457 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
458 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 459
fe56b6ce 460 /* Data transfer between ARM and NEON registers. */
823d2571
TG		 461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
462 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
464 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
466 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
468 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
470 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
472 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
474 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
476 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
478 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
480 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
482 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
484 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
486 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
487 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
488 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 489 /* Half-precision conversion instructions. */
823d2571
TG		 490 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
491 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
492 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
493 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
494 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
495 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
496 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
497 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 498
fe56b6ce 499 /* Floating point coprocessor (VFP) instructions. */
823d2571
TG		 500 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
501 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
502 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
503 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
504 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
505 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
506 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
507 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
40c7d507
RR		 508 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
509 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
823d2571
TG		 510 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
511 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
512 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
513 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
514 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
515 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
516 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
517 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
518 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
519 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
520 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
521 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
40c7d507
RR		 522 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
523 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
823d2571
TG		 524 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
525 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
526 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
527 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
528 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
529 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
530 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
531 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
532 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
533 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
534 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
535 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
536 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
537 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
538 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
539 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
540 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
541 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
542 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
543 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
544 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
545 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
546 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
547 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
548 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
549 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
550 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
551 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
552 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
553 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
554 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
555 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
556 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
557 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
558 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
559 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
560 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
561 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
562 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
563 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
564 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
565 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
566 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
567 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
568 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
569 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
570 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
571 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
572 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
573 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
574 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
575 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
576 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
577 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
578 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
579 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
580 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
581 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
582 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
583 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
584 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
585 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
586 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
587 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
588 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
589 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
590 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
591 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
592 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6f1c2142 593 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
823d2571 594 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6f1c2142 595 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
823d2571
TG		 596 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
597 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
598 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
599 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
600 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
601 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
602 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
603 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
604 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
605 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
606 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
607 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
608 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
609 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
610 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
611 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
612 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
613 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
614 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
615 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
616 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
617 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
618 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
619 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
620 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
621 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
622 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
623 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
624 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
625 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
626 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
627 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
628 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
629 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
630 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
631 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
632 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
633 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
634 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
635 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
636 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
637 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 638
639 /* Cirrus coprocessor instructions. */
823d2571
TG		 640 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
641 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
642 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
643 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
644 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
645 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
646 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
647 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
648 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
649 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
650 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
651 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
652 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
653 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
654 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
655 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
656 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
657 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
658 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
659 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
660 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
661 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
662 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
663 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
664 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
665 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
666 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
667 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
668 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
669 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
670 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
671 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
672 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
673 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
674 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
675 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
676 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
677 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
678 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
679 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
680 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
681 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
682 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
683 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
684 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
685 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
686 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
687 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
688 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
689 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
690 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
691 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
692 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
693 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
694 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
695 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
696 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
697 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
698 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
699 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
700 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
701 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
702 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
703 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
704 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
705 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
706 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
707 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
708 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
709 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
710 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
711 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
712 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
713 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
714 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
715 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
716 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
717 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
718 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
719 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
720 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
721 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
722 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
723 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
724 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
725 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
726 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
727 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
728 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
729 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
730 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
731 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
732 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
733 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
734 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
735 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
736 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
737 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
738 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
739 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
740 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
741 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
742 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
743 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
744 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
745 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
746 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
747 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
748 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
749 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
750 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
751 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
752 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
753 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
754 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
755 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
756 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
757 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
758 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
759 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
760 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
761 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
762 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
763 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
764 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
765 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
766 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
767 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
768 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
769 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
770 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
771 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
772 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
773 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
774 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
775 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
776 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
777 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
778 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
779 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
780 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
781 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
782 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
783 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
784 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
785 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
786 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
787 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
788 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
789 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
790 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
791 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
792 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
793 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
794 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
795 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
796 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
797 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
798 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
799 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
800 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
801 0x0e000600, 0x0ff00f10,
802 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
803 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
804 0x0e100600, 0x0ff00f10,
805 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
806 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
807 0x0e200600, 0x0ff00f10,
808 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
809 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
810 0x0e300600, 0x0ff00f10,
811 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 812
62f3b8c8 813 /* VFP Fused multiply add instructions. */
823d2571
TG		 814 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
815 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
816 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
817 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
818 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
819 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
820 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
821 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
822 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
824 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
825 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
826 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
827 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
828 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
829 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 830
33399f07 831 /* FP v5. */
823d2571 832 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 833 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
823d2571 834 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 835 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
823d2571 836 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 837 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
823d2571 838 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 839 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
823d2571 840 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 841 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
823d2571 842 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 843 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
823d2571
TG		 844 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
845 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
846 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
847 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
848 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
849 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
850 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
851 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
852 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 853 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
823d2571 854 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 855 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 856
05413229 857 /* Generic coprocessor instructions. */
823d2571
TG		 858 {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
860 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
862 0x0c500000, 0x0ff00000,
863 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
865 0x0e000000, 0x0f000010,
866 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
868 0x0e10f010, 0x0f10f010,
869 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
871 0x0e100010, 0x0f100010,
872 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
874 0x0e000010, 0x0f100010,
875 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
877 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
879 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
2fbad815 880
05413229 881 /* V6 coprocessor instructions. */
823d2571
TG		 882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
883 0xfc500000, 0xfff00000,
884 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
886 0xfc400000, 0xfff00000,
887 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
8f06b2d8 888
c28eeff2
SN		 889 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
890 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
891 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
892 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
893 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
894 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
895 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
896 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
897 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
898 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
899 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
900 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
901 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
902 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 903 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
c28eeff2 904 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 905 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
c28eeff2 906 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 907 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
c28eeff2 908 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 909 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
c28eeff2 910
c604a79a
JW		 911 /* Dot Product instructions in the space of coprocessor 13. */
912 {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
913 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
914 {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
915 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
916
dec41383
JW		 917 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
918 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
919 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
920 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
921 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
922 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
923 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
924 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
925 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
926 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
927 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
928 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
929 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
930 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
931 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
932 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
933 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
934
05413229 935 /* V5 coprocessor instructions. */
823d2571
TG		 936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
937 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
939 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
941 0xfe000000, 0xff000010,
942 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
944 0xfe000010, 0xff100010,
945 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
947 0xfe100010, 0xff100010,
948 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
949
b0c11777
RL		 950 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
951 cp_num: bit <11:8> == 0b1001.
952 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
953 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
954 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
955 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
956 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
957 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
958 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
959 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
960 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
961 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
962 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
963 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
964 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
965 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
966 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
967 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
968 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
969 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
970 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
971 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
972 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
973 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
974 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
975 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
976 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
977 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
978 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
979 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
980 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
981 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
982 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
983 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
984 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
985 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
986 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
987 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
988 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
989 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
990 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
991 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
992 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
993 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
994 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
995 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
996 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
997 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
998 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
999 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1000 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1001 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1002 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1003 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1004 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1005 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1006 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1007 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1008 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1009 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1010 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1011 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1012 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1013 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1014 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1015 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1016 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1017 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1018 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1019 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1020 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1021 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1022 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1023
49e8a725
SN		 1024 /* ARMv8.3 javascript conversion instruction. */
1025 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1026 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1027
823d2571 1028 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 1029};
1030
16980d0b
JB		 1031/* Neon opcode table: This does not encode the top byte -- that is
1032 checked by the print_insn_neon routine, as it depends on whether we are
1033 doing thumb32 or arm32 disassembly. */
1034
1035/* print_insn_neon recognizes the following format control codes:
1036
1037 %% %
1038
c22aaad1 1039 %c print condition code
e2efe87d
MGD		 1040 %u print condition code (unconditional in ARM mode,
1041 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 1042 %A print v{st,ld}[1234] operands
1043 %B print v{st,ld}[1234] any one operands
1044 %C print v{st,ld}[1234] single->all operands
1045 %D print scalar
1046 %E print vmov, vmvn, vorr, vbic encoded constant
1047 %F print vtbl,vtbx register list
1048
1049 %<bitfield>r print as an ARM register
1050 %<bitfield>d print the bitfield in decimal
1051 %<bitfield>e print the 2^N - bitfield in decimal
1052 %<bitfield>D print as a NEON D register
1053 %<bitfield>Q print as a NEON Q register
1054 %<bitfield>R print as a NEON D or Q register
1055 %<bitfield>Sn print byte scaled width limited by n
1056 %<bitfield>Tn print short scaled width limited by n
1057 %<bitfield>Un print long scaled width limited by n
43e65147 1058
16980d0b
JB		 1059 %<bitfield>'c print specified char iff bitfield is all ones
1060 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1061 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1062
1063static const struct opcode32 neon_opcodes[] =
1064{
fe56b6ce 1065 /* Extract. */
823d2571
TG		 1066 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1067 0xf2b00840, 0xffb00850,
1068 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1069 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1070 0xf2b00000, 0xffb00810,
1071 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 1072
fe56b6ce 1073 /* Move data element to all lanes. */
823d2571
TG		 1074 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1075 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1076 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1077 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1078 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1079 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 1080
fe56b6ce 1081 /* Table lookup. */
823d2571
TG		 1082 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1083 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1084 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1085 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1086
8e79c3df 1087 /* Half-precision conversions. */
823d2571
TG		 1088 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1089 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1090 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1091 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1092
1093 /* NEON fused multiply add instructions. */
823d2571 1094 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1095 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1096 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1097 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1098 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1099 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1100 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1101 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1102
fe56b6ce 1103 /* Two registers, miscellaneous. */
823d2571
TG		 1104 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1105 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1106 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1107 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1108 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1109 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1110 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1111 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1112 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1113 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1114 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1115 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1116 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1117 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1118 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1119 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1120 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1121 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1122 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1123 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1124 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1125 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1126 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1127 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1128 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1129 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1130 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1131 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1132 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1133 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1134 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1135 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1136 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1137 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1138 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1139 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1140 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1141 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1142 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1143 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1144 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1145 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1146 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1147 0xf3b20300, 0xffb30fd0,
1148 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1149 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1150 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1151 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1152 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1153 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1154 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1155 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1156 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1157 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1158 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1159 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1160 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1161 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1162 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1163 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1164 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1165 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1166 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1167 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1168 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1169 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1170 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1171 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1172 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1173 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1174 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1175 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1176 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1177 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1178 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1179 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1180 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1181 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1182 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1183 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1184 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1185 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1186 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1187 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1188 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1189 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1190 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1191 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1192 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1193 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1194 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1195 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301 1196 0xf3bb0600, 0xffbf0e10,
823d2571 1197 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1198 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1199 0xf3b70600, 0xffbf0e10,
1200 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
16980d0b 1201
fe56b6ce 1202 /* Three registers of the same length. */
823d2571
TG		 1203 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1204 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1205 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1206 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1207 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1208 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1209 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1210 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1211 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1212 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1213 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1214 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1215 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1216 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1217 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1218 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1219 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1220 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1221 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1222 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1223 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1224 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1225 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1226 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1227 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1228 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1229 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1230 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1231 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1232 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1233 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1234 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1235 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1236 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1237 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1238 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1239 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1240 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1241 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1242 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1243 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1244 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1245 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1246 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1247 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1248 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1249 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1250 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1251 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1252 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1253 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1254 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1255 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1256 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1257 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1258 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1259 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1260 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1261 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1262 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1263 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1264 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1265 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1266 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1267 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1268 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1269 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1270 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1271 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1272 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1273 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1274 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1275 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1276 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1277 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1278 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1279 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1280 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1281 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1282 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1283 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1284 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1285 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1286 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1287 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1288 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1289 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1290 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1291 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1292 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1293 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1294 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1295 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1296 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1297 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1298 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1299 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1300 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1301 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1302 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1303 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1304 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1305 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1306 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1307 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1308 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1309 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1310 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1311 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1312 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1313 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1314 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1315 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1316 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1317 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1318 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1319 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1320 0xf2000b00, 0xff800f10,
1321 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1322 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1323 0xf2000b10, 0xff800f10,
1324 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1325 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1326 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1327 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1328 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1329 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1330 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1331 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1332 0xf3000b00, 0xff800f10,
1333 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1334 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1335 0xf2000000, 0xfe800f10,
1336 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1337 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1338 0xf2000010, 0xfe800f10,
1339 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1340 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1341 0xf2000100, 0xfe800f10,
1342 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1343 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1344 0xf2000200, 0xfe800f10,
1345 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1346 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1347 0xf2000210, 0xfe800f10,
1348 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1349 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1350 0xf2000300, 0xfe800f10,
1351 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1352 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1353 0xf2000310, 0xfe800f10,
1354 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1355 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1356 0xf2000400, 0xfe800f10,
1357 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1358 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1359 0xf2000410, 0xfe800f10,
1360 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1361 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1362 0xf2000500, 0xfe800f10,
1363 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1364 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1365 0xf2000510, 0xfe800f10,
1366 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1367 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1368 0xf2000600, 0xfe800f10,
1369 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1370 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1371 0xf2000610, 0xfe800f10,
1372 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1373 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1374 0xf2000700, 0xfe800f10,
1375 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1376 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1377 0xf2000710, 0xfe800f10,
1378 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1379 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1380 0xf2000910, 0xfe800f10,
1381 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1382 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1383 0xf2000a00, 0xfe800f10,
1384 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1385 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1386 0xf2000a10, 0xfe800f10,
1387 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1388 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1389 0xf3000b10, 0xff800f10,
1390 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1391 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1392 0xf3000c10, 0xff800f10,
1393 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1394
fe56b6ce 1395 /* One register and an immediate value. */
823d2571
TG		 1396 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1397 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1398 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1399 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1400 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1401 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1402 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1403 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1404 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1405 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1406 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1407 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1408 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1409 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1410 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1411 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1412 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1413 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1414 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1415 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1416 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1417 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1418 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1419 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1420 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1421 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1422
fe56b6ce 1423 /* Two registers and a shift amount. */
823d2571
TG		 1424 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1425 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1426 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1427 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1428 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1429 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1430 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1431 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1432 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1433 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1434 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1435 0xf2880950, 0xfeb80fd0,
1436 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1437 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1438 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1439 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1440 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1441 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1442 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1443 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1444 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1445 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1446 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1447 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1448 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1449 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1450 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1451 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1452 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1453 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1454 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1456 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1457 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1458 0xf2900950, 0xfeb00fd0,
1459 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1460 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1461 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1462 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1463 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1465 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1466 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1467 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1468 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1469 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1470 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1471 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1473 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1474 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1475 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1477 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1478 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1479 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1481 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1482 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1483 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1484 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1485 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1487 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1489 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1490 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1491 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1492 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1493 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1494 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1495 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1496 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1497 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1498 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1499 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1500 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1501 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1502 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1503 0xf2a00950, 0xfea00fd0,
1504 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1511 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1512 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1515 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1517 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1518 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1519 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1520 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1521 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1522 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1523 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1524 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1525 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1526 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1527 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1528 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1530 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1531 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1532 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1533 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1534 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1535 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1536 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1537 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1538 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1539 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1540 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1541 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1542 0xf2a00e10, 0xfea00e90,
1543 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
cc933301
JW		 1544 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1545 0xf2a00c10, 0xfea00e90,
1546 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 1547
fe56b6ce 1548 /* Three registers of different lengths. */
823d2571
TG		 1549 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1550 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1551 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1552 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1553 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1554 0xf2800400, 0xff800f50,
1555 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1556 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1557 0xf2800600, 0xff800f50,
1558 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1559 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1560 0xf2800900, 0xff800f50,
1561 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1562 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1563 0xf2800b00, 0xff800f50,
1564 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1565 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1566 0xf2800d00, 0xff800f50,
1567 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1568 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1569 0xf3800400, 0xff800f50,
1570 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1571 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1572 0xf3800600, 0xff800f50,
1573 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1574 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1575 0xf2800000, 0xfe800f50,
1576 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1577 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1578 0xf2800100, 0xfe800f50,
1579 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1580 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1581 0xf2800200, 0xfe800f50,
1582 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1583 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1584 0xf2800300, 0xfe800f50,
1585 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1586 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1587 0xf2800500, 0xfe800f50,
1588 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1589 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1590 0xf2800700, 0xfe800f50,
1591 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1592 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1593 0xf2800800, 0xfe800f50,
1594 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1595 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1596 0xf2800a00, 0xfe800f50,
1597 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1598 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1599 0xf2800c00, 0xfe800f50,
1600 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 1601
fe56b6ce 1602 /* Two registers and a scalar. */
823d2571
TG		 1603 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1604 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1605 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1606 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1607 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1608 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1609 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1610 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1611 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1612 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1613 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1614 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1615 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1616 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1618 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1619 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1620 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1621 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1622 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1623 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1624 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1625 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1626 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1627 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1628 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1630 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1631 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1632 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1633 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1634 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1635 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1636 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1638 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1639 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1640 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1641 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1642 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1643 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1644 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1646 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1647 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1648 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1650 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1651 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1652 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1653 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1654 0xf2800240, 0xfe800f50,
1655 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1656 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1657 0xf2800640, 0xfe800f50,
1658 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1659 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1660 0xf2800a40, 0xfe800f50,
1661 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 1662 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1663 0xf2800e40, 0xff800f50,
1664 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1665 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1666 0xf2800f40, 0xff800f50,
1667 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1668 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1669 0xf3800e40, 0xff800f50,
1670 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1671 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1672 0xf3800f40, 0xff800f50,
1673 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1674 },
16980d0b 1675
fe56b6ce 1676 /* Element and structure load/store. */
823d2571
TG		 1677 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1678 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1679 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1680 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1681 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1682 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1683 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1684 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1685 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1686 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1687 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1688 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1689 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1690 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1691 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1692 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1693 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1694 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1695 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1696 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1697 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1698 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1699 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1700 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1701 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1702 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1703 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1704 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1705 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1706 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1707 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1708 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1709 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1710 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1711 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1712 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1713 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1714 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1715
1716 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 1717};
1718
8f06b2d8
PB		 1719/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
1720 ordered: they must be searched linearly from the top to obtain a correct
1721 match. */
1722
1723/* print_insn_arm recognizes the following format control codes:
1724
1725 %% %
1726
1727 %a print address for ldr/str instruction
1728 %s print address for ldr/str halfword/signextend instruction
c1e26897 1729 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 1730 %b print branch destination
1731 %c print condition code (always bits 28-31)
1732 %m print register mask for ldm/stm instruction
1733 %o print operand2 (immediate or register + shift)
1734 %p print 'p' iff bits 12-15 are 15
1735 %t print 't' iff bit 21 set and bit 24 clear
1736 %B print arm BLX(1) destination
1737 %C print the PSR sub type.
62b3e311
PB		 1738 %U print barrier type.
1739 %P print address for pli instruction.
8f06b2d8
PB		 1740
1741 %<bitfield>r print as an ARM register
9eb6c0f1 1742 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 1743 %<bitfield>R as %r but r15 is UNPREDICTABLE
1744 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1745 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 1746 %<bitfield>d print the bitfield in decimal
43e65147 1747 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 1748 %<bitfield>x print the bitfield in hex
1749 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 1750
16980d0b
JB		 1751 %<bitfield>'c print specified char iff bitfield is all ones
1752 %<bitfield>`c print specified char iff bitfield is all zeroes
1753 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 1754
8f06b2d8
PB		 1755 %e print arm SMI operand (bits 0..7,8..19).
1756 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 1757 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
1758 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 1759
8f06b2d8
PB		 1760static const struct opcode32 arm_opcodes[] =
1761{
1762 /* ARM instructions. */
823d2571
TG		 1763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1764 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1766 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1767
1768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
1769 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1771 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1773 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
1775 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1777 0x00800090, 0x0fa000f0,
1778 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1780 0x00a00090, 0x0fa000f0,
1781 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 1782
105bde57 1783 /* V8.2 RAS extension instructions. */
4d1464f2 1784 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 1785 0xe320f010, 0xffffffff, "esb"},
1786
53c4b28b 1787 /* V8 instructions. */
823d2571
TG		 1788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1789 0x0320f005, 0x0fffffff, "sevl"},
f7dd2fb2
TC		 1790 /* Defined in V8 but is in NOP space so available to all arch. */
1791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
823d2571 1792 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
4ed7ed8d 1793 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 1794 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1795 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 1796 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1798 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1800 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 1801 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1802 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1803 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1804 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1805 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1806 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1807 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1808 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1809 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1810 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1811 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1812 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1813 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1814 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1815 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1816 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1817 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1818 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1819 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 1820 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 1821 /* CRC32 instructions. */
823d2571
TG		 1822 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1823 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
1824 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1825 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
1826 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1827 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
1828 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1829 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
1830 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1831 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
1832 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1833 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 1834
ddfded2f
MW		 1835 /* Privileged Access Never extension instructions. */
1836 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
1837 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
1838
90ec0d68 1839 /* Virtualization Extension instructions. */
823d2571
TG		 1840 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
1841 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 1842
eea54501 1843 /* Integer Divide Extension instructions. */
823d2571
TG		 1844 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1845 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1846 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1847 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 1848
60e5ef9f 1849 /* MP Extension instructions. */
823d2571 1850 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 1851
c597cc3d
SD		 1852 /* Speculation Barriers. */
1853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
1854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
1855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
1856
62b3e311 1857 /* V7 instructions. */
823d2571
TG		 1858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
1859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
1861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
1862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a
AV		 1865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
1866 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
62b3e311 1867
c19d1205 1868 /* ARM V6T2 instructions. */
823d2571
TG		 1869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1870 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1872 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1874 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1876 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
1877
1878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1879 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
1880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1881 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1882
ff8646ee 1883 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 1884 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 1885 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 1886 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1888 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1890 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 1891
f4c65163 1892 /* ARM Security extension instructions. */
823d2571
TG		 1893 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
1894 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 1895
8f06b2d8 1896 /* ARM V6K instructions. */
823d2571
TG		 1897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1898 0xf57ff01f, 0xffffffff, "clrex"},
1899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1900 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1902 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1904 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1906 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1908 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1910 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 1911
7fadb25d
SD		 1912 /* ARMv8.5-A instructions. */
1913 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
1914
8f06b2d8 1915 /* ARM V6K NOP hints. */
823d2571
TG		 1916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1917 0x0320f001, 0x0fffffff, "yield%c"},
1918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1919 0x0320f002, 0x0fffffff, "wfe%c"},
1920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1921 0x0320f003, 0x0fffffff, "wfi%c"},
1922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1923 0x0320f004, 0x0fffffff, "sev%c"},
1924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1925 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 1926
fe56b6ce 1927 /* ARM V6 instructions. */
823d2571
TG		 1928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1929 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
1930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1931 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
1932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1933 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
1934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1935 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
1936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1937 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
1938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1939 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
1940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1941 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
1942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1943 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
1944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1945 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
1946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1947 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
1948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1949 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
1950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1951 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
1952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1953 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
1954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1955 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
1956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1957 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
1958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1959 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
1960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1961 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
1962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1963 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
1964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1965 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
1966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1967 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
1968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1969 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
1970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1971 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
1972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1973 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
1974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1975 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
1976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1977 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
1978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1979 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
1980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1981 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
1982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1983 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
1984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1985 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
1986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1987 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
1988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1989 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
1990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1991 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
1992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1993 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
1994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1995 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
1996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1997 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
1998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1999 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
2000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2001 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
2002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2003 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
2004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2005 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
2006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2007 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
2008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2009 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
2010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2011 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
2012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2013 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
2014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2015 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
2016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2017 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
2018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2019 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
2020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2021 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
2022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2023 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
2024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2025 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
2026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2027 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
2028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2029 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
2030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2031 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
2032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2033 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
2034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2035 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
2036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2037 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
2038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2039 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
2040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2041 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
2042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2043 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
2044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2045 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
2046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2047 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
2048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2049 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
2050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2051 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
2052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2053 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
2054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2055 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
2056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2057 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
2058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2059 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
2060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2061 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
2062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2063 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
2064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2065 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
2066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2067 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
2068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2069 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
2070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2071 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
2072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2073 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
2074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2075 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
2076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2077 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
2078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2079 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2081 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2083 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2085 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
2086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2087 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2089 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2091 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2093 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
2094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2095 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2097 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2099 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2101 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
2102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2103 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2105 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2107 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2109 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
2110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2111 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2113 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2115 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
2116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2117 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
2118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2119 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2121 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2123 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2125 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
2126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2127 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
2128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2129 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
2130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2131 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
2132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2133 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2135 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2137 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2139 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2141 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
2142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2143 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2145 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2147 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
2148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2149 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
2150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2151 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
2152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2153 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
2154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2155 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
2156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2157 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
2158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2159 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
2160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2161 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
2162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2163 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2165 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
2166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2167 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
2168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2169 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
2170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2171 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 2172
8f06b2d8 2173 /* V5J instruction. */
823d2571
TG		 2174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
2175 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 2176
8f06b2d8 2177 /* V5 Instructions. */
823d2571
TG		 2178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2179 0xe1200070, 0xfff000f0,
2180 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
2181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2182 0xfa000000, 0xfe000000, "blx\t%B"},
2183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2184 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
2185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2186 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
2187
2188 /* V5E "El Segundo" Instructions. */
2189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2190 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
2191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2192 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
2193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2194 0xf450f000, 0xfc70f000, "pld\t%a"},
2195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2196 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2198 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2200 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2202 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
2203
2204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2205 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2207 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
2208
2209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2210 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2212 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2214 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2216 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2217
2218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2219 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2221 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2223 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2225 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2226
2227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2228 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2230 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2231
2232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2233 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
2234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2235 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2237 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
2238 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2239 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 2240
8f06b2d8 2241 /* ARM Instructions. */
823d2571
TG		 2242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2243 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2244
2245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2246 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2248 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2250 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2252 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2254 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2256 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2257
2258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2259 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2261 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2263 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2265 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2266
2267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2268 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2270 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2272 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2273 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2274 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2275
2276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2277 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2279 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2281 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2282
2283 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2284 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2285 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2286 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2287 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2288 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2289
2290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2291 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2292 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2293 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2294 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2295 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2296
2297 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2298 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2299 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2300 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2301 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2302 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2303
2304 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2305 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2307 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2309 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2310
2311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2312 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2314 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2315 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2316 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2317
2318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2319 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2321 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2323 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2324
2325 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2326 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2327 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2328 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2329 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2330 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2331
2332 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2333 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2335 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2337 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2338
2339 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2340 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2341 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2342 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2343 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2344 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2345
2346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2347 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 2348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2349 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 2350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2351 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
823d2571
TG		 2352
2353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2354 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2356 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2358 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2359
2360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2361 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2363 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2365 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2366
2367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2368 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2370 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2372 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2373
2374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2375 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2377 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2379 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2381 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2383 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2385 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2387 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2388
2389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2390 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2392 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2394 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2395
2396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2397 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2399 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2401 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2402
2403 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2404 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2406 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2407
2408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2409 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2410
2411 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2412 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2413 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2414 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2415
2416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2417 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2418 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2419 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2421 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2423 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2425 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2427 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2429 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2431 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2433 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2434 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2435 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2437 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2439 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2440 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2441 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2443 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2445 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2447 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2448 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2449 0x092d0000, 0x0fff0000, "push%c\t%m"},
2450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2451 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2453 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2454
2455 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2456 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2457 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2458 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2459 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2460 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2461 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2462 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2463 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2464 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2465 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2466 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2467 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2468 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2469 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2470 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2471 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2472 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2473 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2474 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2475 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2476 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2477 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2478 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2479 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2480 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2481 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2482 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2483 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2484 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2485 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2486 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2488 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2489 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2490 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2492 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2493
2494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2495 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2497 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 2498
2499 /* The rest. */
4ab90a7a
AV		 2500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2501 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 2502 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2503 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2504 {ARM_FEATURE_CORE_LOW (0),
2505 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 2506};
2507
2508/* print_insn_thumb16 recognizes the following format control codes:
2509
2510 %S print Thumb register (bits 3..5 as high number if bit 6 set)
2511 %D print Thumb register (bits 0..2 as high number if bit 7 set)
2512 %<bitfield>I print bitfield as a signed decimal
2513 (top bit of range being the sign bit)
2514 %N print Thumb register mask (with LR)
2515 %O print Thumb register mask (with PC)
2516 %M print Thumb register mask
2517 %b print CZB's 6-bit unsigned branch destination
2518 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 2519 %c print the condition code
2520 %C print the condition code, or "s" if not conditional
2521 %x print warning if conditional an not at end of IT block"
2522 %X print "\t; unpredictable <IT:code>" if conditional
2523 %I print IT instruction suffix and operands
4547cb56 2524 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 2525 %<bitfield>r print bitfield as an ARM register
2526 %<bitfield>d print bitfield as a decimal
2527 %<bitfield>H print (bitfield * 2) as a decimal
2528 %<bitfield>W print (bitfield * 4) as a decimal
2529 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
2530 %<bitfield>B print Thumb branch destination (signed displacement)
2531 %<bitfield>c print bitfield as a condition code
2532 %<bitnum>'c print specified char iff bit is one
2533 %<bitnum>?ab print a if bit is one else print b. */
2534
2535static const struct opcode16 thumb_opcodes[] =
2536{
2537 /* Thumb instructions. */
2538
16a1fa25
TP		 2539 /* ARMv8-M Security Extensions instructions. */
2540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
e207bc53 2541 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
16a1fa25 2542
53c4b28b 2543 /* ARM V8 instructions. */
823d2571
TG		 2544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
2545 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
ddfded2f 2546 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
53c4b28b 2547
8f06b2d8 2548 /* ARM V6K no-argument instructions. */
823d2571
TG		 2549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 2555
2556 /* ARM V6T2 instructions. */
ff8646ee
TP		 2557 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2558 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2559 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2560 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 2561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 2562
2563 /* ARM V6. */
823d2571
TG		 2564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 2575
2576 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 2577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2578 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 2579 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 2580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2581 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 2582 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 2583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2584 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 2585 /* Format 4. */
823d2571
TG		 2586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2591 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2599 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2601 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 2602 /* format 13 */
823d2571
TG		 2603 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 2605 /* format 5 */
823d2571
TG		 2606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
2607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
2608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 2610 /* format 14 */
823d2571
TG		 2611 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
2612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 2613 /* format 2 */
823d2571
TG		 2614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2615 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2617 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2619 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2621 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 2622 /* format 8 */
823d2571
TG		 2623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2624 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2626 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2627 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2628 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2629 /* format 7 */
823d2571
TG		 2630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2631 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2633 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2634 /* format 1 */
823d2571
TG		 2635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2637 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 2640 /* format 3 */
823d2571
TG		 2641 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 2645 /* format 6 */
823d2571
TG		 2646 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2648 0x4800, 0xF800,
2649 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 2650 /* format 9 */
823d2571
TG		 2651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2652 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2654 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2656 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2657 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2658 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 2659 /* format 10 */
823d2571
TG		 2660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2661 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2663 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 2664 /* format 11 */
823d2571
TG		 2665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2666 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2667 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2668 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 2669 /* format 12 */
823d2571
TG		 2670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2671 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2673 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 2674 /* format 15 */
823d2571
TG		 2675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 2677 /* format 17 */
823d2571 2678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 2679 /* format 16 */
823d2571
TG		 2680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
2682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 2683 /* format 18 */
823d2571 2684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 2685
2686 /* The E800 .. FFFF range is unconditionally redirected to the
2687 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2688 are processed via that table. Thus, we can never encounter a
2689 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 2690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
2691 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 2692};
2693
2694/* Thumb32 opcodes use the same table structure as the ARM opcodes.
2695 We adopt the convention that hw1 is the high 16 bits of .value and
2696 .mask, hw2 the low 16 bits.
2697
2698 print_insn_thumb32 recognizes the following format control codes:
2699
2700 %% %
2701
2702 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2703 %M print a modified 12-bit immediate (same location)
2704 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2705 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 2706 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 2707 %S print a possibly-shifted Rm
2708
32a94698 2709 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 2710 %a print the address of a plain load/store
2711 %w print the width and signedness of a core load/store
2712 %m print register mask for ldm/stm
2713
2714 %E print the lsb and width fields of a bfc/bfi instruction
2715 %F print the lsb and width fields of a sbfx/ubfx instruction
e12437dc 2716 %G print a fallback offset for Branch Future instructions
e5d6e09e 2717 %W print an offset for BF instruction
1caf72a5 2718 %Y print an offset for BFL instruction
8f06b2d8
PB		 2719 %b print a conditional branch offset
2720 %B print an unconditional branch offset
2721 %s print the shift field of an SSAT instruction
2722 %R print the rotation field of an SXT instruction
62b3e311
PB		 2723 %U print barrier type.
2724 %P print address for pli instruction.
c22aaad1
PB		 2725 %c print the condition code
2726 %x print warning if conditional an not at end of IT block"
2727 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 2728
2729 %<bitfield>d print bitfield in decimal
f0fba320 2730 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 2731 %<bitfield>W print bitfield*4 in decimal
2732 %<bitfield>r print bitfield as an ARM register
dd5181d5 2733 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
f1c7f421 2734 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
8f06b2d8
PB		 2735 %<bitfield>c print bitfield as a condition code
2736
16980d0b
JB		 2737 %<bitfield>'c print specified char iff bitfield is all ones
2738 %<bitfield>`c print specified char iff bitfield is all zeroes
2739 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 2740
2741 With one exception at the bottom (done because BL and BLX(1) need
2742 to come dead last), this table was machine-sorted first in
2743 decreasing order of number of bits set in the mask, then in
2744 increasing numeric order of mask, then in increasing numeric order
2745 of opcode. This order is not the clearest for a human reader, but
2746 is guaranteed never to catch a special-case bit pattern with a more
2747 general mask, which is important, because this instruction encoding
2748 makes heavy use of special-case bit patterns. */
2749static const struct opcode32 thumb32_opcodes[] =
2750{
4389b29a
AV		 2751 /* Armv8.1-M Mainline instructions. */
2752 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2753 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
f1c7f421
AV		 2754 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2755 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
2756 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2757 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
4389b29a
AV		 2758
2759
16a1fa25
TP		 2760 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
2761 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4ed7ed8d
TP		 2762 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2763 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
2764 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2765 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
16a1fa25
TP		 2766 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2767 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
2768 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2769 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4ed7ed8d 2770
105bde57 2771 /* ARM V8.2 RAS extension instructions. */
4d1464f2 2772 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 2773 0xf3af8010, 0xffffffff, "esb"},
2774
53c4b28b 2775 /* V8 instructions. */
823d2571
TG		 2776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2777 0xf3af8005, 0xffffffff, "sevl%c.w"},
2778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2779 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2781 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2783 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
2784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2785 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
2786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2787 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
2788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2789 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
2790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2791 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
2792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2793 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
2794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2795 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2797 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2799 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
2800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2801 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2803 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2805 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2807 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 2808
dd5181d5 2809 /* CRC32 instructions. */
823d2571 2810 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2811 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
823d2571 2812 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2813 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
823d2571 2814 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2815 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
823d2571 2816 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2817 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
823d2571 2818 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2819 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
823d2571 2820 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2821 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
dd5181d5 2822
c597cc3d
SD		 2823 /* Speculation Barriers. */
2824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
2825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
2826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
2827
62b3e311 2828 /* V7 instructions. */
823d2571
TG		 2829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
2830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
2831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
2832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
2833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
2834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
2835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
2836 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2837 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
2838 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2839 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 2840
90ec0d68 2841 /* Virtualization Extension instructions. */
823d2571 2842 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 2843 /* We skip ERET as that is SUBS pc, lr, #0. */
2844
60e5ef9f 2845 /* MP Extension instructions. */
823d2571 2846 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 2847
f4c65163 2848 /* Security extension instructions. */
823d2571 2849 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 2850
7fadb25d
SD		 2851 /* ARMv8.5-A instructions. */
2852 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
2853
8f06b2d8 2854 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 2855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
2856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
2857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
2860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2861 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
2862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
2863
ff8646ee 2864 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2865 0xf3bf8f2f, 0xffffffff, "clrex%c"},
2866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2867 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
2868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2869 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
2870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2871 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
2872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2873 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
2874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2875 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
2876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2877 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
2878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2879 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
2880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2881 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
2882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2883 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
2884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2885 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
2886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2887 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
2888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2889 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
2890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2891 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 2892 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 2893 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 2894 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2895 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
2896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2897 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
2898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2899 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
2900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2901 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
2902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2903 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
2904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2905 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
2906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2907 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
2908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2909 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
2910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2911 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 2912 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2913 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
2914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2915 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
2916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2917 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
2918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2919 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
2920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2921 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
2922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2923 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
2924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2925 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
2926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2927 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
2928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2929 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
2930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2931 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
2932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2933 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
2934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2935 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
2936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2937 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
2938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2939 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
2940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2941 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
2942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2943 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
2944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2945 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
2946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2947 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
2948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2949 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
2950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2951 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
2952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2953 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
2954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2955 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
2956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2957 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
2958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2959 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
2960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2961 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
2962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2963 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
2964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2965 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
2966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2967 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
2968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2969 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
2970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2971 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
2972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2973 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
2974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2975 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
2976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2977 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
2978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2979 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
2980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2981 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
2982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2983 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
2984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2985 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
2986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2987 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
2988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2989 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
2990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2991 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
2992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2993 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
2994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2995 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
2996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2997 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
2998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2999 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
3000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3001 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
3002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3003 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
3004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3005 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
3006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3007 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
3008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3009 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
3010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3011 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
3012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3013 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3015 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3017 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3019 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 3020 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3021 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
3022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 3023 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 3024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3025 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
3026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3027 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
3028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3029 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3031 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
3032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3033 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
3034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3035 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3037 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3039 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3041 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3043 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3045 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3047 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3049 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
3050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3051 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
3052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3053 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
3054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3055 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
3056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3057 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
3058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3059 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
3060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3061 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
3062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3063 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
3064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3065 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
3066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3067 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
3068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3069 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
3070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3071 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
3072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3073 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3075 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3077 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3079 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3081 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3083 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3085 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3087 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 3088 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3089 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
3090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3091 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
3092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3093 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
3094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3095 0xf810f000, 0xff70f000, "pld%c\t%a"},
3096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3097 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3099 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3101 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3103 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3105 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3107 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3109 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3111 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
3112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3113 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
3114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3115 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
3116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3117 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
3118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3119 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
3120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3121 0xfb100000, 0xfff000c0,
3122 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3124 0xfbc00080, 0xfff000c0,
3125 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
3126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3127 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
3128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3129 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
3130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 3131 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 3132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3133 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
3134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3135 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 3136 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3137 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
3138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3139 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 3140 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3141 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
3142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3143 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
3144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3145 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
3146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3147 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
3148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3149 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
3150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3151 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
3152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3153 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
3154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3155 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
3156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3157 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
3158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3159 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
3160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3161 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 3162 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3163 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
3164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3165 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
3166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3167 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
3168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3169 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
3170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3171 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
3172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3173 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
3174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3175 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
3176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3177 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
3178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3179 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
3180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3181 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
3182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3183 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
3184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3185 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
3186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3187 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
3188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3189 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
3190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3191 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
3192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3193 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
3194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3195 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
3196 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3197 0xe9400000, 0xff500000,
3198 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3200 0xe9500000, 0xff500000,
3201 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3203 0xe8600000, 0xff700000,
3204 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3206 0xe8700000, 0xff700000,
3207 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3209 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
3210 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3211 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 3212
3213 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 3214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3215 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
3216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3217 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
3218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3219 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
3220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3221 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 3222
8f06b2d8 3223 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 3224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3225 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
3226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3227 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 3228
3229 /* Fallback. */
823d2571
TG		 3230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3231 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3232 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 3233};
ff4a8d2b 3234
8f06b2d8
PB		 3235static const char *const arm_conditional[] =
3236{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 3237 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 3238
3239static const char *const arm_fp_const[] =
3240{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3241
3242static const char *const arm_shift[] =
3243{"lsl", "lsr", "asr", "ror"};
3244
3245typedef struct
3246{
3247 const char *name;
3248 const char *description;
3249 const char *reg_names[16];
3250}
3251arm_regname;
3252
3253static const arm_regname regnames[] =
3254{
65b48a81 3255 { "reg-names-raw", N_("Select raw register names"),
8f06b2d8 3256 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
65b48a81 3257 { "reg-names-gcc", N_("Select register names used by GCC"),
8f06b2d8 3258 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 3259 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
8f06b2d8 3260 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65b48a81
PB		 3261 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
3262 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
3263 { "reg-names-apcs", N_("Select register names used in the APCS"),
8f06b2d8 3264 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 3265 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
8f06b2d8 3266 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
65b48a81
PB		 3267 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
3268 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
8f06b2d8
PB		 3269};
3270
3271static const char *const iwmmxt_wwnames[] =
3272{"b", "h", "w", "d"};
3273
3274static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 3275{"b", "bus", "bc", "bss",
3276 "h", "hus", "hc", "hss",
3277 "w", "wus", "wc", "wss",
3278 "d", "dus", "dc", "dss"
8f06b2d8
PB		 3279};
3280
3281static const char *const iwmmxt_regnames[] =
3282{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3283 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3284};
3285
3286static const char *const iwmmxt_cregnames[] =
3287{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3288 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3289};
3290
3291/* Default to GCC register name set. */
3292static unsigned int regname_selected = 1;
3293
65b48a81 3294#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
8f06b2d8
PB		 3295#define arm_regnames regnames[regname_selected].reg_names
3296
3297static bfd_boolean force_thumb = FALSE;
3298
c22aaad1
PB		 3299/* Current IT instruction state. This contains the same state as the IT
3300 bits in the CPSR. */
3301static unsigned int ifthen_state;
3302/* IT state for the next instruction. */
3303static unsigned int ifthen_next_state;
3304/* The address of the insn for which the IT state is valid. */
3305static bfd_vma ifthen_address;
3306#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 3307/* Indicates that the current Conditional state is unconditional or outside
3308 an IT block. */
3309#define COND_UNCOND 16
c22aaad1 3310
8f06b2d8
PB		 3311\f
3312/* Functions. */
8f06b2d8 3313
16980d0b
JB		 3314/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3315 Returns pointer to following character of the format string and
3316 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 3317 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 3318
3319static const char *
fe56b6ce
NC		 3320arm_decode_bitfield (const char *ptr,
3321 unsigned long insn,
3322 unsigned long *valuep,
3323 int *widthp)
16980d0b
JB		 3324{
3325 unsigned long value = 0;
3326 int width = 0;
43e65147
L		 3327
3328 do
16980d0b
JB		 3329 {
3330 int start, end;
3331 int bits;
3332
3333 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3334 start = start * 10 + *ptr - '0';
3335 if (*ptr == '-')
3336 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3337 end = end * 10 + *ptr - '0';
3338 else
3339 end = start;
3340 bits = end - start;
3341 if (bits < 0)
3342 abort ();
3343 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3344 width += bits + 1;
3345 }
3346 while (*ptr++ == ',');
3347 *valuep = value;
3348 if (widthp)
3349 *widthp = width;
3350 return ptr - 1;
3351}
3352
8f06b2d8 3353static void
37b37b2d 3354arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 3355 bfd_boolean print_shift)
8f06b2d8
PB		 3356{
3357 func (stream, "%s", arm_regnames[given & 0xf]);
3358
3359 if ((given & 0xff0) != 0)
3360 {
3361 if ((given & 0x10) == 0)
3362 {
3363 int amount = (given & 0xf80) >> 7;
3364 int shift = (given & 0x60) >> 5;
3365
3366 if (amount == 0)
3367 {
3368 if (shift == 3)
3369 {
3370 func (stream, ", rrx");
3371 return;
3372 }
3373
3374 amount = 32;
3375 }
3376
37b37b2d
RE		 3377 if (print_shift)
3378 func (stream, ", %s #%d", arm_shift[shift], amount);
3379 else
3380 func (stream, ", #%d", amount);
8f06b2d8 3381 }
74bdfecf 3382 else if ((given & 0x80) == 0x80)
aefd8a40 3383 func (stream, "\t; <illegal shifter operand>");
37b37b2d 3384 else if (print_shift)
8f06b2d8
PB		 3385 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3386 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 3387 else
3388 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 3389 }
3390}
3391
c1e26897
NC		 3392#define W_BIT 21
3393#define I_BIT 22
3394#define U_BIT 23
3395#define P_BIT 24
3396
3397#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
3398#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
3399#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
3400#define PRE_BIT_SET (given & (1 << P_BIT))
3401
8f06b2d8
PB		 3402/* Print one coprocessor instruction on INFO->STREAM.
3403 Return TRUE if the instuction matched, FALSE if this is not a
3404 recognised coprocessor instruction. */
3405
3406static bfd_boolean
fe56b6ce
NC		 3407print_insn_coprocessor (bfd_vma pc,
3408 struct disassemble_info *info,
3409 long given,
8f06b2d8
PB		 3410 bfd_boolean thumb)
3411{
3412 const struct opcode32 *insn;
3413 void *stream = info->stream;
3414 fprintf_ftype func = info->fprintf_func;
3415 unsigned long mask;
2edcd244 3416 unsigned long value = 0;
c22aaad1 3417 int cond;
8afc7bea 3418 int cp_num;
823d2571
TG		 3419 struct arm_private_data *private_data = info->private_data;
3420 arm_feature_set allowed_arches = ARM_ARCH_NONE;
3421
5b616bef 3422 allowed_arches = private_data->features;
8f06b2d8
PB		 3423
3424 for (insn = coprocessor_opcodes; insn->assembler; insn++)
3425 {
ff4a8d2b
NC		 3426 unsigned long u_reg = 16;
3427 bfd_boolean is_unpredictable = FALSE;
05413229 3428 signed long value_in_comment = 0;
0313a2b8
NC		 3429 const char *c;
3430
823d2571 3431 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 3432 switch (insn->value)
3433 {
3434 case SENTINEL_IWMMXT_START:
3435 if (info->mach != bfd_mach_arm_XScale
3436 && info->mach != bfd_mach_arm_iWMMXt
3437 && info->mach != bfd_mach_arm_iWMMXt2)
3438 do
3439 insn++;
823d2571
TG		 3440 while ((! ARM_FEATURE_ZERO (insn->arch))
3441 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 3442 continue;
3443
3444 case SENTINEL_IWMMXT_END:
3445 continue;
3446
3447 case SENTINEL_GENERIC_START:
5b616bef 3448 allowed_arches = private_data->features;
05413229
NC		 3449 continue;
3450
3451 default:
3452 abort ();
3453 }
8f06b2d8
PB		 3454
3455 mask = insn->mask;
3456 value = insn->value;
8afc7bea
RL		 3457 cp_num = (given >> 8) & 0xf;
3458
8f06b2d8
PB		 3459 if (thumb)
3460 {
3461 /* The high 4 bits are 0xe for Arm conditional instructions, and
3462 0xe for arm unconditional instructions. The rest of the
3463 encoding is the same. */
3464 mask |= 0xf0000000;
3465 value |= 0xe0000000;
c22aaad1
PB		 3466 if (ifthen_state)
3467 cond = IFTHEN_COND;
3468 else
e2efe87d 3469 cond = COND_UNCOND;
8f06b2d8
PB		 3470 }
3471 else
3472 {
3473 /* Only match unconditional instuctions against unconditional
3474 patterns. */
3475 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 3476 {
3477 mask |= 0xf0000000;
e2efe87d 3478 cond = COND_UNCOND;
c22aaad1
PB		 3479 }
3480 else
3481 {
3482 cond = (given >> 28) & 0xf;
3483 if (cond == 0xe)
e2efe87d 3484 cond = COND_UNCOND;
c22aaad1 3485 }
8f06b2d8 3486 }
823d2571 3487
0313a2b8
NC		 3488 if ((given & mask) != value)
3489 continue;
8f06b2d8 3490
823d2571 3491 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 3492 continue;
3493
8afc7bea
RL		 3494 if (insn->value == 0xfe000010 /* mcr2 */
3495 || insn->value == 0xfe100010 /* mrc2 */
3496 || insn->value == 0xfc100000 /* ldc2 */
3497 || insn->value == 0xfc000000) /* stc2 */
3498 {
b0c11777 3499 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea
RL		 3500 is_unpredictable = TRUE;
3501 }
3502 else if (insn->value == 0x0e000000 /* cdp */
3503 || insn->value == 0xfe000000 /* cdp2 */
3504 || insn->value == 0x0e000010 /* mcr */
3505 || insn->value == 0x0e100010 /* mrc */
3506 || insn->value == 0x0c100000 /* ldc */
3507 || insn->value == 0x0c000000) /* stc */
3508 {
3509 /* Floating-point instructions. */
b0c11777 3510 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea
RL		 3511 continue;
3512 }
3513
0313a2b8
NC		 3514 for (c = insn->assembler; *c; c++)
3515 {
3516 if (*c == '%')
8f06b2d8 3517 {
0313a2b8 3518 switch (*++c)
8f06b2d8 3519 {
0313a2b8
NC		 3520 case '%':
3521 func (stream, "%%");
3522 break;
3523
3524 case 'A':
05413229 3525 {
79862e45 3526 int rn = (given >> 16) & 0xf;
b0c11777 3527 bfd_vma offset = given & 0xff;
0313a2b8 3528
05413229 3529 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 3530
79862e45
DJ		 3531 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
3532 {
3533 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 3534 if (cp_num == 9)
3535 /* vldr.16/vstr.16 will shift the address
3536 left by 1 bit only. */
3537 offset = offset * 2;
3538 else
3539 offset = offset * 4;
3540
79862e45
DJ		 3541 if (NEGATIVE_BIT_SET)
3542 offset = - offset;
3543 if (rn != 15)
3544 value_in_comment = offset;
3545 }
3546
c1e26897 3547 if (PRE_BIT_SET)
05413229
NC		 3548 {
3549 if (offset)
fe56b6ce 3550 func (stream, ", #%d]%s",
d908c8af 3551 (int) offset,
c1e26897 3552 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 3553 else if (NEGATIVE_BIT_SET)
3554 func (stream, ", #-0]");
05413229
NC		 3555 else
3556 func (stream, "]");
3557 }
3558 else
3559 {
0313a2b8 3560 func (stream, "]");
8f06b2d8 3561
c1e26897 3562 if (WRITEBACK_BIT_SET)
05413229
NC		 3563 {
3564 if (offset)
d908c8af 3565 func (stream, ", #%d", (int) offset);
26d97720
NS		 3566 else if (NEGATIVE_BIT_SET)
3567 func (stream, ", #-0");
05413229
NC		 3568 }
3569 else
fe56b6ce 3570 {
26d97720
NS		 3571 func (stream, ", {%s%d}",
3572 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 3573 (int) offset);
fe56b6ce
NC		 3574 value_in_comment = offset;
3575 }
05413229 3576 }
79862e45
DJ		 3577 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
3578 {
3579 func (stream, "\t; ");
6844b2c2
MGD		 3580 /* For unaligned PCs, apply off-by-alignment
3581 correction. */
43e65147 3582 info->print_address_func (offset + pc
6844b2c2
MGD		 3583 + info->bytes_per_chunk * 2
3584 - (pc & 3),
dffaa15c 3585 info);
79862e45 3586 }
05413229 3587 }
0313a2b8 3588 break;
8f06b2d8 3589
0313a2b8
NC		 3590 case 'B':
3591 {
3592 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
3593 int offset = (given >> 1) & 0x3f;
3594
3595 if (offset == 1)
3596 func (stream, "{d%d}", regno);
3597 else if (regno + offset > 32)
3598 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
3599 else
3600 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
3601 }
3602 break;
8f06b2d8 3603
e2efe87d
MGD		 3604 case 'u':
3605 if (cond != COND_UNCOND)
3606 is_unpredictable = TRUE;
3607
3608 /* Fall through. */
0313a2b8 3609 case 'c':
b0c11777
RL		 3610 if (cond != COND_UNCOND && cp_num == 9)
3611 is_unpredictable = TRUE;
3612
0313a2b8
NC		 3613 func (stream, "%s", arm_conditional[cond]);
3614 break;
8f06b2d8 3615
0313a2b8
NC		 3616 case 'I':
3617 /* Print a Cirrus/DSP shift immediate. */
3618 /* Immediates are 7bit signed ints with bits 0..3 in
3619 bits 0..3 of opcode and bits 4..6 in bits 5..7
3620 of opcode. */
3621 {
3622 int imm;
8f06b2d8 3623
0313a2b8 3624 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 3625
0313a2b8
NC		 3626 /* Is ``imm'' a negative number? */
3627 if (imm & 0x40)
24b4cf66 3628 imm -= 0x80;
8f06b2d8 3629
0313a2b8
NC		 3630 func (stream, "%d", imm);
3631 }
3632
3633 break;
8f06b2d8 3634
0313a2b8
NC		 3635 case 'F':
3636 switch (given & 0x00408000)
3637 {
3638 case 0:
3639 func (stream, "4");
3640 break;
3641 case 0x8000:
3642 func (stream, "1");
3643 break;
3644 case 0x00400000:
3645 func (stream, "2");
8f06b2d8 3646 break;
0313a2b8
NC		 3647 default:
3648 func (stream, "3");
3649 }
3650 break;
8f06b2d8 3651
0313a2b8
NC		 3652 case 'P':
3653 switch (given & 0x00080080)
3654 {
3655 case 0:
3656 func (stream, "s");
3657 break;
3658 case 0x80:
3659 func (stream, "d");
3660 break;
3661 case 0x00080000:
3662 func (stream, "e");
3663 break;
3664 default:
3665 func (stream, _("<illegal precision>"));
8f06b2d8 3666 break;
0313a2b8
NC		 3667 }
3668 break;
8f06b2d8 3669
0313a2b8
NC		 3670 case 'Q':
3671 switch (given & 0x00408000)
3672 {
3673 case 0:
3674 func (stream, "s");
8f06b2d8 3675 break;
0313a2b8
NC		 3676 case 0x8000:
3677 func (stream, "d");
8f06b2d8 3678 break;
0313a2b8
NC		 3679 case 0x00400000:
3680 func (stream, "e");
3681 break;
3682 default:
3683 func (stream, "p");
8f06b2d8 3684 break;
0313a2b8
NC		 3685 }
3686 break;
8f06b2d8 3687
0313a2b8
NC		 3688 case 'R':
3689 switch (given & 0x60)
3690 {
3691 case 0:
3692 break;
3693 case 0x20:
3694 func (stream, "p");
3695 break;
3696 case 0x40:
3697 func (stream, "m");
3698 break;
3699 default:
3700 func (stream, "z");
3701 break;
3702 }
3703 break;
16980d0b 3704
0313a2b8
NC		 3705 case '0': case '1': case '2': case '3': case '4':
3706 case '5': case '6': case '7': case '8': case '9':
3707 {
3708 int width;
8f06b2d8 3709
0313a2b8 3710 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 3711
0313a2b8
NC		 3712 switch (*c)
3713 {
ff4a8d2b
NC		 3714 case 'R':
3715 if (value == 15)
3716 is_unpredictable = TRUE;
3717 /* Fall through. */
0313a2b8 3718 case 'r':
ff4a8d2b
NC		 3719 if (c[1] == 'u')
3720 {
3721 /* Eat the 'u' character. */
3722 ++ c;
3723
3724 if (u_reg == value)
3725 is_unpredictable = TRUE;
3726 u_reg = value;
3727 }
0313a2b8
NC		 3728 func (stream, "%s", arm_regnames[value]);
3729 break;
c28eeff2
SN		 3730 case 'V':
3731 if (given & (1 << 6))
3732 goto Q;
3733 /* FALLTHROUGH */
0313a2b8
NC		 3734 case 'D':
3735 func (stream, "d%ld", value);
3736 break;
3737 case 'Q':
c28eeff2 3738 Q:
0313a2b8
NC		 3739 if (value & 1)
3740 func (stream, "<illegal reg q%ld.5>", value >> 1);
3741 else
3742 func (stream, "q%ld", value >> 1);
3743 break;
3744 case 'd':
3745 func (stream, "%ld", value);
05413229 3746 value_in_comment = value;
0313a2b8 3747 break;
6f1c2142
AM		 3748 case 'E':
3749 {
3750 /* Converts immediate 8 bit back to float value. */
3751 unsigned floatVal = (value & 0x80) << 24
3752 | (value & 0x3F) << 19
3753 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
3754
3755 /* Quarter float have a maximum value of 31.0.
3756 Get floating point value multiplied by 1e7.
3757 The maximum value stays in limit of a 32-bit int. */
3758 unsigned decVal =
3759 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
3760 (16 + (value & 0xF));
3761
3762 if (!(decVal % 1000000))
3763 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
3764 floatVal, value & 0x80 ? '-' : ' ',
3765 decVal / 10000000,
3766 decVal % 10000000 / 1000000);
3767 else if (!(decVal % 10000))
3768 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
3769 floatVal, value & 0x80 ? '-' : ' ',
3770 decVal / 10000000,
3771 decVal % 10000000 / 10000);
3772 else
3773 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
3774 floatVal, value & 0x80 ? '-' : ' ',
3775 decVal / 10000000, decVal % 10000000);
3776 break;
3777 }
0313a2b8
NC		 3778 case 'k':
3779 {
3780 int from = (given & (1 << 7)) ? 32 : 16;
3781 func (stream, "%ld", from - value);
3782 }
3783 break;
8f06b2d8 3784
0313a2b8
NC		 3785 case 'f':
3786 if (value > 7)
3787 func (stream, "#%s", arm_fp_const[value & 7]);
3788 else
3789 func (stream, "f%ld", value);
3790 break;
4146fd53 3791
0313a2b8
NC		 3792 case 'w':
3793 if (width == 2)
3794 func (stream, "%s", iwmmxt_wwnames[value]);
3795 else
3796 func (stream, "%s", iwmmxt_wwssnames[value]);
3797 break;
4146fd53 3798
0313a2b8
NC		 3799 case 'g':
3800 func (stream, "%s", iwmmxt_regnames[value]);
3801 break;
3802 case 'G':
3803 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 3804 break;
8f06b2d8 3805
0313a2b8 3806 case 'x':
d1aaab3c 3807 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 3808 break;
8f06b2d8 3809
33399f07
MGD		 3810 case 'c':
3811 switch (value)
3812 {
3813 case 0:
3814 func (stream, "eq");
3815 break;
3816
3817 case 1:
3818 func (stream, "vs");
3819 break;
3820
3821 case 2:
3822 func (stream, "ge");
3823 break;
3824
3825 case 3:
3826 func (stream, "gt");
3827 break;
3828
3829 default:
3830 func (stream, "??");
3831 break;
3832 }
3833 break;
3834
0313a2b8
NC		 3835 case '`':
3836 c++;
3837 if (value == 0)
3838 func (stream, "%c", *c);
3839 break;
3840 case '\'':
3841 c++;
3842 if (value == ((1ul << width) - 1))
3843 func (stream, "%c", *c);
3844 break;
3845 case '?':
fe56b6ce 3846 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 3847 c += 1 << width;
3848 break;
3849 default:
3850 abort ();
3851 }
dffaa15c
AM		 3852 }
3853 break;
0313a2b8 3854
dffaa15c
AM		 3855 case 'y':
3856 case 'z':
3857 {
3858 int single = *c++ == 'y';
3859 int regno;
8f06b2d8 3860
dffaa15c
AM		 3861 switch (*c)
3862 {
3863 case '4': /* Sm pair */
3864 case '0': /* Sm, Dm */
3865 regno = given & 0x0000000f;
3866 if (single)
3867 {
3868 regno <<= 1;
3869 regno += (given >> 5) & 1;
3870 }
3871 else
3872 regno += ((given >> 5) & 1) << 4;
3873 break;
8f06b2d8 3874
dffaa15c
AM		 3875 case '1': /* Sd, Dd */
3876 regno = (given >> 12) & 0x0000000f;
3877 if (single)
3878 {
3879 regno <<= 1;
3880 regno += (given >> 22) & 1;
3881 }
3882 else
3883 regno += ((given >> 22) & 1) << 4;
3884 break;
7df76b80 3885
dffaa15c
AM		 3886 case '2': /* Sn, Dn */
3887 regno = (given >> 16) & 0x0000000f;
3888 if (single)
3889 {
3890 regno <<= 1;
3891 regno += (given >> 7) & 1;
3892 }
3893 else
3894 regno += ((given >> 7) & 1) << 4;
3895 break;
a7f8487e 3896
dffaa15c
AM		 3897 case '3': /* List */
3898 func (stream, "{");
3899 regno = (given >> 12) & 0x0000000f;
3900 if (single)
3901 {
3902 regno <<= 1;
3903 regno += (given >> 22) & 1;
3904 }
3905 else
3906 regno += ((given >> 22) & 1) << 4;
3907 break;
a7f8487e 3908
dffaa15c
AM		 3909 default:
3910 abort ();
3911 }
0313a2b8 3912
dffaa15c 3913 func (stream, "%c%d", single ? 's' : 'd', regno);
a7f8487e 3914
dffaa15c
AM		 3915 if (*c == '3')
3916 {
3917 int count = given & 0xff;
b34976b6 3918
dffaa15c
AM		 3919 if (single == 0)
3920 count >>= 1;
0313a2b8 3921
dffaa15c
AM		 3922 if (--count)
3923 {
3924 func (stream, "-%c%d",
3925 single ? 's' : 'd',
3926 regno + count);
3927 }
0313a2b8 3928
dffaa15c 3929 func (stream, "}");
0313a2b8 3930 }
dffaa15c
AM		 3931 else if (*c == '4')
3932 func (stream, ", %c%d", single ? 's' : 'd',
3933 regno + 1);
3934 }
3935 break;
b34976b6 3936
dffaa15c
AM		 3937 case 'L':
3938 switch (given & 0x00400100)
0313a2b8 3939 {
dffaa15c
AM		 3940 case 0x00000000: func (stream, "b"); break;
3941 case 0x00400000: func (stream, "h"); break;
3942 case 0x00000100: func (stream, "w"); break;
3943 case 0x00400100: func (stream, "d"); break;
3944 default:
3945 break;
0313a2b8 3946 }
dffaa15c 3947 break;
2d447fca 3948
dffaa15c
AM		 3949 case 'Z':
3950 {
3951 /* given (20, 23) | given (0, 3) */
3952 value = ((given >> 16) & 0xf0) | (given & 0xf);
3953 func (stream, "%d", (int) value);
3954 }
3955 break;
0313a2b8 3956
dffaa15c
AM		 3957 case 'l':
3958 /* This is like the 'A' operator, except that if
3959 the width field "M" is zero, then the offset is
3960 *not* multiplied by four. */
3961 {
3962 int offset = given & 0xff;
3963 int multiplier = (given & 0x00000100) ? 4 : 1;
0313a2b8 3964
dffaa15c 3965 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
05413229 3966
dffaa15c
AM		 3967 if (multiplier > 1)
3968 {
3969 value_in_comment = offset * multiplier;
3970 if (NEGATIVE_BIT_SET)
3971 value_in_comment = - value_in_comment;
3972 }
0313a2b8 3973
dffaa15c
AM		 3974 if (offset)
3975 {
3976 if (PRE_BIT_SET)
3977 func (stream, ", #%s%d]%s",
3978 NEGATIVE_BIT_SET ? "-" : "",
3979 offset * multiplier,
3980 WRITEBACK_BIT_SET ? "!" : "");
3981 else
3982 func (stream, "], #%s%d",
3983 NEGATIVE_BIT_SET ? "-" : "",
3984 offset * multiplier);
3985 }
3986 else
3987 func (stream, "]");
3988 }
3989 break;
2d447fca 3990
dffaa15c
AM		 3991 case 'r':
3992 {
3993 int imm4 = (given >> 4) & 0xf;
3994 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
3995 int ubit = ! NEGATIVE_BIT_SET;
3996 const char *rm = arm_regnames [given & 0xf];
3997 const char *rn = arm_regnames [(given >> 16) & 0xf];
0313a2b8 3998
dffaa15c
AM		 3999 switch (puw_bits)
4000 {
4001 case 1:
4002 case 3:
4003 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
4004 if (imm4)
4005 func (stream, ", lsl #%d", imm4);
4006 break;
0313a2b8 4007
dffaa15c
AM		 4008 case 4:
4009 case 5:
4010 case 6:
4011 case 7:
4012 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
4013 if (imm4 > 0)
4014 func (stream, ", lsl #%d", imm4);
4015 func (stream, "]");
4016 if (puw_bits == 5 || puw_bits == 7)
4017 func (stream, "!");
4018 break;
2d447fca 4019
dffaa15c
AM		 4020 default:
4021 func (stream, "INVALID");
4022 }
4023 }
4024 break;
0313a2b8 4025
dffaa15c
AM		 4026 case 'i':
4027 {
4028 long imm5;
4029 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
4030 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
0313a2b8 4031 }
dffaa15c
AM		 4032 break;
4033
4034 default:
4035 abort ();
252b5132 4036 }
252b5132 4037 }
0313a2b8
NC		 4038 else
4039 func (stream, "%c", *c);
252b5132 4040 }
05413229
NC		 4041
4042 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 4043 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 4044
ff4a8d2b
NC		 4045 if (is_unpredictable)
4046 func (stream, UNPREDICTABLE_INSTRUCTION);
4047
0313a2b8 4048 return TRUE;
252b5132 4049 }
8f06b2d8 4050 return FALSE;
252b5132
RH		 4051}
4052
05413229
NC		 4053/* Decodes and prints ARM addressing modes. Returns the offset
4054 used in the address, if any, if it is worthwhile printing the
4055 offset as a hexadecimal value in a comment at the end of the
4056 line of disassembly. */
4057
4058static signed long
62b3e311
PB		 4059print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
4060{
4061 void *stream = info->stream;
4062 fprintf_ftype func = info->fprintf_func;
f8b960bc 4063 bfd_vma offset = 0;
62b3e311
PB		 4064
4065 if (((given & 0x000f0000) == 0x000f0000)
4066 && ((given & 0x02000000) == 0))
4067 {
05413229 4068 offset = given & 0xfff;
62b3e311
PB		 4069
4070 func (stream, "[pc");
4071
c1e26897 4072 if (PRE_BIT_SET)
62b3e311 4073 {
26d97720
NS		 4074 /* Pre-indexed. Elide offset of positive zero when
4075 non-writeback. */
4076 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 4077 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 4078
4079 if (NEGATIVE_BIT_SET)
4080 offset = -offset;
62b3e311
PB		 4081
4082 offset += pc + 8;
4083
4084 /* Cope with the possibility of write-back
4085 being used. Probably a very dangerous thing
4086 for the programmer to do, but who are we to
4087 argue ? */
26d97720 4088 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 4089 }
c1e26897 4090 else /* Post indexed. */
62b3e311 4091 {
d908c8af 4092 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 4093
c1e26897 4094 /* Ie ignore the offset. */
62b3e311
PB		 4095 offset = pc + 8;
4096 }
4097
4098 func (stream, "\t; ");
4099 info->print_address_func (offset, info);
05413229 4100 offset = 0;
62b3e311
PB		 4101 }
4102 else
4103 {
4104 func (stream, "[%s",
4105 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 4106
4107 if (PRE_BIT_SET)
62b3e311
PB		 4108 {
4109 if ((given & 0x02000000) == 0)
4110 {
26d97720 4111 /* Elide offset of positive zero when non-writeback. */
05413229 4112 offset = given & 0xfff;
26d97720 4113 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 4114 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 4115 }
4116 else
4117 {
26d97720 4118 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 4119 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 4120 }
4121
4122 func (stream, "]%s",
c1e26897 4123 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 4124 }
4125 else
4126 {
4127 if ((given & 0x02000000) == 0)
4128 {
26d97720 4129 /* Always show offset. */
05413229 4130 offset = given & 0xfff;
26d97720 4131 func (stream, "], #%s%d",
d908c8af 4132 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 4133 }
4134 else
4135 {
4136 func (stream, "], %s",
c1e26897 4137 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 4138 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 4139 }
4140 }
84919466
MR		 4141 if (NEGATIVE_BIT_SET)
4142 offset = -offset;
62b3e311 4143 }
05413229
NC		 4144
4145 return (signed long) offset;
62b3e311
PB		 4146}
4147
16980d0b
JB		 4148/* Print one neon instruction on INFO->STREAM.
4149 Return TRUE if the instuction matched, FALSE if this is not a
4150 recognised neon instruction. */
4151
4152static bfd_boolean
4153print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
4154{
4155 const struct opcode32 *insn;
4156 void *stream = info->stream;
4157 fprintf_ftype func = info->fprintf_func;
4158
4159 if (thumb)
4160 {
4161 if ((given & 0xef000000) == 0xef000000)
4162 {
0313a2b8 4163 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 4164 unsigned long bit28 = given & (1 << 28);
4165
4166 given &= 0x00ffffff;
4167 if (bit28)
4168 given |= 0xf3000000;
4169 else
4170 given |= 0xf2000000;
4171 }
4172 else if ((given & 0xff000000) == 0xf9000000)
4173 given ^= 0xf9000000 ^ 0xf4000000;
4174 else
4175 return FALSE;
4176 }
43e65147 4177
16980d0b
JB		 4178 for (insn = neon_opcodes; insn->assembler; insn++)
4179 {
4180 if ((given & insn->mask) == insn->value)
4181 {
05413229 4182 signed long value_in_comment = 0;
e2efe87d 4183 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 4184 const char *c;
4185
4186 for (c = insn->assembler; *c; c++)
4187 {
4188 if (*c == '%')
4189 {
4190 switch (*++c)
4191 {
4192 case '%':
4193 func (stream, "%%");
4194 break;
4195
e2efe87d
MGD		 4196 case 'u':
4197 if (thumb && ifthen_state)
4198 is_unpredictable = TRUE;
4199
4200 /* Fall through. */
c22aaad1
PB		 4201 case 'c':
4202 if (thumb && ifthen_state)
4203 func (stream, "%s", arm_conditional[IFTHEN_COND]);
4204 break;
4205
16980d0b
JB		 4206 case 'A':
4207 {
43e65147 4208 static const unsigned char enc[16] =
16980d0b
JB		 4209 {
4210 0x4, 0x14, /* st4 0,1 */
4211 0x4, /* st1 2 */
4212 0x4, /* st2 3 */
4213 0x3, /* st3 4 */
4214 0x13, /* st3 5 */
4215 0x3, /* st1 6 */
4216 0x1, /* st1 7 */
4217 0x2, /* st2 8 */
4218 0x12, /* st2 9 */
4219 0x2, /* st1 10 */
4220 0, 0, 0, 0, 0
4221 };
4222 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4223 int rn = ((given >> 16) & 0xf);
4224 int rm = ((given >> 0) & 0xf);
4225 int align = ((given >> 4) & 0x3);
4226 int type = ((given >> 8) & 0xf);
4227 int n = enc[type] & 0xf;
4228 int stride = (enc[type] >> 4) + 1;
4229 int ix;
43e65147 4230
16980d0b
JB		 4231 func (stream, "{");
4232 if (stride > 1)
4233 for (ix = 0; ix != n; ix++)
4234 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
4235 else if (n == 1)
4236 func (stream, "d%d", rd);
4237 else
4238 func (stream, "d%d-d%d", rd, rd + n - 1);
4239 func (stream, "}, [%s", arm_regnames[rn]);
4240 if (align)
8e560766 4241 func (stream, " :%d", 32 << align);
16980d0b
JB		 4242 func (stream, "]");
4243 if (rm == 0xd)
4244 func (stream, "!");
4245 else if (rm != 0xf)
4246 func (stream, ", %s", arm_regnames[rm]);
4247 }
4248 break;
43e65147 4249
16980d0b
JB		 4250 case 'B':
4251 {
4252 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4253 int rn = ((given >> 16) & 0xf);
4254 int rm = ((given >> 0) & 0xf);
4255 int idx_align = ((given >> 4) & 0xf);
4256 int align = 0;
4257 int size = ((given >> 10) & 0x3);
4258 int idx = idx_align >> (size + 1);
4259 int length = ((given >> 8) & 3) + 1;
4260 int stride = 1;
4261 int i;
4262
4263 if (length > 1 && size > 0)
4264 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 4265
16980d0b
JB		 4266 switch (length)
4267 {
4268 case 1:
4269 {
4270 int amask = (1 << size) - 1;
4271 if ((idx_align & (1 << size)) != 0)
4272 return FALSE;
4273 if (size > 0)
4274 {
4275 if ((idx_align & amask) == amask)
4276 align = 8 << size;
4277 else if ((idx_align & amask) != 0)
4278 return FALSE;
4279 }
4280 }
4281 break;
43e65147 4282
16980d0b
JB		 4283 case 2:
4284 if (size == 2 && (idx_align & 2) != 0)
4285 return FALSE;
4286 align = (idx_align & 1) ? 16 << size : 0;
4287 break;
43e65147 4288
16980d0b
JB		 4289 case 3:
4290 if ((size == 2 && (idx_align & 3) != 0)
4291 || (idx_align & 1) != 0)
4292 return FALSE;
4293 break;
43e65147 4294
16980d0b
JB		 4295 case 4:
4296 if (size == 2)
4297 {
4298 if ((idx_align & 3) == 3)
4299 return FALSE;
4300 align = (idx_align & 3) * 64;
4301 }
4302 else
4303 align = (idx_align & 1) ? 32 << size : 0;
4304 break;
43e65147 4305
16980d0b
JB		 4306 default:
4307 abort ();
4308 }
43e65147 4309
16980d0b
JB		 4310 func (stream, "{");
4311 for (i = 0; i < length; i++)
4312 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
4313 rd + i * stride, idx);
4314 func (stream, "}, [%s", arm_regnames[rn]);
4315 if (align)
8e560766 4316 func (stream, " :%d", align);
16980d0b
JB		 4317 func (stream, "]");
4318 if (rm == 0xd)
4319 func (stream, "!");
4320 else if (rm != 0xf)
4321 func (stream, ", %s", arm_regnames[rm]);
4322 }
4323 break;
43e65147 4324
16980d0b
JB		 4325 case 'C':
4326 {
4327 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4328 int rn = ((given >> 16) & 0xf);
4329 int rm = ((given >> 0) & 0xf);
4330 int align = ((given >> 4) & 0x1);
4331 int size = ((given >> 6) & 0x3);
4332 int type = ((given >> 8) & 0x3);
4333 int n = type + 1;
4334 int stride = ((given >> 5) & 0x1);
4335 int ix;
43e65147 4336
16980d0b
JB		 4337 if (stride && (n == 1))
4338 n++;
4339 else
4340 stride++;
43e65147 4341
16980d0b
JB		 4342 func (stream, "{");
4343 if (stride > 1)
4344 for (ix = 0; ix != n; ix++)
4345 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
4346 else if (n == 1)
4347 func (stream, "d%d[]", rd);
4348 else
4349 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
4350 func (stream, "}, [%s", arm_regnames[rn]);
4351 if (align)
4352 {
91d6fa6a 4353 align = (8 * (type + 1)) << size;
16980d0b
JB		 4354 if (type == 3)
4355 align = (size > 1) ? align >> 1 : align;
4356 if (type == 2 || (type == 0 && !size))
8e560766 4357 func (stream, " :<bad align %d>", align);
16980d0b 4358 else
8e560766 4359 func (stream, " :%d", align);
16980d0b
JB		 4360 }
4361 func (stream, "]");
4362 if (rm == 0xd)
4363 func (stream, "!");
4364 else if (rm != 0xf)
4365 func (stream, ", %s", arm_regnames[rm]);
4366 }
4367 break;
43e65147 4368
16980d0b
JB		 4369 case 'D':
4370 {
4371 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
4372 int size = (given >> 20) & 3;
4373 int reg = raw_reg & ((4 << size) - 1);
4374 int ix = raw_reg >> size >> 2;
43e65147 4375
16980d0b
JB		 4376 func (stream, "d%d[%d]", reg, ix);
4377 }
4378 break;
43e65147 4379
16980d0b 4380 case 'E':
fe56b6ce 4381 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 4382 {
4383 int bits = 0;
4384 int cmode = (given >> 8) & 0xf;
4385 int op = (given >> 5) & 0x1;
4386 unsigned long value = 0, hival = 0;
4387 unsigned shift;
4388 int size = 0;
0dbde4cf 4389 int isfloat = 0;
43e65147 4390
16980d0b
JB		 4391 bits |= ((given >> 24) & 1) << 7;
4392 bits |= ((given >> 16) & 7) << 4;
4393 bits |= ((given >> 0) & 15) << 0;
43e65147 4394
16980d0b
JB		 4395 if (cmode < 8)
4396 {
4397 shift = (cmode >> 1) & 3;
fe56b6ce 4398 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4399 size = 32;
4400 }
4401 else if (cmode < 12)
4402 {
4403 shift = (cmode >> 1) & 1;
fe56b6ce 4404 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4405 size = 16;
4406 }
4407 else if (cmode < 14)
4408 {
4409 shift = (cmode & 1) + 1;
fe56b6ce 4410 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4411 value |= (1ul << (8 * shift)) - 1;
4412 size = 32;
4413 }
4414 else if (cmode == 14)
4415 {
4416 if (op)
4417 {
fe56b6ce 4418 /* Bit replication into bytes. */
16980d0b
JB		 4419 int ix;
4420 unsigned long mask;
43e65147 4421
16980d0b
JB		 4422 value = 0;
4423 hival = 0;
4424 for (ix = 7; ix >= 0; ix--)
4425 {
4426 mask = ((bits >> ix) & 1) ? 0xff : 0;
4427 if (ix <= 3)
4428 value = (value << 8) | mask;
4429 else
4430 hival = (hival << 8) | mask;
4431 }
4432 size = 64;
4433 }
4434 else
4435 {
fe56b6ce
NC		 4436 /* Byte replication. */
4437 value = (unsigned long) bits;
16980d0b
JB		 4438 size = 8;
4439 }
4440 }
4441 else if (!op)
4442 {
fe56b6ce 4443 /* Floating point encoding. */
16980d0b 4444 int tmp;
43e65147 4445
fe56b6ce
NC		 4446 value = (unsigned long) (bits & 0x7f) << 19;
4447 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 4448 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 4449 value |= (unsigned long) tmp << 24;
16980d0b 4450 size = 32;
0dbde4cf 4451 isfloat = 1;
16980d0b
JB		 4452 }
4453 else
4454 {
4455 func (stream, "<illegal constant %.8x:%x:%x>",
4456 bits, cmode, op);
4457 size = 32;
4458 break;
4459 }
4460 switch (size)
4461 {
4462 case 8:
4463 func (stream, "#%ld\t; 0x%.2lx", value, value);
4464 break;
43e65147 4465
16980d0b
JB		 4466 case 16:
4467 func (stream, "#%ld\t; 0x%.4lx", value, value);
4468 break;
4469
4470 case 32:
0dbde4cf
JB		 4471 if (isfloat)
4472 {
4473 unsigned char valbytes[4];
4474 double fvalue;
43e65147 4475
0dbde4cf
JB		 4476 /* Do this a byte at a time so we don't have to
4477 worry about the host's endianness. */
4478 valbytes[0] = value & 0xff;
4479 valbytes[1] = (value >> 8) & 0xff;
4480 valbytes[2] = (value >> 16) & 0xff;
4481 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 4482
4483 floatformat_to_double
c1e26897
NC		 4484 (& floatformat_ieee_single_little, valbytes,
4485 & fvalue);
43e65147 4486
0dbde4cf
JB		 4487 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
4488 value);
4489 }
4490 else
4e9d3b81 4491 func (stream, "#%ld\t; 0x%.8lx",
43e65147 4492 (long) (((value & 0x80000000L) != 0)
9d82ec38 4493 ? value | ~0xffffffffL : value),
c1e26897 4494 value);
16980d0b
JB		 4495 break;
4496
4497 case 64:
4498 func (stream, "#0x%.8lx%.8lx", hival, value);
4499 break;
43e65147 4500
16980d0b
JB		 4501 default:
4502 abort ();
4503 }
4504 }
4505 break;
43e65147 4506
16980d0b
JB		 4507 case 'F':
4508 {
4509 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
4510 int num = (given >> 8) & 0x3;
43e65147 4511
16980d0b
JB		 4512 if (!num)
4513 func (stream, "{d%d}", regno);
4514 else if (num + regno >= 32)
4515 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
4516 else
4517 func (stream, "{d%d-d%d}", regno, regno + num);
4518 }
4519 break;
7e8e6784 4520
16980d0b
JB		 4521
4522 case '0': case '1': case '2': case '3': case '4':
4523 case '5': case '6': case '7': case '8': case '9':
4524 {
4525 int width;
4526 unsigned long value;
4527
4528 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 4529
16980d0b
JB		 4530 switch (*c)
4531 {
4532 case 'r':
4533 func (stream, "%s", arm_regnames[value]);
4534 break;
4535 case 'd':
4536 func (stream, "%ld", value);
05413229 4537 value_in_comment = value;
16980d0b
JB		 4538 break;
4539 case 'e':
4540 func (stream, "%ld", (1ul << width) - value);
4541 break;
43e65147 4542
16980d0b
JB		 4543 case 'S':
4544 case 'T':
4545 case 'U':
05413229 4546 /* Various width encodings. */
16980d0b
JB		 4547 {
4548 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
4549 int limit;
4550 unsigned low, high;
4551
4552 c++;
4553 if (*c >= '0' && *c <= '9')
4554 limit = *c - '0';
4555 else if (*c >= 'a' && *c <= 'f')
4556 limit = *c - 'a' + 10;
4557 else
4558 abort ();
4559 low = limit >> 2;
4560 high = limit & 3;
4561
4562 if (value < low || value > high)
4563 func (stream, "<illegal width %d>", base << value);
4564 else
4565 func (stream, "%d", base << value);
4566 }
4567 break;
4568 case 'R':
4569 if (given & (1 << 6))
4570 goto Q;
4571 /* FALLTHROUGH */
4572 case 'D':
4573 func (stream, "d%ld", value);
4574 break;
4575 case 'Q':
4576 Q:
4577 if (value & 1)
4578 func (stream, "<illegal reg q%ld.5>", value >> 1);
4579 else
4580 func (stream, "q%ld", value >> 1);
4581 break;
43e65147 4582
16980d0b
JB		 4583 case '`':
4584 c++;
4585 if (value == 0)
4586 func (stream, "%c", *c);
4587 break;
4588 case '\'':
4589 c++;
4590 if (value == ((1ul << width) - 1))
4591 func (stream, "%c", *c);
4592 break;
4593 case '?':
fe56b6ce 4594 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 4595 c += 1 << width;
4596 break;
4597 default:
4598 abort ();
4599 }
16980d0b 4600 }
dffaa15c
AM		 4601 break;
4602
4603 default:
4604 abort ();
16980d0b
JB		 4605 }
4606 }
4607 else
4608 func (stream, "%c", *c);
4609 }
05413229
NC		 4610
4611 if (value_in_comment > 32 || value_in_comment < -16)
4612 func (stream, "\t; 0x%lx", value_in_comment);
4613
e2efe87d
MGD		 4614 if (is_unpredictable)
4615 func (stream, UNPREDICTABLE_INSTRUCTION);
4616
16980d0b
JB		 4617 return TRUE;
4618 }
4619 }
4620 return FALSE;
4621}
4622
90ec0d68
MGD		 4623/* Return the name of a v7A special register. */
4624
43e65147 4625static const char *
90ec0d68
MGD		 4626banked_regname (unsigned reg)
4627{
4628 switch (reg)
4629 {
4630 case 15: return "CPSR";
43e65147 4631 case 32: return "R8_usr";
90ec0d68
MGD		 4632 case 33: return "R9_usr";
4633 case 34: return "R10_usr";
4634 case 35: return "R11_usr";
4635 case 36: return "R12_usr";
4636 case 37: return "SP_usr";
4637 case 38: return "LR_usr";
43e65147 4638 case 40: return "R8_fiq";
90ec0d68
MGD		 4639 case 41: return "R9_fiq";
4640 case 42: return "R10_fiq";
4641 case 43: return "R11_fiq";
4642 case 44: return "R12_fiq";
4643 case 45: return "SP_fiq";
4644 case 46: return "LR_fiq";
4645 case 48: return "LR_irq";
4646 case 49: return "SP_irq";
4647 case 50: return "LR_svc";
4648 case 51: return "SP_svc";
4649 case 52: return "LR_abt";
4650 case 53: return "SP_abt";
4651 case 54: return "LR_und";
4652 case 55: return "SP_und";
4653 case 60: return "LR_mon";
4654 case 61: return "SP_mon";
4655 case 62: return "ELR_hyp";
4656 case 63: return "SP_hyp";
4657 case 79: return "SPSR";
4658 case 110: return "SPSR_fiq";
4659 case 112: return "SPSR_irq";
4660 case 114: return "SPSR_svc";
4661 case 116: return "SPSR_abt";
4662 case 118: return "SPSR_und";
4663 case 124: return "SPSR_mon";
4664 case 126: return "SPSR_hyp";
4665 default: return NULL;
4666 }
4667}
4668
e797f7e0
MGD		 4669/* Return the name of the DMB/DSB option. */
4670static const char *
4671data_barrier_option (unsigned option)
4672{
4673 switch (option & 0xf)
4674 {
4675 case 0xf: return "sy";
4676 case 0xe: return "st";
4677 case 0xd: return "ld";
4678 case 0xb: return "ish";
4679 case 0xa: return "ishst";
4680 case 0x9: return "ishld";
4681 case 0x7: return "un";
4682 case 0x6: return "unst";
4683 case 0x5: return "nshld";
4684 case 0x3: return "osh";
4685 case 0x2: return "oshst";
4686 case 0x1: return "oshld";
4687 default: return NULL;
4688 }
4689}
4690
4a5329c6
ZW		 4691/* Print one ARM instruction from PC on INFO->STREAM. */
4692
4693static void
4694print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 4695{
6b5d3a4d 4696 const struct opcode32 *insn;
6a51a8a8 4697 void *stream = info->stream;
6b5d3a4d 4698 fprintf_ftype func = info->fprintf_func;
b0e28b39 4699 struct arm_private_data *private_data = info->private_data;
252b5132 4700
16980d0b
JB		 4701 if (print_insn_coprocessor (pc, info, given, FALSE))
4702 return;
4703
4704 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 4705 return;
4706
252b5132
RH		 4707 for (insn = arm_opcodes; insn->assembler; insn++)
4708 {
0313a2b8
NC		 4709 if ((given & insn->mask) != insn->value)
4710 continue;
823d2571
TG		 4711
4712 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 4713 continue;
4714
4715 /* Special case: an instruction with all bits set in the condition field
4716 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
4717 or by the catchall at the end of the table. */
4718 if ((given & 0xF0000000) != 0xF0000000
4719 || (insn->mask & 0xF0000000) == 0xF0000000
4720 || (insn->mask == 0 && insn->value == 0))
252b5132 4721 {
ff4a8d2b
NC		 4722 unsigned long u_reg = 16;
4723 unsigned long U_reg = 16;
ab8e2090 4724 bfd_boolean is_unpredictable = FALSE;
05413229 4725 signed long value_in_comment = 0;
6b5d3a4d 4726 const char *c;
b34976b6 4727
252b5132
RH		 4728 for (c = insn->assembler; *c; c++)
4729 {
4730 if (*c == '%')
4731 {
c1e26897
NC		 4732 bfd_boolean allow_unpredictable = FALSE;
4733
252b5132
RH		 4734 switch (*++c)
4735 {
4736 case '%':
4737 func (stream, "%%");
4738 break;
4739
4740 case 'a':
05413229 4741 value_in_comment = print_arm_address (pc, info, given);
62b3e311 4742 break;
252b5132 4743
62b3e311
PB		 4744 case 'P':
4745 /* Set P address bit and use normal address
4746 printing routine. */
c1e26897 4747 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 4748 break;
4749
c1e26897
NC		 4750 case 'S':
4751 allow_unpredictable = TRUE;
1a0670f3 4752 /* Fall through. */
252b5132
RH		 4753 case 's':
4754 if ((given & 0x004f0000) == 0x004f0000)
4755 {
58efb6c0 4756 /* PC relative with immediate offset. */
f8b960bc 4757 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 4758
aefd8a40
NC		 4759 if (PRE_BIT_SET)
4760 {
26d97720
NS		 4761 /* Elide positive zero offset. */
4762 if (offset || NEGATIVE_BIT_SET)
4763 func (stream, "[pc, #%s%d]\t; ",
d908c8af 4764 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 4765 else
26d97720
NS		 4766 func (stream, "[pc]\t; ");
4767 if (NEGATIVE_BIT_SET)
4768 offset = -offset;
aefd8a40
NC		 4769 info->print_address_func (offset + pc + 8, info);
4770 }
4771 else
4772 {
26d97720
NS		 4773 /* Always show the offset. */
4774 func (stream, "[pc], #%s%d",
d908c8af 4775 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 4776 if (! allow_unpredictable)
4777 is_unpredictable = TRUE;
aefd8a40 4778 }
252b5132
RH		 4779 }
4780 else
4781 {
fe56b6ce
NC		 4782 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
4783
b34976b6 4784 func (stream, "[%s",
252b5132 4785 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 4786
c1e26897 4787 if (PRE_BIT_SET)
252b5132 4788 {
c1e26897 4789 if (IMMEDIATE_BIT_SET)
252b5132 4790 {
26d97720
NS		 4791 /* Elide offset for non-writeback
4792 positive zero. */
4793 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
4794 || offset)
4795 func (stream, ", #%s%d",
4796 NEGATIVE_BIT_SET ? "-" : "", offset);
4797
4798 if (NEGATIVE_BIT_SET)
4799 offset = -offset;
945ee430 4800
fe56b6ce 4801 value_in_comment = offset;
252b5132 4802 }
945ee430 4803 else
ff4a8d2b
NC		 4804 {
4805 /* Register Offset or Register Pre-Indexed. */
4806 func (stream, ", %s%s",
4807 NEGATIVE_BIT_SET ? "-" : "",
4808 arm_regnames[given & 0xf]);
4809
4810 /* Writing back to the register that is the source/
4811 destination of the load/store is unpredictable. */
4812 if (! allow_unpredictable
4813 && WRITEBACK_BIT_SET
4814 && ((given & 0xf) == ((given >> 12) & 0xf)))
4815 is_unpredictable = TRUE;
4816 }
252b5132 4817
b34976b6 4818 func (stream, "]%s",
c1e26897 4819 WRITEBACK_BIT_SET ? "!" : "");
252b5132 4820 }
945ee430 4821 else
252b5132 4822 {
c1e26897 4823 if (IMMEDIATE_BIT_SET)
252b5132 4824 {
945ee430 4825 /* Immediate Post-indexed. */
aefd8a40 4826 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 4827 func (stream, "], #%s%d",
4828 NEGATIVE_BIT_SET ? "-" : "", offset);
4829 if (NEGATIVE_BIT_SET)
4830 offset = -offset;
fe56b6ce 4831 value_in_comment = offset;
252b5132 4832 }
945ee430 4833 else
ff4a8d2b
NC		 4834 {
4835 /* Register Post-indexed. */
4836 func (stream, "], %s%s",
4837 NEGATIVE_BIT_SET ? "-" : "",
4838 arm_regnames[given & 0xf]);
4839
4840 /* Writing back to the register that is the source/
4841 destination of the load/store is unpredictable. */
4842 if (! allow_unpredictable
4843 && (given & 0xf) == ((given >> 12) & 0xf))
4844 is_unpredictable = TRUE;
4845 }
c1e26897 4846
07a28fab
NC		 4847 if (! allow_unpredictable)
4848 {
4849 /* Writeback is automatically implied by post- addressing.
4850 Setting the W bit is unnecessary and ARM specify it as
4851 being unpredictable. */
4852 if (WRITEBACK_BIT_SET
4853 /* Specifying the PC register as the post-indexed
4854 registers is also unpredictable. */
ab8e2090
NC		 4855 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
4856 is_unpredictable = TRUE;
07a28fab 4857 }
252b5132
RH		 4858 }
4859 }
4860 break;
b34976b6 4861
252b5132 4862 case 'b':
6b5d3a4d 4863 {
f8b960bc 4864 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
05413229 4865 info->print_address_func (disp * 4 + pc + 8, info);
6b5d3a4d 4866 }
252b5132
RH		 4867 break;
4868
4869 case 'c':
c22aaad1
PB		 4870 if (((given >> 28) & 0xf) != 0xe)
4871 func (stream, "%s",
4872 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 4873 break;
4874
4875 case 'm':
4876 {
4877 int started = 0;
4878 int reg;
4879
4880 func (stream, "{");
4881 for (reg = 0; reg < 16; reg++)
4882 if ((given & (1 << reg)) != 0)
4883 {
4884 if (started)
4885 func (stream, ", ");
4886 started = 1;
4887 func (stream, "%s", arm_regnames[reg]);
4888 }
4889 func (stream, "}");
ab8e2090
NC		 4890 if (! started)
4891 is_unpredictable = TRUE;
252b5132
RH		 4892 }
4893 break;
4894
37b37b2d 4895 case 'q':
78c66db8 4896 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 4897 break;
4898
252b5132
RH		 4899 case 'o':
4900 if ((given & 0x02000000) != 0)
4901 {
a415b1cd
JB		 4902 unsigned int rotate = (given & 0xf00) >> 7;
4903 unsigned int immed = (given & 0xff);
4904 unsigned int a, i;
4905
4906 a = (((immed << (32 - rotate))
4907 | (immed >> rotate)) & 0xffffffff);
4908 /* If there is another encoding with smaller rotate,
4909 the rotate should be specified directly. */
4910 for (i = 0; i < 32; i += 2)
4911 if ((a << i | a >> (32 - i)) <= 0xff)
4912 break;
4913
4914 if (i != rotate)
4915 func (stream, "#%d, %d", immed, rotate);
4916 else
4917 func (stream, "#%d", a);
4918 value_in_comment = a;
252b5132
RH		 4919 }
4920 else
78c66db8 4921 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 4922 break;
4923
4924 case 'p':
4925 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 4926 {
823d2571
TG		 4927 arm_feature_set arm_ext_v6 =
4928 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
4929
aefd8a40
NC		 4930 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
4931 mechanism for setting PSR flag bits. They are
4932 obsolete in V6 onwards. */
823d2571
TG		 4933 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
4934 arm_ext_v6))
aefd8a40 4935 func (stream, "p");
4ab90a7a
AV		 4936 else
4937 is_unpredictable = TRUE;
aefd8a40 4938 }
252b5132
RH		 4939 break;
4940
4941 case 't':
4942 if ((given & 0x01200000) == 0x00200000)
4943 func (stream, "t");
4944 break;
4945
252b5132 4946 case 'A':
05413229
NC		 4947 {
4948 int offset = given & 0xff;
f02232aa 4949
05413229 4950 value_in_comment = offset * 4;
c1e26897 4951 if (NEGATIVE_BIT_SET)
05413229 4952 value_in_comment = - value_in_comment;
f02232aa 4953
05413229 4954 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 4955
c1e26897 4956 if (PRE_BIT_SET)
05413229
NC		 4957 {
4958 if (offset)
fe56b6ce 4959 func (stream, ", #%d]%s",
d908c8af 4960 (int) value_in_comment,
c1e26897 4961 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 4962 else
4963 func (stream, "]");
4964 }
4965 else
4966 {
4967 func (stream, "]");
f02232aa 4968
c1e26897 4969 if (WRITEBACK_BIT_SET)
05413229
NC		 4970 {
4971 if (offset)
d908c8af 4972 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 4973 }
4974 else
fe56b6ce 4975 {
d908c8af 4976 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 4977 value_in_comment = offset;
4978 }
05413229
NC		 4979 }
4980 }
252b5132
RH		 4981 break;
4982
077b8428
NC		 4983 case 'B':
4984 /* Print ARM V5 BLX(1) address: pc+25 bits. */
4985 {
4986 bfd_vma address;
4987 bfd_vma offset = 0;
b34976b6 4988
c1e26897 4989 if (! NEGATIVE_BIT_SET)
077b8428
NC		 4990 /* Is signed, hi bits should be ones. */
4991 offset = (-1) ^ 0x00ffffff;
4992
4993 /* Offset is (SignExtend(offset field)<<2). */
4994 offset += given & 0x00ffffff;
4995 offset <<= 2;
4996 address = offset + pc + 8;
b34976b6 4997
8f06b2d8
PB		 4998 if (given & 0x01000000)
4999 /* H bit allows addressing to 2-byte boundaries. */
5000 address += 2;
b1ee46c5 5001
8f06b2d8 5002 info->print_address_func (address, info);
b1ee46c5 5003 }
b1ee46c5
AH		 5004 break;
5005
252b5132 5006 case 'C':
90ec0d68
MGD		 5007 if ((given & 0x02000200) == 0x200)
5008 {
5009 const char * name;
5010 unsigned sysm = (given & 0x004f0000) >> 16;
5011
5012 sysm |= (given & 0x300) >> 4;
5013 name = banked_regname (sysm);
5014
5015 if (name != NULL)
5016 func (stream, "%s", name);
5017 else
d908c8af 5018 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 5019 }
5020 else
5021 {
43e65147 5022 func (stream, "%cPSR_",
90ec0d68
MGD		 5023 (given & 0x00400000) ? 'S' : 'C');
5024 if (given & 0x80000)
5025 func (stream, "f");
5026 if (given & 0x40000)
5027 func (stream, "s");
5028 if (given & 0x20000)
5029 func (stream, "x");
5030 if (given & 0x10000)
5031 func (stream, "c");
5032 }
252b5132
RH		 5033 break;
5034
62b3e311 5035 case 'U':
43e65147 5036 if ((given & 0xf0) == 0x60)
62b3e311 5037 {
52e7f43d
RE		 5038 switch (given & 0xf)
5039 {
5040 case 0xf: func (stream, "sy"); break;
5041 default:
5042 func (stream, "#%d", (int) given & 0xf);
5043 break;
5044 }
43e65147
L		 5045 }
5046 else
52e7f43d 5047 {
e797f7e0
MGD		 5048 const char * opt = data_barrier_option (given & 0xf);
5049 if (opt != NULL)
5050 func (stream, "%s", opt);
5051 else
52e7f43d 5052 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 5053 }
5054 break;
5055
b34976b6 5056 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 5057 case '5': case '6': case '7': case '8': case '9':
5058 {
16980d0b
JB		 5059 int width;
5060 unsigned long value;
252b5132 5061
16980d0b 5062 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 5063
252b5132
RH		 5064 switch (*c)
5065 {
ab8e2090
NC		 5066 case 'R':
5067 if (value == 15)
5068 is_unpredictable = TRUE;
5069 /* Fall through. */
16980d0b 5070 case 'r':
9eb6c0f1
MGD		 5071 case 'T':
5072 /* We want register + 1 when decoding T. */
5073 if (*c == 'T')
5074 ++value;
5075
ff4a8d2b
NC		 5076 if (c[1] == 'u')
5077 {
5078 /* Eat the 'u' character. */
5079 ++ c;
5080
5081 if (u_reg == value)
5082 is_unpredictable = TRUE;
5083 u_reg = value;
5084 }
5085 if (c[1] == 'U')
5086 {
5087 /* Eat the 'U' character. */
5088 ++ c;
5089
5090 if (U_reg == value)
5091 is_unpredictable = TRUE;
5092 U_reg = value;
5093 }
16980d0b
JB		 5094 func (stream, "%s", arm_regnames[value]);
5095 break;
5096 case 'd':
5097 func (stream, "%ld", value);
05413229 5098 value_in_comment = value;
16980d0b
JB		 5099 break;
5100 case 'b':
5101 func (stream, "%ld", value * 8);
05413229 5102 value_in_comment = value * 8;
16980d0b
JB		 5103 break;
5104 case 'W':
5105 func (stream, "%ld", value + 1);
05413229 5106 value_in_comment = value + 1;
16980d0b
JB		 5107 break;
5108 case 'x':
5109 func (stream, "0x%08lx", value);
5110
5111 /* Some SWI instructions have special
5112 meanings. */
5113 if ((given & 0x0fffffff) == 0x0FF00000)
5114 func (stream, "\t; IMB");
5115 else if ((given & 0x0fffffff) == 0x0FF00001)
5116 func (stream, "\t; IMBRange");
5117 break;
5118 case 'X':
5119 func (stream, "%01lx", value & 0xf);
05413229 5120 value_in_comment = value;
252b5132
RH		 5121 break;
5122 case '`':
5123 c++;
16980d0b 5124 if (value == 0)
252b5132
RH		 5125 func (stream, "%c", *c);
5126 break;
5127 case '\'':
5128 c++;
16980d0b 5129 if (value == ((1ul << width) - 1))
252b5132
RH		 5130 func (stream, "%c", *c);
5131 break;
5132 case '?':
fe56b6ce 5133 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 5134 c += 1 << width;
252b5132
RH		 5135 break;
5136 default:
5137 abort ();
5138 }
dffaa15c
AM		 5139 }
5140 break;
0dd132b6 5141
dffaa15c
AM		 5142 case 'e':
5143 {
5144 int imm;
0dd132b6 5145
dffaa15c
AM		 5146 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
5147 func (stream, "%d", imm);
5148 value_in_comment = imm;
5149 }
5150 break;
fe56b6ce 5151
dffaa15c
AM		 5152 case 'E':
5153 /* LSB and WIDTH fields of BFI or BFC. The machine-
5154 language instruction encodes LSB and MSB. */
5155 {
5156 long msb = (given & 0x001f0000) >> 16;
5157 long lsb = (given & 0x00000f80) >> 7;
5158 long w = msb - lsb + 1;
0a003adc 5159
dffaa15c
AM		 5160 if (w > 0)
5161 func (stream, "#%lu, #%lu", lsb, w);
5162 else
5163 func (stream, "(invalid: %lu:%lu)", lsb, msb);
5164 }
5165 break;
90ec0d68 5166
dffaa15c
AM		 5167 case 'R':
5168 /* Get the PSR/banked register name. */
5169 {
5170 const char * name;
5171 unsigned sysm = (given & 0x004f0000) >> 16;
90ec0d68 5172
dffaa15c
AM		 5173 sysm |= (given & 0x300) >> 4;
5174 name = banked_regname (sysm);
90ec0d68 5175
dffaa15c
AM		 5176 if (name != NULL)
5177 func (stream, "%s", name);
5178 else
5179 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
5180 }
5181 break;
fe56b6ce 5182
dffaa15c
AM		 5183 case 'V':
5184 /* 16-bit unsigned immediate from a MOVT or MOVW
5185 instruction, encoded in bits 0:11 and 15:19. */
5186 {
5187 long hi = (given & 0x000f0000) >> 4;
5188 long lo = (given & 0x00000fff);
5189 long imm16 = hi | lo;
0a003adc 5190
dffaa15c
AM		 5191 func (stream, "#%lu", imm16);
5192 value_in_comment = imm16;
252b5132 5193 }
dffaa15c
AM		 5194 break;
5195
5196 default:
5197 abort ();
252b5132
RH		 5198 }
5199 }
5200 else
5201 func (stream, "%c", *c);
5202 }
05413229
NC		 5203
5204 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 5205 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 5206
5207 if (is_unpredictable)
5208 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 5209
4a5329c6 5210 return;
252b5132
RH		 5211 }
5212 }
0b347048
TC		 5213 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
5214 return;
252b5132
RH		 5215}
5216
4a5329c6 5217/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 5218
4a5329c6
ZW		 5219static void
5220print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 5221{
6b5d3a4d 5222 const struct opcode16 *insn;
6a51a8a8
AM		 5223 void *stream = info->stream;
5224 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 5225
5226 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 5227 if ((given & insn->mask) == insn->value)
5228 {
05413229 5229 signed long value_in_comment = 0;
6b5d3a4d 5230 const char *c = insn->assembler;
05413229 5231
c19d1205
ZW		 5232 for (; *c; c++)
5233 {
5234 int domaskpc = 0;
5235 int domasklr = 0;
5236
5237 if (*c != '%')
5238 {
5239 func (stream, "%c", *c);
5240 continue;
5241 }
252b5132 5242
c19d1205
ZW		 5243 switch (*++c)
5244 {
5245 case '%':
5246 func (stream, "%%");
5247 break;
b34976b6 5248
c22aaad1
PB		 5249 case 'c':
5250 if (ifthen_state)
5251 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5252 break;
5253
5254 case 'C':
5255 if (ifthen_state)
5256 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5257 else
5258 func (stream, "s");
5259 break;
5260
5261 case 'I':
5262 {
5263 unsigned int tmp;
5264
5265 ifthen_next_state = given & 0xff;
5266 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
5267 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
5268 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
5269 }
5270 break;
5271
5272 case 'x':
5273 if (ifthen_next_state)
5274 func (stream, "\t; unpredictable branch in IT block\n");
5275 break;
5276
5277 case 'X':
5278 if (ifthen_state)
5279 func (stream, "\t; unpredictable <IT:%s>",
5280 arm_conditional[IFTHEN_COND]);
5281 break;
5282
c19d1205
ZW		 5283 case 'S':
5284 {
5285 long reg;
5286
5287 reg = (given >> 3) & 0x7;
5288 if (given & (1 << 6))
5289 reg += 8;
4f3c3dbb 5290
c19d1205
ZW		 5291 func (stream, "%s", arm_regnames[reg]);
5292 }
5293 break;
baf0cc5e 5294
c19d1205 5295 case 'D':
4f3c3dbb 5296 {
c19d1205
ZW		 5297 long reg;
5298
5299 reg = given & 0x7;
5300 if (given & (1 << 7))
5301 reg += 8;
5302
5303 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 5304 }
c19d1205
ZW		 5305 break;
5306
5307 case 'N':
5308 if (given & (1 << 8))
5309 domasklr = 1;
5310 /* Fall through. */
5311 case 'O':
5312 if (*c == 'O' && (given & (1 << 8)))
5313 domaskpc = 1;
5314 /* Fall through. */
5315 case 'M':
5316 {
5317 int started = 0;
5318 int reg;
5319
5320 func (stream, "{");
5321
5322 /* It would be nice if we could spot
5323 ranges, and generate the rS-rE format: */
5324 for (reg = 0; (reg < 8); reg++)
5325 if ((given & (1 << reg)) != 0)
5326 {
5327 if (started)
5328 func (stream, ", ");
5329 started = 1;
5330 func (stream, "%s", arm_regnames[reg]);
5331 }
5332
5333 if (domasklr)
5334 {
5335 if (started)
5336 func (stream, ", ");
5337 started = 1;
d908c8af 5338 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 5339 }
5340
5341 if (domaskpc)
5342 {
5343 if (started)
5344 func (stream, ", ");
d908c8af 5345 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 5346 }
5347
5348 func (stream, "}");
5349 }
5350 break;
5351
4547cb56
NC		 5352 case 'W':
5353 /* Print writeback indicator for a LDMIA. We are doing a
5354 writeback if the base register is not in the register
5355 mask. */
5356 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
5357 func (stream, "!");
dffaa15c 5358 break;
4547cb56 5359
c19d1205
ZW		 5360 case 'b':
5361 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
5362 {
5363 bfd_vma address = (pc + 4
5364 + ((given & 0x00f8) >> 2)
5365 + ((given & 0x0200) >> 3));
5366 info->print_address_func (address, info);
5367 }
5368 break;
5369
5370 case 's':
5371 /* Right shift immediate -- bits 6..10; 1-31 print
5372 as themselves, 0 prints as 32. */
5373 {
5374 long imm = (given & 0x07c0) >> 6;
5375 if (imm == 0)
5376 imm = 32;
0fd3a477 5377 func (stream, "#%ld", imm);
c19d1205
ZW		 5378 }
5379 break;
5380
5381 case '0': case '1': case '2': case '3': case '4':
5382 case '5': case '6': case '7': case '8': case '9':
5383 {
5384 int bitstart = *c++ - '0';
5385 int bitend = 0;
5386
5387 while (*c >= '0' && *c <= '9')
5388 bitstart = (bitstart * 10) + *c++ - '0';
5389
5390 switch (*c)
5391 {
5392 case '-':
5393 {
f8b960bc 5394 bfd_vma reg;
c19d1205
ZW		 5395
5396 c++;
5397 while (*c >= '0' && *c <= '9')
5398 bitend = (bitend * 10) + *c++ - '0';
5399 if (!bitend)
5400 abort ();
5401 reg = given >> bitstart;
5402 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 5403
c19d1205
ZW		 5404 switch (*c)
5405 {
5406 case 'r':
5407 func (stream, "%s", arm_regnames[reg]);
5408 break;
5409
5410 case 'd':
d908c8af 5411 func (stream, "%ld", (long) reg);
05413229 5412 value_in_comment = reg;
c19d1205
ZW		 5413 break;
5414
5415 case 'H':
d908c8af 5416 func (stream, "%ld", (long) (reg << 1));
05413229 5417 value_in_comment = reg << 1;
c19d1205
ZW		 5418 break;
5419
5420 case 'W':
d908c8af 5421 func (stream, "%ld", (long) (reg << 2));
05413229 5422 value_in_comment = reg << 2;
c19d1205
ZW		 5423 break;
5424
5425 case 'a':
5426 /* PC-relative address -- the bottom two
5427 bits of the address are dropped
5428 before the calculation. */
5429 info->print_address_func
5430 (((pc + 4) & ~3) + (reg << 2), info);
05413229 5431 value_in_comment = 0;
c19d1205
ZW		 5432 break;
5433
5434 case 'x':
d908c8af 5435 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 5436 break;
5437
c19d1205
ZW		 5438 case 'B':
5439 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6b5d3a4d 5440 info->print_address_func (reg * 2 + pc + 4, info);
05413229 5441 value_in_comment = 0;
c19d1205
ZW		 5442 break;
5443
5444 case 'c':
c22aaad1 5445 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 5446 break;
5447
5448 default:
5449 abort ();
5450 }
5451 }
5452 break;
5453
5454 case '\'':
5455 c++;
5456 if ((given & (1 << bitstart)) != 0)
5457 func (stream, "%c", *c);
5458 break;
5459
5460 case '?':
5461 ++c;
5462 if ((given & (1 << bitstart)) != 0)
5463 func (stream, "%c", *c++);
5464 else
5465 func (stream, "%c", *++c);
5466 break;
5467
5468 default:
5469 abort ();
5470 }
5471 }
5472 break;
5473
5474 default:
5475 abort ();
5476 }
5477 }
05413229
NC		 5478
5479 if (value_in_comment > 32 || value_in_comment < -16)
5480 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 5481 return;
c19d1205
ZW		 5482 }
5483
5484 /* No match. */
0b347048
TC		 5485 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
5486 return;
c19d1205
ZW		 5487}
5488
62b3e311 5489/* Return the name of an V7M special register. */
fe56b6ce 5490
62b3e311
PB		 5491static const char *
5492psr_name (int regno)
5493{
5494 switch (regno)
5495 {
1a336194
TP		 5496 case 0x0: return "APSR";
5497 case 0x1: return "IAPSR";
5498 case 0x2: return "EAPSR";
5499 case 0x3: return "PSR";
5500 case 0x5: return "IPSR";
5501 case 0x6: return "EPSR";
5502 case 0x7: return "IEPSR";
5503 case 0x8: return "MSP";
5504 case 0x9: return "PSP";
5505 case 0xa: return "MSPLIM";
5506 case 0xb: return "PSPLIM";
5507 case 0x10: return "PRIMASK";
5508 case 0x11: return "BASEPRI";
5509 case 0x12: return "BASEPRI_MAX";
5510 case 0x13: return "FAULTMASK";
5511 case 0x14: return "CONTROL";
16a1fa25
TP		 5512 case 0x88: return "MSP_NS";
5513 case 0x89: return "PSP_NS";
1a336194
TP		 5514 case 0x8a: return "MSPLIM_NS";
5515 case 0x8b: return "PSPLIM_NS";
5516 case 0x90: return "PRIMASK_NS";
5517 case 0x91: return "BASEPRI_NS";
5518 case 0x93: return "FAULTMASK_NS";
5519 case 0x94: return "CONTROL_NS";
5520 case 0x98: return "SP_NS";
62b3e311
PB		 5521 default: return "<unknown>";
5522 }
5523}
5524
4a5329c6
ZW		 5525/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
5526
5527static void
5528print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 5529{
6b5d3a4d 5530 const struct opcode32 *insn;
c19d1205
ZW		 5531 void *stream = info->stream;
5532 fprintf_ftype func = info->fprintf_func;
5533
16980d0b
JB		 5534 if (print_insn_coprocessor (pc, info, given, TRUE))
5535 return;
5536
5537 if (print_insn_neon (info, given, TRUE))
8f06b2d8
PB		 5538 return;
5539
c19d1205
ZW		 5540 for (insn = thumb32_opcodes; insn->assembler; insn++)
5541 if ((given & insn->mask) == insn->value)
5542 {
ff4a8d2b 5543 bfd_boolean is_unpredictable = FALSE;
05413229 5544 signed long value_in_comment = 0;
6b5d3a4d 5545 const char *c = insn->assembler;
05413229 5546
c19d1205
ZW		 5547 for (; *c; c++)
5548 {
5549 if (*c != '%')
5550 {
5551 func (stream, "%c", *c);
5552 continue;
5553 }
5554
5555 switch (*++c)
5556 {
5557 case '%':
5558 func (stream, "%%");
5559 break;
5560
c22aaad1
PB		 5561 case 'c':
5562 if (ifthen_state)
5563 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5564 break;
5565
5566 case 'x':
5567 if (ifthen_next_state)
5568 func (stream, "\t; unpredictable branch in IT block\n");
5569 break;
5570
5571 case 'X':
5572 if (ifthen_state)
5573 func (stream, "\t; unpredictable <IT:%s>",
5574 arm_conditional[IFTHEN_COND]);
5575 break;
5576
c19d1205
ZW		 5577 case 'I':
5578 {
5579 unsigned int imm12 = 0;
fe56b6ce 5580
c19d1205
ZW		 5581 imm12 |= (given & 0x000000ffu);
5582 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 5583 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 5584 func (stream, "#%u", imm12);
5585 value_in_comment = imm12;
c19d1205
ZW		 5586 }
5587 break;
5588
5589 case 'M':
5590 {
5591 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 5592
c19d1205
ZW		 5593 bits |= (given & 0x000000ffu);
5594 bits |= (given & 0x00007000u) >> 4;
5595 bits |= (given & 0x04000000u) >> 15;
5596 imm8 = (bits & 0x0ff);
5597 mod = (bits & 0xf00) >> 8;
5598 switch (mod)
5599 {
5600 case 0: imm = imm8; break;
c1e26897
NC		 5601 case 1: imm = ((imm8 << 16) | imm8); break;
5602 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
5603 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 5604 default:
5605 mod = (bits & 0xf80) >> 7;
5606 imm8 = (bits & 0x07f) | 0x80;
5607 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
5608 }
fe56b6ce
NC		 5609 func (stream, "#%u", imm);
5610 value_in_comment = imm;
c19d1205
ZW		 5611 }
5612 break;
43e65147 5613
c19d1205
ZW		 5614 case 'J':
5615 {
5616 unsigned int imm = 0;
fe56b6ce 5617
c19d1205
ZW		 5618 imm |= (given & 0x000000ffu);
5619 imm |= (given & 0x00007000u) >> 4;
5620 imm |= (given & 0x04000000u) >> 15;
5621 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 5622 func (stream, "#%u", imm);
5623 value_in_comment = imm;
c19d1205
ZW		 5624 }
5625 break;
5626
5627 case 'K':
5628 {
5629 unsigned int imm = 0;
fe56b6ce 5630
c19d1205
ZW		 5631 imm |= (given & 0x000f0000u) >> 16;
5632 imm |= (given & 0x00000ff0u) >> 0;
5633 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 5634 func (stream, "#%u", imm);
5635 value_in_comment = imm;
c19d1205
ZW		 5636 }
5637 break;
5638
74db7efb
NC		 5639 case 'H':
5640 {
5641 unsigned int imm = 0;
5642
5643 imm |= (given & 0x000f0000u) >> 4;
5644 imm |= (given & 0x00000fffu) >> 0;
5645 func (stream, "#%u", imm);
5646 value_in_comment = imm;
5647 }
5648 break;
5649
90ec0d68
MGD		 5650 case 'V':
5651 {
5652 unsigned int imm = 0;
5653
5654 imm |= (given & 0x00000fffu);
5655 imm |= (given & 0x000f0000u) >> 4;
5656 func (stream, "#%u", imm);
5657 value_in_comment = imm;
5658 }
5659 break;
5660
c19d1205
ZW		 5661 case 'S':
5662 {
5663 unsigned int reg = (given & 0x0000000fu);
5664 unsigned int stp = (given & 0x00000030u) >> 4;
5665 unsigned int imm = 0;
5666 imm |= (given & 0x000000c0u) >> 6;
5667 imm |= (given & 0x00007000u) >> 10;
5668
5669 func (stream, "%s", arm_regnames[reg]);
5670 switch (stp)
5671 {
5672 case 0:
5673 if (imm > 0)
5674 func (stream, ", lsl #%u", imm);
5675 break;
5676
5677 case 1:
5678 if (imm == 0)
5679 imm = 32;
5680 func (stream, ", lsr #%u", imm);
5681 break;
5682
5683 case 2:
5684 if (imm == 0)
5685 imm = 32;
5686 func (stream, ", asr #%u", imm);
5687 break;
5688
5689 case 3:
5690 if (imm == 0)
5691 func (stream, ", rrx");
5692 else
5693 func (stream, ", ror #%u", imm);
5694 }
5695 }
5696 break;
5697
5698 case 'a':
5699 {
5700 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 5701 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 5702 unsigned int op = (given & 0x00000f00) >> 8;
5703 unsigned int i12 = (given & 0x00000fff);
5704 unsigned int i8 = (given & 0x000000ff);
5705 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 5706 bfd_vma offset = 0;
c19d1205
ZW		 5707
5708 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 5709 if (U) /* 12-bit positive immediate offset. */
5710 {
5711 offset = i12;
5712 if (Rn != 15)
5713 value_in_comment = offset;
5714 }
5715 else if (Rn == 15) /* 12-bit negative immediate offset. */
5716 offset = - (int) i12;
5717 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 5718 {
5719 unsigned int Rm = (i8 & 0x0f);
5720 unsigned int sh = (i8 & 0x30) >> 4;
05413229 5721
c19d1205
ZW		 5722 func (stream, ", %s", arm_regnames[Rm]);
5723 if (sh)
5724 func (stream, ", lsl #%u", sh);
5725 func (stream, "]");
5726 break;
5727 }
5728 else switch (op)
5729 {
05413229 5730 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 5731 offset = i8;
5732 break;
5733
05413229 5734 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 5735 offset = -i8;
5736 break;
5737
05413229 5738 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 5739 offset = i8;
5740 writeback = TRUE;
5741 break;
5742
05413229 5743 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 5744 offset = -i8;
5745 writeback = TRUE;
5746 break;
5747
05413229 5748 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 5749 offset = i8;
5750 postind = TRUE;
5751 break;
5752
05413229 5753 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 5754 offset = -i8;
5755 postind = TRUE;
5756 break;
5757
5758 default:
5759 func (stream, ", <undefined>]");
5760 goto skip;
5761 }
5762
5763 if (postind)
d908c8af 5764 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 5765 else
5766 {
5767 if (offset)
d908c8af 5768 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 5769 func (stream, writeback ? "]!" : "]");
5770 }
5771
5772 if (Rn == 15)
5773 {
5774 func (stream, "\t; ");
5775 info->print_address_func (((pc + 4) & ~3) + offset, info);
5776 }
5777 }
5778 skip:
5779 break;
5780
5781 case 'A':
5782 {
c1e26897
NC		 5783 unsigned int U = ! NEGATIVE_BIT_SET;
5784 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 5785 unsigned int Rn = (given & 0x000f0000) >> 16;
5786 unsigned int off = (given & 0x000000ff);
5787
5788 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 5789
5790 if (PRE_BIT_SET)
c19d1205
ZW		 5791 {
5792 if (off || !U)
05413229
NC		 5793 {
5794 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
fe50e98c 5795 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 5796 }
c19d1205
ZW		 5797 func (stream, "]");
5798 if (W)
5799 func (stream, "!");
5800 }
5801 else
5802 {
5803 func (stream, "], ");
5804 if (W)
05413229
NC		 5805 {
5806 func (stream, "#%c%u", U ? '+' : '-', off * 4);
fe50e98c 5807 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 5808 }
c19d1205 5809 else
fe56b6ce
NC		 5810 {
5811 func (stream, "{%u}", off);
5812 value_in_comment = off;
5813 }
c19d1205
ZW		 5814 }
5815 }
5816 break;
5817
5818 case 'w':
5819 {
5820 unsigned int Sbit = (given & 0x01000000) >> 24;
5821 unsigned int type = (given & 0x00600000) >> 21;
05413229 5822
c19d1205
ZW		 5823 switch (type)
5824 {
5825 case 0: func (stream, Sbit ? "sb" : "b"); break;
5826 case 1: func (stream, Sbit ? "sh" : "h"); break;
5827 case 2:
5828 if (Sbit)
5829 func (stream, "??");
5830 break;
5831 case 3:
5832 func (stream, "??");
5833 break;
5834 }
5835 }
5836 break;
5837
5838 case 'm':
5839 {
5840 int started = 0;
5841 int reg;
5842
5843 func (stream, "{");
5844 for (reg = 0; reg < 16; reg++)
5845 if ((given & (1 << reg)) != 0)
5846 {
5847 if (started)
5848 func (stream, ", ");
5849 started = 1;
5850 func (stream, "%s", arm_regnames[reg]);
5851 }
5852 func (stream, "}");
5853 }
5854 break;
5855
5856 case 'E':
5857 {
5858 unsigned int msb = (given & 0x0000001f);
5859 unsigned int lsb = 0;
fe56b6ce 5860
c19d1205
ZW		 5861 lsb |= (given & 0x000000c0u) >> 6;
5862 lsb |= (given & 0x00007000u) >> 10;
5863 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
5864 }
5865 break;
5866
5867 case 'F':
5868 {
5869 unsigned int width = (given & 0x0000001f) + 1;
5870 unsigned int lsb = 0;
fe56b6ce 5871
c19d1205
ZW		 5872 lsb |= (given & 0x000000c0u) >> 6;
5873 lsb |= (given & 0x00007000u) >> 10;
5874 func (stream, "#%u, #%u", lsb, width);
5875 }
5876 break;
5877
e12437dc
AV		 5878 case 'G':
5879 {
5880 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
5881 func (stream, "%x", boff);
5882 }
5883 break;
5884
e5d6e09e
AV		 5885 case 'W':
5886 {
5887 unsigned int immA = (given & 0x001f0000u) >> 16;
5888 unsigned int immB = (given & 0x000007feu) >> 1;
5889 unsigned int immC = (given & 0x00000800u) >> 11;
5890 bfd_vma offset = 0;
5891
5892 offset |= immA << 12;
5893 offset |= immB << 2;
5894 offset |= immC << 1;
5895 /* Sign extend. */
5896 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
5897
5898 info->print_address_func (pc + 4 + offset, info);
5899 }
5900 break;
5901
1caf72a5
AV		 5902 case 'Y':
5903 {
5904 unsigned int immA = (given & 0x007f0000u) >> 16;
5905 unsigned int immB = (given & 0x000007feu) >> 1;
5906 unsigned int immC = (given & 0x00000800u) >> 11;
5907 bfd_vma offset = 0;
5908
5909 offset |= immA << 12;
5910 offset |= immB << 2;
5911 offset |= immC << 1;
5912 /* Sign extend. */
5913 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
5914
5915 info->print_address_func (pc + 4 + offset, info);
5916 }
5917 break;
5918
c19d1205
ZW		 5919 case 'b':
5920 {
5921 unsigned int S = (given & 0x04000000u) >> 26;
5922 unsigned int J1 = (given & 0x00002000u) >> 13;
5923 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 5924 bfd_vma offset = 0;
c19d1205
ZW		 5925
5926 offset |= !S << 20;
5927 offset |= J2 << 19;
5928 offset |= J1 << 18;
5929 offset |= (given & 0x003f0000) >> 4;
5930 offset |= (given & 0x000007ff) << 1;
5931 offset -= (1 << 20);
5932
5933 info->print_address_func (pc + 4 + offset, info);
5934 }
5935 break;
5936
5937 case 'B':
5938 {
5939 unsigned int S = (given & 0x04000000u) >> 26;
5940 unsigned int I1 = (given & 0x00002000u) >> 13;
5941 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 5942 bfd_vma offset = 0;
c19d1205
ZW		 5943
5944 offset |= !S << 24;
5945 offset |= !(I1 ^ S) << 23;
5946 offset |= !(I2 ^ S) << 22;
5947 offset |= (given & 0x03ff0000u) >> 4;
5948 offset |= (given & 0x000007ffu) << 1;
5949 offset -= (1 << 24);
36b0c57d 5950 offset += pc + 4;
c19d1205 5951
36b0c57d
PB		 5952 /* BLX target addresses are always word aligned. */
5953 if ((given & 0x00001000u) == 0)
5954 offset &= ~2u;
5955
5956 info->print_address_func (offset, info);
c19d1205
ZW		 5957 }
5958 break;
5959
5960 case 's':
5961 {
5962 unsigned int shift = 0;
fe56b6ce 5963
c19d1205
ZW		 5964 shift |= (given & 0x000000c0u) >> 6;
5965 shift |= (given & 0x00007000u) >> 10;
c1e26897 5966 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 5967 func (stream, ", asr #%u", shift);
5968 else if (shift)
5969 func (stream, ", lsl #%u", shift);
5970 /* else print nothing - lsl #0 */
5971 }
5972 break;
5973
5974 case 'R':
5975 {
5976 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 5977
c19d1205
ZW		 5978 if (rot)
5979 func (stream, ", ror #%u", rot * 8);
5980 }
5981 break;
5982
62b3e311 5983 case 'U':
43e65147 5984 if ((given & 0xf0) == 0x60)
62b3e311 5985 {
52e7f43d
RE		 5986 switch (given & 0xf)
5987 {
5988 case 0xf: func (stream, "sy"); break;
5989 default:
5990 func (stream, "#%d", (int) given & 0xf);
5991 break;
5992 }
62b3e311 5993 }
43e65147 5994 else
52e7f43d 5995 {
e797f7e0
MGD		 5996 const char * opt = data_barrier_option (given & 0xf);
5997 if (opt != NULL)
5998 func (stream, "%s", opt);
5999 else
6000 func (stream, "#%d", (int) given & 0xf);
52e7f43d 6001 }
62b3e311
PB		 6002 break;
6003
6004 case 'C':
6005 if ((given & 0xff) == 0)
6006 {
6007 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
6008 if (given & 0x800)
6009 func (stream, "f");
6010 if (given & 0x400)
6011 func (stream, "s");
6012 if (given & 0x200)
6013 func (stream, "x");
6014 if (given & 0x100)
6015 func (stream, "c");
6016 }
90ec0d68
MGD		 6017 else if ((given & 0x20) == 0x20)
6018 {
6019 char const* name;
6020 unsigned sysm = (given & 0xf00) >> 8;
6021
6022 sysm |= (given & 0x30);
6023 sysm |= (given & 0x00100000) >> 14;
6024 name = banked_regname (sysm);
43e65147 6025
90ec0d68
MGD		 6026 if (name != NULL)
6027 func (stream, "%s", name);
6028 else
d908c8af 6029 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 6030 }
62b3e311
PB		 6031 else
6032 {
d908c8af 6033 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 6034 }
6035 break;
6036
6037 case 'D':
90ec0d68
MGD		 6038 if (((given & 0xff) == 0)
6039 || ((given & 0x20) == 0x20))
6040 {
6041 char const* name;
6042 unsigned sm = (given & 0xf0000) >> 16;
6043
6044 sm |= (given & 0x30);
6045 sm |= (given & 0x00100000) >> 14;
6046 name = banked_regname (sm);
6047
6048 if (name != NULL)
6049 func (stream, "%s", name);
6050 else
d908c8af 6051 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 6052 }
62b3e311 6053 else
d908c8af 6054 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 6055 break;
6056
c19d1205
ZW		 6057 case '0': case '1': case '2': case '3': case '4':
6058 case '5': case '6': case '7': case '8': case '9':
6059 {
16980d0b
JB		 6060 int width;
6061 unsigned long val;
c19d1205 6062
16980d0b 6063 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 6064
c19d1205
ZW		 6065 switch (*c)
6066 {
05413229
NC		 6067 case 'd':
6068 func (stream, "%lu", val);
6069 value_in_comment = val;
6070 break;
ff4a8d2b 6071
f0fba320
RL		 6072 case 'D':
6073 func (stream, "%lu", val + 1);
6074 value_in_comment = val + 1;
6075 break;
6076
05413229
NC		 6077 case 'W':
6078 func (stream, "%lu", val * 4);
6079 value_in_comment = val * 4;
6080 break;
ff4a8d2b 6081
f1c7f421
AV		 6082 case 'S':
6083 if (val == 13)
6084 is_unpredictable = TRUE;
6085 /* Fall through. */
ff4a8d2b
NC		 6086 case 'R':
6087 if (val == 15)
6088 is_unpredictable = TRUE;
6089 /* Fall through. */
6090 case 'r':
6091 func (stream, "%s", arm_regnames[val]);
6092 break;
c19d1205
ZW		 6093
6094 case 'c':
c22aaad1 6095 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 6096 break;
6097
6098 case '\'':
c19d1205 6099 c++;
16980d0b
JB		 6100 if (val == ((1ul << width) - 1))
6101 func (stream, "%c", *c);
c19d1205 6102 break;
43e65147 6103
c19d1205 6104 case '`':
c19d1205 6105 c++;
16980d0b
JB		 6106 if (val == 0)
6107 func (stream, "%c", *c);
c19d1205
ZW		 6108 break;
6109
6110 case '?':
fe56b6ce 6111 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 6112 c += 1 << width;
c19d1205 6113 break;
43e65147 6114
0bb027fd
RR		 6115 case 'x':
6116 func (stream, "0x%lx", val & 0xffffffffUL);
6117 break;
c19d1205
ZW		 6118
6119 default:
6120 abort ();
6121 }
6122 }
6123 break;
6124
32a94698
NC		 6125 case 'L':
6126 /* PR binutils/12534
6127 If we have a PC relative offset in an LDRD or STRD
6128 instructions then display the decoded address. */
6129 if (((given >> 16) & 0xf) == 0xf)
6130 {
6131 bfd_vma offset = (given & 0xff) * 4;
6132
6133 if ((given & (1 << 23)) == 0)
6134 offset = - offset;
6135 func (stream, "\t; ");
6136 info->print_address_func ((pc & ~3) + 4 + offset, info);
6137 }
6138 break;
6139
c19d1205
ZW		 6140 default:
6141 abort ();
6142 }
6143 }
05413229
NC		 6144
6145 if (value_in_comment > 32 || value_in_comment < -16)
6146 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 6147
6148 if (is_unpredictable)
6149 func (stream, UNPREDICTABLE_INSTRUCTION);
6150
4a5329c6 6151 return;
c19d1205 6152 }
252b5132 6153
58efb6c0 6154 /* No match. */
0b347048
TC		 6155 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
6156 return;
252b5132
RH		 6157}
6158
e821645d
DJ		 6159/* Print data bytes on INFO->STREAM. */
6160
6161static void
fe56b6ce
NC		 6162print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
6163 struct disassemble_info *info,
e821645d
DJ		 6164 long given)
6165{
6166 switch (info->bytes_per_chunk)
6167 {
6168 case 1:
6169 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
6170 break;
6171 case 2:
6172 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
6173 break;
6174 case 4:
6175 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
6176 break;
6177 default:
6178 abort ();
6179 }
6180}
6181
22a398e1 6182/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 6183 being displayed in symbol relative addresses.
6184
6185 Also disallow private symbol, with __tagsym$$ prefix,
6186 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 6187
6188bfd_boolean
6189arm_symbol_is_valid (asymbol * sym,
6190 struct disassemble_info * info ATTRIBUTE_UNUSED)
6191{
6192 const char * name;
43e65147 6193
22a398e1
NC		 6194 if (sym == NULL)
6195 return FALSE;
6196
6197 name = bfd_asymbol_name (sym);
6198
d8282f0e 6199 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 6200}
6201
65b48a81 6202/* Parse the string of disassembler options. */
baf0cc5e 6203
65b48a81 6204static void
f995bbe8 6205parse_arm_disassembler_options (const char *options)
dd92f639 6206{
f995bbe8 6207 const char *opt;
b34976b6 6208
65b48a81 6209 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
dd92f639 6210 {
65b48a81
PB		 6211 if (CONST_STRNEQ (opt, "reg-names-"))
6212 {
6213 unsigned int i;
6214 for (i = 0; i < NUM_ARM_OPTIONS; i++)
6215 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
6216 {
6217 regname_selected = i;
6218 break;
6219 }
b34976b6 6220
65b48a81 6221 if (i >= NUM_ARM_OPTIONS)
a6743a54
AM		 6222 /* xgettext: c-format */
6223 opcodes_error_handler (_("unrecognised register name set: %s"),
6224 opt);
65b48a81
PB		 6225 }
6226 else if (CONST_STRNEQ (opt, "force-thumb"))
6227 force_thumb = 1;
6228 else if (CONST_STRNEQ (opt, "no-force-thumb"))
6229 force_thumb = 0;
6230 else
a6743a54
AM		 6231 /* xgettext: c-format */
6232 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
dd92f639 6233 }
b34976b6 6234
dd92f639
NC		 6235 return;
6236}
6237
5bc5ae88
RL		 6238static bfd_boolean
6239mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6240 enum map_type *map_symbol);
6241
c22aaad1
PB		 6242/* Search back through the insn stream to determine if this instruction is
6243 conditionally executed. */
fe56b6ce 6244
c22aaad1 6245static void
fe56b6ce
NC		 6246find_ifthen_state (bfd_vma pc,
6247 struct disassemble_info *info,
c22aaad1
PB		 6248 bfd_boolean little)
6249{
6250 unsigned char b[2];
6251 unsigned int insn;
6252 int status;
6253 /* COUNT is twice the number of instructions seen. It will be odd if we
6254 just crossed an instruction boundary. */
6255 int count;
6256 int it_count;
6257 unsigned int seen_it;
6258 bfd_vma addr;
6259
6260 ifthen_address = pc;
6261 ifthen_state = 0;
6262
6263 addr = pc;
6264 count = 1;
6265 it_count = 0;
6266 seen_it = 0;
6267 /* Scan backwards looking for IT instructions, keeping track of where
6268 instruction boundaries are. We don't know if something is actually an
6269 IT instruction until we find a definite instruction boundary. */
6270 for (;;)
6271 {
fe56b6ce 6272 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 6273 {
6274 /* A symbol must be on an instruction boundary, and will not
6275 be within an IT block. */
6276 if (seen_it && (count & 1))
6277 break;
6278
6279 return;
6280 }
6281 addr -= 2;
fe56b6ce 6282 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 6283 if (status)
6284 return;
6285
6286 if (little)
6287 insn = (b[0]) | (b[1] << 8);
6288 else
6289 insn = (b[1]) | (b[0] << 8);
6290 if (seen_it)
6291 {
6292 if ((insn & 0xf800) < 0xe800)
6293 {
6294 /* Addr + 2 is an instruction boundary. See if this matches
6295 the expected boundary based on the position of the last
6296 IT candidate. */
6297 if (count & 1)
6298 break;
6299 seen_it = 0;
6300 }
6301 }
6302 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
6303 {
5bc5ae88
RL		 6304 enum map_type type = MAP_ARM;
6305 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
6306
6307 if (!found || (found && type == MAP_THUMB))
6308 {
6309 /* This could be an IT instruction. */
6310 seen_it = insn;
6311 it_count = count >> 1;
6312 }
c22aaad1
PB		 6313 }
6314 if ((insn & 0xf800) >= 0xe800)
6315 count++;
6316 else
6317 count = (count + 2) | 1;
6318 /* IT blocks contain at most 4 instructions. */
6319 if (count >= 8 && !seen_it)
6320 return;
6321 }
6322 /* We found an IT instruction. */
6323 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
6324 if ((ifthen_state & 0xf) == 0)
6325 ifthen_state = 0;
6326}
6327
b0e28b39
DJ		 6328/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
6329 mapping symbol. */
6330
6331static int
6332is_mapping_symbol (struct disassemble_info *info, int n,
6333 enum map_type *map_type)
6334{
6335 const char *name;
6336
6337 name = bfd_asymbol_name (info->symtab[n]);
6338 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
6339 && (name[2] == 0 || name[2] == '.'))
6340 {
6341 *map_type = ((name[1] == 'a') ? MAP_ARM
6342 : (name[1] == 't') ? MAP_THUMB
6343 : MAP_DATA);
6344 return TRUE;
6345 }
6346
6347 return FALSE;
6348}
6349
6350/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
6351 Returns nonzero if *MAP_TYPE was set. */
6352
6353static int
6354get_map_sym_type (struct disassemble_info *info,
6355 int n,
6356 enum map_type *map_type)
6357{
6358 /* If the symbol is in a different section, ignore it. */
6359 if (info->section != NULL && info->section != info->symtab[n]->section)
6360 return FALSE;
6361
6362 return is_mapping_symbol (info, n, map_type);
6363}
6364
6365/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 6366 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 6367
6368static int
fe56b6ce
NC		 6369get_sym_code_type (struct disassemble_info *info,
6370 int n,
e821645d 6371 enum map_type *map_type)
2087ad84
PB		 6372{
6373 elf_symbol_type *es;
6374 unsigned int type;
b0e28b39
DJ		 6375
6376 /* If the symbol is in a different section, ignore it. */
6377 if (info->section != NULL && info->section != info->symtab[n]->section)
6378 return FALSE;
2087ad84 6379
e821645d 6380 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 6381 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6382
6383 /* If the symbol has function type then use that. */
34e77a92 6384 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 6385 {
39d911fc
TP		 6386 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6387 == ST_BRANCH_TO_THUMB)
35fc36a8
RS		 6388 *map_type = MAP_THUMB;
6389 else
6390 *map_type = MAP_ARM;
2087ad84
PB		 6391 return TRUE;
6392 }
6393
2087ad84
PB		 6394 return FALSE;
6395}
6396
5bc5ae88
RL		 6397/* Search the mapping symbol state for instruction at pc. This is only
6398 applicable for elf target.
6399
6400 There is an assumption Here, info->private_data contains the correct AND
6401 up-to-date information about current scan process. The information will be
6402 used to speed this search process.
6403
6404 Return TRUE if the mapping state can be determined, and map_symbol
6405 will be updated accordingly. Otherwise, return FALSE. */
6406
6407static bfd_boolean
6408mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6409 enum map_type *map_symbol)
6410{
796d6298
TC		 6411 bfd_vma addr, section_vma = 0;
6412 int n, last_sym = -1;
5bc5ae88 6413 bfd_boolean found = FALSE;
796d6298
TC		 6414 bfd_boolean can_use_search_opt_p = FALSE;
6415
6416 /* Default to DATA. A text section is required by the ABI to contain an
6417 INSN mapping symbol at the start. A data section has no such
6418 requirement, hence if no mapping symbol is found the section must
6419 contain only data. This however isn't very useful if the user has
6420 fully stripped the binaries. If this is the case use the section
6421 attributes to determine the default. If we have no section default to
6422 INSN as well, as we may be disassembling some raw bytes on a baremetal
6423 HEX file or similar. */
6424 enum map_type type = MAP_DATA;
6425 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
6426 type = MAP_ARM;
5bc5ae88
RL		 6427 struct arm_private_data *private_data;
6428
796d6298 6429 if (info->private_data == NULL
5bc5ae88
RL		 6430 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
6431 return FALSE;
6432
6433 private_data = info->private_data;
5bc5ae88 6434
796d6298
TC		 6435 /* First, look for mapping symbols. */
6436 if (info->symtab_size != 0)
6437 {
6438 if (pc <= private_data->last_mapping_addr)
6439 private_data->last_mapping_sym = -1;
6440
6441 /* Start scanning at the start of the function, or wherever
6442 we finished last time. */
6443 n = info->symtab_pos + 1;
6444
6445 /* If the last stop offset is different from the current one it means we
6446 are disassembling a different glob of bytes. As such the optimization
6447 would not be safe and we should start over. */
6448 can_use_search_opt_p
6449 = private_data->last_mapping_sym >= 0
6450 && info->stop_offset == private_data->last_stop_offset;
6451
6452 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
6453 n = private_data->last_mapping_sym;
6454
6455 /* Look down while we haven't passed the location being disassembled.
6456 The reason for this is that there's no defined order between a symbol
6457 and an mapping symbol that may be at the same address. We may have to
6458 look at least one position ahead. */
6459 for (; n < info->symtab_size; n++)
6460 {
6461 addr = bfd_asymbol_value (info->symtab[n]);
6462 if (addr > pc)
6463 break;
6464 if (get_map_sym_type (info, n, &type))
6465 {
6466 last_sym = n;
6467 found = TRUE;
6468 }
6469 }
5bc5ae88 6470
796d6298
TC		 6471 if (!found)
6472 {
6473 n = info->symtab_pos;
6474 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
6475 n = private_data->last_mapping_sym;
6476
6477 /* No mapping symbol found at this address. Look backwards
6478 for a preceeding one, but don't go pass the section start
6479 otherwise a data section with no mapping symbol can pick up
6480 a text mapping symbol of a preceeding section. The documentation
6481 says section can be NULL, in which case we will seek up all the
6482 way to the top. */
6483 if (info->section)
6484 section_vma = info->section->vma;
6485
6486 for (; n >= 0; n--)
6487 {
6488 addr = bfd_asymbol_value (info->symtab[n]);
6489 if (addr < section_vma)
6490 break;
6491
6492 if (get_map_sym_type (info, n, &type))
6493 {
6494 last_sym = n;
6495 found = TRUE;
6496 break;
6497 }
6498 }
6499 }
6500 }
6501
6502 /* If no mapping symbol was found, try looking up without a mapping
6503 symbol. This is done by walking up from the current PC to the nearest
6504 symbol. We don't actually have to loop here since symtab_pos will
6505 contain the nearest symbol already. */
6506 if (!found)
5bc5ae88 6507 {
796d6298
TC		 6508 n = info->symtab_pos;
6509 if (n >= 0 && get_sym_code_type (info, n, &type))
5bc5ae88 6510 {
796d6298
TC		 6511 last_sym = n;
6512 found = TRUE;
5bc5ae88
RL		 6513 }
6514 }
6515
796d6298
TC		 6516 private_data->last_mapping_sym = last_sym;
6517 private_data->last_type = type;
6518 private_data->last_stop_offset = info->stop_offset;
5bc5ae88
RL		 6519
6520 *map_symbol = type;
6521 return found;
6522}
6523
0313a2b8
NC		 6524/* Given a bfd_mach_arm_XXX value, this function fills in the fields
6525 of the supplied arm_feature_set structure with bitmasks indicating
c0c468d5 6526 the supported base architectures and coprocessor extensions.
0313a2b8
NC		 6527
6528 FIXME: This could more efficiently implemented as a constant array,
6529 although it would also be less robust. */
6530
6531static void
6532select_arm_features (unsigned long mach,
6533 arm_feature_set * features)
6534{
c0c468d5
TP		 6535 arm_feature_set arch_fset;
6536 const arm_feature_set fpu_any = FPU_ANY;
6537
1af1dd51
MW		 6538#undef ARM_SET_FEATURES
6539#define ARM_SET_FEATURES(FSET) \
6540 { \
6541 const arm_feature_set fset = FSET; \
c0c468d5 6542 arch_fset = fset; \
1af1dd51 6543 }
823d2571 6544
c0c468d5
TP		 6545 /* When several architecture versions share the same bfd_mach_arm_XXX value
6546 the most featureful is chosen. */
0313a2b8
NC		 6547 switch (mach)
6548 {
c0c468d5
TP		 6549 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
6550 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
6551 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
6552 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
6553 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
6554 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
6555 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
6556 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
6557 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
6558 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
1af1dd51 6559 case bfd_mach_arm_ep9312:
c0c468d5
TP		 6560 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
6561 ARM_CEXT_MAVERICK | FPU_MAVERICK));
1af1dd51 6562 break;
c0c468d5
TP		 6563 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
6564 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
6565 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
6566 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
6567 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
6568 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
6569 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
6570 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
6571 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
6572 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
6573 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
6574 case bfd_mach_arm_8:
6575 {
0632eeea
SD		 6576 /* Add bits for extensions that Armv8.5-A recognizes. */
6577 arm_feature_set armv8_5_ext_fset
6578 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
6579 ARM_SET_FEATURES (ARM_ARCH_V8_5A);
6580 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset);
c0c468d5
TP		 6581 break;
6582 }
6583 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
6584 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
6585 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
031254f2 6586 case bfd_mach_arm_8_1M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN); break;
c0c468d5
TP		 6587 /* If the machine type is unknown allow all architecture types and all
6588 extensions. */
6589 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
0313a2b8
NC		 6590 default:
6591 abort ();
6592 }
1af1dd51 6593#undef ARM_SET_FEATURES
c0c468d5
TP		 6594
6595 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
6596 and thus on bfd_mach_arm_XXX value. Therefore for a given
6597 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
6598 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
0313a2b8
NC		 6599}
6600
6601
58efb6c0
NC		 6602/* NOTE: There are no checks in these routines that
6603 the relevant number of data bytes exist. */
baf0cc5e 6604
58efb6c0 6605static int
4a5329c6 6606print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 6607{
c19d1205
ZW		 6608 unsigned char b[4];
6609 long given;
6610 int status;
e821645d 6611 int is_thumb = FALSE;
b0e28b39 6612 int is_data = FALSE;
bd2e2557 6613 int little_code;
e821645d 6614 unsigned int size = 4;
4a5329c6 6615 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 6616 bfd_boolean found = FALSE;
b0e28b39 6617 struct arm_private_data *private_data;
58efb6c0 6618
dd92f639
NC		 6619 if (info->disassembler_options)
6620 {
65b48a81 6621 parse_arm_disassembler_options (info->disassembler_options);
b34976b6 6622
58efb6c0 6623 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 6624 info->disassembler_options = NULL;
6625 }
b34976b6 6626
0313a2b8
NC		 6627 /* PR 10288: Control which instructions will be disassembled. */
6628 if (info->private_data == NULL)
6629 {
b0e28b39 6630 static struct arm_private_data private;
0313a2b8
NC		 6631
6632 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
6633 /* If the user did not use the -m command line switch then default to
6634 disassembling all types of ARM instruction.
43e65147 6635
0313a2b8
NC		 6636 The info->mach value has to be ignored as this will be based on
6637 the default archictecture for the target and/or hints in the notes
6638 section, but it will never be greater than the current largest arm
6639 machine value (iWMMXt2), which is only equivalent to the V5TE
6640 architecture. ARM architectures have advanced beyond the machine
6641 value encoding, and these newer architectures would be ignored if
6642 the machine value was used.
6643
6644 Ie the -m switch is used to restrict which instructions will be
6645 disassembled. If it is necessary to use the -m switch to tell
6646 objdump that an ARM binary is being disassembled, eg because the
6647 input is a raw binary file, but it is also desired to disassemble
6648 all ARM instructions then use "-marm". This will select the
6649 "unknown" arm architecture which is compatible with any ARM
6650 instruction. */
6651 info->mach = bfd_mach_arm_unknown;
6652
6653 /* Compute the architecture bitmask from the machine number.
6654 Note: This assumes that the machine number will not change
6655 during disassembly.... */
b0e28b39 6656 select_arm_features (info->mach, & private.features);
0313a2b8 6657
1fbaefec
PB		 6658 private.last_mapping_sym = -1;
6659 private.last_mapping_addr = 0;
796d6298 6660 private.last_stop_offset = 0;
b0e28b39
DJ		 6661
6662 info->private_data = & private;
0313a2b8 6663 }
b0e28b39
DJ		 6664
6665 private_data = info->private_data;
6666
bd2e2557
SS		 6667 /* Decide if our code is going to be little-endian, despite what the
6668 function argument might say. */
6669 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
6670
b0e28b39
DJ		 6671 /* For ELF, consult the symbol table to determine what kind of code
6672 or data we have. */
8977d4b2 6673 if (info->symtab_size != 0
e821645d
DJ		 6674 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
6675 {
6676 bfd_vma addr;
796d6298 6677 int n;
e821645d 6678 int last_sym = -1;
b0e28b39 6679 enum map_type type = MAP_ARM;
e821645d 6680
796d6298
TC		 6681 found = mapping_symbol_for_insn (pc, info, &type);
6682 last_sym = private_data->last_mapping_sym;
e821645d 6683
1fbaefec
PB		 6684 is_thumb = (private_data->last_type == MAP_THUMB);
6685 is_data = (private_data->last_type == MAP_DATA);
b34976b6 6686
e821645d
DJ		 6687 /* Look a little bit ahead to see if we should print out
6688 two or four bytes of data. If there's a symbol,
6689 mapping or otherwise, after two bytes then don't
6690 print more. */
6691 if (is_data)
6692 {
6693 size = 4 - (pc & 3);
6694 for (n = last_sym + 1; n < info->symtab_size; n++)
6695 {
6696 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 6697 if (addr > pc
6698 && (info->section == NULL
6699 || info->section == info->symtab[n]->section))
e821645d
DJ		 6700 {
6701 if (addr - pc < size)
6702 size = addr - pc;
6703 break;
6704 }
6705 }
6706 /* If the next symbol is after three bytes, we need to
6707 print only part of the data, so that we can use either
6708 .byte or .short. */
6709 if (size == 3)
6710 size = (pc & 1) ? 1 : 2;
6711 }
6712 }
6713
6714 if (info->symbols != NULL)
252b5132 6715 {
5876e06d
NC		 6716 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
6717 {
2f0ca46a 6718 coff_symbol_type * cs;
b34976b6 6719
5876e06d
NC		 6720 cs = coffsymbol (*info->symbols);
6721 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
6722 || cs->native->u.syment.n_sclass == C_THUMBSTAT
6723 || cs->native->u.syment.n_sclass == C_THUMBLABEL
6724 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
6725 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
6726 }
e821645d
DJ		 6727 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
6728 && !found)
5876e06d 6729 {
2087ad84
PB		 6730 /* If no mapping symbol has been found then fall back to the type
6731 of the function symbol. */
e821645d
DJ		 6732 elf_symbol_type * es;
6733 unsigned int type;
2087ad84 6734
e821645d
DJ		 6735 es = *(elf_symbol_type **)(info->symbols);
6736 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 6737
39d911fc
TP		 6738 is_thumb =
6739 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6740 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
5876e06d 6741 }
e49d43ff
TG		 6742 else if (bfd_asymbol_flavour (*info->symbols)
6743 == bfd_target_mach_o_flavour)
6744 {
6745 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
6746
6747 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
6748 }
5876e06d 6749 }
b34976b6 6750
e821645d
DJ		 6751 if (force_thumb)
6752 is_thumb = TRUE;
6753
b8f9ee44
CL		 6754 if (is_data)
6755 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6756 else
6757 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6758
c19d1205 6759 info->bytes_per_line = 4;
252b5132 6760
1316c8b3
NC		 6761 /* PR 10263: Disassemble data if requested to do so by the user. */
6762 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 6763 {
6764 int i;
6765
1316c8b3 6766 /* Size was already set above. */
e821645d
DJ		 6767 info->bytes_per_chunk = size;
6768 printer = print_insn_data;
6769
fe56b6ce 6770 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 6771 given = 0;
6772 if (little)
6773 for (i = size - 1; i >= 0; i--)
6774 given = b[i] | (given << 8);
6775 else
6776 for (i = 0; i < (int) size; i++)
6777 given = b[i] | (given << 8);
6778 }
6779 else if (!is_thumb)
252b5132 6780 {
c19d1205
ZW		 6781 /* In ARM mode endianness is a straightforward issue: the instruction
6782 is four bytes long and is either ordered 0123 or 3210. */
6783 printer = print_insn_arm;
6784 info->bytes_per_chunk = 4;
4a5329c6 6785 size = 4;
c19d1205 6786
0313a2b8 6787 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 6788 if (little_code)
c19d1205
ZW		 6789 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
6790 else
6791 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
252b5132 6792 }
58efb6c0 6793 else
252b5132 6794 {
c19d1205
ZW		 6795 /* In Thumb mode we have the additional wrinkle of two
6796 instruction lengths. Fortunately, the bits that determine
6797 the length of the current instruction are always to be found
6798 in the first two bytes. */
4a5329c6 6799 printer = print_insn_thumb16;
c19d1205 6800 info->bytes_per_chunk = 2;
4a5329c6
ZW		 6801 size = 2;
6802
fe56b6ce 6803 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 6804 if (little_code)
9a2ff3f5
AM		 6805 given = (b[0]) | (b[1] << 8);
6806 else
6807 given = (b[1]) | (b[0] << 8);
6808
c19d1205 6809 if (!status)
252b5132 6810 {
c19d1205
ZW		 6811 /* These bit patterns signal a four-byte Thumb
6812 instruction. */
6813 if ((given & 0xF800) == 0xF800
6814 || (given & 0xF800) == 0xF000
6815 || (given & 0xF800) == 0xE800)
252b5132 6816 {
0313a2b8 6817 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 6818 if (little_code)
c19d1205 6819 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 6820 else
c19d1205
ZW		 6821 given = (b[1]) | (b[0] << 8) | (given << 16);
6822
6823 printer = print_insn_thumb32;
4a5329c6 6824 size = 4;
252b5132 6825 }
252b5132 6826 }
c22aaad1
PB		 6827
6828 if (ifthen_address != pc)
0313a2b8 6829 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 6830
6831 if (ifthen_state)
6832 {
6833 if ((ifthen_state & 0xf) == 0x8)
6834 ifthen_next_state = 0;
6835 else
6836 ifthen_next_state = (ifthen_state & 0xe0)
6837 | ((ifthen_state & 0xf) << 1);
6838 }
252b5132 6839 }
b34976b6 6840
c19d1205
ZW		 6841 if (status)
6842 {
6843 info->memory_error_func (status, pc, info);
6844 return -1;
6845 }
6a56ec7e
NC		 6846 if (info->flags & INSN_HAS_RELOC)
6847 /* If the instruction has a reloc associated with it, then
6848 the offset field in the instruction will actually be the
6849 addend for the reloc. (We are using REL type relocs).
6850 In such cases, we can ignore the pc when computing
6851 addresses, since the addend is not currently pc-relative. */
6852 pc = 0;
b34976b6 6853
4a5329c6 6854 printer (pc, info, given);
c22aaad1
PB		 6855
6856 if (is_thumb)
6857 {
6858 ifthen_state = ifthen_next_state;
6859 ifthen_address += size;
6860 }
4a5329c6 6861 return size;
252b5132
RH		 6862}
6863
6864int
4a5329c6 6865print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 6866{
bd2e2557
SS		 6867 /* Detect BE8-ness and record it in the disassembler info. */
6868 if (info->flavour == bfd_target_elf_flavour
6869 && info->section != NULL
6870 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
6871 info->endian_code = BFD_ENDIAN_LITTLE;
6872
b34976b6 6873 return print_insn (pc, info, FALSE);
58efb6c0 6874}
01c7f630 6875
58efb6c0 6876int
4a5329c6 6877print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 6878{
b34976b6 6879 return print_insn (pc, info, TRUE);
58efb6c0 6880}
252b5132 6881
471b9d15 6882const disasm_options_and_args_t *
65b48a81
PB		 6883disassembler_options_arm (void)
6884{
471b9d15 6885 static disasm_options_and_args_t *opts_and_args;
65b48a81 6886
471b9d15 6887 if (opts_and_args == NULL)
65b48a81 6888 {
471b9d15 6889 disasm_options_t *opts;
65b48a81 6890 unsigned int i;
471b9d15
MR		 6891
6892 opts_and_args = XNEW (disasm_options_and_args_t);
6893 opts_and_args->args = NULL;
6894
6895 opts = &opts_and_args->options;
65b48a81
PB		 6896 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
6897 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
471b9d15 6898 opts->arg = NULL;
65b48a81
PB		 6899 for (i = 0; i < NUM_ARM_OPTIONS; i++)
6900 {
6901 opts->name[i] = regnames[i].name;
6902 if (regnames[i].description != NULL)
6903 opts->description[i] = _(regnames[i].description);
6904 else
6905 opts->description[i] = NULL;
6906 }
6907 /* The array we return must be NULL terminated. */
6908 opts->name[i] = NULL;
6909 opts->description[i] = NULL;
6910 }
6911
471b9d15 6912 return opts_and_args;
65b48a81
PB		 6913}
6914
58efb6c0 6915void
4a5329c6 6916print_arm_disassembler_options (FILE *stream)
58efb6c0 6917{
65b48a81 6918 unsigned int i, max_len = 0;
58efb6c0
NC		 6919 fprintf (stream, _("\n\
6920The following ARM specific disassembler options are supported for use with\n\
6921the -M switch:\n"));
b34976b6 6922
65b48a81
PB		 6923 for (i = 0; i < NUM_ARM_OPTIONS; i++)
6924 {
6925 unsigned int len = strlen (regnames[i].name);
6926 if (max_len < len)
6927 max_len = len;
6928 }
58efb6c0 6929
65b48a81
PB		 6930 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
6931 fprintf (stream, " %s%*c %s\n",
6932 regnames[i].name,
6933 (int)(max_len - strlen (regnames[i].name)), ' ',
6934 _(regnames[i].description));
252b5132 6935}
GDB Binutils - Deliverables
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