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[OPCODES][ARM]Fix mask for a few coprocessor opcodes.
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
CommitLineData
252b5132 1/* Instruction printing code for the ARM
6f2750fe 2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
2fbad815 24
252b5132 25#include "dis-asm.h"
2fbad815 26#include "opcode/arm.h"
252b5132 27#include "opintl.h"
31e0f3cd 28#include "safe-ctype.h"
0dbde4cf 29#include "floatformat.h"
252b5132 30
baf0cc5e 31/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 32#include "coff/internal.h"
33#include "libcoff.h"
252b5132
RH		 34#include "elf-bfd.h"
35#include "elf/internal.h"
36#include "elf/arm.h"
e49d43ff 37#include "mach-o.h"
252b5132 38
6b5d3a4d 39/* FIXME: Belongs in global header. */
01c7f630 40#ifndef strneq
58efb6c0
NC		 41#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
42#endif
43
44#ifndef NUM_ELEM
45#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
01c7f630
NC		 46#endif
47
1fbaefec
PB		 48/* Cached mapping symbol state. */
49enum map_type
50{
51 MAP_ARM,
52 MAP_THUMB,
53 MAP_DATA
54};
55
b0e28b39
DJ		 56struct arm_private_data
57{
58 /* The features to use when disassembling optional instructions. */
59 arm_feature_set features;
60
61 /* Whether any mapping symbols are present in the provided symbol
62 table. -1 if we do not know yet, otherwise 0 or 1. */
63 int has_mapping_symbols;
1fbaefec
PB		 64
65 /* Track the last type (although this doesn't seem to be useful) */
66 enum map_type last_type;
67
68 /* Tracking symbol table information */
69 int last_mapping_sym;
70 bfd_vma last_mapping_addr;
b0e28b39
DJ		 71};
72
6b5d3a4d
ZW		 73struct opcode32
74{
823d2571
TG		 75 arm_feature_set arch; /* Architecture defining this insn. */
76 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 77 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 78 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 79};
80
81struct opcode16
82{
823d2571 83 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 84 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 85 const char *assembler; /* How to disassemble this insn. */
86};
b7693d02 87
8f06b2d8 88/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 89
2fbad815 90 %% %
4a5329c6 91
c22aaad1 92 %c print condition code (always bits 28-31 in ARM mode)
37b37b2d 93 %q print shifter argument
e2efe87d
MGD		 94 %u print condition code (unconditional in ARM mode,
95 UNPREDICTABLE if not AL in Thumb)
4a5329c6 96 %A print address for ldc/stc/ldf/stf instruction
16980d0b 97 %B print vstm/vldm register list
4a5329c6 98 %I print cirrus signed shift immediate: bits 0..3|4..6
4a5329c6
ZW		 99 %F print the COUNT field of a LFM/SFM instruction.
100 %P print floating point precision in arithmetic insn
101 %Q print floating point precision in ldf/stf insn
102 %R print floating point rounding mode
103
33399f07 104 %<bitfield>c print as a condition code (for vsel)
4a5329c6 105 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 106 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
107 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 108 %<bitfield>d print the bitfield in decimal
16980d0b 109 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 110 %<bitfield>x print the bitfield in hex
111 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 112 %<bitfield>f print a floating point constant if >7 else a
113 floating point register
4a5329c6
ZW		 114 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
115 %<bitfield>g print as an iWMMXt 64-bit register
116 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 117 %<bitfield>D print as a NEON D register
118 %<bitfield>Q print as a NEON Q register
6f1c2142 119 %<bitfield>E print a quarter-float immediate value
4a5329c6 120
16980d0b 121 %y<code> print a single precision VFP reg.
2fbad815 122 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 123 %z<code> print a double precision VFP reg
2fbad815 124 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 125
16980d0b
JB		 126 %<bitfield>'c print specified char iff bitfield is all ones
127 %<bitfield>`c print specified char iff bitfield is all zeroes
128 %<bitfield>?ab... select from array of values in big endian order
43e65147 129
2fbad815 130 %L print as an iWMMXt N/M width field.
4a5329c6 131 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 132 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 133 versions.
134 %i print 5-bit immediate in bits 8,3..0
135 (print "32" when 0)
fe56b6ce 136 %r print register offset address for wldt/wstr instruction. */
2fbad815 137
21d799b5 138enum opcode_sentinel_enum
05413229
NC		 139{
140 SENTINEL_IWMMXT_START = 1,
141 SENTINEL_IWMMXT_END,
142 SENTINEL_GENERIC_START
143} opcode_sentinels;
144
aefd8a40 145#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
c1e26897 146#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 147
8f06b2d8 148/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 149
8f06b2d8 150static const struct opcode32 coprocessor_opcodes[] =
2fbad815 151{
2fbad815 152 /* XScale instructions. */
823d2571
TG		 153 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
154 0x0e200010, 0x0fff0ff0,
155 "mia%c\tacc0, %0-3r, %12-15r"},
156 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
157 0x0e280010, 0x0fff0ff0,
158 "miaph%c\tacc0, %0-3r, %12-15r"},
159 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
160 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
161 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
162 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
163 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
164 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 165
2fbad815 166 /* Intel Wireless MMX technology instructions. */
823d2571
TG		 167 {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
168 {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
169 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
170 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
171 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
172 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
173 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
174 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
175 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
176 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
177 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
178 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
179 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
180 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
181 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
182 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
183 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
184 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
185 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
186 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
187 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
188 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
189 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
190 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
191 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
192 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
193 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
194 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
195 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
196 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
197 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
198 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
199 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
200 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
201 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
202 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
203 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
204 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
205 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
206 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
207 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
208 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
209 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
210 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
211 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
212 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
213 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
214 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
215 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
216 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
217 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
218 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
219 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
220 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
221 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
222 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
223 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
224 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
225 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
226 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
227 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
228 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
229 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
230 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
231 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
232 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
233 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
234 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
235 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
236 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
237 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
238 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
239 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
240 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
241 0x0e800120, 0x0f800ff0,
242 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
243 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
244 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
245 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
246 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
247 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
248 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
249 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
250 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
251 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
252 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
253 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
254 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
255 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
256 0x0e8000a0, 0x0f800ff0,
257 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
258 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
259 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
260 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
261 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
262 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
263 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
264 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
265 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
266 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
267 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
268 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
269 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
270 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
271 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
272 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
273 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
274 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
275 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
276 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
277 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
278 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
279 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
280 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
281 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
282 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
283 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
284 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
285 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
286 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
287 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
288 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
289 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
290 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
291 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
292 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
293 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
294 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
295 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
296 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
297 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
298 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
299 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
300 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
301 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
302 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
303 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
304 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
305 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
306 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
307 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
308 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
309 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
310 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
311 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
312 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
313 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
314 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
315 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
316 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
317 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
318 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
319 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
320 {ARM_FEATURE_CORE_LOW (0),
321 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 322
fe56b6ce 323 /* Floating point coprocessor (FPA) instructions. */
823d2571
TG		 324 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
325 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
326 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
327 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
328 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
329 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
330 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
331 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
332 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
333 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
334 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
335 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
336 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
337 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
338 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
339 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
340 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
341 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
342 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
343 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
344 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
345 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
346 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
347 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
348 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
349 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
350 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
351 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
352 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
353 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
354 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
355 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
356 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
357 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
358 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
359 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
360 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
361 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
362 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
363 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
364 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
365 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
366 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
367 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
368 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
369 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
370 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
371 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
372 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
373 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
374 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
375 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
376 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
377 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
378 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
379 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
380 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
381 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
382 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
383 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
384 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
385 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
386 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
387 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
388 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
389 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
390 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
391 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
392 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
393 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
394 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
395 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
396 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
397 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
398 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
399 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
400 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
401 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
402 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
403 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
404 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
405 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
406 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
407 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
408 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
409 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 410
fe56b6ce 411 /* Register load/store. */
823d2571
TG		 412 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
413 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
414 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
415 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
416 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
417 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
418 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
419 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
420 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
421 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
422 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
423 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
424 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
425 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
426 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
427 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
428 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
429 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
430 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
431 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
432 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
433 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
434 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
435 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
436 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
437 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
438 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
439 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
440 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
441 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
442 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
443 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
444
445 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
446 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
447 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
448 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
449 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
450 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
451 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
452 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 453
fe56b6ce 454 /* Data transfer between ARM and NEON registers. */
823d2571
TG		 455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
456 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
457 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
458 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
459 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
460 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
462 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
464 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
466 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
468 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
470 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
472 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
474 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
476 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
478 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
480 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
482 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 483 /* Half-precision conversion instructions. */
823d2571
TG		 484 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
485 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
486 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
487 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
488 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
489 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
490 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
491 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 492
fe56b6ce 493 /* Floating point coprocessor (VFP) instructions. */
823d2571
TG		 494 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
495 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
496 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
497 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
498 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
499 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
500 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
501 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
502 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
503 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
504 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
505 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
506 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
507 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
508 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
509 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
510 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
511 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
512 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
513 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
514 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
515 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
516 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
517 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
518 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
519 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
520 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
521 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
522 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
523 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
524 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
525 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
526 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
527 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
528 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
529 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
530 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
531 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
532 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
533 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
534 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
535 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
536 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
537 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
538 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
539 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
540 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
541 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
542 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
543 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
544 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
545 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
546 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
547 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
548 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
549 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
550 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
551 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
552 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
553 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
554 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
555 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
556 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
557 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
558 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
559 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
560 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
561 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
562 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
563 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
564 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
565 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
566 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
567 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
568 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
569 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
570 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
571 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
572 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
573 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
574 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
575 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
576 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
577 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
578 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
579 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
580 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
581 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
582 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6f1c2142 583 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
823d2571 584 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6f1c2142 585 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
823d2571
TG		 586 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
587 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
588 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
589 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
590 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
591 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
592 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
593 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
594 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
595 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
596 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
597 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
598 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
599 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
600 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
601 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
602 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
603 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
604 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
605 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
606 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
607 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
608 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
609 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
610 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
611 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
612 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
613 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
614 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
615 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
616 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
617 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
618 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
619 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
620 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
621 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
622 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
623 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
624 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
625 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
626 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
627 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 628
629 /* Cirrus coprocessor instructions. */
823d2571
TG		 630 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
631 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
632 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
633 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
634 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
635 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
636 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
637 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
638 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
639 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
640 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
641 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
642 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
643 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
644 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
645 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
646 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
647 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
648 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
649 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
650 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
651 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
652 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
653 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
654 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
655 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
656 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
657 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
658 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
659 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
660 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
661 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
662 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
663 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
664 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
665 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
666 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
667 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
668 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
669 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
670 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
671 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
672 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
673 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
674 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
675 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
676 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
677 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
678 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
679 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
680 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
681 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
682 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
683 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
684 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
685 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
686 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
687 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
688 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
689 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
690 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
691 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
692 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
693 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
694 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
695 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
696 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
697 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
698 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
699 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
700 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
701 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
702 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
703 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
704 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
705 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
706 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
707 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
708 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
709 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
710 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
711 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
712 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
713 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
714 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
715 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
716 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
717 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
718 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
719 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
720 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
721 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
722 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
723 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
724 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
725 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
726 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
727 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
728 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
729 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
730 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
731 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
732 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
733 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
734 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
735 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
736 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
737 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
738 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
739 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
740 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
741 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
742 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
743 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
744 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
745 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
746 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
747 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
748 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
749 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
750 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
751 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
752 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
753 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
754 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
755 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
756 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
757 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
758 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
759 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
760 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
761 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
762 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
763 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
764 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
765 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
766 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
767 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
768 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
769 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
770 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
771 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
772 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
773 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
774 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
775 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
776 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
777 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
778 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
779 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
780 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
781 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
782 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
783 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
784 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
785 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
786 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
787 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
788 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
789 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
790 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
791 0x0e000600, 0x0ff00f10,
792 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
793 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
794 0x0e100600, 0x0ff00f10,
795 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
796 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
797 0x0e200600, 0x0ff00f10,
798 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
799 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
800 0x0e300600, 0x0ff00f10,
801 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 802
62f3b8c8 803 /* VFP Fused multiply add instructions. */
823d2571
TG		 804 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
805 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
806 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
807 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
808 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
809 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
810 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
811 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
812 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
813 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
814 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
815 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
816 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
817 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
818 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
819 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 820
33399f07 821 /* FP v5. */
823d2571 822 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 823 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
823d2571 824 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 825 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
823d2571 826 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 827 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
823d2571 828 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 829 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
823d2571 830 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 831 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
823d2571 832 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 833 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
823d2571
TG		 834 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
835 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
836 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
837 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
838 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
839 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
840 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
841 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
842 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 843 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
823d2571 844 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 845 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 846
05413229 847 /* Generic coprocessor instructions. */
823d2571
TG		 848 {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
850 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
852 0x0c500000, 0x0ff00000,
853 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
855 0x0e000000, 0x0f000010,
856 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
858 0x0e10f010, 0x0f10f010,
859 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
861 0x0e100010, 0x0f100010,
862 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
864 0x0e000010, 0x0f100010,
865 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
867 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
869 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
2fbad815 870
05413229 871 /* V6 coprocessor instructions. */
823d2571
TG		 872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
873 0xfc500000, 0xfff00000,
874 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
876 0xfc400000, 0xfff00000,
877 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
8f06b2d8 878
05413229 879 /* V5 coprocessor instructions. */
823d2571
TG		 880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
881 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
883 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
885 0xfe000000, 0xff000010,
886 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
888 0xfe000010, 0xff100010,
889 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
891 0xfe100010, 0xff100010,
892 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
893
894 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 895};
896
16980d0b
JB		 897/* Neon opcode table: This does not encode the top byte -- that is
898 checked by the print_insn_neon routine, as it depends on whether we are
899 doing thumb32 or arm32 disassembly. */
900
901/* print_insn_neon recognizes the following format control codes:
902
903 %% %
904
c22aaad1 905 %c print condition code
e2efe87d
MGD		 906 %u print condition code (unconditional in ARM mode,
907 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 908 %A print v{st,ld}[1234] operands
909 %B print v{st,ld}[1234] any one operands
910 %C print v{st,ld}[1234] single->all operands
911 %D print scalar
912 %E print vmov, vmvn, vorr, vbic encoded constant
913 %F print vtbl,vtbx register list
914
915 %<bitfield>r print as an ARM register
916 %<bitfield>d print the bitfield in decimal
917 %<bitfield>e print the 2^N - bitfield in decimal
918 %<bitfield>D print as a NEON D register
919 %<bitfield>Q print as a NEON Q register
920 %<bitfield>R print as a NEON D or Q register
921 %<bitfield>Sn print byte scaled width limited by n
922 %<bitfield>Tn print short scaled width limited by n
923 %<bitfield>Un print long scaled width limited by n
43e65147 924
16980d0b
JB		 925 %<bitfield>'c print specified char iff bitfield is all ones
926 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 927 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 928
929static const struct opcode32 neon_opcodes[] =
930{
fe56b6ce 931 /* Extract. */
823d2571
TG		 932 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
933 0xf2b00840, 0xffb00850,
934 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
935 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
936 0xf2b00000, 0xffb00810,
937 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 938
fe56b6ce 939 /* Move data element to all lanes. */
823d2571
TG		 940 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
941 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
942 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
943 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
944 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
945 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 946
fe56b6ce 947 /* Table lookup. */
823d2571
TG		 948 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
949 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
950 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
951 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
952
8e79c3df 953 /* Half-precision conversions. */
823d2571
TG		 954 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
955 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
956 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
957 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 958
959 /* NEON fused multiply add instructions. */
823d2571
TG		 960 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
961 0xf2000c10, 0xffa00f10, "vfma%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
962 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
963 0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 964
fe56b6ce 965 /* Two registers, miscellaneous. */
823d2571
TG		 966 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
967 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
968 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
969 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
970 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
971 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
972 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
973 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
974 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
975 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
976 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
977 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
978 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
979 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
980 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
981 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
982 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
983 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
984 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
985 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
986 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
987 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
988 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
989 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
990 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
991 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
992 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
993 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
994 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
995 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
996 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
997 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
998 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
999 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1000 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1001 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1002 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1003 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1004 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1005 0xf3b20300, 0xffb30fd0,
1006 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1007 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1008 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1009 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1010 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1011 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1012 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1013 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1014 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1015 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1016 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1017 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1018 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1019 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1020 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1021 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1022 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1023 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1024 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1025 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1026 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1027 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1028 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1029 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1030 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1031 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1032 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1033 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1034 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1035 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1036 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1037 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1038 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1039 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1040 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1041 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1042 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1043 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1044 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1045 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1046 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1047 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1048 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1049 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1050 0xf3b30600, 0xffb30e10,
1051 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
16980d0b 1052
fe56b6ce 1053 /* Three registers of the same length. */
823d2571
TG		 1054 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1055 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1056 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1057 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1058 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1059 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1060 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1061 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1062 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1063 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1064 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1065 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1066 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1067 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1068 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1069 0xf3000f10, 0xffa00f10, "vmaxnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1070 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1071 0xf3200f10, 0xffa00f10, "vminnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1072 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1073 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1074 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1075 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1076 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1077 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1078 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1079 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1080 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1081 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1082 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1083 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1084 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1085 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1086 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1087 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1088 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1089 0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1090 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1091 0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1092 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1093 0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1094 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1095 0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1096 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1097 0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1098 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1099 0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1100 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1101 0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1102 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1103 0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1104 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1105 0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1106 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1107 0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1108 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1109 0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1110 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1111 0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1112 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1113 0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1114 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1115 0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1116 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1117 0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1118 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1119 0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1120 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1121 0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1122 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1123 0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1124 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1125 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1126 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1127 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1128 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1129 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1130 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1131 0xf2000b00, 0xff800f10,
1132 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1133 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1134 0xf2000b10, 0xff800f10,
1135 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1136 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1137 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1138 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1139 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1140 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1141 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1142 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1143 0xf3000b00, 0xff800f10,
1144 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1145 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1146 0xf2000000, 0xfe800f10,
1147 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1148 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1149 0xf2000010, 0xfe800f10,
1150 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1151 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1152 0xf2000100, 0xfe800f10,
1153 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1154 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1155 0xf2000200, 0xfe800f10,
1156 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1157 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1158 0xf2000210, 0xfe800f10,
1159 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1160 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1161 0xf2000300, 0xfe800f10,
1162 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1163 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1164 0xf2000310, 0xfe800f10,
1165 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1166 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1167 0xf2000400, 0xfe800f10,
1168 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1169 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1170 0xf2000410, 0xfe800f10,
1171 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1172 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1173 0xf2000500, 0xfe800f10,
1174 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1175 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1176 0xf2000510, 0xfe800f10,
1177 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1178 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1179 0xf2000600, 0xfe800f10,
1180 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1181 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1182 0xf2000610, 0xfe800f10,
1183 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1184 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1185 0xf2000700, 0xfe800f10,
1186 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1187 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1188 0xf2000710, 0xfe800f10,
1189 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1190 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1191 0xf2000910, 0xfe800f10,
1192 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1193 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1194 0xf2000a00, 0xfe800f10,
1195 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1196 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1197 0xf2000a10, 0xfe800f10,
1198 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1199 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1200 0xf3000b10, 0xff800f10,
1201 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1202 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1203 0xf3000c10, 0xff800f10,
1204 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1205
fe56b6ce 1206 /* One register and an immediate value. */
823d2571
TG		 1207 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1208 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1209 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1210 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1211 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1212 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1213 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1214 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1215 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1216 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1217 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1218 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1219 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1220 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1221 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1222 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1223 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1224 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1225 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1226 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1227 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1228 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1229 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1230 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1231 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1232 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1233
fe56b6ce 1234 /* Two registers and a shift amount. */
823d2571
TG		 1235 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1236 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1237 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1238 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1239 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1240 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1241 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1242 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1243 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1244 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1245 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1246 0xf2880950, 0xfeb80fd0,
1247 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1248 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1249 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1250 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1251 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1252 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1253 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1254 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1255 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1256 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1257 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1258 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1259 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1260 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1261 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1262 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1263 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1264 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1265 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1266 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1267 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1268 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1269 0xf2900950, 0xfeb00fd0,
1270 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1271 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1272 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1273 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1274 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1275 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1276 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1277 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1278 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1279 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1280 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1281 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1282 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1283 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1284 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1285 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1286 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1287 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1288 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1289 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1290 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1291 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1292 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1293 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1294 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1295 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1296 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1297 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1298 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1299 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1300 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1301 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1302 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1303 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1304 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1305 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1306 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1307 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1308 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1309 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1310 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1311 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1312 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1313 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1314 0xf2a00950, 0xfea00fd0,
1315 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1316 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1317 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1318 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1319 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1320 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1321 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1322 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1323 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1324 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1325 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1326 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1327 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1328 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1329 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1330 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1331 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1332 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1333 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1334 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1335 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1336 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1337 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1338 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1339 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1340 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1341 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1342 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1343 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1344 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1345 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1346 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1347 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1348 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1349 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1350 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1351 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1352 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1353 0xf2a00e10, 0xfea00e90,
1354 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 1355
fe56b6ce 1356 /* Three registers of different lengths. */
823d2571
TG		 1357 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1358 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1359 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1360 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1361 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1362 0xf2800400, 0xff800f50,
1363 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1364 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1365 0xf2800600, 0xff800f50,
1366 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1367 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1368 0xf2800900, 0xff800f50,
1369 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1370 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1371 0xf2800b00, 0xff800f50,
1372 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1373 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1374 0xf2800d00, 0xff800f50,
1375 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1376 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1377 0xf3800400, 0xff800f50,
1378 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1379 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1380 0xf3800600, 0xff800f50,
1381 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1382 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1383 0xf2800000, 0xfe800f50,
1384 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1385 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1386 0xf2800100, 0xfe800f50,
1387 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1388 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1389 0xf2800200, 0xfe800f50,
1390 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1391 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1392 0xf2800300, 0xfe800f50,
1393 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1394 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1395 0xf2800500, 0xfe800f50,
1396 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1397 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1398 0xf2800700, 0xfe800f50,
1399 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1400 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1401 0xf2800800, 0xfe800f50,
1402 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1403 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1404 0xf2800a00, 0xfe800f50,
1405 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1406 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1407 0xf2800c00, 0xfe800f50,
1408 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 1409
fe56b6ce 1410 /* Two registers and a scalar. */
823d2571
TG		 1411 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1412 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1413 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1414 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1415 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1416 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1417 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1418 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1419 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1420 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1421 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1422 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1423 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1424 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1425 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1426 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1427 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1428 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1429 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1430 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1431 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1432 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1433 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1434 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1435 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1436 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1437 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1438 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1439 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1440 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1441 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1442 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1443 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1444 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1445 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1446 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1447 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1448 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1449 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1450 0xf2800240, 0xfe800f50,
1451 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1452 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1453 0xf2800640, 0xfe800f50,
1454 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1456 0xf2800a40, 0xfe800f50,
1457 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 1458 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1459 0xf2800e40, 0xff800f50,
1460 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1462 0xf2800f40, 0xff800f50,
1463 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1465 0xf3800e40, 0xff800f50,
1466 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1468 0xf3800f40, 0xff800f50,
1469 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1470 },
16980d0b 1471
fe56b6ce 1472 /* Element and structure load/store. */
823d2571
TG		 1473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1474 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1476 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1478 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1480 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1482 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1484 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1486 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1487 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1488 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1489 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1490 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1492 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1494 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1495 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1496 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1498 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1499 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1500 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1502 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1503 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1504 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1511
1512 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 1513};
1514
8f06b2d8
PB		 1515/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
1516 ordered: they must be searched linearly from the top to obtain a correct
1517 match. */
1518
1519/* print_insn_arm recognizes the following format control codes:
1520
1521 %% %
1522
1523 %a print address for ldr/str instruction
1524 %s print address for ldr/str halfword/signextend instruction
c1e26897 1525 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 1526 %b print branch destination
1527 %c print condition code (always bits 28-31)
1528 %m print register mask for ldm/stm instruction
1529 %o print operand2 (immediate or register + shift)
1530 %p print 'p' iff bits 12-15 are 15
1531 %t print 't' iff bit 21 set and bit 24 clear
1532 %B print arm BLX(1) destination
1533 %C print the PSR sub type.
62b3e311
PB		 1534 %U print barrier type.
1535 %P print address for pli instruction.
8f06b2d8
PB		 1536
1537 %<bitfield>r print as an ARM register
9eb6c0f1 1538 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 1539 %<bitfield>R as %r but r15 is UNPREDICTABLE
1540 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1541 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 1542 %<bitfield>d print the bitfield in decimal
43e65147 1543 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 1544 %<bitfield>x print the bitfield in hex
1545 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 1546
16980d0b
JB		 1547 %<bitfield>'c print specified char iff bitfield is all ones
1548 %<bitfield>`c print specified char iff bitfield is all zeroes
1549 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 1550
8f06b2d8
PB		 1551 %e print arm SMI operand (bits 0..7,8..19).
1552 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 1553 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
1554 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 1555
8f06b2d8
PB		 1556static const struct opcode32 arm_opcodes[] =
1557{
1558 /* ARM instructions. */
823d2571
TG		 1559 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1560 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1562 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1563
1564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
1565 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1567 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1569 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
1571 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1573 0x00800090, 0x0fa000f0,
1574 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1576 0x00a00090, 0x0fa000f0,
1577 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 1578
105bde57
MW		 1579 /* V8.2 RAS extension instructions. */
1580 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A),
1581 0xe320f010, 0xffffffff, "esb"},
1582
53c4b28b 1583 /* V8 instructions. */
823d2571
TG		 1584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1585 0x0320f005, 0x0fffffff, "sevl"},
1586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1587 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
4ed7ed8d 1588 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 1589 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1590 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 1591 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1593 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1595 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 1596 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1597 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1598 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1599 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1600 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1601 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1602 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1603 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1604 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1605 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1606 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1607 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1608 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1609 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1610 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1611 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1612 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1613 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1614 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 1615 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 1616 /* CRC32 instructions. */
823d2571
TG		 1617 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1618 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
1619 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1620 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
1621 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1622 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
1623 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1624 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
1625 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1626 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
1627 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1628 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 1629
ddfded2f
MW		 1630 /* Privileged Access Never extension instructions. */
1631 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
1632 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
1633
90ec0d68 1634 /* Virtualization Extension instructions. */
823d2571
TG		 1635 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
1636 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 1637
eea54501 1638 /* Integer Divide Extension instructions. */
823d2571
TG		 1639 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1640 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1641 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1642 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 1643
60e5ef9f 1644 /* MP Extension instructions. */
823d2571 1645 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 1646
62b3e311 1647 /* V7 instructions. */
823d2571
TG		 1648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
1649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
1651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
1652 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a
AV		 1655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
1656 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
62b3e311 1657
c19d1205 1658 /* ARM V6T2 instructions. */
823d2571
TG		 1659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1660 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1662 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1664 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1666 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
1667
1668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1669 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
1670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1671 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1672
ff8646ee 1673 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 1674 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 1675 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 1676 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1678 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1680 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 1681
f4c65163 1682 /* ARM Security extension instructions. */
823d2571
TG		 1683 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
1684 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 1685
8f06b2d8 1686 /* ARM V6K instructions. */
823d2571
TG		 1687 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1688 0xf57ff01f, 0xffffffff, "clrex"},
1689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1690 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1692 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1694 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1695 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1696 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1697 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1698 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1700 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 1701
8f06b2d8 1702 /* ARM V6K NOP hints. */
823d2571
TG		 1703 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1704 0x0320f001, 0x0fffffff, "yield%c"},
1705 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1706 0x0320f002, 0x0fffffff, "wfe%c"},
1707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1708 0x0320f003, 0x0fffffff, "wfi%c"},
1709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1710 0x0320f004, 0x0fffffff, "sev%c"},
1711 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1712 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 1713
fe56b6ce 1714 /* ARM V6 instructions. */
823d2571
TG		 1715 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1716 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
1717 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1718 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
1719 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1720 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
1721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1722 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
1723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1724 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
1725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1726 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
1727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1728 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
1729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1730 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
1731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1732 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
1733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1734 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
1735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1736 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
1737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1738 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
1739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1740 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
1741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1742 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
1743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1744 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
1745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1746 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
1747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1748 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
1749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1750 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
1751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1752 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
1753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1754 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
1755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1756 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
1757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1758 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
1759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1760 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
1761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1762 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
1763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1764 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
1765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1766 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
1767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1768 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
1769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1770 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
1771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1772 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
1773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1774 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
1775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1776 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
1777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1778 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
1779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1780 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
1781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1782 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
1783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1784 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
1785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1786 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
1787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1788 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
1789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1790 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
1791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1792 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
1793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1794 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
1795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1796 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
1797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1798 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
1799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1800 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
1801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1802 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
1803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1804 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
1805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1806 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
1807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1808 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
1809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1810 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
1811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1812 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
1813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1814 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
1815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1816 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
1817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1818 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
1819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1820 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
1821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1822 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
1823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1824 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
1825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1826 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
1827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1828 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
1829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1830 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
1831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1832 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
1833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1834 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
1835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1836 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
1837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1838 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
1839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1840 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
1841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1842 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
1843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1844 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
1845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1846 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
1847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1848 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
1849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1850 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
1851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1852 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
1853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1854 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
1855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1856 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
1857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1858 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
1859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1860 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
1861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1862 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
1863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1864 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
1865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1866 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1868 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1870 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1872 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
1873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1874 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1876 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1878 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1880 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
1881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1882 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1884 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1886 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1888 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
1889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1890 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1892 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1894 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1896 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
1897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1898 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1900 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1902 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
1903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1904 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
1905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1906 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1908 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1910 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1912 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
1913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1914 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
1915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1916 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
1917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1918 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
1919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1920 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1922 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1924 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1926 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1928 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
1929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1930 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1932 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1934 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
1935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1936 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
1937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1938 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
1939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1940 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
1941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1942 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
1943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1944 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
1945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1946 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
1947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1948 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
1949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1950 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1952 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
1953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1954 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
1955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1956 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
1957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1958 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 1959
8f06b2d8 1960 /* V5J instruction. */
823d2571
TG		 1961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
1962 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 1963
8f06b2d8 1964 /* V5 Instructions. */
823d2571
TG		 1965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1966 0xe1200070, 0xfff000f0,
1967 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
1968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1969 0xfa000000, 0xfe000000, "blx\t%B"},
1970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1971 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
1972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1973 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
1974
1975 /* V5E "El Segundo" Instructions. */
1976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1977 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
1978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1979 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
1980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1981 0xf450f000, 0xfc70f000, "pld\t%a"},
1982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1983 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1985 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1987 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1989 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
1990
1991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1992 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1994 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
1995
1996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1997 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1999 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2001 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2003 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2004
2005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2006 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2008 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2010 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2012 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2013
2014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2015 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2017 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2018
2019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2020 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
2021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2022 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2024 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
2025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2026 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 2027
8f06b2d8 2028 /* ARM Instructions. */
823d2571
TG		 2029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2030 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2031
2032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2033 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2035 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2037 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2039 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2041 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2043 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2044
2045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2046 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2048 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2050 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2052 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2053
2054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2055 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2057 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2059 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2061 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2062
2063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2064 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2066 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2068 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2069
2070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2071 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2073 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2075 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2076
2077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2078 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2080 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2082 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2083
2084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2085 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2087 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2089 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2090
2091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2092 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2094 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2096 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2097
2098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2099 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2101 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2103 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2104
2105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2106 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2108 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2110 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2111
2112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2113 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2115 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2117 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2118
2119 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2120 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2122 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2124 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2125
2126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2127 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2129 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2131 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2132
2133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2134 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 2135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2136 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 2137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a
AV		 2138 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
2139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2140 0x0130f000, 0x0ff0f010, "bx%c\t%0-3r"},
823d2571
TG		 2141
2142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2143 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2145 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2147 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2148
2149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2150 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2152 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2154 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2155
2156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2157 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2159 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2161 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2162
2163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2164 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2166 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2168 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2170 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2172 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2174 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2176 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2177
2178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2179 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2181 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2183 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2184
2185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2186 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2188 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2190 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2191
2192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2193 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2195 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2196
2197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2198 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2199
2200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2201 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2203 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2204
2205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2206 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2208 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2210 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2212 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2214 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2216 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2217 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2218 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2220 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2222 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2224 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2226 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2228 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2230 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2232 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2234 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2236 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2238 0x092d0000, 0x0fff0000, "push%c\t%m"},
2239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2240 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2242 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2243
2244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2245 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2247 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2249 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2251 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2252 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2253 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2255 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2257 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2259 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2261 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2263 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2265 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2266 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2267 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2269 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2271 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2273 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2275 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2277 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2279 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2281 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2282
2283 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2284 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2285 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2286 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 2287
2288 /* The rest. */
4ab90a7a
AV		 2289 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2290 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 2291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2292 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2293 {ARM_FEATURE_CORE_LOW (0),
2294 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 2295};
2296
2297/* print_insn_thumb16 recognizes the following format control codes:
2298
2299 %S print Thumb register (bits 3..5 as high number if bit 6 set)
2300 %D print Thumb register (bits 0..2 as high number if bit 7 set)
2301 %<bitfield>I print bitfield as a signed decimal
2302 (top bit of range being the sign bit)
2303 %N print Thumb register mask (with LR)
2304 %O print Thumb register mask (with PC)
2305 %M print Thumb register mask
2306 %b print CZB's 6-bit unsigned branch destination
2307 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 2308 %c print the condition code
2309 %C print the condition code, or "s" if not conditional
2310 %x print warning if conditional an not at end of IT block"
2311 %X print "\t; unpredictable <IT:code>" if conditional
2312 %I print IT instruction suffix and operands
4547cb56 2313 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 2314 %<bitfield>r print bitfield as an ARM register
2315 %<bitfield>d print bitfield as a decimal
2316 %<bitfield>H print (bitfield * 2) as a decimal
2317 %<bitfield>W print (bitfield * 4) as a decimal
2318 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
2319 %<bitfield>B print Thumb branch destination (signed displacement)
2320 %<bitfield>c print bitfield as a condition code
2321 %<bitnum>'c print specified char iff bit is one
2322 %<bitnum>?ab print a if bit is one else print b. */
2323
2324static const struct opcode16 thumb_opcodes[] =
2325{
2326 /* Thumb instructions. */
2327
53c4b28b 2328 /* ARM V8 instructions. */
823d2571
TG		 2329 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
2330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
ddfded2f 2331 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
53c4b28b 2332
8f06b2d8 2333 /* ARM V6K no-argument instructions. */
823d2571
TG		 2334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2339 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 2340
2341 /* ARM V6T2 instructions. */
ff8646ee
TP		 2342 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2343 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2344 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2345 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 2346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 2347
2348 /* ARM V6. */
823d2571
TG		 2349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 2360
2361 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 2362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2363 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 2364 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 2365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2366 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 2367 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 2368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2369 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 2370 /* Format 4. */
823d2571
TG		 2371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 2387 /* format 13 */
823d2571
TG		 2388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 2390 /* format 5 */
823d2571
TG		 2391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
2392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
2393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 2395 /* format 14 */
823d2571
TG		 2396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
2397 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 2398 /* format 2 */
823d2571
TG		 2399 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2400 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2401 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2402 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2403 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2404 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2406 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 2407 /* format 8 */
823d2571
TG		 2408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2409 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2411 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2413 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2414 /* format 7 */
823d2571
TG		 2415 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2416 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2418 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2419 /* format 1 */
823d2571
TG		 2420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2422 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 2425 /* format 3 */
823d2571
TG		 2426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2427 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2429 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 2430 /* format 6 */
823d2571
TG		 2431 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2433 0x4800, 0xF800,
2434 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 2435 /* format 9 */
823d2571
TG		 2436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2437 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2439 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2440 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2441 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2443 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 2444 /* format 10 */
823d2571
TG		 2445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2446 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2447 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2448 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 2449 /* format 11 */
823d2571
TG		 2450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2451 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2453 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 2454 /* format 12 */
823d2571
TG		 2455 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2456 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2457 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2458 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 2459 /* format 15 */
823d2571
TG		 2460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2461 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 2462 /* format 17 */
823d2571 2463 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 2464 /* format 16 */
823d2571
TG		 2465 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
2467 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 2468 /* format 18 */
823d2571 2469 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 2470
2471 /* The E800 .. FFFF range is unconditionally redirected to the
2472 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2473 are processed via that table. Thus, we can never encounter a
2474 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 2475 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
2476 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 2477};
2478
2479/* Thumb32 opcodes use the same table structure as the ARM opcodes.
2480 We adopt the convention that hw1 is the high 16 bits of .value and
2481 .mask, hw2 the low 16 bits.
2482
2483 print_insn_thumb32 recognizes the following format control codes:
2484
2485 %% %
2486
2487 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2488 %M print a modified 12-bit immediate (same location)
2489 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2490 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 2491 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 2492 %S print a possibly-shifted Rm
2493
32a94698 2494 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 2495 %a print the address of a plain load/store
2496 %w print the width and signedness of a core load/store
2497 %m print register mask for ldm/stm
2498
2499 %E print the lsb and width fields of a bfc/bfi instruction
2500 %F print the lsb and width fields of a sbfx/ubfx instruction
2501 %b print a conditional branch offset
2502 %B print an unconditional branch offset
2503 %s print the shift field of an SSAT instruction
2504 %R print the rotation field of an SXT instruction
62b3e311
PB		 2505 %U print barrier type.
2506 %P print address for pli instruction.
c22aaad1
PB		 2507 %c print the condition code
2508 %x print warning if conditional an not at end of IT block"
2509 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 2510
2511 %<bitfield>d print bitfield in decimal
f0fba320 2512 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 2513 %<bitfield>W print bitfield*4 in decimal
2514 %<bitfield>r print bitfield as an ARM register
dd5181d5
KT		 2515 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
2516 %<bitfield>S as %<>R but r13 is UNPREDICTABLE
8f06b2d8
PB		 2517 %<bitfield>c print bitfield as a condition code
2518
16980d0b
JB		 2519 %<bitfield>'c print specified char iff bitfield is all ones
2520 %<bitfield>`c print specified char iff bitfield is all zeroes
2521 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 2522
2523 With one exception at the bottom (done because BL and BLX(1) need
2524 to come dead last), this table was machine-sorted first in
2525 decreasing order of number of bits set in the mask, then in
2526 increasing numeric order of mask, then in increasing numeric order
2527 of opcode. This order is not the clearest for a human reader, but
2528 is guaranteed never to catch a special-case bit pattern with a more
2529 general mask, which is important, because this instruction encoding
2530 makes heavy use of special-case bit patterns. */
2531static const struct opcode32 thumb32_opcodes[] =
2532{
4ed7ed8d
TP		 2533 /* V8-M instructions. */
2534 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2535 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
2536 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2537 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
2538
105bde57
MW		 2539 /* ARM V8.2 RAS extension instructions. */
2540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A),
2541 0xf3af8010, 0xffffffff, "esb"},
2542
53c4b28b 2543 /* V8 instructions. */
823d2571
TG		 2544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2545 0xf3af8005, 0xffffffff, "sevl%c.w"},
2546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2547 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2549 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2551 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
2552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2553 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
2554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2555 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
2556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2557 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
2558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2559 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
2560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2561 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
2562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2563 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2565 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2567 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
2568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2569 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2571 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2573 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2575 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 2576
dd5181d5 2577 /* CRC32 instructions. */
823d2571
TG		 2578 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2579 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"},
2580 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2581 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"},
2582 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2583 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"},
2584 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2585 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"},
2586 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2587 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"},
2588 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2589 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"},
dd5181d5 2590
62b3e311 2591 /* V7 instructions. */
823d2571
TG		 2592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
2593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
2594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
2595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
2596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
2597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
2598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
2599 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2600 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
2601 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2602 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 2603
90ec0d68 2604 /* Virtualization Extension instructions. */
823d2571 2605 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 2606 /* We skip ERET as that is SUBS pc, lr, #0. */
2607
60e5ef9f 2608 /* MP Extension instructions. */
823d2571 2609 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 2610
f4c65163 2611 /* Security extension instructions. */
823d2571 2612 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 2613
8f06b2d8 2614 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 2615 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
2616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
2617 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2619 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
2620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2621 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
2622 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
2623
ff8646ee 2624 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2625 0xf3bf8f2f, 0xffffffff, "clrex%c"},
2626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2627 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
2628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2629 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
2630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2631 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
2632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2633 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
2634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2635 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
2636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2637 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
2638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2639 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
2640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2641 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
2642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2643 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
2644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2645 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
2646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2647 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
2648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2649 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
2650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2651 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 2652 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 2653 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 2654 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2655 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
2656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2657 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
2658 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2659 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
2660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2661 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
2662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2663 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
2664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2665 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
2666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2667 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
2668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2669 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
2670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2671 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 2672 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2673 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
2674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2675 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
2676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2677 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
2678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2679 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
2680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2681 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
2682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2683 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
2684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2685 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
2686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2687 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
2688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2689 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
2690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2691 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
2692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2693 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
2694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2695 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
2696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2697 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
2698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2699 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
2700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2701 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
2702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2703 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
2704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2705 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
2706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2707 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
2708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2709 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
2710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2711 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
2712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2713 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
2714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2715 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
2716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2717 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
2718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2719 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
2720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2721 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
2722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2723 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
2724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2725 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
2726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2727 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
2728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2729 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
2730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2731 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
2732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2733 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
2734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2735 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
2736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2737 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
2738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2739 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
2740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2741 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
2742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2743 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
2744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2745 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
2746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2747 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
2748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2749 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
2750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2751 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
2752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2753 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
2754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2755 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
2756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2757 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
2758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2759 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
2760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2761 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
2762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2763 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
2764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2765 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
2766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2767 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
2768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2769 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
2770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2771 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
2772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2773 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2775 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2777 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2779 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 2780 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2781 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
2782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 2783 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 2784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2785 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
2786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2787 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
2788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2789 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2791 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
2792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2793 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
2794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2795 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2797 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2799 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2801 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2803 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2805 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2807 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2809 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
2810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2811 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
2812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2813 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
2814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2815 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
2816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2817 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
2818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2819 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
2820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2821 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
2822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2823 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
2824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2825 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
2826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2827 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
2828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2829 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
2830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2831 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
2832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2833 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2835 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2837 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2839 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2841 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2843 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2845 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2847 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 2848 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2849 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
2850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2851 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
2852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2853 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
2854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2855 0xf810f000, 0xff70f000, "pld%c\t%a"},
2856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2857 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2859 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2861 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2863 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2865 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2867 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2869 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2871 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
2872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2873 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
2874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2875 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
2876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2877 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
2878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2879 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
2880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2881 0xfb100000, 0xfff000c0,
2882 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2884 0xfbc00080, 0xfff000c0,
2885 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
2886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2887 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
2888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2889 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
2890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 2891 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 2892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2893 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
2894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2895 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 2896 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2897 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
2898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2899 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 2900 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2901 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
2902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2903 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
2904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2905 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
2906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2907 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
2908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2909 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
2910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2911 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
2912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2913 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
2914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2915 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
2916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2917 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
2918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2919 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
2920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2921 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 2922 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2923 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
2924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2925 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
2926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2927 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
2928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2929 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
2930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2931 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
2932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2933 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
2934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2935 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
2936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2937 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
2938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2939 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
2940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2941 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
2942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2943 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
2944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2945 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
2946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2947 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
2948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2949 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
2950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2951 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
2952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2953 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
2954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2955 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
2956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2957 0xe9400000, 0xff500000,
2958 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
2959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2960 0xe9500000, 0xff500000,
2961 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
2962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2963 0xe8600000, 0xff700000,
2964 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
2965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2966 0xe8700000, 0xff700000,
2967 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
2968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2969 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
2970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2971 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 2972
2973 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 2974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2975 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
2976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2977 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
2978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2979 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
2980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2981 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 2982
8f06b2d8 2983 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 2984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2985 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
2986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2987 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 2988
2989 /* Fallback. */
823d2571
TG		 2990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2991 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2992 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 2993};
ff4a8d2b 2994
8f06b2d8
PB		 2995static const char *const arm_conditional[] =
2996{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 2997 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 2998
2999static const char *const arm_fp_const[] =
3000{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3001
3002static const char *const arm_shift[] =
3003{"lsl", "lsr", "asr", "ror"};
3004
3005typedef struct
3006{
3007 const char *name;
3008 const char *description;
3009 const char *reg_names[16];
3010}
3011arm_regname;
3012
3013static const arm_regname regnames[] =
3014{
3015 { "raw" , "Select raw register names",
3016 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
3017 { "gcc", "Select register names used by GCC",
3018 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
3019 { "std", "Select register names used in ARM's ISA documentation",
3020 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
3021 { "apcs", "Select register names used in the APCS",
3022 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
3023 { "atpcs", "Select register names used in the ATPCS",
3024 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
3025 { "special-atpcs", "Select special register names used in the ATPCS",
3026 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
3027};
3028
3029static const char *const iwmmxt_wwnames[] =
3030{"b", "h", "w", "d"};
3031
3032static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 3033{"b", "bus", "bc", "bss",
3034 "h", "hus", "hc", "hss",
3035 "w", "wus", "wc", "wss",
3036 "d", "dus", "dc", "dss"
8f06b2d8
PB		 3037};
3038
3039static const char *const iwmmxt_regnames[] =
3040{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3041 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3042};
3043
3044static const char *const iwmmxt_cregnames[] =
3045{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3046 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3047};
3048
3049/* Default to GCC register name set. */
3050static unsigned int regname_selected = 1;
3051
3052#define NUM_ARM_REGNAMES NUM_ELEM (regnames)
3053#define arm_regnames regnames[regname_selected].reg_names
3054
3055static bfd_boolean force_thumb = FALSE;
3056
c22aaad1
PB		 3057/* Current IT instruction state. This contains the same state as the IT
3058 bits in the CPSR. */
3059static unsigned int ifthen_state;
3060/* IT state for the next instruction. */
3061static unsigned int ifthen_next_state;
3062/* The address of the insn for which the IT state is valid. */
3063static bfd_vma ifthen_address;
3064#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 3065/* Indicates that the current Conditional state is unconditional or outside
3066 an IT block. */
3067#define COND_UNCOND 16
c22aaad1 3068
8f06b2d8
PB		 3069\f
3070/* Functions. */
3071int
3072get_arm_regname_num_options (void)
3073{
3074 return NUM_ARM_REGNAMES;
3075}
3076
3077int
3078set_arm_regname_option (int option)
3079{
3080 int old = regname_selected;
3081 regname_selected = option;
3082 return old;
3083}
3084
3085int
fe56b6ce
NC		 3086get_arm_regnames (int option,
3087 const char **setname,
3088 const char **setdescription,
8f06b2d8
PB		 3089 const char *const **register_names)
3090{
3091 *setname = regnames[option].name;
3092 *setdescription = regnames[option].description;
3093 *register_names = regnames[option].reg_names;
3094 return 16;
3095}
3096
16980d0b
JB		 3097/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3098 Returns pointer to following character of the format string and
3099 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 3100 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 3101
3102static const char *
fe56b6ce
NC		 3103arm_decode_bitfield (const char *ptr,
3104 unsigned long insn,
3105 unsigned long *valuep,
3106 int *widthp)
16980d0b
JB		 3107{
3108 unsigned long value = 0;
3109 int width = 0;
43e65147
L		 3110
3111 do
16980d0b
JB		 3112 {
3113 int start, end;
3114 int bits;
3115
3116 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3117 start = start * 10 + *ptr - '0';
3118 if (*ptr == '-')
3119 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3120 end = end * 10 + *ptr - '0';
3121 else
3122 end = start;
3123 bits = end - start;
3124 if (bits < 0)
3125 abort ();
3126 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3127 width += bits + 1;
3128 }
3129 while (*ptr++ == ',');
3130 *valuep = value;
3131 if (widthp)
3132 *widthp = width;
3133 return ptr - 1;
3134}
3135
8f06b2d8 3136static void
37b37b2d 3137arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 3138 bfd_boolean print_shift)
8f06b2d8
PB		 3139{
3140 func (stream, "%s", arm_regnames[given & 0xf]);
3141
3142 if ((given & 0xff0) != 0)
3143 {
3144 if ((given & 0x10) == 0)
3145 {
3146 int amount = (given & 0xf80) >> 7;
3147 int shift = (given & 0x60) >> 5;
3148
3149 if (amount == 0)
3150 {
3151 if (shift == 3)
3152 {
3153 func (stream, ", rrx");
3154 return;
3155 }
3156
3157 amount = 32;
3158 }
3159
37b37b2d
RE		 3160 if (print_shift)
3161 func (stream, ", %s #%d", arm_shift[shift], amount);
3162 else
3163 func (stream, ", #%d", amount);
8f06b2d8 3164 }
74bdfecf 3165 else if ((given & 0x80) == 0x80)
aefd8a40 3166 func (stream, "\t; <illegal shifter operand>");
37b37b2d 3167 else if (print_shift)
8f06b2d8
PB		 3168 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3169 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 3170 else
3171 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 3172 }
3173}
3174
c1e26897
NC		 3175#define W_BIT 21
3176#define I_BIT 22
3177#define U_BIT 23
3178#define P_BIT 24
3179
3180#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
3181#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
3182#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
3183#define PRE_BIT_SET (given & (1 << P_BIT))
3184
8f06b2d8
PB		 3185/* Print one coprocessor instruction on INFO->STREAM.
3186 Return TRUE if the instuction matched, FALSE if this is not a
3187 recognised coprocessor instruction. */
3188
3189static bfd_boolean
fe56b6ce
NC		 3190print_insn_coprocessor (bfd_vma pc,
3191 struct disassemble_info *info,
3192 long given,
8f06b2d8
PB		 3193 bfd_boolean thumb)
3194{
3195 const struct opcode32 *insn;
3196 void *stream = info->stream;
3197 fprintf_ftype func = info->fprintf_func;
3198 unsigned long mask;
2edcd244 3199 unsigned long value = 0;
c22aaad1 3200 int cond;
8afc7bea 3201 int cp_num;
823d2571
TG		 3202 struct arm_private_data *private_data = info->private_data;
3203 arm_feature_set allowed_arches = ARM_ARCH_NONE;
3204
3205 ARM_FEATURE_COPY (allowed_arches, private_data->features);
8f06b2d8
PB		 3206
3207 for (insn = coprocessor_opcodes; insn->assembler; insn++)
3208 {
ff4a8d2b
NC		 3209 unsigned long u_reg = 16;
3210 bfd_boolean is_unpredictable = FALSE;
05413229 3211 signed long value_in_comment = 0;
0313a2b8
NC		 3212 const char *c;
3213
823d2571 3214 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 3215 switch (insn->value)
3216 {
3217 case SENTINEL_IWMMXT_START:
3218 if (info->mach != bfd_mach_arm_XScale
3219 && info->mach != bfd_mach_arm_iWMMXt
3220 && info->mach != bfd_mach_arm_iWMMXt2)
3221 do
3222 insn++;
823d2571
TG		 3223 while ((! ARM_FEATURE_ZERO (insn->arch))
3224 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 3225 continue;
3226
3227 case SENTINEL_IWMMXT_END:
3228 continue;
3229
3230 case SENTINEL_GENERIC_START:
823d2571 3231 ARM_FEATURE_COPY (allowed_arches, private_data->features);
05413229
NC		 3232 continue;
3233
3234 default:
3235 abort ();
3236 }
8f06b2d8
PB		 3237
3238 mask = insn->mask;
3239 value = insn->value;
8afc7bea
RL		 3240 cp_num = (given >> 8) & 0xf;
3241
8f06b2d8
PB		 3242 if (thumb)
3243 {
3244 /* The high 4 bits are 0xe for Arm conditional instructions, and
3245 0xe for arm unconditional instructions. The rest of the
3246 encoding is the same. */
3247 mask |= 0xf0000000;
3248 value |= 0xe0000000;
c22aaad1
PB		 3249 if (ifthen_state)
3250 cond = IFTHEN_COND;
3251 else
e2efe87d 3252 cond = COND_UNCOND;
8f06b2d8
PB		 3253 }
3254 else
3255 {
3256 /* Only match unconditional instuctions against unconditional
3257 patterns. */
3258 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 3259 {
3260 mask |= 0xf0000000;
e2efe87d 3261 cond = COND_UNCOND;
c22aaad1
PB		 3262 }
3263 else
3264 {
3265 cond = (given >> 28) & 0xf;
3266 if (cond == 0xe)
e2efe87d 3267 cond = COND_UNCOND;
c22aaad1 3268 }
8f06b2d8 3269 }
823d2571 3270
0313a2b8
NC		 3271 if ((given & mask) != value)
3272 continue;
8f06b2d8 3273
823d2571 3274 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 3275 continue;
3276
8afc7bea
RL		 3277 if (insn->value == 0xfe000010 /* mcr2 */
3278 || insn->value == 0xfe100010 /* mrc2 */
3279 || insn->value == 0xfc100000 /* ldc2 */
3280 || insn->value == 0xfc000000) /* stc2 */
3281 {
3282 if (cp_num == 10 || cp_num == 11)
3283 is_unpredictable = TRUE;
3284 }
3285 else if (insn->value == 0x0e000000 /* cdp */
3286 || insn->value == 0xfe000000 /* cdp2 */
3287 || insn->value == 0x0e000010 /* mcr */
3288 || insn->value == 0x0e100010 /* mrc */
3289 || insn->value == 0x0c100000 /* ldc */
3290 || insn->value == 0x0c000000) /* stc */
3291 {
3292 /* Floating-point instructions. */
3293 if (cp_num == 10 || cp_num == 11)
3294 continue;
3295 }
3296
0313a2b8
NC		 3297 for (c = insn->assembler; *c; c++)
3298 {
3299 if (*c == '%')
8f06b2d8 3300 {
0313a2b8 3301 switch (*++c)
8f06b2d8 3302 {
0313a2b8
NC		 3303 case '%':
3304 func (stream, "%%");
3305 break;
3306
3307 case 'A':
05413229 3308 {
79862e45 3309 int rn = (given >> 16) & 0xf;
f8b960bc 3310 bfd_vma offset = given & 0xff;
0313a2b8 3311
05413229 3312 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 3313
79862e45
DJ		 3314 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
3315 {
3316 /* Not unindexed. The offset is scaled. */
3317 offset = offset * 4;
3318 if (NEGATIVE_BIT_SET)
3319 offset = - offset;
3320 if (rn != 15)
3321 value_in_comment = offset;
3322 }
3323
c1e26897 3324 if (PRE_BIT_SET)
05413229
NC		 3325 {
3326 if (offset)
fe56b6ce 3327 func (stream, ", #%d]%s",
d908c8af 3328 (int) offset,
c1e26897 3329 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 3330 else if (NEGATIVE_BIT_SET)
3331 func (stream, ", #-0]");
05413229
NC		 3332 else
3333 func (stream, "]");
3334 }
3335 else
3336 {
0313a2b8 3337 func (stream, "]");
8f06b2d8 3338
c1e26897 3339 if (WRITEBACK_BIT_SET)
05413229
NC		 3340 {
3341 if (offset)
d908c8af 3342 func (stream, ", #%d", (int) offset);
26d97720
NS		 3343 else if (NEGATIVE_BIT_SET)
3344 func (stream, ", #-0");
05413229
NC		 3345 }
3346 else
fe56b6ce 3347 {
26d97720
NS		 3348 func (stream, ", {%s%d}",
3349 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 3350 (int) offset);
fe56b6ce
NC		 3351 value_in_comment = offset;
3352 }
05413229 3353 }
79862e45
DJ		 3354 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
3355 {
3356 func (stream, "\t; ");
6844b2c2
MGD		 3357 /* For unaligned PCs, apply off-by-alignment
3358 correction. */
43e65147 3359 info->print_address_func (offset + pc
6844b2c2
MGD		 3360 + info->bytes_per_chunk * 2
3361 - (pc & 3),
3362 info);
79862e45 3363 }
05413229 3364 }
0313a2b8 3365 break;
8f06b2d8 3366
0313a2b8
NC		 3367 case 'B':
3368 {
3369 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
3370 int offset = (given >> 1) & 0x3f;
3371
3372 if (offset == 1)
3373 func (stream, "{d%d}", regno);
3374 else if (regno + offset > 32)
3375 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
3376 else
3377 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
3378 }
3379 break;
8f06b2d8 3380
e2efe87d
MGD		 3381 case 'u':
3382 if (cond != COND_UNCOND)
3383 is_unpredictable = TRUE;
3384
3385 /* Fall through. */
0313a2b8
NC		 3386 case 'c':
3387 func (stream, "%s", arm_conditional[cond]);
3388 break;
8f06b2d8 3389
0313a2b8
NC		 3390 case 'I':
3391 /* Print a Cirrus/DSP shift immediate. */
3392 /* Immediates are 7bit signed ints with bits 0..3 in
3393 bits 0..3 of opcode and bits 4..6 in bits 5..7
3394 of opcode. */
3395 {
3396 int imm;
8f06b2d8 3397
0313a2b8 3398 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 3399
0313a2b8
NC		 3400 /* Is ``imm'' a negative number? */
3401 if (imm & 0x40)
24b4cf66 3402 imm -= 0x80;
8f06b2d8 3403
0313a2b8
NC		 3404 func (stream, "%d", imm);
3405 }
3406
3407 break;
8f06b2d8 3408
0313a2b8
NC		 3409 case 'F':
3410 switch (given & 0x00408000)
3411 {
3412 case 0:
3413 func (stream, "4");
3414 break;
3415 case 0x8000:
3416 func (stream, "1");
3417 break;
3418 case 0x00400000:
3419 func (stream, "2");
8f06b2d8 3420 break;
0313a2b8
NC		 3421 default:
3422 func (stream, "3");
3423 }
3424 break;
8f06b2d8 3425
0313a2b8
NC		 3426 case 'P':
3427 switch (given & 0x00080080)
3428 {
3429 case 0:
3430 func (stream, "s");
3431 break;
3432 case 0x80:
3433 func (stream, "d");
3434 break;
3435 case 0x00080000:
3436 func (stream, "e");
3437 break;
3438 default:
3439 func (stream, _("<illegal precision>"));
8f06b2d8 3440 break;
0313a2b8
NC		 3441 }
3442 break;
8f06b2d8 3443
0313a2b8
NC		 3444 case 'Q':
3445 switch (given & 0x00408000)
3446 {
3447 case 0:
3448 func (stream, "s");
8f06b2d8 3449 break;
0313a2b8
NC		 3450 case 0x8000:
3451 func (stream, "d");
8f06b2d8 3452 break;
0313a2b8
NC		 3453 case 0x00400000:
3454 func (stream, "e");
3455 break;
3456 default:
3457 func (stream, "p");
8f06b2d8 3458 break;
0313a2b8
NC		 3459 }
3460 break;
8f06b2d8 3461
0313a2b8
NC		 3462 case 'R':
3463 switch (given & 0x60)
3464 {
3465 case 0:
3466 break;
3467 case 0x20:
3468 func (stream, "p");
3469 break;
3470 case 0x40:
3471 func (stream, "m");
3472 break;
3473 default:
3474 func (stream, "z");
3475 break;
3476 }
3477 break;
16980d0b 3478
0313a2b8
NC		 3479 case '0': case '1': case '2': case '3': case '4':
3480 case '5': case '6': case '7': case '8': case '9':
3481 {
3482 int width;
8f06b2d8 3483
0313a2b8 3484 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 3485
0313a2b8
NC		 3486 switch (*c)
3487 {
ff4a8d2b
NC		 3488 case 'R':
3489 if (value == 15)
3490 is_unpredictable = TRUE;
3491 /* Fall through. */
0313a2b8 3492 case 'r':
ff4a8d2b
NC		 3493 if (c[1] == 'u')
3494 {
3495 /* Eat the 'u' character. */
3496 ++ c;
3497
3498 if (u_reg == value)
3499 is_unpredictable = TRUE;
3500 u_reg = value;
3501 }
0313a2b8
NC		 3502 func (stream, "%s", arm_regnames[value]);
3503 break;
3504 case 'D':
3505 func (stream, "d%ld", value);
3506 break;
3507 case 'Q':
3508 if (value & 1)
3509 func (stream, "<illegal reg q%ld.5>", value >> 1);
3510 else
3511 func (stream, "q%ld", value >> 1);
3512 break;
3513 case 'd':
3514 func (stream, "%ld", value);
05413229 3515 value_in_comment = value;
0313a2b8 3516 break;
6f1c2142
AM		 3517 case 'E':
3518 {
3519 /* Converts immediate 8 bit back to float value. */
3520 unsigned floatVal = (value & 0x80) << 24
3521 | (value & 0x3F) << 19
3522 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
3523
3524 /* Quarter float have a maximum value of 31.0.
3525 Get floating point value multiplied by 1e7.
3526 The maximum value stays in limit of a 32-bit int. */
3527 unsigned decVal =
3528 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
3529 (16 + (value & 0xF));
3530
3531 if (!(decVal % 1000000))
3532 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
3533 floatVal, value & 0x80 ? '-' : ' ',
3534 decVal / 10000000,
3535 decVal % 10000000 / 1000000);
3536 else if (!(decVal % 10000))
3537 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
3538 floatVal, value & 0x80 ? '-' : ' ',
3539 decVal / 10000000,
3540 decVal % 10000000 / 10000);
3541 else
3542 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
3543 floatVal, value & 0x80 ? '-' : ' ',
3544 decVal / 10000000, decVal % 10000000);
3545 break;
3546 }
0313a2b8
NC		 3547 case 'k':
3548 {
3549 int from = (given & (1 << 7)) ? 32 : 16;
3550 func (stream, "%ld", from - value);
3551 }
3552 break;
8f06b2d8 3553
0313a2b8
NC		 3554 case 'f':
3555 if (value > 7)
3556 func (stream, "#%s", arm_fp_const[value & 7]);
3557 else
3558 func (stream, "f%ld", value);
3559 break;
4146fd53 3560
0313a2b8
NC		 3561 case 'w':
3562 if (width == 2)
3563 func (stream, "%s", iwmmxt_wwnames[value]);
3564 else
3565 func (stream, "%s", iwmmxt_wwssnames[value]);
3566 break;
4146fd53 3567
0313a2b8
NC		 3568 case 'g':
3569 func (stream, "%s", iwmmxt_regnames[value]);
3570 break;
3571 case 'G':
3572 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 3573 break;
8f06b2d8 3574
0313a2b8 3575 case 'x':
d1aaab3c 3576 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 3577 break;
8f06b2d8 3578
33399f07
MGD		 3579 case 'c':
3580 switch (value)
3581 {
3582 case 0:
3583 func (stream, "eq");
3584 break;
3585
3586 case 1:
3587 func (stream, "vs");
3588 break;
3589
3590 case 2:
3591 func (stream, "ge");
3592 break;
3593
3594 case 3:
3595 func (stream, "gt");
3596 break;
3597
3598 default:
3599 func (stream, "??");
3600 break;
3601 }
3602 break;
3603
0313a2b8
NC		 3604 case '`':
3605 c++;
3606 if (value == 0)
3607 func (stream, "%c", *c);
3608 break;
3609 case '\'':
3610 c++;
3611 if (value == ((1ul << width) - 1))
3612 func (stream, "%c", *c);
3613 break;
3614 case '?':
fe56b6ce 3615 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 3616 c += 1 << width;
3617 break;
3618 default:
3619 abort ();
3620 }
3621 break;
8f06b2d8 3622
0313a2b8
NC		 3623 case 'y':
3624 case 'z':
3625 {
3626 int single = *c++ == 'y';
3627 int regno;
3628
3629 switch (*c)
3630 {
3631 case '4': /* Sm pair */
3632 case '0': /* Sm, Dm */
3633 regno = given & 0x0000000f;
3634 if (single)
3635 {
3636 regno <<= 1;
3637 regno += (given >> 5) & 1;
16980d0b 3638 }
0313a2b8
NC		 3639 else
3640 regno += ((given >> 5) & 1) << 4;
3641 break;
8f06b2d8 3642
0313a2b8
NC		 3643 case '1': /* Sd, Dd */
3644 regno = (given >> 12) & 0x0000000f;
3645 if (single)
3646 {
3647 regno <<= 1;
3648 regno += (given >> 22) & 1;
3649 }
3650 else
3651 regno += ((given >> 22) & 1) << 4;
3652 break;
8f06b2d8 3653
0313a2b8
NC		 3654 case '2': /* Sn, Dn */
3655 regno = (given >> 16) & 0x0000000f;
3656 if (single)
8f06b2d8 3657 {
0313a2b8
NC		 3658 regno <<= 1;
3659 regno += (given >> 7) & 1;
8f06b2d8 3660 }
0313a2b8
NC		 3661 else
3662 regno += ((given >> 7) & 1) << 4;
3663 break;
7df76b80 3664
0313a2b8
NC		 3665 case '3': /* List */
3666 func (stream, "{");
3667 regno = (given >> 12) & 0x0000000f;
3668 if (single)
3669 {
3670 regno <<= 1;
3671 regno += (given >> 22) & 1;
3672 }
3673 else
3674 regno += ((given >> 22) & 1) << 4;
3675 break;
a7f8487e 3676
0313a2b8
NC		 3677 default:
3678 abort ();
8f06b2d8 3679 }
a7f8487e 3680
0313a2b8
NC		 3681 func (stream, "%c%d", single ? 's' : 'd', regno);
3682
3683 if (*c == '3')
8f06b2d8 3684 {
0313a2b8 3685 int count = given & 0xff;
a7f8487e 3686
0313a2b8
NC		 3687 if (single == 0)
3688 count >>= 1;
b34976b6 3689
0313a2b8 3690 if (--count)
8f06b2d8 3691 {
0313a2b8
NC		 3692 func (stream, "-%c%d",
3693 single ? 's' : 'd',
3694 regno + count);
8f06b2d8 3695 }
0313a2b8
NC		 3696
3697 func (stream, "}");
8f06b2d8 3698 }
0313a2b8
NC		 3699 else if (*c == '4')
3700 func (stream, ", %c%d", single ? 's' : 'd',
3701 regno + 1);
3702 }
3703 break;
3704
3705 case 'L':
3706 switch (given & 0x00400100)
3707 {
3708 case 0x00000000: func (stream, "b"); break;
3709 case 0x00400000: func (stream, "h"); break;
3710 case 0x00000100: func (stream, "w"); break;
3711 case 0x00400100: func (stream, "d"); break;
3712 default:
8f06b2d8 3713 break;
0313a2b8
NC		 3714 }
3715 break;
b34976b6 3716
0313a2b8
NC		 3717 case 'Z':
3718 {
0313a2b8
NC		 3719 /* given (20, 23) | given (0, 3) */
3720 value = ((given >> 16) & 0xf0) | (given & 0xf);
d908c8af 3721 func (stream, "%d", (int) value);
0313a2b8
NC		 3722 }
3723 break;
2d447fca 3724
0313a2b8
NC		 3725 case 'l':
3726 /* This is like the 'A' operator, except that if
3727 the width field "M" is zero, then the offset is
3728 *not* multiplied by four. */
3729 {
3730 int offset = given & 0xff;
3731 int multiplier = (given & 0x00000100) ? 4 : 1;
3732
3733 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3734
05413229
NC		 3735 if (multiplier > 1)
3736 {
3737 value_in_comment = offset * multiplier;
c1e26897 3738 if (NEGATIVE_BIT_SET)
05413229
NC		 3739 value_in_comment = - value_in_comment;
3740 }
3741
0313a2b8
NC		 3742 if (offset)
3743 {
c1e26897 3744 if (PRE_BIT_SET)
0313a2b8 3745 func (stream, ", #%s%d]%s",
c1e26897 3746 NEGATIVE_BIT_SET ? "-" : "",
0313a2b8 3747 offset * multiplier,
c1e26897 3748 WRITEBACK_BIT_SET ? "!" : "");
0313a2b8
NC		 3749 else
3750 func (stream, "], #%s%d",
c1e26897 3751 NEGATIVE_BIT_SET ? "-" : "",
0313a2b8 3752 offset * multiplier);
2d447fca 3753 }
0313a2b8
NC		 3754 else
3755 func (stream, "]");
3756 }
3757 break;
3758
3759 case 'r':
3760 {
3761 int imm4 = (given >> 4) & 0xf;
c1e26897
NC		 3762 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
3763 int ubit = ! NEGATIVE_BIT_SET;
0313a2b8
NC		 3764 const char *rm = arm_regnames [given & 0xf];
3765 const char *rn = arm_regnames [(given >> 16) & 0xf];
2d447fca 3766
0313a2b8 3767 switch (puw_bits)
2d447fca 3768 {
0313a2b8
NC		 3769 case 1:
3770 case 3:
3771 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
3772 if (imm4)
3773 func (stream, ", lsl #%d", imm4);
3774 break;
3775
3776 case 4:
3777 case 5:
3778 case 6:
3779 case 7:
3780 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
3781 if (imm4 > 0)
3782 func (stream, ", lsl #%d", imm4);
3783 func (stream, "]");
3784 if (puw_bits == 5 || puw_bits == 7)
3785 func (stream, "!");
3786 break;
3787
3788 default:
3789 func (stream, "INVALID");
2d447fca 3790 }
0313a2b8
NC		 3791 }
3792 break;
2d447fca 3793
0313a2b8
NC		 3794 case 'i':
3795 {
3796 long imm5;
3797 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
3798 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
8f06b2d8 3799 }
0313a2b8
NC		 3800 break;
3801
3802 default:
3803 abort ();
3804 }
252b5132 3805 }
252b5132 3806 }
0313a2b8
NC		 3807 else
3808 func (stream, "%c", *c);
252b5132 3809 }
05413229
NC		 3810
3811 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 3812 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 3813
ff4a8d2b
NC		 3814 if (is_unpredictable)
3815 func (stream, UNPREDICTABLE_INSTRUCTION);
3816
0313a2b8 3817 return TRUE;
252b5132 3818 }
8f06b2d8 3819 return FALSE;
252b5132
RH		 3820}
3821
05413229
NC		 3822/* Decodes and prints ARM addressing modes. Returns the offset
3823 used in the address, if any, if it is worthwhile printing the
3824 offset as a hexadecimal value in a comment at the end of the
3825 line of disassembly. */
3826
3827static signed long
62b3e311
PB		 3828print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
3829{
3830 void *stream = info->stream;
3831 fprintf_ftype func = info->fprintf_func;
f8b960bc 3832 bfd_vma offset = 0;
62b3e311
PB		 3833
3834 if (((given & 0x000f0000) == 0x000f0000)
3835 && ((given & 0x02000000) == 0))
3836 {
05413229 3837 offset = given & 0xfff;
62b3e311
PB		 3838
3839 func (stream, "[pc");
3840
c1e26897 3841 if (PRE_BIT_SET)
62b3e311 3842 {
26d97720
NS		 3843 /* Pre-indexed. Elide offset of positive zero when
3844 non-writeback. */
3845 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 3846 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 3847
3848 if (NEGATIVE_BIT_SET)
3849 offset = -offset;
62b3e311
PB		 3850
3851 offset += pc + 8;
3852
3853 /* Cope with the possibility of write-back
3854 being used. Probably a very dangerous thing
3855 for the programmer to do, but who are we to
3856 argue ? */
26d97720 3857 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 3858 }
c1e26897 3859 else /* Post indexed. */
62b3e311 3860 {
d908c8af 3861 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 3862
c1e26897 3863 /* Ie ignore the offset. */
62b3e311
PB		 3864 offset = pc + 8;
3865 }
3866
3867 func (stream, "\t; ");
3868 info->print_address_func (offset, info);
05413229 3869 offset = 0;
62b3e311
PB		 3870 }
3871 else
3872 {
3873 func (stream, "[%s",
3874 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 3875
3876 if (PRE_BIT_SET)
62b3e311
PB		 3877 {
3878 if ((given & 0x02000000) == 0)
3879 {
26d97720 3880 /* Elide offset of positive zero when non-writeback. */
05413229 3881 offset = given & 0xfff;
26d97720 3882 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 3883 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 3884 }
3885 else
3886 {
26d97720 3887 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 3888 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 3889 }
3890
3891 func (stream, "]%s",
c1e26897 3892 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 3893 }
3894 else
3895 {
3896 if ((given & 0x02000000) == 0)
3897 {
26d97720 3898 /* Always show offset. */
05413229 3899 offset = given & 0xfff;
26d97720 3900 func (stream, "], #%s%d",
d908c8af 3901 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 3902 }
3903 else
3904 {
3905 func (stream, "], %s",
c1e26897 3906 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 3907 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 3908 }
3909 }
84919466
MR		 3910 if (NEGATIVE_BIT_SET)
3911 offset = -offset;
62b3e311 3912 }
05413229
NC		 3913
3914 return (signed long) offset;
62b3e311
PB		 3915}
3916
16980d0b
JB		 3917/* Print one neon instruction on INFO->STREAM.
3918 Return TRUE if the instuction matched, FALSE if this is not a
3919 recognised neon instruction. */
3920
3921static bfd_boolean
3922print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
3923{
3924 const struct opcode32 *insn;
3925 void *stream = info->stream;
3926 fprintf_ftype func = info->fprintf_func;
3927
3928 if (thumb)
3929 {
3930 if ((given & 0xef000000) == 0xef000000)
3931 {
0313a2b8 3932 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 3933 unsigned long bit28 = given & (1 << 28);
3934
3935 given &= 0x00ffffff;
3936 if (bit28)
3937 given |= 0xf3000000;
3938 else
3939 given |= 0xf2000000;
3940 }
3941 else if ((given & 0xff000000) == 0xf9000000)
3942 given ^= 0xf9000000 ^ 0xf4000000;
3943 else
3944 return FALSE;
3945 }
43e65147 3946
16980d0b
JB		 3947 for (insn = neon_opcodes; insn->assembler; insn++)
3948 {
3949 if ((given & insn->mask) == insn->value)
3950 {
05413229 3951 signed long value_in_comment = 0;
e2efe87d 3952 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 3953 const char *c;
3954
3955 for (c = insn->assembler; *c; c++)
3956 {
3957 if (*c == '%')
3958 {
3959 switch (*++c)
3960 {
3961 case '%':
3962 func (stream, "%%");
3963 break;
3964
e2efe87d
MGD		 3965 case 'u':
3966 if (thumb && ifthen_state)
3967 is_unpredictable = TRUE;
3968
3969 /* Fall through. */
c22aaad1
PB		 3970 case 'c':
3971 if (thumb && ifthen_state)
3972 func (stream, "%s", arm_conditional[IFTHEN_COND]);
3973 break;
3974
16980d0b
JB		 3975 case 'A':
3976 {
43e65147 3977 static const unsigned char enc[16] =
16980d0b
JB		 3978 {
3979 0x4, 0x14, /* st4 0,1 */
3980 0x4, /* st1 2 */
3981 0x4, /* st2 3 */
3982 0x3, /* st3 4 */
3983 0x13, /* st3 5 */
3984 0x3, /* st1 6 */
3985 0x1, /* st1 7 */
3986 0x2, /* st2 8 */
3987 0x12, /* st2 9 */
3988 0x2, /* st1 10 */
3989 0, 0, 0, 0, 0
3990 };
3991 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
3992 int rn = ((given >> 16) & 0xf);
3993 int rm = ((given >> 0) & 0xf);
3994 int align = ((given >> 4) & 0x3);
3995 int type = ((given >> 8) & 0xf);
3996 int n = enc[type] & 0xf;
3997 int stride = (enc[type] >> 4) + 1;
3998 int ix;
43e65147 3999
16980d0b
JB		 4000 func (stream, "{");
4001 if (stride > 1)
4002 for (ix = 0; ix != n; ix++)
4003 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
4004 else if (n == 1)
4005 func (stream, "d%d", rd);
4006 else
4007 func (stream, "d%d-d%d", rd, rd + n - 1);
4008 func (stream, "}, [%s", arm_regnames[rn]);
4009 if (align)
8e560766 4010 func (stream, " :%d", 32 << align);
16980d0b
JB		 4011 func (stream, "]");
4012 if (rm == 0xd)
4013 func (stream, "!");
4014 else if (rm != 0xf)
4015 func (stream, ", %s", arm_regnames[rm]);
4016 }
4017 break;
43e65147 4018
16980d0b
JB		 4019 case 'B':
4020 {
4021 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4022 int rn = ((given >> 16) & 0xf);
4023 int rm = ((given >> 0) & 0xf);
4024 int idx_align = ((given >> 4) & 0xf);
4025 int align = 0;
4026 int size = ((given >> 10) & 0x3);
4027 int idx = idx_align >> (size + 1);
4028 int length = ((given >> 8) & 3) + 1;
4029 int stride = 1;
4030 int i;
4031
4032 if (length > 1 && size > 0)
4033 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 4034
16980d0b
JB		 4035 switch (length)
4036 {
4037 case 1:
4038 {
4039 int amask = (1 << size) - 1;
4040 if ((idx_align & (1 << size)) != 0)
4041 return FALSE;
4042 if (size > 0)
4043 {
4044 if ((idx_align & amask) == amask)
4045 align = 8 << size;
4046 else if ((idx_align & amask) != 0)
4047 return FALSE;
4048 }
4049 }
4050 break;
43e65147 4051
16980d0b
JB		 4052 case 2:
4053 if (size == 2 && (idx_align & 2) != 0)
4054 return FALSE;
4055 align = (idx_align & 1) ? 16 << size : 0;
4056 break;
43e65147 4057
16980d0b
JB		 4058 case 3:
4059 if ((size == 2 && (idx_align & 3) != 0)
4060 || (idx_align & 1) != 0)
4061 return FALSE;
4062 break;
43e65147 4063
16980d0b
JB		 4064 case 4:
4065 if (size == 2)
4066 {
4067 if ((idx_align & 3) == 3)
4068 return FALSE;
4069 align = (idx_align & 3) * 64;
4070 }
4071 else
4072 align = (idx_align & 1) ? 32 << size : 0;
4073 break;
43e65147 4074
16980d0b
JB		 4075 default:
4076 abort ();
4077 }
43e65147 4078
16980d0b
JB		 4079 func (stream, "{");
4080 for (i = 0; i < length; i++)
4081 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
4082 rd + i * stride, idx);
4083 func (stream, "}, [%s", arm_regnames[rn]);
4084 if (align)
8e560766 4085 func (stream, " :%d", align);
16980d0b
JB		 4086 func (stream, "]");
4087 if (rm == 0xd)
4088 func (stream, "!");
4089 else if (rm != 0xf)
4090 func (stream, ", %s", arm_regnames[rm]);
4091 }
4092 break;
43e65147 4093
16980d0b
JB		 4094 case 'C':
4095 {
4096 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4097 int rn = ((given >> 16) & 0xf);
4098 int rm = ((given >> 0) & 0xf);
4099 int align = ((given >> 4) & 0x1);
4100 int size = ((given >> 6) & 0x3);
4101 int type = ((given >> 8) & 0x3);
4102 int n = type + 1;
4103 int stride = ((given >> 5) & 0x1);
4104 int ix;
43e65147 4105
16980d0b
JB		 4106 if (stride && (n == 1))
4107 n++;
4108 else
4109 stride++;
43e65147 4110
16980d0b
JB		 4111 func (stream, "{");
4112 if (stride > 1)
4113 for (ix = 0; ix != n; ix++)
4114 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
4115 else if (n == 1)
4116 func (stream, "d%d[]", rd);
4117 else
4118 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
4119 func (stream, "}, [%s", arm_regnames[rn]);
4120 if (align)
4121 {
91d6fa6a 4122 align = (8 * (type + 1)) << size;
16980d0b
JB		 4123 if (type == 3)
4124 align = (size > 1) ? align >> 1 : align;
4125 if (type == 2 || (type == 0 && !size))
8e560766 4126 func (stream, " :<bad align %d>", align);
16980d0b 4127 else
8e560766 4128 func (stream, " :%d", align);
16980d0b
JB		 4129 }
4130 func (stream, "]");
4131 if (rm == 0xd)
4132 func (stream, "!");
4133 else if (rm != 0xf)
4134 func (stream, ", %s", arm_regnames[rm]);
4135 }
4136 break;
43e65147 4137
16980d0b
JB		 4138 case 'D':
4139 {
4140 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
4141 int size = (given >> 20) & 3;
4142 int reg = raw_reg & ((4 << size) - 1);
4143 int ix = raw_reg >> size >> 2;
43e65147 4144
16980d0b
JB		 4145 func (stream, "d%d[%d]", reg, ix);
4146 }
4147 break;
43e65147 4148
16980d0b 4149 case 'E':
fe56b6ce 4150 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 4151 {
4152 int bits = 0;
4153 int cmode = (given >> 8) & 0xf;
4154 int op = (given >> 5) & 0x1;
4155 unsigned long value = 0, hival = 0;
4156 unsigned shift;
4157 int size = 0;
0dbde4cf 4158 int isfloat = 0;
43e65147 4159
16980d0b
JB		 4160 bits |= ((given >> 24) & 1) << 7;
4161 bits |= ((given >> 16) & 7) << 4;
4162 bits |= ((given >> 0) & 15) << 0;
43e65147 4163
16980d0b
JB		 4164 if (cmode < 8)
4165 {
4166 shift = (cmode >> 1) & 3;
fe56b6ce 4167 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4168 size = 32;
4169 }
4170 else if (cmode < 12)
4171 {
4172 shift = (cmode >> 1) & 1;
fe56b6ce 4173 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4174 size = 16;
4175 }
4176 else if (cmode < 14)
4177 {
4178 shift = (cmode & 1) + 1;
fe56b6ce 4179 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4180 value |= (1ul << (8 * shift)) - 1;
4181 size = 32;
4182 }
4183 else if (cmode == 14)
4184 {
4185 if (op)
4186 {
fe56b6ce 4187 /* Bit replication into bytes. */
16980d0b
JB		 4188 int ix;
4189 unsigned long mask;
43e65147 4190
16980d0b
JB		 4191 value = 0;
4192 hival = 0;
4193 for (ix = 7; ix >= 0; ix--)
4194 {
4195 mask = ((bits >> ix) & 1) ? 0xff : 0;
4196 if (ix <= 3)
4197 value = (value << 8) | mask;
4198 else
4199 hival = (hival << 8) | mask;
4200 }
4201 size = 64;
4202 }
4203 else
4204 {
fe56b6ce
NC		 4205 /* Byte replication. */
4206 value = (unsigned long) bits;
16980d0b
JB		 4207 size = 8;
4208 }
4209 }
4210 else if (!op)
4211 {
fe56b6ce 4212 /* Floating point encoding. */
16980d0b 4213 int tmp;
43e65147 4214
fe56b6ce
NC		 4215 value = (unsigned long) (bits & 0x7f) << 19;
4216 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 4217 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 4218 value |= (unsigned long) tmp << 24;
16980d0b 4219 size = 32;
0dbde4cf 4220 isfloat = 1;
16980d0b
JB		 4221 }
4222 else
4223 {
4224 func (stream, "<illegal constant %.8x:%x:%x>",
4225 bits, cmode, op);
4226 size = 32;
4227 break;
4228 }
4229 switch (size)
4230 {
4231 case 8:
4232 func (stream, "#%ld\t; 0x%.2lx", value, value);
4233 break;
43e65147 4234
16980d0b
JB		 4235 case 16:
4236 func (stream, "#%ld\t; 0x%.4lx", value, value);
4237 break;
4238
4239 case 32:
0dbde4cf
JB		 4240 if (isfloat)
4241 {
4242 unsigned char valbytes[4];
4243 double fvalue;
43e65147 4244
0dbde4cf
JB		 4245 /* Do this a byte at a time so we don't have to
4246 worry about the host's endianness. */
4247 valbytes[0] = value & 0xff;
4248 valbytes[1] = (value >> 8) & 0xff;
4249 valbytes[2] = (value >> 16) & 0xff;
4250 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 4251
4252 floatformat_to_double
c1e26897
NC		 4253 (& floatformat_ieee_single_little, valbytes,
4254 & fvalue);
43e65147 4255
0dbde4cf
JB		 4256 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
4257 value);
4258 }
4259 else
4e9d3b81 4260 func (stream, "#%ld\t; 0x%.8lx",
43e65147 4261 (long) (((value & 0x80000000L) != 0)
9d82ec38 4262 ? value | ~0xffffffffL : value),
c1e26897 4263 value);
16980d0b
JB		 4264 break;
4265
4266 case 64:
4267 func (stream, "#0x%.8lx%.8lx", hival, value);
4268 break;
43e65147 4269
16980d0b
JB		 4270 default:
4271 abort ();
4272 }
4273 }
4274 break;
43e65147 4275
16980d0b
JB		 4276 case 'F':
4277 {
4278 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
4279 int num = (given >> 8) & 0x3;
43e65147 4280
16980d0b
JB		 4281 if (!num)
4282 func (stream, "{d%d}", regno);
4283 else if (num + regno >= 32)
4284 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
4285 else
4286 func (stream, "{d%d-d%d}", regno, regno + num);
4287 }
4288 break;
7e8e6784 4289
16980d0b
JB		 4290
4291 case '0': case '1': case '2': case '3': case '4':
4292 case '5': case '6': case '7': case '8': case '9':
4293 {
4294 int width;
4295 unsigned long value;
4296
4297 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 4298
16980d0b
JB		 4299 switch (*c)
4300 {
4301 case 'r':
4302 func (stream, "%s", arm_regnames[value]);
4303 break;
4304 case 'd':
4305 func (stream, "%ld", value);
05413229 4306 value_in_comment = value;
16980d0b
JB		 4307 break;
4308 case 'e':
4309 func (stream, "%ld", (1ul << width) - value);
4310 break;
43e65147 4311
16980d0b
JB		 4312 case 'S':
4313 case 'T':
4314 case 'U':
05413229 4315 /* Various width encodings. */
16980d0b
JB		 4316 {
4317 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
4318 int limit;
4319 unsigned low, high;
4320
4321 c++;
4322 if (*c >= '0' && *c <= '9')
4323 limit = *c - '0';
4324 else if (*c >= 'a' && *c <= 'f')
4325 limit = *c - 'a' + 10;
4326 else
4327 abort ();
4328 low = limit >> 2;
4329 high = limit & 3;
4330
4331 if (value < low || value > high)
4332 func (stream, "<illegal width %d>", base << value);
4333 else
4334 func (stream, "%d", base << value);
4335 }
4336 break;
4337 case 'R':
4338 if (given & (1 << 6))
4339 goto Q;
4340 /* FALLTHROUGH */
4341 case 'D':
4342 func (stream, "d%ld", value);
4343 break;
4344 case 'Q':
4345 Q:
4346 if (value & 1)
4347 func (stream, "<illegal reg q%ld.5>", value >> 1);
4348 else
4349 func (stream, "q%ld", value >> 1);
4350 break;
43e65147 4351
16980d0b
JB		 4352 case '`':
4353 c++;
4354 if (value == 0)
4355 func (stream, "%c", *c);
4356 break;
4357 case '\'':
4358 c++;
4359 if (value == ((1ul << width) - 1))
4360 func (stream, "%c", *c);
4361 break;
4362 case '?':
fe56b6ce 4363 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 4364 c += 1 << width;
4365 break;
4366 default:
4367 abort ();
4368 }
4369 break;
4370
4371 default:
4372 abort ();
4373 }
4374 }
4375 }
4376 else
4377 func (stream, "%c", *c);
4378 }
05413229
NC		 4379
4380 if (value_in_comment > 32 || value_in_comment < -16)
4381 func (stream, "\t; 0x%lx", value_in_comment);
4382
e2efe87d
MGD		 4383 if (is_unpredictable)
4384 func (stream, UNPREDICTABLE_INSTRUCTION);
4385
16980d0b
JB		 4386 return TRUE;
4387 }
4388 }
4389 return FALSE;
4390}
4391
90ec0d68
MGD		 4392/* Return the name of a v7A special register. */
4393
43e65147 4394static const char *
90ec0d68
MGD		 4395banked_regname (unsigned reg)
4396{
4397 switch (reg)
4398 {
4399 case 15: return "CPSR";
43e65147 4400 case 32: return "R8_usr";
90ec0d68
MGD		 4401 case 33: return "R9_usr";
4402 case 34: return "R10_usr";
4403 case 35: return "R11_usr";
4404 case 36: return "R12_usr";
4405 case 37: return "SP_usr";
4406 case 38: return "LR_usr";
43e65147 4407 case 40: return "R8_fiq";
90ec0d68
MGD		 4408 case 41: return "R9_fiq";
4409 case 42: return "R10_fiq";
4410 case 43: return "R11_fiq";
4411 case 44: return "R12_fiq";
4412 case 45: return "SP_fiq";
4413 case 46: return "LR_fiq";
4414 case 48: return "LR_irq";
4415 case 49: return "SP_irq";
4416 case 50: return "LR_svc";
4417 case 51: return "SP_svc";
4418 case 52: return "LR_abt";
4419 case 53: return "SP_abt";
4420 case 54: return "LR_und";
4421 case 55: return "SP_und";
4422 case 60: return "LR_mon";
4423 case 61: return "SP_mon";
4424 case 62: return "ELR_hyp";
4425 case 63: return "SP_hyp";
4426 case 79: return "SPSR";
4427 case 110: return "SPSR_fiq";
4428 case 112: return "SPSR_irq";
4429 case 114: return "SPSR_svc";
4430 case 116: return "SPSR_abt";
4431 case 118: return "SPSR_und";
4432 case 124: return "SPSR_mon";
4433 case 126: return "SPSR_hyp";
4434 default: return NULL;
4435 }
4436}
4437
e797f7e0
MGD		 4438/* Return the name of the DMB/DSB option. */
4439static const char *
4440data_barrier_option (unsigned option)
4441{
4442 switch (option & 0xf)
4443 {
4444 case 0xf: return "sy";
4445 case 0xe: return "st";
4446 case 0xd: return "ld";
4447 case 0xb: return "ish";
4448 case 0xa: return "ishst";
4449 case 0x9: return "ishld";
4450 case 0x7: return "un";
4451 case 0x6: return "unst";
4452 case 0x5: return "nshld";
4453 case 0x3: return "osh";
4454 case 0x2: return "oshst";
4455 case 0x1: return "oshld";
4456 default: return NULL;
4457 }
4458}
4459
4a5329c6
ZW		 4460/* Print one ARM instruction from PC on INFO->STREAM. */
4461
4462static void
4463print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 4464{
6b5d3a4d 4465 const struct opcode32 *insn;
6a51a8a8 4466 void *stream = info->stream;
6b5d3a4d 4467 fprintf_ftype func = info->fprintf_func;
b0e28b39 4468 struct arm_private_data *private_data = info->private_data;
252b5132 4469
16980d0b
JB		 4470 if (print_insn_coprocessor (pc, info, given, FALSE))
4471 return;
4472
4473 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 4474 return;
4475
252b5132
RH		 4476 for (insn = arm_opcodes; insn->assembler; insn++)
4477 {
0313a2b8
NC		 4478 if ((given & insn->mask) != insn->value)
4479 continue;
823d2571
TG		 4480
4481 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 4482 continue;
4483
4484 /* Special case: an instruction with all bits set in the condition field
4485 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
4486 or by the catchall at the end of the table. */
4487 if ((given & 0xF0000000) != 0xF0000000
4488 || (insn->mask & 0xF0000000) == 0xF0000000
4489 || (insn->mask == 0 && insn->value == 0))
252b5132 4490 {
ff4a8d2b
NC		 4491 unsigned long u_reg = 16;
4492 unsigned long U_reg = 16;
ab8e2090 4493 bfd_boolean is_unpredictable = FALSE;
05413229 4494 signed long value_in_comment = 0;
6b5d3a4d 4495 const char *c;
b34976b6 4496
252b5132
RH		 4497 for (c = insn->assembler; *c; c++)
4498 {
4499 if (*c == '%')
4500 {
c1e26897
NC		 4501 bfd_boolean allow_unpredictable = FALSE;
4502
252b5132
RH		 4503 switch (*++c)
4504 {
4505 case '%':
4506 func (stream, "%%");
4507 break;
4508
4509 case 'a':
05413229 4510 value_in_comment = print_arm_address (pc, info, given);
62b3e311 4511 break;
252b5132 4512
62b3e311
PB		 4513 case 'P':
4514 /* Set P address bit and use normal address
4515 printing routine. */
c1e26897 4516 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 4517 break;
4518
c1e26897
NC		 4519 case 'S':
4520 allow_unpredictable = TRUE;
252b5132
RH		 4521 case 's':
4522 if ((given & 0x004f0000) == 0x004f0000)
4523 {
58efb6c0 4524 /* PC relative with immediate offset. */
f8b960bc 4525 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 4526
aefd8a40
NC		 4527 if (PRE_BIT_SET)
4528 {
26d97720
NS		 4529 /* Elide positive zero offset. */
4530 if (offset || NEGATIVE_BIT_SET)
4531 func (stream, "[pc, #%s%d]\t; ",
d908c8af 4532 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 4533 else
26d97720
NS		 4534 func (stream, "[pc]\t; ");
4535 if (NEGATIVE_BIT_SET)
4536 offset = -offset;
aefd8a40
NC		 4537 info->print_address_func (offset + pc + 8, info);
4538 }
4539 else
4540 {
26d97720
NS		 4541 /* Always show the offset. */
4542 func (stream, "[pc], #%s%d",
d908c8af 4543 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 4544 if (! allow_unpredictable)
4545 is_unpredictable = TRUE;
aefd8a40 4546 }
252b5132
RH		 4547 }
4548 else
4549 {
fe56b6ce
NC		 4550 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
4551
b34976b6 4552 func (stream, "[%s",
252b5132 4553 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 4554
c1e26897 4555 if (PRE_BIT_SET)
252b5132 4556 {
c1e26897 4557 if (IMMEDIATE_BIT_SET)
252b5132 4558 {
26d97720
NS		 4559 /* Elide offset for non-writeback
4560 positive zero. */
4561 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
4562 || offset)
4563 func (stream, ", #%s%d",
4564 NEGATIVE_BIT_SET ? "-" : "", offset);
4565
4566 if (NEGATIVE_BIT_SET)
4567 offset = -offset;
945ee430 4568
fe56b6ce 4569 value_in_comment = offset;
252b5132 4570 }
945ee430 4571 else
ff4a8d2b
NC		 4572 {
4573 /* Register Offset or Register Pre-Indexed. */
4574 func (stream, ", %s%s",
4575 NEGATIVE_BIT_SET ? "-" : "",
4576 arm_regnames[given & 0xf]);
4577
4578 /* Writing back to the register that is the source/
4579 destination of the load/store is unpredictable. */
4580 if (! allow_unpredictable
4581 && WRITEBACK_BIT_SET
4582 && ((given & 0xf) == ((given >> 12) & 0xf)))
4583 is_unpredictable = TRUE;
4584 }
252b5132 4585
b34976b6 4586 func (stream, "]%s",
c1e26897 4587 WRITEBACK_BIT_SET ? "!" : "");
252b5132 4588 }
945ee430 4589 else
252b5132 4590 {
c1e26897 4591 if (IMMEDIATE_BIT_SET)
252b5132 4592 {
945ee430 4593 /* Immediate Post-indexed. */
aefd8a40 4594 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 4595 func (stream, "], #%s%d",
4596 NEGATIVE_BIT_SET ? "-" : "", offset);
4597 if (NEGATIVE_BIT_SET)
4598 offset = -offset;
fe56b6ce 4599 value_in_comment = offset;
252b5132 4600 }
945ee430 4601 else
ff4a8d2b
NC		 4602 {
4603 /* Register Post-indexed. */
4604 func (stream, "], %s%s",
4605 NEGATIVE_BIT_SET ? "-" : "",
4606 arm_regnames[given & 0xf]);
4607
4608 /* Writing back to the register that is the source/
4609 destination of the load/store is unpredictable. */
4610 if (! allow_unpredictable
4611 && (given & 0xf) == ((given >> 12) & 0xf))
4612 is_unpredictable = TRUE;
4613 }
c1e26897 4614
07a28fab
NC		 4615 if (! allow_unpredictable)
4616 {
4617 /* Writeback is automatically implied by post- addressing.
4618 Setting the W bit is unnecessary and ARM specify it as
4619 being unpredictable. */
4620 if (WRITEBACK_BIT_SET
4621 /* Specifying the PC register as the post-indexed
4622 registers is also unpredictable. */
ab8e2090
NC		 4623 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
4624 is_unpredictable = TRUE;
07a28fab 4625 }
252b5132
RH		 4626 }
4627 }
4628 break;
b34976b6 4629
252b5132 4630 case 'b':
6b5d3a4d 4631 {
f8b960bc 4632 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
05413229 4633 info->print_address_func (disp * 4 + pc + 8, info);
6b5d3a4d 4634 }
252b5132
RH		 4635 break;
4636
4637 case 'c':
c22aaad1
PB		 4638 if (((given >> 28) & 0xf) != 0xe)
4639 func (stream, "%s",
4640 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 4641 break;
4642
4643 case 'm':
4644 {
4645 int started = 0;
4646 int reg;
4647
4648 func (stream, "{");
4649 for (reg = 0; reg < 16; reg++)
4650 if ((given & (1 << reg)) != 0)
4651 {
4652 if (started)
4653 func (stream, ", ");
4654 started = 1;
4655 func (stream, "%s", arm_regnames[reg]);
4656 }
4657 func (stream, "}");
ab8e2090
NC		 4658 if (! started)
4659 is_unpredictable = TRUE;
252b5132
RH		 4660 }
4661 break;
4662
37b37b2d 4663 case 'q':
78c66db8 4664 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 4665 break;
4666
252b5132
RH		 4667 case 'o':
4668 if ((given & 0x02000000) != 0)
4669 {
a415b1cd
JB		 4670 unsigned int rotate = (given & 0xf00) >> 7;
4671 unsigned int immed = (given & 0xff);
4672 unsigned int a, i;
4673
4674 a = (((immed << (32 - rotate))
4675 | (immed >> rotate)) & 0xffffffff);
4676 /* If there is another encoding with smaller rotate,
4677 the rotate should be specified directly. */
4678 for (i = 0; i < 32; i += 2)
4679 if ((a << i | a >> (32 - i)) <= 0xff)
4680 break;
4681
4682 if (i != rotate)
4683 func (stream, "#%d, %d", immed, rotate);
4684 else
4685 func (stream, "#%d", a);
4686 value_in_comment = a;
252b5132
RH		 4687 }
4688 else
78c66db8 4689 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 4690 break;
4691
4692 case 'p':
4693 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 4694 {
823d2571
TG		 4695 arm_feature_set arm_ext_v6 =
4696 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
4697
aefd8a40
NC		 4698 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
4699 mechanism for setting PSR flag bits. They are
4700 obsolete in V6 onwards. */
823d2571
TG		 4701 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
4702 arm_ext_v6))
aefd8a40 4703 func (stream, "p");
4ab90a7a
AV		 4704 else
4705 is_unpredictable = TRUE;
aefd8a40 4706 }
252b5132
RH		 4707 break;
4708
4709 case 't':
4710 if ((given & 0x01200000) == 0x00200000)
4711 func (stream, "t");
4712 break;
4713
252b5132 4714 case 'A':
05413229
NC		 4715 {
4716 int offset = given & 0xff;
f02232aa 4717
05413229 4718 value_in_comment = offset * 4;
c1e26897 4719 if (NEGATIVE_BIT_SET)
05413229 4720 value_in_comment = - value_in_comment;
f02232aa 4721
05413229 4722 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 4723
c1e26897 4724 if (PRE_BIT_SET)
05413229
NC		 4725 {
4726 if (offset)
fe56b6ce 4727 func (stream, ", #%d]%s",
d908c8af 4728 (int) value_in_comment,
c1e26897 4729 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 4730 else
4731 func (stream, "]");
4732 }
4733 else
4734 {
4735 func (stream, "]");
f02232aa 4736
c1e26897 4737 if (WRITEBACK_BIT_SET)
05413229
NC		 4738 {
4739 if (offset)
d908c8af 4740 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 4741 }
4742 else
fe56b6ce 4743 {
d908c8af 4744 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 4745 value_in_comment = offset;
4746 }
05413229
NC		 4747 }
4748 }
252b5132
RH		 4749 break;
4750
077b8428
NC		 4751 case 'B':
4752 /* Print ARM V5 BLX(1) address: pc+25 bits. */
4753 {
4754 bfd_vma address;
4755 bfd_vma offset = 0;
b34976b6 4756
c1e26897 4757 if (! NEGATIVE_BIT_SET)
077b8428
NC		 4758 /* Is signed, hi bits should be ones. */
4759 offset = (-1) ^ 0x00ffffff;
4760
4761 /* Offset is (SignExtend(offset field)<<2). */
4762 offset += given & 0x00ffffff;
4763 offset <<= 2;
4764 address = offset + pc + 8;
b34976b6 4765
8f06b2d8
PB		 4766 if (given & 0x01000000)
4767 /* H bit allows addressing to 2-byte boundaries. */
4768 address += 2;
b1ee46c5 4769
8f06b2d8 4770 info->print_address_func (address, info);
b1ee46c5 4771 }
b1ee46c5
AH		 4772 break;
4773
252b5132 4774 case 'C':
90ec0d68
MGD		 4775 if ((given & 0x02000200) == 0x200)
4776 {
4777 const char * name;
4778 unsigned sysm = (given & 0x004f0000) >> 16;
4779
4780 sysm |= (given & 0x300) >> 4;
4781 name = banked_regname (sysm);
4782
4783 if (name != NULL)
4784 func (stream, "%s", name);
4785 else
d908c8af 4786 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 4787 }
4788 else
4789 {
43e65147 4790 func (stream, "%cPSR_",
90ec0d68
MGD		 4791 (given & 0x00400000) ? 'S' : 'C');
4792 if (given & 0x80000)
4793 func (stream, "f");
4794 if (given & 0x40000)
4795 func (stream, "s");
4796 if (given & 0x20000)
4797 func (stream, "x");
4798 if (given & 0x10000)
4799 func (stream, "c");
4800 }
252b5132
RH		 4801 break;
4802
62b3e311 4803 case 'U':
43e65147 4804 if ((given & 0xf0) == 0x60)
62b3e311 4805 {
52e7f43d
RE		 4806 switch (given & 0xf)
4807 {
4808 case 0xf: func (stream, "sy"); break;
4809 default:
4810 func (stream, "#%d", (int) given & 0xf);
4811 break;
4812 }
43e65147
L		 4813 }
4814 else
52e7f43d 4815 {
e797f7e0
MGD		 4816 const char * opt = data_barrier_option (given & 0xf);
4817 if (opt != NULL)
4818 func (stream, "%s", opt);
4819 else
52e7f43d 4820 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 4821 }
4822 break;
4823
b34976b6 4824 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 4825 case '5': case '6': case '7': case '8': case '9':
4826 {
16980d0b
JB		 4827 int width;
4828 unsigned long value;
252b5132 4829
16980d0b 4830 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 4831
252b5132
RH		 4832 switch (*c)
4833 {
ab8e2090
NC		 4834 case 'R':
4835 if (value == 15)
4836 is_unpredictable = TRUE;
4837 /* Fall through. */
16980d0b 4838 case 'r':
9eb6c0f1
MGD		 4839 case 'T':
4840 /* We want register + 1 when decoding T. */
4841 if (*c == 'T')
4842 ++value;
4843
ff4a8d2b
NC		 4844 if (c[1] == 'u')
4845 {
4846 /* Eat the 'u' character. */
4847 ++ c;
4848
4849 if (u_reg == value)
4850 is_unpredictable = TRUE;
4851 u_reg = value;
4852 }
4853 if (c[1] == 'U')
4854 {
4855 /* Eat the 'U' character. */
4856 ++ c;
4857
4858 if (U_reg == value)
4859 is_unpredictable = TRUE;
4860 U_reg = value;
4861 }
16980d0b
JB		 4862 func (stream, "%s", arm_regnames[value]);
4863 break;
4864 case 'd':
4865 func (stream, "%ld", value);
05413229 4866 value_in_comment = value;
16980d0b
JB		 4867 break;
4868 case 'b':
4869 func (stream, "%ld", value * 8);
05413229 4870 value_in_comment = value * 8;
16980d0b
JB		 4871 break;
4872 case 'W':
4873 func (stream, "%ld", value + 1);
05413229 4874 value_in_comment = value + 1;
16980d0b
JB		 4875 break;
4876 case 'x':
4877 func (stream, "0x%08lx", value);
4878
4879 /* Some SWI instructions have special
4880 meanings. */
4881 if ((given & 0x0fffffff) == 0x0FF00000)
4882 func (stream, "\t; IMB");
4883 else if ((given & 0x0fffffff) == 0x0FF00001)
4884 func (stream, "\t; IMBRange");
4885 break;
4886 case 'X':
4887 func (stream, "%01lx", value & 0xf);
05413229 4888 value_in_comment = value;
252b5132
RH		 4889 break;
4890 case '`':
4891 c++;
16980d0b 4892 if (value == 0)
252b5132
RH		 4893 func (stream, "%c", *c);
4894 break;
4895 case '\'':
4896 c++;
16980d0b 4897 if (value == ((1ul << width) - 1))
252b5132
RH		 4898 func (stream, "%c", *c);
4899 break;
4900 case '?':
fe56b6ce 4901 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 4902 c += 1 << width;
252b5132
RH		 4903 break;
4904 default:
4905 abort ();
4906 }
4907 break;
4908
0dd132b6
NC		 4909 case 'e':
4910 {
4911 int imm;
4912
4913 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
4914 func (stream, "%d", imm);
fe56b6ce 4915 value_in_comment = imm;
0dd132b6
NC		 4916 }
4917 break;
4918
0a003adc
ZW		 4919 case 'E':
4920 /* LSB and WIDTH fields of BFI or BFC. The machine-
4921 language instruction encodes LSB and MSB. */
4922 {
4923 long msb = (given & 0x001f0000) >> 16;
4924 long lsb = (given & 0x00000f80) >> 7;
91d6fa6a 4925 long w = msb - lsb + 1;
fe56b6ce 4926
91d6fa6a
NC		 4927 if (w > 0)
4928 func (stream, "#%lu, #%lu", lsb, w);
0a003adc
ZW		 4929 else
4930 func (stream, "(invalid: %lu:%lu)", lsb, msb);
4931 }
4932 break;
4933
90ec0d68
MGD		 4934 case 'R':
4935 /* Get the PSR/banked register name. */
4936 {
4937 const char * name;
4938 unsigned sysm = (given & 0x004f0000) >> 16;
4939
4940 sysm |= (given & 0x300) >> 4;
4941 name = banked_regname (sysm);
4942
4943 if (name != NULL)
4944 func (stream, "%s", name);
4945 else
d908c8af 4946 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 4947 }
4948 break;
4949
0a003adc
ZW		 4950 case 'V':
4951 /* 16-bit unsigned immediate from a MOVT or MOVW
4952 instruction, encoded in bits 0:11 and 15:19. */
4953 {
4954 long hi = (given & 0x000f0000) >> 4;
4955 long lo = (given & 0x00000fff);
4956 long imm16 = hi | lo;
fe56b6ce
NC		 4957
4958 func (stream, "#%lu", imm16);
4959 value_in_comment = imm16;
0a003adc
ZW		 4960 }
4961 break;
4962
252b5132
RH		 4963 default:
4964 abort ();
4965 }
4966 }
4967 }
4968 else
4969 func (stream, "%c", *c);
4970 }
05413229
NC		 4971
4972 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 4973 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 4974
4975 if (is_unpredictable)
4976 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 4977
4a5329c6 4978 return;
252b5132
RH		 4979 }
4980 }
4981 abort ();
4982}
4983
4a5329c6 4984/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 4985
4a5329c6
ZW		 4986static void
4987print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 4988{
6b5d3a4d 4989 const struct opcode16 *insn;
6a51a8a8
AM		 4990 void *stream = info->stream;
4991 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 4992
4993 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 4994 if ((given & insn->mask) == insn->value)
4995 {
05413229 4996 signed long value_in_comment = 0;
6b5d3a4d 4997 const char *c = insn->assembler;
05413229 4998
c19d1205
ZW		 4999 for (; *c; c++)
5000 {
5001 int domaskpc = 0;
5002 int domasklr = 0;
5003
5004 if (*c != '%')
5005 {
5006 func (stream, "%c", *c);
5007 continue;
5008 }
252b5132 5009
c19d1205
ZW		 5010 switch (*++c)
5011 {
5012 case '%':
5013 func (stream, "%%");
5014 break;
b34976b6 5015
c22aaad1
PB		 5016 case 'c':
5017 if (ifthen_state)
5018 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5019 break;
5020
5021 case 'C':
5022 if (ifthen_state)
5023 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5024 else
5025 func (stream, "s");
5026 break;
5027
5028 case 'I':
5029 {
5030 unsigned int tmp;
5031
5032 ifthen_next_state = given & 0xff;
5033 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
5034 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
5035 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
5036 }
5037 break;
5038
5039 case 'x':
5040 if (ifthen_next_state)
5041 func (stream, "\t; unpredictable branch in IT block\n");
5042 break;
5043
5044 case 'X':
5045 if (ifthen_state)
5046 func (stream, "\t; unpredictable <IT:%s>",
5047 arm_conditional[IFTHEN_COND]);
5048 break;
5049
c19d1205
ZW		 5050 case 'S':
5051 {
5052 long reg;
5053
5054 reg = (given >> 3) & 0x7;
5055 if (given & (1 << 6))
5056 reg += 8;
4f3c3dbb 5057
c19d1205
ZW		 5058 func (stream, "%s", arm_regnames[reg]);
5059 }
5060 break;
baf0cc5e 5061
c19d1205 5062 case 'D':
4f3c3dbb 5063 {
c19d1205
ZW		 5064 long reg;
5065
5066 reg = given & 0x7;
5067 if (given & (1 << 7))
5068 reg += 8;
5069
5070 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 5071 }
c19d1205
ZW		 5072 break;
5073
5074 case 'N':
5075 if (given & (1 << 8))
5076 domasklr = 1;
5077 /* Fall through. */
5078 case 'O':
5079 if (*c == 'O' && (given & (1 << 8)))
5080 domaskpc = 1;
5081 /* Fall through. */
5082 case 'M':
5083 {
5084 int started = 0;
5085 int reg;
5086
5087 func (stream, "{");
5088
5089 /* It would be nice if we could spot
5090 ranges, and generate the rS-rE format: */
5091 for (reg = 0; (reg < 8); reg++)
5092 if ((given & (1 << reg)) != 0)
5093 {
5094 if (started)
5095 func (stream, ", ");
5096 started = 1;
5097 func (stream, "%s", arm_regnames[reg]);
5098 }
5099
5100 if (domasklr)
5101 {
5102 if (started)
5103 func (stream, ", ");
5104 started = 1;
d908c8af 5105 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 5106 }
5107
5108 if (domaskpc)
5109 {
5110 if (started)
5111 func (stream, ", ");
d908c8af 5112 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 5113 }
5114
5115 func (stream, "}");
5116 }
5117 break;
5118
4547cb56
NC		 5119 case 'W':
5120 /* Print writeback indicator for a LDMIA. We are doing a
5121 writeback if the base register is not in the register
5122 mask. */
5123 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
5124 func (stream, "!");
5125 break;
5126
c19d1205
ZW		 5127 case 'b':
5128 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
5129 {
5130 bfd_vma address = (pc + 4
5131 + ((given & 0x00f8) >> 2)
5132 + ((given & 0x0200) >> 3));
5133 info->print_address_func (address, info);
5134 }
5135 break;
5136
5137 case 's':
5138 /* Right shift immediate -- bits 6..10; 1-31 print
5139 as themselves, 0 prints as 32. */
5140 {
5141 long imm = (given & 0x07c0) >> 6;
5142 if (imm == 0)
5143 imm = 32;
0fd3a477 5144 func (stream, "#%ld", imm);
c19d1205
ZW		 5145 }
5146 break;
5147
5148 case '0': case '1': case '2': case '3': case '4':
5149 case '5': case '6': case '7': case '8': case '9':
5150 {
5151 int bitstart = *c++ - '0';
5152 int bitend = 0;
5153
5154 while (*c >= '0' && *c <= '9')
5155 bitstart = (bitstart * 10) + *c++ - '0';
5156
5157 switch (*c)
5158 {
5159 case '-':
5160 {
f8b960bc 5161 bfd_vma reg;
c19d1205
ZW		 5162
5163 c++;
5164 while (*c >= '0' && *c <= '9')
5165 bitend = (bitend * 10) + *c++ - '0';
5166 if (!bitend)
5167 abort ();
5168 reg = given >> bitstart;
5169 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 5170
c19d1205
ZW		 5171 switch (*c)
5172 {
5173 case 'r':
5174 func (stream, "%s", arm_regnames[reg]);
5175 break;
5176
5177 case 'd':
d908c8af 5178 func (stream, "%ld", (long) reg);
05413229 5179 value_in_comment = reg;
c19d1205
ZW		 5180 break;
5181
5182 case 'H':
d908c8af 5183 func (stream, "%ld", (long) (reg << 1));
05413229 5184 value_in_comment = reg << 1;
c19d1205
ZW		 5185 break;
5186
5187 case 'W':
d908c8af 5188 func (stream, "%ld", (long) (reg << 2));
05413229 5189 value_in_comment = reg << 2;
c19d1205
ZW		 5190 break;
5191
5192 case 'a':
5193 /* PC-relative address -- the bottom two
5194 bits of the address are dropped
5195 before the calculation. */
5196 info->print_address_func
5197 (((pc + 4) & ~3) + (reg << 2), info);
05413229 5198 value_in_comment = 0;
c19d1205
ZW		 5199 break;
5200
5201 case 'x':
d908c8af 5202 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 5203 break;
5204
c19d1205
ZW		 5205 case 'B':
5206 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6b5d3a4d 5207 info->print_address_func (reg * 2 + pc + 4, info);
05413229 5208 value_in_comment = 0;
c19d1205
ZW		 5209 break;
5210
5211 case 'c':
c22aaad1 5212 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 5213 break;
5214
5215 default:
5216 abort ();
5217 }
5218 }
5219 break;
5220
5221 case '\'':
5222 c++;
5223 if ((given & (1 << bitstart)) != 0)
5224 func (stream, "%c", *c);
5225 break;
5226
5227 case '?':
5228 ++c;
5229 if ((given & (1 << bitstart)) != 0)
5230 func (stream, "%c", *c++);
5231 else
5232 func (stream, "%c", *++c);
5233 break;
5234
5235 default:
5236 abort ();
5237 }
5238 }
5239 break;
5240
5241 default:
5242 abort ();
5243 }
5244 }
05413229
NC		 5245
5246 if (value_in_comment > 32 || value_in_comment < -16)
5247 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 5248 return;
c19d1205
ZW		 5249 }
5250
5251 /* No match. */
5252 abort ();
5253}
5254
62b3e311 5255/* Return the name of an V7M special register. */
fe56b6ce 5256
62b3e311
PB		 5257static const char *
5258psr_name (int regno)
5259{
5260 switch (regno)
5261 {
5262 case 0: return "APSR";
5263 case 1: return "IAPSR";
5264 case 2: return "EAPSR";
5265 case 3: return "PSR";
5266 case 5: return "IPSR";
5267 case 6: return "EPSR";
5268 case 7: return "IEPSR";
5269 case 8: return "MSP";
5270 case 9: return "PSP";
5271 case 16: return "PRIMASK";
5272 case 17: return "BASEPRI";
00bbc0bd 5273 case 18: return "BASEPRI_MAX";
62b3e311
PB		 5274 case 19: return "FAULTMASK";
5275 case 20: return "CONTROL";
5276 default: return "<unknown>";
5277 }
5278}
5279
4a5329c6
ZW		 5280/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
5281
5282static void
5283print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 5284{
6b5d3a4d 5285 const struct opcode32 *insn;
c19d1205
ZW		 5286 void *stream = info->stream;
5287 fprintf_ftype func = info->fprintf_func;
5288
16980d0b
JB		 5289 if (print_insn_coprocessor (pc, info, given, TRUE))
5290 return;
5291
5292 if (print_insn_neon (info, given, TRUE))
8f06b2d8
PB		 5293 return;
5294
c19d1205
ZW		 5295 for (insn = thumb32_opcodes; insn->assembler; insn++)
5296 if ((given & insn->mask) == insn->value)
5297 {
ff4a8d2b 5298 bfd_boolean is_unpredictable = FALSE;
05413229 5299 signed long value_in_comment = 0;
6b5d3a4d 5300 const char *c = insn->assembler;
05413229 5301
c19d1205
ZW		 5302 for (; *c; c++)
5303 {
5304 if (*c != '%')
5305 {
5306 func (stream, "%c", *c);
5307 continue;
5308 }
5309
5310 switch (*++c)
5311 {
5312 case '%':
5313 func (stream, "%%");
5314 break;
5315
c22aaad1
PB		 5316 case 'c':
5317 if (ifthen_state)
5318 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5319 break;
5320
5321 case 'x':
5322 if (ifthen_next_state)
5323 func (stream, "\t; unpredictable branch in IT block\n");
5324 break;
5325
5326 case 'X':
5327 if (ifthen_state)
5328 func (stream, "\t; unpredictable <IT:%s>",
5329 arm_conditional[IFTHEN_COND]);
5330 break;
5331
c19d1205
ZW		 5332 case 'I':
5333 {
5334 unsigned int imm12 = 0;
fe56b6ce 5335
c19d1205
ZW		 5336 imm12 |= (given & 0x000000ffu);
5337 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 5338 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 5339 func (stream, "#%u", imm12);
5340 value_in_comment = imm12;
c19d1205
ZW		 5341 }
5342 break;
5343
5344 case 'M':
5345 {
5346 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 5347
c19d1205
ZW		 5348 bits |= (given & 0x000000ffu);
5349 bits |= (given & 0x00007000u) >> 4;
5350 bits |= (given & 0x04000000u) >> 15;
5351 imm8 = (bits & 0x0ff);
5352 mod = (bits & 0xf00) >> 8;
5353 switch (mod)
5354 {
5355 case 0: imm = imm8; break;
c1e26897
NC		 5356 case 1: imm = ((imm8 << 16) | imm8); break;
5357 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
5358 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 5359 default:
5360 mod = (bits & 0xf80) >> 7;
5361 imm8 = (bits & 0x07f) | 0x80;
5362 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
5363 }
fe56b6ce
NC		 5364 func (stream, "#%u", imm);
5365 value_in_comment = imm;
c19d1205
ZW		 5366 }
5367 break;
43e65147 5368
c19d1205
ZW		 5369 case 'J':
5370 {
5371 unsigned int imm = 0;
fe56b6ce 5372
c19d1205
ZW		 5373 imm |= (given & 0x000000ffu);
5374 imm |= (given & 0x00007000u) >> 4;
5375 imm |= (given & 0x04000000u) >> 15;
5376 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 5377 func (stream, "#%u", imm);
5378 value_in_comment = imm;
c19d1205
ZW		 5379 }
5380 break;
5381
5382 case 'K':
5383 {
5384 unsigned int imm = 0;
fe56b6ce 5385
c19d1205
ZW		 5386 imm |= (given & 0x000f0000u) >> 16;
5387 imm |= (given & 0x00000ff0u) >> 0;
5388 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 5389 func (stream, "#%u", imm);
5390 value_in_comment = imm;
c19d1205
ZW		 5391 }
5392 break;
5393
74db7efb
NC		 5394 case 'H':
5395 {
5396 unsigned int imm = 0;
5397
5398 imm |= (given & 0x000f0000u) >> 4;
5399 imm |= (given & 0x00000fffu) >> 0;
5400 func (stream, "#%u", imm);
5401 value_in_comment = imm;
5402 }
5403 break;
5404
90ec0d68
MGD		 5405 case 'V':
5406 {
5407 unsigned int imm = 0;
5408
5409 imm |= (given & 0x00000fffu);
5410 imm |= (given & 0x000f0000u) >> 4;
5411 func (stream, "#%u", imm);
5412 value_in_comment = imm;
5413 }
5414 break;
5415
c19d1205
ZW		 5416 case 'S':
5417 {
5418 unsigned int reg = (given & 0x0000000fu);
5419 unsigned int stp = (given & 0x00000030u) >> 4;
5420 unsigned int imm = 0;
5421 imm |= (given & 0x000000c0u) >> 6;
5422 imm |= (given & 0x00007000u) >> 10;
5423
5424 func (stream, "%s", arm_regnames[reg]);
5425 switch (stp)
5426 {
5427 case 0:
5428 if (imm > 0)
5429 func (stream, ", lsl #%u", imm);
5430 break;
5431
5432 case 1:
5433 if (imm == 0)
5434 imm = 32;
5435 func (stream, ", lsr #%u", imm);
5436 break;
5437
5438 case 2:
5439 if (imm == 0)
5440 imm = 32;
5441 func (stream, ", asr #%u", imm);
5442 break;
5443
5444 case 3:
5445 if (imm == 0)
5446 func (stream, ", rrx");
5447 else
5448 func (stream, ", ror #%u", imm);
5449 }
5450 }
5451 break;
5452
5453 case 'a':
5454 {
5455 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 5456 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 5457 unsigned int op = (given & 0x00000f00) >> 8;
5458 unsigned int i12 = (given & 0x00000fff);
5459 unsigned int i8 = (given & 0x000000ff);
5460 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 5461 bfd_vma offset = 0;
c19d1205
ZW		 5462
5463 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 5464 if (U) /* 12-bit positive immediate offset. */
5465 {
5466 offset = i12;
5467 if (Rn != 15)
5468 value_in_comment = offset;
5469 }
5470 else if (Rn == 15) /* 12-bit negative immediate offset. */
5471 offset = - (int) i12;
5472 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 5473 {
5474 unsigned int Rm = (i8 & 0x0f);
5475 unsigned int sh = (i8 & 0x30) >> 4;
05413229 5476
c19d1205
ZW		 5477 func (stream, ", %s", arm_regnames[Rm]);
5478 if (sh)
5479 func (stream, ", lsl #%u", sh);
5480 func (stream, "]");
5481 break;
5482 }
5483 else switch (op)
5484 {
05413229 5485 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 5486 offset = i8;
5487 break;
5488
05413229 5489 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 5490 offset = -i8;
5491 break;
5492
05413229 5493 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 5494 offset = i8;
5495 writeback = TRUE;
5496 break;
5497
05413229 5498 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 5499 offset = -i8;
5500 writeback = TRUE;
5501 break;
5502
05413229 5503 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 5504 offset = i8;
5505 postind = TRUE;
5506 break;
5507
05413229 5508 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 5509 offset = -i8;
5510 postind = TRUE;
5511 break;
5512
5513 default:
5514 func (stream, ", <undefined>]");
5515 goto skip;
5516 }
5517
5518 if (postind)
d908c8af 5519 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 5520 else
5521 {
5522 if (offset)
d908c8af 5523 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 5524 func (stream, writeback ? "]!" : "]");
5525 }
5526
5527 if (Rn == 15)
5528 {
5529 func (stream, "\t; ");
5530 info->print_address_func (((pc + 4) & ~3) + offset, info);
5531 }
5532 }
5533 skip:
5534 break;
5535
5536 case 'A':
5537 {
c1e26897
NC		 5538 unsigned int U = ! NEGATIVE_BIT_SET;
5539 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 5540 unsigned int Rn = (given & 0x000f0000) >> 16;
5541 unsigned int off = (given & 0x000000ff);
5542
5543 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 5544
5545 if (PRE_BIT_SET)
c19d1205
ZW		 5546 {
5547 if (off || !U)
05413229
NC		 5548 {
5549 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
5550 value_in_comment = off * 4 * U ? 1 : -1;
5551 }
c19d1205
ZW		 5552 func (stream, "]");
5553 if (W)
5554 func (stream, "!");
5555 }
5556 else
5557 {
5558 func (stream, "], ");
5559 if (W)
05413229
NC		 5560 {
5561 func (stream, "#%c%u", U ? '+' : '-', off * 4);
5562 value_in_comment = off * 4 * U ? 1 : -1;
5563 }
c19d1205 5564 else
fe56b6ce
NC		 5565 {
5566 func (stream, "{%u}", off);
5567 value_in_comment = off;
5568 }
c19d1205
ZW		 5569 }
5570 }
5571 break;
5572
5573 case 'w':
5574 {
5575 unsigned int Sbit = (given & 0x01000000) >> 24;
5576 unsigned int type = (given & 0x00600000) >> 21;
05413229 5577
c19d1205
ZW		 5578 switch (type)
5579 {
5580 case 0: func (stream, Sbit ? "sb" : "b"); break;
5581 case 1: func (stream, Sbit ? "sh" : "h"); break;
5582 case 2:
5583 if (Sbit)
5584 func (stream, "??");
5585 break;
5586 case 3:
5587 func (stream, "??");
5588 break;
5589 }
5590 }
5591 break;
5592
5593 case 'm':
5594 {
5595 int started = 0;
5596 int reg;
5597
5598 func (stream, "{");
5599 for (reg = 0; reg < 16; reg++)
5600 if ((given & (1 << reg)) != 0)
5601 {
5602 if (started)
5603 func (stream, ", ");
5604 started = 1;
5605 func (stream, "%s", arm_regnames[reg]);
5606 }
5607 func (stream, "}");
5608 }
5609 break;
5610
5611 case 'E':
5612 {
5613 unsigned int msb = (given & 0x0000001f);
5614 unsigned int lsb = 0;
fe56b6ce 5615
c19d1205
ZW		 5616 lsb |= (given & 0x000000c0u) >> 6;
5617 lsb |= (given & 0x00007000u) >> 10;
5618 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
5619 }
5620 break;
5621
5622 case 'F':
5623 {
5624 unsigned int width = (given & 0x0000001f) + 1;
5625 unsigned int lsb = 0;
fe56b6ce 5626
c19d1205
ZW		 5627 lsb |= (given & 0x000000c0u) >> 6;
5628 lsb |= (given & 0x00007000u) >> 10;
5629 func (stream, "#%u, #%u", lsb, width);
5630 }
5631 break;
5632
5633 case 'b':
5634 {
5635 unsigned int S = (given & 0x04000000u) >> 26;
5636 unsigned int J1 = (given & 0x00002000u) >> 13;
5637 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 5638 bfd_vma offset = 0;
c19d1205
ZW		 5639
5640 offset |= !S << 20;
5641 offset |= J2 << 19;
5642 offset |= J1 << 18;
5643 offset |= (given & 0x003f0000) >> 4;
5644 offset |= (given & 0x000007ff) << 1;
5645 offset -= (1 << 20);
5646
5647 info->print_address_func (pc + 4 + offset, info);
5648 }
5649 break;
5650
5651 case 'B':
5652 {
5653 unsigned int S = (given & 0x04000000u) >> 26;
5654 unsigned int I1 = (given & 0x00002000u) >> 13;
5655 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 5656 bfd_vma offset = 0;
c19d1205
ZW		 5657
5658 offset |= !S << 24;
5659 offset |= !(I1 ^ S) << 23;
5660 offset |= !(I2 ^ S) << 22;
5661 offset |= (given & 0x03ff0000u) >> 4;
5662 offset |= (given & 0x000007ffu) << 1;
5663 offset -= (1 << 24);
36b0c57d 5664 offset += pc + 4;
c19d1205 5665
36b0c57d
PB		 5666 /* BLX target addresses are always word aligned. */
5667 if ((given & 0x00001000u) == 0)
5668 offset &= ~2u;
5669
5670 info->print_address_func (offset, info);
c19d1205
ZW		 5671 }
5672 break;
5673
5674 case 's':
5675 {
5676 unsigned int shift = 0;
fe56b6ce 5677
c19d1205
ZW		 5678 shift |= (given & 0x000000c0u) >> 6;
5679 shift |= (given & 0x00007000u) >> 10;
c1e26897 5680 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 5681 func (stream, ", asr #%u", shift);
5682 else if (shift)
5683 func (stream, ", lsl #%u", shift);
5684 /* else print nothing - lsl #0 */
5685 }
5686 break;
5687
5688 case 'R':
5689 {
5690 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 5691
c19d1205
ZW		 5692 if (rot)
5693 func (stream, ", ror #%u", rot * 8);
5694 }
5695 break;
5696
62b3e311 5697 case 'U':
43e65147 5698 if ((given & 0xf0) == 0x60)
62b3e311 5699 {
52e7f43d
RE		 5700 switch (given & 0xf)
5701 {
5702 case 0xf: func (stream, "sy"); break;
5703 default:
5704 func (stream, "#%d", (int) given & 0xf);
5705 break;
5706 }
62b3e311 5707 }
43e65147 5708 else
52e7f43d 5709 {
e797f7e0
MGD		 5710 const char * opt = data_barrier_option (given & 0xf);
5711 if (opt != NULL)
5712 func (stream, "%s", opt);
5713 else
5714 func (stream, "#%d", (int) given & 0xf);
52e7f43d 5715 }
62b3e311
PB		 5716 break;
5717
5718 case 'C':
5719 if ((given & 0xff) == 0)
5720 {
5721 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
5722 if (given & 0x800)
5723 func (stream, "f");
5724 if (given & 0x400)
5725 func (stream, "s");
5726 if (given & 0x200)
5727 func (stream, "x");
5728 if (given & 0x100)
5729 func (stream, "c");
5730 }
90ec0d68
MGD		 5731 else if ((given & 0x20) == 0x20)
5732 {
5733 char const* name;
5734 unsigned sysm = (given & 0xf00) >> 8;
5735
5736 sysm |= (given & 0x30);
5737 sysm |= (given & 0x00100000) >> 14;
5738 name = banked_regname (sysm);
43e65147 5739
90ec0d68
MGD		 5740 if (name != NULL)
5741 func (stream, "%s", name);
5742 else
d908c8af 5743 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 5744 }
62b3e311
PB		 5745 else
5746 {
d908c8af 5747 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 5748 }
5749 break;
5750
5751 case 'D':
90ec0d68
MGD		 5752 if (((given & 0xff) == 0)
5753 || ((given & 0x20) == 0x20))
5754 {
5755 char const* name;
5756 unsigned sm = (given & 0xf0000) >> 16;
5757
5758 sm |= (given & 0x30);
5759 sm |= (given & 0x00100000) >> 14;
5760 name = banked_regname (sm);
5761
5762 if (name != NULL)
5763 func (stream, "%s", name);
5764 else
d908c8af 5765 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 5766 }
62b3e311 5767 else
d908c8af 5768 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 5769 break;
5770
c19d1205
ZW		 5771 case '0': case '1': case '2': case '3': case '4':
5772 case '5': case '6': case '7': case '8': case '9':
5773 {
16980d0b
JB		 5774 int width;
5775 unsigned long val;
c19d1205 5776
16980d0b 5777 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 5778
c19d1205
ZW		 5779 switch (*c)
5780 {
05413229
NC		 5781 case 'd':
5782 func (stream, "%lu", val);
5783 value_in_comment = val;
5784 break;
ff4a8d2b 5785
f0fba320
RL		 5786 case 'D':
5787 func (stream, "%lu", val + 1);
5788 value_in_comment = val + 1;
5789 break;
5790
05413229
NC		 5791 case 'W':
5792 func (stream, "%lu", val * 4);
5793 value_in_comment = val * 4;
5794 break;
ff4a8d2b 5795
dd5181d5
KT		 5796 case 'S':
5797 if (val == 13)
5798 is_unpredictable = TRUE;
5799 /* Fall through. */
ff4a8d2b
NC		 5800 case 'R':
5801 if (val == 15)
5802 is_unpredictable = TRUE;
5803 /* Fall through. */
5804 case 'r':
5805 func (stream, "%s", arm_regnames[val]);
5806 break;
c19d1205
ZW		 5807
5808 case 'c':
c22aaad1 5809 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 5810 break;
5811
5812 case '\'':
c19d1205 5813 c++;
16980d0b
JB		 5814 if (val == ((1ul << width) - 1))
5815 func (stream, "%c", *c);
c19d1205 5816 break;
43e65147 5817
c19d1205 5818 case '`':
c19d1205 5819 c++;
16980d0b
JB		 5820 if (val == 0)
5821 func (stream, "%c", *c);
c19d1205
ZW		 5822 break;
5823
5824 case '?':
fe56b6ce 5825 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 5826 c += 1 << width;
c19d1205 5827 break;
43e65147 5828
0bb027fd
RR		 5829 case 'x':
5830 func (stream, "0x%lx", val & 0xffffffffUL);
5831 break;
c19d1205
ZW		 5832
5833 default:
5834 abort ();
5835 }
5836 }
5837 break;
5838
32a94698
NC		 5839 case 'L':
5840 /* PR binutils/12534
5841 If we have a PC relative offset in an LDRD or STRD
5842 instructions then display the decoded address. */
5843 if (((given >> 16) & 0xf) == 0xf)
5844 {
5845 bfd_vma offset = (given & 0xff) * 4;
5846
5847 if ((given & (1 << 23)) == 0)
5848 offset = - offset;
5849 func (stream, "\t; ");
5850 info->print_address_func ((pc & ~3) + 4 + offset, info);
5851 }
5852 break;
5853
c19d1205
ZW		 5854 default:
5855 abort ();
5856 }
5857 }
05413229
NC		 5858
5859 if (value_in_comment > 32 || value_in_comment < -16)
5860 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 5861
5862 if (is_unpredictable)
5863 func (stream, UNPREDICTABLE_INSTRUCTION);
5864
4a5329c6 5865 return;
c19d1205 5866 }
252b5132 5867
58efb6c0 5868 /* No match. */
252b5132
RH		 5869 abort ();
5870}
5871
e821645d
DJ		 5872/* Print data bytes on INFO->STREAM. */
5873
5874static void
fe56b6ce
NC		 5875print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
5876 struct disassemble_info *info,
e821645d
DJ		 5877 long given)
5878{
5879 switch (info->bytes_per_chunk)
5880 {
5881 case 1:
5882 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
5883 break;
5884 case 2:
5885 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
5886 break;
5887 case 4:
5888 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
5889 break;
5890 default:
5891 abort ();
5892 }
5893}
5894
22a398e1 5895/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 5896 being displayed in symbol relative addresses.
5897
5898 Also disallow private symbol, with __tagsym$$ prefix,
5899 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 5900
5901bfd_boolean
5902arm_symbol_is_valid (asymbol * sym,
5903 struct disassemble_info * info ATTRIBUTE_UNUSED)
5904{
5905 const char * name;
43e65147 5906
22a398e1
NC		 5907 if (sym == NULL)
5908 return FALSE;
5909
5910 name = bfd_asymbol_name (sym);
5911
d8282f0e 5912 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 5913}
5914
58efb6c0 5915/* Parse an individual disassembler option. */
baf0cc5e 5916
a3d9c82d 5917void
4a5329c6 5918parse_arm_disassembler_option (char *option)
dd92f639 5919{
01c7f630 5920 if (option == NULL)
dd92f639 5921 return;
b34976b6 5922
0112cd26 5923 if (CONST_STRNEQ (option, "reg-names-"))
dd92f639 5924 {
58efb6c0 5925 int i;
b34976b6 5926
01c7f630 5927 option += 10;
58efb6c0
NC		 5928
5929 for (i = NUM_ARM_REGNAMES; i--;)
31e0f3cd 5930 if (strneq (option, regnames[i].name, strlen (regnames[i].name)))
58efb6c0
NC		 5931 {
5932 regname_selected = i;
5933 break;
5934 }
b34976b6 5935
58efb6c0 5936 if (i < 0)
31e0f3cd 5937 /* XXX - should break 'option' at following delimiter. */
58efb6c0 5938 fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
dd92f639 5939 }
0112cd26 5940 else if (CONST_STRNEQ (option, "force-thumb"))
01c7f630 5941 force_thumb = 1;
0112cd26 5942 else if (CONST_STRNEQ (option, "no-force-thumb"))
01c7f630 5943 force_thumb = 0;
dd92f639 5944 else
31e0f3cd 5945 /* XXX - should break 'option' at following delimiter. */
58efb6c0 5946 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
b34976b6 5947
dd92f639
NC		 5948 return;
5949}
5950
31e0f3cd
NC		 5951/* Parse the string of disassembler options, spliting it at whitespaces
5952 or commas. (Whitespace separators supported for backwards compatibility). */
baf0cc5e 5953
01c7f630 5954static void
4a5329c6 5955parse_disassembler_options (char *options)
01c7f630 5956{
01c7f630
NC		 5957 if (options == NULL)
5958 return;
5959
31e0f3cd 5960 while (*options)
01c7f630 5961 {
31e0f3cd
NC		 5962 parse_arm_disassembler_option (options);
5963
5964 /* Skip forward to next seperator. */
5965 while ((*options) && (! ISSPACE (*options)) && (*options != ','))
5966 ++ options;
5967 /* Skip forward past seperators. */
5968 while (ISSPACE (*options) || (*options == ','))
43e65147 5969 ++ options;
01c7f630 5970 }
01c7f630
NC		 5971}
5972
5bc5ae88
RL		 5973static bfd_boolean
5974mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
5975 enum map_type *map_symbol);
5976
c22aaad1
PB		 5977/* Search back through the insn stream to determine if this instruction is
5978 conditionally executed. */
fe56b6ce 5979
c22aaad1 5980static void
fe56b6ce
NC		 5981find_ifthen_state (bfd_vma pc,
5982 struct disassemble_info *info,
c22aaad1
PB		 5983 bfd_boolean little)
5984{
5985 unsigned char b[2];
5986 unsigned int insn;
5987 int status;
5988 /* COUNT is twice the number of instructions seen. It will be odd if we
5989 just crossed an instruction boundary. */
5990 int count;
5991 int it_count;
5992 unsigned int seen_it;
5993 bfd_vma addr;
5994
5995 ifthen_address = pc;
5996 ifthen_state = 0;
5997
5998 addr = pc;
5999 count = 1;
6000 it_count = 0;
6001 seen_it = 0;
6002 /* Scan backwards looking for IT instructions, keeping track of where
6003 instruction boundaries are. We don't know if something is actually an
6004 IT instruction until we find a definite instruction boundary. */
6005 for (;;)
6006 {
fe56b6ce 6007 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 6008 {
6009 /* A symbol must be on an instruction boundary, and will not
6010 be within an IT block. */
6011 if (seen_it && (count & 1))
6012 break;
6013
6014 return;
6015 }
6016 addr -= 2;
fe56b6ce 6017 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 6018 if (status)
6019 return;
6020
6021 if (little)
6022 insn = (b[0]) | (b[1] << 8);
6023 else
6024 insn = (b[1]) | (b[0] << 8);
6025 if (seen_it)
6026 {
6027 if ((insn & 0xf800) < 0xe800)
6028 {
6029 /* Addr + 2 is an instruction boundary. See if this matches
6030 the expected boundary based on the position of the last
6031 IT candidate. */
6032 if (count & 1)
6033 break;
6034 seen_it = 0;
6035 }
6036 }
6037 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
6038 {
5bc5ae88
RL		 6039 enum map_type type = MAP_ARM;
6040 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
6041
6042 if (!found || (found && type == MAP_THUMB))
6043 {
6044 /* This could be an IT instruction. */
6045 seen_it = insn;
6046 it_count = count >> 1;
6047 }
c22aaad1
PB		 6048 }
6049 if ((insn & 0xf800) >= 0xe800)
6050 count++;
6051 else
6052 count = (count + 2) | 1;
6053 /* IT blocks contain at most 4 instructions. */
6054 if (count >= 8 && !seen_it)
6055 return;
6056 }
6057 /* We found an IT instruction. */
6058 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
6059 if ((ifthen_state & 0xf) == 0)
6060 ifthen_state = 0;
6061}
6062
b0e28b39
DJ		 6063/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
6064 mapping symbol. */
6065
6066static int
6067is_mapping_symbol (struct disassemble_info *info, int n,
6068 enum map_type *map_type)
6069{
6070 const char *name;
6071
6072 name = bfd_asymbol_name (info->symtab[n]);
6073 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
6074 && (name[2] == 0 || name[2] == '.'))
6075 {
6076 *map_type = ((name[1] == 'a') ? MAP_ARM
6077 : (name[1] == 't') ? MAP_THUMB
6078 : MAP_DATA);
6079 return TRUE;
6080 }
6081
6082 return FALSE;
6083}
6084
6085/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
6086 Returns nonzero if *MAP_TYPE was set. */
6087
6088static int
6089get_map_sym_type (struct disassemble_info *info,
6090 int n,
6091 enum map_type *map_type)
6092{
6093 /* If the symbol is in a different section, ignore it. */
6094 if (info->section != NULL && info->section != info->symtab[n]->section)
6095 return FALSE;
6096
6097 return is_mapping_symbol (info, n, map_type);
6098}
6099
6100/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 6101 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 6102
6103static int
fe56b6ce
NC		 6104get_sym_code_type (struct disassemble_info *info,
6105 int n,
e821645d 6106 enum map_type *map_type)
2087ad84
PB		 6107{
6108 elf_symbol_type *es;
6109 unsigned int type;
b0e28b39
DJ		 6110
6111 /* If the symbol is in a different section, ignore it. */
6112 if (info->section != NULL && info->section != info->symtab[n]->section)
6113 return FALSE;
2087ad84 6114
e821645d 6115 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 6116 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6117
6118 /* If the symbol has function type then use that. */
34e77a92 6119 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 6120 {
35fc36a8
RS		 6121 if (ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym) == ST_BRANCH_TO_THUMB)
6122 *map_type = MAP_THUMB;
6123 else
6124 *map_type = MAP_ARM;
2087ad84
PB		 6125 return TRUE;
6126 }
6127
2087ad84
PB		 6128 return FALSE;
6129}
6130
5bc5ae88
RL		 6131/* Search the mapping symbol state for instruction at pc. This is only
6132 applicable for elf target.
6133
6134 There is an assumption Here, info->private_data contains the correct AND
6135 up-to-date information about current scan process. The information will be
6136 used to speed this search process.
6137
6138 Return TRUE if the mapping state can be determined, and map_symbol
6139 will be updated accordingly. Otherwise, return FALSE. */
6140
6141static bfd_boolean
6142mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6143 enum map_type *map_symbol)
6144{
6145 bfd_vma addr;
6146 int n, start = 0;
6147 bfd_boolean found = FALSE;
6148 enum map_type type = MAP_ARM;
6149 struct arm_private_data *private_data;
6150
6151 if (info->private_data == NULL || info->symtab_size == 0
6152 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
6153 return FALSE;
6154
6155 private_data = info->private_data;
6156 if (pc == 0)
6157 start = 0;
6158 else
6159 start = private_data->last_mapping_sym;
6160
6161 start = (start == -1)? 0 : start;
6162 addr = bfd_asymbol_value (info->symtab[start]);
6163
6164 if (pc >= addr)
6165 {
6166 if (get_map_sym_type (info, start, &type))
6167 found = TRUE;
6168 }
6169 else
6170 {
6171 for (n = start - 1; n >= 0; n--)
6172 {
6173 if (get_map_sym_type (info, n, &type))
6174 {
6175 found = TRUE;
6176 break;
6177 }
6178 }
6179 }
6180
6181 /* No mapping symbols were found. A leading $d may be
6182 omitted for sections which start with data; but for
6183 compatibility with legacy and stripped binaries, only
6184 assume the leading $d if there is at least one mapping
6185 symbol in the file. */
6186 if (!found && private_data->has_mapping_symbols == 1)
6187 {
6188 type = MAP_DATA;
6189 found = TRUE;
6190 }
6191
6192 *map_symbol = type;
6193 return found;
6194}
6195
0313a2b8
NC		 6196/* Given a bfd_mach_arm_XXX value, this function fills in the fields
6197 of the supplied arm_feature_set structure with bitmasks indicating
6198 the support base architectures and coprocessor extensions.
6199
6200 FIXME: This could more efficiently implemented as a constant array,
6201 although it would also be less robust. */
6202
6203static void
6204select_arm_features (unsigned long mach,
6205 arm_feature_set * features)
6206{
1af1dd51
MW		 6207#undef ARM_SET_FEATURES
6208#define ARM_SET_FEATURES(FSET) \
6209 { \
6210 const arm_feature_set fset = FSET; \
6211 arm_feature_set tmp = ARM_FEATURE (0, 0, FPU_FPA) ; \
6212 ARM_MERGE_FEATURE_SETS (*features, tmp, fset); \
6213 }
823d2571 6214
0313a2b8
NC		 6215 switch (mach)
6216 {
1af1dd51
MW		 6217 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
6218 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
6219 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
6220 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
6221 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
6222 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
6223 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
6224 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
6225 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
6226 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
6227 case bfd_mach_arm_ep9312:
6228 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
6229 ARM_CEXT_MAVERICK | FPU_MAVERICK));
6230 break;
6231 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
6232 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
0313a2b8
NC		 6233 /* If the machine type is unknown allow all
6234 architecture types and all extensions. */
1af1dd51 6235 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
0313a2b8
NC		 6236 default:
6237 abort ();
6238 }
1af1dd51
MW		 6239
6240#undef ARM_SET_FEATURES
0313a2b8
NC		 6241}
6242
6243
58efb6c0
NC		 6244/* NOTE: There are no checks in these routines that
6245 the relevant number of data bytes exist. */
baf0cc5e 6246
58efb6c0 6247static int
4a5329c6 6248print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 6249{
c19d1205
ZW		 6250 unsigned char b[4];
6251 long given;
6252 int status;
e821645d 6253 int is_thumb = FALSE;
b0e28b39 6254 int is_data = FALSE;
bd2e2557 6255 int little_code;
e821645d 6256 unsigned int size = 4;
4a5329c6 6257 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 6258 bfd_boolean found = FALSE;
b0e28b39 6259 struct arm_private_data *private_data;
58efb6c0 6260
dd92f639
NC		 6261 if (info->disassembler_options)
6262 {
6263 parse_disassembler_options (info->disassembler_options);
b34976b6 6264
58efb6c0 6265 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 6266 info->disassembler_options = NULL;
6267 }
b34976b6 6268
0313a2b8
NC		 6269 /* PR 10288: Control which instructions will be disassembled. */
6270 if (info->private_data == NULL)
6271 {
b0e28b39 6272 static struct arm_private_data private;
0313a2b8
NC		 6273
6274 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
6275 /* If the user did not use the -m command line switch then default to
6276 disassembling all types of ARM instruction.
43e65147 6277
0313a2b8
NC		 6278 The info->mach value has to be ignored as this will be based on
6279 the default archictecture for the target and/or hints in the notes
6280 section, but it will never be greater than the current largest arm
6281 machine value (iWMMXt2), which is only equivalent to the V5TE
6282 architecture. ARM architectures have advanced beyond the machine
6283 value encoding, and these newer architectures would be ignored if
6284 the machine value was used.
6285
6286 Ie the -m switch is used to restrict which instructions will be
6287 disassembled. If it is necessary to use the -m switch to tell
6288 objdump that an ARM binary is being disassembled, eg because the
6289 input is a raw binary file, but it is also desired to disassemble
6290 all ARM instructions then use "-marm". This will select the
6291 "unknown" arm architecture which is compatible with any ARM
6292 instruction. */
6293 info->mach = bfd_mach_arm_unknown;
6294
6295 /* Compute the architecture bitmask from the machine number.
6296 Note: This assumes that the machine number will not change
6297 during disassembly.... */
b0e28b39 6298 select_arm_features (info->mach, & private.features);
0313a2b8 6299
b0e28b39 6300 private.has_mapping_symbols = -1;
1fbaefec
PB		 6301 private.last_mapping_sym = -1;
6302 private.last_mapping_addr = 0;
b0e28b39
DJ		 6303
6304 info->private_data = & private;
0313a2b8 6305 }
b0e28b39
DJ		 6306
6307 private_data = info->private_data;
6308
bd2e2557
SS		 6309 /* Decide if our code is going to be little-endian, despite what the
6310 function argument might say. */
6311 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
6312
b0e28b39
DJ		 6313 /* For ELF, consult the symbol table to determine what kind of code
6314 or data we have. */
8977d4b2 6315 if (info->symtab_size != 0
e821645d
DJ		 6316 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
6317 {
6318 bfd_vma addr;
b0e28b39 6319 int n, start;
e821645d 6320 int last_sym = -1;
b0e28b39 6321 enum map_type type = MAP_ARM;
e821645d 6322
e821645d
DJ		 6323 /* Start scanning at the start of the function, or wherever
6324 we finished last time. */
6750a3a7
NC		 6325 /* PR 14006. When the address is 0 we are either at the start of the
6326 very first function, or else the first function in a new, unlinked
6327 executable section (eg because uf -ffunction-sections). Either way
6328 start scanning from the beginning of the symbol table, not where we
6329 left off last time. */
6330 if (pc == 0)
6331 start = 0;
6332 else
6333 {
6334 start = info->symtab_pos + 1;
6335 if (start < private_data->last_mapping_sym)
6336 start = private_data->last_mapping_sym;
6337 }
b0e28b39 6338 found = FALSE;
e821645d 6339
b0e28b39
DJ		 6340 /* First, look for mapping symbols. */
6341 if (private_data->has_mapping_symbols != 0)
e821645d 6342 {
b0e28b39
DJ		 6343 /* Scan up to the location being disassembled. */
6344 for (n = start; n < info->symtab_size; n++)
6345 {
6346 addr = bfd_asymbol_value (info->symtab[n]);
6347 if (addr > pc)
6348 break;
6349 if (get_map_sym_type (info, n, &type))
6350 {
6351 last_sym = n;
6352 found = TRUE;
6353 }
6354 }
6355
6356 if (!found)
6357 {
6358 /* No mapping symbol found at this address. Look backwards
cc643b88 6359 for a preceding one. */
b0e28b39
DJ		 6360 for (n = start - 1; n >= 0; n--)
6361 {
6362 if (get_map_sym_type (info, n, &type))
6363 {
6364 last_sym = n;
6365 found = TRUE;
6366 break;
6367 }
6368 }
6369 }
6370
6371 if (found)
6372 private_data->has_mapping_symbols = 1;
6373
6374 /* No mapping symbols were found. A leading $d may be
6375 omitted for sections which start with data; but for
6376 compatibility with legacy and stripped binaries, only
6377 assume the leading $d if there is at least one mapping
6378 symbol in the file. */
6379 if (!found && private_data->has_mapping_symbols == -1)
e821645d 6380 {
b0e28b39
DJ		 6381 /* Look for mapping symbols, in any section. */
6382 for (n = 0; n < info->symtab_size; n++)
6383 if (is_mapping_symbol (info, n, &type))
6384 {
6385 private_data->has_mapping_symbols = 1;
6386 break;
6387 }
6388 if (private_data->has_mapping_symbols == -1)
6389 private_data->has_mapping_symbols = 0;
6390 }
6391
6392 if (!found && private_data->has_mapping_symbols == 1)
6393 {
6394 type = MAP_DATA;
e821645d
DJ		 6395 found = TRUE;
6396 }
6397 }
6398
b0e28b39
DJ		 6399 /* Next search for function symbols to separate ARM from Thumb
6400 in binaries without mapping symbols. */
e821645d
DJ		 6401 if (!found)
6402 {
b0e28b39
DJ		 6403 /* Scan up to the location being disassembled. */
6404 for (n = start; n < info->symtab_size; n++)
e821645d 6405 {
b0e28b39
DJ		 6406 addr = bfd_asymbol_value (info->symtab[n]);
6407 if (addr > pc)
6408 break;
6409 if (get_sym_code_type (info, n, &type))
e821645d
DJ		 6410 {
6411 last_sym = n;
6412 found = TRUE;
b0e28b39
DJ		 6413 }
6414 }
6415
6416 if (!found)
6417 {
6418 /* No mapping symbol found at this address. Look backwards
cc643b88 6419 for a preceding one. */
b0e28b39
DJ		 6420 for (n = start - 1; n >= 0; n--)
6421 {
6422 if (get_sym_code_type (info, n, &type))
6423 {
6424 last_sym = n;
6425 found = TRUE;
6426 break;
6427 }
e821645d
DJ		 6428 }
6429 }
6430 }
6431
1fbaefec
PB		 6432 private_data->last_mapping_sym = last_sym;
6433 private_data->last_type = type;
6434 is_thumb = (private_data->last_type == MAP_THUMB);
6435 is_data = (private_data->last_type == MAP_DATA);
b34976b6 6436
e821645d
DJ		 6437 /* Look a little bit ahead to see if we should print out
6438 two or four bytes of data. If there's a symbol,
6439 mapping or otherwise, after two bytes then don't
6440 print more. */
6441 if (is_data)
6442 {
6443 size = 4 - (pc & 3);
6444 for (n = last_sym + 1; n < info->symtab_size; n++)
6445 {
6446 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 6447 if (addr > pc
6448 && (info->section == NULL
6449 || info->section == info->symtab[n]->section))
e821645d
DJ		 6450 {
6451 if (addr - pc < size)
6452 size = addr - pc;
6453 break;
6454 }
6455 }
6456 /* If the next symbol is after three bytes, we need to
6457 print only part of the data, so that we can use either
6458 .byte or .short. */
6459 if (size == 3)
6460 size = (pc & 1) ? 1 : 2;
6461 }
6462 }
6463
6464 if (info->symbols != NULL)
252b5132 6465 {
5876e06d
NC		 6466 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
6467 {
2f0ca46a 6468 coff_symbol_type * cs;
b34976b6 6469
5876e06d
NC		 6470 cs = coffsymbol (*info->symbols);
6471 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
6472 || cs->native->u.syment.n_sclass == C_THUMBSTAT
6473 || cs->native->u.syment.n_sclass == C_THUMBLABEL
6474 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
6475 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
6476 }
e821645d
DJ		 6477 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
6478 && !found)
5876e06d 6479 {
2087ad84
PB		 6480 /* If no mapping symbol has been found then fall back to the type
6481 of the function symbol. */
e821645d
DJ		 6482 elf_symbol_type * es;
6483 unsigned int type;
2087ad84 6484
e821645d
DJ		 6485 es = *(elf_symbol_type **)(info->symbols);
6486 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 6487
35fc36a8
RS		 6488 is_thumb = ((ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym)
6489 == ST_BRANCH_TO_THUMB)
6490 || type == STT_ARM_16BIT);
5876e06d 6491 }
e49d43ff
TG		 6492 else if (bfd_asymbol_flavour (*info->symbols)
6493 == bfd_target_mach_o_flavour)
6494 {
6495 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
6496
6497 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
6498 }
5876e06d 6499 }
b34976b6 6500
e821645d
DJ		 6501 if (force_thumb)
6502 is_thumb = TRUE;
6503
b8f9ee44
CL		 6504 if (is_data)
6505 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6506 else
6507 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6508
c19d1205 6509 info->bytes_per_line = 4;
252b5132 6510
1316c8b3
NC		 6511 /* PR 10263: Disassemble data if requested to do so by the user. */
6512 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 6513 {
6514 int i;
6515
1316c8b3 6516 /* Size was already set above. */
e821645d
DJ		 6517 info->bytes_per_chunk = size;
6518 printer = print_insn_data;
6519
fe56b6ce 6520 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 6521 given = 0;
6522 if (little)
6523 for (i = size - 1; i >= 0; i--)
6524 given = b[i] | (given << 8);
6525 else
6526 for (i = 0; i < (int) size; i++)
6527 given = b[i] | (given << 8);
6528 }
6529 else if (!is_thumb)
252b5132 6530 {
c19d1205
ZW		 6531 /* In ARM mode endianness is a straightforward issue: the instruction
6532 is four bytes long and is either ordered 0123 or 3210. */
6533 printer = print_insn_arm;
6534 info->bytes_per_chunk = 4;
4a5329c6 6535 size = 4;
c19d1205 6536
0313a2b8 6537 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 6538 if (little_code)
c19d1205
ZW		 6539 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
6540 else
6541 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
252b5132 6542 }
58efb6c0 6543 else
252b5132 6544 {
c19d1205
ZW		 6545 /* In Thumb mode we have the additional wrinkle of two
6546 instruction lengths. Fortunately, the bits that determine
6547 the length of the current instruction are always to be found
6548 in the first two bytes. */
4a5329c6 6549 printer = print_insn_thumb16;
c19d1205 6550 info->bytes_per_chunk = 2;
4a5329c6
ZW		 6551 size = 2;
6552
fe56b6ce 6553 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 6554 if (little_code)
9a2ff3f5
AM		 6555 given = (b[0]) | (b[1] << 8);
6556 else
6557 given = (b[1]) | (b[0] << 8);
6558
c19d1205 6559 if (!status)
252b5132 6560 {
c19d1205
ZW		 6561 /* These bit patterns signal a four-byte Thumb
6562 instruction. */
6563 if ((given & 0xF800) == 0xF800
6564 || (given & 0xF800) == 0xF000
6565 || (given & 0xF800) == 0xE800)
252b5132 6566 {
0313a2b8 6567 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 6568 if (little_code)
c19d1205 6569 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 6570 else
c19d1205
ZW		 6571 given = (b[1]) | (b[0] << 8) | (given << 16);
6572
6573 printer = print_insn_thumb32;
4a5329c6 6574 size = 4;
252b5132 6575 }
252b5132 6576 }
c22aaad1
PB		 6577
6578 if (ifthen_address != pc)
0313a2b8 6579 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 6580
6581 if (ifthen_state)
6582 {
6583 if ((ifthen_state & 0xf) == 0x8)
6584 ifthen_next_state = 0;
6585 else
6586 ifthen_next_state = (ifthen_state & 0xe0)
6587 | ((ifthen_state & 0xf) << 1);
6588 }
252b5132 6589 }
b34976b6 6590
c19d1205
ZW		 6591 if (status)
6592 {
6593 info->memory_error_func (status, pc, info);
6594 return -1;
6595 }
6a56ec7e
NC		 6596 if (info->flags & INSN_HAS_RELOC)
6597 /* If the instruction has a reloc associated with it, then
6598 the offset field in the instruction will actually be the
6599 addend for the reloc. (We are using REL type relocs).
6600 In such cases, we can ignore the pc when computing
6601 addresses, since the addend is not currently pc-relative. */
6602 pc = 0;
b34976b6 6603
4a5329c6 6604 printer (pc, info, given);
c22aaad1
PB		 6605
6606 if (is_thumb)
6607 {
6608 ifthen_state = ifthen_next_state;
6609 ifthen_address += size;
6610 }
4a5329c6 6611 return size;
252b5132
RH		 6612}
6613
6614int
4a5329c6 6615print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 6616{
bd2e2557
SS		 6617 /* Detect BE8-ness and record it in the disassembler info. */
6618 if (info->flavour == bfd_target_elf_flavour
6619 && info->section != NULL
6620 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
6621 info->endian_code = BFD_ENDIAN_LITTLE;
6622
b34976b6 6623 return print_insn (pc, info, FALSE);
58efb6c0 6624}
01c7f630 6625
58efb6c0 6626int
4a5329c6 6627print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 6628{
b34976b6 6629 return print_insn (pc, info, TRUE);
58efb6c0 6630}
252b5132 6631
58efb6c0 6632void
4a5329c6 6633print_arm_disassembler_options (FILE *stream)
58efb6c0
NC		 6634{
6635 int i;
252b5132 6636
58efb6c0
NC		 6637 fprintf (stream, _("\n\
6638The following ARM specific disassembler options are supported for use with\n\
6639the -M switch:\n"));
b34976b6 6640
58efb6c0
NC		 6641 for (i = NUM_ARM_REGNAMES; i--;)
6642 fprintf (stream, " reg-names-%s %*c%s\n",
6643 regnames[i].name,
d5b2f4d6 6644 (int)(14 - strlen (regnames[i].name)), ' ',
58efb6c0
NC		 6645 regnames[i].description);
6646
6647 fprintf (stream, " force-thumb Assume all insns are Thumb insns\n");
cc643b88 6648 fprintf (stream, " no-force-thumb Examine preceding label to determine an insn's type\n\n");
252b5132 6649}
GDB Binutils - Deliverables
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