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[binutils][arm] arm support for ARMv8.m Custom Datapath Extension
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
CommitLineData
252b5132 1/* Instruction printing code for the ARM
b3adc24a 2 Copyright (C) 1994-2020 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
143275ea 24#include <assert.h>
2fbad815 25
6394c606 26#include "disassemble.h"
2fbad815 27#include "opcode/arm.h"
252b5132 28#include "opintl.h"
31e0f3cd 29#include "safe-ctype.h"
65b48a81 30#include "libiberty.h"
0dbde4cf 31#include "floatformat.h"
252b5132 32
baf0cc5e 33/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 34#include "coff/internal.h"
35#include "libcoff.h"
2d5d5a8f 36#include "bfd.h"
252b5132
RH		 37#include "elf-bfd.h"
38#include "elf/internal.h"
39#include "elf/arm.h"
e49d43ff 40#include "mach-o.h"
252b5132 41
6b5d3a4d 42/* FIXME: Belongs in global header. */
01c7f630 43#ifndef strneq
58efb6c0
NC		 44#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
45#endif
46
1fbaefec
PB		 47/* Cached mapping symbol state. */
48enum map_type
49{
50 MAP_ARM,
51 MAP_THUMB,
52 MAP_DATA
53};
54
b0e28b39
DJ		 55struct arm_private_data
56{
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features;
59
1fbaefec
PB		 60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type;
62
63 /* Tracking symbol table information */
64 int last_mapping_sym;
796d6298
TC		 65
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset;
1fbaefec 68 bfd_vma last_mapping_addr;
b0e28b39
DJ		 69};
70
73cd51e5
AV		 71enum mve_instructions
72{
143275ea
AV		 73 MVE_VPST,
74 MVE_VPT_FP_T1,
75 MVE_VPT_FP_T2,
76 MVE_VPT_VEC_T1,
77 MVE_VPT_VEC_T2,
78 MVE_VPT_VEC_T3,
79 MVE_VPT_VEC_T4,
80 MVE_VPT_VEC_T5,
81 MVE_VPT_VEC_T6,
82 MVE_VCMP_FP_T1,
83 MVE_VCMP_FP_T2,
84 MVE_VCMP_VEC_T1,
85 MVE_VCMP_VEC_T2,
86 MVE_VCMP_VEC_T3,
87 MVE_VCMP_VEC_T4,
88 MVE_VCMP_VEC_T5,
89 MVE_VCMP_VEC_T6,
9743db03
AV		 90 MVE_VDUP,
91 MVE_VEOR,
92 MVE_VFMAS_FP_SCALAR,
93 MVE_VFMA_FP_SCALAR,
94 MVE_VFMA_FP,
95 MVE_VFMS_FP,
96 MVE_VHADD_T1,
97 MVE_VHADD_T2,
98 MVE_VHSUB_T1,
99 MVE_VHSUB_T2,
100 MVE_VRHADD,
04d54ace
AV		 101 MVE_VLD2,
102 MVE_VLD4,
103 MVE_VST2,
104 MVE_VST4,
aef6d006
AV		 105 MVE_VLDRB_T1,
106 MVE_VLDRH_T2,
107 MVE_VLDRB_T5,
108 MVE_VLDRH_T6,
109 MVE_VLDRW_T7,
110 MVE_VSTRB_T1,
111 MVE_VSTRH_T2,
112 MVE_VSTRB_T5,
113 MVE_VSTRH_T6,
114 MVE_VSTRW_T7,
ef1576a1
AV		 115 MVE_VLDRB_GATHER_T1,
116 MVE_VLDRH_GATHER_T2,
117 MVE_VLDRW_GATHER_T3,
118 MVE_VLDRD_GATHER_T4,
119 MVE_VLDRW_GATHER_T5,
120 MVE_VLDRD_GATHER_T6,
121 MVE_VSTRB_SCATTER_T1,
122 MVE_VSTRH_SCATTER_T2,
123 MVE_VSTRW_SCATTER_T3,
124 MVE_VSTRD_SCATTER_T4,
125 MVE_VSTRW_SCATTER_T5,
126 MVE_VSTRD_SCATTER_T6,
bf0b396d
AV		 127 MVE_VCVT_FP_FIX_VEC,
128 MVE_VCVT_BETWEEN_FP_INT,
129 MVE_VCVT_FP_HALF_FP,
130 MVE_VCVT_FROM_FP_TO_INT,
131 MVE_VRINT_FP,
c507f10b
AV		 132 MVE_VMOV_HFP_TO_GP,
133 MVE_VMOV_GP_TO_VEC_LANE,
134 MVE_VMOV_IMM_TO_VEC,
135 MVE_VMOV_VEC_TO_VEC,
136 MVE_VMOV2_VEC_LANE_TO_GP,
137 MVE_VMOV2_GP_TO_VEC_LANE,
138 MVE_VMOV_VEC_LANE_TO_GP,
139 MVE_VMVN_IMM,
140 MVE_VMVN_REG,
141 MVE_VORR_IMM,
142 MVE_VORR_REG,
143 MVE_VORN,
144 MVE_VBIC_IMM,
145 MVE_VBIC_REG,
146 MVE_VMOVX,
14925797
AV		 147 MVE_VMOVL,
148 MVE_VMOVN,
149 MVE_VMULL_INT,
150 MVE_VMULL_POLY,
151 MVE_VQDMULL_T1,
152 MVE_VQDMULL_T2,
153 MVE_VQMOVN,
154 MVE_VQMOVUN,
d3b63143
AV		 155 MVE_VADDV,
156 MVE_VMLADAV_T1,
157 MVE_VMLADAV_T2,
158 MVE_VMLALDAV,
159 MVE_VMLAS,
160 MVE_VADDLV,
161 MVE_VMLSDAV_T1,
162 MVE_VMLSDAV_T2,
163 MVE_VMLSLDAV,
164 MVE_VRMLALDAVH,
165 MVE_VRMLSLDAVH,
166 MVE_VQDMLADH,
167 MVE_VQRDMLADH,
168 MVE_VQDMLAH,
169 MVE_VQRDMLAH,
170 MVE_VQDMLASH,
171 MVE_VQRDMLASH,
172 MVE_VQDMLSDH,
173 MVE_VQRDMLSDH,
174 MVE_VQDMULH_T1,
175 MVE_VQRDMULH_T2,
176 MVE_VQDMULH_T3,
177 MVE_VQRDMULH_T4,
1c8f2df8
AV		 178 MVE_VDDUP,
179 MVE_VDWDUP,
180 MVE_VIWDUP,
181 MVE_VIDUP,
897b9bbc
AV		 182 MVE_VCADD_FP,
183 MVE_VCADD_VEC,
184 MVE_VHCADD,
185 MVE_VCMLA_FP,
186 MVE_VCMUL_FP,
ed63aa17
AV		 187 MVE_VQRSHL_T1,
188 MVE_VQRSHL_T2,
189 MVE_VQRSHRN,
190 MVE_VQRSHRUN,
191 MVE_VQSHL_T1,
192 MVE_VQSHL_T2,
193 MVE_VQSHLU_T3,
194 MVE_VQSHL_T4,
195 MVE_VQSHRN,
196 MVE_VQSHRUN,
197 MVE_VRSHL_T1,
198 MVE_VRSHL_T2,
199 MVE_VRSHR,
200 MVE_VRSHRN,
201 MVE_VSHL_T1,
202 MVE_VSHL_T2,
203 MVE_VSHL_T3,
204 MVE_VSHLC,
205 MVE_VSHLL_T1,
206 MVE_VSHLL_T2,
207 MVE_VSHR,
208 MVE_VSHRN,
209 MVE_VSLI,
210 MVE_VSRI,
66dcaa5d
AV		 211 MVE_VADC,
212 MVE_VABAV,
213 MVE_VABD_FP,
214 MVE_VABD_VEC,
215 MVE_VABS_FP,
216 MVE_VABS_VEC,
217 MVE_VADD_FP_T1,
218 MVE_VADD_FP_T2,
219 MVE_VADD_VEC_T1,
220 MVE_VADD_VEC_T2,
221 MVE_VSBC,
222 MVE_VSUB_FP_T1,
223 MVE_VSUB_FP_T2,
224 MVE_VSUB_VEC_T1,
225 MVE_VSUB_VEC_T2,
e523f101
AV		 226 MVE_VAND,
227 MVE_VBRSR,
228 MVE_VCLS,
229 MVE_VCLZ,
230 MVE_VCTP,
56858bea
AV		 231 MVE_VMAX,
232 MVE_VMAXA,
233 MVE_VMAXNM_FP,
234 MVE_VMAXNMA_FP,
235 MVE_VMAXNMV_FP,
236 MVE_VMAXNMAV_FP,
237 MVE_VMAXV,
238 MVE_VMAXAV,
239 MVE_VMIN,
240 MVE_VMINA,
241 MVE_VMINNM_FP,
242 MVE_VMINNMA_FP,
243 MVE_VMINNMV_FP,
244 MVE_VMINNMAV_FP,
245 MVE_VMINV,
246 MVE_VMINAV,
247 MVE_VMLA,
f49bb598
AV		 248 MVE_VMUL_FP_T1,
249 MVE_VMUL_FP_T2,
250 MVE_VMUL_VEC_T1,
251 MVE_VMUL_VEC_T2,
252 MVE_VMULH,
253 MVE_VRMULH,
254 MVE_VNEG_FP,
255 MVE_VNEG_VEC,
14b456f2
AV		 256 MVE_VPNOT,
257 MVE_VPSEL,
258 MVE_VQABS,
259 MVE_VQADD_T1,
260 MVE_VQADD_T2,
261 MVE_VQSUB_T1,
262 MVE_VQSUB_T2,
263 MVE_VQNEG,
264 MVE_VREV16,
265 MVE_VREV32,
266 MVE_VREV64,
23d00a41
SD		 267 MVE_LSLL,
268 MVE_LSLLI,
269 MVE_LSRL,
270 MVE_ASRL,
271 MVE_ASRLI,
272 MVE_SQRSHRL,
273 MVE_SQRSHR,
274 MVE_UQRSHL,
275 MVE_UQRSHLL,
276 MVE_UQSHL,
277 MVE_UQSHLL,
278 MVE_URSHRL,
279 MVE_URSHR,
280 MVE_SRSHRL,
281 MVE_SRSHR,
282 MVE_SQSHLL,
283 MVE_SQSHL,
e39c1607
SD		 284 MVE_CINC,
285 MVE_CINV,
286 MVE_CNEG,
287 MVE_CSINC,
288 MVE_CSINV,
289 MVE_CSET,
290 MVE_CSETM,
291 MVE_CSNEG,
292 MVE_CSEL,
73cd51e5
AV		 293 MVE_NONE
294};
295
296enum mve_unpredictable
297{
298 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
299 */
143275ea
AV		 300 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and
301 fcB = 1 (vpt). */
302 UNPRED_R13, /* Unpredictable because r13 (sp) or
303 r15 (sp) used. */
9743db03 304 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
04d54ace
AV		 305 UNPRED_Q_GT_4, /* Unpredictable because
306 vec reg start > 4 (vld4/st4). */
307 UNPRED_Q_GT_6, /* Unpredictable because
308 vec reg start > 6 (vld2/st2). */
309 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
310 and WB bit = 1. */
ef1576a1
AV		 311 UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are
312 equal. */
313 UNPRED_OS, /* Unpredictable because offset scaled == 1. */
bf0b396d
AV		 314 UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the
315 same. */
c507f10b
AV		 316 UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and
317 size = 1. */
318 UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and
319 size = 2. */
73cd51e5
AV		 320 UNPRED_NONE /* No unpredictable behavior. */
321};
322
323enum mve_undefined
324{
ed63aa17 325 UNDEF_SIZE, /* undefined size. */
bf0b396d 326 UNDEF_SIZE_0, /* undefined because size == 0. */
c507f10b 327 UNDEF_SIZE_2, /* undefined because size == 2. */
aef6d006
AV		 328 UNDEF_SIZE_3, /* undefined because size == 3. */
329 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
14b456f2 330 UNDEF_SIZE_NOT_0, /* undefined because size != 0. */
ef1576a1
AV		 331 UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
332 UNDEF_SIZE_NOT_3, /* undefined because size != 3. */
333 UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and
334 size == 0. */
335 UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and
336 size == 1. */
337 UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
bf0b396d
AV		 338 UNDEF_VCVT_IMM6, /* imm6 < 32. */
339 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
c507f10b
AV		 340 UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and
341 op1 == (0 or 1). */
342 UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and
343 op2 == 0 and op1 == (0 or 1). */
344 UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode
345 in {0xx1, x0x1}. */
d3b63143 346 UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */
73cd51e5
AV		 347 UNDEF_NONE /* no undefined behavior. */
348};
349
6b5d3a4d
ZW		 350struct opcode32
351{
823d2571
TG		 352 arm_feature_set arch; /* Architecture defining this insn. */
353 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 354 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 355 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 356};
357
4934a27c
MM		 358struct cdeopcode32
359{
360 arm_feature_set arch; /* Architecture defining this insn. */
361 uint8_t coproc_shift; /* coproc is this far into op. */
362 uint16_t coproc_mask; /* Length of coproc field in op. */
363 unsigned long value; /* If arch is 0 then value is a sentinel. */
364 unsigned long mask; /* Recognise insn if (op & mask) == value. */
365 const char * assembler; /* How to disassemble this insn. */
366};
367
73cd51e5
AV		 368/* MVE opcodes. */
369
370struct mopcode32
371{
372 arm_feature_set arch; /* Architecture defining this insn. */
373 enum mve_instructions mve_op; /* Specific mve instruction for faster
374 decoding. */
375 unsigned long value; /* If arch is 0 then value is a sentinel. */
376 unsigned long mask; /* Recognise insn if (op & mask) == value. */
377 const char * assembler; /* How to disassemble this insn. */
378};
379
6b0dd094
AV		 380enum isa {
381 ANY,
382 T32,
383 ARM
384};
385
386
387/* Shared (between Arm and Thumb mode) opcode. */
388struct sopcode32
389{
390 enum isa isa; /* Execution mode instruction availability. */
391 arm_feature_set arch; /* Architecture defining this insn. */
392 unsigned long value; /* If arch is 0 then value is a sentinel. */
393 unsigned long mask; /* Recognise insn if (op & mask) == value. */
394 const char * assembler; /* How to disassemble this insn. */
395};
396
6b5d3a4d
ZW		 397struct opcode16
398{
823d2571 399 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 400 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 401 const char *assembler; /* How to disassemble this insn. */
402};
b7693d02 403
8f06b2d8 404/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 405
2fbad815 406 %% %
4a5329c6 407
c22aaad1 408 %c print condition code (always bits 28-31 in ARM mode)
aab2c27d 409 %b print condition code allowing cp_num == 9
37b37b2d 410 %q print shifter argument
e2efe87d
MGD		 411 %u print condition code (unconditional in ARM mode,
412 UNPREDICTABLE if not AL in Thumb)
4a5329c6 413 %A print address for ldc/stc/ldf/stf instruction
16980d0b 414 %B print vstm/vldm register list
efd6b359 415 %C print vscclrm register list
4a5329c6 416 %I print cirrus signed shift immediate: bits 0..3|4..6
32c36c3c
AV		 417 %J print register for VLDR instruction
418 %K print address for VLDR instruction
4a5329c6
ZW		 419 %F print the COUNT field of a LFM/SFM instruction.
420 %P print floating point precision in arithmetic insn
421 %Q print floating point precision in ldf/stf insn
422 %R print floating point rounding mode
423
33399f07 424 %<bitfield>c print as a condition code (for vsel)
4a5329c6 425 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 426 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
427 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 428 %<bitfield>d print the bitfield in decimal
16980d0b 429 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 430 %<bitfield>x print the bitfield in hex
431 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 432 %<bitfield>f print a floating point constant if >7 else a
433 floating point register
4a5329c6
ZW		 434 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
435 %<bitfield>g print as an iWMMXt 64-bit register
436 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 437 %<bitfield>D print as a NEON D register
438 %<bitfield>Q print as a NEON Q register
c28eeff2 439 %<bitfield>V print as a NEON D or Q register
6f1c2142 440 %<bitfield>E print a quarter-float immediate value
4a5329c6 441
16980d0b 442 %y<code> print a single precision VFP reg.
2fbad815 443 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 444 %z<code> print a double precision VFP reg
2fbad815 445 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 446
16980d0b
JB		 447 %<bitfield>'c print specified char iff bitfield is all ones
448 %<bitfield>`c print specified char iff bitfield is all zeroes
449 %<bitfield>?ab... select from array of values in big endian order
43e65147 450
2fbad815 451 %L print as an iWMMXt N/M width field.
4a5329c6 452 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 453 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 454 versions.
455 %i print 5-bit immediate in bits 8,3..0
456 (print "32" when 0)
fe56b6ce 457 %r print register offset address for wldt/wstr instruction. */
2fbad815 458
21d799b5 459enum opcode_sentinel_enum
05413229
NC		 460{
461 SENTINEL_IWMMXT_START = 1,
462 SENTINEL_IWMMXT_END,
463 SENTINEL_GENERIC_START
464} opcode_sentinels;
465
aefd8a40 466#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
0b347048
TC		 467#define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
468#define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
c1e26897 469#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 470
8f06b2d8 471/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 472
4934a27c
MM		 473/* print_insn_cde recognizes the following format control codes:
474
475 %% %
476
477 %a print 'a' iff bit 28 is 1
478 %p print bits 8-10 as coprocessor
479 %<bitfield>d print as decimal
480 %<bitfield>r print as an ARM register
481 %<bitfield>n print as an ARM register but r15 is APSR_nzcv
482 %<bitfield>T print as an ARM register + 1
483 %<bitfield>R as %r but r13 is UNPREDICTABLE
484 %<bitfield>S as %r but rX where X > 10 is UNPREDICTABLE
485 %j print immediate taken from bits (16..21,7,0..5)
486 %k print immediate taken from bits (20..21,7,0..5).
487 %l print immediate taken from bits (20..22,7,4..5). */
488
489/* At the moment there is only one valid position for the coprocessor number,
490 and hence that's encoded in the macro below. */
491#define CDE_OPCODE(ARCH, VALUE, MASK, ASM) \
492 { ARCH, 8, 7, VALUE, MASK, ASM }
493static const struct cdeopcode32 cde_opcodes[] =
494{
495 /* Custom Datapath Extension instructions. */
496 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
497 0xee000000, 0xefc00840,
498 "cx1%a\t%p, %12-15n, #%0-5,7,16-21d"),
499 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
500 0xee000040, 0xefc00840,
501 "cx1d%a\t%p, %12-15S, %12-15T, #%0-5,7,16-21d"),
502
503 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
504 0xee400000, 0xefc00840,
505 "cx2%a\t%p, %12-15n, %16-19n, #%0-5,7,20-21d"),
506 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
507 0xee400040, 0xefc00840,
508 "cx2d%a\t%p, %12-15S, %12-15T, %16-19n, #%0-5,7,20-21d"),
509
510 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
511 0xee800000, 0xef800840,
512 "cx3%a\t%p, %0-3n, %16-19n, %12-15n, #%4-5,7,20-22d"),
513 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
514 0xee800040, 0xef800840,
515 "cx3d%a\t%p, %0-3S, %0-3T, %16-19n, %12-15n, #%4-5,7,20-22d"),
516
517 CDE_OPCODE (ARM_FEATURE_CORE_LOW (0), 0, 0, 0)
518
519};
520
6b0dd094 521static const struct sopcode32 coprocessor_opcodes[] =
2fbad815 522{
2fbad815 523 /* XScale instructions. */
6b0dd094 524 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 525 0x0e200010, 0x0fff0ff0,
526 "mia%c\tacc0, %0-3r, %12-15r"},
6b0dd094 527 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 528 0x0e280010, 0x0fff0ff0,
529 "miaph%c\tacc0, %0-3r, %12-15r"},
6b0dd094 530 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 531 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
6b0dd094 532 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 533 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
6b0dd094 534 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 535 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 536
2fbad815 537 /* Intel Wireless MMX technology instructions. */
6b0dd094
AV		 538 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
539 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
823d2571 540 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
6b0dd094 541 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 542 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
6b0dd094 543 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 544 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
6b0dd094 545 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 546 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
6b0dd094 547 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 548 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
6b0dd094 549 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 550 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
6b0dd094 551 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 552 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
6b0dd094 553 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 554 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 555 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 556 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 557 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 558 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 559 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 560 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
6b0dd094 561 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 562 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
6b0dd094 563 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 564 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
6b0dd094 565 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 566 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
6b0dd094 567 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 568 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
6b0dd094 569 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 570 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 571 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 572 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 573 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 574 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 575 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 576 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 577 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 578 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 579 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 580 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
6b0dd094 581 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 582 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 583 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 584 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 585 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 586 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 587 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 588 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 589 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 590 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 591 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 592 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 593 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 594 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
6b0dd094 595 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 596 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
6b0dd094 597 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 598 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
6b0dd094 599 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 600 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 601 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 602 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 603 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 604 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 605 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 606 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 607 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 608 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
6b0dd094 609 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 610 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 611 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 612 0x0e800120, 0x0f800ff0,
613 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 614 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 615 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 616 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 617 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 618 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 619 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 620 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 621 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 622 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 623 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 624 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 625 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 626 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 627 0x0e8000a0, 0x0f800ff0,
628 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 629 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 630 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 631 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 632 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 633 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 634 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 635 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 636 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 637 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 638 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 639 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 640 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 641 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 642 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 643 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 644 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 645 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 646 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
6b0dd094 647 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 648 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 649 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 650 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 651 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 652 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 653 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 654 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 655 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 656 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 657 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 658 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 659 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 660 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 661 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 662 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 663 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 664 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 665 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 666 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
6b0dd094 667 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 668 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
6b0dd094 669 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 670 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
6b0dd094 671 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 672 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 673 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 674 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 675 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 676 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 677 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 678 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
6b0dd094 679 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 680 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
6b0dd094 681 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 682 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
6b0dd094 683 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 684 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 685 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 686 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 687 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 688 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 689 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 690 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 691 {ANY, ARM_FEATURE_CORE_LOW (0),
823d2571 692 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 693
fe56b6ce 694 /* Floating point coprocessor (FPA) instructions. */
6b0dd094 695 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 696 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 697 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 698 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 699 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 700 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 701 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 702 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 703 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 704 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 705 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 706 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 707 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 708 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 709 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 710 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 711 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 712 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 713 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 714 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 715 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 716 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 717 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 718 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 719 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 720 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 721 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 722 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 723 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 724 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 725 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 726 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 727 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 728 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 729 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 730 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
6b0dd094 731 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 732 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
6b0dd094 733 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 734 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 735 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 736 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
6b0dd094 737 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 738 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
6b0dd094 739 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 740 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
6b0dd094 741 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 742 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
6b0dd094 743 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 744 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 745 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 746 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 747 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 748 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 749 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 750 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 751 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 752 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
6b0dd094 753 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 754 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
6b0dd094 755 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 756 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
6b0dd094 757 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 758 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
6b0dd094 759 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 760 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
6b0dd094 761 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 762 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
6b0dd094 763 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 764 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
6b0dd094 765 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 766 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
6b0dd094 767 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 768 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
6b0dd094 769 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 770 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
6b0dd094 771 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 772 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
6b0dd094 773 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 774 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
6b0dd094 775 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 776 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
6b0dd094 777 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 778 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
6b0dd094 779 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 780 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 781
efd6b359
AV		 782 /* Armv8.1-M Mainline instructions. */
783 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
784 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
785 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
786 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
787
16a1fa25 788 /* ARMv8-M Mainline Security Extensions instructions. */
6b0dd094 789 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25 790 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
6b0dd094 791 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25
TP		 792 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
793
fe56b6ce 794 /* Register load/store. */
6b0dd094 795 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 796 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
6b0dd094 797 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 798 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
6b0dd094 799 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 800 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
6b0dd094 801 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 802 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
6b0dd094 803 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 804 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
6b0dd094 805 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 806 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
6b0dd094 807 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 808 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
6b0dd094 809 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 810 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
6b0dd094 811 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 812 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
6b0dd094 813 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 814 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
6b0dd094 815 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 816 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
6b0dd094 817 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 818 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
6b0dd094 819 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 820 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
6b0dd094 821 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 822 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
6b0dd094 823 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 824 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
6b0dd094 825 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 826 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
32c36c3c
AV		 827 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
828 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
829 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
830 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
823d2571 831
6b0dd094 832 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 833 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 834 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 835 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 836 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 837 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
6b0dd094 838 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 839 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 840
fe56b6ce 841 /* Data transfer between ARM and NEON registers. */
6b0dd094 842 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 843 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
6b0dd094 844 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 845 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
6b0dd094 846 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 847 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
6b0dd094 848 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 849 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
6b0dd094 850 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 851 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
6b0dd094 852 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 853 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
6b0dd094 854 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 855 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
6b0dd094 856 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 857 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 858 /* Half-precision conversion instructions. */
6b0dd094 859 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 860 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
6b0dd094 861 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 862 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
6b0dd094 863 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 864 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
6b0dd094 865 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 866 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 867
fe56b6ce 868 /* Floating point coprocessor (VFP) instructions. */
6b0dd094 869 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 870 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
2da2eaf4 871 {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
823d2571 872 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
ba6cd17f
SD		 873 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
874 0x0ee20a10, 0x0fff0fff, "vmsr%c\tfpscr_nzcvqc, %12-15r"},
6b0dd094 875 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 876 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
6b0dd094 877 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 878 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
6b0dd094 879 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 880 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
6b0dd094 881 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 882 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
6b0dd094 883 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 884 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
6b0dd094 885 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 886 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
2da2eaf4 887 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ba6cd17f 888 0x0eec0a10, 0x0fff0fff, "vmsr%c\tvpr, %12-15r"},
2da2eaf4 889 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ba6cd17f
SD		 890 0x0eed0a10, 0x0fff0fff, "vmsr%c\tp0, %12-15r"},
891 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
892 0x0eee0a10, 0x0fff0fff, "vmsr%c\tfpcxt_ns, %12-15r"},
893 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
894 0x0eef0a10, 0x0fff0fff, "vmsr%c\tfpcxt_s, %12-15r"},
6b0dd094 895 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 896 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
6b0dd094 897 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 898 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
2da2eaf4 899 {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
823d2571 900 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
ba6cd17f
SD		 901 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
902 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr_nzcvqc"},
6b0dd094 903 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 904 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
6b0dd094 905 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 906 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
6b0dd094 907 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 908 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
6b0dd094 909 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 910 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
6b0dd094 911 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 912 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
6b0dd094 913 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 914 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
2da2eaf4 915 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ba6cd17f 916 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, vpr"},
2da2eaf4 917 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ba6cd17f
SD		 918 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, p0"},
919 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
920 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_ns"},
921 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
922 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_s"},
6b0dd094 923 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 924 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
6b0dd094 925 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 926 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
6b0dd094 927 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 928 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
6b0dd094 929 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 930 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
6b0dd094 931 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 932 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
6b0dd094 933 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 934 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
6b0dd094 935 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 936 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
6b0dd094 937 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 938 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
6b0dd094 939 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 940 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
6b0dd094 941 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 942 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
6b0dd094 943 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 944 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
6b0dd094 945 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 946 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
6b0dd094 947 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 948 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
6b0dd094 949 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 950 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
6b0dd094 951 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 952 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
6b0dd094 953 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 954 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
6b0dd094 955 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 956 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
6b0dd094 957 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 958 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
6b0dd094 959 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 960 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
6b0dd094 961 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 962 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
6b0dd094 963 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 964 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
6b0dd094 965 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 966 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
6b0dd094 967 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 968 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 969 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 970 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
6b0dd094 971 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 972 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
6b0dd094 973 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 974 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
6b0dd094 975 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 976 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
6b0dd094 977 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 978 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
6b0dd094 979 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 980 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
6b0dd094 981 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6f1c2142 982 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
6b0dd094 983 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6f1c2142 984 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
6b0dd094 985 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 986 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
6b0dd094 987 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 988 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
6b0dd094 989 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 990 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
6b0dd094 991 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 992 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 993 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 994 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 995 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 996 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 997 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 998 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 999 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1000 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 1001 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1002 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 1003 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1004 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 1005 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1006 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 1007 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1008 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 1009 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1010 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 1011 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1012 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 1013 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1014 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 1015 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1016 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
6b0dd094 1017 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1018 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
6b0dd094 1019 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1020 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
6b0dd094 1021 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1022 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
6b0dd094 1023 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1024 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
6b0dd094 1025 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1026 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 1027
1028 /* Cirrus coprocessor instructions. */
6b0dd094 1029 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1030 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 1031 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1032 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 1033 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1034 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 1035 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1036 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 1037 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1038 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 1039 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1040 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 1041 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1042 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 1043 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1044 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 1045 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1046 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 1047 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1048 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 1049 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1050 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 1051 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1052 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 1053 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1054 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 1055 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1056 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 1057 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1058 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 1059 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1060 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 1061 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1062 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
6b0dd094 1063 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1064 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
6b0dd094 1065 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1066 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
6b0dd094 1067 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1068 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
6b0dd094 1069 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1070 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
6b0dd094 1071 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1072 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
6b0dd094 1073 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1074 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 1075 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1076 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
6b0dd094 1077 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1078 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 1079 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1080 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
6b0dd094 1081 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1082 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1083 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1084 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1085 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1086 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1087 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1088 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1089 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1090 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1091 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1092 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1093 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1094 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1095 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1096 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1097 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1098 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
6b0dd094 1099 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1100 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
6b0dd094 1101 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1102 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
6b0dd094 1103 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1104 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
6b0dd094 1105 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1106 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1107 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1108 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1109 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1110 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
6b0dd094 1111 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1112 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
6b0dd094 1113 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1114 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
6b0dd094 1115 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1116 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
6b0dd094 1117 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1118 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
6b0dd094 1119 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1120 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
6b0dd094 1121 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1122 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 1123 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1124 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 1125 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1126 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 1127 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1128 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 1129 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1130 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
6b0dd094 1131 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1132 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
6b0dd094 1133 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1134 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
6b0dd094 1135 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1136 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
6b0dd094 1137 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1138 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
6b0dd094 1139 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1140 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
6b0dd094 1141 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1142 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1143 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1144 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1145 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1146 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1147 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1148 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1149 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1150 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1151 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1152 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1153 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1154 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1155 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1156 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1157 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1158 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1159 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1160 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1161 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1162 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1163 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1164 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1165 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1166 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 1167 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1168 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 1169 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1170 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 1171 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1172 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 1173 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1174 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1175 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1176 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1177 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1178 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1179 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1180 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1181 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1182 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1183 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1184 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1185 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1186 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1187 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1188 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1189 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1190 0x0e000600, 0x0ff00f10,
1191 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1192 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1193 0x0e100600, 0x0ff00f10,
1194 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1195 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1196 0x0e200600, 0x0ff00f10,
1197 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1198 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1199 0x0e300600, 0x0ff00f10,
1200 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 1201
62f3b8c8 1202 /* VFP Fused multiply add instructions. */
6b0dd094 1203 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1204 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1205 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1206 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1207 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1208 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1209 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1210 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
6b0dd094 1211 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1212 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1213 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1214 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1215 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1216 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1217 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1218 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 1219
33399f07 1220 /* FP v5. */
6b0dd094 1221 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1222 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
6b0dd094 1223 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1224 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
6b0dd094 1225 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1226 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1227 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1228 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1229 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1230 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1231 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1232 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1233 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1234 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
6b0dd094 1235 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1236 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
6b0dd094 1237 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1238 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
6b0dd094 1239 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1240 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
6b0dd094 1241 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1242 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
6b0dd094 1243 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1244 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 1245
6b0dd094 1246 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
c28eeff2 1247 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
6b0dd094 1248 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1249 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1250 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1251 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1252 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1253 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1254 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1255 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1256 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1257 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1258 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1259 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1260 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1261 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
6b0dd094 1262 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1263 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
6b0dd094 1264 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1265 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
6b0dd094 1266 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1267 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
c28eeff2 1268
aab2c27d
MM		 1269 /* BFloat16 instructions. */
1270 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1271 0x0eb30940, 0x0fbf0f50, "vcvt%7?tb%b.bf16.f32\t%y1, %y0"},
1272
c604a79a 1273 /* Dot Product instructions in the space of coprocessor 13. */
6b0dd094 1274 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a 1275 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
6b0dd094 1276 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
aab2c27d 1277 0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
c604a79a 1278
dec41383 1279 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
6b0dd094 1280 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1281 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1282 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1283 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1284 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1285 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1286 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1287 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1288 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1289 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1290 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1291 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1292 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1293 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
6b0dd094 1294 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383
JW		 1295 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1296
b0c11777
RL		 1297 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1298 cp_num: bit <11:8> == 0b1001.
1299 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
6b0dd094 1300 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1301 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
6b0dd094 1302 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1303 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
6b0dd094 1304 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1305 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
6b0dd094 1306 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1307 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
6b0dd094 1308 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1309 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 1310 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1311 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
6b0dd094 1312 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1313 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
6b0dd094 1314 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1315 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
6b0dd094 1316 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1317 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
6b0dd094 1318 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1319 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
6b0dd094 1320 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1321 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1322 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1323 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1324 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1325 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1326 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1327 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1328 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1329 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
6b0dd094 1330 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1331 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
6b0dd094 1332 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1333 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
6b0dd094 1334 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1335 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
6b0dd094 1336 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1337 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1338 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1339 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1340 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1341 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1342 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1343 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1344 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1345 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
6b0dd094 1346 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1347 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
6b0dd094 1348 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1349 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
6b0dd094 1350 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1351 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1352 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1353 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
6b0dd094 1354 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1355 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1356 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1357 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1358 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1359 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1360 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1361 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
6b0dd094 1362 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1363 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
6b0dd094 1364 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1365 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
6b0dd094 1366 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1367 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
6b0dd094 1368 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777
RL		 1369 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1370
49e8a725 1371 /* ARMv8.3 javascript conversion instruction. */
6b0dd094 1372 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
49e8a725
SN		 1373 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1374
6b0dd094 1375 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 1376};
1377
33593eaf
MM		 1378/* Generic coprocessor instructions. These are only matched if a more specific
1379 SIMD or co-processor instruction does not match first. */
1380
1381static const struct sopcode32 generic_coprocessor_opcodes[] =
1382{
1383 /* Generic coprocessor instructions. */
1384 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1385 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
1386 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1387 0x0c500000, 0x0ff00000,
1388 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1389 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1390 0x0e000000, 0x0f000010,
1391 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1392 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1393 0x0e10f010, 0x0f10f010,
1394 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
1395 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1396 0x0e100010, 0x0f100010,
1397 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1398 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1399 0x0e000010, 0x0f100010,
1400 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1401 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1402 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
1403 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1404 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
1405
1406 /* V6 coprocessor instructions. */
1407 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1408 0xfc500000, 0xfff00000,
1409 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1410 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1411 0xfc400000, 0xfff00000,
1412 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
1413
1414 /* V5 coprocessor instructions. */
1415 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1416 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1417 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1418 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1419 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1420 0xfe000000, 0xff000010,
1421 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1422 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1423 0xfe000010, 0xff100010,
1424 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1425 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1426 0xfe100010, 0xff100010,
1427 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1428
1429 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1430};
1431
16980d0b
JB		 1432/* Neon opcode table: This does not encode the top byte -- that is
1433 checked by the print_insn_neon routine, as it depends on whether we are
1434 doing thumb32 or arm32 disassembly. */
1435
1436/* print_insn_neon recognizes the following format control codes:
1437
1438 %% %
1439
c22aaad1 1440 %c print condition code
e2efe87d
MGD		 1441 %u print condition code (unconditional in ARM mode,
1442 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 1443 %A print v{st,ld}[1234] operands
1444 %B print v{st,ld}[1234] any one operands
1445 %C print v{st,ld}[1234] single->all operands
1446 %D print scalar
1447 %E print vmov, vmvn, vorr, vbic encoded constant
1448 %F print vtbl,vtbx register list
1449
1450 %<bitfield>r print as an ARM register
1451 %<bitfield>d print the bitfield in decimal
1452 %<bitfield>e print the 2^N - bitfield in decimal
1453 %<bitfield>D print as a NEON D register
1454 %<bitfield>Q print as a NEON Q register
1455 %<bitfield>R print as a NEON D or Q register
1456 %<bitfield>Sn print byte scaled width limited by n
1457 %<bitfield>Tn print short scaled width limited by n
1458 %<bitfield>Un print long scaled width limited by n
43e65147 1459
16980d0b
JB		 1460 %<bitfield>'c print specified char iff bitfield is all ones
1461 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1462 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1463
1464static const struct opcode32 neon_opcodes[] =
1465{
fe56b6ce 1466 /* Extract. */
823d2571
TG		 1467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1468 0xf2b00840, 0xffb00850,
1469 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1470 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1471 0xf2b00000, 0xffb00810,
1472 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 1473
9743db03
AV		 1474 /* Data transfer between ARM and NEON registers. */
1475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1476 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1478 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1480 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1482 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1484 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1486 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1487
fe56b6ce 1488 /* Move data element to all lanes. */
823d2571
TG		 1489 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1490 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1492 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1494 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 1495
fe56b6ce 1496 /* Table lookup. */
823d2571
TG		 1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1498 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1499 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1500 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1501
8e79c3df 1502 /* Half-precision conversions. */
823d2571
TG		 1503 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1504 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1505 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1506 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1507
1508 /* NEON fused multiply add instructions. */
823d2571 1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1510 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1511 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1512 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1514 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1515 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1516 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1517
aab2c27d
MM		 1518 /* BFloat16 instructions. */
1519 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1520 0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1521 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1522 0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1523 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1524 0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1525 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1526 0xf3b60640, 0xffbf0fd0, "vcvt%c.bf16.f32\t%12-15,22D, %0-3,5Q"},
1527 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1528 0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1529 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1530 0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-2D[%3,5d]"},
1531
616ce08e
MM		 1532 /* Matrix Multiply instructions. */
1533 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1534 0xfc200c40, 0xffb00f50, "vsmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1536 0xfc200c50, 0xffb00f50, "vummla.u8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1537 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1538 0xfca00c40, 0xffb00f50, "vusmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1539 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1540 0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1541 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1542 0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1543 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1544 0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1545
fe56b6ce 1546 /* Two registers, miscellaneous. */
823d2571
TG		 1547 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1548 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1549 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1550 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1551 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1552 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1553 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1554 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1555 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1556 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1557 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1558 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1559 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1560 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1561 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1562 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1563 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1564 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1565 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1566 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1567 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1568 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1569 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1570 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1571 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1572 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1573 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1574 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1576 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1577 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1578 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1579 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1580 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1581 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1582 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1583 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1584 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1585 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1586 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1587 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1588 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1589 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1590 0xf3b20300, 0xffb30fd0,
1591 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1592 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1593 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1594 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1595 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1596 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1597 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1598 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1599 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1600 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1601 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1602 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1603 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1604 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1605 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1606 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1607 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1608 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1609 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1610 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1611 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1612 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1613 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1614 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1615 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1616 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1617 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1618 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1619 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1621 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1622 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1623 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1624 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1625 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1626 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1627 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1628 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1629 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1630 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1631 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1632 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1633 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1634 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1635 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1636 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1637 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1638 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301 1639 0xf3bb0600, 0xffbf0e10,
823d2571 1640 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1641 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1642 0xf3b70600, 0xffbf0e10,
1643 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
16980d0b 1644
fe56b6ce 1645 /* Three registers of the same length. */
823d2571
TG		 1646 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1647 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1648 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1649 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1650 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1651 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1652 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1653 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1654 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1655 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1656 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1657 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1658 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1659 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1660 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1661 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1662 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1663 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1664 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1665 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1666 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1667 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1668 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1669 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1670 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1671 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1672 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1673 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1674 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1675 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1676 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1677 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1678 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1679 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1680 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1681 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1682 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1683 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1685 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1686 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1687 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1688 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1689 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1690 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1691 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1692 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1693 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1694 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1695 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1696 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1697 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1698 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1699 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1700 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1701 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1702 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1703 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1704 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1705 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1706 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1707 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1708 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1709 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1710 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1711 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1712 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1713 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1714 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1715 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1716 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1717 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1718 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1719 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1720 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1721 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1722 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1723 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1724 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1725 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1726 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1727 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1728 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1729 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1730 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1731 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1732 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1733 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1734 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1735 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1736 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1737 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1738 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1739 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1740 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1741 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1742 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1743 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1744 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1745 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1746 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1747 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1748 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1749 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1750 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1751 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1753 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1754 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1755 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1756 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1757 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1758 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1759 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1760 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1761 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1762 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1763 0xf2000b00, 0xff800f10,
1764 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1765 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1766 0xf2000b10, 0xff800f10,
1767 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1768 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1769 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1770 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1771 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1772 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1773 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1774 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1775 0xf3000b00, 0xff800f10,
1776 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1777 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1778 0xf2000000, 0xfe800f10,
1779 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1780 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1781 0xf2000010, 0xfe800f10,
1782 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1783 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1784 0xf2000100, 0xfe800f10,
1785 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1786 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1787 0xf2000200, 0xfe800f10,
1788 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1789 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1790 0xf2000210, 0xfe800f10,
1791 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1792 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1793 0xf2000300, 0xfe800f10,
1794 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1795 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1796 0xf2000310, 0xfe800f10,
1797 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1798 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1799 0xf2000400, 0xfe800f10,
1800 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1801 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1802 0xf2000410, 0xfe800f10,
1803 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1804 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1805 0xf2000500, 0xfe800f10,
1806 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1807 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1808 0xf2000510, 0xfe800f10,
1809 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1810 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1811 0xf2000600, 0xfe800f10,
1812 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1813 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1814 0xf2000610, 0xfe800f10,
1815 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1816 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1817 0xf2000700, 0xfe800f10,
1818 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1819 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1820 0xf2000710, 0xfe800f10,
1821 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1822 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1823 0xf2000910, 0xfe800f10,
1824 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1825 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1826 0xf2000a00, 0xfe800f10,
1827 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1828 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1829 0xf2000a10, 0xfe800f10,
1830 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1831 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1832 0xf3000b10, 0xff800f10,
1833 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1834 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1835 0xf3000c10, 0xff800f10,
1836 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1837
fe56b6ce 1838 /* One register and an immediate value. */
823d2571
TG		 1839 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1840 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1841 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1842 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1843 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1844 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1845 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1846 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1847 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1848 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1849 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1850 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1851 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1852 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1853 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1854 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1855 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1856 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1857 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1858 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1859 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1860 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1861 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1862 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1863 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1864 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1865
fe56b6ce 1866 /* Two registers and a shift amount. */
823d2571
TG		 1867 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1868 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1869 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1870 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1871 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1872 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1873 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1874 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1875 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1876 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1877 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1878 0xf2880950, 0xfeb80fd0,
1879 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1880 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1881 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1882 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1883 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1884 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1885 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1886 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1887 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1888 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1889 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1890 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1891 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1892 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1893 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1894 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1895 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1896 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1897 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1898 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1899 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1900 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1901 0xf2900950, 0xfeb00fd0,
1902 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1903 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1904 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1905 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1906 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1907 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1908 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1909 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1910 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1911 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1912 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1913 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1914 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1915 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1916 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1917 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1918 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1919 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1920 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1921 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1922 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1923 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1924 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1925 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1926 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1927 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1928 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1929 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1930 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1931 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1932 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1933 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1934 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1935 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1936 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1937 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1938 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1939 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1940 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1941 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1942 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1943 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1944 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1945 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1946 0xf2a00950, 0xfea00fd0,
1947 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1948 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1949 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1950 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1951 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1952 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1953 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1954 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1955 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1956 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1957 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1958 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1959 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1960 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1961 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1962 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1963 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1964 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1965 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1966 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1967 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1968 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1969 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1970 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1971 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1972 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1973 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1974 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1975 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1976 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1977 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1978 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1979 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1980 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1981 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1982 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1983 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1984 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1985 0xf2a00e10, 0xfea00e90,
1986 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
cc933301
JW		 1987 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1988 0xf2a00c10, 0xfea00e90,
1989 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 1990
fe56b6ce 1991 /* Three registers of different lengths. */
823d2571
TG		 1992 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1993 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1994 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1995 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1996 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1997 0xf2800400, 0xff800f50,
1998 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1999 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2000 0xf2800600, 0xff800f50,
2001 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2002 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2003 0xf2800900, 0xff800f50,
2004 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2005 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2006 0xf2800b00, 0xff800f50,
2007 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2008 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2009 0xf2800d00, 0xff800f50,
2010 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2011 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2012 0xf3800400, 0xff800f50,
2013 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2014 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2015 0xf3800600, 0xff800f50,
2016 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2017 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2018 0xf2800000, 0xfe800f50,
2019 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2020 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2021 0xf2800100, 0xfe800f50,
2022 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
2023 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2024 0xf2800200, 0xfe800f50,
2025 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2026 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2027 0xf2800300, 0xfe800f50,
2028 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
2029 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2030 0xf2800500, 0xfe800f50,
2031 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2032 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2033 0xf2800700, 0xfe800f50,
2034 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2035 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2036 0xf2800800, 0xfe800f50,
2037 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2038 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2039 0xf2800a00, 0xfe800f50,
2040 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2041 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2042 0xf2800c00, 0xfe800f50,
2043 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 2044
fe56b6ce 2045 /* Two registers and a scalar. */
823d2571
TG		 2046 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2047 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2048 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2049 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
2050 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2051 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 2052 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2053 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2054 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2055 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2056 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2057 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2058 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2059 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 2060 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2061 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2062 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2063 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2064 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2065 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
2066 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2067 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 2068 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2069 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2070 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2071 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2072 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2073 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2074 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2075 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2076 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2077 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2078 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2079 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 2080 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2081 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2082 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2083 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2084 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2085 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 2086 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2087 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2088 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2089 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2090 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2091 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 2092 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2093 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2094 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2095 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2096 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2097 0xf2800240, 0xfe800f50,
2098 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2099 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2100 0xf2800640, 0xfe800f50,
2101 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2102 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2103 0xf2800a40, 0xfe800f50,
2104 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 2105 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2106 0xf2800e40, 0xff800f50,
2107 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2108 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2109 0xf2800f40, 0xff800f50,
2110 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2111 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2112 0xf3800e40, 0xff800f50,
2113 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2114 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2115 0xf3800f40, 0xff800f50,
2116 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
2117 },
16980d0b 2118
fe56b6ce 2119 /* Element and structure load/store. */
823d2571
TG		 2120 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2121 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
2122 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2123 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
2124 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2125 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
2126 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2127 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
2128 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2129 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
2130 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2131 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2132 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2133 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2134 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2135 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2136 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2137 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2138 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2139 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2140 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2141 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2142 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2143 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2144 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2145 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2146 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2147 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2148 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2149 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
2150 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2151 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
2152 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2153 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
2154 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2155 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
2156 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2157 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
2158
2159 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 2160};
2161
73cd51e5
AV		 2162/* mve opcode table. */
2163
2164/* print_insn_mve recognizes the following format control codes:
2165
2166 %% %
2167
ef1576a1
AV		 2168 %a print '+' or '-' or imm offset in vldr[bhwd] and
2169 vstr[bhwd]
9743db03 2170 %c print condition code
aef6d006
AV		 2171 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
2172 %u print 'U' (unsigned) or 'S' for various mve instructions
143275ea 2173 %i print MVE predicate(s) for vpt and vpst
23d00a41 2174 %j print a 5-bit immediate from hw2[14:12,7:6]
08132bdd 2175 %k print 48 if the 7th position bit is set else print 64.
bf0b396d 2176 %m print rounding mode for vcvt and vrint
143275ea 2177 %n print vector comparison code for predicated instruction
bf0b396d 2178 %s print size for various vcvt instructions
143275ea
AV		 2179 %v print vector predicate for instruction in predicated
2180 block
ef1576a1 2181 %o print offset scaled for vldr[hwd] and vstr[hwd]
04d54ace
AV		 2182 %w print writeback mode for MVE v{st,ld}[24]
2183 %B print v{st,ld}[24] any one operands
c507f10b
AV		 2184 %E print vmov, vmvn, vorr, vbic encoded constant
2185 %N print generic index for vmov
14925797 2186 %T print bottom ('b') or top ('t') of source register
d3b63143 2187 %X print exchange field in vmla* instructions
04d54ace 2188
9743db03 2189 %<bitfield>r print as an ARM register
04d54ace 2190 %<bitfield>d print the bitfield in decimal
d3b63143 2191 %<bitfield>A print accumulate or not
e39c1607
SD		 2192 %<bitfield>c print bitfield as a condition code
2193 %<bitfield>C print bitfield as an inverted condition code
143275ea 2194 %<bitfield>Q print as a MVE Q register
c507f10b 2195 %<bitfield>F print as a MVE S register
143275ea
AV		 2196 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
2197 UNPREDICTABLE
23d00a41
SD		 2198
2199 %<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE
143275ea 2200 %<bitfield>s print size for vector predicate & non VMOV instructions
66dcaa5d 2201 %<bitfield>I print carry flag or not
ef1576a1 2202 %<bitfield>i print immediate for vstr/vldr reg +/- imm
1c8f2df8 2203 %<bitfield>h print high half of 64-bit destination reg
bf0b396d 2204 %<bitfield>k print immediate for vector conversion instruction
1c8f2df8 2205 %<bitfield>l print low half of 64-bit destination reg
897b9bbc 2206 %<bitfield>o print rotate value for vcmul
1c8f2df8 2207 %<bitfield>u print immediate value for vddup/vdwdup
c507f10b 2208 %<bitfield>x print the bitfield in hex.
1c8f2df8 2209 */
73cd51e5
AV		 2210
2211static const struct mopcode32 mve_opcodes[] =
2212{
143275ea
AV		 2213 /* MVE. */
2214
2da2eaf4 2215 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2216 MVE_VPST,
2217 0xfe310f4d, 0xffbf1fff,
2218 "vpst%i"
2219 },
2220
2221 /* Floating point VPT T1. */
2da2eaf4 2222 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2223 MVE_VPT_FP_T1,
2224 0xee310f00, 0xefb10f50,
2225 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2226 /* Floating point VPT T2. */
2da2eaf4 2227 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2228 MVE_VPT_FP_T2,
2229 0xee310f40, 0xefb10f50,
2230 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2231
2232 /* Vector VPT T1. */
2da2eaf4 2233 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2234 MVE_VPT_VEC_T1,
2235 0xfe010f00, 0xff811f51,
2236 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2237 /* Vector VPT T2. */
2da2eaf4 2238 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2239 MVE_VPT_VEC_T2,
2240 0xfe010f01, 0xff811f51,
2241 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2242 /* Vector VPT T3. */
2da2eaf4 2243 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2244 MVE_VPT_VEC_T3,
2245 0xfe011f00, 0xff811f50,
2246 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2247 /* Vector VPT T4. */
2da2eaf4 2248 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2249 MVE_VPT_VEC_T4,
2250 0xfe010f40, 0xff811f70,
2251 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2252 /* Vector VPT T5. */
2da2eaf4 2253 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2254 MVE_VPT_VEC_T5,
2255 0xfe010f60, 0xff811f70,
2256 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2257 /* Vector VPT T6. */
2da2eaf4 2258 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2259 MVE_VPT_VEC_T6,
2260 0xfe011f40, 0xff811f50,
2261 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2262
c507f10b 2263 /* Vector VBIC immediate. */
2da2eaf4 2264 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2265 MVE_VBIC_IMM,
2266 0xef800070, 0xefb81070,
2267 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2268
2269 /* Vector VBIC register. */
2da2eaf4 2270 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2271 MVE_VBIC_REG,
2272 0xef100150, 0xffb11f51,
2273 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2274
66dcaa5d 2275 /* Vector VABAV. */
2da2eaf4 2276 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2277 MVE_VABAV,
2278 0xee800f01, 0xefc10f51,
2279 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2280
2281 /* Vector VABD floating point. */
2da2eaf4 2282 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2283 MVE_VABD_FP,
2284 0xff200d40, 0xffa11f51,
2285 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2286
2287 /* Vector VABD. */
2da2eaf4 2288 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2289 MVE_VABD_VEC,
2290 0xef000740, 0xef811f51,
2291 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2292
2293 /* Vector VABS floating point. */
2da2eaf4 2294 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2295 MVE_VABS_FP,
2296 0xFFB10740, 0xFFB31FD1,
2297 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2298 /* Vector VABS. */
2da2eaf4 2299 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2300 MVE_VABS_VEC,
2301 0xffb10340, 0xffb31fd1,
2302 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2303
2304 /* Vector VADD floating point T1. */
2da2eaf4 2305 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2306 MVE_VADD_FP_T1,
2307 0xef000d40, 0xffa11f51,
2308 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2309 /* Vector VADD floating point T2. */
2da2eaf4 2310 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2311 MVE_VADD_FP_T2,
2312 0xee300f40, 0xefb11f70,
2313 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2314 /* Vector VADD T1. */
2da2eaf4 2315 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2316 MVE_VADD_VEC_T1,
2317 0xef000840, 0xff811f51,
2318 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2319 /* Vector VADD T2. */
2da2eaf4 2320 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2321 MVE_VADD_VEC_T2,
2322 0xee010f40, 0xff811f70,
2323 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2324
d3b63143 2325 /* Vector VADDLV. */
2da2eaf4 2326 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2327 MVE_VADDLV,
2328 0xee890f00, 0xef8f1fd1,
2329 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2330
2331 /* Vector VADDV. */
2da2eaf4 2332 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2333 MVE_VADDV,
2334 0xeef10f00, 0xeff31fd1,
2335 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2336
66dcaa5d 2337 /* Vector VADC. */
2da2eaf4 2338 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2339 MVE_VADC,
2340 0xee300f00, 0xffb10f51,
2341 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2342
e523f101 2343 /* Vector VAND. */
2da2eaf4 2344 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2345 MVE_VAND,
2346 0xef000150, 0xffb11f51,
2347 "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2348
2349 /* Vector VBRSR register. */
2da2eaf4 2350 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2351 MVE_VBRSR,
2352 0xfe011e60, 0xff811f70,
2353 "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2354
897b9bbc 2355 /* Vector VCADD floating point. */
2da2eaf4 2356 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
897b9bbc
AV		 2357 MVE_VCADD_FP,
2358 0xfc800840, 0xfea11f51,
2359 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2360
2361 /* Vector VCADD. */
2da2eaf4 2362 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
897b9bbc
AV		 2363 MVE_VCADD_VEC,
2364 0xfe000f00, 0xff810f51,
2365 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2366
e523f101 2367 /* Vector VCLS. */
2da2eaf4 2368 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2369 MVE_VCLS,
2370 0xffb00440, 0xffb31fd1,
2371 "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2372
2373 /* Vector VCLZ. */
2da2eaf4 2374 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2375 MVE_VCLZ,
2376 0xffb004c0, 0xffb31fd1,
2377 "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2378
897b9bbc 2379 /* Vector VCMLA. */
2da2eaf4 2380 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
897b9bbc
AV		 2381 MVE_VCMLA_FP,
2382 0xfc200840, 0xfe211f51,
2383 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2384
143275ea 2385 /* Vector VCMP floating point T1. */
2da2eaf4 2386 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2387 MVE_VCMP_FP_T1,
2388 0xee310f00, 0xeff1ef50,
2389 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2390
2391 /* Vector VCMP floating point T2. */
2da2eaf4 2392 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2393 MVE_VCMP_FP_T2,
2394 0xee310f40, 0xeff1ef50,
2395 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2396
2397 /* Vector VCMP T1. */
2da2eaf4 2398 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2399 MVE_VCMP_VEC_T1,
2400 0xfe010f00, 0xffc1ff51,
2401 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2402 /* Vector VCMP T2. */
2da2eaf4 2403 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2404 MVE_VCMP_VEC_T2,
2405 0xfe010f01, 0xffc1ff51,
2406 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2407 /* Vector VCMP T3. */
2da2eaf4 2408 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2409 MVE_VCMP_VEC_T3,
2410 0xfe011f00, 0xffc1ff50,
2411 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2412 /* Vector VCMP T4. */
2da2eaf4 2413 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2414 MVE_VCMP_VEC_T4,
2415 0xfe010f40, 0xffc1ff70,
2416 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2417 /* Vector VCMP T5. */
2da2eaf4 2418 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2419 MVE_VCMP_VEC_T5,
2420 0xfe010f60, 0xffc1ff70,
2421 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2422 /* Vector VCMP T6. */
2da2eaf4 2423 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2424 MVE_VCMP_VEC_T6,
2425 0xfe011f40, 0xffc1ff50,
2426 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2427
9743db03 2428 /* Vector VDUP. */
2da2eaf4 2429 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2430 MVE_VDUP,
2431 0xeea00b10, 0xffb10f5f,
2432 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2433
2434 /* Vector VEOR. */
2da2eaf4 2435 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2436 MVE_VEOR,
2437 0xff000150, 0xffd11f51,
2438 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2439
2440 /* Vector VFMA, vector * scalar. */
2da2eaf4 2441 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2442 MVE_VFMA_FP_SCALAR,
2443 0xee310e40, 0xefb11f70,
2444 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2445
2446 /* Vector VFMA floating point. */
2da2eaf4 2447 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2448 MVE_VFMA_FP,
2449 0xef000c50, 0xffa11f51,
2450 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2451
2452 /* Vector VFMS floating point. */
2da2eaf4 2453 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2454 MVE_VFMS_FP,
2455 0xef200c50, 0xffa11f51,
2456 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2457
2458 /* Vector VFMAS, vector * scalar. */
2da2eaf4 2459 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2460 MVE_VFMAS_FP_SCALAR,
2461 0xee311e40, 0xefb11f70,
2462 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2463
2464 /* Vector VHADD T1. */
2da2eaf4 2465 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2466 MVE_VHADD_T1,
2467 0xef000040, 0xef811f51,
2468 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2469
2470 /* Vector VHADD T2. */
2da2eaf4 2471 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2472 MVE_VHADD_T2,
2473 0xee000f40, 0xef811f70,
2474 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2475
2476 /* Vector VHSUB T1. */
2da2eaf4 2477 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2478 MVE_VHSUB_T1,
2479 0xef000240, 0xef811f51,
2480 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2481
2482 /* Vector VHSUB T2. */
2da2eaf4 2483 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2484 MVE_VHSUB_T2,
2485 0xee001f40, 0xef811f70,
2486 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2487
897b9bbc 2488 /* Vector VCMUL. */
2da2eaf4 2489 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
897b9bbc
AV		 2490 MVE_VCMUL_FP,
2491 0xee300e00, 0xefb10f50,
2492 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2493
e523f101 2494 /* Vector VCTP. */
2da2eaf4 2495 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2496 MVE_VCTP,
2497 0xf000e801, 0xffc0ffff,
2498 "vctp%v.%20-21s\t%16-19r"},
2499
9743db03 2500 /* Vector VDUP. */
2da2eaf4 2501 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2502 MVE_VDUP,
2503 0xeea00b10, 0xffb10f5f,
2504 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2505
2506 /* Vector VRHADD. */
2da2eaf4 2507 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2508 MVE_VRHADD,
2509 0xef000140, 0xef811f51,
2510 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2511
bf0b396d 2512 /* Vector VCVT. */
2da2eaf4 2513 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2514 MVE_VCVT_FP_FIX_VEC,
2515 0xef800c50, 0xef801cd1,
2516 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2517
2518 /* Vector VCVT. */
2da2eaf4 2519 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2520 MVE_VCVT_BETWEEN_FP_INT,
2521 0xffb30640, 0xffb31e51,
2522 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2523
2524 /* Vector VCVT between single and half-precision float, bottom half. */
2da2eaf4 2525 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2526 MVE_VCVT_FP_HALF_FP,
2527 0xee3f0e01, 0xefbf1fd1,
2528 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2529
2530 /* Vector VCVT between single and half-precision float, top half. */
2da2eaf4 2531 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2532 MVE_VCVT_FP_HALF_FP,
2533 0xee3f1e01, 0xefbf1fd1,
2534 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2535
2536 /* Vector VCVT. */
2da2eaf4 2537 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2538 MVE_VCVT_FROM_FP_TO_INT,
2539 0xffb30040, 0xffb31c51,
2540 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2541
1c8f2df8 2542 /* Vector VDDUP. */
2da2eaf4 2543 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2544 MVE_VDDUP,
2545 0xee011f6e, 0xff811f7e,
2546 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2547
2548 /* Vector VDWDUP. */
2da2eaf4 2549 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2550 MVE_VDWDUP,
2551 0xee011f60, 0xff811f70,
2552 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2553
897b9bbc 2554 /* Vector VHCADD. */
2da2eaf4 2555 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
897b9bbc
AV		 2556 MVE_VHCADD,
2557 0xee000f00, 0xff810f51,
2558 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2559
1c8f2df8 2560 /* Vector VIWDUP. */
2da2eaf4 2561 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2562 MVE_VIWDUP,
2563 0xee010f60, 0xff811f70,
2564 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2565
2566 /* Vector VIDUP. */
2da2eaf4 2567 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2568 MVE_VIDUP,
2569 0xee010f6e, 0xff811f7e,
2570 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2571
04d54ace 2572 /* Vector VLD2. */
2da2eaf4 2573 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 2574 MVE_VLD2,
2575 0xfc901e00, 0xff901e5f,
2576 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2577
2578 /* Vector VLD4. */
2da2eaf4 2579 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 2580 MVE_VLD4,
2581 0xfc901e01, 0xff901e1f,
2582 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2583
ef1576a1 2584 /* Vector VLDRB gather load. */
2da2eaf4 2585 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2586 MVE_VLDRB_GATHER_T1,
2587 0xec900e00, 0xefb01e50,
2588 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2589
2590 /* Vector VLDRH gather load. */
2da2eaf4 2591 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2592 MVE_VLDRH_GATHER_T2,
2593 0xec900e10, 0xefb01e50,
2594 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2595
2596 /* Vector VLDRW gather load. */
2da2eaf4 2597 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2598 MVE_VLDRW_GATHER_T3,
2599 0xfc900f40, 0xffb01fd0,
2600 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2601
2602 /* Vector VLDRD gather load. */
2da2eaf4 2603 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2604 MVE_VLDRD_GATHER_T4,
2605 0xec900fd0, 0xefb01fd0,
2606 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2607
2608 /* Vector VLDRW gather load. */
2da2eaf4 2609 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2610 MVE_VLDRW_GATHER_T5,
2611 0xfd101e00, 0xff111f00,
2612 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2613
2614 /* Vector VLDRD gather load, variant T6. */
2da2eaf4 2615 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2616 MVE_VLDRD_GATHER_T6,
2617 0xfd101f00, 0xff111f00,
2618 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2619
aef6d006 2620 /* Vector VLDRB. */
2da2eaf4 2621 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2622 MVE_VLDRB_T1,
2623 0xec100e00, 0xee581e00,
2624 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2625
2626 /* Vector VLDRH. */
2da2eaf4 2627 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2628 MVE_VLDRH_T2,
2629 0xec180e00, 0xee581e00,
2630 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2631
2632 /* Vector VLDRB unsigned, variant T5. */
2da2eaf4 2633 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2634 MVE_VLDRB_T5,
2635 0xec101e00, 0xfe101f80,
2636 "vldrb%v.u8\t%13-15,22Q, %d"},
2637
2638 /* Vector VLDRH unsigned, variant T6. */
2da2eaf4 2639 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2640 MVE_VLDRH_T6,
2641 0xec101e80, 0xfe101f80,
2642 "vldrh%v.u16\t%13-15,22Q, %d"},
2643
2644 /* Vector VLDRW unsigned, variant T7. */
2da2eaf4 2645 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2646 MVE_VLDRW_T7,
2647 0xec101f00, 0xfe101f80,
2648 "vldrw%v.u32\t%13-15,22Q, %d"},
2649
56858bea 2650 /* Vector VMAX. */
2da2eaf4 2651 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2652 MVE_VMAX,
2653 0xef000640, 0xef811f51,
2654 "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2655
2656 /* Vector VMAXA. */
2da2eaf4 2657 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2658 MVE_VMAXA,
2659 0xee330e81, 0xffb31fd1,
2660 "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2661
2662 /* Vector VMAXNM floating point. */
2da2eaf4 2663 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2664 MVE_VMAXNM_FP,
2665 0xff000f50, 0xffa11f51,
2666 "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2667
2668 /* Vector VMAXNMA floating point. */
2da2eaf4 2669 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2670 MVE_VMAXNMA_FP,
2671 0xee3f0e81, 0xefbf1fd1,
2672 "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2673
2674 /* Vector VMAXNMV floating point. */
2da2eaf4 2675 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2676 MVE_VMAXNMV_FP,
2677 0xeeee0f00, 0xefff0fd1,
2678 "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2679
2680 /* Vector VMAXNMAV floating point. */
2da2eaf4 2681 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2682 MVE_VMAXNMAV_FP,
2683 0xeeec0f00, 0xefff0fd1,
2684 "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2685
2686 /* Vector VMAXV. */
2da2eaf4 2687 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2688 MVE_VMAXV,
2689 0xeee20f00, 0xeff30fd1,
2690 "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2691
2692 /* Vector VMAXAV. */
2da2eaf4 2693 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2694 MVE_VMAXAV,
2695 0xeee00f00, 0xfff30fd1,
2696 "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2697
2698 /* Vector VMIN. */
2da2eaf4 2699 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2700 MVE_VMIN,
2701 0xef000650, 0xef811f51,
2702 "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2703
2704 /* Vector VMINA. */
2da2eaf4 2705 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2706 MVE_VMINA,
2707 0xee331e81, 0xffb31fd1,
2708 "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2709
2710 /* Vector VMINNM floating point. */
2da2eaf4 2711 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2712 MVE_VMINNM_FP,
2713 0xff200f50, 0xffa11f51,
2714 "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2715
2716 /* Vector VMINNMA floating point. */
2da2eaf4 2717 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2718 MVE_VMINNMA_FP,
2719 0xee3f1e81, 0xefbf1fd1,
2720 "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2721
2722 /* Vector VMINNMV floating point. */
2da2eaf4 2723 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2724 MVE_VMINNMV_FP,
2725 0xeeee0f80, 0xefff0fd1,
2726 "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2727
2728 /* Vector VMINNMAV floating point. */
2da2eaf4 2729 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2730 MVE_VMINNMAV_FP,
2731 0xeeec0f80, 0xefff0fd1,
2732 "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2733
2734 /* Vector VMINV. */
2da2eaf4 2735 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2736 MVE_VMINV,
2737 0xeee20f80, 0xeff30fd1,
2738 "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2739
2740 /* Vector VMINAV. */
2da2eaf4 2741 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2742 MVE_VMINAV,
2743 0xeee00f80, 0xfff30fd1,
2744 "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2745
2746 /* Vector VMLA. */
2da2eaf4 2747 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2748 MVE_VMLA,
2749 0xee010e40, 0xef811f70,
2750 "vmla%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2751
d3b63143
AV		 2752 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2753 opcode aliasing. */
2da2eaf4 2754 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2755 MVE_VMLALDAV,
2756 0xee801e00, 0xef801f51,
2757 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2758
2da2eaf4 2759 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2760 MVE_VMLALDAV,
2761 0xee800e00, 0xef801f51,
2762 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2763
2764 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2da2eaf4 2765 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2766 MVE_VMLADAV_T1,
2767 0xeef00e00, 0xeff01f51,
2768 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2769
2770 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2da2eaf4 2771 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2772 MVE_VMLADAV_T2,
2773 0xeef00f00, 0xeff11f51,
2774 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2775
2776 /* Vector VMLADAV T1 variant. */
2da2eaf4 2777 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2778 MVE_VMLADAV_T1,
2779 0xeef01e00, 0xeff01f51,
2780 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2781
2782 /* Vector VMLADAV T2 variant. */
2da2eaf4 2783 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2784 MVE_VMLADAV_T2,
2785 0xeef01f00, 0xeff11f51,
2786 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2787
2788 /* Vector VMLAS. */
2da2eaf4 2789 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2790 MVE_VMLAS,
2791 0xee011e40, 0xef811f70,
2792 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2793
2794 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2795 opcode aliasing. */
2da2eaf4 2796 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2797 MVE_VRMLSLDAVH,
2798 0xfe800e01, 0xff810f51,
2799 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2800
2801 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2802 opcdoe aliasing. */
2da2eaf4 2803 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2804 MVE_VMLSLDAV,
2805 0xee800e01, 0xff800f51,
2806 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2807
2808 /* Vector VMLSDAV T1 Variant. */
2da2eaf4 2809 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2810 MVE_VMLSDAV_T1,
2811 0xeef00e01, 0xfff00f51,
2812 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2813
2814 /* Vector VMLSDAV T2 Variant. */
2da2eaf4 2815 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2816 MVE_VMLSDAV_T2,
2817 0xfef00e01, 0xfff10f51,
2818 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2819
c507f10b 2820 /* Vector VMOV between gpr and half precision register, op == 0. */
2da2eaf4 2821 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2822 MVE_VMOV_HFP_TO_GP,
2823 0xee000910, 0xfff00f7f,
2824 "vmov.f16\t%7,16-19F, %12-15r"},
2825
2826 /* Vector VMOV between gpr and half precision register, op == 1. */
2da2eaf4 2827 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2828 MVE_VMOV_HFP_TO_GP,
2829 0xee100910, 0xfff00f7f,
2830 "vmov.f16\t%12-15r, %7,16-19F"},
2831
2da2eaf4 2832 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2833 MVE_VMOV_GP_TO_VEC_LANE,
2834 0xee000b10, 0xff900f1f,
2835 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2836
2837 /* Vector VORR immediate to vector.
2838 NOTE: MVE_VORR_IMM must appear in the table
2839 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2840 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2841 MVE_VORR_IMM,
2842 0xef800050, 0xefb810f0,
2843 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2844
ed63aa17
AV		 2845 /* Vector VQSHL T2 Variant.
2846 NOTE: MVE_VQSHL_T2 must appear in the table before
2847 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2848 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2849 MVE_VQSHL_T2,
2850 0xef800750, 0xef801fd1,
2851 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2852
2853 /* Vector VQSHLU T3 Variant
2854 NOTE: MVE_VQSHL_T2 must appear in the table before
2855 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2856
2da2eaf4 2857 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2858 MVE_VQSHLU_T3,
2859 0xff800650, 0xff801fd1,
2860 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2861
2862 /* Vector VRSHR
2863 NOTE: MVE_VRSHR must appear in the table before
2864 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2865 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2866 MVE_VRSHR,
2867 0xef800250, 0xef801fd1,
2868 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2869
2870 /* Vector VSHL.
2871 NOTE: MVE_VSHL must appear in the table before
2872 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2873 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2874 MVE_VSHL_T1,
2875 0xef800550, 0xff801fd1,
2876 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2877
2878 /* Vector VSHR
2879 NOTE: MVE_VSHR must appear in the table before
2880 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2881 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2882 MVE_VSHR,
2883 0xef800050, 0xef801fd1,
2884 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2885
2886 /* Vector VSLI
2887 NOTE: MVE_VSLI must appear in the table before
2888 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2889 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2890 MVE_VSLI,
2891 0xff800550, 0xff801fd1,
2892 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2893
2894 /* Vector VSRI
2895 NOTE: MVE_VSRI must appear in the table before
2896 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2897 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2898 MVE_VSRI,
2899 0xff800450, 0xff801fd1,
2900 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2901
c507f10b 2902 /* Vector VMOV immediate to vector,
ce760a76 2903 undefinded for cmode == 1111 */
2da2eaf4 2904 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ce760a76
MI		 2905 MVE_VMVN_IMM, 0xef800f70, 0xefb81ff0, UNDEFINED_INSTRUCTION},
2906
2907 /* Vector VMOV immediate to vector,
2908 cmode == 1101 */
2da2eaf4 2909 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ce760a76
MI		 2910 MVE_VMOV_IMM_TO_VEC, 0xef800d50, 0xefb81fd0,
2911 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
c507f10b
AV		 2912
2913 /* Vector VMOV immediate to vector. */
2da2eaf4 2914 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2915 MVE_VMOV_IMM_TO_VEC,
2916 0xef800050, 0xefb810d0,
2917 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2918
2919 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2da2eaf4 2920 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2921 MVE_VMOV2_VEC_LANE_TO_GP,
2922 0xec000f00, 0xffb01ff0,
2923 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2924
2925 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2da2eaf4 2926 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2927 MVE_VMOV2_VEC_LANE_TO_GP,
2928 0xec000f10, 0xffb01ff0,
2929 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2930
2931 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2da2eaf4 2932 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2933 MVE_VMOV2_GP_TO_VEC_LANE,
2934 0xec100f00, 0xffb01ff0,
2935 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2936
2937 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2da2eaf4 2938 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2939 MVE_VMOV2_GP_TO_VEC_LANE,
2940 0xec100f10, 0xffb01ff0,
2941 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2942
2943 /* Vector VMOV Vector lane to gpr. */
2da2eaf4 2944 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2945 MVE_VMOV_VEC_LANE_TO_GP,
2946 0xee100b10, 0xff100f1f,
2947 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2948
ed63aa17
AV		 2949 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
2950 to instruction opcode aliasing. */
2da2eaf4 2951 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2952 MVE_VSHLL_T1,
2953 0xeea00f40, 0xefa00fd1,
2954 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2955
14925797 2956 /* Vector VMOVL long. */
2da2eaf4 2957 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 2958 MVE_VMOVL,
2959 0xeea00f40, 0xefa70fd1,
2960 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2961
2962 /* Vector VMOV and narrow. */
2da2eaf4 2963 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 2964 MVE_VMOVN,
2965 0xfe310e81, 0xffb30fd1,
2966 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2967
c507f10b 2968 /* Floating point move extract. */
2da2eaf4 2969 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2970 MVE_VMOVX,
2971 0xfeb00a40, 0xffbf0fd0,
2972 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2973
f49bb598 2974 /* Vector VMUL floating-point T1 variant. */
2da2eaf4 2975 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
f49bb598
AV		 2976 MVE_VMUL_FP_T1,
2977 0xff000d50, 0xffa11f51,
2978 "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2979
2980 /* Vector VMUL floating-point T2 variant. */
2da2eaf4 2981 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
f49bb598
AV		 2982 MVE_VMUL_FP_T2,
2983 0xee310e60, 0xefb11f70,
2984 "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2985
2986 /* Vector VMUL T1 variant. */
2da2eaf4 2987 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 2988 MVE_VMUL_VEC_T1,
2989 0xef000950, 0xff811f51,
2990 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2991
2992 /* Vector VMUL T2 variant. */
2da2eaf4 2993 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 2994 MVE_VMUL_VEC_T2,
2995 0xee011e60, 0xff811f70,
2996 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2997
2998 /* Vector VMULH. */
2da2eaf4 2999 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 3000 MVE_VMULH,
3001 0xee010e01, 0xef811f51,
3002 "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3003
3004 /* Vector VRMULH. */
2da2eaf4 3005 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 3006 MVE_VRMULH,
3007 0xee011e01, 0xef811f51,
3008 "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3009
14925797 3010 /* Vector VMULL integer. */
2da2eaf4 3011 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3012 MVE_VMULL_INT,
3013 0xee010e00, 0xef810f51,
3014 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3015
3016 /* Vector VMULL polynomial. */
2da2eaf4 3017 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3018 MVE_VMULL_POLY,
3019 0xee310e00, 0xefb10f51,
3020 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3021
c507f10b 3022 /* Vector VMVN immediate to vector. */
2da2eaf4 3023 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 3024 MVE_VMVN_IMM,
3025 0xef800070, 0xefb810f0,
3026 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
3027
3028 /* Vector VMVN register. */
2da2eaf4 3029 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 3030 MVE_VMVN_REG,
3031 0xffb005c0, 0xffbf1fd1,
3032 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
3033
f49bb598 3034 /* Vector VNEG floating point. */
2da2eaf4 3035 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
f49bb598
AV		 3036 MVE_VNEG_FP,
3037 0xffb107c0, 0xffb31fd1,
3038 "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3039
3040 /* Vector VNEG. */
2da2eaf4 3041 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 3042 MVE_VNEG_VEC,
3043 0xffb103c0, 0xffb31fd1,
3044 "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3045
c507f10b 3046 /* Vector VORN, vector bitwise or not. */
2da2eaf4 3047 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 3048 MVE_VORN,
3049 0xef300150, 0xffb11f51,
3050 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3051
3052 /* Vector VORR register. */
2da2eaf4 3053 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 3054 MVE_VORR_REG,
3055 0xef200150, 0xffb11f51,
3056 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3057
c4a23bf8
SP		 3058 /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if
3059 "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen
3060 MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes
3061 array. */
3062
2da2eaf4 3063 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c4a23bf8
SP		 3064 MVE_VMOV_VEC_TO_VEC,
3065 0xef200150, 0xffb11f51,
3066 "vmov%v\t%13-15,22Q, %17-19,7Q"},
3067
14925797 3068 /* Vector VQDMULL T1 variant. */
2da2eaf4 3069 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3070 MVE_VQDMULL_T1,
3071 0xee300f01, 0xefb10f51,
3072 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3073
14b456f2 3074 /* Vector VPNOT. */
2da2eaf4 3075 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3076 MVE_VPNOT,
3077 0xfe310f4d, 0xffffffff,
3078 "vpnot%v"},
3079
3080 /* Vector VPSEL. */
2da2eaf4 3081 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3082 MVE_VPSEL,
3083 0xfe310f01, 0xffb11f51,
3084 "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3085
3086 /* Vector VQABS. */
2da2eaf4 3087 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3088 MVE_VQABS,
3089 0xffb00740, 0xffb31fd1,
3090 "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3091
3092 /* Vector VQADD T1 variant. */
2da2eaf4 3093 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3094 MVE_VQADD_T1,
3095 0xef000050, 0xef811f51,
3096 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3097
3098 /* Vector VQADD T2 variant. */
2da2eaf4 3099 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3100 MVE_VQADD_T2,
3101 0xee000f60, 0xef811f70,
3102 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3103
14925797 3104 /* Vector VQDMULL T2 variant. */
2da2eaf4 3105 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3106 MVE_VQDMULL_T2,
3107 0xee300f60, 0xefb10f70,
3108 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3109
3110 /* Vector VQMOVN. */
2da2eaf4 3111 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3112 MVE_VQMOVN,
3113 0xee330e01, 0xefb30fd1,
3114 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
3115
3116 /* Vector VQMOVUN. */
2da2eaf4 3117 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3118 MVE_VQMOVUN,
3119 0xee310e81, 0xffb30fd1,
3120 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3121
d3b63143 3122 /* Vector VQDMLADH. */
2da2eaf4 3123 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3124 MVE_VQDMLADH,
3125 0xee000e00, 0xff810f51,
3126 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3127
3128 /* Vector VQRDMLADH. */
2da2eaf4 3129 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3130 MVE_VQRDMLADH,
3131 0xee000e01, 0xff810f51,
3132 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3133
3134 /* Vector VQDMLAH. */
2da2eaf4 3135 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 3136 MVE_VQDMLAH,
23d188c7 3137 0xee000e60, 0xff811f70,
d3b63143
AV		 3138 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3139
3140 /* Vector VQRDMLAH. */
2da2eaf4 3141 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 3142 MVE_VQRDMLAH,
23d188c7 3143 0xee000e40, 0xff811f70,
d3b63143
AV		 3144 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3145
3146 /* Vector VQDMLASH. */
2da2eaf4 3147 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 3148 MVE_VQDMLASH,
23d188c7 3149 0xee001e60, 0xff811f70,
d3b63143
AV		 3150 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3151
3152 /* Vector VQRDMLASH. */
2da2eaf4 3153 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 3154 MVE_VQRDMLASH,
23d188c7 3155 0xee001e40, 0xff811f70,
d3b63143
AV		 3156 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3157
3158 /* Vector VQDMLSDH. */
2da2eaf4 3159 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3160 MVE_VQDMLSDH,
3161 0xfe000e00, 0xff810f51,
3162 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3163
3164 /* Vector VQRDMLSDH. */
2da2eaf4 3165 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3166 MVE_VQRDMLSDH,
3167 0xfe000e01, 0xff810f51,
3168 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3169
3170 /* Vector VQDMULH T1 variant. */
2da2eaf4 3171 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3172 MVE_VQDMULH_T1,
3173 0xef000b40, 0xff811f51,
3174 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3175
3176 /* Vector VQRDMULH T2 variant. */
2da2eaf4 3177 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3178 MVE_VQRDMULH_T2,
3179 0xff000b40, 0xff811f51,
3180 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3181
3182 /* Vector VQDMULH T3 variant. */
2da2eaf4 3183 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3184 MVE_VQDMULH_T3,
3185 0xee010e60, 0xff811f70,
3186 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3187
3188 /* Vector VQRDMULH T4 variant. */
2da2eaf4 3189 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3190 MVE_VQRDMULH_T4,
3191 0xfe010e60, 0xff811f70,
3192 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3193
14b456f2 3194 /* Vector VQNEG. */
2da2eaf4 3195 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3196 MVE_VQNEG,
3197 0xffb007c0, 0xffb31fd1,
3198 "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3199
ed63aa17 3200 /* Vector VQRSHL T1 variant. */
2da2eaf4 3201 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3202 MVE_VQRSHL_T1,
3203 0xef000550, 0xef811f51,
3204 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3205
3206 /* Vector VQRSHL T2 variant. */
2da2eaf4 3207 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3208 MVE_VQRSHL_T2,
3209 0xee331ee0, 0xefb31ff0,
3210 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3211
3212 /* Vector VQRSHRN. */
2da2eaf4 3213 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3214 MVE_VQRSHRN,
3215 0xee800f41, 0xefa00fd1,
3216 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3217
3218 /* Vector VQRSHRUN. */
2da2eaf4 3219 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3220 MVE_VQRSHRUN,
3221 0xfe800fc0, 0xffa00fd1,
3222 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3223
3224 /* Vector VQSHL T1 Variant. */
2da2eaf4 3225 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3226 MVE_VQSHL_T1,
3227 0xee311ee0, 0xefb31ff0,
3228 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3229
3230 /* Vector VQSHL T4 Variant. */
2da2eaf4 3231 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3232 MVE_VQSHL_T4,
3233 0xef000450, 0xef811f51,
3234 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3235
3236 /* Vector VQSHRN. */
2da2eaf4 3237 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3238 MVE_VQSHRN,
3239 0xee800f40, 0xefa00fd1,
3240 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3241
3242 /* Vector VQSHRUN. */
2da2eaf4 3243 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3244 MVE_VQSHRUN,
3245 0xee800fc0, 0xffa00fd1,
3246 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3247
14b456f2 3248 /* Vector VQSUB T1 Variant. */
2da2eaf4 3249 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3250 MVE_VQSUB_T1,
3251 0xef000250, 0xef811f51,
3252 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3253
3254 /* Vector VQSUB T2 Variant. */
2da2eaf4 3255 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3256 MVE_VQSUB_T2,
3257 0xee001f60, 0xef811f70,
3258 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3259
3260 /* Vector VREV16. */
2da2eaf4 3261 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3262 MVE_VREV16,
3263 0xffb00140, 0xffb31fd1,
3264 "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
3265
3266 /* Vector VREV32. */
2da2eaf4 3267 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3268 MVE_VREV32,
3269 0xffb000c0, 0xffb31fd1,
3270 "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3271
3272 /* Vector VREV64. */
2da2eaf4 3273 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3274 MVE_VREV64,
3275 0xffb00040, 0xffb31fd1,
3276 "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3277
bf0b396d 3278 /* Vector VRINT floating point. */
2da2eaf4 3279 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 3280 MVE_VRINT_FP,
3281 0xffb20440, 0xffb31c51,
3282 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3283
d3b63143 3284 /* Vector VRMLALDAVH. */
2da2eaf4 3285 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3286 MVE_VRMLALDAVH,
3287 0xee800f00, 0xef811f51,
3288 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3289
3290 /* Vector VRMLALDAVH. */
2da2eaf4 3291 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3292 MVE_VRMLALDAVH,
3293 0xee801f00, 0xef811f51,
3294 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3295
ed63aa17 3296 /* Vector VRSHL T1 Variant. */
2da2eaf4 3297 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3298 MVE_VRSHL_T1,
3299 0xef000540, 0xef811f51,
3300 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3301
3302 /* Vector VRSHL T2 Variant. */
2da2eaf4 3303 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3304 MVE_VRSHL_T2,
3305 0xee331e60, 0xefb31ff0,
3306 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3307
3308 /* Vector VRSHRN. */
2da2eaf4 3309 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3310 MVE_VRSHRN,
3311 0xfe800fc1, 0xffa00fd1,
3312 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3313
66dcaa5d 3314 /* Vector VSBC. */
2da2eaf4 3315 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 3316 MVE_VSBC,
3317 0xfe300f00, 0xffb10f51,
3318 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3319
ed63aa17 3320 /* Vector VSHL T2 Variant. */
2da2eaf4 3321 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3322 MVE_VSHL_T2,
3323 0xee311e60, 0xefb31ff0,
3324 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3325
3326 /* Vector VSHL T3 Variant. */
2da2eaf4 3327 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3328 MVE_VSHL_T3,
3329 0xef000440, 0xef811f51,
3330 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3331
3332 /* Vector VSHLC. */
2da2eaf4 3333 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3334 MVE_VSHLC,
3335 0xeea00fc0, 0xffa01ff0,
3336 "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
3337
3338 /* Vector VSHLL T2 Variant. */
2da2eaf4 3339 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3340 MVE_VSHLL_T2,
3341 0xee310e01, 0xefb30fd1,
3342 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
3343
3344 /* Vector VSHRN. */
2da2eaf4 3345 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3346 MVE_VSHRN,
3347 0xee800fc1, 0xffa00fd1,
3348 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3349
04d54ace 3350 /* Vector VST2 no writeback. */
2da2eaf4 3351 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3352 MVE_VST2,
3353 0xfc801e00, 0xffb01e5f,
3354 "vst2%5d.%7-8s\t%B, [%16-19r]"},
3355
3356 /* Vector VST2 writeback. */
2da2eaf4 3357 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3358 MVE_VST2,
3359 0xfca01e00, 0xffb01e5f,
3360 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3361
3362 /* Vector VST4 no writeback. */
2da2eaf4 3363 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3364 MVE_VST4,
3365 0xfc801e01, 0xffb01e1f,
3366 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3367
3368 /* Vector VST4 writeback. */
2da2eaf4 3369 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3370 MVE_VST4,
3371 0xfca01e01, 0xffb01e1f,
3372 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3373
ef1576a1 3374 /* Vector VSTRB scatter store, T1 variant. */
2da2eaf4 3375 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3376 MVE_VSTRB_SCATTER_T1,
3377 0xec800e00, 0xffb01e50,
3378 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3379
3380 /* Vector VSTRH scatter store, T2 variant. */
2da2eaf4 3381 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3382 MVE_VSTRH_SCATTER_T2,
3383 0xec800e10, 0xffb01e50,
3384 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3385
3386 /* Vector VSTRW scatter store, T3 variant. */
2da2eaf4 3387 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3388 MVE_VSTRW_SCATTER_T3,
3389 0xec800e40, 0xffb01e50,
3390 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3391
3392 /* Vector VSTRD scatter store, T4 variant. */
2da2eaf4 3393 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3394 MVE_VSTRD_SCATTER_T4,
3395 0xec800fd0, 0xffb01fd0,
3396 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3397
3398 /* Vector VSTRW scatter store, T5 variant. */
2da2eaf4 3399 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3400 MVE_VSTRW_SCATTER_T5,
3401 0xfd001e00, 0xff111f00,
3402 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3403
3404 /* Vector VSTRD scatter store, T6 variant. */
2da2eaf4 3405 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3406 MVE_VSTRD_SCATTER_T6,
3407 0xfd001f00, 0xff111f00,
3408 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3409
aef6d006 3410 /* Vector VSTRB. */
2da2eaf4 3411 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3412 MVE_VSTRB_T1,
3413 0xec000e00, 0xfe581e00,
3414 "vstrb%v.%7-8s\t%13-15Q, %d"},
3415
3416 /* Vector VSTRH. */
2da2eaf4 3417 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3418 MVE_VSTRH_T2,
3419 0xec080e00, 0xfe581e00,
3420 "vstrh%v.%7-8s\t%13-15Q, %d"},
3421
3422 /* Vector VSTRB variant T5. */
2da2eaf4 3423 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3424 MVE_VSTRB_T5,
3425 0xec001e00, 0xfe101f80,
3426 "vstrb%v.8\t%13-15,22Q, %d"},
3427
3428 /* Vector VSTRH variant T6. */
2da2eaf4 3429 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3430 MVE_VSTRH_T6,
3431 0xec001e80, 0xfe101f80,
3432 "vstrh%v.16\t%13-15,22Q, %d"},
3433
3434 /* Vector VSTRW variant T7. */
2da2eaf4 3435 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3436 MVE_VSTRW_T7,
3437 0xec001f00, 0xfe101f80,
3438 "vstrw%v.32\t%13-15,22Q, %d"},
3439
66dcaa5d 3440 /* Vector VSUB floating point T1 variant. */
2da2eaf4 3441 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 3442 MVE_VSUB_FP_T1,
3443 0xef200d40, 0xffa11f51,
3444 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3445
3446 /* Vector VSUB floating point T2 variant. */
2da2eaf4 3447 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 3448 MVE_VSUB_FP_T2,
3449 0xee301f40, 0xefb11f70,
3450 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3451
3452 /* Vector VSUB T1 variant. */
2da2eaf4 3453 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 3454 MVE_VSUB_VEC_T1,
3455 0xff000840, 0xff811f51,
3456 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3457
3458 /* Vector VSUB T2 variant. */
2da2eaf4 3459 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 3460 MVE_VSUB_VEC_T2,
3461 0xee011f40, 0xff811f70,
3462 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3463
2da2eaf4 3464 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3465 MVE_ASRLI,
3466 0xea50012f, 0xfff1813f,
3467 "asrl%c\t%17-19l, %9-11h, %j"},
3468
2da2eaf4 3469 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3470 MVE_ASRL,
3471 0xea50012d, 0xfff101ff,
3472 "asrl%c\t%17-19l, %9-11h, %12-15S"},
3473
2da2eaf4 3474 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3475 MVE_LSLLI,
3476 0xea50010f, 0xfff1813f,
3477 "lsll%c\t%17-19l, %9-11h, %j"},
3478
2da2eaf4 3479 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3480 MVE_LSLL,
3481 0xea50010d, 0xfff101ff,
3482 "lsll%c\t%17-19l, %9-11h, %12-15S"},
3483
2da2eaf4 3484 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3485 MVE_LSRL,
3486 0xea50011f, 0xfff1813f,
3487 "lsrl%c\t%17-19l, %9-11h, %j"},
3488
2da2eaf4 3489 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41 3490 MVE_SQRSHRL,
08132bdd
SP		 3491 0xea51012d, 0xfff1017f,
3492 "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"},
23d00a41 3493
2da2eaf4 3494 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3495 MVE_SQRSHR,
3496 0xea500f2d, 0xfff00fff,
3497 "sqrshr%c\t%16-19S, %12-15S"},
3498
2da2eaf4 3499 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3500 MVE_SQSHLL,
3501 0xea51013f, 0xfff1813f,
3502 "sqshll%c\t%17-19l, %9-11h, %j"},
3503
2da2eaf4 3504 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3505 MVE_SQSHL,
3506 0xea500f3f, 0xfff08f3f,
3507 "sqshl%c\t%16-19S, %j"},
3508
2da2eaf4 3509 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3510 MVE_SRSHRL,
3511 0xea51012f, 0xfff1813f,
3512 "srshrl%c\t%17-19l, %9-11h, %j"},
3513
2da2eaf4 3514 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3515 MVE_SRSHR,
3516 0xea500f2f, 0xfff08f3f,
3517 "srshr%c\t%16-19S, %j"},
3518
2da2eaf4 3519 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41 3520 MVE_UQRSHLL,
08132bdd
SP		 3521 0xea51010d, 0xfff1017f,
3522 "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"},
23d00a41 3523
2da2eaf4 3524 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3525 MVE_UQRSHL,
3526 0xea500f0d, 0xfff00fff,
3527 "uqrshl%c\t%16-19S, %12-15S"},
3528
2da2eaf4 3529 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3530 MVE_UQSHLL,
3531 0xea51010f, 0xfff1813f,
3532 "uqshll%c\t%17-19l, %9-11h, %j"},
3533
2da2eaf4 3534 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3535 MVE_UQSHL,
3536 0xea500f0f, 0xfff08f3f,
3537 "uqshl%c\t%16-19S, %j"},
3538
2da2eaf4 3539 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3540 MVE_URSHRL,
3541 0xea51011f, 0xfff1813f,
3542 "urshrl%c\t%17-19l, %9-11h, %j"},
3543
2da2eaf4 3544 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3545 MVE_URSHR,
3546 0xea500f1f, 0xfff08f3f,
3547 "urshr%c\t%16-19S, %j"},
3548
e39c1607
SD		 3549 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3550 MVE_CSINC,
3551 0xea509000, 0xfff0f000,
3552 "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3553
3554 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3555 MVE_CSINV,
3556 0xea50a000, 0xfff0f000,
3557 "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3558
3559 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3560 MVE_CSET,
3561 0xea5f900f, 0xfffff00f,
3562 "cset\t%8-11S, %4-7C"},
3563
3564 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3565 MVE_CSETM,
3566 0xea5fa00f, 0xfffff00f,
3567 "csetm\t%8-11S, %4-7C"},
3568
3569 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3570 MVE_CSEL,
3571 0xea508000, 0xfff0f000,
3572 "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3573
3574 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3575 MVE_CSNEG,
3576 0xea50b000, 0xfff0f000,
3577 "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3578
3579 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3580 MVE_CINC,
3581 0xea509000, 0xfff0f000,
3582 "cinc\t%8-11S, %16-19Z, %4-7C"},
3583
3584 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3585 MVE_CINV,
3586 0xea50a000, 0xfff0f000,
3587 "cinv\t%8-11S, %16-19Z, %4-7C"},
3588
3589 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3590 MVE_CNEG,
3591 0xea50b000, 0xfff0f000,
3592 "cneg\t%8-11S, %16-19Z, %4-7C"},
3593
143275ea
AV		 3594 {ARM_FEATURE_CORE_LOW (0),
3595 MVE_NONE,
3596 0x00000000, 0x00000000, 0}
73cd51e5
AV		 3597};
3598
8f06b2d8
PB		 3599/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
3600 ordered: they must be searched linearly from the top to obtain a correct
3601 match. */
3602
3603/* print_insn_arm recognizes the following format control codes:
3604
3605 %% %
3606
3607 %a print address for ldr/str instruction
3608 %s print address for ldr/str halfword/signextend instruction
c1e26897 3609 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 3610 %b print branch destination
3611 %c print condition code (always bits 28-31)
3612 %m print register mask for ldm/stm instruction
3613 %o print operand2 (immediate or register + shift)
3614 %p print 'p' iff bits 12-15 are 15
3615 %t print 't' iff bit 21 set and bit 24 clear
3616 %B print arm BLX(1) destination
3617 %C print the PSR sub type.
62b3e311
PB		 3618 %U print barrier type.
3619 %P print address for pli instruction.
8f06b2d8
PB		 3620
3621 %<bitfield>r print as an ARM register
9eb6c0f1 3622 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 3623 %<bitfield>R as %r but r15 is UNPREDICTABLE
3624 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3625 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 3626 %<bitfield>d print the bitfield in decimal
43e65147 3627 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 3628 %<bitfield>x print the bitfield in hex
3629 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 3630
16980d0b
JB		 3631 %<bitfield>'c print specified char iff bitfield is all ones
3632 %<bitfield>`c print specified char iff bitfield is all zeroes
3633 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 3634
8f06b2d8
PB		 3635 %e print arm SMI operand (bits 0..7,8..19).
3636 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 3637 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
3638 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 3639
8f06b2d8
PB		 3640static const struct opcode32 arm_opcodes[] =
3641{
3642 /* ARM instructions. */
823d2571
TG		 3643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3644 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
3645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3646 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
3647
3648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
3649 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3651 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3652 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3653 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
3655 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3657 0x00800090, 0x0fa000f0,
3658 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3660 0x00a00090, 0x0fa000f0,
3661 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 3662
105bde57 3663 /* V8.2 RAS extension instructions. */
4d1464f2 3664 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 3665 0xe320f010, 0xffffffff, "esb"},
3666
53c4b28b 3667 /* V8 instructions. */
823d2571
TG		 3668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3669 0x0320f005, 0x0fffffff, "sevl"},
f7dd2fb2
TC		 3670 /* Defined in V8 but is in NOP space so available to all arch. */
3671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
823d2571 3672 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
4ed7ed8d 3673 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 3674 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3675 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 3676 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3678 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3680 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 3681 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3682 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3683 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3684 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3685 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3686 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3687 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3688 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3689 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3690 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3691 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3692 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3693 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3694 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3695 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3696 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3697 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3698 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3699 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 3700 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 3701 /* CRC32 instructions. */
8b301fbb 3702 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3703 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3704 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3705 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3706 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3707 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3708 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3709 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3710 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3711 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3712 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3713 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 3714
ddfded2f
MW		 3715 /* Privileged Access Never extension instructions. */
3716 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
3717 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
3718
90ec0d68 3719 /* Virtualization Extension instructions. */
823d2571
TG		 3720 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
3721 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 3722
eea54501 3723 /* Integer Divide Extension instructions. */
823d2571
TG		 3724 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3725 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3726 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3727 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 3728
60e5ef9f 3729 /* MP Extension instructions. */
823d2571 3730 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 3731
c597cc3d
SD		 3732 /* Speculation Barriers. */
3733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
3734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
3735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
3736
62b3e311 3737 /* V7 instructions. */
823d2571
TG		 3738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
3739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
3740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a
AV		 3745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3746 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
62b3e311 3747
c19d1205 3748 /* ARM V6T2 instructions. */
823d2571
TG		 3749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3750 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3752 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3754 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3756 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3757
3758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3759 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
3760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3761 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3762
ff8646ee 3763 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 3764 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 3765 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3766 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3768 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3770 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 3771
f4c65163 3772 /* ARM Security extension instructions. */
823d2571
TG		 3773 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
3774 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 3775
8f06b2d8 3776 /* ARM V6K instructions. */
823d2571
TG		 3777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3778 0xf57ff01f, 0xffffffff, "clrex"},
3779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3780 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3782 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3784 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3786 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3788 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3790 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 3791
7fadb25d
SD		 3792 /* ARMv8.5-A instructions. */
3793 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
3794
8f06b2d8 3795 /* ARM V6K NOP hints. */
823d2571
TG		 3796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3797 0x0320f001, 0x0fffffff, "yield%c"},
3798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3799 0x0320f002, 0x0fffffff, "wfe%c"},
3800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3801 0x0320f003, 0x0fffffff, "wfi%c"},
3802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3803 0x0320f004, 0x0fffffff, "sev%c"},
3804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3805 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 3806
fe56b6ce 3807 /* ARM V6 instructions. */
823d2571
TG		 3808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3809 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
3810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3811 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
3812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3813 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
3814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3815 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
3816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3817 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
3818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3819 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3821 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
3822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3823 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
3824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3825 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
3826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3827 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
3828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3829 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3831 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3833 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3835 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3837 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3839 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3841 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3843 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3845 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3847 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3849 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3851 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3853 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3855 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3857 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3859 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3861 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3863 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3865 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3867 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3869 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3871 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3873 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3875 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3877 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3879 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3881 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3883 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3885 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3887 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3889 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3891 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3893 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3895 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3897 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3899 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3901 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3903 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3905 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3907 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3909 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3911 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3913 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3915 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3917 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3919 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3921 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3923 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3925 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3927 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3929 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3931 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3933 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3935 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3937 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3939 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3941 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3943 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3945 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3947 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3949 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3951 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3953 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3955 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3957 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3959 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3961 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3963 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3965 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3967 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3969 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3971 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3973 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3975 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3977 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3979 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3981 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3983 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3985 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3987 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3989 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3991 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3993 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3995 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
3996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3997 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3999 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
4000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4001 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
4002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4003 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
4004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4005 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
4006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4007 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
4008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4009 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
4010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4011 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
4012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4013 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4015 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4017 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4019 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4021 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
4022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4023 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4025 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4027 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
4028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4029 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
4030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4031 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
4032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4033 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
4034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4035 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
4036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4037 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
4038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4039 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
4040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4041 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
4042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4043 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4045 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
4046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4047 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
4048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4049 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
4050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4051 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 4052
8f06b2d8 4053 /* V5J instruction. */
823d2571
TG		 4054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
4055 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 4056
8f06b2d8 4057 /* V5 Instructions. */
823d2571
TG		 4058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4059 0xe1200070, 0xfff000f0,
4060 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
4061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4062 0xfa000000, 0xfe000000, "blx\t%B"},
4063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4064 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
4065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4066 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
4067
4068 /* V5E "El Segundo" Instructions. */
4069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4070 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
4071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4072 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
4073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4074 0xf450f000, 0xfc70f000, "pld\t%a"},
4075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4076 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4078 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4080 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4082 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
4083
4084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4085 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4087 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
4088
4089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4090 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4092 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4094 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4096 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4097
4098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4099 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
4100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4101 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
4102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4103 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
4104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4105 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
4106
4107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4108 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
4109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4110 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
4111
4112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4113 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
4114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4115 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
4116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4117 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
4118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4119 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 4120
8f06b2d8 4121 /* ARM Instructions. */
823d2571
TG		 4122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4123 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
4124
4125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4126 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
4127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4128 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
4129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4130 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
4131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4132 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
4133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4134 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
4135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4136 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
4137
4138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4139 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
4140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4141 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
4142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4143 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
4144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4145 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
4146
4147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4148 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
4149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4150 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
4151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4152 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
4153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4154 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
4155
4156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4157 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
4158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4159 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
4160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4161 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
4162
4163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4164 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
4165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4166 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
4167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4168 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
4169
4170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4171 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
4172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4173 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
4174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4175 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
4176
4177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4178 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4180 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4182 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
4183
4184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4185 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
4186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4187 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
4188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4189 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
4190
4191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4192 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
4193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4194 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
4195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4196 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
4197
4198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4199 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4201 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4203 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
4204
4205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4206 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4208 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4210 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
4211
4212 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
4213 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
4214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4215 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
4216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4217 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
4218
4219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4220 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
4221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4222 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
4223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4224 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
4225
4226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4227 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 4228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4229 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 4230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4231 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
823d2571
TG		 4232
4233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4234 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
4235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4236 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
4237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4238 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
4239
4240 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4241 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
4242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4243 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
4244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4245 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
4246
4247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4248 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
4249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4250 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
4251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4252 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
4253
4254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4255 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
4256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4257 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
4258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4259 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
4260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4261 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
4262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4263 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
4264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4265 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
4266 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4267 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
4268
4269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4270 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
4271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4272 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
4273 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4274 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
4275
4276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4277 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
4278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4279 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
4280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4281 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
4282
4283 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4284 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
4285 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4286 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
4287
4288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4289 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
4290
4291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4292 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
4293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4294 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
4295
4296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4297 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4299 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4301 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4302 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4303 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4304 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4305 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4307 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4309 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4310 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4311 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4313 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4315 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4317 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4319 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4321 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4323 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4325 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4327 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4329 0x092d0000, 0x0fff0000, "push%c\t%m"},
4330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4331 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
4332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4333 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4334
4335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4336 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4338 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4339 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4340 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4341 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4342 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4343 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4344 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4345 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4346 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4348 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4350 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4352 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4354 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4356 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4358 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4360 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4362 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4364 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4366 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4368 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
4369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4370 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
4371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4372 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4373
4374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4375 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4377 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 4378
4379 /* The rest. */
4ab90a7a
AV		 4380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
4381 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 4382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4383 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4384 {ARM_FEATURE_CORE_LOW (0),
4385 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 4386};
4387
4388/* print_insn_thumb16 recognizes the following format control codes:
4389
4390 %S print Thumb register (bits 3..5 as high number if bit 6 set)
4391 %D print Thumb register (bits 0..2 as high number if bit 7 set)
4392 %<bitfield>I print bitfield as a signed decimal
4393 (top bit of range being the sign bit)
4394 %N print Thumb register mask (with LR)
4395 %O print Thumb register mask (with PC)
4396 %M print Thumb register mask
4397 %b print CZB's 6-bit unsigned branch destination
4398 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 4399 %c print the condition code
4400 %C print the condition code, or "s" if not conditional
4401 %x print warning if conditional an not at end of IT block"
4402 %X print "\t; unpredictable <IT:code>" if conditional
4403 %I print IT instruction suffix and operands
4547cb56 4404 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 4405 %<bitfield>r print bitfield as an ARM register
4406 %<bitfield>d print bitfield as a decimal
4407 %<bitfield>H print (bitfield * 2) as a decimal
4408 %<bitfield>W print (bitfield * 4) as a decimal
4409 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
4410 %<bitfield>B print Thumb branch destination (signed displacement)
4411 %<bitfield>c print bitfield as a condition code
4412 %<bitnum>'c print specified char iff bit is one
4413 %<bitnum>?ab print a if bit is one else print b. */
4414
4415static const struct opcode16 thumb_opcodes[] =
4416{
4417 /* Thumb instructions. */
4418
16a1fa25
TP		 4419 /* ARMv8-M Security Extensions instructions. */
4420 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
e207bc53 4421 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
16a1fa25 4422
53c4b28b 4423 /* ARM V8 instructions. */
823d2571
TG		 4424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
4425 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
ddfded2f 4426 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
53c4b28b 4427
8f06b2d8 4428 /* ARM V6K no-argument instructions. */
823d2571
TG		 4429 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
4430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
4431 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
4432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
4433 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
4434 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 4435
4436 /* ARM V6T2 instructions. */
ff8646ee
TP		 4437 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4438 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4439 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4440 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 4441 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 4442
4443 /* ARM V6. */
823d2571
TG		 4444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
4445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
4446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4447 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4448 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
4450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
4451 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4453 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 4455
4456 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 4457 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4458 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 4459 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 4460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4461 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 4462 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 4463 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4464 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 4465 /* Format 4. */
823d2571
TG		 4466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4467 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4469 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4471 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4473 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4475 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4476 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4477 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4478 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4479 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4480 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4481 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 4482 /* format 13 */
823d2571
TG		 4483 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
4484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 4485 /* format 5 */
823d2571
TG		 4486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
4487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
4488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4489 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 4490 /* format 14 */
823d2571
TG		 4491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
4492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 4493 /* format 2 */
823d2571
TG		 4494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4495 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4497 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4499 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
4500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4501 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 4502 /* format 8 */
823d2571
TG		 4503 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4504 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4505 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4506 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4507 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4508 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 4509 /* format 7 */
823d2571
TG		 4510 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4511 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4513 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 4514 /* format 1 */
823d2571
TG		 4515 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4517 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
4518 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4519 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 4520 /* format 3 */
823d2571
TG		 4521 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
4522 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
4523 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
4524 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 4525 /* format 6 */
823d2571
TG		 4526 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4527 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4528 0x4800, 0xF800,
4529 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 4530 /* format 9 */
823d2571
TG		 4531 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4532 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
4533 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4534 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
4535 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4536 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
4537 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4538 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 4539 /* format 10 */
823d2571
TG		 4540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4541 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
4542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4543 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 4544 /* format 11 */
823d2571
TG		 4545 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4546 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
4547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4548 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 4549 /* format 12 */
823d2571
TG		 4550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4551 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
4552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4553 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 4554 /* format 15 */
823d2571
TG		 4555 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 4557 /* format 17 */
823d2571 4558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 4559 /* format 16 */
823d2571
TG		 4560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
4561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
4562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 4563 /* format 18 */
823d2571 4564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 4565
4566 /* The E800 .. FFFF range is unconditionally redirected to the
4567 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4568 are processed via that table. Thus, we can never encounter a
4569 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 4570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
4571 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 4572};
4573
4574/* Thumb32 opcodes use the same table structure as the ARM opcodes.
4575 We adopt the convention that hw1 is the high 16 bits of .value and
4576 .mask, hw2 the low 16 bits.
4577
4578 print_insn_thumb32 recognizes the following format control codes:
4579
4580 %% %
4581
4582 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4583 %M print a modified 12-bit immediate (same location)
4584 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4585 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 4586 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 4587 %S print a possibly-shifted Rm
4588
32a94698 4589 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 4590 %a print the address of a plain load/store
4591 %w print the width and signedness of a core load/store
4592 %m print register mask for ldm/stm
4b5a202f 4593 %n print register mask for clrm
8f06b2d8
PB		 4594
4595 %E print the lsb and width fields of a bfc/bfi instruction
4596 %F print the lsb and width fields of a sbfx/ubfx instruction
e12437dc 4597 %G print a fallback offset for Branch Future instructions
e5d6e09e 4598 %W print an offset for BF instruction
1caf72a5 4599 %Y print an offset for BFL instruction
1889da70 4600 %Z print an offset for BFCSEL instruction
60f993ce
AV		 4601 %Q print an offset for Low Overhead Loop instructions
4602 %P print an offset for Low Overhead Loop end instructions
8f06b2d8
PB		 4603 %b print a conditional branch offset
4604 %B print an unconditional branch offset
4605 %s print the shift field of an SSAT instruction
4606 %R print the rotation field of an SXT instruction
62b3e311
PB		 4607 %U print barrier type.
4608 %P print address for pli instruction.
c22aaad1
PB		 4609 %c print the condition code
4610 %x print warning if conditional an not at end of IT block"
4611 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 4612
4613 %<bitfield>d print bitfield in decimal
f0fba320 4614 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 4615 %<bitfield>W print bitfield*4 in decimal
4616 %<bitfield>r print bitfield as an ARM register
dd5181d5 4617 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
f1c7f421 4618 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
8f06b2d8
PB		 4619 %<bitfield>c print bitfield as a condition code
4620
16980d0b
JB		 4621 %<bitfield>'c print specified char iff bitfield is all ones
4622 %<bitfield>`c print specified char iff bitfield is all zeroes
4623 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 4624
4625 With one exception at the bottom (done because BL and BLX(1) need
4626 to come dead last), this table was machine-sorted first in
4627 decreasing order of number of bits set in the mask, then in
4628 increasing numeric order of mask, then in increasing numeric order
4629 of opcode. This order is not the clearest for a human reader, but
4630 is guaranteed never to catch a special-case bit pattern with a more
4631 general mask, which is important, because this instruction encoding
4632 makes heavy use of special-case bit patterns. */
4633static const struct opcode32 thumb32_opcodes[] =
4634{
4b5a202f
AV		 4635 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4636 instructions. */
60f993ce 4637 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
d052b9b7 4638 0xf00fe001, 0xffffffff, "lctp%c"},
60f993ce
AV		 4639 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4640 0xf02fc001, 0xfffff001, "le\t%P"},
4641 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4642 0xf00fc001, 0xfffff001, "le\tlr, %P"},
d052b9b7
AV		 4643 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4644 0xf01fc001, 0xfffff001, "letp\tlr, %P"},
4645 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4646 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
4647 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4648 0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
4649 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4650 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
4651 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4652 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
60f993ce 4653
4389b29a
AV		 4654 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4655 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
f1c7f421
AV		 4656 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4657 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
65d1bc05
AV		 4658 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4659 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
f1c7f421
AV		 4660 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4661 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
f6b2b12d
AV		 4662 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4663 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4389b29a 4664
4b5a202f
AV		 4665 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4666 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4389b29a 4667
16a1fa25
TP		 4668 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
4669 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4ed7ed8d
TP		 4670 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4671 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4672 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4673 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
16a1fa25
TP		 4674 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4675 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4676 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4677 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4ed7ed8d 4678
105bde57 4679 /* ARM V8.2 RAS extension instructions. */
4d1464f2 4680 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 4681 0xf3af8010, 0xffffffff, "esb"},
4682
53c4b28b 4683 /* V8 instructions. */
823d2571
TG		 4684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4685 0xf3af8005, 0xffffffff, "sevl%c.w"},
4686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4687 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4689 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4691 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4693 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4695 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4697 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4699 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4701 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4703 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4705 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4707 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4709 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4711 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4713 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4715 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 4716
dd5181d5 4717 /* CRC32 instructions. */
8b301fbb 4718 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4719 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4720 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4721 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
8b301fbb 4722 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4723 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4724 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4725 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4726 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4727 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4728 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4729 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
dd5181d5 4730
c597cc3d
SD		 4731 /* Speculation Barriers. */
4732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
4733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
4734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
4735
62b3e311 4736 /* V7 instructions. */
823d2571
TG		 4737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
4739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4744 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4745 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4746 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4747 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 4748
90ec0d68 4749 /* Virtualization Extension instructions. */
823d2571 4750 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 4751 /* We skip ERET as that is SUBS pc, lr, #0. */
4752
60e5ef9f 4753 /* MP Extension instructions. */
823d2571 4754 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 4755
f4c65163 4756 /* Security extension instructions. */
823d2571 4757 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 4758
7fadb25d
SD		 4759 /* ARMv8.5-A instructions. */
4760 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
4761
8f06b2d8 4762 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 4763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
4764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
4765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
4768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4769 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
4770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4771
ff8646ee 4772 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4773 0xf3bf8f2f, 0xffffffff, "clrex%c"},
4774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4775 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
4776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4777 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
4778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4779 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4781 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4783 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4785 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4787 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
4788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4789 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4791 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
4792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4793 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
4794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4795 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
4796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4797 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
4798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4799 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 4800 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 4801 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 4802 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4803 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4805 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
4806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4807 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
4808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4809 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4811 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4813 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4815 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4817 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4819 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 4820 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4821 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4823 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4825 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4827 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4829 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4831 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4833 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4835 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4837 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4839 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4841 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4843 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4845 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4847 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4849 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4851 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4853 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4855 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4857 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4859 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4861 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4863 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4865 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4867 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4869 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4871 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4873 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4875 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4877 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4879 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4881 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4883 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4885 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4887 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4889 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4891 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4893 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4895 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4897 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4899 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4901 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4903 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4905 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4907 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4909 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4911 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4913 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4915 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4917 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4919 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4921 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4923 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4925 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4927 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 4928 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4929 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 4931 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 4932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4933 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4935 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4937 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4939 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4941 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4943 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4945 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4947 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4949 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4951 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4953 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4955 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4957 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4959 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4961 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4963 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4965 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4967 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4969 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4971 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4973 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4975 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4977 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4979 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4981 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4983 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4985 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4987 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4989 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4991 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4993 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4995 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 4996 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4997 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
4998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4999 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
5000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5001 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
5002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5003 0xf810f000, 0xff70f000, "pld%c\t%a"},
5004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5005 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5007 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5009 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5011 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5013 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5015 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5017 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5019 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
5020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5021 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
5022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5023 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
5024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5025 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
5026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5027 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
5028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5029 0xfb100000, 0xfff000c0,
5030 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5032 0xfbc00080, 0xfff000c0,
5033 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
5034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5035 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
5036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5037 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
5038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 5039 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 5040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5041 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
5042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5043 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 5044 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 5045 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
5046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5047 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 5048 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 5049 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
5050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5051 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
5052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5053 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
5054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5055 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
5056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5057 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
5058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5059 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
5060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5061 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
5062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5063 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
5064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5065 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
5066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5067 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
5068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5069 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 5070 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 5071 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
5072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5073 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
5074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5075 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
5076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5077 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
5078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5079 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
5080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5081 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
5082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5083 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
5084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5085 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
5086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5087 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
5088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5089 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
5090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5091 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
5092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5093 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
5094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5095 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
5096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5097 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
5098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5099 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
5100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5101 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
5102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5103 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
5104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5105 0xe9400000, 0xff500000,
5106 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5108 0xe9500000, 0xff500000,
5109 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5111 0xe8600000, 0xff700000,
5112 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5114 0xe8700000, 0xff700000,
5115 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5117 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
5118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5119 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 5120
5121 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 5122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5123 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
5124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5125 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
5126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5127 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
5128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5129 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 5130
8f06b2d8 5131 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 5132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5133 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
5134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5135 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 5136
5137 /* Fallback. */
823d2571
TG		 5138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
5139 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
5140 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 5141};
ff4a8d2b 5142
8f06b2d8
PB		 5143static const char *const arm_conditional[] =
5144{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 5145 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 5146
5147static const char *const arm_fp_const[] =
5148{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
5149
5150static const char *const arm_shift[] =
5151{"lsl", "lsr", "asr", "ror"};
5152
5153typedef struct
5154{
5155 const char *name;
5156 const char *description;
5157 const char *reg_names[16];
5158}
5159arm_regname;
5160
5161static const arm_regname regnames[] =
5162{
65b48a81 5163 { "reg-names-raw", N_("Select raw register names"),
8f06b2d8 5164 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
65b48a81 5165 { "reg-names-gcc", N_("Select register names used by GCC"),
8f06b2d8 5166 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 5167 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
8f06b2d8 5168 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65b48a81
PB		 5169 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
5170 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
5171 { "reg-names-apcs", N_("Select register names used in the APCS"),
8f06b2d8 5172 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 5173 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
8f06b2d8 5174 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
65b48a81 5175 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
4934a27c
MM		 5176 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
5177 { "coproc<N>=(cde|generic)", N_("Enable CDE extensions for coprocessor N space"), { NULL } }
8f06b2d8
PB		 5178};
5179
5180static const char *const iwmmxt_wwnames[] =
5181{"b", "h", "w", "d"};
5182
5183static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 5184{"b", "bus", "bc", "bss",
5185 "h", "hus", "hc", "hss",
5186 "w", "wus", "wc", "wss",
5187 "d", "dus", "dc", "dss"
8f06b2d8
PB		 5188};
5189
5190static const char *const iwmmxt_regnames[] =
5191{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
5192 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
5193};
5194
5195static const char *const iwmmxt_cregnames[] =
5196{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
5197 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
5198};
5199
143275ea
AV		 5200static const char *const vec_condnames[] =
5201{ "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
5202};
5203
5204static const char *const mve_predicatenames[] =
5205{ "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
5206 "eee", "ee", "eet", "e", "ett", "et", "ete"
5207};
5208
5209/* Names for 2-bit size field for mve vector isntructions. */
5210static const char *const mve_vec_sizename[] =
5211 { "8", "16", "32", "64"};
5212
5213/* Indicates whether we are processing a then predicate,
5214 else predicate or none at all. */
5215enum vpt_pred_state
5216{
5217 PRED_NONE,
5218 PRED_THEN,
5219 PRED_ELSE
5220};
5221
5222/* Information used to process a vpt block and subsequent instructions. */
5223struct vpt_block
5224{
5225 /* Are we in a vpt block. */
5226 bfd_boolean in_vpt_block;
5227
5228 /* Next predicate state if in vpt block. */
5229 enum vpt_pred_state next_pred_state;
5230
5231 /* Mask from vpt/vpst instruction. */
5232 long predicate_mask;
5233
5234 /* Instruction number in vpt block. */
5235 long current_insn_num;
5236
5237 /* Number of instructions in vpt block.. */
5238 long num_pred_insn;
5239};
5240
5241static struct vpt_block vpt_block_state =
5242{
5243 FALSE,
5244 PRED_NONE,
5245 0,
5246 0,
5247 0
5248};
5249
8f06b2d8
PB		 5250/* Default to GCC register name set. */
5251static unsigned int regname_selected = 1;
5252
65b48a81 5253#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
8f06b2d8
PB		 5254#define arm_regnames regnames[regname_selected].reg_names
5255
5256static bfd_boolean force_thumb = FALSE;
4934a27c 5257static uint16_t cde_coprocs = 0;
8f06b2d8 5258
c22aaad1
PB		 5259/* Current IT instruction state. This contains the same state as the IT
5260 bits in the CPSR. */
5261static unsigned int ifthen_state;
5262/* IT state for the next instruction. */
5263static unsigned int ifthen_next_state;
5264/* The address of the insn for which the IT state is valid. */
5265static bfd_vma ifthen_address;
5266#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 5267/* Indicates that the current Conditional state is unconditional or outside
5268 an IT block. */
5269#define COND_UNCOND 16
c22aaad1 5270
8f06b2d8
PB		 5271\f
5272/* Functions. */
143275ea
AV		 5273/* Extract the predicate mask for a VPT or VPST instruction.
5274 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
5275
5276static long
5277mve_extract_pred_mask (long given)
5278{
5279 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
5280}
5281
5282/* Return the number of instructions in a MVE predicate block. */
5283static long
5284num_instructions_vpt_block (long given)
5285{
5286 long mask = mve_extract_pred_mask (given);
5287 if (mask == 0)
5288 return 0;
5289
5290 if (mask == 8)
5291 return 1;
5292
5293 if ((mask & 7) == 4)
5294 return 2;
5295
5296 if ((mask & 3) == 2)
5297 return 3;
5298
5299 if ((mask & 1) == 1)
5300 return 4;
5301
5302 return 0;
5303}
5304
5305static void
5306mark_outside_vpt_block (void)
5307{
5308 vpt_block_state.in_vpt_block = FALSE;
5309 vpt_block_state.next_pred_state = PRED_NONE;
5310 vpt_block_state.predicate_mask = 0;
5311 vpt_block_state.current_insn_num = 0;
5312 vpt_block_state.num_pred_insn = 0;
5313}
5314
5315static void
5316mark_inside_vpt_block (long given)
5317{
5318 vpt_block_state.in_vpt_block = TRUE;
5319 vpt_block_state.next_pred_state = PRED_THEN;
5320 vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
5321 vpt_block_state.current_insn_num = 0;
5322 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
5323 assert (vpt_block_state.num_pred_insn >= 1);
5324}
5325
5326static enum vpt_pred_state
5327invert_next_predicate_state (enum vpt_pred_state astate)
5328{
5329 if (astate == PRED_THEN)
5330 return PRED_ELSE;
5331 else if (astate == PRED_ELSE)
5332 return PRED_THEN;
5333 else
5334 return PRED_NONE;
5335}
5336
5337static enum vpt_pred_state
5338update_next_predicate_state (void)
5339{
5340 long pred_mask = vpt_block_state.predicate_mask;
5341 long mask_for_insn = 0;
5342
5343 switch (vpt_block_state.current_insn_num)
5344 {
5345 case 1:
5346 mask_for_insn = 8;
5347 break;
5348
5349 case 2:
5350 mask_for_insn = 4;
5351 break;
5352
5353 case 3:
5354 mask_for_insn = 2;
5355 break;
5356
5357 case 4:
5358 return PRED_NONE;
5359 }
5360
5361 if (pred_mask & mask_for_insn)
5362 return invert_next_predicate_state (vpt_block_state.next_pred_state);
5363 else
5364 return vpt_block_state.next_pred_state;
5365}
5366
5367static void
5368update_vpt_block_state (void)
5369{
5370 vpt_block_state.current_insn_num++;
5371 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
5372 {
5373 /* No more instructions to process in vpt block. */
5374 mark_outside_vpt_block ();
5375 return;
5376 }
5377
5378 vpt_block_state.next_pred_state = update_next_predicate_state ();
5379}
8f06b2d8 5380
16980d0b
JB		 5381/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5382 Returns pointer to following character of the format string and
5383 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 5384 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 5385
5386static const char *
fe56b6ce
NC		 5387arm_decode_bitfield (const char *ptr,
5388 unsigned long insn,
5389 unsigned long *valuep,
5390 int *widthp)
16980d0b
JB		 5391{
5392 unsigned long value = 0;
5393 int width = 0;
43e65147
L		 5394
5395 do
16980d0b
JB		 5396 {
5397 int start, end;
5398 int bits;
5399
5400 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
5401 start = start * 10 + *ptr - '0';
5402 if (*ptr == '-')
5403 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
5404 end = end * 10 + *ptr - '0';
5405 else
5406 end = start;
5407 bits = end - start;
5408 if (bits < 0)
5409 abort ();
5410 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
5411 width += bits + 1;
5412 }
5413 while (*ptr++ == ',');
5414 *valuep = value;
5415 if (widthp)
5416 *widthp = width;
5417 return ptr - 1;
5418}
5419
8f06b2d8 5420static void
37b37b2d 5421arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 5422 bfd_boolean print_shift)
8f06b2d8
PB		 5423{
5424 func (stream, "%s", arm_regnames[given & 0xf]);
5425
5426 if ((given & 0xff0) != 0)
5427 {
5428 if ((given & 0x10) == 0)
5429 {
5430 int amount = (given & 0xf80) >> 7;
5431 int shift = (given & 0x60) >> 5;
5432
5433 if (amount == 0)
5434 {
5435 if (shift == 3)
5436 {
5437 func (stream, ", rrx");
5438 return;
5439 }
5440
5441 amount = 32;
5442 }
5443
37b37b2d
RE		 5444 if (print_shift)
5445 func (stream, ", %s #%d", arm_shift[shift], amount);
5446 else
5447 func (stream, ", #%d", amount);
8f06b2d8 5448 }
74bdfecf 5449 else if ((given & 0x80) == 0x80)
aefd8a40 5450 func (stream, "\t; <illegal shifter operand>");
37b37b2d 5451 else if (print_shift)
8f06b2d8
PB		 5452 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
5453 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 5454 else
5455 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 5456 }
5457}
5458
73cd51e5
AV		 5459/* Return TRUE if the MATCHED_INSN can be inside an IT block. */
5460
5461static bfd_boolean
5462is_mve_okay_in_it (enum mve_instructions matched_insn)
5463{
c507f10b
AV		 5464 switch (matched_insn)
5465 {
5466 case MVE_VMOV_GP_TO_VEC_LANE:
5467 case MVE_VMOV2_VEC_LANE_TO_GP:
5468 case MVE_VMOV2_GP_TO_VEC_LANE:
5469 case MVE_VMOV_VEC_LANE_TO_GP:
23d00a41
SD		 5470 case MVE_LSLL:
5471 case MVE_LSLLI:
5472 case MVE_LSRL:
5473 case MVE_ASRL:
5474 case MVE_ASRLI:
5475 case MVE_SQRSHRL:
5476 case MVE_SQRSHR:
5477 case MVE_UQRSHL:
5478 case MVE_UQRSHLL:
5479 case MVE_UQSHL:
5480 case MVE_UQSHLL:
5481 case MVE_URSHRL:
5482 case MVE_URSHR:
5483 case MVE_SRSHRL:
5484 case MVE_SRSHR:
5485 case MVE_SQSHLL:
5486 case MVE_SQSHL:
c507f10b
AV		 5487 return TRUE;
5488 default:
5489 return FALSE;
5490 }
73cd51e5
AV		 5491}
5492
5493static bfd_boolean
5494is_mve_architecture (struct disassemble_info *info)
5495{
5496 struct arm_private_data *private_data = info->private_data;
5497 arm_feature_set allowed_arches = private_data->features;
5498
5499 arm_feature_set arm_ext_v8_1m_main
5500 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
5501
5502 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
5503 && !ARM_CPU_IS_ANY (allowed_arches))
5504 return TRUE;
5505 else
5506 return FALSE;
5507}
5508
143275ea
AV		 5509static bfd_boolean
5510is_vpt_instruction (long given)
5511{
5512
5513 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
5514 if ((given & 0x0040e000) == 0)
5515 return FALSE;
5516
5517 /* VPT floating point T1 variant. */
5518 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
5519 /* VPT floating point T2 variant. */
5520 || ((given & 0xefb10f50) == 0xee310f40)
5521 /* VPT vector T1 variant. */
5522 || ((given & 0xff811f51) == 0xfe010f00)
5523 /* VPT vector T2 variant. */
5524 || ((given & 0xff811f51) == 0xfe010f01
5525 && ((given & 0x300000) != 0x300000))
5526 /* VPT vector T3 variant. */
5527 || ((given & 0xff811f50) == 0xfe011f00)
5528 /* VPT vector T4 variant. */
5529 || ((given & 0xff811f70) == 0xfe010f40)
5530 /* VPT vector T5 variant. */
5531 || ((given & 0xff811f70) == 0xfe010f60)
5532 /* VPT vector T6 variant. */
5533 || ((given & 0xff811f50) == 0xfe011f40)
5534 /* VPST vector T variant. */
5535 || ((given & 0xffbf1fff) == 0xfe310f4d))
5536 return TRUE;
5537 else
5538 return FALSE;
5539}
5540
73cd51e5
AV		 5541/* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5542 and ending bitfield = END. END must be greater than START. */
5543
5544static unsigned long
5545arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
5546{
5547 int bits = end - start;
5548
5549 if (bits < 0)
5550 abort ();
5551
5552 return ((given >> start) & ((2ul << bits) - 1));
5553}
5554
5555/* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5556 START:END and START2:END2. END/END2 must be greater than
5557 START/START2. */
5558
5559static unsigned long
5560arm_decode_field_multiple (unsigned long given, unsigned int start,
5561 unsigned int end, unsigned int start2,
5562 unsigned int end2)
5563{
5564 int bits = end - start;
5565 int bits2 = end2 - start2;
5566 unsigned long value = 0;
5567 int width = 0;
5568
5569 if (bits2 < 0)
5570 abort ();
5571
5572 value = arm_decode_field (given, start, end);
5573 width += bits + 1;
5574
5575 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
5576 return value;
5577}
5578
5579/* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5580 This helps us decode instructions that change mnemonic depending on specific
5581 operand values/encodings. */
5582
5583static bfd_boolean
5584is_mve_encoding_conflict (unsigned long given,
5585 enum mve_instructions matched_insn)
5586{
143275ea
AV		 5587 switch (matched_insn)
5588 {
5589 case MVE_VPST:
5590 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5591 return TRUE;
5592 else
5593 return FALSE;
5594
5595 case MVE_VPT_FP_T1:
5596 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5597 return TRUE;
5598 if ((arm_decode_field (given, 12, 12) == 0)
5599 && (arm_decode_field (given, 0, 0) == 1))
5600 return TRUE;
5601 return FALSE;
5602
5603 case MVE_VPT_FP_T2:
5604 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5605 return TRUE;
5606 if (arm_decode_field (given, 0, 3) == 0xd)
5607 return TRUE;
5608 return FALSE;
5609
5610 case MVE_VPT_VEC_T1:
5611 case MVE_VPT_VEC_T2:
5612 case MVE_VPT_VEC_T3:
5613 case MVE_VPT_VEC_T4:
5614 case MVE_VPT_VEC_T5:
5615 case MVE_VPT_VEC_T6:
5616 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5617 return TRUE;
5618 if (arm_decode_field (given, 20, 21) == 3)
5619 return TRUE;
5620 return FALSE;
5621
5622 case MVE_VCMP_FP_T1:
5623 if ((arm_decode_field (given, 12, 12) == 0)
5624 && (arm_decode_field (given, 0, 0) == 1))
5625 return TRUE;
5626 else
5627 return FALSE;
5628
5629 case MVE_VCMP_FP_T2:
5630 if (arm_decode_field (given, 0, 3) == 0xd)
5631 return TRUE;
5632 else
5633 return FALSE;
5634
14b456f2
AV		 5635 case MVE_VQADD_T2:
5636 case MVE_VQSUB_T2:
f49bb598
AV		 5637 case MVE_VMUL_VEC_T2:
5638 case MVE_VMULH:
5639 case MVE_VRMULH:
56858bea
AV		 5640 case MVE_VMLA:
5641 case MVE_VMAX:
5642 case MVE_VMIN:
e523f101 5643 case MVE_VBRSR:
66dcaa5d
AV		 5644 case MVE_VADD_VEC_T2:
5645 case MVE_VSUB_VEC_T2:
5646 case MVE_VABAV:
ed63aa17
AV		 5647 case MVE_VQRSHL_T1:
5648 case MVE_VQSHL_T4:
5649 case MVE_VRSHL_T1:
5650 case MVE_VSHL_T3:
897b9bbc
AV		 5651 case MVE_VCADD_VEC:
5652 case MVE_VHCADD:
1c8f2df8
AV		 5653 case MVE_VDDUP:
5654 case MVE_VIDUP:
d3b63143
AV		 5655 case MVE_VQRDMLADH:
5656 case MVE_VQDMLAH:
5657 case MVE_VQRDMLAH:
5658 case MVE_VQDMLASH:
5659 case MVE_VQRDMLASH:
5660 case MVE_VQDMLSDH:
5661 case MVE_VQRDMLSDH:
5662 case MVE_VQDMULH_T3:
5663 case MVE_VQRDMULH_T4:
5664 case MVE_VQDMLADH:
5665 case MVE_VMLAS:
14925797 5666 case MVE_VMULL_INT:
9743db03
AV		 5667 case MVE_VHADD_T2:
5668 case MVE_VHSUB_T2:
143275ea
AV		 5669 case MVE_VCMP_VEC_T1:
5670 case MVE_VCMP_VEC_T2:
5671 case MVE_VCMP_VEC_T3:
5672 case MVE_VCMP_VEC_T4:
5673 case MVE_VCMP_VEC_T5:
5674 case MVE_VCMP_VEC_T6:
5675 if (arm_decode_field (given, 20, 21) == 3)
5676 return TRUE;
5677 else
5678 return FALSE;
5679
04d54ace
AV		 5680 case MVE_VLD2:
5681 case MVE_VLD4:
5682 case MVE_VST2:
5683 case MVE_VST4:
5684 if (arm_decode_field (given, 7, 8) == 3)
5685 return TRUE;
5686 else
5687 return FALSE;
5688
aef6d006
AV		 5689 case MVE_VSTRB_T1:
5690 case MVE_VSTRH_T2:
5691 if ((arm_decode_field (given, 24, 24) == 0)
5692 && (arm_decode_field (given, 21, 21) == 0))
5693 {
5694 return TRUE;
5695 }
5696 else if ((arm_decode_field (given, 7, 8) == 3))
5697 return TRUE;
5698 else
5699 return FALSE;
5700
5701 case MVE_VSTRB_T5:
5702 case MVE_VSTRH_T6:
5703 case MVE_VSTRW_T7:
5704 if ((arm_decode_field (given, 24, 24) == 0)
5705 && (arm_decode_field (given, 21, 21) == 0))
5706 {
5707 return TRUE;
5708 }
5709 else
5710 return FALSE;
5711
bf0b396d
AV		 5712 case MVE_VCVT_FP_FIX_VEC:
5713 return (arm_decode_field (given, 16, 21) & 0x38) == 0;
5714
c507f10b
AV		 5715 case MVE_VBIC_IMM:
5716 case MVE_VORR_IMM:
5717 {
5718 unsigned long cmode = arm_decode_field (given, 8, 11);
5719
5720 if ((cmode & 1) == 0)
5721 return TRUE;
5722 else if ((cmode & 0xc) == 0xc)
5723 return TRUE;
5724 else
5725 return FALSE;
5726 }
5727
5728 case MVE_VMVN_IMM:
5729 {
5730 unsigned long cmode = arm_decode_field (given, 8, 11);
5731
ce760a76 5732 if (cmode == 0xe)
c507f10b 5733 return TRUE;
ce760a76 5734 else if ((cmode & 0x9) == 1)
c507f10b 5735 return TRUE;
ce760a76 5736 else if ((cmode & 0xd) == 9)
c507f10b
AV		 5737 return TRUE;
5738 else
5739 return FALSE;
5740 }
5741
5742 case MVE_VMOV_IMM_TO_VEC:
5743 if ((arm_decode_field (given, 5, 5) == 1)
5744 && (arm_decode_field (given, 8, 11) != 0xe))
5745 return TRUE;
5746 else
5747 return FALSE;
5748
14925797
AV		 5749 case MVE_VMOVL:
5750 {
5751 unsigned long size = arm_decode_field (given, 19, 20);
5752 if ((size == 0) || (size == 3))
5753 return TRUE;
5754 else
5755 return FALSE;
5756 }
5757
56858bea
AV		 5758 case MVE_VMAXA:
5759 case MVE_VMINA:
5760 case MVE_VMAXV:
5761 case MVE_VMAXAV:
5762 case MVE_VMINV:
5763 case MVE_VMINAV:
ed63aa17
AV		 5764 case MVE_VQRSHL_T2:
5765 case MVE_VQSHL_T1:
5766 case MVE_VRSHL_T2:
5767 case MVE_VSHL_T2:
5768 case MVE_VSHLL_T2:
d3b63143 5769 case MVE_VADDV:
14925797
AV		 5770 case MVE_VMOVN:
5771 case MVE_VQMOVUN:
5772 case MVE_VQMOVN:
5773 if (arm_decode_field (given, 18, 19) == 3)
5774 return TRUE;
5775 else
5776 return FALSE;
5777
d3b63143
AV		 5778 case MVE_VMLSLDAV:
5779 case MVE_VRMLSLDAVH:
5780 case MVE_VMLALDAV:
5781 case MVE_VADDLV:
5782 if (arm_decode_field (given, 20, 22) == 7)
5783 return TRUE;
5784 else
5785 return FALSE;
5786
5787 case MVE_VRMLALDAVH:
5788 if ((arm_decode_field (given, 20, 22) & 6) == 6)
5789 return TRUE;
5790 else
5791 return FALSE;
5792
1c8f2df8
AV		 5793 case MVE_VDWDUP:
5794 case MVE_VIWDUP:
5795 if ((arm_decode_field (given, 20, 21) == 3)
5796 || (arm_decode_field (given, 1, 3) == 7))
5797 return TRUE;
5798 else
5799 return FALSE;
5800
ed63aa17
AV		 5801
5802 case MVE_VSHLL_T1:
5803 if (arm_decode_field (given, 16, 18) == 0)
5804 {
5805 unsigned long sz = arm_decode_field (given, 19, 20);
5806
5807 if ((sz == 1) || (sz == 2))
5808 return TRUE;
5809 else
5810 return FALSE;
5811 }
5812 else
5813 return FALSE;
5814
5815 case MVE_VQSHL_T2:
5816 case MVE_VQSHLU_T3:
5817 case MVE_VRSHR:
5818 case MVE_VSHL_T1:
5819 case MVE_VSHR:
5820 case MVE_VSLI:
5821 case MVE_VSRI:
5822 if (arm_decode_field (given, 19, 21) == 0)
5823 return TRUE;
5824 else
5825 return FALSE;
5826
e523f101
AV		 5827 case MVE_VCTP:
5828 if (arm_decode_field (given, 16, 19) == 0xf)
5829 return TRUE;
5830 else
5831 return FALSE;
5832
23d00a41
SD		 5833 case MVE_ASRLI:
5834 case MVE_ASRL:
5835 case MVE_LSLLI:
5836 case MVE_LSLL:
5837 case MVE_LSRL:
5838 case MVE_SQRSHRL:
5839 case MVE_SQSHLL:
5840 case MVE_SRSHRL:
5841 case MVE_UQRSHLL:
5842 case MVE_UQSHLL:
5843 case MVE_URSHRL:
5844 if (arm_decode_field (given, 9, 11) == 0x7)
5845 return TRUE;
5846 else
5847 return FALSE;
5848
e39c1607
SD		 5849 case MVE_CSINC:
5850 case MVE_CSINV:
5851 {
5852 unsigned long rm, rn;
5853 rm = arm_decode_field (given, 0, 3);
5854 rn = arm_decode_field (given, 16, 19);
5855 /* CSET/CSETM. */
5856 if (rm == 0xf && rn == 0xf)
5857 return TRUE;
5858 /* CINC/CINV. */
5859 else if (rn == rm && rn != 0xf)
5860 return TRUE;
5861 }
5862 /* Fall through. */
5863 case MVE_CSEL:
5864 case MVE_CSNEG:
5865 if (arm_decode_field (given, 0, 3) == 0xd)
5866 return TRUE;
5867 /* CNEG. */
5868 else if (matched_insn == MVE_CSNEG)
5869 if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19))
5870 return TRUE;
5871 return FALSE;
5872
143275ea 5873 default:
66dcaa5d
AV		 5874 case MVE_VADD_FP_T1:
5875 case MVE_VADD_FP_T2:
5876 case MVE_VADD_VEC_T1:
143275ea
AV		 5877 return FALSE;
5878
5879 }
73cd51e5
AV		 5880}
5881
aef6d006
AV		 5882static void
5883print_mve_vld_str_addr (struct disassemble_info *info,
5884 unsigned long given,
5885 enum mve_instructions matched_insn)
5886{
5887 void *stream = info->stream;
5888 fprintf_ftype func = info->fprintf_func;
5889
5890 unsigned long p, w, gpr, imm, add, mod_imm;
5891
5892 imm = arm_decode_field (given, 0, 6);
5893 mod_imm = imm;
5894
5895 switch (matched_insn)
5896 {
5897 case MVE_VLDRB_T1:
5898 case MVE_VSTRB_T1:
5899 gpr = arm_decode_field (given, 16, 18);
5900 break;
5901
5902 case MVE_VLDRH_T2:
5903 case MVE_VSTRH_T2:
5904 gpr = arm_decode_field (given, 16, 18);
5905 mod_imm = imm << 1;
5906 break;
5907
5908 case MVE_VLDRH_T6:
5909 case MVE_VSTRH_T6:
5910 gpr = arm_decode_field (given, 16, 19);
5911 mod_imm = imm << 1;
5912 break;
5913
5914 case MVE_VLDRW_T7:
5915 case MVE_VSTRW_T7:
5916 gpr = arm_decode_field (given, 16, 19);
5917 mod_imm = imm << 2;
5918 break;
5919
5920 case MVE_VLDRB_T5:
5921 case MVE_VSTRB_T5:
5922 gpr = arm_decode_field (given, 16, 19);
5923 break;
5924
5925 default:
5926 return;
5927 }
5928
5929 p = arm_decode_field (given, 24, 24);
5930 w = arm_decode_field (given, 21, 21);
5931
5932 add = arm_decode_field (given, 23, 23);
5933
5934 char * add_sub;
5935
5936 /* Don't print anything for '+' as it is implied. */
5937 if (add == 1)
5938 add_sub = "";
5939 else
5940 add_sub = "-";
5941
5942 if (p == 1)
5943 {
5944 /* Offset mode. */
5945 if (w == 0)
5946 func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm);
5947 /* Pre-indexed mode. */
5948 else
5949 func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm);
5950 }
5951 else if ((p == 0) && (w == 1))
5952 /* Post-index mode. */
5953 func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm);
5954}
5955
73cd51e5
AV		 5956/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5957 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5958 this encoding is undefined. */
5959
5960static bfd_boolean
5961is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
5962 enum mve_undefined *undefined_code)
5963{
5964 *undefined_code = UNDEF_NONE;
5965
9743db03
AV		 5966 switch (matched_insn)
5967 {
5968 case MVE_VDUP:
5969 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
5970 {
5971 *undefined_code = UNDEF_SIZE_3;
5972 return TRUE;
5973 }
5974 else
5975 return FALSE;
5976
14b456f2
AV		 5977 case MVE_VQADD_T1:
5978 case MVE_VQSUB_T1:
f49bb598 5979 case MVE_VMUL_VEC_T1:
66dcaa5d
AV		 5980 case MVE_VABD_VEC:
5981 case MVE_VADD_VEC_T1:
5982 case MVE_VSUB_VEC_T1:
d3b63143
AV		 5983 case MVE_VQDMULH_T1:
5984 case MVE_VQRDMULH_T2:
9743db03
AV		 5985 case MVE_VRHADD:
5986 case MVE_VHADD_T1:
5987 case MVE_VHSUB_T1:
5988 if (arm_decode_field (given, 20, 21) == 3)
5989 {
5990 *undefined_code = UNDEF_SIZE_3;
5991 return TRUE;
5992 }
5993 else
5994 return FALSE;
5995
aef6d006
AV		 5996 case MVE_VLDRB_T1:
5997 if (arm_decode_field (given, 7, 8) == 3)
5998 {
5999 *undefined_code = UNDEF_SIZE_3;
6000 return TRUE;
6001 }
6002 else
6003 return FALSE;
6004
6005 case MVE_VLDRH_T2:
6006 if (arm_decode_field (given, 7, 8) <= 1)
6007 {
6008 *undefined_code = UNDEF_SIZE_LE_1;
6009 return TRUE;
6010 }
6011 else
6012 return FALSE;
6013
6014 case MVE_VSTRB_T1:
6015 if ((arm_decode_field (given, 7, 8) == 0))
6016 {
6017 *undefined_code = UNDEF_SIZE_0;
6018 return TRUE;
6019 }
6020 else
6021 return FALSE;
6022
6023 case MVE_VSTRH_T2:
6024 if ((arm_decode_field (given, 7, 8) <= 1))
6025 {
6026 *undefined_code = UNDEF_SIZE_LE_1;
6027 return TRUE;
6028 }
6029 else
6030 return FALSE;
6031
ef1576a1
AV		 6032 case MVE_VLDRB_GATHER_T1:
6033 if (arm_decode_field (given, 7, 8) == 3)
6034 {
6035 *undefined_code = UNDEF_SIZE_3;
6036 return TRUE;
6037 }
6038 else if ((arm_decode_field (given, 28, 28) == 0)
6039 && (arm_decode_field (given, 7, 8) == 0))
6040 {
6041 *undefined_code = UNDEF_NOT_UNS_SIZE_0;
6042 return TRUE;
6043 }
6044 else
6045 return FALSE;
6046
6047 case MVE_VLDRH_GATHER_T2:
6048 if (arm_decode_field (given, 7, 8) == 3)
6049 {
6050 *undefined_code = UNDEF_SIZE_3;
6051 return TRUE;
6052 }
6053 else if ((arm_decode_field (given, 28, 28) == 0)
6054 && (arm_decode_field (given, 7, 8) == 1))
6055 {
6056 *undefined_code = UNDEF_NOT_UNS_SIZE_1;
6057 return TRUE;
6058 }
6059 else if (arm_decode_field (given, 7, 8) == 0)
6060 {
6061 *undefined_code = UNDEF_SIZE_0;
6062 return TRUE;
6063 }
6064 else
6065 return FALSE;
6066
6067 case MVE_VLDRW_GATHER_T3:
6068 if (arm_decode_field (given, 7, 8) != 2)
6069 {
6070 *undefined_code = UNDEF_SIZE_NOT_2;
6071 return TRUE;
6072 }
6073 else if (arm_decode_field (given, 28, 28) == 0)
6074 {
6075 *undefined_code = UNDEF_NOT_UNSIGNED;
6076 return TRUE;
6077 }
6078 else
6079 return FALSE;
6080
6081 case MVE_VLDRD_GATHER_T4:
6082 if (arm_decode_field (given, 7, 8) != 3)
6083 {
6084 *undefined_code = UNDEF_SIZE_NOT_3;
6085 return TRUE;
6086 }
6087 else if (arm_decode_field (given, 28, 28) == 0)
6088 {
6089 *undefined_code = UNDEF_NOT_UNSIGNED;
6090 return TRUE;
6091 }
6092 else
6093 return FALSE;
6094
6095 case MVE_VSTRB_SCATTER_T1:
6096 if (arm_decode_field (given, 7, 8) == 3)
6097 {
6098 *undefined_code = UNDEF_SIZE_3;
6099 return TRUE;
6100 }
6101 else
6102 return FALSE;
6103
6104 case MVE_VSTRH_SCATTER_T2:
6105 {
6106 unsigned long size = arm_decode_field (given, 7, 8);
6107 if (size == 3)
6108 {
6109 *undefined_code = UNDEF_SIZE_3;
6110 return TRUE;
6111 }
6112 else if (size == 0)
6113 {
6114 *undefined_code = UNDEF_SIZE_0;
6115 return TRUE;
6116 }
6117 else
6118 return FALSE;
6119 }
6120
6121 case MVE_VSTRW_SCATTER_T3:
6122 if (arm_decode_field (given, 7, 8) != 2)
6123 {
6124 *undefined_code = UNDEF_SIZE_NOT_2;
6125 return TRUE;
6126 }
6127 else
6128 return FALSE;
6129
6130 case MVE_VSTRD_SCATTER_T4:
6131 if (arm_decode_field (given, 7, 8) != 3)
6132 {
6133 *undefined_code = UNDEF_SIZE_NOT_3;
6134 return TRUE;
6135 }
6136 else
6137 return FALSE;
6138
bf0b396d
AV		 6139 case MVE_VCVT_FP_FIX_VEC:
6140 {
6141 unsigned long imm6 = arm_decode_field (given, 16, 21);
6142 if ((imm6 & 0x20) == 0)
6143 {
6144 *undefined_code = UNDEF_VCVT_IMM6;
6145 return TRUE;
6146 }
6147
6148 if ((arm_decode_field (given, 9, 9) == 0)
6149 && ((imm6 & 0x30) == 0x20))
6150 {
6151 *undefined_code = UNDEF_VCVT_FSI_IMM6;
6152 return TRUE;
6153 }
6154
6155 return FALSE;
6156 }
6157
f49bb598 6158 case MVE_VNEG_FP:
66dcaa5d 6159 case MVE_VABS_FP:
bf0b396d
AV		 6160 case MVE_VCVT_BETWEEN_FP_INT:
6161 case MVE_VCVT_FROM_FP_TO_INT:
6162 {
6163 unsigned long size = arm_decode_field (given, 18, 19);
6164 if (size == 0)
6165 {
6166 *undefined_code = UNDEF_SIZE_0;
6167 return TRUE;
6168 }
6169 else if (size == 3)
6170 {
6171 *undefined_code = UNDEF_SIZE_3;
6172 return TRUE;
6173 }
6174 else
6175 return FALSE;
6176 }
6177
c507f10b
AV		 6178 case MVE_VMOV_VEC_LANE_TO_GP:
6179 {
6180 unsigned long op1 = arm_decode_field (given, 21, 22);
6181 unsigned long op2 = arm_decode_field (given, 5, 6);
6182 unsigned long u = arm_decode_field (given, 23, 23);
6183
6184 if ((op2 == 0) && (u == 1))
6185 {
6186 if ((op1 == 0) || (op1 == 1))
6187 {
6188 *undefined_code = UNDEF_BAD_U_OP1_OP2;
6189 return TRUE;
6190 }
6191 else
6192 return FALSE;
6193 }
6194 else if (op2 == 2)
6195 {
6196 if ((op1 == 0) || (op1 == 1))
6197 {
6198 *undefined_code = UNDEF_BAD_OP1_OP2;
6199 return TRUE;
6200 }
6201 else
6202 return FALSE;
6203 }
6204
6205 return FALSE;
6206 }
6207
6208 case MVE_VMOV_GP_TO_VEC_LANE:
6209 if (arm_decode_field (given, 5, 6) == 2)
6210 {
6211 unsigned long op1 = arm_decode_field (given, 21, 22);
6212 if ((op1 == 0) || (op1 == 1))
6213 {
6214 *undefined_code = UNDEF_BAD_OP1_OP2;
6215 return TRUE;
6216 }
6217 else
6218 return FALSE;
6219 }
6220 else
6221 return FALSE;
6222
c4a23bf8
SP		 6223 case MVE_VMOV_VEC_TO_VEC:
6224 if ((arm_decode_field (given, 5, 5) == 1)
6225 || (arm_decode_field (given, 22, 22) == 1))
6226 return TRUE;
6227 return FALSE;
6228
c507f10b
AV		 6229 case MVE_VMOV_IMM_TO_VEC:
6230 if (arm_decode_field (given, 5, 5) == 0)
6231 {
6232 unsigned long cmode = arm_decode_field (given, 8, 11);
6233
6234 if (((cmode & 9) == 1) || ((cmode & 5) == 1))
6235 {
6236 *undefined_code = UNDEF_OP_0_BAD_CMODE;
6237 return TRUE;
6238 }
6239 else
6240 return FALSE;
6241 }
6242 else
6243 return FALSE;
6244
ed63aa17 6245 case MVE_VSHLL_T2:
14925797
AV		 6246 case MVE_VMOVN:
6247 if (arm_decode_field (given, 18, 19) == 2)
6248 {
6249 *undefined_code = UNDEF_SIZE_2;
6250 return TRUE;
6251 }
6252 else
6253 return FALSE;
6254
d3b63143
AV		 6255 case MVE_VRMLALDAVH:
6256 case MVE_VMLADAV_T1:
6257 case MVE_VMLADAV_T2:
6258 case MVE_VMLALDAV:
6259 if ((arm_decode_field (given, 28, 28) == 1)
6260 && (arm_decode_field (given, 12, 12) == 1))
6261 {
6262 *undefined_code = UNDEF_XCHG_UNS;
6263 return TRUE;
6264 }
6265 else
6266 return FALSE;
6267
ed63aa17
AV		 6268 case MVE_VQSHRN:
6269 case MVE_VQSHRUN:
6270 case MVE_VSHLL_T1:
6271 case MVE_VSHRN:
6272 {
6273 unsigned long sz = arm_decode_field (given, 19, 20);
6274 if (sz == 1)
6275 return FALSE;
6276 else if ((sz & 2) == 2)
6277 return FALSE;
6278 else
6279 {
6280 *undefined_code = UNDEF_SIZE;
6281 return TRUE;
6282 }
6283 }
6284 break;
6285
6286 case MVE_VQSHL_T2:
6287 case MVE_VQSHLU_T3:
6288 case MVE_VRSHR:
6289 case MVE_VSHL_T1:
6290 case MVE_VSHR:
6291 case MVE_VSLI:
6292 case MVE_VSRI:
6293 {
6294 unsigned long sz = arm_decode_field (given, 19, 21);
6295 if ((sz & 7) == 1)
6296 return FALSE;
6297 else if ((sz & 6) == 2)
6298 return FALSE;
6299 else if ((sz & 4) == 4)
6300 return FALSE;
6301 else
6302 {
6303 *undefined_code = UNDEF_SIZE;
6304 return TRUE;
6305 }
6306 }
6307
6308 case MVE_VQRSHRN:
6309 case MVE_VQRSHRUN:
6310 if (arm_decode_field (given, 19, 20) == 0)
6311 {
6312 *undefined_code = UNDEF_SIZE_0;
6313 return TRUE;
6314 }
6315 else
6316 return FALSE;
6317
66dcaa5d
AV		 6318 case MVE_VABS_VEC:
6319 if (arm_decode_field (given, 18, 19) == 3)
6320 {
6321 *undefined_code = UNDEF_SIZE_3;
6322 return TRUE;
6323 }
6324 else
6325 return FALSE;
6326
14b456f2
AV		 6327 case MVE_VQNEG:
6328 case MVE_VQABS:
f49bb598 6329 case MVE_VNEG_VEC:
e523f101
AV		 6330 case MVE_VCLS:
6331 case MVE_VCLZ:
6332 if (arm_decode_field (given, 18, 19) == 3)
6333 {
6334 *undefined_code = UNDEF_SIZE_3;
6335 return TRUE;
6336 }
6337 else
6338 return FALSE;
6339
14b456f2
AV		 6340 case MVE_VREV16:
6341 if (arm_decode_field (given, 18, 19) == 0)
6342 return FALSE;
6343 else
6344 {
6345 *undefined_code = UNDEF_SIZE_NOT_0;
6346 return TRUE;
6347 }
6348
6349 case MVE_VREV32:
6350 {
6351 unsigned long size = arm_decode_field (given, 18, 19);
6352 if ((size & 2) == 2)
6353 {
6354 *undefined_code = UNDEF_SIZE_2;
6355 return TRUE;
6356 }
6357 else
6358 return FALSE;
6359 }
6360
6361 case MVE_VREV64:
6362 if (arm_decode_field (given, 18, 19) != 3)
6363 return FALSE;
6364 else
6365 {
6366 *undefined_code = UNDEF_SIZE_3;
6367 return TRUE;
6368 }
6369
9743db03
AV		 6370 default:
6371 return FALSE;
6372 }
73cd51e5
AV		 6373}
6374
6375/* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6376 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
6377 why this encoding is unpredictable. */
6378
6379static bfd_boolean
6380is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
6381 enum mve_unpredictable *unpredictable_code)
6382{
6383 *unpredictable_code = UNPRED_NONE;
6384
143275ea
AV		 6385 switch (matched_insn)
6386 {
6387 case MVE_VCMP_FP_T2:
6388 case MVE_VPT_FP_T2:
6389 if ((arm_decode_field (given, 12, 12) == 0)
6390 && (arm_decode_field (given, 5, 5) == 1))
6391 {
6392 *unpredictable_code = UNPRED_FCA_0_FCB_1;
6393 return TRUE;
6394 }
6395 else
6396 return FALSE;
73cd51e5 6397
143275ea
AV		 6398 case MVE_VPT_VEC_T4:
6399 case MVE_VPT_VEC_T5:
6400 case MVE_VPT_VEC_T6:
6401 case MVE_VCMP_VEC_T4:
6402 case MVE_VCMP_VEC_T5:
6403 case MVE_VCMP_VEC_T6:
6404 if (arm_decode_field (given, 0, 3) == 0xd)
6405 {
6406 *unpredictable_code = UNPRED_R13;
6407 return TRUE;
6408 }
6409 else
6410 return FALSE;
c1e26897 6411
9743db03
AV		 6412 case MVE_VDUP:
6413 {
6414 unsigned long gpr = arm_decode_field (given, 12, 15);
6415 if (gpr == 0xd)
6416 {
6417 *unpredictable_code = UNPRED_R13;
6418 return TRUE;
6419 }
6420 else if (gpr == 0xf)
6421 {
6422 *unpredictable_code = UNPRED_R15;
6423 return TRUE;
6424 }
6425
6426 return FALSE;
6427 }
6428
14b456f2
AV		 6429 case MVE_VQADD_T2:
6430 case MVE_VQSUB_T2:
f49bb598
AV		 6431 case MVE_VMUL_FP_T2:
6432 case MVE_VMUL_VEC_T2:
56858bea 6433 case MVE_VMLA:
e523f101 6434 case MVE_VBRSR:
66dcaa5d
AV		 6435 case MVE_VADD_FP_T2:
6436 case MVE_VSUB_FP_T2:
6437 case MVE_VADD_VEC_T2:
6438 case MVE_VSUB_VEC_T2:
ed63aa17
AV		 6439 case MVE_VQRSHL_T2:
6440 case MVE_VQSHL_T1:
6441 case MVE_VRSHL_T2:
6442 case MVE_VSHL_T2:
6443 case MVE_VSHLC:
d3b63143
AV		 6444 case MVE_VQDMLAH:
6445 case MVE_VQRDMLAH:
6446 case MVE_VQDMLASH:
6447 case MVE_VQRDMLASH:
6448 case MVE_VQDMULH_T3:
6449 case MVE_VQRDMULH_T4:
6450 case MVE_VMLAS:
9743db03
AV		 6451 case MVE_VFMA_FP_SCALAR:
6452 case MVE_VFMAS_FP_SCALAR:
6453 case MVE_VHADD_T2:
6454 case MVE_VHSUB_T2:
6455 {
6456 unsigned long gpr = arm_decode_field (given, 0, 3);
6457 if (gpr == 0xd)
6458 {
6459 *unpredictable_code = UNPRED_R13;
6460 return TRUE;
6461 }
6462 else if (gpr == 0xf)
6463 {
6464 *unpredictable_code = UNPRED_R15;
6465 return TRUE;
6466 }
6467
6468 return FALSE;
6469 }
6470
04d54ace
AV		 6471 case MVE_VLD2:
6472 case MVE_VST2:
6473 {
6474 unsigned long rn = arm_decode_field (given, 16, 19);
6475
6476 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6477 {
6478 *unpredictable_code = UNPRED_R13_AND_WB;
6479 return TRUE;
6480 }
6481
6482 if (rn == 0xf)
6483 {
6484 *unpredictable_code = UNPRED_R15;
6485 return TRUE;
6486 }
6487
6488 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
6489 {
6490 *unpredictable_code = UNPRED_Q_GT_6;
6491 return TRUE;
6492 }
6493 else
6494 return FALSE;
6495 }
6496
6497 case MVE_VLD4:
6498 case MVE_VST4:
6499 {
6500 unsigned long rn = arm_decode_field (given, 16, 19);
6501
6502 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6503 {
6504 *unpredictable_code = UNPRED_R13_AND_WB;
6505 return TRUE;
6506 }
6507
6508 if (rn == 0xf)
6509 {
6510 *unpredictable_code = UNPRED_R15;
6511 return TRUE;
6512 }
6513
6514 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
6515 {
6516 *unpredictable_code = UNPRED_Q_GT_4;
6517 return TRUE;
6518 }
6519 else
6520 return FALSE;
6521 }
6522
aef6d006
AV		 6523 case MVE_VLDRB_T5:
6524 case MVE_VLDRH_T6:
6525 case MVE_VLDRW_T7:
6526 case MVE_VSTRB_T5:
6527 case MVE_VSTRH_T6:
6528 case MVE_VSTRW_T7:
6529 {
6530 unsigned long rn = arm_decode_field (given, 16, 19);
6531
6532 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6533 {
6534 *unpredictable_code = UNPRED_R13_AND_WB;
6535 return TRUE;
6536 }
6537 else if (rn == 0xf)
6538 {
6539 *unpredictable_code = UNPRED_R15;
6540 return TRUE;
6541 }
6542 else
6543 return FALSE;
6544 }
6545
ef1576a1
AV		 6546 case MVE_VLDRB_GATHER_T1:
6547 if (arm_decode_field (given, 0, 0) == 1)
6548 {
6549 *unpredictable_code = UNPRED_OS;
6550 return TRUE;
6551 }
6552
6553 /* fall through. */
6554 /* To handle common code with T2-T4 variants. */
6555 case MVE_VLDRH_GATHER_T2:
6556 case MVE_VLDRW_GATHER_T3:
6557 case MVE_VLDRD_GATHER_T4:
6558 {
6559 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6560 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6561
6562 if (qd == qm)
6563 {
6564 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6565 return TRUE;
6566 }
6567
6568 if (arm_decode_field (given, 16, 19) == 0xf)
6569 {
6570 *unpredictable_code = UNPRED_R15;
6571 return TRUE;
6572 }
6573
6574 return FALSE;
6575 }
6576
6577 case MVE_VLDRW_GATHER_T5:
6578 case MVE_VLDRD_GATHER_T6:
6579 {
6580 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6581 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
6582
6583 if (qd == qm)
6584 {
6585 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6586 return TRUE;
6587 }
6588 else
6589 return FALSE;
6590 }
6591
6592 case MVE_VSTRB_SCATTER_T1:
6593 if (arm_decode_field (given, 16, 19) == 0xf)
6594 {
6595 *unpredictable_code = UNPRED_R15;
6596 return TRUE;
6597 }
6598 else if (arm_decode_field (given, 0, 0) == 1)
6599 {
6600 *unpredictable_code = UNPRED_OS;
6601 return TRUE;
6602 }
6603 else
6604 return FALSE;
6605
6606 case MVE_VSTRH_SCATTER_T2:
6607 case MVE_VSTRW_SCATTER_T3:
6608 case MVE_VSTRD_SCATTER_T4:
6609 if (arm_decode_field (given, 16, 19) == 0xf)
6610 {
6611 *unpredictable_code = UNPRED_R15;
6612 return TRUE;
6613 }
6614 else
6615 return FALSE;
6616
c507f10b
AV		 6617 case MVE_VMOV2_VEC_LANE_TO_GP:
6618 case MVE_VMOV2_GP_TO_VEC_LANE:
bf0b396d
AV		 6619 case MVE_VCVT_BETWEEN_FP_INT:
6620 case MVE_VCVT_FROM_FP_TO_INT:
6621 {
6622 unsigned long rt = arm_decode_field (given, 0, 3);
6623 unsigned long rt2 = arm_decode_field (given, 16, 19);
6624
6625 if ((rt == 0xd) || (rt2 == 0xd))
6626 {
6627 *unpredictable_code = UNPRED_R13;
6628 return TRUE;
6629 }
6630 else if ((rt == 0xf) || (rt2 == 0xf))
6631 {
6632 *unpredictable_code = UNPRED_R15;
6633 return TRUE;
6634 }
6635 else if (rt == rt2)
6636 {
6637 *unpredictable_code = UNPRED_GP_REGS_EQUAL;
6638 return TRUE;
6639 }
6640
6641 return FALSE;
6642 }
6643
56858bea
AV		 6644 case MVE_VMAXV:
6645 case MVE_VMAXAV:
6646 case MVE_VMAXNMV_FP:
6647 case MVE_VMAXNMAV_FP:
6648 case MVE_VMINNMV_FP:
6649 case MVE_VMINNMAV_FP:
6650 case MVE_VMINV:
6651 case MVE_VMINAV:
66dcaa5d 6652 case MVE_VABAV:
c507f10b
AV		 6653 case MVE_VMOV_HFP_TO_GP:
6654 case MVE_VMOV_GP_TO_VEC_LANE:
6655 case MVE_VMOV_VEC_LANE_TO_GP:
6656 {
6657 unsigned long rda = arm_decode_field (given, 12, 15);
6658 if (rda == 0xd)
6659 {
6660 *unpredictable_code = UNPRED_R13;
6661 return TRUE;
6662 }
6663 else if (rda == 0xf)
6664 {
6665 *unpredictable_code = UNPRED_R15;
6666 return TRUE;
6667 }
6668
6669 return FALSE;
6670 }
6671
14925797
AV		 6672 case MVE_VMULL_INT:
6673 {
6674 unsigned long Qd;
6675 unsigned long Qm;
6676 unsigned long Qn;
6677
6678 if (arm_decode_field (given, 20, 21) == 2)
6679 {
6680 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6681 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6682 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6683
6684 if ((Qd == Qn) || (Qd == Qm))
6685 {
6686 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6687 return TRUE;
6688 }
6689 else
6690 return FALSE;
6691 }
6692 else
6693 return FALSE;
6694 }
6695
897b9bbc 6696 case MVE_VCMUL_FP:
14925797
AV		 6697 case MVE_VQDMULL_T1:
6698 {
6699 unsigned long Qd;
6700 unsigned long Qm;
6701 unsigned long Qn;
6702
6703 if (arm_decode_field (given, 28, 28) == 1)
6704 {
6705 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6706 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6707 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6708
6709 if ((Qd == Qn) || (Qd == Qm))
6710 {
6711 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6712 return TRUE;
6713 }
6714 else
6715 return FALSE;
6716 }
6717 else
6718 return FALSE;
6719 }
6720
6721 case MVE_VQDMULL_T2:
6722 {
6723 unsigned long gpr = arm_decode_field (given, 0, 3);
6724 if (gpr == 0xd)
6725 {
6726 *unpredictable_code = UNPRED_R13;
6727 return TRUE;
6728 }
6729 else if (gpr == 0xf)
6730 {
6731 *unpredictable_code = UNPRED_R15;
6732 return TRUE;
6733 }
6734
6735 if (arm_decode_field (given, 28, 28) == 1)
6736 {
6737 unsigned long Qd
6738 = arm_decode_field_multiple (given, 13, 15, 22, 22);
6739 unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6740
a9d96ab9 6741 if (Qd == Qn)
14925797
AV		 6742 {
6743 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6744 return TRUE;
6745 }
6746 else
6747 return FALSE;
6748 }
6749
6750 return FALSE;
6751 }
6752
d3b63143
AV		 6753 case MVE_VMLSLDAV:
6754 case MVE_VRMLSLDAVH:
6755 case MVE_VMLALDAV:
6756 case MVE_VADDLV:
6757 if (arm_decode_field (given, 20, 22) == 6)
6758 {
6759 *unpredictable_code = UNPRED_R13;
6760 return TRUE;
6761 }
6762 else
6763 return FALSE;
6764
1c8f2df8
AV		 6765 case MVE_VDWDUP:
6766 case MVE_VIWDUP:
6767 if (arm_decode_field (given, 1, 3) == 6)
6768 {
6769 *unpredictable_code = UNPRED_R13;
6770 return TRUE;
6771 }
6772 else
6773 return FALSE;
6774
897b9bbc
AV		 6775 case MVE_VCADD_VEC:
6776 case MVE_VHCADD:
6777 {
6778 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6779 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6780 if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
6781 {
6782 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6783 return TRUE;
6784 }
6785 else
6786 return FALSE;
6787 }
6788
6789 case MVE_VCADD_FP:
6790 {
6791 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6792 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6793 if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
6794 {
6795 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6796 return TRUE;
6797 }
6798 else
6799 return FALSE;
6800 }
6801
6802 case MVE_VCMLA_FP:
6803 {
6804 unsigned long Qda;
6805 unsigned long Qm;
6806 unsigned long Qn;
6807
6808 if (arm_decode_field (given, 20, 20) == 1)
6809 {
6810 Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
6811 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6812 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6813
6814 if ((Qda == Qn) || (Qda == Qm))
6815 {
6816 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6817 return TRUE;
6818 }
6819 else
6820 return FALSE;
6821 }
6822 else
6823 return FALSE;
6824
6825 }
6826
e523f101
AV		 6827 case MVE_VCTP:
6828 if (arm_decode_field (given, 16, 19) == 0xd)
6829 {
6830 *unpredictable_code = UNPRED_R13;
6831 return TRUE;
6832 }
6833 else
6834 return FALSE;
6835
14b456f2
AV		 6836 case MVE_VREV64:
6837 {
6838 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6839 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6);
6840
6841 if (qd == qm)
6842 {
6843 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6844 return TRUE;
6845 }
6846 else
6847 return FALSE;
6848 }
6849
23d00a41
SD		 6850 case MVE_LSLL:
6851 case MVE_LSLLI:
6852 case MVE_LSRL:
6853 case MVE_ASRL:
6854 case MVE_ASRLI:
6855 case MVE_UQSHLL:
6856 case MVE_UQRSHLL:
6857 case MVE_URSHRL:
6858 case MVE_SRSHRL:
6859 case MVE_SQSHLL:
6860 case MVE_SQRSHRL:
6861 {
6862 unsigned long gpr = arm_decode_field (given, 9, 11);
6863 gpr = ((gpr << 1) | 1);
6864 if (gpr == 0xd)
6865 {
6866 *unpredictable_code = UNPRED_R13;
6867 return TRUE;
6868 }
6869 else if (gpr == 0xf)
6870 {
6871 *unpredictable_code = UNPRED_R15;
6872 return TRUE;
6873 }
6874
6875 return FALSE;
6876 }
6877
143275ea
AV		 6878 default:
6879 return FALSE;
6880 }
6881}
c1e26897 6882
c507f10b
AV		 6883static void
6884print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
6885{
6886 unsigned long op1 = arm_decode_field (given, 21, 22);
6887 unsigned long op2 = arm_decode_field (given, 5, 6);
6888 unsigned long h = arm_decode_field (given, 16, 16);
43dd7626 6889 unsigned long index_operand, esize, targetBeat, idx;
c507f10b
AV		 6890 void *stream = info->stream;
6891 fprintf_ftype func = info->fprintf_func;
6892
6893 if ((op1 & 0x2) == 0x2)
6894 {
43dd7626 6895 index_operand = op2;
c507f10b
AV		 6896 esize = 8;
6897 }
6898 else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
6899 {
43dd7626 6900 index_operand = op2 >> 1;
c507f10b
AV		 6901 esize = 16;
6902 }
6903 else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
6904 {
43dd7626 6905 index_operand = 0;
c507f10b
AV		 6906 esize = 32;
6907 }
6908 else
6909 {
6910 func (stream, "<undefined index>");
6911 return;
6912 }
6913
6914 targetBeat = (op1 & 0x1) | (h << 1);
43dd7626 6915 idx = index_operand + targetBeat * (32/esize);
c507f10b
AV		 6916
6917 func (stream, "%lu", idx);
6918}
6919
6920/* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6921 in length and integer of floating-point type. */
6922static void
6923print_simd_imm8 (struct disassemble_info *info, unsigned long given,
6924 unsigned int ibit_loc, const struct mopcode32 *insn)
6925{
6926 int bits = 0;
6927 int cmode = (given >> 8) & 0xf;
6928 int op = (given >> 5) & 0x1;
6929 unsigned long value = 0, hival = 0;
6930 unsigned shift;
6931 int size = 0;
6932 int isfloat = 0;
6933 void *stream = info->stream;
6934 fprintf_ftype func = info->fprintf_func;
6935
6936 /* On Neon the 'i' bit is at bit 24, on mve it is
6937 at bit 28. */
6938 bits |= ((given >> ibit_loc) & 1) << 7;
6939 bits |= ((given >> 16) & 7) << 4;
6940 bits |= ((given >> 0) & 15) << 0;
6941
6942 if (cmode < 8)
6943 {
6944 shift = (cmode >> 1) & 3;
6945 value = (unsigned long) bits << (8 * shift);
6946 size = 32;
6947 }
6948 else if (cmode < 12)
6949 {
6950 shift = (cmode >> 1) & 1;
6951 value = (unsigned long) bits << (8 * shift);
6952 size = 16;
6953 }
6954 else if (cmode < 14)
6955 {
6956 shift = (cmode & 1) + 1;
6957 value = (unsigned long) bits << (8 * shift);
6958 value |= (1ul << (8 * shift)) - 1;
6959 size = 32;
6960 }
6961 else if (cmode == 14)
6962 {
6963 if (op)
6964 {
6965 /* Bit replication into bytes. */
6966 int ix;
6967 unsigned long mask;
6968
6969 value = 0;
6970 hival = 0;
6971 for (ix = 7; ix >= 0; ix--)
6972 {
6973 mask = ((bits >> ix) & 1) ? 0xff : 0;
6974 if (ix <= 3)
6975 value = (value << 8) | mask;
6976 else
6977 hival = (hival << 8) | mask;
6978 }
6979 size = 64;
6980 }
6981 else
6982 {
6983 /* Byte replication. */
6984 value = (unsigned long) bits;
6985 size = 8;
6986 }
6987 }
6988 else if (!op)
6989 {
6990 /* Floating point encoding. */
6991 int tmp;
6992
6993 value = (unsigned long) (bits & 0x7f) << 19;
6994 value |= (unsigned long) (bits & 0x80) << 24;
6995 tmp = bits & 0x40 ? 0x3c : 0x40;
6996 value |= (unsigned long) tmp << 24;
6997 size = 32;
6998 isfloat = 1;
6999 }
7000 else
7001 {
7002 func (stream, "<illegal constant %.8x:%x:%x>",
7003 bits, cmode, op);
7004 size = 32;
7005 return;
7006 }
7007
7008 // printU determines whether the immediate value should be printed as
7009 // unsigned.
7010 unsigned printU = 0;
7011 switch (insn->mve_op)
7012 {
7013 default:
7014 break;
7015 // We want this for instructions that don't have a 'signed' type
7016 case MVE_VBIC_IMM:
7017 case MVE_VORR_IMM:
7018 case MVE_VMVN_IMM:
7019 case MVE_VMOV_IMM_TO_VEC:
7020 printU = 1;
7021 break;
7022 }
7023 switch (size)
7024 {
7025 case 8:
7026 func (stream, "#%ld\t; 0x%.2lx", value, value);
7027 break;
7028
7029 case 16:
7030 func (stream,
7031 printU
7032 ? "#%lu\t; 0x%.4lx"
7033 : "#%ld\t; 0x%.4lx", value, value);
7034 break;
7035
7036 case 32:
7037 if (isfloat)
7038 {
7039 unsigned char valbytes[4];
7040 double fvalue;
7041
7042 /* Do this a byte at a time so we don't have to
7043 worry about the host's endianness. */
7044 valbytes[0] = value & 0xff;
7045 valbytes[1] = (value >> 8) & 0xff;
7046 valbytes[2] = (value >> 16) & 0xff;
7047 valbytes[3] = (value >> 24) & 0xff;
7048
7049 floatformat_to_double
7050 (& floatformat_ieee_single_little, valbytes,
7051 & fvalue);
7052
7053 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
7054 value);
7055 }
7056 else
7057 func (stream,
7058 printU
7059 ? "#%lu\t; 0x%.8lx"
7060 : "#%ld\t; 0x%.8lx",
7061 (long) (((value & 0x80000000L) != 0)
7062 && !printU
7063 ? value | ~0xffffffffL : value),
7064 value);
7065 break;
7066
7067 case 64:
7068 func (stream, "#0x%.8lx%.8lx", hival, value);
7069 break;
7070
7071 default:
7072 abort ();
7073 }
7074
7075}
7076
73cd51e5
AV		 7077static void
7078print_mve_undefined (struct disassemble_info *info,
7079 enum mve_undefined undefined_code)
7080{
7081 void *stream = info->stream;
7082 fprintf_ftype func = info->fprintf_func;
7083
7084 func (stream, "\t\tundefined instruction: ");
7085
7086 switch (undefined_code)
7087 {
ed63aa17
AV		 7088 case UNDEF_SIZE:
7089 func (stream, "illegal size");
7090 break;
7091
aef6d006
AV		 7092 case UNDEF_SIZE_0:
7093 func (stream, "size equals zero");
7094 break;
7095
c507f10b
AV		 7096 case UNDEF_SIZE_2:
7097 func (stream, "size equals two");
7098 break;
7099
9743db03
AV		 7100 case UNDEF_SIZE_3:
7101 func (stream, "size equals three");
7102 break;
7103
aef6d006
AV		 7104 case UNDEF_SIZE_LE_1:
7105 func (stream, "size <= 1");
7106 break;
7107
14b456f2
AV		 7108 case UNDEF_SIZE_NOT_0:
7109 func (stream, "size not equal to 0");
7110 break;
7111
ef1576a1
AV		 7112 case UNDEF_SIZE_NOT_2:
7113 func (stream, "size not equal to 2");
7114 break;
7115
7116 case UNDEF_SIZE_NOT_3:
7117 func (stream, "size not equal to 3");
7118 break;
7119
7120 case UNDEF_NOT_UNS_SIZE_0:
7121 func (stream, "not unsigned and size = zero");
7122 break;
7123
7124 case UNDEF_NOT_UNS_SIZE_1:
7125 func (stream, "not unsigned and size = one");
7126 break;
7127
7128 case UNDEF_NOT_UNSIGNED:
7129 func (stream, "not unsigned");
7130 break;
7131
bf0b396d
AV		 7132 case UNDEF_VCVT_IMM6:
7133 func (stream, "invalid imm6");
7134 break;
7135
7136 case UNDEF_VCVT_FSI_IMM6:
7137 func (stream, "fsi = 0 and invalid imm6");
7138 break;
7139
c507f10b
AV		 7140 case UNDEF_BAD_OP1_OP2:
7141 func (stream, "bad size with op2 = 2 and op1 = 0 or 1");
7142 break;
7143
7144 case UNDEF_BAD_U_OP1_OP2:
7145 func (stream, "unsigned with op2 = 0 and op1 = 0 or 1");
7146 break;
7147
7148 case UNDEF_OP_0_BAD_CMODE:
7149 func (stream, "op field equal 0 and bad cmode");
7150 break;
7151
d3b63143
AV		 7152 case UNDEF_XCHG_UNS:
7153 func (stream, "exchange and unsigned together");
7154 break;
7155
73cd51e5
AV		 7156 case UNDEF_NONE:
7157 break;
7158 }
7159
7160}
7161
7162static void
7163print_mve_unpredictable (struct disassemble_info *info,
7164 enum mve_unpredictable unpredict_code)
7165{
7166 void *stream = info->stream;
7167 fprintf_ftype func = info->fprintf_func;
7168
7169 func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
7170
7171 switch (unpredict_code)
7172 {
7173 case UNPRED_IT_BLOCK:
7174 func (stream, "mve instruction in it block");
7175 break;
7176
143275ea
AV		 7177 case UNPRED_FCA_0_FCB_1:
7178 func (stream, "condition bits, fca = 0 and fcb = 1");
7179 break;
7180
7181 case UNPRED_R13:
7182 func (stream, "use of r13 (sp)");
7183 break;
7184
9743db03
AV		 7185 case UNPRED_R15:
7186 func (stream, "use of r15 (pc)");
7187 break;
7188
04d54ace
AV		 7189 case UNPRED_Q_GT_4:
7190 func (stream, "start register block > r4");
7191 break;
7192
7193 case UNPRED_Q_GT_6:
7194 func (stream, "start register block > r6");
7195 break;
7196
7197 case UNPRED_R13_AND_WB:
7198 func (stream, "use of r13 and write back");
7199 break;
7200
ef1576a1
AV		 7201 case UNPRED_Q_REGS_EQUAL:
7202 func (stream,
7203 "same vector register used for destination and other operand");
7204 break;
7205
7206 case UNPRED_OS:
7207 func (stream, "use of offset scaled");
7208 break;
7209
bf0b396d
AV		 7210 case UNPRED_GP_REGS_EQUAL:
7211 func (stream, "same general-purpose register used for both operands");
7212 break;
7213
c507f10b
AV		 7214 case UNPRED_Q_REGS_EQ_AND_SIZE_1:
7215 func (stream, "use of identical q registers and size = 1");
7216 break;
7217
7218 case UNPRED_Q_REGS_EQ_AND_SIZE_2:
7219 func (stream, "use of identical q registers and size = 1");
7220 break;
7221
73cd51e5
AV		 7222 case UNPRED_NONE:
7223 break;
7224 }
7225}
7226
04d54ace
AV		 7227/* Print register block operand for mve vld2/vld4/vst2/vld4. */
7228
7229static void
7230print_mve_register_blocks (struct disassemble_info *info,
7231 unsigned long given,
7232 enum mve_instructions matched_insn)
7233{
7234 void *stream = info->stream;
7235 fprintf_ftype func = info->fprintf_func;
7236
7237 unsigned long q_reg_start = arm_decode_field_multiple (given,
7238 13, 15,
7239 22, 22);
7240 switch (matched_insn)
7241 {
7242 case MVE_VLD2:
7243 case MVE_VST2:
7244 if (q_reg_start <= 6)
7245 func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
7246 else
7247 func (stream, "<illegal reg q%ld>", q_reg_start);
7248 break;
7249
7250 case MVE_VLD4:
7251 case MVE_VST4:
7252 if (q_reg_start <= 4)
7253 func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
7254 q_reg_start + 1, q_reg_start + 2,
7255 q_reg_start + 3);
7256 else
7257 func (stream, "<illegal reg q%ld>", q_reg_start);
7258 break;
7259
7260 default:
7261 break;
7262 }
7263}
7264
bf0b396d
AV		 7265static void
7266print_mve_rounding_mode (struct disassemble_info *info,
7267 unsigned long given,
7268 enum mve_instructions matched_insn)
7269{
7270 void *stream = info->stream;
7271 fprintf_ftype func = info->fprintf_func;
7272
7273 switch (matched_insn)
7274 {
7275 case MVE_VCVT_FROM_FP_TO_INT:
7276 {
7277 switch (arm_decode_field (given, 8, 9))
7278 {
7279 case 0:
7280 func (stream, "a");
7281 break;
7282
7283 case 1:
7284 func (stream, "n");
7285 break;
7286
7287 case 2:
7288 func (stream, "p");
7289 break;
7290
7291 case 3:
7292 func (stream, "m");
7293 break;
7294
7295 default:
7296 break;
7297 }
7298 }
7299 break;
7300
7301 case MVE_VRINT_FP:
7302 {
7303 switch (arm_decode_field (given, 7, 9))
7304 {
7305 case 0:
7306 func (stream, "n");
7307 break;
7308
7309 case 1:
7310 func (stream, "x");
7311 break;
7312
7313 case 2:
7314 func (stream, "a");
7315 break;
7316
7317 case 3:
7318 func (stream, "z");
7319 break;
7320
7321 case 5:
7322 func (stream, "m");
7323 break;
7324
7325 case 7:
7326 func (stream, "p");
7327
7328 case 4:
7329 case 6:
7330 default:
7331 break;
7332 }
7333 }
7334 break;
7335
7336 default:
7337 break;
7338 }
7339}
7340
7341static void
7342print_mve_vcvt_size (struct disassemble_info *info,
7343 unsigned long given,
7344 enum mve_instructions matched_insn)
7345{
7346 unsigned long mode = 0;
7347 void *stream = info->stream;
7348 fprintf_ftype func = info->fprintf_func;
7349
7350 switch (matched_insn)
7351 {
7352 case MVE_VCVT_FP_FIX_VEC:
7353 {
7354 mode = (((given & 0x200) >> 7)
7355 | ((given & 0x10000000) >> 27)
7356 | ((given & 0x100) >> 8));
7357
7358 switch (mode)
7359 {
7360 case 0:
7361 func (stream, "f16.s16");
7362 break;
7363
7364 case 1:
7365 func (stream, "s16.f16");
7366 break;
7367
7368 case 2:
7369 func (stream, "f16.u16");
7370 break;
7371
7372 case 3:
7373 func (stream, "u16.f16");
7374 break;
7375
7376 case 4:
7377 func (stream, "f32.s32");
7378 break;
7379
7380 case 5:
7381 func (stream, "s32.f32");
7382 break;
7383
7384 case 6:
7385 func (stream, "f32.u32");
7386 break;
7387
7388 case 7:
7389 func (stream, "u32.f32");
7390 break;
7391
7392 default:
7393 break;
7394 }
7395 break;
7396 }
7397 case MVE_VCVT_BETWEEN_FP_INT:
7398 {
7399 unsigned long size = arm_decode_field (given, 18, 19);
7400 unsigned long op = arm_decode_field (given, 7, 8);
7401
7402 if (size == 1)
7403 {
7404 switch (op)
7405 {
7406 case 0:
7407 func (stream, "f16.s16");
7408 break;
7409
7410 case 1:
7411 func (stream, "f16.u16");
7412 break;
7413
7414 case 2:
7415 func (stream, "s16.f16");
7416 break;
7417
7418 case 3:
7419 func (stream, "u16.f16");
7420 break;
7421
7422 default:
7423 break;
7424 }
7425 }
7426 else if (size == 2)
7427 {
7428 switch (op)
7429 {
7430 case 0:
7431 func (stream, "f32.s32");
7432 break;
7433
7434 case 1:
7435 func (stream, "f32.u32");
7436 break;
7437
7438 case 2:
7439 func (stream, "s32.f32");
7440 break;
7441
7442 case 3:
7443 func (stream, "u32.f32");
7444 break;
7445 }
7446 }
7447 }
7448 break;
7449
7450 case MVE_VCVT_FP_HALF_FP:
7451 {
7452 unsigned long op = arm_decode_field (given, 28, 28);
7453 if (op == 0)
7454 func (stream, "f16.f32");
7455 else if (op == 1)
7456 func (stream, "f32.f16");
7457 }
7458 break;
7459
7460 case MVE_VCVT_FROM_FP_TO_INT:
7461 {
7462 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
7463
7464 switch (size)
7465 {
7466 case 2:
7467 func (stream, "s16.f16");
7468 break;
7469
7470 case 3:
7471 func (stream, "u16.f16");
7472 break;
7473
7474 case 4:
7475 func (stream, "s32.f32");
7476 break;
7477
7478 case 5:
7479 func (stream, "u32.f32");
7480 break;
7481
7482 default:
7483 break;
7484 }
7485 }
7486 break;
7487
7488 default:
7489 break;
7490 }
7491}
7492
897b9bbc
AV		 7493static void
7494print_mve_rotate (struct disassemble_info *info, unsigned long rot,
7495 unsigned long rot_width)
7496{
7497 void *stream = info->stream;
7498 fprintf_ftype func = info->fprintf_func;
7499
7500 if (rot_width == 1)
7501 {
7502 switch (rot)
7503 {
7504 case 0:
7505 func (stream, "90");
7506 break;
7507 case 1:
7508 func (stream, "270");
7509 break;
7510 default:
7511 break;
7512 }
7513 }
7514 else if (rot_width == 2)
7515 {
7516 switch (rot)
7517 {
7518 case 0:
7519 func (stream, "0");
7520 break;
7521 case 1:
7522 func (stream, "90");
7523 break;
7524 case 2:
7525 func (stream, "180");
7526 break;
7527 case 3:
7528 func (stream, "270");
7529 break;
7530 default:
7531 break;
7532 }
7533 }
7534}
7535
143275ea
AV		 7536static void
7537print_instruction_predicate (struct disassemble_info *info)
7538{
7539 void *stream = info->stream;
7540 fprintf_ftype func = info->fprintf_func;
7541
7542 if (vpt_block_state.next_pred_state == PRED_THEN)
7543 func (stream, "t");
7544 else if (vpt_block_state.next_pred_state == PRED_ELSE)
7545 func (stream, "e");
7546}
7547
7548static void
7549print_mve_size (struct disassemble_info *info,
7550 unsigned long size,
7551 enum mve_instructions matched_insn)
7552{
7553 void *stream = info->stream;
7554 fprintf_ftype func = info->fprintf_func;
7555
7556 switch (matched_insn)
7557 {
66dcaa5d
AV		 7558 case MVE_VABAV:
7559 case MVE_VABD_VEC:
7560 case MVE_VABS_FP:
7561 case MVE_VABS_VEC:
7562 case MVE_VADD_VEC_T1:
7563 case MVE_VADD_VEC_T2:
d3b63143 7564 case MVE_VADDV:
e523f101 7565 case MVE_VBRSR:
897b9bbc 7566 case MVE_VCADD_VEC:
e523f101
AV		 7567 case MVE_VCLS:
7568 case MVE_VCLZ:
143275ea
AV		 7569 case MVE_VCMP_VEC_T1:
7570 case MVE_VCMP_VEC_T2:
7571 case MVE_VCMP_VEC_T3:
7572 case MVE_VCMP_VEC_T4:
7573 case MVE_VCMP_VEC_T5:
7574 case MVE_VCMP_VEC_T6:
e523f101 7575 case MVE_VCTP:
1c8f2df8
AV		 7576 case MVE_VDDUP:
7577 case MVE_VDWDUP:
9743db03
AV		 7578 case MVE_VHADD_T1:
7579 case MVE_VHADD_T2:
897b9bbc 7580 case MVE_VHCADD:
9743db03
AV		 7581 case MVE_VHSUB_T1:
7582 case MVE_VHSUB_T2:
1c8f2df8
AV		 7583 case MVE_VIDUP:
7584 case MVE_VIWDUP:
04d54ace
AV		 7585 case MVE_VLD2:
7586 case MVE_VLD4:
ef1576a1
AV		 7587 case MVE_VLDRB_GATHER_T1:
7588 case MVE_VLDRH_GATHER_T2:
7589 case MVE_VLDRW_GATHER_T3:
7590 case MVE_VLDRD_GATHER_T4:
aef6d006
AV		 7591 case MVE_VLDRB_T1:
7592 case MVE_VLDRH_T2:
56858bea
AV		 7593 case MVE_VMAX:
7594 case MVE_VMAXA:
7595 case MVE_VMAXV:
7596 case MVE_VMAXAV:
7597 case MVE_VMIN:
7598 case MVE_VMINA:
7599 case MVE_VMINV:
7600 case MVE_VMINAV:
7601 case MVE_VMLA:
d3b63143 7602 case MVE_VMLAS:
f49bb598
AV		 7603 case MVE_VMUL_VEC_T1:
7604 case MVE_VMUL_VEC_T2:
7605 case MVE_VMULH:
7606 case MVE_VRMULH:
7607 case MVE_VMULL_INT:
7608 case MVE_VNEG_FP:
7609 case MVE_VNEG_VEC:
143275ea
AV		 7610 case MVE_VPT_VEC_T1:
7611 case MVE_VPT_VEC_T2:
7612 case MVE_VPT_VEC_T3:
7613 case MVE_VPT_VEC_T4:
7614 case MVE_VPT_VEC_T5:
7615 case MVE_VPT_VEC_T6:
14b456f2
AV		 7616 case MVE_VQABS:
7617 case MVE_VQADD_T1:
7618 case MVE_VQADD_T2:
d3b63143
AV		 7619 case MVE_VQDMLADH:
7620 case MVE_VQRDMLADH:
7621 case MVE_VQDMLAH:
7622 case MVE_VQRDMLAH:
7623 case MVE_VQDMLASH:
7624 case MVE_VQRDMLASH:
7625 case MVE_VQDMLSDH:
7626 case MVE_VQRDMLSDH:
7627 case MVE_VQDMULH_T1:
7628 case MVE_VQRDMULH_T2:
7629 case MVE_VQDMULH_T3:
7630 case MVE_VQRDMULH_T4:
14b456f2 7631 case MVE_VQNEG:
ed63aa17
AV		 7632 case MVE_VQRSHL_T1:
7633 case MVE_VQRSHL_T2:
7634 case MVE_VQSHL_T1:
7635 case MVE_VQSHL_T4:
14b456f2
AV		 7636 case MVE_VQSUB_T1:
7637 case MVE_VQSUB_T2:
7638 case MVE_VREV32:
7639 case MVE_VREV64:
9743db03 7640 case MVE_VRHADD:
bf0b396d 7641 case MVE_VRINT_FP:
ed63aa17
AV		 7642 case MVE_VRSHL_T1:
7643 case MVE_VRSHL_T2:
7644 case MVE_VSHL_T2:
7645 case MVE_VSHL_T3:
7646 case MVE_VSHLL_T2:
04d54ace
AV		 7647 case MVE_VST2:
7648 case MVE_VST4:
ef1576a1
AV		 7649 case MVE_VSTRB_SCATTER_T1:
7650 case MVE_VSTRH_SCATTER_T2:
7651 case MVE_VSTRW_SCATTER_T3:
aef6d006
AV		 7652 case MVE_VSTRB_T1:
7653 case MVE_VSTRH_T2:
66dcaa5d
AV		 7654 case MVE_VSUB_VEC_T1:
7655 case MVE_VSUB_VEC_T2:
143275ea
AV		 7656 if (size <= 3)
7657 func (stream, "%s", mve_vec_sizename[size]);
7658 else
7659 func (stream, "<undef size>");
7660 break;
7661
66dcaa5d
AV		 7662 case MVE_VABD_FP:
7663 case MVE_VADD_FP_T1:
7664 case MVE_VADD_FP_T2:
7665 case MVE_VSUB_FP_T1:
7666 case MVE_VSUB_FP_T2:
143275ea
AV		 7667 case MVE_VCMP_FP_T1:
7668 case MVE_VCMP_FP_T2:
9743db03
AV		 7669 case MVE_VFMA_FP_SCALAR:
7670 case MVE_VFMA_FP:
7671 case MVE_VFMS_FP:
7672 case MVE_VFMAS_FP_SCALAR:
56858bea
AV		 7673 case MVE_VMAXNM_FP:
7674 case MVE_VMAXNMA_FP:
7675 case MVE_VMAXNMV_FP:
7676 case MVE_VMAXNMAV_FP:
7677 case MVE_VMINNM_FP:
7678 case MVE_VMINNMA_FP:
7679 case MVE_VMINNMV_FP:
7680 case MVE_VMINNMAV_FP:
f49bb598
AV		 7681 case MVE_VMUL_FP_T1:
7682 case MVE_VMUL_FP_T2:
143275ea
AV		 7683 case MVE_VPT_FP_T1:
7684 case MVE_VPT_FP_T2:
7685 if (size == 0)
7686 func (stream, "32");
7687 else if (size == 1)
7688 func (stream, "16");
7689 break;
7690
897b9bbc
AV		 7691 case MVE_VCADD_FP:
7692 case MVE_VCMLA_FP:
7693 case MVE_VCMUL_FP:
d3b63143
AV		 7694 case MVE_VMLADAV_T1:
7695 case MVE_VMLALDAV:
7696 case MVE_VMLSDAV_T1:
7697 case MVE_VMLSLDAV:
14925797
AV		 7698 case MVE_VMOVN:
7699 case MVE_VQDMULL_T1:
7700 case MVE_VQDMULL_T2:
7701 case MVE_VQMOVN:
7702 case MVE_VQMOVUN:
7703 if (size == 0)
7704 func (stream, "16");
7705 else if (size == 1)
7706 func (stream, "32");
7707 break;
7708
7709 case MVE_VMOVL:
7710 if (size == 1)
7711 func (stream, "8");
7712 else if (size == 2)
7713 func (stream, "16");
7714 break;
7715
9743db03
AV		 7716 case MVE_VDUP:
7717 switch (size)
7718 {
7719 case 0:
7720 func (stream, "32");
7721 break;
7722 case 1:
7723 func (stream, "16");
7724 break;
7725 case 2:
7726 func (stream, "8");
7727 break;
7728 default:
7729 break;
7730 }
7731 break;
7732
c507f10b
AV		 7733 case MVE_VMOV_GP_TO_VEC_LANE:
7734 case MVE_VMOV_VEC_LANE_TO_GP:
7735 switch (size)
7736 {
7737 case 0: case 4:
7738 func (stream, "32");
7739 break;
7740
7741 case 1: case 3:
7742 case 5: case 7:
7743 func (stream, "16");
7744 break;
7745
7746 case 8: case 9: case 10: case 11:
7747 case 12: case 13: case 14: case 15:
7748 func (stream, "8");
7749 break;
7750
7751 default:
7752 break;
7753 }
7754 break;
7755
7756 case MVE_VMOV_IMM_TO_VEC:
7757 switch (size)
7758 {
7759 case 0: case 4: case 8:
7760 case 12: case 24: case 26:
7761 func (stream, "i32");
7762 break;
7763 case 16: case 20:
7764 func (stream, "i16");
7765 break;
7766 case 28:
7767 func (stream, "i8");
7768 break;
7769 case 29:
7770 func (stream, "i64");
7771 break;
7772 case 30:
7773 func (stream, "f32");
7774 break;
7775 default:
7776 break;
7777 }
7778 break;
7779
14925797
AV		 7780 case MVE_VMULL_POLY:
7781 if (size == 0)
7782 func (stream, "p8");
7783 else if (size == 1)
7784 func (stream, "p16");
7785 break;
7786
c507f10b
AV		 7787 case MVE_VMVN_IMM:
7788 switch (size)
7789 {
7790 case 0: case 2: case 4:
7791 case 6: case 12: case 13:
7792 func (stream, "32");
7793 break;
7794
7795 case 8: case 10:
7796 func (stream, "16");
7797 break;
7798
7799 default:
7800 break;
7801 }
7802 break;
7803
7804 case MVE_VBIC_IMM:
7805 case MVE_VORR_IMM:
7806 switch (size)
7807 {
7808 case 1: case 3:
7809 case 5: case 7:
7810 func (stream, "32");
7811 break;
7812
7813 case 9: case 11:
7814 func (stream, "16");
7815 break;
7816
7817 default:
7818 break;
7819 }
7820 break;
7821
ed63aa17
AV		 7822 case MVE_VQSHRN:
7823 case MVE_VQSHRUN:
7824 case MVE_VQRSHRN:
7825 case MVE_VQRSHRUN:
7826 case MVE_VRSHRN:
7827 case MVE_VSHRN:
7828 {
7829 switch (size)
7830 {
7831 case 1:
7832 func (stream, "16");
7833 break;
7834
7835 case 2: case 3:
7836 func (stream, "32");
7837 break;
7838
7839 default:
7840 break;
7841 }
7842 }
7843 break;
7844
7845 case MVE_VQSHL_T2:
7846 case MVE_VQSHLU_T3:
7847 case MVE_VRSHR:
7848 case MVE_VSHL_T1:
7849 case MVE_VSHLL_T1:
7850 case MVE_VSHR:
7851 case MVE_VSLI:
7852 case MVE_VSRI:
7853 {
7854 switch (size)
7855 {
7856 case 1:
7857 func (stream, "8");
7858 break;
7859
7860 case 2: case 3:
7861 func (stream, "16");
7862 break;
7863
7864 case 4: case 5: case 6: case 7:
7865 func (stream, "32");
7866 break;
7867
7868 default:
7869 break;
7870 }
7871 }
7872 break;
7873
143275ea
AV		 7874 default:
7875 break;
7876 }
7877}
7878
ed63aa17
AV		 7879static void
7880print_mve_shift_n (struct disassemble_info *info, long given,
7881 enum mve_instructions matched_insn)
7882{
7883 void *stream = info->stream;
7884 fprintf_ftype func = info->fprintf_func;
7885
7886 int startAt0
7887 = matched_insn == MVE_VQSHL_T2
7888 || matched_insn == MVE_VQSHLU_T3
7889 || matched_insn == MVE_VSHL_T1
7890 || matched_insn == MVE_VSHLL_T1
7891 || matched_insn == MVE_VSLI;
7892
7893 unsigned imm6 = (given & 0x3f0000) >> 16;
7894
7895 if (matched_insn == MVE_VSHLL_T1)
7896 imm6 &= 0x1f;
7897
7898 unsigned shiftAmount = 0;
7899 if ((imm6 & 0x20) != 0)
7900 shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
7901 else if ((imm6 & 0x10) != 0)
7902 shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
7903 else if ((imm6 & 0x08) != 0)
7904 shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
7905 else
7906 print_mve_undefined (info, UNDEF_SIZE_0);
7907
7908 func (stream, "%u", shiftAmount);
7909}
7910
143275ea
AV		 7911static void
7912print_vec_condition (struct disassemble_info *info, long given,
7913 enum mve_instructions matched_insn)
7914{
7915 void *stream = info->stream;
7916 fprintf_ftype func = info->fprintf_func;
7917 long vec_cond = 0;
7918
7919 switch (matched_insn)
7920 {
7921 case MVE_VPT_FP_T1:
7922 case MVE_VCMP_FP_T1:
7923 vec_cond = (((given & 0x1000) >> 10)
7924 | ((given & 1) << 1)
7925 | ((given & 0x0080) >> 7));
7926 func (stream, "%s",vec_condnames[vec_cond]);
7927 break;
7928
7929 case MVE_VPT_FP_T2:
7930 case MVE_VCMP_FP_T2:
7931 vec_cond = (((given & 0x1000) >> 10)
7932 | ((given & 0x0020) >> 4)
7933 | ((given & 0x0080) >> 7));
7934 func (stream, "%s",vec_condnames[vec_cond]);
7935 break;
7936
7937 case MVE_VPT_VEC_T1:
7938 case MVE_VCMP_VEC_T1:
7939 vec_cond = (given & 0x0080) >> 7;
7940 func (stream, "%s",vec_condnames[vec_cond]);
7941 break;
7942
7943 case MVE_VPT_VEC_T2:
7944 case MVE_VCMP_VEC_T2:
7945 vec_cond = 2 | ((given & 0x0080) >> 7);
7946 func (stream, "%s",vec_condnames[vec_cond]);
7947 break;
7948
7949 case MVE_VPT_VEC_T3:
7950 case MVE_VCMP_VEC_T3:
7951 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
7952 func (stream, "%s",vec_condnames[vec_cond]);
7953 break;
7954
7955 case MVE_VPT_VEC_T4:
7956 case MVE_VCMP_VEC_T4:
7957 vec_cond = (given & 0x0080) >> 7;
7958 func (stream, "%s",vec_condnames[vec_cond]);
7959 break;
7960
7961 case MVE_VPT_VEC_T5:
7962 case MVE_VCMP_VEC_T5:
7963 vec_cond = 2 | ((given & 0x0080) >> 7);
7964 func (stream, "%s",vec_condnames[vec_cond]);
7965 break;
7966
7967 case MVE_VPT_VEC_T6:
7968 case MVE_VCMP_VEC_T6:
7969 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
7970 func (stream, "%s",vec_condnames[vec_cond]);
7971 break;
7972
7973 case MVE_NONE:
7974 case MVE_VPST:
7975 default:
7976 break;
7977 }
7978}
7979
7980#define W_BIT 21
7981#define I_BIT 22
7982#define U_BIT 23
7983#define P_BIT 24
7984
7985#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
7986#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
7987#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
7988#define PRE_BIT_SET (given & (1 << P_BIT))
7989
7990
8f06b2d8
PB		 7991/* Print one coprocessor instruction on INFO->STREAM.
7992 Return TRUE if the instuction matched, FALSE if this is not a
7993 recognised coprocessor instruction. */
7994
7995static bfd_boolean
33593eaf
MM		 7996print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
7997 bfd_vma pc,
7998 struct disassemble_info *info,
7999 long given,
8000 bfd_boolean thumb)
8f06b2d8 8001{
6b0dd094 8002 const struct sopcode32 *insn;
8f06b2d8
PB		 8003 void *stream = info->stream;
8004 fprintf_ftype func = info->fprintf_func;
8005 unsigned long mask;
2edcd244 8006 unsigned long value = 0;
c22aaad1 8007 int cond;
8afc7bea 8008 int cp_num;
823d2571
TG		 8009 struct arm_private_data *private_data = info->private_data;
8010 arm_feature_set allowed_arches = ARM_ARCH_NONE;
32c36c3c
AV		 8011 arm_feature_set arm_ext_v8_1m_main =
8012 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
823d2571 8013
5b616bef 8014 allowed_arches = private_data->features;
8f06b2d8 8015
33593eaf 8016 for (insn = opcodes; insn->assembler; insn++)
8f06b2d8 8017 {
ff4a8d2b
NC		 8018 unsigned long u_reg = 16;
8019 bfd_boolean is_unpredictable = FALSE;
05413229 8020 signed long value_in_comment = 0;
0313a2b8
NC		 8021 const char *c;
8022
823d2571 8023 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 8024 switch (insn->value)
8025 {
8026 case SENTINEL_IWMMXT_START:
8027 if (info->mach != bfd_mach_arm_XScale
8028 && info->mach != bfd_mach_arm_iWMMXt
8029 && info->mach != bfd_mach_arm_iWMMXt2)
8030 do
8031 insn++;
823d2571
TG		 8032 while ((! ARM_FEATURE_ZERO (insn->arch))
8033 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 8034 continue;
8035
8036 case SENTINEL_IWMMXT_END:
8037 continue;
8038
8039 case SENTINEL_GENERIC_START:
5b616bef 8040 allowed_arches = private_data->features;
05413229
NC		 8041 continue;
8042
8043 default:
8044 abort ();
8045 }
8f06b2d8
PB		 8046
8047 mask = insn->mask;
8048 value = insn->value;
8afc7bea
RL		 8049 cp_num = (given >> 8) & 0xf;
8050
8f06b2d8
PB		 8051 if (thumb)
8052 {
8053 /* The high 4 bits are 0xe for Arm conditional instructions, and
8054 0xe for arm unconditional instructions. The rest of the
8055 encoding is the same. */
8056 mask |= 0xf0000000;
8057 value |= 0xe0000000;
c22aaad1
PB		 8058 if (ifthen_state)
8059 cond = IFTHEN_COND;
8060 else
e2efe87d 8061 cond = COND_UNCOND;
8f06b2d8
PB		 8062 }
8063 else
8064 {
8065 /* Only match unconditional instuctions against unconditional
8066 patterns. */
8067 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 8068 {
8069 mask |= 0xf0000000;
e2efe87d 8070 cond = COND_UNCOND;
c22aaad1
PB		 8071 }
8072 else
8073 {
8074 cond = (given >> 28) & 0xf;
8075 if (cond == 0xe)
e2efe87d 8076 cond = COND_UNCOND;
c22aaad1 8077 }
8f06b2d8 8078 }
823d2571 8079
6b0dd094
AV		 8080 if ((insn->isa == T32 && !thumb)
8081 || (insn->isa == ARM && thumb))
8082 continue;
8083
0313a2b8
NC		 8084 if ((given & mask) != value)
8085 continue;
8f06b2d8 8086
823d2571 8087 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 8088 continue;
8089
8afc7bea
RL		 8090 if (insn->value == 0xfe000010 /* mcr2 */
8091 || insn->value == 0xfe100010 /* mrc2 */
8092 || insn->value == 0xfc100000 /* ldc2 */
8093 || insn->value == 0xfc000000) /* stc2 */
8094 {
b0c11777 8095 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 8096 is_unpredictable = TRUE;
f08d8ce3
AV		 8097
8098 /* Armv8.1-M Mainline FP & MVE instructions. */
8099 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8100 && !ARM_CPU_IS_ANY (allowed_arches)
8101 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8102 continue;
8103
8afc7bea
RL		 8104 }
8105 else if (insn->value == 0x0e000000 /* cdp */
8106 || insn->value == 0xfe000000 /* cdp2 */
8107 || insn->value == 0x0e000010 /* mcr */
8108 || insn->value == 0x0e100010 /* mrc */
8109 || insn->value == 0x0c100000 /* ldc */
8110 || insn->value == 0x0c000000) /* stc */
8111 {
8112 /* Floating-point instructions. */
b0c11777 8113 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 8114 continue;
32c36c3c
AV		 8115
8116 /* Armv8.1-M Mainline FP & MVE instructions. */
8117 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8118 && !ARM_CPU_IS_ANY (allowed_arches)
8119 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8120 continue;
8afc7bea 8121 }
aef6d006
AV		 8122 else if ((insn->value == 0xec100f80 /* vldr (system register) */
8123 || insn->value == 0xec000f80) /* vstr (system register) */
8124 && arm_decode_field (given, 24, 24) == 0
8125 && arm_decode_field (given, 21, 21) == 0)
8126 /* If the P and W bits are both 0 then these encodings match the MVE
8127 VLDR and VSTR instructions, these are in a different table, so we
8128 don't let it match here. */
8129 continue;
8130
0313a2b8
NC		 8131 for (c = insn->assembler; *c; c++)
8132 {
8133 if (*c == '%')
8f06b2d8 8134 {
32c36c3c
AV		 8135 const char mod = *++c;
8136 switch (mod)
8f06b2d8 8137 {
0313a2b8
NC		 8138 case '%':
8139 func (stream, "%%");
8140 break;
8141
8142 case 'A':
32c36c3c 8143 case 'K':
05413229 8144 {
79862e45 8145 int rn = (given >> 16) & 0xf;
b0c11777 8146 bfd_vma offset = given & 0xff;
0313a2b8 8147
32c36c3c
AV		 8148 if (mod == 'K')
8149 offset = given & 0x7f;
8150
05413229 8151 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 8152
79862e45
DJ		 8153 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
8154 {
8155 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 8156 if (cp_num == 9)
8157 /* vldr.16/vstr.16 will shift the address
8158 left by 1 bit only. */
8159 offset = offset * 2;
8160 else
8161 offset = offset * 4;
8162
79862e45
DJ		 8163 if (NEGATIVE_BIT_SET)
8164 offset = - offset;
8165 if (rn != 15)
8166 value_in_comment = offset;
8167 }
8168
c1e26897 8169 if (PRE_BIT_SET)
05413229
NC		 8170 {
8171 if (offset)
fe56b6ce 8172 func (stream, ", #%d]%s",
d908c8af 8173 (int) offset,
c1e26897 8174 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 8175 else if (NEGATIVE_BIT_SET)
8176 func (stream, ", #-0]");
05413229
NC		 8177 else
8178 func (stream, "]");
8179 }
8180 else
8181 {
0313a2b8 8182 func (stream, "]");
8f06b2d8 8183
c1e26897 8184 if (WRITEBACK_BIT_SET)
05413229
NC		 8185 {
8186 if (offset)
d908c8af 8187 func (stream, ", #%d", (int) offset);
26d97720
NS		 8188 else if (NEGATIVE_BIT_SET)
8189 func (stream, ", #-0");
05413229
NC		 8190 }
8191 else
fe56b6ce 8192 {
26d97720
NS		 8193 func (stream, ", {%s%d}",
8194 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 8195 (int) offset);
fe56b6ce
NC		 8196 value_in_comment = offset;
8197 }
05413229 8198 }
79862e45
DJ		 8199 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
8200 {
8201 func (stream, "\t; ");
6844b2c2
MGD		 8202 /* For unaligned PCs, apply off-by-alignment
8203 correction. */
43e65147 8204 info->print_address_func (offset + pc
6844b2c2
MGD		 8205 + info->bytes_per_chunk * 2
8206 - (pc & 3),
dffaa15c 8207 info);
79862e45 8208 }
05413229 8209 }
0313a2b8 8210 break;
8f06b2d8 8211
0313a2b8
NC		 8212 case 'B':
8213 {
8214 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
8215 int offset = (given >> 1) & 0x3f;
8216
8217 if (offset == 1)
8218 func (stream, "{d%d}", regno);
8219 else if (regno + offset > 32)
8220 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
8221 else
8222 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
8223 }
8224 break;
8f06b2d8 8225
efd6b359
AV		 8226 case 'C':
8227 {
8228 bfd_boolean single = ((given >> 8) & 1) == 0;
8229 char reg_prefix = single ? 's' : 'd';
8230 int Dreg = (given >> 22) & 0x1;
8231 int Vdreg = (given >> 12) & 0xf;
8232 int reg = single ? ((Vdreg << 1) | Dreg)
8233 : ((Dreg << 4) | Vdreg);
8234 int num = (given >> (single ? 0 : 1)) & 0x7f;
8235 int maxreg = single ? 31 : 15;
8236 int topreg = reg + num - 1;
8237
8238 if (!num)
8239 func (stream, "{VPR}");
8240 else if (num == 1)
8241 func (stream, "{%c%d, VPR}", reg_prefix, reg);
8242 else if (topreg > maxreg)
8243 func (stream, "{%c%d-<overflow reg d%d, VPR}",
8244 reg_prefix, reg, single ? topreg >> 1 : topreg);
8245 else
8246 func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
8247 reg_prefix, topreg);
8248 }
8249 break;
8250
e2efe87d
MGD		 8251 case 'u':
8252 if (cond != COND_UNCOND)
8253 is_unpredictable = TRUE;
8254
8255 /* Fall through. */
0313a2b8 8256 case 'c':
b0c11777
RL		 8257 if (cond != COND_UNCOND && cp_num == 9)
8258 is_unpredictable = TRUE;
8259
aab2c27d
MM		 8260 /* Fall through. */
8261 case 'b':
0313a2b8
NC		 8262 func (stream, "%s", arm_conditional[cond]);
8263 break;
8f06b2d8 8264
0313a2b8
NC		 8265 case 'I':
8266 /* Print a Cirrus/DSP shift immediate. */
8267 /* Immediates are 7bit signed ints with bits 0..3 in
8268 bits 0..3 of opcode and bits 4..6 in bits 5..7
8269 of opcode. */
8270 {
8271 int imm;
8f06b2d8 8272
0313a2b8 8273 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 8274
0313a2b8
NC		 8275 /* Is ``imm'' a negative number? */
8276 if (imm & 0x40)
24b4cf66 8277 imm -= 0x80;
8f06b2d8 8278
0313a2b8
NC		 8279 func (stream, "%d", imm);
8280 }
8281
8282 break;
8f06b2d8 8283
32c36c3c
AV		 8284 case 'J':
8285 {
73cd51e5
AV		 8286 unsigned long regno
8287 = arm_decode_field_multiple (given, 13, 15, 22, 22);
32c36c3c
AV		 8288
8289 switch (regno)
8290 {
8291 case 0x1:
8292 func (stream, "FPSCR");
8293 break;
8294 case 0x2:
8295 func (stream, "FPSCR_nzcvqc");
8296 break;
8297 case 0xc:
8298 func (stream, "VPR");
8299 break;
8300 case 0xd:
8301 func (stream, "P0");
8302 break;
8303 case 0xe:
8304 func (stream, "FPCXTNS");
8305 break;
8306 case 0xf:
8307 func (stream, "FPCXTS");
8308 break;
8309 default:
73cd51e5 8310 func (stream, "<invalid reg %lu>", regno);
32c36c3c
AV		 8311 break;
8312 }
8313 }
8314 break;
8315
0313a2b8
NC		 8316 case 'F':
8317 switch (given & 0x00408000)
8318 {
8319 case 0:
8320 func (stream, "4");
8321 break;
8322 case 0x8000:
8323 func (stream, "1");
8324 break;
8325 case 0x00400000:
8326 func (stream, "2");
8f06b2d8 8327 break;
0313a2b8
NC		 8328 default:
8329 func (stream, "3");
8330 }
8331 break;
8f06b2d8 8332
0313a2b8
NC		 8333 case 'P':
8334 switch (given & 0x00080080)
8335 {
8336 case 0:
8337 func (stream, "s");
8338 break;
8339 case 0x80:
8340 func (stream, "d");
8341 break;
8342 case 0x00080000:
8343 func (stream, "e");
8344 break;
8345 default:
8346 func (stream, _("<illegal precision>"));
8f06b2d8 8347 break;
0313a2b8
NC		 8348 }
8349 break;
8f06b2d8 8350
0313a2b8
NC		 8351 case 'Q':
8352 switch (given & 0x00408000)
8353 {
8354 case 0:
8355 func (stream, "s");
8f06b2d8 8356 break;
0313a2b8
NC		 8357 case 0x8000:
8358 func (stream, "d");
8f06b2d8 8359 break;
0313a2b8
NC		 8360 case 0x00400000:
8361 func (stream, "e");
8362 break;
8363 default:
8364 func (stream, "p");
8f06b2d8 8365 break;
0313a2b8
NC		 8366 }
8367 break;
8f06b2d8 8368
0313a2b8
NC		 8369 case 'R':
8370 switch (given & 0x60)
8371 {
8372 case 0:
8373 break;
8374 case 0x20:
8375 func (stream, "p");
8376 break;
8377 case 0x40:
8378 func (stream, "m");
8379 break;
8380 default:
8381 func (stream, "z");
8382 break;
8383 }
8384 break;
16980d0b 8385
0313a2b8
NC		 8386 case '0': case '1': case '2': case '3': case '4':
8387 case '5': case '6': case '7': case '8': case '9':
8388 {
8389 int width;
8f06b2d8 8390
0313a2b8 8391 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 8392
0313a2b8
NC		 8393 switch (*c)
8394 {
ff4a8d2b
NC		 8395 case 'R':
8396 if (value == 15)
8397 is_unpredictable = TRUE;
8398 /* Fall through. */
0313a2b8 8399 case 'r':
ff4a8d2b
NC		 8400 if (c[1] == 'u')
8401 {
8402 /* Eat the 'u' character. */
8403 ++ c;
8404
8405 if (u_reg == value)
8406 is_unpredictable = TRUE;
8407 u_reg = value;
8408 }
0313a2b8
NC		 8409 func (stream, "%s", arm_regnames[value]);
8410 break;
c28eeff2
SN		 8411 case 'V':
8412 if (given & (1 << 6))
8413 goto Q;
8414 /* FALLTHROUGH */
0313a2b8
NC		 8415 case 'D':
8416 func (stream, "d%ld", value);
8417 break;
8418 case 'Q':
c28eeff2 8419 Q:
0313a2b8
NC		 8420 if (value & 1)
8421 func (stream, "<illegal reg q%ld.5>", value >> 1);
8422 else
8423 func (stream, "q%ld", value >> 1);
8424 break;
8425 case 'd':
8426 func (stream, "%ld", value);
05413229 8427 value_in_comment = value;
0313a2b8 8428 break;
6f1c2142
AM		 8429 case 'E':
8430 {
8431 /* Converts immediate 8 bit back to float value. */
8432 unsigned floatVal = (value & 0x80) << 24
8433 | (value & 0x3F) << 19
8434 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
8435
8436 /* Quarter float have a maximum value of 31.0.
8437 Get floating point value multiplied by 1e7.
8438 The maximum value stays in limit of a 32-bit int. */
8439 unsigned decVal =
8440 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
8441 (16 + (value & 0xF));
8442
8443 if (!(decVal % 1000000))
8444 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
8445 floatVal, value & 0x80 ? '-' : ' ',
8446 decVal / 10000000,
8447 decVal % 10000000 / 1000000);
8448 else if (!(decVal % 10000))
8449 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
8450 floatVal, value & 0x80 ? '-' : ' ',
8451 decVal / 10000000,
8452 decVal % 10000000 / 10000);
8453 else
8454 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
8455 floatVal, value & 0x80 ? '-' : ' ',
8456 decVal / 10000000, decVal % 10000000);
8457 break;
8458 }
0313a2b8
NC		 8459 case 'k':
8460 {
8461 int from = (given & (1 << 7)) ? 32 : 16;
8462 func (stream, "%ld", from - value);
8463 }
8464 break;
8f06b2d8 8465
0313a2b8
NC		 8466 case 'f':
8467 if (value > 7)
8468 func (stream, "#%s", arm_fp_const[value & 7]);
8469 else
8470 func (stream, "f%ld", value);
8471 break;
4146fd53 8472
0313a2b8
NC		 8473 case 'w':
8474 if (width == 2)
8475 func (stream, "%s", iwmmxt_wwnames[value]);
8476 else
8477 func (stream, "%s", iwmmxt_wwssnames[value]);
8478 break;
4146fd53 8479
0313a2b8
NC		 8480 case 'g':
8481 func (stream, "%s", iwmmxt_regnames[value]);
8482 break;
8483 case 'G':
8484 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 8485 break;
8f06b2d8 8486
0313a2b8 8487 case 'x':
d1aaab3c 8488 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 8489 break;
8f06b2d8 8490
33399f07
MGD		 8491 case 'c':
8492 switch (value)
8493 {
8494 case 0:
8495 func (stream, "eq");
8496 break;
8497
8498 case 1:
8499 func (stream, "vs");
8500 break;
8501
8502 case 2:
8503 func (stream, "ge");
8504 break;
8505
8506 case 3:
8507 func (stream, "gt");
8508 break;
8509
8510 default:
8511 func (stream, "??");
8512 break;
8513 }
8514 break;
8515
0313a2b8
NC		 8516 case '`':
8517 c++;
8518 if (value == 0)
8519 func (stream, "%c", *c);
8520 break;
8521 case '\'':
8522 c++;
8523 if (value == ((1ul << width) - 1))
8524 func (stream, "%c", *c);
8525 break;
8526 case '?':
fe56b6ce 8527 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 8528 c += 1 << width;
8529 break;
8530 default:
8531 abort ();
8532 }
dffaa15c
AM		 8533 }
8534 break;
0313a2b8 8535
dffaa15c
AM		 8536 case 'y':
8537 case 'z':
8538 {
8539 int single = *c++ == 'y';
8540 int regno;
8f06b2d8 8541
dffaa15c
AM		 8542 switch (*c)
8543 {
8544 case '4': /* Sm pair */
8545 case '0': /* Sm, Dm */
8546 regno = given & 0x0000000f;
8547 if (single)
8548 {
8549 regno <<= 1;
8550 regno += (given >> 5) & 1;
8551 }
8552 else
8553 regno += ((given >> 5) & 1) << 4;
8554 break;
8f06b2d8 8555
dffaa15c
AM		 8556 case '1': /* Sd, Dd */
8557 regno = (given >> 12) & 0x0000000f;
8558 if (single)
8559 {
8560 regno <<= 1;
8561 regno += (given >> 22) & 1;
8562 }
8563 else
8564 regno += ((given >> 22) & 1) << 4;
8565 break;
7df76b80 8566
dffaa15c
AM		 8567 case '2': /* Sn, Dn */
8568 regno = (given >> 16) & 0x0000000f;
8569 if (single)
8570 {
8571 regno <<= 1;
8572 regno += (given >> 7) & 1;
8573 }
8574 else
8575 regno += ((given >> 7) & 1) << 4;
8576 break;
a7f8487e 8577
dffaa15c
AM		 8578 case '3': /* List */
8579 func (stream, "{");
8580 regno = (given >> 12) & 0x0000000f;
8581 if (single)
8582 {
8583 regno <<= 1;
8584 regno += (given >> 22) & 1;
8585 }
8586 else
8587 regno += ((given >> 22) & 1) << 4;
8588 break;
a7f8487e 8589
dffaa15c
AM		 8590 default:
8591 abort ();
8592 }
0313a2b8 8593
dffaa15c 8594 func (stream, "%c%d", single ? 's' : 'd', regno);
a7f8487e 8595
dffaa15c
AM		 8596 if (*c == '3')
8597 {
8598 int count = given & 0xff;
b34976b6 8599
dffaa15c
AM		 8600 if (single == 0)
8601 count >>= 1;
0313a2b8 8602
dffaa15c
AM		 8603 if (--count)
8604 {
8605 func (stream, "-%c%d",
8606 single ? 's' : 'd',
8607 regno + count);
8608 }
0313a2b8 8609
dffaa15c 8610 func (stream, "}");
0313a2b8 8611 }
dffaa15c
AM		 8612 else if (*c == '4')
8613 func (stream, ", %c%d", single ? 's' : 'd',
8614 regno + 1);
8615 }
8616 break;
b34976b6 8617
dffaa15c
AM		 8618 case 'L':
8619 switch (given & 0x00400100)
0313a2b8 8620 {
dffaa15c
AM		 8621 case 0x00000000: func (stream, "b"); break;
8622 case 0x00400000: func (stream, "h"); break;
8623 case 0x00000100: func (stream, "w"); break;
8624 case 0x00400100: func (stream, "d"); break;
8625 default:
8626 break;
0313a2b8 8627 }
dffaa15c 8628 break;
2d447fca 8629
dffaa15c
AM		 8630 case 'Z':
8631 {
8632 /* given (20, 23) | given (0, 3) */
8633 value = ((given >> 16) & 0xf0) | (given & 0xf);
8634 func (stream, "%d", (int) value);
8635 }
8636 break;
0313a2b8 8637
dffaa15c
AM		 8638 case 'l':
8639 /* This is like the 'A' operator, except that if
8640 the width field "M" is zero, then the offset is
8641 *not* multiplied by four. */
8642 {
8643 int offset = given & 0xff;
8644 int multiplier = (given & 0x00000100) ? 4 : 1;
0313a2b8 8645
dffaa15c 8646 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
05413229 8647
dffaa15c
AM		 8648 if (multiplier > 1)
8649 {
8650 value_in_comment = offset * multiplier;
8651 if (NEGATIVE_BIT_SET)
8652 value_in_comment = - value_in_comment;
8653 }
0313a2b8 8654
dffaa15c
AM		 8655 if (offset)
8656 {
8657 if (PRE_BIT_SET)
8658 func (stream, ", #%s%d]%s",
8659 NEGATIVE_BIT_SET ? "-" : "",
8660 offset * multiplier,
8661 WRITEBACK_BIT_SET ? "!" : "");
8662 else
8663 func (stream, "], #%s%d",
8664 NEGATIVE_BIT_SET ? "-" : "",
8665 offset * multiplier);
8666 }
8667 else
8668 func (stream, "]");
8669 }
8670 break;
2d447fca 8671
dffaa15c
AM		 8672 case 'r':
8673 {
8674 int imm4 = (given >> 4) & 0xf;
8675 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
8676 int ubit = ! NEGATIVE_BIT_SET;
8677 const char *rm = arm_regnames [given & 0xf];
8678 const char *rn = arm_regnames [(given >> 16) & 0xf];
0313a2b8 8679
dffaa15c
AM		 8680 switch (puw_bits)
8681 {
8682 case 1:
8683 case 3:
8684 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
8685 if (imm4)
8686 func (stream, ", lsl #%d", imm4);
8687 break;
0313a2b8 8688
dffaa15c
AM		 8689 case 4:
8690 case 5:
8691 case 6:
8692 case 7:
8693 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
8694 if (imm4 > 0)
8695 func (stream, ", lsl #%d", imm4);
8696 func (stream, "]");
8697 if (puw_bits == 5 || puw_bits == 7)
8698 func (stream, "!");
8699 break;
2d447fca 8700
dffaa15c
AM		 8701 default:
8702 func (stream, "INVALID");
8703 }
8704 }
8705 break;
0313a2b8 8706
dffaa15c
AM		 8707 case 'i':
8708 {
8709 long imm5;
8710 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
8711 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
0313a2b8 8712 }
dffaa15c
AM		 8713 break;
8714
8715 default:
8716 abort ();
252b5132 8717 }
252b5132 8718 }
0313a2b8
NC		 8719 else
8720 func (stream, "%c", *c);
252b5132 8721 }
05413229
NC		 8722
8723 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 8724 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 8725
ff4a8d2b
NC		 8726 if (is_unpredictable)
8727 func (stream, UNPREDICTABLE_INSTRUCTION);
8728
0313a2b8 8729 return TRUE;
252b5132 8730 }
8f06b2d8 8731 return FALSE;
252b5132
RH		 8732}
8733
33593eaf
MM		 8734static bfd_boolean
8735print_insn_coprocessor (bfd_vma pc,
8736 struct disassemble_info *info,
8737 long given,
8738 bfd_boolean thumb)
8739{
8740 return print_insn_coprocessor_1 (coprocessor_opcodes,
8741 pc, info, given, thumb);
8742}
8743
8744static bfd_boolean
8745print_insn_generic_coprocessor (bfd_vma pc,
8746 struct disassemble_info *info,
8747 long given,
8748 bfd_boolean thumb)
8749{
8750 return print_insn_coprocessor_1 (generic_coprocessor_opcodes,
8751 pc, info, given, thumb);
8752}
8753
05413229
NC		 8754/* Decodes and prints ARM addressing modes. Returns the offset
8755 used in the address, if any, if it is worthwhile printing the
8756 offset as a hexadecimal value in a comment at the end of the
8757 line of disassembly. */
8758
8759static signed long
62b3e311
PB		 8760print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
8761{
8762 void *stream = info->stream;
8763 fprintf_ftype func = info->fprintf_func;
f8b960bc 8764 bfd_vma offset = 0;
62b3e311
PB		 8765
8766 if (((given & 0x000f0000) == 0x000f0000)
8767 && ((given & 0x02000000) == 0))
8768 {
05413229 8769 offset = given & 0xfff;
62b3e311
PB		 8770
8771 func (stream, "[pc");
8772
c1e26897 8773 if (PRE_BIT_SET)
62b3e311 8774 {
26d97720
NS		 8775 /* Pre-indexed. Elide offset of positive zero when
8776 non-writeback. */
8777 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 8778 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 8779
8780 if (NEGATIVE_BIT_SET)
8781 offset = -offset;
62b3e311
PB		 8782
8783 offset += pc + 8;
8784
8785 /* Cope with the possibility of write-back
8786 being used. Probably a very dangerous thing
8787 for the programmer to do, but who are we to
8788 argue ? */
26d97720 8789 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 8790 }
c1e26897 8791 else /* Post indexed. */
62b3e311 8792 {
d908c8af 8793 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 8794
c1e26897 8795 /* Ie ignore the offset. */
62b3e311
PB		 8796 offset = pc + 8;
8797 }
8798
8799 func (stream, "\t; ");
8800 info->print_address_func (offset, info);
05413229 8801 offset = 0;
62b3e311
PB		 8802 }
8803 else
8804 {
8805 func (stream, "[%s",
8806 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 8807
8808 if (PRE_BIT_SET)
62b3e311
PB		 8809 {
8810 if ((given & 0x02000000) == 0)
8811 {
26d97720 8812 /* Elide offset of positive zero when non-writeback. */
05413229 8813 offset = given & 0xfff;
26d97720 8814 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 8815 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 8816 }
8817 else
8818 {
26d97720 8819 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 8820 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 8821 }
8822
8823 func (stream, "]%s",
c1e26897 8824 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 8825 }
8826 else
8827 {
8828 if ((given & 0x02000000) == 0)
8829 {
26d97720 8830 /* Always show offset. */
05413229 8831 offset = given & 0xfff;
26d97720 8832 func (stream, "], #%s%d",
d908c8af 8833 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 8834 }
8835 else
8836 {
8837 func (stream, "], %s",
c1e26897 8838 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 8839 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 8840 }
8841 }
84919466
MR		 8842 if (NEGATIVE_BIT_SET)
8843 offset = -offset;
62b3e311 8844 }
05413229
NC		 8845
8846 return (signed long) offset;
62b3e311
PB		 8847}
8848
4934a27c
MM		 8849
8850/* Print one cde instruction on INFO->STREAM.
8851 Return TRUE if the instuction matched, FALSE if this is not a
8852 recognised cde instruction. */
8853static bfd_boolean
8854print_insn_cde (struct disassemble_info *info, long given, bfd_boolean thumb)
8855{
8856 const struct cdeopcode32 *insn;
8857 void *stream = info->stream;
8858 fprintf_ftype func = info->fprintf_func;
8859
8860 if (thumb)
8861 {
8862 /* Manually extract the coprocessor code from a known point.
8863 This position is the same across all CDE instructions. */
8864 for (insn = cde_opcodes; insn->assembler; insn++)
8865 {
8866 uint16_t coproc = (given >> insn->coproc_shift) & insn->coproc_mask;
8867 uint16_t coproc_mask = 1 << coproc;
8868 if (! (coproc_mask & cde_coprocs))
8869 continue;
8870
8871 if ((given & insn->mask) == insn->value)
8872 {
8873 bfd_boolean is_unpredictable = FALSE;
8874 const char *c;
8875
8876 for (c = insn->assembler; *c; c++)
8877 {
8878 if (*c == '%')
8879 {
8880 switch (*++c)
8881 {
8882 case '%':
8883 func (stream, "%%");
8884 break;
8885
8886 case '0': case '1': case '2': case '3': case '4':
8887 case '5': case '6': case '7': case '8': case '9':
8888 {
8889 int width;
8890 unsigned long value;
8891
8892 c = arm_decode_bitfield (c, given, &value, &width);
8893
8894 switch (*c)
8895 {
8896 case 'S':
8897 if (value > 10)
8898 is_unpredictable = TRUE;
8899 /* Fall through. */
8900 case 'R':
8901 if (value == 13)
8902 is_unpredictable = TRUE;
8903 /* Fall through. */
8904 case 'r':
8905 func (stream, "%s", arm_regnames[value]);
8906 break;
8907
8908 case 'n':
8909 if (value == 15)
8910 func (stream, "%s", "APSR_nzcv");
8911 else
8912 func (stream, "%s", arm_regnames[value]);
8913 break;
8914
8915 case 'T':
8916 func (stream, "%s", arm_regnames[value + 1]);
8917 break;
8918
8919 case 'd':
8920 func (stream, "%ld", value);
8921 break;
8922
8923 default:
8924 abort ();
8925 }
8926 }
8927 break;
8928
8929 case 'p':
8930 {
8931 uint8_t proc_number = (given >> 8) & 0x7;
8932 func (stream, "p%u", proc_number);
8933 break;
8934 }
8935
8936 case 'a':
8937 {
8938 uint8_t a_offset = 28;
8939 if (given & (1 << a_offset))
8940 func (stream, "a");
8941 break;
8942 }
8943 default:
8944 abort ();
8945 }
8946 }
8947 else
8948 func (stream, "%c", *c);
8949 }
8950
8951 if (is_unpredictable)
8952 func (stream, UNPREDICTABLE_INSTRUCTION);
8953
8954 return TRUE;
8955 }
8956 }
8957 return FALSE;
8958 }
8959 else
8960 return FALSE;
8961}
8962
8963
16980d0b
JB		 8964/* Print one neon instruction on INFO->STREAM.
8965 Return TRUE if the instuction matched, FALSE if this is not a
8966 recognised neon instruction. */
8967
8968static bfd_boolean
8969print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
8970{
8971 const struct opcode32 *insn;
8972 void *stream = info->stream;
8973 fprintf_ftype func = info->fprintf_func;
8974
8975 if (thumb)
8976 {
8977 if ((given & 0xef000000) == 0xef000000)
8978 {
0313a2b8 8979 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 8980 unsigned long bit28 = given & (1 << 28);
8981
8982 given &= 0x00ffffff;
8983 if (bit28)
8984 given |= 0xf3000000;
8985 else
8986 given |= 0xf2000000;
8987 }
8988 else if ((given & 0xff000000) == 0xf9000000)
8989 given ^= 0xf9000000 ^ 0xf4000000;
aab2c27d
MM		 8990 /* BFloat16 neon instructions without special top byte handling. */
8991 else if ((given & 0xff000000) == 0xfe000000
8992 || (given & 0xff000000) == 0xfc000000)
8993 ;
9743db03
AV		 8994 /* vdup is also a valid neon instruction. */
8995 else if ((given & 0xff910f5f) != 0xee800b10)
16980d0b
JB		 8996 return FALSE;
8997 }
43e65147 8998
16980d0b
JB		 8999 for (insn = neon_opcodes; insn->assembler; insn++)
9000 {
9001 if ((given & insn->mask) == insn->value)
9002 {
05413229 9003 signed long value_in_comment = 0;
e2efe87d 9004 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 9005 const char *c;
9006
9007 for (c = insn->assembler; *c; c++)
9008 {
9009 if (*c == '%')
9010 {
9011 switch (*++c)
9012 {
9013 case '%':
9014 func (stream, "%%");
9015 break;
9016
e2efe87d
MGD		 9017 case 'u':
9018 if (thumb && ifthen_state)
9019 is_unpredictable = TRUE;
9020
9021 /* Fall through. */
c22aaad1
PB		 9022 case 'c':
9023 if (thumb && ifthen_state)
9024 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9025 break;
9026
16980d0b
JB		 9027 case 'A':
9028 {
43e65147 9029 static const unsigned char enc[16] =
16980d0b
JB		 9030 {
9031 0x4, 0x14, /* st4 0,1 */
9032 0x4, /* st1 2 */
9033 0x4, /* st2 3 */
9034 0x3, /* st3 4 */
9035 0x13, /* st3 5 */
9036 0x3, /* st1 6 */
9037 0x1, /* st1 7 */
9038 0x2, /* st2 8 */
9039 0x12, /* st2 9 */
9040 0x2, /* st1 10 */
9041 0, 0, 0, 0, 0
9042 };
9043 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9044 int rn = ((given >> 16) & 0xf);
9045 int rm = ((given >> 0) & 0xf);
9046 int align = ((given >> 4) & 0x3);
9047 int type = ((given >> 8) & 0xf);
9048 int n = enc[type] & 0xf;
9049 int stride = (enc[type] >> 4) + 1;
9050 int ix;
43e65147 9051
16980d0b
JB		 9052 func (stream, "{");
9053 if (stride > 1)
9054 for (ix = 0; ix != n; ix++)
9055 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
9056 else if (n == 1)
9057 func (stream, "d%d", rd);
9058 else
9059 func (stream, "d%d-d%d", rd, rd + n - 1);
9060 func (stream, "}, [%s", arm_regnames[rn]);
9061 if (align)
8e560766 9062 func (stream, " :%d", 32 << align);
16980d0b
JB		 9063 func (stream, "]");
9064 if (rm == 0xd)
9065 func (stream, "!");
9066 else if (rm != 0xf)
9067 func (stream, ", %s", arm_regnames[rm]);
9068 }
9069 break;
43e65147 9070
16980d0b
JB		 9071 case 'B':
9072 {
9073 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9074 int rn = ((given >> 16) & 0xf);
9075 int rm = ((given >> 0) & 0xf);
9076 int idx_align = ((given >> 4) & 0xf);
9077 int align = 0;
9078 int size = ((given >> 10) & 0x3);
9079 int idx = idx_align >> (size + 1);
9080 int length = ((given >> 8) & 3) + 1;
9081 int stride = 1;
9082 int i;
9083
9084 if (length > 1 && size > 0)
9085 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 9086
16980d0b
JB		 9087 switch (length)
9088 {
9089 case 1:
9090 {
9091 int amask = (1 << size) - 1;
9092 if ((idx_align & (1 << size)) != 0)
9093 return FALSE;
9094 if (size > 0)
9095 {
9096 if ((idx_align & amask) == amask)
9097 align = 8 << size;
9098 else if ((idx_align & amask) != 0)
9099 return FALSE;
9100 }
9101 }
9102 break;
43e65147 9103
16980d0b
JB		 9104 case 2:
9105 if (size == 2 && (idx_align & 2) != 0)
9106 return FALSE;
9107 align = (idx_align & 1) ? 16 << size : 0;
9108 break;
43e65147 9109
16980d0b
JB		 9110 case 3:
9111 if ((size == 2 && (idx_align & 3) != 0)
9112 || (idx_align & 1) != 0)
9113 return FALSE;
9114 break;
43e65147 9115
16980d0b
JB		 9116 case 4:
9117 if (size == 2)
9118 {
9119 if ((idx_align & 3) == 3)
9120 return FALSE;
9121 align = (idx_align & 3) * 64;
9122 }
9123 else
9124 align = (idx_align & 1) ? 32 << size : 0;
9125 break;
43e65147 9126
16980d0b
JB		 9127 default:
9128 abort ();
9129 }
43e65147 9130
16980d0b
JB		 9131 func (stream, "{");
9132 for (i = 0; i < length; i++)
9133 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
9134 rd + i * stride, idx);
9135 func (stream, "}, [%s", arm_regnames[rn]);
9136 if (align)
8e560766 9137 func (stream, " :%d", align);
16980d0b
JB		 9138 func (stream, "]");
9139 if (rm == 0xd)
9140 func (stream, "!");
9141 else if (rm != 0xf)
9142 func (stream, ", %s", arm_regnames[rm]);
9143 }
9144 break;
43e65147 9145
16980d0b
JB		 9146 case 'C':
9147 {
9148 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9149 int rn = ((given >> 16) & 0xf);
9150 int rm = ((given >> 0) & 0xf);
9151 int align = ((given >> 4) & 0x1);
9152 int size = ((given >> 6) & 0x3);
9153 int type = ((given >> 8) & 0x3);
9154 int n = type + 1;
9155 int stride = ((given >> 5) & 0x1);
9156 int ix;
43e65147 9157
16980d0b
JB		 9158 if (stride && (n == 1))
9159 n++;
9160 else
9161 stride++;
43e65147 9162
16980d0b
JB		 9163 func (stream, "{");
9164 if (stride > 1)
9165 for (ix = 0; ix != n; ix++)
9166 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
9167 else if (n == 1)
9168 func (stream, "d%d[]", rd);
9169 else
9170 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
9171 func (stream, "}, [%s", arm_regnames[rn]);
9172 if (align)
9173 {
91d6fa6a 9174 align = (8 * (type + 1)) << size;
16980d0b
JB		 9175 if (type == 3)
9176 align = (size > 1) ? align >> 1 : align;
9177 if (type == 2 || (type == 0 && !size))
8e560766 9178 func (stream, " :<bad align %d>", align);
16980d0b 9179 else
8e560766 9180 func (stream, " :%d", align);
16980d0b
JB		 9181 }
9182 func (stream, "]");
9183 if (rm == 0xd)
9184 func (stream, "!");
9185 else if (rm != 0xf)
9186 func (stream, ", %s", arm_regnames[rm]);
9187 }
9188 break;
43e65147 9189
16980d0b
JB		 9190 case 'D':
9191 {
9192 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
9193 int size = (given >> 20) & 3;
9194 int reg = raw_reg & ((4 << size) - 1);
9195 int ix = raw_reg >> size >> 2;
43e65147 9196
16980d0b
JB		 9197 func (stream, "d%d[%d]", reg, ix);
9198 }
9199 break;
43e65147 9200
16980d0b 9201 case 'E':
fe56b6ce 9202 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 9203 {
9204 int bits = 0;
9205 int cmode = (given >> 8) & 0xf;
9206 int op = (given >> 5) & 0x1;
9207 unsigned long value = 0, hival = 0;
9208 unsigned shift;
9209 int size = 0;
0dbde4cf 9210 int isfloat = 0;
43e65147 9211
16980d0b
JB		 9212 bits |= ((given >> 24) & 1) << 7;
9213 bits |= ((given >> 16) & 7) << 4;
9214 bits |= ((given >> 0) & 15) << 0;
43e65147 9215
16980d0b
JB		 9216 if (cmode < 8)
9217 {
9218 shift = (cmode >> 1) & 3;
fe56b6ce 9219 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 9220 size = 32;
9221 }
9222 else if (cmode < 12)
9223 {
9224 shift = (cmode >> 1) & 1;
fe56b6ce 9225 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 9226 size = 16;
9227 }
9228 else if (cmode < 14)
9229 {
9230 shift = (cmode & 1) + 1;
fe56b6ce 9231 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 9232 value |= (1ul << (8 * shift)) - 1;
9233 size = 32;
9234 }
9235 else if (cmode == 14)
9236 {
9237 if (op)
9238 {
fe56b6ce 9239 /* Bit replication into bytes. */
16980d0b
JB		 9240 int ix;
9241 unsigned long mask;
43e65147 9242
16980d0b
JB		 9243 value = 0;
9244 hival = 0;
9245 for (ix = 7; ix >= 0; ix--)
9246 {
9247 mask = ((bits >> ix) & 1) ? 0xff : 0;
9248 if (ix <= 3)
9249 value = (value << 8) | mask;
9250 else
9251 hival = (hival << 8) | mask;
9252 }
9253 size = 64;
9254 }
9255 else
9256 {
fe56b6ce
NC		 9257 /* Byte replication. */
9258 value = (unsigned long) bits;
16980d0b
JB		 9259 size = 8;
9260 }
9261 }
9262 else if (!op)
9263 {
fe56b6ce 9264 /* Floating point encoding. */
16980d0b 9265 int tmp;
43e65147 9266
fe56b6ce
NC		 9267 value = (unsigned long) (bits & 0x7f) << 19;
9268 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 9269 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 9270 value |= (unsigned long) tmp << 24;
16980d0b 9271 size = 32;
0dbde4cf 9272 isfloat = 1;
16980d0b
JB		 9273 }
9274 else
9275 {
9276 func (stream, "<illegal constant %.8x:%x:%x>",
9277 bits, cmode, op);
9278 size = 32;
9279 break;
9280 }
9281 switch (size)
9282 {
9283 case 8:
9284 func (stream, "#%ld\t; 0x%.2lx", value, value);
9285 break;
43e65147 9286
16980d0b
JB		 9287 case 16:
9288 func (stream, "#%ld\t; 0x%.4lx", value, value);
9289 break;
9290
9291 case 32:
0dbde4cf
JB		 9292 if (isfloat)
9293 {
9294 unsigned char valbytes[4];
9295 double fvalue;
43e65147 9296
0dbde4cf
JB		 9297 /* Do this a byte at a time so we don't have to
9298 worry about the host's endianness. */
9299 valbytes[0] = value & 0xff;
9300 valbytes[1] = (value >> 8) & 0xff;
9301 valbytes[2] = (value >> 16) & 0xff;
9302 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 9303
9304 floatformat_to_double
c1e26897
NC		 9305 (& floatformat_ieee_single_little, valbytes,
9306 & fvalue);
43e65147 9307
0dbde4cf
JB		 9308 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
9309 value);
9310 }
9311 else
4e9d3b81 9312 func (stream, "#%ld\t; 0x%.8lx",
43e65147 9313 (long) (((value & 0x80000000L) != 0)
9d82ec38 9314 ? value | ~0xffffffffL : value),
c1e26897 9315 value);
16980d0b
JB		 9316 break;
9317
9318 case 64:
9319 func (stream, "#0x%.8lx%.8lx", hival, value);
9320 break;
43e65147 9321
16980d0b
JB		 9322 default:
9323 abort ();
9324 }
9325 }
9326 break;
43e65147 9327
16980d0b
JB		 9328 case 'F':
9329 {
9330 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
9331 int num = (given >> 8) & 0x3;
43e65147 9332
16980d0b
JB		 9333 if (!num)
9334 func (stream, "{d%d}", regno);
9335 else if (num + regno >= 32)
9336 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
9337 else
9338 func (stream, "{d%d-d%d}", regno, regno + num);
9339 }
9340 break;
7e8e6784 9341
16980d0b
JB		 9342
9343 case '0': case '1': case '2': case '3': case '4':
9344 case '5': case '6': case '7': case '8': case '9':
9345 {
9346 int width;
9347 unsigned long value;
9348
9349 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 9350
16980d0b
JB		 9351 switch (*c)
9352 {
9353 case 'r':
9354 func (stream, "%s", arm_regnames[value]);
9355 break;
9356 case 'd':
9357 func (stream, "%ld", value);
05413229 9358 value_in_comment = value;
16980d0b
JB		 9359 break;
9360 case 'e':
9361 func (stream, "%ld", (1ul << width) - value);
9362 break;
43e65147 9363
16980d0b
JB		 9364 case 'S':
9365 case 'T':
9366 case 'U':
05413229 9367 /* Various width encodings. */
16980d0b
JB		 9368 {
9369 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
9370 int limit;
9371 unsigned low, high;
9372
9373 c++;
9374 if (*c >= '0' && *c <= '9')
9375 limit = *c - '0';
9376 else if (*c >= 'a' && *c <= 'f')
9377 limit = *c - 'a' + 10;
9378 else
9379 abort ();
9380 low = limit >> 2;
9381 high = limit & 3;
9382
9383 if (value < low || value > high)
9384 func (stream, "<illegal width %d>", base << value);
9385 else
9386 func (stream, "%d", base << value);
9387 }
9388 break;
9389 case 'R':
9390 if (given & (1 << 6))
9391 goto Q;
9392 /* FALLTHROUGH */
9393 case 'D':
9394 func (stream, "d%ld", value);
9395 break;
9396 case 'Q':
9397 Q:
9398 if (value & 1)
9399 func (stream, "<illegal reg q%ld.5>", value >> 1);
9400 else
9401 func (stream, "q%ld", value >> 1);
9402 break;
43e65147 9403
16980d0b
JB		 9404 case '`':
9405 c++;
9406 if (value == 0)
9407 func (stream, "%c", *c);
9408 break;
9409 case '\'':
9410 c++;
9411 if (value == ((1ul << width) - 1))
9412 func (stream, "%c", *c);
9413 break;
9414 case '?':
fe56b6ce 9415 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 9416 c += 1 << width;
9417 break;
9418 default:
9419 abort ();
9420 }
16980d0b 9421 }
dffaa15c
AM		 9422 break;
9423
9424 default:
9425 abort ();
16980d0b
JB		 9426 }
9427 }
9428 else
9429 func (stream, "%c", *c);
9430 }
05413229
NC		 9431
9432 if (value_in_comment > 32 || value_in_comment < -16)
9433 func (stream, "\t; 0x%lx", value_in_comment);
9434
e2efe87d
MGD		 9435 if (is_unpredictable)
9436 func (stream, UNPREDICTABLE_INSTRUCTION);
9437
16980d0b
JB		 9438 return TRUE;
9439 }
9440 }
9441 return FALSE;
9442}
9443
73cd51e5
AV		 9444/* Print one mve instruction on INFO->STREAM.
9445 Return TRUE if the instuction matched, FALSE if this is not a
9446 recognised mve instruction. */
9447
9448static bfd_boolean
9449print_insn_mve (struct disassemble_info *info, long given)
9450{
9451 const struct mopcode32 *insn;
9452 void *stream = info->stream;
9453 fprintf_ftype func = info->fprintf_func;
9454
9455 for (insn = mve_opcodes; insn->assembler; insn++)
9456 {
9457 if (((given & insn->mask) == insn->value)
9458 && !is_mve_encoding_conflict (given, insn->mve_op))
9459 {
9460 signed long value_in_comment = 0;
9461 bfd_boolean is_unpredictable = FALSE;
9462 bfd_boolean is_undefined = FALSE;
9463 const char *c;
9464 enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
9465 enum mve_undefined undefined_cond = UNDEF_NONE;
9466
9467 /* Most vector mve instruction are illegal in a it block.
9468 There are a few exceptions; check for them. */
9469 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
9470 {
9471 is_unpredictable = TRUE;
9472 unpredictable_cond = UNPRED_IT_BLOCK;
9473 }
9474 else if (is_mve_unpredictable (given, insn->mve_op,
9475 &unpredictable_cond))
9476 is_unpredictable = TRUE;
9477
9478 if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
9479 is_undefined = TRUE;
9480
c4a23bf8
SP		 9481 /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV,
9482 i.e "VMOV Qd, Qm". */
9483 if ((insn->mve_op == MVE_VORR_REG)
9484 && (arm_decode_field (given, 1, 3)
9485 == arm_decode_field (given, 17, 19)))
9486 continue;
9487
73cd51e5
AV		 9488 for (c = insn->assembler; *c; c++)
9489 {
9490 if (*c == '%')
9491 {
9492 switch (*++c)
9493 {
9494 case '%':
9495 func (stream, "%%");
9496 break;
9497
ef1576a1
AV		 9498 case 'a':
9499 /* Don't print anything for '+' as it is implied. */
9500 if (arm_decode_field (given, 23, 23) == 0)
9501 func (stream, "-");
9502 break;
9503
143275ea
AV		 9504 case 'c':
9505 if (ifthen_state)
9506 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9507 break;
9508
aef6d006
AV		 9509 case 'd':
9510 print_mve_vld_str_addr (info, given, insn->mve_op);
9511 break;
9512
143275ea
AV		 9513 case 'i':
9514 {
9515 long mve_mask = mve_extract_pred_mask (given);
9516 func (stream, "%s", mve_predicatenames[mve_mask]);
9517 }
9518 break;
9519
23d00a41
SD		 9520 case 'j':
9521 {
9522 unsigned int imm5 = 0;
9523 imm5 |= arm_decode_field (given, 6, 7);
9524 imm5 |= (arm_decode_field (given, 12, 14) << 2);
9525 func (stream, "#%u", (imm5 == 0) ? 32 : imm5);
9526 }
9527 break;
9528
08132bdd
SP		 9529 case 'k':
9530 func (stream, "#%u",
9531 (arm_decode_field (given, 7, 7) == 0) ? 64 : 48);
9532 break;
9533
143275ea
AV		 9534 case 'n':
9535 print_vec_condition (info, given, insn->mve_op);
9536 break;
9537
ef1576a1
AV		 9538 case 'o':
9539 if (arm_decode_field (given, 0, 0) == 1)
9540 {
9541 unsigned long size
9542 = arm_decode_field (given, 4, 4)
9543 | (arm_decode_field (given, 6, 6) << 1);
9544
9545 func (stream, ", uxtw #%lu", size);
9546 }
9547 break;
9548
bf0b396d
AV		 9549 case 'm':
9550 print_mve_rounding_mode (info, given, insn->mve_op);
9551 break;
9552
9553 case 's':
9554 print_mve_vcvt_size (info, given, insn->mve_op);
9555 break;
9556
aef6d006
AV		 9557 case 'u':
9558 {
c507f10b
AV		 9559 unsigned long op1 = arm_decode_field (given, 21, 22);
9560
9561 if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
9562 {
9563 /* Check for signed. */
9564 if (arm_decode_field (given, 23, 23) == 0)
9565 {
9566 /* We don't print 's' for S32. */
9567 if ((arm_decode_field (given, 5, 6) == 0)
9568 && ((op1 == 0) || (op1 == 1)))
9569 ;
9570 else
9571 func (stream, "s");
9572 }
9573 else
9574 func (stream, "u");
9575 }
aef6d006 9576 else
c507f10b
AV		 9577 {
9578 if (arm_decode_field (given, 28, 28) == 0)
9579 func (stream, "s");
9580 else
9581 func (stream, "u");
9582 }
aef6d006 9583 }
ef1576a1 9584 break;
aef6d006 9585
143275ea
AV		 9586 case 'v':
9587 print_instruction_predicate (info);
9588 break;
9589
04d54ace
AV		 9590 case 'w':
9591 if (arm_decode_field (given, 21, 21) == 1)
9592 func (stream, "!");
9593 break;
9594
9595 case 'B':
9596 print_mve_register_blocks (info, given, insn->mve_op);
9597 break;
9598
c507f10b
AV		 9599 case 'E':
9600 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
9601
9602 print_simd_imm8 (info, given, 28, insn);
9603 break;
9604
9605 case 'N':
9606 print_mve_vmov_index (info, given);
9607 break;
9608
14925797
AV		 9609 case 'T':
9610 if (arm_decode_field (given, 12, 12) == 0)
9611 func (stream, "b");
9612 else
9613 func (stream, "t");
9614 break;
9615
d3b63143
AV		 9616 case 'X':
9617 if (arm_decode_field (given, 12, 12) == 1)
9618 func (stream, "x");
9619 break;
9620
143275ea
AV		 9621 case '0': case '1': case '2': case '3': case '4':
9622 case '5': case '6': case '7': case '8': case '9':
9623 {
9624 int width;
9625 unsigned long value;
9626
9627 c = arm_decode_bitfield (c, given, &value, &width);
9628
9629 switch (*c)
9630 {
9631 case 'Z':
9632 if (value == 13)
9633 is_unpredictable = TRUE;
9634 else if (value == 15)
9635 func (stream, "zr");
9636 else
9637 func (stream, "%s", arm_regnames[value]);
9638 break;
23d00a41 9639
e39c1607
SD		 9640 case 'c':
9641 func (stream, "%s", arm_conditional[value]);
9642 break;
9643
9644 case 'C':
9645 value ^= 1;
9646 func (stream, "%s", arm_conditional[value]);
9647 break;
9648
23d00a41
SD		 9649 case 'S':
9650 if (value == 13 || value == 15)
9651 is_unpredictable = TRUE;
9652 else
9653 func (stream, "%s", arm_regnames[value]);
9654 break;
9655
143275ea
AV		 9656 case 's':
9657 print_mve_size (info,
9658 value,
9659 insn->mve_op);
9660 break;
66dcaa5d
AV		 9661 case 'I':
9662 if (value == 1)
9663 func (stream, "i");
9664 break;
d3b63143
AV		 9665 case 'A':
9666 if (value == 1)
9667 func (stream, "a");
9668 break;
1c8f2df8
AV		 9669 case 'h':
9670 {
9671 unsigned int odd_reg = (value << 1) | 1;
9672 func (stream, "%s", arm_regnames[odd_reg]);
9673 }
9674 break;
ef1576a1
AV		 9675 case 'i':
9676 {
9677 unsigned long imm
9678 = arm_decode_field (given, 0, 6);
9679 unsigned long mod_imm = imm;
9680
9681 switch (insn->mve_op)
9682 {
9683 case MVE_VLDRW_GATHER_T5:
9684 case MVE_VSTRW_SCATTER_T5:
9685 mod_imm = mod_imm << 2;
9686 break;
9687 case MVE_VSTRD_SCATTER_T6:
9688 case MVE_VLDRD_GATHER_T6:
9689 mod_imm = mod_imm << 3;
9690 break;
9691
9692 default:
9693 break;
9694 }
9695
9696 func (stream, "%lu", mod_imm);
9697 }
9698 break;
bf0b396d
AV		 9699 case 'k':
9700 func (stream, "%lu", 64 - value);
9701 break;
1c8f2df8
AV		 9702 case 'l':
9703 {
9704 unsigned int even_reg = value << 1;
9705 func (stream, "%s", arm_regnames[even_reg]);
9706 }
9707 break;
9708 case 'u':
9709 switch (value)
9710 {
9711 case 0:
9712 func (stream, "1");
9713 break;
9714 case 1:
9715 func (stream, "2");
9716 break;
9717 case 2:
9718 func (stream, "4");
9719 break;
9720 case 3:
9721 func (stream, "8");
9722 break;
9723 default:
9724 break;
9725 }
9726 break;
897b9bbc
AV		 9727 case 'o':
9728 print_mve_rotate (info, value, width);
9729 break;
9743db03
AV		 9730 case 'r':
9731 func (stream, "%s", arm_regnames[value]);
9732 break;
04d54ace 9733 case 'd':
ed63aa17
AV		 9734 if (insn->mve_op == MVE_VQSHL_T2
9735 || insn->mve_op == MVE_VQSHLU_T3
9736 || insn->mve_op == MVE_VRSHR
9737 || insn->mve_op == MVE_VRSHRN
9738 || insn->mve_op == MVE_VSHL_T1
9739 || insn->mve_op == MVE_VSHLL_T1
9740 || insn->mve_op == MVE_VSHR
9741 || insn->mve_op == MVE_VSHRN
9742 || insn->mve_op == MVE_VSLI
9743 || insn->mve_op == MVE_VSRI)
9744 print_mve_shift_n (info, given, insn->mve_op);
9745 else if (insn->mve_op == MVE_VSHLL_T2)
9746 {
9747 switch (value)
9748 {
9749 case 0x00:
9750 func (stream, "8");
9751 break;
9752 case 0x01:
9753 func (stream, "16");
9754 break;
9755 case 0x10:
9756 print_mve_undefined (info, UNDEF_SIZE_0);
9757 break;
9758 default:
9759 assert (0);
9760 break;
9761 }
9762 }
9763 else
9764 {
9765 if (insn->mve_op == MVE_VSHLC && value == 0)
9766 value = 32;
9767 func (stream, "%ld", value);
9768 value_in_comment = value;
9769 }
04d54ace 9770 break;
c507f10b
AV		 9771 case 'F':
9772 func (stream, "s%ld", value);
9773 break;
143275ea
AV		 9774 case 'Q':
9775 if (value & 0x8)
9776 func (stream, "<illegal reg q%ld.5>", value);
9777 else
9778 func (stream, "q%ld", value);
9779 break;
c507f10b
AV		 9780 case 'x':
9781 func (stream, "0x%08lx", value);
9782 break;
143275ea
AV		 9783 default:
9784 abort ();
9785 }
9786 break;
9787 default:
9788 abort ();
9789 }
73cd51e5
AV		 9790 }
9791 }
9792 else
9793 func (stream, "%c", *c);
9794 }
9795
9796 if (value_in_comment > 32 || value_in_comment < -16)
9797 func (stream, "\t; 0x%lx", value_in_comment);
9798
9799 if (is_unpredictable)
9800 print_mve_unpredictable (info, unpredictable_cond);
9801
9802 if (is_undefined)
9803 print_mve_undefined (info, undefined_cond);
9804
143275ea
AV		 9805 if ((vpt_block_state.in_vpt_block == FALSE)
9806 && !ifthen_state
9807 && (is_vpt_instruction (given) == TRUE))
9808 mark_inside_vpt_block (given);
9809 else if (vpt_block_state.in_vpt_block == TRUE)
9810 update_vpt_block_state ();
9811
73cd51e5
AV		 9812 return TRUE;
9813 }
9814 }
9815 return FALSE;
9816}
9817
9818
90ec0d68
MGD		 9819/* Return the name of a v7A special register. */
9820
43e65147 9821static const char *
90ec0d68
MGD		 9822banked_regname (unsigned reg)
9823{
9824 switch (reg)
9825 {
9826 case 15: return "CPSR";
43e65147 9827 case 32: return "R8_usr";
90ec0d68
MGD		 9828 case 33: return "R9_usr";
9829 case 34: return "R10_usr";
9830 case 35: return "R11_usr";
9831 case 36: return "R12_usr";
9832 case 37: return "SP_usr";
9833 case 38: return "LR_usr";
43e65147 9834 case 40: return "R8_fiq";
90ec0d68
MGD		 9835 case 41: return "R9_fiq";
9836 case 42: return "R10_fiq";
9837 case 43: return "R11_fiq";
9838 case 44: return "R12_fiq";
9839 case 45: return "SP_fiq";
9840 case 46: return "LR_fiq";
9841 case 48: return "LR_irq";
9842 case 49: return "SP_irq";
9843 case 50: return "LR_svc";
9844 case 51: return "SP_svc";
9845 case 52: return "LR_abt";
9846 case 53: return "SP_abt";
9847 case 54: return "LR_und";
9848 case 55: return "SP_und";
9849 case 60: return "LR_mon";
9850 case 61: return "SP_mon";
9851 case 62: return "ELR_hyp";
9852 case 63: return "SP_hyp";
9853 case 79: return "SPSR";
9854 case 110: return "SPSR_fiq";
9855 case 112: return "SPSR_irq";
9856 case 114: return "SPSR_svc";
9857 case 116: return "SPSR_abt";
9858 case 118: return "SPSR_und";
9859 case 124: return "SPSR_mon";
9860 case 126: return "SPSR_hyp";
9861 default: return NULL;
9862 }
9863}
9864
e797f7e0
MGD		 9865/* Return the name of the DMB/DSB option. */
9866static const char *
9867data_barrier_option (unsigned option)
9868{
9869 switch (option & 0xf)
9870 {
9871 case 0xf: return "sy";
9872 case 0xe: return "st";
9873 case 0xd: return "ld";
9874 case 0xb: return "ish";
9875 case 0xa: return "ishst";
9876 case 0x9: return "ishld";
9877 case 0x7: return "un";
9878 case 0x6: return "unst";
9879 case 0x5: return "nshld";
9880 case 0x3: return "osh";
9881 case 0x2: return "oshst";
9882 case 0x1: return "oshld";
9883 default: return NULL;
9884 }
9885}
9886
4a5329c6
ZW		 9887/* Print one ARM instruction from PC on INFO->STREAM. */
9888
9889static void
9890print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 9891{
6b5d3a4d 9892 const struct opcode32 *insn;
6a51a8a8 9893 void *stream = info->stream;
6b5d3a4d 9894 fprintf_ftype func = info->fprintf_func;
b0e28b39 9895 struct arm_private_data *private_data = info->private_data;
252b5132 9896
16980d0b
JB		 9897 if (print_insn_coprocessor (pc, info, given, FALSE))
9898 return;
9899
9900 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 9901 return;
9902
33593eaf
MM		 9903 if (print_insn_generic_coprocessor (pc, info, given, FALSE))
9904 return;
9905
252b5132
RH		 9906 for (insn = arm_opcodes; insn->assembler; insn++)
9907 {
0313a2b8
NC		 9908 if ((given & insn->mask) != insn->value)
9909 continue;
823d2571
TG		 9910
9911 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 9912 continue;
9913
9914 /* Special case: an instruction with all bits set in the condition field
9915 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
9916 or by the catchall at the end of the table. */
9917 if ((given & 0xF0000000) != 0xF0000000
9918 || (insn->mask & 0xF0000000) == 0xF0000000
9919 || (insn->mask == 0 && insn->value == 0))
252b5132 9920 {
ff4a8d2b
NC		 9921 unsigned long u_reg = 16;
9922 unsigned long U_reg = 16;
ab8e2090 9923 bfd_boolean is_unpredictable = FALSE;
05413229 9924 signed long value_in_comment = 0;
6b5d3a4d 9925 const char *c;
b34976b6 9926
252b5132
RH		 9927 for (c = insn->assembler; *c; c++)
9928 {
9929 if (*c == '%')
9930 {
c1e26897
NC		 9931 bfd_boolean allow_unpredictable = FALSE;
9932
252b5132
RH		 9933 switch (*++c)
9934 {
9935 case '%':
9936 func (stream, "%%");
9937 break;
9938
9939 case 'a':
05413229 9940 value_in_comment = print_arm_address (pc, info, given);
62b3e311 9941 break;
252b5132 9942
62b3e311
PB		 9943 case 'P':
9944 /* Set P address bit and use normal address
9945 printing routine. */
c1e26897 9946 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 9947 break;
9948
c1e26897
NC		 9949 case 'S':
9950 allow_unpredictable = TRUE;
1a0670f3 9951 /* Fall through. */
252b5132
RH		 9952 case 's':
9953 if ((given & 0x004f0000) == 0x004f0000)
9954 {
58efb6c0 9955 /* PC relative with immediate offset. */
f8b960bc 9956 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 9957
aefd8a40
NC		 9958 if (PRE_BIT_SET)
9959 {
26d97720
NS		 9960 /* Elide positive zero offset. */
9961 if (offset || NEGATIVE_BIT_SET)
9962 func (stream, "[pc, #%s%d]\t; ",
d908c8af 9963 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 9964 else
26d97720
NS		 9965 func (stream, "[pc]\t; ");
9966 if (NEGATIVE_BIT_SET)
9967 offset = -offset;
aefd8a40
NC		 9968 info->print_address_func (offset + pc + 8, info);
9969 }
9970 else
9971 {
26d97720
NS		 9972 /* Always show the offset. */
9973 func (stream, "[pc], #%s%d",
d908c8af 9974 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 9975 if (! allow_unpredictable)
9976 is_unpredictable = TRUE;
aefd8a40 9977 }
252b5132
RH		 9978 }
9979 else
9980 {
fe56b6ce
NC		 9981 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
9982
b34976b6 9983 func (stream, "[%s",
252b5132 9984 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 9985
c1e26897 9986 if (PRE_BIT_SET)
252b5132 9987 {
c1e26897 9988 if (IMMEDIATE_BIT_SET)
252b5132 9989 {
26d97720
NS		 9990 /* Elide offset for non-writeback
9991 positive zero. */
9992 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
9993 || offset)
9994 func (stream, ", #%s%d",
9995 NEGATIVE_BIT_SET ? "-" : "", offset);
9996
9997 if (NEGATIVE_BIT_SET)
9998 offset = -offset;
945ee430 9999
fe56b6ce 10000 value_in_comment = offset;
252b5132 10001 }
945ee430 10002 else
ff4a8d2b
NC		 10003 {
10004 /* Register Offset or Register Pre-Indexed. */
10005 func (stream, ", %s%s",
10006 NEGATIVE_BIT_SET ? "-" : "",
10007 arm_regnames[given & 0xf]);
10008
10009 /* Writing back to the register that is the source/
10010 destination of the load/store is unpredictable. */
10011 if (! allow_unpredictable
10012 && WRITEBACK_BIT_SET
10013 && ((given & 0xf) == ((given >> 12) & 0xf)))
10014 is_unpredictable = TRUE;
10015 }
252b5132 10016
b34976b6 10017 func (stream, "]%s",
c1e26897 10018 WRITEBACK_BIT_SET ? "!" : "");
252b5132 10019 }
945ee430 10020 else
252b5132 10021 {
c1e26897 10022 if (IMMEDIATE_BIT_SET)
252b5132 10023 {
945ee430 10024 /* Immediate Post-indexed. */
aefd8a40 10025 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 10026 func (stream, "], #%s%d",
10027 NEGATIVE_BIT_SET ? "-" : "", offset);
10028 if (NEGATIVE_BIT_SET)
10029 offset = -offset;
fe56b6ce 10030 value_in_comment = offset;
252b5132 10031 }
945ee430 10032 else
ff4a8d2b
NC		 10033 {
10034 /* Register Post-indexed. */
10035 func (stream, "], %s%s",
10036 NEGATIVE_BIT_SET ? "-" : "",
10037 arm_regnames[given & 0xf]);
10038
10039 /* Writing back to the register that is the source/
10040 destination of the load/store is unpredictable. */
10041 if (! allow_unpredictable
10042 && (given & 0xf) == ((given >> 12) & 0xf))
10043 is_unpredictable = TRUE;
10044 }
c1e26897 10045
07a28fab
NC		 10046 if (! allow_unpredictable)
10047 {
10048 /* Writeback is automatically implied by post- addressing.
10049 Setting the W bit is unnecessary and ARM specify it as
10050 being unpredictable. */
10051 if (WRITEBACK_BIT_SET
10052 /* Specifying the PC register as the post-indexed
10053 registers is also unpredictable. */
ab8e2090
NC		 10054 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
10055 is_unpredictable = TRUE;
07a28fab 10056 }
252b5132
RH		 10057 }
10058 }
10059 break;
b34976b6 10060
252b5132 10061 case 'b':
6b5d3a4d 10062 {
f8b960bc 10063 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
1d67fe3b
TT		 10064 bfd_vma target = disp * 4 + pc + 8;
10065 info->print_address_func (target, info);
10066
10067 /* Fill in instruction information. */
10068 info->insn_info_valid = 1;
10069 info->insn_type = dis_branch;
10070 info->target = target;
6b5d3a4d 10071 }
252b5132
RH		 10072 break;
10073
10074 case 'c':
c22aaad1
PB		 10075 if (((given >> 28) & 0xf) != 0xe)
10076 func (stream, "%s",
10077 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 10078 break;
10079
10080 case 'm':
10081 {
10082 int started = 0;
10083 int reg;
10084
10085 func (stream, "{");
10086 for (reg = 0; reg < 16; reg++)
10087 if ((given & (1 << reg)) != 0)
10088 {
10089 if (started)
10090 func (stream, ", ");
10091 started = 1;
10092 func (stream, "%s", arm_regnames[reg]);
10093 }
10094 func (stream, "}");
ab8e2090
NC		 10095 if (! started)
10096 is_unpredictable = TRUE;
252b5132
RH		 10097 }
10098 break;
10099
37b37b2d 10100 case 'q':
78c66db8 10101 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 10102 break;
10103
252b5132
RH		 10104 case 'o':
10105 if ((given & 0x02000000) != 0)
10106 {
a415b1cd
JB		 10107 unsigned int rotate = (given & 0xf00) >> 7;
10108 unsigned int immed = (given & 0xff);
10109 unsigned int a, i;
10110
ebd1c6d1
AM		 10111 a = (immed << ((32 - rotate) & 31)
10112 | immed >> rotate) & 0xffffffff;
a415b1cd
JB		 10113 /* If there is another encoding with smaller rotate,
10114 the rotate should be specified directly. */
10115 for (i = 0; i < 32; i += 2)
ebd1c6d1 10116 if ((a << i | a >> ((32 - i) & 31)) <= 0xff)
a415b1cd
JB		 10117 break;
10118
10119 if (i != rotate)
10120 func (stream, "#%d, %d", immed, rotate);
10121 else
10122 func (stream, "#%d", a);
10123 value_in_comment = a;
252b5132
RH		 10124 }
10125 else
78c66db8 10126 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 10127 break;
10128
10129 case 'p':
10130 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 10131 {
823d2571
TG		 10132 arm_feature_set arm_ext_v6 =
10133 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
10134
aefd8a40
NC		 10135 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
10136 mechanism for setting PSR flag bits. They are
10137 obsolete in V6 onwards. */
823d2571
TG		 10138 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
10139 arm_ext_v6))
aefd8a40 10140 func (stream, "p");
4ab90a7a
AV		 10141 else
10142 is_unpredictable = TRUE;
aefd8a40 10143 }
252b5132
RH		 10144 break;
10145
10146 case 't':
10147 if ((given & 0x01200000) == 0x00200000)
10148 func (stream, "t");
10149 break;
10150
252b5132 10151 case 'A':
05413229
NC		 10152 {
10153 int offset = given & 0xff;
f02232aa 10154
05413229 10155 value_in_comment = offset * 4;
c1e26897 10156 if (NEGATIVE_BIT_SET)
05413229 10157 value_in_comment = - value_in_comment;
f02232aa 10158
05413229 10159 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 10160
c1e26897 10161 if (PRE_BIT_SET)
05413229
NC		 10162 {
10163 if (offset)
fe56b6ce 10164 func (stream, ", #%d]%s",
d908c8af 10165 (int) value_in_comment,
c1e26897 10166 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 10167 else
10168 func (stream, "]");
10169 }
10170 else
10171 {
10172 func (stream, "]");
f02232aa 10173
c1e26897 10174 if (WRITEBACK_BIT_SET)
05413229
NC		 10175 {
10176 if (offset)
d908c8af 10177 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 10178 }
10179 else
fe56b6ce 10180 {
d908c8af 10181 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 10182 value_in_comment = offset;
10183 }
05413229
NC		 10184 }
10185 }
252b5132
RH		 10186 break;
10187
077b8428
NC		 10188 case 'B':
10189 /* Print ARM V5 BLX(1) address: pc+25 bits. */
10190 {
10191 bfd_vma address;
10192 bfd_vma offset = 0;
b34976b6 10193
c1e26897 10194 if (! NEGATIVE_BIT_SET)
077b8428
NC		 10195 /* Is signed, hi bits should be ones. */
10196 offset = (-1) ^ 0x00ffffff;
10197
10198 /* Offset is (SignExtend(offset field)<<2). */
10199 offset += given & 0x00ffffff;
10200 offset <<= 2;
10201 address = offset + pc + 8;
b34976b6 10202
8f06b2d8
PB		 10203 if (given & 0x01000000)
10204 /* H bit allows addressing to 2-byte boundaries. */
10205 address += 2;
b1ee46c5 10206
8f06b2d8 10207 info->print_address_func (address, info);
1d67fe3b
TT		 10208
10209 /* Fill in instruction information. */
10210 info->insn_info_valid = 1;
10211 info->insn_type = dis_branch;
10212 info->target = address;
b1ee46c5 10213 }
b1ee46c5
AH		 10214 break;
10215
252b5132 10216 case 'C':
90ec0d68
MGD		 10217 if ((given & 0x02000200) == 0x200)
10218 {
10219 const char * name;
10220 unsigned sysm = (given & 0x004f0000) >> 16;
10221
10222 sysm |= (given & 0x300) >> 4;
10223 name = banked_regname (sysm);
10224
10225 if (name != NULL)
10226 func (stream, "%s", name);
10227 else
d908c8af 10228 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 10229 }
10230 else
10231 {
43e65147 10232 func (stream, "%cPSR_",
90ec0d68
MGD		 10233 (given & 0x00400000) ? 'S' : 'C');
10234 if (given & 0x80000)
10235 func (stream, "f");
10236 if (given & 0x40000)
10237 func (stream, "s");
10238 if (given & 0x20000)
10239 func (stream, "x");
10240 if (given & 0x10000)
10241 func (stream, "c");
10242 }
252b5132
RH		 10243 break;
10244
62b3e311 10245 case 'U':
43e65147 10246 if ((given & 0xf0) == 0x60)
62b3e311 10247 {
52e7f43d
RE		 10248 switch (given & 0xf)
10249 {
10250 case 0xf: func (stream, "sy"); break;
10251 default:
10252 func (stream, "#%d", (int) given & 0xf);
10253 break;
10254 }
43e65147
L		 10255 }
10256 else
52e7f43d 10257 {
e797f7e0
MGD		 10258 const char * opt = data_barrier_option (given & 0xf);
10259 if (opt != NULL)
10260 func (stream, "%s", opt);
10261 else
52e7f43d 10262 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 10263 }
10264 break;
10265
b34976b6 10266 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 10267 case '5': case '6': case '7': case '8': case '9':
10268 {
16980d0b
JB		 10269 int width;
10270 unsigned long value;
252b5132 10271
16980d0b 10272 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 10273
252b5132
RH		 10274 switch (*c)
10275 {
ab8e2090
NC		 10276 case 'R':
10277 if (value == 15)
10278 is_unpredictable = TRUE;
10279 /* Fall through. */
16980d0b 10280 case 'r':
9eb6c0f1
MGD		 10281 case 'T':
10282 /* We want register + 1 when decoding T. */
10283 if (*c == 'T')
2bddb71a 10284 value = (value + 1) & 0xf;
9eb6c0f1 10285
ff4a8d2b
NC		 10286 if (c[1] == 'u')
10287 {
10288 /* Eat the 'u' character. */
10289 ++ c;
10290
10291 if (u_reg == value)
10292 is_unpredictable = TRUE;
10293 u_reg = value;
10294 }
10295 if (c[1] == 'U')
10296 {
10297 /* Eat the 'U' character. */
10298 ++ c;
10299
10300 if (U_reg == value)
10301 is_unpredictable = TRUE;
10302 U_reg = value;
10303 }
16980d0b
JB		 10304 func (stream, "%s", arm_regnames[value]);
10305 break;
10306 case 'd':
10307 func (stream, "%ld", value);
05413229 10308 value_in_comment = value;
16980d0b
JB		 10309 break;
10310 case 'b':
10311 func (stream, "%ld", value * 8);
05413229 10312 value_in_comment = value * 8;
16980d0b
JB		 10313 break;
10314 case 'W':
10315 func (stream, "%ld", value + 1);
05413229 10316 value_in_comment = value + 1;
16980d0b
JB		 10317 break;
10318 case 'x':
10319 func (stream, "0x%08lx", value);
10320
10321 /* Some SWI instructions have special
10322 meanings. */
10323 if ((given & 0x0fffffff) == 0x0FF00000)
10324 func (stream, "\t; IMB");
10325 else if ((given & 0x0fffffff) == 0x0FF00001)
10326 func (stream, "\t; IMBRange");
10327 break;
10328 case 'X':
10329 func (stream, "%01lx", value & 0xf);
05413229 10330 value_in_comment = value;
252b5132
RH		 10331 break;
10332 case '`':
10333 c++;
16980d0b 10334 if (value == 0)
252b5132
RH		 10335 func (stream, "%c", *c);
10336 break;
10337 case '\'':
10338 c++;
16980d0b 10339 if (value == ((1ul << width) - 1))
252b5132
RH		 10340 func (stream, "%c", *c);
10341 break;
10342 case '?':
fe56b6ce 10343 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 10344 c += 1 << width;
252b5132
RH		 10345 break;
10346 default:
10347 abort ();
10348 }
dffaa15c
AM		 10349 }
10350 break;
0dd132b6 10351
dffaa15c
AM		 10352 case 'e':
10353 {
10354 int imm;
0dd132b6 10355
dffaa15c
AM		 10356 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
10357 func (stream, "%d", imm);
10358 value_in_comment = imm;
10359 }
10360 break;
fe56b6ce 10361
dffaa15c
AM		 10362 case 'E':
10363 /* LSB and WIDTH fields of BFI or BFC. The machine-
10364 language instruction encodes LSB and MSB. */
10365 {
10366 long msb = (given & 0x001f0000) >> 16;
10367 long lsb = (given & 0x00000f80) >> 7;
10368 long w = msb - lsb + 1;
0a003adc 10369
dffaa15c
AM		 10370 if (w > 0)
10371 func (stream, "#%lu, #%lu", lsb, w);
10372 else
10373 func (stream, "(invalid: %lu:%lu)", lsb, msb);
10374 }
10375 break;
90ec0d68 10376
dffaa15c
AM		 10377 case 'R':
10378 /* Get the PSR/banked register name. */
10379 {
10380 const char * name;
10381 unsigned sysm = (given & 0x004f0000) >> 16;
90ec0d68 10382
dffaa15c
AM		 10383 sysm |= (given & 0x300) >> 4;
10384 name = banked_regname (sysm);
90ec0d68 10385
dffaa15c
AM		 10386 if (name != NULL)
10387 func (stream, "%s", name);
10388 else
10389 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
10390 }
10391 break;
fe56b6ce 10392
dffaa15c
AM		 10393 case 'V':
10394 /* 16-bit unsigned immediate from a MOVT or MOVW
10395 instruction, encoded in bits 0:11 and 15:19. */
10396 {
10397 long hi = (given & 0x000f0000) >> 4;
10398 long lo = (given & 0x00000fff);
10399 long imm16 = hi | lo;
0a003adc 10400
dffaa15c
AM		 10401 func (stream, "#%lu", imm16);
10402 value_in_comment = imm16;
252b5132 10403 }
dffaa15c
AM		 10404 break;
10405
10406 default:
10407 abort ();
252b5132
RH		 10408 }
10409 }
10410 else
10411 func (stream, "%c", *c);
10412 }
05413229
NC		 10413
10414 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 10415 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 10416
10417 if (is_unpredictable)
10418 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 10419
4a5329c6 10420 return;
252b5132
RH		 10421 }
10422 }
0b347048
TC		 10423 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
10424 return;
252b5132
RH		 10425}
10426
4a5329c6 10427/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 10428
4a5329c6
ZW		 10429static void
10430print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 10431{
6b5d3a4d 10432 const struct opcode16 *insn;
6a51a8a8
AM		 10433 void *stream = info->stream;
10434 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 10435
10436 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 10437 if ((given & insn->mask) == insn->value)
10438 {
05413229 10439 signed long value_in_comment = 0;
6b5d3a4d 10440 const char *c = insn->assembler;
05413229 10441
c19d1205
ZW		 10442 for (; *c; c++)
10443 {
10444 int domaskpc = 0;
10445 int domasklr = 0;
10446
10447 if (*c != '%')
10448 {
10449 func (stream, "%c", *c);
10450 continue;
10451 }
252b5132 10452
c19d1205
ZW		 10453 switch (*++c)
10454 {
10455 case '%':
10456 func (stream, "%%");
10457 break;
b34976b6 10458
c22aaad1
PB		 10459 case 'c':
10460 if (ifthen_state)
10461 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10462 break;
10463
10464 case 'C':
10465 if (ifthen_state)
10466 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10467 else
10468 func (stream, "s");
10469 break;
10470
10471 case 'I':
10472 {
10473 unsigned int tmp;
10474
10475 ifthen_next_state = given & 0xff;
10476 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
10477 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
10478 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
10479 }
10480 break;
10481
10482 case 'x':
10483 if (ifthen_next_state)
10484 func (stream, "\t; unpredictable branch in IT block\n");
10485 break;
10486
10487 case 'X':
10488 if (ifthen_state)
10489 func (stream, "\t; unpredictable <IT:%s>",
10490 arm_conditional[IFTHEN_COND]);
10491 break;
10492
c19d1205
ZW		 10493 case 'S':
10494 {
10495 long reg;
10496
10497 reg = (given >> 3) & 0x7;
10498 if (given & (1 << 6))
10499 reg += 8;
4f3c3dbb 10500
c19d1205
ZW		 10501 func (stream, "%s", arm_regnames[reg]);
10502 }
10503 break;
baf0cc5e 10504
c19d1205 10505 case 'D':
4f3c3dbb 10506 {
c19d1205
ZW		 10507 long reg;
10508
10509 reg = given & 0x7;
10510 if (given & (1 << 7))
10511 reg += 8;
10512
10513 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 10514 }
c19d1205
ZW		 10515 break;
10516
10517 case 'N':
10518 if (given & (1 << 8))
10519 domasklr = 1;
10520 /* Fall through. */
10521 case 'O':
10522 if (*c == 'O' && (given & (1 << 8)))
10523 domaskpc = 1;
10524 /* Fall through. */
10525 case 'M':
10526 {
10527 int started = 0;
10528 int reg;
10529
10530 func (stream, "{");
10531
10532 /* It would be nice if we could spot
10533 ranges, and generate the rS-rE format: */
10534 for (reg = 0; (reg < 8); reg++)
10535 if ((given & (1 << reg)) != 0)
10536 {
10537 if (started)
10538 func (stream, ", ");
10539 started = 1;
10540 func (stream, "%s", arm_regnames[reg]);
10541 }
10542
10543 if (domasklr)
10544 {
10545 if (started)
10546 func (stream, ", ");
10547 started = 1;
d908c8af 10548 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 10549 }
10550
10551 if (domaskpc)
10552 {
10553 if (started)
10554 func (stream, ", ");
d908c8af 10555 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 10556 }
10557
10558 func (stream, "}");
10559 }
10560 break;
10561
4547cb56
NC		 10562 case 'W':
10563 /* Print writeback indicator for a LDMIA. We are doing a
10564 writeback if the base register is not in the register
10565 mask. */
10566 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
10567 func (stream, "!");
dffaa15c 10568 break;
4547cb56 10569
c19d1205
ZW		 10570 case 'b':
10571 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
10572 {
10573 bfd_vma address = (pc + 4
10574 + ((given & 0x00f8) >> 2)
10575 + ((given & 0x0200) >> 3));
10576 info->print_address_func (address, info);
1d67fe3b
TT		 10577
10578 /* Fill in instruction information. */
10579 info->insn_info_valid = 1;
10580 info->insn_type = dis_branch;
10581 info->target = address;
c19d1205
ZW		 10582 }
10583 break;
10584
10585 case 's':
10586 /* Right shift immediate -- bits 6..10; 1-31 print
10587 as themselves, 0 prints as 32. */
10588 {
10589 long imm = (given & 0x07c0) >> 6;
10590 if (imm == 0)
10591 imm = 32;
0fd3a477 10592 func (stream, "#%ld", imm);
c19d1205
ZW		 10593 }
10594 break;
10595
10596 case '0': case '1': case '2': case '3': case '4':
10597 case '5': case '6': case '7': case '8': case '9':
10598 {
10599 int bitstart = *c++ - '0';
10600 int bitend = 0;
10601
10602 while (*c >= '0' && *c <= '9')
10603 bitstart = (bitstart * 10) + *c++ - '0';
10604
10605 switch (*c)
10606 {
10607 case '-':
10608 {
f8b960bc 10609 bfd_vma reg;
c19d1205
ZW		 10610
10611 c++;
10612 while (*c >= '0' && *c <= '9')
10613 bitend = (bitend * 10) + *c++ - '0';
10614 if (!bitend)
10615 abort ();
10616 reg = given >> bitstart;
10617 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 10618
c19d1205
ZW		 10619 switch (*c)
10620 {
10621 case 'r':
10622 func (stream, "%s", arm_regnames[reg]);
10623 break;
10624
10625 case 'd':
d908c8af 10626 func (stream, "%ld", (long) reg);
05413229 10627 value_in_comment = reg;
c19d1205
ZW		 10628 break;
10629
10630 case 'H':
d908c8af 10631 func (stream, "%ld", (long) (reg << 1));
05413229 10632 value_in_comment = reg << 1;
c19d1205
ZW		 10633 break;
10634
10635 case 'W':
d908c8af 10636 func (stream, "%ld", (long) (reg << 2));
05413229 10637 value_in_comment = reg << 2;
c19d1205
ZW		 10638 break;
10639
10640 case 'a':
10641 /* PC-relative address -- the bottom two
10642 bits of the address are dropped
10643 before the calculation. */
10644 info->print_address_func
10645 (((pc + 4) & ~3) + (reg << 2), info);
05413229 10646 value_in_comment = 0;
c19d1205
ZW		 10647 break;
10648
10649 case 'x':
d908c8af 10650 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 10651 break;
10652
c19d1205
ZW		 10653 case 'B':
10654 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
1d67fe3b
TT		 10655 bfd_vma target = reg * 2 + pc + 4;
10656 info->print_address_func (target, info);
05413229 10657 value_in_comment = 0;
1d67fe3b
TT		 10658
10659 /* Fill in instruction information. */
10660 info->insn_info_valid = 1;
10661 info->insn_type = dis_branch;
10662 info->target = target;
c19d1205
ZW		 10663 break;
10664
10665 case 'c':
c22aaad1 10666 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 10667 break;
10668
10669 default:
10670 abort ();
10671 }
10672 }
10673 break;
10674
10675 case '\'':
10676 c++;
10677 if ((given & (1 << bitstart)) != 0)
10678 func (stream, "%c", *c);
10679 break;
10680
10681 case '?':
10682 ++c;
10683 if ((given & (1 << bitstart)) != 0)
10684 func (stream, "%c", *c++);
10685 else
10686 func (stream, "%c", *++c);
10687 break;
10688
10689 default:
10690 abort ();
10691 }
10692 }
10693 break;
10694
10695 default:
10696 abort ();
10697 }
10698 }
05413229
NC		 10699
10700 if (value_in_comment > 32 || value_in_comment < -16)
10701 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 10702 return;
c19d1205
ZW		 10703 }
10704
10705 /* No match. */
0b347048
TC		 10706 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
10707 return;
c19d1205
ZW		 10708}
10709
62b3e311 10710/* Return the name of an V7M special register. */
fe56b6ce 10711
62b3e311
PB		 10712static const char *
10713psr_name (int regno)
10714{
10715 switch (regno)
10716 {
1a336194
TP		 10717 case 0x0: return "APSR";
10718 case 0x1: return "IAPSR";
10719 case 0x2: return "EAPSR";
10720 case 0x3: return "PSR";
10721 case 0x5: return "IPSR";
10722 case 0x6: return "EPSR";
10723 case 0x7: return "IEPSR";
10724 case 0x8: return "MSP";
10725 case 0x9: return "PSP";
10726 case 0xa: return "MSPLIM";
10727 case 0xb: return "PSPLIM";
10728 case 0x10: return "PRIMASK";
10729 case 0x11: return "BASEPRI";
10730 case 0x12: return "BASEPRI_MAX";
10731 case 0x13: return "FAULTMASK";
10732 case 0x14: return "CONTROL";
16a1fa25
TP		 10733 case 0x88: return "MSP_NS";
10734 case 0x89: return "PSP_NS";
1a336194
TP		 10735 case 0x8a: return "MSPLIM_NS";
10736 case 0x8b: return "PSPLIM_NS";
10737 case 0x90: return "PRIMASK_NS";
10738 case 0x91: return "BASEPRI_NS";
10739 case 0x93: return "FAULTMASK_NS";
10740 case 0x94: return "CONTROL_NS";
10741 case 0x98: return "SP_NS";
62b3e311
PB		 10742 default: return "<unknown>";
10743 }
10744}
10745
4a5329c6
ZW		 10746/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
10747
10748static void
10749print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 10750{
6b5d3a4d 10751 const struct opcode32 *insn;
c19d1205
ZW		 10752 void *stream = info->stream;
10753 fprintf_ftype func = info->fprintf_func;
73cd51e5 10754 bfd_boolean is_mve = is_mve_architecture (info);
c19d1205 10755
16980d0b
JB		 10756 if (print_insn_coprocessor (pc, info, given, TRUE))
10757 return;
10758
73cd51e5
AV		 10759 if ((is_mve == FALSE) && print_insn_neon (info, given, TRUE))
10760 return;
10761
10762 if (is_mve && print_insn_mve (info, given))
8f06b2d8
PB		 10763 return;
10764
4934a27c
MM		 10765 if (print_insn_cde (info, given, TRUE))
10766 return;
10767
33593eaf
MM		 10768 if (print_insn_generic_coprocessor (pc, info, given, TRUE))
10769 return;
10770
c19d1205
ZW		 10771 for (insn = thumb32_opcodes; insn->assembler; insn++)
10772 if ((given & insn->mask) == insn->value)
10773 {
4b5a202f 10774 bfd_boolean is_clrm = FALSE;
ff4a8d2b 10775 bfd_boolean is_unpredictable = FALSE;
05413229 10776 signed long value_in_comment = 0;
6b5d3a4d 10777 const char *c = insn->assembler;
05413229 10778
c19d1205
ZW		 10779 for (; *c; c++)
10780 {
10781 if (*c != '%')
10782 {
10783 func (stream, "%c", *c);
10784 continue;
10785 }
10786
10787 switch (*++c)
10788 {
10789 case '%':
10790 func (stream, "%%");
10791 break;
10792
c22aaad1
PB		 10793 case 'c':
10794 if (ifthen_state)
10795 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10796 break;
10797
10798 case 'x':
10799 if (ifthen_next_state)
10800 func (stream, "\t; unpredictable branch in IT block\n");
10801 break;
10802
10803 case 'X':
10804 if (ifthen_state)
10805 func (stream, "\t; unpredictable <IT:%s>",
10806 arm_conditional[IFTHEN_COND]);
10807 break;
10808
c19d1205
ZW		 10809 case 'I':
10810 {
10811 unsigned int imm12 = 0;
fe56b6ce 10812
c19d1205
ZW		 10813 imm12 |= (given & 0x000000ffu);
10814 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 10815 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 10816 func (stream, "#%u", imm12);
10817 value_in_comment = imm12;
c19d1205
ZW		 10818 }
10819 break;
10820
10821 case 'M':
10822 {
10823 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 10824
c19d1205
ZW		 10825 bits |= (given & 0x000000ffu);
10826 bits |= (given & 0x00007000u) >> 4;
10827 bits |= (given & 0x04000000u) >> 15;
10828 imm8 = (bits & 0x0ff);
10829 mod = (bits & 0xf00) >> 8;
10830 switch (mod)
10831 {
10832 case 0: imm = imm8; break;
c1e26897
NC		 10833 case 1: imm = ((imm8 << 16) | imm8); break;
10834 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
10835 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 10836 default:
10837 mod = (bits & 0xf80) >> 7;
10838 imm8 = (bits & 0x07f) | 0x80;
10839 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
10840 }
fe56b6ce
NC		 10841 func (stream, "#%u", imm);
10842 value_in_comment = imm;
c19d1205
ZW		 10843 }
10844 break;
43e65147 10845
c19d1205
ZW		 10846 case 'J':
10847 {
10848 unsigned int imm = 0;
fe56b6ce 10849
c19d1205
ZW		 10850 imm |= (given & 0x000000ffu);
10851 imm |= (given & 0x00007000u) >> 4;
10852 imm |= (given & 0x04000000u) >> 15;
10853 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 10854 func (stream, "#%u", imm);
10855 value_in_comment = imm;
c19d1205
ZW		 10856 }
10857 break;
10858
10859 case 'K':
10860 {
10861 unsigned int imm = 0;
fe56b6ce 10862
c19d1205
ZW		 10863 imm |= (given & 0x000f0000u) >> 16;
10864 imm |= (given & 0x00000ff0u) >> 0;
10865 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 10866 func (stream, "#%u", imm);
10867 value_in_comment = imm;
c19d1205
ZW		 10868 }
10869 break;
10870
74db7efb
NC		 10871 case 'H':
10872 {
10873 unsigned int imm = 0;
10874
10875 imm |= (given & 0x000f0000u) >> 4;
10876 imm |= (given & 0x00000fffu) >> 0;
10877 func (stream, "#%u", imm);
10878 value_in_comment = imm;
10879 }
10880 break;
10881
90ec0d68
MGD		 10882 case 'V':
10883 {
10884 unsigned int imm = 0;
10885
10886 imm |= (given & 0x00000fffu);
10887 imm |= (given & 0x000f0000u) >> 4;
10888 func (stream, "#%u", imm);
10889 value_in_comment = imm;
10890 }
10891 break;
10892
c19d1205
ZW		 10893 case 'S':
10894 {
10895 unsigned int reg = (given & 0x0000000fu);
10896 unsigned int stp = (given & 0x00000030u) >> 4;
10897 unsigned int imm = 0;
10898 imm |= (given & 0x000000c0u) >> 6;
10899 imm |= (given & 0x00007000u) >> 10;
10900
10901 func (stream, "%s", arm_regnames[reg]);
10902 switch (stp)
10903 {
10904 case 0:
10905 if (imm > 0)
10906 func (stream, ", lsl #%u", imm);
10907 break;
10908
10909 case 1:
10910 if (imm == 0)
10911 imm = 32;
10912 func (stream, ", lsr #%u", imm);
10913 break;
10914
10915 case 2:
10916 if (imm == 0)
10917 imm = 32;
10918 func (stream, ", asr #%u", imm);
10919 break;
10920
10921 case 3:
10922 if (imm == 0)
10923 func (stream, ", rrx");
10924 else
10925 func (stream, ", ror #%u", imm);
10926 }
10927 }
10928 break;
10929
10930 case 'a':
10931 {
10932 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 10933 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 10934 unsigned int op = (given & 0x00000f00) >> 8;
10935 unsigned int i12 = (given & 0x00000fff);
10936 unsigned int i8 = (given & 0x000000ff);
10937 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 10938 bfd_vma offset = 0;
c19d1205
ZW		 10939
10940 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 10941 if (U) /* 12-bit positive immediate offset. */
10942 {
10943 offset = i12;
10944 if (Rn != 15)
10945 value_in_comment = offset;
10946 }
10947 else if (Rn == 15) /* 12-bit negative immediate offset. */
10948 offset = - (int) i12;
10949 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 10950 {
10951 unsigned int Rm = (i8 & 0x0f);
10952 unsigned int sh = (i8 & 0x30) >> 4;
05413229 10953
c19d1205
ZW		 10954 func (stream, ", %s", arm_regnames[Rm]);
10955 if (sh)
10956 func (stream, ", lsl #%u", sh);
10957 func (stream, "]");
10958 break;
10959 }
10960 else switch (op)
10961 {
05413229 10962 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 10963 offset = i8;
10964 break;
10965
05413229 10966 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 10967 offset = -i8;
10968 break;
10969
05413229 10970 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 10971 offset = i8;
10972 writeback = TRUE;
10973 break;
10974
05413229 10975 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 10976 offset = -i8;
10977 writeback = TRUE;
10978 break;
10979
05413229 10980 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 10981 offset = i8;
10982 postind = TRUE;
10983 break;
10984
05413229 10985 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 10986 offset = -i8;
10987 postind = TRUE;
10988 break;
10989
10990 default:
10991 func (stream, ", <undefined>]");
10992 goto skip;
10993 }
10994
10995 if (postind)
d908c8af 10996 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 10997 else
10998 {
10999 if (offset)
d908c8af 11000 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 11001 func (stream, writeback ? "]!" : "]");
11002 }
11003
11004 if (Rn == 15)
11005 {
11006 func (stream, "\t; ");
11007 info->print_address_func (((pc + 4) & ~3) + offset, info);
11008 }
11009 }
11010 skip:
11011 break;
11012
11013 case 'A':
11014 {
c1e26897
NC		 11015 unsigned int U = ! NEGATIVE_BIT_SET;
11016 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 11017 unsigned int Rn = (given & 0x000f0000) >> 16;
11018 unsigned int off = (given & 0x000000ff);
11019
11020 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 11021
11022 if (PRE_BIT_SET)
c19d1205
ZW		 11023 {
11024 if (off || !U)
05413229
NC		 11025 {
11026 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
fe50e98c 11027 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 11028 }
c19d1205
ZW		 11029 func (stream, "]");
11030 if (W)
11031 func (stream, "!");
11032 }
11033 else
11034 {
11035 func (stream, "], ");
11036 if (W)
05413229
NC		 11037 {
11038 func (stream, "#%c%u", U ? '+' : '-', off * 4);
fe50e98c 11039 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 11040 }
c19d1205 11041 else
fe56b6ce
NC		 11042 {
11043 func (stream, "{%u}", off);
11044 value_in_comment = off;
11045 }
c19d1205
ZW		 11046 }
11047 }
11048 break;
11049
11050 case 'w':
11051 {
11052 unsigned int Sbit = (given & 0x01000000) >> 24;
11053 unsigned int type = (given & 0x00600000) >> 21;
05413229 11054
c19d1205
ZW		 11055 switch (type)
11056 {
11057 case 0: func (stream, Sbit ? "sb" : "b"); break;
11058 case 1: func (stream, Sbit ? "sh" : "h"); break;
11059 case 2:
11060 if (Sbit)
11061 func (stream, "??");
11062 break;
11063 case 3:
11064 func (stream, "??");
11065 break;
11066 }
11067 }
11068 break;
11069
4b5a202f
AV		 11070 case 'n':
11071 is_clrm = TRUE;
11072 /* Fall through. */
c19d1205
ZW		 11073 case 'm':
11074 {
11075 int started = 0;
11076 int reg;
11077
11078 func (stream, "{");
11079 for (reg = 0; reg < 16; reg++)
11080 if ((given & (1 << reg)) != 0)
11081 {
11082 if (started)
11083 func (stream, ", ");
11084 started = 1;
4b5a202f
AV		 11085 if (is_clrm && reg == 13)
11086 func (stream, "(invalid: %s)", arm_regnames[reg]);
11087 else if (is_clrm && reg == 15)
11088 func (stream, "%s", "APSR");
11089 else
11090 func (stream, "%s", arm_regnames[reg]);
c19d1205
ZW		 11091 }
11092 func (stream, "}");
11093 }
11094 break;
11095
11096 case 'E':
11097 {
11098 unsigned int msb = (given & 0x0000001f);
11099 unsigned int lsb = 0;
fe56b6ce 11100
c19d1205
ZW		 11101 lsb |= (given & 0x000000c0u) >> 6;
11102 lsb |= (given & 0x00007000u) >> 10;
11103 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
11104 }
11105 break;
11106
11107 case 'F':
11108 {
11109 unsigned int width = (given & 0x0000001f) + 1;
11110 unsigned int lsb = 0;
fe56b6ce 11111
c19d1205
ZW		 11112 lsb |= (given & 0x000000c0u) >> 6;
11113 lsb |= (given & 0x00007000u) >> 10;
11114 func (stream, "#%u, #%u", lsb, width);
11115 }
11116 break;
11117
e12437dc
AV		 11118 case 'G':
11119 {
11120 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
11121 func (stream, "%x", boff);
11122 }
11123 break;
11124
e5d6e09e
AV		 11125 case 'W':
11126 {
11127 unsigned int immA = (given & 0x001f0000u) >> 16;
11128 unsigned int immB = (given & 0x000007feu) >> 1;
11129 unsigned int immC = (given & 0x00000800u) >> 11;
11130 bfd_vma offset = 0;
11131
11132 offset |= immA << 12;
11133 offset |= immB << 2;
11134 offset |= immC << 1;
11135 /* Sign extend. */
11136 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
11137
11138 info->print_address_func (pc + 4 + offset, info);
11139 }
11140 break;
11141
1caf72a5
AV		 11142 case 'Y':
11143 {
11144 unsigned int immA = (given & 0x007f0000u) >> 16;
11145 unsigned int immB = (given & 0x000007feu) >> 1;
11146 unsigned int immC = (given & 0x00000800u) >> 11;
11147 bfd_vma offset = 0;
11148
11149 offset |= immA << 12;
11150 offset |= immB << 2;
11151 offset |= immC << 1;
11152 /* Sign extend. */
11153 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
11154
11155 info->print_address_func (pc + 4 + offset, info);
11156 }
11157 break;
11158
1889da70
AV		 11159 case 'Z':
11160 {
11161 unsigned int immA = (given & 0x00010000u) >> 16;
11162 unsigned int immB = (given & 0x000007feu) >> 1;
11163 unsigned int immC = (given & 0x00000800u) >> 11;
11164 bfd_vma offset = 0;
11165
11166 offset |= immA << 12;
11167 offset |= immB << 2;
11168 offset |= immC << 1;
11169 /* Sign extend. */
11170 offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
11171
11172 info->print_address_func (pc + 4 + offset, info);
f6b2b12d
AV		 11173
11174 unsigned int T = (given & 0x00020000u) >> 17;
11175 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
11176 unsigned int boffset = (T == 1) ? 4 : 2;
11177 func (stream, ", ");
11178 func (stream, "%x", endoffset + boffset);
1889da70
AV		 11179 }
11180 break;
11181
60f993ce
AV		 11182 case 'Q':
11183 {
11184 unsigned int immh = (given & 0x000007feu) >> 1;
11185 unsigned int imml = (given & 0x00000800u) >> 11;
11186 bfd_vma imm32 = 0;
11187
11188 imm32 |= immh << 2;
11189 imm32 |= imml << 1;
11190
11191 info->print_address_func (pc + 4 + imm32, info);
11192 }
11193 break;
11194
11195 case 'P':
11196 {
11197 unsigned int immh = (given & 0x000007feu) >> 1;
11198 unsigned int imml = (given & 0x00000800u) >> 11;
11199 bfd_vma imm32 = 0;
11200
11201 imm32 |= immh << 2;
11202 imm32 |= imml << 1;
11203
11204 info->print_address_func (pc + 4 - imm32, info);
11205 }
11206 break;
11207
c19d1205
ZW		 11208 case 'b':
11209 {
11210 unsigned int S = (given & 0x04000000u) >> 26;
11211 unsigned int J1 = (given & 0x00002000u) >> 13;
11212 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 11213 bfd_vma offset = 0;
c19d1205
ZW		 11214
11215 offset |= !S << 20;
11216 offset |= J2 << 19;
11217 offset |= J1 << 18;
11218 offset |= (given & 0x003f0000) >> 4;
11219 offset |= (given & 0x000007ff) << 1;
11220 offset -= (1 << 20);
11221
1d67fe3b
TT		 11222 bfd_vma target = pc + 4 + offset;
11223 info->print_address_func (target, info);
11224
11225 /* Fill in instruction information. */
11226 info->insn_info_valid = 1;
11227 info->insn_type = dis_branch;
11228 info->target = target;
c19d1205
ZW		 11229 }
11230 break;
11231
11232 case 'B':
11233 {
11234 unsigned int S = (given & 0x04000000u) >> 26;
11235 unsigned int I1 = (given & 0x00002000u) >> 13;
11236 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 11237 bfd_vma offset = 0;
c19d1205
ZW		 11238
11239 offset |= !S << 24;
11240 offset |= !(I1 ^ S) << 23;
11241 offset |= !(I2 ^ S) << 22;
11242 offset |= (given & 0x03ff0000u) >> 4;
11243 offset |= (given & 0x000007ffu) << 1;
11244 offset -= (1 << 24);
36b0c57d 11245 offset += pc + 4;
c19d1205 11246
36b0c57d
PB		 11247 /* BLX target addresses are always word aligned. */
11248 if ((given & 0x00001000u) == 0)
11249 offset &= ~2u;
11250
11251 info->print_address_func (offset, info);
1d67fe3b
TT		 11252
11253 /* Fill in instruction information. */
11254 info->insn_info_valid = 1;
11255 info->insn_type = dis_branch;
11256 info->target = offset;
c19d1205
ZW		 11257 }
11258 break;
11259
11260 case 's':
11261 {
11262 unsigned int shift = 0;
fe56b6ce 11263
c19d1205
ZW		 11264 shift |= (given & 0x000000c0u) >> 6;
11265 shift |= (given & 0x00007000u) >> 10;
c1e26897 11266 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 11267 func (stream, ", asr #%u", shift);
11268 else if (shift)
11269 func (stream, ", lsl #%u", shift);
11270 /* else print nothing - lsl #0 */
11271 }
11272 break;
11273
11274 case 'R':
11275 {
11276 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 11277
c19d1205
ZW		 11278 if (rot)
11279 func (stream, ", ror #%u", rot * 8);
11280 }
11281 break;
11282
62b3e311 11283 case 'U':
43e65147 11284 if ((given & 0xf0) == 0x60)
62b3e311 11285 {
52e7f43d
RE		 11286 switch (given & 0xf)
11287 {
11288 case 0xf: func (stream, "sy"); break;
11289 default:
11290 func (stream, "#%d", (int) given & 0xf);
11291 break;
11292 }
62b3e311 11293 }
43e65147 11294 else
52e7f43d 11295 {
e797f7e0
MGD		 11296 const char * opt = data_barrier_option (given & 0xf);
11297 if (opt != NULL)
11298 func (stream, "%s", opt);
11299 else
11300 func (stream, "#%d", (int) given & 0xf);
52e7f43d 11301 }
62b3e311
PB		 11302 break;
11303
11304 case 'C':
11305 if ((given & 0xff) == 0)
11306 {
11307 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
11308 if (given & 0x800)
11309 func (stream, "f");
11310 if (given & 0x400)
11311 func (stream, "s");
11312 if (given & 0x200)
11313 func (stream, "x");
11314 if (given & 0x100)
11315 func (stream, "c");
11316 }
90ec0d68
MGD		 11317 else if ((given & 0x20) == 0x20)
11318 {
11319 char const* name;
11320 unsigned sysm = (given & 0xf00) >> 8;
11321
11322 sysm |= (given & 0x30);
11323 sysm |= (given & 0x00100000) >> 14;
11324 name = banked_regname (sysm);
43e65147 11325
90ec0d68
MGD		 11326 if (name != NULL)
11327 func (stream, "%s", name);
11328 else
d908c8af 11329 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 11330 }
62b3e311
PB		 11331 else
11332 {
d908c8af 11333 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 11334 }
11335 break;
11336
11337 case 'D':
90ec0d68
MGD		 11338 if (((given & 0xff) == 0)
11339 || ((given & 0x20) == 0x20))
11340 {
11341 char const* name;
11342 unsigned sm = (given & 0xf0000) >> 16;
11343
11344 sm |= (given & 0x30);
11345 sm |= (given & 0x00100000) >> 14;
11346 name = banked_regname (sm);
11347
11348 if (name != NULL)
11349 func (stream, "%s", name);
11350 else
d908c8af 11351 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 11352 }
62b3e311 11353 else
d908c8af 11354 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 11355 break;
11356
c19d1205
ZW		 11357 case '0': case '1': case '2': case '3': case '4':
11358 case '5': case '6': case '7': case '8': case '9':
11359 {
16980d0b
JB		 11360 int width;
11361 unsigned long val;
c19d1205 11362
16980d0b 11363 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 11364
c19d1205
ZW		 11365 switch (*c)
11366 {
d052b9b7
AV		 11367 case 's':
11368 if (val <= 3)
11369 func (stream, "%s", mve_vec_sizename[val]);
11370 else
11371 func (stream, "<undef size>");
11372 break;
11373
05413229
NC		 11374 case 'd':
11375 func (stream, "%lu", val);
11376 value_in_comment = val;
11377 break;
ff4a8d2b 11378
f0fba320
RL		 11379 case 'D':
11380 func (stream, "%lu", val + 1);
11381 value_in_comment = val + 1;
11382 break;
11383
05413229
NC		 11384 case 'W':
11385 func (stream, "%lu", val * 4);
11386 value_in_comment = val * 4;
11387 break;
ff4a8d2b 11388
f1c7f421
AV		 11389 case 'S':
11390 if (val == 13)
11391 is_unpredictable = TRUE;
11392 /* Fall through. */
ff4a8d2b
NC		 11393 case 'R':
11394 if (val == 15)
11395 is_unpredictable = TRUE;
11396 /* Fall through. */
11397 case 'r':
11398 func (stream, "%s", arm_regnames[val]);
11399 break;
c19d1205
ZW		 11400
11401 case 'c':
c22aaad1 11402 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 11403 break;
11404
11405 case '\'':
c19d1205 11406 c++;
16980d0b
JB		 11407 if (val == ((1ul << width) - 1))
11408 func (stream, "%c", *c);
c19d1205 11409 break;
43e65147 11410
c19d1205 11411 case '`':
c19d1205 11412 c++;
16980d0b
JB		 11413 if (val == 0)
11414 func (stream, "%c", *c);
c19d1205
ZW		 11415 break;
11416
11417 case '?':
fe56b6ce 11418 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 11419 c += 1 << width;
c19d1205 11420 break;
43e65147 11421
0bb027fd
RR		 11422 case 'x':
11423 func (stream, "0x%lx", val & 0xffffffffUL);
11424 break;
c19d1205
ZW		 11425
11426 default:
11427 abort ();
11428 }
11429 }
11430 break;
11431
32a94698
NC		 11432 case 'L':
11433 /* PR binutils/12534
11434 If we have a PC relative offset in an LDRD or STRD
11435 instructions then display the decoded address. */
11436 if (((given >> 16) & 0xf) == 0xf)
11437 {
11438 bfd_vma offset = (given & 0xff) * 4;
11439
11440 if ((given & (1 << 23)) == 0)
11441 offset = - offset;
11442 func (stream, "\t; ");
11443 info->print_address_func ((pc & ~3) + 4 + offset, info);
11444 }
11445 break;
11446
c19d1205
ZW		 11447 default:
11448 abort ();
11449 }
11450 }
05413229
NC		 11451
11452 if (value_in_comment > 32 || value_in_comment < -16)
11453 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 11454
11455 if (is_unpredictable)
11456 func (stream, UNPREDICTABLE_INSTRUCTION);
11457
4a5329c6 11458 return;
c19d1205 11459 }
252b5132 11460
58efb6c0 11461 /* No match. */
0b347048
TC		 11462 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
11463 return;
252b5132
RH		 11464}
11465
e821645d
DJ		 11466/* Print data bytes on INFO->STREAM. */
11467
11468static void
fe56b6ce
NC		 11469print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
11470 struct disassemble_info *info,
e821645d
DJ		 11471 long given)
11472{
11473 switch (info->bytes_per_chunk)
11474 {
11475 case 1:
11476 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
11477 break;
11478 case 2:
11479 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
11480 break;
11481 case 4:
11482 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
11483 break;
11484 default:
11485 abort ();
11486 }
11487}
11488
22a398e1 11489/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 11490 being displayed in symbol relative addresses.
11491
11492 Also disallow private symbol, with __tagsym$$ prefix,
11493 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 11494
11495bfd_boolean
11496arm_symbol_is_valid (asymbol * sym,
11497 struct disassemble_info * info ATTRIBUTE_UNUSED)
11498{
11499 const char * name;
43e65147 11500
22a398e1
NC		 11501 if (sym == NULL)
11502 return FALSE;
11503
11504 name = bfd_asymbol_name (sym);
11505
d8282f0e 11506 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 11507}
11508
65b48a81 11509/* Parse the string of disassembler options. */
baf0cc5e 11510
65b48a81 11511static void
f995bbe8 11512parse_arm_disassembler_options (const char *options)
dd92f639 11513{
f995bbe8 11514 const char *opt;
b34976b6 11515
65b48a81 11516 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
dd92f639 11517 {
65b48a81
PB		 11518 if (CONST_STRNEQ (opt, "reg-names-"))
11519 {
11520 unsigned int i;
11521 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11522 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
11523 {
11524 regname_selected = i;
11525 break;
11526 }
b34976b6 11527
65b48a81 11528 if (i >= NUM_ARM_OPTIONS)
a6743a54
AM		 11529 /* xgettext: c-format */
11530 opcodes_error_handler (_("unrecognised register name set: %s"),
11531 opt);
65b48a81
PB		 11532 }
11533 else if (CONST_STRNEQ (opt, "force-thumb"))
11534 force_thumb = 1;
11535 else if (CONST_STRNEQ (opt, "no-force-thumb"))
11536 force_thumb = 0;
4934a27c
MM		 11537 else if (CONST_STRNEQ (opt, "coproc"))
11538 {
11539 const char *procptr = opt + sizeof ("coproc") - 1;
11540 char *endptr;
11541 uint8_t coproc_number = strtol (procptr, &endptr, 10);
11542 if (endptr != procptr + 1 || coproc_number > 7)
11543 {
11544 opcodes_error_handler (_("cde coprocessor not between 0-7: %s"),
11545 opt);
11546 continue;
11547 }
11548 if (*endptr != '=')
11549 {
11550 opcodes_error_handler (_("coproc must have an argument: %s"),
11551 opt);
11552 continue;
11553 }
11554 endptr += 1;
11555 if (CONST_STRNEQ (endptr, "generic"))
11556 cde_coprocs &= ~(1 << coproc_number);
11557 else if (CONST_STRNEQ (endptr, "cde")
11558 || CONST_STRNEQ (endptr, "CDE"))
11559 cde_coprocs |= (1 << coproc_number);
11560 else
11561 {
11562 opcodes_error_handler (
11563 _("coprocN argument takes options \"generic\","
11564 " \"cde\", or \"CDE\": %s"), opt);
11565 }
11566 }
65b48a81 11567 else
a6743a54
AM		 11568 /* xgettext: c-format */
11569 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
dd92f639 11570 }
b34976b6 11571
dd92f639
NC		 11572 return;
11573}
11574
5bc5ae88
RL		 11575static bfd_boolean
11576mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11577 enum map_type *map_symbol);
11578
c22aaad1
PB		 11579/* Search back through the insn stream to determine if this instruction is
11580 conditionally executed. */
fe56b6ce 11581
c22aaad1 11582static void
fe56b6ce
NC		 11583find_ifthen_state (bfd_vma pc,
11584 struct disassemble_info *info,
c22aaad1
PB		 11585 bfd_boolean little)
11586{
11587 unsigned char b[2];
11588 unsigned int insn;
11589 int status;
11590 /* COUNT is twice the number of instructions seen. It will be odd if we
11591 just crossed an instruction boundary. */
11592 int count;
11593 int it_count;
11594 unsigned int seen_it;
11595 bfd_vma addr;
11596
11597 ifthen_address = pc;
11598 ifthen_state = 0;
11599
11600 addr = pc;
11601 count = 1;
11602 it_count = 0;
11603 seen_it = 0;
11604 /* Scan backwards looking for IT instructions, keeping track of where
11605 instruction boundaries are. We don't know if something is actually an
11606 IT instruction until we find a definite instruction boundary. */
11607 for (;;)
11608 {
fe56b6ce 11609 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 11610 {
11611 /* A symbol must be on an instruction boundary, and will not
11612 be within an IT block. */
11613 if (seen_it && (count & 1))
11614 break;
11615
11616 return;
11617 }
11618 addr -= 2;
fe56b6ce 11619 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 11620 if (status)
11621 return;
11622
11623 if (little)
11624 insn = (b[0]) | (b[1] << 8);
11625 else
11626 insn = (b[1]) | (b[0] << 8);
11627 if (seen_it)
11628 {
11629 if ((insn & 0xf800) < 0xe800)
11630 {
11631 /* Addr + 2 is an instruction boundary. See if this matches
11632 the expected boundary based on the position of the last
11633 IT candidate. */
11634 if (count & 1)
11635 break;
11636 seen_it = 0;
11637 }
11638 }
11639 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
11640 {
5bc5ae88
RL		 11641 enum map_type type = MAP_ARM;
11642 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
11643
11644 if (!found || (found && type == MAP_THUMB))
11645 {
11646 /* This could be an IT instruction. */
11647 seen_it = insn;
11648 it_count = count >> 1;
11649 }
c22aaad1
PB		 11650 }
11651 if ((insn & 0xf800) >= 0xe800)
11652 count++;
11653 else
11654 count = (count + 2) | 1;
11655 /* IT blocks contain at most 4 instructions. */
11656 if (count >= 8 && !seen_it)
11657 return;
11658 }
11659 /* We found an IT instruction. */
11660 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
11661 if ((ifthen_state & 0xf) == 0)
11662 ifthen_state = 0;
11663}
11664
b0e28b39
DJ		 11665/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
11666 mapping symbol. */
11667
11668static int
11669is_mapping_symbol (struct disassemble_info *info, int n,
11670 enum map_type *map_type)
11671{
11672 const char *name;
11673
11674 name = bfd_asymbol_name (info->symtab[n]);
11675 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
11676 && (name[2] == 0 || name[2] == '.'))
11677 {
11678 *map_type = ((name[1] == 'a') ? MAP_ARM
11679 : (name[1] == 't') ? MAP_THUMB
11680 : MAP_DATA);
11681 return TRUE;
11682 }
11683
11684 return FALSE;
11685}
11686
11687/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
11688 Returns nonzero if *MAP_TYPE was set. */
11689
11690static int
11691get_map_sym_type (struct disassemble_info *info,
11692 int n,
11693 enum map_type *map_type)
11694{
11695 /* If the symbol is in a different section, ignore it. */
11696 if (info->section != NULL && info->section != info->symtab[n]->section)
11697 return FALSE;
11698
11699 return is_mapping_symbol (info, n, map_type);
11700}
11701
11702/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 11703 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 11704
11705static int
fe56b6ce
NC		 11706get_sym_code_type (struct disassemble_info *info,
11707 int n,
e821645d 11708 enum map_type *map_type)
2087ad84
PB		 11709{
11710 elf_symbol_type *es;
11711 unsigned int type;
b0e28b39
DJ		 11712
11713 /* If the symbol is in a different section, ignore it. */
11714 if (info->section != NULL && info->section != info->symtab[n]->section)
11715 return FALSE;
2087ad84 11716
e821645d 11717 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 11718 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
11719
11720 /* If the symbol has function type then use that. */
34e77a92 11721 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 11722 {
39d911fc
TP		 11723 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
11724 == ST_BRANCH_TO_THUMB)
35fc36a8
RS		 11725 *map_type = MAP_THUMB;
11726 else
11727 *map_type = MAP_ARM;
2087ad84
PB		 11728 return TRUE;
11729 }
11730
2087ad84
PB		 11731 return FALSE;
11732}
11733
5bc5ae88
RL		 11734/* Search the mapping symbol state for instruction at pc. This is only
11735 applicable for elf target.
11736
11737 There is an assumption Here, info->private_data contains the correct AND
11738 up-to-date information about current scan process. The information will be
11739 used to speed this search process.
11740
11741 Return TRUE if the mapping state can be determined, and map_symbol
11742 will be updated accordingly. Otherwise, return FALSE. */
11743
11744static bfd_boolean
11745mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11746 enum map_type *map_symbol)
11747{
796d6298
TC		 11748 bfd_vma addr, section_vma = 0;
11749 int n, last_sym = -1;
5bc5ae88 11750 bfd_boolean found = FALSE;
796d6298
TC		 11751 bfd_boolean can_use_search_opt_p = FALSE;
11752
11753 /* Default to DATA. A text section is required by the ABI to contain an
11754 INSN mapping symbol at the start. A data section has no such
11755 requirement, hence if no mapping symbol is found the section must
11756 contain only data. This however isn't very useful if the user has
11757 fully stripped the binaries. If this is the case use the section
11758 attributes to determine the default. If we have no section default to
11759 INSN as well, as we may be disassembling some raw bytes on a baremetal
11760 HEX file or similar. */
11761 enum map_type type = MAP_DATA;
11762 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
11763 type = MAP_ARM;
5bc5ae88
RL		 11764 struct arm_private_data *private_data;
11765
796d6298 11766 if (info->private_data == NULL
5bc5ae88
RL		 11767 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
11768 return FALSE;
11769
11770 private_data = info->private_data;
5bc5ae88 11771
796d6298
TC		 11772 /* First, look for mapping symbols. */
11773 if (info->symtab_size != 0)
11774 {
11775 if (pc <= private_data->last_mapping_addr)
11776 private_data->last_mapping_sym = -1;
11777
11778 /* Start scanning at the start of the function, or wherever
11779 we finished last time. */
11780 n = info->symtab_pos + 1;
11781
11782 /* If the last stop offset is different from the current one it means we
11783 are disassembling a different glob of bytes. As such the optimization
11784 would not be safe and we should start over. */
11785 can_use_search_opt_p
11786 = private_data->last_mapping_sym >= 0
11787 && info->stop_offset == private_data->last_stop_offset;
11788
11789 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11790 n = private_data->last_mapping_sym;
11791
11792 /* Look down while we haven't passed the location being disassembled.
11793 The reason for this is that there's no defined order between a symbol
11794 and an mapping symbol that may be at the same address. We may have to
11795 look at least one position ahead. */
11796 for (; n < info->symtab_size; n++)
11797 {
11798 addr = bfd_asymbol_value (info->symtab[n]);
11799 if (addr > pc)
11800 break;
11801 if (get_map_sym_type (info, n, &type))
11802 {
11803 last_sym = n;
11804 found = TRUE;
11805 }
11806 }
5bc5ae88 11807
796d6298
TC		 11808 if (!found)
11809 {
11810 n = info->symtab_pos;
11811 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11812 n = private_data->last_mapping_sym;
11813
11814 /* No mapping symbol found at this address. Look backwards
11815 for a preceeding one, but don't go pass the section start
11816 otherwise a data section with no mapping symbol can pick up
11817 a text mapping symbol of a preceeding section. The documentation
11818 says section can be NULL, in which case we will seek up all the
11819 way to the top. */
11820 if (info->section)
11821 section_vma = info->section->vma;
11822
11823 for (; n >= 0; n--)
11824 {
11825 addr = bfd_asymbol_value (info->symtab[n]);
11826 if (addr < section_vma)
11827 break;
11828
11829 if (get_map_sym_type (info, n, &type))
11830 {
11831 last_sym = n;
11832 found = TRUE;
11833 break;
11834 }
11835 }
11836 }
11837 }
11838
11839 /* If no mapping symbol was found, try looking up without a mapping
11840 symbol. This is done by walking up from the current PC to the nearest
11841 symbol. We don't actually have to loop here since symtab_pos will
11842 contain the nearest symbol already. */
11843 if (!found)
5bc5ae88 11844 {
796d6298
TC		 11845 n = info->symtab_pos;
11846 if (n >= 0 && get_sym_code_type (info, n, &type))
5bc5ae88 11847 {
796d6298
TC		 11848 last_sym = n;
11849 found = TRUE;
5bc5ae88
RL		 11850 }
11851 }
11852
796d6298
TC		 11853 private_data->last_mapping_sym = last_sym;
11854 private_data->last_type = type;
11855 private_data->last_stop_offset = info->stop_offset;
5bc5ae88
RL		 11856
11857 *map_symbol = type;
11858 return found;
11859}
11860
0313a2b8
NC		 11861/* Given a bfd_mach_arm_XXX value, this function fills in the fields
11862 of the supplied arm_feature_set structure with bitmasks indicating
c0c468d5 11863 the supported base architectures and coprocessor extensions.
0313a2b8
NC		 11864
11865 FIXME: This could more efficiently implemented as a constant array,
11866 although it would also be less robust. */
11867
11868static void
11869select_arm_features (unsigned long mach,
11870 arm_feature_set * features)
11871{
c0c468d5
TP		 11872 arm_feature_set arch_fset;
11873 const arm_feature_set fpu_any = FPU_ANY;
11874
1af1dd51
MW		 11875#undef ARM_SET_FEATURES
11876#define ARM_SET_FEATURES(FSET) \
11877 { \
11878 const arm_feature_set fset = FSET; \
c0c468d5 11879 arch_fset = fset; \
1af1dd51 11880 }
823d2571 11881
c0c468d5
TP		 11882 /* When several architecture versions share the same bfd_mach_arm_XXX value
11883 the most featureful is chosen. */
0313a2b8
NC		 11884 switch (mach)
11885 {
c0c468d5
TP		 11886 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
11887 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
11888 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
11889 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
11890 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
11891 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
11892 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
11893 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
11894 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
11895 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
1af1dd51 11896 case bfd_mach_arm_ep9312:
c0c468d5
TP		 11897 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
11898 ARM_CEXT_MAVERICK | FPU_MAVERICK));
1af1dd51 11899 break;
c0c468d5
TP		 11900 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
11901 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
11902 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
11903 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
11904 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
11905 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
11906 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
11907 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
11908 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
11909 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
11910 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
11911 case bfd_mach_arm_8:
11912 {
aab2c27d
MM		 11913 /* Add bits for extensions that Armv8.6-A recognizes. */
11914 arm_feature_set armv8_6_ext_fset
0632eeea 11915 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
aab2c27d
MM		 11916 ARM_SET_FEATURES (ARM_ARCH_V8_6A);
11917 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_6_ext_fset);
c0c468d5
TP		 11918 break;
11919 }
11920 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
11921 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
11922 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
73cd51e5
AV		 11923 case bfd_mach_arm_8_1M_MAIN:
11924 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
2da2eaf4
AV		 11925 arm_feature_set mve_all
11926 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP);
11927 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, mve_all);
73cd51e5
AV		 11928 force_thumb = 1;
11929 break;
c0c468d5 11930 /* If the machine type is unknown allow all architecture types and all
2da2eaf4
AV		 11931 extensions, with the exception of MVE as that clashes with NEON. */
11932 case bfd_mach_arm_unknown:
11933 ARM_SET_FEATURES (ARM_FEATURE (-1,
11934 -1 & ~(ARM_EXT2_MVE | ARM_EXT2_MVE_FP),
11935 -1));
11936 break;
0313a2b8
NC		 11937 default:
11938 abort ();
11939 }
1af1dd51 11940#undef ARM_SET_FEATURES
c0c468d5
TP		 11941
11942 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
11943 and thus on bfd_mach_arm_XXX value. Therefore for a given
11944 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
11945 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
0313a2b8
NC		 11946}
11947
11948
58efb6c0
NC		 11949/* NOTE: There are no checks in these routines that
11950 the relevant number of data bytes exist. */
baf0cc5e 11951
58efb6c0 11952static int
4a5329c6 11953print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 11954{
c19d1205 11955 unsigned char b[4];
2480b6fa 11956 unsigned long given;
c19d1205 11957 int status;
e821645d 11958 int is_thumb = FALSE;
b0e28b39 11959 int is_data = FALSE;
bd2e2557 11960 int little_code;
e821645d 11961 unsigned int size = 4;
4a5329c6 11962 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 11963 bfd_boolean found = FALSE;
b0e28b39 11964 struct arm_private_data *private_data;
58efb6c0 11965
1d67fe3b
TT		 11966 /* Clear instruction information field. */
11967 info->insn_info_valid = 0;
11968 info->branch_delay_insns = 0;
11969 info->data_size = 0;
11970 info->insn_type = dis_noninsn;
11971 info->target = 0;
11972 info->target2 = 0;
11973
dd92f639
NC		 11974 if (info->disassembler_options)
11975 {
65b48a81 11976 parse_arm_disassembler_options (info->disassembler_options);
b34976b6 11977
58efb6c0 11978 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 11979 info->disassembler_options = NULL;
11980 }
b34976b6 11981
0313a2b8
NC		 11982 /* PR 10288: Control which instructions will be disassembled. */
11983 if (info->private_data == NULL)
11984 {
b0e28b39 11985 static struct arm_private_data private;
0313a2b8
NC		 11986
11987 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
11988 /* If the user did not use the -m command line switch then default to
11989 disassembling all types of ARM instruction.
43e65147 11990
0313a2b8
NC		 11991 The info->mach value has to be ignored as this will be based on
11992 the default archictecture for the target and/or hints in the notes
11993 section, but it will never be greater than the current largest arm
11994 machine value (iWMMXt2), which is only equivalent to the V5TE
11995 architecture. ARM architectures have advanced beyond the machine
11996 value encoding, and these newer architectures would be ignored if
11997 the machine value was used.
11998
11999 Ie the -m switch is used to restrict which instructions will be
12000 disassembled. If it is necessary to use the -m switch to tell
12001 objdump that an ARM binary is being disassembled, eg because the
12002 input is a raw binary file, but it is also desired to disassemble
12003 all ARM instructions then use "-marm". This will select the
12004 "unknown" arm architecture which is compatible with any ARM
12005 instruction. */
12006 info->mach = bfd_mach_arm_unknown;
12007
12008 /* Compute the architecture bitmask from the machine number.
12009 Note: This assumes that the machine number will not change
12010 during disassembly.... */
b0e28b39 12011 select_arm_features (info->mach, & private.features);
0313a2b8 12012
1fbaefec
PB		 12013 private.last_mapping_sym = -1;
12014 private.last_mapping_addr = 0;
796d6298 12015 private.last_stop_offset = 0;
b0e28b39
DJ		 12016
12017 info->private_data = & private;
0313a2b8 12018 }
b0e28b39
DJ		 12019
12020 private_data = info->private_data;
12021
bd2e2557
SS		 12022 /* Decide if our code is going to be little-endian, despite what the
12023 function argument might say. */
12024 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
12025
b0e28b39
DJ		 12026 /* For ELF, consult the symbol table to determine what kind of code
12027 or data we have. */
8977d4b2 12028 if (info->symtab_size != 0
e821645d
DJ		 12029 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
12030 {
12031 bfd_vma addr;
796d6298 12032 int n;
e821645d 12033 int last_sym = -1;
b0e28b39 12034 enum map_type type = MAP_ARM;
e821645d 12035
796d6298
TC		 12036 found = mapping_symbol_for_insn (pc, info, &type);
12037 last_sym = private_data->last_mapping_sym;
e821645d 12038
1fbaefec
PB		 12039 is_thumb = (private_data->last_type == MAP_THUMB);
12040 is_data = (private_data->last_type == MAP_DATA);
b34976b6 12041
e821645d
DJ		 12042 /* Look a little bit ahead to see if we should print out
12043 two or four bytes of data. If there's a symbol,
12044 mapping or otherwise, after two bytes then don't
12045 print more. */
12046 if (is_data)
12047 {
12048 size = 4 - (pc & 3);
12049 for (n = last_sym + 1; n < info->symtab_size; n++)
12050 {
12051 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 12052 if (addr > pc
12053 && (info->section == NULL
12054 || info->section == info->symtab[n]->section))
e821645d
DJ		 12055 {
12056 if (addr - pc < size)
12057 size = addr - pc;
12058 break;
12059 }
12060 }
12061 /* If the next symbol is after three bytes, we need to
12062 print only part of the data, so that we can use either
12063 .byte or .short. */
12064 if (size == 3)
12065 size = (pc & 1) ? 1 : 2;
12066 }
12067 }
12068
12069 if (info->symbols != NULL)
252b5132 12070 {
5876e06d
NC		 12071 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
12072 {
2f0ca46a 12073 coff_symbol_type * cs;
b34976b6 12074
5876e06d
NC		 12075 cs = coffsymbol (*info->symbols);
12076 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
12077 || cs->native->u.syment.n_sclass == C_THUMBSTAT
12078 || cs->native->u.syment.n_sclass == C_THUMBLABEL
12079 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
12080 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
12081 }
e821645d
DJ		 12082 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
12083 && !found)
5876e06d 12084 {
2087ad84
PB		 12085 /* If no mapping symbol has been found then fall back to the type
12086 of the function symbol. */
e821645d
DJ		 12087 elf_symbol_type * es;
12088 unsigned int type;
2087ad84 12089
e821645d
DJ		 12090 es = *(elf_symbol_type **)(info->symbols);
12091 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 12092
39d911fc
TP		 12093 is_thumb =
12094 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
12095 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
5876e06d 12096 }
e49d43ff
TG		 12097 else if (bfd_asymbol_flavour (*info->symbols)
12098 == bfd_target_mach_o_flavour)
12099 {
12100 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
12101
12102 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
12103 }
5876e06d 12104 }
b34976b6 12105
e821645d
DJ		 12106 if (force_thumb)
12107 is_thumb = TRUE;
12108
b8f9ee44
CL		 12109 if (is_data)
12110 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
12111 else
12112 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
12113
c19d1205 12114 info->bytes_per_line = 4;
252b5132 12115
1316c8b3
NC		 12116 /* PR 10263: Disassemble data if requested to do so by the user. */
12117 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 12118 {
12119 int i;
12120
1316c8b3 12121 /* Size was already set above. */
e821645d
DJ		 12122 info->bytes_per_chunk = size;
12123 printer = print_insn_data;
12124
fe56b6ce 12125 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 12126 given = 0;
12127 if (little)
12128 for (i = size - 1; i >= 0; i--)
12129 given = b[i] | (given << 8);
12130 else
12131 for (i = 0; i < (int) size; i++)
12132 given = b[i] | (given << 8);
12133 }
12134 else if (!is_thumb)
252b5132 12135 {
c19d1205
ZW		 12136 /* In ARM mode endianness is a straightforward issue: the instruction
12137 is four bytes long and is either ordered 0123 or 3210. */
12138 printer = print_insn_arm;
12139 info->bytes_per_chunk = 4;
4a5329c6 12140 size = 4;
c19d1205 12141
0313a2b8 12142 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 12143 if (little_code)
2480b6fa 12144 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | ((unsigned) b[3] << 24);
c19d1205 12145 else
2480b6fa 12146 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | ((unsigned) b[0] << 24);
252b5132 12147 }
58efb6c0 12148 else
252b5132 12149 {
c19d1205
ZW		 12150 /* In Thumb mode we have the additional wrinkle of two
12151 instruction lengths. Fortunately, the bits that determine
12152 the length of the current instruction are always to be found
12153 in the first two bytes. */
4a5329c6 12154 printer = print_insn_thumb16;
c19d1205 12155 info->bytes_per_chunk = 2;
4a5329c6
ZW		 12156 size = 2;
12157
fe56b6ce 12158 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 12159 if (little_code)
9a2ff3f5
AM		 12160 given = (b[0]) | (b[1] << 8);
12161 else
12162 given = (b[1]) | (b[0] << 8);
12163
c19d1205 12164 if (!status)
252b5132 12165 {
c19d1205
ZW		 12166 /* These bit patterns signal a four-byte Thumb
12167 instruction. */
12168 if ((given & 0xF800) == 0xF800
12169 || (given & 0xF800) == 0xF000
12170 || (given & 0xF800) == 0xE800)
252b5132 12171 {
0313a2b8 12172 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 12173 if (little_code)
c19d1205 12174 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 12175 else
c19d1205
ZW		 12176 given = (b[1]) | (b[0] << 8) | (given << 16);
12177
12178 printer = print_insn_thumb32;
4a5329c6 12179 size = 4;
252b5132 12180 }
252b5132 12181 }
c22aaad1
PB		 12182
12183 if (ifthen_address != pc)
0313a2b8 12184 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 12185
12186 if (ifthen_state)
12187 {
12188 if ((ifthen_state & 0xf) == 0x8)
12189 ifthen_next_state = 0;
12190 else
12191 ifthen_next_state = (ifthen_state & 0xe0)
12192 | ((ifthen_state & 0xf) << 1);
12193 }
252b5132 12194 }
b34976b6 12195
c19d1205
ZW		 12196 if (status)
12197 {
12198 info->memory_error_func (status, pc, info);
12199 return -1;
12200 }
6a56ec7e
NC		 12201 if (info->flags & INSN_HAS_RELOC)
12202 /* If the instruction has a reloc associated with it, then
12203 the offset field in the instruction will actually be the
12204 addend for the reloc. (We are using REL type relocs).
12205 In such cases, we can ignore the pc when computing
12206 addresses, since the addend is not currently pc-relative. */
12207 pc = 0;
b34976b6 12208
4a5329c6 12209 printer (pc, info, given);
c22aaad1
PB		 12210
12211 if (is_thumb)
12212 {
12213 ifthen_state = ifthen_next_state;
12214 ifthen_address += size;
12215 }
4a5329c6 12216 return size;
252b5132
RH		 12217}
12218
12219int
4a5329c6 12220print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 12221{
bd2e2557
SS		 12222 /* Detect BE8-ness and record it in the disassembler info. */
12223 if (info->flavour == bfd_target_elf_flavour
12224 && info->section != NULL
12225 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
12226 info->endian_code = BFD_ENDIAN_LITTLE;
12227
b34976b6 12228 return print_insn (pc, info, FALSE);
58efb6c0 12229}
01c7f630 12230
58efb6c0 12231int
4a5329c6 12232print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 12233{
b34976b6 12234 return print_insn (pc, info, TRUE);
58efb6c0 12235}
252b5132 12236
471b9d15 12237const disasm_options_and_args_t *
65b48a81
PB		 12238disassembler_options_arm (void)
12239{
471b9d15 12240 static disasm_options_and_args_t *opts_and_args;
65b48a81 12241
471b9d15 12242 if (opts_and_args == NULL)
65b48a81 12243 {
471b9d15 12244 disasm_options_t *opts;
65b48a81 12245 unsigned int i;
471b9d15
MR		 12246
12247 opts_and_args = XNEW (disasm_options_and_args_t);
12248 opts_and_args->args = NULL;
12249
12250 opts = &opts_and_args->options;
65b48a81
PB		 12251 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
12252 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
471b9d15 12253 opts->arg = NULL;
65b48a81
PB		 12254 for (i = 0; i < NUM_ARM_OPTIONS; i++)
12255 {
12256 opts->name[i] = regnames[i].name;
12257 if (regnames[i].description != NULL)
12258 opts->description[i] = _(regnames[i].description);
12259 else
12260 opts->description[i] = NULL;
12261 }
12262 /* The array we return must be NULL terminated. */
12263 opts->name[i] = NULL;
12264 opts->description[i] = NULL;
12265 }
12266
471b9d15 12267 return opts_and_args;
65b48a81
PB		 12268}
12269
58efb6c0 12270void
4a5329c6 12271print_arm_disassembler_options (FILE *stream)
58efb6c0 12272{
65b48a81 12273 unsigned int i, max_len = 0;
58efb6c0
NC		 12274 fprintf (stream, _("\n\
12275The following ARM specific disassembler options are supported for use with\n\
12276the -M switch:\n"));
b34976b6 12277
65b48a81
PB		 12278 for (i = 0; i < NUM_ARM_OPTIONS; i++)
12279 {
12280 unsigned int len = strlen (regnames[i].name);
12281 if (max_len < len)
12282 max_len = len;
12283 }
58efb6c0 12284
65b48a81
PB		 12285 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
12286 fprintf (stream, " %s%*c %s\n",
12287 regnames[i].name,
12288 (int)(max_len - strlen (regnames[i].name)), ' ',
12289 _(regnames[i].description));
252b5132 12290}
GDB Binutils - Deliverables
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