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sim: profile: disconnect from watchpoint core
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
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252b5132 1/* Instruction printing code for the ARM
b90efa5b 2 Copyright (C) 1994-2015 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
2fbad815 24
252b5132 25#include "dis-asm.h"
2fbad815 26#include "opcode/arm.h"
252b5132 27#include "opintl.h"
31e0f3cd 28#include "safe-ctype.h"
0dbde4cf 29#include "floatformat.h"
252b5132 30
baf0cc5e 31/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 32#include "coff/internal.h"
33#include "libcoff.h"
252b5132
RH		 34#include "elf-bfd.h"
35#include "elf/internal.h"
36#include "elf/arm.h"
37
6b5d3a4d 38/* FIXME: Belongs in global header. */
01c7f630 39#ifndef strneq
58efb6c0
NC		 40#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
41#endif
42
43#ifndef NUM_ELEM
44#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
01c7f630
NC		 45#endif
46
1fbaefec
PB		 47/* Cached mapping symbol state. */
48enum map_type
49{
50 MAP_ARM,
51 MAP_THUMB,
52 MAP_DATA
53};
54
b0e28b39
DJ		 55struct arm_private_data
56{
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features;
59
60 /* Whether any mapping symbols are present in the provided symbol
61 table. -1 if we do not know yet, otherwise 0 or 1. */
62 int has_mapping_symbols;
1fbaefec
PB		 63
64 /* Track the last type (although this doesn't seem to be useful) */
65 enum map_type last_type;
66
67 /* Tracking symbol table information */
68 int last_mapping_sym;
69 bfd_vma last_mapping_addr;
b0e28b39
DJ		 70};
71
6b5d3a4d
ZW		 72struct opcode32
73{
74 unsigned long arch; /* Architecture defining this insn. */
fe56b6ce
NC		 75 unsigned long value; /* If arch == 0 then value is a sentinel. */
76 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 77 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 78};
79
80struct opcode16
81{
82 unsigned long arch; /* Architecture defining this insn. */
aefd8a40 83 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 84 const char *assembler; /* How to disassemble this insn. */
85};
b7693d02 86
8f06b2d8 87/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 88
2fbad815 89 %% %
4a5329c6 90
c22aaad1 91 %c print condition code (always bits 28-31 in ARM mode)
37b37b2d 92 %q print shifter argument
e2efe87d
MGD		 93 %u print condition code (unconditional in ARM mode,
94 UNPREDICTABLE if not AL in Thumb)
4a5329c6 95 %A print address for ldc/stc/ldf/stf instruction
16980d0b 96 %B print vstm/vldm register list
4a5329c6 97 %I print cirrus signed shift immediate: bits 0..3|4..6
4a5329c6
ZW		 98 %F print the COUNT field of a LFM/SFM instruction.
99 %P print floating point precision in arithmetic insn
100 %Q print floating point precision in ldf/stf insn
101 %R print floating point rounding mode
102
33399f07 103 %<bitfield>c print as a condition code (for vsel)
4a5329c6 104 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 105 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
106 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 107 %<bitfield>d print the bitfield in decimal
16980d0b 108 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 109 %<bitfield>x print the bitfield in hex
110 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 111 %<bitfield>f print a floating point constant if >7 else a
112 floating point register
4a5329c6
ZW		 113 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
114 %<bitfield>g print as an iWMMXt 64-bit register
115 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 116 %<bitfield>D print as a NEON D register
117 %<bitfield>Q print as a NEON Q register
4a5329c6 118
16980d0b 119 %y<code> print a single precision VFP reg.
2fbad815 120 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 121 %z<code> print a double precision VFP reg
2fbad815 122 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 123
16980d0b
JB		 124 %<bitfield>'c print specified char iff bitfield is all ones
125 %<bitfield>`c print specified char iff bitfield is all zeroes
126 %<bitfield>?ab... select from array of values in big endian order
127
2fbad815 128 %L print as an iWMMXt N/M width field.
4a5329c6 129 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 130 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 131 versions.
132 %i print 5-bit immediate in bits 8,3..0
133 (print "32" when 0)
fe56b6ce 134 %r print register offset address for wldt/wstr instruction. */
2fbad815 135
21d799b5 136enum opcode_sentinel_enum
05413229
NC		 137{
138 SENTINEL_IWMMXT_START = 1,
139 SENTINEL_IWMMXT_END,
140 SENTINEL_GENERIC_START
141} opcode_sentinels;
142
aefd8a40 143#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
c1e26897 144#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 145
8f06b2d8 146/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 147
8f06b2d8 148static const struct opcode32 coprocessor_opcodes[] =
2fbad815 149{
2fbad815
RE		 150 /* XScale instructions. */
151 {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"},
152 {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"},
153 {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
154 {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
155 {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 156
2fbad815 157 /* Intel Wireless MMX technology instructions. */
05413229 158 { 0, SENTINEL_IWMMXT_START, 0, "" },
2fbad815
RE		 159 {ARM_CEXT_IWMMXT, 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
160 {ARM_CEXT_XSCALE, 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
161 {ARM_CEXT_XSCALE, 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
162 {ARM_CEXT_XSCALE, 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
163 {ARM_CEXT_XSCALE, 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
164 {ARM_CEXT_XSCALE, 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
165 {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
166 {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
167 {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
168 {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
169 {ARM_CEXT_XSCALE, 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
170 {ARM_CEXT_XSCALE, 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
171 {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
172 {ARM_CEXT_XSCALE, 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
1103f72c 173 {ARM_CEXT_XSCALE, 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
2d447fca 174 {ARM_CEXT_XSCALE, 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
2fbad815
RE		 175 {ARM_CEXT_XSCALE, 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
176 {ARM_CEXT_XSCALE, 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
1103f72c 177 {ARM_CEXT_XSCALE, 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
2d447fca 178 {ARM_CEXT_XSCALE, 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
2fbad815
RE		 179 {ARM_CEXT_XSCALE, 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
180 {ARM_CEXT_XSCALE, 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
181 {ARM_CEXT_XSCALE, 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
182 {ARM_CEXT_XSCALE, 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
2d447fca 183 {ARM_CEXT_XSCALE, 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
2fbad815
RE		 184 {ARM_CEXT_XSCALE, 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
185 {ARM_CEXT_XSCALE, 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
2d447fca 186 {ARM_CEXT_XSCALE, 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
2fbad815
RE		 187 {ARM_CEXT_XSCALE, 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
188 {ARM_CEXT_XSCALE, 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
189 {ARM_CEXT_XSCALE, 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
2d447fca
JM		 190 {ARM_CEXT_XSCALE, 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
191 {ARM_CEXT_XSCALE, 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
2fbad815 192 {ARM_CEXT_XSCALE, 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
2d447fca
JM		 193 {ARM_CEXT_XSCALE, 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
194 {ARM_CEXT_XSCALE, 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
195 {ARM_CEXT_XSCALE, 0x0e800120, 0x0f800ff0, "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
2fbad815 196 {ARM_CEXT_XSCALE, 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
2d447fca
JM		 197 {ARM_CEXT_XSCALE, 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
198 {ARM_CEXT_XSCALE, 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
199 {ARM_CEXT_XSCALE, 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
200 {ARM_CEXT_XSCALE, 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
201 {ARM_CEXT_XSCALE, 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
202 {ARM_CEXT_XSCALE, 0x0e8000a0, 0x0f800ff0, "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
203 {ARM_CEXT_XSCALE, 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
204 {ARM_CEXT_XSCALE, 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
2fbad815
RE		 205 {ARM_CEXT_XSCALE, 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
206 {ARM_CEXT_XSCALE, 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
2d447fca
JM		 207 {ARM_CEXT_XSCALE, 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
208 {ARM_CEXT_XSCALE, 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
209 {ARM_CEXT_XSCALE, 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
2fbad815
RE		 210 {ARM_CEXT_XSCALE, 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
211 {ARM_CEXT_XSCALE, 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
2d447fca 212 {ARM_CEXT_XSCALE, 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
2fbad815
RE		 213 {ARM_CEXT_XSCALE, 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
214 {ARM_CEXT_XSCALE, 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
2d447fca 215 {ARM_CEXT_XSCALE, 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
2fbad815
RE		 216 {ARM_CEXT_XSCALE, 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
217 {ARM_CEXT_XSCALE, 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
2d447fca 218 {ARM_CEXT_XSCALE, 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
2fbad815
RE		 219 {ARM_CEXT_XSCALE, 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
220 {ARM_CEXT_XSCALE, 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
2d447fca 221 {ARM_CEXT_XSCALE, 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
2fbad815
RE		 222 {ARM_CEXT_XSCALE, 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
223 {ARM_CEXT_XSCALE, 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
224 {ARM_CEXT_XSCALE, 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
2d447fca
JM		 225 {ARM_CEXT_XSCALE, 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
226 {ARM_CEXT_XSCALE, 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
227 {ARM_CEXT_XSCALE, 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
228 {ARM_CEXT_XSCALE, 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
229 {ARM_CEXT_XSCALE, 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
2fbad815
RE		 230 {ARM_CEXT_XSCALE, 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
231 {ARM_CEXT_XSCALE, 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
232 {ARM_CEXT_XSCALE, 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
233 {ARM_CEXT_XSCALE, 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
05413229 234 { 0, SENTINEL_IWMMXT_END, 0, "" },
2fbad815 235
fe56b6ce 236 /* Floating point coprocessor (FPA) instructions. */
8f06b2d8
PB		 237 {FPU_FPA_EXT_V1, 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
238 {FPU_FPA_EXT_V1, 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
239 {FPU_FPA_EXT_V1, 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
240 {FPU_FPA_EXT_V1, 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
241 {FPU_FPA_EXT_V1, 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
242 {FPU_FPA_EXT_V1, 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
243 {FPU_FPA_EXT_V1, 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
244 {FPU_FPA_EXT_V1, 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
245 {FPU_FPA_EXT_V1, 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
246 {FPU_FPA_EXT_V1, 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
247 {FPU_FPA_EXT_V1, 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
248 {FPU_FPA_EXT_V1, 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
249 {FPU_FPA_EXT_V1, 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
250 {FPU_FPA_EXT_V1, 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
251 {FPU_FPA_EXT_V1, 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
252 {FPU_FPA_EXT_V1, 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
253 {FPU_FPA_EXT_V1, 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
254 {FPU_FPA_EXT_V1, 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
255 {FPU_FPA_EXT_V1, 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
256 {FPU_FPA_EXT_V1, 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
257 {FPU_FPA_EXT_V1, 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
258 {FPU_FPA_EXT_V1, 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
259 {FPU_FPA_EXT_V1, 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
260 {FPU_FPA_EXT_V1, 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
261 {FPU_FPA_EXT_V1, 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
262 {FPU_FPA_EXT_V1, 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
263 {FPU_FPA_EXT_V1, 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
264 {FPU_FPA_EXT_V1, 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
265 {FPU_FPA_EXT_V1, 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
266 {FPU_FPA_EXT_V1, 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
267 {FPU_FPA_EXT_V1, 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
268 {FPU_FPA_EXT_V1, 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
269 {FPU_FPA_EXT_V1, 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
270 {FPU_FPA_EXT_V1, 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
271 {FPU_FPA_EXT_V1, 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
272 {FPU_FPA_EXT_V1, 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
273 {FPU_FPA_EXT_V1, 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
274 {FPU_FPA_EXT_V1, 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
275 {FPU_FPA_EXT_V1, 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
276 {FPU_FPA_EXT_V1, 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
277 {FPU_FPA_EXT_V1, 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
79862e45
DJ		 278 {FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
279 {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 280
fe56b6ce 281 /* Register load/store. */
7df76b80
RE		 282 {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
283 {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
284 {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
285 {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
286 {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
287 {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
79862e45
DJ		 288 {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
289 {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
7df76b80
RE		 290 {FPU_VFP_EXT_V1xD, 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
291 {FPU_VFP_EXT_V1xD, 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
292 {FPU_VFP_EXT_V1xD, 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
293 {FPU_VFP_EXT_V1xD, 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
294 {FPU_VFP_EXT_V1xD, 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
295 {FPU_VFP_EXT_V1xD, 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
296 {FPU_VFP_EXT_V1xD, 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
297 {FPU_VFP_EXT_V1xD, 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
298
299 {FPU_VFP_EXT_V1xD, 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
300 {FPU_VFP_EXT_V1xD, 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
301 {FPU_VFP_EXT_V1xD, 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
302 {FPU_VFP_EXT_V1xD, 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 303
fe56b6ce 304 /* Data transfer between ARM and NEON registers. */
16980d0b
JB		 305 {FPU_NEON_EXT_V1, 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
306 {FPU_NEON_EXT_V1, 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
307 {FPU_NEON_EXT_V1, 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
308 {FPU_NEON_EXT_V1, 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
309 {FPU_NEON_EXT_V1, 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
310 {FPU_NEON_EXT_V1, 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
311 {FPU_NEON_EXT_V1, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
312 {FPU_NEON_EXT_V1, 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
313 {FPU_NEON_EXT_V1, 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
314 {FPU_NEON_EXT_V1, 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
315 {FPU_NEON_EXT_V1, 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
316 {FPU_NEON_EXT_V1, 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
317 {FPU_NEON_EXT_V1, 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
318 {FPU_NEON_EXT_V1, 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 319 /* Half-precision conversion instructions. */
c70a8987
MGD		 320 {FPU_VFP_EXT_ARMV8, 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
321 {FPU_VFP_EXT_ARMV8, 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
62f3b8c8
PB		 322 {FPU_VFP_EXT_FP16, 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
323 {FPU_VFP_EXT_FP16, 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 324
fe56b6ce 325 /* Floating point coprocessor (VFP) instructions. */
7df76b80
RE		 326 {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
327 {FPU_VFP_EXT_V1xD, 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
328 {FPU_VFP_EXT_V1xD, 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
329 {FPU_VFP_EXT_V1xD, 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
330 {FPU_VFP_EXT_V1xD, 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
331 {FPU_VFP_EXT_V1xD, 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
332 {FPU_VFP_EXT_V1xD, 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
333 {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
334 {FPU_VFP_EXT_V1xD, 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
335 {FPU_VFP_EXT_V1xD, 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
336 {FPU_VFP_EXT_V1xD, 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
337 {FPU_VFP_EXT_V1xD, 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
338 {FPU_VFP_EXT_V1xD, 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
339 {FPU_VFP_EXT_V1xD, 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
340 {FPU_VFP_EXT_V1xD, 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
341 {FPU_VFP_EXT_V1, 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
342 {FPU_VFP_EXT_V1, 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
343 {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
344 {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
345 {FPU_VFP_EXT_V1xD, 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
346 {FPU_VFP_EXT_V1xD, 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
347 {FPU_VFP_EXT_V1xD, 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
348 {FPU_VFP_EXT_V1, 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
349 {FPU_VFP_EXT_V1xD, 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
350 {FPU_VFP_EXT_V1xD, 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
351 {FPU_VFP_EXT_V1, 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
352 {FPU_VFP_EXT_V1, 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
353 {FPU_VFP_EXT_V1xD, 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
354 {FPU_VFP_EXT_V1xD, 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
355 {FPU_VFP_EXT_V1, 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
356 {FPU_VFP_EXT_V1, 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
357 {FPU_VFP_EXT_V1, 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
358 {FPU_VFP_EXT_V1, 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
359 {FPU_VFP_EXT_V1xD, 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
360 {FPU_VFP_EXT_V1, 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
361 {FPU_VFP_EXT_V1xD, 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
362 {FPU_VFP_EXT_V1, 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
62f3b8c8 363 {FPU_VFP_EXT_V3xD, 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
7df76b80
RE		 364 {FPU_VFP_EXT_V3, 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
365 {FPU_VFP_EXT_V1xD, 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
366 {FPU_VFP_EXT_V1, 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
62f3b8c8 367 {FPU_VFP_EXT_V3xD, 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
7df76b80
RE		 368 {FPU_VFP_EXT_V3, 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
369 {FPU_VFP_EXT_V1, 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
62f3b8c8 370 {FPU_VFP_EXT_V3xD, 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19d"},
7df76b80
RE		 371 {FPU_VFP_EXT_V3, 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19d"},
372 {FPU_VFP_EXT_V2, 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
373 {FPU_VFP_EXT_V2, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
374 {FPU_VFP_EXT_V2, 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
375 {FPU_VFP_EXT_V1xD, 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
376 {FPU_VFP_EXT_V1xD, 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
377 {FPU_VFP_EXT_V1, 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
378 {FPU_VFP_EXT_V1, 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
379 {FPU_VFP_EXT_V1xD, 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
380 {FPU_VFP_EXT_V1xD, 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
381 {FPU_VFP_EXT_V1, 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
382 {FPU_VFP_EXT_V1, 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
383 {FPU_VFP_EXT_V1xD, 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
384 {FPU_VFP_EXT_V1xD, 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
385 {FPU_VFP_EXT_V1, 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
386 {FPU_VFP_EXT_V1, 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
387 {FPU_VFP_EXT_V1xD, 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
388 {FPU_VFP_EXT_V1xD, 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
389 {FPU_VFP_EXT_V1, 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
390 {FPU_VFP_EXT_V1, 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
391 {FPU_VFP_EXT_V1xD, 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
392 {FPU_VFP_EXT_V1, 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 393
394 /* Cirrus coprocessor instructions. */
395 {ARM_CEXT_MAVERICK, 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
396 {ARM_CEXT_MAVERICK, 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
397 {ARM_CEXT_MAVERICK, 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
398 {ARM_CEXT_MAVERICK, 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
399 {ARM_CEXT_MAVERICK, 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
400 {ARM_CEXT_MAVERICK, 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
401 {ARM_CEXT_MAVERICK, 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
402 {ARM_CEXT_MAVERICK, 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
403 {ARM_CEXT_MAVERICK, 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
404 {ARM_CEXT_MAVERICK, 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
405 {ARM_CEXT_MAVERICK, 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
406 {ARM_CEXT_MAVERICK, 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
407 {ARM_CEXT_MAVERICK, 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
408 {ARM_CEXT_MAVERICK, 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
409 {ARM_CEXT_MAVERICK, 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
410 {ARM_CEXT_MAVERICK, 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
411 {ARM_CEXT_MAVERICK, 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
412 {ARM_CEXT_MAVERICK, 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
413 {ARM_CEXT_MAVERICK, 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
414 {ARM_CEXT_MAVERICK, 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
415 {ARM_CEXT_MAVERICK, 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
416 {ARM_CEXT_MAVERICK, 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
417 {ARM_CEXT_MAVERICK, 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
418 {ARM_CEXT_MAVERICK, 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
419 {ARM_CEXT_MAVERICK, 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
420 {ARM_CEXT_MAVERICK, 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
421 {ARM_CEXT_MAVERICK, 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
422 {ARM_CEXT_MAVERICK, 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
423 {ARM_CEXT_MAVERICK, 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
424 {ARM_CEXT_MAVERICK, 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
425 {ARM_CEXT_MAVERICK, 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
426 {ARM_CEXT_MAVERICK, 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
427 {ARM_CEXT_MAVERICK, 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
428 {ARM_CEXT_MAVERICK, 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
429 {ARM_CEXT_MAVERICK, 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
430 {ARM_CEXT_MAVERICK, 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
431 {ARM_CEXT_MAVERICK, 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
432 {ARM_CEXT_MAVERICK, 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
433 {ARM_CEXT_MAVERICK, 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
434 {ARM_CEXT_MAVERICK, 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
435 {ARM_CEXT_MAVERICK, 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
436 {ARM_CEXT_MAVERICK, 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
437 {ARM_CEXT_MAVERICK, 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
438 {ARM_CEXT_MAVERICK, 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
439 {ARM_CEXT_MAVERICK, 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
440 {ARM_CEXT_MAVERICK, 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
441 {ARM_CEXT_MAVERICK, 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
442 {ARM_CEXT_MAVERICK, 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
443 {ARM_CEXT_MAVERICK, 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
444 {ARM_CEXT_MAVERICK, 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
445 {ARM_CEXT_MAVERICK, 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
446 {ARM_CEXT_MAVERICK, 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
19590ef7
RE		 447 {ARM_CEXT_MAVERICK, 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
448 {ARM_CEXT_MAVERICK, 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
2fbad815
RE		 449 {ARM_CEXT_MAVERICK, 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
450 {ARM_CEXT_MAVERICK, 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
451 {ARM_CEXT_MAVERICK, 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
452 {ARM_CEXT_MAVERICK, 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
453 {ARM_CEXT_MAVERICK, 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
454 {ARM_CEXT_MAVERICK, 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
455 {ARM_CEXT_MAVERICK, 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
456 {ARM_CEXT_MAVERICK, 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
457 {ARM_CEXT_MAVERICK, 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
458 {ARM_CEXT_MAVERICK, 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
459 {ARM_CEXT_MAVERICK, 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
460 {ARM_CEXT_MAVERICK, 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
461 {ARM_CEXT_MAVERICK, 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
462 {ARM_CEXT_MAVERICK, 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
463 {ARM_CEXT_MAVERICK, 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
464 {ARM_CEXT_MAVERICK, 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
465 {ARM_CEXT_MAVERICK, 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
466 {ARM_CEXT_MAVERICK, 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
467 {ARM_CEXT_MAVERICK, 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
468 {ARM_CEXT_MAVERICK, 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
469 {ARM_CEXT_MAVERICK, 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
470 {ARM_CEXT_MAVERICK, 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
471 {ARM_CEXT_MAVERICK, 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
472 {ARM_CEXT_MAVERICK, 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
473 {ARM_CEXT_MAVERICK, 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
474 {ARM_CEXT_MAVERICK, 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
19590ef7
RE		 475 {ARM_CEXT_MAVERICK, 0x0e000600, 0x0ff00f10, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
476 {ARM_CEXT_MAVERICK, 0x0e100600, 0x0ff00f10, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
477 {ARM_CEXT_MAVERICK, 0x0e200600, 0x0ff00f10, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
478 {ARM_CEXT_MAVERICK, 0x0e300600, 0x0ff00f10, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 479
62f3b8c8
PB		 480 /* VFP Fused multiply add instructions. */
481 {FPU_VFP_EXT_FMA, 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
482 {FPU_VFP_EXT_FMA, 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
483 {FPU_VFP_EXT_FMA, 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
484 {FPU_VFP_EXT_FMA, 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
485 {FPU_VFP_EXT_FMA, 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
486 {FPU_VFP_EXT_FMA, 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
487 {FPU_VFP_EXT_FMA, 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
488 {FPU_VFP_EXT_FMA, 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
489
33399f07
MGD		 490 /* FP v5. */
491 {FPU_VFP_EXT_ARMV8, 0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
492 {FPU_VFP_EXT_ARMV8, 0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
73924fbc
MGD		 493 {FPU_VFP_EXT_ARMV8, 0xfe800a00, 0xffb00f40, "vmaxnm%u.f32\t%y1, %y2, %y0"},
494 {FPU_VFP_EXT_ARMV8, 0xfe800b00, 0xffb00f40, "vmaxnm%u.f64\t%z1, %z2, %z0"},
495 {FPU_VFP_EXT_ARMV8, 0xfe800a40, 0xffb00f40, "vminnm%u.f32\t%y1, %y2, %y0"},
496 {FPU_VFP_EXT_ARMV8, 0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"},
7e8e6784
MGD		 497 {FPU_VFP_EXT_ARMV8, 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
498 {FPU_VFP_EXT_ARMV8, 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
f8ece37f
RE		 499 {FPU_VFP_EXT_ARMV8, 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
500 {FPU_VFP_EXT_ARMV8, 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
501 {FPU_VFP_EXT_ARMV8, 0xfeb80a40, 0xffbc0f50, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
502 {FPU_VFP_EXT_ARMV8, 0xfeb80b40, 0xffbc0f50, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 503
05413229
NC		 504 /* Generic coprocessor instructions. */
505 { 0, SENTINEL_GENERIC_START, 0, "" },
ff4a8d2b
NC		 506 {ARM_EXT_V5E, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
507 {ARM_EXT_V5E, 0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
2fbad815 508 {ARM_EXT_V2, 0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
db472d6f 509 {ARM_EXT_V2, 0x0e10f010, 0x0f10f010, "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
2fbad815 510 {ARM_EXT_V2, 0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
ff4a8d2b 511 {ARM_EXT_V2, 0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
37b37b2d
RE		 512 {ARM_EXT_V2, 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
513 {ARM_EXT_V2, 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
2fbad815 514
05413229 515 /* V6 coprocessor instructions. */
ff4a8d2b
NC		 516 {ARM_EXT_V6, 0xfc500000, 0xfff00000, "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
517 {ARM_EXT_V6, 0xfc400000, 0xfff00000, "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
8f06b2d8 518
05413229 519 /* V5 coprocessor instructions. */
c22aaad1
PB		 520 {ARM_EXT_V5, 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
521 {ARM_EXT_V5, 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
522 {ARM_EXT_V5, 0xfe000000, 0xff000010, "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
ff4a8d2b 523 {ARM_EXT_V5, 0xfe000010, 0xff100010, "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
c22aaad1 524 {ARM_EXT_V5, 0xfe100010, 0xff100010, "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
16980d0b 525
b13dd07a 526 {0, 0, 0, 0}
2fbad815
RE		 527};
528
16980d0b
JB		 529/* Neon opcode table: This does not encode the top byte -- that is
530 checked by the print_insn_neon routine, as it depends on whether we are
531 doing thumb32 or arm32 disassembly. */
532
533/* print_insn_neon recognizes the following format control codes:
534
535 %% %
536
c22aaad1 537 %c print condition code
e2efe87d
MGD		 538 %u print condition code (unconditional in ARM mode,
539 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 540 %A print v{st,ld}[1234] operands
541 %B print v{st,ld}[1234] any one operands
542 %C print v{st,ld}[1234] single->all operands
543 %D print scalar
544 %E print vmov, vmvn, vorr, vbic encoded constant
545 %F print vtbl,vtbx register list
546
547 %<bitfield>r print as an ARM register
548 %<bitfield>d print the bitfield in decimal
549 %<bitfield>e print the 2^N - bitfield in decimal
550 %<bitfield>D print as a NEON D register
551 %<bitfield>Q print as a NEON Q register
552 %<bitfield>R print as a NEON D or Q register
553 %<bitfield>Sn print byte scaled width limited by n
554 %<bitfield>Tn print short scaled width limited by n
555 %<bitfield>Un print long scaled width limited by n
556
557 %<bitfield>'c print specified char iff bitfield is all ones
558 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 559 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 560
561static const struct opcode32 neon_opcodes[] =
562{
fe56b6ce 563 /* Extract. */
c22aaad1
PB		 564 {FPU_NEON_EXT_V1, 0xf2b00840, 0xffb00850, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
565 {FPU_NEON_EXT_V1, 0xf2b00000, 0xffb00810, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 566
fe56b6ce 567 /* Move data element to all lanes. */
c22aaad1
PB		 568 {FPU_NEON_EXT_V1, 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
569 {FPU_NEON_EXT_V1, 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
570 {FPU_NEON_EXT_V1, 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 571
fe56b6ce 572 /* Table lookup. */
c22aaad1
PB		 573 {FPU_NEON_EXT_V1, 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
574 {FPU_NEON_EXT_V1, 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
16980d0b 575
8e79c3df 576 /* Half-precision conversions. */
62f3b8c8
PB		 577 {FPU_VFP_EXT_FP16, 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
578 {FPU_VFP_EXT_FP16, 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
579
580 /* NEON fused multiply add instructions. */
581 {FPU_NEON_EXT_FMA, 0xf2000c10, 0xffa00f10, "vfma%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
582 {FPU_NEON_EXT_FMA, 0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 583
fe56b6ce 584 /* Two registers, miscellaneous. */
f8ece37f 585 {FPU_NEON_EXT_ARMV8, 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
7e8e6784 586 {FPU_NEON_EXT_ARMV8, 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
91ff7894
MGD		 587 {FPU_CRYPTO_EXT_ARMV8, 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
588 {FPU_CRYPTO_EXT_ARMV8, 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
589 {FPU_CRYPTO_EXT_ARMV8, 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
590 {FPU_CRYPTO_EXT_ARMV8, 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
3c9017d2
MGD		 591 {FPU_CRYPTO_EXT_ARMV8, 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
592 {FPU_CRYPTO_EXT_ARMV8, 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
593 {FPU_CRYPTO_EXT_ARMV8, 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
c22aaad1
PB		 594 {FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
595 {FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
596 {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
597 {FPU_NEON_EXT_V1, 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
598 {FPU_NEON_EXT_V1, 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
599 {FPU_NEON_EXT_V1, 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
428e3f1f 600 {FPU_NEON_EXT_V1, 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
c22aaad1
PB		 601 {FPU_NEON_EXT_V1, 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
602 {FPU_NEON_EXT_V1, 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
603 {FPU_NEON_EXT_V1, 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
604 {FPU_NEON_EXT_V1, 0xf3b20300, 0xffb30fd0, "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
605 {FPU_NEON_EXT_V1, 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
606 {FPU_NEON_EXT_V1, 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
607 {FPU_NEON_EXT_V1, 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
608 {FPU_NEON_EXT_V1, 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
609 {FPU_NEON_EXT_V1, 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
610 {FPU_NEON_EXT_V1, 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
611 {FPU_NEON_EXT_V1, 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
612 {FPU_NEON_EXT_V1, 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
613 {FPU_NEON_EXT_V1, 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
614 {FPU_NEON_EXT_V1, 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
615 {FPU_NEON_EXT_V1, 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
616 {FPU_NEON_EXT_V1, 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
617 {FPU_NEON_EXT_V1, 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
618 {FPU_NEON_EXT_V1, 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
619 {FPU_NEON_EXT_V1, 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
620 {FPU_NEON_EXT_V1, 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
621 {FPU_NEON_EXT_V1, 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
622 {FPU_NEON_EXT_V1, 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
623 {FPU_NEON_EXT_V1, 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
624 {FPU_NEON_EXT_V1, 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
625 {FPU_NEON_EXT_V1, 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
626 {FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
16980d0b 627
fe56b6ce 628 /* Three registers of the same length. */
48adcd8e
MGD		 629 {FPU_CRYPTO_EXT_ARMV8, 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
630 {FPU_CRYPTO_EXT_ARMV8, 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
631 {FPU_CRYPTO_EXT_ARMV8, 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
632 {FPU_CRYPTO_EXT_ARMV8, 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
633 {FPU_CRYPTO_EXT_ARMV8, 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
634 {FPU_CRYPTO_EXT_ARMV8, 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
635 {FPU_CRYPTO_EXT_ARMV8, 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
73924fbc
MGD		 636 {FPU_NEON_EXT_ARMV8, 0xf3000f10, 0xffa00f10, "vmaxnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
637 {FPU_NEON_EXT_ARMV8, 0xf3200f10, 0xffa00f10, "vminnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
c22aaad1
PB		 638 {FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
639 {FPU_NEON_EXT_V1, 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
640 {FPU_NEON_EXT_V1, 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
641 {FPU_NEON_EXT_V1, 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
642 {FPU_NEON_EXT_V1, 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
643 {FPU_NEON_EXT_V1, 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
644 {FPU_NEON_EXT_V1, 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
645 {FPU_NEON_EXT_V1, 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
646 {FPU_NEON_EXT_V1, 0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
647 {FPU_NEON_EXT_V1, 0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
648 {FPU_NEON_EXT_V1, 0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
649 {FPU_NEON_EXT_V1, 0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
650 {FPU_NEON_EXT_V1, 0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
651 {FPU_NEON_EXT_V1, 0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
652 {FPU_NEON_EXT_V1, 0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
653 {FPU_NEON_EXT_V1, 0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
654 {FPU_NEON_EXT_V1, 0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
655 {FPU_NEON_EXT_V1, 0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
656 {FPU_NEON_EXT_V1, 0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
657 {FPU_NEON_EXT_V1, 0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
658 {FPU_NEON_EXT_V1, 0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
659 {FPU_NEON_EXT_V1, 0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
660 {FPU_NEON_EXT_V1, 0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
661 {FPU_NEON_EXT_V1, 0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
662 {FPU_NEON_EXT_V1, 0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
663 {FPU_NEON_EXT_V1, 0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
664 {FPU_NEON_EXT_V1, 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
665 {FPU_NEON_EXT_V1, 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
666 {FPU_NEON_EXT_V1, 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
667 {FPU_NEON_EXT_V1, 0xf2000b00, 0xff800f10, "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
668 {FPU_NEON_EXT_V1, 0xf2000b10, 0xff800f10, "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
669 {FPU_NEON_EXT_V1, 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
670 {FPU_NEON_EXT_V1, 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
671 {FPU_NEON_EXT_V1, 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
672 {FPU_NEON_EXT_V1, 0xf3000b00, 0xff800f10, "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
673 {FPU_NEON_EXT_V1, 0xf2000000, 0xfe800f10, "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
674 {FPU_NEON_EXT_V1, 0xf2000010, 0xfe800f10, "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
675 {FPU_NEON_EXT_V1, 0xf2000100, 0xfe800f10, "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
676 {FPU_NEON_EXT_V1, 0xf2000200, 0xfe800f10, "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
677 {FPU_NEON_EXT_V1, 0xf2000210, 0xfe800f10, "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
678 {FPU_NEON_EXT_V1, 0xf2000300, 0xfe800f10, "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
679 {FPU_NEON_EXT_V1, 0xf2000310, 0xfe800f10, "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
62ac925e
JB		 680 {FPU_NEON_EXT_V1, 0xf2000400, 0xfe800f10, "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
681 {FPU_NEON_EXT_V1, 0xf2000410, 0xfe800f10, "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
682 {FPU_NEON_EXT_V1, 0xf2000500, 0xfe800f10, "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
683 {FPU_NEON_EXT_V1, 0xf2000510, 0xfe800f10, "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
c22aaad1
PB		 684 {FPU_NEON_EXT_V1, 0xf2000600, 0xfe800f10, "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
685 {FPU_NEON_EXT_V1, 0xf2000610, 0xfe800f10, "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
686 {FPU_NEON_EXT_V1, 0xf2000700, 0xfe800f10, "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
687 {FPU_NEON_EXT_V1, 0xf2000710, 0xfe800f10, "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
688 {FPU_NEON_EXT_V1, 0xf2000910, 0xfe800f10, "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
689 {FPU_NEON_EXT_V1, 0xf2000a00, 0xfe800f10, "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
690 {FPU_NEON_EXT_V1, 0xf2000a10, 0xfe800f10, "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 691
fe56b6ce 692 /* One register and an immediate value. */
c22aaad1
PB		 693 {FPU_NEON_EXT_V1, 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
694 {FPU_NEON_EXT_V1, 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
695 {FPU_NEON_EXT_V1, 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
696 {FPU_NEON_EXT_V1, 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
697 {FPU_NEON_EXT_V1, 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
698 {FPU_NEON_EXT_V1, 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
699 {FPU_NEON_EXT_V1, 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
700 {FPU_NEON_EXT_V1, 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
701 {FPU_NEON_EXT_V1, 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
702 {FPU_NEON_EXT_V1, 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
703 {FPU_NEON_EXT_V1, 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
704 {FPU_NEON_EXT_V1, 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
705 {FPU_NEON_EXT_V1, 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 706
fe56b6ce 707 /* Two registers and a shift amount. */
c22aaad1
PB		 708 {FPU_NEON_EXT_V1, 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
709 {FPU_NEON_EXT_V1, 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
710 {FPU_NEON_EXT_V1, 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
711 {FPU_NEON_EXT_V1, 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
712 {FPU_NEON_EXT_V1, 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
713 {FPU_NEON_EXT_V1, 0xf2880950, 0xfeb80fd0, "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
85181173 714 {FPU_NEON_EXT_V1, 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
c22aaad1
PB		 715 {FPU_NEON_EXT_V1, 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
716 {FPU_NEON_EXT_V1, 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
717 {FPU_NEON_EXT_V1, 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
718 {FPU_NEON_EXT_V1, 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
719 {FPU_NEON_EXT_V1, 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
720 {FPU_NEON_EXT_V1, 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
721 {FPU_NEON_EXT_V1, 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
722 {FPU_NEON_EXT_V1, 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
723 {FPU_NEON_EXT_V1, 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
724 {FPU_NEON_EXT_V1, 0xf2900950, 0xfeb00fd0, "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
85181173 725 {FPU_NEON_EXT_V1, 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
c22aaad1
PB		 726 {FPU_NEON_EXT_V1, 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
727 {FPU_NEON_EXT_V1, 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
728 {FPU_NEON_EXT_V1, 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
729 {FPU_NEON_EXT_V1, 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
730 {FPU_NEON_EXT_V1, 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
731 {FPU_NEON_EXT_V1, 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
732 {FPU_NEON_EXT_V1, 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
733 {FPU_NEON_EXT_V1, 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
734 {FPU_NEON_EXT_V1, 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
735 {FPU_NEON_EXT_V1, 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
736 {FPU_NEON_EXT_V1, 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
85181173 737 {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
c22aaad1
PB		 738 {FPU_NEON_EXT_V1, 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
739 {FPU_NEON_EXT_V1, 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
740 {FPU_NEON_EXT_V1, 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
741 {FPU_NEON_EXT_V1, 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
742 {FPU_NEON_EXT_V1, 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
4ce8808b
RE		 743 {FPU_NEON_EXT_V1, 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
744 {FPU_NEON_EXT_V1, 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
745 {FPU_NEON_EXT_V1, 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
746 {FPU_NEON_EXT_V1, 0xf2a00950, 0xfea00fd0, "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
c22aaad1
PB		 747 {FPU_NEON_EXT_V1, 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
748 {FPU_NEON_EXT_V1, 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
749 {FPU_NEON_EXT_V1, 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
750 {FPU_NEON_EXT_V1, 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
751 {FPU_NEON_EXT_V1, 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
752 {FPU_NEON_EXT_V1, 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
753 {FPU_NEON_EXT_V1, 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
754 {FPU_NEON_EXT_V1, 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
755 {FPU_NEON_EXT_V1, 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
756 {FPU_NEON_EXT_V1, 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
757 {FPU_NEON_EXT_V1, 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
758 {FPU_NEON_EXT_V1, 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
759 {FPU_NEON_EXT_V1, 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
760 {FPU_NEON_EXT_V1, 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
761 {FPU_NEON_EXT_V1, 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
762 {FPU_NEON_EXT_V1, 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
763 {FPU_NEON_EXT_V1, 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
764 {FPU_NEON_EXT_V1, 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
765 {FPU_NEON_EXT_V1, 0xf2a00e10, 0xfea00e90, "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 766
fe56b6ce 767 /* Three registers of different lengths. */
4f51b4bd 768 {FPU_CRYPTO_EXT_ARMV8, 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
c22aaad1
PB		 769 {FPU_NEON_EXT_V1, 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
770 {FPU_NEON_EXT_V1, 0xf2800400, 0xff800f50, "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
771 {FPU_NEON_EXT_V1, 0xf2800600, 0xff800f50, "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
772 {FPU_NEON_EXT_V1, 0xf2800900, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
773 {FPU_NEON_EXT_V1, 0xf2800b00, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
774 {FPU_NEON_EXT_V1, 0xf2800d00, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
775 {FPU_NEON_EXT_V1, 0xf3800400, 0xff800f50, "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
776 {FPU_NEON_EXT_V1, 0xf3800600, 0xff800f50, "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
777 {FPU_NEON_EXT_V1, 0xf2800000, 0xfe800f50, "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
778 {FPU_NEON_EXT_V1, 0xf2800100, 0xfe800f50, "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
779 {FPU_NEON_EXT_V1, 0xf2800200, 0xfe800f50, "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
780 {FPU_NEON_EXT_V1, 0xf2800300, 0xfe800f50, "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
781 {FPU_NEON_EXT_V1, 0xf2800500, 0xfe800f50, "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
782 {FPU_NEON_EXT_V1, 0xf2800700, 0xfe800f50, "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
783 {FPU_NEON_EXT_V1, 0xf2800800, 0xfe800f50, "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
784 {FPU_NEON_EXT_V1, 0xf2800a00, 0xfe800f50, "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
785 {FPU_NEON_EXT_V1, 0xf2800c00, 0xfe800f50, "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 786
fe56b6ce 787 /* Two registers and a scalar. */
c22aaad1
PB		 788 {FPU_NEON_EXT_V1, 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
789 {FPU_NEON_EXT_V1, 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
790 {FPU_NEON_EXT_V1, 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
791 {FPU_NEON_EXT_V1, 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
792 {FPU_NEON_EXT_V1, 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
793 {FPU_NEON_EXT_V1, 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
794 {FPU_NEON_EXT_V1, 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
795 {FPU_NEON_EXT_V1, 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
796 {FPU_NEON_EXT_V1, 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
797 {FPU_NEON_EXT_V1, 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
798 {FPU_NEON_EXT_V1, 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
799 {FPU_NEON_EXT_V1, 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
800 {FPU_NEON_EXT_V1, 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
801 {FPU_NEON_EXT_V1, 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
802 {FPU_NEON_EXT_V1, 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
803 {FPU_NEON_EXT_V1, 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
804 {FPU_NEON_EXT_V1, 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
805 {FPU_NEON_EXT_V1, 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
806 {FPU_NEON_EXT_V1, 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
807 {FPU_NEON_EXT_V1, 0xf2800240, 0xfe800f50, "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
808 {FPU_NEON_EXT_V1, 0xf2800640, 0xfe800f50, "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
809 {FPU_NEON_EXT_V1, 0xf2800a40, 0xfe800f50, "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
16980d0b 810
fe56b6ce 811 /* Element and structure load/store. */
c22aaad1
PB		 812 {FPU_NEON_EXT_V1, 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
813 {FPU_NEON_EXT_V1, 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
814 {FPU_NEON_EXT_V1, 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
815 {FPU_NEON_EXT_V1, 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
816 {FPU_NEON_EXT_V1, 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
817 {FPU_NEON_EXT_V1, 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
818 {FPU_NEON_EXT_V1, 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
819 {FPU_NEON_EXT_V1, 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
820 {FPU_NEON_EXT_V1, 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
821 {FPU_NEON_EXT_V1, 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
822 {FPU_NEON_EXT_V1, 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
823 {FPU_NEON_EXT_V1, 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
824 {FPU_NEON_EXT_V1, 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
825 {FPU_NEON_EXT_V1, 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
826 {FPU_NEON_EXT_V1, 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
827 {FPU_NEON_EXT_V1, 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
828 {FPU_NEON_EXT_V1, 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
829 {FPU_NEON_EXT_V1, 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
830 {FPU_NEON_EXT_V1, 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
16980d0b
JB		 831
832 {0,0 ,0, 0}
833};
834
8f06b2d8
PB		 835/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
836 ordered: they must be searched linearly from the top to obtain a correct
837 match. */
838
839/* print_insn_arm recognizes the following format control codes:
840
841 %% %
842
843 %a print address for ldr/str instruction
844 %s print address for ldr/str halfword/signextend instruction
c1e26897 845 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 846 %b print branch destination
847 %c print condition code (always bits 28-31)
848 %m print register mask for ldm/stm instruction
849 %o print operand2 (immediate or register + shift)
850 %p print 'p' iff bits 12-15 are 15
851 %t print 't' iff bit 21 set and bit 24 clear
852 %B print arm BLX(1) destination
853 %C print the PSR sub type.
62b3e311
PB		 854 %U print barrier type.
855 %P print address for pli instruction.
8f06b2d8
PB		 856
857 %<bitfield>r print as an ARM register
9eb6c0f1 858 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 859 %<bitfield>R as %r but r15 is UNPREDICTABLE
860 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
861 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8
PB		 862 %<bitfield>d print the bitfield in decimal
863 %<bitfield>W print the bitfield plus one in decimal
864 %<bitfield>x print the bitfield in hex
865 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
16980d0b
JB		 866
867 %<bitfield>'c print specified char iff bitfield is all ones
868 %<bitfield>`c print specified char iff bitfield is all zeroes
869 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 870
8f06b2d8
PB		 871 %e print arm SMI operand (bits 0..7,8..19).
872 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 873 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
874 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 875
8f06b2d8
PB		 876static const struct opcode32 arm_opcodes[] =
877{
878 /* ARM instructions. */
fe56b6ce 879 {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
74db7efb
NC		 880 {ARM_EXT_V1, 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
881
8f06b2d8 882 {ARM_EXT_V4T | ARM_EXT_V5, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
ab8e2090
NC		 883 {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
884 {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
ff4a8d2b
NC		 885 {ARM_EXT_V2S, 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
886 {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
887 {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 888
53c4b28b
MGD		 889 /* V8 instructions. */
890 {ARM_EXT_V8, 0x0320f005, 0x0fffffff, "sevl"},
8884b720 891 {ARM_EXT_V8, 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
4b8c8c02
RE		 892 {ARM_EXT_V8, 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
893 {ARM_EXT_V8, 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
894 {ARM_EXT_V8, 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
895 {ARM_EXT_V8, 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
896 {ARM_EXT_V8, 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
897 {ARM_EXT_V8, 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
898 {ARM_EXT_V8, 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
899 {ARM_EXT_V8, 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
900 {ARM_EXT_V8, 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
901 {ARM_EXT_V8, 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
902 {ARM_EXT_V8, 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
903 {ARM_EXT_V8, 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
904 {ARM_EXT_V8, 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
905 {ARM_EXT_V8, 0x01f00c9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
dd5181d5
KT		 906 /* CRC32 instructions. */
907 {CRC_EXT_ARMV8, 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
908 {CRC_EXT_ARMV8, 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
909 {CRC_EXT_ARMV8, 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
910 {CRC_EXT_ARMV8, 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
911 {CRC_EXT_ARMV8, 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
912 {CRC_EXT_ARMV8, 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 913
90ec0d68
MGD		 914 /* Virtualization Extension instructions. */
915 {ARM_EXT_VIRT, 0x0160006e, 0x0fffffff, "eret%c"},
916 {ARM_EXT_VIRT, 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
917
eea54501
MGD		 918 /* Integer Divide Extension instructions. */
919 {ARM_EXT_ADIV, 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
920 {ARM_EXT_ADIV, 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
921
60e5ef9f
MGD		 922 /* MP Extension instructions. */
923 {ARM_EXT_MP, 0xf410f000, 0xfc70f000, "pldw\t%a"},
924
62b3e311
PB		 925 /* V7 instructions. */
926 {ARM_EXT_V7, 0xf450f000, 0xfd70f000, "pli\t%P"},
927 {ARM_EXT_V7, 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
e797f7e0
MGD		 928 {ARM_EXT_V8, 0xf57ff051, 0xfffffff3, "dmb\t%U"},
929 {ARM_EXT_V8, 0xf57ff041, 0xfffffff3, "dsb\t%U"},
62b3e311
PB		 930 {ARM_EXT_V7, 0xf57ff050, 0xfffffff0, "dmb\t%U"},
931 {ARM_EXT_V7, 0xf57ff040, 0xfffffff0, "dsb\t%U"},
932 {ARM_EXT_V7, 0xf57ff060, 0xfffffff0, "isb\t%U"},
933
c19d1205 934 /* ARM V6T2 instructions. */
ff4a8d2b
NC		 935 {ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
936 {ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
937 {ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
6fe6ded9
RE		 938 {ARM_EXT_V6T2, 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
939
aefd8a40 940 {ARM_EXT_V6T2, 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
ff4a8d2b 941 {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
aefd8a40 942
ff4a8d2b
NC		 943 {ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
944 {ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
945 {ARM_EXT_V6T2, 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
8f06b2d8 946 {ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 947
f4c65163
MGD		 948 /* ARM Security extension instructions. */
949 {ARM_EXT_SEC, 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 950
8f06b2d8
PB		 951 /* ARM V6K instructions. */
952 {ARM_EXT_V6K, 0xf57ff01f, 0xffffffff, "clrex"},
ff4a8d2b
NC		 953 {ARM_EXT_V6K, 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
954 {ARM_EXT_V6K, 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
955 {ARM_EXT_V6K, 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
956 {ARM_EXT_V6K, 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
957 {ARM_EXT_V6K, 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
958 {ARM_EXT_V6K, 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 959
8f06b2d8
PB		 960 /* ARM V6K NOP hints. */
961 {ARM_EXT_V6K, 0x0320f001, 0x0fffffff, "yield%c"},
962 {ARM_EXT_V6K, 0x0320f002, 0x0fffffff, "wfe%c"},
963 {ARM_EXT_V6K, 0x0320f003, 0x0fffffff, "wfi%c"},
964 {ARM_EXT_V6K, 0x0320f004, 0x0fffffff, "sev%c"},
965 {ARM_EXT_V6K, 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 966
fe56b6ce 967 /* ARM V6 instructions. */
a028a6f5
PB		 968 {ARM_EXT_V6, 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
969 {ARM_EXT_V6, 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
970 {ARM_EXT_V6, 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
971 {ARM_EXT_V6, 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
8f06b2d8 972 {ARM_EXT_V6, 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
ff4a8d2b
NC		 973 {ARM_EXT_V6, 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
974 {ARM_EXT_V6, 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
975 {ARM_EXT_V6, 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
976 {ARM_EXT_V6, 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
977 {ARM_EXT_V6, 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
978 {ARM_EXT_V6, 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
979 {ARM_EXT_V6, 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
c060226a 980 {ARM_EXT_V6, 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
ff4a8d2b
NC		 981 {ARM_EXT_V6, 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
982 {ARM_EXT_V6, 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
c060226a 983 {ARM_EXT_V6, 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
ff4a8d2b
NC		 984 {ARM_EXT_V6, 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
985 {ARM_EXT_V6, 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
c060226a 986 {ARM_EXT_V6, 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
ff4a8d2b
NC		 987 {ARM_EXT_V6, 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
988 {ARM_EXT_V6, 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
c060226a 989 {ARM_EXT_V6, 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
ff4a8d2b
NC		 990 {ARM_EXT_V6, 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
991 {ARM_EXT_V6, 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
c060226a 992 {ARM_EXT_V6, 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
ff4a8d2b
NC		 993 {ARM_EXT_V6, 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
994 {ARM_EXT_V6, 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
c060226a 995 {ARM_EXT_V6, 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
ff4a8d2b
NC		 996 {ARM_EXT_V6, 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
997 {ARM_EXT_V6, 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
c060226a 998 {ARM_EXT_V6, 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
ff4a8d2b
NC		 999 {ARM_EXT_V6, 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
1000 {ARM_EXT_V6, 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
c060226a 1001 {ARM_EXT_V6, 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
ff4a8d2b
NC		 1002 {ARM_EXT_V6, 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
1003 {ARM_EXT_V6, 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
c060226a 1004 {ARM_EXT_V6, 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
ff4a8d2b
NC		 1005 {ARM_EXT_V6, 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
1006 {ARM_EXT_V6, 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
c060226a 1007 {ARM_EXT_V6, 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
ff4a8d2b
NC		 1008 {ARM_EXT_V6, 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
1009 {ARM_EXT_V6, 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
c060226a 1010 {ARM_EXT_V6, 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
ff4a8d2b
NC		 1011 {ARM_EXT_V6, 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
1012 {ARM_EXT_V6, 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
c060226a 1013 {ARM_EXT_V6, 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
ff4a8d2b
NC		 1014 {ARM_EXT_V6, 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
1015 {ARM_EXT_V6, 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
1016 {ARM_EXT_V6, 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
92c8bd79 1017 {ARM_EXT_V6, 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
ff4a8d2b
NC		 1018 {ARM_EXT_V6, 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
1019 {ARM_EXT_V6, 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
1020 {ARM_EXT_V6, 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
1021 {ARM_EXT_V6, 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
1022 {ARM_EXT_V6, 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
1023 {ARM_EXT_V6, 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
1024 {ARM_EXT_V6, 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
1025 {ARM_EXT_V6, 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
1026 {ARM_EXT_V6, 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
1027 {ARM_EXT_V6, 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
1028 {ARM_EXT_V6, 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
1029 {ARM_EXT_V6, 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
1030 {ARM_EXT_V6, 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
1031 {ARM_EXT_V6, 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
1032 {ARM_EXT_V6, 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
1033 {ARM_EXT_V6, 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
1034 {ARM_EXT_V6, 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
1035 {ARM_EXT_V6, 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
1036 {ARM_EXT_V6, 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
1037 {ARM_EXT_V6, 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
1038 {ARM_EXT_V6, 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
1039 {ARM_EXT_V6, 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
1040 {ARM_EXT_V6, 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
1041 {ARM_EXT_V6, 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
1042 {ARM_EXT_V6, 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
1043 {ARM_EXT_V6, 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1044 {ARM_EXT_V6, 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1045 {ARM_EXT_V6, 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1046 {ARM_EXT_V6, 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
1047 {ARM_EXT_V6, 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1048 {ARM_EXT_V6, 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1049 {ARM_EXT_V6, 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1050 {ARM_EXT_V6, 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
1051 {ARM_EXT_V6, 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1052 {ARM_EXT_V6, 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1053 {ARM_EXT_V6, 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1054 {ARM_EXT_V6, 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
1055 {ARM_EXT_V6, 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1056 {ARM_EXT_V6, 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1057 {ARM_EXT_V6, 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1058 {ARM_EXT_V6, 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
1059 {ARM_EXT_V6, 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1060 {ARM_EXT_V6, 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1061 {ARM_EXT_V6, 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
1062 {ARM_EXT_V6, 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
1063 {ARM_EXT_V6, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1064 {ARM_EXT_V6, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1065 {ARM_EXT_V6, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1066 {ARM_EXT_V6, 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
8f06b2d8 1067 {ARM_EXT_V6, 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
ff4a8d2b
NC		 1068 {ARM_EXT_V6, 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
1069 {ARM_EXT_V6, 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
1070 {ARM_EXT_V6, 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1071 {ARM_EXT_V6, 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1072 {ARM_EXT_V6, 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1073 {ARM_EXT_V6, 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1074 {ARM_EXT_V6, 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
1075 {ARM_EXT_V6, 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1076 {ARM_EXT_V6, 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
b6702015 1077 {ARM_EXT_V6, 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
ff4a8d2b
NC		 1078 {ARM_EXT_V6, 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
1079 {ARM_EXT_V6, 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
1080 {ARM_EXT_V6, 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
8f06b2d8 1081 {ARM_EXT_V6, 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
ff4a8d2b
NC		 1082 {ARM_EXT_V6, 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
1083 {ARM_EXT_V6, 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
1084 {ARM_EXT_V6, 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
1085 {ARM_EXT_V6, 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1086 {ARM_EXT_V6, 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
1087 {ARM_EXT_V6, 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
1088 {ARM_EXT_V6, 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
1089 {ARM_EXT_V6, 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 1090
8f06b2d8 1091 /* V5J instruction. */
ff4a8d2b 1092 {ARM_EXT_V5J, 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 1093
8f06b2d8
PB		 1094 /* V5 Instructions. */
1095 {ARM_EXT_V5, 0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
1096 {ARM_EXT_V5, 0xfa000000, 0xfe000000, "blx\t%B"},
ff4a8d2b 1097 {ARM_EXT_V5, 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
ab8e2090 1098 {ARM_EXT_V5, 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
c19d1205 1099
8f06b2d8 1100 /* V5E "El Segundo" Instructions. */
37b37b2d
RE		 1101 {ARM_EXT_V5E, 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
1102 {ARM_EXT_V5E, 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
8f06b2d8 1103 {ARM_EXT_V5E, 0xf450f000, 0xfc70f000, "pld\t%a"},
ff4a8d2b
NC		 1104 {ARM_EXT_V5ExP, 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1105 {ARM_EXT_V5ExP, 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1106 {ARM_EXT_V5ExP, 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1107 {ARM_EXT_V5ExP, 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
c19d1205 1108
ff4a8d2b
NC		 1109 {ARM_EXT_V5ExP, 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1110 {ARM_EXT_V5ExP, 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
c19d1205 1111
ff4a8d2b
NC		 1112 {ARM_EXT_V5ExP, 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1113 {ARM_EXT_V5ExP, 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1114 {ARM_EXT_V5ExP, 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1115 {ARM_EXT_V5ExP, 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 1116
ff4a8d2b
NC		 1117 {ARM_EXT_V5ExP, 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
1118 {ARM_EXT_V5ExP, 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
1119 {ARM_EXT_V5ExP, 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
1120 {ARM_EXT_V5ExP, 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
4a5329c6 1121
ff4a8d2b
NC		 1122 {ARM_EXT_V5ExP, 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
1123 {ARM_EXT_V5ExP, 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
4a5329c6 1124
ff4a8d2b
NC		 1125 {ARM_EXT_V5ExP, 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
1126 {ARM_EXT_V5ExP, 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
1127 {ARM_EXT_V5ExP, 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
1128 {ARM_EXT_V5ExP, 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 1129
8f06b2d8 1130 /* ARM Instructions. */
05413229 1131 {ARM_EXT_V1, 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
ab8e2090
NC		 1132
1133 {ARM_EXT_V1, 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
1134 {ARM_EXT_V1, 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
1135 {ARM_EXT_V1, 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
1136 {ARM_EXT_V1, 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
1137 {ARM_EXT_V1, 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
1138 {ARM_EXT_V1, 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
1139
1140 {ARM_EXT_V1, 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
1141 {ARM_EXT_V1, 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
1142 {ARM_EXT_V1, 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
1143 {ARM_EXT_V1, 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
aefd8a40
NC		 1144
1145 {ARM_EXT_V1, 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
ab8e2090 1146 {ARM_EXT_V1, 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
aefd8a40 1147 {ARM_EXT_V1, 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
ab8e2090 1148 {ARM_EXT_V1, 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
74bdfecf
NC		 1149
1150 {ARM_EXT_V1, 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
1151 {ARM_EXT_V1, 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
ff4a8d2b 1152 {ARM_EXT_V1, 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
74bdfecf
NC		 1153
1154 {ARM_EXT_V1, 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
1155 {ARM_EXT_V1, 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
ff4a8d2b 1156 {ARM_EXT_V1, 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
74bdfecf
NC		 1157
1158 {ARM_EXT_V1, 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
1159 {ARM_EXT_V1, 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
ff4a8d2b 1160 {ARM_EXT_V1, 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
74bdfecf
NC		 1161
1162 {ARM_EXT_V1, 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
1163 {ARM_EXT_V1, 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
ff4a8d2b 1164 {ARM_EXT_V1, 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
74bdfecf
NC		 1165
1166 {ARM_EXT_V1, 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
1167 {ARM_EXT_V1, 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
ff4a8d2b 1168 {ARM_EXT_V1, 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
74bdfecf
NC		 1169
1170 {ARM_EXT_V1, 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
1171 {ARM_EXT_V1, 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
ff4a8d2b 1172 {ARM_EXT_V1, 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
74bdfecf
NC		 1173
1174 {ARM_EXT_V1, 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
1175 {ARM_EXT_V1, 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
ff4a8d2b 1176 {ARM_EXT_V1, 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
74bdfecf
NC		 1177
1178 {ARM_EXT_V1, 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
1179 {ARM_EXT_V1, 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
ff4a8d2b 1180 {ARM_EXT_V1, 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
74bdfecf 1181
90ec0d68
MGD		 1182 {ARM_EXT_VIRT, 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
1183 {ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
1184 {ARM_EXT_V3, 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
74bdfecf
NC		 1185
1186 {ARM_EXT_V1, 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
1187 {ARM_EXT_V1, 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
ff4a8d2b 1188 {ARM_EXT_V1, 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
74bdfecf
NC		 1189
1190 {ARM_EXT_V1, 0x03200000, 0x0fe00000, "teq%p%c\t%16-19r, %o"},
1191 {ARM_EXT_V1, 0x01200000, 0x0fe00010, "teq%p%c\t%16-19r, %o"},
ff4a8d2b 1192 {ARM_EXT_V1, 0x01200010, 0x0fe00090, "teq%p%c\t%16-19R, %o"},
74bdfecf
NC		 1193
1194 {ARM_EXT_V1, 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
1195 {ARM_EXT_V1, 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
ff4a8d2b 1196 {ARM_EXT_V1, 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
74bdfecf
NC		 1197
1198 {ARM_EXT_V1, 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
1199 {ARM_EXT_V1, 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
ff4a8d2b 1200 {ARM_EXT_V1, 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
74bdfecf
NC		 1201
1202 {ARM_EXT_V1, 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
1203 {ARM_EXT_V1, 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
ff4a8d2b 1204 {ARM_EXT_V1, 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
74bdfecf 1205
37b37b2d
RE		 1206 {ARM_EXT_V1, 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
1207 {ARM_EXT_V1, 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
ff4a8d2b
NC		 1208 {ARM_EXT_V1, 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
1209 {ARM_EXT_V1, 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
1210 {ARM_EXT_V1, 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
37b37b2d 1211 {ARM_EXT_V1, 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
ff4a8d2b 1212 {ARM_EXT_V1, 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
74bdfecf
NC		 1213
1214 {ARM_EXT_V1, 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
1215 {ARM_EXT_V1, 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
ff4a8d2b 1216 {ARM_EXT_V1, 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
74bdfecf
NC		 1217
1218 {ARM_EXT_V1, 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
1219 {ARM_EXT_V1, 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
ff4a8d2b 1220 {ARM_EXT_V1, 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
74bdfecf 1221
05413229 1222 {ARM_EXT_V1, 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
37b37b2d 1223 {ARM_EXT_V1, 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
ab8e2090
NC		 1224
1225 {ARM_EXT_V1, 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
1226
1227 {ARM_EXT_V1, 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
1228 {ARM_EXT_V1, 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
1229
101af531
NC		 1230 {ARM_EXT_V1, 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1231 {ARM_EXT_V1, 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1232 {ARM_EXT_V1, 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1233 {ARM_EXT_V1, 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1234 {ARM_EXT_V1, 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1235 {ARM_EXT_V1, 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1236 {ARM_EXT_V1, 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1237 {ARM_EXT_V1, 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1238 {ARM_EXT_V1, 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1239 {ARM_EXT_V1, 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1240 {ARM_EXT_V1, 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1241 {ARM_EXT_V1, 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1242 {ARM_EXT_V1, 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1243 {ARM_EXT_V1, 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1244 {ARM_EXT_V1, 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1245 {ARM_EXT_V1, 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
37b37b2d 1246 {ARM_EXT_V1, 0x092d0000, 0x0fff0000, "push%c\t%m"},
ab8e2090
NC		 1247 {ARM_EXT_V1, 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
1248 {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
101af531
NC		 1249
1250 {ARM_EXT_V1, 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1251 {ARM_EXT_V1, 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1252 {ARM_EXT_V1, 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1253 {ARM_EXT_V1, 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1254 {ARM_EXT_V1, 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1255 {ARM_EXT_V1, 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1256 {ARM_EXT_V1, 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1257 {ARM_EXT_V1, 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1258 {ARM_EXT_V1, 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1259 {ARM_EXT_V1, 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1260 {ARM_EXT_V1, 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1261 {ARM_EXT_V1, 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1262 {ARM_EXT_V1, 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1263 {ARM_EXT_V1, 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1264 {ARM_EXT_V1, 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1265 {ARM_EXT_V1, 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
37b37b2d 1266 {ARM_EXT_V1, 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
ab8e2090
NC		 1267 {ARM_EXT_V1, 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
1268 {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
101af531 1269
8f06b2d8 1270 {ARM_EXT_V1, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
c16d2bf0 1271 {ARM_EXT_V1, 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 1272
1273 /* The rest. */
05413229 1274 {ARM_EXT_V1, 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
8f06b2d8
PB		 1275 {0, 0x00000000, 0x00000000, 0}
1276};
1277
1278/* print_insn_thumb16 recognizes the following format control codes:
1279
1280 %S print Thumb register (bits 3..5 as high number if bit 6 set)
1281 %D print Thumb register (bits 0..2 as high number if bit 7 set)
1282 %<bitfield>I print bitfield as a signed decimal
1283 (top bit of range being the sign bit)
1284 %N print Thumb register mask (with LR)
1285 %O print Thumb register mask (with PC)
1286 %M print Thumb register mask
1287 %b print CZB's 6-bit unsigned branch destination
1288 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 1289 %c print the condition code
1290 %C print the condition code, or "s" if not conditional
1291 %x print warning if conditional an not at end of IT block"
1292 %X print "\t; unpredictable <IT:code>" if conditional
1293 %I print IT instruction suffix and operands
4547cb56 1294 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 1295 %<bitfield>r print bitfield as an ARM register
1296 %<bitfield>d print bitfield as a decimal
1297 %<bitfield>H print (bitfield * 2) as a decimal
1298 %<bitfield>W print (bitfield * 4) as a decimal
1299 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
1300 %<bitfield>B print Thumb branch destination (signed displacement)
1301 %<bitfield>c print bitfield as a condition code
1302 %<bitnum>'c print specified char iff bit is one
1303 %<bitnum>?ab print a if bit is one else print b. */
1304
1305static const struct opcode16 thumb_opcodes[] =
1306{
1307 /* Thumb instructions. */
1308
53c4b28b
MGD		 1309 /* ARM V8 instructions. */
1310 {ARM_EXT_V8, 0xbf50, 0xffff, "sevl%c"},
8884b720 1311 {ARM_EXT_V8, 0xba80, 0xffc0, "hlt\t%0-5x"},
53c4b28b 1312
8f06b2d8 1313 /* ARM V6K no-argument instructions. */
c22aaad1
PB		 1314 {ARM_EXT_V6K, 0xbf00, 0xffff, "nop%c"},
1315 {ARM_EXT_V6K, 0xbf10, 0xffff, "yield%c"},
1316 {ARM_EXT_V6K, 0xbf20, 0xffff, "wfe%c"},
1317 {ARM_EXT_V6K, 0xbf30, 0xffff, "wfi%c"},
1318 {ARM_EXT_V6K, 0xbf40, 0xffff, "sev%c"},
1319 {ARM_EXT_V6K, 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 1320
1321 /* ARM V6T2 instructions. */
c22aaad1
PB		 1322 {ARM_EXT_V6T2, 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
1323 {ARM_EXT_V6T2, 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
1324 {ARM_EXT_V6T2, 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 1325
1326 /* ARM V6. */
c22aaad1
PB		 1327 {ARM_EXT_V6, 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
1328 {ARM_EXT_V6, 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
1329 {ARM_EXT_V6, 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
1330 {ARM_EXT_V6, 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
1331 {ARM_EXT_V6, 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
1332 {ARM_EXT_V6, 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
1333 {ARM_EXT_V6, 0xb650, 0xfff7, "setend\t%3?ble%X"},
1334 {ARM_EXT_V6, 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
1335 {ARM_EXT_V6, 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
1336 {ARM_EXT_V6, 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
1337 {ARM_EXT_V6, 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 1338
1339 /* ARM V5 ISA extends Thumb. */
c22aaad1 1340 {ARM_EXT_V5T, 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 1341 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
c22aaad1 1342 {ARM_EXT_V5T, 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 1343 /* ARM V4T ISA (Thumb v1). */
fe56b6ce 1344 {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 1345 /* Format 4. */
c22aaad1
PB		 1346 {ARM_EXT_V4T, 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
1347 {ARM_EXT_V4T, 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
1348 {ARM_EXT_V4T, 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
1349 {ARM_EXT_V4T, 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
1350 {ARM_EXT_V4T, 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
1351 {ARM_EXT_V4T, 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
1352 {ARM_EXT_V4T, 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
1353 {ARM_EXT_V4T, 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
1354 {ARM_EXT_V4T, 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
1355 {ARM_EXT_V4T, 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
1356 {ARM_EXT_V4T, 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
1357 {ARM_EXT_V4T, 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
1358 {ARM_EXT_V4T, 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
1359 {ARM_EXT_V4T, 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
1360 {ARM_EXT_V4T, 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
1361 {ARM_EXT_V4T, 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 1362 /* format 13 */
c22aaad1
PB		 1363 {ARM_EXT_V4T, 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
1364 {ARM_EXT_V4T, 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 1365 /* format 5 */
c22aaad1
PB		 1366 {ARM_EXT_V4T, 0x4700, 0xFF80, "bx%c\t%S%x"},
1367 {ARM_EXT_V4T, 0x4400, 0xFF00, "add%c\t%D, %S"},
1368 {ARM_EXT_V4T, 0x4500, 0xFF00, "cmp%c\t%D, %S"},
1369 {ARM_EXT_V4T, 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 1370 /* format 14 */
c22aaad1
PB		 1371 {ARM_EXT_V4T, 0xB400, 0xFE00, "push%c\t%N"},
1372 {ARM_EXT_V4T, 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 1373 /* format 2 */
c22aaad1
PB		 1374 {ARM_EXT_V4T, 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
1375 {ARM_EXT_V4T, 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
1376 {ARM_EXT_V4T, 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
1377 {ARM_EXT_V4T, 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 1378 /* format 8 */
c22aaad1
PB		 1379 {ARM_EXT_V4T, 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
1380 {ARM_EXT_V4T, 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
1381 {ARM_EXT_V4T, 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 1382 /* format 7 */
c22aaad1
PB		 1383 {ARM_EXT_V4T, 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
1384 {ARM_EXT_V4T, 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 1385 /* format 1 */
1f4e4950 1386 {ARM_EXT_V4T, 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
c22aaad1
PB		 1387 {ARM_EXT_V4T, 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
1388 {ARM_EXT_V4T, 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
1389 {ARM_EXT_V4T, 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 1390 /* format 3 */
c22aaad1
PB		 1391 {ARM_EXT_V4T, 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
1392 {ARM_EXT_V4T, 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
1393 {ARM_EXT_V4T, 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
1394 {ARM_EXT_V4T, 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 1395 /* format 6 */
fe56b6ce 1396 {ARM_EXT_V4T, 0x4800, 0xF800, "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
8f06b2d8 1397 /* format 9 */
c22aaad1
PB		 1398 {ARM_EXT_V4T, 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
1399 {ARM_EXT_V4T, 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
1400 {ARM_EXT_V4T, 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
1401 {ARM_EXT_V4T, 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 1402 /* format 10 */
c22aaad1
PB		 1403 {ARM_EXT_V4T, 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
1404 {ARM_EXT_V4T, 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 1405 /* format 11 */
c22aaad1
PB		 1406 {ARM_EXT_V4T, 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
1407 {ARM_EXT_V4T, 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 1408 /* format 12 */
fe56b6ce 1409 {ARM_EXT_V4T, 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
c22aaad1 1410 {ARM_EXT_V4T, 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 1411 /* format 15 */
c22aaad1 1412 {ARM_EXT_V4T, 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4547cb56 1413 {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 1414 /* format 17 */
c22aaad1 1415 {ARM_EXT_V4T, 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 1416 /* format 16 */
74db7efb 1417 {ARM_EXT_V4T, 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
05413229 1418 {ARM_EXT_V4T, 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
c22aaad1 1419 {ARM_EXT_V4T, 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 1420 /* format 18 */
c22aaad1 1421 {ARM_EXT_V4T, 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 1422
1423 /* The E800 .. FFFF range is unconditionally redirected to the
1424 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
1425 are processed via that table. Thus, we can never encounter a
1426 bare "second half of BL/BLX(1)" instruction here. */
05413229 1427 {ARM_EXT_V1, 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
8f06b2d8
PB		 1428 {0, 0, 0, 0}
1429};
1430
1431/* Thumb32 opcodes use the same table structure as the ARM opcodes.
1432 We adopt the convention that hw1 is the high 16 bits of .value and
1433 .mask, hw2 the low 16 bits.
1434
1435 print_insn_thumb32 recognizes the following format control codes:
1436
1437 %% %
1438
1439 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
1440 %M print a modified 12-bit immediate (same location)
1441 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
1442 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 1443 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 1444 %S print a possibly-shifted Rm
1445
32a94698 1446 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 1447 %a print the address of a plain load/store
1448 %w print the width and signedness of a core load/store
1449 %m print register mask for ldm/stm
1450
1451 %E print the lsb and width fields of a bfc/bfi instruction
1452 %F print the lsb and width fields of a sbfx/ubfx instruction
1453 %b print a conditional branch offset
1454 %B print an unconditional branch offset
1455 %s print the shift field of an SSAT instruction
1456 %R print the rotation field of an SXT instruction
62b3e311
PB		 1457 %U print barrier type.
1458 %P print address for pli instruction.
c22aaad1
PB		 1459 %c print the condition code
1460 %x print warning if conditional an not at end of IT block"
1461 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 1462
1463 %<bitfield>d print bitfield in decimal
1464 %<bitfield>W print bitfield*4 in decimal
1465 %<bitfield>r print bitfield as an ARM register
dd5181d5
KT		 1466 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
1467 %<bitfield>S as %<>R but r13 is UNPREDICTABLE
8f06b2d8
PB		 1468 %<bitfield>c print bitfield as a condition code
1469
16980d0b
JB		 1470 %<bitfield>'c print specified char iff bitfield is all ones
1471 %<bitfield>`c print specified char iff bitfield is all zeroes
1472 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 1473
1474 With one exception at the bottom (done because BL and BLX(1) need
1475 to come dead last), this table was machine-sorted first in
1476 decreasing order of number of bits set in the mask, then in
1477 increasing numeric order of mask, then in increasing numeric order
1478 of opcode. This order is not the clearest for a human reader, but
1479 is guaranteed never to catch a special-case bit pattern with a more
1480 general mask, which is important, because this instruction encoding
1481 makes heavy use of special-case bit patterns. */
1482static const struct opcode32 thumb32_opcodes[] =
1483{
53c4b28b
MGD		 1484 /* V8 instructions. */
1485 {ARM_EXT_V8, 0xf3af8005, 0xffffffff, "sevl%c.w"},
b79f7053 1486 {ARM_EXT_V8, 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4b8c8c02
RE		 1487 {ARM_EXT_V8, 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
1488 {ARM_EXT_V8, 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
1489 {ARM_EXT_V8, 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
1490 {ARM_EXT_V8, 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
1491 {ARM_EXT_V8, 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
1492 {ARM_EXT_V8, 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
1493 {ARM_EXT_V8, 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
1494 {ARM_EXT_V8, 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
1495 {ARM_EXT_V8, 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
1496 {ARM_EXT_V8, 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
1497 {ARM_EXT_V8, 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
1498 {ARM_EXT_V8, 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
1499 {ARM_EXT_V8, 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1500 {ARM_EXT_V8, 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 1501
dd5181d5
KT		 1502 /* CRC32 instructions. */
1503 {CRC_EXT_ARMV8, 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"},
1504 {CRC_EXT_ARMV8, 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"},
1505 {CRC_EXT_ARMV8, 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"},
1506 {CRC_EXT_ARMV8, 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"},
1507 {CRC_EXT_ARMV8, 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"},
1508 {CRC_EXT_ARMV8, 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"},
1509
62b3e311 1510 /* V7 instructions. */
c22aaad1
PB		 1511 {ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"},
1512 {ARM_EXT_V7, 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
e797f7e0
MGD		 1513 {ARM_EXT_V8, 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
1514 {ARM_EXT_V8, 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
c22aaad1
PB		 1515 {ARM_EXT_V7, 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
1516 {ARM_EXT_V7, 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
1517 {ARM_EXT_V7, 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
1518 {ARM_EXT_DIV, 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
1519 {ARM_EXT_DIV, 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 1520
90ec0d68
MGD		 1521 /* Virtualization Extension instructions. */
1522 {ARM_EXT_VIRT, 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
1523 /* We skip ERET as that is SUBS pc, lr, #0. */
1524
60e5ef9f
MGD		 1525 /* MP Extension instructions. */
1526 {ARM_EXT_MP, 0xf830f000, 0xff70f000, "pldw%c\t%a"},
1527
f4c65163
MGD		 1528 /* Security extension instructions. */
1529 {ARM_EXT_SEC, 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
1530
8f06b2d8 1531 /* Instructions defined in the basic V6T2 set. */
c22aaad1
PB		 1532 {ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "nop%c.w"},
1533 {ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield%c.w"},
1534 {ARM_EXT_V6T2, 0xf3af8002, 0xffffffff, "wfe%c.w"},
1535 {ARM_EXT_V6T2, 0xf3af8003, 0xffffffff, "wfi%c.w"},
fe2ceba1 1536 {ARM_EXT_V6T2, 0xf3af8004, 0xffffffff, "sev%c.w"},
c22aaad1 1537 {ARM_EXT_V6T2, 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
74db7efb 1538 {ARM_EXT_V6T2, 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
c22aaad1
PB		 1539
1540 {ARM_EXT_V6T2, 0xf3bf8f2f, 0xffffffff, "clrex%c"},
1541 {ARM_EXT_V6T2, 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
1542 {ARM_EXT_V6T2, 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
1543 {ARM_EXT_V6T2, 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
1544 {ARM_EXT_V6T2, 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
1545 {ARM_EXT_V6T2, 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
90ec0d68 1546 {ARM_EXT_V6T2, 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
c22aaad1
PB		 1547 {ARM_EXT_V6T2, 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
1548 {ARM_EXT_V6T2, 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
1549 {ARM_EXT_V6T2, 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
1550 {ARM_EXT_V6T2, 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
1551 {ARM_EXT_V6T2, 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
1552 {ARM_EXT_V6T2, 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
1553 {ARM_EXT_V6T2, 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
1554 {ARM_EXT_V6T2, 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
1555 {ARM_EXT_V6T2, 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
b6702015
PB		 1556 {ARM_EXT_V6T2, 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
1557 {ARM_EXT_V6T2, 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
c22aaad1
PB		 1558 {ARM_EXT_V6T2, 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
1559 {ARM_EXT_V6T2, 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
1560 {ARM_EXT_V6T2, 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
1561 {ARM_EXT_V6T2, 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
1562 {ARM_EXT_V6T2, 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
1563 {ARM_EXT_V6T2, 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
1564 {ARM_EXT_V6T2, 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
1565 {ARM_EXT_V6T2, 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
1566 {ARM_EXT_V6T2, 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
1567 {ARM_EXT_V6T2, 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
1568 {ARM_EXT_V6T2, 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
1569 {ARM_EXT_V6T2, 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
1570 {ARM_EXT_V6T2, 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
1571 {ARM_EXT_V6T2, 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
03ee1b7f
NC		 1572 {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
1573 {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
1574 {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
1575 {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
c22aaad1
PB		 1576 {ARM_EXT_V6T2, 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
1577 {ARM_EXT_V6T2, 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
1578 {ARM_EXT_V6T2, 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
1579 {ARM_EXT_V6T2, 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
1580 {ARM_EXT_V6T2, 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
1581 {ARM_EXT_V6T2, 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
1582 {ARM_EXT_V6T2, 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
1583 {ARM_EXT_V6T2, 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
1584 {ARM_EXT_V6T2, 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
1585 {ARM_EXT_V6T2, 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
c060226a
NC		 1586 {ARM_EXT_V6T2, 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
1587 {ARM_EXT_V6T2, 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
1588 {ARM_EXT_V6T2, 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
1589 {ARM_EXT_V6T2, 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
1590 {ARM_EXT_V6T2, 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
1591 {ARM_EXT_V6T2, 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
c22aaad1
PB		 1592 {ARM_EXT_V6T2, 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
1593 {ARM_EXT_V6T2, 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
1594 {ARM_EXT_V6T2, 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
1595 {ARM_EXT_V6T2, 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
1596 {ARM_EXT_V6T2, 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
1597 {ARM_EXT_V6T2, 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
1598 {ARM_EXT_V6T2, 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
1599 {ARM_EXT_V6T2, 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
1600 {ARM_EXT_V6T2, 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
1601 {ARM_EXT_V6T2, 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
1602 {ARM_EXT_V6T2, 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
1603 {ARM_EXT_V6T2, 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
1604 {ARM_EXT_V6T2, 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
1605 {ARM_EXT_V6T2, 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
c060226a
NC		 1606 {ARM_EXT_V6T2, 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
1607 {ARM_EXT_V6T2, 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
1608 {ARM_EXT_V6T2, 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
1609 {ARM_EXT_V6T2, 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
1610 {ARM_EXT_V6T2, 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
1611 {ARM_EXT_V6T2, 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
c22aaad1
PB		 1612 {ARM_EXT_V6T2, 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
1613 {ARM_EXT_V6T2, 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
ff4a8d2b
NC		 1614 {ARM_EXT_V6T2, 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
1615 {ARM_EXT_V6T2, 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
1616 {ARM_EXT_V6T2, 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
c22aaad1
PB		 1617 {ARM_EXT_V6T2, 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
1618 {ARM_EXT_V6T2, 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
1619 {ARM_EXT_V6T2, 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4d, %16-19r"},
1620 {ARM_EXT_V6T2, 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
1621 {ARM_EXT_V6T2, 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
1622 {ARM_EXT_V6T2, 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
1623 {ARM_EXT_V6T2, 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
1624 {ARM_EXT_V6T2, 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
1625 {ARM_EXT_V6T2, 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
1626 {ARM_EXT_V6T2, 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
1627 {ARM_EXT_V6T2, 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
1628 {ARM_EXT_V6T2, 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
1629 {ARM_EXT_V6T2, 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
1630 {ARM_EXT_V6T2, 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
1631 {ARM_EXT_V6T2, 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
1632 {ARM_EXT_V6T2, 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
1633 {ARM_EXT_V6T2, 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
1634 {ARM_EXT_V6T2, 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
1635 {ARM_EXT_V6T2, 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
1636 {ARM_EXT_V6T2, 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
1637 {ARM_EXT_V6T2, 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
1638 {ARM_EXT_V6T2, 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
1639 {ARM_EXT_V6T2, 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
1640 {ARM_EXT_V6T2, 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
1641 {ARM_EXT_V6T2, 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
1642 {ARM_EXT_V6T2, 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
1643 {ARM_EXT_V6T2, 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
1644 {ARM_EXT_V6T2, 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1645 {ARM_EXT_V6T2, 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
ff4a8d2b
NC		 1646 {ARM_EXT_V6T2, 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1647 {ARM_EXT_V6T2, 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1648 {ARM_EXT_V6T2, 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1649 {ARM_EXT_V6T2, 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1650 {ARM_EXT_V6T2, 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1651 {ARM_EXT_V6T2, 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
c22aaad1 1652 {ARM_EXT_V6T2, 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
c22aaad1
PB		 1653 {ARM_EXT_V6T2, 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
1654 {ARM_EXT_V6T2, 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
1655 {ARM_EXT_V6T2, 0xf810f000, 0xff70f000, "pld%c\t%a"},
ff4a8d2b
NC		 1656 {ARM_EXT_V6T2, 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1657 {ARM_EXT_V6T2, 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1658 {ARM_EXT_V6T2, 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1659 {ARM_EXT_V6T2, 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1660 {ARM_EXT_V6T2, 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1661 {ARM_EXT_V6T2, 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1662 {ARM_EXT_V6T2, 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
c22aaad1
PB		 1663 {ARM_EXT_V6T2, 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
1664 {ARM_EXT_V6T2, 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
1665 {ARM_EXT_V6T2, 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
1666 {ARM_EXT_V6T2, 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
1667 {ARM_EXT_V6T2, 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
1668 {ARM_EXT_V6T2, 0xfb100000, 0xfff000c0, "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1669 {ARM_EXT_V6T2, 0xfbc00080, 0xfff000c0, "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
1670 {ARM_EXT_V6T2, 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
1671 {ARM_EXT_V6T2, 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
1672 {ARM_EXT_V6T2, 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4d, %16-19r%s"},
1673 {ARM_EXT_V6T2, 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
1674 {ARM_EXT_V6T2, 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
1675 {ARM_EXT_V6T2, 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
1676 {ARM_EXT_V6T2, 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
1677 {ARM_EXT_V6T2, 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
1678 {ARM_EXT_V6T2, 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
1679 {ARM_EXT_V6T2, 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
1680 {ARM_EXT_V6T2, 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
1681 {ARM_EXT_V6T2, 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
1682 {ARM_EXT_V6T2, 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
1683 {ARM_EXT_V6T2, 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
1684 {ARM_EXT_V6T2, 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
1685 {ARM_EXT_V6T2, 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
1686 {ARM_EXT_V6T2, 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
1687 {ARM_EXT_V6T2, 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
1688 {ARM_EXT_V6T2, 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
1689 {ARM_EXT_V6T2, 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
1690 {ARM_EXT_V6T2, 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
1691 {ARM_EXT_V6T2, 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
1692 {ARM_EXT_V6T2, 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
1693 {ARM_EXT_V6T2, 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
1694 {ARM_EXT_V6T2, 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
1695 {ARM_EXT_V6T2, 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
1696 {ARM_EXT_V6T2, 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
1697 {ARM_EXT_V6T2, 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
1698 {ARM_EXT_V6T2, 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
1699 {ARM_EXT_V6T2, 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
1700 {ARM_EXT_V6T2, 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
1701 {ARM_EXT_V6T2, 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
1702 {ARM_EXT_V6T2, 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
1703 {ARM_EXT_V6T2, 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
1704 {ARM_EXT_V6T2, 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
32a94698
NC		 1705 {ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
1706 {ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
1707 {ARM_EXT_V6T2, 0xe8600000, 0xff700000, "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
1708 {ARM_EXT_V6T2, 0xe8700000, 0xff700000, "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
c22aaad1
PB		 1709 {ARM_EXT_V6T2, 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
1710 {ARM_EXT_V6T2, 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 1711
1712 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
1713 {ARM_EXT_V6T2, 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
1714 {ARM_EXT_V6T2, 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
c22aaad1
PB		 1715 {ARM_EXT_V6T2, 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
1716 {ARM_EXT_V6T2, 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 1717
8f06b2d8 1718 /* These have been 32-bit since the invention of Thumb. */
639e30d2 1719 {ARM_EXT_V4T, 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
c22aaad1 1720 {ARM_EXT_V4T, 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 1721
1722 /* Fallback. */
05413229 1723 {ARM_EXT_V1, 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
8f06b2d8
PB		 1724 {0, 0, 0, 0}
1725};
ff4a8d2b 1726
8f06b2d8
PB		 1727static const char *const arm_conditional[] =
1728{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 1729 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 1730
1731static const char *const arm_fp_const[] =
1732{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
1733
1734static const char *const arm_shift[] =
1735{"lsl", "lsr", "asr", "ror"};
1736
1737typedef struct
1738{
1739 const char *name;
1740 const char *description;
1741 const char *reg_names[16];
1742}
1743arm_regname;
1744
1745static const arm_regname regnames[] =
1746{
1747 { "raw" , "Select raw register names",
1748 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
1749 { "gcc", "Select register names used by GCC",
1750 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
1751 { "std", "Select register names used in ARM's ISA documentation",
1752 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
1753 { "apcs", "Select register names used in the APCS",
1754 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
1755 { "atpcs", "Select register names used in the ATPCS",
1756 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
1757 { "special-atpcs", "Select special register names used in the ATPCS",
1758 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
1759};
1760
1761static const char *const iwmmxt_wwnames[] =
1762{"b", "h", "w", "d"};
1763
1764static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 1765{"b", "bus", "bc", "bss",
1766 "h", "hus", "hc", "hss",
1767 "w", "wus", "wc", "wss",
1768 "d", "dus", "dc", "dss"
8f06b2d8
PB		 1769};
1770
1771static const char *const iwmmxt_regnames[] =
1772{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
1773 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
1774};
1775
1776static const char *const iwmmxt_cregnames[] =
1777{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
1778 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
1779};
1780
1781/* Default to GCC register name set. */
1782static unsigned int regname_selected = 1;
1783
1784#define NUM_ARM_REGNAMES NUM_ELEM (regnames)
1785#define arm_regnames regnames[regname_selected].reg_names
1786
1787static bfd_boolean force_thumb = FALSE;
1788
c22aaad1
PB		 1789/* Current IT instruction state. This contains the same state as the IT
1790 bits in the CPSR. */
1791static unsigned int ifthen_state;
1792/* IT state for the next instruction. */
1793static unsigned int ifthen_next_state;
1794/* The address of the insn for which the IT state is valid. */
1795static bfd_vma ifthen_address;
1796#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 1797/* Indicates that the current Conditional state is unconditional or outside
1798 an IT block. */
1799#define COND_UNCOND 16
c22aaad1 1800
8f06b2d8
PB		 1801\f
1802/* Functions. */
1803int
1804get_arm_regname_num_options (void)
1805{
1806 return NUM_ARM_REGNAMES;
1807}
1808
1809int
1810set_arm_regname_option (int option)
1811{
1812 int old = regname_selected;
1813 regname_selected = option;
1814 return old;
1815}
1816
1817int
fe56b6ce
NC		 1818get_arm_regnames (int option,
1819 const char **setname,
1820 const char **setdescription,
8f06b2d8
PB		 1821 const char *const **register_names)
1822{
1823 *setname = regnames[option].name;
1824 *setdescription = regnames[option].description;
1825 *register_names = regnames[option].reg_names;
1826 return 16;
1827}
1828
16980d0b
JB		 1829/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
1830 Returns pointer to following character of the format string and
1831 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 1832 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 1833
1834static const char *
fe56b6ce
NC		 1835arm_decode_bitfield (const char *ptr,
1836 unsigned long insn,
1837 unsigned long *valuep,
1838 int *widthp)
16980d0b
JB		 1839{
1840 unsigned long value = 0;
1841 int width = 0;
1842
1843 do
1844 {
1845 int start, end;
1846 int bits;
1847
1848 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
1849 start = start * 10 + *ptr - '0';
1850 if (*ptr == '-')
1851 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
1852 end = end * 10 + *ptr - '0';
1853 else
1854 end = start;
1855 bits = end - start;
1856 if (bits < 0)
1857 abort ();
1858 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
1859 width += bits + 1;
1860 }
1861 while (*ptr++ == ',');
1862 *valuep = value;
1863 if (widthp)
1864 *widthp = width;
1865 return ptr - 1;
1866}
1867
8f06b2d8 1868static void
37b37b2d 1869arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 1870 bfd_boolean print_shift)
8f06b2d8
PB		 1871{
1872 func (stream, "%s", arm_regnames[given & 0xf]);
1873
1874 if ((given & 0xff0) != 0)
1875 {
1876 if ((given & 0x10) == 0)
1877 {
1878 int amount = (given & 0xf80) >> 7;
1879 int shift = (given & 0x60) >> 5;
1880
1881 if (amount == 0)
1882 {
1883 if (shift == 3)
1884 {
1885 func (stream, ", rrx");
1886 return;
1887 }
1888
1889 amount = 32;
1890 }
1891
37b37b2d
RE		 1892 if (print_shift)
1893 func (stream, ", %s #%d", arm_shift[shift], amount);
1894 else
1895 func (stream, ", #%d", amount);
8f06b2d8 1896 }
74bdfecf 1897 else if ((given & 0x80) == 0x80)
aefd8a40 1898 func (stream, "\t; <illegal shifter operand>");
37b37b2d 1899 else if (print_shift)
8f06b2d8
PB		 1900 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
1901 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 1902 else
1903 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 1904 }
1905}
1906
c1e26897
NC		 1907#define W_BIT 21
1908#define I_BIT 22
1909#define U_BIT 23
1910#define P_BIT 24
1911
1912#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
1913#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
1914#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
1915#define PRE_BIT_SET (given & (1 << P_BIT))
1916
8f06b2d8
PB		 1917/* Print one coprocessor instruction on INFO->STREAM.
1918 Return TRUE if the instuction matched, FALSE if this is not a
1919 recognised coprocessor instruction. */
1920
1921static bfd_boolean
fe56b6ce
NC		 1922print_insn_coprocessor (bfd_vma pc,
1923 struct disassemble_info *info,
1924 long given,
8f06b2d8
PB		 1925 bfd_boolean thumb)
1926{
1927 const struct opcode32 *insn;
1928 void *stream = info->stream;
1929 fprintf_ftype func = info->fprintf_func;
1930 unsigned long mask;
2edcd244 1931 unsigned long value = 0;
b0e28b39
DJ		 1932 struct arm_private_data *private_data = info->private_data;
1933 unsigned long allowed_arches = private_data->features.coproc;
c22aaad1 1934 int cond;
8f06b2d8
PB		 1935
1936 for (insn = coprocessor_opcodes; insn->assembler; insn++)
1937 {
ff4a8d2b
NC		 1938 unsigned long u_reg = 16;
1939 bfd_boolean is_unpredictable = FALSE;
05413229 1940 signed long value_in_comment = 0;
0313a2b8
NC		 1941 const char *c;
1942
05413229
NC		 1943 if (insn->arch == 0)
1944 switch (insn->value)
1945 {
1946 case SENTINEL_IWMMXT_START:
1947 if (info->mach != bfd_mach_arm_XScale
1948 && info->mach != bfd_mach_arm_iWMMXt
1949 && info->mach != bfd_mach_arm_iWMMXt2)
1950 do
1951 insn++;
1952 while (insn->arch != 0 && insn->value != SENTINEL_IWMMXT_END);
1953 continue;
1954
1955 case SENTINEL_IWMMXT_END:
1956 continue;
1957
1958 case SENTINEL_GENERIC_START:
b0e28b39 1959 allowed_arches = private_data->features.core;
05413229
NC		 1960 continue;
1961
1962 default:
1963 abort ();
1964 }
8f06b2d8
PB		 1965
1966 mask = insn->mask;
1967 value = insn->value;
1968 if (thumb)
1969 {
1970 /* The high 4 bits are 0xe for Arm conditional instructions, and
1971 0xe for arm unconditional instructions. The rest of the
1972 encoding is the same. */
1973 mask |= 0xf0000000;
1974 value |= 0xe0000000;
c22aaad1
PB		 1975 if (ifthen_state)
1976 cond = IFTHEN_COND;
1977 else
e2efe87d 1978 cond = COND_UNCOND;
8f06b2d8
PB		 1979 }
1980 else
1981 {
1982 /* Only match unconditional instuctions against unconditional
1983 patterns. */
1984 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 1985 {
1986 mask |= 0xf0000000;
e2efe87d 1987 cond = COND_UNCOND;
c22aaad1
PB		 1988 }
1989 else
1990 {
1991 cond = (given >> 28) & 0xf;
1992 if (cond == 0xe)
e2efe87d 1993 cond = COND_UNCOND;
c22aaad1 1994 }
8f06b2d8 1995 }
0313a2b8
NC		 1996
1997 if ((given & mask) != value)
1998 continue;
8f06b2d8 1999
05413229 2000 if ((insn->arch & allowed_arches) == 0)
0313a2b8
NC		 2001 continue;
2002
2003 for (c = insn->assembler; *c; c++)
2004 {
2005 if (*c == '%')
8f06b2d8 2006 {
0313a2b8 2007 switch (*++c)
8f06b2d8 2008 {
0313a2b8
NC		 2009 case '%':
2010 func (stream, "%%");
2011 break;
2012
2013 case 'A':
05413229 2014 {
79862e45 2015 int rn = (given >> 16) & 0xf;
f8b960bc 2016 bfd_vma offset = given & 0xff;
0313a2b8 2017
05413229 2018 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 2019
79862e45
DJ		 2020 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
2021 {
2022 /* Not unindexed. The offset is scaled. */
2023 offset = offset * 4;
2024 if (NEGATIVE_BIT_SET)
2025 offset = - offset;
2026 if (rn != 15)
2027 value_in_comment = offset;
2028 }
2029
c1e26897 2030 if (PRE_BIT_SET)
05413229
NC		 2031 {
2032 if (offset)
fe56b6ce 2033 func (stream, ", #%d]%s",
d908c8af 2034 (int) offset,
c1e26897 2035 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 2036 else if (NEGATIVE_BIT_SET)
2037 func (stream, ", #-0]");
05413229
NC		 2038 else
2039 func (stream, "]");
2040 }
2041 else
2042 {
0313a2b8 2043 func (stream, "]");
8f06b2d8 2044
c1e26897 2045 if (WRITEBACK_BIT_SET)
05413229
NC		 2046 {
2047 if (offset)
d908c8af 2048 func (stream, ", #%d", (int) offset);
26d97720
NS		 2049 else if (NEGATIVE_BIT_SET)
2050 func (stream, ", #-0");
05413229
NC		 2051 }
2052 else
fe56b6ce 2053 {
26d97720
NS		 2054 func (stream, ", {%s%d}",
2055 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 2056 (int) offset);
fe56b6ce
NC		 2057 value_in_comment = offset;
2058 }
05413229 2059 }
79862e45
DJ		 2060 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
2061 {
2062 func (stream, "\t; ");
6844b2c2
MGD		 2063 /* For unaligned PCs, apply off-by-alignment
2064 correction. */
2065 info->print_address_func (offset + pc
2066 + info->bytes_per_chunk * 2
2067 - (pc & 3),
2068 info);
79862e45 2069 }
05413229 2070 }
0313a2b8 2071 break;
8f06b2d8 2072
0313a2b8
NC		 2073 case 'B':
2074 {
2075 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
2076 int offset = (given >> 1) & 0x3f;
2077
2078 if (offset == 1)
2079 func (stream, "{d%d}", regno);
2080 else if (regno + offset > 32)
2081 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
2082 else
2083 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
2084 }
2085 break;
8f06b2d8 2086
e2efe87d
MGD		 2087 case 'u':
2088 if (cond != COND_UNCOND)
2089 is_unpredictable = TRUE;
2090
2091 /* Fall through. */
0313a2b8
NC		 2092 case 'c':
2093 func (stream, "%s", arm_conditional[cond]);
2094 break;
8f06b2d8 2095
0313a2b8
NC		 2096 case 'I':
2097 /* Print a Cirrus/DSP shift immediate. */
2098 /* Immediates are 7bit signed ints with bits 0..3 in
2099 bits 0..3 of opcode and bits 4..6 in bits 5..7
2100 of opcode. */
2101 {
2102 int imm;
8f06b2d8 2103
0313a2b8 2104 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 2105
0313a2b8
NC		 2106 /* Is ``imm'' a negative number? */
2107 if (imm & 0x40)
2108 imm |= (-1 << 7);
8f06b2d8 2109
0313a2b8
NC		 2110 func (stream, "%d", imm);
2111 }
2112
2113 break;
8f06b2d8 2114
0313a2b8
NC		 2115 case 'F':
2116 switch (given & 0x00408000)
2117 {
2118 case 0:
2119 func (stream, "4");
2120 break;
2121 case 0x8000:
2122 func (stream, "1");
2123 break;
2124 case 0x00400000:
2125 func (stream, "2");
8f06b2d8 2126 break;
0313a2b8
NC		 2127 default:
2128 func (stream, "3");
2129 }
2130 break;
8f06b2d8 2131
0313a2b8
NC		 2132 case 'P':
2133 switch (given & 0x00080080)
2134 {
2135 case 0:
2136 func (stream, "s");
2137 break;
2138 case 0x80:
2139 func (stream, "d");
2140 break;
2141 case 0x00080000:
2142 func (stream, "e");
2143 break;
2144 default:
2145 func (stream, _("<illegal precision>"));
8f06b2d8 2146 break;
0313a2b8
NC		 2147 }
2148 break;
8f06b2d8 2149
0313a2b8
NC		 2150 case 'Q':
2151 switch (given & 0x00408000)
2152 {
2153 case 0:
2154 func (stream, "s");
8f06b2d8 2155 break;
0313a2b8
NC		 2156 case 0x8000:
2157 func (stream, "d");
8f06b2d8 2158 break;
0313a2b8
NC		 2159 case 0x00400000:
2160 func (stream, "e");
2161 break;
2162 default:
2163 func (stream, "p");
8f06b2d8 2164 break;
0313a2b8
NC		 2165 }
2166 break;
8f06b2d8 2167
0313a2b8
NC		 2168 case 'R':
2169 switch (given & 0x60)
2170 {
2171 case 0:
2172 break;
2173 case 0x20:
2174 func (stream, "p");
2175 break;
2176 case 0x40:
2177 func (stream, "m");
2178 break;
2179 default:
2180 func (stream, "z");
2181 break;
2182 }
2183 break;
16980d0b 2184
0313a2b8
NC		 2185 case '0': case '1': case '2': case '3': case '4':
2186 case '5': case '6': case '7': case '8': case '9':
2187 {
2188 int width;
8f06b2d8 2189
0313a2b8 2190 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 2191
0313a2b8
NC		 2192 switch (*c)
2193 {
ff4a8d2b
NC		 2194 case 'R':
2195 if (value == 15)
2196 is_unpredictable = TRUE;
2197 /* Fall through. */
0313a2b8 2198 case 'r':
ff4a8d2b
NC		 2199 if (c[1] == 'u')
2200 {
2201 /* Eat the 'u' character. */
2202 ++ c;
2203
2204 if (u_reg == value)
2205 is_unpredictable = TRUE;
2206 u_reg = value;
2207 }
0313a2b8
NC		 2208 func (stream, "%s", arm_regnames[value]);
2209 break;
2210 case 'D':
2211 func (stream, "d%ld", value);
2212 break;
2213 case 'Q':
2214 if (value & 1)
2215 func (stream, "<illegal reg q%ld.5>", value >> 1);
2216 else
2217 func (stream, "q%ld", value >> 1);
2218 break;
2219 case 'd':
2220 func (stream, "%ld", value);
05413229 2221 value_in_comment = value;
0313a2b8
NC		 2222 break;
2223 case 'k':
2224 {
2225 int from = (given & (1 << 7)) ? 32 : 16;
2226 func (stream, "%ld", from - value);
2227 }
2228 break;
8f06b2d8 2229
0313a2b8
NC		 2230 case 'f':
2231 if (value > 7)
2232 func (stream, "#%s", arm_fp_const[value & 7]);
2233 else
2234 func (stream, "f%ld", value);
2235 break;
4146fd53 2236
0313a2b8
NC		 2237 case 'w':
2238 if (width == 2)
2239 func (stream, "%s", iwmmxt_wwnames[value]);
2240 else
2241 func (stream, "%s", iwmmxt_wwssnames[value]);
2242 break;
4146fd53 2243
0313a2b8
NC		 2244 case 'g':
2245 func (stream, "%s", iwmmxt_regnames[value]);
2246 break;
2247 case 'G':
2248 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 2249 break;
8f06b2d8 2250
0313a2b8 2251 case 'x':
d1aaab3c 2252 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 2253 break;
8f06b2d8 2254
33399f07
MGD		 2255 case 'c':
2256 switch (value)
2257 {
2258 case 0:
2259 func (stream, "eq");
2260 break;
2261
2262 case 1:
2263 func (stream, "vs");
2264 break;
2265
2266 case 2:
2267 func (stream, "ge");
2268 break;
2269
2270 case 3:
2271 func (stream, "gt");
2272 break;
2273
2274 default:
2275 func (stream, "??");
2276 break;
2277 }
2278 break;
2279
0313a2b8
NC		 2280 case '`':
2281 c++;
2282 if (value == 0)
2283 func (stream, "%c", *c);
2284 break;
2285 case '\'':
2286 c++;
2287 if (value == ((1ul << width) - 1))
2288 func (stream, "%c", *c);
2289 break;
2290 case '?':
fe56b6ce 2291 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 2292 c += 1 << width;
2293 break;
2294 default:
2295 abort ();
2296 }
2297 break;
8f06b2d8 2298
0313a2b8
NC		 2299 case 'y':
2300 case 'z':
2301 {
2302 int single = *c++ == 'y';
2303 int regno;
2304
2305 switch (*c)
2306 {
2307 case '4': /* Sm pair */
2308 case '0': /* Sm, Dm */
2309 regno = given & 0x0000000f;
2310 if (single)
2311 {
2312 regno <<= 1;
2313 regno += (given >> 5) & 1;
16980d0b 2314 }
0313a2b8
NC		 2315 else
2316 regno += ((given >> 5) & 1) << 4;
2317 break;
8f06b2d8 2318
0313a2b8
NC		 2319 case '1': /* Sd, Dd */
2320 regno = (given >> 12) & 0x0000000f;
2321 if (single)
2322 {
2323 regno <<= 1;
2324 regno += (given >> 22) & 1;
2325 }
2326 else
2327 regno += ((given >> 22) & 1) << 4;
2328 break;
8f06b2d8 2329
0313a2b8
NC		 2330 case '2': /* Sn, Dn */
2331 regno = (given >> 16) & 0x0000000f;
2332 if (single)
8f06b2d8 2333 {
0313a2b8
NC		 2334 regno <<= 1;
2335 regno += (given >> 7) & 1;
8f06b2d8 2336 }
0313a2b8
NC		 2337 else
2338 regno += ((given >> 7) & 1) << 4;
2339 break;
7df76b80 2340
0313a2b8
NC		 2341 case '3': /* List */
2342 func (stream, "{");
2343 regno = (given >> 12) & 0x0000000f;
2344 if (single)
2345 {
2346 regno <<= 1;
2347 regno += (given >> 22) & 1;
2348 }
2349 else
2350 regno += ((given >> 22) & 1) << 4;
2351 break;
a7f8487e 2352
0313a2b8
NC		 2353 default:
2354 abort ();
8f06b2d8 2355 }
a7f8487e 2356
0313a2b8
NC		 2357 func (stream, "%c%d", single ? 's' : 'd', regno);
2358
2359 if (*c == '3')
8f06b2d8 2360 {
0313a2b8 2361 int count = given & 0xff;
a7f8487e 2362
0313a2b8
NC		 2363 if (single == 0)
2364 count >>= 1;
b34976b6 2365
0313a2b8 2366 if (--count)
8f06b2d8 2367 {
0313a2b8
NC		 2368 func (stream, "-%c%d",
2369 single ? 's' : 'd',
2370 regno + count);
8f06b2d8 2371 }
0313a2b8
NC		 2372
2373 func (stream, "}");
8f06b2d8 2374 }
0313a2b8
NC		 2375 else if (*c == '4')
2376 func (stream, ", %c%d", single ? 's' : 'd',
2377 regno + 1);
2378 }
2379 break;
2380
2381 case 'L':
2382 switch (given & 0x00400100)
2383 {
2384 case 0x00000000: func (stream, "b"); break;
2385 case 0x00400000: func (stream, "h"); break;
2386 case 0x00000100: func (stream, "w"); break;
2387 case 0x00400100: func (stream, "d"); break;
2388 default:
8f06b2d8 2389 break;
0313a2b8
NC		 2390 }
2391 break;
b34976b6 2392
0313a2b8
NC		 2393 case 'Z':
2394 {
0313a2b8
NC		 2395 /* given (20, 23) | given (0, 3) */
2396 value = ((given >> 16) & 0xf0) | (given & 0xf);
d908c8af 2397 func (stream, "%d", (int) value);
0313a2b8
NC		 2398 }
2399 break;
2d447fca 2400
0313a2b8
NC		 2401 case 'l':
2402 /* This is like the 'A' operator, except that if
2403 the width field "M" is zero, then the offset is
2404 *not* multiplied by four. */
2405 {
2406 int offset = given & 0xff;
2407 int multiplier = (given & 0x00000100) ? 4 : 1;
2408
2409 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
2410
05413229
NC		 2411 if (multiplier > 1)
2412 {
2413 value_in_comment = offset * multiplier;
c1e26897 2414 if (NEGATIVE_BIT_SET)
05413229
NC		 2415 value_in_comment = - value_in_comment;
2416 }
2417
0313a2b8
NC		 2418 if (offset)
2419 {
c1e26897 2420 if (PRE_BIT_SET)
0313a2b8 2421 func (stream, ", #%s%d]%s",
c1e26897 2422 NEGATIVE_BIT_SET ? "-" : "",
0313a2b8 2423 offset * multiplier,
c1e26897 2424 WRITEBACK_BIT_SET ? "!" : "");
0313a2b8
NC		 2425 else
2426 func (stream, "], #%s%d",
c1e26897 2427 NEGATIVE_BIT_SET ? "-" : "",
0313a2b8 2428 offset * multiplier);
2d447fca 2429 }
0313a2b8
NC		 2430 else
2431 func (stream, "]");
2432 }
2433 break;
2434
2435 case 'r':
2436 {
2437 int imm4 = (given >> 4) & 0xf;
c1e26897
NC		 2438 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
2439 int ubit = ! NEGATIVE_BIT_SET;
0313a2b8
NC		 2440 const char *rm = arm_regnames [given & 0xf];
2441 const char *rn = arm_regnames [(given >> 16) & 0xf];
2d447fca 2442
0313a2b8 2443 switch (puw_bits)
2d447fca 2444 {
0313a2b8
NC		 2445 case 1:
2446 case 3:
2447 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
2448 if (imm4)
2449 func (stream, ", lsl #%d", imm4);
2450 break;
2451
2452 case 4:
2453 case 5:
2454 case 6:
2455 case 7:
2456 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
2457 if (imm4 > 0)
2458 func (stream, ", lsl #%d", imm4);
2459 func (stream, "]");
2460 if (puw_bits == 5 || puw_bits == 7)
2461 func (stream, "!");
2462 break;
2463
2464 default:
2465 func (stream, "INVALID");
2d447fca 2466 }
0313a2b8
NC		 2467 }
2468 break;
2d447fca 2469
0313a2b8
NC		 2470 case 'i':
2471 {
2472 long imm5;
2473 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
2474 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
8f06b2d8 2475 }
0313a2b8
NC		 2476 break;
2477
2478 default:
2479 abort ();
2480 }
252b5132 2481 }
252b5132 2482 }
0313a2b8
NC		 2483 else
2484 func (stream, "%c", *c);
252b5132 2485 }
05413229
NC		 2486
2487 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 2488 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 2489
ff4a8d2b
NC		 2490 if (is_unpredictable)
2491 func (stream, UNPREDICTABLE_INSTRUCTION);
2492
0313a2b8 2493 return TRUE;
252b5132 2494 }
8f06b2d8 2495 return FALSE;
252b5132
RH		 2496}
2497
05413229
NC		 2498/* Decodes and prints ARM addressing modes. Returns the offset
2499 used in the address, if any, if it is worthwhile printing the
2500 offset as a hexadecimal value in a comment at the end of the
2501 line of disassembly. */
2502
2503static signed long
62b3e311
PB		 2504print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
2505{
2506 void *stream = info->stream;
2507 fprintf_ftype func = info->fprintf_func;
f8b960bc 2508 bfd_vma offset = 0;
62b3e311
PB		 2509
2510 if (((given & 0x000f0000) == 0x000f0000)
2511 && ((given & 0x02000000) == 0))
2512 {
05413229 2513 offset = given & 0xfff;
62b3e311
PB		 2514
2515 func (stream, "[pc");
2516
c1e26897 2517 if (PRE_BIT_SET)
62b3e311 2518 {
26d97720
NS		 2519 /* Pre-indexed. Elide offset of positive zero when
2520 non-writeback. */
2521 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 2522 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 2523
2524 if (NEGATIVE_BIT_SET)
2525 offset = -offset;
62b3e311
PB		 2526
2527 offset += pc + 8;
2528
2529 /* Cope with the possibility of write-back
2530 being used. Probably a very dangerous thing
2531 for the programmer to do, but who are we to
2532 argue ? */
26d97720 2533 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 2534 }
c1e26897 2535 else /* Post indexed. */
62b3e311 2536 {
d908c8af 2537 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 2538
c1e26897 2539 /* Ie ignore the offset. */
62b3e311
PB		 2540 offset = pc + 8;
2541 }
2542
2543 func (stream, "\t; ");
2544 info->print_address_func (offset, info);
05413229 2545 offset = 0;
62b3e311
PB		 2546 }
2547 else
2548 {
2549 func (stream, "[%s",
2550 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 2551
2552 if (PRE_BIT_SET)
62b3e311
PB		 2553 {
2554 if ((given & 0x02000000) == 0)
2555 {
26d97720 2556 /* Elide offset of positive zero when non-writeback. */
05413229 2557 offset = given & 0xfff;
26d97720 2558 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 2559 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 2560 }
2561 else
2562 {
26d97720 2563 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 2564 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 2565 }
2566
2567 func (stream, "]%s",
c1e26897 2568 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 2569 }
2570 else
2571 {
2572 if ((given & 0x02000000) == 0)
2573 {
26d97720 2574 /* Always show offset. */
05413229 2575 offset = given & 0xfff;
26d97720 2576 func (stream, "], #%s%d",
d908c8af 2577 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 2578 }
2579 else
2580 {
2581 func (stream, "], %s",
c1e26897 2582 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 2583 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 2584 }
2585 }
84919466
MR		 2586 if (NEGATIVE_BIT_SET)
2587 offset = -offset;
62b3e311 2588 }
05413229
NC		 2589
2590 return (signed long) offset;
62b3e311
PB		 2591}
2592
16980d0b
JB		 2593/* Print one neon instruction on INFO->STREAM.
2594 Return TRUE if the instuction matched, FALSE if this is not a
2595 recognised neon instruction. */
2596
2597static bfd_boolean
2598print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
2599{
2600 const struct opcode32 *insn;
2601 void *stream = info->stream;
2602 fprintf_ftype func = info->fprintf_func;
2603
2604 if (thumb)
2605 {
2606 if ((given & 0xef000000) == 0xef000000)
2607 {
0313a2b8 2608 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 2609 unsigned long bit28 = given & (1 << 28);
2610
2611 given &= 0x00ffffff;
2612 if (bit28)
2613 given |= 0xf3000000;
2614 else
2615 given |= 0xf2000000;
2616 }
2617 else if ((given & 0xff000000) == 0xf9000000)
2618 given ^= 0xf9000000 ^ 0xf4000000;
2619 else
2620 return FALSE;
2621 }
2622
2623 for (insn = neon_opcodes; insn->assembler; insn++)
2624 {
2625 if ((given & insn->mask) == insn->value)
2626 {
05413229 2627 signed long value_in_comment = 0;
e2efe87d 2628 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 2629 const char *c;
2630
2631 for (c = insn->assembler; *c; c++)
2632 {
2633 if (*c == '%')
2634 {
2635 switch (*++c)
2636 {
2637 case '%':
2638 func (stream, "%%");
2639 break;
2640
e2efe87d
MGD		 2641 case 'u':
2642 if (thumb && ifthen_state)
2643 is_unpredictable = TRUE;
2644
2645 /* Fall through. */
c22aaad1
PB		 2646 case 'c':
2647 if (thumb && ifthen_state)
2648 func (stream, "%s", arm_conditional[IFTHEN_COND]);
2649 break;
2650
16980d0b
JB		 2651 case 'A':
2652 {
2653 static const unsigned char enc[16] =
2654 {
2655 0x4, 0x14, /* st4 0,1 */
2656 0x4, /* st1 2 */
2657 0x4, /* st2 3 */
2658 0x3, /* st3 4 */
2659 0x13, /* st3 5 */
2660 0x3, /* st1 6 */
2661 0x1, /* st1 7 */
2662 0x2, /* st2 8 */
2663 0x12, /* st2 9 */
2664 0x2, /* st1 10 */
2665 0, 0, 0, 0, 0
2666 };
2667 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
2668 int rn = ((given >> 16) & 0xf);
2669 int rm = ((given >> 0) & 0xf);
2670 int align = ((given >> 4) & 0x3);
2671 int type = ((given >> 8) & 0xf);
2672 int n = enc[type] & 0xf;
2673 int stride = (enc[type] >> 4) + 1;
2674 int ix;
2675
2676 func (stream, "{");
2677 if (stride > 1)
2678 for (ix = 0; ix != n; ix++)
2679 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
2680 else if (n == 1)
2681 func (stream, "d%d", rd);
2682 else
2683 func (stream, "d%d-d%d", rd, rd + n - 1);
2684 func (stream, "}, [%s", arm_regnames[rn]);
2685 if (align)
8e560766 2686 func (stream, " :%d", 32 << align);
16980d0b
JB		 2687 func (stream, "]");
2688 if (rm == 0xd)
2689 func (stream, "!");
2690 else if (rm != 0xf)
2691 func (stream, ", %s", arm_regnames[rm]);
2692 }
2693 break;
2694
2695 case 'B':
2696 {
2697 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
2698 int rn = ((given >> 16) & 0xf);
2699 int rm = ((given >> 0) & 0xf);
2700 int idx_align = ((given >> 4) & 0xf);
2701 int align = 0;
2702 int size = ((given >> 10) & 0x3);
2703 int idx = idx_align >> (size + 1);
2704 int length = ((given >> 8) & 3) + 1;
2705 int stride = 1;
2706 int i;
2707
2708 if (length > 1 && size > 0)
2709 stride = (idx_align & (1 << size)) ? 2 : 1;
2710
2711 switch (length)
2712 {
2713 case 1:
2714 {
2715 int amask = (1 << size) - 1;
2716 if ((idx_align & (1 << size)) != 0)
2717 return FALSE;
2718 if (size > 0)
2719 {
2720 if ((idx_align & amask) == amask)
2721 align = 8 << size;
2722 else if ((idx_align & amask) != 0)
2723 return FALSE;
2724 }
2725 }
2726 break;
2727
2728 case 2:
2729 if (size == 2 && (idx_align & 2) != 0)
2730 return FALSE;
2731 align = (idx_align & 1) ? 16 << size : 0;
2732 break;
2733
2734 case 3:
2735 if ((size == 2 && (idx_align & 3) != 0)
2736 || (idx_align & 1) != 0)
2737 return FALSE;
2738 break;
2739
2740 case 4:
2741 if (size == 2)
2742 {
2743 if ((idx_align & 3) == 3)
2744 return FALSE;
2745 align = (idx_align & 3) * 64;
2746 }
2747 else
2748 align = (idx_align & 1) ? 32 << size : 0;
2749 break;
2750
2751 default:
2752 abort ();
2753 }
2754
2755 func (stream, "{");
2756 for (i = 0; i < length; i++)
2757 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
2758 rd + i * stride, idx);
2759 func (stream, "}, [%s", arm_regnames[rn]);
2760 if (align)
8e560766 2761 func (stream, " :%d", align);
16980d0b
JB		 2762 func (stream, "]");
2763 if (rm == 0xd)
2764 func (stream, "!");
2765 else if (rm != 0xf)
2766 func (stream, ", %s", arm_regnames[rm]);
2767 }
2768 break;
2769
2770 case 'C':
2771 {
2772 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
2773 int rn = ((given >> 16) & 0xf);
2774 int rm = ((given >> 0) & 0xf);
2775 int align = ((given >> 4) & 0x1);
2776 int size = ((given >> 6) & 0x3);
2777 int type = ((given >> 8) & 0x3);
2778 int n = type + 1;
2779 int stride = ((given >> 5) & 0x1);
2780 int ix;
2781
2782 if (stride && (n == 1))
2783 n++;
2784 else
2785 stride++;
2786
2787 func (stream, "{");
2788 if (stride > 1)
2789 for (ix = 0; ix != n; ix++)
2790 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
2791 else if (n == 1)
2792 func (stream, "d%d[]", rd);
2793 else
2794 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
2795 func (stream, "}, [%s", arm_regnames[rn]);
2796 if (align)
2797 {
91d6fa6a 2798 align = (8 * (type + 1)) << size;
16980d0b
JB		 2799 if (type == 3)
2800 align = (size > 1) ? align >> 1 : align;
2801 if (type == 2 || (type == 0 && !size))
8e560766 2802 func (stream, " :<bad align %d>", align);
16980d0b 2803 else
8e560766 2804 func (stream, " :%d", align);
16980d0b
JB		 2805 }
2806 func (stream, "]");
2807 if (rm == 0xd)
2808 func (stream, "!");
2809 else if (rm != 0xf)
2810 func (stream, ", %s", arm_regnames[rm]);
2811 }
2812 break;
2813
2814 case 'D':
2815 {
2816 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
2817 int size = (given >> 20) & 3;
2818 int reg = raw_reg & ((4 << size) - 1);
2819 int ix = raw_reg >> size >> 2;
2820
2821 func (stream, "d%d[%d]", reg, ix);
2822 }
2823 break;
2824
2825 case 'E':
fe56b6ce 2826 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 2827 {
2828 int bits = 0;
2829 int cmode = (given >> 8) & 0xf;
2830 int op = (given >> 5) & 0x1;
2831 unsigned long value = 0, hival = 0;
2832 unsigned shift;
2833 int size = 0;
0dbde4cf 2834 int isfloat = 0;
16980d0b
JB		 2835
2836 bits |= ((given >> 24) & 1) << 7;
2837 bits |= ((given >> 16) & 7) << 4;
2838 bits |= ((given >> 0) & 15) << 0;
2839
2840 if (cmode < 8)
2841 {
2842 shift = (cmode >> 1) & 3;
fe56b6ce 2843 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 2844 size = 32;
2845 }
2846 else if (cmode < 12)
2847 {
2848 shift = (cmode >> 1) & 1;
fe56b6ce 2849 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 2850 size = 16;
2851 }
2852 else if (cmode < 14)
2853 {
2854 shift = (cmode & 1) + 1;
fe56b6ce 2855 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 2856 value |= (1ul << (8 * shift)) - 1;
2857 size = 32;
2858 }
2859 else if (cmode == 14)
2860 {
2861 if (op)
2862 {
fe56b6ce 2863 /* Bit replication into bytes. */
16980d0b
JB		 2864 int ix;
2865 unsigned long mask;
2866
2867 value = 0;
2868 hival = 0;
2869 for (ix = 7; ix >= 0; ix--)
2870 {
2871 mask = ((bits >> ix) & 1) ? 0xff : 0;
2872 if (ix <= 3)
2873 value = (value << 8) | mask;
2874 else
2875 hival = (hival << 8) | mask;
2876 }
2877 size = 64;
2878 }
2879 else
2880 {
fe56b6ce
NC		 2881 /* Byte replication. */
2882 value = (unsigned long) bits;
16980d0b
JB		 2883 size = 8;
2884 }
2885 }
2886 else if (!op)
2887 {
fe56b6ce 2888 /* Floating point encoding. */
16980d0b
JB		 2889 int tmp;
2890
fe56b6ce
NC		 2891 value = (unsigned long) (bits & 0x7f) << 19;
2892 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 2893 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 2894 value |= (unsigned long) tmp << 24;
16980d0b 2895 size = 32;
0dbde4cf 2896 isfloat = 1;
16980d0b
JB		 2897 }
2898 else
2899 {
2900 func (stream, "<illegal constant %.8x:%x:%x>",
2901 bits, cmode, op);
2902 size = 32;
2903 break;
2904 }
2905 switch (size)
2906 {
2907 case 8:
2908 func (stream, "#%ld\t; 0x%.2lx", value, value);
2909 break;
2910
2911 case 16:
2912 func (stream, "#%ld\t; 0x%.4lx", value, value);
2913 break;
2914
2915 case 32:
0dbde4cf
JB		 2916 if (isfloat)
2917 {
2918 unsigned char valbytes[4];
2919 double fvalue;
2920
2921 /* Do this a byte at a time so we don't have to
2922 worry about the host's endianness. */
2923 valbytes[0] = value & 0xff;
2924 valbytes[1] = (value >> 8) & 0xff;
2925 valbytes[2] = (value >> 16) & 0xff;
2926 valbytes[3] = (value >> 24) & 0xff;
2927
2928 floatformat_to_double
c1e26897
NC		 2929 (& floatformat_ieee_single_little, valbytes,
2930 & fvalue);
0dbde4cf
JB		 2931
2932 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
2933 value);
2934 }
2935 else
4e9d3b81 2936 func (stream, "#%ld\t; 0x%.8lx",
9d82ec38
MGD		 2937 (long) (((value & 0x80000000L) != 0)
2938 ? value | ~0xffffffffL : value),
c1e26897 2939 value);
16980d0b
JB		 2940 break;
2941
2942 case 64:
2943 func (stream, "#0x%.8lx%.8lx", hival, value);
2944 break;
2945
2946 default:
2947 abort ();
2948 }
2949 }
2950 break;
2951
2952 case 'F':
2953 {
2954 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
2955 int num = (given >> 8) & 0x3;
2956
2957 if (!num)
2958 func (stream, "{d%d}", regno);
2959 else if (num + regno >= 32)
2960 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
2961 else
2962 func (stream, "{d%d-d%d}", regno, regno + num);
2963 }
2964 break;
7e8e6784 2965
16980d0b
JB		 2966
2967 case '0': case '1': case '2': case '3': case '4':
2968 case '5': case '6': case '7': case '8': case '9':
2969 {
2970 int width;
2971 unsigned long value;
2972
2973 c = arm_decode_bitfield (c, given, &value, &width);
2974
2975 switch (*c)
2976 {
2977 case 'r':
2978 func (stream, "%s", arm_regnames[value]);
2979 break;
2980 case 'd':
2981 func (stream, "%ld", value);
05413229 2982 value_in_comment = value;
16980d0b
JB		 2983 break;
2984 case 'e':
2985 func (stream, "%ld", (1ul << width) - value);
2986 break;
2987
2988 case 'S':
2989 case 'T':
2990 case 'U':
05413229 2991 /* Various width encodings. */
16980d0b
JB		 2992 {
2993 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
2994 int limit;
2995 unsigned low, high;
2996
2997 c++;
2998 if (*c >= '0' && *c <= '9')
2999 limit = *c - '0';
3000 else if (*c >= 'a' && *c <= 'f')
3001 limit = *c - 'a' + 10;
3002 else
3003 abort ();
3004 low = limit >> 2;
3005 high = limit & 3;
3006
3007 if (value < low || value > high)
3008 func (stream, "<illegal width %d>", base << value);
3009 else
3010 func (stream, "%d", base << value);
3011 }
3012 break;
3013 case 'R':
3014 if (given & (1 << 6))
3015 goto Q;
3016 /* FALLTHROUGH */
3017 case 'D':
3018 func (stream, "d%ld", value);
3019 break;
3020 case 'Q':
3021 Q:
3022 if (value & 1)
3023 func (stream, "<illegal reg q%ld.5>", value >> 1);
3024 else
3025 func (stream, "q%ld", value >> 1);
3026 break;
3027
3028 case '`':
3029 c++;
3030 if (value == 0)
3031 func (stream, "%c", *c);
3032 break;
3033 case '\'':
3034 c++;
3035 if (value == ((1ul << width) - 1))
3036 func (stream, "%c", *c);
3037 break;
3038 case '?':
fe56b6ce 3039 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 3040 c += 1 << width;
3041 break;
3042 default:
3043 abort ();
3044 }
3045 break;
3046
3047 default:
3048 abort ();
3049 }
3050 }
3051 }
3052 else
3053 func (stream, "%c", *c);
3054 }
05413229
NC		 3055
3056 if (value_in_comment > 32 || value_in_comment < -16)
3057 func (stream, "\t; 0x%lx", value_in_comment);
3058
e2efe87d
MGD		 3059 if (is_unpredictable)
3060 func (stream, UNPREDICTABLE_INSTRUCTION);
3061
16980d0b
JB		 3062 return TRUE;
3063 }
3064 }
3065 return FALSE;
3066}
3067
90ec0d68
MGD		 3068/* Return the name of a v7A special register. */
3069
3070static const char *
3071banked_regname (unsigned reg)
3072{
3073 switch (reg)
3074 {
3075 case 15: return "CPSR";
3076 case 32: return "R8_usr";
3077 case 33: return "R9_usr";
3078 case 34: return "R10_usr";
3079 case 35: return "R11_usr";
3080 case 36: return "R12_usr";
3081 case 37: return "SP_usr";
3082 case 38: return "LR_usr";
3083 case 40: return "R8_fiq";
3084 case 41: return "R9_fiq";
3085 case 42: return "R10_fiq";
3086 case 43: return "R11_fiq";
3087 case 44: return "R12_fiq";
3088 case 45: return "SP_fiq";
3089 case 46: return "LR_fiq";
3090 case 48: return "LR_irq";
3091 case 49: return "SP_irq";
3092 case 50: return "LR_svc";
3093 case 51: return "SP_svc";
3094 case 52: return "LR_abt";
3095 case 53: return "SP_abt";
3096 case 54: return "LR_und";
3097 case 55: return "SP_und";
3098 case 60: return "LR_mon";
3099 case 61: return "SP_mon";
3100 case 62: return "ELR_hyp";
3101 case 63: return "SP_hyp";
3102 case 79: return "SPSR";
3103 case 110: return "SPSR_fiq";
3104 case 112: return "SPSR_irq";
3105 case 114: return "SPSR_svc";
3106 case 116: return "SPSR_abt";
3107 case 118: return "SPSR_und";
3108 case 124: return "SPSR_mon";
3109 case 126: return "SPSR_hyp";
3110 default: return NULL;
3111 }
3112}
3113
e797f7e0
MGD		 3114/* Return the name of the DMB/DSB option. */
3115static const char *
3116data_barrier_option (unsigned option)
3117{
3118 switch (option & 0xf)
3119 {
3120 case 0xf: return "sy";
3121 case 0xe: return "st";
3122 case 0xd: return "ld";
3123 case 0xb: return "ish";
3124 case 0xa: return "ishst";
3125 case 0x9: return "ishld";
3126 case 0x7: return "un";
3127 case 0x6: return "unst";
3128 case 0x5: return "nshld";
3129 case 0x3: return "osh";
3130 case 0x2: return "oshst";
3131 case 0x1: return "oshld";
3132 default: return NULL;
3133 }
3134}
3135
4a5329c6
ZW		 3136/* Print one ARM instruction from PC on INFO->STREAM. */
3137
3138static void
3139print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 3140{
6b5d3a4d 3141 const struct opcode32 *insn;
6a51a8a8 3142 void *stream = info->stream;
6b5d3a4d 3143 fprintf_ftype func = info->fprintf_func;
b0e28b39 3144 struct arm_private_data *private_data = info->private_data;
252b5132 3145
16980d0b
JB		 3146 if (print_insn_coprocessor (pc, info, given, FALSE))
3147 return;
3148
3149 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 3150 return;
3151
252b5132
RH		 3152 for (insn = arm_opcodes; insn->assembler; insn++)
3153 {
0313a2b8
NC		 3154 if ((given & insn->mask) != insn->value)
3155 continue;
3156
b0e28b39 3157 if ((insn->arch & private_data->features.core) == 0)
0313a2b8
NC		 3158 continue;
3159
3160 /* Special case: an instruction with all bits set in the condition field
3161 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
3162 or by the catchall at the end of the table. */
3163 if ((given & 0xF0000000) != 0xF0000000
3164 || (insn->mask & 0xF0000000) == 0xF0000000
3165 || (insn->mask == 0 && insn->value == 0))
252b5132 3166 {
ff4a8d2b
NC		 3167 unsigned long u_reg = 16;
3168 unsigned long U_reg = 16;
ab8e2090 3169 bfd_boolean is_unpredictable = FALSE;
05413229 3170 signed long value_in_comment = 0;
6b5d3a4d 3171 const char *c;
b34976b6 3172
252b5132
RH		 3173 for (c = insn->assembler; *c; c++)
3174 {
3175 if (*c == '%')
3176 {
c1e26897
NC		 3177 bfd_boolean allow_unpredictable = FALSE;
3178
252b5132
RH		 3179 switch (*++c)
3180 {
3181 case '%':
3182 func (stream, "%%");
3183 break;
3184
3185 case 'a':
05413229 3186 value_in_comment = print_arm_address (pc, info, given);
62b3e311 3187 break;
252b5132 3188
62b3e311
PB		 3189 case 'P':
3190 /* Set P address bit and use normal address
3191 printing routine. */
c1e26897 3192 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 3193 break;
3194
c1e26897
NC		 3195 case 'S':
3196 allow_unpredictable = TRUE;
252b5132
RH		 3197 case 's':
3198 if ((given & 0x004f0000) == 0x004f0000)
3199 {
58efb6c0 3200 /* PC relative with immediate offset. */
f8b960bc 3201 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 3202
aefd8a40
NC		 3203 if (PRE_BIT_SET)
3204 {
26d97720
NS		 3205 /* Elide positive zero offset. */
3206 if (offset || NEGATIVE_BIT_SET)
3207 func (stream, "[pc, #%s%d]\t; ",
d908c8af 3208 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 3209 else
26d97720
NS		 3210 func (stream, "[pc]\t; ");
3211 if (NEGATIVE_BIT_SET)
3212 offset = -offset;
aefd8a40
NC		 3213 info->print_address_func (offset + pc + 8, info);
3214 }
3215 else
3216 {
26d97720
NS		 3217 /* Always show the offset. */
3218 func (stream, "[pc], #%s%d",
d908c8af 3219 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 3220 if (! allow_unpredictable)
3221 is_unpredictable = TRUE;
aefd8a40 3222 }
252b5132
RH		 3223 }
3224 else
3225 {
fe56b6ce
NC		 3226 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
3227
b34976b6 3228 func (stream, "[%s",
252b5132 3229 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 3230
c1e26897 3231 if (PRE_BIT_SET)
252b5132 3232 {
c1e26897 3233 if (IMMEDIATE_BIT_SET)
252b5132 3234 {
26d97720
NS		 3235 /* Elide offset for non-writeback
3236 positive zero. */
3237 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
3238 || offset)
3239 func (stream, ", #%s%d",
3240 NEGATIVE_BIT_SET ? "-" : "", offset);
3241
3242 if (NEGATIVE_BIT_SET)
3243 offset = -offset;
945ee430 3244
fe56b6ce 3245 value_in_comment = offset;
252b5132 3246 }
945ee430 3247 else
ff4a8d2b
NC		 3248 {
3249 /* Register Offset or Register Pre-Indexed. */
3250 func (stream, ", %s%s",
3251 NEGATIVE_BIT_SET ? "-" : "",
3252 arm_regnames[given & 0xf]);
3253
3254 /* Writing back to the register that is the source/
3255 destination of the load/store is unpredictable. */
3256 if (! allow_unpredictable
3257 && WRITEBACK_BIT_SET
3258 && ((given & 0xf) == ((given >> 12) & 0xf)))
3259 is_unpredictable = TRUE;
3260 }
252b5132 3261
b34976b6 3262 func (stream, "]%s",
c1e26897 3263 WRITEBACK_BIT_SET ? "!" : "");
252b5132 3264 }
945ee430 3265 else
252b5132 3266 {
c1e26897 3267 if (IMMEDIATE_BIT_SET)
252b5132 3268 {
945ee430 3269 /* Immediate Post-indexed. */
aefd8a40 3270 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 3271 func (stream, "], #%s%d",
3272 NEGATIVE_BIT_SET ? "-" : "", offset);
3273 if (NEGATIVE_BIT_SET)
3274 offset = -offset;
fe56b6ce 3275 value_in_comment = offset;
252b5132 3276 }
945ee430 3277 else
ff4a8d2b
NC		 3278 {
3279 /* Register Post-indexed. */
3280 func (stream, "], %s%s",
3281 NEGATIVE_BIT_SET ? "-" : "",
3282 arm_regnames[given & 0xf]);
3283
3284 /* Writing back to the register that is the source/
3285 destination of the load/store is unpredictable. */
3286 if (! allow_unpredictable
3287 && (given & 0xf) == ((given >> 12) & 0xf))
3288 is_unpredictable = TRUE;
3289 }
c1e26897 3290
07a28fab
NC		 3291 if (! allow_unpredictable)
3292 {
3293 /* Writeback is automatically implied by post- addressing.
3294 Setting the W bit is unnecessary and ARM specify it as
3295 being unpredictable. */
3296 if (WRITEBACK_BIT_SET
3297 /* Specifying the PC register as the post-indexed
3298 registers is also unpredictable. */
ab8e2090
NC		 3299 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
3300 is_unpredictable = TRUE;
07a28fab 3301 }
252b5132
RH		 3302 }
3303 }
3304 break;
b34976b6 3305
252b5132 3306 case 'b':
6b5d3a4d 3307 {
f8b960bc 3308 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
05413229 3309 info->print_address_func (disp * 4 + pc + 8, info);
6b5d3a4d 3310 }
252b5132
RH		 3311 break;
3312
3313 case 'c':
c22aaad1
PB		 3314 if (((given >> 28) & 0xf) != 0xe)
3315 func (stream, "%s",
3316 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 3317 break;
3318
3319 case 'm':
3320 {
3321 int started = 0;
3322 int reg;
3323
3324 func (stream, "{");
3325 for (reg = 0; reg < 16; reg++)
3326 if ((given & (1 << reg)) != 0)
3327 {
3328 if (started)
3329 func (stream, ", ");
3330 started = 1;
3331 func (stream, "%s", arm_regnames[reg]);
3332 }
3333 func (stream, "}");
ab8e2090
NC		 3334 if (! started)
3335 is_unpredictable = TRUE;
252b5132
RH		 3336 }
3337 break;
3338
37b37b2d 3339 case 'q':
78c66db8 3340 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 3341 break;
3342
252b5132
RH		 3343 case 'o':
3344 if ((given & 0x02000000) != 0)
3345 {
a415b1cd
JB		 3346 unsigned int rotate = (given & 0xf00) >> 7;
3347 unsigned int immed = (given & 0xff);
3348 unsigned int a, i;
3349
3350 a = (((immed << (32 - rotate))
3351 | (immed >> rotate)) & 0xffffffff);
3352 /* If there is another encoding with smaller rotate,
3353 the rotate should be specified directly. */
3354 for (i = 0; i < 32; i += 2)
3355 if ((a << i | a >> (32 - i)) <= 0xff)
3356 break;
3357
3358 if (i != rotate)
3359 func (stream, "#%d, %d", immed, rotate);
3360 else
3361 func (stream, "#%d", a);
3362 value_in_comment = a;
252b5132
RH		 3363 }
3364 else
78c66db8 3365 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 3366 break;
3367
3368 case 'p':
3369 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40
NC		 3370 {
3371 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
3372 mechanism for setting PSR flag bits. They are
3373 obsolete in V6 onwards. */
b0e28b39 3374 if ((private_data->features.core & ARM_EXT_V6) == 0)
aefd8a40
NC		 3375 func (stream, "p");
3376 }
252b5132
RH		 3377 break;
3378
3379 case 't':
3380 if ((given & 0x01200000) == 0x00200000)
3381 func (stream, "t");
3382 break;
3383
252b5132 3384 case 'A':
05413229
NC		 3385 {
3386 int offset = given & 0xff;
f02232aa 3387
05413229 3388 value_in_comment = offset * 4;
c1e26897 3389 if (NEGATIVE_BIT_SET)
05413229 3390 value_in_comment = - value_in_comment;
f02232aa 3391
05413229 3392 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 3393
c1e26897 3394 if (PRE_BIT_SET)
05413229
NC		 3395 {
3396 if (offset)
fe56b6ce 3397 func (stream, ", #%d]%s",
d908c8af 3398 (int) value_in_comment,
c1e26897 3399 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 3400 else
3401 func (stream, "]");
3402 }
3403 else
3404 {
3405 func (stream, "]");
f02232aa 3406
c1e26897 3407 if (WRITEBACK_BIT_SET)
05413229
NC		 3408 {
3409 if (offset)
d908c8af 3410 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 3411 }
3412 else
fe56b6ce 3413 {
d908c8af 3414 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 3415 value_in_comment = offset;
3416 }
05413229
NC		 3417 }
3418 }
252b5132
RH		 3419 break;
3420
077b8428
NC		 3421 case 'B':
3422 /* Print ARM V5 BLX(1) address: pc+25 bits. */
3423 {
3424 bfd_vma address;
3425 bfd_vma offset = 0;
b34976b6 3426
c1e26897 3427 if (! NEGATIVE_BIT_SET)
077b8428
NC		 3428 /* Is signed, hi bits should be ones. */
3429 offset = (-1) ^ 0x00ffffff;
3430
3431 /* Offset is (SignExtend(offset field)<<2). */
3432 offset += given & 0x00ffffff;
3433 offset <<= 2;
3434 address = offset + pc + 8;
b34976b6 3435
8f06b2d8
PB		 3436 if (given & 0x01000000)
3437 /* H bit allows addressing to 2-byte boundaries. */
3438 address += 2;
b1ee46c5 3439
8f06b2d8 3440 info->print_address_func (address, info);
b1ee46c5 3441 }
b1ee46c5
AH		 3442 break;
3443
252b5132 3444 case 'C':
90ec0d68
MGD		 3445 if ((given & 0x02000200) == 0x200)
3446 {
3447 const char * name;
3448 unsigned sysm = (given & 0x004f0000) >> 16;
3449
3450 sysm |= (given & 0x300) >> 4;
3451 name = banked_regname (sysm);
3452
3453 if (name != NULL)
3454 func (stream, "%s", name);
3455 else
d908c8af 3456 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 3457 }
3458 else
3459 {
3460 func (stream, "%cPSR_",
3461 (given & 0x00400000) ? 'S' : 'C');
3462 if (given & 0x80000)
3463 func (stream, "f");
3464 if (given & 0x40000)
3465 func (stream, "s");
3466 if (given & 0x20000)
3467 func (stream, "x");
3468 if (given & 0x10000)
3469 func (stream, "c");
3470 }
252b5132
RH		 3471 break;
3472
62b3e311 3473 case 'U':
52e7f43d 3474 if ((given & 0xf0) == 0x60)
62b3e311 3475 {
52e7f43d
RE		 3476 switch (given & 0xf)
3477 {
3478 case 0xf: func (stream, "sy"); break;
3479 default:
3480 func (stream, "#%d", (int) given & 0xf);
3481 break;
3482 }
3483 }
3484 else
3485 {
e797f7e0
MGD		 3486 const char * opt = data_barrier_option (given & 0xf);
3487 if (opt != NULL)
3488 func (stream, "%s", opt);
3489 else
52e7f43d 3490 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 3491 }
3492 break;
3493
b34976b6 3494 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 3495 case '5': case '6': case '7': case '8': case '9':
3496 {
16980d0b
JB		 3497 int width;
3498 unsigned long value;
252b5132 3499
16980d0b
JB		 3500 c = arm_decode_bitfield (c, given, &value, &width);
3501
252b5132
RH		 3502 switch (*c)
3503 {
ab8e2090
NC		 3504 case 'R':
3505 if (value == 15)
3506 is_unpredictable = TRUE;
3507 /* Fall through. */
16980d0b 3508 case 'r':
9eb6c0f1
MGD		 3509 case 'T':
3510 /* We want register + 1 when decoding T. */
3511 if (*c == 'T')
3512 ++value;
3513
ff4a8d2b
NC		 3514 if (c[1] == 'u')
3515 {
3516 /* Eat the 'u' character. */
3517 ++ c;
3518
3519 if (u_reg == value)
3520 is_unpredictable = TRUE;
3521 u_reg = value;
3522 }
3523 if (c[1] == 'U')
3524 {
3525 /* Eat the 'U' character. */
3526 ++ c;
3527
3528 if (U_reg == value)
3529 is_unpredictable = TRUE;
3530 U_reg = value;
3531 }
16980d0b
JB		 3532 func (stream, "%s", arm_regnames[value]);
3533 break;
3534 case 'd':
3535 func (stream, "%ld", value);
05413229 3536 value_in_comment = value;
16980d0b
JB		 3537 break;
3538 case 'b':
3539 func (stream, "%ld", value * 8);
05413229 3540 value_in_comment = value * 8;
16980d0b
JB		 3541 break;
3542 case 'W':
3543 func (stream, "%ld", value + 1);
05413229 3544 value_in_comment = value + 1;
16980d0b
JB		 3545 break;
3546 case 'x':
3547 func (stream, "0x%08lx", value);
3548
3549 /* Some SWI instructions have special
3550 meanings. */
3551 if ((given & 0x0fffffff) == 0x0FF00000)
3552 func (stream, "\t; IMB");
3553 else if ((given & 0x0fffffff) == 0x0FF00001)
3554 func (stream, "\t; IMBRange");
3555 break;
3556 case 'X':
3557 func (stream, "%01lx", value & 0xf);
05413229 3558 value_in_comment = value;
252b5132
RH		 3559 break;
3560 case '`':
3561 c++;
16980d0b 3562 if (value == 0)
252b5132
RH		 3563 func (stream, "%c", *c);
3564 break;
3565 case '\'':
3566 c++;
16980d0b 3567 if (value == ((1ul << width) - 1))
252b5132
RH		 3568 func (stream, "%c", *c);
3569 break;
3570 case '?':
fe56b6ce 3571 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 3572 c += 1 << width;
252b5132
RH		 3573 break;
3574 default:
3575 abort ();
3576 }
3577 break;
3578
0dd132b6
NC		 3579 case 'e':
3580 {
3581 int imm;
3582
3583 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
3584 func (stream, "%d", imm);
fe56b6ce 3585 value_in_comment = imm;
0dd132b6
NC		 3586 }
3587 break;
3588
0a003adc
ZW		 3589 case 'E':
3590 /* LSB and WIDTH fields of BFI or BFC. The machine-
3591 language instruction encodes LSB and MSB. */
3592 {
3593 long msb = (given & 0x001f0000) >> 16;
3594 long lsb = (given & 0x00000f80) >> 7;
91d6fa6a 3595 long w = msb - lsb + 1;
fe56b6ce 3596
91d6fa6a
NC		 3597 if (w > 0)
3598 func (stream, "#%lu, #%lu", lsb, w);
0a003adc
ZW		 3599 else
3600 func (stream, "(invalid: %lu:%lu)", lsb, msb);
3601 }
3602 break;
3603
90ec0d68
MGD		 3604 case 'R':
3605 /* Get the PSR/banked register name. */
3606 {
3607 const char * name;
3608 unsigned sysm = (given & 0x004f0000) >> 16;
3609
3610 sysm |= (given & 0x300) >> 4;
3611 name = banked_regname (sysm);
3612
3613 if (name != NULL)
3614 func (stream, "%s", name);
3615 else
d908c8af 3616 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 3617 }
3618 break;
3619
0a003adc
ZW		 3620 case 'V':
3621 /* 16-bit unsigned immediate from a MOVT or MOVW
3622 instruction, encoded in bits 0:11 and 15:19. */
3623 {
3624 long hi = (given & 0x000f0000) >> 4;
3625 long lo = (given & 0x00000fff);
3626 long imm16 = hi | lo;
fe56b6ce
NC		 3627
3628 func (stream, "#%lu", imm16);
3629 value_in_comment = imm16;
0a003adc
ZW		 3630 }
3631 break;
3632
252b5132
RH		 3633 default:
3634 abort ();
3635 }
3636 }
3637 }
3638 else
3639 func (stream, "%c", *c);
3640 }
05413229
NC		 3641
3642 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 3643 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 3644
3645 if (is_unpredictable)
3646 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 3647
4a5329c6 3648 return;
252b5132
RH		 3649 }
3650 }
3651 abort ();
3652}
3653
4a5329c6 3654/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 3655
4a5329c6
ZW		 3656static void
3657print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 3658{
6b5d3a4d 3659 const struct opcode16 *insn;
6a51a8a8
AM		 3660 void *stream = info->stream;
3661 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 3662
3663 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 3664 if ((given & insn->mask) == insn->value)
3665 {
05413229 3666 signed long value_in_comment = 0;
6b5d3a4d 3667 const char *c = insn->assembler;
05413229 3668
c19d1205
ZW		 3669 for (; *c; c++)
3670 {
3671 int domaskpc = 0;
3672 int domasklr = 0;
3673
3674 if (*c != '%')
3675 {
3676 func (stream, "%c", *c);
3677 continue;
3678 }
252b5132 3679
c19d1205
ZW		 3680 switch (*++c)
3681 {
3682 case '%':
3683 func (stream, "%%");
3684 break;
b34976b6 3685
c22aaad1
PB		 3686 case 'c':
3687 if (ifthen_state)
3688 func (stream, "%s", arm_conditional[IFTHEN_COND]);
3689 break;
3690
3691 case 'C':
3692 if (ifthen_state)
3693 func (stream, "%s", arm_conditional[IFTHEN_COND]);
3694 else
3695 func (stream, "s");
3696 break;
3697
3698 case 'I':
3699 {
3700 unsigned int tmp;
3701
3702 ifthen_next_state = given & 0xff;
3703 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
3704 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
3705 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
3706 }
3707 break;
3708
3709 case 'x':
3710 if (ifthen_next_state)
3711 func (stream, "\t; unpredictable branch in IT block\n");
3712 break;
3713
3714 case 'X':
3715 if (ifthen_state)
3716 func (stream, "\t; unpredictable <IT:%s>",
3717 arm_conditional[IFTHEN_COND]);
3718 break;
3719
c19d1205
ZW		 3720 case 'S':
3721 {
3722 long reg;
3723
3724 reg = (given >> 3) & 0x7;
3725 if (given & (1 << 6))
3726 reg += 8;
4f3c3dbb 3727
c19d1205
ZW		 3728 func (stream, "%s", arm_regnames[reg]);
3729 }
3730 break;
baf0cc5e 3731
c19d1205 3732 case 'D':
4f3c3dbb 3733 {
c19d1205
ZW		 3734 long reg;
3735
3736 reg = given & 0x7;
3737 if (given & (1 << 7))
3738 reg += 8;
3739
3740 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 3741 }
c19d1205
ZW		 3742 break;
3743
3744 case 'N':
3745 if (given & (1 << 8))
3746 domasklr = 1;
3747 /* Fall through. */
3748 case 'O':
3749 if (*c == 'O' && (given & (1 << 8)))
3750 domaskpc = 1;
3751 /* Fall through. */
3752 case 'M':
3753 {
3754 int started = 0;
3755 int reg;
3756
3757 func (stream, "{");
3758
3759 /* It would be nice if we could spot
3760 ranges, and generate the rS-rE format: */
3761 for (reg = 0; (reg < 8); reg++)
3762 if ((given & (1 << reg)) != 0)
3763 {
3764 if (started)
3765 func (stream, ", ");
3766 started = 1;
3767 func (stream, "%s", arm_regnames[reg]);
3768 }
3769
3770 if (domasklr)
3771 {
3772 if (started)
3773 func (stream, ", ");
3774 started = 1;
d908c8af 3775 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 3776 }
3777
3778 if (domaskpc)
3779 {
3780 if (started)
3781 func (stream, ", ");
d908c8af 3782 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 3783 }
3784
3785 func (stream, "}");
3786 }
3787 break;
3788
4547cb56
NC		 3789 case 'W':
3790 /* Print writeback indicator for a LDMIA. We are doing a
3791 writeback if the base register is not in the register
3792 mask. */
3793 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
3794 func (stream, "!");
3795 break;
3796
c19d1205
ZW		 3797 case 'b':
3798 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
3799 {
3800 bfd_vma address = (pc + 4
3801 + ((given & 0x00f8) >> 2)
3802 + ((given & 0x0200) >> 3));
3803 info->print_address_func (address, info);
3804 }
3805 break;
3806
3807 case 's':
3808 /* Right shift immediate -- bits 6..10; 1-31 print
3809 as themselves, 0 prints as 32. */
3810 {
3811 long imm = (given & 0x07c0) >> 6;
3812 if (imm == 0)
3813 imm = 32;
0fd3a477 3814 func (stream, "#%ld", imm);
c19d1205
ZW		 3815 }
3816 break;
3817
3818 case '0': case '1': case '2': case '3': case '4':
3819 case '5': case '6': case '7': case '8': case '9':
3820 {
3821 int bitstart = *c++ - '0';
3822 int bitend = 0;
3823
3824 while (*c >= '0' && *c <= '9')
3825 bitstart = (bitstart * 10) + *c++ - '0';
3826
3827 switch (*c)
3828 {
3829 case '-':
3830 {
f8b960bc 3831 bfd_vma reg;
c19d1205
ZW		 3832
3833 c++;
3834 while (*c >= '0' && *c <= '9')
3835 bitend = (bitend * 10) + *c++ - '0';
3836 if (!bitend)
3837 abort ();
3838 reg = given >> bitstart;
3839 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 3840
c19d1205
ZW		 3841 switch (*c)
3842 {
3843 case 'r':
3844 func (stream, "%s", arm_regnames[reg]);
3845 break;
3846
3847 case 'd':
d908c8af 3848 func (stream, "%ld", (long) reg);
05413229 3849 value_in_comment = reg;
c19d1205
ZW		 3850 break;
3851
3852 case 'H':
d908c8af 3853 func (stream, "%ld", (long) (reg << 1));
05413229 3854 value_in_comment = reg << 1;
c19d1205
ZW		 3855 break;
3856
3857 case 'W':
d908c8af 3858 func (stream, "%ld", (long) (reg << 2));
05413229 3859 value_in_comment = reg << 2;
c19d1205
ZW		 3860 break;
3861
3862 case 'a':
3863 /* PC-relative address -- the bottom two
3864 bits of the address are dropped
3865 before the calculation. */
3866 info->print_address_func
3867 (((pc + 4) & ~3) + (reg << 2), info);
05413229 3868 value_in_comment = 0;
c19d1205
ZW		 3869 break;
3870
3871 case 'x':
d908c8af 3872 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 3873 break;
3874
c19d1205
ZW		 3875 case 'B':
3876 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6b5d3a4d 3877 info->print_address_func (reg * 2 + pc + 4, info);
05413229 3878 value_in_comment = 0;
c19d1205
ZW		 3879 break;
3880
3881 case 'c':
c22aaad1 3882 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 3883 break;
3884
3885 default:
3886 abort ();
3887 }
3888 }
3889 break;
3890
3891 case '\'':
3892 c++;
3893 if ((given & (1 << bitstart)) != 0)
3894 func (stream, "%c", *c);
3895 break;
3896
3897 case '?':
3898 ++c;
3899 if ((given & (1 << bitstart)) != 0)
3900 func (stream, "%c", *c++);
3901 else
3902 func (stream, "%c", *++c);
3903 break;
3904
3905 default:
3906 abort ();
3907 }
3908 }
3909 break;
3910
3911 default:
3912 abort ();
3913 }
3914 }
05413229
NC		 3915
3916 if (value_in_comment > 32 || value_in_comment < -16)
3917 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 3918 return;
c19d1205
ZW		 3919 }
3920
3921 /* No match. */
3922 abort ();
3923}
3924
62b3e311 3925/* Return the name of an V7M special register. */
fe56b6ce 3926
62b3e311
PB		 3927static const char *
3928psr_name (int regno)
3929{
3930 switch (regno)
3931 {
3932 case 0: return "APSR";
3933 case 1: return "IAPSR";
3934 case 2: return "EAPSR";
3935 case 3: return "PSR";
3936 case 5: return "IPSR";
3937 case 6: return "EPSR";
3938 case 7: return "IEPSR";
3939 case 8: return "MSP";
3940 case 9: return "PSP";
3941 case 16: return "PRIMASK";
3942 case 17: return "BASEPRI";
00bbc0bd 3943 case 18: return "BASEPRI_MAX";
62b3e311
PB		 3944 case 19: return "FAULTMASK";
3945 case 20: return "CONTROL";
3946 default: return "<unknown>";
3947 }
3948}
3949
4a5329c6
ZW		 3950/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
3951
3952static void
3953print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 3954{
6b5d3a4d 3955 const struct opcode32 *insn;
c19d1205
ZW		 3956 void *stream = info->stream;
3957 fprintf_ftype func = info->fprintf_func;
3958
16980d0b
JB		 3959 if (print_insn_coprocessor (pc, info, given, TRUE))
3960 return;
3961
3962 if (print_insn_neon (info, given, TRUE))
8f06b2d8
PB		 3963 return;
3964
c19d1205
ZW		 3965 for (insn = thumb32_opcodes; insn->assembler; insn++)
3966 if ((given & insn->mask) == insn->value)
3967 {
ff4a8d2b 3968 bfd_boolean is_unpredictable = FALSE;
05413229 3969 signed long value_in_comment = 0;
6b5d3a4d 3970 const char *c = insn->assembler;
05413229 3971
c19d1205
ZW		 3972 for (; *c; c++)
3973 {
3974 if (*c != '%')
3975 {
3976 func (stream, "%c", *c);
3977 continue;
3978 }
3979
3980 switch (*++c)
3981 {
3982 case '%':
3983 func (stream, "%%");
3984 break;
3985
c22aaad1
PB		 3986 case 'c':
3987 if (ifthen_state)
3988 func (stream, "%s", arm_conditional[IFTHEN_COND]);
3989 break;
3990
3991 case 'x':
3992 if (ifthen_next_state)
3993 func (stream, "\t; unpredictable branch in IT block\n");
3994 break;
3995
3996 case 'X':
3997 if (ifthen_state)
3998 func (stream, "\t; unpredictable <IT:%s>",
3999 arm_conditional[IFTHEN_COND]);
4000 break;
4001
c19d1205
ZW		 4002 case 'I':
4003 {
4004 unsigned int imm12 = 0;
fe56b6ce 4005
c19d1205
ZW		 4006 imm12 |= (given & 0x000000ffu);
4007 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 4008 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 4009 func (stream, "#%u", imm12);
4010 value_in_comment = imm12;
c19d1205
ZW		 4011 }
4012 break;
4013
4014 case 'M':
4015 {
4016 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 4017
c19d1205
ZW		 4018 bits |= (given & 0x000000ffu);
4019 bits |= (given & 0x00007000u) >> 4;
4020 bits |= (given & 0x04000000u) >> 15;
4021 imm8 = (bits & 0x0ff);
4022 mod = (bits & 0xf00) >> 8;
4023 switch (mod)
4024 {
4025 case 0: imm = imm8; break;
c1e26897
NC		 4026 case 1: imm = ((imm8 << 16) | imm8); break;
4027 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
4028 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 4029 default:
4030 mod = (bits & 0xf80) >> 7;
4031 imm8 = (bits & 0x07f) | 0x80;
4032 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
4033 }
fe56b6ce
NC		 4034 func (stream, "#%u", imm);
4035 value_in_comment = imm;
c19d1205
ZW		 4036 }
4037 break;
4038
4039 case 'J':
4040 {
4041 unsigned int imm = 0;
fe56b6ce 4042
c19d1205
ZW		 4043 imm |= (given & 0x000000ffu);
4044 imm |= (given & 0x00007000u) >> 4;
4045 imm |= (given & 0x04000000u) >> 15;
4046 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 4047 func (stream, "#%u", imm);
4048 value_in_comment = imm;
c19d1205
ZW		 4049 }
4050 break;
4051
4052 case 'K':
4053 {
4054 unsigned int imm = 0;
fe56b6ce 4055
c19d1205
ZW		 4056 imm |= (given & 0x000f0000u) >> 16;
4057 imm |= (given & 0x00000ff0u) >> 0;
4058 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 4059 func (stream, "#%u", imm);
4060 value_in_comment = imm;
c19d1205
ZW		 4061 }
4062 break;
4063
74db7efb
NC		 4064 case 'H':
4065 {
4066 unsigned int imm = 0;
4067
4068 imm |= (given & 0x000f0000u) >> 4;
4069 imm |= (given & 0x00000fffu) >> 0;
4070 func (stream, "#%u", imm);
4071 value_in_comment = imm;
4072 }
4073 break;
4074
90ec0d68
MGD		 4075 case 'V':
4076 {
4077 unsigned int imm = 0;
4078
4079 imm |= (given & 0x00000fffu);
4080 imm |= (given & 0x000f0000u) >> 4;
4081 func (stream, "#%u", imm);
4082 value_in_comment = imm;
4083 }
4084 break;
4085
c19d1205
ZW		 4086 case 'S':
4087 {
4088 unsigned int reg = (given & 0x0000000fu);
4089 unsigned int stp = (given & 0x00000030u) >> 4;
4090 unsigned int imm = 0;
4091 imm |= (given & 0x000000c0u) >> 6;
4092 imm |= (given & 0x00007000u) >> 10;
4093
4094 func (stream, "%s", arm_regnames[reg]);
4095 switch (stp)
4096 {
4097 case 0:
4098 if (imm > 0)
4099 func (stream, ", lsl #%u", imm);
4100 break;
4101
4102 case 1:
4103 if (imm == 0)
4104 imm = 32;
4105 func (stream, ", lsr #%u", imm);
4106 break;
4107
4108 case 2:
4109 if (imm == 0)
4110 imm = 32;
4111 func (stream, ", asr #%u", imm);
4112 break;
4113
4114 case 3:
4115 if (imm == 0)
4116 func (stream, ", rrx");
4117 else
4118 func (stream, ", ror #%u", imm);
4119 }
4120 }
4121 break;
4122
4123 case 'a':
4124 {
4125 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 4126 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 4127 unsigned int op = (given & 0x00000f00) >> 8;
4128 unsigned int i12 = (given & 0x00000fff);
4129 unsigned int i8 = (given & 0x000000ff);
4130 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 4131 bfd_vma offset = 0;
c19d1205
ZW		 4132
4133 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 4134 if (U) /* 12-bit positive immediate offset. */
4135 {
4136 offset = i12;
4137 if (Rn != 15)
4138 value_in_comment = offset;
4139 }
4140 else if (Rn == 15) /* 12-bit negative immediate offset. */
4141 offset = - (int) i12;
4142 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 4143 {
4144 unsigned int Rm = (i8 & 0x0f);
4145 unsigned int sh = (i8 & 0x30) >> 4;
05413229 4146
c19d1205
ZW		 4147 func (stream, ", %s", arm_regnames[Rm]);
4148 if (sh)
4149 func (stream, ", lsl #%u", sh);
4150 func (stream, "]");
4151 break;
4152 }
4153 else switch (op)
4154 {
05413229 4155 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 4156 offset = i8;
4157 break;
4158
05413229 4159 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 4160 offset = -i8;
4161 break;
4162
05413229 4163 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 4164 offset = i8;
4165 writeback = TRUE;
4166 break;
4167
05413229 4168 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 4169 offset = -i8;
4170 writeback = TRUE;
4171 break;
4172
05413229 4173 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 4174 offset = i8;
4175 postind = TRUE;
4176 break;
4177
05413229 4178 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 4179 offset = -i8;
4180 postind = TRUE;
4181 break;
4182
4183 default:
4184 func (stream, ", <undefined>]");
4185 goto skip;
4186 }
4187
4188 if (postind)
d908c8af 4189 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 4190 else
4191 {
4192 if (offset)
d908c8af 4193 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 4194 func (stream, writeback ? "]!" : "]");
4195 }
4196
4197 if (Rn == 15)
4198 {
4199 func (stream, "\t; ");
4200 info->print_address_func (((pc + 4) & ~3) + offset, info);
4201 }
4202 }
4203 skip:
4204 break;
4205
4206 case 'A':
4207 {
c1e26897
NC		 4208 unsigned int U = ! NEGATIVE_BIT_SET;
4209 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 4210 unsigned int Rn = (given & 0x000f0000) >> 16;
4211 unsigned int off = (given & 0x000000ff);
4212
4213 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 4214
4215 if (PRE_BIT_SET)
c19d1205
ZW		 4216 {
4217 if (off || !U)
05413229
NC		 4218 {
4219 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
4220 value_in_comment = off * 4 * U ? 1 : -1;
4221 }
c19d1205
ZW		 4222 func (stream, "]");
4223 if (W)
4224 func (stream, "!");
4225 }
4226 else
4227 {
4228 func (stream, "], ");
4229 if (W)
05413229
NC		 4230 {
4231 func (stream, "#%c%u", U ? '+' : '-', off * 4);
4232 value_in_comment = off * 4 * U ? 1 : -1;
4233 }
c19d1205 4234 else
fe56b6ce
NC		 4235 {
4236 func (stream, "{%u}", off);
4237 value_in_comment = off;
4238 }
c19d1205
ZW		 4239 }
4240 }
4241 break;
4242
4243 case 'w':
4244 {
4245 unsigned int Sbit = (given & 0x01000000) >> 24;
4246 unsigned int type = (given & 0x00600000) >> 21;
05413229 4247
c19d1205
ZW		 4248 switch (type)
4249 {
4250 case 0: func (stream, Sbit ? "sb" : "b"); break;
4251 case 1: func (stream, Sbit ? "sh" : "h"); break;
4252 case 2:
4253 if (Sbit)
4254 func (stream, "??");
4255 break;
4256 case 3:
4257 func (stream, "??");
4258 break;
4259 }
4260 }
4261 break;
4262
4263 case 'm':
4264 {
4265 int started = 0;
4266 int reg;
4267
4268 func (stream, "{");
4269 for (reg = 0; reg < 16; reg++)
4270 if ((given & (1 << reg)) != 0)
4271 {
4272 if (started)
4273 func (stream, ", ");
4274 started = 1;
4275 func (stream, "%s", arm_regnames[reg]);
4276 }
4277 func (stream, "}");
4278 }
4279 break;
4280
4281 case 'E':
4282 {
4283 unsigned int msb = (given & 0x0000001f);
4284 unsigned int lsb = 0;
fe56b6ce 4285
c19d1205
ZW		 4286 lsb |= (given & 0x000000c0u) >> 6;
4287 lsb |= (given & 0x00007000u) >> 10;
4288 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
4289 }
4290 break;
4291
4292 case 'F':
4293 {
4294 unsigned int width = (given & 0x0000001f) + 1;
4295 unsigned int lsb = 0;
fe56b6ce 4296
c19d1205
ZW		 4297 lsb |= (given & 0x000000c0u) >> 6;
4298 lsb |= (given & 0x00007000u) >> 10;
4299 func (stream, "#%u, #%u", lsb, width);
4300 }
4301 break;
4302
4303 case 'b':
4304 {
4305 unsigned int S = (given & 0x04000000u) >> 26;
4306 unsigned int J1 = (given & 0x00002000u) >> 13;
4307 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 4308 bfd_vma offset = 0;
c19d1205
ZW		 4309
4310 offset |= !S << 20;
4311 offset |= J2 << 19;
4312 offset |= J1 << 18;
4313 offset |= (given & 0x003f0000) >> 4;
4314 offset |= (given & 0x000007ff) << 1;
4315 offset -= (1 << 20);
4316
4317 info->print_address_func (pc + 4 + offset, info);
4318 }
4319 break;
4320
4321 case 'B':
4322 {
4323 unsigned int S = (given & 0x04000000u) >> 26;
4324 unsigned int I1 = (given & 0x00002000u) >> 13;
4325 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 4326 bfd_vma offset = 0;
c19d1205
ZW		 4327
4328 offset |= !S << 24;
4329 offset |= !(I1 ^ S) << 23;
4330 offset |= !(I2 ^ S) << 22;
4331 offset |= (given & 0x03ff0000u) >> 4;
4332 offset |= (given & 0x000007ffu) << 1;
4333 offset -= (1 << 24);
36b0c57d 4334 offset += pc + 4;
c19d1205 4335
36b0c57d
PB		 4336 /* BLX target addresses are always word aligned. */
4337 if ((given & 0x00001000u) == 0)
4338 offset &= ~2u;
4339
4340 info->print_address_func (offset, info);
c19d1205
ZW		 4341 }
4342 break;
4343
4344 case 's':
4345 {
4346 unsigned int shift = 0;
fe56b6ce 4347
c19d1205
ZW		 4348 shift |= (given & 0x000000c0u) >> 6;
4349 shift |= (given & 0x00007000u) >> 10;
c1e26897 4350 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 4351 func (stream, ", asr #%u", shift);
4352 else if (shift)
4353 func (stream, ", lsl #%u", shift);
4354 /* else print nothing - lsl #0 */
4355 }
4356 break;
4357
4358 case 'R':
4359 {
4360 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 4361
c19d1205
ZW		 4362 if (rot)
4363 func (stream, ", ror #%u", rot * 8);
4364 }
4365 break;
4366
62b3e311 4367 case 'U':
52e7f43d 4368 if ((given & 0xf0) == 0x60)
62b3e311 4369 {
52e7f43d
RE		 4370 switch (given & 0xf)
4371 {
4372 case 0xf: func (stream, "sy"); break;
4373 default:
4374 func (stream, "#%d", (int) given & 0xf);
4375 break;
4376 }
62b3e311 4377 }
52e7f43d
RE		 4378 else
4379 {
e797f7e0
MGD		 4380 const char * opt = data_barrier_option (given & 0xf);
4381 if (opt != NULL)
4382 func (stream, "%s", opt);
4383 else
4384 func (stream, "#%d", (int) given & 0xf);
52e7f43d 4385 }
62b3e311
PB		 4386 break;
4387
4388 case 'C':
4389 if ((given & 0xff) == 0)
4390 {
4391 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
4392 if (given & 0x800)
4393 func (stream, "f");
4394 if (given & 0x400)
4395 func (stream, "s");
4396 if (given & 0x200)
4397 func (stream, "x");
4398 if (given & 0x100)
4399 func (stream, "c");
4400 }
90ec0d68
MGD		 4401 else if ((given & 0x20) == 0x20)
4402 {
4403 char const* name;
4404 unsigned sysm = (given & 0xf00) >> 8;
4405
4406 sysm |= (given & 0x30);
4407 sysm |= (given & 0x00100000) >> 14;
4408 name = banked_regname (sysm);
4409
4410 if (name != NULL)
4411 func (stream, "%s", name);
4412 else
d908c8af 4413 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 4414 }
62b3e311
PB		 4415 else
4416 {
d908c8af 4417 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 4418 }
4419 break;
4420
4421 case 'D':
90ec0d68
MGD		 4422 if (((given & 0xff) == 0)
4423 || ((given & 0x20) == 0x20))
4424 {
4425 char const* name;
4426 unsigned sm = (given & 0xf0000) >> 16;
4427
4428 sm |= (given & 0x30);
4429 sm |= (given & 0x00100000) >> 14;
4430 name = banked_regname (sm);
4431
4432 if (name != NULL)
4433 func (stream, "%s", name);
4434 else
d908c8af 4435 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 4436 }
62b3e311 4437 else
d908c8af 4438 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 4439 break;
4440
c19d1205
ZW		 4441 case '0': case '1': case '2': case '3': case '4':
4442 case '5': case '6': case '7': case '8': case '9':
4443 {
16980d0b
JB		 4444 int width;
4445 unsigned long val;
c19d1205 4446
16980d0b
JB		 4447 c = arm_decode_bitfield (c, given, &val, &width);
4448
c19d1205
ZW		 4449 switch (*c)
4450 {
05413229
NC		 4451 case 'd':
4452 func (stream, "%lu", val);
4453 value_in_comment = val;
4454 break;
ff4a8d2b 4455
05413229
NC		 4456 case 'W':
4457 func (stream, "%lu", val * 4);
4458 value_in_comment = val * 4;
4459 break;
ff4a8d2b 4460
dd5181d5
KT		 4461 case 'S':
4462 if (val == 13)
4463 is_unpredictable = TRUE;
4464 /* Fall through. */
ff4a8d2b
NC		 4465 case 'R':
4466 if (val == 15)
4467 is_unpredictable = TRUE;
4468 /* Fall through. */
4469 case 'r':
4470 func (stream, "%s", arm_regnames[val]);
4471 break;
c19d1205
ZW		 4472
4473 case 'c':
c22aaad1 4474 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 4475 break;
4476
4477 case '\'':
c19d1205 4478 c++;
16980d0b
JB		 4479 if (val == ((1ul << width) - 1))
4480 func (stream, "%c", *c);
c19d1205
ZW		 4481 break;
4482
4483 case '`':
c19d1205 4484 c++;
16980d0b
JB		 4485 if (val == 0)
4486 func (stream, "%c", *c);
c19d1205
ZW		 4487 break;
4488
4489 case '?':
fe56b6ce 4490 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 4491 c += 1 << width;
c19d1205 4492 break;
0bb027fd
RR		 4493
4494 case 'x':
4495 func (stream, "0x%lx", val & 0xffffffffUL);
4496 break;
c19d1205
ZW		 4497
4498 default:
4499 abort ();
4500 }
4501 }
4502 break;
4503
32a94698
NC		 4504 case 'L':
4505 /* PR binutils/12534
4506 If we have a PC relative offset in an LDRD or STRD
4507 instructions then display the decoded address. */
4508 if (((given >> 16) & 0xf) == 0xf)
4509 {
4510 bfd_vma offset = (given & 0xff) * 4;
4511
4512 if ((given & (1 << 23)) == 0)
4513 offset = - offset;
4514 func (stream, "\t; ");
4515 info->print_address_func ((pc & ~3) + 4 + offset, info);
4516 }
4517 break;
4518
c19d1205
ZW		 4519 default:
4520 abort ();
4521 }
4522 }
05413229
NC		 4523
4524 if (value_in_comment > 32 || value_in_comment < -16)
4525 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 4526
4527 if (is_unpredictable)
4528 func (stream, UNPREDICTABLE_INSTRUCTION);
4529
4a5329c6 4530 return;
c19d1205 4531 }
252b5132 4532
58efb6c0 4533 /* No match. */
252b5132
RH		 4534 abort ();
4535}
4536
e821645d
DJ		 4537/* Print data bytes on INFO->STREAM. */
4538
4539static void
fe56b6ce
NC		 4540print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
4541 struct disassemble_info *info,
e821645d
DJ		 4542 long given)
4543{
4544 switch (info->bytes_per_chunk)
4545 {
4546 case 1:
4547 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
4548 break;
4549 case 2:
4550 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
4551 break;
4552 case 4:
4553 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
4554 break;
4555 default:
4556 abort ();
4557 }
4558}
4559
22a398e1 4560/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 4561 being displayed in symbol relative addresses.
4562
4563 Also disallow private symbol, with __tagsym$$ prefix,
4564 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 4565
4566bfd_boolean
4567arm_symbol_is_valid (asymbol * sym,
4568 struct disassemble_info * info ATTRIBUTE_UNUSED)
4569{
4570 const char * name;
4571
4572 if (sym == NULL)
4573 return FALSE;
4574
4575 name = bfd_asymbol_name (sym);
4576
d8282f0e 4577 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 4578}
4579
58efb6c0 4580/* Parse an individual disassembler option. */
baf0cc5e 4581
a3d9c82d 4582void
4a5329c6 4583parse_arm_disassembler_option (char *option)
dd92f639 4584{
01c7f630 4585 if (option == NULL)
dd92f639 4586 return;
b34976b6 4587
0112cd26 4588 if (CONST_STRNEQ (option, "reg-names-"))
dd92f639 4589 {
58efb6c0 4590 int i;
b34976b6 4591
01c7f630 4592 option += 10;
58efb6c0
NC		 4593
4594 for (i = NUM_ARM_REGNAMES; i--;)
31e0f3cd 4595 if (strneq (option, regnames[i].name, strlen (regnames[i].name)))
58efb6c0
NC		 4596 {
4597 regname_selected = i;
4598 break;
4599 }
b34976b6 4600
58efb6c0 4601 if (i < 0)
31e0f3cd 4602 /* XXX - should break 'option' at following delimiter. */
58efb6c0 4603 fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
dd92f639 4604 }
0112cd26 4605 else if (CONST_STRNEQ (option, "force-thumb"))
01c7f630 4606 force_thumb = 1;
0112cd26 4607 else if (CONST_STRNEQ (option, "no-force-thumb"))
01c7f630 4608 force_thumb = 0;
dd92f639 4609 else
31e0f3cd 4610 /* XXX - should break 'option' at following delimiter. */
58efb6c0 4611 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
b34976b6 4612
dd92f639
NC		 4613 return;
4614}
4615
31e0f3cd
NC		 4616/* Parse the string of disassembler options, spliting it at whitespaces
4617 or commas. (Whitespace separators supported for backwards compatibility). */
baf0cc5e 4618
01c7f630 4619static void
4a5329c6 4620parse_disassembler_options (char *options)
01c7f630 4621{
01c7f630
NC		 4622 if (options == NULL)
4623 return;
4624
31e0f3cd 4625 while (*options)
01c7f630 4626 {
31e0f3cd
NC		 4627 parse_arm_disassembler_option (options);
4628
4629 /* Skip forward to next seperator. */
4630 while ((*options) && (! ISSPACE (*options)) && (*options != ','))
4631 ++ options;
4632 /* Skip forward past seperators. */
4633 while (ISSPACE (*options) || (*options == ','))
4634 ++ options;
01c7f630 4635 }
01c7f630
NC		 4636}
4637
c22aaad1
PB		 4638/* Search back through the insn stream to determine if this instruction is
4639 conditionally executed. */
fe56b6ce 4640
c22aaad1 4641static void
fe56b6ce
NC		 4642find_ifthen_state (bfd_vma pc,
4643 struct disassemble_info *info,
c22aaad1
PB		 4644 bfd_boolean little)
4645{
4646 unsigned char b[2];
4647 unsigned int insn;
4648 int status;
4649 /* COUNT is twice the number of instructions seen. It will be odd if we
4650 just crossed an instruction boundary. */
4651 int count;
4652 int it_count;
4653 unsigned int seen_it;
4654 bfd_vma addr;
4655
4656 ifthen_address = pc;
4657 ifthen_state = 0;
4658
4659 addr = pc;
4660 count = 1;
4661 it_count = 0;
4662 seen_it = 0;
4663 /* Scan backwards looking for IT instructions, keeping track of where
4664 instruction boundaries are. We don't know if something is actually an
4665 IT instruction until we find a definite instruction boundary. */
4666 for (;;)
4667 {
fe56b6ce 4668 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 4669 {
4670 /* A symbol must be on an instruction boundary, and will not
4671 be within an IT block. */
4672 if (seen_it && (count & 1))
4673 break;
4674
4675 return;
4676 }
4677 addr -= 2;
fe56b6ce 4678 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 4679 if (status)
4680 return;
4681
4682 if (little)
4683 insn = (b[0]) | (b[1] << 8);
4684 else
4685 insn = (b[1]) | (b[0] << 8);
4686 if (seen_it)
4687 {
4688 if ((insn & 0xf800) < 0xe800)
4689 {
4690 /* Addr + 2 is an instruction boundary. See if this matches
4691 the expected boundary based on the position of the last
4692 IT candidate. */
4693 if (count & 1)
4694 break;
4695 seen_it = 0;
4696 }
4697 }
4698 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
4699 {
4700 /* This could be an IT instruction. */
4701 seen_it = insn;
4702 it_count = count >> 1;
4703 }
4704 if ((insn & 0xf800) >= 0xe800)
4705 count++;
4706 else
4707 count = (count + 2) | 1;
4708 /* IT blocks contain at most 4 instructions. */
4709 if (count >= 8 && !seen_it)
4710 return;
4711 }
4712 /* We found an IT instruction. */
4713 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
4714 if ((ifthen_state & 0xf) == 0)
4715 ifthen_state = 0;
4716}
4717
b0e28b39
DJ		 4718/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
4719 mapping symbol. */
4720
4721static int
4722is_mapping_symbol (struct disassemble_info *info, int n,
4723 enum map_type *map_type)
4724{
4725 const char *name;
4726
4727 name = bfd_asymbol_name (info->symtab[n]);
4728 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
4729 && (name[2] == 0 || name[2] == '.'))
4730 {
4731 *map_type = ((name[1] == 'a') ? MAP_ARM
4732 : (name[1] == 't') ? MAP_THUMB
4733 : MAP_DATA);
4734 return TRUE;
4735 }
4736
4737 return FALSE;
4738}
4739
4740/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
4741 Returns nonzero if *MAP_TYPE was set. */
4742
4743static int
4744get_map_sym_type (struct disassemble_info *info,
4745 int n,
4746 enum map_type *map_type)
4747{
4748 /* If the symbol is in a different section, ignore it. */
4749 if (info->section != NULL && info->section != info->symtab[n]->section)
4750 return FALSE;
4751
4752 return is_mapping_symbol (info, n, map_type);
4753}
4754
4755/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 4756 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 4757
4758static int
fe56b6ce
NC		 4759get_sym_code_type (struct disassemble_info *info,
4760 int n,
e821645d 4761 enum map_type *map_type)
2087ad84
PB		 4762{
4763 elf_symbol_type *es;
4764 unsigned int type;
b0e28b39
DJ		 4765
4766 /* If the symbol is in a different section, ignore it. */
4767 if (info->section != NULL && info->section != info->symtab[n]->section)
4768 return FALSE;
2087ad84 4769
e821645d 4770 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 4771 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
4772
4773 /* If the symbol has function type then use that. */
34e77a92 4774 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 4775 {
35fc36a8
RS		 4776 if (ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym) == ST_BRANCH_TO_THUMB)
4777 *map_type = MAP_THUMB;
4778 else
4779 *map_type = MAP_ARM;
2087ad84
PB		 4780 return TRUE;
4781 }
4782
2087ad84
PB		 4783 return FALSE;
4784}
4785
0313a2b8
NC		 4786/* Given a bfd_mach_arm_XXX value, this function fills in the fields
4787 of the supplied arm_feature_set structure with bitmasks indicating
4788 the support base architectures and coprocessor extensions.
4789
4790 FIXME: This could more efficiently implemented as a constant array,
4791 although it would also be less robust. */
4792
4793static void
4794select_arm_features (unsigned long mach,
4795 arm_feature_set * features)
4796{
4797#undef ARM_FEATURE
4798#define ARM_FEATURE(ARCH,CEXT) \
4799 features->core = (ARCH); \
4800 features->coproc = (CEXT) | FPU_FPA; \
4801 return
4802
4803 switch (mach)
4804 {
4805 case bfd_mach_arm_2: ARM_ARCH_V2;
4806 case bfd_mach_arm_2a: ARM_ARCH_V2S;
4807 case bfd_mach_arm_3: ARM_ARCH_V3;
4808 case bfd_mach_arm_3M: ARM_ARCH_V3M;
4809 case bfd_mach_arm_4: ARM_ARCH_V4;
4810 case bfd_mach_arm_4T: ARM_ARCH_V4T;
4811 case bfd_mach_arm_5: ARM_ARCH_V5;
4812 case bfd_mach_arm_5T: ARM_ARCH_V5T;
4813 case bfd_mach_arm_5TE: ARM_ARCH_V5TE;
4814 case bfd_mach_arm_XScale: ARM_ARCH_XSCALE;
4815 case bfd_mach_arm_ep9312: ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK | FPU_MAVERICK);
4816 case bfd_mach_arm_iWMMXt: ARM_ARCH_IWMMXT;
4817 case bfd_mach_arm_iWMMXt2: ARM_ARCH_IWMMXT2;
4818 /* If the machine type is unknown allow all
4819 architecture types and all extensions. */
4820 case bfd_mach_arm_unknown: ARM_FEATURE (-1UL, -1UL);
4821 default:
4822 abort ();
4823 }
4824}
4825
4826
58efb6c0
NC		 4827/* NOTE: There are no checks in these routines that
4828 the relevant number of data bytes exist. */
baf0cc5e 4829
58efb6c0 4830static int
4a5329c6 4831print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 4832{
c19d1205
ZW		 4833 unsigned char b[4];
4834 long given;
4835 int status;
e821645d 4836 int is_thumb = FALSE;
b0e28b39 4837 int is_data = FALSE;
bd2e2557 4838 int little_code;
e821645d 4839 unsigned int size = 4;
4a5329c6 4840 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 4841 bfd_boolean found = FALSE;
b0e28b39 4842 struct arm_private_data *private_data;
58efb6c0 4843
dd92f639
NC		 4844 if (info->disassembler_options)
4845 {
4846 parse_disassembler_options (info->disassembler_options);
b34976b6 4847
58efb6c0 4848 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 4849 info->disassembler_options = NULL;
4850 }
b34976b6 4851
0313a2b8
NC		 4852 /* PR 10288: Control which instructions will be disassembled. */
4853 if (info->private_data == NULL)
4854 {
b0e28b39 4855 static struct arm_private_data private;
0313a2b8
NC		 4856
4857 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
4858 /* If the user did not use the -m command line switch then default to
4859 disassembling all types of ARM instruction.
4860
4861 The info->mach value has to be ignored as this will be based on
4862 the default archictecture for the target and/or hints in the notes
4863 section, but it will never be greater than the current largest arm
4864 machine value (iWMMXt2), which is only equivalent to the V5TE
4865 architecture. ARM architectures have advanced beyond the machine
4866 value encoding, and these newer architectures would be ignored if
4867 the machine value was used.
4868
4869 Ie the -m switch is used to restrict which instructions will be
4870 disassembled. If it is necessary to use the -m switch to tell
4871 objdump that an ARM binary is being disassembled, eg because the
4872 input is a raw binary file, but it is also desired to disassemble
4873 all ARM instructions then use "-marm". This will select the
4874 "unknown" arm architecture which is compatible with any ARM
4875 instruction. */
4876 info->mach = bfd_mach_arm_unknown;
4877
4878 /* Compute the architecture bitmask from the machine number.
4879 Note: This assumes that the machine number will not change
4880 during disassembly.... */
b0e28b39 4881 select_arm_features (info->mach, & private.features);
0313a2b8 4882
b0e28b39 4883 private.has_mapping_symbols = -1;
1fbaefec
PB		 4884 private.last_mapping_sym = -1;
4885 private.last_mapping_addr = 0;
b0e28b39
DJ		 4886
4887 info->private_data = & private;
0313a2b8 4888 }
b0e28b39
DJ		 4889
4890 private_data = info->private_data;
4891
bd2e2557
SS		 4892 /* Decide if our code is going to be little-endian, despite what the
4893 function argument might say. */
4894 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
4895
b0e28b39
DJ		 4896 /* For ELF, consult the symbol table to determine what kind of code
4897 or data we have. */
8977d4b2 4898 if (info->symtab_size != 0
e821645d
DJ		 4899 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
4900 {
4901 bfd_vma addr;
b0e28b39 4902 int n, start;
e821645d 4903 int last_sym = -1;
b0e28b39 4904 enum map_type type = MAP_ARM;
e821645d 4905
e821645d
DJ		 4906 /* Start scanning at the start of the function, or wherever
4907 we finished last time. */
6750a3a7
NC		 4908 /* PR 14006. When the address is 0 we are either at the start of the
4909 very first function, or else the first function in a new, unlinked
4910 executable section (eg because uf -ffunction-sections). Either way
4911 start scanning from the beginning of the symbol table, not where we
4912 left off last time. */
4913 if (pc == 0)
4914 start = 0;
4915 else
4916 {
4917 start = info->symtab_pos + 1;
4918 if (start < private_data->last_mapping_sym)
4919 start = private_data->last_mapping_sym;
4920 }
b0e28b39 4921 found = FALSE;
e821645d 4922
b0e28b39
DJ		 4923 /* First, look for mapping symbols. */
4924 if (private_data->has_mapping_symbols != 0)
e821645d 4925 {
b0e28b39
DJ		 4926 /* Scan up to the location being disassembled. */
4927 for (n = start; n < info->symtab_size; n++)
4928 {
4929 addr = bfd_asymbol_value (info->symtab[n]);
4930 if (addr > pc)
4931 break;
4932 if (get_map_sym_type (info, n, &type))
4933 {
4934 last_sym = n;
4935 found = TRUE;
4936 }
4937 }
4938
4939 if (!found)
4940 {
4941 /* No mapping symbol found at this address. Look backwards
cc643b88 4942 for a preceding one. */
b0e28b39
DJ		 4943 for (n = start - 1; n >= 0; n--)
4944 {
4945 if (get_map_sym_type (info, n, &type))
4946 {
4947 last_sym = n;
4948 found = TRUE;
4949 break;
4950 }
4951 }
4952 }
4953
4954 if (found)
4955 private_data->has_mapping_symbols = 1;
4956
4957 /* No mapping symbols were found. A leading $d may be
4958 omitted for sections which start with data; but for
4959 compatibility with legacy and stripped binaries, only
4960 assume the leading $d if there is at least one mapping
4961 symbol in the file. */
4962 if (!found && private_data->has_mapping_symbols == -1)
e821645d 4963 {
b0e28b39
DJ		 4964 /* Look for mapping symbols, in any section. */
4965 for (n = 0; n < info->symtab_size; n++)
4966 if (is_mapping_symbol (info, n, &type))
4967 {
4968 private_data->has_mapping_symbols = 1;
4969 break;
4970 }
4971 if (private_data->has_mapping_symbols == -1)
4972 private_data->has_mapping_symbols = 0;
4973 }
4974
4975 if (!found && private_data->has_mapping_symbols == 1)
4976 {
4977 type = MAP_DATA;
e821645d
DJ		 4978 found = TRUE;
4979 }
4980 }
4981
b0e28b39
DJ		 4982 /* Next search for function symbols to separate ARM from Thumb
4983 in binaries without mapping symbols. */
e821645d
DJ		 4984 if (!found)
4985 {
b0e28b39
DJ		 4986 /* Scan up to the location being disassembled. */
4987 for (n = start; n < info->symtab_size; n++)
e821645d 4988 {
b0e28b39
DJ		 4989 addr = bfd_asymbol_value (info->symtab[n]);
4990 if (addr > pc)
4991 break;
4992 if (get_sym_code_type (info, n, &type))
e821645d
DJ		 4993 {
4994 last_sym = n;
4995 found = TRUE;
b0e28b39
DJ		 4996 }
4997 }
4998
4999 if (!found)
5000 {
5001 /* No mapping symbol found at this address. Look backwards
cc643b88 5002 for a preceding one. */
b0e28b39
DJ		 5003 for (n = start - 1; n >= 0; n--)
5004 {
5005 if (get_sym_code_type (info, n, &type))
5006 {
5007 last_sym = n;
5008 found = TRUE;
5009 break;
5010 }
e821645d
DJ		 5011 }
5012 }
5013 }
5014
1fbaefec
PB		 5015 private_data->last_mapping_sym = last_sym;
5016 private_data->last_type = type;
5017 is_thumb = (private_data->last_type == MAP_THUMB);
5018 is_data = (private_data->last_type == MAP_DATA);
b34976b6 5019
e821645d
DJ		 5020 /* Look a little bit ahead to see if we should print out
5021 two or four bytes of data. If there's a symbol,
5022 mapping or otherwise, after two bytes then don't
5023 print more. */
5024 if (is_data)
5025 {
5026 size = 4 - (pc & 3);
5027 for (n = last_sym + 1; n < info->symtab_size; n++)
5028 {
5029 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 5030 if (addr > pc
5031 && (info->section == NULL
5032 || info->section == info->symtab[n]->section))
e821645d
DJ		 5033 {
5034 if (addr - pc < size)
5035 size = addr - pc;
5036 break;
5037 }
5038 }
5039 /* If the next symbol is after three bytes, we need to
5040 print only part of the data, so that we can use either
5041 .byte or .short. */
5042 if (size == 3)
5043 size = (pc & 1) ? 1 : 2;
5044 }
5045 }
5046
5047 if (info->symbols != NULL)
252b5132 5048 {
5876e06d
NC		 5049 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
5050 {
2f0ca46a 5051 coff_symbol_type * cs;
b34976b6 5052
5876e06d
NC		 5053 cs = coffsymbol (*info->symbols);
5054 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
5055 || cs->native->u.syment.n_sclass == C_THUMBSTAT
5056 || cs->native->u.syment.n_sclass == C_THUMBLABEL
5057 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
5058 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
5059 }
e821645d
DJ		 5060 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
5061 && !found)
5876e06d 5062 {
2087ad84
PB		 5063 /* If no mapping symbol has been found then fall back to the type
5064 of the function symbol. */
e821645d
DJ		 5065 elf_symbol_type * es;
5066 unsigned int type;
2087ad84 5067
e821645d
DJ		 5068 es = *(elf_symbol_type **)(info->symbols);
5069 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 5070
35fc36a8
RS		 5071 is_thumb = ((ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym)
5072 == ST_BRANCH_TO_THUMB)
5073 || type == STT_ARM_16BIT);
5876e06d
NC		 5074 }
5075 }
b34976b6 5076
e821645d
DJ		 5077 if (force_thumb)
5078 is_thumb = TRUE;
5079
b8f9ee44
CL		 5080 if (is_data)
5081 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
5082 else
5083 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
5084
c19d1205 5085 info->bytes_per_line = 4;
252b5132 5086
1316c8b3
NC		 5087 /* PR 10263: Disassemble data if requested to do so by the user. */
5088 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 5089 {
5090 int i;
5091
1316c8b3 5092 /* Size was already set above. */
e821645d
DJ		 5093 info->bytes_per_chunk = size;
5094 printer = print_insn_data;
5095
fe56b6ce 5096 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 5097 given = 0;
5098 if (little)
5099 for (i = size - 1; i >= 0; i--)
5100 given = b[i] | (given << 8);
5101 else
5102 for (i = 0; i < (int) size; i++)
5103 given = b[i] | (given << 8);
5104 }
5105 else if (!is_thumb)
252b5132 5106 {
c19d1205
ZW		 5107 /* In ARM mode endianness is a straightforward issue: the instruction
5108 is four bytes long and is either ordered 0123 or 3210. */
5109 printer = print_insn_arm;
5110 info->bytes_per_chunk = 4;
4a5329c6 5111 size = 4;
c19d1205 5112
0313a2b8 5113 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 5114 if (little_code)
c19d1205
ZW		 5115 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
5116 else
5117 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
252b5132 5118 }
58efb6c0 5119 else
252b5132 5120 {
c19d1205
ZW		 5121 /* In Thumb mode we have the additional wrinkle of two
5122 instruction lengths. Fortunately, the bits that determine
5123 the length of the current instruction are always to be found
5124 in the first two bytes. */
4a5329c6 5125 printer = print_insn_thumb16;
c19d1205 5126 info->bytes_per_chunk = 2;
4a5329c6
ZW		 5127 size = 2;
5128
fe56b6ce 5129 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 5130 if (little_code)
9a2ff3f5
AM		 5131 given = (b[0]) | (b[1] << 8);
5132 else
5133 given = (b[1]) | (b[0] << 8);
5134
c19d1205 5135 if (!status)
252b5132 5136 {
c19d1205
ZW		 5137 /* These bit patterns signal a four-byte Thumb
5138 instruction. */
5139 if ((given & 0xF800) == 0xF800
5140 || (given & 0xF800) == 0xF000
5141 || (given & 0xF800) == 0xE800)
252b5132 5142 {
0313a2b8 5143 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 5144 if (little_code)
c19d1205 5145 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 5146 else
c19d1205
ZW		 5147 given = (b[1]) | (b[0] << 8) | (given << 16);
5148
5149 printer = print_insn_thumb32;
4a5329c6 5150 size = 4;
252b5132 5151 }
252b5132 5152 }
c22aaad1
PB		 5153
5154 if (ifthen_address != pc)
0313a2b8 5155 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 5156
5157 if (ifthen_state)
5158 {
5159 if ((ifthen_state & 0xf) == 0x8)
5160 ifthen_next_state = 0;
5161 else
5162 ifthen_next_state = (ifthen_state & 0xe0)
5163 | ((ifthen_state & 0xf) << 1);
5164 }
252b5132 5165 }
b34976b6 5166
c19d1205
ZW		 5167 if (status)
5168 {
5169 info->memory_error_func (status, pc, info);
5170 return -1;
5171 }
6a56ec7e
NC		 5172 if (info->flags & INSN_HAS_RELOC)
5173 /* If the instruction has a reloc associated with it, then
5174 the offset field in the instruction will actually be the
5175 addend for the reloc. (We are using REL type relocs).
5176 In such cases, we can ignore the pc when computing
5177 addresses, since the addend is not currently pc-relative. */
5178 pc = 0;
b34976b6 5179
4a5329c6 5180 printer (pc, info, given);
c22aaad1
PB		 5181
5182 if (is_thumb)
5183 {
5184 ifthen_state = ifthen_next_state;
5185 ifthen_address += size;
5186 }
4a5329c6 5187 return size;
252b5132
RH		 5188}
5189
5190int
4a5329c6 5191print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 5192{
bd2e2557
SS		 5193 /* Detect BE8-ness and record it in the disassembler info. */
5194 if (info->flavour == bfd_target_elf_flavour
5195 && info->section != NULL
5196 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
5197 info->endian_code = BFD_ENDIAN_LITTLE;
5198
b34976b6 5199 return print_insn (pc, info, FALSE);
58efb6c0 5200}
01c7f630 5201
58efb6c0 5202int
4a5329c6 5203print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 5204{
b34976b6 5205 return print_insn (pc, info, TRUE);
58efb6c0 5206}
252b5132 5207
58efb6c0 5208void
4a5329c6 5209print_arm_disassembler_options (FILE *stream)
58efb6c0
NC		 5210{
5211 int i;
252b5132 5212
58efb6c0
NC		 5213 fprintf (stream, _("\n\
5214The following ARM specific disassembler options are supported for use with\n\
5215the -M switch:\n"));
b34976b6 5216
58efb6c0
NC		 5217 for (i = NUM_ARM_REGNAMES; i--;)
5218 fprintf (stream, " reg-names-%s %*c%s\n",
5219 regnames[i].name,
d5b2f4d6 5220 (int)(14 - strlen (regnames[i].name)), ' ',
58efb6c0
NC		 5221 regnames[i].description);
5222
5223 fprintf (stream, " force-thumb Assume all insns are Thumb insns\n");
cc643b88 5224 fprintf (stream, " no-force-thumb Examine preceding label to determine an insn's type\n\n");
252b5132 5225}
GDB Binutils - Deliverables
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