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[Patch][binutils][arm] Armv8.6-A Matrix Multiply extension [9/10]
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
CommitLineData
252b5132 1/* Instruction printing code for the ARM
82704155 2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
143275ea 24#include <assert.h>
2fbad815 25
6394c606 26#include "disassemble.h"
2fbad815 27#include "opcode/arm.h"
252b5132 28#include "opintl.h"
31e0f3cd 29#include "safe-ctype.h"
65b48a81 30#include "libiberty.h"
0dbde4cf 31#include "floatformat.h"
252b5132 32
baf0cc5e 33/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 34#include "coff/internal.h"
35#include "libcoff.h"
2d5d5a8f 36#include "bfd.h"
252b5132
RH		 37#include "elf-bfd.h"
38#include "elf/internal.h"
39#include "elf/arm.h"
e49d43ff 40#include "mach-o.h"
252b5132 41
6b5d3a4d 42/* FIXME: Belongs in global header. */
01c7f630 43#ifndef strneq
58efb6c0
NC		 44#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
45#endif
46
1fbaefec
PB		 47/* Cached mapping symbol state. */
48enum map_type
49{
50 MAP_ARM,
51 MAP_THUMB,
52 MAP_DATA
53};
54
b0e28b39
DJ		 55struct arm_private_data
56{
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features;
59
1fbaefec
PB		 60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type;
62
63 /* Tracking symbol table information */
64 int last_mapping_sym;
796d6298
TC		 65
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset;
1fbaefec 68 bfd_vma last_mapping_addr;
b0e28b39
DJ		 69};
70
73cd51e5
AV		 71enum mve_instructions
72{
143275ea
AV		 73 MVE_VPST,
74 MVE_VPT_FP_T1,
75 MVE_VPT_FP_T2,
76 MVE_VPT_VEC_T1,
77 MVE_VPT_VEC_T2,
78 MVE_VPT_VEC_T3,
79 MVE_VPT_VEC_T4,
80 MVE_VPT_VEC_T5,
81 MVE_VPT_VEC_T6,
82 MVE_VCMP_FP_T1,
83 MVE_VCMP_FP_T2,
84 MVE_VCMP_VEC_T1,
85 MVE_VCMP_VEC_T2,
86 MVE_VCMP_VEC_T3,
87 MVE_VCMP_VEC_T4,
88 MVE_VCMP_VEC_T5,
89 MVE_VCMP_VEC_T6,
9743db03
AV		 90 MVE_VDUP,
91 MVE_VEOR,
92 MVE_VFMAS_FP_SCALAR,
93 MVE_VFMA_FP_SCALAR,
94 MVE_VFMA_FP,
95 MVE_VFMS_FP,
96 MVE_VHADD_T1,
97 MVE_VHADD_T2,
98 MVE_VHSUB_T1,
99 MVE_VHSUB_T2,
100 MVE_VRHADD,
04d54ace
AV		 101 MVE_VLD2,
102 MVE_VLD4,
103 MVE_VST2,
104 MVE_VST4,
aef6d006
AV		 105 MVE_VLDRB_T1,
106 MVE_VLDRH_T2,
107 MVE_VLDRB_T5,
108 MVE_VLDRH_T6,
109 MVE_VLDRW_T7,
110 MVE_VSTRB_T1,
111 MVE_VSTRH_T2,
112 MVE_VSTRB_T5,
113 MVE_VSTRH_T6,
114 MVE_VSTRW_T7,
ef1576a1
AV		 115 MVE_VLDRB_GATHER_T1,
116 MVE_VLDRH_GATHER_T2,
117 MVE_VLDRW_GATHER_T3,
118 MVE_VLDRD_GATHER_T4,
119 MVE_VLDRW_GATHER_T5,
120 MVE_VLDRD_GATHER_T6,
121 MVE_VSTRB_SCATTER_T1,
122 MVE_VSTRH_SCATTER_T2,
123 MVE_VSTRW_SCATTER_T3,
124 MVE_VSTRD_SCATTER_T4,
125 MVE_VSTRW_SCATTER_T5,
126 MVE_VSTRD_SCATTER_T6,
bf0b396d
AV		 127 MVE_VCVT_FP_FIX_VEC,
128 MVE_VCVT_BETWEEN_FP_INT,
129 MVE_VCVT_FP_HALF_FP,
130 MVE_VCVT_FROM_FP_TO_INT,
131 MVE_VRINT_FP,
c507f10b
AV		 132 MVE_VMOV_HFP_TO_GP,
133 MVE_VMOV_GP_TO_VEC_LANE,
134 MVE_VMOV_IMM_TO_VEC,
135 MVE_VMOV_VEC_TO_VEC,
136 MVE_VMOV2_VEC_LANE_TO_GP,
137 MVE_VMOV2_GP_TO_VEC_LANE,
138 MVE_VMOV_VEC_LANE_TO_GP,
139 MVE_VMVN_IMM,
140 MVE_VMVN_REG,
141 MVE_VORR_IMM,
142 MVE_VORR_REG,
143 MVE_VORN,
144 MVE_VBIC_IMM,
145 MVE_VBIC_REG,
146 MVE_VMOVX,
14925797
AV		 147 MVE_VMOVL,
148 MVE_VMOVN,
149 MVE_VMULL_INT,
150 MVE_VMULL_POLY,
151 MVE_VQDMULL_T1,
152 MVE_VQDMULL_T2,
153 MVE_VQMOVN,
154 MVE_VQMOVUN,
d3b63143
AV		 155 MVE_VADDV,
156 MVE_VMLADAV_T1,
157 MVE_VMLADAV_T2,
158 MVE_VMLALDAV,
159 MVE_VMLAS,
160 MVE_VADDLV,
161 MVE_VMLSDAV_T1,
162 MVE_VMLSDAV_T2,
163 MVE_VMLSLDAV,
164 MVE_VRMLALDAVH,
165 MVE_VRMLSLDAVH,
166 MVE_VQDMLADH,
167 MVE_VQRDMLADH,
168 MVE_VQDMLAH,
169 MVE_VQRDMLAH,
170 MVE_VQDMLASH,
171 MVE_VQRDMLASH,
172 MVE_VQDMLSDH,
173 MVE_VQRDMLSDH,
174 MVE_VQDMULH_T1,
175 MVE_VQRDMULH_T2,
176 MVE_VQDMULH_T3,
177 MVE_VQRDMULH_T4,
1c8f2df8
AV		 178 MVE_VDDUP,
179 MVE_VDWDUP,
180 MVE_VIWDUP,
181 MVE_VIDUP,
897b9bbc
AV		 182 MVE_VCADD_FP,
183 MVE_VCADD_VEC,
184 MVE_VHCADD,
185 MVE_VCMLA_FP,
186 MVE_VCMUL_FP,
ed63aa17
AV		 187 MVE_VQRSHL_T1,
188 MVE_VQRSHL_T2,
189 MVE_VQRSHRN,
190 MVE_VQRSHRUN,
191 MVE_VQSHL_T1,
192 MVE_VQSHL_T2,
193 MVE_VQSHLU_T3,
194 MVE_VQSHL_T4,
195 MVE_VQSHRN,
196 MVE_VQSHRUN,
197 MVE_VRSHL_T1,
198 MVE_VRSHL_T2,
199 MVE_VRSHR,
200 MVE_VRSHRN,
201 MVE_VSHL_T1,
202 MVE_VSHL_T2,
203 MVE_VSHL_T3,
204 MVE_VSHLC,
205 MVE_VSHLL_T1,
206 MVE_VSHLL_T2,
207 MVE_VSHR,
208 MVE_VSHRN,
209 MVE_VSLI,
210 MVE_VSRI,
66dcaa5d
AV		 211 MVE_VADC,
212 MVE_VABAV,
213 MVE_VABD_FP,
214 MVE_VABD_VEC,
215 MVE_VABS_FP,
216 MVE_VABS_VEC,
217 MVE_VADD_FP_T1,
218 MVE_VADD_FP_T2,
219 MVE_VADD_VEC_T1,
220 MVE_VADD_VEC_T2,
221 MVE_VSBC,
222 MVE_VSUB_FP_T1,
223 MVE_VSUB_FP_T2,
224 MVE_VSUB_VEC_T1,
225 MVE_VSUB_VEC_T2,
e523f101
AV		 226 MVE_VAND,
227 MVE_VBRSR,
228 MVE_VCLS,
229 MVE_VCLZ,
230 MVE_VCTP,
56858bea
AV		 231 MVE_VMAX,
232 MVE_VMAXA,
233 MVE_VMAXNM_FP,
234 MVE_VMAXNMA_FP,
235 MVE_VMAXNMV_FP,
236 MVE_VMAXNMAV_FP,
237 MVE_VMAXV,
238 MVE_VMAXAV,
239 MVE_VMIN,
240 MVE_VMINA,
241 MVE_VMINNM_FP,
242 MVE_VMINNMA_FP,
243 MVE_VMINNMV_FP,
244 MVE_VMINNMAV_FP,
245 MVE_VMINV,
246 MVE_VMINAV,
247 MVE_VMLA,
f49bb598
AV		 248 MVE_VMUL_FP_T1,
249 MVE_VMUL_FP_T2,
250 MVE_VMUL_VEC_T1,
251 MVE_VMUL_VEC_T2,
252 MVE_VMULH,
253 MVE_VRMULH,
254 MVE_VNEG_FP,
255 MVE_VNEG_VEC,
14b456f2
AV		 256 MVE_VPNOT,
257 MVE_VPSEL,
258 MVE_VQABS,
259 MVE_VQADD_T1,
260 MVE_VQADD_T2,
261 MVE_VQSUB_T1,
262 MVE_VQSUB_T2,
263 MVE_VQNEG,
264 MVE_VREV16,
265 MVE_VREV32,
266 MVE_VREV64,
23d00a41
SD		 267 MVE_LSLL,
268 MVE_LSLLI,
269 MVE_LSRL,
270 MVE_ASRL,
271 MVE_ASRLI,
272 MVE_SQRSHRL,
273 MVE_SQRSHR,
274 MVE_UQRSHL,
275 MVE_UQRSHLL,
276 MVE_UQSHL,
277 MVE_UQSHLL,
278 MVE_URSHRL,
279 MVE_URSHR,
280 MVE_SRSHRL,
281 MVE_SRSHR,
282 MVE_SQSHLL,
283 MVE_SQSHL,
e39c1607
SD		 284 MVE_CINC,
285 MVE_CINV,
286 MVE_CNEG,
287 MVE_CSINC,
288 MVE_CSINV,
289 MVE_CSET,
290 MVE_CSETM,
291 MVE_CSNEG,
292 MVE_CSEL,
73cd51e5
AV		 293 MVE_NONE
294};
295
296enum mve_unpredictable
297{
298 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
299 */
143275ea
AV		 300 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and
301 fcB = 1 (vpt). */
302 UNPRED_R13, /* Unpredictable because r13 (sp) or
303 r15 (sp) used. */
9743db03 304 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
04d54ace
AV		 305 UNPRED_Q_GT_4, /* Unpredictable because
306 vec reg start > 4 (vld4/st4). */
307 UNPRED_Q_GT_6, /* Unpredictable because
308 vec reg start > 6 (vld2/st2). */
309 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
310 and WB bit = 1. */
ef1576a1
AV		 311 UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are
312 equal. */
313 UNPRED_OS, /* Unpredictable because offset scaled == 1. */
bf0b396d
AV		 314 UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the
315 same. */
c507f10b
AV		 316 UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and
317 size = 1. */
318 UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and
319 size = 2. */
73cd51e5
AV		 320 UNPRED_NONE /* No unpredictable behavior. */
321};
322
323enum mve_undefined
324{
ed63aa17 325 UNDEF_SIZE, /* undefined size. */
bf0b396d 326 UNDEF_SIZE_0, /* undefined because size == 0. */
c507f10b 327 UNDEF_SIZE_2, /* undefined because size == 2. */
aef6d006
AV		 328 UNDEF_SIZE_3, /* undefined because size == 3. */
329 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
14b456f2 330 UNDEF_SIZE_NOT_0, /* undefined because size != 0. */
ef1576a1
AV		 331 UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
332 UNDEF_SIZE_NOT_3, /* undefined because size != 3. */
333 UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and
334 size == 0. */
335 UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and
336 size == 1. */
337 UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
bf0b396d
AV		 338 UNDEF_VCVT_IMM6, /* imm6 < 32. */
339 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
c507f10b
AV		 340 UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and
341 op1 == (0 or 1). */
342 UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and
343 op2 == 0 and op1 == (0 or 1). */
344 UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode
345 in {0xx1, x0x1}. */
d3b63143 346 UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */
73cd51e5
AV		 347 UNDEF_NONE /* no undefined behavior. */
348};
349
6b5d3a4d
ZW		 350struct opcode32
351{
823d2571
TG		 352 arm_feature_set arch; /* Architecture defining this insn. */
353 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 354 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 355 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 356};
357
73cd51e5
AV		 358/* MVE opcodes. */
359
360struct mopcode32
361{
362 arm_feature_set arch; /* Architecture defining this insn. */
363 enum mve_instructions mve_op; /* Specific mve instruction for faster
364 decoding. */
365 unsigned long value; /* If arch is 0 then value is a sentinel. */
366 unsigned long mask; /* Recognise insn if (op & mask) == value. */
367 const char * assembler; /* How to disassemble this insn. */
368};
369
6b0dd094
AV		 370enum isa {
371 ANY,
372 T32,
373 ARM
374};
375
376
377/* Shared (between Arm and Thumb mode) opcode. */
378struct sopcode32
379{
380 enum isa isa; /* Execution mode instruction availability. */
381 arm_feature_set arch; /* Architecture defining this insn. */
382 unsigned long value; /* If arch is 0 then value is a sentinel. */
383 unsigned long mask; /* Recognise insn if (op & mask) == value. */
384 const char * assembler; /* How to disassemble this insn. */
385};
386
6b5d3a4d
ZW		 387struct opcode16
388{
823d2571 389 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 390 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 391 const char *assembler; /* How to disassemble this insn. */
392};
b7693d02 393
8f06b2d8 394/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 395
2fbad815 396 %% %
4a5329c6 397
c22aaad1 398 %c print condition code (always bits 28-31 in ARM mode)
aab2c27d 399 %b print condition code allowing cp_num == 9
37b37b2d 400 %q print shifter argument
e2efe87d
MGD		 401 %u print condition code (unconditional in ARM mode,
402 UNPREDICTABLE if not AL in Thumb)
4a5329c6 403 %A print address for ldc/stc/ldf/stf instruction
16980d0b 404 %B print vstm/vldm register list
efd6b359 405 %C print vscclrm register list
4a5329c6 406 %I print cirrus signed shift immediate: bits 0..3|4..6
32c36c3c
AV		 407 %J print register for VLDR instruction
408 %K print address for VLDR instruction
4a5329c6
ZW		 409 %F print the COUNT field of a LFM/SFM instruction.
410 %P print floating point precision in arithmetic insn
411 %Q print floating point precision in ldf/stf insn
412 %R print floating point rounding mode
413
33399f07 414 %<bitfield>c print as a condition code (for vsel)
4a5329c6 415 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 416 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
417 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 418 %<bitfield>d print the bitfield in decimal
16980d0b 419 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 420 %<bitfield>x print the bitfield in hex
421 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 422 %<bitfield>f print a floating point constant if >7 else a
423 floating point register
4a5329c6
ZW		 424 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
425 %<bitfield>g print as an iWMMXt 64-bit register
426 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 427 %<bitfield>D print as a NEON D register
428 %<bitfield>Q print as a NEON Q register
c28eeff2 429 %<bitfield>V print as a NEON D or Q register
6f1c2142 430 %<bitfield>E print a quarter-float immediate value
4a5329c6 431
16980d0b 432 %y<code> print a single precision VFP reg.
2fbad815 433 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 434 %z<code> print a double precision VFP reg
2fbad815 435 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 436
16980d0b
JB		 437 %<bitfield>'c print specified char iff bitfield is all ones
438 %<bitfield>`c print specified char iff bitfield is all zeroes
439 %<bitfield>?ab... select from array of values in big endian order
43e65147 440
2fbad815 441 %L print as an iWMMXt N/M width field.
4a5329c6 442 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 443 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 444 versions.
445 %i print 5-bit immediate in bits 8,3..0
446 (print "32" when 0)
fe56b6ce 447 %r print register offset address for wldt/wstr instruction. */
2fbad815 448
21d799b5 449enum opcode_sentinel_enum
05413229
NC		 450{
451 SENTINEL_IWMMXT_START = 1,
452 SENTINEL_IWMMXT_END,
453 SENTINEL_GENERIC_START
454} opcode_sentinels;
455
aefd8a40 456#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
0b347048
TC		 457#define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
458#define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
c1e26897 459#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 460
8f06b2d8 461/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 462
6b0dd094 463static const struct sopcode32 coprocessor_opcodes[] =
2fbad815 464{
2fbad815 465 /* XScale instructions. */
6b0dd094 466 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 467 0x0e200010, 0x0fff0ff0,
468 "mia%c\tacc0, %0-3r, %12-15r"},
6b0dd094 469 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 470 0x0e280010, 0x0fff0ff0,
471 "miaph%c\tacc0, %0-3r, %12-15r"},
6b0dd094 472 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 473 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
6b0dd094 474 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 475 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
6b0dd094 476 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 477 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 478
2fbad815 479 /* Intel Wireless MMX technology instructions. */
6b0dd094
AV		 480 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
481 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
823d2571 482 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
6b0dd094 483 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 484 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
6b0dd094 485 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 486 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
6b0dd094 487 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 488 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
6b0dd094 489 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 490 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
6b0dd094 491 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 492 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
6b0dd094 493 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 494 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
6b0dd094 495 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 496 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 497 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 498 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 499 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 500 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 501 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 502 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
6b0dd094 503 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 504 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
6b0dd094 505 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 506 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
6b0dd094 507 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 508 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
6b0dd094 509 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 510 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
6b0dd094 511 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 512 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 513 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 514 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 515 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 516 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 517 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 518 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 519 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 520 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 521 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 522 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
6b0dd094 523 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 524 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 525 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 526 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 527 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 528 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 529 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 530 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 531 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 532 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 533 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 534 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 535 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 536 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
6b0dd094 537 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 538 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
6b0dd094 539 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 540 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
6b0dd094 541 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 542 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 543 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 544 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 545 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 546 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 547 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 548 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 549 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 550 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
6b0dd094 551 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 552 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 553 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 554 0x0e800120, 0x0f800ff0,
555 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 556 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 557 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 558 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 559 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 560 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 561 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 562 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 563 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 564 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 565 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 566 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 567 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 568 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 569 0x0e8000a0, 0x0f800ff0,
570 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 571 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 572 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 573 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 574 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 575 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 576 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 577 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 578 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 579 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 580 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 581 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 582 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 583 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 584 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 585 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 586 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 587 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 588 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
6b0dd094 589 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 590 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 591 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 592 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 593 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 594 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 595 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 596 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 597 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 598 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 599 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 600 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 601 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 602 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 603 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 604 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 605 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 606 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 607 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 608 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
6b0dd094 609 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 610 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
6b0dd094 611 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 612 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
6b0dd094 613 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 614 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 615 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 616 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 617 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 618 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 619 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 620 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
6b0dd094 621 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 622 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
6b0dd094 623 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 624 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
6b0dd094 625 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 626 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 627 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 628 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 629 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 630 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 631 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 632 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 633 {ANY, ARM_FEATURE_CORE_LOW (0),
823d2571 634 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 635
fe56b6ce 636 /* Floating point coprocessor (FPA) instructions. */
6b0dd094 637 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 638 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 639 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 640 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 641 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 642 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 643 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 644 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 645 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 646 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 647 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 648 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 649 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 650 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 651 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 652 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 653 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 654 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 655 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 656 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 657 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 658 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 659 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 660 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 661 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 662 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 663 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 664 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 665 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 666 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 667 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 668 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 669 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 670 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 671 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 672 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
6b0dd094 673 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 674 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
6b0dd094 675 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 676 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 677 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 678 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
6b0dd094 679 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 680 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
6b0dd094 681 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 682 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
6b0dd094 683 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 684 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
6b0dd094 685 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 686 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 687 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 688 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 689 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 690 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 691 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 692 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 693 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 694 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
6b0dd094 695 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 696 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
6b0dd094 697 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 698 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
6b0dd094 699 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 700 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
6b0dd094 701 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 702 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
6b0dd094 703 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 704 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
6b0dd094 705 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 706 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
6b0dd094 707 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 708 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
6b0dd094 709 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 710 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
6b0dd094 711 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 712 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
6b0dd094 713 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 714 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
6b0dd094 715 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 716 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
6b0dd094 717 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 718 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
6b0dd094 719 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 720 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
6b0dd094 721 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 722 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 723
efd6b359
AV		 724 /* Armv8.1-M Mainline instructions. */
725 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
726 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
727 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
728 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
729
16a1fa25 730 /* ARMv8-M Mainline Security Extensions instructions. */
6b0dd094 731 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25 732 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
6b0dd094 733 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25
TP		 734 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
735
fe56b6ce 736 /* Register load/store. */
6b0dd094 737 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 738 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
6b0dd094 739 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 740 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
6b0dd094 741 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 742 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
6b0dd094 743 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 744 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
6b0dd094 745 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 746 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
6b0dd094 747 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 748 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
6b0dd094 749 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 750 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
6b0dd094 751 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 752 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
6b0dd094 753 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 754 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
6b0dd094 755 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 756 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
6b0dd094 757 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 758 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
6b0dd094 759 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 760 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
6b0dd094 761 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 762 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
6b0dd094 763 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 764 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
6b0dd094 765 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 766 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
6b0dd094 767 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 768 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
32c36c3c
AV		 769 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
770 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
771 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
772 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
823d2571 773
6b0dd094 774 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 775 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 776 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 777 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 778 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 779 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
6b0dd094 780 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 781 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 782
fe56b6ce 783 /* Data transfer between ARM and NEON registers. */
6b0dd094 784 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 785 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
6b0dd094 786 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 787 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
6b0dd094 788 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 789 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
6b0dd094 790 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 791 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
6b0dd094 792 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 793 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
6b0dd094 794 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 795 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
6b0dd094 796 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 797 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
6b0dd094 798 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 799 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 800 /* Half-precision conversion instructions. */
6b0dd094 801 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 802 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
6b0dd094 803 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 804 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
6b0dd094 805 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 806 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
6b0dd094 807 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 808 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 809
fe56b6ce 810 /* Floating point coprocessor (VFP) instructions. */
6b0dd094 811 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 812 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
ba6cd17f 813 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_MVE),
823d2571 814 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
ba6cd17f
SD		 815 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
816 0x0ee20a10, 0x0fff0fff, "vmsr%c\tfpscr_nzcvqc, %12-15r"},
6b0dd094 817 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 818 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
6b0dd094 819 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 820 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
6b0dd094 821 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 822 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
6b0dd094 823 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 824 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
6b0dd094 825 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 826 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
6b0dd094 827 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 828 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
ba6cd17f
SD		 829 {ANY, ARM_FEATURE_COPROC (FPU_MVE),
830 0x0eec0a10, 0x0fff0fff, "vmsr%c\tvpr, %12-15r"},
831 {ANY, ARM_FEATURE_COPROC (FPU_MVE),
832 0x0eed0a10, 0x0fff0fff, "vmsr%c\tp0, %12-15r"},
833 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
834 0x0eee0a10, 0x0fff0fff, "vmsr%c\tfpcxt_ns, %12-15r"},
835 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
836 0x0eef0a10, 0x0fff0fff, "vmsr%c\tfpcxt_s, %12-15r"},
6b0dd094 837 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 838 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
6b0dd094 839 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 840 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
ba6cd17f 841 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_MVE),
823d2571 842 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
ba6cd17f
SD		 843 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
844 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr_nzcvqc"},
6b0dd094 845 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 846 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
6b0dd094 847 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 848 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
6b0dd094 849 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 850 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
6b0dd094 851 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 852 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
6b0dd094 853 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 854 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
6b0dd094 855 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 856 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
ba6cd17f
SD		 857 {ANY, ARM_FEATURE_COPROC (FPU_MVE),
858 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, vpr"},
859 {ANY, ARM_FEATURE_COPROC (FPU_MVE),
860 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, p0"},
861 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
862 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_ns"},
863 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
864 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_s"},
6b0dd094 865 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 866 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
6b0dd094 867 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 868 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
6b0dd094 869 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 870 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
6b0dd094 871 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 872 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
6b0dd094 873 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 874 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
6b0dd094 875 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 876 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
6b0dd094 877 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 878 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
6b0dd094 879 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 880 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
6b0dd094 881 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 882 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
6b0dd094 883 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 884 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
6b0dd094 885 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 886 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
6b0dd094 887 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 888 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
6b0dd094 889 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 890 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
6b0dd094 891 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 892 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
6b0dd094 893 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 894 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
6b0dd094 895 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 896 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
6b0dd094 897 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 898 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
6b0dd094 899 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 900 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
6b0dd094 901 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 902 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
6b0dd094 903 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 904 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
6b0dd094 905 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 906 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
6b0dd094 907 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 908 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
6b0dd094 909 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 910 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 911 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 912 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
6b0dd094 913 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 914 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
6b0dd094 915 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 916 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
6b0dd094 917 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 918 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
6b0dd094 919 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 920 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
6b0dd094 921 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 922 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
6b0dd094 923 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6f1c2142 924 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
6b0dd094 925 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6f1c2142 926 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
6b0dd094 927 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 928 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
6b0dd094 929 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 930 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
6b0dd094 931 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 932 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
6b0dd094 933 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 934 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 935 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 936 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 937 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 938 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 939 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 940 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 941 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 942 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 943 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 944 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 945 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 946 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 947 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 948 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 949 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 950 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 951 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 952 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 953 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 954 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 955 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 956 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 957 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 958 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
6b0dd094 959 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 960 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
6b0dd094 961 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 962 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
6b0dd094 963 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 964 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
6b0dd094 965 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 966 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
6b0dd094 967 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 968 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 969
970 /* Cirrus coprocessor instructions. */
6b0dd094 971 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 972 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 973 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 974 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 975 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 976 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 977 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 978 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 979 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 980 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 981 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 982 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 983 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 984 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 985 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 986 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 987 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 988 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 989 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 990 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 991 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 992 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 993 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 994 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 995 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 996 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 997 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 998 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 999 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1000 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 1001 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1002 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 1003 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1004 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
6b0dd094 1005 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1006 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
6b0dd094 1007 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1008 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
6b0dd094 1009 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1010 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
6b0dd094 1011 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1012 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
6b0dd094 1013 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1014 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
6b0dd094 1015 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1016 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 1017 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1018 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
6b0dd094 1019 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1020 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 1021 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1022 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
6b0dd094 1023 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1024 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1025 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1026 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1027 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1028 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1029 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1030 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1031 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1032 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1033 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1034 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1035 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1036 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1037 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1038 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1039 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1040 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
6b0dd094 1041 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1042 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
6b0dd094 1043 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1044 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
6b0dd094 1045 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1046 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
6b0dd094 1047 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1048 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1049 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1050 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1051 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1052 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
6b0dd094 1053 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1054 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
6b0dd094 1055 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1056 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
6b0dd094 1057 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1058 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
6b0dd094 1059 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1060 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
6b0dd094 1061 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1062 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
6b0dd094 1063 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1064 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 1065 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1066 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 1067 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1068 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 1069 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1070 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 1071 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1072 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
6b0dd094 1073 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1074 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
6b0dd094 1075 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1076 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
6b0dd094 1077 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1078 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
6b0dd094 1079 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1080 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
6b0dd094 1081 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1082 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
6b0dd094 1083 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1084 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1085 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1086 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1087 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1088 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1089 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1090 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1091 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1092 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1093 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1094 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1095 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1096 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1097 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1098 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1099 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1100 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1101 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1102 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1103 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1104 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1105 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1106 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1107 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1108 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 1109 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1110 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 1111 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1112 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 1113 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1114 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 1115 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1116 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1117 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1118 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1119 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1120 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1121 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1122 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1123 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1124 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1125 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1126 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1127 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1128 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1129 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1130 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1131 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1132 0x0e000600, 0x0ff00f10,
1133 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1134 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1135 0x0e100600, 0x0ff00f10,
1136 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1137 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1138 0x0e200600, 0x0ff00f10,
1139 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1140 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1141 0x0e300600, 0x0ff00f10,
1142 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 1143
62f3b8c8 1144 /* VFP Fused multiply add instructions. */
6b0dd094 1145 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1146 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1147 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1148 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1149 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1150 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1151 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1152 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
6b0dd094 1153 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1154 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1155 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1156 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1157 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1158 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1159 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1160 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 1161
33399f07 1162 /* FP v5. */
6b0dd094 1163 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1164 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
6b0dd094 1165 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1166 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
6b0dd094 1167 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1168 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1169 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1170 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1171 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1172 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1173 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1174 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1175 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1176 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
6b0dd094 1177 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1178 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
6b0dd094 1179 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1180 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
6b0dd094 1181 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1182 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
6b0dd094 1183 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1184 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
6b0dd094 1185 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1186 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 1187
6b0dd094 1188 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
c28eeff2 1189 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
6b0dd094 1190 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1191 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1192 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1193 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1194 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1195 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1196 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1197 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1198 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1199 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1200 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1201 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1202 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1203 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
6b0dd094 1204 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1205 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
6b0dd094 1206 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1207 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
6b0dd094 1208 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1209 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
c28eeff2 1210
aab2c27d
MM		 1211 /* BFloat16 instructions. */
1212 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1213 0x0eb30940, 0x0fbf0f50, "vcvt%7?tb%b.bf16.f32\t%y1, %y0"},
1214
c604a79a 1215 /* Dot Product instructions in the space of coprocessor 13. */
6b0dd094 1216 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a 1217 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
6b0dd094 1218 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
aab2c27d 1219 0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
c604a79a 1220
dec41383 1221 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
6b0dd094 1222 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1223 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1224 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1225 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1226 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1227 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1228 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1229 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1230 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1231 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1232 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1233 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1234 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1235 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
6b0dd094 1236 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383
JW		 1237 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1238
b0c11777
RL		 1239 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1240 cp_num: bit <11:8> == 0b1001.
1241 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
6b0dd094 1242 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1243 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
6b0dd094 1244 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1245 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
6b0dd094 1246 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1247 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
6b0dd094 1248 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1249 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
6b0dd094 1250 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1251 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 1252 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1253 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
6b0dd094 1254 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1255 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
6b0dd094 1256 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1257 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
6b0dd094 1258 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1259 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
6b0dd094 1260 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1261 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
6b0dd094 1262 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1263 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1264 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1265 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1266 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1267 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1268 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1269 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1270 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1271 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
6b0dd094 1272 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1273 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
6b0dd094 1274 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1275 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
6b0dd094 1276 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1277 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
6b0dd094 1278 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1279 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1280 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1281 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1282 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1283 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1284 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1285 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1286 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1287 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
6b0dd094 1288 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1289 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
6b0dd094 1290 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1291 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
6b0dd094 1292 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1293 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1294 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1295 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
6b0dd094 1296 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1297 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1298 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1299 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1300 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1301 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1302 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1303 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
6b0dd094 1304 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1305 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
6b0dd094 1306 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1307 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
6b0dd094 1308 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1309 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
6b0dd094 1310 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777
RL		 1311 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1312
49e8a725 1313 /* ARMv8.3 javascript conversion instruction. */
6b0dd094 1314 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
49e8a725
SN		 1315 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1316
6b0dd094 1317 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 1318};
1319
33593eaf
MM		 1320/* Generic coprocessor instructions. These are only matched if a more specific
1321 SIMD or co-processor instruction does not match first. */
1322
1323static const struct sopcode32 generic_coprocessor_opcodes[] =
1324{
1325 /* Generic coprocessor instructions. */
1326 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1327 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
1328 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1329 0x0c500000, 0x0ff00000,
1330 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1331 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1332 0x0e000000, 0x0f000010,
1333 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1334 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1335 0x0e10f010, 0x0f10f010,
1336 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
1337 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1338 0x0e100010, 0x0f100010,
1339 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1340 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1341 0x0e000010, 0x0f100010,
1342 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1343 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1344 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
1345 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1346 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
1347
1348 /* V6 coprocessor instructions. */
1349 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1350 0xfc500000, 0xfff00000,
1351 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1352 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1353 0xfc400000, 0xfff00000,
1354 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
1355
1356 /* V5 coprocessor instructions. */
1357 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1358 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1359 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1360 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1361 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1362 0xfe000000, 0xff000010,
1363 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1364 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1365 0xfe000010, 0xff100010,
1366 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1367 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1368 0xfe100010, 0xff100010,
1369 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1370
1371 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1372};
1373
16980d0b
JB		 1374/* Neon opcode table: This does not encode the top byte -- that is
1375 checked by the print_insn_neon routine, as it depends on whether we are
1376 doing thumb32 or arm32 disassembly. */
1377
1378/* print_insn_neon recognizes the following format control codes:
1379
1380 %% %
1381
c22aaad1 1382 %c print condition code
e2efe87d
MGD		 1383 %u print condition code (unconditional in ARM mode,
1384 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 1385 %A print v{st,ld}[1234] operands
1386 %B print v{st,ld}[1234] any one operands
1387 %C print v{st,ld}[1234] single->all operands
1388 %D print scalar
1389 %E print vmov, vmvn, vorr, vbic encoded constant
1390 %F print vtbl,vtbx register list
1391
1392 %<bitfield>r print as an ARM register
1393 %<bitfield>d print the bitfield in decimal
1394 %<bitfield>e print the 2^N - bitfield in decimal
1395 %<bitfield>D print as a NEON D register
1396 %<bitfield>Q print as a NEON Q register
1397 %<bitfield>R print as a NEON D or Q register
1398 %<bitfield>Sn print byte scaled width limited by n
1399 %<bitfield>Tn print short scaled width limited by n
1400 %<bitfield>Un print long scaled width limited by n
43e65147 1401
16980d0b
JB		 1402 %<bitfield>'c print specified char iff bitfield is all ones
1403 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1404 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1405
1406static const struct opcode32 neon_opcodes[] =
1407{
fe56b6ce 1408 /* Extract. */
823d2571
TG		 1409 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1410 0xf2b00840, 0xffb00850,
1411 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1412 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1413 0xf2b00000, 0xffb00810,
1414 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 1415
9743db03
AV		 1416 /* Data transfer between ARM and NEON registers. */
1417 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1418 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1419 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1420 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1421 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1422 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1423 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1424 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1425 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1426 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1427 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1428 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1429
fe56b6ce 1430 /* Move data element to all lanes. */
823d2571
TG		 1431 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1432 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1433 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1434 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1435 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1436 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 1437
fe56b6ce 1438 /* Table lookup. */
823d2571
TG		 1439 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1440 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1441 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1442 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1443
8e79c3df 1444 /* Half-precision conversions. */
823d2571
TG		 1445 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1446 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1447 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1448 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1449
1450 /* NEON fused multiply add instructions. */
823d2571 1451 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1452 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1453 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1454 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1456 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1457 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1458 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1459
aab2c27d
MM		 1460 /* BFloat16 instructions. */
1461 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1462 0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1463 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1464 0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1465 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1466 0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1467 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1468 0xf3b60640, 0xffbf0fd0, "vcvt%c.bf16.f32\t%12-15,22D, %0-3,5Q"},
1469 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1470 0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1471 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1472 0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-2D[%3,5d]"},
1473
616ce08e
MM		 1474 /* Matrix Multiply instructions. */
1475 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1476 0xfc200c40, 0xffb00f50, "vsmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1477 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1478 0xfc200c50, 0xffb00f50, "vummla.u8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1479 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1480 0xfca00c40, 0xffb00f50, "vusmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1481 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1482 0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1483 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1484 0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1485 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1486 0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1487
fe56b6ce 1488 /* Two registers, miscellaneous. */
823d2571
TG		 1489 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1490 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1491 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1492 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1494 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1495 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1496 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1497 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1498 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1499 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1500 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1501 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1502 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1503 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1504 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1505 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1506 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1507 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1508 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1509 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1510 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1511 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1512 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1515 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1517 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1518 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1519 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1520 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1521 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1522 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1523 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1524 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1525 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1526 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1527 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1528 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1530 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1531 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1532 0xf3b20300, 0xffb30fd0,
1533 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1534 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1535 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1536 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1537 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1538 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1539 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1541 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1542 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1543 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1544 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1545 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1546 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1547 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1548 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1549 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1550 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1551 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1552 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1553 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1554 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1555 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1556 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1557 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1558 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1559 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1560 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1561 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1562 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1563 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1564 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1565 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1566 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1567 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1568 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1569 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1570 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1571 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1572 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1573 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1574 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1575 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1576 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1577 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1578 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1579 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1580 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301 1581 0xf3bb0600, 0xffbf0e10,
823d2571 1582 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1583 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1584 0xf3b70600, 0xffbf0e10,
1585 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
16980d0b 1586
fe56b6ce 1587 /* Three registers of the same length. */
823d2571
TG		 1588 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1589 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1590 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1591 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1592 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1593 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1594 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1595 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1596 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1597 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1598 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1599 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1600 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1601 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1602 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1603 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1604 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1605 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1606 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1607 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1608 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1609 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1610 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1611 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1612 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1613 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1614 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1615 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1616 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1617 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1618 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1619 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1621 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1622 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1623 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1624 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1625 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1626 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1627 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1628 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1629 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1630 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1631 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1632 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1633 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1634 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1635 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1636 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1637 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1638 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1639 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1640 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1641 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1642 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1643 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1644 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1645 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1646 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1647 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1648 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1649 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1650 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1651 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1652 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1653 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1654 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1655 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1656 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1657 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1658 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1659 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1660 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1661 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1662 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1663 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1664 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1665 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1666 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1667 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1668 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1669 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1670 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1671 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1672 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1673 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1674 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1675 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1676 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1677 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1678 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1679 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1680 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1681 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1682 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1683 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1684 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1685 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1687 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1688 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1689 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1691 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1692 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1693 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1694 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1695 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1696 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1697 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1698 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1699 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1700 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1701 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1702 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1703 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1704 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1705 0xf2000b00, 0xff800f10,
1706 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1707 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1708 0xf2000b10, 0xff800f10,
1709 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1710 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1711 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1712 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1713 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1714 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1715 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1716 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1717 0xf3000b00, 0xff800f10,
1718 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1719 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1720 0xf2000000, 0xfe800f10,
1721 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1722 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1723 0xf2000010, 0xfe800f10,
1724 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1725 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1726 0xf2000100, 0xfe800f10,
1727 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1728 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1729 0xf2000200, 0xfe800f10,
1730 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1731 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1732 0xf2000210, 0xfe800f10,
1733 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1734 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1735 0xf2000300, 0xfe800f10,
1736 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1737 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1738 0xf2000310, 0xfe800f10,
1739 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1740 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1741 0xf2000400, 0xfe800f10,
1742 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1743 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1744 0xf2000410, 0xfe800f10,
1745 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1746 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1747 0xf2000500, 0xfe800f10,
1748 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1749 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1750 0xf2000510, 0xfe800f10,
1751 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1753 0xf2000600, 0xfe800f10,
1754 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1755 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1756 0xf2000610, 0xfe800f10,
1757 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1758 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1759 0xf2000700, 0xfe800f10,
1760 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1761 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1762 0xf2000710, 0xfe800f10,
1763 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1764 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1765 0xf2000910, 0xfe800f10,
1766 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1767 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1768 0xf2000a00, 0xfe800f10,
1769 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1770 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1771 0xf2000a10, 0xfe800f10,
1772 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1773 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1774 0xf3000b10, 0xff800f10,
1775 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1776 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1777 0xf3000c10, 0xff800f10,
1778 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1779
fe56b6ce 1780 /* One register and an immediate value. */
823d2571
TG		 1781 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1782 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1783 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1784 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1785 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1786 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1787 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1788 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1789 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1790 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1791 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1792 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1793 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1794 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1795 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1796 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1797 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1798 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1799 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1800 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1801 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1802 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1803 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1804 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1805 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1806 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1807
fe56b6ce 1808 /* Two registers and a shift amount. */
823d2571
TG		 1809 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1810 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1811 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1812 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1813 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1814 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1815 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1816 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1817 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1818 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1819 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1820 0xf2880950, 0xfeb80fd0,
1821 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1822 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1823 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1824 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1825 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1826 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1827 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1828 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1829 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1830 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1831 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1832 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1833 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1834 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1835 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1836 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1837 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1838 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1839 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1840 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1841 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1842 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1843 0xf2900950, 0xfeb00fd0,
1844 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1845 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1846 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1847 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1848 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1849 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1850 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1851 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1852 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1853 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1854 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1855 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1856 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1857 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1858 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1859 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1860 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1861 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1862 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1863 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1864 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1865 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1866 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1867 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1868 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1869 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1870 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1871 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1872 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1873 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1874 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1875 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1876 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1877 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1878 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1879 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1880 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1881 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1882 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1883 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1884 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1885 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1886 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1887 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1888 0xf2a00950, 0xfea00fd0,
1889 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1890 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1891 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1892 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1893 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1894 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1895 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1896 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1897 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1898 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1899 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1900 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1901 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1902 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1903 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1904 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1905 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1906 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1907 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1908 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1909 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1910 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1911 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1912 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1913 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1914 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1915 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1916 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1917 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1918 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1919 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1920 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1921 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1922 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1923 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1924 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1925 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1926 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1927 0xf2a00e10, 0xfea00e90,
1928 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
cc933301
JW		 1929 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1930 0xf2a00c10, 0xfea00e90,
1931 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 1932
fe56b6ce 1933 /* Three registers of different lengths. */
823d2571
TG		 1934 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1935 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1936 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1937 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1938 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1939 0xf2800400, 0xff800f50,
1940 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1941 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1942 0xf2800600, 0xff800f50,
1943 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1944 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1945 0xf2800900, 0xff800f50,
1946 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1947 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1948 0xf2800b00, 0xff800f50,
1949 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1950 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1951 0xf2800d00, 0xff800f50,
1952 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1953 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1954 0xf3800400, 0xff800f50,
1955 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1956 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1957 0xf3800600, 0xff800f50,
1958 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1959 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1960 0xf2800000, 0xfe800f50,
1961 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1962 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1963 0xf2800100, 0xfe800f50,
1964 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1965 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1966 0xf2800200, 0xfe800f50,
1967 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1968 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1969 0xf2800300, 0xfe800f50,
1970 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1971 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1972 0xf2800500, 0xfe800f50,
1973 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1974 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1975 0xf2800700, 0xfe800f50,
1976 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1977 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1978 0xf2800800, 0xfe800f50,
1979 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1980 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1981 0xf2800a00, 0xfe800f50,
1982 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1983 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1984 0xf2800c00, 0xfe800f50,
1985 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 1986
fe56b6ce 1987 /* Two registers and a scalar. */
823d2571
TG		 1988 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1989 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1990 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1991 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1992 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1993 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1994 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1995 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1996 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1997 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1998 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1999 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2000 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2001 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 2002 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2003 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2004 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2005 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2006 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2007 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
2008 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2009 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 2010 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2011 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2012 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2013 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2014 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2015 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2016 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2017 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2018 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2019 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2020 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2021 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 2022 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2023 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2024 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2025 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2026 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2027 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 2028 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2029 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2030 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2031 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2032 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2033 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 2034 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2035 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2036 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2037 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2038 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2039 0xf2800240, 0xfe800f50,
2040 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2041 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2042 0xf2800640, 0xfe800f50,
2043 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2044 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2045 0xf2800a40, 0xfe800f50,
2046 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 2047 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2048 0xf2800e40, 0xff800f50,
2049 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2050 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2051 0xf2800f40, 0xff800f50,
2052 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2053 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2054 0xf3800e40, 0xff800f50,
2055 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2056 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2057 0xf3800f40, 0xff800f50,
2058 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
2059 },
16980d0b 2060
fe56b6ce 2061 /* Element and structure load/store. */
823d2571
TG		 2062 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2063 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
2064 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2065 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
2066 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2067 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
2068 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2069 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
2070 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2071 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
2072 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2073 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2074 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2075 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2076 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2077 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2078 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2079 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2080 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2081 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2082 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2083 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2084 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2085 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2086 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2087 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2088 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2089 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2090 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2091 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
2092 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2093 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
2094 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2095 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
2096 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2097 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
2098 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2099 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
2100
2101 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 2102};
2103
73cd51e5
AV		 2104/* mve opcode table. */
2105
2106/* print_insn_mve recognizes the following format control codes:
2107
2108 %% %
2109
ef1576a1
AV		 2110 %a print '+' or '-' or imm offset in vldr[bhwd] and
2111 vstr[bhwd]
9743db03 2112 %c print condition code
aef6d006
AV		 2113 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
2114 %u print 'U' (unsigned) or 'S' for various mve instructions
143275ea 2115 %i print MVE predicate(s) for vpt and vpst
23d00a41 2116 %j print a 5-bit immediate from hw2[14:12,7:6]
08132bdd 2117 %k print 48 if the 7th position bit is set else print 64.
bf0b396d 2118 %m print rounding mode for vcvt and vrint
143275ea 2119 %n print vector comparison code for predicated instruction
bf0b396d 2120 %s print size for various vcvt instructions
143275ea
AV		 2121 %v print vector predicate for instruction in predicated
2122 block
ef1576a1 2123 %o print offset scaled for vldr[hwd] and vstr[hwd]
04d54ace
AV		 2124 %w print writeback mode for MVE v{st,ld}[24]
2125 %B print v{st,ld}[24] any one operands
c507f10b
AV		 2126 %E print vmov, vmvn, vorr, vbic encoded constant
2127 %N print generic index for vmov
14925797 2128 %T print bottom ('b') or top ('t') of source register
d3b63143 2129 %X print exchange field in vmla* instructions
04d54ace 2130
9743db03 2131 %<bitfield>r print as an ARM register
04d54ace 2132 %<bitfield>d print the bitfield in decimal
d3b63143 2133 %<bitfield>A print accumulate or not
e39c1607
SD		 2134 %<bitfield>c print bitfield as a condition code
2135 %<bitfield>C print bitfield as an inverted condition code
143275ea 2136 %<bitfield>Q print as a MVE Q register
c507f10b 2137 %<bitfield>F print as a MVE S register
143275ea
AV		 2138 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
2139 UNPREDICTABLE
23d00a41
SD		 2140
2141 %<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE
143275ea 2142 %<bitfield>s print size for vector predicate & non VMOV instructions
66dcaa5d 2143 %<bitfield>I print carry flag or not
ef1576a1 2144 %<bitfield>i print immediate for vstr/vldr reg +/- imm
1c8f2df8 2145 %<bitfield>h print high half of 64-bit destination reg
bf0b396d 2146 %<bitfield>k print immediate for vector conversion instruction
1c8f2df8 2147 %<bitfield>l print low half of 64-bit destination reg
897b9bbc 2148 %<bitfield>o print rotate value for vcmul
1c8f2df8 2149 %<bitfield>u print immediate value for vddup/vdwdup
c507f10b 2150 %<bitfield>x print the bitfield in hex.
1c8f2df8 2151 */
73cd51e5
AV		 2152
2153static const struct mopcode32 mve_opcodes[] =
2154{
143275ea
AV		 2155 /* MVE. */
2156
2157 {ARM_FEATURE_COPROC (FPU_MVE),
2158 MVE_VPST,
2159 0xfe310f4d, 0xffbf1fff,
2160 "vpst%i"
2161 },
2162
2163 /* Floating point VPT T1. */
2164 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2165 MVE_VPT_FP_T1,
2166 0xee310f00, 0xefb10f50,
2167 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2168 /* Floating point VPT T2. */
2169 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2170 MVE_VPT_FP_T2,
2171 0xee310f40, 0xefb10f50,
2172 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2173
2174 /* Vector VPT T1. */
2175 {ARM_FEATURE_COPROC (FPU_MVE),
2176 MVE_VPT_VEC_T1,
2177 0xfe010f00, 0xff811f51,
2178 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2179 /* Vector VPT T2. */
2180 {ARM_FEATURE_COPROC (FPU_MVE),
2181 MVE_VPT_VEC_T2,
2182 0xfe010f01, 0xff811f51,
2183 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2184 /* Vector VPT T3. */
2185 {ARM_FEATURE_COPROC (FPU_MVE),
2186 MVE_VPT_VEC_T3,
2187 0xfe011f00, 0xff811f50,
2188 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2189 /* Vector VPT T4. */
2190 {ARM_FEATURE_COPROC (FPU_MVE),
2191 MVE_VPT_VEC_T4,
2192 0xfe010f40, 0xff811f70,
2193 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2194 /* Vector VPT T5. */
2195 {ARM_FEATURE_COPROC (FPU_MVE),
2196 MVE_VPT_VEC_T5,
2197 0xfe010f60, 0xff811f70,
2198 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2199 /* Vector VPT T6. */
2200 {ARM_FEATURE_COPROC (FPU_MVE),
2201 MVE_VPT_VEC_T6,
2202 0xfe011f40, 0xff811f50,
2203 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2204
c507f10b
AV		 2205 /* Vector VBIC immediate. */
2206 {ARM_FEATURE_COPROC (FPU_MVE),
2207 MVE_VBIC_IMM,
2208 0xef800070, 0xefb81070,
2209 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2210
2211 /* Vector VBIC register. */
2212 {ARM_FEATURE_COPROC (FPU_MVE),
2213 MVE_VBIC_REG,
2214 0xef100150, 0xffb11f51,
2215 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2216
66dcaa5d
AV		 2217 /* Vector VABAV. */
2218 {ARM_FEATURE_COPROC (FPU_MVE),
2219 MVE_VABAV,
2220 0xee800f01, 0xefc10f51,
2221 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2222
2223 /* Vector VABD floating point. */
2224 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2225 MVE_VABD_FP,
2226 0xff200d40, 0xffa11f51,
2227 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2228
2229 /* Vector VABD. */
2230 {ARM_FEATURE_COPROC (FPU_MVE),
2231 MVE_VABD_VEC,
2232 0xef000740, 0xef811f51,
2233 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2234
2235 /* Vector VABS floating point. */
2236 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2237 MVE_VABS_FP,
2238 0xFFB10740, 0xFFB31FD1,
2239 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2240 /* Vector VABS. */
2241 {ARM_FEATURE_COPROC (FPU_MVE),
2242 MVE_VABS_VEC,
2243 0xffb10340, 0xffb31fd1,
2244 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2245
2246 /* Vector VADD floating point T1. */
2247 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2248 MVE_VADD_FP_T1,
2249 0xef000d40, 0xffa11f51,
2250 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2251 /* Vector VADD floating point T2. */
2252 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2253 MVE_VADD_FP_T2,
2254 0xee300f40, 0xefb11f70,
2255 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2256 /* Vector VADD T1. */
2257 {ARM_FEATURE_COPROC (FPU_MVE),
2258 MVE_VADD_VEC_T1,
2259 0xef000840, 0xff811f51,
2260 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2261 /* Vector VADD T2. */
2262 {ARM_FEATURE_COPROC (FPU_MVE),
2263 MVE_VADD_VEC_T2,
2264 0xee010f40, 0xff811f70,
2265 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2266
d3b63143
AV		 2267 /* Vector VADDLV. */
2268 {ARM_FEATURE_COPROC (FPU_MVE),
2269 MVE_VADDLV,
2270 0xee890f00, 0xef8f1fd1,
2271 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2272
2273 /* Vector VADDV. */
2274 {ARM_FEATURE_COPROC (FPU_MVE),
2275 MVE_VADDV,
2276 0xeef10f00, 0xeff31fd1,
2277 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2278
66dcaa5d
AV		 2279 /* Vector VADC. */
2280 {ARM_FEATURE_COPROC (FPU_MVE),
2281 MVE_VADC,
2282 0xee300f00, 0xffb10f51,
2283 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2284
e523f101
AV		 2285 /* Vector VAND. */
2286 {ARM_FEATURE_COPROC (FPU_MVE),
2287 MVE_VAND,
2288 0xef000150, 0xffb11f51,
2289 "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2290
2291 /* Vector VBRSR register. */
2292 {ARM_FEATURE_COPROC (FPU_MVE),
2293 MVE_VBRSR,
2294 0xfe011e60, 0xff811f70,
2295 "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2296
897b9bbc
AV		 2297 /* Vector VCADD floating point. */
2298 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2299 MVE_VCADD_FP,
2300 0xfc800840, 0xfea11f51,
2301 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2302
2303 /* Vector VCADD. */
2304 {ARM_FEATURE_COPROC (FPU_MVE),
2305 MVE_VCADD_VEC,
2306 0xfe000f00, 0xff810f51,
2307 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2308
e523f101
AV		 2309 /* Vector VCLS. */
2310 {ARM_FEATURE_COPROC (FPU_MVE),
2311 MVE_VCLS,
2312 0xffb00440, 0xffb31fd1,
2313 "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2314
2315 /* Vector VCLZ. */
2316 {ARM_FEATURE_COPROC (FPU_MVE),
2317 MVE_VCLZ,
2318 0xffb004c0, 0xffb31fd1,
2319 "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2320
897b9bbc
AV		 2321 /* Vector VCMLA. */
2322 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2323 MVE_VCMLA_FP,
2324 0xfc200840, 0xfe211f51,
2325 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2326
143275ea
AV		 2327 /* Vector VCMP floating point T1. */
2328 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2329 MVE_VCMP_FP_T1,
2330 0xee310f00, 0xeff1ef50,
2331 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2332
2333 /* Vector VCMP floating point T2. */
2334 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2335 MVE_VCMP_FP_T2,
2336 0xee310f40, 0xeff1ef50,
2337 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2338
2339 /* Vector VCMP T1. */
2340 {ARM_FEATURE_COPROC (FPU_MVE),
2341 MVE_VCMP_VEC_T1,
2342 0xfe010f00, 0xffc1ff51,
2343 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2344 /* Vector VCMP T2. */
2345 {ARM_FEATURE_COPROC (FPU_MVE),
2346 MVE_VCMP_VEC_T2,
2347 0xfe010f01, 0xffc1ff51,
2348 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2349 /* Vector VCMP T3. */
2350 {ARM_FEATURE_COPROC (FPU_MVE),
2351 MVE_VCMP_VEC_T3,
2352 0xfe011f00, 0xffc1ff50,
2353 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2354 /* Vector VCMP T4. */
2355 {ARM_FEATURE_COPROC (FPU_MVE),
2356 MVE_VCMP_VEC_T4,
2357 0xfe010f40, 0xffc1ff70,
2358 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2359 /* Vector VCMP T5. */
2360 {ARM_FEATURE_COPROC (FPU_MVE),
2361 MVE_VCMP_VEC_T5,
2362 0xfe010f60, 0xffc1ff70,
2363 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2364 /* Vector VCMP T6. */
2365 {ARM_FEATURE_COPROC (FPU_MVE),
2366 MVE_VCMP_VEC_T6,
2367 0xfe011f40, 0xffc1ff50,
2368 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2369
9743db03
AV		 2370 /* Vector VDUP. */
2371 {ARM_FEATURE_COPROC (FPU_MVE),
2372 MVE_VDUP,
2373 0xeea00b10, 0xffb10f5f,
2374 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2375
2376 /* Vector VEOR. */
2377 {ARM_FEATURE_COPROC (FPU_MVE),
2378 MVE_VEOR,
2379 0xff000150, 0xffd11f51,
2380 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2381
2382 /* Vector VFMA, vector * scalar. */
2383 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2384 MVE_VFMA_FP_SCALAR,
2385 0xee310e40, 0xefb11f70,
2386 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2387
2388 /* Vector VFMA floating point. */
2389 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2390 MVE_VFMA_FP,
2391 0xef000c50, 0xffa11f51,
2392 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2393
2394 /* Vector VFMS floating point. */
2395 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2396 MVE_VFMS_FP,
2397 0xef200c50, 0xffa11f51,
2398 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2399
2400 /* Vector VFMAS, vector * scalar. */
2401 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2402 MVE_VFMAS_FP_SCALAR,
2403 0xee311e40, 0xefb11f70,
2404 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2405
2406 /* Vector VHADD T1. */
2407 {ARM_FEATURE_COPROC (FPU_MVE),
2408 MVE_VHADD_T1,
2409 0xef000040, 0xef811f51,
2410 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2411
2412 /* Vector VHADD T2. */
2413 {ARM_FEATURE_COPROC (FPU_MVE),
2414 MVE_VHADD_T2,
2415 0xee000f40, 0xef811f70,
2416 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2417
2418 /* Vector VHSUB T1. */
2419 {ARM_FEATURE_COPROC (FPU_MVE),
2420 MVE_VHSUB_T1,
2421 0xef000240, 0xef811f51,
2422 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2423
2424 /* Vector VHSUB T2. */
2425 {ARM_FEATURE_COPROC (FPU_MVE),
2426 MVE_VHSUB_T2,
2427 0xee001f40, 0xef811f70,
2428 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2429
897b9bbc
AV		 2430 /* Vector VCMUL. */
2431 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2432 MVE_VCMUL_FP,
2433 0xee300e00, 0xefb10f50,
2434 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2435
e523f101
AV		 2436 /* Vector VCTP. */
2437 {ARM_FEATURE_COPROC (FPU_MVE),
2438 MVE_VCTP,
2439 0xf000e801, 0xffc0ffff,
2440 "vctp%v.%20-21s\t%16-19r"},
2441
9743db03
AV		 2442 /* Vector VDUP. */
2443 {ARM_FEATURE_COPROC (FPU_MVE),
2444 MVE_VDUP,
2445 0xeea00b10, 0xffb10f5f,
2446 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2447
2448 /* Vector VRHADD. */
2449 {ARM_FEATURE_COPROC (FPU_MVE),
2450 MVE_VRHADD,
2451 0xef000140, 0xef811f51,
2452 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2453
bf0b396d
AV		 2454 /* Vector VCVT. */
2455 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2456 MVE_VCVT_FP_FIX_VEC,
2457 0xef800c50, 0xef801cd1,
2458 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2459
2460 /* Vector VCVT. */
2461 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2462 MVE_VCVT_BETWEEN_FP_INT,
2463 0xffb30640, 0xffb31e51,
2464 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2465
2466 /* Vector VCVT between single and half-precision float, bottom half. */
2467 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2468 MVE_VCVT_FP_HALF_FP,
2469 0xee3f0e01, 0xefbf1fd1,
2470 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2471
2472 /* Vector VCVT between single and half-precision float, top half. */
2473 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2474 MVE_VCVT_FP_HALF_FP,
2475 0xee3f1e01, 0xefbf1fd1,
2476 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2477
2478 /* Vector VCVT. */
2479 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2480 MVE_VCVT_FROM_FP_TO_INT,
2481 0xffb30040, 0xffb31c51,
2482 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2483
1c8f2df8
AV		 2484 /* Vector VDDUP. */
2485 {ARM_FEATURE_COPROC (FPU_MVE),
2486 MVE_VDDUP,
2487 0xee011f6e, 0xff811f7e,
2488 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2489
2490 /* Vector VDWDUP. */
2491 {ARM_FEATURE_COPROC (FPU_MVE),
2492 MVE_VDWDUP,
2493 0xee011f60, 0xff811f70,
2494 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2495
897b9bbc
AV		 2496 /* Vector VHCADD. */
2497 {ARM_FEATURE_COPROC (FPU_MVE),
2498 MVE_VHCADD,
2499 0xee000f00, 0xff810f51,
2500 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2501
1c8f2df8
AV		 2502 /* Vector VIWDUP. */
2503 {ARM_FEATURE_COPROC (FPU_MVE),
2504 MVE_VIWDUP,
2505 0xee010f60, 0xff811f70,
2506 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2507
2508 /* Vector VIDUP. */
2509 {ARM_FEATURE_COPROC (FPU_MVE),
2510 MVE_VIDUP,
2511 0xee010f6e, 0xff811f7e,
2512 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2513
04d54ace
AV		 2514 /* Vector VLD2. */
2515 {ARM_FEATURE_COPROC (FPU_MVE),
2516 MVE_VLD2,
2517 0xfc901e00, 0xff901e5f,
2518 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2519
2520 /* Vector VLD4. */
2521 {ARM_FEATURE_COPROC (FPU_MVE),
2522 MVE_VLD4,
2523 0xfc901e01, 0xff901e1f,
2524 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2525
ef1576a1
AV		 2526 /* Vector VLDRB gather load. */
2527 {ARM_FEATURE_COPROC (FPU_MVE),
2528 MVE_VLDRB_GATHER_T1,
2529 0xec900e00, 0xefb01e50,
2530 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2531
2532 /* Vector VLDRH gather load. */
2533 {ARM_FEATURE_COPROC (FPU_MVE),
2534 MVE_VLDRH_GATHER_T2,
2535 0xec900e10, 0xefb01e50,
2536 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2537
2538 /* Vector VLDRW gather load. */
2539 {ARM_FEATURE_COPROC (FPU_MVE),
2540 MVE_VLDRW_GATHER_T3,
2541 0xfc900f40, 0xffb01fd0,
2542 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2543
2544 /* Vector VLDRD gather load. */
2545 {ARM_FEATURE_COPROC (FPU_MVE),
2546 MVE_VLDRD_GATHER_T4,
2547 0xec900fd0, 0xefb01fd0,
2548 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2549
2550 /* Vector VLDRW gather load. */
2551 {ARM_FEATURE_COPROC (FPU_MVE),
2552 MVE_VLDRW_GATHER_T5,
2553 0xfd101e00, 0xff111f00,
2554 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2555
2556 /* Vector VLDRD gather load, variant T6. */
2557 {ARM_FEATURE_COPROC (FPU_MVE),
2558 MVE_VLDRD_GATHER_T6,
2559 0xfd101f00, 0xff111f00,
2560 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2561
aef6d006
AV		 2562 /* Vector VLDRB. */
2563 {ARM_FEATURE_COPROC (FPU_MVE),
2564 MVE_VLDRB_T1,
2565 0xec100e00, 0xee581e00,
2566 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2567
2568 /* Vector VLDRH. */
2569 {ARM_FEATURE_COPROC (FPU_MVE),
2570 MVE_VLDRH_T2,
2571 0xec180e00, 0xee581e00,
2572 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2573
2574 /* Vector VLDRB unsigned, variant T5. */
2575 {ARM_FEATURE_COPROC (FPU_MVE),
2576 MVE_VLDRB_T5,
2577 0xec101e00, 0xfe101f80,
2578 "vldrb%v.u8\t%13-15,22Q, %d"},
2579
2580 /* Vector VLDRH unsigned, variant T6. */
2581 {ARM_FEATURE_COPROC (FPU_MVE),
2582 MVE_VLDRH_T6,
2583 0xec101e80, 0xfe101f80,
2584 "vldrh%v.u16\t%13-15,22Q, %d"},
2585
2586 /* Vector VLDRW unsigned, variant T7. */
2587 {ARM_FEATURE_COPROC (FPU_MVE),
2588 MVE_VLDRW_T7,
2589 0xec101f00, 0xfe101f80,
2590 "vldrw%v.u32\t%13-15,22Q, %d"},
2591
56858bea
AV		 2592 /* Vector VMAX. */
2593 {ARM_FEATURE_COPROC (FPU_MVE),
2594 MVE_VMAX,
2595 0xef000640, 0xef811f51,
2596 "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2597
2598 /* Vector VMAXA. */
2599 {ARM_FEATURE_COPROC (FPU_MVE),
2600 MVE_VMAXA,
2601 0xee330e81, 0xffb31fd1,
2602 "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2603
2604 /* Vector VMAXNM floating point. */
2605 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2606 MVE_VMAXNM_FP,
2607 0xff000f50, 0xffa11f51,
2608 "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2609
2610 /* Vector VMAXNMA floating point. */
2611 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2612 MVE_VMAXNMA_FP,
2613 0xee3f0e81, 0xefbf1fd1,
2614 "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2615
2616 /* Vector VMAXNMV floating point. */
2617 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2618 MVE_VMAXNMV_FP,
2619 0xeeee0f00, 0xefff0fd1,
2620 "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2621
2622 /* Vector VMAXNMAV floating point. */
2623 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2624 MVE_VMAXNMAV_FP,
2625 0xeeec0f00, 0xefff0fd1,
2626 "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2627
2628 /* Vector VMAXV. */
2629 {ARM_FEATURE_COPROC (FPU_MVE),
2630 MVE_VMAXV,
2631 0xeee20f00, 0xeff30fd1,
2632 "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2633
2634 /* Vector VMAXAV. */
2635 {ARM_FEATURE_COPROC (FPU_MVE),
2636 MVE_VMAXAV,
2637 0xeee00f00, 0xfff30fd1,
2638 "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2639
2640 /* Vector VMIN. */
2641 {ARM_FEATURE_COPROC (FPU_MVE),
2642 MVE_VMIN,
2643 0xef000650, 0xef811f51,
2644 "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2645
2646 /* Vector VMINA. */
2647 {ARM_FEATURE_COPROC (FPU_MVE),
2648 MVE_VMINA,
2649 0xee331e81, 0xffb31fd1,
2650 "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2651
2652 /* Vector VMINNM floating point. */
2653 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2654 MVE_VMINNM_FP,
2655 0xff200f50, 0xffa11f51,
2656 "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2657
2658 /* Vector VMINNMA floating point. */
2659 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2660 MVE_VMINNMA_FP,
2661 0xee3f1e81, 0xefbf1fd1,
2662 "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2663
2664 /* Vector VMINNMV floating point. */
2665 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2666 MVE_VMINNMV_FP,
2667 0xeeee0f80, 0xefff0fd1,
2668 "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2669
2670 /* Vector VMINNMAV floating point. */
2671 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2672 MVE_VMINNMAV_FP,
2673 0xeeec0f80, 0xefff0fd1,
2674 "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2675
2676 /* Vector VMINV. */
2677 {ARM_FEATURE_COPROC (FPU_MVE),
2678 MVE_VMINV,
2679 0xeee20f80, 0xeff30fd1,
2680 "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2681
2682 /* Vector VMINAV. */
2683 {ARM_FEATURE_COPROC (FPU_MVE),
2684 MVE_VMINAV,
2685 0xeee00f80, 0xfff30fd1,
2686 "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2687
2688 /* Vector VMLA. */
2689 {ARM_FEATURE_COPROC (FPU_MVE),
2690 MVE_VMLA,
2691 0xee010e40, 0xef811f70,
2692 "vmla%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2693
d3b63143
AV		 2694 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2695 opcode aliasing. */
2696 {ARM_FEATURE_COPROC (FPU_MVE),
2697 MVE_VMLALDAV,
2698 0xee801e00, 0xef801f51,
2699 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2700
2701 {ARM_FEATURE_COPROC (FPU_MVE),
2702 MVE_VMLALDAV,
2703 0xee800e00, 0xef801f51,
2704 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2705
2706 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2707 {ARM_FEATURE_COPROC (FPU_MVE),
2708 MVE_VMLADAV_T1,
2709 0xeef00e00, 0xeff01f51,
2710 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2711
2712 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2713 {ARM_FEATURE_COPROC (FPU_MVE),
2714 MVE_VMLADAV_T2,
2715 0xeef00f00, 0xeff11f51,
2716 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2717
2718 /* Vector VMLADAV T1 variant. */
2719 {ARM_FEATURE_COPROC (FPU_MVE),
2720 MVE_VMLADAV_T1,
2721 0xeef01e00, 0xeff01f51,
2722 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2723
2724 /* Vector VMLADAV T2 variant. */
2725 {ARM_FEATURE_COPROC (FPU_MVE),
2726 MVE_VMLADAV_T2,
2727 0xeef01f00, 0xeff11f51,
2728 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2729
2730 /* Vector VMLAS. */
2731 {ARM_FEATURE_COPROC (FPU_MVE),
2732 MVE_VMLAS,
2733 0xee011e40, 0xef811f70,
2734 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2735
2736 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2737 opcode aliasing. */
2738 {ARM_FEATURE_COPROC (FPU_MVE),
2739 MVE_VRMLSLDAVH,
2740 0xfe800e01, 0xff810f51,
2741 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2742
2743 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2744 opcdoe aliasing. */
2745 {ARM_FEATURE_COPROC (FPU_MVE),
2746 MVE_VMLSLDAV,
2747 0xee800e01, 0xff800f51,
2748 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2749
2750 /* Vector VMLSDAV T1 Variant. */
2751 {ARM_FEATURE_COPROC (FPU_MVE),
2752 MVE_VMLSDAV_T1,
2753 0xeef00e01, 0xfff00f51,
2754 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2755
2756 /* Vector VMLSDAV T2 Variant. */
2757 {ARM_FEATURE_COPROC (FPU_MVE),
2758 MVE_VMLSDAV_T2,
2759 0xfef00e01, 0xfff10f51,
2760 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2761
c507f10b
AV		 2762 /* Vector VMOV between gpr and half precision register, op == 0. */
2763 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2764 MVE_VMOV_HFP_TO_GP,
2765 0xee000910, 0xfff00f7f,
2766 "vmov.f16\t%7,16-19F, %12-15r"},
2767
2768 /* Vector VMOV between gpr and half precision register, op == 1. */
2769 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2770 MVE_VMOV_HFP_TO_GP,
2771 0xee100910, 0xfff00f7f,
2772 "vmov.f16\t%12-15r, %7,16-19F"},
2773
2774 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2775 MVE_VMOV_GP_TO_VEC_LANE,
2776 0xee000b10, 0xff900f1f,
2777 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2778
2779 /* Vector VORR immediate to vector.
2780 NOTE: MVE_VORR_IMM must appear in the table
2781 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2782 {ARM_FEATURE_COPROC (FPU_MVE),
2783 MVE_VORR_IMM,
2784 0xef800050, 0xefb810f0,
2785 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2786
ed63aa17
AV		 2787 /* Vector VQSHL T2 Variant.
2788 NOTE: MVE_VQSHL_T2 must appear in the table before
2789 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2790 {ARM_FEATURE_COPROC (FPU_MVE),
2791 MVE_VQSHL_T2,
2792 0xef800750, 0xef801fd1,
2793 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2794
2795 /* Vector VQSHLU T3 Variant
2796 NOTE: MVE_VQSHL_T2 must appear in the table before
2797 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2798
2799 {ARM_FEATURE_COPROC (FPU_MVE),
2800 MVE_VQSHLU_T3,
2801 0xff800650, 0xff801fd1,
2802 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2803
2804 /* Vector VRSHR
2805 NOTE: MVE_VRSHR must appear in the table before
2806 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2807 {ARM_FEATURE_COPROC (FPU_MVE),
2808 MVE_VRSHR,
2809 0xef800250, 0xef801fd1,
2810 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2811
2812 /* Vector VSHL.
2813 NOTE: MVE_VSHL must appear in the table before
2814 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2815 {ARM_FEATURE_COPROC (FPU_MVE),
2816 MVE_VSHL_T1,
2817 0xef800550, 0xff801fd1,
2818 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2819
2820 /* Vector VSHR
2821 NOTE: MVE_VSHR must appear in the table before
2822 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2823 {ARM_FEATURE_COPROC (FPU_MVE),
2824 MVE_VSHR,
2825 0xef800050, 0xef801fd1,
2826 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2827
2828 /* Vector VSLI
2829 NOTE: MVE_VSLI must appear in the table before
2830 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2831 {ARM_FEATURE_COPROC (FPU_MVE),
2832 MVE_VSLI,
2833 0xff800550, 0xff801fd1,
2834 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2835
2836 /* Vector VSRI
2837 NOTE: MVE_VSRI must appear in the table before
2838 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2839 {ARM_FEATURE_COPROC (FPU_MVE),
2840 MVE_VSRI,
2841 0xff800450, 0xff801fd1,
2842 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2843
c507f10b
AV		 2844 /* Vector VMOV immediate to vector,
2845 cmode == 11x1 -> VMVN which is UNDEFINED
2846 for such a cmode. */
2847 {ARM_FEATURE_COPROC (FPU_MVE),
2848 MVE_VMVN_IMM, 0xef800d50, 0xefb81dd0, UNDEFINED_INSTRUCTION},
2849
2850 /* Vector VMOV immediate to vector. */
2851 {ARM_FEATURE_COPROC (FPU_MVE),
2852 MVE_VMOV_IMM_TO_VEC,
2853 0xef800050, 0xefb810d0,
2854 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2855
2856 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2857 {ARM_FEATURE_COPROC (FPU_MVE),
2858 MVE_VMOV2_VEC_LANE_TO_GP,
2859 0xec000f00, 0xffb01ff0,
2860 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2861
2862 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2863 {ARM_FEATURE_COPROC (FPU_MVE),
2864 MVE_VMOV2_VEC_LANE_TO_GP,
2865 0xec000f10, 0xffb01ff0,
2866 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2867
2868 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2869 {ARM_FEATURE_COPROC (FPU_MVE),
2870 MVE_VMOV2_GP_TO_VEC_LANE,
2871 0xec100f00, 0xffb01ff0,
2872 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2873
2874 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2875 {ARM_FEATURE_COPROC (FPU_MVE),
2876 MVE_VMOV2_GP_TO_VEC_LANE,
2877 0xec100f10, 0xffb01ff0,
2878 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2879
2880 /* Vector VMOV Vector lane to gpr. */
2881 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2882 MVE_VMOV_VEC_LANE_TO_GP,
2883 0xee100b10, 0xff100f1f,
2884 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2885
ed63aa17
AV		 2886 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
2887 to instruction opcode aliasing. */
2888 {ARM_FEATURE_COPROC (FPU_MVE),
2889 MVE_VSHLL_T1,
2890 0xeea00f40, 0xefa00fd1,
2891 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2892
14925797
AV		 2893 /* Vector VMOVL long. */
2894 {ARM_FEATURE_COPROC (FPU_MVE),
2895 MVE_VMOVL,
2896 0xeea00f40, 0xefa70fd1,
2897 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2898
2899 /* Vector VMOV and narrow. */
2900 {ARM_FEATURE_COPROC (FPU_MVE),
2901 MVE_VMOVN,
2902 0xfe310e81, 0xffb30fd1,
2903 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2904
c507f10b
AV		 2905 /* Floating point move extract. */
2906 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2907 MVE_VMOVX,
2908 0xfeb00a40, 0xffbf0fd0,
2909 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2910
f49bb598
AV		 2911 /* Vector VMUL floating-point T1 variant. */
2912 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2913 MVE_VMUL_FP_T1,
2914 0xff000d50, 0xffa11f51,
2915 "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2916
2917 /* Vector VMUL floating-point T2 variant. */
2918 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2919 MVE_VMUL_FP_T2,
2920 0xee310e60, 0xefb11f70,
2921 "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2922
2923 /* Vector VMUL T1 variant. */
2924 {ARM_FEATURE_COPROC (FPU_MVE),
2925 MVE_VMUL_VEC_T1,
2926 0xef000950, 0xff811f51,
2927 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2928
2929 /* Vector VMUL T2 variant. */
2930 {ARM_FEATURE_COPROC (FPU_MVE),
2931 MVE_VMUL_VEC_T2,
2932 0xee011e60, 0xff811f70,
2933 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2934
2935 /* Vector VMULH. */
2936 {ARM_FEATURE_COPROC (FPU_MVE),
2937 MVE_VMULH,
2938 0xee010e01, 0xef811f51,
2939 "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2940
2941 /* Vector VRMULH. */
2942 {ARM_FEATURE_COPROC (FPU_MVE),
2943 MVE_VRMULH,
2944 0xee011e01, 0xef811f51,
2945 "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2946
14925797
AV		 2947 /* Vector VMULL integer. */
2948 {ARM_FEATURE_COPROC (FPU_MVE),
2949 MVE_VMULL_INT,
2950 0xee010e00, 0xef810f51,
2951 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2952
2953 /* Vector VMULL polynomial. */
2954 {ARM_FEATURE_COPROC (FPU_MVE),
2955 MVE_VMULL_POLY,
2956 0xee310e00, 0xefb10f51,
2957 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2958
c507f10b
AV		 2959 /* Vector VMVN immediate to vector. */
2960 {ARM_FEATURE_COPROC (FPU_MVE),
2961 MVE_VMVN_IMM,
2962 0xef800070, 0xefb810f0,
2963 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2964
2965 /* Vector VMVN register. */
2966 {ARM_FEATURE_COPROC (FPU_MVE),
2967 MVE_VMVN_REG,
2968 0xffb005c0, 0xffbf1fd1,
2969 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2970
f49bb598
AV		 2971 /* Vector VNEG floating point. */
2972 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2973 MVE_VNEG_FP,
2974 0xffb107c0, 0xffb31fd1,
2975 "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2976
2977 /* Vector VNEG. */
2978 {ARM_FEATURE_COPROC (FPU_MVE),
2979 MVE_VNEG_VEC,
2980 0xffb103c0, 0xffb31fd1,
2981 "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2982
c507f10b
AV		 2983 /* Vector VORN, vector bitwise or not. */
2984 {ARM_FEATURE_COPROC (FPU_MVE),
2985 MVE_VORN,
2986 0xef300150, 0xffb11f51,
2987 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2988
2989 /* Vector VORR register. */
2990 {ARM_FEATURE_COPROC (FPU_MVE),
2991 MVE_VORR_REG,
2992 0xef200150, 0xffb11f51,
2993 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2994
c4a23bf8
SP		 2995 /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if
2996 "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen
2997 MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes
2998 array. */
2999
3000 {ARM_FEATURE_COPROC (FPU_MVE),
3001 MVE_VMOV_VEC_TO_VEC,
3002 0xef200150, 0xffb11f51,
3003 "vmov%v\t%13-15,22Q, %17-19,7Q"},
3004
14925797
AV		 3005 /* Vector VQDMULL T1 variant. */
3006 {ARM_FEATURE_COPROC (FPU_MVE),
3007 MVE_VQDMULL_T1,
3008 0xee300f01, 0xefb10f51,
3009 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3010
14b456f2
AV		 3011 /* Vector VPNOT. */
3012 {ARM_FEATURE_COPROC (FPU_MVE),
3013 MVE_VPNOT,
3014 0xfe310f4d, 0xffffffff,
3015 "vpnot%v"},
3016
3017 /* Vector VPSEL. */
3018 {ARM_FEATURE_COPROC (FPU_MVE),
3019 MVE_VPSEL,
3020 0xfe310f01, 0xffb11f51,
3021 "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3022
3023 /* Vector VQABS. */
3024 {ARM_FEATURE_COPROC (FPU_MVE),
3025 MVE_VQABS,
3026 0xffb00740, 0xffb31fd1,
3027 "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3028
3029 /* Vector VQADD T1 variant. */
3030 {ARM_FEATURE_COPROC (FPU_MVE),
3031 MVE_VQADD_T1,
3032 0xef000050, 0xef811f51,
3033 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3034
3035 /* Vector VQADD T2 variant. */
3036 {ARM_FEATURE_COPROC (FPU_MVE),
3037 MVE_VQADD_T2,
3038 0xee000f60, 0xef811f70,
3039 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3040
14925797
AV		 3041 /* Vector VQDMULL T2 variant. */
3042 {ARM_FEATURE_COPROC (FPU_MVE),
3043 MVE_VQDMULL_T2,
3044 0xee300f60, 0xefb10f70,
3045 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3046
3047 /* Vector VQMOVN. */
3048 {ARM_FEATURE_COPROC (FPU_MVE),
3049 MVE_VQMOVN,
3050 0xee330e01, 0xefb30fd1,
3051 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
3052
3053 /* Vector VQMOVUN. */
3054 {ARM_FEATURE_COPROC (FPU_MVE),
3055 MVE_VQMOVUN,
3056 0xee310e81, 0xffb30fd1,
3057 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3058
d3b63143
AV		 3059 /* Vector VQDMLADH. */
3060 {ARM_FEATURE_COPROC (FPU_MVE),
3061 MVE_VQDMLADH,
3062 0xee000e00, 0xff810f51,
3063 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3064
3065 /* Vector VQRDMLADH. */
3066 {ARM_FEATURE_COPROC (FPU_MVE),
3067 MVE_VQRDMLADH,
3068 0xee000e01, 0xff810f51,
3069 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3070
3071 /* Vector VQDMLAH. */
3072 {ARM_FEATURE_COPROC (FPU_MVE),
3073 MVE_VQDMLAH,
23d188c7 3074 0xee000e60, 0xff811f70,
d3b63143
AV		 3075 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3076
3077 /* Vector VQRDMLAH. */
3078 {ARM_FEATURE_COPROC (FPU_MVE),
3079 MVE_VQRDMLAH,
23d188c7 3080 0xee000e40, 0xff811f70,
d3b63143
AV		 3081 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3082
3083 /* Vector VQDMLASH. */
3084 {ARM_FEATURE_COPROC (FPU_MVE),
3085 MVE_VQDMLASH,
23d188c7 3086 0xee001e60, 0xff811f70,
d3b63143
AV		 3087 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3088
3089 /* Vector VQRDMLASH. */
3090 {ARM_FEATURE_COPROC (FPU_MVE),
3091 MVE_VQRDMLASH,
23d188c7 3092 0xee001e40, 0xff811f70,
d3b63143
AV		 3093 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3094
3095 /* Vector VQDMLSDH. */
3096 {ARM_FEATURE_COPROC (FPU_MVE),
3097 MVE_VQDMLSDH,
3098 0xfe000e00, 0xff810f51,
3099 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3100
3101 /* Vector VQRDMLSDH. */
3102 {ARM_FEATURE_COPROC (FPU_MVE),
3103 MVE_VQRDMLSDH,
3104 0xfe000e01, 0xff810f51,
3105 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3106
3107 /* Vector VQDMULH T1 variant. */
3108 {ARM_FEATURE_COPROC (FPU_MVE),
3109 MVE_VQDMULH_T1,
3110 0xef000b40, 0xff811f51,
3111 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3112
3113 /* Vector VQRDMULH T2 variant. */
3114 {ARM_FEATURE_COPROC (FPU_MVE),
3115 MVE_VQRDMULH_T2,
3116 0xff000b40, 0xff811f51,
3117 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3118
3119 /* Vector VQDMULH T3 variant. */
3120 {ARM_FEATURE_COPROC (FPU_MVE),
3121 MVE_VQDMULH_T3,
3122 0xee010e60, 0xff811f70,
3123 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3124
3125 /* Vector VQRDMULH T4 variant. */
3126 {ARM_FEATURE_COPROC (FPU_MVE),
3127 MVE_VQRDMULH_T4,
3128 0xfe010e60, 0xff811f70,
3129 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3130
14b456f2
AV		 3131 /* Vector VQNEG. */
3132 {ARM_FEATURE_COPROC (FPU_MVE),
3133 MVE_VQNEG,
3134 0xffb007c0, 0xffb31fd1,
3135 "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3136
ed63aa17
AV		 3137 /* Vector VQRSHL T1 variant. */
3138 {ARM_FEATURE_COPROC (FPU_MVE),
3139 MVE_VQRSHL_T1,
3140 0xef000550, 0xef811f51,
3141 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3142
3143 /* Vector VQRSHL T2 variant. */
3144 {ARM_FEATURE_COPROC (FPU_MVE),
3145 MVE_VQRSHL_T2,
3146 0xee331ee0, 0xefb31ff0,
3147 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3148
3149 /* Vector VQRSHRN. */
3150 {ARM_FEATURE_COPROC (FPU_MVE),
3151 MVE_VQRSHRN,
3152 0xee800f41, 0xefa00fd1,
3153 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3154
3155 /* Vector VQRSHRUN. */
3156 {ARM_FEATURE_COPROC (FPU_MVE),
3157 MVE_VQRSHRUN,
3158 0xfe800fc0, 0xffa00fd1,
3159 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3160
3161 /* Vector VQSHL T1 Variant. */
3162 {ARM_FEATURE_COPROC (FPU_MVE),
3163 MVE_VQSHL_T1,
3164 0xee311ee0, 0xefb31ff0,
3165 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3166
3167 /* Vector VQSHL T4 Variant. */
3168 {ARM_FEATURE_COPROC (FPU_MVE),
3169 MVE_VQSHL_T4,
3170 0xef000450, 0xef811f51,
3171 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3172
3173 /* Vector VQSHRN. */
3174 {ARM_FEATURE_COPROC (FPU_MVE),
3175 MVE_VQSHRN,
3176 0xee800f40, 0xefa00fd1,
3177 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3178
3179 /* Vector VQSHRUN. */
3180 {ARM_FEATURE_COPROC (FPU_MVE),
3181 MVE_VQSHRUN,
3182 0xee800fc0, 0xffa00fd1,
3183 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3184
14b456f2
AV		 3185 /* Vector VQSUB T1 Variant. */
3186 {ARM_FEATURE_COPROC (FPU_MVE),
3187 MVE_VQSUB_T1,
3188 0xef000250, 0xef811f51,
3189 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3190
3191 /* Vector VQSUB T2 Variant. */
3192 {ARM_FEATURE_COPROC (FPU_MVE),
3193 MVE_VQSUB_T2,
3194 0xee001f60, 0xef811f70,
3195 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3196
3197 /* Vector VREV16. */
3198 {ARM_FEATURE_COPROC (FPU_MVE),
3199 MVE_VREV16,
3200 0xffb00140, 0xffb31fd1,
3201 "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
3202
3203 /* Vector VREV32. */
3204 {ARM_FEATURE_COPROC (FPU_MVE),
3205 MVE_VREV32,
3206 0xffb000c0, 0xffb31fd1,
3207 "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3208
3209 /* Vector VREV64. */
3210 {ARM_FEATURE_COPROC (FPU_MVE),
3211 MVE_VREV64,
3212 0xffb00040, 0xffb31fd1,
3213 "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3214
bf0b396d
AV		 3215 /* Vector VRINT floating point. */
3216 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3217 MVE_VRINT_FP,
3218 0xffb20440, 0xffb31c51,
3219 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3220
d3b63143
AV		 3221 /* Vector VRMLALDAVH. */
3222 {ARM_FEATURE_COPROC (FPU_MVE),
3223 MVE_VRMLALDAVH,
3224 0xee800f00, 0xef811f51,
3225 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3226
3227 /* Vector VRMLALDAVH. */
3228 {ARM_FEATURE_COPROC (FPU_MVE),
3229 MVE_VRMLALDAVH,
3230 0xee801f00, 0xef811f51,
3231 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3232
ed63aa17
AV		 3233 /* Vector VRSHL T1 Variant. */
3234 {ARM_FEATURE_COPROC (FPU_MVE),
3235 MVE_VRSHL_T1,
3236 0xef000540, 0xef811f51,
3237 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3238
3239 /* Vector VRSHL T2 Variant. */
3240 {ARM_FEATURE_COPROC (FPU_MVE),
3241 MVE_VRSHL_T2,
3242 0xee331e60, 0xefb31ff0,
3243 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3244
3245 /* Vector VRSHRN. */
3246 {ARM_FEATURE_COPROC (FPU_MVE),
3247 MVE_VRSHRN,
3248 0xfe800fc1, 0xffa00fd1,
3249 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3250
66dcaa5d
AV		 3251 /* Vector VSBC. */
3252 {ARM_FEATURE_COPROC (FPU_MVE),
3253 MVE_VSBC,
3254 0xfe300f00, 0xffb10f51,
3255 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3256
ed63aa17
AV		 3257 /* Vector VSHL T2 Variant. */
3258 {ARM_FEATURE_COPROC (FPU_MVE),
3259 MVE_VSHL_T2,
3260 0xee311e60, 0xefb31ff0,
3261 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3262
3263 /* Vector VSHL T3 Variant. */
3264 {ARM_FEATURE_COPROC (FPU_MVE),
3265 MVE_VSHL_T3,
3266 0xef000440, 0xef811f51,
3267 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3268
3269 /* Vector VSHLC. */
3270 {ARM_FEATURE_COPROC (FPU_MVE),
3271 MVE_VSHLC,
3272 0xeea00fc0, 0xffa01ff0,
3273 "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
3274
3275 /* Vector VSHLL T2 Variant. */
3276 {ARM_FEATURE_COPROC (FPU_MVE),
3277 MVE_VSHLL_T2,
3278 0xee310e01, 0xefb30fd1,
3279 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
3280
3281 /* Vector VSHRN. */
3282 {ARM_FEATURE_COPROC (FPU_MVE),
3283 MVE_VSHRN,
3284 0xee800fc1, 0xffa00fd1,
3285 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3286
04d54ace
AV		 3287 /* Vector VST2 no writeback. */
3288 {ARM_FEATURE_COPROC (FPU_MVE),
3289 MVE_VST2,
3290 0xfc801e00, 0xffb01e5f,
3291 "vst2%5d.%7-8s\t%B, [%16-19r]"},
3292
3293 /* Vector VST2 writeback. */
3294 {ARM_FEATURE_COPROC (FPU_MVE),
3295 MVE_VST2,
3296 0xfca01e00, 0xffb01e5f,
3297 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3298
3299 /* Vector VST4 no writeback. */
3300 {ARM_FEATURE_COPROC (FPU_MVE),
3301 MVE_VST4,
3302 0xfc801e01, 0xffb01e1f,
3303 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3304
3305 /* Vector VST4 writeback. */
3306 {ARM_FEATURE_COPROC (FPU_MVE),
3307 MVE_VST4,
3308 0xfca01e01, 0xffb01e1f,
3309 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3310
ef1576a1
AV		 3311 /* Vector VSTRB scatter store, T1 variant. */
3312 {ARM_FEATURE_COPROC (FPU_MVE),
3313 MVE_VSTRB_SCATTER_T1,
3314 0xec800e00, 0xffb01e50,
3315 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3316
3317 /* Vector VSTRH scatter store, T2 variant. */
3318 {ARM_FEATURE_COPROC (FPU_MVE),
3319 MVE_VSTRH_SCATTER_T2,
3320 0xec800e10, 0xffb01e50,
3321 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3322
3323 /* Vector VSTRW scatter store, T3 variant. */
3324 {ARM_FEATURE_COPROC (FPU_MVE),
3325 MVE_VSTRW_SCATTER_T3,
3326 0xec800e40, 0xffb01e50,
3327 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3328
3329 /* Vector VSTRD scatter store, T4 variant. */
3330 {ARM_FEATURE_COPROC (FPU_MVE),
3331 MVE_VSTRD_SCATTER_T4,
3332 0xec800fd0, 0xffb01fd0,
3333 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3334
3335 /* Vector VSTRW scatter store, T5 variant. */
3336 {ARM_FEATURE_COPROC (FPU_MVE),
3337 MVE_VSTRW_SCATTER_T5,
3338 0xfd001e00, 0xff111f00,
3339 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3340
3341 /* Vector VSTRD scatter store, T6 variant. */
3342 {ARM_FEATURE_COPROC (FPU_MVE),
3343 MVE_VSTRD_SCATTER_T6,
3344 0xfd001f00, 0xff111f00,
3345 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3346
aef6d006
AV		 3347 /* Vector VSTRB. */
3348 {ARM_FEATURE_COPROC (FPU_MVE),
3349 MVE_VSTRB_T1,
3350 0xec000e00, 0xfe581e00,
3351 "vstrb%v.%7-8s\t%13-15Q, %d"},
3352
3353 /* Vector VSTRH. */
3354 {ARM_FEATURE_COPROC (FPU_MVE),
3355 MVE_VSTRH_T2,
3356 0xec080e00, 0xfe581e00,
3357 "vstrh%v.%7-8s\t%13-15Q, %d"},
3358
3359 /* Vector VSTRB variant T5. */
3360 {ARM_FEATURE_COPROC (FPU_MVE),
3361 MVE_VSTRB_T5,
3362 0xec001e00, 0xfe101f80,
3363 "vstrb%v.8\t%13-15,22Q, %d"},
3364
3365 /* Vector VSTRH variant T6. */
3366 {ARM_FEATURE_COPROC (FPU_MVE),
3367 MVE_VSTRH_T6,
3368 0xec001e80, 0xfe101f80,
3369 "vstrh%v.16\t%13-15,22Q, %d"},
3370
3371 /* Vector VSTRW variant T7. */
3372 {ARM_FEATURE_COPROC (FPU_MVE),
3373 MVE_VSTRW_T7,
3374 0xec001f00, 0xfe101f80,
3375 "vstrw%v.32\t%13-15,22Q, %d"},
3376
66dcaa5d
AV		 3377 /* Vector VSUB floating point T1 variant. */
3378 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3379 MVE_VSUB_FP_T1,
3380 0xef200d40, 0xffa11f51,
3381 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3382
3383 /* Vector VSUB floating point T2 variant. */
3384 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3385 MVE_VSUB_FP_T2,
3386 0xee301f40, 0xefb11f70,
3387 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3388
3389 /* Vector VSUB T1 variant. */
3390 {ARM_FEATURE_COPROC (FPU_MVE),
3391 MVE_VSUB_VEC_T1,
3392 0xff000840, 0xff811f51,
3393 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3394
3395 /* Vector VSUB T2 variant. */
3396 {ARM_FEATURE_COPROC (FPU_MVE),
3397 MVE_VSUB_VEC_T2,
3398 0xee011f40, 0xff811f70,
3399 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3400
23d00a41
SD		 3401 {ARM_FEATURE_COPROC (FPU_MVE),
3402 MVE_ASRLI,
3403 0xea50012f, 0xfff1813f,
3404 "asrl%c\t%17-19l, %9-11h, %j"},
3405
3406 {ARM_FEATURE_COPROC (FPU_MVE),
3407 MVE_ASRL,
3408 0xea50012d, 0xfff101ff,
3409 "asrl%c\t%17-19l, %9-11h, %12-15S"},
3410
3411 {ARM_FEATURE_COPROC (FPU_MVE),
3412 MVE_LSLLI,
3413 0xea50010f, 0xfff1813f,
3414 "lsll%c\t%17-19l, %9-11h, %j"},
3415
3416 {ARM_FEATURE_COPROC (FPU_MVE),
3417 MVE_LSLL,
3418 0xea50010d, 0xfff101ff,
3419 "lsll%c\t%17-19l, %9-11h, %12-15S"},
3420
3421 {ARM_FEATURE_COPROC (FPU_MVE),
3422 MVE_LSRL,
3423 0xea50011f, 0xfff1813f,
3424 "lsrl%c\t%17-19l, %9-11h, %j"},
3425
3426 {ARM_FEATURE_COPROC (FPU_MVE),
3427 MVE_SQRSHRL,
08132bdd
SP		 3428 0xea51012d, 0xfff1017f,
3429 "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"},
23d00a41
SD		 3430
3431 {ARM_FEATURE_COPROC (FPU_MVE),
3432 MVE_SQRSHR,
3433 0xea500f2d, 0xfff00fff,
3434 "sqrshr%c\t%16-19S, %12-15S"},
3435
3436 {ARM_FEATURE_COPROC (FPU_MVE),
3437 MVE_SQSHLL,
3438 0xea51013f, 0xfff1813f,
3439 "sqshll%c\t%17-19l, %9-11h, %j"},
3440
3441 {ARM_FEATURE_COPROC (FPU_MVE),
3442 MVE_SQSHL,
3443 0xea500f3f, 0xfff08f3f,
3444 "sqshl%c\t%16-19S, %j"},
3445
3446 {ARM_FEATURE_COPROC (FPU_MVE),
3447 MVE_SRSHRL,
3448 0xea51012f, 0xfff1813f,
3449 "srshrl%c\t%17-19l, %9-11h, %j"},
3450
3451 {ARM_FEATURE_COPROC (FPU_MVE),
3452 MVE_SRSHR,
3453 0xea500f2f, 0xfff08f3f,
3454 "srshr%c\t%16-19S, %j"},
3455
3456 {ARM_FEATURE_COPROC (FPU_MVE),
3457 MVE_UQRSHLL,
08132bdd
SP		 3458 0xea51010d, 0xfff1017f,
3459 "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"},
23d00a41
SD		 3460
3461 {ARM_FEATURE_COPROC (FPU_MVE),
3462 MVE_UQRSHL,
3463 0xea500f0d, 0xfff00fff,
3464 "uqrshl%c\t%16-19S, %12-15S"},
3465
3466 {ARM_FEATURE_COPROC (FPU_MVE),
3467 MVE_UQSHLL,
3468 0xea51010f, 0xfff1813f,
3469 "uqshll%c\t%17-19l, %9-11h, %j"},
3470
3471 {ARM_FEATURE_COPROC (FPU_MVE),
3472 MVE_UQSHL,
3473 0xea500f0f, 0xfff08f3f,
3474 "uqshl%c\t%16-19S, %j"},
3475
3476 {ARM_FEATURE_COPROC (FPU_MVE),
3477 MVE_URSHRL,
3478 0xea51011f, 0xfff1813f,
3479 "urshrl%c\t%17-19l, %9-11h, %j"},
3480
3481 {ARM_FEATURE_COPROC (FPU_MVE),
3482 MVE_URSHR,
3483 0xea500f1f, 0xfff08f3f,
3484 "urshr%c\t%16-19S, %j"},
3485
e39c1607
SD		 3486 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3487 MVE_CSINC,
3488 0xea509000, 0xfff0f000,
3489 "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3490
3491 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3492 MVE_CSINV,
3493 0xea50a000, 0xfff0f000,
3494 "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3495
3496 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3497 MVE_CSET,
3498 0xea5f900f, 0xfffff00f,
3499 "cset\t%8-11S, %4-7C"},
3500
3501 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3502 MVE_CSETM,
3503 0xea5fa00f, 0xfffff00f,
3504 "csetm\t%8-11S, %4-7C"},
3505
3506 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3507 MVE_CSEL,
3508 0xea508000, 0xfff0f000,
3509 "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3510
3511 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3512 MVE_CSNEG,
3513 0xea50b000, 0xfff0f000,
3514 "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3515
3516 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3517 MVE_CINC,
3518 0xea509000, 0xfff0f000,
3519 "cinc\t%8-11S, %16-19Z, %4-7C"},
3520
3521 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3522 MVE_CINV,
3523 0xea50a000, 0xfff0f000,
3524 "cinv\t%8-11S, %16-19Z, %4-7C"},
3525
3526 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3527 MVE_CNEG,
3528 0xea50b000, 0xfff0f000,
3529 "cneg\t%8-11S, %16-19Z, %4-7C"},
3530
143275ea
AV		 3531 {ARM_FEATURE_CORE_LOW (0),
3532 MVE_NONE,
3533 0x00000000, 0x00000000, 0}
73cd51e5
AV		 3534};
3535
8f06b2d8
PB		 3536/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
3537 ordered: they must be searched linearly from the top to obtain a correct
3538 match. */
3539
3540/* print_insn_arm recognizes the following format control codes:
3541
3542 %% %
3543
3544 %a print address for ldr/str instruction
3545 %s print address for ldr/str halfword/signextend instruction
c1e26897 3546 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 3547 %b print branch destination
3548 %c print condition code (always bits 28-31)
3549 %m print register mask for ldm/stm instruction
3550 %o print operand2 (immediate or register + shift)
3551 %p print 'p' iff bits 12-15 are 15
3552 %t print 't' iff bit 21 set and bit 24 clear
3553 %B print arm BLX(1) destination
3554 %C print the PSR sub type.
62b3e311
PB		 3555 %U print barrier type.
3556 %P print address for pli instruction.
8f06b2d8
PB		 3557
3558 %<bitfield>r print as an ARM register
9eb6c0f1 3559 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 3560 %<bitfield>R as %r but r15 is UNPREDICTABLE
3561 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3562 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 3563 %<bitfield>d print the bitfield in decimal
43e65147 3564 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 3565 %<bitfield>x print the bitfield in hex
3566 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 3567
16980d0b
JB		 3568 %<bitfield>'c print specified char iff bitfield is all ones
3569 %<bitfield>`c print specified char iff bitfield is all zeroes
3570 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 3571
8f06b2d8
PB		 3572 %e print arm SMI operand (bits 0..7,8..19).
3573 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 3574 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
3575 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 3576
8f06b2d8
PB		 3577static const struct opcode32 arm_opcodes[] =
3578{
3579 /* ARM instructions. */
823d2571
TG		 3580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3581 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
3582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3583 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
3584
3585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
3586 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3588 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3590 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3591 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
3592 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3594 0x00800090, 0x0fa000f0,
3595 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3597 0x00a00090, 0x0fa000f0,
3598 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 3599
105bde57 3600 /* V8.2 RAS extension instructions. */
4d1464f2 3601 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 3602 0xe320f010, 0xffffffff, "esb"},
3603
53c4b28b 3604 /* V8 instructions. */
823d2571
TG		 3605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3606 0x0320f005, 0x0fffffff, "sevl"},
f7dd2fb2
TC		 3607 /* Defined in V8 but is in NOP space so available to all arch. */
3608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
823d2571 3609 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
4ed7ed8d 3610 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 3611 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3612 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 3613 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3615 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3617 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 3618 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3619 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3620 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3621 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3622 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3623 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3624 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3625 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3626 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3627 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3628 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3629 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3630 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3631 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3632 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3633 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3634 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3635 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3636 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 3637 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 3638 /* CRC32 instructions. */
823d2571
TG		 3639 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3640 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
3641 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3642 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
3643 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3644 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
3645 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3646 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
3647 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3648 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
3649 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3650 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 3651
ddfded2f
MW		 3652 /* Privileged Access Never extension instructions. */
3653 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
3654 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
3655
90ec0d68 3656 /* Virtualization Extension instructions. */
823d2571
TG		 3657 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
3658 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 3659
eea54501 3660 /* Integer Divide Extension instructions. */
823d2571
TG		 3661 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3662 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3663 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3664 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 3665
60e5ef9f 3666 /* MP Extension instructions. */
823d2571 3667 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 3668
c597cc3d
SD		 3669 /* Speculation Barriers. */
3670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
3671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
3672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
3673
62b3e311 3674 /* V7 instructions. */
823d2571
TG		 3675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
3676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
3677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a
AV		 3682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3683 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
62b3e311 3684
c19d1205 3685 /* ARM V6T2 instructions. */
823d2571
TG		 3686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3687 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3689 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3691 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3693 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3694
3695 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3696 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
3697 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3698 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3699
ff8646ee 3700 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 3701 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 3702 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3703 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3705 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3707 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 3708
f4c65163 3709 /* ARM Security extension instructions. */
823d2571
TG		 3710 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
3711 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 3712
8f06b2d8 3713 /* ARM V6K instructions. */
823d2571
TG		 3714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3715 0xf57ff01f, 0xffffffff, "clrex"},
3716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3717 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3719 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3721 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3723 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3725 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3727 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 3728
7fadb25d
SD		 3729 /* ARMv8.5-A instructions. */
3730 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
3731
8f06b2d8 3732 /* ARM V6K NOP hints. */
823d2571
TG		 3733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3734 0x0320f001, 0x0fffffff, "yield%c"},
3735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3736 0x0320f002, 0x0fffffff, "wfe%c"},
3737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3738 0x0320f003, 0x0fffffff, "wfi%c"},
3739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3740 0x0320f004, 0x0fffffff, "sev%c"},
3741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3742 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 3743
fe56b6ce 3744 /* ARM V6 instructions. */
823d2571
TG		 3745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3746 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
3747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3748 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
3749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3750 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
3751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3752 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
3753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3754 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
3755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3756 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3758 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
3759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3760 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
3761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3762 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
3763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3764 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
3765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3766 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3768 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3770 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3772 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3774 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3776 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3778 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3780 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3782 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3784 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3786 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3788 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3790 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3792 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3794 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3796 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3798 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3800 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3802 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3804 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3806 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3808 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3810 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3812 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3814 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3816 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3818 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3820 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3822 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3824 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3826 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3828 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3830 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3832 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3834 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3836 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3838 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3840 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3842 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3844 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3846 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3848 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3850 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3852 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3854 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3856 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3858 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3860 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3862 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3864 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3866 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3868 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3870 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3872 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3874 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3876 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3878 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3880 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3882 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3884 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3886 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3888 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3890 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3892 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3894 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3896 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3898 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3900 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3902 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3904 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3906 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3908 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3910 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3912 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3914 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3916 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3918 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3920 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3922 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3924 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3926 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3928 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3930 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3932 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
3933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3934 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3936 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3938 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3940 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3942 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
3943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3944 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
3945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3946 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
3947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3948 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
3949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3950 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3952 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3954 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3956 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3958 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
3959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3960 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3962 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3964 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
3965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3966 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
3967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3968 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
3969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3970 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
3971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3972 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
3973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3974 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
3975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3976 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
3977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3978 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
3979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3980 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3982 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
3983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3984 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
3985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3986 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
3987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3988 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 3989
8f06b2d8 3990 /* V5J instruction. */
823d2571
TG		 3991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
3992 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 3993
8f06b2d8 3994 /* V5 Instructions. */
823d2571
TG		 3995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3996 0xe1200070, 0xfff000f0,
3997 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
3998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3999 0xfa000000, 0xfe000000, "blx\t%B"},
4000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4001 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
4002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4003 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
4004
4005 /* V5E "El Segundo" Instructions. */
4006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4007 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
4008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4009 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
4010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4011 0xf450f000, 0xfc70f000, "pld\t%a"},
4012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4013 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4015 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4017 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4019 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
4020
4021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4022 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4024 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
4025
4026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4027 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4029 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4031 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4033 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4034
4035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4036 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
4037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4038 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
4039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4040 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
4041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4042 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
4043
4044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4045 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
4046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4047 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
4048
4049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4050 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
4051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4052 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
4053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4054 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
4055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4056 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 4057
8f06b2d8 4058 /* ARM Instructions. */
823d2571
TG		 4059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4060 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
4061
4062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4063 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
4064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4065 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
4066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4067 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
4068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4069 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
4070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4071 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
4072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4073 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
4074
4075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4076 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
4077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4078 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
4079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4080 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
4081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4082 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
4083
4084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4085 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
4086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4087 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
4088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4089 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
4090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4091 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
4092
4093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4094 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
4095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4096 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
4097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4098 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
4099
4100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4101 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
4102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4103 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
4104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4105 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
4106
4107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4108 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
4109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4110 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
4111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4112 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
4113
4114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4115 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4117 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4119 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
4120
4121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4122 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
4123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4124 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
4125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4126 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
4127
4128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4129 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
4130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4131 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
4132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4133 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
4134
4135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4136 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4138 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4140 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
4141
4142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4143 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4145 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4147 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
4148
4149 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
4150 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
4151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4152 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
4153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4154 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
4155
4156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4157 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
4158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4159 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
4160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4161 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
4162
4163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4164 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 4165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4166 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 4167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4168 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
823d2571
TG		 4169
4170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4171 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
4172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4173 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
4174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4175 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
4176
4177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4178 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
4179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4180 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
4181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4182 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
4183
4184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4185 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
4186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4187 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
4188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4189 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
4190
4191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4192 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
4193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4194 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
4195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4196 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
4197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4198 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
4199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4200 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
4201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4202 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
4203 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4204 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
4205
4206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4207 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
4208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4209 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
4210 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4211 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
4212
4213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4214 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
4215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4216 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
4217 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4218 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
4219
4220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4221 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
4222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4223 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
4224
4225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4226 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
4227
4228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4229 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
4230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4231 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
4232
4233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4234 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4236 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4238 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4240 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4242 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4244 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4246 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4248 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4250 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4252 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4254 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4256 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4257 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4258 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4259 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4260 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4261 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4262 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4263 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4264 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4266 0x092d0000, 0x0fff0000, "push%c\t%m"},
4267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4268 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
4269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4270 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4271
4272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4273 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4275 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4277 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4279 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4281 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4282 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4283 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4285 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4287 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4289 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4291 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4292 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4293 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4294 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4295 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4297 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4299 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4301 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4302 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4303 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4304 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4305 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
4306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4307 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
4308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4309 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4310
4311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4312 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4314 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 4315
4316 /* The rest. */
4ab90a7a
AV		 4317 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
4318 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 4319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4320 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4321 {ARM_FEATURE_CORE_LOW (0),
4322 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 4323};
4324
4325/* print_insn_thumb16 recognizes the following format control codes:
4326
4327 %S print Thumb register (bits 3..5 as high number if bit 6 set)
4328 %D print Thumb register (bits 0..2 as high number if bit 7 set)
4329 %<bitfield>I print bitfield as a signed decimal
4330 (top bit of range being the sign bit)
4331 %N print Thumb register mask (with LR)
4332 %O print Thumb register mask (with PC)
4333 %M print Thumb register mask
4334 %b print CZB's 6-bit unsigned branch destination
4335 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 4336 %c print the condition code
4337 %C print the condition code, or "s" if not conditional
4338 %x print warning if conditional an not at end of IT block"
4339 %X print "\t; unpredictable <IT:code>" if conditional
4340 %I print IT instruction suffix and operands
4547cb56 4341 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 4342 %<bitfield>r print bitfield as an ARM register
4343 %<bitfield>d print bitfield as a decimal
4344 %<bitfield>H print (bitfield * 2) as a decimal
4345 %<bitfield>W print (bitfield * 4) as a decimal
4346 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
4347 %<bitfield>B print Thumb branch destination (signed displacement)
4348 %<bitfield>c print bitfield as a condition code
4349 %<bitnum>'c print specified char iff bit is one
4350 %<bitnum>?ab print a if bit is one else print b. */
4351
4352static const struct opcode16 thumb_opcodes[] =
4353{
4354 /* Thumb instructions. */
4355
16a1fa25
TP		 4356 /* ARMv8-M Security Extensions instructions. */
4357 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
e207bc53 4358 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
16a1fa25 4359
53c4b28b 4360 /* ARM V8 instructions. */
823d2571
TG		 4361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
4362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
ddfded2f 4363 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
53c4b28b 4364
8f06b2d8 4365 /* ARM V6K no-argument instructions. */
823d2571
TG		 4366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
4367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
4368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
4369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
4370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
4371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 4372
4373 /* ARM V6T2 instructions. */
ff8646ee
TP		 4374 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4375 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4376 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4377 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 4378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 4379
4380 /* ARM V6. */
823d2571
TG		 4381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
4382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
4383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
4387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
4388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 4392
4393 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 4394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4395 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 4396 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 4397 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4398 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 4399 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 4400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4401 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 4402 /* Format 4. */
823d2571
TG		 4403 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4411 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4413 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4415 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4418 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 4419 /* format 13 */
823d2571
TG		 4420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
4421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 4422 /* format 5 */
823d2571
TG		 4423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
4424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
4425 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 4427 /* format 14 */
823d2571
TG		 4428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
4429 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 4430 /* format 2 */
823d2571
TG		 4431 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4432 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4433 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4434 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4435 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4436 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
4437 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4438 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 4439 /* format 8 */
823d2571
TG		 4440 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4441 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4443 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4445 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 4446 /* format 7 */
823d2571
TG		 4447 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4448 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4450 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 4451 /* format 1 */
823d2571
TG		 4452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4453 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4454 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
4455 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 4457 /* format 3 */
823d2571
TG		 4458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
4459 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
4460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
4461 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 4462 /* format 6 */
823d2571
TG		 4463 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4465 0x4800, 0xF800,
4466 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 4467 /* format 9 */
823d2571
TG		 4468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4469 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
4470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4471 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
4472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4473 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
4474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4475 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 4476 /* format 10 */
823d2571
TG		 4477 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4478 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
4479 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4480 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 4481 /* format 11 */
823d2571
TG		 4482 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4483 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
4484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4485 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 4486 /* format 12 */
823d2571
TG		 4487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4488 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
4489 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4490 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 4491 /* format 15 */
823d2571
TG		 4492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 4494 /* format 17 */
823d2571 4495 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 4496 /* format 16 */
823d2571
TG		 4497 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
4498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
4499 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 4500 /* format 18 */
823d2571 4501 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 4502
4503 /* The E800 .. FFFF range is unconditionally redirected to the
4504 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4505 are processed via that table. Thus, we can never encounter a
4506 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 4507 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
4508 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 4509};
4510
4511/* Thumb32 opcodes use the same table structure as the ARM opcodes.
4512 We adopt the convention that hw1 is the high 16 bits of .value and
4513 .mask, hw2 the low 16 bits.
4514
4515 print_insn_thumb32 recognizes the following format control codes:
4516
4517 %% %
4518
4519 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4520 %M print a modified 12-bit immediate (same location)
4521 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4522 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 4523 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 4524 %S print a possibly-shifted Rm
4525
32a94698 4526 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 4527 %a print the address of a plain load/store
4528 %w print the width and signedness of a core load/store
4529 %m print register mask for ldm/stm
4b5a202f 4530 %n print register mask for clrm
8f06b2d8
PB		 4531
4532 %E print the lsb and width fields of a bfc/bfi instruction
4533 %F print the lsb and width fields of a sbfx/ubfx instruction
e12437dc 4534 %G print a fallback offset for Branch Future instructions
e5d6e09e 4535 %W print an offset for BF instruction
1caf72a5 4536 %Y print an offset for BFL instruction
1889da70 4537 %Z print an offset for BFCSEL instruction
60f993ce
AV		 4538 %Q print an offset for Low Overhead Loop instructions
4539 %P print an offset for Low Overhead Loop end instructions
8f06b2d8
PB		 4540 %b print a conditional branch offset
4541 %B print an unconditional branch offset
4542 %s print the shift field of an SSAT instruction
4543 %R print the rotation field of an SXT instruction
62b3e311
PB		 4544 %U print barrier type.
4545 %P print address for pli instruction.
c22aaad1
PB		 4546 %c print the condition code
4547 %x print warning if conditional an not at end of IT block"
4548 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 4549
4550 %<bitfield>d print bitfield in decimal
f0fba320 4551 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 4552 %<bitfield>W print bitfield*4 in decimal
4553 %<bitfield>r print bitfield as an ARM register
dd5181d5 4554 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
f1c7f421 4555 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
8f06b2d8
PB		 4556 %<bitfield>c print bitfield as a condition code
4557
16980d0b
JB		 4558 %<bitfield>'c print specified char iff bitfield is all ones
4559 %<bitfield>`c print specified char iff bitfield is all zeroes
4560 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 4561
4562 With one exception at the bottom (done because BL and BLX(1) need
4563 to come dead last), this table was machine-sorted first in
4564 decreasing order of number of bits set in the mask, then in
4565 increasing numeric order of mask, then in increasing numeric order
4566 of opcode. This order is not the clearest for a human reader, but
4567 is guaranteed never to catch a special-case bit pattern with a more
4568 general mask, which is important, because this instruction encoding
4569 makes heavy use of special-case bit patterns. */
4570static const struct opcode32 thumb32_opcodes[] =
4571{
4b5a202f
AV		 4572 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4573 instructions. */
60f993ce 4574 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
d052b9b7 4575 0xf00fe001, 0xffffffff, "lctp%c"},
60f993ce
AV		 4576 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4577 0xf02fc001, 0xfffff001, "le\t%P"},
4578 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4579 0xf00fc001, 0xfffff001, "le\tlr, %P"},
d052b9b7
AV		 4580 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4581 0xf01fc001, 0xfffff001, "letp\tlr, %P"},
4582 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4583 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
4584 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4585 0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
4586 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4587 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
4588 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4589 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
60f993ce 4590
4389b29a
AV		 4591 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4592 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
f1c7f421
AV		 4593 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4594 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
65d1bc05
AV		 4595 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4596 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
f1c7f421
AV		 4597 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4598 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
f6b2b12d
AV		 4599 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4600 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4389b29a 4601
4b5a202f
AV		 4602 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4603 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4389b29a 4604
16a1fa25
TP		 4605 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
4606 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4ed7ed8d
TP		 4607 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4608 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4609 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4610 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
16a1fa25
TP		 4611 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4612 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4613 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4614 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4ed7ed8d 4615
105bde57 4616 /* ARM V8.2 RAS extension instructions. */
4d1464f2 4617 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 4618 0xf3af8010, 0xffffffff, "esb"},
4619
53c4b28b 4620 /* V8 instructions. */
823d2571
TG		 4621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4622 0xf3af8005, 0xffffffff, "sevl%c.w"},
4623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4624 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4626 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4627 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4628 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4629 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4630 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4631 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4632 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4634 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4636 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4638 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4640 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4641 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4642 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4644 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4646 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4648 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4650 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4652 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 4653
dd5181d5 4654 /* CRC32 instructions. */
823d2571 4655 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4656 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
823d2571 4657 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4658 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
823d2571 4659 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4660 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
823d2571 4661 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4662 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
823d2571 4663 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4664 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
823d2571 4665 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4666 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
dd5181d5 4667
c597cc3d
SD		 4668 /* Speculation Barriers. */
4669 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
4670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
4671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
4672
62b3e311 4673 /* V7 instructions. */
823d2571
TG		 4674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
4676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4681 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4682 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4683 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4684 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 4685
90ec0d68 4686 /* Virtualization Extension instructions. */
823d2571 4687 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 4688 /* We skip ERET as that is SUBS pc, lr, #0. */
4689
60e5ef9f 4690 /* MP Extension instructions. */
823d2571 4691 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 4692
f4c65163 4693 /* Security extension instructions. */
823d2571 4694 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 4695
7fadb25d
SD		 4696 /* ARMv8.5-A instructions. */
4697 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
4698
8f06b2d8 4699 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 4700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
4701 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
4702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4703 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
4705 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4706 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
4707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4708
ff8646ee 4709 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4710 0xf3bf8f2f, 0xffffffff, "clrex%c"},
4711 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4712 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
4713 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4714 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
4715 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4716 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4717 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4718 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4719 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4720 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4722 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4724 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
4725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4726 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4728 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
4729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4730 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
4731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4732 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
4733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4734 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
4735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4736 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 4737 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 4738 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 4739 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4740 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4742 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
4743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4744 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
4745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4746 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4748 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4750 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4752 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4754 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4756 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 4757 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4758 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4760 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4762 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4764 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4766 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4768 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4770 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4772 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4774 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4776 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4778 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4780 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4782 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4784 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4786 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4788 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4790 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4792 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4794 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4796 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4798 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4800 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4802 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4804 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4806 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4808 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4810 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4812 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4814 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4816 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4818 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4820 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4822 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4824 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4826 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4828 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4830 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4832 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4834 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4836 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4838 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4840 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4842 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4844 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4846 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4848 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4850 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4852 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4854 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4856 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4858 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4860 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4862 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4864 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 4865 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4866 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 4868 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 4869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4870 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4872 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4874 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4876 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4878 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4880 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4882 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4884 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4886 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4888 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4890 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4892 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4894 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4896 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4898 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4900 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4902 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4904 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4906 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4908 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4910 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4912 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4914 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4916 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4918 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4920 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4922 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4924 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4926 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4928 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4930 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4932 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 4933 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4934 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
4935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4936 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
4937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4938 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
4939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4940 0xf810f000, 0xff70f000, "pld%c\t%a"},
4941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4942 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4944 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4946 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4948 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4950 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4952 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4954 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4956 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
4957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4958 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
4959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4960 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
4961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4962 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
4963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4964 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
4965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4966 0xfb100000, 0xfff000c0,
4967 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4969 0xfbc00080, 0xfff000c0,
4970 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
4971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4972 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
4973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4974 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
4975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 4976 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 4977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4978 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
4979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4980 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 4981 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4982 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
4983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4984 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 4985 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4986 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
4987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4988 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
4989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4990 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
4991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4992 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
4993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4994 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
4995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4996 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
4997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4998 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
4999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5000 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
5001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5002 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
5003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5004 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
5005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5006 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 5007 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 5008 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
5009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5010 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
5011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5012 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
5013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5014 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
5015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5016 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
5017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5018 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
5019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5020 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
5021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5022 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
5023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5024 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
5025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5026 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
5027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5028 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
5029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5030 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
5031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5032 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
5033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5034 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
5035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5036 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
5037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5038 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
5039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5040 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
5041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5042 0xe9400000, 0xff500000,
5043 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5045 0xe9500000, 0xff500000,
5046 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5048 0xe8600000, 0xff700000,
5049 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5051 0xe8700000, 0xff700000,
5052 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5054 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
5055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5056 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 5057
5058 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 5059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5060 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
5061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5062 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
5063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5064 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
5065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5066 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 5067
8f06b2d8 5068 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 5069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5070 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
5071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5072 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 5073
5074 /* Fallback. */
823d2571
TG		 5075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
5076 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
5077 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 5078};
ff4a8d2b 5079
8f06b2d8
PB		 5080static const char *const arm_conditional[] =
5081{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 5082 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 5083
5084static const char *const arm_fp_const[] =
5085{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
5086
5087static const char *const arm_shift[] =
5088{"lsl", "lsr", "asr", "ror"};
5089
5090typedef struct
5091{
5092 const char *name;
5093 const char *description;
5094 const char *reg_names[16];
5095}
5096arm_regname;
5097
5098static const arm_regname regnames[] =
5099{
65b48a81 5100 { "reg-names-raw", N_("Select raw register names"),
8f06b2d8 5101 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
65b48a81 5102 { "reg-names-gcc", N_("Select register names used by GCC"),
8f06b2d8 5103 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 5104 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
8f06b2d8 5105 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65b48a81
PB		 5106 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
5107 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
5108 { "reg-names-apcs", N_("Select register names used in the APCS"),
8f06b2d8 5109 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 5110 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
8f06b2d8 5111 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
65b48a81
PB		 5112 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
5113 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
8f06b2d8
PB		 5114};
5115
5116static const char *const iwmmxt_wwnames[] =
5117{"b", "h", "w", "d"};
5118
5119static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 5120{"b", "bus", "bc", "bss",
5121 "h", "hus", "hc", "hss",
5122 "w", "wus", "wc", "wss",
5123 "d", "dus", "dc", "dss"
8f06b2d8
PB		 5124};
5125
5126static const char *const iwmmxt_regnames[] =
5127{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
5128 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
5129};
5130
5131static const char *const iwmmxt_cregnames[] =
5132{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
5133 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
5134};
5135
143275ea
AV		 5136static const char *const vec_condnames[] =
5137{ "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
5138};
5139
5140static const char *const mve_predicatenames[] =
5141{ "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
5142 "eee", "ee", "eet", "e", "ett", "et", "ete"
5143};
5144
5145/* Names for 2-bit size field for mve vector isntructions. */
5146static const char *const mve_vec_sizename[] =
5147 { "8", "16", "32", "64"};
5148
5149/* Indicates whether we are processing a then predicate,
5150 else predicate or none at all. */
5151enum vpt_pred_state
5152{
5153 PRED_NONE,
5154 PRED_THEN,
5155 PRED_ELSE
5156};
5157
5158/* Information used to process a vpt block and subsequent instructions. */
5159struct vpt_block
5160{
5161 /* Are we in a vpt block. */
5162 bfd_boolean in_vpt_block;
5163
5164 /* Next predicate state if in vpt block. */
5165 enum vpt_pred_state next_pred_state;
5166
5167 /* Mask from vpt/vpst instruction. */
5168 long predicate_mask;
5169
5170 /* Instruction number in vpt block. */
5171 long current_insn_num;
5172
5173 /* Number of instructions in vpt block.. */
5174 long num_pred_insn;
5175};
5176
5177static struct vpt_block vpt_block_state =
5178{
5179 FALSE,
5180 PRED_NONE,
5181 0,
5182 0,
5183 0
5184};
5185
8f06b2d8
PB		 5186/* Default to GCC register name set. */
5187static unsigned int regname_selected = 1;
5188
65b48a81 5189#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
8f06b2d8
PB		 5190#define arm_regnames regnames[regname_selected].reg_names
5191
5192static bfd_boolean force_thumb = FALSE;
5193
c22aaad1
PB		 5194/* Current IT instruction state. This contains the same state as the IT
5195 bits in the CPSR. */
5196static unsigned int ifthen_state;
5197/* IT state for the next instruction. */
5198static unsigned int ifthen_next_state;
5199/* The address of the insn for which the IT state is valid. */
5200static bfd_vma ifthen_address;
5201#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 5202/* Indicates that the current Conditional state is unconditional or outside
5203 an IT block. */
5204#define COND_UNCOND 16
c22aaad1 5205
8f06b2d8
PB		 5206\f
5207/* Functions. */
143275ea
AV		 5208/* Extract the predicate mask for a VPT or VPST instruction.
5209 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
5210
5211static long
5212mve_extract_pred_mask (long given)
5213{
5214 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
5215}
5216
5217/* Return the number of instructions in a MVE predicate block. */
5218static long
5219num_instructions_vpt_block (long given)
5220{
5221 long mask = mve_extract_pred_mask (given);
5222 if (mask == 0)
5223 return 0;
5224
5225 if (mask == 8)
5226 return 1;
5227
5228 if ((mask & 7) == 4)
5229 return 2;
5230
5231 if ((mask & 3) == 2)
5232 return 3;
5233
5234 if ((mask & 1) == 1)
5235 return 4;
5236
5237 return 0;
5238}
5239
5240static void
5241mark_outside_vpt_block (void)
5242{
5243 vpt_block_state.in_vpt_block = FALSE;
5244 vpt_block_state.next_pred_state = PRED_NONE;
5245 vpt_block_state.predicate_mask = 0;
5246 vpt_block_state.current_insn_num = 0;
5247 vpt_block_state.num_pred_insn = 0;
5248}
5249
5250static void
5251mark_inside_vpt_block (long given)
5252{
5253 vpt_block_state.in_vpt_block = TRUE;
5254 vpt_block_state.next_pred_state = PRED_THEN;
5255 vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
5256 vpt_block_state.current_insn_num = 0;
5257 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
5258 assert (vpt_block_state.num_pred_insn >= 1);
5259}
5260
5261static enum vpt_pred_state
5262invert_next_predicate_state (enum vpt_pred_state astate)
5263{
5264 if (astate == PRED_THEN)
5265 return PRED_ELSE;
5266 else if (astate == PRED_ELSE)
5267 return PRED_THEN;
5268 else
5269 return PRED_NONE;
5270}
5271
5272static enum vpt_pred_state
5273update_next_predicate_state (void)
5274{
5275 long pred_mask = vpt_block_state.predicate_mask;
5276 long mask_for_insn = 0;
5277
5278 switch (vpt_block_state.current_insn_num)
5279 {
5280 case 1:
5281 mask_for_insn = 8;
5282 break;
5283
5284 case 2:
5285 mask_for_insn = 4;
5286 break;
5287
5288 case 3:
5289 mask_for_insn = 2;
5290 break;
5291
5292 case 4:
5293 return PRED_NONE;
5294 }
5295
5296 if (pred_mask & mask_for_insn)
5297 return invert_next_predicate_state (vpt_block_state.next_pred_state);
5298 else
5299 return vpt_block_state.next_pred_state;
5300}
5301
5302static void
5303update_vpt_block_state (void)
5304{
5305 vpt_block_state.current_insn_num++;
5306 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
5307 {
5308 /* No more instructions to process in vpt block. */
5309 mark_outside_vpt_block ();
5310 return;
5311 }
5312
5313 vpt_block_state.next_pred_state = update_next_predicate_state ();
5314}
8f06b2d8 5315
16980d0b
JB		 5316/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5317 Returns pointer to following character of the format string and
5318 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 5319 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 5320
5321static const char *
fe56b6ce
NC		 5322arm_decode_bitfield (const char *ptr,
5323 unsigned long insn,
5324 unsigned long *valuep,
5325 int *widthp)
16980d0b
JB		 5326{
5327 unsigned long value = 0;
5328 int width = 0;
43e65147
L		 5329
5330 do
16980d0b
JB		 5331 {
5332 int start, end;
5333 int bits;
5334
5335 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
5336 start = start * 10 + *ptr - '0';
5337 if (*ptr == '-')
5338 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
5339 end = end * 10 + *ptr - '0';
5340 else
5341 end = start;
5342 bits = end - start;
5343 if (bits < 0)
5344 abort ();
5345 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
5346 width += bits + 1;
5347 }
5348 while (*ptr++ == ',');
5349 *valuep = value;
5350 if (widthp)
5351 *widthp = width;
5352 return ptr - 1;
5353}
5354
8f06b2d8 5355static void
37b37b2d 5356arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 5357 bfd_boolean print_shift)
8f06b2d8
PB		 5358{
5359 func (stream, "%s", arm_regnames[given & 0xf]);
5360
5361 if ((given & 0xff0) != 0)
5362 {
5363 if ((given & 0x10) == 0)
5364 {
5365 int amount = (given & 0xf80) >> 7;
5366 int shift = (given & 0x60) >> 5;
5367
5368 if (amount == 0)
5369 {
5370 if (shift == 3)
5371 {
5372 func (stream, ", rrx");
5373 return;
5374 }
5375
5376 amount = 32;
5377 }
5378
37b37b2d
RE		 5379 if (print_shift)
5380 func (stream, ", %s #%d", arm_shift[shift], amount);
5381 else
5382 func (stream, ", #%d", amount);
8f06b2d8 5383 }
74bdfecf 5384 else if ((given & 0x80) == 0x80)
aefd8a40 5385 func (stream, "\t; <illegal shifter operand>");
37b37b2d 5386 else if (print_shift)
8f06b2d8
PB		 5387 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
5388 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 5389 else
5390 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 5391 }
5392}
5393
73cd51e5
AV		 5394/* Return TRUE if the MATCHED_INSN can be inside an IT block. */
5395
5396static bfd_boolean
5397is_mve_okay_in_it (enum mve_instructions matched_insn)
5398{
c507f10b
AV		 5399 switch (matched_insn)
5400 {
5401 case MVE_VMOV_GP_TO_VEC_LANE:
5402 case MVE_VMOV2_VEC_LANE_TO_GP:
5403 case MVE_VMOV2_GP_TO_VEC_LANE:
5404 case MVE_VMOV_VEC_LANE_TO_GP:
23d00a41
SD		 5405 case MVE_LSLL:
5406 case MVE_LSLLI:
5407 case MVE_LSRL:
5408 case MVE_ASRL:
5409 case MVE_ASRLI:
5410 case MVE_SQRSHRL:
5411 case MVE_SQRSHR:
5412 case MVE_UQRSHL:
5413 case MVE_UQRSHLL:
5414 case MVE_UQSHL:
5415 case MVE_UQSHLL:
5416 case MVE_URSHRL:
5417 case MVE_URSHR:
5418 case MVE_SRSHRL:
5419 case MVE_SRSHR:
5420 case MVE_SQSHLL:
5421 case MVE_SQSHL:
c507f10b
AV		 5422 return TRUE;
5423 default:
5424 return FALSE;
5425 }
73cd51e5
AV		 5426}
5427
5428static bfd_boolean
5429is_mve_architecture (struct disassemble_info *info)
5430{
5431 struct arm_private_data *private_data = info->private_data;
5432 arm_feature_set allowed_arches = private_data->features;
5433
5434 arm_feature_set arm_ext_v8_1m_main
5435 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
5436
5437 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
5438 && !ARM_CPU_IS_ANY (allowed_arches))
5439 return TRUE;
5440 else
5441 return FALSE;
5442}
5443
143275ea
AV		 5444static bfd_boolean
5445is_vpt_instruction (long given)
5446{
5447
5448 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
5449 if ((given & 0x0040e000) == 0)
5450 return FALSE;
5451
5452 /* VPT floating point T1 variant. */
5453 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
5454 /* VPT floating point T2 variant. */
5455 || ((given & 0xefb10f50) == 0xee310f40)
5456 /* VPT vector T1 variant. */
5457 || ((given & 0xff811f51) == 0xfe010f00)
5458 /* VPT vector T2 variant. */
5459 || ((given & 0xff811f51) == 0xfe010f01
5460 && ((given & 0x300000) != 0x300000))
5461 /* VPT vector T3 variant. */
5462 || ((given & 0xff811f50) == 0xfe011f00)
5463 /* VPT vector T4 variant. */
5464 || ((given & 0xff811f70) == 0xfe010f40)
5465 /* VPT vector T5 variant. */
5466 || ((given & 0xff811f70) == 0xfe010f60)
5467 /* VPT vector T6 variant. */
5468 || ((given & 0xff811f50) == 0xfe011f40)
5469 /* VPST vector T variant. */
5470 || ((given & 0xffbf1fff) == 0xfe310f4d))
5471 return TRUE;
5472 else
5473 return FALSE;
5474}
5475
73cd51e5
AV		 5476/* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5477 and ending bitfield = END. END must be greater than START. */
5478
5479static unsigned long
5480arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
5481{
5482 int bits = end - start;
5483
5484 if (bits < 0)
5485 abort ();
5486
5487 return ((given >> start) & ((2ul << bits) - 1));
5488}
5489
5490/* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5491 START:END and START2:END2. END/END2 must be greater than
5492 START/START2. */
5493
5494static unsigned long
5495arm_decode_field_multiple (unsigned long given, unsigned int start,
5496 unsigned int end, unsigned int start2,
5497 unsigned int end2)
5498{
5499 int bits = end - start;
5500 int bits2 = end2 - start2;
5501 unsigned long value = 0;
5502 int width = 0;
5503
5504 if (bits2 < 0)
5505 abort ();
5506
5507 value = arm_decode_field (given, start, end);
5508 width += bits + 1;
5509
5510 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
5511 return value;
5512}
5513
5514/* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5515 This helps us decode instructions that change mnemonic depending on specific
5516 operand values/encodings. */
5517
5518static bfd_boolean
5519is_mve_encoding_conflict (unsigned long given,
5520 enum mve_instructions matched_insn)
5521{
143275ea
AV		 5522 switch (matched_insn)
5523 {
5524 case MVE_VPST:
5525 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5526 return TRUE;
5527 else
5528 return FALSE;
5529
5530 case MVE_VPT_FP_T1:
5531 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5532 return TRUE;
5533 if ((arm_decode_field (given, 12, 12) == 0)
5534 && (arm_decode_field (given, 0, 0) == 1))
5535 return TRUE;
5536 return FALSE;
5537
5538 case MVE_VPT_FP_T2:
5539 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5540 return TRUE;
5541 if (arm_decode_field (given, 0, 3) == 0xd)
5542 return TRUE;
5543 return FALSE;
5544
5545 case MVE_VPT_VEC_T1:
5546 case MVE_VPT_VEC_T2:
5547 case MVE_VPT_VEC_T3:
5548 case MVE_VPT_VEC_T4:
5549 case MVE_VPT_VEC_T5:
5550 case MVE_VPT_VEC_T6:
5551 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5552 return TRUE;
5553 if (arm_decode_field (given, 20, 21) == 3)
5554 return TRUE;
5555 return FALSE;
5556
5557 case MVE_VCMP_FP_T1:
5558 if ((arm_decode_field (given, 12, 12) == 0)
5559 && (arm_decode_field (given, 0, 0) == 1))
5560 return TRUE;
5561 else
5562 return FALSE;
5563
5564 case MVE_VCMP_FP_T2:
5565 if (arm_decode_field (given, 0, 3) == 0xd)
5566 return TRUE;
5567 else
5568 return FALSE;
5569
14b456f2
AV		 5570 case MVE_VQADD_T2:
5571 case MVE_VQSUB_T2:
f49bb598
AV		 5572 case MVE_VMUL_VEC_T2:
5573 case MVE_VMULH:
5574 case MVE_VRMULH:
56858bea
AV		 5575 case MVE_VMLA:
5576 case MVE_VMAX:
5577 case MVE_VMIN:
e523f101 5578 case MVE_VBRSR:
66dcaa5d
AV		 5579 case MVE_VADD_VEC_T2:
5580 case MVE_VSUB_VEC_T2:
5581 case MVE_VABAV:
ed63aa17
AV		 5582 case MVE_VQRSHL_T1:
5583 case MVE_VQSHL_T4:
5584 case MVE_VRSHL_T1:
5585 case MVE_VSHL_T3:
897b9bbc
AV		 5586 case MVE_VCADD_VEC:
5587 case MVE_VHCADD:
1c8f2df8
AV		 5588 case MVE_VDDUP:
5589 case MVE_VIDUP:
d3b63143
AV		 5590 case MVE_VQRDMLADH:
5591 case MVE_VQDMLAH:
5592 case MVE_VQRDMLAH:
5593 case MVE_VQDMLASH:
5594 case MVE_VQRDMLASH:
5595 case MVE_VQDMLSDH:
5596 case MVE_VQRDMLSDH:
5597 case MVE_VQDMULH_T3:
5598 case MVE_VQRDMULH_T4:
5599 case MVE_VQDMLADH:
5600 case MVE_VMLAS:
14925797 5601 case MVE_VMULL_INT:
9743db03
AV		 5602 case MVE_VHADD_T2:
5603 case MVE_VHSUB_T2:
143275ea
AV		 5604 case MVE_VCMP_VEC_T1:
5605 case MVE_VCMP_VEC_T2:
5606 case MVE_VCMP_VEC_T3:
5607 case MVE_VCMP_VEC_T4:
5608 case MVE_VCMP_VEC_T5:
5609 case MVE_VCMP_VEC_T6:
5610 if (arm_decode_field (given, 20, 21) == 3)
5611 return TRUE;
5612 else
5613 return FALSE;
5614
04d54ace
AV		 5615 case MVE_VLD2:
5616 case MVE_VLD4:
5617 case MVE_VST2:
5618 case MVE_VST4:
5619 if (arm_decode_field (given, 7, 8) == 3)
5620 return TRUE;
5621 else
5622 return FALSE;
5623
aef6d006
AV		 5624 case MVE_VSTRB_T1:
5625 case MVE_VSTRH_T2:
5626 if ((arm_decode_field (given, 24, 24) == 0)
5627 && (arm_decode_field (given, 21, 21) == 0))
5628 {
5629 return TRUE;
5630 }
5631 else if ((arm_decode_field (given, 7, 8) == 3))
5632 return TRUE;
5633 else
5634 return FALSE;
5635
5636 case MVE_VSTRB_T5:
5637 case MVE_VSTRH_T6:
5638 case MVE_VSTRW_T7:
5639 if ((arm_decode_field (given, 24, 24) == 0)
5640 && (arm_decode_field (given, 21, 21) == 0))
5641 {
5642 return TRUE;
5643 }
5644 else
5645 return FALSE;
5646
bf0b396d
AV		 5647 case MVE_VCVT_FP_FIX_VEC:
5648 return (arm_decode_field (given, 16, 21) & 0x38) == 0;
5649
c507f10b
AV		 5650 case MVE_VBIC_IMM:
5651 case MVE_VORR_IMM:
5652 {
5653 unsigned long cmode = arm_decode_field (given, 8, 11);
5654
5655 if ((cmode & 1) == 0)
5656 return TRUE;
5657 else if ((cmode & 0xc) == 0xc)
5658 return TRUE;
5659 else
5660 return FALSE;
5661 }
5662
5663 case MVE_VMVN_IMM:
5664 {
5665 unsigned long cmode = arm_decode_field (given, 8, 11);
5666
5667 if ((cmode & 9) == 1)
5668 return TRUE;
5669 else if ((cmode & 5) == 1)
5670 return TRUE;
5671 else if ((cmode & 0xe) == 0xe)
5672 return TRUE;
5673 else
5674 return FALSE;
5675 }
5676
5677 case MVE_VMOV_IMM_TO_VEC:
5678 if ((arm_decode_field (given, 5, 5) == 1)
5679 && (arm_decode_field (given, 8, 11) != 0xe))
5680 return TRUE;
5681 else
5682 return FALSE;
5683
14925797
AV		 5684 case MVE_VMOVL:
5685 {
5686 unsigned long size = arm_decode_field (given, 19, 20);
5687 if ((size == 0) || (size == 3))
5688 return TRUE;
5689 else
5690 return FALSE;
5691 }
5692
56858bea
AV		 5693 case MVE_VMAXA:
5694 case MVE_VMINA:
5695 case MVE_VMAXV:
5696 case MVE_VMAXAV:
5697 case MVE_VMINV:
5698 case MVE_VMINAV:
ed63aa17
AV		 5699 case MVE_VQRSHL_T2:
5700 case MVE_VQSHL_T1:
5701 case MVE_VRSHL_T2:
5702 case MVE_VSHL_T2:
5703 case MVE_VSHLL_T2:
d3b63143 5704 case MVE_VADDV:
14925797
AV		 5705 case MVE_VMOVN:
5706 case MVE_VQMOVUN:
5707 case MVE_VQMOVN:
5708 if (arm_decode_field (given, 18, 19) == 3)
5709 return TRUE;
5710 else
5711 return FALSE;
5712
d3b63143
AV		 5713 case MVE_VMLSLDAV:
5714 case MVE_VRMLSLDAVH:
5715 case MVE_VMLALDAV:
5716 case MVE_VADDLV:
5717 if (arm_decode_field (given, 20, 22) == 7)
5718 return TRUE;
5719 else
5720 return FALSE;
5721
5722 case MVE_VRMLALDAVH:
5723 if ((arm_decode_field (given, 20, 22) & 6) == 6)
5724 return TRUE;
5725 else
5726 return FALSE;
5727
1c8f2df8
AV		 5728 case MVE_VDWDUP:
5729 case MVE_VIWDUP:
5730 if ((arm_decode_field (given, 20, 21) == 3)
5731 || (arm_decode_field (given, 1, 3) == 7))
5732 return TRUE;
5733 else
5734 return FALSE;
5735
ed63aa17
AV		 5736
5737 case MVE_VSHLL_T1:
5738 if (arm_decode_field (given, 16, 18) == 0)
5739 {
5740 unsigned long sz = arm_decode_field (given, 19, 20);
5741
5742 if ((sz == 1) || (sz == 2))
5743 return TRUE;
5744 else
5745 return FALSE;
5746 }
5747 else
5748 return FALSE;
5749
5750 case MVE_VQSHL_T2:
5751 case MVE_VQSHLU_T3:
5752 case MVE_VRSHR:
5753 case MVE_VSHL_T1:
5754 case MVE_VSHR:
5755 case MVE_VSLI:
5756 case MVE_VSRI:
5757 if (arm_decode_field (given, 19, 21) == 0)
5758 return TRUE;
5759 else
5760 return FALSE;
5761
e523f101
AV		 5762 case MVE_VCTP:
5763 if (arm_decode_field (given, 16, 19) == 0xf)
5764 return TRUE;
5765 else
5766 return FALSE;
5767
23d00a41
SD		 5768 case MVE_ASRLI:
5769 case MVE_ASRL:
5770 case MVE_LSLLI:
5771 case MVE_LSLL:
5772 case MVE_LSRL:
5773 case MVE_SQRSHRL:
5774 case MVE_SQSHLL:
5775 case MVE_SRSHRL:
5776 case MVE_UQRSHLL:
5777 case MVE_UQSHLL:
5778 case MVE_URSHRL:
5779 if (arm_decode_field (given, 9, 11) == 0x7)
5780 return TRUE;
5781 else
5782 return FALSE;
5783
e39c1607
SD		 5784 case MVE_CSINC:
5785 case MVE_CSINV:
5786 {
5787 unsigned long rm, rn;
5788 rm = arm_decode_field (given, 0, 3);
5789 rn = arm_decode_field (given, 16, 19);
5790 /* CSET/CSETM. */
5791 if (rm == 0xf && rn == 0xf)
5792 return TRUE;
5793 /* CINC/CINV. */
5794 else if (rn == rm && rn != 0xf)
5795 return TRUE;
5796 }
5797 /* Fall through. */
5798 case MVE_CSEL:
5799 case MVE_CSNEG:
5800 if (arm_decode_field (given, 0, 3) == 0xd)
5801 return TRUE;
5802 /* CNEG. */
5803 else if (matched_insn == MVE_CSNEG)
5804 if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19))
5805 return TRUE;
5806 return FALSE;
5807
143275ea 5808 default:
66dcaa5d
AV		 5809 case MVE_VADD_FP_T1:
5810 case MVE_VADD_FP_T2:
5811 case MVE_VADD_VEC_T1:
143275ea
AV		 5812 return FALSE;
5813
5814 }
73cd51e5
AV		 5815}
5816
aef6d006
AV		 5817static void
5818print_mve_vld_str_addr (struct disassemble_info *info,
5819 unsigned long given,
5820 enum mve_instructions matched_insn)
5821{
5822 void *stream = info->stream;
5823 fprintf_ftype func = info->fprintf_func;
5824
5825 unsigned long p, w, gpr, imm, add, mod_imm;
5826
5827 imm = arm_decode_field (given, 0, 6);
5828 mod_imm = imm;
5829
5830 switch (matched_insn)
5831 {
5832 case MVE_VLDRB_T1:
5833 case MVE_VSTRB_T1:
5834 gpr = arm_decode_field (given, 16, 18);
5835 break;
5836
5837 case MVE_VLDRH_T2:
5838 case MVE_VSTRH_T2:
5839 gpr = arm_decode_field (given, 16, 18);
5840 mod_imm = imm << 1;
5841 break;
5842
5843 case MVE_VLDRH_T6:
5844 case MVE_VSTRH_T6:
5845 gpr = arm_decode_field (given, 16, 19);
5846 mod_imm = imm << 1;
5847 break;
5848
5849 case MVE_VLDRW_T7:
5850 case MVE_VSTRW_T7:
5851 gpr = arm_decode_field (given, 16, 19);
5852 mod_imm = imm << 2;
5853 break;
5854
5855 case MVE_VLDRB_T5:
5856 case MVE_VSTRB_T5:
5857 gpr = arm_decode_field (given, 16, 19);
5858 break;
5859
5860 default:
5861 return;
5862 }
5863
5864 p = arm_decode_field (given, 24, 24);
5865 w = arm_decode_field (given, 21, 21);
5866
5867 add = arm_decode_field (given, 23, 23);
5868
5869 char * add_sub;
5870
5871 /* Don't print anything for '+' as it is implied. */
5872 if (add == 1)
5873 add_sub = "";
5874 else
5875 add_sub = "-";
5876
5877 if (p == 1)
5878 {
5879 /* Offset mode. */
5880 if (w == 0)
5881 func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm);
5882 /* Pre-indexed mode. */
5883 else
5884 func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm);
5885 }
5886 else if ((p == 0) && (w == 1))
5887 /* Post-index mode. */
5888 func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm);
5889}
5890
73cd51e5
AV		 5891/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5892 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5893 this encoding is undefined. */
5894
5895static bfd_boolean
5896is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
5897 enum mve_undefined *undefined_code)
5898{
5899 *undefined_code = UNDEF_NONE;
5900
9743db03
AV		 5901 switch (matched_insn)
5902 {
5903 case MVE_VDUP:
5904 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
5905 {
5906 *undefined_code = UNDEF_SIZE_3;
5907 return TRUE;
5908 }
5909 else
5910 return FALSE;
5911
14b456f2
AV		 5912 case MVE_VQADD_T1:
5913 case MVE_VQSUB_T1:
f49bb598 5914 case MVE_VMUL_VEC_T1:
66dcaa5d
AV		 5915 case MVE_VABD_VEC:
5916 case MVE_VADD_VEC_T1:
5917 case MVE_VSUB_VEC_T1:
d3b63143
AV		 5918 case MVE_VQDMULH_T1:
5919 case MVE_VQRDMULH_T2:
9743db03
AV		 5920 case MVE_VRHADD:
5921 case MVE_VHADD_T1:
5922 case MVE_VHSUB_T1:
5923 if (arm_decode_field (given, 20, 21) == 3)
5924 {
5925 *undefined_code = UNDEF_SIZE_3;
5926 return TRUE;
5927 }
5928 else
5929 return FALSE;
5930
aef6d006
AV		 5931 case MVE_VLDRB_T1:
5932 if (arm_decode_field (given, 7, 8) == 3)
5933 {
5934 *undefined_code = UNDEF_SIZE_3;
5935 return TRUE;
5936 }
5937 else
5938 return FALSE;
5939
5940 case MVE_VLDRH_T2:
5941 if (arm_decode_field (given, 7, 8) <= 1)
5942 {
5943 *undefined_code = UNDEF_SIZE_LE_1;
5944 return TRUE;
5945 }
5946 else
5947 return FALSE;
5948
5949 case MVE_VSTRB_T1:
5950 if ((arm_decode_field (given, 7, 8) == 0))
5951 {
5952 *undefined_code = UNDEF_SIZE_0;
5953 return TRUE;
5954 }
5955 else
5956 return FALSE;
5957
5958 case MVE_VSTRH_T2:
5959 if ((arm_decode_field (given, 7, 8) <= 1))
5960 {
5961 *undefined_code = UNDEF_SIZE_LE_1;
5962 return TRUE;
5963 }
5964 else
5965 return FALSE;
5966
ef1576a1
AV		 5967 case MVE_VLDRB_GATHER_T1:
5968 if (arm_decode_field (given, 7, 8) == 3)
5969 {
5970 *undefined_code = UNDEF_SIZE_3;
5971 return TRUE;
5972 }
5973 else if ((arm_decode_field (given, 28, 28) == 0)
5974 && (arm_decode_field (given, 7, 8) == 0))
5975 {
5976 *undefined_code = UNDEF_NOT_UNS_SIZE_0;
5977 return TRUE;
5978 }
5979 else
5980 return FALSE;
5981
5982 case MVE_VLDRH_GATHER_T2:
5983 if (arm_decode_field (given, 7, 8) == 3)
5984 {
5985 *undefined_code = UNDEF_SIZE_3;
5986 return TRUE;
5987 }
5988 else if ((arm_decode_field (given, 28, 28) == 0)
5989 && (arm_decode_field (given, 7, 8) == 1))
5990 {
5991 *undefined_code = UNDEF_NOT_UNS_SIZE_1;
5992 return TRUE;
5993 }
5994 else if (arm_decode_field (given, 7, 8) == 0)
5995 {
5996 *undefined_code = UNDEF_SIZE_0;
5997 return TRUE;
5998 }
5999 else
6000 return FALSE;
6001
6002 case MVE_VLDRW_GATHER_T3:
6003 if (arm_decode_field (given, 7, 8) != 2)
6004 {
6005 *undefined_code = UNDEF_SIZE_NOT_2;
6006 return TRUE;
6007 }
6008 else if (arm_decode_field (given, 28, 28) == 0)
6009 {
6010 *undefined_code = UNDEF_NOT_UNSIGNED;
6011 return TRUE;
6012 }
6013 else
6014 return FALSE;
6015
6016 case MVE_VLDRD_GATHER_T4:
6017 if (arm_decode_field (given, 7, 8) != 3)
6018 {
6019 *undefined_code = UNDEF_SIZE_NOT_3;
6020 return TRUE;
6021 }
6022 else if (arm_decode_field (given, 28, 28) == 0)
6023 {
6024 *undefined_code = UNDEF_NOT_UNSIGNED;
6025 return TRUE;
6026 }
6027 else
6028 return FALSE;
6029
6030 case MVE_VSTRB_SCATTER_T1:
6031 if (arm_decode_field (given, 7, 8) == 3)
6032 {
6033 *undefined_code = UNDEF_SIZE_3;
6034 return TRUE;
6035 }
6036 else
6037 return FALSE;
6038
6039 case MVE_VSTRH_SCATTER_T2:
6040 {
6041 unsigned long size = arm_decode_field (given, 7, 8);
6042 if (size == 3)
6043 {
6044 *undefined_code = UNDEF_SIZE_3;
6045 return TRUE;
6046 }
6047 else if (size == 0)
6048 {
6049 *undefined_code = UNDEF_SIZE_0;
6050 return TRUE;
6051 }
6052 else
6053 return FALSE;
6054 }
6055
6056 case MVE_VSTRW_SCATTER_T3:
6057 if (arm_decode_field (given, 7, 8) != 2)
6058 {
6059 *undefined_code = UNDEF_SIZE_NOT_2;
6060 return TRUE;
6061 }
6062 else
6063 return FALSE;
6064
6065 case MVE_VSTRD_SCATTER_T4:
6066 if (arm_decode_field (given, 7, 8) != 3)
6067 {
6068 *undefined_code = UNDEF_SIZE_NOT_3;
6069 return TRUE;
6070 }
6071 else
6072 return FALSE;
6073
bf0b396d
AV		 6074 case MVE_VCVT_FP_FIX_VEC:
6075 {
6076 unsigned long imm6 = arm_decode_field (given, 16, 21);
6077 if ((imm6 & 0x20) == 0)
6078 {
6079 *undefined_code = UNDEF_VCVT_IMM6;
6080 return TRUE;
6081 }
6082
6083 if ((arm_decode_field (given, 9, 9) == 0)
6084 && ((imm6 & 0x30) == 0x20))
6085 {
6086 *undefined_code = UNDEF_VCVT_FSI_IMM6;
6087 return TRUE;
6088 }
6089
6090 return FALSE;
6091 }
6092
f49bb598 6093 case MVE_VNEG_FP:
66dcaa5d 6094 case MVE_VABS_FP:
bf0b396d
AV		 6095 case MVE_VCVT_BETWEEN_FP_INT:
6096 case MVE_VCVT_FROM_FP_TO_INT:
6097 {
6098 unsigned long size = arm_decode_field (given, 18, 19);
6099 if (size == 0)
6100 {
6101 *undefined_code = UNDEF_SIZE_0;
6102 return TRUE;
6103 }
6104 else if (size == 3)
6105 {
6106 *undefined_code = UNDEF_SIZE_3;
6107 return TRUE;
6108 }
6109 else
6110 return FALSE;
6111 }
6112
c507f10b
AV		 6113 case MVE_VMOV_VEC_LANE_TO_GP:
6114 {
6115 unsigned long op1 = arm_decode_field (given, 21, 22);
6116 unsigned long op2 = arm_decode_field (given, 5, 6);
6117 unsigned long u = arm_decode_field (given, 23, 23);
6118
6119 if ((op2 == 0) && (u == 1))
6120 {
6121 if ((op1 == 0) || (op1 == 1))
6122 {
6123 *undefined_code = UNDEF_BAD_U_OP1_OP2;
6124 return TRUE;
6125 }
6126 else
6127 return FALSE;
6128 }
6129 else if (op2 == 2)
6130 {
6131 if ((op1 == 0) || (op1 == 1))
6132 {
6133 *undefined_code = UNDEF_BAD_OP1_OP2;
6134 return TRUE;
6135 }
6136 else
6137 return FALSE;
6138 }
6139
6140 return FALSE;
6141 }
6142
6143 case MVE_VMOV_GP_TO_VEC_LANE:
6144 if (arm_decode_field (given, 5, 6) == 2)
6145 {
6146 unsigned long op1 = arm_decode_field (given, 21, 22);
6147 if ((op1 == 0) || (op1 == 1))
6148 {
6149 *undefined_code = UNDEF_BAD_OP1_OP2;
6150 return TRUE;
6151 }
6152 else
6153 return FALSE;
6154 }
6155 else
6156 return FALSE;
6157
c4a23bf8
SP		 6158 case MVE_VMOV_VEC_TO_VEC:
6159 if ((arm_decode_field (given, 5, 5) == 1)
6160 || (arm_decode_field (given, 22, 22) == 1))
6161 return TRUE;
6162 return FALSE;
6163
c507f10b
AV		 6164 case MVE_VMOV_IMM_TO_VEC:
6165 if (arm_decode_field (given, 5, 5) == 0)
6166 {
6167 unsigned long cmode = arm_decode_field (given, 8, 11);
6168
6169 if (((cmode & 9) == 1) || ((cmode & 5) == 1))
6170 {
6171 *undefined_code = UNDEF_OP_0_BAD_CMODE;
6172 return TRUE;
6173 }
6174 else
6175 return FALSE;
6176 }
6177 else
6178 return FALSE;
6179
ed63aa17 6180 case MVE_VSHLL_T2:
14925797
AV		 6181 case MVE_VMOVN:
6182 if (arm_decode_field (given, 18, 19) == 2)
6183 {
6184 *undefined_code = UNDEF_SIZE_2;
6185 return TRUE;
6186 }
6187 else
6188 return FALSE;
6189
d3b63143
AV		 6190 case MVE_VRMLALDAVH:
6191 case MVE_VMLADAV_T1:
6192 case MVE_VMLADAV_T2:
6193 case MVE_VMLALDAV:
6194 if ((arm_decode_field (given, 28, 28) == 1)
6195 && (arm_decode_field (given, 12, 12) == 1))
6196 {
6197 *undefined_code = UNDEF_XCHG_UNS;
6198 return TRUE;
6199 }
6200 else
6201 return FALSE;
6202
ed63aa17
AV		 6203 case MVE_VQSHRN:
6204 case MVE_VQSHRUN:
6205 case MVE_VSHLL_T1:
6206 case MVE_VSHRN:
6207 {
6208 unsigned long sz = arm_decode_field (given, 19, 20);
6209 if (sz == 1)
6210 return FALSE;
6211 else if ((sz & 2) == 2)
6212 return FALSE;
6213 else
6214 {
6215 *undefined_code = UNDEF_SIZE;
6216 return TRUE;
6217 }
6218 }
6219 break;
6220
6221 case MVE_VQSHL_T2:
6222 case MVE_VQSHLU_T3:
6223 case MVE_VRSHR:
6224 case MVE_VSHL_T1:
6225 case MVE_VSHR:
6226 case MVE_VSLI:
6227 case MVE_VSRI:
6228 {
6229 unsigned long sz = arm_decode_field (given, 19, 21);
6230 if ((sz & 7) == 1)
6231 return FALSE;
6232 else if ((sz & 6) == 2)
6233 return FALSE;
6234 else if ((sz & 4) == 4)
6235 return FALSE;
6236 else
6237 {
6238 *undefined_code = UNDEF_SIZE;
6239 return TRUE;
6240 }
6241 }
6242
6243 case MVE_VQRSHRN:
6244 case MVE_VQRSHRUN:
6245 if (arm_decode_field (given, 19, 20) == 0)
6246 {
6247 *undefined_code = UNDEF_SIZE_0;
6248 return TRUE;
6249 }
6250 else
6251 return FALSE;
6252
66dcaa5d
AV		 6253 case MVE_VABS_VEC:
6254 if (arm_decode_field (given, 18, 19) == 3)
6255 {
6256 *undefined_code = UNDEF_SIZE_3;
6257 return TRUE;
6258 }
6259 else
6260 return FALSE;
6261
14b456f2
AV		 6262 case MVE_VQNEG:
6263 case MVE_VQABS:
f49bb598 6264 case MVE_VNEG_VEC:
e523f101
AV		 6265 case MVE_VCLS:
6266 case MVE_VCLZ:
6267 if (arm_decode_field (given, 18, 19) == 3)
6268 {
6269 *undefined_code = UNDEF_SIZE_3;
6270 return TRUE;
6271 }
6272 else
6273 return FALSE;
6274
14b456f2
AV		 6275 case MVE_VREV16:
6276 if (arm_decode_field (given, 18, 19) == 0)
6277 return FALSE;
6278 else
6279 {
6280 *undefined_code = UNDEF_SIZE_NOT_0;
6281 return TRUE;
6282 }
6283
6284 case MVE_VREV32:
6285 {
6286 unsigned long size = arm_decode_field (given, 18, 19);
6287 if ((size & 2) == 2)
6288 {
6289 *undefined_code = UNDEF_SIZE_2;
6290 return TRUE;
6291 }
6292 else
6293 return FALSE;
6294 }
6295
6296 case MVE_VREV64:
6297 if (arm_decode_field (given, 18, 19) != 3)
6298 return FALSE;
6299 else
6300 {
6301 *undefined_code = UNDEF_SIZE_3;
6302 return TRUE;
6303 }
6304
9743db03
AV		 6305 default:
6306 return FALSE;
6307 }
73cd51e5
AV		 6308}
6309
6310/* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6311 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
6312 why this encoding is unpredictable. */
6313
6314static bfd_boolean
6315is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
6316 enum mve_unpredictable *unpredictable_code)
6317{
6318 *unpredictable_code = UNPRED_NONE;
6319
143275ea
AV		 6320 switch (matched_insn)
6321 {
6322 case MVE_VCMP_FP_T2:
6323 case MVE_VPT_FP_T2:
6324 if ((arm_decode_field (given, 12, 12) == 0)
6325 && (arm_decode_field (given, 5, 5) == 1))
6326 {
6327 *unpredictable_code = UNPRED_FCA_0_FCB_1;
6328 return TRUE;
6329 }
6330 else
6331 return FALSE;
73cd51e5 6332
143275ea
AV		 6333 case MVE_VPT_VEC_T4:
6334 case MVE_VPT_VEC_T5:
6335 case MVE_VPT_VEC_T6:
6336 case MVE_VCMP_VEC_T4:
6337 case MVE_VCMP_VEC_T5:
6338 case MVE_VCMP_VEC_T6:
6339 if (arm_decode_field (given, 0, 3) == 0xd)
6340 {
6341 *unpredictable_code = UNPRED_R13;
6342 return TRUE;
6343 }
6344 else
6345 return FALSE;
c1e26897 6346
9743db03
AV		 6347 case MVE_VDUP:
6348 {
6349 unsigned long gpr = arm_decode_field (given, 12, 15);
6350 if (gpr == 0xd)
6351 {
6352 *unpredictable_code = UNPRED_R13;
6353 return TRUE;
6354 }
6355 else if (gpr == 0xf)
6356 {
6357 *unpredictable_code = UNPRED_R15;
6358 return TRUE;
6359 }
6360
6361 return FALSE;
6362 }
6363
14b456f2
AV		 6364 case MVE_VQADD_T2:
6365 case MVE_VQSUB_T2:
f49bb598
AV		 6366 case MVE_VMUL_FP_T2:
6367 case MVE_VMUL_VEC_T2:
56858bea 6368 case MVE_VMLA:
e523f101 6369 case MVE_VBRSR:
66dcaa5d
AV		 6370 case MVE_VADD_FP_T2:
6371 case MVE_VSUB_FP_T2:
6372 case MVE_VADD_VEC_T2:
6373 case MVE_VSUB_VEC_T2:
ed63aa17
AV		 6374 case MVE_VQRSHL_T2:
6375 case MVE_VQSHL_T1:
6376 case MVE_VRSHL_T2:
6377 case MVE_VSHL_T2:
6378 case MVE_VSHLC:
d3b63143
AV		 6379 case MVE_VQDMLAH:
6380 case MVE_VQRDMLAH:
6381 case MVE_VQDMLASH:
6382 case MVE_VQRDMLASH:
6383 case MVE_VQDMULH_T3:
6384 case MVE_VQRDMULH_T4:
6385 case MVE_VMLAS:
9743db03
AV		 6386 case MVE_VFMA_FP_SCALAR:
6387 case MVE_VFMAS_FP_SCALAR:
6388 case MVE_VHADD_T2:
6389 case MVE_VHSUB_T2:
6390 {
6391 unsigned long gpr = arm_decode_field (given, 0, 3);
6392 if (gpr == 0xd)
6393 {
6394 *unpredictable_code = UNPRED_R13;
6395 return TRUE;
6396 }
6397 else if (gpr == 0xf)
6398 {
6399 *unpredictable_code = UNPRED_R15;
6400 return TRUE;
6401 }
6402
6403 return FALSE;
6404 }
6405
04d54ace
AV		 6406 case MVE_VLD2:
6407 case MVE_VST2:
6408 {
6409 unsigned long rn = arm_decode_field (given, 16, 19);
6410
6411 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6412 {
6413 *unpredictable_code = UNPRED_R13_AND_WB;
6414 return TRUE;
6415 }
6416
6417 if (rn == 0xf)
6418 {
6419 *unpredictable_code = UNPRED_R15;
6420 return TRUE;
6421 }
6422
6423 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
6424 {
6425 *unpredictable_code = UNPRED_Q_GT_6;
6426 return TRUE;
6427 }
6428 else
6429 return FALSE;
6430 }
6431
6432 case MVE_VLD4:
6433 case MVE_VST4:
6434 {
6435 unsigned long rn = arm_decode_field (given, 16, 19);
6436
6437 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6438 {
6439 *unpredictable_code = UNPRED_R13_AND_WB;
6440 return TRUE;
6441 }
6442
6443 if (rn == 0xf)
6444 {
6445 *unpredictable_code = UNPRED_R15;
6446 return TRUE;
6447 }
6448
6449 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
6450 {
6451 *unpredictable_code = UNPRED_Q_GT_4;
6452 return TRUE;
6453 }
6454 else
6455 return FALSE;
6456 }
6457
aef6d006
AV		 6458 case MVE_VLDRB_T5:
6459 case MVE_VLDRH_T6:
6460 case MVE_VLDRW_T7:
6461 case MVE_VSTRB_T5:
6462 case MVE_VSTRH_T6:
6463 case MVE_VSTRW_T7:
6464 {
6465 unsigned long rn = arm_decode_field (given, 16, 19);
6466
6467 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6468 {
6469 *unpredictable_code = UNPRED_R13_AND_WB;
6470 return TRUE;
6471 }
6472 else if (rn == 0xf)
6473 {
6474 *unpredictable_code = UNPRED_R15;
6475 return TRUE;
6476 }
6477 else
6478 return FALSE;
6479 }
6480
ef1576a1
AV		 6481 case MVE_VLDRB_GATHER_T1:
6482 if (arm_decode_field (given, 0, 0) == 1)
6483 {
6484 *unpredictable_code = UNPRED_OS;
6485 return TRUE;
6486 }
6487
6488 /* fall through. */
6489 /* To handle common code with T2-T4 variants. */
6490 case MVE_VLDRH_GATHER_T2:
6491 case MVE_VLDRW_GATHER_T3:
6492 case MVE_VLDRD_GATHER_T4:
6493 {
6494 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6495 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6496
6497 if (qd == qm)
6498 {
6499 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6500 return TRUE;
6501 }
6502
6503 if (arm_decode_field (given, 16, 19) == 0xf)
6504 {
6505 *unpredictable_code = UNPRED_R15;
6506 return TRUE;
6507 }
6508
6509 return FALSE;
6510 }
6511
6512 case MVE_VLDRW_GATHER_T5:
6513 case MVE_VLDRD_GATHER_T6:
6514 {
6515 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6516 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
6517
6518 if (qd == qm)
6519 {
6520 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6521 return TRUE;
6522 }
6523 else
6524 return FALSE;
6525 }
6526
6527 case MVE_VSTRB_SCATTER_T1:
6528 if (arm_decode_field (given, 16, 19) == 0xf)
6529 {
6530 *unpredictable_code = UNPRED_R15;
6531 return TRUE;
6532 }
6533 else if (arm_decode_field (given, 0, 0) == 1)
6534 {
6535 *unpredictable_code = UNPRED_OS;
6536 return TRUE;
6537 }
6538 else
6539 return FALSE;
6540
6541 case MVE_VSTRH_SCATTER_T2:
6542 case MVE_VSTRW_SCATTER_T3:
6543 case MVE_VSTRD_SCATTER_T4:
6544 if (arm_decode_field (given, 16, 19) == 0xf)
6545 {
6546 *unpredictable_code = UNPRED_R15;
6547 return TRUE;
6548 }
6549 else
6550 return FALSE;
6551
c507f10b
AV		 6552 case MVE_VMOV2_VEC_LANE_TO_GP:
6553 case MVE_VMOV2_GP_TO_VEC_LANE:
bf0b396d
AV		 6554 case MVE_VCVT_BETWEEN_FP_INT:
6555 case MVE_VCVT_FROM_FP_TO_INT:
6556 {
6557 unsigned long rt = arm_decode_field (given, 0, 3);
6558 unsigned long rt2 = arm_decode_field (given, 16, 19);
6559
6560 if ((rt == 0xd) || (rt2 == 0xd))
6561 {
6562 *unpredictable_code = UNPRED_R13;
6563 return TRUE;
6564 }
6565 else if ((rt == 0xf) || (rt2 == 0xf))
6566 {
6567 *unpredictable_code = UNPRED_R15;
6568 return TRUE;
6569 }
6570 else if (rt == rt2)
6571 {
6572 *unpredictable_code = UNPRED_GP_REGS_EQUAL;
6573 return TRUE;
6574 }
6575
6576 return FALSE;
6577 }
6578
56858bea
AV		 6579 case MVE_VMAXV:
6580 case MVE_VMAXAV:
6581 case MVE_VMAXNMV_FP:
6582 case MVE_VMAXNMAV_FP:
6583 case MVE_VMINNMV_FP:
6584 case MVE_VMINNMAV_FP:
6585 case MVE_VMINV:
6586 case MVE_VMINAV:
66dcaa5d 6587 case MVE_VABAV:
c507f10b
AV		 6588 case MVE_VMOV_HFP_TO_GP:
6589 case MVE_VMOV_GP_TO_VEC_LANE:
6590 case MVE_VMOV_VEC_LANE_TO_GP:
6591 {
6592 unsigned long rda = arm_decode_field (given, 12, 15);
6593 if (rda == 0xd)
6594 {
6595 *unpredictable_code = UNPRED_R13;
6596 return TRUE;
6597 }
6598 else if (rda == 0xf)
6599 {
6600 *unpredictable_code = UNPRED_R15;
6601 return TRUE;
6602 }
6603
6604 return FALSE;
6605 }
6606
14925797
AV		 6607 case MVE_VMULL_INT:
6608 {
6609 unsigned long Qd;
6610 unsigned long Qm;
6611 unsigned long Qn;
6612
6613 if (arm_decode_field (given, 20, 21) == 2)
6614 {
6615 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6616 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6617 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6618
6619 if ((Qd == Qn) || (Qd == Qm))
6620 {
6621 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6622 return TRUE;
6623 }
6624 else
6625 return FALSE;
6626 }
6627 else
6628 return FALSE;
6629 }
6630
897b9bbc 6631 case MVE_VCMUL_FP:
14925797
AV		 6632 case MVE_VQDMULL_T1:
6633 {
6634 unsigned long Qd;
6635 unsigned long Qm;
6636 unsigned long Qn;
6637
6638 if (arm_decode_field (given, 28, 28) == 1)
6639 {
6640 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6641 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6642 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6643
6644 if ((Qd == Qn) || (Qd == Qm))
6645 {
6646 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6647 return TRUE;
6648 }
6649 else
6650 return FALSE;
6651 }
6652 else
6653 return FALSE;
6654 }
6655
6656 case MVE_VQDMULL_T2:
6657 {
6658 unsigned long gpr = arm_decode_field (given, 0, 3);
6659 if (gpr == 0xd)
6660 {
6661 *unpredictable_code = UNPRED_R13;
6662 return TRUE;
6663 }
6664 else if (gpr == 0xf)
6665 {
6666 *unpredictable_code = UNPRED_R15;
6667 return TRUE;
6668 }
6669
6670 if (arm_decode_field (given, 28, 28) == 1)
6671 {
6672 unsigned long Qd
6673 = arm_decode_field_multiple (given, 13, 15, 22, 22);
6674 unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6675
a9d96ab9 6676 if (Qd == Qn)
14925797
AV		 6677 {
6678 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6679 return TRUE;
6680 }
6681 else
6682 return FALSE;
6683 }
6684
6685 return FALSE;
6686 }
6687
d3b63143
AV		 6688 case MVE_VMLSLDAV:
6689 case MVE_VRMLSLDAVH:
6690 case MVE_VMLALDAV:
6691 case MVE_VADDLV:
6692 if (arm_decode_field (given, 20, 22) == 6)
6693 {
6694 *unpredictable_code = UNPRED_R13;
6695 return TRUE;
6696 }
6697 else
6698 return FALSE;
6699
1c8f2df8
AV		 6700 case MVE_VDWDUP:
6701 case MVE_VIWDUP:
6702 if (arm_decode_field (given, 1, 3) == 6)
6703 {
6704 *unpredictable_code = UNPRED_R13;
6705 return TRUE;
6706 }
6707 else
6708 return FALSE;
6709
897b9bbc
AV		 6710 case MVE_VCADD_VEC:
6711 case MVE_VHCADD:
6712 {
6713 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6714 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6715 if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
6716 {
6717 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6718 return TRUE;
6719 }
6720 else
6721 return FALSE;
6722 }
6723
6724 case MVE_VCADD_FP:
6725 {
6726 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6727 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6728 if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
6729 {
6730 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6731 return TRUE;
6732 }
6733 else
6734 return FALSE;
6735 }
6736
6737 case MVE_VCMLA_FP:
6738 {
6739 unsigned long Qda;
6740 unsigned long Qm;
6741 unsigned long Qn;
6742
6743 if (arm_decode_field (given, 20, 20) == 1)
6744 {
6745 Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
6746 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6747 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6748
6749 if ((Qda == Qn) || (Qda == Qm))
6750 {
6751 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6752 return TRUE;
6753 }
6754 else
6755 return FALSE;
6756 }
6757 else
6758 return FALSE;
6759
6760 }
6761
e523f101
AV		 6762 case MVE_VCTP:
6763 if (arm_decode_field (given, 16, 19) == 0xd)
6764 {
6765 *unpredictable_code = UNPRED_R13;
6766 return TRUE;
6767 }
6768 else
6769 return FALSE;
6770
14b456f2
AV		 6771 case MVE_VREV64:
6772 {
6773 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6774 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6);
6775
6776 if (qd == qm)
6777 {
6778 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6779 return TRUE;
6780 }
6781 else
6782 return FALSE;
6783 }
6784
23d00a41
SD		 6785 case MVE_LSLL:
6786 case MVE_LSLLI:
6787 case MVE_LSRL:
6788 case MVE_ASRL:
6789 case MVE_ASRLI:
6790 case MVE_UQSHLL:
6791 case MVE_UQRSHLL:
6792 case MVE_URSHRL:
6793 case MVE_SRSHRL:
6794 case MVE_SQSHLL:
6795 case MVE_SQRSHRL:
6796 {
6797 unsigned long gpr = arm_decode_field (given, 9, 11);
6798 gpr = ((gpr << 1) | 1);
6799 if (gpr == 0xd)
6800 {
6801 *unpredictable_code = UNPRED_R13;
6802 return TRUE;
6803 }
6804 else if (gpr == 0xf)
6805 {
6806 *unpredictable_code = UNPRED_R15;
6807 return TRUE;
6808 }
6809
6810 return FALSE;
6811 }
6812
143275ea
AV		 6813 default:
6814 return FALSE;
6815 }
6816}
c1e26897 6817
c507f10b
AV		 6818static void
6819print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
6820{
6821 unsigned long op1 = arm_decode_field (given, 21, 22);
6822 unsigned long op2 = arm_decode_field (given, 5, 6);
6823 unsigned long h = arm_decode_field (given, 16, 16);
43dd7626 6824 unsigned long index_operand, esize, targetBeat, idx;
c507f10b
AV		 6825 void *stream = info->stream;
6826 fprintf_ftype func = info->fprintf_func;
6827
6828 if ((op1 & 0x2) == 0x2)
6829 {
43dd7626 6830 index_operand = op2;
c507f10b
AV		 6831 esize = 8;
6832 }
6833 else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
6834 {
43dd7626 6835 index_operand = op2 >> 1;
c507f10b
AV		 6836 esize = 16;
6837 }
6838 else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
6839 {
43dd7626 6840 index_operand = 0;
c507f10b
AV		 6841 esize = 32;
6842 }
6843 else
6844 {
6845 func (stream, "<undefined index>");
6846 return;
6847 }
6848
6849 targetBeat = (op1 & 0x1) | (h << 1);
43dd7626 6850 idx = index_operand + targetBeat * (32/esize);
c507f10b
AV		 6851
6852 func (stream, "%lu", idx);
6853}
6854
6855/* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6856 in length and integer of floating-point type. */
6857static void
6858print_simd_imm8 (struct disassemble_info *info, unsigned long given,
6859 unsigned int ibit_loc, const struct mopcode32 *insn)
6860{
6861 int bits = 0;
6862 int cmode = (given >> 8) & 0xf;
6863 int op = (given >> 5) & 0x1;
6864 unsigned long value = 0, hival = 0;
6865 unsigned shift;
6866 int size = 0;
6867 int isfloat = 0;
6868 void *stream = info->stream;
6869 fprintf_ftype func = info->fprintf_func;
6870
6871 /* On Neon the 'i' bit is at bit 24, on mve it is
6872 at bit 28. */
6873 bits |= ((given >> ibit_loc) & 1) << 7;
6874 bits |= ((given >> 16) & 7) << 4;
6875 bits |= ((given >> 0) & 15) << 0;
6876
6877 if (cmode < 8)
6878 {
6879 shift = (cmode >> 1) & 3;
6880 value = (unsigned long) bits << (8 * shift);
6881 size = 32;
6882 }
6883 else if (cmode < 12)
6884 {
6885 shift = (cmode >> 1) & 1;
6886 value = (unsigned long) bits << (8 * shift);
6887 size = 16;
6888 }
6889 else if (cmode < 14)
6890 {
6891 shift = (cmode & 1) + 1;
6892 value = (unsigned long) bits << (8 * shift);
6893 value |= (1ul << (8 * shift)) - 1;
6894 size = 32;
6895 }
6896 else if (cmode == 14)
6897 {
6898 if (op)
6899 {
6900 /* Bit replication into bytes. */
6901 int ix;
6902 unsigned long mask;
6903
6904 value = 0;
6905 hival = 0;
6906 for (ix = 7; ix >= 0; ix--)
6907 {
6908 mask = ((bits >> ix) & 1) ? 0xff : 0;
6909 if (ix <= 3)
6910 value = (value << 8) | mask;
6911 else
6912 hival = (hival << 8) | mask;
6913 }
6914 size = 64;
6915 }
6916 else
6917 {
6918 /* Byte replication. */
6919 value = (unsigned long) bits;
6920 size = 8;
6921 }
6922 }
6923 else if (!op)
6924 {
6925 /* Floating point encoding. */
6926 int tmp;
6927
6928 value = (unsigned long) (bits & 0x7f) << 19;
6929 value |= (unsigned long) (bits & 0x80) << 24;
6930 tmp = bits & 0x40 ? 0x3c : 0x40;
6931 value |= (unsigned long) tmp << 24;
6932 size = 32;
6933 isfloat = 1;
6934 }
6935 else
6936 {
6937 func (stream, "<illegal constant %.8x:%x:%x>",
6938 bits, cmode, op);
6939 size = 32;
6940 return;
6941 }
6942
6943 // printU determines whether the immediate value should be printed as
6944 // unsigned.
6945 unsigned printU = 0;
6946 switch (insn->mve_op)
6947 {
6948 default:
6949 break;
6950 // We want this for instructions that don't have a 'signed' type
6951 case MVE_VBIC_IMM:
6952 case MVE_VORR_IMM:
6953 case MVE_VMVN_IMM:
6954 case MVE_VMOV_IMM_TO_VEC:
6955 printU = 1;
6956 break;
6957 }
6958 switch (size)
6959 {
6960 case 8:
6961 func (stream, "#%ld\t; 0x%.2lx", value, value);
6962 break;
6963
6964 case 16:
6965 func (stream,
6966 printU
6967 ? "#%lu\t; 0x%.4lx"
6968 : "#%ld\t; 0x%.4lx", value, value);
6969 break;
6970
6971 case 32:
6972 if (isfloat)
6973 {
6974 unsigned char valbytes[4];
6975 double fvalue;
6976
6977 /* Do this a byte at a time so we don't have to
6978 worry about the host's endianness. */
6979 valbytes[0] = value & 0xff;
6980 valbytes[1] = (value >> 8) & 0xff;
6981 valbytes[2] = (value >> 16) & 0xff;
6982 valbytes[3] = (value >> 24) & 0xff;
6983
6984 floatformat_to_double
6985 (& floatformat_ieee_single_little, valbytes,
6986 & fvalue);
6987
6988 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
6989 value);
6990 }
6991 else
6992 func (stream,
6993 printU
6994 ? "#%lu\t; 0x%.8lx"
6995 : "#%ld\t; 0x%.8lx",
6996 (long) (((value & 0x80000000L) != 0)
6997 && !printU
6998 ? value | ~0xffffffffL : value),
6999 value);
7000 break;
7001
7002 case 64:
7003 func (stream, "#0x%.8lx%.8lx", hival, value);
7004 break;
7005
7006 default:
7007 abort ();
7008 }
7009
7010}
7011
73cd51e5
AV		 7012static void
7013print_mve_undefined (struct disassemble_info *info,
7014 enum mve_undefined undefined_code)
7015{
7016 void *stream = info->stream;
7017 fprintf_ftype func = info->fprintf_func;
7018
7019 func (stream, "\t\tundefined instruction: ");
7020
7021 switch (undefined_code)
7022 {
ed63aa17
AV		 7023 case UNDEF_SIZE:
7024 func (stream, "illegal size");
7025 break;
7026
aef6d006
AV		 7027 case UNDEF_SIZE_0:
7028 func (stream, "size equals zero");
7029 break;
7030
c507f10b
AV		 7031 case UNDEF_SIZE_2:
7032 func (stream, "size equals two");
7033 break;
7034
9743db03
AV		 7035 case UNDEF_SIZE_3:
7036 func (stream, "size equals three");
7037 break;
7038
aef6d006
AV		 7039 case UNDEF_SIZE_LE_1:
7040 func (stream, "size <= 1");
7041 break;
7042
14b456f2
AV		 7043 case UNDEF_SIZE_NOT_0:
7044 func (stream, "size not equal to 0");
7045 break;
7046
ef1576a1
AV		 7047 case UNDEF_SIZE_NOT_2:
7048 func (stream, "size not equal to 2");
7049 break;
7050
7051 case UNDEF_SIZE_NOT_3:
7052 func (stream, "size not equal to 3");
7053 break;
7054
7055 case UNDEF_NOT_UNS_SIZE_0:
7056 func (stream, "not unsigned and size = zero");
7057 break;
7058
7059 case UNDEF_NOT_UNS_SIZE_1:
7060 func (stream, "not unsigned and size = one");
7061 break;
7062
7063 case UNDEF_NOT_UNSIGNED:
7064 func (stream, "not unsigned");
7065 break;
7066
bf0b396d
AV		 7067 case UNDEF_VCVT_IMM6:
7068 func (stream, "invalid imm6");
7069 break;
7070
7071 case UNDEF_VCVT_FSI_IMM6:
7072 func (stream, "fsi = 0 and invalid imm6");
7073 break;
7074
c507f10b
AV		 7075 case UNDEF_BAD_OP1_OP2:
7076 func (stream, "bad size with op2 = 2 and op1 = 0 or 1");
7077 break;
7078
7079 case UNDEF_BAD_U_OP1_OP2:
7080 func (stream, "unsigned with op2 = 0 and op1 = 0 or 1");
7081 break;
7082
7083 case UNDEF_OP_0_BAD_CMODE:
7084 func (stream, "op field equal 0 and bad cmode");
7085 break;
7086
d3b63143
AV		 7087 case UNDEF_XCHG_UNS:
7088 func (stream, "exchange and unsigned together");
7089 break;
7090
73cd51e5
AV		 7091 case UNDEF_NONE:
7092 break;
7093 }
7094
7095}
7096
7097static void
7098print_mve_unpredictable (struct disassemble_info *info,
7099 enum mve_unpredictable unpredict_code)
7100{
7101 void *stream = info->stream;
7102 fprintf_ftype func = info->fprintf_func;
7103
7104 func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
7105
7106 switch (unpredict_code)
7107 {
7108 case UNPRED_IT_BLOCK:
7109 func (stream, "mve instruction in it block");
7110 break;
7111
143275ea
AV		 7112 case UNPRED_FCA_0_FCB_1:
7113 func (stream, "condition bits, fca = 0 and fcb = 1");
7114 break;
7115
7116 case UNPRED_R13:
7117 func (stream, "use of r13 (sp)");
7118 break;
7119
9743db03
AV		 7120 case UNPRED_R15:
7121 func (stream, "use of r15 (pc)");
7122 break;
7123
04d54ace
AV		 7124 case UNPRED_Q_GT_4:
7125 func (stream, "start register block > r4");
7126 break;
7127
7128 case UNPRED_Q_GT_6:
7129 func (stream, "start register block > r6");
7130 break;
7131
7132 case UNPRED_R13_AND_WB:
7133 func (stream, "use of r13 and write back");
7134 break;
7135
ef1576a1
AV		 7136 case UNPRED_Q_REGS_EQUAL:
7137 func (stream,
7138 "same vector register used for destination and other operand");
7139 break;
7140
7141 case UNPRED_OS:
7142 func (stream, "use of offset scaled");
7143 break;
7144
bf0b396d
AV		 7145 case UNPRED_GP_REGS_EQUAL:
7146 func (stream, "same general-purpose register used for both operands");
7147 break;
7148
c507f10b
AV		 7149 case UNPRED_Q_REGS_EQ_AND_SIZE_1:
7150 func (stream, "use of identical q registers and size = 1");
7151 break;
7152
7153 case UNPRED_Q_REGS_EQ_AND_SIZE_2:
7154 func (stream, "use of identical q registers and size = 1");
7155 break;
7156
73cd51e5
AV		 7157 case UNPRED_NONE:
7158 break;
7159 }
7160}
7161
04d54ace
AV		 7162/* Print register block operand for mve vld2/vld4/vst2/vld4. */
7163
7164static void
7165print_mve_register_blocks (struct disassemble_info *info,
7166 unsigned long given,
7167 enum mve_instructions matched_insn)
7168{
7169 void *stream = info->stream;
7170 fprintf_ftype func = info->fprintf_func;
7171
7172 unsigned long q_reg_start = arm_decode_field_multiple (given,
7173 13, 15,
7174 22, 22);
7175 switch (matched_insn)
7176 {
7177 case MVE_VLD2:
7178 case MVE_VST2:
7179 if (q_reg_start <= 6)
7180 func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
7181 else
7182 func (stream, "<illegal reg q%ld>", q_reg_start);
7183 break;
7184
7185 case MVE_VLD4:
7186 case MVE_VST4:
7187 if (q_reg_start <= 4)
7188 func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
7189 q_reg_start + 1, q_reg_start + 2,
7190 q_reg_start + 3);
7191 else
7192 func (stream, "<illegal reg q%ld>", q_reg_start);
7193 break;
7194
7195 default:
7196 break;
7197 }
7198}
7199
bf0b396d
AV		 7200static void
7201print_mve_rounding_mode (struct disassemble_info *info,
7202 unsigned long given,
7203 enum mve_instructions matched_insn)
7204{
7205 void *stream = info->stream;
7206 fprintf_ftype func = info->fprintf_func;
7207
7208 switch (matched_insn)
7209 {
7210 case MVE_VCVT_FROM_FP_TO_INT:
7211 {
7212 switch (arm_decode_field (given, 8, 9))
7213 {
7214 case 0:
7215 func (stream, "a");
7216 break;
7217
7218 case 1:
7219 func (stream, "n");
7220 break;
7221
7222 case 2:
7223 func (stream, "p");
7224 break;
7225
7226 case 3:
7227 func (stream, "m");
7228 break;
7229
7230 default:
7231 break;
7232 }
7233 }
7234 break;
7235
7236 case MVE_VRINT_FP:
7237 {
7238 switch (arm_decode_field (given, 7, 9))
7239 {
7240 case 0:
7241 func (stream, "n");
7242 break;
7243
7244 case 1:
7245 func (stream, "x");
7246 break;
7247
7248 case 2:
7249 func (stream, "a");
7250 break;
7251
7252 case 3:
7253 func (stream, "z");
7254 break;
7255
7256 case 5:
7257 func (stream, "m");
7258 break;
7259
7260 case 7:
7261 func (stream, "p");
7262
7263 case 4:
7264 case 6:
7265 default:
7266 break;
7267 }
7268 }
7269 break;
7270
7271 default:
7272 break;
7273 }
7274}
7275
7276static void
7277print_mve_vcvt_size (struct disassemble_info *info,
7278 unsigned long given,
7279 enum mve_instructions matched_insn)
7280{
7281 unsigned long mode = 0;
7282 void *stream = info->stream;
7283 fprintf_ftype func = info->fprintf_func;
7284
7285 switch (matched_insn)
7286 {
7287 case MVE_VCVT_FP_FIX_VEC:
7288 {
7289 mode = (((given & 0x200) >> 7)
7290 | ((given & 0x10000000) >> 27)
7291 | ((given & 0x100) >> 8));
7292
7293 switch (mode)
7294 {
7295 case 0:
7296 func (stream, "f16.s16");
7297 break;
7298
7299 case 1:
7300 func (stream, "s16.f16");
7301 break;
7302
7303 case 2:
7304 func (stream, "f16.u16");
7305 break;
7306
7307 case 3:
7308 func (stream, "u16.f16");
7309 break;
7310
7311 case 4:
7312 func (stream, "f32.s32");
7313 break;
7314
7315 case 5:
7316 func (stream, "s32.f32");
7317 break;
7318
7319 case 6:
7320 func (stream, "f32.u32");
7321 break;
7322
7323 case 7:
7324 func (stream, "u32.f32");
7325 break;
7326
7327 default:
7328 break;
7329 }
7330 break;
7331 }
7332 case MVE_VCVT_BETWEEN_FP_INT:
7333 {
7334 unsigned long size = arm_decode_field (given, 18, 19);
7335 unsigned long op = arm_decode_field (given, 7, 8);
7336
7337 if (size == 1)
7338 {
7339 switch (op)
7340 {
7341 case 0:
7342 func (stream, "f16.s16");
7343 break;
7344
7345 case 1:
7346 func (stream, "f16.u16");
7347 break;
7348
7349 case 2:
7350 func (stream, "s16.f16");
7351 break;
7352
7353 case 3:
7354 func (stream, "u16.f16");
7355 break;
7356
7357 default:
7358 break;
7359 }
7360 }
7361 else if (size == 2)
7362 {
7363 switch (op)
7364 {
7365 case 0:
7366 func (stream, "f32.s32");
7367 break;
7368
7369 case 1:
7370 func (stream, "f32.u32");
7371 break;
7372
7373 case 2:
7374 func (stream, "s32.f32");
7375 break;
7376
7377 case 3:
7378 func (stream, "u32.f32");
7379 break;
7380 }
7381 }
7382 }
7383 break;
7384
7385 case MVE_VCVT_FP_HALF_FP:
7386 {
7387 unsigned long op = arm_decode_field (given, 28, 28);
7388 if (op == 0)
7389 func (stream, "f16.f32");
7390 else if (op == 1)
7391 func (stream, "f32.f16");
7392 }
7393 break;
7394
7395 case MVE_VCVT_FROM_FP_TO_INT:
7396 {
7397 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
7398
7399 switch (size)
7400 {
7401 case 2:
7402 func (stream, "s16.f16");
7403 break;
7404
7405 case 3:
7406 func (stream, "u16.f16");
7407 break;
7408
7409 case 4:
7410 func (stream, "s32.f32");
7411 break;
7412
7413 case 5:
7414 func (stream, "u32.f32");
7415 break;
7416
7417 default:
7418 break;
7419 }
7420 }
7421 break;
7422
7423 default:
7424 break;
7425 }
7426}
7427
897b9bbc
AV		 7428static void
7429print_mve_rotate (struct disassemble_info *info, unsigned long rot,
7430 unsigned long rot_width)
7431{
7432 void *stream = info->stream;
7433 fprintf_ftype func = info->fprintf_func;
7434
7435 if (rot_width == 1)
7436 {
7437 switch (rot)
7438 {
7439 case 0:
7440 func (stream, "90");
7441 break;
7442 case 1:
7443 func (stream, "270");
7444 break;
7445 default:
7446 break;
7447 }
7448 }
7449 else if (rot_width == 2)
7450 {
7451 switch (rot)
7452 {
7453 case 0:
7454 func (stream, "0");
7455 break;
7456 case 1:
7457 func (stream, "90");
7458 break;
7459 case 2:
7460 func (stream, "180");
7461 break;
7462 case 3:
7463 func (stream, "270");
7464 break;
7465 default:
7466 break;
7467 }
7468 }
7469}
7470
143275ea
AV		 7471static void
7472print_instruction_predicate (struct disassemble_info *info)
7473{
7474 void *stream = info->stream;
7475 fprintf_ftype func = info->fprintf_func;
7476
7477 if (vpt_block_state.next_pred_state == PRED_THEN)
7478 func (stream, "t");
7479 else if (vpt_block_state.next_pred_state == PRED_ELSE)
7480 func (stream, "e");
7481}
7482
7483static void
7484print_mve_size (struct disassemble_info *info,
7485 unsigned long size,
7486 enum mve_instructions matched_insn)
7487{
7488 void *stream = info->stream;
7489 fprintf_ftype func = info->fprintf_func;
7490
7491 switch (matched_insn)
7492 {
66dcaa5d
AV		 7493 case MVE_VABAV:
7494 case MVE_VABD_VEC:
7495 case MVE_VABS_FP:
7496 case MVE_VABS_VEC:
7497 case MVE_VADD_VEC_T1:
7498 case MVE_VADD_VEC_T2:
d3b63143 7499 case MVE_VADDV:
e523f101 7500 case MVE_VBRSR:
897b9bbc 7501 case MVE_VCADD_VEC:
e523f101
AV		 7502 case MVE_VCLS:
7503 case MVE_VCLZ:
143275ea
AV		 7504 case MVE_VCMP_VEC_T1:
7505 case MVE_VCMP_VEC_T2:
7506 case MVE_VCMP_VEC_T3:
7507 case MVE_VCMP_VEC_T4:
7508 case MVE_VCMP_VEC_T5:
7509 case MVE_VCMP_VEC_T6:
e523f101 7510 case MVE_VCTP:
1c8f2df8
AV		 7511 case MVE_VDDUP:
7512 case MVE_VDWDUP:
9743db03
AV		 7513 case MVE_VHADD_T1:
7514 case MVE_VHADD_T2:
897b9bbc 7515 case MVE_VHCADD:
9743db03
AV		 7516 case MVE_VHSUB_T1:
7517 case MVE_VHSUB_T2:
1c8f2df8
AV		 7518 case MVE_VIDUP:
7519 case MVE_VIWDUP:
04d54ace
AV		 7520 case MVE_VLD2:
7521 case MVE_VLD4:
ef1576a1
AV		 7522 case MVE_VLDRB_GATHER_T1:
7523 case MVE_VLDRH_GATHER_T2:
7524 case MVE_VLDRW_GATHER_T3:
7525 case MVE_VLDRD_GATHER_T4:
aef6d006
AV		 7526 case MVE_VLDRB_T1:
7527 case MVE_VLDRH_T2:
56858bea
AV		 7528 case MVE_VMAX:
7529 case MVE_VMAXA:
7530 case MVE_VMAXV:
7531 case MVE_VMAXAV:
7532 case MVE_VMIN:
7533 case MVE_VMINA:
7534 case MVE_VMINV:
7535 case MVE_VMINAV:
7536 case MVE_VMLA:
d3b63143 7537 case MVE_VMLAS:
f49bb598
AV		 7538 case MVE_VMUL_VEC_T1:
7539 case MVE_VMUL_VEC_T2:
7540 case MVE_VMULH:
7541 case MVE_VRMULH:
7542 case MVE_VMULL_INT:
7543 case MVE_VNEG_FP:
7544 case MVE_VNEG_VEC:
143275ea
AV		 7545 case MVE_VPT_VEC_T1:
7546 case MVE_VPT_VEC_T2:
7547 case MVE_VPT_VEC_T3:
7548 case MVE_VPT_VEC_T4:
7549 case MVE_VPT_VEC_T5:
7550 case MVE_VPT_VEC_T6:
14b456f2
AV		 7551 case MVE_VQABS:
7552 case MVE_VQADD_T1:
7553 case MVE_VQADD_T2:
d3b63143
AV		 7554 case MVE_VQDMLADH:
7555 case MVE_VQRDMLADH:
7556 case MVE_VQDMLAH:
7557 case MVE_VQRDMLAH:
7558 case MVE_VQDMLASH:
7559 case MVE_VQRDMLASH:
7560 case MVE_VQDMLSDH:
7561 case MVE_VQRDMLSDH:
7562 case MVE_VQDMULH_T1:
7563 case MVE_VQRDMULH_T2:
7564 case MVE_VQDMULH_T3:
7565 case MVE_VQRDMULH_T4:
14b456f2 7566 case MVE_VQNEG:
ed63aa17
AV		 7567 case MVE_VQRSHL_T1:
7568 case MVE_VQRSHL_T2:
7569 case MVE_VQSHL_T1:
7570 case MVE_VQSHL_T4:
14b456f2
AV		 7571 case MVE_VQSUB_T1:
7572 case MVE_VQSUB_T2:
7573 case MVE_VREV32:
7574 case MVE_VREV64:
9743db03 7575 case MVE_VRHADD:
bf0b396d 7576 case MVE_VRINT_FP:
ed63aa17
AV		 7577 case MVE_VRSHL_T1:
7578 case MVE_VRSHL_T2:
7579 case MVE_VSHL_T2:
7580 case MVE_VSHL_T3:
7581 case MVE_VSHLL_T2:
04d54ace
AV		 7582 case MVE_VST2:
7583 case MVE_VST4:
ef1576a1
AV		 7584 case MVE_VSTRB_SCATTER_T1:
7585 case MVE_VSTRH_SCATTER_T2:
7586 case MVE_VSTRW_SCATTER_T3:
aef6d006
AV		 7587 case MVE_VSTRB_T1:
7588 case MVE_VSTRH_T2:
66dcaa5d
AV		 7589 case MVE_VSUB_VEC_T1:
7590 case MVE_VSUB_VEC_T2:
143275ea
AV		 7591 if (size <= 3)
7592 func (stream, "%s", mve_vec_sizename[size]);
7593 else
7594 func (stream, "<undef size>");
7595 break;
7596
66dcaa5d
AV		 7597 case MVE_VABD_FP:
7598 case MVE_VADD_FP_T1:
7599 case MVE_VADD_FP_T2:
7600 case MVE_VSUB_FP_T1:
7601 case MVE_VSUB_FP_T2:
143275ea
AV		 7602 case MVE_VCMP_FP_T1:
7603 case MVE_VCMP_FP_T2:
9743db03
AV		 7604 case MVE_VFMA_FP_SCALAR:
7605 case MVE_VFMA_FP:
7606 case MVE_VFMS_FP:
7607 case MVE_VFMAS_FP_SCALAR:
56858bea
AV		 7608 case MVE_VMAXNM_FP:
7609 case MVE_VMAXNMA_FP:
7610 case MVE_VMAXNMV_FP:
7611 case MVE_VMAXNMAV_FP:
7612 case MVE_VMINNM_FP:
7613 case MVE_VMINNMA_FP:
7614 case MVE_VMINNMV_FP:
7615 case MVE_VMINNMAV_FP:
f49bb598
AV		 7616 case MVE_VMUL_FP_T1:
7617 case MVE_VMUL_FP_T2:
143275ea
AV		 7618 case MVE_VPT_FP_T1:
7619 case MVE_VPT_FP_T2:
7620 if (size == 0)
7621 func (stream, "32");
7622 else if (size == 1)
7623 func (stream, "16");
7624 break;
7625
897b9bbc
AV		 7626 case MVE_VCADD_FP:
7627 case MVE_VCMLA_FP:
7628 case MVE_VCMUL_FP:
d3b63143
AV		 7629 case MVE_VMLADAV_T1:
7630 case MVE_VMLALDAV:
7631 case MVE_VMLSDAV_T1:
7632 case MVE_VMLSLDAV:
14925797
AV		 7633 case MVE_VMOVN:
7634 case MVE_VQDMULL_T1:
7635 case MVE_VQDMULL_T2:
7636 case MVE_VQMOVN:
7637 case MVE_VQMOVUN:
7638 if (size == 0)
7639 func (stream, "16");
7640 else if (size == 1)
7641 func (stream, "32");
7642 break;
7643
7644 case MVE_VMOVL:
7645 if (size == 1)
7646 func (stream, "8");
7647 else if (size == 2)
7648 func (stream, "16");
7649 break;
7650
9743db03
AV		 7651 case MVE_VDUP:
7652 switch (size)
7653 {
7654 case 0:
7655 func (stream, "32");
7656 break;
7657 case 1:
7658 func (stream, "16");
7659 break;
7660 case 2:
7661 func (stream, "8");
7662 break;
7663 default:
7664 break;
7665 }
7666 break;
7667
c507f10b
AV		 7668 case MVE_VMOV_GP_TO_VEC_LANE:
7669 case MVE_VMOV_VEC_LANE_TO_GP:
7670 switch (size)
7671 {
7672 case 0: case 4:
7673 func (stream, "32");
7674 break;
7675
7676 case 1: case 3:
7677 case 5: case 7:
7678 func (stream, "16");
7679 break;
7680
7681 case 8: case 9: case 10: case 11:
7682 case 12: case 13: case 14: case 15:
7683 func (stream, "8");
7684 break;
7685
7686 default:
7687 break;
7688 }
7689 break;
7690
7691 case MVE_VMOV_IMM_TO_VEC:
7692 switch (size)
7693 {
7694 case 0: case 4: case 8:
7695 case 12: case 24: case 26:
7696 func (stream, "i32");
7697 break;
7698 case 16: case 20:
7699 func (stream, "i16");
7700 break;
7701 case 28:
7702 func (stream, "i8");
7703 break;
7704 case 29:
7705 func (stream, "i64");
7706 break;
7707 case 30:
7708 func (stream, "f32");
7709 break;
7710 default:
7711 break;
7712 }
7713 break;
7714
14925797
AV		 7715 case MVE_VMULL_POLY:
7716 if (size == 0)
7717 func (stream, "p8");
7718 else if (size == 1)
7719 func (stream, "p16");
7720 break;
7721
c507f10b
AV		 7722 case MVE_VMVN_IMM:
7723 switch (size)
7724 {
7725 case 0: case 2: case 4:
7726 case 6: case 12: case 13:
7727 func (stream, "32");
7728 break;
7729
7730 case 8: case 10:
7731 func (stream, "16");
7732 break;
7733
7734 default:
7735 break;
7736 }
7737 break;
7738
7739 case MVE_VBIC_IMM:
7740 case MVE_VORR_IMM:
7741 switch (size)
7742 {
7743 case 1: case 3:
7744 case 5: case 7:
7745 func (stream, "32");
7746 break;
7747
7748 case 9: case 11:
7749 func (stream, "16");
7750 break;
7751
7752 default:
7753 break;
7754 }
7755 break;
7756
ed63aa17
AV		 7757 case MVE_VQSHRN:
7758 case MVE_VQSHRUN:
7759 case MVE_VQRSHRN:
7760 case MVE_VQRSHRUN:
7761 case MVE_VRSHRN:
7762 case MVE_VSHRN:
7763 {
7764 switch (size)
7765 {
7766 case 1:
7767 func (stream, "16");
7768 break;
7769
7770 case 2: case 3:
7771 func (stream, "32");
7772 break;
7773
7774 default:
7775 break;
7776 }
7777 }
7778 break;
7779
7780 case MVE_VQSHL_T2:
7781 case MVE_VQSHLU_T3:
7782 case MVE_VRSHR:
7783 case MVE_VSHL_T1:
7784 case MVE_VSHLL_T1:
7785 case MVE_VSHR:
7786 case MVE_VSLI:
7787 case MVE_VSRI:
7788 {
7789 switch (size)
7790 {
7791 case 1:
7792 func (stream, "8");
7793 break;
7794
7795 case 2: case 3:
7796 func (stream, "16");
7797 break;
7798
7799 case 4: case 5: case 6: case 7:
7800 func (stream, "32");
7801 break;
7802
7803 default:
7804 break;
7805 }
7806 }
7807 break;
7808
143275ea
AV		 7809 default:
7810 break;
7811 }
7812}
7813
ed63aa17
AV		 7814static void
7815print_mve_shift_n (struct disassemble_info *info, long given,
7816 enum mve_instructions matched_insn)
7817{
7818 void *stream = info->stream;
7819 fprintf_ftype func = info->fprintf_func;
7820
7821 int startAt0
7822 = matched_insn == MVE_VQSHL_T2
7823 || matched_insn == MVE_VQSHLU_T3
7824 || matched_insn == MVE_VSHL_T1
7825 || matched_insn == MVE_VSHLL_T1
7826 || matched_insn == MVE_VSLI;
7827
7828 unsigned imm6 = (given & 0x3f0000) >> 16;
7829
7830 if (matched_insn == MVE_VSHLL_T1)
7831 imm6 &= 0x1f;
7832
7833 unsigned shiftAmount = 0;
7834 if ((imm6 & 0x20) != 0)
7835 shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
7836 else if ((imm6 & 0x10) != 0)
7837 shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
7838 else if ((imm6 & 0x08) != 0)
7839 shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
7840 else
7841 print_mve_undefined (info, UNDEF_SIZE_0);
7842
7843 func (stream, "%u", shiftAmount);
7844}
7845
143275ea
AV		 7846static void
7847print_vec_condition (struct disassemble_info *info, long given,
7848 enum mve_instructions matched_insn)
7849{
7850 void *stream = info->stream;
7851 fprintf_ftype func = info->fprintf_func;
7852 long vec_cond = 0;
7853
7854 switch (matched_insn)
7855 {
7856 case MVE_VPT_FP_T1:
7857 case MVE_VCMP_FP_T1:
7858 vec_cond = (((given & 0x1000) >> 10)
7859 | ((given & 1) << 1)
7860 | ((given & 0x0080) >> 7));
7861 func (stream, "%s",vec_condnames[vec_cond]);
7862 break;
7863
7864 case MVE_VPT_FP_T2:
7865 case MVE_VCMP_FP_T2:
7866 vec_cond = (((given & 0x1000) >> 10)
7867 | ((given & 0x0020) >> 4)
7868 | ((given & 0x0080) >> 7));
7869 func (stream, "%s",vec_condnames[vec_cond]);
7870 break;
7871
7872 case MVE_VPT_VEC_T1:
7873 case MVE_VCMP_VEC_T1:
7874 vec_cond = (given & 0x0080) >> 7;
7875 func (stream, "%s",vec_condnames[vec_cond]);
7876 break;
7877
7878 case MVE_VPT_VEC_T2:
7879 case MVE_VCMP_VEC_T2:
7880 vec_cond = 2 | ((given & 0x0080) >> 7);
7881 func (stream, "%s",vec_condnames[vec_cond]);
7882 break;
7883
7884 case MVE_VPT_VEC_T3:
7885 case MVE_VCMP_VEC_T3:
7886 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
7887 func (stream, "%s",vec_condnames[vec_cond]);
7888 break;
7889
7890 case MVE_VPT_VEC_T4:
7891 case MVE_VCMP_VEC_T4:
7892 vec_cond = (given & 0x0080) >> 7;
7893 func (stream, "%s",vec_condnames[vec_cond]);
7894 break;
7895
7896 case MVE_VPT_VEC_T5:
7897 case MVE_VCMP_VEC_T5:
7898 vec_cond = 2 | ((given & 0x0080) >> 7);
7899 func (stream, "%s",vec_condnames[vec_cond]);
7900 break;
7901
7902 case MVE_VPT_VEC_T6:
7903 case MVE_VCMP_VEC_T6:
7904 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
7905 func (stream, "%s",vec_condnames[vec_cond]);
7906 break;
7907
7908 case MVE_NONE:
7909 case MVE_VPST:
7910 default:
7911 break;
7912 }
7913}
7914
7915#define W_BIT 21
7916#define I_BIT 22
7917#define U_BIT 23
7918#define P_BIT 24
7919
7920#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
7921#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
7922#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
7923#define PRE_BIT_SET (given & (1 << P_BIT))
7924
7925
8f06b2d8
PB		 7926/* Print one coprocessor instruction on INFO->STREAM.
7927 Return TRUE if the instuction matched, FALSE if this is not a
7928 recognised coprocessor instruction. */
7929
7930static bfd_boolean
33593eaf
MM		 7931print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
7932 bfd_vma pc,
7933 struct disassemble_info *info,
7934 long given,
7935 bfd_boolean thumb)
8f06b2d8 7936{
6b0dd094 7937 const struct sopcode32 *insn;
8f06b2d8
PB		 7938 void *stream = info->stream;
7939 fprintf_ftype func = info->fprintf_func;
7940 unsigned long mask;
2edcd244 7941 unsigned long value = 0;
c22aaad1 7942 int cond;
8afc7bea 7943 int cp_num;
823d2571
TG		 7944 struct arm_private_data *private_data = info->private_data;
7945 arm_feature_set allowed_arches = ARM_ARCH_NONE;
32c36c3c
AV		 7946 arm_feature_set arm_ext_v8_1m_main =
7947 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
823d2571 7948
5b616bef 7949 allowed_arches = private_data->features;
8f06b2d8 7950
33593eaf 7951 for (insn = opcodes; insn->assembler; insn++)
8f06b2d8 7952 {
ff4a8d2b
NC		 7953 unsigned long u_reg = 16;
7954 bfd_boolean is_unpredictable = FALSE;
05413229 7955 signed long value_in_comment = 0;
0313a2b8
NC		 7956 const char *c;
7957
823d2571 7958 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 7959 switch (insn->value)
7960 {
7961 case SENTINEL_IWMMXT_START:
7962 if (info->mach != bfd_mach_arm_XScale
7963 && info->mach != bfd_mach_arm_iWMMXt
7964 && info->mach != bfd_mach_arm_iWMMXt2)
7965 do
7966 insn++;
823d2571
TG		 7967 while ((! ARM_FEATURE_ZERO (insn->arch))
7968 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 7969 continue;
7970
7971 case SENTINEL_IWMMXT_END:
7972 continue;
7973
7974 case SENTINEL_GENERIC_START:
5b616bef 7975 allowed_arches = private_data->features;
05413229
NC		 7976 continue;
7977
7978 default:
7979 abort ();
7980 }
8f06b2d8
PB		 7981
7982 mask = insn->mask;
7983 value = insn->value;
8afc7bea
RL		 7984 cp_num = (given >> 8) & 0xf;
7985
8f06b2d8
PB		 7986 if (thumb)
7987 {
7988 /* The high 4 bits are 0xe for Arm conditional instructions, and
7989 0xe for arm unconditional instructions. The rest of the
7990 encoding is the same. */
7991 mask |= 0xf0000000;
7992 value |= 0xe0000000;
c22aaad1
PB		 7993 if (ifthen_state)
7994 cond = IFTHEN_COND;
7995 else
e2efe87d 7996 cond = COND_UNCOND;
8f06b2d8
PB		 7997 }
7998 else
7999 {
8000 /* Only match unconditional instuctions against unconditional
8001 patterns. */
8002 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 8003 {
8004 mask |= 0xf0000000;
e2efe87d 8005 cond = COND_UNCOND;
c22aaad1
PB		 8006 }
8007 else
8008 {
8009 cond = (given >> 28) & 0xf;
8010 if (cond == 0xe)
e2efe87d 8011 cond = COND_UNCOND;
c22aaad1 8012 }
8f06b2d8 8013 }
823d2571 8014
6b0dd094
AV		 8015 if ((insn->isa == T32 && !thumb)
8016 || (insn->isa == ARM && thumb))
8017 continue;
8018
0313a2b8
NC		 8019 if ((given & mask) != value)
8020 continue;
8f06b2d8 8021
823d2571 8022 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 8023 continue;
8024
8afc7bea
RL		 8025 if (insn->value == 0xfe000010 /* mcr2 */
8026 || insn->value == 0xfe100010 /* mrc2 */
8027 || insn->value == 0xfc100000 /* ldc2 */
8028 || insn->value == 0xfc000000) /* stc2 */
8029 {
b0c11777 8030 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 8031 is_unpredictable = TRUE;
f08d8ce3
AV		 8032
8033 /* Armv8.1-M Mainline FP & MVE instructions. */
8034 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8035 && !ARM_CPU_IS_ANY (allowed_arches)
8036 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8037 continue;
8038
8afc7bea
RL		 8039 }
8040 else if (insn->value == 0x0e000000 /* cdp */
8041 || insn->value == 0xfe000000 /* cdp2 */
8042 || insn->value == 0x0e000010 /* mcr */
8043 || insn->value == 0x0e100010 /* mrc */
8044 || insn->value == 0x0c100000 /* ldc */
8045 || insn->value == 0x0c000000) /* stc */
8046 {
8047 /* Floating-point instructions. */
b0c11777 8048 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 8049 continue;
32c36c3c
AV		 8050
8051 /* Armv8.1-M Mainline FP & MVE instructions. */
8052 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8053 && !ARM_CPU_IS_ANY (allowed_arches)
8054 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8055 continue;
8afc7bea 8056 }
aef6d006
AV		 8057 else if ((insn->value == 0xec100f80 /* vldr (system register) */
8058 || insn->value == 0xec000f80) /* vstr (system register) */
8059 && arm_decode_field (given, 24, 24) == 0
8060 && arm_decode_field (given, 21, 21) == 0)
8061 /* If the P and W bits are both 0 then these encodings match the MVE
8062 VLDR and VSTR instructions, these are in a different table, so we
8063 don't let it match here. */
8064 continue;
8065
0313a2b8
NC		 8066 for (c = insn->assembler; *c; c++)
8067 {
8068 if (*c == '%')
8f06b2d8 8069 {
32c36c3c
AV		 8070 const char mod = *++c;
8071 switch (mod)
8f06b2d8 8072 {
0313a2b8
NC		 8073 case '%':
8074 func (stream, "%%");
8075 break;
8076
8077 case 'A':
32c36c3c 8078 case 'K':
05413229 8079 {
79862e45 8080 int rn = (given >> 16) & 0xf;
b0c11777 8081 bfd_vma offset = given & 0xff;
0313a2b8 8082
32c36c3c
AV		 8083 if (mod == 'K')
8084 offset = given & 0x7f;
8085
05413229 8086 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 8087
79862e45
DJ		 8088 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
8089 {
8090 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 8091 if (cp_num == 9)
8092 /* vldr.16/vstr.16 will shift the address
8093 left by 1 bit only. */
8094 offset = offset * 2;
8095 else
8096 offset = offset * 4;
8097
79862e45
DJ		 8098 if (NEGATIVE_BIT_SET)
8099 offset = - offset;
8100 if (rn != 15)
8101 value_in_comment = offset;
8102 }
8103
c1e26897 8104 if (PRE_BIT_SET)
05413229
NC		 8105 {
8106 if (offset)
fe56b6ce 8107 func (stream, ", #%d]%s",
d908c8af 8108 (int) offset,
c1e26897 8109 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 8110 else if (NEGATIVE_BIT_SET)
8111 func (stream, ", #-0]");
05413229
NC		 8112 else
8113 func (stream, "]");
8114 }
8115 else
8116 {
0313a2b8 8117 func (stream, "]");
8f06b2d8 8118
c1e26897 8119 if (WRITEBACK_BIT_SET)
05413229
NC		 8120 {
8121 if (offset)
d908c8af 8122 func (stream, ", #%d", (int) offset);
26d97720
NS		 8123 else if (NEGATIVE_BIT_SET)
8124 func (stream, ", #-0");
05413229
NC		 8125 }
8126 else
fe56b6ce 8127 {
26d97720
NS		 8128 func (stream, ", {%s%d}",
8129 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 8130 (int) offset);
fe56b6ce
NC		 8131 value_in_comment = offset;
8132 }
05413229 8133 }
79862e45
DJ		 8134 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
8135 {
8136 func (stream, "\t; ");
6844b2c2
MGD		 8137 /* For unaligned PCs, apply off-by-alignment
8138 correction. */
43e65147 8139 info->print_address_func (offset + pc
6844b2c2
MGD		 8140 + info->bytes_per_chunk * 2
8141 - (pc & 3),
dffaa15c 8142 info);
79862e45 8143 }
05413229 8144 }
0313a2b8 8145 break;
8f06b2d8 8146
0313a2b8
NC		 8147 case 'B':
8148 {
8149 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
8150 int offset = (given >> 1) & 0x3f;
8151
8152 if (offset == 1)
8153 func (stream, "{d%d}", regno);
8154 else if (regno + offset > 32)
8155 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
8156 else
8157 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
8158 }
8159 break;
8f06b2d8 8160
efd6b359
AV		 8161 case 'C':
8162 {
8163 bfd_boolean single = ((given >> 8) & 1) == 0;
8164 char reg_prefix = single ? 's' : 'd';
8165 int Dreg = (given >> 22) & 0x1;
8166 int Vdreg = (given >> 12) & 0xf;
8167 int reg = single ? ((Vdreg << 1) | Dreg)
8168 : ((Dreg << 4) | Vdreg);
8169 int num = (given >> (single ? 0 : 1)) & 0x7f;
8170 int maxreg = single ? 31 : 15;
8171 int topreg = reg + num - 1;
8172
8173 if (!num)
8174 func (stream, "{VPR}");
8175 else if (num == 1)
8176 func (stream, "{%c%d, VPR}", reg_prefix, reg);
8177 else if (topreg > maxreg)
8178 func (stream, "{%c%d-<overflow reg d%d, VPR}",
8179 reg_prefix, reg, single ? topreg >> 1 : topreg);
8180 else
8181 func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
8182 reg_prefix, topreg);
8183 }
8184 break;
8185
e2efe87d
MGD		 8186 case 'u':
8187 if (cond != COND_UNCOND)
8188 is_unpredictable = TRUE;
8189
8190 /* Fall through. */
0313a2b8 8191 case 'c':
b0c11777
RL		 8192 if (cond != COND_UNCOND && cp_num == 9)
8193 is_unpredictable = TRUE;
8194
aab2c27d
MM		 8195 /* Fall through. */
8196 case 'b':
0313a2b8
NC		 8197 func (stream, "%s", arm_conditional[cond]);
8198 break;
8f06b2d8 8199
0313a2b8
NC		 8200 case 'I':
8201 /* Print a Cirrus/DSP shift immediate. */
8202 /* Immediates are 7bit signed ints with bits 0..3 in
8203 bits 0..3 of opcode and bits 4..6 in bits 5..7
8204 of opcode. */
8205 {
8206 int imm;
8f06b2d8 8207
0313a2b8 8208 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 8209
0313a2b8
NC		 8210 /* Is ``imm'' a negative number? */
8211 if (imm & 0x40)
24b4cf66 8212 imm -= 0x80;
8f06b2d8 8213
0313a2b8
NC		 8214 func (stream, "%d", imm);
8215 }
8216
8217 break;
8f06b2d8 8218
32c36c3c
AV		 8219 case 'J':
8220 {
73cd51e5
AV		 8221 unsigned long regno
8222 = arm_decode_field_multiple (given, 13, 15, 22, 22);
32c36c3c
AV		 8223
8224 switch (regno)
8225 {
8226 case 0x1:
8227 func (stream, "FPSCR");
8228 break;
8229 case 0x2:
8230 func (stream, "FPSCR_nzcvqc");
8231 break;
8232 case 0xc:
8233 func (stream, "VPR");
8234 break;
8235 case 0xd:
8236 func (stream, "P0");
8237 break;
8238 case 0xe:
8239 func (stream, "FPCXTNS");
8240 break;
8241 case 0xf:
8242 func (stream, "FPCXTS");
8243 break;
8244 default:
73cd51e5 8245 func (stream, "<invalid reg %lu>", regno);
32c36c3c
AV		 8246 break;
8247 }
8248 }
8249 break;
8250
0313a2b8
NC		 8251 case 'F':
8252 switch (given & 0x00408000)
8253 {
8254 case 0:
8255 func (stream, "4");
8256 break;
8257 case 0x8000:
8258 func (stream, "1");
8259 break;
8260 case 0x00400000:
8261 func (stream, "2");
8f06b2d8 8262 break;
0313a2b8
NC		 8263 default:
8264 func (stream, "3");
8265 }
8266 break;
8f06b2d8 8267
0313a2b8
NC		 8268 case 'P':
8269 switch (given & 0x00080080)
8270 {
8271 case 0:
8272 func (stream, "s");
8273 break;
8274 case 0x80:
8275 func (stream, "d");
8276 break;
8277 case 0x00080000:
8278 func (stream, "e");
8279 break;
8280 default:
8281 func (stream, _("<illegal precision>"));
8f06b2d8 8282 break;
0313a2b8
NC		 8283 }
8284 break;
8f06b2d8 8285
0313a2b8
NC		 8286 case 'Q':
8287 switch (given & 0x00408000)
8288 {
8289 case 0:
8290 func (stream, "s");
8f06b2d8 8291 break;
0313a2b8
NC		 8292 case 0x8000:
8293 func (stream, "d");
8f06b2d8 8294 break;
0313a2b8
NC		 8295 case 0x00400000:
8296 func (stream, "e");
8297 break;
8298 default:
8299 func (stream, "p");
8f06b2d8 8300 break;
0313a2b8
NC		 8301 }
8302 break;
8f06b2d8 8303
0313a2b8
NC		 8304 case 'R':
8305 switch (given & 0x60)
8306 {
8307 case 0:
8308 break;
8309 case 0x20:
8310 func (stream, "p");
8311 break;
8312 case 0x40:
8313 func (stream, "m");
8314 break;
8315 default:
8316 func (stream, "z");
8317 break;
8318 }
8319 break;
16980d0b 8320
0313a2b8
NC		 8321 case '0': case '1': case '2': case '3': case '4':
8322 case '5': case '6': case '7': case '8': case '9':
8323 {
8324 int width;
8f06b2d8 8325
0313a2b8 8326 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 8327
0313a2b8
NC		 8328 switch (*c)
8329 {
ff4a8d2b
NC		 8330 case 'R':
8331 if (value == 15)
8332 is_unpredictable = TRUE;
8333 /* Fall through. */
0313a2b8 8334 case 'r':
ff4a8d2b
NC		 8335 if (c[1] == 'u')
8336 {
8337 /* Eat the 'u' character. */
8338 ++ c;
8339
8340 if (u_reg == value)
8341 is_unpredictable = TRUE;
8342 u_reg = value;
8343 }
0313a2b8
NC		 8344 func (stream, "%s", arm_regnames[value]);
8345 break;
c28eeff2
SN		 8346 case 'V':
8347 if (given & (1 << 6))
8348 goto Q;
8349 /* FALLTHROUGH */
0313a2b8
NC		 8350 case 'D':
8351 func (stream, "d%ld", value);
8352 break;
8353 case 'Q':
c28eeff2 8354 Q:
0313a2b8
NC		 8355 if (value & 1)
8356 func (stream, "<illegal reg q%ld.5>", value >> 1);
8357 else
8358 func (stream, "q%ld", value >> 1);
8359 break;
8360 case 'd':
8361 func (stream, "%ld", value);
05413229 8362 value_in_comment = value;
0313a2b8 8363 break;
6f1c2142
AM		 8364 case 'E':
8365 {
8366 /* Converts immediate 8 bit back to float value. */
8367 unsigned floatVal = (value & 0x80) << 24
8368 | (value & 0x3F) << 19
8369 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
8370
8371 /* Quarter float have a maximum value of 31.0.
8372 Get floating point value multiplied by 1e7.
8373 The maximum value stays in limit of a 32-bit int. */
8374 unsigned decVal =
8375 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
8376 (16 + (value & 0xF));
8377
8378 if (!(decVal % 1000000))
8379 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
8380 floatVal, value & 0x80 ? '-' : ' ',
8381 decVal / 10000000,
8382 decVal % 10000000 / 1000000);
8383 else if (!(decVal % 10000))
8384 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
8385 floatVal, value & 0x80 ? '-' : ' ',
8386 decVal / 10000000,
8387 decVal % 10000000 / 10000);
8388 else
8389 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
8390 floatVal, value & 0x80 ? '-' : ' ',
8391 decVal / 10000000, decVal % 10000000);
8392 break;
8393 }
0313a2b8
NC		 8394 case 'k':
8395 {
8396 int from = (given & (1 << 7)) ? 32 : 16;
8397 func (stream, "%ld", from - value);
8398 }
8399 break;
8f06b2d8 8400
0313a2b8
NC		 8401 case 'f':
8402 if (value > 7)
8403 func (stream, "#%s", arm_fp_const[value & 7]);
8404 else
8405 func (stream, "f%ld", value);
8406 break;
4146fd53 8407
0313a2b8
NC		 8408 case 'w':
8409 if (width == 2)
8410 func (stream, "%s", iwmmxt_wwnames[value]);
8411 else
8412 func (stream, "%s", iwmmxt_wwssnames[value]);
8413 break;
4146fd53 8414
0313a2b8
NC		 8415 case 'g':
8416 func (stream, "%s", iwmmxt_regnames[value]);
8417 break;
8418 case 'G':
8419 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 8420 break;
8f06b2d8 8421
0313a2b8 8422 case 'x':
d1aaab3c 8423 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 8424 break;
8f06b2d8 8425
33399f07
MGD		 8426 case 'c':
8427 switch (value)
8428 {
8429 case 0:
8430 func (stream, "eq");
8431 break;
8432
8433 case 1:
8434 func (stream, "vs");
8435 break;
8436
8437 case 2:
8438 func (stream, "ge");
8439 break;
8440
8441 case 3:
8442 func (stream, "gt");
8443 break;
8444
8445 default:
8446 func (stream, "??");
8447 break;
8448 }
8449 break;
8450
0313a2b8
NC		 8451 case '`':
8452 c++;
8453 if (value == 0)
8454 func (stream, "%c", *c);
8455 break;
8456 case '\'':
8457 c++;
8458 if (value == ((1ul << width) - 1))
8459 func (stream, "%c", *c);
8460 break;
8461 case '?':
fe56b6ce 8462 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 8463 c += 1 << width;
8464 break;
8465 default:
8466 abort ();
8467 }
dffaa15c
AM		 8468 }
8469 break;
0313a2b8 8470
dffaa15c
AM		 8471 case 'y':
8472 case 'z':
8473 {
8474 int single = *c++ == 'y';
8475 int regno;
8f06b2d8 8476
dffaa15c
AM		 8477 switch (*c)
8478 {
8479 case '4': /* Sm pair */
8480 case '0': /* Sm, Dm */
8481 regno = given & 0x0000000f;
8482 if (single)
8483 {
8484 regno <<= 1;
8485 regno += (given >> 5) & 1;
8486 }
8487 else
8488 regno += ((given >> 5) & 1) << 4;
8489 break;
8f06b2d8 8490
dffaa15c
AM		 8491 case '1': /* Sd, Dd */
8492 regno = (given >> 12) & 0x0000000f;
8493 if (single)
8494 {
8495 regno <<= 1;
8496 regno += (given >> 22) & 1;
8497 }
8498 else
8499 regno += ((given >> 22) & 1) << 4;
8500 break;
7df76b80 8501
dffaa15c
AM		 8502 case '2': /* Sn, Dn */
8503 regno = (given >> 16) & 0x0000000f;
8504 if (single)
8505 {
8506 regno <<= 1;
8507 regno += (given >> 7) & 1;
8508 }
8509 else
8510 regno += ((given >> 7) & 1) << 4;
8511 break;
a7f8487e 8512
dffaa15c
AM		 8513 case '3': /* List */
8514 func (stream, "{");
8515 regno = (given >> 12) & 0x0000000f;
8516 if (single)
8517 {
8518 regno <<= 1;
8519 regno += (given >> 22) & 1;
8520 }
8521 else
8522 regno += ((given >> 22) & 1) << 4;
8523 break;
a7f8487e 8524
dffaa15c
AM		 8525 default:
8526 abort ();
8527 }
0313a2b8 8528
dffaa15c 8529 func (stream, "%c%d", single ? 's' : 'd', regno);
a7f8487e 8530
dffaa15c
AM		 8531 if (*c == '3')
8532 {
8533 int count = given & 0xff;
b34976b6 8534
dffaa15c
AM		 8535 if (single == 0)
8536 count >>= 1;
0313a2b8 8537
dffaa15c
AM		 8538 if (--count)
8539 {
8540 func (stream, "-%c%d",
8541 single ? 's' : 'd',
8542 regno + count);
8543 }
0313a2b8 8544
dffaa15c 8545 func (stream, "}");
0313a2b8 8546 }
dffaa15c
AM		 8547 else if (*c == '4')
8548 func (stream, ", %c%d", single ? 's' : 'd',
8549 regno + 1);
8550 }
8551 break;
b34976b6 8552
dffaa15c
AM		 8553 case 'L':
8554 switch (given & 0x00400100)
0313a2b8 8555 {
dffaa15c
AM		 8556 case 0x00000000: func (stream, "b"); break;
8557 case 0x00400000: func (stream, "h"); break;
8558 case 0x00000100: func (stream, "w"); break;
8559 case 0x00400100: func (stream, "d"); break;
8560 default:
8561 break;
0313a2b8 8562 }
dffaa15c 8563 break;
2d447fca 8564
dffaa15c
AM		 8565 case 'Z':
8566 {
8567 /* given (20, 23) | given (0, 3) */
8568 value = ((given >> 16) & 0xf0) | (given & 0xf);
8569 func (stream, "%d", (int) value);
8570 }
8571 break;
0313a2b8 8572
dffaa15c
AM		 8573 case 'l':
8574 /* This is like the 'A' operator, except that if
8575 the width field "M" is zero, then the offset is
8576 *not* multiplied by four. */
8577 {
8578 int offset = given & 0xff;
8579 int multiplier = (given & 0x00000100) ? 4 : 1;
0313a2b8 8580
dffaa15c 8581 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
05413229 8582
dffaa15c
AM		 8583 if (multiplier > 1)
8584 {
8585 value_in_comment = offset * multiplier;
8586 if (NEGATIVE_BIT_SET)
8587 value_in_comment = - value_in_comment;
8588 }
0313a2b8 8589
dffaa15c
AM		 8590 if (offset)
8591 {
8592 if (PRE_BIT_SET)
8593 func (stream, ", #%s%d]%s",
8594 NEGATIVE_BIT_SET ? "-" : "",
8595 offset * multiplier,
8596 WRITEBACK_BIT_SET ? "!" : "");
8597 else
8598 func (stream, "], #%s%d",
8599 NEGATIVE_BIT_SET ? "-" : "",
8600 offset * multiplier);
8601 }
8602 else
8603 func (stream, "]");
8604 }
8605 break;
2d447fca 8606
dffaa15c
AM		 8607 case 'r':
8608 {
8609 int imm4 = (given >> 4) & 0xf;
8610 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
8611 int ubit = ! NEGATIVE_BIT_SET;
8612 const char *rm = arm_regnames [given & 0xf];
8613 const char *rn = arm_regnames [(given >> 16) & 0xf];
0313a2b8 8614
dffaa15c
AM		 8615 switch (puw_bits)
8616 {
8617 case 1:
8618 case 3:
8619 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
8620 if (imm4)
8621 func (stream, ", lsl #%d", imm4);
8622 break;
0313a2b8 8623
dffaa15c
AM		 8624 case 4:
8625 case 5:
8626 case 6:
8627 case 7:
8628 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
8629 if (imm4 > 0)
8630 func (stream, ", lsl #%d", imm4);
8631 func (stream, "]");
8632 if (puw_bits == 5 || puw_bits == 7)
8633 func (stream, "!");
8634 break;
2d447fca 8635
dffaa15c
AM		 8636 default:
8637 func (stream, "INVALID");
8638 }
8639 }
8640 break;
0313a2b8 8641
dffaa15c
AM		 8642 case 'i':
8643 {
8644 long imm5;
8645 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
8646 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
0313a2b8 8647 }
dffaa15c
AM		 8648 break;
8649
8650 default:
8651 abort ();
252b5132 8652 }
252b5132 8653 }
0313a2b8
NC		 8654 else
8655 func (stream, "%c", *c);
252b5132 8656 }
05413229
NC		 8657
8658 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 8659 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 8660
ff4a8d2b
NC		 8661 if (is_unpredictable)
8662 func (stream, UNPREDICTABLE_INSTRUCTION);
8663
0313a2b8 8664 return TRUE;
252b5132 8665 }
8f06b2d8 8666 return FALSE;
252b5132
RH		 8667}
8668
33593eaf
MM		 8669static bfd_boolean
8670print_insn_coprocessor (bfd_vma pc,
8671 struct disassemble_info *info,
8672 long given,
8673 bfd_boolean thumb)
8674{
8675 return print_insn_coprocessor_1 (coprocessor_opcodes,
8676 pc, info, given, thumb);
8677}
8678
8679static bfd_boolean
8680print_insn_generic_coprocessor (bfd_vma pc,
8681 struct disassemble_info *info,
8682 long given,
8683 bfd_boolean thumb)
8684{
8685 return print_insn_coprocessor_1 (generic_coprocessor_opcodes,
8686 pc, info, given, thumb);
8687}
8688
05413229
NC		 8689/* Decodes and prints ARM addressing modes. Returns the offset
8690 used in the address, if any, if it is worthwhile printing the
8691 offset as a hexadecimal value in a comment at the end of the
8692 line of disassembly. */
8693
8694static signed long
62b3e311
PB		 8695print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
8696{
8697 void *stream = info->stream;
8698 fprintf_ftype func = info->fprintf_func;
f8b960bc 8699 bfd_vma offset = 0;
62b3e311
PB		 8700
8701 if (((given & 0x000f0000) == 0x000f0000)
8702 && ((given & 0x02000000) == 0))
8703 {
05413229 8704 offset = given & 0xfff;
62b3e311
PB		 8705
8706 func (stream, "[pc");
8707
c1e26897 8708 if (PRE_BIT_SET)
62b3e311 8709 {
26d97720
NS		 8710 /* Pre-indexed. Elide offset of positive zero when
8711 non-writeback. */
8712 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 8713 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 8714
8715 if (NEGATIVE_BIT_SET)
8716 offset = -offset;
62b3e311
PB		 8717
8718 offset += pc + 8;
8719
8720 /* Cope with the possibility of write-back
8721 being used. Probably a very dangerous thing
8722 for the programmer to do, but who are we to
8723 argue ? */
26d97720 8724 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 8725 }
c1e26897 8726 else /* Post indexed. */
62b3e311 8727 {
d908c8af 8728 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 8729
c1e26897 8730 /* Ie ignore the offset. */
62b3e311
PB		 8731 offset = pc + 8;
8732 }
8733
8734 func (stream, "\t; ");
8735 info->print_address_func (offset, info);
05413229 8736 offset = 0;
62b3e311
PB		 8737 }
8738 else
8739 {
8740 func (stream, "[%s",
8741 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 8742
8743 if (PRE_BIT_SET)
62b3e311
PB		 8744 {
8745 if ((given & 0x02000000) == 0)
8746 {
26d97720 8747 /* Elide offset of positive zero when non-writeback. */
05413229 8748 offset = given & 0xfff;
26d97720 8749 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 8750 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 8751 }
8752 else
8753 {
26d97720 8754 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 8755 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 8756 }
8757
8758 func (stream, "]%s",
c1e26897 8759 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 8760 }
8761 else
8762 {
8763 if ((given & 0x02000000) == 0)
8764 {
26d97720 8765 /* Always show offset. */
05413229 8766 offset = given & 0xfff;
26d97720 8767 func (stream, "], #%s%d",
d908c8af 8768 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 8769 }
8770 else
8771 {
8772 func (stream, "], %s",
c1e26897 8773 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 8774 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 8775 }
8776 }
84919466
MR		 8777 if (NEGATIVE_BIT_SET)
8778 offset = -offset;
62b3e311 8779 }
05413229
NC		 8780
8781 return (signed long) offset;
62b3e311
PB		 8782}
8783
16980d0b
JB		 8784/* Print one neon instruction on INFO->STREAM.
8785 Return TRUE if the instuction matched, FALSE if this is not a
8786 recognised neon instruction. */
8787
8788static bfd_boolean
8789print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
8790{
8791 const struct opcode32 *insn;
8792 void *stream = info->stream;
8793 fprintf_ftype func = info->fprintf_func;
8794
8795 if (thumb)
8796 {
8797 if ((given & 0xef000000) == 0xef000000)
8798 {
0313a2b8 8799 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 8800 unsigned long bit28 = given & (1 << 28);
8801
8802 given &= 0x00ffffff;
8803 if (bit28)
8804 given |= 0xf3000000;
8805 else
8806 given |= 0xf2000000;
8807 }
8808 else if ((given & 0xff000000) == 0xf9000000)
8809 given ^= 0xf9000000 ^ 0xf4000000;
aab2c27d
MM		 8810 /* BFloat16 neon instructions without special top byte handling. */
8811 else if ((given & 0xff000000) == 0xfe000000
8812 || (given & 0xff000000) == 0xfc000000)
8813 ;
9743db03
AV		 8814 /* vdup is also a valid neon instruction. */
8815 else if ((given & 0xff910f5f) != 0xee800b10)
16980d0b
JB		 8816 return FALSE;
8817 }
43e65147 8818
16980d0b
JB		 8819 for (insn = neon_opcodes; insn->assembler; insn++)
8820 {
8821 if ((given & insn->mask) == insn->value)
8822 {
05413229 8823 signed long value_in_comment = 0;
e2efe87d 8824 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 8825 const char *c;
8826
8827 for (c = insn->assembler; *c; c++)
8828 {
8829 if (*c == '%')
8830 {
8831 switch (*++c)
8832 {
8833 case '%':
8834 func (stream, "%%");
8835 break;
8836
e2efe87d
MGD		 8837 case 'u':
8838 if (thumb && ifthen_state)
8839 is_unpredictable = TRUE;
8840
8841 /* Fall through. */
c22aaad1
PB		 8842 case 'c':
8843 if (thumb && ifthen_state)
8844 func (stream, "%s", arm_conditional[IFTHEN_COND]);
8845 break;
8846
16980d0b
JB		 8847 case 'A':
8848 {
43e65147 8849 static const unsigned char enc[16] =
16980d0b
JB		 8850 {
8851 0x4, 0x14, /* st4 0,1 */
8852 0x4, /* st1 2 */
8853 0x4, /* st2 3 */
8854 0x3, /* st3 4 */
8855 0x13, /* st3 5 */
8856 0x3, /* st1 6 */
8857 0x1, /* st1 7 */
8858 0x2, /* st2 8 */
8859 0x12, /* st2 9 */
8860 0x2, /* st1 10 */
8861 0, 0, 0, 0, 0
8862 };
8863 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8864 int rn = ((given >> 16) & 0xf);
8865 int rm = ((given >> 0) & 0xf);
8866 int align = ((given >> 4) & 0x3);
8867 int type = ((given >> 8) & 0xf);
8868 int n = enc[type] & 0xf;
8869 int stride = (enc[type] >> 4) + 1;
8870 int ix;
43e65147 8871
16980d0b
JB		 8872 func (stream, "{");
8873 if (stride > 1)
8874 for (ix = 0; ix != n; ix++)
8875 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
8876 else if (n == 1)
8877 func (stream, "d%d", rd);
8878 else
8879 func (stream, "d%d-d%d", rd, rd + n - 1);
8880 func (stream, "}, [%s", arm_regnames[rn]);
8881 if (align)
8e560766 8882 func (stream, " :%d", 32 << align);
16980d0b
JB		 8883 func (stream, "]");
8884 if (rm == 0xd)
8885 func (stream, "!");
8886 else if (rm != 0xf)
8887 func (stream, ", %s", arm_regnames[rm]);
8888 }
8889 break;
43e65147 8890
16980d0b
JB		 8891 case 'B':
8892 {
8893 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8894 int rn = ((given >> 16) & 0xf);
8895 int rm = ((given >> 0) & 0xf);
8896 int idx_align = ((given >> 4) & 0xf);
8897 int align = 0;
8898 int size = ((given >> 10) & 0x3);
8899 int idx = idx_align >> (size + 1);
8900 int length = ((given >> 8) & 3) + 1;
8901 int stride = 1;
8902 int i;
8903
8904 if (length > 1 && size > 0)
8905 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 8906
16980d0b
JB		 8907 switch (length)
8908 {
8909 case 1:
8910 {
8911 int amask = (1 << size) - 1;
8912 if ((idx_align & (1 << size)) != 0)
8913 return FALSE;
8914 if (size > 0)
8915 {
8916 if ((idx_align & amask) == amask)
8917 align = 8 << size;
8918 else if ((idx_align & amask) != 0)
8919 return FALSE;
8920 }
8921 }
8922 break;
43e65147 8923
16980d0b
JB		 8924 case 2:
8925 if (size == 2 && (idx_align & 2) != 0)
8926 return FALSE;
8927 align = (idx_align & 1) ? 16 << size : 0;
8928 break;
43e65147 8929
16980d0b
JB		 8930 case 3:
8931 if ((size == 2 && (idx_align & 3) != 0)
8932 || (idx_align & 1) != 0)
8933 return FALSE;
8934 break;
43e65147 8935
16980d0b
JB		 8936 case 4:
8937 if (size == 2)
8938 {
8939 if ((idx_align & 3) == 3)
8940 return FALSE;
8941 align = (idx_align & 3) * 64;
8942 }
8943 else
8944 align = (idx_align & 1) ? 32 << size : 0;
8945 break;
43e65147 8946
16980d0b
JB		 8947 default:
8948 abort ();
8949 }
43e65147 8950
16980d0b
JB		 8951 func (stream, "{");
8952 for (i = 0; i < length; i++)
8953 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
8954 rd + i * stride, idx);
8955 func (stream, "}, [%s", arm_regnames[rn]);
8956 if (align)
8e560766 8957 func (stream, " :%d", align);
16980d0b
JB		 8958 func (stream, "]");
8959 if (rm == 0xd)
8960 func (stream, "!");
8961 else if (rm != 0xf)
8962 func (stream, ", %s", arm_regnames[rm]);
8963 }
8964 break;
43e65147 8965
16980d0b
JB		 8966 case 'C':
8967 {
8968 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8969 int rn = ((given >> 16) & 0xf);
8970 int rm = ((given >> 0) & 0xf);
8971 int align = ((given >> 4) & 0x1);
8972 int size = ((given >> 6) & 0x3);
8973 int type = ((given >> 8) & 0x3);
8974 int n = type + 1;
8975 int stride = ((given >> 5) & 0x1);
8976 int ix;
43e65147 8977
16980d0b
JB		 8978 if (stride && (n == 1))
8979 n++;
8980 else
8981 stride++;
43e65147 8982
16980d0b
JB		 8983 func (stream, "{");
8984 if (stride > 1)
8985 for (ix = 0; ix != n; ix++)
8986 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
8987 else if (n == 1)
8988 func (stream, "d%d[]", rd);
8989 else
8990 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
8991 func (stream, "}, [%s", arm_regnames[rn]);
8992 if (align)
8993 {
91d6fa6a 8994 align = (8 * (type + 1)) << size;
16980d0b
JB		 8995 if (type == 3)
8996 align = (size > 1) ? align >> 1 : align;
8997 if (type == 2 || (type == 0 && !size))
8e560766 8998 func (stream, " :<bad align %d>", align);
16980d0b 8999 else
8e560766 9000 func (stream, " :%d", align);
16980d0b
JB		 9001 }
9002 func (stream, "]");
9003 if (rm == 0xd)
9004 func (stream, "!");
9005 else if (rm != 0xf)
9006 func (stream, ", %s", arm_regnames[rm]);
9007 }
9008 break;
43e65147 9009
16980d0b
JB		 9010 case 'D':
9011 {
9012 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
9013 int size = (given >> 20) & 3;
9014 int reg = raw_reg & ((4 << size) - 1);
9015 int ix = raw_reg >> size >> 2;
43e65147 9016
16980d0b
JB		 9017 func (stream, "d%d[%d]", reg, ix);
9018 }
9019 break;
43e65147 9020
16980d0b 9021 case 'E':
fe56b6ce 9022 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 9023 {
9024 int bits = 0;
9025 int cmode = (given >> 8) & 0xf;
9026 int op = (given >> 5) & 0x1;
9027 unsigned long value = 0, hival = 0;
9028 unsigned shift;
9029 int size = 0;
0dbde4cf 9030 int isfloat = 0;
43e65147 9031
16980d0b
JB		 9032 bits |= ((given >> 24) & 1) << 7;
9033 bits |= ((given >> 16) & 7) << 4;
9034 bits |= ((given >> 0) & 15) << 0;
43e65147 9035
16980d0b
JB		 9036 if (cmode < 8)
9037 {
9038 shift = (cmode >> 1) & 3;
fe56b6ce 9039 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 9040 size = 32;
9041 }
9042 else if (cmode < 12)
9043 {
9044 shift = (cmode >> 1) & 1;
fe56b6ce 9045 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 9046 size = 16;
9047 }
9048 else if (cmode < 14)
9049 {
9050 shift = (cmode & 1) + 1;
fe56b6ce 9051 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 9052 value |= (1ul << (8 * shift)) - 1;
9053 size = 32;
9054 }
9055 else if (cmode == 14)
9056 {
9057 if (op)
9058 {
fe56b6ce 9059 /* Bit replication into bytes. */
16980d0b
JB		 9060 int ix;
9061 unsigned long mask;
43e65147 9062
16980d0b
JB		 9063 value = 0;
9064 hival = 0;
9065 for (ix = 7; ix >= 0; ix--)
9066 {
9067 mask = ((bits >> ix) & 1) ? 0xff : 0;
9068 if (ix <= 3)
9069 value = (value << 8) | mask;
9070 else
9071 hival = (hival << 8) | mask;
9072 }
9073 size = 64;
9074 }
9075 else
9076 {
fe56b6ce
NC		 9077 /* Byte replication. */
9078 value = (unsigned long) bits;
16980d0b
JB		 9079 size = 8;
9080 }
9081 }
9082 else if (!op)
9083 {
fe56b6ce 9084 /* Floating point encoding. */
16980d0b 9085 int tmp;
43e65147 9086
fe56b6ce
NC		 9087 value = (unsigned long) (bits & 0x7f) << 19;
9088 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 9089 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 9090 value |= (unsigned long) tmp << 24;
16980d0b 9091 size = 32;
0dbde4cf 9092 isfloat = 1;
16980d0b
JB		 9093 }
9094 else
9095 {
9096 func (stream, "<illegal constant %.8x:%x:%x>",
9097 bits, cmode, op);
9098 size = 32;
9099 break;
9100 }
9101 switch (size)
9102 {
9103 case 8:
9104 func (stream, "#%ld\t; 0x%.2lx", value, value);
9105 break;
43e65147 9106
16980d0b
JB		 9107 case 16:
9108 func (stream, "#%ld\t; 0x%.4lx", value, value);
9109 break;
9110
9111 case 32:
0dbde4cf
JB		 9112 if (isfloat)
9113 {
9114 unsigned char valbytes[4];
9115 double fvalue;
43e65147 9116
0dbde4cf
JB		 9117 /* Do this a byte at a time so we don't have to
9118 worry about the host's endianness. */
9119 valbytes[0] = value & 0xff;
9120 valbytes[1] = (value >> 8) & 0xff;
9121 valbytes[2] = (value >> 16) & 0xff;
9122 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 9123
9124 floatformat_to_double
c1e26897
NC		 9125 (& floatformat_ieee_single_little, valbytes,
9126 & fvalue);
43e65147 9127
0dbde4cf
JB		 9128 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
9129 value);
9130 }
9131 else
4e9d3b81 9132 func (stream, "#%ld\t; 0x%.8lx",
43e65147 9133 (long) (((value & 0x80000000L) != 0)
9d82ec38 9134 ? value | ~0xffffffffL : value),
c1e26897 9135 value);
16980d0b
JB		 9136 break;
9137
9138 case 64:
9139 func (stream, "#0x%.8lx%.8lx", hival, value);
9140 break;
43e65147 9141
16980d0b
JB		 9142 default:
9143 abort ();
9144 }
9145 }
9146 break;
43e65147 9147
16980d0b
JB		 9148 case 'F':
9149 {
9150 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
9151 int num = (given >> 8) & 0x3;
43e65147 9152
16980d0b
JB		 9153 if (!num)
9154 func (stream, "{d%d}", regno);
9155 else if (num + regno >= 32)
9156 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
9157 else
9158 func (stream, "{d%d-d%d}", regno, regno + num);
9159 }
9160 break;
7e8e6784 9161
16980d0b
JB		 9162
9163 case '0': case '1': case '2': case '3': case '4':
9164 case '5': case '6': case '7': case '8': case '9':
9165 {
9166 int width;
9167 unsigned long value;
9168
9169 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 9170
16980d0b
JB		 9171 switch (*c)
9172 {
9173 case 'r':
9174 func (stream, "%s", arm_regnames[value]);
9175 break;
9176 case 'd':
9177 func (stream, "%ld", value);
05413229 9178 value_in_comment = value;
16980d0b
JB		 9179 break;
9180 case 'e':
9181 func (stream, "%ld", (1ul << width) - value);
9182 break;
43e65147 9183
16980d0b
JB		 9184 case 'S':
9185 case 'T':
9186 case 'U':
05413229 9187 /* Various width encodings. */
16980d0b
JB		 9188 {
9189 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
9190 int limit;
9191 unsigned low, high;
9192
9193 c++;
9194 if (*c >= '0' && *c <= '9')
9195 limit = *c - '0';
9196 else if (*c >= 'a' && *c <= 'f')
9197 limit = *c - 'a' + 10;
9198 else
9199 abort ();
9200 low = limit >> 2;
9201 high = limit & 3;
9202
9203 if (value < low || value > high)
9204 func (stream, "<illegal width %d>", base << value);
9205 else
9206 func (stream, "%d", base << value);
9207 }
9208 break;
9209 case 'R':
9210 if (given & (1 << 6))
9211 goto Q;
9212 /* FALLTHROUGH */
9213 case 'D':
9214 func (stream, "d%ld", value);
9215 break;
9216 case 'Q':
9217 Q:
9218 if (value & 1)
9219 func (stream, "<illegal reg q%ld.5>", value >> 1);
9220 else
9221 func (stream, "q%ld", value >> 1);
9222 break;
43e65147 9223
16980d0b
JB		 9224 case '`':
9225 c++;
9226 if (value == 0)
9227 func (stream, "%c", *c);
9228 break;
9229 case '\'':
9230 c++;
9231 if (value == ((1ul << width) - 1))
9232 func (stream, "%c", *c);
9233 break;
9234 case '?':
fe56b6ce 9235 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 9236 c += 1 << width;
9237 break;
9238 default:
9239 abort ();
9240 }
16980d0b 9241 }
dffaa15c
AM		 9242 break;
9243
9244 default:
9245 abort ();
16980d0b
JB		 9246 }
9247 }
9248 else
9249 func (stream, "%c", *c);
9250 }
05413229
NC		 9251
9252 if (value_in_comment > 32 || value_in_comment < -16)
9253 func (stream, "\t; 0x%lx", value_in_comment);
9254
e2efe87d
MGD		 9255 if (is_unpredictable)
9256 func (stream, UNPREDICTABLE_INSTRUCTION);
9257
16980d0b
JB		 9258 return TRUE;
9259 }
9260 }
9261 return FALSE;
9262}
9263
73cd51e5
AV		 9264/* Print one mve instruction on INFO->STREAM.
9265 Return TRUE if the instuction matched, FALSE if this is not a
9266 recognised mve instruction. */
9267
9268static bfd_boolean
9269print_insn_mve (struct disassemble_info *info, long given)
9270{
9271 const struct mopcode32 *insn;
9272 void *stream = info->stream;
9273 fprintf_ftype func = info->fprintf_func;
9274
9275 for (insn = mve_opcodes; insn->assembler; insn++)
9276 {
9277 if (((given & insn->mask) == insn->value)
9278 && !is_mve_encoding_conflict (given, insn->mve_op))
9279 {
9280 signed long value_in_comment = 0;
9281 bfd_boolean is_unpredictable = FALSE;
9282 bfd_boolean is_undefined = FALSE;
9283 const char *c;
9284 enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
9285 enum mve_undefined undefined_cond = UNDEF_NONE;
9286
9287 /* Most vector mve instruction are illegal in a it block.
9288 There are a few exceptions; check for them. */
9289 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
9290 {
9291 is_unpredictable = TRUE;
9292 unpredictable_cond = UNPRED_IT_BLOCK;
9293 }
9294 else if (is_mve_unpredictable (given, insn->mve_op,
9295 &unpredictable_cond))
9296 is_unpredictable = TRUE;
9297
9298 if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
9299 is_undefined = TRUE;
9300
c4a23bf8
SP		 9301 /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV,
9302 i.e "VMOV Qd, Qm". */
9303 if ((insn->mve_op == MVE_VORR_REG)
9304 && (arm_decode_field (given, 1, 3)
9305 == arm_decode_field (given, 17, 19)))
9306 continue;
9307
73cd51e5
AV		 9308 for (c = insn->assembler; *c; c++)
9309 {
9310 if (*c == '%')
9311 {
9312 switch (*++c)
9313 {
9314 case '%':
9315 func (stream, "%%");
9316 break;
9317
ef1576a1
AV		 9318 case 'a':
9319 /* Don't print anything for '+' as it is implied. */
9320 if (arm_decode_field (given, 23, 23) == 0)
9321 func (stream, "-");
9322 break;
9323
143275ea
AV		 9324 case 'c':
9325 if (ifthen_state)
9326 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9327 break;
9328
aef6d006
AV		 9329 case 'd':
9330 print_mve_vld_str_addr (info, given, insn->mve_op);
9331 break;
9332
143275ea
AV		 9333 case 'i':
9334 {
9335 long mve_mask = mve_extract_pred_mask (given);
9336 func (stream, "%s", mve_predicatenames[mve_mask]);
9337 }
9338 break;
9339
23d00a41
SD		 9340 case 'j':
9341 {
9342 unsigned int imm5 = 0;
9343 imm5 |= arm_decode_field (given, 6, 7);
9344 imm5 |= (arm_decode_field (given, 12, 14) << 2);
9345 func (stream, "#%u", (imm5 == 0) ? 32 : imm5);
9346 }
9347 break;
9348
08132bdd
SP		 9349 case 'k':
9350 func (stream, "#%u",
9351 (arm_decode_field (given, 7, 7) == 0) ? 64 : 48);
9352 break;
9353
143275ea
AV		 9354 case 'n':
9355 print_vec_condition (info, given, insn->mve_op);
9356 break;
9357
ef1576a1
AV		 9358 case 'o':
9359 if (arm_decode_field (given, 0, 0) == 1)
9360 {
9361 unsigned long size
9362 = arm_decode_field (given, 4, 4)
9363 | (arm_decode_field (given, 6, 6) << 1);
9364
9365 func (stream, ", uxtw #%lu", size);
9366 }
9367 break;
9368
bf0b396d
AV		 9369 case 'm':
9370 print_mve_rounding_mode (info, given, insn->mve_op);
9371 break;
9372
9373 case 's':
9374 print_mve_vcvt_size (info, given, insn->mve_op);
9375 break;
9376
aef6d006
AV		 9377 case 'u':
9378 {
c507f10b
AV		 9379 unsigned long op1 = arm_decode_field (given, 21, 22);
9380
9381 if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
9382 {
9383 /* Check for signed. */
9384 if (arm_decode_field (given, 23, 23) == 0)
9385 {
9386 /* We don't print 's' for S32. */
9387 if ((arm_decode_field (given, 5, 6) == 0)
9388 && ((op1 == 0) || (op1 == 1)))
9389 ;
9390 else
9391 func (stream, "s");
9392 }
9393 else
9394 func (stream, "u");
9395 }
aef6d006 9396 else
c507f10b
AV		 9397 {
9398 if (arm_decode_field (given, 28, 28) == 0)
9399 func (stream, "s");
9400 else
9401 func (stream, "u");
9402 }
aef6d006 9403 }
ef1576a1 9404 break;
aef6d006 9405
143275ea
AV		 9406 case 'v':
9407 print_instruction_predicate (info);
9408 break;
9409
04d54ace
AV		 9410 case 'w':
9411 if (arm_decode_field (given, 21, 21) == 1)
9412 func (stream, "!");
9413 break;
9414
9415 case 'B':
9416 print_mve_register_blocks (info, given, insn->mve_op);
9417 break;
9418
c507f10b
AV		 9419 case 'E':
9420 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
9421
9422 print_simd_imm8 (info, given, 28, insn);
9423 break;
9424
9425 case 'N':
9426 print_mve_vmov_index (info, given);
9427 break;
9428
14925797
AV		 9429 case 'T':
9430 if (arm_decode_field (given, 12, 12) == 0)
9431 func (stream, "b");
9432 else
9433 func (stream, "t");
9434 break;
9435
d3b63143
AV		 9436 case 'X':
9437 if (arm_decode_field (given, 12, 12) == 1)
9438 func (stream, "x");
9439 break;
9440
143275ea
AV		 9441 case '0': case '1': case '2': case '3': case '4':
9442 case '5': case '6': case '7': case '8': case '9':
9443 {
9444 int width;
9445 unsigned long value;
9446
9447 c = arm_decode_bitfield (c, given, &value, &width);
9448
9449 switch (*c)
9450 {
9451 case 'Z':
9452 if (value == 13)
9453 is_unpredictable = TRUE;
9454 else if (value == 15)
9455 func (stream, "zr");
9456 else
9457 func (stream, "%s", arm_regnames[value]);
9458 break;
23d00a41 9459
e39c1607
SD		 9460 case 'c':
9461 func (stream, "%s", arm_conditional[value]);
9462 break;
9463
9464 case 'C':
9465 value ^= 1;
9466 func (stream, "%s", arm_conditional[value]);
9467 break;
9468
23d00a41
SD		 9469 case 'S':
9470 if (value == 13 || value == 15)
9471 is_unpredictable = TRUE;
9472 else
9473 func (stream, "%s", arm_regnames[value]);
9474 break;
9475
143275ea
AV		 9476 case 's':
9477 print_mve_size (info,
9478 value,
9479 insn->mve_op);
9480 break;
66dcaa5d
AV		 9481 case 'I':
9482 if (value == 1)
9483 func (stream, "i");
9484 break;
d3b63143
AV		 9485 case 'A':
9486 if (value == 1)
9487 func (stream, "a");
9488 break;
1c8f2df8
AV		 9489 case 'h':
9490 {
9491 unsigned int odd_reg = (value << 1) | 1;
9492 func (stream, "%s", arm_regnames[odd_reg]);
9493 }
9494 break;
ef1576a1
AV		 9495 case 'i':
9496 {
9497 unsigned long imm
9498 = arm_decode_field (given, 0, 6);
9499 unsigned long mod_imm = imm;
9500
9501 switch (insn->mve_op)
9502 {
9503 case MVE_VLDRW_GATHER_T5:
9504 case MVE_VSTRW_SCATTER_T5:
9505 mod_imm = mod_imm << 2;
9506 break;
9507 case MVE_VSTRD_SCATTER_T6:
9508 case MVE_VLDRD_GATHER_T6:
9509 mod_imm = mod_imm << 3;
9510 break;
9511
9512 default:
9513 break;
9514 }
9515
9516 func (stream, "%lu", mod_imm);
9517 }
9518 break;
bf0b396d
AV		 9519 case 'k':
9520 func (stream, "%lu", 64 - value);
9521 break;
1c8f2df8
AV		 9522 case 'l':
9523 {
9524 unsigned int even_reg = value << 1;
9525 func (stream, "%s", arm_regnames[even_reg]);
9526 }
9527 break;
9528 case 'u':
9529 switch (value)
9530 {
9531 case 0:
9532 func (stream, "1");
9533 break;
9534 case 1:
9535 func (stream, "2");
9536 break;
9537 case 2:
9538 func (stream, "4");
9539 break;
9540 case 3:
9541 func (stream, "8");
9542 break;
9543 default:
9544 break;
9545 }
9546 break;
897b9bbc
AV		 9547 case 'o':
9548 print_mve_rotate (info, value, width);
9549 break;
9743db03
AV		 9550 case 'r':
9551 func (stream, "%s", arm_regnames[value]);
9552 break;
04d54ace 9553 case 'd':
ed63aa17
AV		 9554 if (insn->mve_op == MVE_VQSHL_T2
9555 || insn->mve_op == MVE_VQSHLU_T3
9556 || insn->mve_op == MVE_VRSHR
9557 || insn->mve_op == MVE_VRSHRN
9558 || insn->mve_op == MVE_VSHL_T1
9559 || insn->mve_op == MVE_VSHLL_T1
9560 || insn->mve_op == MVE_VSHR
9561 || insn->mve_op == MVE_VSHRN
9562 || insn->mve_op == MVE_VSLI
9563 || insn->mve_op == MVE_VSRI)
9564 print_mve_shift_n (info, given, insn->mve_op);
9565 else if (insn->mve_op == MVE_VSHLL_T2)
9566 {
9567 switch (value)
9568 {
9569 case 0x00:
9570 func (stream, "8");
9571 break;
9572 case 0x01:
9573 func (stream, "16");
9574 break;
9575 case 0x10:
9576 print_mve_undefined (info, UNDEF_SIZE_0);
9577 break;
9578 default:
9579 assert (0);
9580 break;
9581 }
9582 }
9583 else
9584 {
9585 if (insn->mve_op == MVE_VSHLC && value == 0)
9586 value = 32;
9587 func (stream, "%ld", value);
9588 value_in_comment = value;
9589 }
04d54ace 9590 break;
c507f10b
AV		 9591 case 'F':
9592 func (stream, "s%ld", value);
9593 break;
143275ea
AV		 9594 case 'Q':
9595 if (value & 0x8)
9596 func (stream, "<illegal reg q%ld.5>", value);
9597 else
9598 func (stream, "q%ld", value);
9599 break;
c507f10b
AV		 9600 case 'x':
9601 func (stream, "0x%08lx", value);
9602 break;
143275ea
AV		 9603 default:
9604 abort ();
9605 }
9606 break;
9607 default:
9608 abort ();
9609 }
73cd51e5
AV		 9610 }
9611 }
9612 else
9613 func (stream, "%c", *c);
9614 }
9615
9616 if (value_in_comment > 32 || value_in_comment < -16)
9617 func (stream, "\t; 0x%lx", value_in_comment);
9618
9619 if (is_unpredictable)
9620 print_mve_unpredictable (info, unpredictable_cond);
9621
9622 if (is_undefined)
9623 print_mve_undefined (info, undefined_cond);
9624
143275ea
AV		 9625 if ((vpt_block_state.in_vpt_block == FALSE)
9626 && !ifthen_state
9627 && (is_vpt_instruction (given) == TRUE))
9628 mark_inside_vpt_block (given);
9629 else if (vpt_block_state.in_vpt_block == TRUE)
9630 update_vpt_block_state ();
9631
73cd51e5
AV		 9632 return TRUE;
9633 }
9634 }
9635 return FALSE;
9636}
9637
9638
90ec0d68
MGD		 9639/* Return the name of a v7A special register. */
9640
43e65147 9641static const char *
90ec0d68
MGD		 9642banked_regname (unsigned reg)
9643{
9644 switch (reg)
9645 {
9646 case 15: return "CPSR";
43e65147 9647 case 32: return "R8_usr";
90ec0d68
MGD		 9648 case 33: return "R9_usr";
9649 case 34: return "R10_usr";
9650 case 35: return "R11_usr";
9651 case 36: return "R12_usr";
9652 case 37: return "SP_usr";
9653 case 38: return "LR_usr";
43e65147 9654 case 40: return "R8_fiq";
90ec0d68
MGD		 9655 case 41: return "R9_fiq";
9656 case 42: return "R10_fiq";
9657 case 43: return "R11_fiq";
9658 case 44: return "R12_fiq";
9659 case 45: return "SP_fiq";
9660 case 46: return "LR_fiq";
9661 case 48: return "LR_irq";
9662 case 49: return "SP_irq";
9663 case 50: return "LR_svc";
9664 case 51: return "SP_svc";
9665 case 52: return "LR_abt";
9666 case 53: return "SP_abt";
9667 case 54: return "LR_und";
9668 case 55: return "SP_und";
9669 case 60: return "LR_mon";
9670 case 61: return "SP_mon";
9671 case 62: return "ELR_hyp";
9672 case 63: return "SP_hyp";
9673 case 79: return "SPSR";
9674 case 110: return "SPSR_fiq";
9675 case 112: return "SPSR_irq";
9676 case 114: return "SPSR_svc";
9677 case 116: return "SPSR_abt";
9678 case 118: return "SPSR_und";
9679 case 124: return "SPSR_mon";
9680 case 126: return "SPSR_hyp";
9681 default: return NULL;
9682 }
9683}
9684
e797f7e0
MGD		 9685/* Return the name of the DMB/DSB option. */
9686static const char *
9687data_barrier_option (unsigned option)
9688{
9689 switch (option & 0xf)
9690 {
9691 case 0xf: return "sy";
9692 case 0xe: return "st";
9693 case 0xd: return "ld";
9694 case 0xb: return "ish";
9695 case 0xa: return "ishst";
9696 case 0x9: return "ishld";
9697 case 0x7: return "un";
9698 case 0x6: return "unst";
9699 case 0x5: return "nshld";
9700 case 0x3: return "osh";
9701 case 0x2: return "oshst";
9702 case 0x1: return "oshld";
9703 default: return NULL;
9704 }
9705}
9706
4a5329c6
ZW		 9707/* Print one ARM instruction from PC on INFO->STREAM. */
9708
9709static void
9710print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 9711{
6b5d3a4d 9712 const struct opcode32 *insn;
6a51a8a8 9713 void *stream = info->stream;
6b5d3a4d 9714 fprintf_ftype func = info->fprintf_func;
b0e28b39 9715 struct arm_private_data *private_data = info->private_data;
252b5132 9716
16980d0b
JB		 9717 if (print_insn_coprocessor (pc, info, given, FALSE))
9718 return;
9719
9720 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 9721 return;
9722
33593eaf
MM		 9723 if (print_insn_generic_coprocessor (pc, info, given, FALSE))
9724 return;
9725
252b5132
RH		 9726 for (insn = arm_opcodes; insn->assembler; insn++)
9727 {
0313a2b8
NC		 9728 if ((given & insn->mask) != insn->value)
9729 continue;
823d2571
TG		 9730
9731 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 9732 continue;
9733
9734 /* Special case: an instruction with all bits set in the condition field
9735 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
9736 or by the catchall at the end of the table. */
9737 if ((given & 0xF0000000) != 0xF0000000
9738 || (insn->mask & 0xF0000000) == 0xF0000000
9739 || (insn->mask == 0 && insn->value == 0))
252b5132 9740 {
ff4a8d2b
NC		 9741 unsigned long u_reg = 16;
9742 unsigned long U_reg = 16;
ab8e2090 9743 bfd_boolean is_unpredictable = FALSE;
05413229 9744 signed long value_in_comment = 0;
6b5d3a4d 9745 const char *c;
b34976b6 9746
252b5132
RH		 9747 for (c = insn->assembler; *c; c++)
9748 {
9749 if (*c == '%')
9750 {
c1e26897
NC		 9751 bfd_boolean allow_unpredictable = FALSE;
9752
252b5132
RH		 9753 switch (*++c)
9754 {
9755 case '%':
9756 func (stream, "%%");
9757 break;
9758
9759 case 'a':
05413229 9760 value_in_comment = print_arm_address (pc, info, given);
62b3e311 9761 break;
252b5132 9762
62b3e311
PB		 9763 case 'P':
9764 /* Set P address bit and use normal address
9765 printing routine. */
c1e26897 9766 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 9767 break;
9768
c1e26897
NC		 9769 case 'S':
9770 allow_unpredictable = TRUE;
1a0670f3 9771 /* Fall through. */
252b5132
RH		 9772 case 's':
9773 if ((given & 0x004f0000) == 0x004f0000)
9774 {
58efb6c0 9775 /* PC relative with immediate offset. */
f8b960bc 9776 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 9777
aefd8a40
NC		 9778 if (PRE_BIT_SET)
9779 {
26d97720
NS		 9780 /* Elide positive zero offset. */
9781 if (offset || NEGATIVE_BIT_SET)
9782 func (stream, "[pc, #%s%d]\t; ",
d908c8af 9783 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 9784 else
26d97720
NS		 9785 func (stream, "[pc]\t; ");
9786 if (NEGATIVE_BIT_SET)
9787 offset = -offset;
aefd8a40
NC		 9788 info->print_address_func (offset + pc + 8, info);
9789 }
9790 else
9791 {
26d97720
NS		 9792 /* Always show the offset. */
9793 func (stream, "[pc], #%s%d",
d908c8af 9794 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 9795 if (! allow_unpredictable)
9796 is_unpredictable = TRUE;
aefd8a40 9797 }
252b5132
RH		 9798 }
9799 else
9800 {
fe56b6ce
NC		 9801 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
9802
b34976b6 9803 func (stream, "[%s",
252b5132 9804 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 9805
c1e26897 9806 if (PRE_BIT_SET)
252b5132 9807 {
c1e26897 9808 if (IMMEDIATE_BIT_SET)
252b5132 9809 {
26d97720
NS		 9810 /* Elide offset for non-writeback
9811 positive zero. */
9812 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
9813 || offset)
9814 func (stream, ", #%s%d",
9815 NEGATIVE_BIT_SET ? "-" : "", offset);
9816
9817 if (NEGATIVE_BIT_SET)
9818 offset = -offset;
945ee430 9819
fe56b6ce 9820 value_in_comment = offset;
252b5132 9821 }
945ee430 9822 else
ff4a8d2b
NC		 9823 {
9824 /* Register Offset or Register Pre-Indexed. */
9825 func (stream, ", %s%s",
9826 NEGATIVE_BIT_SET ? "-" : "",
9827 arm_regnames[given & 0xf]);
9828
9829 /* Writing back to the register that is the source/
9830 destination of the load/store is unpredictable. */
9831 if (! allow_unpredictable
9832 && WRITEBACK_BIT_SET
9833 && ((given & 0xf) == ((given >> 12) & 0xf)))
9834 is_unpredictable = TRUE;
9835 }
252b5132 9836
b34976b6 9837 func (stream, "]%s",
c1e26897 9838 WRITEBACK_BIT_SET ? "!" : "");
252b5132 9839 }
945ee430 9840 else
252b5132 9841 {
c1e26897 9842 if (IMMEDIATE_BIT_SET)
252b5132 9843 {
945ee430 9844 /* Immediate Post-indexed. */
aefd8a40 9845 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 9846 func (stream, "], #%s%d",
9847 NEGATIVE_BIT_SET ? "-" : "", offset);
9848 if (NEGATIVE_BIT_SET)
9849 offset = -offset;
fe56b6ce 9850 value_in_comment = offset;
252b5132 9851 }
945ee430 9852 else
ff4a8d2b
NC		 9853 {
9854 /* Register Post-indexed. */
9855 func (stream, "], %s%s",
9856 NEGATIVE_BIT_SET ? "-" : "",
9857 arm_regnames[given & 0xf]);
9858
9859 /* Writing back to the register that is the source/
9860 destination of the load/store is unpredictable. */
9861 if (! allow_unpredictable
9862 && (given & 0xf) == ((given >> 12) & 0xf))
9863 is_unpredictable = TRUE;
9864 }
c1e26897 9865
07a28fab
NC		 9866 if (! allow_unpredictable)
9867 {
9868 /* Writeback is automatically implied by post- addressing.
9869 Setting the W bit is unnecessary and ARM specify it as
9870 being unpredictable. */
9871 if (WRITEBACK_BIT_SET
9872 /* Specifying the PC register as the post-indexed
9873 registers is also unpredictable. */
ab8e2090
NC		 9874 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
9875 is_unpredictable = TRUE;
07a28fab 9876 }
252b5132
RH		 9877 }
9878 }
9879 break;
b34976b6 9880
252b5132 9881 case 'b':
6b5d3a4d 9882 {
f8b960bc 9883 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
05413229 9884 info->print_address_func (disp * 4 + pc + 8, info);
6b5d3a4d 9885 }
252b5132
RH		 9886 break;
9887
9888 case 'c':
c22aaad1
PB		 9889 if (((given >> 28) & 0xf) != 0xe)
9890 func (stream, "%s",
9891 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 9892 break;
9893
9894 case 'm':
9895 {
9896 int started = 0;
9897 int reg;
9898
9899 func (stream, "{");
9900 for (reg = 0; reg < 16; reg++)
9901 if ((given & (1 << reg)) != 0)
9902 {
9903 if (started)
9904 func (stream, ", ");
9905 started = 1;
9906 func (stream, "%s", arm_regnames[reg]);
9907 }
9908 func (stream, "}");
ab8e2090
NC		 9909 if (! started)
9910 is_unpredictable = TRUE;
252b5132
RH		 9911 }
9912 break;
9913
37b37b2d 9914 case 'q':
78c66db8 9915 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 9916 break;
9917
252b5132
RH		 9918 case 'o':
9919 if ((given & 0x02000000) != 0)
9920 {
a415b1cd
JB		 9921 unsigned int rotate = (given & 0xf00) >> 7;
9922 unsigned int immed = (given & 0xff);
9923 unsigned int a, i;
9924
9925 a = (((immed << (32 - rotate))
9926 | (immed >> rotate)) & 0xffffffff);
9927 /* If there is another encoding with smaller rotate,
9928 the rotate should be specified directly. */
9929 for (i = 0; i < 32; i += 2)
9930 if ((a << i | a >> (32 - i)) <= 0xff)
9931 break;
9932
9933 if (i != rotate)
9934 func (stream, "#%d, %d", immed, rotate);
9935 else
9936 func (stream, "#%d", a);
9937 value_in_comment = a;
252b5132
RH		 9938 }
9939 else
78c66db8 9940 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 9941 break;
9942
9943 case 'p':
9944 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 9945 {
823d2571
TG		 9946 arm_feature_set arm_ext_v6 =
9947 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
9948
aefd8a40
NC		 9949 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
9950 mechanism for setting PSR flag bits. They are
9951 obsolete in V6 onwards. */
823d2571
TG		 9952 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
9953 arm_ext_v6))
aefd8a40 9954 func (stream, "p");
4ab90a7a
AV		 9955 else
9956 is_unpredictable = TRUE;
aefd8a40 9957 }
252b5132
RH		 9958 break;
9959
9960 case 't':
9961 if ((given & 0x01200000) == 0x00200000)
9962 func (stream, "t");
9963 break;
9964
252b5132 9965 case 'A':
05413229
NC		 9966 {
9967 int offset = given & 0xff;
f02232aa 9968
05413229 9969 value_in_comment = offset * 4;
c1e26897 9970 if (NEGATIVE_BIT_SET)
05413229 9971 value_in_comment = - value_in_comment;
f02232aa 9972
05413229 9973 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 9974
c1e26897 9975 if (PRE_BIT_SET)
05413229
NC		 9976 {
9977 if (offset)
fe56b6ce 9978 func (stream, ", #%d]%s",
d908c8af 9979 (int) value_in_comment,
c1e26897 9980 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 9981 else
9982 func (stream, "]");
9983 }
9984 else
9985 {
9986 func (stream, "]");
f02232aa 9987
c1e26897 9988 if (WRITEBACK_BIT_SET)
05413229
NC		 9989 {
9990 if (offset)
d908c8af 9991 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 9992 }
9993 else
fe56b6ce 9994 {
d908c8af 9995 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 9996 value_in_comment = offset;
9997 }
05413229
NC		 9998 }
9999 }
252b5132
RH		 10000 break;
10001
077b8428
NC		 10002 case 'B':
10003 /* Print ARM V5 BLX(1) address: pc+25 bits. */
10004 {
10005 bfd_vma address;
10006 bfd_vma offset = 0;
b34976b6 10007
c1e26897 10008 if (! NEGATIVE_BIT_SET)
077b8428
NC		 10009 /* Is signed, hi bits should be ones. */
10010 offset = (-1) ^ 0x00ffffff;
10011
10012 /* Offset is (SignExtend(offset field)<<2). */
10013 offset += given & 0x00ffffff;
10014 offset <<= 2;
10015 address = offset + pc + 8;
b34976b6 10016
8f06b2d8
PB		 10017 if (given & 0x01000000)
10018 /* H bit allows addressing to 2-byte boundaries. */
10019 address += 2;
b1ee46c5 10020
8f06b2d8 10021 info->print_address_func (address, info);
b1ee46c5 10022 }
b1ee46c5
AH		 10023 break;
10024
252b5132 10025 case 'C':
90ec0d68
MGD		 10026 if ((given & 0x02000200) == 0x200)
10027 {
10028 const char * name;
10029 unsigned sysm = (given & 0x004f0000) >> 16;
10030
10031 sysm |= (given & 0x300) >> 4;
10032 name = banked_regname (sysm);
10033
10034 if (name != NULL)
10035 func (stream, "%s", name);
10036 else
d908c8af 10037 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 10038 }
10039 else
10040 {
43e65147 10041 func (stream, "%cPSR_",
90ec0d68
MGD		 10042 (given & 0x00400000) ? 'S' : 'C');
10043 if (given & 0x80000)
10044 func (stream, "f");
10045 if (given & 0x40000)
10046 func (stream, "s");
10047 if (given & 0x20000)
10048 func (stream, "x");
10049 if (given & 0x10000)
10050 func (stream, "c");
10051 }
252b5132
RH		 10052 break;
10053
62b3e311 10054 case 'U':
43e65147 10055 if ((given & 0xf0) == 0x60)
62b3e311 10056 {
52e7f43d
RE		 10057 switch (given & 0xf)
10058 {
10059 case 0xf: func (stream, "sy"); break;
10060 default:
10061 func (stream, "#%d", (int) given & 0xf);
10062 break;
10063 }
43e65147
L		 10064 }
10065 else
52e7f43d 10066 {
e797f7e0
MGD		 10067 const char * opt = data_barrier_option (given & 0xf);
10068 if (opt != NULL)
10069 func (stream, "%s", opt);
10070 else
52e7f43d 10071 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 10072 }
10073 break;
10074
b34976b6 10075 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 10076 case '5': case '6': case '7': case '8': case '9':
10077 {
16980d0b
JB		 10078 int width;
10079 unsigned long value;
252b5132 10080
16980d0b 10081 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 10082
252b5132
RH		 10083 switch (*c)
10084 {
ab8e2090
NC		 10085 case 'R':
10086 if (value == 15)
10087 is_unpredictable = TRUE;
10088 /* Fall through. */
16980d0b 10089 case 'r':
9eb6c0f1
MGD		 10090 case 'T':
10091 /* We want register + 1 when decoding T. */
10092 if (*c == 'T')
10093 ++value;
10094
ff4a8d2b
NC		 10095 if (c[1] == 'u')
10096 {
10097 /* Eat the 'u' character. */
10098 ++ c;
10099
10100 if (u_reg == value)
10101 is_unpredictable = TRUE;
10102 u_reg = value;
10103 }
10104 if (c[1] == 'U')
10105 {
10106 /* Eat the 'U' character. */
10107 ++ c;
10108
10109 if (U_reg == value)
10110 is_unpredictable = TRUE;
10111 U_reg = value;
10112 }
16980d0b
JB		 10113 func (stream, "%s", arm_regnames[value]);
10114 break;
10115 case 'd':
10116 func (stream, "%ld", value);
05413229 10117 value_in_comment = value;
16980d0b
JB		 10118 break;
10119 case 'b':
10120 func (stream, "%ld", value * 8);
05413229 10121 value_in_comment = value * 8;
16980d0b
JB		 10122 break;
10123 case 'W':
10124 func (stream, "%ld", value + 1);
05413229 10125 value_in_comment = value + 1;
16980d0b
JB		 10126 break;
10127 case 'x':
10128 func (stream, "0x%08lx", value);
10129
10130 /* Some SWI instructions have special
10131 meanings. */
10132 if ((given & 0x0fffffff) == 0x0FF00000)
10133 func (stream, "\t; IMB");
10134 else if ((given & 0x0fffffff) == 0x0FF00001)
10135 func (stream, "\t; IMBRange");
10136 break;
10137 case 'X':
10138 func (stream, "%01lx", value & 0xf);
05413229 10139 value_in_comment = value;
252b5132
RH		 10140 break;
10141 case '`':
10142 c++;
16980d0b 10143 if (value == 0)
252b5132
RH		 10144 func (stream, "%c", *c);
10145 break;
10146 case '\'':
10147 c++;
16980d0b 10148 if (value == ((1ul << width) - 1))
252b5132
RH		 10149 func (stream, "%c", *c);
10150 break;
10151 case '?':
fe56b6ce 10152 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 10153 c += 1 << width;
252b5132
RH		 10154 break;
10155 default:
10156 abort ();
10157 }
dffaa15c
AM		 10158 }
10159 break;
0dd132b6 10160
dffaa15c
AM		 10161 case 'e':
10162 {
10163 int imm;
0dd132b6 10164
dffaa15c
AM		 10165 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
10166 func (stream, "%d", imm);
10167 value_in_comment = imm;
10168 }
10169 break;
fe56b6ce 10170
dffaa15c
AM		 10171 case 'E':
10172 /* LSB and WIDTH fields of BFI or BFC. The machine-
10173 language instruction encodes LSB and MSB. */
10174 {
10175 long msb = (given & 0x001f0000) >> 16;
10176 long lsb = (given & 0x00000f80) >> 7;
10177 long w = msb - lsb + 1;
0a003adc 10178
dffaa15c
AM		 10179 if (w > 0)
10180 func (stream, "#%lu, #%lu", lsb, w);
10181 else
10182 func (stream, "(invalid: %lu:%lu)", lsb, msb);
10183 }
10184 break;
90ec0d68 10185
dffaa15c
AM		 10186 case 'R':
10187 /* Get the PSR/banked register name. */
10188 {
10189 const char * name;
10190 unsigned sysm = (given & 0x004f0000) >> 16;
90ec0d68 10191
dffaa15c
AM		 10192 sysm |= (given & 0x300) >> 4;
10193 name = banked_regname (sysm);
90ec0d68 10194
dffaa15c
AM		 10195 if (name != NULL)
10196 func (stream, "%s", name);
10197 else
10198 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
10199 }
10200 break;
fe56b6ce 10201
dffaa15c
AM		 10202 case 'V':
10203 /* 16-bit unsigned immediate from a MOVT or MOVW
10204 instruction, encoded in bits 0:11 and 15:19. */
10205 {
10206 long hi = (given & 0x000f0000) >> 4;
10207 long lo = (given & 0x00000fff);
10208 long imm16 = hi | lo;
0a003adc 10209
dffaa15c
AM		 10210 func (stream, "#%lu", imm16);
10211 value_in_comment = imm16;
252b5132 10212 }
dffaa15c
AM		 10213 break;
10214
10215 default:
10216 abort ();
252b5132
RH		 10217 }
10218 }
10219 else
10220 func (stream, "%c", *c);
10221 }
05413229
NC		 10222
10223 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 10224 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 10225
10226 if (is_unpredictable)
10227 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 10228
4a5329c6 10229 return;
252b5132
RH		 10230 }
10231 }
0b347048
TC		 10232 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
10233 return;
252b5132
RH		 10234}
10235
4a5329c6 10236/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 10237
4a5329c6
ZW		 10238static void
10239print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 10240{
6b5d3a4d 10241 const struct opcode16 *insn;
6a51a8a8
AM		 10242 void *stream = info->stream;
10243 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 10244
10245 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 10246 if ((given & insn->mask) == insn->value)
10247 {
05413229 10248 signed long value_in_comment = 0;
6b5d3a4d 10249 const char *c = insn->assembler;
05413229 10250
c19d1205
ZW		 10251 for (; *c; c++)
10252 {
10253 int domaskpc = 0;
10254 int domasklr = 0;
10255
10256 if (*c != '%')
10257 {
10258 func (stream, "%c", *c);
10259 continue;
10260 }
252b5132 10261
c19d1205
ZW		 10262 switch (*++c)
10263 {
10264 case '%':
10265 func (stream, "%%");
10266 break;
b34976b6 10267
c22aaad1
PB		 10268 case 'c':
10269 if (ifthen_state)
10270 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10271 break;
10272
10273 case 'C':
10274 if (ifthen_state)
10275 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10276 else
10277 func (stream, "s");
10278 break;
10279
10280 case 'I':
10281 {
10282 unsigned int tmp;
10283
10284 ifthen_next_state = given & 0xff;
10285 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
10286 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
10287 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
10288 }
10289 break;
10290
10291 case 'x':
10292 if (ifthen_next_state)
10293 func (stream, "\t; unpredictable branch in IT block\n");
10294 break;
10295
10296 case 'X':
10297 if (ifthen_state)
10298 func (stream, "\t; unpredictable <IT:%s>",
10299 arm_conditional[IFTHEN_COND]);
10300 break;
10301
c19d1205
ZW		 10302 case 'S':
10303 {
10304 long reg;
10305
10306 reg = (given >> 3) & 0x7;
10307 if (given & (1 << 6))
10308 reg += 8;
4f3c3dbb 10309
c19d1205
ZW		 10310 func (stream, "%s", arm_regnames[reg]);
10311 }
10312 break;
baf0cc5e 10313
c19d1205 10314 case 'D':
4f3c3dbb 10315 {
c19d1205
ZW		 10316 long reg;
10317
10318 reg = given & 0x7;
10319 if (given & (1 << 7))
10320 reg += 8;
10321
10322 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 10323 }
c19d1205
ZW		 10324 break;
10325
10326 case 'N':
10327 if (given & (1 << 8))
10328 domasklr = 1;
10329 /* Fall through. */
10330 case 'O':
10331 if (*c == 'O' && (given & (1 << 8)))
10332 domaskpc = 1;
10333 /* Fall through. */
10334 case 'M':
10335 {
10336 int started = 0;
10337 int reg;
10338
10339 func (stream, "{");
10340
10341 /* It would be nice if we could spot
10342 ranges, and generate the rS-rE format: */
10343 for (reg = 0; (reg < 8); reg++)
10344 if ((given & (1 << reg)) != 0)
10345 {
10346 if (started)
10347 func (stream, ", ");
10348 started = 1;
10349 func (stream, "%s", arm_regnames[reg]);
10350 }
10351
10352 if (domasklr)
10353 {
10354 if (started)
10355 func (stream, ", ");
10356 started = 1;
d908c8af 10357 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 10358 }
10359
10360 if (domaskpc)
10361 {
10362 if (started)
10363 func (stream, ", ");
d908c8af 10364 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 10365 }
10366
10367 func (stream, "}");
10368 }
10369 break;
10370
4547cb56
NC		 10371 case 'W':
10372 /* Print writeback indicator for a LDMIA. We are doing a
10373 writeback if the base register is not in the register
10374 mask. */
10375 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
10376 func (stream, "!");
dffaa15c 10377 break;
4547cb56 10378
c19d1205
ZW		 10379 case 'b':
10380 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
10381 {
10382 bfd_vma address = (pc + 4
10383 + ((given & 0x00f8) >> 2)
10384 + ((given & 0x0200) >> 3));
10385 info->print_address_func (address, info);
10386 }
10387 break;
10388
10389 case 's':
10390 /* Right shift immediate -- bits 6..10; 1-31 print
10391 as themselves, 0 prints as 32. */
10392 {
10393 long imm = (given & 0x07c0) >> 6;
10394 if (imm == 0)
10395 imm = 32;
0fd3a477 10396 func (stream, "#%ld", imm);
c19d1205
ZW		 10397 }
10398 break;
10399
10400 case '0': case '1': case '2': case '3': case '4':
10401 case '5': case '6': case '7': case '8': case '9':
10402 {
10403 int bitstart = *c++ - '0';
10404 int bitend = 0;
10405
10406 while (*c >= '0' && *c <= '9')
10407 bitstart = (bitstart * 10) + *c++ - '0';
10408
10409 switch (*c)
10410 {
10411 case '-':
10412 {
f8b960bc 10413 bfd_vma reg;
c19d1205
ZW		 10414
10415 c++;
10416 while (*c >= '0' && *c <= '9')
10417 bitend = (bitend * 10) + *c++ - '0';
10418 if (!bitend)
10419 abort ();
10420 reg = given >> bitstart;
10421 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 10422
c19d1205
ZW		 10423 switch (*c)
10424 {
10425 case 'r':
10426 func (stream, "%s", arm_regnames[reg]);
10427 break;
10428
10429 case 'd':
d908c8af 10430 func (stream, "%ld", (long) reg);
05413229 10431 value_in_comment = reg;
c19d1205
ZW		 10432 break;
10433
10434 case 'H':
d908c8af 10435 func (stream, "%ld", (long) (reg << 1));
05413229 10436 value_in_comment = reg << 1;
c19d1205
ZW		 10437 break;
10438
10439 case 'W':
d908c8af 10440 func (stream, "%ld", (long) (reg << 2));
05413229 10441 value_in_comment = reg << 2;
c19d1205
ZW		 10442 break;
10443
10444 case 'a':
10445 /* PC-relative address -- the bottom two
10446 bits of the address are dropped
10447 before the calculation. */
10448 info->print_address_func
10449 (((pc + 4) & ~3) + (reg << 2), info);
05413229 10450 value_in_comment = 0;
c19d1205
ZW		 10451 break;
10452
10453 case 'x':
d908c8af 10454 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 10455 break;
10456
c19d1205
ZW		 10457 case 'B':
10458 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6b5d3a4d 10459 info->print_address_func (reg * 2 + pc + 4, info);
05413229 10460 value_in_comment = 0;
c19d1205
ZW		 10461 break;
10462
10463 case 'c':
c22aaad1 10464 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 10465 break;
10466
10467 default:
10468 abort ();
10469 }
10470 }
10471 break;
10472
10473 case '\'':
10474 c++;
10475 if ((given & (1 << bitstart)) != 0)
10476 func (stream, "%c", *c);
10477 break;
10478
10479 case '?':
10480 ++c;
10481 if ((given & (1 << bitstart)) != 0)
10482 func (stream, "%c", *c++);
10483 else
10484 func (stream, "%c", *++c);
10485 break;
10486
10487 default:
10488 abort ();
10489 }
10490 }
10491 break;
10492
10493 default:
10494 abort ();
10495 }
10496 }
05413229
NC		 10497
10498 if (value_in_comment > 32 || value_in_comment < -16)
10499 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 10500 return;
c19d1205
ZW		 10501 }
10502
10503 /* No match. */
0b347048
TC		 10504 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
10505 return;
c19d1205
ZW		 10506}
10507
62b3e311 10508/* Return the name of an V7M special register. */
fe56b6ce 10509
62b3e311
PB		 10510static const char *
10511psr_name (int regno)
10512{
10513 switch (regno)
10514 {
1a336194
TP		 10515 case 0x0: return "APSR";
10516 case 0x1: return "IAPSR";
10517 case 0x2: return "EAPSR";
10518 case 0x3: return "PSR";
10519 case 0x5: return "IPSR";
10520 case 0x6: return "EPSR";
10521 case 0x7: return "IEPSR";
10522 case 0x8: return "MSP";
10523 case 0x9: return "PSP";
10524 case 0xa: return "MSPLIM";
10525 case 0xb: return "PSPLIM";
10526 case 0x10: return "PRIMASK";
10527 case 0x11: return "BASEPRI";
10528 case 0x12: return "BASEPRI_MAX";
10529 case 0x13: return "FAULTMASK";
10530 case 0x14: return "CONTROL";
16a1fa25
TP		 10531 case 0x88: return "MSP_NS";
10532 case 0x89: return "PSP_NS";
1a336194
TP		 10533 case 0x8a: return "MSPLIM_NS";
10534 case 0x8b: return "PSPLIM_NS";
10535 case 0x90: return "PRIMASK_NS";
10536 case 0x91: return "BASEPRI_NS";
10537 case 0x93: return "FAULTMASK_NS";
10538 case 0x94: return "CONTROL_NS";
10539 case 0x98: return "SP_NS";
62b3e311
PB		 10540 default: return "<unknown>";
10541 }
10542}
10543
4a5329c6
ZW		 10544/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
10545
10546static void
10547print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 10548{
6b5d3a4d 10549 const struct opcode32 *insn;
c19d1205
ZW		 10550 void *stream = info->stream;
10551 fprintf_ftype func = info->fprintf_func;
73cd51e5 10552 bfd_boolean is_mve = is_mve_architecture (info);
c19d1205 10553
16980d0b
JB		 10554 if (print_insn_coprocessor (pc, info, given, TRUE))
10555 return;
10556
73cd51e5
AV		 10557 if ((is_mve == FALSE) && print_insn_neon (info, given, TRUE))
10558 return;
10559
10560 if (is_mve && print_insn_mve (info, given))
8f06b2d8
PB		 10561 return;
10562
33593eaf
MM		 10563 if (print_insn_generic_coprocessor (pc, info, given, TRUE))
10564 return;
10565
c19d1205
ZW		 10566 for (insn = thumb32_opcodes; insn->assembler; insn++)
10567 if ((given & insn->mask) == insn->value)
10568 {
4b5a202f 10569 bfd_boolean is_clrm = FALSE;
ff4a8d2b 10570 bfd_boolean is_unpredictable = FALSE;
05413229 10571 signed long value_in_comment = 0;
6b5d3a4d 10572 const char *c = insn->assembler;
05413229 10573
c19d1205
ZW		 10574 for (; *c; c++)
10575 {
10576 if (*c != '%')
10577 {
10578 func (stream, "%c", *c);
10579 continue;
10580 }
10581
10582 switch (*++c)
10583 {
10584 case '%':
10585 func (stream, "%%");
10586 break;
10587
c22aaad1
PB		 10588 case 'c':
10589 if (ifthen_state)
10590 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10591 break;
10592
10593 case 'x':
10594 if (ifthen_next_state)
10595 func (stream, "\t; unpredictable branch in IT block\n");
10596 break;
10597
10598 case 'X':
10599 if (ifthen_state)
10600 func (stream, "\t; unpredictable <IT:%s>",
10601 arm_conditional[IFTHEN_COND]);
10602 break;
10603
c19d1205
ZW		 10604 case 'I':
10605 {
10606 unsigned int imm12 = 0;
fe56b6ce 10607
c19d1205
ZW		 10608 imm12 |= (given & 0x000000ffu);
10609 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 10610 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 10611 func (stream, "#%u", imm12);
10612 value_in_comment = imm12;
c19d1205
ZW		 10613 }
10614 break;
10615
10616 case 'M':
10617 {
10618 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 10619
c19d1205
ZW		 10620 bits |= (given & 0x000000ffu);
10621 bits |= (given & 0x00007000u) >> 4;
10622 bits |= (given & 0x04000000u) >> 15;
10623 imm8 = (bits & 0x0ff);
10624 mod = (bits & 0xf00) >> 8;
10625 switch (mod)
10626 {
10627 case 0: imm = imm8; break;
c1e26897
NC		 10628 case 1: imm = ((imm8 << 16) | imm8); break;
10629 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
10630 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 10631 default:
10632 mod = (bits & 0xf80) >> 7;
10633 imm8 = (bits & 0x07f) | 0x80;
10634 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
10635 }
fe56b6ce
NC		 10636 func (stream, "#%u", imm);
10637 value_in_comment = imm;
c19d1205
ZW		 10638 }
10639 break;
43e65147 10640
c19d1205
ZW		 10641 case 'J':
10642 {
10643 unsigned int imm = 0;
fe56b6ce 10644
c19d1205
ZW		 10645 imm |= (given & 0x000000ffu);
10646 imm |= (given & 0x00007000u) >> 4;
10647 imm |= (given & 0x04000000u) >> 15;
10648 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 10649 func (stream, "#%u", imm);
10650 value_in_comment = imm;
c19d1205
ZW		 10651 }
10652 break;
10653
10654 case 'K':
10655 {
10656 unsigned int imm = 0;
fe56b6ce 10657
c19d1205
ZW		 10658 imm |= (given & 0x000f0000u) >> 16;
10659 imm |= (given & 0x00000ff0u) >> 0;
10660 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 10661 func (stream, "#%u", imm);
10662 value_in_comment = imm;
c19d1205
ZW		 10663 }
10664 break;
10665
74db7efb
NC		 10666 case 'H':
10667 {
10668 unsigned int imm = 0;
10669
10670 imm |= (given & 0x000f0000u) >> 4;
10671 imm |= (given & 0x00000fffu) >> 0;
10672 func (stream, "#%u", imm);
10673 value_in_comment = imm;
10674 }
10675 break;
10676
90ec0d68
MGD		 10677 case 'V':
10678 {
10679 unsigned int imm = 0;
10680
10681 imm |= (given & 0x00000fffu);
10682 imm |= (given & 0x000f0000u) >> 4;
10683 func (stream, "#%u", imm);
10684 value_in_comment = imm;
10685 }
10686 break;
10687
c19d1205
ZW		 10688 case 'S':
10689 {
10690 unsigned int reg = (given & 0x0000000fu);
10691 unsigned int stp = (given & 0x00000030u) >> 4;
10692 unsigned int imm = 0;
10693 imm |= (given & 0x000000c0u) >> 6;
10694 imm |= (given & 0x00007000u) >> 10;
10695
10696 func (stream, "%s", arm_regnames[reg]);
10697 switch (stp)
10698 {
10699 case 0:
10700 if (imm > 0)
10701 func (stream, ", lsl #%u", imm);
10702 break;
10703
10704 case 1:
10705 if (imm == 0)
10706 imm = 32;
10707 func (stream, ", lsr #%u", imm);
10708 break;
10709
10710 case 2:
10711 if (imm == 0)
10712 imm = 32;
10713 func (stream, ", asr #%u", imm);
10714 break;
10715
10716 case 3:
10717 if (imm == 0)
10718 func (stream, ", rrx");
10719 else
10720 func (stream, ", ror #%u", imm);
10721 }
10722 }
10723 break;
10724
10725 case 'a':
10726 {
10727 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 10728 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 10729 unsigned int op = (given & 0x00000f00) >> 8;
10730 unsigned int i12 = (given & 0x00000fff);
10731 unsigned int i8 = (given & 0x000000ff);
10732 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 10733 bfd_vma offset = 0;
c19d1205
ZW		 10734
10735 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 10736 if (U) /* 12-bit positive immediate offset. */
10737 {
10738 offset = i12;
10739 if (Rn != 15)
10740 value_in_comment = offset;
10741 }
10742 else if (Rn == 15) /* 12-bit negative immediate offset. */
10743 offset = - (int) i12;
10744 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 10745 {
10746 unsigned int Rm = (i8 & 0x0f);
10747 unsigned int sh = (i8 & 0x30) >> 4;
05413229 10748
c19d1205
ZW		 10749 func (stream, ", %s", arm_regnames[Rm]);
10750 if (sh)
10751 func (stream, ", lsl #%u", sh);
10752 func (stream, "]");
10753 break;
10754 }
10755 else switch (op)
10756 {
05413229 10757 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 10758 offset = i8;
10759 break;
10760
05413229 10761 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 10762 offset = -i8;
10763 break;
10764
05413229 10765 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 10766 offset = i8;
10767 writeback = TRUE;
10768 break;
10769
05413229 10770 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 10771 offset = -i8;
10772 writeback = TRUE;
10773 break;
10774
05413229 10775 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 10776 offset = i8;
10777 postind = TRUE;
10778 break;
10779
05413229 10780 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 10781 offset = -i8;
10782 postind = TRUE;
10783 break;
10784
10785 default:
10786 func (stream, ", <undefined>]");
10787 goto skip;
10788 }
10789
10790 if (postind)
d908c8af 10791 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 10792 else
10793 {
10794 if (offset)
d908c8af 10795 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 10796 func (stream, writeback ? "]!" : "]");
10797 }
10798
10799 if (Rn == 15)
10800 {
10801 func (stream, "\t; ");
10802 info->print_address_func (((pc + 4) & ~3) + offset, info);
10803 }
10804 }
10805 skip:
10806 break;
10807
10808 case 'A':
10809 {
c1e26897
NC		 10810 unsigned int U = ! NEGATIVE_BIT_SET;
10811 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 10812 unsigned int Rn = (given & 0x000f0000) >> 16;
10813 unsigned int off = (given & 0x000000ff);
10814
10815 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 10816
10817 if (PRE_BIT_SET)
c19d1205
ZW		 10818 {
10819 if (off || !U)
05413229
NC		 10820 {
10821 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
fe50e98c 10822 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 10823 }
c19d1205
ZW		 10824 func (stream, "]");
10825 if (W)
10826 func (stream, "!");
10827 }
10828 else
10829 {
10830 func (stream, "], ");
10831 if (W)
05413229
NC		 10832 {
10833 func (stream, "#%c%u", U ? '+' : '-', off * 4);
fe50e98c 10834 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 10835 }
c19d1205 10836 else
fe56b6ce
NC		 10837 {
10838 func (stream, "{%u}", off);
10839 value_in_comment = off;
10840 }
c19d1205
ZW		 10841 }
10842 }
10843 break;
10844
10845 case 'w':
10846 {
10847 unsigned int Sbit = (given & 0x01000000) >> 24;
10848 unsigned int type = (given & 0x00600000) >> 21;
05413229 10849
c19d1205
ZW		 10850 switch (type)
10851 {
10852 case 0: func (stream, Sbit ? "sb" : "b"); break;
10853 case 1: func (stream, Sbit ? "sh" : "h"); break;
10854 case 2:
10855 if (Sbit)
10856 func (stream, "??");
10857 break;
10858 case 3:
10859 func (stream, "??");
10860 break;
10861 }
10862 }
10863 break;
10864
4b5a202f
AV		 10865 case 'n':
10866 is_clrm = TRUE;
10867 /* Fall through. */
c19d1205
ZW		 10868 case 'm':
10869 {
10870 int started = 0;
10871 int reg;
10872
10873 func (stream, "{");
10874 for (reg = 0; reg < 16; reg++)
10875 if ((given & (1 << reg)) != 0)
10876 {
10877 if (started)
10878 func (stream, ", ");
10879 started = 1;
4b5a202f
AV		 10880 if (is_clrm && reg == 13)
10881 func (stream, "(invalid: %s)", arm_regnames[reg]);
10882 else if (is_clrm && reg == 15)
10883 func (stream, "%s", "APSR");
10884 else
10885 func (stream, "%s", arm_regnames[reg]);
c19d1205
ZW		 10886 }
10887 func (stream, "}");
10888 }
10889 break;
10890
10891 case 'E':
10892 {
10893 unsigned int msb = (given & 0x0000001f);
10894 unsigned int lsb = 0;
fe56b6ce 10895
c19d1205
ZW		 10896 lsb |= (given & 0x000000c0u) >> 6;
10897 lsb |= (given & 0x00007000u) >> 10;
10898 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
10899 }
10900 break;
10901
10902 case 'F':
10903 {
10904 unsigned int width = (given & 0x0000001f) + 1;
10905 unsigned int lsb = 0;
fe56b6ce 10906
c19d1205
ZW		 10907 lsb |= (given & 0x000000c0u) >> 6;
10908 lsb |= (given & 0x00007000u) >> 10;
10909 func (stream, "#%u, #%u", lsb, width);
10910 }
10911 break;
10912
e12437dc
AV		 10913 case 'G':
10914 {
10915 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
10916 func (stream, "%x", boff);
10917 }
10918 break;
10919
e5d6e09e
AV		 10920 case 'W':
10921 {
10922 unsigned int immA = (given & 0x001f0000u) >> 16;
10923 unsigned int immB = (given & 0x000007feu) >> 1;
10924 unsigned int immC = (given & 0x00000800u) >> 11;
10925 bfd_vma offset = 0;
10926
10927 offset |= immA << 12;
10928 offset |= immB << 2;
10929 offset |= immC << 1;
10930 /* Sign extend. */
10931 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
10932
10933 info->print_address_func (pc + 4 + offset, info);
10934 }
10935 break;
10936
1caf72a5
AV		 10937 case 'Y':
10938 {
10939 unsigned int immA = (given & 0x007f0000u) >> 16;
10940 unsigned int immB = (given & 0x000007feu) >> 1;
10941 unsigned int immC = (given & 0x00000800u) >> 11;
10942 bfd_vma offset = 0;
10943
10944 offset |= immA << 12;
10945 offset |= immB << 2;
10946 offset |= immC << 1;
10947 /* Sign extend. */
10948 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
10949
10950 info->print_address_func (pc + 4 + offset, info);
10951 }
10952 break;
10953
1889da70
AV		 10954 case 'Z':
10955 {
10956 unsigned int immA = (given & 0x00010000u) >> 16;
10957 unsigned int immB = (given & 0x000007feu) >> 1;
10958 unsigned int immC = (given & 0x00000800u) >> 11;
10959 bfd_vma offset = 0;
10960
10961 offset |= immA << 12;
10962 offset |= immB << 2;
10963 offset |= immC << 1;
10964 /* Sign extend. */
10965 offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
10966
10967 info->print_address_func (pc + 4 + offset, info);
f6b2b12d
AV		 10968
10969 unsigned int T = (given & 0x00020000u) >> 17;
10970 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
10971 unsigned int boffset = (T == 1) ? 4 : 2;
10972 func (stream, ", ");
10973 func (stream, "%x", endoffset + boffset);
1889da70
AV		 10974 }
10975 break;
10976
60f993ce
AV		 10977 case 'Q':
10978 {
10979 unsigned int immh = (given & 0x000007feu) >> 1;
10980 unsigned int imml = (given & 0x00000800u) >> 11;
10981 bfd_vma imm32 = 0;
10982
10983 imm32 |= immh << 2;
10984 imm32 |= imml << 1;
10985
10986 info->print_address_func (pc + 4 + imm32, info);
10987 }
10988 break;
10989
10990 case 'P':
10991 {
10992 unsigned int immh = (given & 0x000007feu) >> 1;
10993 unsigned int imml = (given & 0x00000800u) >> 11;
10994 bfd_vma imm32 = 0;
10995
10996 imm32 |= immh << 2;
10997 imm32 |= imml << 1;
10998
10999 info->print_address_func (pc + 4 - imm32, info);
11000 }
11001 break;
11002
c19d1205
ZW		 11003 case 'b':
11004 {
11005 unsigned int S = (given & 0x04000000u) >> 26;
11006 unsigned int J1 = (given & 0x00002000u) >> 13;
11007 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 11008 bfd_vma offset = 0;
c19d1205
ZW		 11009
11010 offset |= !S << 20;
11011 offset |= J2 << 19;
11012 offset |= J1 << 18;
11013 offset |= (given & 0x003f0000) >> 4;
11014 offset |= (given & 0x000007ff) << 1;
11015 offset -= (1 << 20);
11016
11017 info->print_address_func (pc + 4 + offset, info);
11018 }
11019 break;
11020
11021 case 'B':
11022 {
11023 unsigned int S = (given & 0x04000000u) >> 26;
11024 unsigned int I1 = (given & 0x00002000u) >> 13;
11025 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 11026 bfd_vma offset = 0;
c19d1205
ZW		 11027
11028 offset |= !S << 24;
11029 offset |= !(I1 ^ S) << 23;
11030 offset |= !(I2 ^ S) << 22;
11031 offset |= (given & 0x03ff0000u) >> 4;
11032 offset |= (given & 0x000007ffu) << 1;
11033 offset -= (1 << 24);
36b0c57d 11034 offset += pc + 4;
c19d1205 11035
36b0c57d
PB		 11036 /* BLX target addresses are always word aligned. */
11037 if ((given & 0x00001000u) == 0)
11038 offset &= ~2u;
11039
11040 info->print_address_func (offset, info);
c19d1205
ZW		 11041 }
11042 break;
11043
11044 case 's':
11045 {
11046 unsigned int shift = 0;
fe56b6ce 11047
c19d1205
ZW		 11048 shift |= (given & 0x000000c0u) >> 6;
11049 shift |= (given & 0x00007000u) >> 10;
c1e26897 11050 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 11051 func (stream, ", asr #%u", shift);
11052 else if (shift)
11053 func (stream, ", lsl #%u", shift);
11054 /* else print nothing - lsl #0 */
11055 }
11056 break;
11057
11058 case 'R':
11059 {
11060 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 11061
c19d1205
ZW		 11062 if (rot)
11063 func (stream, ", ror #%u", rot * 8);
11064 }
11065 break;
11066
62b3e311 11067 case 'U':
43e65147 11068 if ((given & 0xf0) == 0x60)
62b3e311 11069 {
52e7f43d
RE		 11070 switch (given & 0xf)
11071 {
11072 case 0xf: func (stream, "sy"); break;
11073 default:
11074 func (stream, "#%d", (int) given & 0xf);
11075 break;
11076 }
62b3e311 11077 }
43e65147 11078 else
52e7f43d 11079 {
e797f7e0
MGD		 11080 const char * opt = data_barrier_option (given & 0xf);
11081 if (opt != NULL)
11082 func (stream, "%s", opt);
11083 else
11084 func (stream, "#%d", (int) given & 0xf);
52e7f43d 11085 }
62b3e311
PB		 11086 break;
11087
11088 case 'C':
11089 if ((given & 0xff) == 0)
11090 {
11091 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
11092 if (given & 0x800)
11093 func (stream, "f");
11094 if (given & 0x400)
11095 func (stream, "s");
11096 if (given & 0x200)
11097 func (stream, "x");
11098 if (given & 0x100)
11099 func (stream, "c");
11100 }
90ec0d68
MGD		 11101 else if ((given & 0x20) == 0x20)
11102 {
11103 char const* name;
11104 unsigned sysm = (given & 0xf00) >> 8;
11105
11106 sysm |= (given & 0x30);
11107 sysm |= (given & 0x00100000) >> 14;
11108 name = banked_regname (sysm);
43e65147 11109
90ec0d68
MGD		 11110 if (name != NULL)
11111 func (stream, "%s", name);
11112 else
d908c8af 11113 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 11114 }
62b3e311
PB		 11115 else
11116 {
d908c8af 11117 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 11118 }
11119 break;
11120
11121 case 'D':
90ec0d68
MGD		 11122 if (((given & 0xff) == 0)
11123 || ((given & 0x20) == 0x20))
11124 {
11125 char const* name;
11126 unsigned sm = (given & 0xf0000) >> 16;
11127
11128 sm |= (given & 0x30);
11129 sm |= (given & 0x00100000) >> 14;
11130 name = banked_regname (sm);
11131
11132 if (name != NULL)
11133 func (stream, "%s", name);
11134 else
d908c8af 11135 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 11136 }
62b3e311 11137 else
d908c8af 11138 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 11139 break;
11140
c19d1205
ZW		 11141 case '0': case '1': case '2': case '3': case '4':
11142 case '5': case '6': case '7': case '8': case '9':
11143 {
16980d0b
JB		 11144 int width;
11145 unsigned long val;
c19d1205 11146
16980d0b 11147 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 11148
c19d1205
ZW		 11149 switch (*c)
11150 {
d052b9b7
AV		 11151 case 's':
11152 if (val <= 3)
11153 func (stream, "%s", mve_vec_sizename[val]);
11154 else
11155 func (stream, "<undef size>");
11156 break;
11157
05413229
NC		 11158 case 'd':
11159 func (stream, "%lu", val);
11160 value_in_comment = val;
11161 break;
ff4a8d2b 11162
f0fba320
RL		 11163 case 'D':
11164 func (stream, "%lu", val + 1);
11165 value_in_comment = val + 1;
11166 break;
11167
05413229
NC		 11168 case 'W':
11169 func (stream, "%lu", val * 4);
11170 value_in_comment = val * 4;
11171 break;
ff4a8d2b 11172
f1c7f421
AV		 11173 case 'S':
11174 if (val == 13)
11175 is_unpredictable = TRUE;
11176 /* Fall through. */
ff4a8d2b
NC		 11177 case 'R':
11178 if (val == 15)
11179 is_unpredictable = TRUE;
11180 /* Fall through. */
11181 case 'r':
11182 func (stream, "%s", arm_regnames[val]);
11183 break;
c19d1205
ZW		 11184
11185 case 'c':
c22aaad1 11186 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 11187 break;
11188
11189 case '\'':
c19d1205 11190 c++;
16980d0b
JB		 11191 if (val == ((1ul << width) - 1))
11192 func (stream, "%c", *c);
c19d1205 11193 break;
43e65147 11194
c19d1205 11195 case '`':
c19d1205 11196 c++;
16980d0b
JB		 11197 if (val == 0)
11198 func (stream, "%c", *c);
c19d1205
ZW		 11199 break;
11200
11201 case '?':
fe56b6ce 11202 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 11203 c += 1 << width;
c19d1205 11204 break;
43e65147 11205
0bb027fd
RR		 11206 case 'x':
11207 func (stream, "0x%lx", val & 0xffffffffUL);
11208 break;
c19d1205
ZW		 11209
11210 default:
11211 abort ();
11212 }
11213 }
11214 break;
11215
32a94698
NC		 11216 case 'L':
11217 /* PR binutils/12534
11218 If we have a PC relative offset in an LDRD or STRD
11219 instructions then display the decoded address. */
11220 if (((given >> 16) & 0xf) == 0xf)
11221 {
11222 bfd_vma offset = (given & 0xff) * 4;
11223
11224 if ((given & (1 << 23)) == 0)
11225 offset = - offset;
11226 func (stream, "\t; ");
11227 info->print_address_func ((pc & ~3) + 4 + offset, info);
11228 }
11229 break;
11230
c19d1205
ZW		 11231 default:
11232 abort ();
11233 }
11234 }
05413229
NC		 11235
11236 if (value_in_comment > 32 || value_in_comment < -16)
11237 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 11238
11239 if (is_unpredictable)
11240 func (stream, UNPREDICTABLE_INSTRUCTION);
11241
4a5329c6 11242 return;
c19d1205 11243 }
252b5132 11244
58efb6c0 11245 /* No match. */
0b347048
TC		 11246 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
11247 return;
252b5132
RH		 11248}
11249
e821645d
DJ		 11250/* Print data bytes on INFO->STREAM. */
11251
11252static void
fe56b6ce
NC		 11253print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
11254 struct disassemble_info *info,
e821645d
DJ		 11255 long given)
11256{
11257 switch (info->bytes_per_chunk)
11258 {
11259 case 1:
11260 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
11261 break;
11262 case 2:
11263 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
11264 break;
11265 case 4:
11266 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
11267 break;
11268 default:
11269 abort ();
11270 }
11271}
11272
22a398e1 11273/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 11274 being displayed in symbol relative addresses.
11275
11276 Also disallow private symbol, with __tagsym$$ prefix,
11277 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 11278
11279bfd_boolean
11280arm_symbol_is_valid (asymbol * sym,
11281 struct disassemble_info * info ATTRIBUTE_UNUSED)
11282{
11283 const char * name;
43e65147 11284
22a398e1
NC		 11285 if (sym == NULL)
11286 return FALSE;
11287
11288 name = bfd_asymbol_name (sym);
11289
d8282f0e 11290 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 11291}
11292
65b48a81 11293/* Parse the string of disassembler options. */
baf0cc5e 11294
65b48a81 11295static void
f995bbe8 11296parse_arm_disassembler_options (const char *options)
dd92f639 11297{
f995bbe8 11298 const char *opt;
b34976b6 11299
65b48a81 11300 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
dd92f639 11301 {
65b48a81
PB		 11302 if (CONST_STRNEQ (opt, "reg-names-"))
11303 {
11304 unsigned int i;
11305 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11306 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
11307 {
11308 regname_selected = i;
11309 break;
11310 }
b34976b6 11311
65b48a81 11312 if (i >= NUM_ARM_OPTIONS)
a6743a54
AM		 11313 /* xgettext: c-format */
11314 opcodes_error_handler (_("unrecognised register name set: %s"),
11315 opt);
65b48a81
PB		 11316 }
11317 else if (CONST_STRNEQ (opt, "force-thumb"))
11318 force_thumb = 1;
11319 else if (CONST_STRNEQ (opt, "no-force-thumb"))
11320 force_thumb = 0;
11321 else
a6743a54
AM		 11322 /* xgettext: c-format */
11323 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
dd92f639 11324 }
b34976b6 11325
dd92f639
NC		 11326 return;
11327}
11328
5bc5ae88
RL		 11329static bfd_boolean
11330mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11331 enum map_type *map_symbol);
11332
c22aaad1
PB		 11333/* Search back through the insn stream to determine if this instruction is
11334 conditionally executed. */
fe56b6ce 11335
c22aaad1 11336static void
fe56b6ce
NC		 11337find_ifthen_state (bfd_vma pc,
11338 struct disassemble_info *info,
c22aaad1
PB		 11339 bfd_boolean little)
11340{
11341 unsigned char b[2];
11342 unsigned int insn;
11343 int status;
11344 /* COUNT is twice the number of instructions seen. It will be odd if we
11345 just crossed an instruction boundary. */
11346 int count;
11347 int it_count;
11348 unsigned int seen_it;
11349 bfd_vma addr;
11350
11351 ifthen_address = pc;
11352 ifthen_state = 0;
11353
11354 addr = pc;
11355 count = 1;
11356 it_count = 0;
11357 seen_it = 0;
11358 /* Scan backwards looking for IT instructions, keeping track of where
11359 instruction boundaries are. We don't know if something is actually an
11360 IT instruction until we find a definite instruction boundary. */
11361 for (;;)
11362 {
fe56b6ce 11363 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 11364 {
11365 /* A symbol must be on an instruction boundary, and will not
11366 be within an IT block. */
11367 if (seen_it && (count & 1))
11368 break;
11369
11370 return;
11371 }
11372 addr -= 2;
fe56b6ce 11373 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 11374 if (status)
11375 return;
11376
11377 if (little)
11378 insn = (b[0]) | (b[1] << 8);
11379 else
11380 insn = (b[1]) | (b[0] << 8);
11381 if (seen_it)
11382 {
11383 if ((insn & 0xf800) < 0xe800)
11384 {
11385 /* Addr + 2 is an instruction boundary. See if this matches
11386 the expected boundary based on the position of the last
11387 IT candidate. */
11388 if (count & 1)
11389 break;
11390 seen_it = 0;
11391 }
11392 }
11393 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
11394 {
5bc5ae88
RL		 11395 enum map_type type = MAP_ARM;
11396 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
11397
11398 if (!found || (found && type == MAP_THUMB))
11399 {
11400 /* This could be an IT instruction. */
11401 seen_it = insn;
11402 it_count = count >> 1;
11403 }
c22aaad1
PB		 11404 }
11405 if ((insn & 0xf800) >= 0xe800)
11406 count++;
11407 else
11408 count = (count + 2) | 1;
11409 /* IT blocks contain at most 4 instructions. */
11410 if (count >= 8 && !seen_it)
11411 return;
11412 }
11413 /* We found an IT instruction. */
11414 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
11415 if ((ifthen_state & 0xf) == 0)
11416 ifthen_state = 0;
11417}
11418
b0e28b39
DJ		 11419/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
11420 mapping symbol. */
11421
11422static int
11423is_mapping_symbol (struct disassemble_info *info, int n,
11424 enum map_type *map_type)
11425{
11426 const char *name;
11427
11428 name = bfd_asymbol_name (info->symtab[n]);
11429 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
11430 && (name[2] == 0 || name[2] == '.'))
11431 {
11432 *map_type = ((name[1] == 'a') ? MAP_ARM
11433 : (name[1] == 't') ? MAP_THUMB
11434 : MAP_DATA);
11435 return TRUE;
11436 }
11437
11438 return FALSE;
11439}
11440
11441/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
11442 Returns nonzero if *MAP_TYPE was set. */
11443
11444static int
11445get_map_sym_type (struct disassemble_info *info,
11446 int n,
11447 enum map_type *map_type)
11448{
11449 /* If the symbol is in a different section, ignore it. */
11450 if (info->section != NULL && info->section != info->symtab[n]->section)
11451 return FALSE;
11452
11453 return is_mapping_symbol (info, n, map_type);
11454}
11455
11456/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 11457 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 11458
11459static int
fe56b6ce
NC		 11460get_sym_code_type (struct disassemble_info *info,
11461 int n,
e821645d 11462 enum map_type *map_type)
2087ad84
PB		 11463{
11464 elf_symbol_type *es;
11465 unsigned int type;
b0e28b39
DJ		 11466
11467 /* If the symbol is in a different section, ignore it. */
11468 if (info->section != NULL && info->section != info->symtab[n]->section)
11469 return FALSE;
2087ad84 11470
e821645d 11471 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 11472 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
11473
11474 /* If the symbol has function type then use that. */
34e77a92 11475 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 11476 {
39d911fc
TP		 11477 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
11478 == ST_BRANCH_TO_THUMB)
35fc36a8
RS		 11479 *map_type = MAP_THUMB;
11480 else
11481 *map_type = MAP_ARM;
2087ad84
PB		 11482 return TRUE;
11483 }
11484
2087ad84
PB		 11485 return FALSE;
11486}
11487
5bc5ae88
RL		 11488/* Search the mapping symbol state for instruction at pc. This is only
11489 applicable for elf target.
11490
11491 There is an assumption Here, info->private_data contains the correct AND
11492 up-to-date information about current scan process. The information will be
11493 used to speed this search process.
11494
11495 Return TRUE if the mapping state can be determined, and map_symbol
11496 will be updated accordingly. Otherwise, return FALSE. */
11497
11498static bfd_boolean
11499mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11500 enum map_type *map_symbol)
11501{
796d6298
TC		 11502 bfd_vma addr, section_vma = 0;
11503 int n, last_sym = -1;
5bc5ae88 11504 bfd_boolean found = FALSE;
796d6298
TC		 11505 bfd_boolean can_use_search_opt_p = FALSE;
11506
11507 /* Default to DATA. A text section is required by the ABI to contain an
11508 INSN mapping symbol at the start. A data section has no such
11509 requirement, hence if no mapping symbol is found the section must
11510 contain only data. This however isn't very useful if the user has
11511 fully stripped the binaries. If this is the case use the section
11512 attributes to determine the default. If we have no section default to
11513 INSN as well, as we may be disassembling some raw bytes on a baremetal
11514 HEX file or similar. */
11515 enum map_type type = MAP_DATA;
11516 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
11517 type = MAP_ARM;
5bc5ae88
RL		 11518 struct arm_private_data *private_data;
11519
796d6298 11520 if (info->private_data == NULL
5bc5ae88
RL		 11521 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
11522 return FALSE;
11523
11524 private_data = info->private_data;
5bc5ae88 11525
796d6298
TC		 11526 /* First, look for mapping symbols. */
11527 if (info->symtab_size != 0)
11528 {
11529 if (pc <= private_data->last_mapping_addr)
11530 private_data->last_mapping_sym = -1;
11531
11532 /* Start scanning at the start of the function, or wherever
11533 we finished last time. */
11534 n = info->symtab_pos + 1;
11535
11536 /* If the last stop offset is different from the current one it means we
11537 are disassembling a different glob of bytes. As such the optimization
11538 would not be safe and we should start over. */
11539 can_use_search_opt_p
11540 = private_data->last_mapping_sym >= 0
11541 && info->stop_offset == private_data->last_stop_offset;
11542
11543 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11544 n = private_data->last_mapping_sym;
11545
11546 /* Look down while we haven't passed the location being disassembled.
11547 The reason for this is that there's no defined order between a symbol
11548 and an mapping symbol that may be at the same address. We may have to
11549 look at least one position ahead. */
11550 for (; n < info->symtab_size; n++)
11551 {
11552 addr = bfd_asymbol_value (info->symtab[n]);
11553 if (addr > pc)
11554 break;
11555 if (get_map_sym_type (info, n, &type))
11556 {
11557 last_sym = n;
11558 found = TRUE;
11559 }
11560 }
5bc5ae88 11561
796d6298
TC		 11562 if (!found)
11563 {
11564 n = info->symtab_pos;
11565 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11566 n = private_data->last_mapping_sym;
11567
11568 /* No mapping symbol found at this address. Look backwards
11569 for a preceeding one, but don't go pass the section start
11570 otherwise a data section with no mapping symbol can pick up
11571 a text mapping symbol of a preceeding section. The documentation
11572 says section can be NULL, in which case we will seek up all the
11573 way to the top. */
11574 if (info->section)
11575 section_vma = info->section->vma;
11576
11577 for (; n >= 0; n--)
11578 {
11579 addr = bfd_asymbol_value (info->symtab[n]);
11580 if (addr < section_vma)
11581 break;
11582
11583 if (get_map_sym_type (info, n, &type))
11584 {
11585 last_sym = n;
11586 found = TRUE;
11587 break;
11588 }
11589 }
11590 }
11591 }
11592
11593 /* If no mapping symbol was found, try looking up without a mapping
11594 symbol. This is done by walking up from the current PC to the nearest
11595 symbol. We don't actually have to loop here since symtab_pos will
11596 contain the nearest symbol already. */
11597 if (!found)
5bc5ae88 11598 {
796d6298
TC		 11599 n = info->symtab_pos;
11600 if (n >= 0 && get_sym_code_type (info, n, &type))
5bc5ae88 11601 {
796d6298
TC		 11602 last_sym = n;
11603 found = TRUE;
5bc5ae88
RL		 11604 }
11605 }
11606
796d6298
TC		 11607 private_data->last_mapping_sym = last_sym;
11608 private_data->last_type = type;
11609 private_data->last_stop_offset = info->stop_offset;
5bc5ae88
RL		 11610
11611 *map_symbol = type;
11612 return found;
11613}
11614
0313a2b8
NC		 11615/* Given a bfd_mach_arm_XXX value, this function fills in the fields
11616 of the supplied arm_feature_set structure with bitmasks indicating
c0c468d5 11617 the supported base architectures and coprocessor extensions.
0313a2b8
NC		 11618
11619 FIXME: This could more efficiently implemented as a constant array,
11620 although it would also be less robust. */
11621
11622static void
11623select_arm_features (unsigned long mach,
11624 arm_feature_set * features)
11625{
c0c468d5
TP		 11626 arm_feature_set arch_fset;
11627 const arm_feature_set fpu_any = FPU_ANY;
11628
1af1dd51
MW		 11629#undef ARM_SET_FEATURES
11630#define ARM_SET_FEATURES(FSET) \
11631 { \
11632 const arm_feature_set fset = FSET; \
c0c468d5 11633 arch_fset = fset; \
1af1dd51 11634 }
823d2571 11635
c0c468d5
TP		 11636 /* When several architecture versions share the same bfd_mach_arm_XXX value
11637 the most featureful is chosen. */
0313a2b8
NC		 11638 switch (mach)
11639 {
c0c468d5
TP		 11640 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
11641 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
11642 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
11643 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
11644 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
11645 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
11646 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
11647 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
11648 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
11649 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
1af1dd51 11650 case bfd_mach_arm_ep9312:
c0c468d5
TP		 11651 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
11652 ARM_CEXT_MAVERICK | FPU_MAVERICK));
1af1dd51 11653 break;
c0c468d5
TP		 11654 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
11655 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
11656 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
11657 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
11658 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
11659 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
11660 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
11661 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
11662 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
11663 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
11664 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
11665 case bfd_mach_arm_8:
11666 {
aab2c27d
MM		 11667 /* Add bits for extensions that Armv8.6-A recognizes. */
11668 arm_feature_set armv8_6_ext_fset
0632eeea 11669 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
aab2c27d
MM		 11670 ARM_SET_FEATURES (ARM_ARCH_V8_6A);
11671 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_6_ext_fset);
c0c468d5
TP		 11672 break;
11673 }
11674 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
11675 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
11676 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
73cd51e5
AV		 11677 case bfd_mach_arm_8_1M_MAIN:
11678 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
11679 force_thumb = 1;
11680 break;
c0c468d5
TP		 11681 /* If the machine type is unknown allow all architecture types and all
11682 extensions. */
11683 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
0313a2b8
NC		 11684 default:
11685 abort ();
11686 }
1af1dd51 11687#undef ARM_SET_FEATURES
c0c468d5
TP		 11688
11689 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
11690 and thus on bfd_mach_arm_XXX value. Therefore for a given
11691 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
11692 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
0313a2b8
NC		 11693}
11694
11695
58efb6c0
NC		 11696/* NOTE: There are no checks in these routines that
11697 the relevant number of data bytes exist. */
baf0cc5e 11698
58efb6c0 11699static int
4a5329c6 11700print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 11701{
c19d1205
ZW		 11702 unsigned char b[4];
11703 long given;
11704 int status;
e821645d 11705 int is_thumb = FALSE;
b0e28b39 11706 int is_data = FALSE;
bd2e2557 11707 int little_code;
e821645d 11708 unsigned int size = 4;
4a5329c6 11709 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 11710 bfd_boolean found = FALSE;
b0e28b39 11711 struct arm_private_data *private_data;
58efb6c0 11712
dd92f639
NC		 11713 if (info->disassembler_options)
11714 {
65b48a81 11715 parse_arm_disassembler_options (info->disassembler_options);
b34976b6 11716
58efb6c0 11717 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 11718 info->disassembler_options = NULL;
11719 }
b34976b6 11720
0313a2b8
NC		 11721 /* PR 10288: Control which instructions will be disassembled. */
11722 if (info->private_data == NULL)
11723 {
b0e28b39 11724 static struct arm_private_data private;
0313a2b8
NC		 11725
11726 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
11727 /* If the user did not use the -m command line switch then default to
11728 disassembling all types of ARM instruction.
43e65147 11729
0313a2b8
NC		 11730 The info->mach value has to be ignored as this will be based on
11731 the default archictecture for the target and/or hints in the notes
11732 section, but it will never be greater than the current largest arm
11733 machine value (iWMMXt2), which is only equivalent to the V5TE
11734 architecture. ARM architectures have advanced beyond the machine
11735 value encoding, and these newer architectures would be ignored if
11736 the machine value was used.
11737
11738 Ie the -m switch is used to restrict which instructions will be
11739 disassembled. If it is necessary to use the -m switch to tell
11740 objdump that an ARM binary is being disassembled, eg because the
11741 input is a raw binary file, but it is also desired to disassemble
11742 all ARM instructions then use "-marm". This will select the
11743 "unknown" arm architecture which is compatible with any ARM
11744 instruction. */
11745 info->mach = bfd_mach_arm_unknown;
11746
11747 /* Compute the architecture bitmask from the machine number.
11748 Note: This assumes that the machine number will not change
11749 during disassembly.... */
b0e28b39 11750 select_arm_features (info->mach, & private.features);
0313a2b8 11751
1fbaefec
PB		 11752 private.last_mapping_sym = -1;
11753 private.last_mapping_addr = 0;
796d6298 11754 private.last_stop_offset = 0;
b0e28b39
DJ		 11755
11756 info->private_data = & private;
0313a2b8 11757 }
b0e28b39
DJ		 11758
11759 private_data = info->private_data;
11760
bd2e2557
SS		 11761 /* Decide if our code is going to be little-endian, despite what the
11762 function argument might say. */
11763 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
11764
b0e28b39
DJ		 11765 /* For ELF, consult the symbol table to determine what kind of code
11766 or data we have. */
8977d4b2 11767 if (info->symtab_size != 0
e821645d
DJ		 11768 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
11769 {
11770 bfd_vma addr;
796d6298 11771 int n;
e821645d 11772 int last_sym = -1;
b0e28b39 11773 enum map_type type = MAP_ARM;
e821645d 11774
796d6298
TC		 11775 found = mapping_symbol_for_insn (pc, info, &type);
11776 last_sym = private_data->last_mapping_sym;
e821645d 11777
1fbaefec
PB		 11778 is_thumb = (private_data->last_type == MAP_THUMB);
11779 is_data = (private_data->last_type == MAP_DATA);
b34976b6 11780
e821645d
DJ		 11781 /* Look a little bit ahead to see if we should print out
11782 two or four bytes of data. If there's a symbol,
11783 mapping or otherwise, after two bytes then don't
11784 print more. */
11785 if (is_data)
11786 {
11787 size = 4 - (pc & 3);
11788 for (n = last_sym + 1; n < info->symtab_size; n++)
11789 {
11790 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 11791 if (addr > pc
11792 && (info->section == NULL
11793 || info->section == info->symtab[n]->section))
e821645d
DJ		 11794 {
11795 if (addr - pc < size)
11796 size = addr - pc;
11797 break;
11798 }
11799 }
11800 /* If the next symbol is after three bytes, we need to
11801 print only part of the data, so that we can use either
11802 .byte or .short. */
11803 if (size == 3)
11804 size = (pc & 1) ? 1 : 2;
11805 }
11806 }
11807
11808 if (info->symbols != NULL)
252b5132 11809 {
5876e06d
NC		 11810 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
11811 {
2f0ca46a 11812 coff_symbol_type * cs;
b34976b6 11813
5876e06d
NC		 11814 cs = coffsymbol (*info->symbols);
11815 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
11816 || cs->native->u.syment.n_sclass == C_THUMBSTAT
11817 || cs->native->u.syment.n_sclass == C_THUMBLABEL
11818 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
11819 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
11820 }
e821645d
DJ		 11821 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
11822 && !found)
5876e06d 11823 {
2087ad84
PB		 11824 /* If no mapping symbol has been found then fall back to the type
11825 of the function symbol. */
e821645d
DJ		 11826 elf_symbol_type * es;
11827 unsigned int type;
2087ad84 11828
e821645d
DJ		 11829 es = *(elf_symbol_type **)(info->symbols);
11830 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 11831
39d911fc
TP		 11832 is_thumb =
11833 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
11834 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
5876e06d 11835 }
e49d43ff
TG		 11836 else if (bfd_asymbol_flavour (*info->symbols)
11837 == bfd_target_mach_o_flavour)
11838 {
11839 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
11840
11841 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
11842 }
5876e06d 11843 }
b34976b6 11844
e821645d
DJ		 11845 if (force_thumb)
11846 is_thumb = TRUE;
11847
b8f9ee44
CL		 11848 if (is_data)
11849 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
11850 else
11851 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
11852
c19d1205 11853 info->bytes_per_line = 4;
252b5132 11854
1316c8b3
NC		 11855 /* PR 10263: Disassemble data if requested to do so by the user. */
11856 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 11857 {
11858 int i;
11859
1316c8b3 11860 /* Size was already set above. */
e821645d
DJ		 11861 info->bytes_per_chunk = size;
11862 printer = print_insn_data;
11863
fe56b6ce 11864 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 11865 given = 0;
11866 if (little)
11867 for (i = size - 1; i >= 0; i--)
11868 given = b[i] | (given << 8);
11869 else
11870 for (i = 0; i < (int) size; i++)
11871 given = b[i] | (given << 8);
11872 }
11873 else if (!is_thumb)
252b5132 11874 {
c19d1205
ZW		 11875 /* In ARM mode endianness is a straightforward issue: the instruction
11876 is four bytes long and is either ordered 0123 or 3210. */
11877 printer = print_insn_arm;
11878 info->bytes_per_chunk = 4;
4a5329c6 11879 size = 4;
c19d1205 11880
0313a2b8 11881 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 11882 if (little_code)
c19d1205
ZW		 11883 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
11884 else
11885 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
252b5132 11886 }
58efb6c0 11887 else
252b5132 11888 {
c19d1205
ZW		 11889 /* In Thumb mode we have the additional wrinkle of two
11890 instruction lengths. Fortunately, the bits that determine
11891 the length of the current instruction are always to be found
11892 in the first two bytes. */
4a5329c6 11893 printer = print_insn_thumb16;
c19d1205 11894 info->bytes_per_chunk = 2;
4a5329c6
ZW		 11895 size = 2;
11896
fe56b6ce 11897 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 11898 if (little_code)
9a2ff3f5
AM		 11899 given = (b[0]) | (b[1] << 8);
11900 else
11901 given = (b[1]) | (b[0] << 8);
11902
c19d1205 11903 if (!status)
252b5132 11904 {
c19d1205
ZW		 11905 /* These bit patterns signal a four-byte Thumb
11906 instruction. */
11907 if ((given & 0xF800) == 0xF800
11908 || (given & 0xF800) == 0xF000
11909 || (given & 0xF800) == 0xE800)
252b5132 11910 {
0313a2b8 11911 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 11912 if (little_code)
c19d1205 11913 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 11914 else
c19d1205
ZW		 11915 given = (b[1]) | (b[0] << 8) | (given << 16);
11916
11917 printer = print_insn_thumb32;
4a5329c6 11918 size = 4;
252b5132 11919 }
252b5132 11920 }
c22aaad1
PB		 11921
11922 if (ifthen_address != pc)
0313a2b8 11923 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 11924
11925 if (ifthen_state)
11926 {
11927 if ((ifthen_state & 0xf) == 0x8)
11928 ifthen_next_state = 0;
11929 else
11930 ifthen_next_state = (ifthen_state & 0xe0)
11931 | ((ifthen_state & 0xf) << 1);
11932 }
252b5132 11933 }
b34976b6 11934
c19d1205
ZW		 11935 if (status)
11936 {
11937 info->memory_error_func (status, pc, info);
11938 return -1;
11939 }
6a56ec7e
NC		 11940 if (info->flags & INSN_HAS_RELOC)
11941 /* If the instruction has a reloc associated with it, then
11942 the offset field in the instruction will actually be the
11943 addend for the reloc. (We are using REL type relocs).
11944 In such cases, we can ignore the pc when computing
11945 addresses, since the addend is not currently pc-relative. */
11946 pc = 0;
b34976b6 11947
4a5329c6 11948 printer (pc, info, given);
c22aaad1
PB		 11949
11950 if (is_thumb)
11951 {
11952 ifthen_state = ifthen_next_state;
11953 ifthen_address += size;
11954 }
4a5329c6 11955 return size;
252b5132
RH		 11956}
11957
11958int
4a5329c6 11959print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 11960{
bd2e2557
SS		 11961 /* Detect BE8-ness and record it in the disassembler info. */
11962 if (info->flavour == bfd_target_elf_flavour
11963 && info->section != NULL
11964 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
11965 info->endian_code = BFD_ENDIAN_LITTLE;
11966
b34976b6 11967 return print_insn (pc, info, FALSE);
58efb6c0 11968}
01c7f630 11969
58efb6c0 11970int
4a5329c6 11971print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 11972{
b34976b6 11973 return print_insn (pc, info, TRUE);
58efb6c0 11974}
252b5132 11975
471b9d15 11976const disasm_options_and_args_t *
65b48a81
PB		 11977disassembler_options_arm (void)
11978{
471b9d15 11979 static disasm_options_and_args_t *opts_and_args;
65b48a81 11980
471b9d15 11981 if (opts_and_args == NULL)
65b48a81 11982 {
471b9d15 11983 disasm_options_t *opts;
65b48a81 11984 unsigned int i;
471b9d15
MR		 11985
11986 opts_and_args = XNEW (disasm_options_and_args_t);
11987 opts_and_args->args = NULL;
11988
11989 opts = &opts_and_args->options;
65b48a81
PB		 11990 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
11991 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
471b9d15 11992 opts->arg = NULL;
65b48a81
PB		 11993 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11994 {
11995 opts->name[i] = regnames[i].name;
11996 if (regnames[i].description != NULL)
11997 opts->description[i] = _(regnames[i].description);
11998 else
11999 opts->description[i] = NULL;
12000 }
12001 /* The array we return must be NULL terminated. */
12002 opts->name[i] = NULL;
12003 opts->description[i] = NULL;
12004 }
12005
471b9d15 12006 return opts_and_args;
65b48a81
PB		 12007}
12008
58efb6c0 12009void
4a5329c6 12010print_arm_disassembler_options (FILE *stream)
58efb6c0 12011{
65b48a81 12012 unsigned int i, max_len = 0;
58efb6c0
NC		 12013 fprintf (stream, _("\n\
12014The following ARM specific disassembler options are supported for use with\n\
12015the -M switch:\n"));
b34976b6 12016
65b48a81
PB		 12017 for (i = 0; i < NUM_ARM_OPTIONS; i++)
12018 {
12019 unsigned int len = strlen (regnames[i].name);
12020 if (max_len < len)
12021 max_len = len;
12022 }
58efb6c0 12023
65b48a81
PB		 12024 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
12025 fprintf (stream, " %s%*c %s\n",
12026 regnames[i].name,
12027 (int)(max_len - strlen (regnames[i].name)), ' ',
12028 _(regnames[i].description));
252b5132 12029}
GDB Binutils - Deliverables
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