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gdbserver: fix uClibc build whithout MMU.
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
CommitLineData
252b5132 1/* Instruction printing code for the ARM
b90efa5b 2 Copyright (C) 1994-2015 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
2fbad815 24
252b5132 25#include "dis-asm.h"
2fbad815 26#include "opcode/arm.h"
252b5132 27#include "opintl.h"
31e0f3cd 28#include "safe-ctype.h"
0dbde4cf 29#include "floatformat.h"
252b5132 30
baf0cc5e 31/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 32#include "coff/internal.h"
33#include "libcoff.h"
252b5132
RH		 34#include "elf-bfd.h"
35#include "elf/internal.h"
36#include "elf/arm.h"
37
6b5d3a4d 38/* FIXME: Belongs in global header. */
01c7f630 39#ifndef strneq
58efb6c0
NC		 40#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
41#endif
42
43#ifndef NUM_ELEM
44#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
01c7f630
NC		 45#endif
46
1fbaefec
PB		 47/* Cached mapping symbol state. */
48enum map_type
49{
50 MAP_ARM,
51 MAP_THUMB,
52 MAP_DATA
53};
54
b0e28b39
DJ		 55struct arm_private_data
56{
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features;
59
60 /* Whether any mapping symbols are present in the provided symbol
61 table. -1 if we do not know yet, otherwise 0 or 1. */
62 int has_mapping_symbols;
1fbaefec
PB		 63
64 /* Track the last type (although this doesn't seem to be useful) */
65 enum map_type last_type;
66
67 /* Tracking symbol table information */
68 int last_mapping_sym;
69 bfd_vma last_mapping_addr;
b0e28b39
DJ		 70};
71
6b5d3a4d
ZW		 72struct opcode32
73{
823d2571
TG		 74 arm_feature_set arch; /* Architecture defining this insn. */
75 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 76 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 77 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 78};
79
80struct opcode16
81{
823d2571 82 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 83 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 84 const char *assembler; /* How to disassemble this insn. */
85};
b7693d02 86
8f06b2d8 87/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 88
2fbad815 89 %% %
4a5329c6 90
c22aaad1 91 %c print condition code (always bits 28-31 in ARM mode)
37b37b2d 92 %q print shifter argument
e2efe87d
MGD		 93 %u print condition code (unconditional in ARM mode,
94 UNPREDICTABLE if not AL in Thumb)
4a5329c6 95 %A print address for ldc/stc/ldf/stf instruction
16980d0b 96 %B print vstm/vldm register list
4a5329c6 97 %I print cirrus signed shift immediate: bits 0..3|4..6
4a5329c6
ZW		 98 %F print the COUNT field of a LFM/SFM instruction.
99 %P print floating point precision in arithmetic insn
100 %Q print floating point precision in ldf/stf insn
101 %R print floating point rounding mode
102
33399f07 103 %<bitfield>c print as a condition code (for vsel)
4a5329c6 104 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 105 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
106 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 107 %<bitfield>d print the bitfield in decimal
16980d0b 108 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 109 %<bitfield>x print the bitfield in hex
110 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 111 %<bitfield>f print a floating point constant if >7 else a
112 floating point register
4a5329c6
ZW		 113 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
114 %<bitfield>g print as an iWMMXt 64-bit register
115 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 116 %<bitfield>D print as a NEON D register
117 %<bitfield>Q print as a NEON Q register
4a5329c6 118
16980d0b 119 %y<code> print a single precision VFP reg.
2fbad815 120 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 121 %z<code> print a double precision VFP reg
2fbad815 122 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 123
16980d0b
JB		 124 %<bitfield>'c print specified char iff bitfield is all ones
125 %<bitfield>`c print specified char iff bitfield is all zeroes
126 %<bitfield>?ab... select from array of values in big endian order
127
2fbad815 128 %L print as an iWMMXt N/M width field.
4a5329c6 129 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 130 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 131 versions.
132 %i print 5-bit immediate in bits 8,3..0
133 (print "32" when 0)
fe56b6ce 134 %r print register offset address for wldt/wstr instruction. */
2fbad815 135
21d799b5 136enum opcode_sentinel_enum
05413229
NC		 137{
138 SENTINEL_IWMMXT_START = 1,
139 SENTINEL_IWMMXT_END,
140 SENTINEL_GENERIC_START
141} opcode_sentinels;
142
aefd8a40 143#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
c1e26897 144#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 145
8f06b2d8 146/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 147
8f06b2d8 148static const struct opcode32 coprocessor_opcodes[] =
2fbad815 149{
2fbad815 150 /* XScale instructions. */
823d2571
TG		 151 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
152 0x0e200010, 0x0fff0ff0,
153 "mia%c\tacc0, %0-3r, %12-15r"},
154 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
155 0x0e280010, 0x0fff0ff0,
156 "miaph%c\tacc0, %0-3r, %12-15r"},
157 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
158 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
159 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
160 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
161 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
162 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 163
2fbad815 164 /* Intel Wireless MMX technology instructions. */
823d2571
TG		 165 {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
166 {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
167 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
168 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
169 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
170 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
171 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
172 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
173 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
174 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
175 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
176 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
177 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
178 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
179 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
180 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
181 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
182 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
183 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
184 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
185 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
186 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
187 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
188 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
189 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
190 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
191 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
192 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
193 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
194 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
195 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
196 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
197 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
198 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
199 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
200 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
201 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
202 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
203 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
204 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
205 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
206 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
207 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
208 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
209 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
210 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
211 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
212 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
213 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
214 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
215 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
216 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
217 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
218 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
219 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
220 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
221 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
222 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
223 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
224 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
225 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
226 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
227 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
228 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
229 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
230 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
231 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
232 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
233 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
234 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
235 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
236 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
237 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
238 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
239 0x0e800120, 0x0f800ff0,
240 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
241 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
242 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
243 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
244 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
245 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
246 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
247 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
248 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
249 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
250 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
251 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
252 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
253 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
254 0x0e8000a0, 0x0f800ff0,
255 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
256 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
257 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
258 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
259 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
260 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
261 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
262 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
263 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
264 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
265 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
266 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
267 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
268 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
269 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
270 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
271 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
272 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
273 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
274 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
275 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
276 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
277 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
278 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
279 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
280 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
281 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
282 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
283 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
284 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
285 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
286 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
287 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
288 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
289 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
290 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
291 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
292 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
293 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
294 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
295 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
296 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
297 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
298 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
299 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
300 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
301 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
302 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
303 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
304 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
305 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
306 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
307 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
308 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
309 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
310 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
311 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
312 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
313 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
314 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
315 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
316 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
317 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
318 {ARM_FEATURE_CORE_LOW (0),
319 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 320
fe56b6ce 321 /* Floating point coprocessor (FPA) instructions. */
823d2571
TG		 322 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
323 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
324 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
325 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
326 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
327 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
328 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
329 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
330 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
331 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
332 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
333 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
334 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
335 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
336 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
337 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
338 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
339 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
340 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
341 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
342 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
343 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
344 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
345 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
346 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
347 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
348 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
349 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
350 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
351 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
352 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
353 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
354 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
355 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
356 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
357 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
358 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
359 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
360 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
361 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
362 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
363 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
364 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
365 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
366 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
367 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
368 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
369 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
370 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
371 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
372 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
373 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
374 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
375 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
376 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
377 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
378 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
379 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
380 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
381 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
382 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
383 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
384 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
385 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
386 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
387 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
388 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
389 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
390 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
391 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
392 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
393 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
394 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
395 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
396 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
397 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
398 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
399 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
400 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
401 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
402 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
403 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
404 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
405 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
406 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
407 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 408
fe56b6ce 409 /* Register load/store. */
823d2571
TG		 410 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
411 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
412 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
413 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
414 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
415 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
416 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
417 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
418 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
419 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
420 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
421 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
422 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
423 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
424 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
425 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
426 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
427 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
428 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
429 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
430 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
431 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
432 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
433 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
434 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
435 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
436 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
437 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
438 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
439 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
440 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
441 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
442
443 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
444 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
445 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
446 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
447 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
448 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
449 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
450 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 451
fe56b6ce 452 /* Data transfer between ARM and NEON registers. */
823d2571
TG		 453 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
454 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
456 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
457 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
458 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
459 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
460 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
462 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
464 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
466 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
468 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
470 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
472 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
474 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
476 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
478 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
480 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 481 /* Half-precision conversion instructions. */
823d2571
TG		 482 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
483 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
484 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
485 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
486 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
487 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
488 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
489 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 490
fe56b6ce 491 /* Floating point coprocessor (VFP) instructions. */
823d2571
TG		 492 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
493 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
494 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
495 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
496 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
497 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
498 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
499 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
500 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
501 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
502 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
503 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
504 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
505 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
506 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
507 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
508 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
509 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
510 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
511 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
512 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
513 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
514 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
515 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
516 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
517 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
518 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
519 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
520 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
521 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
522 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
523 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
524 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
525 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
526 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
527 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
528 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
529 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
530 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
531 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
532 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
533 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
534 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
535 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
536 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
537 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
538 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
539 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
540 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
541 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
542 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
543 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
544 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
545 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
546 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
547 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
548 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
549 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
550 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
551 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
552 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
553 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
554 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
555 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
556 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
557 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
558 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
559 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
560 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
561 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
562 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
563 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
564 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
565 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
566 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
567 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
568 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
569 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
570 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
571 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
572 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
573 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
574 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
575 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
576 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
577 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
578 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
579 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
580 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
581 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19d"},
582 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
583 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19d"},
584 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
585 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
586 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
587 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
588 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
589 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
590 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
591 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
592 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
593 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
594 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
595 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
596 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
597 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
598 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
599 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
600 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
601 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
602 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
603 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
604 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
605 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
606 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
607 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
608 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
609 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
610 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
611 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
612 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
613 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
614 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
615 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
616 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
617 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
618 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
619 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
620 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
621 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
622 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
623 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
624 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
625 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 626
627 /* Cirrus coprocessor instructions. */
823d2571
TG		 628 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
629 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
630 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
631 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
632 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
633 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
634 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
635 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
636 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
637 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
638 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
639 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
640 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
641 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
642 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
643 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
644 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
645 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
646 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
647 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
648 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
649 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
650 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
651 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
652 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
653 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
654 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
655 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
656 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
657 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
658 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
659 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
660 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
661 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
662 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
663 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
664 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
665 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
666 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
667 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
668 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
669 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
670 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
671 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
672 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
673 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
674 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
675 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
676 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
677 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
678 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
679 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
680 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
681 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
682 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
683 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
684 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
685 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
686 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
687 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
688 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
689 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
690 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
691 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
692 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
693 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
694 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
695 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
696 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
697 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
698 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
699 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
700 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
701 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
702 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
703 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
704 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
705 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
706 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
707 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
708 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
709 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
710 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
711 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
712 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
713 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
714 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
715 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
716 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
717 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
718 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
719 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
720 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
721 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
722 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
723 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
724 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
725 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
726 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
727 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
728 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
729 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
730 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
731 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
732 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
733 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
734 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
735 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
736 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
737 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
738 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
739 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
740 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
741 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
742 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
743 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
744 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
745 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
746 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
747 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
748 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
749 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
750 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
751 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
752 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
753 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
754 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
755 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
756 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
757 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
758 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
759 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
760 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
761 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
762 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
763 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
764 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
765 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
766 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
767 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
768 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
769 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
770 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
771 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
772 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
773 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
774 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
775 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
776 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
777 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
778 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
779 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
780 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
781 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
782 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
783 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
784 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
785 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
786 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
787 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
788 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
789 0x0e000600, 0x0ff00f10,
790 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
791 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
792 0x0e100600, 0x0ff00f10,
793 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
794 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
795 0x0e200600, 0x0ff00f10,
796 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
797 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
798 0x0e300600, 0x0ff00f10,
799 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 800
62f3b8c8 801 /* VFP Fused multiply add instructions. */
823d2571
TG		 802 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
803 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
804 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
805 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
806 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
807 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
808 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
809 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
810 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
811 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
812 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
813 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
814 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
815 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
816 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
817 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 818
33399f07 819 /* FP v5. */
823d2571
TG		 820 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
821 0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
822 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823 0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
824 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
825 0xfe800a00, 0xffb00f40, "vmaxnm%u.f32\t%y1, %y2, %y0"},
826 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
827 0xfe800b00, 0xffb00f40, "vmaxnm%u.f64\t%z1, %z2, %z0"},
828 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
829 0xfe800a40, 0xffb00f40, "vminnm%u.f32\t%y1, %y2, %y0"},
830 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
831 0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"},
832 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
833 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
834 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
835 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
836 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
837 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
838 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
839 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
840 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
841 0xfeb80a40, 0xffbc0f50, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
842 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
843 0xfeb80b40, 0xffbc0f50, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 844
05413229 845 /* Generic coprocessor instructions. */
823d2571
TG		 846 {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
848 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
850 0x0c500000, 0x0ff00000,
851 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
853 0x0e000000, 0x0f000010,
854 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
856 0x0e10f010, 0x0f10f010,
857 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
859 0x0e100010, 0x0f100010,
860 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
862 0x0e000010, 0x0f100010,
863 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
865 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
867 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
2fbad815 868
05413229 869 /* V6 coprocessor instructions. */
823d2571
TG		 870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
871 0xfc500000, 0xfff00000,
872 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
874 0xfc400000, 0xfff00000,
875 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
8f06b2d8 876
05413229 877 /* V5 coprocessor instructions. */
823d2571
TG		 878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
879 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
881 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
883 0xfe000000, 0xff000010,
884 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
886 0xfe000010, 0xff100010,
887 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
889 0xfe100010, 0xff100010,
890 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
891
892 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 893};
894
16980d0b
JB		 895/* Neon opcode table: This does not encode the top byte -- that is
896 checked by the print_insn_neon routine, as it depends on whether we are
897 doing thumb32 or arm32 disassembly. */
898
899/* print_insn_neon recognizes the following format control codes:
900
901 %% %
902
c22aaad1 903 %c print condition code
e2efe87d
MGD		 904 %u print condition code (unconditional in ARM mode,
905 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 906 %A print v{st,ld}[1234] operands
907 %B print v{st,ld}[1234] any one operands
908 %C print v{st,ld}[1234] single->all operands
909 %D print scalar
910 %E print vmov, vmvn, vorr, vbic encoded constant
911 %F print vtbl,vtbx register list
912
913 %<bitfield>r print as an ARM register
914 %<bitfield>d print the bitfield in decimal
915 %<bitfield>e print the 2^N - bitfield in decimal
916 %<bitfield>D print as a NEON D register
917 %<bitfield>Q print as a NEON Q register
918 %<bitfield>R print as a NEON D or Q register
919 %<bitfield>Sn print byte scaled width limited by n
920 %<bitfield>Tn print short scaled width limited by n
921 %<bitfield>Un print long scaled width limited by n
922
923 %<bitfield>'c print specified char iff bitfield is all ones
924 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 925 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 926
927static const struct opcode32 neon_opcodes[] =
928{
fe56b6ce 929 /* Extract. */
823d2571
TG		 930 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
931 0xf2b00840, 0xffb00850,
932 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
933 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
934 0xf2b00000, 0xffb00810,
935 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 936
fe56b6ce 937 /* Move data element to all lanes. */
823d2571
TG		 938 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
939 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
940 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
941 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
942 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
943 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 944
fe56b6ce 945 /* Table lookup. */
823d2571
TG		 946 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
947 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
948 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
949 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
950
8e79c3df 951 /* Half-precision conversions. */
823d2571
TG		 952 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
953 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
954 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
955 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 956
957 /* NEON fused multiply add instructions. */
823d2571
TG		 958 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
959 0xf2000c10, 0xffa00f10, "vfma%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
960 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
961 0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 962
fe56b6ce 963 /* Two registers, miscellaneous. */
823d2571
TG		 964 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
965 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
966 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
967 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
968 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
969 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
970 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
971 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
972 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
973 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
974 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
975 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
976 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
977 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
978 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
979 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
980 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
981 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
982 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
983 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
984 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
985 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
986 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
987 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
988 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
989 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
990 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
991 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
992 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
993 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
994 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
995 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
996 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
997 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
998 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
999 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1000 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1001 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1002 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1003 0xf3b20300, 0xffb30fd0,
1004 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1005 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1006 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1007 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1008 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1009 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1010 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1011 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1012 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1013 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1014 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1015 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1016 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1017 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1018 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1019 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1020 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1021 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1022 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1023 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1024 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1025 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1026 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1027 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1028 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1029 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1030 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1031 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1032 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1033 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1034 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1035 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1036 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1037 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1038 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1039 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1040 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1041 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1042 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1043 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1044 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1045 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1046 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1047 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1048 0xf3b30600, 0xffb30e10,
1049 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
16980d0b 1050
fe56b6ce 1051 /* Three registers of the same length. */
823d2571
TG		 1052 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1053 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1054 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1055 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1056 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1057 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1058 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1059 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1060 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1061 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1062 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1063 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1064 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1065 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1066 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1067 0xf3000f10, 0xffa00f10, "vmaxnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1068 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1069 0xf3200f10, 0xffa00f10, "vminnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1070 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1071 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1072 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1073 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1074 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1075 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1076 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1077 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1078 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1079 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1080 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1081 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1082 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1083 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1084 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1085 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1086 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1087 0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1088 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1089 0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1090 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1091 0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1092 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1093 0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1094 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1095 0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1096 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1097 0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1098 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1099 0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1100 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1101 0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1102 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1103 0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1104 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1105 0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1106 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1107 0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1108 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1109 0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1110 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1111 0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1112 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1113 0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1114 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1115 0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1116 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1117 0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1118 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1119 0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1120 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1121 0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
1122 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1123 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1124 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1125 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1126 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1127 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1128 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1129 0xf2000b00, 0xff800f10,
1130 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1131 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1132 0xf2000b10, 0xff800f10,
1133 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1134 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1135 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1136 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1137 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1138 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1139 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1140 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1141 0xf3000b00, 0xff800f10,
1142 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1143 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1144 0xf2000000, 0xfe800f10,
1145 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1146 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1147 0xf2000010, 0xfe800f10,
1148 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1149 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1150 0xf2000100, 0xfe800f10,
1151 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1152 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1153 0xf2000200, 0xfe800f10,
1154 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1155 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1156 0xf2000210, 0xfe800f10,
1157 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1158 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1159 0xf2000300, 0xfe800f10,
1160 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1161 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1162 0xf2000310, 0xfe800f10,
1163 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1164 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1165 0xf2000400, 0xfe800f10,
1166 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1167 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1168 0xf2000410, 0xfe800f10,
1169 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1170 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1171 0xf2000500, 0xfe800f10,
1172 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1173 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1174 0xf2000510, 0xfe800f10,
1175 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1176 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1177 0xf2000600, 0xfe800f10,
1178 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1179 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1180 0xf2000610, 0xfe800f10,
1181 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1182 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1183 0xf2000700, 0xfe800f10,
1184 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1185 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1186 0xf2000710, 0xfe800f10,
1187 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1188 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1189 0xf2000910, 0xfe800f10,
1190 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1191 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1192 0xf2000a00, 0xfe800f10,
1193 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1194 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1195 0xf2000a10, 0xfe800f10,
1196 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1197
fe56b6ce 1198 /* One register and an immediate value. */
823d2571
TG		 1199 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1200 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1201 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1202 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1203 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1204 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1205 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1206 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1207 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1208 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1209 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1210 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1211 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1212 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1213 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1214 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1215 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1216 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1217 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1218 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1219 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1220 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1221 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1222 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1223 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1224 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1225
fe56b6ce 1226 /* Two registers and a shift amount. */
823d2571
TG		 1227 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1228 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1229 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1230 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1231 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1232 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1233 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1234 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1235 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1236 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1237 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1238 0xf2880950, 0xfeb80fd0,
1239 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1240 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1241 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1242 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1243 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1244 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1245 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1246 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1247 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1248 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1249 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1250 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1251 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1252 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1253 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1254 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1255 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1256 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1257 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1258 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1259 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1260 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1261 0xf2900950, 0xfeb00fd0,
1262 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1263 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1264 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1265 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1266 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1267 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1268 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1269 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1270 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1271 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1272 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1273 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1274 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1275 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1276 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1277 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1278 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1279 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1280 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1281 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1282 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1283 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1284 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1285 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1286 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1287 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1288 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1289 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1290 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1291 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1292 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1293 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1294 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1295 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1296 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1297 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1298 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1299 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1300 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1301 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1302 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1303 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1304 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1305 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1306 0xf2a00950, 0xfea00fd0,
1307 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1308 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1309 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1310 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1311 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1312 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1313 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1314 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1315 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1316 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1317 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1318 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1319 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1320 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1321 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1322 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1323 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1324 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1325 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1326 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1327 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1328 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1329 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1330 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1331 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1332 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1333 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1334 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1335 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1336 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1337 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1338 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1339 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1340 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1341 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1342 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1343 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1344 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1345 0xf2a00e10, 0xfea00e90,
1346 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 1347
fe56b6ce 1348 /* Three registers of different lengths. */
823d2571
TG		 1349 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1350 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1351 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1352 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1353 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1354 0xf2800400, 0xff800f50,
1355 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1356 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1357 0xf2800600, 0xff800f50,
1358 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1359 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1360 0xf2800900, 0xff800f50,
1361 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1362 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1363 0xf2800b00, 0xff800f50,
1364 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1365 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1366 0xf2800d00, 0xff800f50,
1367 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1368 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1369 0xf3800400, 0xff800f50,
1370 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1371 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1372 0xf3800600, 0xff800f50,
1373 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1374 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1375 0xf2800000, 0xfe800f50,
1376 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1377 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1378 0xf2800100, 0xfe800f50,
1379 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1380 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1381 0xf2800200, 0xfe800f50,
1382 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1383 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1384 0xf2800300, 0xfe800f50,
1385 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1386 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1387 0xf2800500, 0xfe800f50,
1388 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1389 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1390 0xf2800700, 0xfe800f50,
1391 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1392 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1393 0xf2800800, 0xfe800f50,
1394 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1395 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1396 0xf2800a00, 0xfe800f50,
1397 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1398 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1399 0xf2800c00, 0xfe800f50,
1400 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 1401
fe56b6ce 1402 /* Two registers and a scalar. */
823d2571
TG		 1403 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1404 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1405 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1406 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1407 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1408 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1409 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1410 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1411 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1412 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1413 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1414 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1415 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1416 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1417 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1418 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1419 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1420 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1421 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1422 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1423 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1424 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1425 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1426 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1427 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1428 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1429 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1430 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1431 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1432 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1433 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1434 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1435 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1436 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1437 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1438 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1439 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1440 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1441 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1442 0xf2800240, 0xfe800f50,
1443 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1444 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1445 0xf2800640, 0xfe800f50,
1446 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1447 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1448 0xf2800a40, 0xfe800f50,
1449 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
16980d0b 1450
fe56b6ce 1451 /* Element and structure load/store. */
823d2571
TG		 1452 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1453 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1454 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1455 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1456 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1457 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1458 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1459 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1460 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1461 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1462 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1463 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1465 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1466 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1467 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1468 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1469 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1470 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1471 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1473 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1474 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1475 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1477 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1478 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1479 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1481 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1482 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1483 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1484 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1485 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1487 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1489 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1490
1491 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 1492};
1493
8f06b2d8
PB		 1494/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
1495 ordered: they must be searched linearly from the top to obtain a correct
1496 match. */
1497
1498/* print_insn_arm recognizes the following format control codes:
1499
1500 %% %
1501
1502 %a print address for ldr/str instruction
1503 %s print address for ldr/str halfword/signextend instruction
c1e26897 1504 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 1505 %b print branch destination
1506 %c print condition code (always bits 28-31)
1507 %m print register mask for ldm/stm instruction
1508 %o print operand2 (immediate or register + shift)
1509 %p print 'p' iff bits 12-15 are 15
1510 %t print 't' iff bit 21 set and bit 24 clear
1511 %B print arm BLX(1) destination
1512 %C print the PSR sub type.
62b3e311
PB		 1513 %U print barrier type.
1514 %P print address for pli instruction.
8f06b2d8
PB		 1515
1516 %<bitfield>r print as an ARM register
9eb6c0f1 1517 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 1518 %<bitfield>R as %r but r15 is UNPREDICTABLE
1519 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1520 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8
PB		 1521 %<bitfield>d print the bitfield in decimal
1522 %<bitfield>W print the bitfield plus one in decimal
1523 %<bitfield>x print the bitfield in hex
1524 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
16980d0b
JB		 1525
1526 %<bitfield>'c print specified char iff bitfield is all ones
1527 %<bitfield>`c print specified char iff bitfield is all zeroes
1528 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 1529
8f06b2d8
PB		 1530 %e print arm SMI operand (bits 0..7,8..19).
1531 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 1532 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
1533 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 1534
8f06b2d8
PB		 1535static const struct opcode32 arm_opcodes[] =
1536{
1537 /* ARM instructions. */
823d2571
TG		 1538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1539 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1541 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1542
1543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
1544 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1545 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1546 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1548 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
1550 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1552 0x00800090, 0x0fa000f0,
1553 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1555 0x00a00090, 0x0fa000f0,
1556 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 1557
53c4b28b 1558 /* V8 instructions. */
823d2571
TG		 1559 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1560 0x0320f005, 0x0fffffff, "sevl"},
1561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1562 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
1563 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1564 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
1565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1566 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1568 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1570 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
1571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1572 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
1573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1574 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
1575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1576 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
1577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1578 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
1579 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1580 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
1581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1582 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
1583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1584 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
1585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1586 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
1587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1588 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
1589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1590 0x01f00c9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
dd5181d5 1591 /* CRC32 instructions. */
823d2571
TG		 1592 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1593 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
1594 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1595 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
1596 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1597 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
1598 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1599 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
1600 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1601 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
1602 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1603 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 1604
90ec0d68 1605 /* Virtualization Extension instructions. */
823d2571
TG		 1606 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
1607 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 1608
eea54501 1609 /* Integer Divide Extension instructions. */
823d2571
TG		 1610 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1611 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1612 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1613 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 1614
60e5ef9f 1615 /* MP Extension instructions. */
823d2571 1616 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 1617
62b3e311 1618 /* V7 instructions. */
823d2571
TG		 1619 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
1620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
1622 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
1623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
62b3e311 1626
c19d1205 1627 /* ARM V6T2 instructions. */
823d2571
TG		 1628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1629 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1631 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1633 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1635 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
1636
1637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1638 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
1639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1640 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1641
1642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1643 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
1644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1645 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1647 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1649 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 1650
f4c65163 1651 /* ARM Security extension instructions. */
823d2571
TG		 1652 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
1653 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 1654
8f06b2d8 1655 /* ARM V6K instructions. */
823d2571
TG		 1656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1657 0xf57ff01f, 0xffffffff, "clrex"},
1658 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1659 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1661 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1663 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1665 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1667 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1669 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 1670
8f06b2d8 1671 /* ARM V6K NOP hints. */
823d2571
TG		 1672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1673 0x0320f001, 0x0fffffff, "yield%c"},
1674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1675 0x0320f002, 0x0fffffff, "wfe%c"},
1676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1677 0x0320f003, 0x0fffffff, "wfi%c"},
1678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1679 0x0320f004, 0x0fffffff, "sev%c"},
1680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1681 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 1682
fe56b6ce 1683 /* ARM V6 instructions. */
823d2571
TG		 1684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1685 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
1686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1687 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
1688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1689 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
1690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1691 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
1692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1693 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
1694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1695 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
1696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1697 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
1698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1699 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
1700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1701 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
1702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1703 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
1704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1705 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
1706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1707 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
1708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1709 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
1710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1711 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
1712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1713 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
1714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1715 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
1716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1717 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
1718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1719 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
1720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1721 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
1722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1723 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
1724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1725 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
1726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1727 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
1728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1729 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
1730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1731 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
1732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1733 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
1734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1735 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
1736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1737 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
1738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1739 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
1740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1741 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
1742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1743 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
1744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1745 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
1746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1747 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
1748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1749 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
1750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1751 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
1752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1753 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
1754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1755 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
1756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1757 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
1758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1759 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
1760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1761 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
1762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1763 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
1764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1765 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
1766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1767 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
1768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1769 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
1770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1771 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
1772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1773 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
1774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1775 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
1776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1777 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
1778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1779 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
1780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1781 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
1782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1783 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
1784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1785 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
1786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1787 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
1788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1789 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
1790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1791 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
1792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1793 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
1794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1795 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
1796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1797 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
1798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1799 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
1800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1801 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
1802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1803 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
1804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1805 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
1806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1807 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
1808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1809 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
1810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1811 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
1812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1813 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
1814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1815 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
1816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1817 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
1818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1819 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
1820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1821 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
1822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1823 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
1824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1825 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
1826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1827 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
1828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1829 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
1830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1831 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
1832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1833 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
1834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1835 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1837 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1839 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1841 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
1842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1843 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1845 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1847 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1849 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
1850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1851 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1853 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1855 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1857 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
1858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1859 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1861 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1863 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1865 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
1866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1867 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1869 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1871 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
1872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1873 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
1874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1875 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1877 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1879 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1881 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
1882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1883 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
1884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1885 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
1886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1887 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
1888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1889 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1891 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1893 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1895 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1897 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
1898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1899 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1901 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1903 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
1904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1905 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
1906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1907 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
1908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1909 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
1910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1911 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
1912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1913 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
1914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1915 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
1916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1917 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
1918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1919 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1921 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
1922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1923 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
1924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1925 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
1926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1927 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 1928
8f06b2d8 1929 /* V5J instruction. */
823d2571
TG		 1930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
1931 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 1932
8f06b2d8 1933 /* V5 Instructions. */
823d2571
TG		 1934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1935 0xe1200070, 0xfff000f0,
1936 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
1937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1938 0xfa000000, 0xfe000000, "blx\t%B"},
1939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1940 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
1941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1942 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
1943
1944 /* V5E "El Segundo" Instructions. */
1945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1946 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
1947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1948 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
1949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1950 0xf450f000, 0xfc70f000, "pld\t%a"},
1951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1952 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1954 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1956 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1958 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
1959
1960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1961 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1963 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
1964
1965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1966 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1968 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1970 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1972 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1973
1974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1975 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
1976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1977 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
1978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1979 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
1980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1981 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
1982
1983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1984 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
1985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1986 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
1987
1988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1989 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
1990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1991 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
1992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1993 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
1994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
1995 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 1996
8f06b2d8 1997 /* ARM Instructions. */
823d2571
TG		 1998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1999 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2000
2001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2002 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2004 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2006 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2008 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2010 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2012 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2013
2014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2015 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2017 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2019 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2021 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2022
2023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2024 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2026 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2028 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2030 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2031
2032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2033 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2035 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2037 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2038
2039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2040 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2042 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2044 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2045
2046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2047 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2049 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2051 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2052
2053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2054 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2056 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2058 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2059
2060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2061 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2063 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2065 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2066
2067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2068 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2070 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2072 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2073
2074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2075 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2077 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2079 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2080
2081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2082 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2084 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2086 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2087
2088 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2089 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2091 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2093 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2094
2095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2096 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2098 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2100 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2101
2102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2103 0x03200000, 0x0fe00000, "teq%p%c\t%16-19r, %o"},
2104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2105 0x01200000, 0x0fe00010, "teq%p%c\t%16-19r, %o"},
2106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2107 0x01200010, 0x0fe00090, "teq%p%c\t%16-19R, %o"},
2108
2109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2110 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2112 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2114 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2115
2116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2117 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2119 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2121 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2122
2123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2124 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2126 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2128 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2129
2130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2131 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2133 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2135 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2137 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2139 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2141 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2143 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2144
2145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2146 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2148 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2150 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2151
2152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2153 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2155 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2157 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2158
2159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2160 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2162 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2163
2164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2165 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2166
2167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2168 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2170 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2171
2172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2173 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2175 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2177 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2179 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2181 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2183 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2185 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2187 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2189 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2191 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2193 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2195 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2196 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2197 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2199 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2201 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2203 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2205 0x092d0000, 0x0fff0000, "push%c\t%m"},
2206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2207 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2209 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2210
2211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2212 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2214 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2216 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2217 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2218 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2220 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2222 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2224 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2226 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2228 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2230 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2232 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2234 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2236 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2238 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2240 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2242 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2244 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2246 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2248 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2249
2250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2251 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2252 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2253 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 2254
2255 /* The rest. */
823d2571
TG		 2256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2257 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2258 {ARM_FEATURE_CORE_LOW (0),
2259 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 2260};
2261
2262/* print_insn_thumb16 recognizes the following format control codes:
2263
2264 %S print Thumb register (bits 3..5 as high number if bit 6 set)
2265 %D print Thumb register (bits 0..2 as high number if bit 7 set)
2266 %<bitfield>I print bitfield as a signed decimal
2267 (top bit of range being the sign bit)
2268 %N print Thumb register mask (with LR)
2269 %O print Thumb register mask (with PC)
2270 %M print Thumb register mask
2271 %b print CZB's 6-bit unsigned branch destination
2272 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 2273 %c print the condition code
2274 %C print the condition code, or "s" if not conditional
2275 %x print warning if conditional an not at end of IT block"
2276 %X print "\t; unpredictable <IT:code>" if conditional
2277 %I print IT instruction suffix and operands
4547cb56 2278 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 2279 %<bitfield>r print bitfield as an ARM register
2280 %<bitfield>d print bitfield as a decimal
2281 %<bitfield>H print (bitfield * 2) as a decimal
2282 %<bitfield>W print (bitfield * 4) as a decimal
2283 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
2284 %<bitfield>B print Thumb branch destination (signed displacement)
2285 %<bitfield>c print bitfield as a condition code
2286 %<bitnum>'c print specified char iff bit is one
2287 %<bitnum>?ab print a if bit is one else print b. */
2288
2289static const struct opcode16 thumb_opcodes[] =
2290{
2291 /* Thumb instructions. */
2292
53c4b28b 2293 /* ARM V8 instructions. */
823d2571
TG		 2294 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
2295 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
53c4b28b 2296
8f06b2d8 2297 /* ARM V6K no-argument instructions. */
823d2571
TG		 2298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2299 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2301 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2302 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 2304
2305 /* ARM V6T2 instructions. */
823d2571
TG		 2306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2307 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
2308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 2309
2310 /* ARM V6. */
823d2571
TG		 2311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2315 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2317 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 2322
2323 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 2324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2325 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 2326 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 2327 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2328 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 2329 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 2330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2331 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 2332 /* Format 4. */
823d2571
TG		 2333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2339 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2341 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2343 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2345 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 2349 /* format 13 */
823d2571
TG		 2350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 2352 /* format 5 */
823d2571
TG		 2353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
2354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
2355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 2357 /* format 14 */
823d2571
TG		 2358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
2359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 2360 /* format 2 */
823d2571
TG		 2361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2362 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2364 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2366 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2368 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 2369 /* format 8 */
823d2571
TG		 2370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2371 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2373 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2375 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2376 /* format 7 */
823d2571
TG		 2377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2378 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2380 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2381 /* format 1 */
823d2571
TG		 2382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2384 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 2387 /* format 3 */
823d2571
TG		 2388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 2392 /* format 6 */
823d2571
TG		 2393 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2395 0x4800, 0xF800,
2396 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 2397 /* format 9 */
823d2571
TG		 2398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2399 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2401 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2403 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2405 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 2406 /* format 10 */
823d2571
TG		 2407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2408 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2410 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 2411 /* format 11 */
823d2571
TG		 2412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2413 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2415 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 2416 /* format 12 */
823d2571
TG		 2417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2418 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2419 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2420 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 2421 /* format 15 */
823d2571
TG		 2422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 2424 /* format 17 */
823d2571 2425 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 2426 /* format 16 */
823d2571
TG		 2427 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
2429 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 2430 /* format 18 */
823d2571 2431 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 2432
2433 /* The E800 .. FFFF range is unconditionally redirected to the
2434 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2435 are processed via that table. Thus, we can never encounter a
2436 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 2437 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
2438 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 2439};
2440
2441/* Thumb32 opcodes use the same table structure as the ARM opcodes.
2442 We adopt the convention that hw1 is the high 16 bits of .value and
2443 .mask, hw2 the low 16 bits.
2444
2445 print_insn_thumb32 recognizes the following format control codes:
2446
2447 %% %
2448
2449 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2450 %M print a modified 12-bit immediate (same location)
2451 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2452 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 2453 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 2454 %S print a possibly-shifted Rm
2455
32a94698 2456 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 2457 %a print the address of a plain load/store
2458 %w print the width and signedness of a core load/store
2459 %m print register mask for ldm/stm
2460
2461 %E print the lsb and width fields of a bfc/bfi instruction
2462 %F print the lsb and width fields of a sbfx/ubfx instruction
2463 %b print a conditional branch offset
2464 %B print an unconditional branch offset
2465 %s print the shift field of an SSAT instruction
2466 %R print the rotation field of an SXT instruction
62b3e311
PB		 2467 %U print barrier type.
2468 %P print address for pli instruction.
c22aaad1
PB		 2469 %c print the condition code
2470 %x print warning if conditional an not at end of IT block"
2471 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 2472
2473 %<bitfield>d print bitfield in decimal
2474 %<bitfield>W print bitfield*4 in decimal
2475 %<bitfield>r print bitfield as an ARM register
dd5181d5
KT		 2476 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
2477 %<bitfield>S as %<>R but r13 is UNPREDICTABLE
8f06b2d8
PB		 2478 %<bitfield>c print bitfield as a condition code
2479
16980d0b
JB		 2480 %<bitfield>'c print specified char iff bitfield is all ones
2481 %<bitfield>`c print specified char iff bitfield is all zeroes
2482 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 2483
2484 With one exception at the bottom (done because BL and BLX(1) need
2485 to come dead last), this table was machine-sorted first in
2486 decreasing order of number of bits set in the mask, then in
2487 increasing numeric order of mask, then in increasing numeric order
2488 of opcode. This order is not the clearest for a human reader, but
2489 is guaranteed never to catch a special-case bit pattern with a more
2490 general mask, which is important, because this instruction encoding
2491 makes heavy use of special-case bit patterns. */
2492static const struct opcode32 thumb32_opcodes[] =
2493{
53c4b28b 2494 /* V8 instructions. */
823d2571
TG		 2495 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2496 0xf3af8005, 0xffffffff, "sevl%c.w"},
2497 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2498 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2499 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2500 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2501 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2502 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
2503 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2504 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
2505 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2506 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
2507 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2508 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
2509 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2510 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
2511 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2512 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
2513 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2514 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2515 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2516 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2517 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2518 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
2519 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2520 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2521 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2522 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2523 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2524 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2525 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2526 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 2527
dd5181d5 2528 /* CRC32 instructions. */
823d2571
TG		 2529 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2530 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"},
2531 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2532 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"},
2533 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2534 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"},
2535 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2536 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"},
2537 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2538 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"},
2539 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2540 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"},
dd5181d5 2541
62b3e311 2542 /* V7 instructions. */
823d2571
TG		 2543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
2544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
2545 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
2546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
2547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
2548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
2549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
2550 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2551 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
2552 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2553 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 2554
90ec0d68 2555 /* Virtualization Extension instructions. */
823d2571 2556 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 2557 /* We skip ERET as that is SUBS pc, lr, #0. */
2558
60e5ef9f 2559 /* MP Extension instructions. */
823d2571 2560 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 2561
f4c65163 2562 /* Security extension instructions. */
823d2571 2563 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 2564
8f06b2d8 2565 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 2566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
2567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
2568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
2571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2572 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
2573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
2574
2575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2576 0xf3bf8f2f, 0xffffffff, "clrex%c"},
2577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2578 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
2579 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2580 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
2581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2582 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
2583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2584 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
2585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2586 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
2587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2588 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
2589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2590 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
2591 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2592 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
2593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2594 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
2595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2596 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
2597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2598 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
2599 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2600 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
2601 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2602 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
2603 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2604 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
2605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2606 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
2607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2608 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
2609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2610 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
2611 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2612 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
2613 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2614 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
2615 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2616 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
2617 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2618 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
2619 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2620 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
2621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2622 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
2623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2624 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
2625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2626 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
2627 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2628 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
2629 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2630 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
2631 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2632 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
2633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2634 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
2635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2636 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
2637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2638 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
2639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2640 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
2641 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2642 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
2643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2644 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
2645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2646 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
2647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2648 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
2649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2650 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
2651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2652 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
2653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2654 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
2655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2656 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
2657 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2658 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
2659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2660 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
2661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2662 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
2663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2664 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
2665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2666 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
2667 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2668 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
2669 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2670 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
2671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2672 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
2673 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2674 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
2675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2676 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
2677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2678 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
2679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2680 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
2681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2682 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
2683 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2684 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
2685 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2686 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
2687 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2688 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
2689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2690 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
2691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2692 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
2693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2694 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
2695 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2696 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
2697 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2698 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
2699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2700 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
2701 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2702 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
2703 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2704 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
2705 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2706 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
2707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2708 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
2709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2710 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
2711 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2712 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
2713 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2714 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
2715 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2716 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
2717 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2718 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
2719 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2720 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
2721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2722 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
2723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2724 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2726 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2728 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2730 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
2731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2732 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
2733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2734 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4d, %16-19r"},
2735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2736 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
2737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2738 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
2739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2740 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2742 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
2743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2744 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
2745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2746 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2748 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2750 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2752 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2754 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2756 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2758 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2760 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
2761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2762 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
2763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2764 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
2765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2766 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
2767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2768 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
2769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2770 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
2771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2772 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
2773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2774 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
2775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2776 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
2777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2778 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
2779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2780 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
2781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2782 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
2783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2784 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2786 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2788 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2790 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2792 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2794 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2796 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2798 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2800 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
2801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2802 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
2803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2804 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
2805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2806 0xf810f000, 0xff70f000, "pld%c\t%a"},
2807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2808 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2810 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2812 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2814 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2816 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2818 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2820 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2822 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
2823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2824 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
2825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2826 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
2827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2828 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
2829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2830 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
2831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2832 0xfb100000, 0xfff000c0,
2833 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2835 0xfbc00080, 0xfff000c0,
2836 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
2837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2838 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
2839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2840 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
2841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2842 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4d, %16-19r%s"},
2843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2844 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
2845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2846 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
2847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2848 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
2849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2850 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
2851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2852 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
2853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2854 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
2855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2856 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
2857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2858 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
2859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2860 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
2861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2862 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
2863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2864 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
2865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2866 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
2867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2868 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
2869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2870 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
2871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2872 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
2873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2874 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
2875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2876 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
2877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2878 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
2879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2880 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
2881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2882 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
2883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2884 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
2885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2886 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
2887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2888 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
2889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2890 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
2891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2892 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
2893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2894 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
2895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2896 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
2897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2898 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
2899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2900 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
2901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2902 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
2903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2904 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
2905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2906 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
2907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2908 0xe9400000, 0xff500000,
2909 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
2910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2911 0xe9500000, 0xff500000,
2912 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
2913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2914 0xe8600000, 0xff700000,
2915 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
2916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2917 0xe8700000, 0xff700000,
2918 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
2919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2920 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
2921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2922 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 2923
2924 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 2925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2926 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
2927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2928 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
2929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2930 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
2931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2932 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 2933
8f06b2d8 2934 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 2935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2936 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
2937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2938 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 2939
2940 /* Fallback. */
823d2571
TG		 2941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2942 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2943 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 2944};
ff4a8d2b 2945
8f06b2d8
PB		 2946static const char *const arm_conditional[] =
2947{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 2948 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 2949
2950static const char *const arm_fp_const[] =
2951{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
2952
2953static const char *const arm_shift[] =
2954{"lsl", "lsr", "asr", "ror"};
2955
2956typedef struct
2957{
2958 const char *name;
2959 const char *description;
2960 const char *reg_names[16];
2961}
2962arm_regname;
2963
2964static const arm_regname regnames[] =
2965{
2966 { "raw" , "Select raw register names",
2967 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
2968 { "gcc", "Select register names used by GCC",
2969 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
2970 { "std", "Select register names used in ARM's ISA documentation",
2971 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
2972 { "apcs", "Select register names used in the APCS",
2973 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
2974 { "atpcs", "Select register names used in the ATPCS",
2975 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
2976 { "special-atpcs", "Select special register names used in the ATPCS",
2977 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
2978};
2979
2980static const char *const iwmmxt_wwnames[] =
2981{"b", "h", "w", "d"};
2982
2983static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 2984{"b", "bus", "bc", "bss",
2985 "h", "hus", "hc", "hss",
2986 "w", "wus", "wc", "wss",
2987 "d", "dus", "dc", "dss"
8f06b2d8
PB		 2988};
2989
2990static const char *const iwmmxt_regnames[] =
2991{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
2992 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
2993};
2994
2995static const char *const iwmmxt_cregnames[] =
2996{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
2997 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
2998};
2999
3000/* Default to GCC register name set. */
3001static unsigned int regname_selected = 1;
3002
3003#define NUM_ARM_REGNAMES NUM_ELEM (regnames)
3004#define arm_regnames regnames[regname_selected].reg_names
3005
3006static bfd_boolean force_thumb = FALSE;
3007
c22aaad1
PB		 3008/* Current IT instruction state. This contains the same state as the IT
3009 bits in the CPSR. */
3010static unsigned int ifthen_state;
3011/* IT state for the next instruction. */
3012static unsigned int ifthen_next_state;
3013/* The address of the insn for which the IT state is valid. */
3014static bfd_vma ifthen_address;
3015#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 3016/* Indicates that the current Conditional state is unconditional or outside
3017 an IT block. */
3018#define COND_UNCOND 16
c22aaad1 3019
8f06b2d8
PB		 3020\f
3021/* Functions. */
3022int
3023get_arm_regname_num_options (void)
3024{
3025 return NUM_ARM_REGNAMES;
3026}
3027
3028int
3029set_arm_regname_option (int option)
3030{
3031 int old = regname_selected;
3032 regname_selected = option;
3033 return old;
3034}
3035
3036int
fe56b6ce
NC		 3037get_arm_regnames (int option,
3038 const char **setname,
3039 const char **setdescription,
8f06b2d8
PB		 3040 const char *const **register_names)
3041{
3042 *setname = regnames[option].name;
3043 *setdescription = regnames[option].description;
3044 *register_names = regnames[option].reg_names;
3045 return 16;
3046}
3047
16980d0b
JB		 3048/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3049 Returns pointer to following character of the format string and
3050 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 3051 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 3052
3053static const char *
fe56b6ce
NC		 3054arm_decode_bitfield (const char *ptr,
3055 unsigned long insn,
3056 unsigned long *valuep,
3057 int *widthp)
16980d0b
JB		 3058{
3059 unsigned long value = 0;
3060 int width = 0;
3061
3062 do
3063 {
3064 int start, end;
3065 int bits;
3066
3067 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3068 start = start * 10 + *ptr - '0';
3069 if (*ptr == '-')
3070 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3071 end = end * 10 + *ptr - '0';
3072 else
3073 end = start;
3074 bits = end - start;
3075 if (bits < 0)
3076 abort ();
3077 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3078 width += bits + 1;
3079 }
3080 while (*ptr++ == ',');
3081 *valuep = value;
3082 if (widthp)
3083 *widthp = width;
3084 return ptr - 1;
3085}
3086
8f06b2d8 3087static void
37b37b2d 3088arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 3089 bfd_boolean print_shift)
8f06b2d8
PB		 3090{
3091 func (stream, "%s", arm_regnames[given & 0xf]);
3092
3093 if ((given & 0xff0) != 0)
3094 {
3095 if ((given & 0x10) == 0)
3096 {
3097 int amount = (given & 0xf80) >> 7;
3098 int shift = (given & 0x60) >> 5;
3099
3100 if (amount == 0)
3101 {
3102 if (shift == 3)
3103 {
3104 func (stream, ", rrx");
3105 return;
3106 }
3107
3108 amount = 32;
3109 }
3110
37b37b2d
RE		 3111 if (print_shift)
3112 func (stream, ", %s #%d", arm_shift[shift], amount);
3113 else
3114 func (stream, ", #%d", amount);
8f06b2d8 3115 }
74bdfecf 3116 else if ((given & 0x80) == 0x80)
aefd8a40 3117 func (stream, "\t; <illegal shifter operand>");
37b37b2d 3118 else if (print_shift)
8f06b2d8
PB		 3119 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3120 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 3121 else
3122 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 3123 }
3124}
3125
c1e26897
NC		 3126#define W_BIT 21
3127#define I_BIT 22
3128#define U_BIT 23
3129#define P_BIT 24
3130
3131#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
3132#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
3133#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
3134#define PRE_BIT_SET (given & (1 << P_BIT))
3135
8f06b2d8
PB		 3136/* Print one coprocessor instruction on INFO->STREAM.
3137 Return TRUE if the instuction matched, FALSE if this is not a
3138 recognised coprocessor instruction. */
3139
3140static bfd_boolean
fe56b6ce
NC		 3141print_insn_coprocessor (bfd_vma pc,
3142 struct disassemble_info *info,
3143 long given,
8f06b2d8
PB		 3144 bfd_boolean thumb)
3145{
3146 const struct opcode32 *insn;
3147 void *stream = info->stream;
3148 fprintf_ftype func = info->fprintf_func;
3149 unsigned long mask;
2edcd244 3150 unsigned long value = 0;
c22aaad1 3151 int cond;
823d2571
TG		 3152 struct arm_private_data *private_data = info->private_data;
3153 arm_feature_set allowed_arches = ARM_ARCH_NONE;
3154
3155 ARM_FEATURE_COPY (allowed_arches, private_data->features);
8f06b2d8
PB		 3156
3157 for (insn = coprocessor_opcodes; insn->assembler; insn++)
3158 {
ff4a8d2b
NC		 3159 unsigned long u_reg = 16;
3160 bfd_boolean is_unpredictable = FALSE;
05413229 3161 signed long value_in_comment = 0;
0313a2b8
NC		 3162 const char *c;
3163
823d2571 3164 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 3165 switch (insn->value)
3166 {
3167 case SENTINEL_IWMMXT_START:
3168 if (info->mach != bfd_mach_arm_XScale
3169 && info->mach != bfd_mach_arm_iWMMXt
3170 && info->mach != bfd_mach_arm_iWMMXt2)
3171 do
3172 insn++;
823d2571
TG		 3173 while ((! ARM_FEATURE_ZERO (insn->arch))
3174 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 3175 continue;
3176
3177 case SENTINEL_IWMMXT_END:
3178 continue;
3179
3180 case SENTINEL_GENERIC_START:
823d2571 3181 ARM_FEATURE_COPY (allowed_arches, private_data->features);
05413229
NC		 3182 continue;
3183
3184 default:
3185 abort ();
3186 }
8f06b2d8
PB		 3187
3188 mask = insn->mask;
3189 value = insn->value;
3190 if (thumb)
3191 {
3192 /* The high 4 bits are 0xe for Arm conditional instructions, and
3193 0xe for arm unconditional instructions. The rest of the
3194 encoding is the same. */
3195 mask |= 0xf0000000;
3196 value |= 0xe0000000;
c22aaad1
PB		 3197 if (ifthen_state)
3198 cond = IFTHEN_COND;
3199 else
e2efe87d 3200 cond = COND_UNCOND;
8f06b2d8
PB		 3201 }
3202 else
3203 {
3204 /* Only match unconditional instuctions against unconditional
3205 patterns. */
3206 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 3207 {
3208 mask |= 0xf0000000;
e2efe87d 3209 cond = COND_UNCOND;
c22aaad1
PB		 3210 }
3211 else
3212 {
3213 cond = (given >> 28) & 0xf;
3214 if (cond == 0xe)
e2efe87d 3215 cond = COND_UNCOND;
c22aaad1 3216 }
8f06b2d8 3217 }
823d2571 3218
0313a2b8
NC		 3219 if ((given & mask) != value)
3220 continue;
8f06b2d8 3221
823d2571 3222 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 3223 continue;
3224
3225 for (c = insn->assembler; *c; c++)
3226 {
3227 if (*c == '%')
8f06b2d8 3228 {
0313a2b8 3229 switch (*++c)
8f06b2d8 3230 {
0313a2b8
NC		 3231 case '%':
3232 func (stream, "%%");
3233 break;
3234
3235 case 'A':
05413229 3236 {
79862e45 3237 int rn = (given >> 16) & 0xf;
f8b960bc 3238 bfd_vma offset = given & 0xff;
0313a2b8 3239
05413229 3240 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 3241
79862e45
DJ		 3242 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
3243 {
3244 /* Not unindexed. The offset is scaled. */
3245 offset = offset * 4;
3246 if (NEGATIVE_BIT_SET)
3247 offset = - offset;
3248 if (rn != 15)
3249 value_in_comment = offset;
3250 }
3251
c1e26897 3252 if (PRE_BIT_SET)
05413229
NC		 3253 {
3254 if (offset)
fe56b6ce 3255 func (stream, ", #%d]%s",
d908c8af 3256 (int) offset,
c1e26897 3257 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 3258 else if (NEGATIVE_BIT_SET)
3259 func (stream, ", #-0]");
05413229
NC		 3260 else
3261 func (stream, "]");
3262 }
3263 else
3264 {
0313a2b8 3265 func (stream, "]");
8f06b2d8 3266
c1e26897 3267 if (WRITEBACK_BIT_SET)
05413229
NC		 3268 {
3269 if (offset)
d908c8af 3270 func (stream, ", #%d", (int) offset);
26d97720
NS		 3271 else if (NEGATIVE_BIT_SET)
3272 func (stream, ", #-0");
05413229
NC		 3273 }
3274 else
fe56b6ce 3275 {
26d97720
NS		 3276 func (stream, ", {%s%d}",
3277 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 3278 (int) offset);
fe56b6ce
NC		 3279 value_in_comment = offset;
3280 }
05413229 3281 }
79862e45
DJ		 3282 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
3283 {
3284 func (stream, "\t; ");
6844b2c2
MGD		 3285 /* For unaligned PCs, apply off-by-alignment
3286 correction. */
3287 info->print_address_func (offset + pc
3288 + info->bytes_per_chunk * 2
3289 - (pc & 3),
3290 info);
79862e45 3291 }
05413229 3292 }
0313a2b8 3293 break;
8f06b2d8 3294
0313a2b8
NC		 3295 case 'B':
3296 {
3297 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
3298 int offset = (given >> 1) & 0x3f;
3299
3300 if (offset == 1)
3301 func (stream, "{d%d}", regno);
3302 else if (regno + offset > 32)
3303 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
3304 else
3305 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
3306 }
3307 break;
8f06b2d8 3308
e2efe87d
MGD		 3309 case 'u':
3310 if (cond != COND_UNCOND)
3311 is_unpredictable = TRUE;
3312
3313 /* Fall through. */
0313a2b8
NC		 3314 case 'c':
3315 func (stream, "%s", arm_conditional[cond]);
3316 break;
8f06b2d8 3317
0313a2b8
NC		 3318 case 'I':
3319 /* Print a Cirrus/DSP shift immediate. */
3320 /* Immediates are 7bit signed ints with bits 0..3 in
3321 bits 0..3 of opcode and bits 4..6 in bits 5..7
3322 of opcode. */
3323 {
3324 int imm;
8f06b2d8 3325
0313a2b8 3326 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 3327
0313a2b8
NC		 3328 /* Is ``imm'' a negative number? */
3329 if (imm & 0x40)
3330 imm |= (-1 << 7);
8f06b2d8 3331
0313a2b8
NC		 3332 func (stream, "%d", imm);
3333 }
3334
3335 break;
8f06b2d8 3336
0313a2b8
NC		 3337 case 'F':
3338 switch (given & 0x00408000)
3339 {
3340 case 0:
3341 func (stream, "4");
3342 break;
3343 case 0x8000:
3344 func (stream, "1");
3345 break;
3346 case 0x00400000:
3347 func (stream, "2");
8f06b2d8 3348 break;
0313a2b8
NC		 3349 default:
3350 func (stream, "3");
3351 }
3352 break;
8f06b2d8 3353
0313a2b8
NC		 3354 case 'P':
3355 switch (given & 0x00080080)
3356 {
3357 case 0:
3358 func (stream, "s");
3359 break;
3360 case 0x80:
3361 func (stream, "d");
3362 break;
3363 case 0x00080000:
3364 func (stream, "e");
3365 break;
3366 default:
3367 func (stream, _("<illegal precision>"));
8f06b2d8 3368 break;
0313a2b8
NC		 3369 }
3370 break;
8f06b2d8 3371
0313a2b8
NC		 3372 case 'Q':
3373 switch (given & 0x00408000)
3374 {
3375 case 0:
3376 func (stream, "s");
8f06b2d8 3377 break;
0313a2b8
NC		 3378 case 0x8000:
3379 func (stream, "d");
8f06b2d8 3380 break;
0313a2b8
NC		 3381 case 0x00400000:
3382 func (stream, "e");
3383 break;
3384 default:
3385 func (stream, "p");
8f06b2d8 3386 break;
0313a2b8
NC		 3387 }
3388 break;
8f06b2d8 3389
0313a2b8
NC		 3390 case 'R':
3391 switch (given & 0x60)
3392 {
3393 case 0:
3394 break;
3395 case 0x20:
3396 func (stream, "p");
3397 break;
3398 case 0x40:
3399 func (stream, "m");
3400 break;
3401 default:
3402 func (stream, "z");
3403 break;
3404 }
3405 break;
16980d0b 3406
0313a2b8
NC		 3407 case '0': case '1': case '2': case '3': case '4':
3408 case '5': case '6': case '7': case '8': case '9':
3409 {
3410 int width;
8f06b2d8 3411
0313a2b8 3412 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 3413
0313a2b8
NC		 3414 switch (*c)
3415 {
ff4a8d2b
NC		 3416 case 'R':
3417 if (value == 15)
3418 is_unpredictable = TRUE;
3419 /* Fall through. */
0313a2b8 3420 case 'r':
ff4a8d2b
NC		 3421 if (c[1] == 'u')
3422 {
3423 /* Eat the 'u' character. */
3424 ++ c;
3425
3426 if (u_reg == value)
3427 is_unpredictable = TRUE;
3428 u_reg = value;
3429 }
0313a2b8
NC		 3430 func (stream, "%s", arm_regnames[value]);
3431 break;
3432 case 'D':
3433 func (stream, "d%ld", value);
3434 break;
3435 case 'Q':
3436 if (value & 1)
3437 func (stream, "<illegal reg q%ld.5>", value >> 1);
3438 else
3439 func (stream, "q%ld", value >> 1);
3440 break;
3441 case 'd':
3442 func (stream, "%ld", value);
05413229 3443 value_in_comment = value;
0313a2b8
NC		 3444 break;
3445 case 'k':
3446 {
3447 int from = (given & (1 << 7)) ? 32 : 16;
3448 func (stream, "%ld", from - value);
3449 }
3450 break;
8f06b2d8 3451
0313a2b8
NC		 3452 case 'f':
3453 if (value > 7)
3454 func (stream, "#%s", arm_fp_const[value & 7]);
3455 else
3456 func (stream, "f%ld", value);
3457 break;
4146fd53 3458
0313a2b8
NC		 3459 case 'w':
3460 if (width == 2)
3461 func (stream, "%s", iwmmxt_wwnames[value]);
3462 else
3463 func (stream, "%s", iwmmxt_wwssnames[value]);
3464 break;
4146fd53 3465
0313a2b8
NC		 3466 case 'g':
3467 func (stream, "%s", iwmmxt_regnames[value]);
3468 break;
3469 case 'G':
3470 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 3471 break;
8f06b2d8 3472
0313a2b8 3473 case 'x':
d1aaab3c 3474 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 3475 break;
8f06b2d8 3476
33399f07
MGD		 3477 case 'c':
3478 switch (value)
3479 {
3480 case 0:
3481 func (stream, "eq");
3482 break;
3483
3484 case 1:
3485 func (stream, "vs");
3486 break;
3487
3488 case 2:
3489 func (stream, "ge");
3490 break;
3491
3492 case 3:
3493 func (stream, "gt");
3494 break;
3495
3496 default:
3497 func (stream, "??");
3498 break;
3499 }
3500 break;
3501
0313a2b8
NC		 3502 case '`':
3503 c++;
3504 if (value == 0)
3505 func (stream, "%c", *c);
3506 break;
3507 case '\'':
3508 c++;
3509 if (value == ((1ul << width) - 1))
3510 func (stream, "%c", *c);
3511 break;
3512 case '?':
fe56b6ce 3513 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 3514 c += 1 << width;
3515 break;
3516 default:
3517 abort ();
3518 }
3519 break;
8f06b2d8 3520
0313a2b8
NC		 3521 case 'y':
3522 case 'z':
3523 {
3524 int single = *c++ == 'y';
3525 int regno;
3526
3527 switch (*c)
3528 {
3529 case '4': /* Sm pair */
3530 case '0': /* Sm, Dm */
3531 regno = given & 0x0000000f;
3532 if (single)
3533 {
3534 regno <<= 1;
3535 regno += (given >> 5) & 1;
16980d0b 3536 }
0313a2b8
NC		 3537 else
3538 regno += ((given >> 5) & 1) << 4;
3539 break;
8f06b2d8 3540
0313a2b8
NC		 3541 case '1': /* Sd, Dd */
3542 regno = (given >> 12) & 0x0000000f;
3543 if (single)
3544 {
3545 regno <<= 1;
3546 regno += (given >> 22) & 1;
3547 }
3548 else
3549 regno += ((given >> 22) & 1) << 4;
3550 break;
8f06b2d8 3551
0313a2b8
NC		 3552 case '2': /* Sn, Dn */
3553 regno = (given >> 16) & 0x0000000f;
3554 if (single)
8f06b2d8 3555 {
0313a2b8
NC		 3556 regno <<= 1;
3557 regno += (given >> 7) & 1;
8f06b2d8 3558 }
0313a2b8
NC		 3559 else
3560 regno += ((given >> 7) & 1) << 4;
3561 break;
7df76b80 3562
0313a2b8
NC		 3563 case '3': /* List */
3564 func (stream, "{");
3565 regno = (given >> 12) & 0x0000000f;
3566 if (single)
3567 {
3568 regno <<= 1;
3569 regno += (given >> 22) & 1;
3570 }
3571 else
3572 regno += ((given >> 22) & 1) << 4;
3573 break;
a7f8487e 3574
0313a2b8
NC		 3575 default:
3576 abort ();
8f06b2d8 3577 }
a7f8487e 3578
0313a2b8
NC		 3579 func (stream, "%c%d", single ? 's' : 'd', regno);
3580
3581 if (*c == '3')
8f06b2d8 3582 {
0313a2b8 3583 int count = given & 0xff;
a7f8487e 3584
0313a2b8
NC		 3585 if (single == 0)
3586 count >>= 1;
b34976b6 3587
0313a2b8 3588 if (--count)
8f06b2d8 3589 {
0313a2b8
NC		 3590 func (stream, "-%c%d",
3591 single ? 's' : 'd',
3592 regno + count);
8f06b2d8 3593 }
0313a2b8
NC		 3594
3595 func (stream, "}");
8f06b2d8 3596 }
0313a2b8
NC		 3597 else if (*c == '4')
3598 func (stream, ", %c%d", single ? 's' : 'd',
3599 regno + 1);
3600 }
3601 break;
3602
3603 case 'L':
3604 switch (given & 0x00400100)
3605 {
3606 case 0x00000000: func (stream, "b"); break;
3607 case 0x00400000: func (stream, "h"); break;
3608 case 0x00000100: func (stream, "w"); break;
3609 case 0x00400100: func (stream, "d"); break;
3610 default:
8f06b2d8 3611 break;
0313a2b8
NC		 3612 }
3613 break;
b34976b6 3614
0313a2b8
NC		 3615 case 'Z':
3616 {
0313a2b8
NC		 3617 /* given (20, 23) | given (0, 3) */
3618 value = ((given >> 16) & 0xf0) | (given & 0xf);
d908c8af 3619 func (stream, "%d", (int) value);
0313a2b8
NC		 3620 }
3621 break;
2d447fca 3622
0313a2b8
NC		 3623 case 'l':
3624 /* This is like the 'A' operator, except that if
3625 the width field "M" is zero, then the offset is
3626 *not* multiplied by four. */
3627 {
3628 int offset = given & 0xff;
3629 int multiplier = (given & 0x00000100) ? 4 : 1;
3630
3631 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3632
05413229
NC		 3633 if (multiplier > 1)
3634 {
3635 value_in_comment = offset * multiplier;
c1e26897 3636 if (NEGATIVE_BIT_SET)
05413229
NC		 3637 value_in_comment = - value_in_comment;
3638 }
3639
0313a2b8
NC		 3640 if (offset)
3641 {
c1e26897 3642 if (PRE_BIT_SET)
0313a2b8 3643 func (stream, ", #%s%d]%s",
c1e26897 3644 NEGATIVE_BIT_SET ? "-" : "",
0313a2b8 3645 offset * multiplier,
c1e26897 3646 WRITEBACK_BIT_SET ? "!" : "");
0313a2b8
NC		 3647 else
3648 func (stream, "], #%s%d",
c1e26897 3649 NEGATIVE_BIT_SET ? "-" : "",
0313a2b8 3650 offset * multiplier);
2d447fca 3651 }
0313a2b8
NC		 3652 else
3653 func (stream, "]");
3654 }
3655 break;
3656
3657 case 'r':
3658 {
3659 int imm4 = (given >> 4) & 0xf;
c1e26897
NC		 3660 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
3661 int ubit = ! NEGATIVE_BIT_SET;
0313a2b8
NC		 3662 const char *rm = arm_regnames [given & 0xf];
3663 const char *rn = arm_regnames [(given >> 16) & 0xf];
2d447fca 3664
0313a2b8 3665 switch (puw_bits)
2d447fca 3666 {
0313a2b8
NC		 3667 case 1:
3668 case 3:
3669 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
3670 if (imm4)
3671 func (stream, ", lsl #%d", imm4);
3672 break;
3673
3674 case 4:
3675 case 5:
3676 case 6:
3677 case 7:
3678 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
3679 if (imm4 > 0)
3680 func (stream, ", lsl #%d", imm4);
3681 func (stream, "]");
3682 if (puw_bits == 5 || puw_bits == 7)
3683 func (stream, "!");
3684 break;
3685
3686 default:
3687 func (stream, "INVALID");
2d447fca 3688 }
0313a2b8
NC		 3689 }
3690 break;
2d447fca 3691
0313a2b8
NC		 3692 case 'i':
3693 {
3694 long imm5;
3695 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
3696 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
8f06b2d8 3697 }
0313a2b8
NC		 3698 break;
3699
3700 default:
3701 abort ();
3702 }
252b5132 3703 }
252b5132 3704 }
0313a2b8
NC		 3705 else
3706 func (stream, "%c", *c);
252b5132 3707 }
05413229
NC		 3708
3709 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 3710 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 3711
ff4a8d2b
NC		 3712 if (is_unpredictable)
3713 func (stream, UNPREDICTABLE_INSTRUCTION);
3714
0313a2b8 3715 return TRUE;
252b5132 3716 }
8f06b2d8 3717 return FALSE;
252b5132
RH		 3718}
3719
05413229
NC		 3720/* Decodes and prints ARM addressing modes. Returns the offset
3721 used in the address, if any, if it is worthwhile printing the
3722 offset as a hexadecimal value in a comment at the end of the
3723 line of disassembly. */
3724
3725static signed long
62b3e311
PB		 3726print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
3727{
3728 void *stream = info->stream;
3729 fprintf_ftype func = info->fprintf_func;
f8b960bc 3730 bfd_vma offset = 0;
62b3e311
PB		 3731
3732 if (((given & 0x000f0000) == 0x000f0000)
3733 && ((given & 0x02000000) == 0))
3734 {
05413229 3735 offset = given & 0xfff;
62b3e311
PB		 3736
3737 func (stream, "[pc");
3738
c1e26897 3739 if (PRE_BIT_SET)
62b3e311 3740 {
26d97720
NS		 3741 /* Pre-indexed. Elide offset of positive zero when
3742 non-writeback. */
3743 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 3744 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 3745
3746 if (NEGATIVE_BIT_SET)
3747 offset = -offset;
62b3e311
PB		 3748
3749 offset += pc + 8;
3750
3751 /* Cope with the possibility of write-back
3752 being used. Probably a very dangerous thing
3753 for the programmer to do, but who are we to
3754 argue ? */
26d97720 3755 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 3756 }
c1e26897 3757 else /* Post indexed. */
62b3e311 3758 {
d908c8af 3759 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 3760
c1e26897 3761 /* Ie ignore the offset. */
62b3e311
PB		 3762 offset = pc + 8;
3763 }
3764
3765 func (stream, "\t; ");
3766 info->print_address_func (offset, info);
05413229 3767 offset = 0;
62b3e311
PB		 3768 }
3769 else
3770 {
3771 func (stream, "[%s",
3772 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 3773
3774 if (PRE_BIT_SET)
62b3e311
PB		 3775 {
3776 if ((given & 0x02000000) == 0)
3777 {
26d97720 3778 /* Elide offset of positive zero when non-writeback. */
05413229 3779 offset = given & 0xfff;
26d97720 3780 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 3781 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 3782 }
3783 else
3784 {
26d97720 3785 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 3786 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 3787 }
3788
3789 func (stream, "]%s",
c1e26897 3790 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 3791 }
3792 else
3793 {
3794 if ((given & 0x02000000) == 0)
3795 {
26d97720 3796 /* Always show offset. */
05413229 3797 offset = given & 0xfff;
26d97720 3798 func (stream, "], #%s%d",
d908c8af 3799 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 3800 }
3801 else
3802 {
3803 func (stream, "], %s",
c1e26897 3804 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 3805 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 3806 }
3807 }
84919466
MR		 3808 if (NEGATIVE_BIT_SET)
3809 offset = -offset;
62b3e311 3810 }
05413229
NC		 3811
3812 return (signed long) offset;
62b3e311
PB		 3813}
3814
16980d0b
JB		 3815/* Print one neon instruction on INFO->STREAM.
3816 Return TRUE if the instuction matched, FALSE if this is not a
3817 recognised neon instruction. */
3818
3819static bfd_boolean
3820print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
3821{
3822 const struct opcode32 *insn;
3823 void *stream = info->stream;
3824 fprintf_ftype func = info->fprintf_func;
3825
3826 if (thumb)
3827 {
3828 if ((given & 0xef000000) == 0xef000000)
3829 {
0313a2b8 3830 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 3831 unsigned long bit28 = given & (1 << 28);
3832
3833 given &= 0x00ffffff;
3834 if (bit28)
3835 given |= 0xf3000000;
3836 else
3837 given |= 0xf2000000;
3838 }
3839 else if ((given & 0xff000000) == 0xf9000000)
3840 given ^= 0xf9000000 ^ 0xf4000000;
3841 else
3842 return FALSE;
3843 }
3844
3845 for (insn = neon_opcodes; insn->assembler; insn++)
3846 {
3847 if ((given & insn->mask) == insn->value)
3848 {
05413229 3849 signed long value_in_comment = 0;
e2efe87d 3850 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 3851 const char *c;
3852
3853 for (c = insn->assembler; *c; c++)
3854 {
3855 if (*c == '%')
3856 {
3857 switch (*++c)
3858 {
3859 case '%':
3860 func (stream, "%%");
3861 break;
3862
e2efe87d
MGD		 3863 case 'u':
3864 if (thumb && ifthen_state)
3865 is_unpredictable = TRUE;
3866
3867 /* Fall through. */
c22aaad1
PB		 3868 case 'c':
3869 if (thumb && ifthen_state)
3870 func (stream, "%s", arm_conditional[IFTHEN_COND]);
3871 break;
3872
16980d0b
JB		 3873 case 'A':
3874 {
3875 static const unsigned char enc[16] =
3876 {
3877 0x4, 0x14, /* st4 0,1 */
3878 0x4, /* st1 2 */
3879 0x4, /* st2 3 */
3880 0x3, /* st3 4 */
3881 0x13, /* st3 5 */
3882 0x3, /* st1 6 */
3883 0x1, /* st1 7 */
3884 0x2, /* st2 8 */
3885 0x12, /* st2 9 */
3886 0x2, /* st1 10 */
3887 0, 0, 0, 0, 0
3888 };
3889 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
3890 int rn = ((given >> 16) & 0xf);
3891 int rm = ((given >> 0) & 0xf);
3892 int align = ((given >> 4) & 0x3);
3893 int type = ((given >> 8) & 0xf);
3894 int n = enc[type] & 0xf;
3895 int stride = (enc[type] >> 4) + 1;
3896 int ix;
3897
3898 func (stream, "{");
3899 if (stride > 1)
3900 for (ix = 0; ix != n; ix++)
3901 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
3902 else if (n == 1)
3903 func (stream, "d%d", rd);
3904 else
3905 func (stream, "d%d-d%d", rd, rd + n - 1);
3906 func (stream, "}, [%s", arm_regnames[rn]);
3907 if (align)
8e560766 3908 func (stream, " :%d", 32 << align);
16980d0b
JB		 3909 func (stream, "]");
3910 if (rm == 0xd)
3911 func (stream, "!");
3912 else if (rm != 0xf)
3913 func (stream, ", %s", arm_regnames[rm]);
3914 }
3915 break;
3916
3917 case 'B':
3918 {
3919 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
3920 int rn = ((given >> 16) & 0xf);
3921 int rm = ((given >> 0) & 0xf);
3922 int idx_align = ((given >> 4) & 0xf);
3923 int align = 0;
3924 int size = ((given >> 10) & 0x3);
3925 int idx = idx_align >> (size + 1);
3926 int length = ((given >> 8) & 3) + 1;
3927 int stride = 1;
3928 int i;
3929
3930 if (length > 1 && size > 0)
3931 stride = (idx_align & (1 << size)) ? 2 : 1;
3932
3933 switch (length)
3934 {
3935 case 1:
3936 {
3937 int amask = (1 << size) - 1;
3938 if ((idx_align & (1 << size)) != 0)
3939 return FALSE;
3940 if (size > 0)
3941 {
3942 if ((idx_align & amask) == amask)
3943 align = 8 << size;
3944 else if ((idx_align & amask) != 0)
3945 return FALSE;
3946 }
3947 }
3948 break;
3949
3950 case 2:
3951 if (size == 2 && (idx_align & 2) != 0)
3952 return FALSE;
3953 align = (idx_align & 1) ? 16 << size : 0;
3954 break;
3955
3956 case 3:
3957 if ((size == 2 && (idx_align & 3) != 0)
3958 || (idx_align & 1) != 0)
3959 return FALSE;
3960 break;
3961
3962 case 4:
3963 if (size == 2)
3964 {
3965 if ((idx_align & 3) == 3)
3966 return FALSE;
3967 align = (idx_align & 3) * 64;
3968 }
3969 else
3970 align = (idx_align & 1) ? 32 << size : 0;
3971 break;
3972
3973 default:
3974 abort ();
3975 }
3976
3977 func (stream, "{");
3978 for (i = 0; i < length; i++)
3979 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
3980 rd + i * stride, idx);
3981 func (stream, "}, [%s", arm_regnames[rn]);
3982 if (align)
8e560766 3983 func (stream, " :%d", align);
16980d0b
JB		 3984 func (stream, "]");
3985 if (rm == 0xd)
3986 func (stream, "!");
3987 else if (rm != 0xf)
3988 func (stream, ", %s", arm_regnames[rm]);
3989 }
3990 break;
3991
3992 case 'C':
3993 {
3994 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
3995 int rn = ((given >> 16) & 0xf);
3996 int rm = ((given >> 0) & 0xf);
3997 int align = ((given >> 4) & 0x1);
3998 int size = ((given >> 6) & 0x3);
3999 int type = ((given >> 8) & 0x3);
4000 int n = type + 1;
4001 int stride = ((given >> 5) & 0x1);
4002 int ix;
4003
4004 if (stride && (n == 1))
4005 n++;
4006 else
4007 stride++;
4008
4009 func (stream, "{");
4010 if (stride > 1)
4011 for (ix = 0; ix != n; ix++)
4012 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
4013 else if (n == 1)
4014 func (stream, "d%d[]", rd);
4015 else
4016 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
4017 func (stream, "}, [%s", arm_regnames[rn]);
4018 if (align)
4019 {
91d6fa6a 4020 align = (8 * (type + 1)) << size;
16980d0b
JB		 4021 if (type == 3)
4022 align = (size > 1) ? align >> 1 : align;
4023 if (type == 2 || (type == 0 && !size))
8e560766 4024 func (stream, " :<bad align %d>", align);
16980d0b 4025 else
8e560766 4026 func (stream, " :%d", align);
16980d0b
JB		 4027 }
4028 func (stream, "]");
4029 if (rm == 0xd)
4030 func (stream, "!");
4031 else if (rm != 0xf)
4032 func (stream, ", %s", arm_regnames[rm]);
4033 }
4034 break;
4035
4036 case 'D':
4037 {
4038 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
4039 int size = (given >> 20) & 3;
4040 int reg = raw_reg & ((4 << size) - 1);
4041 int ix = raw_reg >> size >> 2;
4042
4043 func (stream, "d%d[%d]", reg, ix);
4044 }
4045 break;
4046
4047 case 'E':
fe56b6ce 4048 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 4049 {
4050 int bits = 0;
4051 int cmode = (given >> 8) & 0xf;
4052 int op = (given >> 5) & 0x1;
4053 unsigned long value = 0, hival = 0;
4054 unsigned shift;
4055 int size = 0;
0dbde4cf 4056 int isfloat = 0;
16980d0b
JB		 4057
4058 bits |= ((given >> 24) & 1) << 7;
4059 bits |= ((given >> 16) & 7) << 4;
4060 bits |= ((given >> 0) & 15) << 0;
4061
4062 if (cmode < 8)
4063 {
4064 shift = (cmode >> 1) & 3;
fe56b6ce 4065 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4066 size = 32;
4067 }
4068 else if (cmode < 12)
4069 {
4070 shift = (cmode >> 1) & 1;
fe56b6ce 4071 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4072 size = 16;
4073 }
4074 else if (cmode < 14)
4075 {
4076 shift = (cmode & 1) + 1;
fe56b6ce 4077 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4078 value |= (1ul << (8 * shift)) - 1;
4079 size = 32;
4080 }
4081 else if (cmode == 14)
4082 {
4083 if (op)
4084 {
fe56b6ce 4085 /* Bit replication into bytes. */
16980d0b
JB		 4086 int ix;
4087 unsigned long mask;
4088
4089 value = 0;
4090 hival = 0;
4091 for (ix = 7; ix >= 0; ix--)
4092 {
4093 mask = ((bits >> ix) & 1) ? 0xff : 0;
4094 if (ix <= 3)
4095 value = (value << 8) | mask;
4096 else
4097 hival = (hival << 8) | mask;
4098 }
4099 size = 64;
4100 }
4101 else
4102 {
fe56b6ce
NC		 4103 /* Byte replication. */
4104 value = (unsigned long) bits;
16980d0b
JB		 4105 size = 8;
4106 }
4107 }
4108 else if (!op)
4109 {
fe56b6ce 4110 /* Floating point encoding. */
16980d0b
JB		 4111 int tmp;
4112
fe56b6ce
NC		 4113 value = (unsigned long) (bits & 0x7f) << 19;
4114 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 4115 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 4116 value |= (unsigned long) tmp << 24;
16980d0b 4117 size = 32;
0dbde4cf 4118 isfloat = 1;
16980d0b
JB		 4119 }
4120 else
4121 {
4122 func (stream, "<illegal constant %.8x:%x:%x>",
4123 bits, cmode, op);
4124 size = 32;
4125 break;
4126 }
4127 switch (size)
4128 {
4129 case 8:
4130 func (stream, "#%ld\t; 0x%.2lx", value, value);
4131 break;
4132
4133 case 16:
4134 func (stream, "#%ld\t; 0x%.4lx", value, value);
4135 break;
4136
4137 case 32:
0dbde4cf
JB		 4138 if (isfloat)
4139 {
4140 unsigned char valbytes[4];
4141 double fvalue;
4142
4143 /* Do this a byte at a time so we don't have to
4144 worry about the host's endianness. */
4145 valbytes[0] = value & 0xff;
4146 valbytes[1] = (value >> 8) & 0xff;
4147 valbytes[2] = (value >> 16) & 0xff;
4148 valbytes[3] = (value >> 24) & 0xff;
4149
4150 floatformat_to_double
c1e26897
NC		 4151 (& floatformat_ieee_single_little, valbytes,
4152 & fvalue);
0dbde4cf
JB		 4153
4154 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
4155 value);
4156 }
4157 else
4e9d3b81 4158 func (stream, "#%ld\t; 0x%.8lx",
9d82ec38
MGD		 4159 (long) (((value & 0x80000000L) != 0)
4160 ? value | ~0xffffffffL : value),
c1e26897 4161 value);
16980d0b
JB		 4162 break;
4163
4164 case 64:
4165 func (stream, "#0x%.8lx%.8lx", hival, value);
4166 break;
4167
4168 default:
4169 abort ();
4170 }
4171 }
4172 break;
4173
4174 case 'F':
4175 {
4176 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
4177 int num = (given >> 8) & 0x3;
4178
4179 if (!num)
4180 func (stream, "{d%d}", regno);
4181 else if (num + regno >= 32)
4182 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
4183 else
4184 func (stream, "{d%d-d%d}", regno, regno + num);
4185 }
4186 break;
7e8e6784 4187
16980d0b
JB		 4188
4189 case '0': case '1': case '2': case '3': case '4':
4190 case '5': case '6': case '7': case '8': case '9':
4191 {
4192 int width;
4193 unsigned long value;
4194
4195 c = arm_decode_bitfield (c, given, &value, &width);
4196
4197 switch (*c)
4198 {
4199 case 'r':
4200 func (stream, "%s", arm_regnames[value]);
4201 break;
4202 case 'd':
4203 func (stream, "%ld", value);
05413229 4204 value_in_comment = value;
16980d0b
JB		 4205 break;
4206 case 'e':
4207 func (stream, "%ld", (1ul << width) - value);
4208 break;
4209
4210 case 'S':
4211 case 'T':
4212 case 'U':
05413229 4213 /* Various width encodings. */
16980d0b
JB		 4214 {
4215 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
4216 int limit;
4217 unsigned low, high;
4218
4219 c++;
4220 if (*c >= '0' && *c <= '9')
4221 limit = *c - '0';
4222 else if (*c >= 'a' && *c <= 'f')
4223 limit = *c - 'a' + 10;
4224 else
4225 abort ();
4226 low = limit >> 2;
4227 high = limit & 3;
4228
4229 if (value < low || value > high)
4230 func (stream, "<illegal width %d>", base << value);
4231 else
4232 func (stream, "%d", base << value);
4233 }
4234 break;
4235 case 'R':
4236 if (given & (1 << 6))
4237 goto Q;
4238 /* FALLTHROUGH */
4239 case 'D':
4240 func (stream, "d%ld", value);
4241 break;
4242 case 'Q':
4243 Q:
4244 if (value & 1)
4245 func (stream, "<illegal reg q%ld.5>", value >> 1);
4246 else
4247 func (stream, "q%ld", value >> 1);
4248 break;
4249
4250 case '`':
4251 c++;
4252 if (value == 0)
4253 func (stream, "%c", *c);
4254 break;
4255 case '\'':
4256 c++;
4257 if (value == ((1ul << width) - 1))
4258 func (stream, "%c", *c);
4259 break;
4260 case '?':
fe56b6ce 4261 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 4262 c += 1 << width;
4263 break;
4264 default:
4265 abort ();
4266 }
4267 break;
4268
4269 default:
4270 abort ();
4271 }
4272 }
4273 }
4274 else
4275 func (stream, "%c", *c);
4276 }
05413229
NC		 4277
4278 if (value_in_comment > 32 || value_in_comment < -16)
4279 func (stream, "\t; 0x%lx", value_in_comment);
4280
e2efe87d
MGD		 4281 if (is_unpredictable)
4282 func (stream, UNPREDICTABLE_INSTRUCTION);
4283
16980d0b
JB		 4284 return TRUE;
4285 }
4286 }
4287 return FALSE;
4288}
4289
90ec0d68
MGD		 4290/* Return the name of a v7A special register. */
4291
4292static const char *
4293banked_regname (unsigned reg)
4294{
4295 switch (reg)
4296 {
4297 case 15: return "CPSR";
4298 case 32: return "R8_usr";
4299 case 33: return "R9_usr";
4300 case 34: return "R10_usr";
4301 case 35: return "R11_usr";
4302 case 36: return "R12_usr";
4303 case 37: return "SP_usr";
4304 case 38: return "LR_usr";
4305 case 40: return "R8_fiq";
4306 case 41: return "R9_fiq";
4307 case 42: return "R10_fiq";
4308 case 43: return "R11_fiq";
4309 case 44: return "R12_fiq";
4310 case 45: return "SP_fiq";
4311 case 46: return "LR_fiq";
4312 case 48: return "LR_irq";
4313 case 49: return "SP_irq";
4314 case 50: return "LR_svc";
4315 case 51: return "SP_svc";
4316 case 52: return "LR_abt";
4317 case 53: return "SP_abt";
4318 case 54: return "LR_und";
4319 case 55: return "SP_und";
4320 case 60: return "LR_mon";
4321 case 61: return "SP_mon";
4322 case 62: return "ELR_hyp";
4323 case 63: return "SP_hyp";
4324 case 79: return "SPSR";
4325 case 110: return "SPSR_fiq";
4326 case 112: return "SPSR_irq";
4327 case 114: return "SPSR_svc";
4328 case 116: return "SPSR_abt";
4329 case 118: return "SPSR_und";
4330 case 124: return "SPSR_mon";
4331 case 126: return "SPSR_hyp";
4332 default: return NULL;
4333 }
4334}
4335
e797f7e0
MGD		 4336/* Return the name of the DMB/DSB option. */
4337static const char *
4338data_barrier_option (unsigned option)
4339{
4340 switch (option & 0xf)
4341 {
4342 case 0xf: return "sy";
4343 case 0xe: return "st";
4344 case 0xd: return "ld";
4345 case 0xb: return "ish";
4346 case 0xa: return "ishst";
4347 case 0x9: return "ishld";
4348 case 0x7: return "un";
4349 case 0x6: return "unst";
4350 case 0x5: return "nshld";
4351 case 0x3: return "osh";
4352 case 0x2: return "oshst";
4353 case 0x1: return "oshld";
4354 default: return NULL;
4355 }
4356}
4357
4a5329c6
ZW		 4358/* Print one ARM instruction from PC on INFO->STREAM. */
4359
4360static void
4361print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 4362{
6b5d3a4d 4363 const struct opcode32 *insn;
6a51a8a8 4364 void *stream = info->stream;
6b5d3a4d 4365 fprintf_ftype func = info->fprintf_func;
b0e28b39 4366 struct arm_private_data *private_data = info->private_data;
252b5132 4367
16980d0b
JB		 4368 if (print_insn_coprocessor (pc, info, given, FALSE))
4369 return;
4370
4371 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 4372 return;
4373
252b5132
RH		 4374 for (insn = arm_opcodes; insn->assembler; insn++)
4375 {
0313a2b8
NC		 4376 if ((given & insn->mask) != insn->value)
4377 continue;
823d2571
TG		 4378
4379 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 4380 continue;
4381
4382 /* Special case: an instruction with all bits set in the condition field
4383 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
4384 or by the catchall at the end of the table. */
4385 if ((given & 0xF0000000) != 0xF0000000
4386 || (insn->mask & 0xF0000000) == 0xF0000000
4387 || (insn->mask == 0 && insn->value == 0))
252b5132 4388 {
ff4a8d2b
NC		 4389 unsigned long u_reg = 16;
4390 unsigned long U_reg = 16;
ab8e2090 4391 bfd_boolean is_unpredictable = FALSE;
05413229 4392 signed long value_in_comment = 0;
6b5d3a4d 4393 const char *c;
b34976b6 4394
252b5132
RH		 4395 for (c = insn->assembler; *c; c++)
4396 {
4397 if (*c == '%')
4398 {
c1e26897
NC		 4399 bfd_boolean allow_unpredictable = FALSE;
4400
252b5132
RH		 4401 switch (*++c)
4402 {
4403 case '%':
4404 func (stream, "%%");
4405 break;
4406
4407 case 'a':
05413229 4408 value_in_comment = print_arm_address (pc, info, given);
62b3e311 4409 break;
252b5132 4410
62b3e311
PB		 4411 case 'P':
4412 /* Set P address bit and use normal address
4413 printing routine. */
c1e26897 4414 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 4415 break;
4416
c1e26897
NC		 4417 case 'S':
4418 allow_unpredictable = TRUE;
252b5132
RH		 4419 case 's':
4420 if ((given & 0x004f0000) == 0x004f0000)
4421 {
58efb6c0 4422 /* PC relative with immediate offset. */
f8b960bc 4423 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 4424
aefd8a40
NC		 4425 if (PRE_BIT_SET)
4426 {
26d97720
NS		 4427 /* Elide positive zero offset. */
4428 if (offset || NEGATIVE_BIT_SET)
4429 func (stream, "[pc, #%s%d]\t; ",
d908c8af 4430 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 4431 else
26d97720
NS		 4432 func (stream, "[pc]\t; ");
4433 if (NEGATIVE_BIT_SET)
4434 offset = -offset;
aefd8a40
NC		 4435 info->print_address_func (offset + pc + 8, info);
4436 }
4437 else
4438 {
26d97720
NS		 4439 /* Always show the offset. */
4440 func (stream, "[pc], #%s%d",
d908c8af 4441 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 4442 if (! allow_unpredictable)
4443 is_unpredictable = TRUE;
aefd8a40 4444 }
252b5132
RH		 4445 }
4446 else
4447 {
fe56b6ce
NC		 4448 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
4449
b34976b6 4450 func (stream, "[%s",
252b5132 4451 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 4452
c1e26897 4453 if (PRE_BIT_SET)
252b5132 4454 {
c1e26897 4455 if (IMMEDIATE_BIT_SET)
252b5132 4456 {
26d97720
NS		 4457 /* Elide offset for non-writeback
4458 positive zero. */
4459 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
4460 || offset)
4461 func (stream, ", #%s%d",
4462 NEGATIVE_BIT_SET ? "-" : "", offset);
4463
4464 if (NEGATIVE_BIT_SET)
4465 offset = -offset;
945ee430 4466
fe56b6ce 4467 value_in_comment = offset;
252b5132 4468 }
945ee430 4469 else
ff4a8d2b
NC		 4470 {
4471 /* Register Offset or Register Pre-Indexed. */
4472 func (stream, ", %s%s",
4473 NEGATIVE_BIT_SET ? "-" : "",
4474 arm_regnames[given & 0xf]);
4475
4476 /* Writing back to the register that is the source/
4477 destination of the load/store is unpredictable. */
4478 if (! allow_unpredictable
4479 && WRITEBACK_BIT_SET
4480 && ((given & 0xf) == ((given >> 12) & 0xf)))
4481 is_unpredictable = TRUE;
4482 }
252b5132 4483
b34976b6 4484 func (stream, "]%s",
c1e26897 4485 WRITEBACK_BIT_SET ? "!" : "");
252b5132 4486 }
945ee430 4487 else
252b5132 4488 {
c1e26897 4489 if (IMMEDIATE_BIT_SET)
252b5132 4490 {
945ee430 4491 /* Immediate Post-indexed. */
aefd8a40 4492 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 4493 func (stream, "], #%s%d",
4494 NEGATIVE_BIT_SET ? "-" : "", offset);
4495 if (NEGATIVE_BIT_SET)
4496 offset = -offset;
fe56b6ce 4497 value_in_comment = offset;
252b5132 4498 }
945ee430 4499 else
ff4a8d2b
NC		 4500 {
4501 /* Register Post-indexed. */
4502 func (stream, "], %s%s",
4503 NEGATIVE_BIT_SET ? "-" : "",
4504 arm_regnames[given & 0xf]);
4505
4506 /* Writing back to the register that is the source/
4507 destination of the load/store is unpredictable. */
4508 if (! allow_unpredictable
4509 && (given & 0xf) == ((given >> 12) & 0xf))
4510 is_unpredictable = TRUE;
4511 }
c1e26897 4512
07a28fab
NC		 4513 if (! allow_unpredictable)
4514 {
4515 /* Writeback is automatically implied by post- addressing.
4516 Setting the W bit is unnecessary and ARM specify it as
4517 being unpredictable. */
4518 if (WRITEBACK_BIT_SET
4519 /* Specifying the PC register as the post-indexed
4520 registers is also unpredictable. */
ab8e2090
NC		 4521 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
4522 is_unpredictable = TRUE;
07a28fab 4523 }
252b5132
RH		 4524 }
4525 }
4526 break;
b34976b6 4527
252b5132 4528 case 'b':
6b5d3a4d 4529 {
f8b960bc 4530 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
05413229 4531 info->print_address_func (disp * 4 + pc + 8, info);
6b5d3a4d 4532 }
252b5132
RH		 4533 break;
4534
4535 case 'c':
c22aaad1
PB		 4536 if (((given >> 28) & 0xf) != 0xe)
4537 func (stream, "%s",
4538 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 4539 break;
4540
4541 case 'm':
4542 {
4543 int started = 0;
4544 int reg;
4545
4546 func (stream, "{");
4547 for (reg = 0; reg < 16; reg++)
4548 if ((given & (1 << reg)) != 0)
4549 {
4550 if (started)
4551 func (stream, ", ");
4552 started = 1;
4553 func (stream, "%s", arm_regnames[reg]);
4554 }
4555 func (stream, "}");
ab8e2090
NC		 4556 if (! started)
4557 is_unpredictable = TRUE;
252b5132
RH		 4558 }
4559 break;
4560
37b37b2d 4561 case 'q':
78c66db8 4562 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 4563 break;
4564
252b5132
RH		 4565 case 'o':
4566 if ((given & 0x02000000) != 0)
4567 {
a415b1cd
JB		 4568 unsigned int rotate = (given & 0xf00) >> 7;
4569 unsigned int immed = (given & 0xff);
4570 unsigned int a, i;
4571
4572 a = (((immed << (32 - rotate))
4573 | (immed >> rotate)) & 0xffffffff);
4574 /* If there is another encoding with smaller rotate,
4575 the rotate should be specified directly. */
4576 for (i = 0; i < 32; i += 2)
4577 if ((a << i | a >> (32 - i)) <= 0xff)
4578 break;
4579
4580 if (i != rotate)
4581 func (stream, "#%d, %d", immed, rotate);
4582 else
4583 func (stream, "#%d", a);
4584 value_in_comment = a;
252b5132
RH		 4585 }
4586 else
78c66db8 4587 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 4588 break;
4589
4590 case 'p':
4591 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 4592 {
823d2571
TG		 4593 arm_feature_set arm_ext_v6 =
4594 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
4595
aefd8a40
NC		 4596 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
4597 mechanism for setting PSR flag bits. They are
4598 obsolete in V6 onwards. */
823d2571
TG		 4599 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
4600 arm_ext_v6))
aefd8a40
NC		 4601 func (stream, "p");
4602 }
252b5132
RH		 4603 break;
4604
4605 case 't':
4606 if ((given & 0x01200000) == 0x00200000)
4607 func (stream, "t");
4608 break;
4609
252b5132 4610 case 'A':
05413229
NC		 4611 {
4612 int offset = given & 0xff;
f02232aa 4613
05413229 4614 value_in_comment = offset * 4;
c1e26897 4615 if (NEGATIVE_BIT_SET)
05413229 4616 value_in_comment = - value_in_comment;
f02232aa 4617
05413229 4618 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 4619
c1e26897 4620 if (PRE_BIT_SET)
05413229
NC		 4621 {
4622 if (offset)
fe56b6ce 4623 func (stream, ", #%d]%s",
d908c8af 4624 (int) value_in_comment,
c1e26897 4625 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 4626 else
4627 func (stream, "]");
4628 }
4629 else
4630 {
4631 func (stream, "]");
f02232aa 4632
c1e26897 4633 if (WRITEBACK_BIT_SET)
05413229
NC		 4634 {
4635 if (offset)
d908c8af 4636 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 4637 }
4638 else
fe56b6ce 4639 {
d908c8af 4640 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 4641 value_in_comment = offset;
4642 }
05413229
NC		 4643 }
4644 }
252b5132
RH		 4645 break;
4646
077b8428
NC		 4647 case 'B':
4648 /* Print ARM V5 BLX(1) address: pc+25 bits. */
4649 {
4650 bfd_vma address;
4651 bfd_vma offset = 0;
b34976b6 4652
c1e26897 4653 if (! NEGATIVE_BIT_SET)
077b8428
NC		 4654 /* Is signed, hi bits should be ones. */
4655 offset = (-1) ^ 0x00ffffff;
4656
4657 /* Offset is (SignExtend(offset field)<<2). */
4658 offset += given & 0x00ffffff;
4659 offset <<= 2;
4660 address = offset + pc + 8;
b34976b6 4661
8f06b2d8
PB		 4662 if (given & 0x01000000)
4663 /* H bit allows addressing to 2-byte boundaries. */
4664 address += 2;
b1ee46c5 4665
8f06b2d8 4666 info->print_address_func (address, info);
b1ee46c5 4667 }
b1ee46c5
AH		 4668 break;
4669
252b5132 4670 case 'C':
90ec0d68
MGD		 4671 if ((given & 0x02000200) == 0x200)
4672 {
4673 const char * name;
4674 unsigned sysm = (given & 0x004f0000) >> 16;
4675
4676 sysm |= (given & 0x300) >> 4;
4677 name = banked_regname (sysm);
4678
4679 if (name != NULL)
4680 func (stream, "%s", name);
4681 else
d908c8af 4682 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 4683 }
4684 else
4685 {
4686 func (stream, "%cPSR_",
4687 (given & 0x00400000) ? 'S' : 'C');
4688 if (given & 0x80000)
4689 func (stream, "f");
4690 if (given & 0x40000)
4691 func (stream, "s");
4692 if (given & 0x20000)
4693 func (stream, "x");
4694 if (given & 0x10000)
4695 func (stream, "c");
4696 }
252b5132
RH		 4697 break;
4698
62b3e311 4699 case 'U':
52e7f43d 4700 if ((given & 0xf0) == 0x60)
62b3e311 4701 {
52e7f43d
RE		 4702 switch (given & 0xf)
4703 {
4704 case 0xf: func (stream, "sy"); break;
4705 default:
4706 func (stream, "#%d", (int) given & 0xf);
4707 break;
4708 }
4709 }
4710 else
4711 {
e797f7e0
MGD		 4712 const char * opt = data_barrier_option (given & 0xf);
4713 if (opt != NULL)
4714 func (stream, "%s", opt);
4715 else
52e7f43d 4716 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 4717 }
4718 break;
4719
b34976b6 4720 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 4721 case '5': case '6': case '7': case '8': case '9':
4722 {
16980d0b
JB		 4723 int width;
4724 unsigned long value;
252b5132 4725
16980d0b
JB		 4726 c = arm_decode_bitfield (c, given, &value, &width);
4727
252b5132
RH		 4728 switch (*c)
4729 {
ab8e2090
NC		 4730 case 'R':
4731 if (value == 15)
4732 is_unpredictable = TRUE;
4733 /* Fall through. */
16980d0b 4734 case 'r':
9eb6c0f1
MGD		 4735 case 'T':
4736 /* We want register + 1 when decoding T. */
4737 if (*c == 'T')
4738 ++value;
4739
ff4a8d2b
NC		 4740 if (c[1] == 'u')
4741 {
4742 /* Eat the 'u' character. */
4743 ++ c;
4744
4745 if (u_reg == value)
4746 is_unpredictable = TRUE;
4747 u_reg = value;
4748 }
4749 if (c[1] == 'U')
4750 {
4751 /* Eat the 'U' character. */
4752 ++ c;
4753
4754 if (U_reg == value)
4755 is_unpredictable = TRUE;
4756 U_reg = value;
4757 }
16980d0b
JB		 4758 func (stream, "%s", arm_regnames[value]);
4759 break;
4760 case 'd':
4761 func (stream, "%ld", value);
05413229 4762 value_in_comment = value;
16980d0b
JB		 4763 break;
4764 case 'b':
4765 func (stream, "%ld", value * 8);
05413229 4766 value_in_comment = value * 8;
16980d0b
JB		 4767 break;
4768 case 'W':
4769 func (stream, "%ld", value + 1);
05413229 4770 value_in_comment = value + 1;
16980d0b
JB		 4771 break;
4772 case 'x':
4773 func (stream, "0x%08lx", value);
4774
4775 /* Some SWI instructions have special
4776 meanings. */
4777 if ((given & 0x0fffffff) == 0x0FF00000)
4778 func (stream, "\t; IMB");
4779 else if ((given & 0x0fffffff) == 0x0FF00001)
4780 func (stream, "\t; IMBRange");
4781 break;
4782 case 'X':
4783 func (stream, "%01lx", value & 0xf);
05413229 4784 value_in_comment = value;
252b5132
RH		 4785 break;
4786 case '`':
4787 c++;
16980d0b 4788 if (value == 0)
252b5132
RH		 4789 func (stream, "%c", *c);
4790 break;
4791 case '\'':
4792 c++;
16980d0b 4793 if (value == ((1ul << width) - 1))
252b5132
RH		 4794 func (stream, "%c", *c);
4795 break;
4796 case '?':
fe56b6ce 4797 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 4798 c += 1 << width;
252b5132
RH		 4799 break;
4800 default:
4801 abort ();
4802 }
4803 break;
4804
0dd132b6
NC		 4805 case 'e':
4806 {
4807 int imm;
4808
4809 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
4810 func (stream, "%d", imm);
fe56b6ce 4811 value_in_comment = imm;
0dd132b6
NC		 4812 }
4813 break;
4814
0a003adc
ZW		 4815 case 'E':
4816 /* LSB and WIDTH fields of BFI or BFC. The machine-
4817 language instruction encodes LSB and MSB. */
4818 {
4819 long msb = (given & 0x001f0000) >> 16;
4820 long lsb = (given & 0x00000f80) >> 7;
91d6fa6a 4821 long w = msb - lsb + 1;
fe56b6ce 4822
91d6fa6a
NC		 4823 if (w > 0)
4824 func (stream, "#%lu, #%lu", lsb, w);
0a003adc
ZW		 4825 else
4826 func (stream, "(invalid: %lu:%lu)", lsb, msb);
4827 }
4828 break;
4829
90ec0d68
MGD		 4830 case 'R':
4831 /* Get the PSR/banked register name. */
4832 {
4833 const char * name;
4834 unsigned sysm = (given & 0x004f0000) >> 16;
4835
4836 sysm |= (given & 0x300) >> 4;
4837 name = banked_regname (sysm);
4838
4839 if (name != NULL)
4840 func (stream, "%s", name);
4841 else
d908c8af 4842 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 4843 }
4844 break;
4845
0a003adc
ZW		 4846 case 'V':
4847 /* 16-bit unsigned immediate from a MOVT or MOVW
4848 instruction, encoded in bits 0:11 and 15:19. */
4849 {
4850 long hi = (given & 0x000f0000) >> 4;
4851 long lo = (given & 0x00000fff);
4852 long imm16 = hi | lo;
fe56b6ce
NC		 4853
4854 func (stream, "#%lu", imm16);
4855 value_in_comment = imm16;
0a003adc
ZW		 4856 }
4857 break;
4858
252b5132
RH		 4859 default:
4860 abort ();
4861 }
4862 }
4863 }
4864 else
4865 func (stream, "%c", *c);
4866 }
05413229
NC		 4867
4868 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 4869 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 4870
4871 if (is_unpredictable)
4872 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 4873
4a5329c6 4874 return;
252b5132
RH		 4875 }
4876 }
4877 abort ();
4878}
4879
4a5329c6 4880/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 4881
4a5329c6
ZW		 4882static void
4883print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 4884{
6b5d3a4d 4885 const struct opcode16 *insn;
6a51a8a8
AM		 4886 void *stream = info->stream;
4887 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 4888
4889 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 4890 if ((given & insn->mask) == insn->value)
4891 {
05413229 4892 signed long value_in_comment = 0;
6b5d3a4d 4893 const char *c = insn->assembler;
05413229 4894
c19d1205
ZW		 4895 for (; *c; c++)
4896 {
4897 int domaskpc = 0;
4898 int domasklr = 0;
4899
4900 if (*c != '%')
4901 {
4902 func (stream, "%c", *c);
4903 continue;
4904 }
252b5132 4905
c19d1205
ZW		 4906 switch (*++c)
4907 {
4908 case '%':
4909 func (stream, "%%");
4910 break;
b34976b6 4911
c22aaad1
PB		 4912 case 'c':
4913 if (ifthen_state)
4914 func (stream, "%s", arm_conditional[IFTHEN_COND]);
4915 break;
4916
4917 case 'C':
4918 if (ifthen_state)
4919 func (stream, "%s", arm_conditional[IFTHEN_COND]);
4920 else
4921 func (stream, "s");
4922 break;
4923
4924 case 'I':
4925 {
4926 unsigned int tmp;
4927
4928 ifthen_next_state = given & 0xff;
4929 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
4930 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
4931 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
4932 }
4933 break;
4934
4935 case 'x':
4936 if (ifthen_next_state)
4937 func (stream, "\t; unpredictable branch in IT block\n");
4938 break;
4939
4940 case 'X':
4941 if (ifthen_state)
4942 func (stream, "\t; unpredictable <IT:%s>",
4943 arm_conditional[IFTHEN_COND]);
4944 break;
4945
c19d1205
ZW		 4946 case 'S':
4947 {
4948 long reg;
4949
4950 reg = (given >> 3) & 0x7;
4951 if (given & (1 << 6))
4952 reg += 8;
4f3c3dbb 4953
c19d1205
ZW		 4954 func (stream, "%s", arm_regnames[reg]);
4955 }
4956 break;
baf0cc5e 4957
c19d1205 4958 case 'D':
4f3c3dbb 4959 {
c19d1205
ZW		 4960 long reg;
4961
4962 reg = given & 0x7;
4963 if (given & (1 << 7))
4964 reg += 8;
4965
4966 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 4967 }
c19d1205
ZW		 4968 break;
4969
4970 case 'N':
4971 if (given & (1 << 8))
4972 domasklr = 1;
4973 /* Fall through. */
4974 case 'O':
4975 if (*c == 'O' && (given & (1 << 8)))
4976 domaskpc = 1;
4977 /* Fall through. */
4978 case 'M':
4979 {
4980 int started = 0;
4981 int reg;
4982
4983 func (stream, "{");
4984
4985 /* It would be nice if we could spot
4986 ranges, and generate the rS-rE format: */
4987 for (reg = 0; (reg < 8); reg++)
4988 if ((given & (1 << reg)) != 0)
4989 {
4990 if (started)
4991 func (stream, ", ");
4992 started = 1;
4993 func (stream, "%s", arm_regnames[reg]);
4994 }
4995
4996 if (domasklr)
4997 {
4998 if (started)
4999 func (stream, ", ");
5000 started = 1;
d908c8af 5001 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 5002 }
5003
5004 if (domaskpc)
5005 {
5006 if (started)
5007 func (stream, ", ");
d908c8af 5008 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 5009 }
5010
5011 func (stream, "}");
5012 }
5013 break;
5014
4547cb56
NC		 5015 case 'W':
5016 /* Print writeback indicator for a LDMIA. We are doing a
5017 writeback if the base register is not in the register
5018 mask. */
5019 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
5020 func (stream, "!");
5021 break;
5022
c19d1205
ZW		 5023 case 'b':
5024 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
5025 {
5026 bfd_vma address = (pc + 4
5027 + ((given & 0x00f8) >> 2)
5028 + ((given & 0x0200) >> 3));
5029 info->print_address_func (address, info);
5030 }
5031 break;
5032
5033 case 's':
5034 /* Right shift immediate -- bits 6..10; 1-31 print
5035 as themselves, 0 prints as 32. */
5036 {
5037 long imm = (given & 0x07c0) >> 6;
5038 if (imm == 0)
5039 imm = 32;
0fd3a477 5040 func (stream, "#%ld", imm);
c19d1205
ZW		 5041 }
5042 break;
5043
5044 case '0': case '1': case '2': case '3': case '4':
5045 case '5': case '6': case '7': case '8': case '9':
5046 {
5047 int bitstart = *c++ - '0';
5048 int bitend = 0;
5049
5050 while (*c >= '0' && *c <= '9')
5051 bitstart = (bitstart * 10) + *c++ - '0';
5052
5053 switch (*c)
5054 {
5055 case '-':
5056 {
f8b960bc 5057 bfd_vma reg;
c19d1205
ZW		 5058
5059 c++;
5060 while (*c >= '0' && *c <= '9')
5061 bitend = (bitend * 10) + *c++ - '0';
5062 if (!bitend)
5063 abort ();
5064 reg = given >> bitstart;
5065 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 5066
c19d1205
ZW		 5067 switch (*c)
5068 {
5069 case 'r':
5070 func (stream, "%s", arm_regnames[reg]);
5071 break;
5072
5073 case 'd':
d908c8af 5074 func (stream, "%ld", (long) reg);
05413229 5075 value_in_comment = reg;
c19d1205
ZW		 5076 break;
5077
5078 case 'H':
d908c8af 5079 func (stream, "%ld", (long) (reg << 1));
05413229 5080 value_in_comment = reg << 1;
c19d1205
ZW		 5081 break;
5082
5083 case 'W':
d908c8af 5084 func (stream, "%ld", (long) (reg << 2));
05413229 5085 value_in_comment = reg << 2;
c19d1205
ZW		 5086 break;
5087
5088 case 'a':
5089 /* PC-relative address -- the bottom two
5090 bits of the address are dropped
5091 before the calculation. */
5092 info->print_address_func
5093 (((pc + 4) & ~3) + (reg << 2), info);
05413229 5094 value_in_comment = 0;
c19d1205
ZW		 5095 break;
5096
5097 case 'x':
d908c8af 5098 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 5099 break;
5100
c19d1205
ZW		 5101 case 'B':
5102 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6b5d3a4d 5103 info->print_address_func (reg * 2 + pc + 4, info);
05413229 5104 value_in_comment = 0;
c19d1205
ZW		 5105 break;
5106
5107 case 'c':
c22aaad1 5108 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 5109 break;
5110
5111 default:
5112 abort ();
5113 }
5114 }
5115 break;
5116
5117 case '\'':
5118 c++;
5119 if ((given & (1 << bitstart)) != 0)
5120 func (stream, "%c", *c);
5121 break;
5122
5123 case '?':
5124 ++c;
5125 if ((given & (1 << bitstart)) != 0)
5126 func (stream, "%c", *c++);
5127 else
5128 func (stream, "%c", *++c);
5129 break;
5130
5131 default:
5132 abort ();
5133 }
5134 }
5135 break;
5136
5137 default:
5138 abort ();
5139 }
5140 }
05413229
NC		 5141
5142 if (value_in_comment > 32 || value_in_comment < -16)
5143 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 5144 return;
c19d1205
ZW		 5145 }
5146
5147 /* No match. */
5148 abort ();
5149}
5150
62b3e311 5151/* Return the name of an V7M special register. */
fe56b6ce 5152
62b3e311
PB		 5153static const char *
5154psr_name (int regno)
5155{
5156 switch (regno)
5157 {
5158 case 0: return "APSR";
5159 case 1: return "IAPSR";
5160 case 2: return "EAPSR";
5161 case 3: return "PSR";
5162 case 5: return "IPSR";
5163 case 6: return "EPSR";
5164 case 7: return "IEPSR";
5165 case 8: return "MSP";
5166 case 9: return "PSP";
5167 case 16: return "PRIMASK";
5168 case 17: return "BASEPRI";
00bbc0bd 5169 case 18: return "BASEPRI_MAX";
62b3e311
PB		 5170 case 19: return "FAULTMASK";
5171 case 20: return "CONTROL";
5172 default: return "<unknown>";
5173 }
5174}
5175
4a5329c6
ZW		 5176/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
5177
5178static void
5179print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 5180{
6b5d3a4d 5181 const struct opcode32 *insn;
c19d1205
ZW		 5182 void *stream = info->stream;
5183 fprintf_ftype func = info->fprintf_func;
5184
16980d0b
JB		 5185 if (print_insn_coprocessor (pc, info, given, TRUE))
5186 return;
5187
5188 if (print_insn_neon (info, given, TRUE))
8f06b2d8
PB		 5189 return;
5190
c19d1205
ZW		 5191 for (insn = thumb32_opcodes; insn->assembler; insn++)
5192 if ((given & insn->mask) == insn->value)
5193 {
ff4a8d2b 5194 bfd_boolean is_unpredictable = FALSE;
05413229 5195 signed long value_in_comment = 0;
6b5d3a4d 5196 const char *c = insn->assembler;
05413229 5197
c19d1205
ZW		 5198 for (; *c; c++)
5199 {
5200 if (*c != '%')
5201 {
5202 func (stream, "%c", *c);
5203 continue;
5204 }
5205
5206 switch (*++c)
5207 {
5208 case '%':
5209 func (stream, "%%");
5210 break;
5211
c22aaad1
PB		 5212 case 'c':
5213 if (ifthen_state)
5214 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5215 break;
5216
5217 case 'x':
5218 if (ifthen_next_state)
5219 func (stream, "\t; unpredictable branch in IT block\n");
5220 break;
5221
5222 case 'X':
5223 if (ifthen_state)
5224 func (stream, "\t; unpredictable <IT:%s>",
5225 arm_conditional[IFTHEN_COND]);
5226 break;
5227
c19d1205
ZW		 5228 case 'I':
5229 {
5230 unsigned int imm12 = 0;
fe56b6ce 5231
c19d1205
ZW		 5232 imm12 |= (given & 0x000000ffu);
5233 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 5234 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 5235 func (stream, "#%u", imm12);
5236 value_in_comment = imm12;
c19d1205
ZW		 5237 }
5238 break;
5239
5240 case 'M':
5241 {
5242 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 5243
c19d1205
ZW		 5244 bits |= (given & 0x000000ffu);
5245 bits |= (given & 0x00007000u) >> 4;
5246 bits |= (given & 0x04000000u) >> 15;
5247 imm8 = (bits & 0x0ff);
5248 mod = (bits & 0xf00) >> 8;
5249 switch (mod)
5250 {
5251 case 0: imm = imm8; break;
c1e26897
NC		 5252 case 1: imm = ((imm8 << 16) | imm8); break;
5253 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
5254 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 5255 default:
5256 mod = (bits & 0xf80) >> 7;
5257 imm8 = (bits & 0x07f) | 0x80;
5258 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
5259 }
fe56b6ce
NC		 5260 func (stream, "#%u", imm);
5261 value_in_comment = imm;
c19d1205
ZW		 5262 }
5263 break;
5264
5265 case 'J':
5266 {
5267 unsigned int imm = 0;
fe56b6ce 5268
c19d1205
ZW		 5269 imm |= (given & 0x000000ffu);
5270 imm |= (given & 0x00007000u) >> 4;
5271 imm |= (given & 0x04000000u) >> 15;
5272 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 5273 func (stream, "#%u", imm);
5274 value_in_comment = imm;
c19d1205
ZW		 5275 }
5276 break;
5277
5278 case 'K':
5279 {
5280 unsigned int imm = 0;
fe56b6ce 5281
c19d1205
ZW		 5282 imm |= (given & 0x000f0000u) >> 16;
5283 imm |= (given & 0x00000ff0u) >> 0;
5284 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 5285 func (stream, "#%u", imm);
5286 value_in_comment = imm;
c19d1205
ZW		 5287 }
5288 break;
5289
74db7efb
NC		 5290 case 'H':
5291 {
5292 unsigned int imm = 0;
5293
5294 imm |= (given & 0x000f0000u) >> 4;
5295 imm |= (given & 0x00000fffu) >> 0;
5296 func (stream, "#%u", imm);
5297 value_in_comment = imm;
5298 }
5299 break;
5300
90ec0d68
MGD		 5301 case 'V':
5302 {
5303 unsigned int imm = 0;
5304
5305 imm |= (given & 0x00000fffu);
5306 imm |= (given & 0x000f0000u) >> 4;
5307 func (stream, "#%u", imm);
5308 value_in_comment = imm;
5309 }
5310 break;
5311
c19d1205
ZW		 5312 case 'S':
5313 {
5314 unsigned int reg = (given & 0x0000000fu);
5315 unsigned int stp = (given & 0x00000030u) >> 4;
5316 unsigned int imm = 0;
5317 imm |= (given & 0x000000c0u) >> 6;
5318 imm |= (given & 0x00007000u) >> 10;
5319
5320 func (stream, "%s", arm_regnames[reg]);
5321 switch (stp)
5322 {
5323 case 0:
5324 if (imm > 0)
5325 func (stream, ", lsl #%u", imm);
5326 break;
5327
5328 case 1:
5329 if (imm == 0)
5330 imm = 32;
5331 func (stream, ", lsr #%u", imm);
5332 break;
5333
5334 case 2:
5335 if (imm == 0)
5336 imm = 32;
5337 func (stream, ", asr #%u", imm);
5338 break;
5339
5340 case 3:
5341 if (imm == 0)
5342 func (stream, ", rrx");
5343 else
5344 func (stream, ", ror #%u", imm);
5345 }
5346 }
5347 break;
5348
5349 case 'a':
5350 {
5351 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 5352 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 5353 unsigned int op = (given & 0x00000f00) >> 8;
5354 unsigned int i12 = (given & 0x00000fff);
5355 unsigned int i8 = (given & 0x000000ff);
5356 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 5357 bfd_vma offset = 0;
c19d1205
ZW		 5358
5359 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 5360 if (U) /* 12-bit positive immediate offset. */
5361 {
5362 offset = i12;
5363 if (Rn != 15)
5364 value_in_comment = offset;
5365 }
5366 else if (Rn == 15) /* 12-bit negative immediate offset. */
5367 offset = - (int) i12;
5368 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 5369 {
5370 unsigned int Rm = (i8 & 0x0f);
5371 unsigned int sh = (i8 & 0x30) >> 4;
05413229 5372
c19d1205
ZW		 5373 func (stream, ", %s", arm_regnames[Rm]);
5374 if (sh)
5375 func (stream, ", lsl #%u", sh);
5376 func (stream, "]");
5377 break;
5378 }
5379 else switch (op)
5380 {
05413229 5381 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 5382 offset = i8;
5383 break;
5384
05413229 5385 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 5386 offset = -i8;
5387 break;
5388
05413229 5389 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 5390 offset = i8;
5391 writeback = TRUE;
5392 break;
5393
05413229 5394 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 5395 offset = -i8;
5396 writeback = TRUE;
5397 break;
5398
05413229 5399 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 5400 offset = i8;
5401 postind = TRUE;
5402 break;
5403
05413229 5404 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 5405 offset = -i8;
5406 postind = TRUE;
5407 break;
5408
5409 default:
5410 func (stream, ", <undefined>]");
5411 goto skip;
5412 }
5413
5414 if (postind)
d908c8af 5415 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 5416 else
5417 {
5418 if (offset)
d908c8af 5419 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 5420 func (stream, writeback ? "]!" : "]");
5421 }
5422
5423 if (Rn == 15)
5424 {
5425 func (stream, "\t; ");
5426 info->print_address_func (((pc + 4) & ~3) + offset, info);
5427 }
5428 }
5429 skip:
5430 break;
5431
5432 case 'A':
5433 {
c1e26897
NC		 5434 unsigned int U = ! NEGATIVE_BIT_SET;
5435 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 5436 unsigned int Rn = (given & 0x000f0000) >> 16;
5437 unsigned int off = (given & 0x000000ff);
5438
5439 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 5440
5441 if (PRE_BIT_SET)
c19d1205
ZW		 5442 {
5443 if (off || !U)
05413229
NC		 5444 {
5445 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
5446 value_in_comment = off * 4 * U ? 1 : -1;
5447 }
c19d1205
ZW		 5448 func (stream, "]");
5449 if (W)
5450 func (stream, "!");
5451 }
5452 else
5453 {
5454 func (stream, "], ");
5455 if (W)
05413229
NC		 5456 {
5457 func (stream, "#%c%u", U ? '+' : '-', off * 4);
5458 value_in_comment = off * 4 * U ? 1 : -1;
5459 }
c19d1205 5460 else
fe56b6ce
NC		 5461 {
5462 func (stream, "{%u}", off);
5463 value_in_comment = off;
5464 }
c19d1205
ZW		 5465 }
5466 }
5467 break;
5468
5469 case 'w':
5470 {
5471 unsigned int Sbit = (given & 0x01000000) >> 24;
5472 unsigned int type = (given & 0x00600000) >> 21;
05413229 5473
c19d1205
ZW		 5474 switch (type)
5475 {
5476 case 0: func (stream, Sbit ? "sb" : "b"); break;
5477 case 1: func (stream, Sbit ? "sh" : "h"); break;
5478 case 2:
5479 if (Sbit)
5480 func (stream, "??");
5481 break;
5482 case 3:
5483 func (stream, "??");
5484 break;
5485 }
5486 }
5487 break;
5488
5489 case 'm':
5490 {
5491 int started = 0;
5492 int reg;
5493
5494 func (stream, "{");
5495 for (reg = 0; reg < 16; reg++)
5496 if ((given & (1 << reg)) != 0)
5497 {
5498 if (started)
5499 func (stream, ", ");
5500 started = 1;
5501 func (stream, "%s", arm_regnames[reg]);
5502 }
5503 func (stream, "}");
5504 }
5505 break;
5506
5507 case 'E':
5508 {
5509 unsigned int msb = (given & 0x0000001f);
5510 unsigned int lsb = 0;
fe56b6ce 5511
c19d1205
ZW		 5512 lsb |= (given & 0x000000c0u) >> 6;
5513 lsb |= (given & 0x00007000u) >> 10;
5514 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
5515 }
5516 break;
5517
5518 case 'F':
5519 {
5520 unsigned int width = (given & 0x0000001f) + 1;
5521 unsigned int lsb = 0;
fe56b6ce 5522
c19d1205
ZW		 5523 lsb |= (given & 0x000000c0u) >> 6;
5524 lsb |= (given & 0x00007000u) >> 10;
5525 func (stream, "#%u, #%u", lsb, width);
5526 }
5527 break;
5528
5529 case 'b':
5530 {
5531 unsigned int S = (given & 0x04000000u) >> 26;
5532 unsigned int J1 = (given & 0x00002000u) >> 13;
5533 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 5534 bfd_vma offset = 0;
c19d1205
ZW		 5535
5536 offset |= !S << 20;
5537 offset |= J2 << 19;
5538 offset |= J1 << 18;
5539 offset |= (given & 0x003f0000) >> 4;
5540 offset |= (given & 0x000007ff) << 1;
5541 offset -= (1 << 20);
5542
5543 info->print_address_func (pc + 4 + offset, info);
5544 }
5545 break;
5546
5547 case 'B':
5548 {
5549 unsigned int S = (given & 0x04000000u) >> 26;
5550 unsigned int I1 = (given & 0x00002000u) >> 13;
5551 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 5552 bfd_vma offset = 0;
c19d1205
ZW		 5553
5554 offset |= !S << 24;
5555 offset |= !(I1 ^ S) << 23;
5556 offset |= !(I2 ^ S) << 22;
5557 offset |= (given & 0x03ff0000u) >> 4;
5558 offset |= (given & 0x000007ffu) << 1;
5559 offset -= (1 << 24);
36b0c57d 5560 offset += pc + 4;
c19d1205 5561
36b0c57d
PB		 5562 /* BLX target addresses are always word aligned. */
5563 if ((given & 0x00001000u) == 0)
5564 offset &= ~2u;
5565
5566 info->print_address_func (offset, info);
c19d1205
ZW		 5567 }
5568 break;
5569
5570 case 's':
5571 {
5572 unsigned int shift = 0;
fe56b6ce 5573
c19d1205
ZW		 5574 shift |= (given & 0x000000c0u) >> 6;
5575 shift |= (given & 0x00007000u) >> 10;
c1e26897 5576 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 5577 func (stream, ", asr #%u", shift);
5578 else if (shift)
5579 func (stream, ", lsl #%u", shift);
5580 /* else print nothing - lsl #0 */
5581 }
5582 break;
5583
5584 case 'R':
5585 {
5586 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 5587
c19d1205
ZW		 5588 if (rot)
5589 func (stream, ", ror #%u", rot * 8);
5590 }
5591 break;
5592
62b3e311 5593 case 'U':
52e7f43d 5594 if ((given & 0xf0) == 0x60)
62b3e311 5595 {
52e7f43d
RE		 5596 switch (given & 0xf)
5597 {
5598 case 0xf: func (stream, "sy"); break;
5599 default:
5600 func (stream, "#%d", (int) given & 0xf);
5601 break;
5602 }
62b3e311 5603 }
52e7f43d
RE		 5604 else
5605 {
e797f7e0
MGD		 5606 const char * opt = data_barrier_option (given & 0xf);
5607 if (opt != NULL)
5608 func (stream, "%s", opt);
5609 else
5610 func (stream, "#%d", (int) given & 0xf);
52e7f43d 5611 }
62b3e311
PB		 5612 break;
5613
5614 case 'C':
5615 if ((given & 0xff) == 0)
5616 {
5617 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
5618 if (given & 0x800)
5619 func (stream, "f");
5620 if (given & 0x400)
5621 func (stream, "s");
5622 if (given & 0x200)
5623 func (stream, "x");
5624 if (given & 0x100)
5625 func (stream, "c");
5626 }
90ec0d68
MGD		 5627 else if ((given & 0x20) == 0x20)
5628 {
5629 char const* name;
5630 unsigned sysm = (given & 0xf00) >> 8;
5631
5632 sysm |= (given & 0x30);
5633 sysm |= (given & 0x00100000) >> 14;
5634 name = banked_regname (sysm);
5635
5636 if (name != NULL)
5637 func (stream, "%s", name);
5638 else
d908c8af 5639 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 5640 }
62b3e311
PB		 5641 else
5642 {
d908c8af 5643 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 5644 }
5645 break;
5646
5647 case 'D':
90ec0d68
MGD		 5648 if (((given & 0xff) == 0)
5649 || ((given & 0x20) == 0x20))
5650 {
5651 char const* name;
5652 unsigned sm = (given & 0xf0000) >> 16;
5653
5654 sm |= (given & 0x30);
5655 sm |= (given & 0x00100000) >> 14;
5656 name = banked_regname (sm);
5657
5658 if (name != NULL)
5659 func (stream, "%s", name);
5660 else
d908c8af 5661 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 5662 }
62b3e311 5663 else
d908c8af 5664 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 5665 break;
5666
c19d1205
ZW		 5667 case '0': case '1': case '2': case '3': case '4':
5668 case '5': case '6': case '7': case '8': case '9':
5669 {
16980d0b
JB		 5670 int width;
5671 unsigned long val;
c19d1205 5672
16980d0b
JB		 5673 c = arm_decode_bitfield (c, given, &val, &width);
5674
c19d1205
ZW		 5675 switch (*c)
5676 {
05413229
NC		 5677 case 'd':
5678 func (stream, "%lu", val);
5679 value_in_comment = val;
5680 break;
ff4a8d2b 5681
05413229
NC		 5682 case 'W':
5683 func (stream, "%lu", val * 4);
5684 value_in_comment = val * 4;
5685 break;
ff4a8d2b 5686
dd5181d5
KT		 5687 case 'S':
5688 if (val == 13)
5689 is_unpredictable = TRUE;
5690 /* Fall through. */
ff4a8d2b
NC		 5691 case 'R':
5692 if (val == 15)
5693 is_unpredictable = TRUE;
5694 /* Fall through. */
5695 case 'r':
5696 func (stream, "%s", arm_regnames[val]);
5697 break;
c19d1205
ZW		 5698
5699 case 'c':
c22aaad1 5700 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 5701 break;
5702
5703 case '\'':
c19d1205 5704 c++;
16980d0b
JB		 5705 if (val == ((1ul << width) - 1))
5706 func (stream, "%c", *c);
c19d1205
ZW		 5707 break;
5708
5709 case '`':
c19d1205 5710 c++;
16980d0b
JB		 5711 if (val == 0)
5712 func (stream, "%c", *c);
c19d1205
ZW		 5713 break;
5714
5715 case '?':
fe56b6ce 5716 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 5717 c += 1 << width;
c19d1205 5718 break;
0bb027fd
RR		 5719
5720 case 'x':
5721 func (stream, "0x%lx", val & 0xffffffffUL);
5722 break;
c19d1205
ZW		 5723
5724 default:
5725 abort ();
5726 }
5727 }
5728 break;
5729
32a94698
NC		 5730 case 'L':
5731 /* PR binutils/12534
5732 If we have a PC relative offset in an LDRD or STRD
5733 instructions then display the decoded address. */
5734 if (((given >> 16) & 0xf) == 0xf)
5735 {
5736 bfd_vma offset = (given & 0xff) * 4;
5737
5738 if ((given & (1 << 23)) == 0)
5739 offset = - offset;
5740 func (stream, "\t; ");
5741 info->print_address_func ((pc & ~3) + 4 + offset, info);
5742 }
5743 break;
5744
c19d1205
ZW		 5745 default:
5746 abort ();
5747 }
5748 }
05413229
NC		 5749
5750 if (value_in_comment > 32 || value_in_comment < -16)
5751 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 5752
5753 if (is_unpredictable)
5754 func (stream, UNPREDICTABLE_INSTRUCTION);
5755
4a5329c6 5756 return;
c19d1205 5757 }
252b5132 5758
58efb6c0 5759 /* No match. */
252b5132
RH		 5760 abort ();
5761}
5762
e821645d
DJ		 5763/* Print data bytes on INFO->STREAM. */
5764
5765static void
fe56b6ce
NC		 5766print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
5767 struct disassemble_info *info,
e821645d
DJ		 5768 long given)
5769{
5770 switch (info->bytes_per_chunk)
5771 {
5772 case 1:
5773 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
5774 break;
5775 case 2:
5776 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
5777 break;
5778 case 4:
5779 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
5780 break;
5781 default:
5782 abort ();
5783 }
5784}
5785
22a398e1 5786/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 5787 being displayed in symbol relative addresses.
5788
5789 Also disallow private symbol, with __tagsym$$ prefix,
5790 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 5791
5792bfd_boolean
5793arm_symbol_is_valid (asymbol * sym,
5794 struct disassemble_info * info ATTRIBUTE_UNUSED)
5795{
5796 const char * name;
5797
5798 if (sym == NULL)
5799 return FALSE;
5800
5801 name = bfd_asymbol_name (sym);
5802
d8282f0e 5803 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 5804}
5805
58efb6c0 5806/* Parse an individual disassembler option. */
baf0cc5e 5807
a3d9c82d 5808void
4a5329c6 5809parse_arm_disassembler_option (char *option)
dd92f639 5810{
01c7f630 5811 if (option == NULL)
dd92f639 5812 return;
b34976b6 5813
0112cd26 5814 if (CONST_STRNEQ (option, "reg-names-"))
dd92f639 5815 {
58efb6c0 5816 int i;
b34976b6 5817
01c7f630 5818 option += 10;
58efb6c0
NC		 5819
5820 for (i = NUM_ARM_REGNAMES; i--;)
31e0f3cd 5821 if (strneq (option, regnames[i].name, strlen (regnames[i].name)))
58efb6c0
NC		 5822 {
5823 regname_selected = i;
5824 break;
5825 }
b34976b6 5826
58efb6c0 5827 if (i < 0)
31e0f3cd 5828 /* XXX - should break 'option' at following delimiter. */
58efb6c0 5829 fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
dd92f639 5830 }
0112cd26 5831 else if (CONST_STRNEQ (option, "force-thumb"))
01c7f630 5832 force_thumb = 1;
0112cd26 5833 else if (CONST_STRNEQ (option, "no-force-thumb"))
01c7f630 5834 force_thumb = 0;
dd92f639 5835 else
31e0f3cd 5836 /* XXX - should break 'option' at following delimiter. */
58efb6c0 5837 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
b34976b6 5838
dd92f639
NC		 5839 return;
5840}
5841
31e0f3cd
NC		 5842/* Parse the string of disassembler options, spliting it at whitespaces
5843 or commas. (Whitespace separators supported for backwards compatibility). */
baf0cc5e 5844
01c7f630 5845static void
4a5329c6 5846parse_disassembler_options (char *options)
01c7f630 5847{
01c7f630
NC		 5848 if (options == NULL)
5849 return;
5850
31e0f3cd 5851 while (*options)
01c7f630 5852 {
31e0f3cd
NC		 5853 parse_arm_disassembler_option (options);
5854
5855 /* Skip forward to next seperator. */
5856 while ((*options) && (! ISSPACE (*options)) && (*options != ','))
5857 ++ options;
5858 /* Skip forward past seperators. */
5859 while (ISSPACE (*options) || (*options == ','))
5860 ++ options;
01c7f630 5861 }
01c7f630
NC		 5862}
5863
c22aaad1
PB		 5864/* Search back through the insn stream to determine if this instruction is
5865 conditionally executed. */
fe56b6ce 5866
c22aaad1 5867static void
fe56b6ce
NC		 5868find_ifthen_state (bfd_vma pc,
5869 struct disassemble_info *info,
c22aaad1
PB		 5870 bfd_boolean little)
5871{
5872 unsigned char b[2];
5873 unsigned int insn;
5874 int status;
5875 /* COUNT is twice the number of instructions seen. It will be odd if we
5876 just crossed an instruction boundary. */
5877 int count;
5878 int it_count;
5879 unsigned int seen_it;
5880 bfd_vma addr;
5881
5882 ifthen_address = pc;
5883 ifthen_state = 0;
5884
5885 addr = pc;
5886 count = 1;
5887 it_count = 0;
5888 seen_it = 0;
5889 /* Scan backwards looking for IT instructions, keeping track of where
5890 instruction boundaries are. We don't know if something is actually an
5891 IT instruction until we find a definite instruction boundary. */
5892 for (;;)
5893 {
fe56b6ce 5894 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 5895 {
5896 /* A symbol must be on an instruction boundary, and will not
5897 be within an IT block. */
5898 if (seen_it && (count & 1))
5899 break;
5900
5901 return;
5902 }
5903 addr -= 2;
fe56b6ce 5904 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 5905 if (status)
5906 return;
5907
5908 if (little)
5909 insn = (b[0]) | (b[1] << 8);
5910 else
5911 insn = (b[1]) | (b[0] << 8);
5912 if (seen_it)
5913 {
5914 if ((insn & 0xf800) < 0xe800)
5915 {
5916 /* Addr + 2 is an instruction boundary. See if this matches
5917 the expected boundary based on the position of the last
5918 IT candidate. */
5919 if (count & 1)
5920 break;
5921 seen_it = 0;
5922 }
5923 }
5924 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
5925 {
5926 /* This could be an IT instruction. */
5927 seen_it = insn;
5928 it_count = count >> 1;
5929 }
5930 if ((insn & 0xf800) >= 0xe800)
5931 count++;
5932 else
5933 count = (count + 2) | 1;
5934 /* IT blocks contain at most 4 instructions. */
5935 if (count >= 8 && !seen_it)
5936 return;
5937 }
5938 /* We found an IT instruction. */
5939 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
5940 if ((ifthen_state & 0xf) == 0)
5941 ifthen_state = 0;
5942}
5943
b0e28b39
DJ		 5944/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
5945 mapping symbol. */
5946
5947static int
5948is_mapping_symbol (struct disassemble_info *info, int n,
5949 enum map_type *map_type)
5950{
5951 const char *name;
5952
5953 name = bfd_asymbol_name (info->symtab[n]);
5954 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
5955 && (name[2] == 0 || name[2] == '.'))
5956 {
5957 *map_type = ((name[1] == 'a') ? MAP_ARM
5958 : (name[1] == 't') ? MAP_THUMB
5959 : MAP_DATA);
5960 return TRUE;
5961 }
5962
5963 return FALSE;
5964}
5965
5966/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
5967 Returns nonzero if *MAP_TYPE was set. */
5968
5969static int
5970get_map_sym_type (struct disassemble_info *info,
5971 int n,
5972 enum map_type *map_type)
5973{
5974 /* If the symbol is in a different section, ignore it. */
5975 if (info->section != NULL && info->section != info->symtab[n]->section)
5976 return FALSE;
5977
5978 return is_mapping_symbol (info, n, map_type);
5979}
5980
5981/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 5982 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 5983
5984static int
fe56b6ce
NC		 5985get_sym_code_type (struct disassemble_info *info,
5986 int n,
e821645d 5987 enum map_type *map_type)
2087ad84
PB		 5988{
5989 elf_symbol_type *es;
5990 unsigned int type;
b0e28b39
DJ		 5991
5992 /* If the symbol is in a different section, ignore it. */
5993 if (info->section != NULL && info->section != info->symtab[n]->section)
5994 return FALSE;
2087ad84 5995
e821645d 5996 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 5997 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
5998
5999 /* If the symbol has function type then use that. */
34e77a92 6000 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 6001 {
35fc36a8
RS		 6002 if (ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym) == ST_BRANCH_TO_THUMB)
6003 *map_type = MAP_THUMB;
6004 else
6005 *map_type = MAP_ARM;
2087ad84
PB		 6006 return TRUE;
6007 }
6008
2087ad84
PB		 6009 return FALSE;
6010}
6011
0313a2b8
NC		 6012/* Given a bfd_mach_arm_XXX value, this function fills in the fields
6013 of the supplied arm_feature_set structure with bitmasks indicating
6014 the support base architectures and coprocessor extensions.
6015
6016 FIXME: This could more efficiently implemented as a constant array,
6017 although it would also be less robust. */
6018
6019static void
6020select_arm_features (unsigned long mach,
6021 arm_feature_set * features)
6022{
823d2571
TG		 6023#undef ARM_FEATURE_LOW
6024#define ARM_FEATURE_LOW(ARCH1,CEXT) \
6025 features->core[0] = (ARCH1); \
6026 features->core[1] = 0; \
0313a2b8
NC		 6027 features->coproc = (CEXT) | FPU_FPA; \
6028 return
6029
823d2571
TG		 6030#undef ARM_FEATURE_CORE_LOW
6031#define ARM_FEATURE_CORE_LOW(ARCH1) \
6032 features->core[0] = (ARCH1); \
6033 features->core[1] = 0; \
6034 features->coproc = FPU_FPA; \
6035 return
6036
0313a2b8
NC		 6037 switch (mach)
6038 {
6039 case bfd_mach_arm_2: ARM_ARCH_V2;
6040 case bfd_mach_arm_2a: ARM_ARCH_V2S;
6041 case bfd_mach_arm_3: ARM_ARCH_V3;
6042 case bfd_mach_arm_3M: ARM_ARCH_V3M;
6043 case bfd_mach_arm_4: ARM_ARCH_V4;
6044 case bfd_mach_arm_4T: ARM_ARCH_V4T;
6045 case bfd_mach_arm_5: ARM_ARCH_V5;
6046 case bfd_mach_arm_5T: ARM_ARCH_V5T;
6047 case bfd_mach_arm_5TE: ARM_ARCH_V5TE;
6048 case bfd_mach_arm_XScale: ARM_ARCH_XSCALE;
823d2571
TG		 6049 case bfd_mach_arm_ep9312: ARM_FEATURE_LOW (ARM_AEXT_V4T, \
6050 ARM_CEXT_MAVERICK \
6051 | FPU_MAVERICK);
0313a2b8
NC		 6052 case bfd_mach_arm_iWMMXt: ARM_ARCH_IWMMXT;
6053 case bfd_mach_arm_iWMMXt2: ARM_ARCH_IWMMXT2;
6054 /* If the machine type is unknown allow all
6055 architecture types and all extensions. */
823d2571 6056 case bfd_mach_arm_unknown: ARM_FEATURE_LOW (-1UL, -1UL);
0313a2b8
NC		 6057 default:
6058 abort ();
6059 }
6060}
6061
6062
58efb6c0
NC		 6063/* NOTE: There are no checks in these routines that
6064 the relevant number of data bytes exist. */
baf0cc5e 6065
58efb6c0 6066static int
4a5329c6 6067print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 6068{
c19d1205
ZW		 6069 unsigned char b[4];
6070 long given;
6071 int status;
e821645d 6072 int is_thumb = FALSE;
b0e28b39 6073 int is_data = FALSE;
bd2e2557 6074 int little_code;
e821645d 6075 unsigned int size = 4;
4a5329c6 6076 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 6077 bfd_boolean found = FALSE;
b0e28b39 6078 struct arm_private_data *private_data;
58efb6c0 6079
dd92f639
NC		 6080 if (info->disassembler_options)
6081 {
6082 parse_disassembler_options (info->disassembler_options);
b34976b6 6083
58efb6c0 6084 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 6085 info->disassembler_options = NULL;
6086 }
b34976b6 6087
0313a2b8
NC		 6088 /* PR 10288: Control which instructions will be disassembled. */
6089 if (info->private_data == NULL)
6090 {
b0e28b39 6091 static struct arm_private_data private;
0313a2b8
NC		 6092
6093 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
6094 /* If the user did not use the -m command line switch then default to
6095 disassembling all types of ARM instruction.
6096
6097 The info->mach value has to be ignored as this will be based on
6098 the default archictecture for the target and/or hints in the notes
6099 section, but it will never be greater than the current largest arm
6100 machine value (iWMMXt2), which is only equivalent to the V5TE
6101 architecture. ARM architectures have advanced beyond the machine
6102 value encoding, and these newer architectures would be ignored if
6103 the machine value was used.
6104
6105 Ie the -m switch is used to restrict which instructions will be
6106 disassembled. If it is necessary to use the -m switch to tell
6107 objdump that an ARM binary is being disassembled, eg because the
6108 input is a raw binary file, but it is also desired to disassemble
6109 all ARM instructions then use "-marm". This will select the
6110 "unknown" arm architecture which is compatible with any ARM
6111 instruction. */
6112 info->mach = bfd_mach_arm_unknown;
6113
6114 /* Compute the architecture bitmask from the machine number.
6115 Note: This assumes that the machine number will not change
6116 during disassembly.... */
b0e28b39 6117 select_arm_features (info->mach, & private.features);
0313a2b8 6118
b0e28b39 6119 private.has_mapping_symbols = -1;
1fbaefec
PB		 6120 private.last_mapping_sym = -1;
6121 private.last_mapping_addr = 0;
b0e28b39
DJ		 6122
6123 info->private_data = & private;
0313a2b8 6124 }
b0e28b39
DJ		 6125
6126 private_data = info->private_data;
6127
bd2e2557
SS		 6128 /* Decide if our code is going to be little-endian, despite what the
6129 function argument might say. */
6130 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
6131
b0e28b39
DJ		 6132 /* For ELF, consult the symbol table to determine what kind of code
6133 or data we have. */
8977d4b2 6134 if (info->symtab_size != 0
e821645d
DJ		 6135 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
6136 {
6137 bfd_vma addr;
b0e28b39 6138 int n, start;
e821645d 6139 int last_sym = -1;
b0e28b39 6140 enum map_type type = MAP_ARM;
e821645d 6141
e821645d
DJ		 6142 /* Start scanning at the start of the function, or wherever
6143 we finished last time. */
6750a3a7
NC		 6144 /* PR 14006. When the address is 0 we are either at the start of the
6145 very first function, or else the first function in a new, unlinked
6146 executable section (eg because uf -ffunction-sections). Either way
6147 start scanning from the beginning of the symbol table, not where we
6148 left off last time. */
6149 if (pc == 0)
6150 start = 0;
6151 else
6152 {
6153 start = info->symtab_pos + 1;
6154 if (start < private_data->last_mapping_sym)
6155 start = private_data->last_mapping_sym;
6156 }
b0e28b39 6157 found = FALSE;
e821645d 6158
b0e28b39
DJ		 6159 /* First, look for mapping symbols. */
6160 if (private_data->has_mapping_symbols != 0)
e821645d 6161 {
b0e28b39
DJ		 6162 /* Scan up to the location being disassembled. */
6163 for (n = start; n < info->symtab_size; n++)
6164 {
6165 addr = bfd_asymbol_value (info->symtab[n]);
6166 if (addr > pc)
6167 break;
6168 if (get_map_sym_type (info, n, &type))
6169 {
6170 last_sym = n;
6171 found = TRUE;
6172 }
6173 }
6174
6175 if (!found)
6176 {
6177 /* No mapping symbol found at this address. Look backwards
cc643b88 6178 for a preceding one. */
b0e28b39
DJ		 6179 for (n = start - 1; n >= 0; n--)
6180 {
6181 if (get_map_sym_type (info, n, &type))
6182 {
6183 last_sym = n;
6184 found = TRUE;
6185 break;
6186 }
6187 }
6188 }
6189
6190 if (found)
6191 private_data->has_mapping_symbols = 1;
6192
6193 /* No mapping symbols were found. A leading $d may be
6194 omitted for sections which start with data; but for
6195 compatibility with legacy and stripped binaries, only
6196 assume the leading $d if there is at least one mapping
6197 symbol in the file. */
6198 if (!found && private_data->has_mapping_symbols == -1)
e821645d 6199 {
b0e28b39
DJ		 6200 /* Look for mapping symbols, in any section. */
6201 for (n = 0; n < info->symtab_size; n++)
6202 if (is_mapping_symbol (info, n, &type))
6203 {
6204 private_data->has_mapping_symbols = 1;
6205 break;
6206 }
6207 if (private_data->has_mapping_symbols == -1)
6208 private_data->has_mapping_symbols = 0;
6209 }
6210
6211 if (!found && private_data->has_mapping_symbols == 1)
6212 {
6213 type = MAP_DATA;
e821645d
DJ		 6214 found = TRUE;
6215 }
6216 }
6217
b0e28b39
DJ		 6218 /* Next search for function symbols to separate ARM from Thumb
6219 in binaries without mapping symbols. */
e821645d
DJ		 6220 if (!found)
6221 {
b0e28b39
DJ		 6222 /* Scan up to the location being disassembled. */
6223 for (n = start; n < info->symtab_size; n++)
e821645d 6224 {
b0e28b39
DJ		 6225 addr = bfd_asymbol_value (info->symtab[n]);
6226 if (addr > pc)
6227 break;
6228 if (get_sym_code_type (info, n, &type))
e821645d
DJ		 6229 {
6230 last_sym = n;
6231 found = TRUE;
b0e28b39
DJ		 6232 }
6233 }
6234
6235 if (!found)
6236 {
6237 /* No mapping symbol found at this address. Look backwards
cc643b88 6238 for a preceding one. */
b0e28b39
DJ		 6239 for (n = start - 1; n >= 0; n--)
6240 {
6241 if (get_sym_code_type (info, n, &type))
6242 {
6243 last_sym = n;
6244 found = TRUE;
6245 break;
6246 }
e821645d
DJ		 6247 }
6248 }
6249 }
6250
1fbaefec
PB		 6251 private_data->last_mapping_sym = last_sym;
6252 private_data->last_type = type;
6253 is_thumb = (private_data->last_type == MAP_THUMB);
6254 is_data = (private_data->last_type == MAP_DATA);
b34976b6 6255
e821645d
DJ		 6256 /* Look a little bit ahead to see if we should print out
6257 two or four bytes of data. If there's a symbol,
6258 mapping or otherwise, after two bytes then don't
6259 print more. */
6260 if (is_data)
6261 {
6262 size = 4 - (pc & 3);
6263 for (n = last_sym + 1; n < info->symtab_size; n++)
6264 {
6265 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 6266 if (addr > pc
6267 && (info->section == NULL
6268 || info->section == info->symtab[n]->section))
e821645d
DJ		 6269 {
6270 if (addr - pc < size)
6271 size = addr - pc;
6272 break;
6273 }
6274 }
6275 /* If the next symbol is after three bytes, we need to
6276 print only part of the data, so that we can use either
6277 .byte or .short. */
6278 if (size == 3)
6279 size = (pc & 1) ? 1 : 2;
6280 }
6281 }
6282
6283 if (info->symbols != NULL)
252b5132 6284 {
5876e06d
NC		 6285 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
6286 {
2f0ca46a 6287 coff_symbol_type * cs;
b34976b6 6288
5876e06d
NC		 6289 cs = coffsymbol (*info->symbols);
6290 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
6291 || cs->native->u.syment.n_sclass == C_THUMBSTAT
6292 || cs->native->u.syment.n_sclass == C_THUMBLABEL
6293 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
6294 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
6295 }
e821645d
DJ		 6296 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
6297 && !found)
5876e06d 6298 {
2087ad84
PB		 6299 /* If no mapping symbol has been found then fall back to the type
6300 of the function symbol. */
e821645d
DJ		 6301 elf_symbol_type * es;
6302 unsigned int type;
2087ad84 6303
e821645d
DJ		 6304 es = *(elf_symbol_type **)(info->symbols);
6305 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 6306
35fc36a8
RS		 6307 is_thumb = ((ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym)
6308 == ST_BRANCH_TO_THUMB)
6309 || type == STT_ARM_16BIT);
5876e06d
NC		 6310 }
6311 }
b34976b6 6312
e821645d
DJ		 6313 if (force_thumb)
6314 is_thumb = TRUE;
6315
b8f9ee44
CL		 6316 if (is_data)
6317 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6318 else
6319 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6320
c19d1205 6321 info->bytes_per_line = 4;
252b5132 6322
1316c8b3
NC		 6323 /* PR 10263: Disassemble data if requested to do so by the user. */
6324 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 6325 {
6326 int i;
6327
1316c8b3 6328 /* Size was already set above. */
e821645d
DJ		 6329 info->bytes_per_chunk = size;
6330 printer = print_insn_data;
6331
fe56b6ce 6332 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 6333 given = 0;
6334 if (little)
6335 for (i = size - 1; i >= 0; i--)
6336 given = b[i] | (given << 8);
6337 else
6338 for (i = 0; i < (int) size; i++)
6339 given = b[i] | (given << 8);
6340 }
6341 else if (!is_thumb)
252b5132 6342 {
c19d1205
ZW		 6343 /* In ARM mode endianness is a straightforward issue: the instruction
6344 is four bytes long and is either ordered 0123 or 3210. */
6345 printer = print_insn_arm;
6346 info->bytes_per_chunk = 4;
4a5329c6 6347 size = 4;
c19d1205 6348
0313a2b8 6349 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 6350 if (little_code)
c19d1205
ZW		 6351 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
6352 else
6353 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
252b5132 6354 }
58efb6c0 6355 else
252b5132 6356 {
c19d1205
ZW		 6357 /* In Thumb mode we have the additional wrinkle of two
6358 instruction lengths. Fortunately, the bits that determine
6359 the length of the current instruction are always to be found
6360 in the first two bytes. */
4a5329c6 6361 printer = print_insn_thumb16;
c19d1205 6362 info->bytes_per_chunk = 2;
4a5329c6
ZW		 6363 size = 2;
6364
fe56b6ce 6365 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 6366 if (little_code)
9a2ff3f5
AM		 6367 given = (b[0]) | (b[1] << 8);
6368 else
6369 given = (b[1]) | (b[0] << 8);
6370
c19d1205 6371 if (!status)
252b5132 6372 {
c19d1205
ZW		 6373 /* These bit patterns signal a four-byte Thumb
6374 instruction. */
6375 if ((given & 0xF800) == 0xF800
6376 || (given & 0xF800) == 0xF000
6377 || (given & 0xF800) == 0xE800)
252b5132 6378 {
0313a2b8 6379 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 6380 if (little_code)
c19d1205 6381 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 6382 else
c19d1205
ZW		 6383 given = (b[1]) | (b[0] << 8) | (given << 16);
6384
6385 printer = print_insn_thumb32;
4a5329c6 6386 size = 4;
252b5132 6387 }
252b5132 6388 }
c22aaad1
PB		 6389
6390 if (ifthen_address != pc)
0313a2b8 6391 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 6392
6393 if (ifthen_state)
6394 {
6395 if ((ifthen_state & 0xf) == 0x8)
6396 ifthen_next_state = 0;
6397 else
6398 ifthen_next_state = (ifthen_state & 0xe0)
6399 | ((ifthen_state & 0xf) << 1);
6400 }
252b5132 6401 }
b34976b6 6402
c19d1205
ZW		 6403 if (status)
6404 {
6405 info->memory_error_func (status, pc, info);
6406 return -1;
6407 }
6a56ec7e
NC		 6408 if (info->flags & INSN_HAS_RELOC)
6409 /* If the instruction has a reloc associated with it, then
6410 the offset field in the instruction will actually be the
6411 addend for the reloc. (We are using REL type relocs).
6412 In such cases, we can ignore the pc when computing
6413 addresses, since the addend is not currently pc-relative. */
6414 pc = 0;
b34976b6 6415
4a5329c6 6416 printer (pc, info, given);
c22aaad1
PB		 6417
6418 if (is_thumb)
6419 {
6420 ifthen_state = ifthen_next_state;
6421 ifthen_address += size;
6422 }
4a5329c6 6423 return size;
252b5132
RH		 6424}
6425
6426int
4a5329c6 6427print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 6428{
bd2e2557
SS		 6429 /* Detect BE8-ness and record it in the disassembler info. */
6430 if (info->flavour == bfd_target_elf_flavour
6431 && info->section != NULL
6432 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
6433 info->endian_code = BFD_ENDIAN_LITTLE;
6434
b34976b6 6435 return print_insn (pc, info, FALSE);
58efb6c0 6436}
01c7f630 6437
58efb6c0 6438int
4a5329c6 6439print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 6440{
b34976b6 6441 return print_insn (pc, info, TRUE);
58efb6c0 6442}
252b5132 6443
58efb6c0 6444void
4a5329c6 6445print_arm_disassembler_options (FILE *stream)
58efb6c0
NC		 6446{
6447 int i;
252b5132 6448
58efb6c0
NC		 6449 fprintf (stream, _("\n\
6450The following ARM specific disassembler options are supported for use with\n\
6451the -M switch:\n"));
b34976b6 6452
58efb6c0
NC		 6453 for (i = NUM_ARM_REGNAMES; i--;)
6454 fprintf (stream, " reg-names-%s %*c%s\n",
6455 regnames[i].name,
d5b2f4d6 6456 (int)(14 - strlen (regnames[i].name)), ' ',
58efb6c0
NC		 6457 regnames[i].description);
6458
6459 fprintf (stream, " force-thumb Assume all insns are Thumb insns\n");
cc643b88 6460 fprintf (stream, " no-force-thumb Examine preceding label to determine an insn's type\n\n");
252b5132 6461}
GDB Binutils - Deliverables
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