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Don't use print_insn_XXX in GDB
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
CommitLineData
252b5132 1/* Instruction printing code for the ARM
2571583a 2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
2fbad815 24
6394c606 25#include "disassemble.h"
2fbad815 26#include "opcode/arm.h"
252b5132 27#include "opintl.h"
31e0f3cd 28#include "safe-ctype.h"
65b48a81 29#include "libiberty.h"
0dbde4cf 30#include "floatformat.h"
252b5132 31
baf0cc5e 32/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 33#include "coff/internal.h"
34#include "libcoff.h"
252b5132
RH		 35#include "elf-bfd.h"
36#include "elf/internal.h"
37#include "elf/arm.h"
e49d43ff 38#include "mach-o.h"
252b5132 39
6b5d3a4d 40/* FIXME: Belongs in global header. */
01c7f630 41#ifndef strneq
58efb6c0
NC		 42#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
43#endif
44
1fbaefec
PB		 45/* Cached mapping symbol state. */
46enum map_type
47{
48 MAP_ARM,
49 MAP_THUMB,
50 MAP_DATA
51};
52
b0e28b39
DJ		 53struct arm_private_data
54{
55 /* The features to use when disassembling optional instructions. */
56 arm_feature_set features;
57
58 /* Whether any mapping symbols are present in the provided symbol
59 table. -1 if we do not know yet, otherwise 0 or 1. */
60 int has_mapping_symbols;
1fbaefec
PB		 61
62 /* Track the last type (although this doesn't seem to be useful) */
63 enum map_type last_type;
64
65 /* Tracking symbol table information */
66 int last_mapping_sym;
67 bfd_vma last_mapping_addr;
b0e28b39
DJ		 68};
69
6b5d3a4d
ZW		 70struct opcode32
71{
823d2571
TG		 72 arm_feature_set arch; /* Architecture defining this insn. */
73 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 74 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 75 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 76};
77
78struct opcode16
79{
823d2571 80 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 81 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 82 const char *assembler; /* How to disassemble this insn. */
83};
b7693d02 84
8f06b2d8 85/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 86
2fbad815 87 %% %
4a5329c6 88
c22aaad1 89 %c print condition code (always bits 28-31 in ARM mode)
37b37b2d 90 %q print shifter argument
e2efe87d
MGD		 91 %u print condition code (unconditional in ARM mode,
92 UNPREDICTABLE if not AL in Thumb)
4a5329c6 93 %A print address for ldc/stc/ldf/stf instruction
16980d0b 94 %B print vstm/vldm register list
4a5329c6 95 %I print cirrus signed shift immediate: bits 0..3|4..6
4a5329c6
ZW		 96 %F print the COUNT field of a LFM/SFM instruction.
97 %P print floating point precision in arithmetic insn
98 %Q print floating point precision in ldf/stf insn
99 %R print floating point rounding mode
100
33399f07 101 %<bitfield>c print as a condition code (for vsel)
4a5329c6 102 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 103 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
104 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 105 %<bitfield>d print the bitfield in decimal
16980d0b 106 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 107 %<bitfield>x print the bitfield in hex
108 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 109 %<bitfield>f print a floating point constant if >7 else a
110 floating point register
4a5329c6
ZW		 111 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
112 %<bitfield>g print as an iWMMXt 64-bit register
113 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 114 %<bitfield>D print as a NEON D register
115 %<bitfield>Q print as a NEON Q register
c28eeff2 116 %<bitfield>V print as a NEON D or Q register
6f1c2142 117 %<bitfield>E print a quarter-float immediate value
4a5329c6 118
16980d0b 119 %y<code> print a single precision VFP reg.
2fbad815 120 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 121 %z<code> print a double precision VFP reg
2fbad815 122 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 123
16980d0b
JB		 124 %<bitfield>'c print specified char iff bitfield is all ones
125 %<bitfield>`c print specified char iff bitfield is all zeroes
126 %<bitfield>?ab... select from array of values in big endian order
43e65147 127
2fbad815 128 %L print as an iWMMXt N/M width field.
4a5329c6 129 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 130 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 131 versions.
132 %i print 5-bit immediate in bits 8,3..0
133 (print "32" when 0)
fe56b6ce 134 %r print register offset address for wldt/wstr instruction. */
2fbad815 135
21d799b5 136enum opcode_sentinel_enum
05413229
NC		 137{
138 SENTINEL_IWMMXT_START = 1,
139 SENTINEL_IWMMXT_END,
140 SENTINEL_GENERIC_START
141} opcode_sentinels;
142
aefd8a40 143#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
c1e26897 144#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 145
8f06b2d8 146/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 147
8f06b2d8 148static const struct opcode32 coprocessor_opcodes[] =
2fbad815 149{
2fbad815 150 /* XScale instructions. */
823d2571
TG		 151 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
152 0x0e200010, 0x0fff0ff0,
153 "mia%c\tacc0, %0-3r, %12-15r"},
154 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
155 0x0e280010, 0x0fff0ff0,
156 "miaph%c\tacc0, %0-3r, %12-15r"},
157 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
158 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
159 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
160 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
161 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
162 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 163
2fbad815 164 /* Intel Wireless MMX technology instructions. */
823d2571
TG		 165 {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
166 {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
167 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
168 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
169 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
170 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
171 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
172 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
173 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
174 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
175 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
176 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
177 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
178 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
179 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
180 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
181 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
182 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
183 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
184 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
185 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
186 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
187 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
188 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
189 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
190 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
191 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
192 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
193 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
194 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
195 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
196 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
197 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
198 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
199 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
200 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
201 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
202 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
203 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
204 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
205 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
206 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
207 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
208 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
209 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
210 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
211 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
212 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
213 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
214 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
215 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
216 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
217 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
218 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
219 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
220 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
221 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
222 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
223 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
224 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
225 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
226 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
227 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
228 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
229 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
230 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
231 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
232 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
233 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
234 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
235 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
236 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
237 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
238 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
239 0x0e800120, 0x0f800ff0,
240 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
241 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
242 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
243 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
244 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
245 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
246 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
247 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
248 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
249 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
250 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
251 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
252 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
253 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
254 0x0e8000a0, 0x0f800ff0,
255 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
256 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
257 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
258 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
259 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
260 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
261 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
262 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
263 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
264 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
265 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
266 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
267 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
268 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
269 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
270 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
271 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
272 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
273 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
274 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
275 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
276 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
277 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
278 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
279 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
280 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
281 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
282 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
283 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
284 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
285 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
286 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
287 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
288 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
289 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
290 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
291 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
292 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
293 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
294 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
295 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
296 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
297 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
298 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
299 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
300 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
301 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
302 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
303 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
304 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
305 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
306 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
307 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
308 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
309 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
310 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
311 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
312 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
313 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
314 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
315 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
316 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
317 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
318 {ARM_FEATURE_CORE_LOW (0),
319 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 320
fe56b6ce 321 /* Floating point coprocessor (FPA) instructions. */
823d2571
TG		 322 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
323 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
324 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
325 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
326 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
327 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
328 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
329 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
330 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
331 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
332 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
333 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
334 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
335 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
336 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
337 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
338 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
339 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
340 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
341 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
342 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
343 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
344 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
345 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
346 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
347 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
348 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
349 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
350 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
351 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
352 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
353 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
354 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
355 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
356 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
357 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
358 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
359 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
360 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
361 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
362 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
363 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
364 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
365 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
366 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
367 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
368 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
369 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
370 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
371 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
372 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
373 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
374 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
375 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
376 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
377 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
378 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
379 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
380 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
381 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
382 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
383 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
384 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
385 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
386 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
387 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
388 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
389 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
390 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
391 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
392 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
393 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
394 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
395 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
396 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
397 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
398 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
399 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
400 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
401 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
402 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
403 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
404 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
405 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
406 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
407 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 408
16a1fa25
TP		 409 /* ARMv8-M Mainline Security Extensions instructions. */
410 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
411 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
412 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
413 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
414
fe56b6ce 415 /* Register load/store. */
823d2571
TG		 416 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
417 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
418 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
419 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
420 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
421 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
422 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
423 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
424 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
425 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
426 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
427 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
428 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
429 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
430 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
431 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
432 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
433 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
434 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
435 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
436 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
437 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
438 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
439 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
440 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
441 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
442 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
443 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
444 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
445 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
446 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
447 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
448
449 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
450 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
451 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
452 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
453 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
454 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
455 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
456 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 457
fe56b6ce 458 /* Data transfer between ARM and NEON registers. */
823d2571
TG		 459 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
460 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
462 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
464 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
466 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
468 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
470 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
472 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
474 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
476 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
478 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
480 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
482 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
484 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
486 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 487 /* Half-precision conversion instructions. */
823d2571
TG		 488 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
489 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
490 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
491 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
492 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
493 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
494 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
495 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 496
fe56b6ce 497 /* Floating point coprocessor (VFP) instructions. */
823d2571
TG		 498 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
499 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
500 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
501 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
502 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
503 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
504 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
505 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
506 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
507 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
508 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
509 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
510 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
511 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
512 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
513 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
514 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
515 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
516 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
517 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
518 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
519 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
520 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
521 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
522 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
523 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
524 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
525 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
526 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
527 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
528 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
529 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
530 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
531 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
532 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
533 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
534 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
535 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
536 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
537 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
538 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
539 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
540 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
541 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
542 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
543 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
544 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
545 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
546 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
547 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
548 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
549 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
550 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
551 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
552 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
553 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
554 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
555 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
556 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
557 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
558 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
559 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
560 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
561 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
562 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
563 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
564 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
565 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
566 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
567 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
568 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
569 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
570 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
571 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
572 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
573 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
574 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
575 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
576 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
577 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
578 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
579 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
580 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
581 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
582 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
583 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
584 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
585 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
586 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6f1c2142 587 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
823d2571 588 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6f1c2142 589 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
823d2571
TG		 590 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
591 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
592 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
593 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
594 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
595 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
596 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
597 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
598 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
599 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
600 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
601 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
602 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
603 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
604 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
605 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
606 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
607 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
608 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
609 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
610 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
611 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
612 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
613 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
614 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
615 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
616 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
617 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
618 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
619 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
620 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
621 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
622 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
623 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
624 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
625 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
626 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
627 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
628 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
629 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
630 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
631 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 632
633 /* Cirrus coprocessor instructions. */
823d2571
TG		 634 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
635 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
636 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
637 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
638 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
639 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
640 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
641 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
642 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
643 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
644 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
645 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
646 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
647 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
648 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
649 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
650 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
651 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
652 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
653 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
654 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
655 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
656 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
657 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
658 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
659 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
660 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
661 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
662 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
663 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
664 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
665 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
666 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
667 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
668 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
669 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
670 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
671 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
672 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
673 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
674 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
675 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
676 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
677 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
678 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
679 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
680 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
681 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
682 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
683 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
684 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
685 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
686 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
687 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
688 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
689 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
690 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
691 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
692 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
693 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
694 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
695 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
696 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
697 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
698 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
699 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
700 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
701 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
702 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
703 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
704 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
705 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
706 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
707 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
708 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
709 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
710 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
711 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
712 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
713 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
714 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
715 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
716 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
717 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
718 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
719 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
720 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
721 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
722 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
723 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
724 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
725 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
726 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
727 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
728 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
729 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
730 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
731 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
732 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
733 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
734 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
735 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
736 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
737 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
738 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
739 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
740 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
741 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
742 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
743 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
744 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
745 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
746 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
747 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
748 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
749 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
750 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
751 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
752 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
753 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
754 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
755 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
756 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
757 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
758 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
759 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
760 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
761 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
762 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
763 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
764 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
765 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
766 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
767 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
768 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
769 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
770 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
771 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
772 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
773 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
774 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
775 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
776 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
777 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
778 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
779 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
780 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
781 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
782 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
783 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
784 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
785 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
786 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
787 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
788 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
789 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
790 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
791 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
792 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
793 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
794 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
795 0x0e000600, 0x0ff00f10,
796 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
797 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
798 0x0e100600, 0x0ff00f10,
799 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
800 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
801 0x0e200600, 0x0ff00f10,
802 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
803 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
804 0x0e300600, 0x0ff00f10,
805 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 806
62f3b8c8 807 /* VFP Fused multiply add instructions. */
823d2571
TG		 808 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
809 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
810 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
811 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
812 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
813 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
814 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
815 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
816 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
817 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
818 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
819 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
820 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
821 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
822 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 824
33399f07 825 /* FP v5. */
823d2571 826 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 827 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
823d2571 828 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 829 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
823d2571 830 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 831 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
823d2571 832 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 833 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
823d2571 834 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 835 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
823d2571 836 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 837 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
823d2571
TG		 838 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
839 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
840 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
841 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
842 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
843 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
844 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
845 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
846 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 847 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
823d2571 848 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 849 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 850
05413229 851 /* Generic coprocessor instructions. */
823d2571
TG		 852 {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
854 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
856 0x0c500000, 0x0ff00000,
857 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
859 0x0e000000, 0x0f000010,
860 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
862 0x0e10f010, 0x0f10f010,
863 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
865 0x0e100010, 0x0f100010,
866 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
868 0x0e000010, 0x0f100010,
869 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
871 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
873 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
2fbad815 874
05413229 875 /* V6 coprocessor instructions. */
823d2571
TG		 876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
877 0xfc500000, 0xfff00000,
878 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
880 0xfc400000, 0xfff00000,
881 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
8f06b2d8 882
c28eeff2
SN		 883 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
884 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
885 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
886 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
887 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
888 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
889 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
890 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
891 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
892 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
893 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
894 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
895 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
896 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 897 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
c28eeff2 898 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 899 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
c28eeff2 900 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 901 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
c28eeff2 902 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 903 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
c28eeff2 904
05413229 905 /* V5 coprocessor instructions. */
823d2571
TG		 906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
907 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
909 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
911 0xfe000000, 0xff000010,
912 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
914 0xfe000010, 0xff100010,
915 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
917 0xfe100010, 0xff100010,
918 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
919
b0c11777
RL		 920 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
921 cp_num: bit <11:8> == 0b1001.
922 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
923 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
924 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
925 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
926 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
927 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
928 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
929 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
930 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
931 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
932 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
933 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
934 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
935 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
936 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
937 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
938 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
939 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
940 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
941 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
942 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
943 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
944 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
945 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
946 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
947 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
948 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
949 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
950 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
951 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
952 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
953 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
954 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
955 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
956 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
957 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
958 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
959 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
960 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
961 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
962 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
963 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
964 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
965 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
966 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
967 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
968 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
969 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
970 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
971 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
972 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
973 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
974 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
975 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
976 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
977 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
978 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
979 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
980 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
981 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
982 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
983 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
984 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
985 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
986 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
987 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
988 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
989 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
990 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
991 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
992 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
993
49e8a725
SN		 994 /* ARMv8.3 javascript conversion instruction. */
995 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
996 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
997
823d2571 998 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 999};
1000
16980d0b
JB		 1001/* Neon opcode table: This does not encode the top byte -- that is
1002 checked by the print_insn_neon routine, as it depends on whether we are
1003 doing thumb32 or arm32 disassembly. */
1004
1005/* print_insn_neon recognizes the following format control codes:
1006
1007 %% %
1008
c22aaad1 1009 %c print condition code
e2efe87d
MGD		 1010 %u print condition code (unconditional in ARM mode,
1011 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 1012 %A print v{st,ld}[1234] operands
1013 %B print v{st,ld}[1234] any one operands
1014 %C print v{st,ld}[1234] single->all operands
1015 %D print scalar
1016 %E print vmov, vmvn, vorr, vbic encoded constant
1017 %F print vtbl,vtbx register list
1018
1019 %<bitfield>r print as an ARM register
1020 %<bitfield>d print the bitfield in decimal
1021 %<bitfield>e print the 2^N - bitfield in decimal
1022 %<bitfield>D print as a NEON D register
1023 %<bitfield>Q print as a NEON Q register
1024 %<bitfield>R print as a NEON D or Q register
1025 %<bitfield>Sn print byte scaled width limited by n
1026 %<bitfield>Tn print short scaled width limited by n
1027 %<bitfield>Un print long scaled width limited by n
43e65147 1028
16980d0b
JB		 1029 %<bitfield>'c print specified char iff bitfield is all ones
1030 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1031 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1032
1033static const struct opcode32 neon_opcodes[] =
1034{
fe56b6ce 1035 /* Extract. */
823d2571
TG		 1036 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1037 0xf2b00840, 0xffb00850,
1038 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1039 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1040 0xf2b00000, 0xffb00810,
1041 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 1042
fe56b6ce 1043 /* Move data element to all lanes. */
823d2571
TG		 1044 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1045 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1046 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1047 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1048 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1049 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 1050
fe56b6ce 1051 /* Table lookup. */
823d2571
TG		 1052 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1053 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1054 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1055 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1056
8e79c3df 1057 /* Half-precision conversions. */
823d2571
TG		 1058 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1059 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1060 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1061 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1062
1063 /* NEON fused multiply add instructions. */
823d2571 1064 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1065 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1066 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1067 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1068 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1069 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1070 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1071 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1072
fe56b6ce 1073 /* Two registers, miscellaneous. */
823d2571
TG		 1074 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1075 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1076 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1077 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1078 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1079 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1080 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1081 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1082 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1083 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1084 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1085 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1086 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1087 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1088 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1089 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1090 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1091 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1092 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1093 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1094 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1095 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1096 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1097 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1098 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1099 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1100 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1101 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1102 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1103 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1104 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1105 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1106 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1107 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1108 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1109 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1110 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1111 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1112 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1113 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1114 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1115 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1116 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1117 0xf3b20300, 0xffb30fd0,
1118 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1119 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1120 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1121 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1122 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1123 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1124 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1125 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1126 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1127 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1128 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1129 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1130 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1131 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1132 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1133 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1134 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1135 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1136 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1137 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1138 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1139 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1140 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1141 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1142 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1143 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1144 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1145 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1146 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1147 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1148 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1149 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1150 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1151 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1152 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1153 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1154 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1155 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1156 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1157 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1158 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1159 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1160 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1161 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1162 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1163 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1164 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1165 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301 1166 0xf3bb0600, 0xffbf0e10,
823d2571 1167 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1168 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1169 0xf3b70600, 0xffbf0e10,
1170 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
16980d0b 1171
fe56b6ce 1172 /* Three registers of the same length. */
823d2571
TG		 1173 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1174 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1175 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1176 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1177 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1178 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1179 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1180 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1181 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1182 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1183 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1184 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1185 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1186 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1187 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1188 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1189 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1190 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1191 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1192 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1193 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1194 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1195 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1196 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1197 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1198 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1199 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1200 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1201 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1202 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1203 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1204 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1205 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1206 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1207 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1208 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1209 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1210 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1211 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1212 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1213 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1214 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1215 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1216 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1217 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1218 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1219 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1220 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1221 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1222 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1223 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1224 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1225 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1226 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1227 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1228 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1229 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1230 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1231 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1232 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1233 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1234 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1235 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1236 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1237 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1238 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1239 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1240 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1241 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1242 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1243 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1244 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1245 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1246 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1247 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1248 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1249 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1250 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1251 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1252 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1253 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1254 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1255 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1256 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1257 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1258 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1259 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1260 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1261 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1262 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1263 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1264 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1265 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1266 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1267 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1268 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1269 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1270 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1271 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1272 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1273 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1274 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1275 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1276 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1277 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1278 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1279 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1280 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1281 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1282 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1283 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1284 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1285 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1286 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1287 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1288 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1289 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1290 0xf2000b00, 0xff800f10,
1291 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1292 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1293 0xf2000b10, 0xff800f10,
1294 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1295 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1296 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1297 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1298 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1299 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1300 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1301 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1302 0xf3000b00, 0xff800f10,
1303 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1304 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1305 0xf2000000, 0xfe800f10,
1306 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1307 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1308 0xf2000010, 0xfe800f10,
1309 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1310 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1311 0xf2000100, 0xfe800f10,
1312 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1313 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1314 0xf2000200, 0xfe800f10,
1315 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1316 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1317 0xf2000210, 0xfe800f10,
1318 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1319 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1320 0xf2000300, 0xfe800f10,
1321 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1322 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1323 0xf2000310, 0xfe800f10,
1324 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1325 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1326 0xf2000400, 0xfe800f10,
1327 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1328 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1329 0xf2000410, 0xfe800f10,
1330 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1331 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1332 0xf2000500, 0xfe800f10,
1333 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1334 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1335 0xf2000510, 0xfe800f10,
1336 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1337 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1338 0xf2000600, 0xfe800f10,
1339 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1340 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1341 0xf2000610, 0xfe800f10,
1342 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1343 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1344 0xf2000700, 0xfe800f10,
1345 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1346 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1347 0xf2000710, 0xfe800f10,
1348 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1349 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1350 0xf2000910, 0xfe800f10,
1351 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1352 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1353 0xf2000a00, 0xfe800f10,
1354 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1355 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1356 0xf2000a10, 0xfe800f10,
1357 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1358 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1359 0xf3000b10, 0xff800f10,
1360 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1361 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1362 0xf3000c10, 0xff800f10,
1363 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1364
fe56b6ce 1365 /* One register and an immediate value. */
823d2571
TG		 1366 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1367 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1368 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1369 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1370 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1371 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1372 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1373 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1374 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1375 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1376 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1377 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1378 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1379 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1380 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1381 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1382 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1383 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1384 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1385 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1386 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1387 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1388 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1389 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1390 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1391 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1392
fe56b6ce 1393 /* Two registers and a shift amount. */
823d2571
TG		 1394 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1395 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1396 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1397 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1398 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1399 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1400 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1401 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1402 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1403 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1404 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1405 0xf2880950, 0xfeb80fd0,
1406 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1407 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1408 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1409 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1410 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1411 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1412 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1413 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1414 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1415 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1416 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1417 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1418 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1419 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1420 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1421 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1422 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1423 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1424 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1425 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1426 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1427 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1428 0xf2900950, 0xfeb00fd0,
1429 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1430 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1431 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1432 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1433 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1434 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1435 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1436 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1437 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1438 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1439 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1440 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1441 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1442 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1443 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1444 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1445 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1446 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1447 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1448 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1449 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1450 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1451 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1452 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1453 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1454 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1455 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1456 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1457 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1458 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1459 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1460 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1461 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1462 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1463 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1465 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1466 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1467 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1468 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1469 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1470 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1471 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1473 0xf2a00950, 0xfea00fd0,
1474 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1476 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1478 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1480 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1482 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1484 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1486 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1487 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1488 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1489 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1490 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1492 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1494 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1495 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1496 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1498 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1499 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1500 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1502 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1503 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1504 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1511 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1512 0xf2a00e10, 0xfea00e90,
1513 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
cc933301
JW		 1514 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1515 0xf2a00c10, 0xfea00e90,
1516 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 1517
fe56b6ce 1518 /* Three registers of different lengths. */
823d2571
TG		 1519 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1520 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1521 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1522 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1523 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1524 0xf2800400, 0xff800f50,
1525 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1526 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1527 0xf2800600, 0xff800f50,
1528 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1530 0xf2800900, 0xff800f50,
1531 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1532 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1533 0xf2800b00, 0xff800f50,
1534 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1535 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1536 0xf2800d00, 0xff800f50,
1537 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1538 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1539 0xf3800400, 0xff800f50,
1540 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1541 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1542 0xf3800600, 0xff800f50,
1543 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1544 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1545 0xf2800000, 0xfe800f50,
1546 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1547 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1548 0xf2800100, 0xfe800f50,
1549 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1550 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1551 0xf2800200, 0xfe800f50,
1552 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1553 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1554 0xf2800300, 0xfe800f50,
1555 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1556 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1557 0xf2800500, 0xfe800f50,
1558 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1559 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1560 0xf2800700, 0xfe800f50,
1561 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1562 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1563 0xf2800800, 0xfe800f50,
1564 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1565 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1566 0xf2800a00, 0xfe800f50,
1567 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1568 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1569 0xf2800c00, 0xfe800f50,
1570 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 1571
fe56b6ce 1572 /* Two registers and a scalar. */
823d2571
TG		 1573 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1574 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1576 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1577 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1578 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1579 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1580 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1581 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1582 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1583 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1584 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1585 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1586 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1587 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1588 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1589 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1590 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1591 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1592 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1593 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1594 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1595 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1596 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1597 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1598 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1599 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1600 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1601 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1602 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1603 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1604 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1605 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1606 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1607 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1608 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1609 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1610 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1611 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1612 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1613 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1614 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1615 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1616 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1617 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1618 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1619 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1620 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1621 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1622 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1623 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1624 0xf2800240, 0xfe800f50,
1625 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1626 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1627 0xf2800640, 0xfe800f50,
1628 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1630 0xf2800a40, 0xfe800f50,
1631 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 1632 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1633 0xf2800e40, 0xff800f50,
1634 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1635 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1636 0xf2800f40, 0xff800f50,
1637 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1638 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1639 0xf3800e40, 0xff800f50,
1640 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1642 0xf3800f40, 0xff800f50,
1643 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1644 },
16980d0b 1645
fe56b6ce 1646 /* Element and structure load/store. */
823d2571
TG		 1647 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1648 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1650 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1651 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1652 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1653 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1654 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1655 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1656 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1658 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1659 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1660 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1661 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1662 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1663 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1664 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1665 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1666 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1667 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1668 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1669 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1670 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1671 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1672 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1673 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1674 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1675 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1676 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1677 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1678 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1679 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1680 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1681 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1682 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1683 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1684 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1685
1686 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 1687};
1688
8f06b2d8
PB		 1689/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
1690 ordered: they must be searched linearly from the top to obtain a correct
1691 match. */
1692
1693/* print_insn_arm recognizes the following format control codes:
1694
1695 %% %
1696
1697 %a print address for ldr/str instruction
1698 %s print address for ldr/str halfword/signextend instruction
c1e26897 1699 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 1700 %b print branch destination
1701 %c print condition code (always bits 28-31)
1702 %m print register mask for ldm/stm instruction
1703 %o print operand2 (immediate or register + shift)
1704 %p print 'p' iff bits 12-15 are 15
1705 %t print 't' iff bit 21 set and bit 24 clear
1706 %B print arm BLX(1) destination
1707 %C print the PSR sub type.
62b3e311
PB		 1708 %U print barrier type.
1709 %P print address for pli instruction.
8f06b2d8
PB		 1710
1711 %<bitfield>r print as an ARM register
9eb6c0f1 1712 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 1713 %<bitfield>R as %r but r15 is UNPREDICTABLE
1714 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1715 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 1716 %<bitfield>d print the bitfield in decimal
43e65147 1717 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 1718 %<bitfield>x print the bitfield in hex
1719 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 1720
16980d0b
JB		 1721 %<bitfield>'c print specified char iff bitfield is all ones
1722 %<bitfield>`c print specified char iff bitfield is all zeroes
1723 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 1724
8f06b2d8
PB		 1725 %e print arm SMI operand (bits 0..7,8..19).
1726 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 1727 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
1728 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 1729
8f06b2d8
PB		 1730static const struct opcode32 arm_opcodes[] =
1731{
1732 /* ARM instructions. */
823d2571
TG		 1733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1734 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1736 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1737
1738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
1739 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1741 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1743 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
1745 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1747 0x00800090, 0x0fa000f0,
1748 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1750 0x00a00090, 0x0fa000f0,
1751 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 1752
105bde57 1753 /* V8.2 RAS extension instructions. */
4d1464f2 1754 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 1755 0xe320f010, 0xffffffff, "esb"},
1756
53c4b28b 1757 /* V8 instructions. */
823d2571
TG		 1758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1759 0x0320f005, 0x0fffffff, "sevl"},
1760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1761 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
4ed7ed8d 1762 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 1763 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1764 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 1765 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1767 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1769 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 1770 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1771 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1772 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1773 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1774 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1775 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1776 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1777 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1778 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1779 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1780 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1781 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1782 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1783 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1784 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1785 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1786 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1787 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1788 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 1789 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 1790 /* CRC32 instructions. */
823d2571
TG		 1791 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1792 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
1793 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1794 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
1795 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1796 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
1797 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1798 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
1799 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1800 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
1801 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1802 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 1803
ddfded2f
MW		 1804 /* Privileged Access Never extension instructions. */
1805 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
1806 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
1807
90ec0d68 1808 /* Virtualization Extension instructions. */
823d2571
TG		 1809 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
1810 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 1811
eea54501 1812 /* Integer Divide Extension instructions. */
823d2571
TG		 1813 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1814 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1815 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1816 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 1817
60e5ef9f 1818 /* MP Extension instructions. */
823d2571 1819 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 1820
62b3e311 1821 /* V7 instructions. */
823d2571
TG		 1822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
1823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
1825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
1826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a
AV		 1829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
1830 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
62b3e311 1831
c19d1205 1832 /* ARM V6T2 instructions. */
823d2571
TG		 1833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1834 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1836 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1838 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1840 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
1841
1842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1843 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
1844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1845 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1846
ff8646ee 1847 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 1848 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 1849 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 1850 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1852 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1854 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 1855
f4c65163 1856 /* ARM Security extension instructions. */
823d2571
TG		 1857 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
1858 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 1859
8f06b2d8 1860 /* ARM V6K instructions. */
823d2571
TG		 1861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1862 0xf57ff01f, 0xffffffff, "clrex"},
1863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1864 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1866 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1868 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1870 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1872 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1874 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 1875
8f06b2d8 1876 /* ARM V6K NOP hints. */
823d2571
TG		 1877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1878 0x0320f001, 0x0fffffff, "yield%c"},
1879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1880 0x0320f002, 0x0fffffff, "wfe%c"},
1881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1882 0x0320f003, 0x0fffffff, "wfi%c"},
1883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1884 0x0320f004, 0x0fffffff, "sev%c"},
1885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1886 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 1887
fe56b6ce 1888 /* ARM V6 instructions. */
823d2571
TG		 1889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1890 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
1891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1892 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
1893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1894 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
1895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1896 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
1897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1898 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
1899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1900 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
1901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1902 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
1903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1904 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
1905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1906 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
1907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1908 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
1909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1910 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
1911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1912 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
1913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1914 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
1915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1916 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
1917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1918 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
1919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1920 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
1921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1922 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
1923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1924 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
1925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1926 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
1927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1928 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
1929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1930 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
1931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1932 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
1933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1934 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
1935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1936 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
1937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1938 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
1939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1940 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
1941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1942 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
1943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1944 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
1945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1946 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
1947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1948 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
1949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1950 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
1951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1952 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
1953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1954 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
1955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1956 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
1957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1958 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
1959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1960 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
1961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1962 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
1963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1964 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
1965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1966 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
1967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1968 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
1969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1970 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
1971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1972 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
1973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1974 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
1975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1976 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
1977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1978 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
1979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1980 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
1981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1982 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
1983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1984 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
1985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1986 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
1987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1988 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
1989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1990 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
1991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1992 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
1993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1994 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
1995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1996 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
1997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1998 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
1999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2000 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
2001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2002 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
2003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2004 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
2005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2006 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
2007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2008 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
2009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2010 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
2011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2012 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
2013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2014 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
2015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2016 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
2017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2018 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
2019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2020 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
2021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2022 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
2023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2024 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
2025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2026 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
2027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2028 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
2029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2030 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
2031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2032 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
2033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2034 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
2035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2036 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
2037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2038 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
2039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2040 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2042 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2044 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2046 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
2047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2048 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2050 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2052 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2054 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
2055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2056 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2058 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2060 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2062 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
2063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2064 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2066 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2068 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2070 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
2071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2072 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2074 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2076 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
2077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2078 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
2079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2080 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2082 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2084 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2086 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
2087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2088 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
2089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2090 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
2091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2092 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
2093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2094 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2096 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2098 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2100 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2102 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
2103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2104 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2106 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2108 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
2109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2110 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
2111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2112 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
2113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2114 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
2115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2116 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
2117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2118 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
2119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2120 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
2121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2122 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
2123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2124 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2126 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
2127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2128 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
2129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2130 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
2131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2132 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 2133
8f06b2d8 2134 /* V5J instruction. */
823d2571
TG		 2135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
2136 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 2137
8f06b2d8 2138 /* V5 Instructions. */
823d2571
TG		 2139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2140 0xe1200070, 0xfff000f0,
2141 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
2142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2143 0xfa000000, 0xfe000000, "blx\t%B"},
2144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2145 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
2146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2147 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
2148
2149 /* V5E "El Segundo" Instructions. */
2150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2151 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
2152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2153 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
2154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2155 0xf450f000, 0xfc70f000, "pld\t%a"},
2156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2157 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2159 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2161 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2163 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
2164
2165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2166 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2168 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
2169
2170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2171 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2173 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2175 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2177 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2178
2179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2180 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2182 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2184 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2186 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2187
2188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2189 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2191 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2192
2193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2194 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
2195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2196 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2198 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
2199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2200 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 2201
8f06b2d8 2202 /* ARM Instructions. */
823d2571
TG		 2203 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2204 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2205
2206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2207 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2209 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2210 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2211 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2212 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2213 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2215 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2217 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2218
2219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2220 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2222 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2224 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2226 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2227
2228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2229 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2231 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2233 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2235 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2236
2237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2238 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2240 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2242 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2243
2244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2245 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2247 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2249 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2250
2251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2252 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2254 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2256 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2257
2258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2259 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2261 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2263 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2264
2265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2266 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2268 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2270 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2271
2272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2273 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2275 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2277 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2278
2279 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2280 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2281 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2282 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2283 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2284 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2285
2286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2287 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2289 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2291 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2292
2293 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2294 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2295 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2296 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2297 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2298 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2299
2300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2301 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2302 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2303 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2304 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2305 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2306
2307 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2308 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 2309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2310 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 2311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2312 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
823d2571
TG		 2313
2314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2315 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2317 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2319 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2320
2321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2322 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2323 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2324 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2325 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2326 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2327
2328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2329 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2331 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2333 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2334
2335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2336 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2338 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2339 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2340 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2341 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2342 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2343 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2344 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2345 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2346 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2348 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2349
2350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2351 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2353 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2355 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2356
2357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2358 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2360 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2362 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2363
2364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2365 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2367 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2368
2369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2370 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2371
2372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2373 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2375 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2376
2377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2378 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2380 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2382 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2384 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2386 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2388 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2390 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2392 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2394 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2395 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2396 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2397 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2398 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2399 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2400 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2401 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2402 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2403 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2404 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2406 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2408 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2410 0x092d0000, 0x0fff0000, "push%c\t%m"},
2411 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2412 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2413 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2414 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2415
2416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2417 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2418 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2419 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2421 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2423 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2425 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2427 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2429 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2431 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2433 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2434 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2435 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2437 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2439 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2440 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2441 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2443 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2445 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2447 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2448 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2449 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2451 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2453 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2454
2455 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2456 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2457 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2458 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 2459
2460 /* The rest. */
4ab90a7a
AV		 2461 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2462 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 2463 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2464 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2465 {ARM_FEATURE_CORE_LOW (0),
2466 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 2467};
2468
2469/* print_insn_thumb16 recognizes the following format control codes:
2470
2471 %S print Thumb register (bits 3..5 as high number if bit 6 set)
2472 %D print Thumb register (bits 0..2 as high number if bit 7 set)
2473 %<bitfield>I print bitfield as a signed decimal
2474 (top bit of range being the sign bit)
2475 %N print Thumb register mask (with LR)
2476 %O print Thumb register mask (with PC)
2477 %M print Thumb register mask
2478 %b print CZB's 6-bit unsigned branch destination
2479 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 2480 %c print the condition code
2481 %C print the condition code, or "s" if not conditional
2482 %x print warning if conditional an not at end of IT block"
2483 %X print "\t; unpredictable <IT:code>" if conditional
2484 %I print IT instruction suffix and operands
4547cb56 2485 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 2486 %<bitfield>r print bitfield as an ARM register
2487 %<bitfield>d print bitfield as a decimal
2488 %<bitfield>H print (bitfield * 2) as a decimal
2489 %<bitfield>W print (bitfield * 4) as a decimal
2490 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
2491 %<bitfield>B print Thumb branch destination (signed displacement)
2492 %<bitfield>c print bitfield as a condition code
2493 %<bitnum>'c print specified char iff bit is one
2494 %<bitnum>?ab print a if bit is one else print b. */
2495
2496static const struct opcode16 thumb_opcodes[] =
2497{
2498 /* Thumb instructions. */
2499
16a1fa25
TP		 2500 /* ARMv8-M Security Extensions instructions. */
2501 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
2502 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff07, "bxns\t%3-6r"},
2503
53c4b28b 2504 /* ARM V8 instructions. */
823d2571
TG		 2505 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
2506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
ddfded2f 2507 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
53c4b28b 2508
8f06b2d8 2509 /* ARM V6K no-argument instructions. */
823d2571
TG		 2510 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2511 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2513 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2515 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 2516
2517 /* ARM V6T2 instructions. */
ff8646ee
TP		 2518 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2519 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2520 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2521 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 2522 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 2523
2524 /* ARM V6. */
823d2571
TG		 2525 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2526 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2527 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2528 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2529 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2531 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2533 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2534 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2535 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 2536
2537 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 2538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2539 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 2540 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 2541 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2542 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 2543 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 2544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2545 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 2546 /* Format 4. */
823d2571
TG		 2547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2555 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2557 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2559 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 2563 /* format 13 */
823d2571
TG		 2564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 2566 /* format 5 */
823d2571
TG		 2567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
2568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
2569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 2571 /* format 14 */
823d2571
TG		 2572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
2573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 2574 /* format 2 */
823d2571
TG		 2575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2576 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2578 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2579 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2580 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2582 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 2583 /* format 8 */
823d2571
TG		 2584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2585 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2587 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2589 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2590 /* format 7 */
823d2571
TG		 2591 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2592 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2594 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2595 /* format 1 */
823d2571
TG		 2596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2598 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2599 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 2601 /* format 3 */
823d2571
TG		 2602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2603 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 2606 /* format 6 */
823d2571
TG		 2607 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2609 0x4800, 0xF800,
2610 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 2611 /* format 9 */
823d2571
TG		 2612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2613 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2615 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2617 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2619 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 2620 /* format 10 */
823d2571
TG		 2621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2622 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2624 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 2625 /* format 11 */
823d2571
TG		 2626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2627 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2629 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 2630 /* format 12 */
823d2571
TG		 2631 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2632 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2634 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 2635 /* format 15 */
823d2571
TG		 2636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 2638 /* format 17 */
823d2571 2639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 2640 /* format 16 */
823d2571
TG		 2641 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
2643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 2644 /* format 18 */
823d2571 2645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 2646
2647 /* The E800 .. FFFF range is unconditionally redirected to the
2648 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2649 are processed via that table. Thus, we can never encounter a
2650 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 2651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
2652 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 2653};
2654
2655/* Thumb32 opcodes use the same table structure as the ARM opcodes.
2656 We adopt the convention that hw1 is the high 16 bits of .value and
2657 .mask, hw2 the low 16 bits.
2658
2659 print_insn_thumb32 recognizes the following format control codes:
2660
2661 %% %
2662
2663 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2664 %M print a modified 12-bit immediate (same location)
2665 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2666 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 2667 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 2668 %S print a possibly-shifted Rm
2669
32a94698 2670 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 2671 %a print the address of a plain load/store
2672 %w print the width and signedness of a core load/store
2673 %m print register mask for ldm/stm
2674
2675 %E print the lsb and width fields of a bfc/bfi instruction
2676 %F print the lsb and width fields of a sbfx/ubfx instruction
2677 %b print a conditional branch offset
2678 %B print an unconditional branch offset
2679 %s print the shift field of an SSAT instruction
2680 %R print the rotation field of an SXT instruction
62b3e311
PB		 2681 %U print barrier type.
2682 %P print address for pli instruction.
c22aaad1
PB		 2683 %c print the condition code
2684 %x print warning if conditional an not at end of IT block"
2685 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 2686
2687 %<bitfield>d print bitfield in decimal
f0fba320 2688 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 2689 %<bitfield>W print bitfield*4 in decimal
2690 %<bitfield>r print bitfield as an ARM register
dd5181d5
KT		 2691 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
2692 %<bitfield>S as %<>R but r13 is UNPREDICTABLE
8f06b2d8
PB		 2693 %<bitfield>c print bitfield as a condition code
2694
16980d0b
JB		 2695 %<bitfield>'c print specified char iff bitfield is all ones
2696 %<bitfield>`c print specified char iff bitfield is all zeroes
2697 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 2698
2699 With one exception at the bottom (done because BL and BLX(1) need
2700 to come dead last), this table was machine-sorted first in
2701 decreasing order of number of bits set in the mask, then in
2702 increasing numeric order of mask, then in increasing numeric order
2703 of opcode. This order is not the clearest for a human reader, but
2704 is guaranteed never to catch a special-case bit pattern with a more
2705 general mask, which is important, because this instruction encoding
2706 makes heavy use of special-case bit patterns. */
2707static const struct opcode32 thumb32_opcodes[] =
2708{
16a1fa25
TP		 2709 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
2710 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4ed7ed8d
TP		 2711 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2712 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
2713 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2714 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
16a1fa25
TP		 2715 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2716 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
2717 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2718 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4ed7ed8d 2719
105bde57 2720 /* ARM V8.2 RAS extension instructions. */
4d1464f2 2721 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 2722 0xf3af8010, 0xffffffff, "esb"},
2723
53c4b28b 2724 /* V8 instructions. */
823d2571
TG		 2725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2726 0xf3af8005, 0xffffffff, "sevl%c.w"},
2727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2728 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2730 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2732 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
2733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2734 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
2735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2736 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
2737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2738 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
2739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2740 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
2741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2742 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
2743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2744 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2746 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2748 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
2749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2750 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2752 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2754 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2756 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 2757
dd5181d5 2758 /* CRC32 instructions. */
823d2571
TG		 2759 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2760 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"},
2761 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2762 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"},
2763 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2764 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"},
2765 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2766 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"},
2767 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2768 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"},
2769 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2770 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"},
dd5181d5 2771
62b3e311 2772 /* V7 instructions. */
823d2571
TG		 2773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
2774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
2775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
2776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
2777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
2778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
2779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
2780 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2781 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
2782 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2783 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 2784
90ec0d68 2785 /* Virtualization Extension instructions. */
823d2571 2786 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 2787 /* We skip ERET as that is SUBS pc, lr, #0. */
2788
60e5ef9f 2789 /* MP Extension instructions. */
823d2571 2790 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 2791
f4c65163 2792 /* Security extension instructions. */
823d2571 2793 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 2794
8f06b2d8 2795 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 2796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
2797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
2798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
2801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2802 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
2803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
2804
ff8646ee 2805 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2806 0xf3bf8f2f, 0xffffffff, "clrex%c"},
2807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2808 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
2809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2810 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
2811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2812 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
2813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2814 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
2815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2816 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
2817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2818 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
2819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2820 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
2821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2822 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
2823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2824 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
2825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2826 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
2827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2828 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
2829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2830 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
2831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2832 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 2833 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 2834 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 2835 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2836 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
2837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2838 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
2839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2840 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
2841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2842 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
2843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2844 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
2845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2846 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
2847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2848 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
2849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2850 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
2851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2852 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 2853 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2854 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
2855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2856 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
2857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2858 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
2859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2860 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
2861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2862 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
2863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2864 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
2865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2866 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
2867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2868 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
2869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2870 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
2871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2872 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
2873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2874 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
2875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2876 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
2877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2878 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
2879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2880 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
2881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2882 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
2883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2884 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
2885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2886 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
2887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2888 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
2889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2890 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
2891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2892 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
2893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2894 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
2895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2896 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
2897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2898 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
2899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2900 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
2901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2902 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
2903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2904 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
2905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2906 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
2907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2908 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
2909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2910 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
2911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2912 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
2913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2914 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
2915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2916 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
2917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2918 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
2919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2920 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
2921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2922 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
2923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2924 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
2925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2926 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
2927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2928 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
2929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2930 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
2931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2932 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
2933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2934 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
2935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2936 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
2937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2938 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
2939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2940 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
2941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2942 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
2943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2944 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
2945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2946 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
2947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2948 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
2949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2950 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
2951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2952 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
2953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2954 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2956 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2958 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2960 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 2961 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2962 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
2963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 2964 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 2965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2966 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
2967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2968 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
2969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2970 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2972 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
2973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2974 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
2975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2976 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2978 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2980 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2982 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2984 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2986 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2988 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2990 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
2991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2992 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
2993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2994 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
2995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2996 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
2997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2998 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
2999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3000 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
3001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3002 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
3003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3004 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
3005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3006 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
3007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3008 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
3009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3010 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
3011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3012 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
3013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3014 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3016 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3018 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3020 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3022 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3024 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3026 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3028 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 3029 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3030 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
3031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3032 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
3033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3034 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
3035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3036 0xf810f000, 0xff70f000, "pld%c\t%a"},
3037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3038 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3040 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3042 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3044 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3046 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3048 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3050 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3052 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
3053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3054 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
3055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3056 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
3057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3058 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
3059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3060 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
3061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3062 0xfb100000, 0xfff000c0,
3063 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3065 0xfbc00080, 0xfff000c0,
3066 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
3067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3068 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
3069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3070 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
3071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 3072 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 3073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3074 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
3075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3076 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 3077 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3078 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
3079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3080 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 3081 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3082 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
3083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3084 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
3085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3086 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
3087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3088 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
3089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3090 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
3091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3092 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
3093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3094 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
3095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3096 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
3097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3098 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
3099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3100 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
3101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3102 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 3103 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3104 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
3105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3106 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
3107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3108 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
3109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3110 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
3111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3112 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
3113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3114 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
3115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3116 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
3117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3118 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
3119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3120 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
3121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3122 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
3123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3124 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
3125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3126 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
3127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3128 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
3129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3130 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
3131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3132 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
3133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3134 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
3135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3136 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
3137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3138 0xe9400000, 0xff500000,
3139 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3141 0xe9500000, 0xff500000,
3142 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3144 0xe8600000, 0xff700000,
3145 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3147 0xe8700000, 0xff700000,
3148 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3150 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
3151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3152 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 3153
3154 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 3155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3156 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
3157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3158 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
3159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3160 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
3161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3162 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 3163
8f06b2d8 3164 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 3165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3166 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
3167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3168 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 3169
3170 /* Fallback. */
823d2571
TG		 3171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3172 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3173 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 3174};
ff4a8d2b 3175
8f06b2d8
PB		 3176static const char *const arm_conditional[] =
3177{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 3178 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 3179
3180static const char *const arm_fp_const[] =
3181{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3182
3183static const char *const arm_shift[] =
3184{"lsl", "lsr", "asr", "ror"};
3185
3186typedef struct
3187{
3188 const char *name;
3189 const char *description;
3190 const char *reg_names[16];
3191}
3192arm_regname;
3193
3194static const arm_regname regnames[] =
3195{
65b48a81 3196 { "reg-names-raw", N_("Select raw register names"),
8f06b2d8 3197 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
65b48a81 3198 { "reg-names-gcc", N_("Select register names used by GCC"),
8f06b2d8 3199 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 3200 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
8f06b2d8 3201 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65b48a81
PB		 3202 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
3203 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
3204 { "reg-names-apcs", N_("Select register names used in the APCS"),
8f06b2d8 3205 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 3206 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
8f06b2d8 3207 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
65b48a81
PB		 3208 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
3209 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
8f06b2d8
PB		 3210};
3211
3212static const char *const iwmmxt_wwnames[] =
3213{"b", "h", "w", "d"};
3214
3215static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 3216{"b", "bus", "bc", "bss",
3217 "h", "hus", "hc", "hss",
3218 "w", "wus", "wc", "wss",
3219 "d", "dus", "dc", "dss"
8f06b2d8
PB		 3220};
3221
3222static const char *const iwmmxt_regnames[] =
3223{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3224 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3225};
3226
3227static const char *const iwmmxt_cregnames[] =
3228{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3229 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3230};
3231
3232/* Default to GCC register name set. */
3233static unsigned int regname_selected = 1;
3234
65b48a81 3235#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
8f06b2d8
PB		 3236#define arm_regnames regnames[regname_selected].reg_names
3237
3238static bfd_boolean force_thumb = FALSE;
3239
c22aaad1
PB		 3240/* Current IT instruction state. This contains the same state as the IT
3241 bits in the CPSR. */
3242static unsigned int ifthen_state;
3243/* IT state for the next instruction. */
3244static unsigned int ifthen_next_state;
3245/* The address of the insn for which the IT state is valid. */
3246static bfd_vma ifthen_address;
3247#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 3248/* Indicates that the current Conditional state is unconditional or outside
3249 an IT block. */
3250#define COND_UNCOND 16
c22aaad1 3251
8f06b2d8
PB		 3252\f
3253/* Functions. */
8f06b2d8 3254
16980d0b
JB		 3255/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3256 Returns pointer to following character of the format string and
3257 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 3258 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 3259
3260static const char *
fe56b6ce
NC		 3261arm_decode_bitfield (const char *ptr,
3262 unsigned long insn,
3263 unsigned long *valuep,
3264 int *widthp)
16980d0b
JB		 3265{
3266 unsigned long value = 0;
3267 int width = 0;
43e65147
L		 3268
3269 do
16980d0b
JB		 3270 {
3271 int start, end;
3272 int bits;
3273
3274 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3275 start = start * 10 + *ptr - '0';
3276 if (*ptr == '-')
3277 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3278 end = end * 10 + *ptr - '0';
3279 else
3280 end = start;
3281 bits = end - start;
3282 if (bits < 0)
3283 abort ();
3284 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3285 width += bits + 1;
3286 }
3287 while (*ptr++ == ',');
3288 *valuep = value;
3289 if (widthp)
3290 *widthp = width;
3291 return ptr - 1;
3292}
3293
8f06b2d8 3294static void
37b37b2d 3295arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 3296 bfd_boolean print_shift)
8f06b2d8
PB		 3297{
3298 func (stream, "%s", arm_regnames[given & 0xf]);
3299
3300 if ((given & 0xff0) != 0)
3301 {
3302 if ((given & 0x10) == 0)
3303 {
3304 int amount = (given & 0xf80) >> 7;
3305 int shift = (given & 0x60) >> 5;
3306
3307 if (amount == 0)
3308 {
3309 if (shift == 3)
3310 {
3311 func (stream, ", rrx");
3312 return;
3313 }
3314
3315 amount = 32;
3316 }
3317
37b37b2d
RE		 3318 if (print_shift)
3319 func (stream, ", %s #%d", arm_shift[shift], amount);
3320 else
3321 func (stream, ", #%d", amount);
8f06b2d8 3322 }
74bdfecf 3323 else if ((given & 0x80) == 0x80)
aefd8a40 3324 func (stream, "\t; <illegal shifter operand>");
37b37b2d 3325 else if (print_shift)
8f06b2d8
PB		 3326 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3327 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 3328 else
3329 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 3330 }
3331}
3332
c1e26897
NC		 3333#define W_BIT 21
3334#define I_BIT 22
3335#define U_BIT 23
3336#define P_BIT 24
3337
3338#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
3339#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
3340#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
3341#define PRE_BIT_SET (given & (1 << P_BIT))
3342
8f06b2d8
PB		 3343/* Print one coprocessor instruction on INFO->STREAM.
3344 Return TRUE if the instuction matched, FALSE if this is not a
3345 recognised coprocessor instruction. */
3346
3347static bfd_boolean
fe56b6ce
NC		 3348print_insn_coprocessor (bfd_vma pc,
3349 struct disassemble_info *info,
3350 long given,
8f06b2d8
PB		 3351 bfd_boolean thumb)
3352{
3353 const struct opcode32 *insn;
3354 void *stream = info->stream;
3355 fprintf_ftype func = info->fprintf_func;
3356 unsigned long mask;
2edcd244 3357 unsigned long value = 0;
c22aaad1 3358 int cond;
8afc7bea 3359 int cp_num;
823d2571
TG		 3360 struct arm_private_data *private_data = info->private_data;
3361 arm_feature_set allowed_arches = ARM_ARCH_NONE;
3362
3363 ARM_FEATURE_COPY (allowed_arches, private_data->features);
8f06b2d8
PB		 3364
3365 for (insn = coprocessor_opcodes; insn->assembler; insn++)
3366 {
ff4a8d2b
NC		 3367 unsigned long u_reg = 16;
3368 bfd_boolean is_unpredictable = FALSE;
05413229 3369 signed long value_in_comment = 0;
0313a2b8
NC		 3370 const char *c;
3371
823d2571 3372 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 3373 switch (insn->value)
3374 {
3375 case SENTINEL_IWMMXT_START:
3376 if (info->mach != bfd_mach_arm_XScale
3377 && info->mach != bfd_mach_arm_iWMMXt
3378 && info->mach != bfd_mach_arm_iWMMXt2)
3379 do
3380 insn++;
823d2571
TG		 3381 while ((! ARM_FEATURE_ZERO (insn->arch))
3382 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 3383 continue;
3384
3385 case SENTINEL_IWMMXT_END:
3386 continue;
3387
3388 case SENTINEL_GENERIC_START:
823d2571 3389 ARM_FEATURE_COPY (allowed_arches, private_data->features);
05413229
NC		 3390 continue;
3391
3392 default:
3393 abort ();
3394 }
8f06b2d8
PB		 3395
3396 mask = insn->mask;
3397 value = insn->value;
8afc7bea
RL		 3398 cp_num = (given >> 8) & 0xf;
3399
8f06b2d8
PB		 3400 if (thumb)
3401 {
3402 /* The high 4 bits are 0xe for Arm conditional instructions, and
3403 0xe for arm unconditional instructions. The rest of the
3404 encoding is the same. */
3405 mask |= 0xf0000000;
3406 value |= 0xe0000000;
c22aaad1
PB		 3407 if (ifthen_state)
3408 cond = IFTHEN_COND;
3409 else
e2efe87d 3410 cond = COND_UNCOND;
8f06b2d8
PB		 3411 }
3412 else
3413 {
3414 /* Only match unconditional instuctions against unconditional
3415 patterns. */
3416 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 3417 {
3418 mask |= 0xf0000000;
e2efe87d 3419 cond = COND_UNCOND;
c22aaad1
PB		 3420 }
3421 else
3422 {
3423 cond = (given >> 28) & 0xf;
3424 if (cond == 0xe)
e2efe87d 3425 cond = COND_UNCOND;
c22aaad1 3426 }
8f06b2d8 3427 }
823d2571 3428
0313a2b8
NC		 3429 if ((given & mask) != value)
3430 continue;
8f06b2d8 3431
823d2571 3432 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 3433 continue;
3434
8afc7bea
RL		 3435 if (insn->value == 0xfe000010 /* mcr2 */
3436 || insn->value == 0xfe100010 /* mrc2 */
3437 || insn->value == 0xfc100000 /* ldc2 */
3438 || insn->value == 0xfc000000) /* stc2 */
3439 {
b0c11777 3440 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea
RL		 3441 is_unpredictable = TRUE;
3442 }
3443 else if (insn->value == 0x0e000000 /* cdp */
3444 || insn->value == 0xfe000000 /* cdp2 */
3445 || insn->value == 0x0e000010 /* mcr */
3446 || insn->value == 0x0e100010 /* mrc */
3447 || insn->value == 0x0c100000 /* ldc */
3448 || insn->value == 0x0c000000) /* stc */
3449 {
3450 /* Floating-point instructions. */
b0c11777 3451 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea
RL		 3452 continue;
3453 }
3454
0313a2b8
NC		 3455 for (c = insn->assembler; *c; c++)
3456 {
3457 if (*c == '%')
8f06b2d8 3458 {
0313a2b8 3459 switch (*++c)
8f06b2d8 3460 {
0313a2b8
NC		 3461 case '%':
3462 func (stream, "%%");
3463 break;
3464
3465 case 'A':
05413229 3466 {
79862e45 3467 int rn = (given >> 16) & 0xf;
b0c11777 3468 bfd_vma offset = given & 0xff;
0313a2b8 3469
05413229 3470 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 3471
79862e45
DJ		 3472 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
3473 {
3474 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 3475 if (cp_num == 9)
3476 /* vldr.16/vstr.16 will shift the address
3477 left by 1 bit only. */
3478 offset = offset * 2;
3479 else
3480 offset = offset * 4;
3481
79862e45
DJ		 3482 if (NEGATIVE_BIT_SET)
3483 offset = - offset;
3484 if (rn != 15)
3485 value_in_comment = offset;
3486 }
3487
c1e26897 3488 if (PRE_BIT_SET)
05413229
NC		 3489 {
3490 if (offset)
fe56b6ce 3491 func (stream, ", #%d]%s",
d908c8af 3492 (int) offset,
c1e26897 3493 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 3494 else if (NEGATIVE_BIT_SET)
3495 func (stream, ", #-0]");
05413229
NC		 3496 else
3497 func (stream, "]");
3498 }
3499 else
3500 {
0313a2b8 3501 func (stream, "]");
8f06b2d8 3502
c1e26897 3503 if (WRITEBACK_BIT_SET)
05413229
NC		 3504 {
3505 if (offset)
d908c8af 3506 func (stream, ", #%d", (int) offset);
26d97720
NS		 3507 else if (NEGATIVE_BIT_SET)
3508 func (stream, ", #-0");
05413229
NC		 3509 }
3510 else
fe56b6ce 3511 {
26d97720
NS		 3512 func (stream, ", {%s%d}",
3513 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 3514 (int) offset);
fe56b6ce
NC		 3515 value_in_comment = offset;
3516 }
05413229 3517 }
79862e45
DJ		 3518 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
3519 {
3520 func (stream, "\t; ");
6844b2c2
MGD		 3521 /* For unaligned PCs, apply off-by-alignment
3522 correction. */
43e65147 3523 info->print_address_func (offset + pc
6844b2c2
MGD		 3524 + info->bytes_per_chunk * 2
3525 - (pc & 3),
3526 info);
79862e45 3527 }
05413229 3528 }
0313a2b8 3529 break;
8f06b2d8 3530
0313a2b8
NC		 3531 case 'B':
3532 {
3533 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
3534 int offset = (given >> 1) & 0x3f;
3535
3536 if (offset == 1)
3537 func (stream, "{d%d}", regno);
3538 else if (regno + offset > 32)
3539 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
3540 else
3541 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
3542 }
3543 break;
8f06b2d8 3544
e2efe87d
MGD		 3545 case 'u':
3546 if (cond != COND_UNCOND)
3547 is_unpredictable = TRUE;
3548
3549 /* Fall through. */
0313a2b8 3550 case 'c':
b0c11777
RL		 3551 if (cond != COND_UNCOND && cp_num == 9)
3552 is_unpredictable = TRUE;
3553
0313a2b8
NC		 3554 func (stream, "%s", arm_conditional[cond]);
3555 break;
8f06b2d8 3556
0313a2b8
NC		 3557 case 'I':
3558 /* Print a Cirrus/DSP shift immediate. */
3559 /* Immediates are 7bit signed ints with bits 0..3 in
3560 bits 0..3 of opcode and bits 4..6 in bits 5..7
3561 of opcode. */
3562 {
3563 int imm;
8f06b2d8 3564
0313a2b8 3565 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 3566
0313a2b8
NC		 3567 /* Is ``imm'' a negative number? */
3568 if (imm & 0x40)
24b4cf66 3569 imm -= 0x80;
8f06b2d8 3570
0313a2b8
NC		 3571 func (stream, "%d", imm);
3572 }
3573
3574 break;
8f06b2d8 3575
0313a2b8
NC		 3576 case 'F':
3577 switch (given & 0x00408000)
3578 {
3579 case 0:
3580 func (stream, "4");
3581 break;
3582 case 0x8000:
3583 func (stream, "1");
3584 break;
3585 case 0x00400000:
3586 func (stream, "2");
8f06b2d8 3587 break;
0313a2b8
NC		 3588 default:
3589 func (stream, "3");
3590 }
3591 break;
8f06b2d8 3592
0313a2b8
NC		 3593 case 'P':
3594 switch (given & 0x00080080)
3595 {
3596 case 0:
3597 func (stream, "s");
3598 break;
3599 case 0x80:
3600 func (stream, "d");
3601 break;
3602 case 0x00080000:
3603 func (stream, "e");
3604 break;
3605 default:
3606 func (stream, _("<illegal precision>"));
8f06b2d8 3607 break;
0313a2b8
NC		 3608 }
3609 break;
8f06b2d8 3610
0313a2b8
NC		 3611 case 'Q':
3612 switch (given & 0x00408000)
3613 {
3614 case 0:
3615 func (stream, "s");
8f06b2d8 3616 break;
0313a2b8
NC		 3617 case 0x8000:
3618 func (stream, "d");
8f06b2d8 3619 break;
0313a2b8
NC		 3620 case 0x00400000:
3621 func (stream, "e");
3622 break;
3623 default:
3624 func (stream, "p");
8f06b2d8 3625 break;
0313a2b8
NC		 3626 }
3627 break;
8f06b2d8 3628
0313a2b8
NC		 3629 case 'R':
3630 switch (given & 0x60)
3631 {
3632 case 0:
3633 break;
3634 case 0x20:
3635 func (stream, "p");
3636 break;
3637 case 0x40:
3638 func (stream, "m");
3639 break;
3640 default:
3641 func (stream, "z");
3642 break;
3643 }
3644 break;
16980d0b 3645
0313a2b8
NC		 3646 case '0': case '1': case '2': case '3': case '4':
3647 case '5': case '6': case '7': case '8': case '9':
3648 {
3649 int width;
8f06b2d8 3650
0313a2b8 3651 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 3652
0313a2b8
NC		 3653 switch (*c)
3654 {
ff4a8d2b
NC		 3655 case 'R':
3656 if (value == 15)
3657 is_unpredictable = TRUE;
3658 /* Fall through. */
0313a2b8 3659 case 'r':
ff4a8d2b
NC		 3660 if (c[1] == 'u')
3661 {
3662 /* Eat the 'u' character. */
3663 ++ c;
3664
3665 if (u_reg == value)
3666 is_unpredictable = TRUE;
3667 u_reg = value;
3668 }
0313a2b8
NC		 3669 func (stream, "%s", arm_regnames[value]);
3670 break;
c28eeff2
SN		 3671 case 'V':
3672 if (given & (1 << 6))
3673 goto Q;
3674 /* FALLTHROUGH */
0313a2b8
NC		 3675 case 'D':
3676 func (stream, "d%ld", value);
3677 break;
3678 case 'Q':
c28eeff2 3679 Q:
0313a2b8
NC		 3680 if (value & 1)
3681 func (stream, "<illegal reg q%ld.5>", value >> 1);
3682 else
3683 func (stream, "q%ld", value >> 1);
3684 break;
3685 case 'd':
3686 func (stream, "%ld", value);
05413229 3687 value_in_comment = value;
0313a2b8 3688 break;
6f1c2142
AM		 3689 case 'E':
3690 {
3691 /* Converts immediate 8 bit back to float value. */
3692 unsigned floatVal = (value & 0x80) << 24
3693 | (value & 0x3F) << 19
3694 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
3695
3696 /* Quarter float have a maximum value of 31.0.
3697 Get floating point value multiplied by 1e7.
3698 The maximum value stays in limit of a 32-bit int. */
3699 unsigned decVal =
3700 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
3701 (16 + (value & 0xF));
3702
3703 if (!(decVal % 1000000))
3704 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
3705 floatVal, value & 0x80 ? '-' : ' ',
3706 decVal / 10000000,
3707 decVal % 10000000 / 1000000);
3708 else if (!(decVal % 10000))
3709 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
3710 floatVal, value & 0x80 ? '-' : ' ',
3711 decVal / 10000000,
3712 decVal % 10000000 / 10000);
3713 else
3714 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
3715 floatVal, value & 0x80 ? '-' : ' ',
3716 decVal / 10000000, decVal % 10000000);
3717 break;
3718 }
0313a2b8
NC		 3719 case 'k':
3720 {
3721 int from = (given & (1 << 7)) ? 32 : 16;
3722 func (stream, "%ld", from - value);
3723 }
3724 break;
8f06b2d8 3725
0313a2b8
NC		 3726 case 'f':
3727 if (value > 7)
3728 func (stream, "#%s", arm_fp_const[value & 7]);
3729 else
3730 func (stream, "f%ld", value);
3731 break;
4146fd53 3732
0313a2b8
NC		 3733 case 'w':
3734 if (width == 2)
3735 func (stream, "%s", iwmmxt_wwnames[value]);
3736 else
3737 func (stream, "%s", iwmmxt_wwssnames[value]);
3738 break;
4146fd53 3739
0313a2b8
NC		 3740 case 'g':
3741 func (stream, "%s", iwmmxt_regnames[value]);
3742 break;
3743 case 'G':
3744 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 3745 break;
8f06b2d8 3746
0313a2b8 3747 case 'x':
d1aaab3c 3748 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 3749 break;
8f06b2d8 3750
33399f07
MGD		 3751 case 'c':
3752 switch (value)
3753 {
3754 case 0:
3755 func (stream, "eq");
3756 break;
3757
3758 case 1:
3759 func (stream, "vs");
3760 break;
3761
3762 case 2:
3763 func (stream, "ge");
3764 break;
3765
3766 case 3:
3767 func (stream, "gt");
3768 break;
3769
3770 default:
3771 func (stream, "??");
3772 break;
3773 }
3774 break;
3775
0313a2b8
NC		 3776 case '`':
3777 c++;
3778 if (value == 0)
3779 func (stream, "%c", *c);
3780 break;
3781 case '\'':
3782 c++;
3783 if (value == ((1ul << width) - 1))
3784 func (stream, "%c", *c);
3785 break;
3786 case '?':
fe56b6ce 3787 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 3788 c += 1 << width;
3789 break;
3790 default:
3791 abort ();
3792 }
3793 break;
8f06b2d8 3794
0313a2b8
NC		 3795 case 'y':
3796 case 'z':
3797 {
3798 int single = *c++ == 'y';
3799 int regno;
3800
3801 switch (*c)
3802 {
3803 case '4': /* Sm pair */
3804 case '0': /* Sm, Dm */
3805 regno = given & 0x0000000f;
3806 if (single)
3807 {
3808 regno <<= 1;
3809 regno += (given >> 5) & 1;
16980d0b 3810 }
0313a2b8
NC		 3811 else
3812 regno += ((given >> 5) & 1) << 4;
3813 break;
8f06b2d8 3814
0313a2b8
NC		 3815 case '1': /* Sd, Dd */
3816 regno = (given >> 12) & 0x0000000f;
3817 if (single)
3818 {
3819 regno <<= 1;
3820 regno += (given >> 22) & 1;
3821 }
3822 else
3823 regno += ((given >> 22) & 1) << 4;
3824 break;
8f06b2d8 3825
0313a2b8
NC		 3826 case '2': /* Sn, Dn */
3827 regno = (given >> 16) & 0x0000000f;
3828 if (single)
8f06b2d8 3829 {
0313a2b8
NC		 3830 regno <<= 1;
3831 regno += (given >> 7) & 1;
8f06b2d8 3832 }
0313a2b8
NC		 3833 else
3834 regno += ((given >> 7) & 1) << 4;
3835 break;
7df76b80 3836
0313a2b8
NC		 3837 case '3': /* List */
3838 func (stream, "{");
3839 regno = (given >> 12) & 0x0000000f;
3840 if (single)
3841 {
3842 regno <<= 1;
3843 regno += (given >> 22) & 1;
3844 }
3845 else
3846 regno += ((given >> 22) & 1) << 4;
3847 break;
a7f8487e 3848
0313a2b8
NC		 3849 default:
3850 abort ();
8f06b2d8 3851 }
a7f8487e 3852
0313a2b8
NC		 3853 func (stream, "%c%d", single ? 's' : 'd', regno);
3854
3855 if (*c == '3')
8f06b2d8 3856 {
0313a2b8 3857 int count = given & 0xff;
a7f8487e 3858
0313a2b8
NC		 3859 if (single == 0)
3860 count >>= 1;
b34976b6 3861
0313a2b8 3862 if (--count)
8f06b2d8 3863 {
0313a2b8
NC		 3864 func (stream, "-%c%d",
3865 single ? 's' : 'd',
3866 regno + count);
8f06b2d8 3867 }
0313a2b8
NC		 3868
3869 func (stream, "}");
8f06b2d8 3870 }
0313a2b8
NC		 3871 else if (*c == '4')
3872 func (stream, ", %c%d", single ? 's' : 'd',
3873 regno + 1);
3874 }
3875 break;
3876
3877 case 'L':
3878 switch (given & 0x00400100)
3879 {
3880 case 0x00000000: func (stream, "b"); break;
3881 case 0x00400000: func (stream, "h"); break;
3882 case 0x00000100: func (stream, "w"); break;
3883 case 0x00400100: func (stream, "d"); break;
3884 default:
8f06b2d8 3885 break;
0313a2b8
NC		 3886 }
3887 break;
b34976b6 3888
0313a2b8
NC		 3889 case 'Z':
3890 {
0313a2b8
NC		 3891 /* given (20, 23) | given (0, 3) */
3892 value = ((given >> 16) & 0xf0) | (given & 0xf);
d908c8af 3893 func (stream, "%d", (int) value);
0313a2b8
NC		 3894 }
3895 break;
2d447fca 3896
0313a2b8
NC		 3897 case 'l':
3898 /* This is like the 'A' operator, except that if
3899 the width field "M" is zero, then the offset is
3900 *not* multiplied by four. */
3901 {
3902 int offset = given & 0xff;
3903 int multiplier = (given & 0x00000100) ? 4 : 1;
3904
3905 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3906
05413229
NC		 3907 if (multiplier > 1)
3908 {
3909 value_in_comment = offset * multiplier;
c1e26897 3910 if (NEGATIVE_BIT_SET)
05413229
NC		 3911 value_in_comment = - value_in_comment;
3912 }
3913
0313a2b8
NC		 3914 if (offset)
3915 {
c1e26897 3916 if (PRE_BIT_SET)
0313a2b8 3917 func (stream, ", #%s%d]%s",
c1e26897 3918 NEGATIVE_BIT_SET ? "-" : "",
0313a2b8 3919 offset * multiplier,
c1e26897 3920 WRITEBACK_BIT_SET ? "!" : "");
0313a2b8
NC		 3921 else
3922 func (stream, "], #%s%d",
c1e26897 3923 NEGATIVE_BIT_SET ? "-" : "",
0313a2b8 3924 offset * multiplier);
2d447fca 3925 }
0313a2b8
NC		 3926 else
3927 func (stream, "]");
3928 }
3929 break;
3930
3931 case 'r':
3932 {
3933 int imm4 = (given >> 4) & 0xf;
c1e26897
NC		 3934 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
3935 int ubit = ! NEGATIVE_BIT_SET;
0313a2b8
NC		 3936 const char *rm = arm_regnames [given & 0xf];
3937 const char *rn = arm_regnames [(given >> 16) & 0xf];
2d447fca 3938
0313a2b8 3939 switch (puw_bits)
2d447fca 3940 {
0313a2b8
NC		 3941 case 1:
3942 case 3:
3943 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
3944 if (imm4)
3945 func (stream, ", lsl #%d", imm4);
3946 break;
3947
3948 case 4:
3949 case 5:
3950 case 6:
3951 case 7:
3952 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
3953 if (imm4 > 0)
3954 func (stream, ", lsl #%d", imm4);
3955 func (stream, "]");
3956 if (puw_bits == 5 || puw_bits == 7)
3957 func (stream, "!");
3958 break;
3959
3960 default:
3961 func (stream, "INVALID");
2d447fca 3962 }
0313a2b8
NC		 3963 }
3964 break;
2d447fca 3965
0313a2b8
NC		 3966 case 'i':
3967 {
3968 long imm5;
3969 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
3970 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
8f06b2d8 3971 }
0313a2b8
NC		 3972 break;
3973
3974 default:
3975 abort ();
3976 }
252b5132 3977 }
252b5132 3978 }
0313a2b8
NC		 3979 else
3980 func (stream, "%c", *c);
252b5132 3981 }
05413229
NC		 3982
3983 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 3984 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 3985
ff4a8d2b
NC		 3986 if (is_unpredictable)
3987 func (stream, UNPREDICTABLE_INSTRUCTION);
3988
0313a2b8 3989 return TRUE;
252b5132 3990 }
8f06b2d8 3991 return FALSE;
252b5132
RH		 3992}
3993
05413229
NC		 3994/* Decodes and prints ARM addressing modes. Returns the offset
3995 used in the address, if any, if it is worthwhile printing the
3996 offset as a hexadecimal value in a comment at the end of the
3997 line of disassembly. */
3998
3999static signed long
62b3e311
PB		 4000print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
4001{
4002 void *stream = info->stream;
4003 fprintf_ftype func = info->fprintf_func;
f8b960bc 4004 bfd_vma offset = 0;
62b3e311
PB		 4005
4006 if (((given & 0x000f0000) == 0x000f0000)
4007 && ((given & 0x02000000) == 0))
4008 {
05413229 4009 offset = given & 0xfff;
62b3e311
PB		 4010
4011 func (stream, "[pc");
4012
c1e26897 4013 if (PRE_BIT_SET)
62b3e311 4014 {
26d97720
NS		 4015 /* Pre-indexed. Elide offset of positive zero when
4016 non-writeback. */
4017 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 4018 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 4019
4020 if (NEGATIVE_BIT_SET)
4021 offset = -offset;
62b3e311
PB		 4022
4023 offset += pc + 8;
4024
4025 /* Cope with the possibility of write-back
4026 being used. Probably a very dangerous thing
4027 for the programmer to do, but who are we to
4028 argue ? */
26d97720 4029 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 4030 }
c1e26897 4031 else /* Post indexed. */
62b3e311 4032 {
d908c8af 4033 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 4034
c1e26897 4035 /* Ie ignore the offset. */
62b3e311
PB		 4036 offset = pc + 8;
4037 }
4038
4039 func (stream, "\t; ");
4040 info->print_address_func (offset, info);
05413229 4041 offset = 0;
62b3e311
PB		 4042 }
4043 else
4044 {
4045 func (stream, "[%s",
4046 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 4047
4048 if (PRE_BIT_SET)
62b3e311
PB		 4049 {
4050 if ((given & 0x02000000) == 0)
4051 {
26d97720 4052 /* Elide offset of positive zero when non-writeback. */
05413229 4053 offset = given & 0xfff;
26d97720 4054 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 4055 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 4056 }
4057 else
4058 {
26d97720 4059 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 4060 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 4061 }
4062
4063 func (stream, "]%s",
c1e26897 4064 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 4065 }
4066 else
4067 {
4068 if ((given & 0x02000000) == 0)
4069 {
26d97720 4070 /* Always show offset. */
05413229 4071 offset = given & 0xfff;
26d97720 4072 func (stream, "], #%s%d",
d908c8af 4073 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 4074 }
4075 else
4076 {
4077 func (stream, "], %s",
c1e26897 4078 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 4079 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 4080 }
4081 }
84919466
MR		 4082 if (NEGATIVE_BIT_SET)
4083 offset = -offset;
62b3e311 4084 }
05413229
NC		 4085
4086 return (signed long) offset;
62b3e311
PB		 4087}
4088
16980d0b
JB		 4089/* Print one neon instruction on INFO->STREAM.
4090 Return TRUE if the instuction matched, FALSE if this is not a
4091 recognised neon instruction. */
4092
4093static bfd_boolean
4094print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
4095{
4096 const struct opcode32 *insn;
4097 void *stream = info->stream;
4098 fprintf_ftype func = info->fprintf_func;
4099
4100 if (thumb)
4101 {
4102 if ((given & 0xef000000) == 0xef000000)
4103 {
0313a2b8 4104 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 4105 unsigned long bit28 = given & (1 << 28);
4106
4107 given &= 0x00ffffff;
4108 if (bit28)
4109 given |= 0xf3000000;
4110 else
4111 given |= 0xf2000000;
4112 }
4113 else if ((given & 0xff000000) == 0xf9000000)
4114 given ^= 0xf9000000 ^ 0xf4000000;
4115 else
4116 return FALSE;
4117 }
43e65147 4118
16980d0b
JB		 4119 for (insn = neon_opcodes; insn->assembler; insn++)
4120 {
4121 if ((given & insn->mask) == insn->value)
4122 {
05413229 4123 signed long value_in_comment = 0;
e2efe87d 4124 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 4125 const char *c;
4126
4127 for (c = insn->assembler; *c; c++)
4128 {
4129 if (*c == '%')
4130 {
4131 switch (*++c)
4132 {
4133 case '%':
4134 func (stream, "%%");
4135 break;
4136
e2efe87d
MGD		 4137 case 'u':
4138 if (thumb && ifthen_state)
4139 is_unpredictable = TRUE;
4140
4141 /* Fall through. */
c22aaad1
PB		 4142 case 'c':
4143 if (thumb && ifthen_state)
4144 func (stream, "%s", arm_conditional[IFTHEN_COND]);
4145 break;
4146
16980d0b
JB		 4147 case 'A':
4148 {
43e65147 4149 static const unsigned char enc[16] =
16980d0b
JB		 4150 {
4151 0x4, 0x14, /* st4 0,1 */
4152 0x4, /* st1 2 */
4153 0x4, /* st2 3 */
4154 0x3, /* st3 4 */
4155 0x13, /* st3 5 */
4156 0x3, /* st1 6 */
4157 0x1, /* st1 7 */
4158 0x2, /* st2 8 */
4159 0x12, /* st2 9 */
4160 0x2, /* st1 10 */
4161 0, 0, 0, 0, 0
4162 };
4163 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4164 int rn = ((given >> 16) & 0xf);
4165 int rm = ((given >> 0) & 0xf);
4166 int align = ((given >> 4) & 0x3);
4167 int type = ((given >> 8) & 0xf);
4168 int n = enc[type] & 0xf;
4169 int stride = (enc[type] >> 4) + 1;
4170 int ix;
43e65147 4171
16980d0b
JB		 4172 func (stream, "{");
4173 if (stride > 1)
4174 for (ix = 0; ix != n; ix++)
4175 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
4176 else if (n == 1)
4177 func (stream, "d%d", rd);
4178 else
4179 func (stream, "d%d-d%d", rd, rd + n - 1);
4180 func (stream, "}, [%s", arm_regnames[rn]);
4181 if (align)
8e560766 4182 func (stream, " :%d", 32 << align);
16980d0b
JB		 4183 func (stream, "]");
4184 if (rm == 0xd)
4185 func (stream, "!");
4186 else if (rm != 0xf)
4187 func (stream, ", %s", arm_regnames[rm]);
4188 }
4189 break;
43e65147 4190
16980d0b
JB		 4191 case 'B':
4192 {
4193 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4194 int rn = ((given >> 16) & 0xf);
4195 int rm = ((given >> 0) & 0xf);
4196 int idx_align = ((given >> 4) & 0xf);
4197 int align = 0;
4198 int size = ((given >> 10) & 0x3);
4199 int idx = idx_align >> (size + 1);
4200 int length = ((given >> 8) & 3) + 1;
4201 int stride = 1;
4202 int i;
4203
4204 if (length > 1 && size > 0)
4205 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 4206
16980d0b
JB		 4207 switch (length)
4208 {
4209 case 1:
4210 {
4211 int amask = (1 << size) - 1;
4212 if ((idx_align & (1 << size)) != 0)
4213 return FALSE;
4214 if (size > 0)
4215 {
4216 if ((idx_align & amask) == amask)
4217 align = 8 << size;
4218 else if ((idx_align & amask) != 0)
4219 return FALSE;
4220 }
4221 }
4222 break;
43e65147 4223
16980d0b
JB		 4224 case 2:
4225 if (size == 2 && (idx_align & 2) != 0)
4226 return FALSE;
4227 align = (idx_align & 1) ? 16 << size : 0;
4228 break;
43e65147 4229
16980d0b
JB		 4230 case 3:
4231 if ((size == 2 && (idx_align & 3) != 0)
4232 || (idx_align & 1) != 0)
4233 return FALSE;
4234 break;
43e65147 4235
16980d0b
JB		 4236 case 4:
4237 if (size == 2)
4238 {
4239 if ((idx_align & 3) == 3)
4240 return FALSE;
4241 align = (idx_align & 3) * 64;
4242 }
4243 else
4244 align = (idx_align & 1) ? 32 << size : 0;
4245 break;
43e65147 4246
16980d0b
JB		 4247 default:
4248 abort ();
4249 }
43e65147 4250
16980d0b
JB		 4251 func (stream, "{");
4252 for (i = 0; i < length; i++)
4253 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
4254 rd + i * stride, idx);
4255 func (stream, "}, [%s", arm_regnames[rn]);
4256 if (align)
8e560766 4257 func (stream, " :%d", align);
16980d0b
JB		 4258 func (stream, "]");
4259 if (rm == 0xd)
4260 func (stream, "!");
4261 else if (rm != 0xf)
4262 func (stream, ", %s", arm_regnames[rm]);
4263 }
4264 break;
43e65147 4265
16980d0b
JB		 4266 case 'C':
4267 {
4268 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4269 int rn = ((given >> 16) & 0xf);
4270 int rm = ((given >> 0) & 0xf);
4271 int align = ((given >> 4) & 0x1);
4272 int size = ((given >> 6) & 0x3);
4273 int type = ((given >> 8) & 0x3);
4274 int n = type + 1;
4275 int stride = ((given >> 5) & 0x1);
4276 int ix;
43e65147 4277
16980d0b
JB		 4278 if (stride && (n == 1))
4279 n++;
4280 else
4281 stride++;
43e65147 4282
16980d0b
JB		 4283 func (stream, "{");
4284 if (stride > 1)
4285 for (ix = 0; ix != n; ix++)
4286 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
4287 else if (n == 1)
4288 func (stream, "d%d[]", rd);
4289 else
4290 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
4291 func (stream, "}, [%s", arm_regnames[rn]);
4292 if (align)
4293 {
91d6fa6a 4294 align = (8 * (type + 1)) << size;
16980d0b
JB		 4295 if (type == 3)
4296 align = (size > 1) ? align >> 1 : align;
4297 if (type == 2 || (type == 0 && !size))
8e560766 4298 func (stream, " :<bad align %d>", align);
16980d0b 4299 else
8e560766 4300 func (stream, " :%d", align);
16980d0b
JB		 4301 }
4302 func (stream, "]");
4303 if (rm == 0xd)
4304 func (stream, "!");
4305 else if (rm != 0xf)
4306 func (stream, ", %s", arm_regnames[rm]);
4307 }
4308 break;
43e65147 4309
16980d0b
JB		 4310 case 'D':
4311 {
4312 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
4313 int size = (given >> 20) & 3;
4314 int reg = raw_reg & ((4 << size) - 1);
4315 int ix = raw_reg >> size >> 2;
43e65147 4316
16980d0b
JB		 4317 func (stream, "d%d[%d]", reg, ix);
4318 }
4319 break;
43e65147 4320
16980d0b 4321 case 'E':
fe56b6ce 4322 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 4323 {
4324 int bits = 0;
4325 int cmode = (given >> 8) & 0xf;
4326 int op = (given >> 5) & 0x1;
4327 unsigned long value = 0, hival = 0;
4328 unsigned shift;
4329 int size = 0;
0dbde4cf 4330 int isfloat = 0;
43e65147 4331
16980d0b
JB		 4332 bits |= ((given >> 24) & 1) << 7;
4333 bits |= ((given >> 16) & 7) << 4;
4334 bits |= ((given >> 0) & 15) << 0;
43e65147 4335
16980d0b
JB		 4336 if (cmode < 8)
4337 {
4338 shift = (cmode >> 1) & 3;
fe56b6ce 4339 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4340 size = 32;
4341 }
4342 else if (cmode < 12)
4343 {
4344 shift = (cmode >> 1) & 1;
fe56b6ce 4345 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4346 size = 16;
4347 }
4348 else if (cmode < 14)
4349 {
4350 shift = (cmode & 1) + 1;
fe56b6ce 4351 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4352 value |= (1ul << (8 * shift)) - 1;
4353 size = 32;
4354 }
4355 else if (cmode == 14)
4356 {
4357 if (op)
4358 {
fe56b6ce 4359 /* Bit replication into bytes. */
16980d0b
JB		 4360 int ix;
4361 unsigned long mask;
43e65147 4362
16980d0b
JB		 4363 value = 0;
4364 hival = 0;
4365 for (ix = 7; ix >= 0; ix--)
4366 {
4367 mask = ((bits >> ix) & 1) ? 0xff : 0;
4368 if (ix <= 3)
4369 value = (value << 8) | mask;
4370 else
4371 hival = (hival << 8) | mask;
4372 }
4373 size = 64;
4374 }
4375 else
4376 {
fe56b6ce
NC		 4377 /* Byte replication. */
4378 value = (unsigned long) bits;
16980d0b
JB		 4379 size = 8;
4380 }
4381 }
4382 else if (!op)
4383 {
fe56b6ce 4384 /* Floating point encoding. */
16980d0b 4385 int tmp;
43e65147 4386
fe56b6ce
NC		 4387 value = (unsigned long) (bits & 0x7f) << 19;
4388 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 4389 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 4390 value |= (unsigned long) tmp << 24;
16980d0b 4391 size = 32;
0dbde4cf 4392 isfloat = 1;
16980d0b
JB		 4393 }
4394 else
4395 {
4396 func (stream, "<illegal constant %.8x:%x:%x>",
4397 bits, cmode, op);
4398 size = 32;
4399 break;
4400 }
4401 switch (size)
4402 {
4403 case 8:
4404 func (stream, "#%ld\t; 0x%.2lx", value, value);
4405 break;
43e65147 4406
16980d0b
JB		 4407 case 16:
4408 func (stream, "#%ld\t; 0x%.4lx", value, value);
4409 break;
4410
4411 case 32:
0dbde4cf
JB		 4412 if (isfloat)
4413 {
4414 unsigned char valbytes[4];
4415 double fvalue;
43e65147 4416
0dbde4cf
JB		 4417 /* Do this a byte at a time so we don't have to
4418 worry about the host's endianness. */
4419 valbytes[0] = value & 0xff;
4420 valbytes[1] = (value >> 8) & 0xff;
4421 valbytes[2] = (value >> 16) & 0xff;
4422 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 4423
4424 floatformat_to_double
c1e26897
NC		 4425 (& floatformat_ieee_single_little, valbytes,
4426 & fvalue);
43e65147 4427
0dbde4cf
JB		 4428 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
4429 value);
4430 }
4431 else
4e9d3b81 4432 func (stream, "#%ld\t; 0x%.8lx",
43e65147 4433 (long) (((value & 0x80000000L) != 0)
9d82ec38 4434 ? value | ~0xffffffffL : value),
c1e26897 4435 value);
16980d0b
JB		 4436 break;
4437
4438 case 64:
4439 func (stream, "#0x%.8lx%.8lx", hival, value);
4440 break;
43e65147 4441
16980d0b
JB		 4442 default:
4443 abort ();
4444 }
4445 }
4446 break;
43e65147 4447
16980d0b
JB		 4448 case 'F':
4449 {
4450 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
4451 int num = (given >> 8) & 0x3;
43e65147 4452
16980d0b
JB		 4453 if (!num)
4454 func (stream, "{d%d}", regno);
4455 else if (num + regno >= 32)
4456 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
4457 else
4458 func (stream, "{d%d-d%d}", regno, regno + num);
4459 }
4460 break;
7e8e6784 4461
16980d0b
JB		 4462
4463 case '0': case '1': case '2': case '3': case '4':
4464 case '5': case '6': case '7': case '8': case '9':
4465 {
4466 int width;
4467 unsigned long value;
4468
4469 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 4470
16980d0b
JB		 4471 switch (*c)
4472 {
4473 case 'r':
4474 func (stream, "%s", arm_regnames[value]);
4475 break;
4476 case 'd':
4477 func (stream, "%ld", value);
05413229 4478 value_in_comment = value;
16980d0b
JB		 4479 break;
4480 case 'e':
4481 func (stream, "%ld", (1ul << width) - value);
4482 break;
43e65147 4483
16980d0b
JB		 4484 case 'S':
4485 case 'T':
4486 case 'U':
05413229 4487 /* Various width encodings. */
16980d0b
JB		 4488 {
4489 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
4490 int limit;
4491 unsigned low, high;
4492
4493 c++;
4494 if (*c >= '0' && *c <= '9')
4495 limit = *c - '0';
4496 else if (*c >= 'a' && *c <= 'f')
4497 limit = *c - 'a' + 10;
4498 else
4499 abort ();
4500 low = limit >> 2;
4501 high = limit & 3;
4502
4503 if (value < low || value > high)
4504 func (stream, "<illegal width %d>", base << value);
4505 else
4506 func (stream, "%d", base << value);
4507 }
4508 break;
4509 case 'R':
4510 if (given & (1 << 6))
4511 goto Q;
4512 /* FALLTHROUGH */
4513 case 'D':
4514 func (stream, "d%ld", value);
4515 break;
4516 case 'Q':
4517 Q:
4518 if (value & 1)
4519 func (stream, "<illegal reg q%ld.5>", value >> 1);
4520 else
4521 func (stream, "q%ld", value >> 1);
4522 break;
43e65147 4523
16980d0b
JB		 4524 case '`':
4525 c++;
4526 if (value == 0)
4527 func (stream, "%c", *c);
4528 break;
4529 case '\'':
4530 c++;
4531 if (value == ((1ul << width) - 1))
4532 func (stream, "%c", *c);
4533 break;
4534 case '?':
fe56b6ce 4535 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 4536 c += 1 << width;
4537 break;
4538 default:
4539 abort ();
4540 }
4541 break;
4542
4543 default:
4544 abort ();
4545 }
4546 }
4547 }
4548 else
4549 func (stream, "%c", *c);
4550 }
05413229
NC		 4551
4552 if (value_in_comment > 32 || value_in_comment < -16)
4553 func (stream, "\t; 0x%lx", value_in_comment);
4554
e2efe87d
MGD		 4555 if (is_unpredictable)
4556 func (stream, UNPREDICTABLE_INSTRUCTION);
4557
16980d0b
JB		 4558 return TRUE;
4559 }
4560 }
4561 return FALSE;
4562}
4563
90ec0d68
MGD		 4564/* Return the name of a v7A special register. */
4565
43e65147 4566static const char *
90ec0d68
MGD		 4567banked_regname (unsigned reg)
4568{
4569 switch (reg)
4570 {
4571 case 15: return "CPSR";
43e65147 4572 case 32: return "R8_usr";
90ec0d68
MGD		 4573 case 33: return "R9_usr";
4574 case 34: return "R10_usr";
4575 case 35: return "R11_usr";
4576 case 36: return "R12_usr";
4577 case 37: return "SP_usr";
4578 case 38: return "LR_usr";
43e65147 4579 case 40: return "R8_fiq";
90ec0d68
MGD		 4580 case 41: return "R9_fiq";
4581 case 42: return "R10_fiq";
4582 case 43: return "R11_fiq";
4583 case 44: return "R12_fiq";
4584 case 45: return "SP_fiq";
4585 case 46: return "LR_fiq";
4586 case 48: return "LR_irq";
4587 case 49: return "SP_irq";
4588 case 50: return "LR_svc";
4589 case 51: return "SP_svc";
4590 case 52: return "LR_abt";
4591 case 53: return "SP_abt";
4592 case 54: return "LR_und";
4593 case 55: return "SP_und";
4594 case 60: return "LR_mon";
4595 case 61: return "SP_mon";
4596 case 62: return "ELR_hyp";
4597 case 63: return "SP_hyp";
4598 case 79: return "SPSR";
4599 case 110: return "SPSR_fiq";
4600 case 112: return "SPSR_irq";
4601 case 114: return "SPSR_svc";
4602 case 116: return "SPSR_abt";
4603 case 118: return "SPSR_und";
4604 case 124: return "SPSR_mon";
4605 case 126: return "SPSR_hyp";
4606 default: return NULL;
4607 }
4608}
4609
e797f7e0
MGD		 4610/* Return the name of the DMB/DSB option. */
4611static const char *
4612data_barrier_option (unsigned option)
4613{
4614 switch (option & 0xf)
4615 {
4616 case 0xf: return "sy";
4617 case 0xe: return "st";
4618 case 0xd: return "ld";
4619 case 0xb: return "ish";
4620 case 0xa: return "ishst";
4621 case 0x9: return "ishld";
4622 case 0x7: return "un";
4623 case 0x6: return "unst";
4624 case 0x5: return "nshld";
4625 case 0x3: return "osh";
4626 case 0x2: return "oshst";
4627 case 0x1: return "oshld";
4628 default: return NULL;
4629 }
4630}
4631
4a5329c6
ZW		 4632/* Print one ARM instruction from PC on INFO->STREAM. */
4633
4634static void
4635print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 4636{
6b5d3a4d 4637 const struct opcode32 *insn;
6a51a8a8 4638 void *stream = info->stream;
6b5d3a4d 4639 fprintf_ftype func = info->fprintf_func;
b0e28b39 4640 struct arm_private_data *private_data = info->private_data;
252b5132 4641
16980d0b
JB		 4642 if (print_insn_coprocessor (pc, info, given, FALSE))
4643 return;
4644
4645 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 4646 return;
4647
252b5132
RH		 4648 for (insn = arm_opcodes; insn->assembler; insn++)
4649 {
0313a2b8
NC		 4650 if ((given & insn->mask) != insn->value)
4651 continue;
823d2571
TG		 4652
4653 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 4654 continue;
4655
4656 /* Special case: an instruction with all bits set in the condition field
4657 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
4658 or by the catchall at the end of the table. */
4659 if ((given & 0xF0000000) != 0xF0000000
4660 || (insn->mask & 0xF0000000) == 0xF0000000
4661 || (insn->mask == 0 && insn->value == 0))
252b5132 4662 {
ff4a8d2b
NC		 4663 unsigned long u_reg = 16;
4664 unsigned long U_reg = 16;
ab8e2090 4665 bfd_boolean is_unpredictable = FALSE;
05413229 4666 signed long value_in_comment = 0;
6b5d3a4d 4667 const char *c;
b34976b6 4668
252b5132
RH		 4669 for (c = insn->assembler; *c; c++)
4670 {
4671 if (*c == '%')
4672 {
c1e26897
NC		 4673 bfd_boolean allow_unpredictable = FALSE;
4674
252b5132
RH		 4675 switch (*++c)
4676 {
4677 case '%':
4678 func (stream, "%%");
4679 break;
4680
4681 case 'a':
05413229 4682 value_in_comment = print_arm_address (pc, info, given);
62b3e311 4683 break;
252b5132 4684
62b3e311
PB		 4685 case 'P':
4686 /* Set P address bit and use normal address
4687 printing routine. */
c1e26897 4688 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 4689 break;
4690
c1e26897
NC		 4691 case 'S':
4692 allow_unpredictable = TRUE;
1a0670f3 4693 /* Fall through. */
252b5132
RH		 4694 case 's':
4695 if ((given & 0x004f0000) == 0x004f0000)
4696 {
58efb6c0 4697 /* PC relative with immediate offset. */
f8b960bc 4698 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 4699
aefd8a40
NC		 4700 if (PRE_BIT_SET)
4701 {
26d97720
NS		 4702 /* Elide positive zero offset. */
4703 if (offset || NEGATIVE_BIT_SET)
4704 func (stream, "[pc, #%s%d]\t; ",
d908c8af 4705 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 4706 else
26d97720
NS		 4707 func (stream, "[pc]\t; ");
4708 if (NEGATIVE_BIT_SET)
4709 offset = -offset;
aefd8a40
NC		 4710 info->print_address_func (offset + pc + 8, info);
4711 }
4712 else
4713 {
26d97720
NS		 4714 /* Always show the offset. */
4715 func (stream, "[pc], #%s%d",
d908c8af 4716 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 4717 if (! allow_unpredictable)
4718 is_unpredictable = TRUE;
aefd8a40 4719 }
252b5132
RH		 4720 }
4721 else
4722 {
fe56b6ce
NC		 4723 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
4724
b34976b6 4725 func (stream, "[%s",
252b5132 4726 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 4727
c1e26897 4728 if (PRE_BIT_SET)
252b5132 4729 {
c1e26897 4730 if (IMMEDIATE_BIT_SET)
252b5132 4731 {
26d97720
NS		 4732 /* Elide offset for non-writeback
4733 positive zero. */
4734 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
4735 || offset)
4736 func (stream, ", #%s%d",
4737 NEGATIVE_BIT_SET ? "-" : "", offset);
4738
4739 if (NEGATIVE_BIT_SET)
4740 offset = -offset;
945ee430 4741
fe56b6ce 4742 value_in_comment = offset;
252b5132 4743 }
945ee430 4744 else
ff4a8d2b
NC		 4745 {
4746 /* Register Offset or Register Pre-Indexed. */
4747 func (stream, ", %s%s",
4748 NEGATIVE_BIT_SET ? "-" : "",
4749 arm_regnames[given & 0xf]);
4750
4751 /* Writing back to the register that is the source/
4752 destination of the load/store is unpredictable. */
4753 if (! allow_unpredictable
4754 && WRITEBACK_BIT_SET
4755 && ((given & 0xf) == ((given >> 12) & 0xf)))
4756 is_unpredictable = TRUE;
4757 }
252b5132 4758
b34976b6 4759 func (stream, "]%s",
c1e26897 4760 WRITEBACK_BIT_SET ? "!" : "");
252b5132 4761 }
945ee430 4762 else
252b5132 4763 {
c1e26897 4764 if (IMMEDIATE_BIT_SET)
252b5132 4765 {
945ee430 4766 /* Immediate Post-indexed. */
aefd8a40 4767 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 4768 func (stream, "], #%s%d",
4769 NEGATIVE_BIT_SET ? "-" : "", offset);
4770 if (NEGATIVE_BIT_SET)
4771 offset = -offset;
fe56b6ce 4772 value_in_comment = offset;
252b5132 4773 }
945ee430 4774 else
ff4a8d2b
NC		 4775 {
4776 /* Register Post-indexed. */
4777 func (stream, "], %s%s",
4778 NEGATIVE_BIT_SET ? "-" : "",
4779 arm_regnames[given & 0xf]);
4780
4781 /* Writing back to the register that is the source/
4782 destination of the load/store is unpredictable. */
4783 if (! allow_unpredictable
4784 && (given & 0xf) == ((given >> 12) & 0xf))
4785 is_unpredictable = TRUE;
4786 }
c1e26897 4787
07a28fab
NC		 4788 if (! allow_unpredictable)
4789 {
4790 /* Writeback is automatically implied by post- addressing.
4791 Setting the W bit is unnecessary and ARM specify it as
4792 being unpredictable. */
4793 if (WRITEBACK_BIT_SET
4794 /* Specifying the PC register as the post-indexed
4795 registers is also unpredictable. */
ab8e2090
NC		 4796 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
4797 is_unpredictable = TRUE;
07a28fab 4798 }
252b5132
RH		 4799 }
4800 }
4801 break;
b34976b6 4802
252b5132 4803 case 'b':
6b5d3a4d 4804 {
f8b960bc 4805 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
05413229 4806 info->print_address_func (disp * 4 + pc + 8, info);
6b5d3a4d 4807 }
252b5132
RH		 4808 break;
4809
4810 case 'c':
c22aaad1
PB		 4811 if (((given >> 28) & 0xf) != 0xe)
4812 func (stream, "%s",
4813 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 4814 break;
4815
4816 case 'm':
4817 {
4818 int started = 0;
4819 int reg;
4820
4821 func (stream, "{");
4822 for (reg = 0; reg < 16; reg++)
4823 if ((given & (1 << reg)) != 0)
4824 {
4825 if (started)
4826 func (stream, ", ");
4827 started = 1;
4828 func (stream, "%s", arm_regnames[reg]);
4829 }
4830 func (stream, "}");
ab8e2090
NC		 4831 if (! started)
4832 is_unpredictable = TRUE;
252b5132
RH		 4833 }
4834 break;
4835
37b37b2d 4836 case 'q':
78c66db8 4837 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 4838 break;
4839
252b5132
RH		 4840 case 'o':
4841 if ((given & 0x02000000) != 0)
4842 {
a415b1cd
JB		 4843 unsigned int rotate = (given & 0xf00) >> 7;
4844 unsigned int immed = (given & 0xff);
4845 unsigned int a, i;
4846
4847 a = (((immed << (32 - rotate))
4848 | (immed >> rotate)) & 0xffffffff);
4849 /* If there is another encoding with smaller rotate,
4850 the rotate should be specified directly. */
4851 for (i = 0; i < 32; i += 2)
4852 if ((a << i | a >> (32 - i)) <= 0xff)
4853 break;
4854
4855 if (i != rotate)
4856 func (stream, "#%d, %d", immed, rotate);
4857 else
4858 func (stream, "#%d", a);
4859 value_in_comment = a;
252b5132
RH		 4860 }
4861 else
78c66db8 4862 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 4863 break;
4864
4865 case 'p':
4866 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 4867 {
823d2571
TG		 4868 arm_feature_set arm_ext_v6 =
4869 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
4870
aefd8a40
NC		 4871 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
4872 mechanism for setting PSR flag bits. They are
4873 obsolete in V6 onwards. */
823d2571
TG		 4874 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
4875 arm_ext_v6))
aefd8a40 4876 func (stream, "p");
4ab90a7a
AV		 4877 else
4878 is_unpredictable = TRUE;
aefd8a40 4879 }
252b5132
RH		 4880 break;
4881
4882 case 't':
4883 if ((given & 0x01200000) == 0x00200000)
4884 func (stream, "t");
4885 break;
4886
252b5132 4887 case 'A':
05413229
NC		 4888 {
4889 int offset = given & 0xff;
f02232aa 4890
05413229 4891 value_in_comment = offset * 4;
c1e26897 4892 if (NEGATIVE_BIT_SET)
05413229 4893 value_in_comment = - value_in_comment;
f02232aa 4894
05413229 4895 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 4896
c1e26897 4897 if (PRE_BIT_SET)
05413229
NC		 4898 {
4899 if (offset)
fe56b6ce 4900 func (stream, ", #%d]%s",
d908c8af 4901 (int) value_in_comment,
c1e26897 4902 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 4903 else
4904 func (stream, "]");
4905 }
4906 else
4907 {
4908 func (stream, "]");
f02232aa 4909
c1e26897 4910 if (WRITEBACK_BIT_SET)
05413229
NC		 4911 {
4912 if (offset)
d908c8af 4913 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 4914 }
4915 else
fe56b6ce 4916 {
d908c8af 4917 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 4918 value_in_comment = offset;
4919 }
05413229
NC		 4920 }
4921 }
252b5132
RH		 4922 break;
4923
077b8428
NC		 4924 case 'B':
4925 /* Print ARM V5 BLX(1) address: pc+25 bits. */
4926 {
4927 bfd_vma address;
4928 bfd_vma offset = 0;
b34976b6 4929
c1e26897 4930 if (! NEGATIVE_BIT_SET)
077b8428
NC		 4931 /* Is signed, hi bits should be ones. */
4932 offset = (-1) ^ 0x00ffffff;
4933
4934 /* Offset is (SignExtend(offset field)<<2). */
4935 offset += given & 0x00ffffff;
4936 offset <<= 2;
4937 address = offset + pc + 8;
b34976b6 4938
8f06b2d8
PB		 4939 if (given & 0x01000000)
4940 /* H bit allows addressing to 2-byte boundaries. */
4941 address += 2;
b1ee46c5 4942
8f06b2d8 4943 info->print_address_func (address, info);
b1ee46c5 4944 }
b1ee46c5
AH		 4945 break;
4946
252b5132 4947 case 'C':
90ec0d68
MGD		 4948 if ((given & 0x02000200) == 0x200)
4949 {
4950 const char * name;
4951 unsigned sysm = (given & 0x004f0000) >> 16;
4952
4953 sysm |= (given & 0x300) >> 4;
4954 name = banked_regname (sysm);
4955
4956 if (name != NULL)
4957 func (stream, "%s", name);
4958 else
d908c8af 4959 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 4960 }
4961 else
4962 {
43e65147 4963 func (stream, "%cPSR_",
90ec0d68
MGD		 4964 (given & 0x00400000) ? 'S' : 'C');
4965 if (given & 0x80000)
4966 func (stream, "f");
4967 if (given & 0x40000)
4968 func (stream, "s");
4969 if (given & 0x20000)
4970 func (stream, "x");
4971 if (given & 0x10000)
4972 func (stream, "c");
4973 }
252b5132
RH		 4974 break;
4975
62b3e311 4976 case 'U':
43e65147 4977 if ((given & 0xf0) == 0x60)
62b3e311 4978 {
52e7f43d
RE		 4979 switch (given & 0xf)
4980 {
4981 case 0xf: func (stream, "sy"); break;
4982 default:
4983 func (stream, "#%d", (int) given & 0xf);
4984 break;
4985 }
43e65147
L		 4986 }
4987 else
52e7f43d 4988 {
e797f7e0
MGD		 4989 const char * opt = data_barrier_option (given & 0xf);
4990 if (opt != NULL)
4991 func (stream, "%s", opt);
4992 else
52e7f43d 4993 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 4994 }
4995 break;
4996
b34976b6 4997 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 4998 case '5': case '6': case '7': case '8': case '9':
4999 {
16980d0b
JB		 5000 int width;
5001 unsigned long value;
252b5132 5002
16980d0b 5003 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 5004
252b5132
RH		 5005 switch (*c)
5006 {
ab8e2090
NC		 5007 case 'R':
5008 if (value == 15)
5009 is_unpredictable = TRUE;
5010 /* Fall through. */
16980d0b 5011 case 'r':
9eb6c0f1
MGD		 5012 case 'T':
5013 /* We want register + 1 when decoding T. */
5014 if (*c == 'T')
5015 ++value;
5016
ff4a8d2b
NC		 5017 if (c[1] == 'u')
5018 {
5019 /* Eat the 'u' character. */
5020 ++ c;
5021
5022 if (u_reg == value)
5023 is_unpredictable = TRUE;
5024 u_reg = value;
5025 }
5026 if (c[1] == 'U')
5027 {
5028 /* Eat the 'U' character. */
5029 ++ c;
5030
5031 if (U_reg == value)
5032 is_unpredictable = TRUE;
5033 U_reg = value;
5034 }
16980d0b
JB		 5035 func (stream, "%s", arm_regnames[value]);
5036 break;
5037 case 'd':
5038 func (stream, "%ld", value);
05413229 5039 value_in_comment = value;
16980d0b
JB		 5040 break;
5041 case 'b':
5042 func (stream, "%ld", value * 8);
05413229 5043 value_in_comment = value * 8;
16980d0b
JB		 5044 break;
5045 case 'W':
5046 func (stream, "%ld", value + 1);
05413229 5047 value_in_comment = value + 1;
16980d0b
JB		 5048 break;
5049 case 'x':
5050 func (stream, "0x%08lx", value);
5051
5052 /* Some SWI instructions have special
5053 meanings. */
5054 if ((given & 0x0fffffff) == 0x0FF00000)
5055 func (stream, "\t; IMB");
5056 else if ((given & 0x0fffffff) == 0x0FF00001)
5057 func (stream, "\t; IMBRange");
5058 break;
5059 case 'X':
5060 func (stream, "%01lx", value & 0xf);
05413229 5061 value_in_comment = value;
252b5132
RH		 5062 break;
5063 case '`':
5064 c++;
16980d0b 5065 if (value == 0)
252b5132
RH		 5066 func (stream, "%c", *c);
5067 break;
5068 case '\'':
5069 c++;
16980d0b 5070 if (value == ((1ul << width) - 1))
252b5132
RH		 5071 func (stream, "%c", *c);
5072 break;
5073 case '?':
fe56b6ce 5074 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 5075 c += 1 << width;
252b5132
RH		 5076 break;
5077 default:
5078 abort ();
5079 }
5080 break;
5081
0dd132b6
NC		 5082 case 'e':
5083 {
5084 int imm;
5085
5086 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
5087 func (stream, "%d", imm);
fe56b6ce 5088 value_in_comment = imm;
0dd132b6
NC		 5089 }
5090 break;
5091
0a003adc
ZW		 5092 case 'E':
5093 /* LSB and WIDTH fields of BFI or BFC. The machine-
5094 language instruction encodes LSB and MSB. */
5095 {
5096 long msb = (given & 0x001f0000) >> 16;
5097 long lsb = (given & 0x00000f80) >> 7;
91d6fa6a 5098 long w = msb - lsb + 1;
fe56b6ce 5099
91d6fa6a
NC		 5100 if (w > 0)
5101 func (stream, "#%lu, #%lu", lsb, w);
0a003adc
ZW		 5102 else
5103 func (stream, "(invalid: %lu:%lu)", lsb, msb);
5104 }
5105 break;
5106
90ec0d68
MGD		 5107 case 'R':
5108 /* Get the PSR/banked register name. */
5109 {
5110 const char * name;
5111 unsigned sysm = (given & 0x004f0000) >> 16;
5112
5113 sysm |= (given & 0x300) >> 4;
5114 name = banked_regname (sysm);
5115
5116 if (name != NULL)
5117 func (stream, "%s", name);
5118 else
d908c8af 5119 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 5120 }
5121 break;
5122
0a003adc
ZW		 5123 case 'V':
5124 /* 16-bit unsigned immediate from a MOVT or MOVW
5125 instruction, encoded in bits 0:11 and 15:19. */
5126 {
5127 long hi = (given & 0x000f0000) >> 4;
5128 long lo = (given & 0x00000fff);
5129 long imm16 = hi | lo;
fe56b6ce
NC		 5130
5131 func (stream, "#%lu", imm16);
5132 value_in_comment = imm16;
0a003adc
ZW		 5133 }
5134 break;
5135
252b5132
RH		 5136 default:
5137 abort ();
5138 }
5139 }
5140 }
5141 else
5142 func (stream, "%c", *c);
5143 }
05413229
NC		 5144
5145 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 5146 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 5147
5148 if (is_unpredictable)
5149 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 5150
4a5329c6 5151 return;
252b5132
RH		 5152 }
5153 }
5154 abort ();
5155}
5156
4a5329c6 5157/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 5158
4a5329c6
ZW		 5159static void
5160print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 5161{
6b5d3a4d 5162 const struct opcode16 *insn;
6a51a8a8
AM		 5163 void *stream = info->stream;
5164 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 5165
5166 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 5167 if ((given & insn->mask) == insn->value)
5168 {
05413229 5169 signed long value_in_comment = 0;
6b5d3a4d 5170 const char *c = insn->assembler;
05413229 5171
c19d1205
ZW		 5172 for (; *c; c++)
5173 {
5174 int domaskpc = 0;
5175 int domasklr = 0;
5176
5177 if (*c != '%')
5178 {
5179 func (stream, "%c", *c);
5180 continue;
5181 }
252b5132 5182
c19d1205
ZW		 5183 switch (*++c)
5184 {
5185 case '%':
5186 func (stream, "%%");
5187 break;
b34976b6 5188
c22aaad1
PB		 5189 case 'c':
5190 if (ifthen_state)
5191 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5192 break;
5193
5194 case 'C':
5195 if (ifthen_state)
5196 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5197 else
5198 func (stream, "s");
5199 break;
5200
5201 case 'I':
5202 {
5203 unsigned int tmp;
5204
5205 ifthen_next_state = given & 0xff;
5206 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
5207 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
5208 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
5209 }
5210 break;
5211
5212 case 'x':
5213 if (ifthen_next_state)
5214 func (stream, "\t; unpredictable branch in IT block\n");
5215 break;
5216
5217 case 'X':
5218 if (ifthen_state)
5219 func (stream, "\t; unpredictable <IT:%s>",
5220 arm_conditional[IFTHEN_COND]);
5221 break;
5222
c19d1205
ZW		 5223 case 'S':
5224 {
5225 long reg;
5226
5227 reg = (given >> 3) & 0x7;
5228 if (given & (1 << 6))
5229 reg += 8;
4f3c3dbb 5230
c19d1205
ZW		 5231 func (stream, "%s", arm_regnames[reg]);
5232 }
5233 break;
baf0cc5e 5234
c19d1205 5235 case 'D':
4f3c3dbb 5236 {
c19d1205
ZW		 5237 long reg;
5238
5239 reg = given & 0x7;
5240 if (given & (1 << 7))
5241 reg += 8;
5242
5243 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 5244 }
c19d1205
ZW		 5245 break;
5246
5247 case 'N':
5248 if (given & (1 << 8))
5249 domasklr = 1;
5250 /* Fall through. */
5251 case 'O':
5252 if (*c == 'O' && (given & (1 << 8)))
5253 domaskpc = 1;
5254 /* Fall through. */
5255 case 'M':
5256 {
5257 int started = 0;
5258 int reg;
5259
5260 func (stream, "{");
5261
5262 /* It would be nice if we could spot
5263 ranges, and generate the rS-rE format: */
5264 for (reg = 0; (reg < 8); reg++)
5265 if ((given & (1 << reg)) != 0)
5266 {
5267 if (started)
5268 func (stream, ", ");
5269 started = 1;
5270 func (stream, "%s", arm_regnames[reg]);
5271 }
5272
5273 if (domasklr)
5274 {
5275 if (started)
5276 func (stream, ", ");
5277 started = 1;
d908c8af 5278 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 5279 }
5280
5281 if (domaskpc)
5282 {
5283 if (started)
5284 func (stream, ", ");
d908c8af 5285 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 5286 }
5287
5288 func (stream, "}");
5289 }
5290 break;
5291
4547cb56
NC		 5292 case 'W':
5293 /* Print writeback indicator for a LDMIA. We are doing a
5294 writeback if the base register is not in the register
5295 mask. */
5296 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
5297 func (stream, "!");
5298 break;
5299
c19d1205
ZW		 5300 case 'b':
5301 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
5302 {
5303 bfd_vma address = (pc + 4
5304 + ((given & 0x00f8) >> 2)
5305 + ((given & 0x0200) >> 3));
5306 info->print_address_func (address, info);
5307 }
5308 break;
5309
5310 case 's':
5311 /* Right shift immediate -- bits 6..10; 1-31 print
5312 as themselves, 0 prints as 32. */
5313 {
5314 long imm = (given & 0x07c0) >> 6;
5315 if (imm == 0)
5316 imm = 32;
0fd3a477 5317 func (stream, "#%ld", imm);
c19d1205
ZW		 5318 }
5319 break;
5320
5321 case '0': case '1': case '2': case '3': case '4':
5322 case '5': case '6': case '7': case '8': case '9':
5323 {
5324 int bitstart = *c++ - '0';
5325 int bitend = 0;
5326
5327 while (*c >= '0' && *c <= '9')
5328 bitstart = (bitstart * 10) + *c++ - '0';
5329
5330 switch (*c)
5331 {
5332 case '-':
5333 {
f8b960bc 5334 bfd_vma reg;
c19d1205
ZW		 5335
5336 c++;
5337 while (*c >= '0' && *c <= '9')
5338 bitend = (bitend * 10) + *c++ - '0';
5339 if (!bitend)
5340 abort ();
5341 reg = given >> bitstart;
5342 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 5343
c19d1205
ZW		 5344 switch (*c)
5345 {
5346 case 'r':
5347 func (stream, "%s", arm_regnames[reg]);
5348 break;
5349
5350 case 'd':
d908c8af 5351 func (stream, "%ld", (long) reg);
05413229 5352 value_in_comment = reg;
c19d1205
ZW		 5353 break;
5354
5355 case 'H':
d908c8af 5356 func (stream, "%ld", (long) (reg << 1));
05413229 5357 value_in_comment = reg << 1;
c19d1205
ZW		 5358 break;
5359
5360 case 'W':
d908c8af 5361 func (stream, "%ld", (long) (reg << 2));
05413229 5362 value_in_comment = reg << 2;
c19d1205
ZW		 5363 break;
5364
5365 case 'a':
5366 /* PC-relative address -- the bottom two
5367 bits of the address are dropped
5368 before the calculation. */
5369 info->print_address_func
5370 (((pc + 4) & ~3) + (reg << 2), info);
05413229 5371 value_in_comment = 0;
c19d1205
ZW		 5372 break;
5373
5374 case 'x':
d908c8af 5375 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 5376 break;
5377
c19d1205
ZW		 5378 case 'B':
5379 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6b5d3a4d 5380 info->print_address_func (reg * 2 + pc + 4, info);
05413229 5381 value_in_comment = 0;
c19d1205
ZW		 5382 break;
5383
5384 case 'c':
c22aaad1 5385 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 5386 break;
5387
5388 default:
5389 abort ();
5390 }
5391 }
5392 break;
5393
5394 case '\'':
5395 c++;
5396 if ((given & (1 << bitstart)) != 0)
5397 func (stream, "%c", *c);
5398 break;
5399
5400 case '?':
5401 ++c;
5402 if ((given & (1 << bitstart)) != 0)
5403 func (stream, "%c", *c++);
5404 else
5405 func (stream, "%c", *++c);
5406 break;
5407
5408 default:
5409 abort ();
5410 }
5411 }
5412 break;
5413
5414 default:
5415 abort ();
5416 }
5417 }
05413229
NC		 5418
5419 if (value_in_comment > 32 || value_in_comment < -16)
5420 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 5421 return;
c19d1205
ZW		 5422 }
5423
5424 /* No match. */
5425 abort ();
5426}
5427
62b3e311 5428/* Return the name of an V7M special register. */
fe56b6ce 5429
62b3e311
PB		 5430static const char *
5431psr_name (int regno)
5432{
5433 switch (regno)
5434 {
1a336194
TP		 5435 case 0x0: return "APSR";
5436 case 0x1: return "IAPSR";
5437 case 0x2: return "EAPSR";
5438 case 0x3: return "PSR";
5439 case 0x5: return "IPSR";
5440 case 0x6: return "EPSR";
5441 case 0x7: return "IEPSR";
5442 case 0x8: return "MSP";
5443 case 0x9: return "PSP";
5444 case 0xa: return "MSPLIM";
5445 case 0xb: return "PSPLIM";
5446 case 0x10: return "PRIMASK";
5447 case 0x11: return "BASEPRI";
5448 case 0x12: return "BASEPRI_MAX";
5449 case 0x13: return "FAULTMASK";
5450 case 0x14: return "CONTROL";
16a1fa25
TP		 5451 case 0x88: return "MSP_NS";
5452 case 0x89: return "PSP_NS";
1a336194
TP		 5453 case 0x8a: return "MSPLIM_NS";
5454 case 0x8b: return "PSPLIM_NS";
5455 case 0x90: return "PRIMASK_NS";
5456 case 0x91: return "BASEPRI_NS";
5457 case 0x93: return "FAULTMASK_NS";
5458 case 0x94: return "CONTROL_NS";
5459 case 0x98: return "SP_NS";
62b3e311
PB		 5460 default: return "<unknown>";
5461 }
5462}
5463
4a5329c6
ZW		 5464/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
5465
5466static void
5467print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 5468{
6b5d3a4d 5469 const struct opcode32 *insn;
c19d1205
ZW		 5470 void *stream = info->stream;
5471 fprintf_ftype func = info->fprintf_func;
5472
16980d0b
JB		 5473 if (print_insn_coprocessor (pc, info, given, TRUE))
5474 return;
5475
5476 if (print_insn_neon (info, given, TRUE))
8f06b2d8
PB		 5477 return;
5478
c19d1205
ZW		 5479 for (insn = thumb32_opcodes; insn->assembler; insn++)
5480 if ((given & insn->mask) == insn->value)
5481 {
ff4a8d2b 5482 bfd_boolean is_unpredictable = FALSE;
05413229 5483 signed long value_in_comment = 0;
6b5d3a4d 5484 const char *c = insn->assembler;
05413229 5485
c19d1205
ZW		 5486 for (; *c; c++)
5487 {
5488 if (*c != '%')
5489 {
5490 func (stream, "%c", *c);
5491 continue;
5492 }
5493
5494 switch (*++c)
5495 {
5496 case '%':
5497 func (stream, "%%");
5498 break;
5499
c22aaad1
PB		 5500 case 'c':
5501 if (ifthen_state)
5502 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5503 break;
5504
5505 case 'x':
5506 if (ifthen_next_state)
5507 func (stream, "\t; unpredictable branch in IT block\n");
5508 break;
5509
5510 case 'X':
5511 if (ifthen_state)
5512 func (stream, "\t; unpredictable <IT:%s>",
5513 arm_conditional[IFTHEN_COND]);
5514 break;
5515
c19d1205
ZW		 5516 case 'I':
5517 {
5518 unsigned int imm12 = 0;
fe56b6ce 5519
c19d1205
ZW		 5520 imm12 |= (given & 0x000000ffu);
5521 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 5522 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 5523 func (stream, "#%u", imm12);
5524 value_in_comment = imm12;
c19d1205
ZW		 5525 }
5526 break;
5527
5528 case 'M':
5529 {
5530 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 5531
c19d1205
ZW		 5532 bits |= (given & 0x000000ffu);
5533 bits |= (given & 0x00007000u) >> 4;
5534 bits |= (given & 0x04000000u) >> 15;
5535 imm8 = (bits & 0x0ff);
5536 mod = (bits & 0xf00) >> 8;
5537 switch (mod)
5538 {
5539 case 0: imm = imm8; break;
c1e26897
NC		 5540 case 1: imm = ((imm8 << 16) | imm8); break;
5541 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
5542 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 5543 default:
5544 mod = (bits & 0xf80) >> 7;
5545 imm8 = (bits & 0x07f) | 0x80;
5546 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
5547 }
fe56b6ce
NC		 5548 func (stream, "#%u", imm);
5549 value_in_comment = imm;
c19d1205
ZW		 5550 }
5551 break;
43e65147 5552
c19d1205
ZW		 5553 case 'J':
5554 {
5555 unsigned int imm = 0;
fe56b6ce 5556
c19d1205
ZW		 5557 imm |= (given & 0x000000ffu);
5558 imm |= (given & 0x00007000u) >> 4;
5559 imm |= (given & 0x04000000u) >> 15;
5560 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 5561 func (stream, "#%u", imm);
5562 value_in_comment = imm;
c19d1205
ZW		 5563 }
5564 break;
5565
5566 case 'K':
5567 {
5568 unsigned int imm = 0;
fe56b6ce 5569
c19d1205
ZW		 5570 imm |= (given & 0x000f0000u) >> 16;
5571 imm |= (given & 0x00000ff0u) >> 0;
5572 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 5573 func (stream, "#%u", imm);
5574 value_in_comment = imm;
c19d1205
ZW		 5575 }
5576 break;
5577
74db7efb
NC		 5578 case 'H':
5579 {
5580 unsigned int imm = 0;
5581
5582 imm |= (given & 0x000f0000u) >> 4;
5583 imm |= (given & 0x00000fffu) >> 0;
5584 func (stream, "#%u", imm);
5585 value_in_comment = imm;
5586 }
5587 break;
5588
90ec0d68
MGD		 5589 case 'V':
5590 {
5591 unsigned int imm = 0;
5592
5593 imm |= (given & 0x00000fffu);
5594 imm |= (given & 0x000f0000u) >> 4;
5595 func (stream, "#%u", imm);
5596 value_in_comment = imm;
5597 }
5598 break;
5599
c19d1205
ZW		 5600 case 'S':
5601 {
5602 unsigned int reg = (given & 0x0000000fu);
5603 unsigned int stp = (given & 0x00000030u) >> 4;
5604 unsigned int imm = 0;
5605 imm |= (given & 0x000000c0u) >> 6;
5606 imm |= (given & 0x00007000u) >> 10;
5607
5608 func (stream, "%s", arm_regnames[reg]);
5609 switch (stp)
5610 {
5611 case 0:
5612 if (imm > 0)
5613 func (stream, ", lsl #%u", imm);
5614 break;
5615
5616 case 1:
5617 if (imm == 0)
5618 imm = 32;
5619 func (stream, ", lsr #%u", imm);
5620 break;
5621
5622 case 2:
5623 if (imm == 0)
5624 imm = 32;
5625 func (stream, ", asr #%u", imm);
5626 break;
5627
5628 case 3:
5629 if (imm == 0)
5630 func (stream, ", rrx");
5631 else
5632 func (stream, ", ror #%u", imm);
5633 }
5634 }
5635 break;
5636
5637 case 'a':
5638 {
5639 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 5640 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 5641 unsigned int op = (given & 0x00000f00) >> 8;
5642 unsigned int i12 = (given & 0x00000fff);
5643 unsigned int i8 = (given & 0x000000ff);
5644 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 5645 bfd_vma offset = 0;
c19d1205
ZW		 5646
5647 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 5648 if (U) /* 12-bit positive immediate offset. */
5649 {
5650 offset = i12;
5651 if (Rn != 15)
5652 value_in_comment = offset;
5653 }
5654 else if (Rn == 15) /* 12-bit negative immediate offset. */
5655 offset = - (int) i12;
5656 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 5657 {
5658 unsigned int Rm = (i8 & 0x0f);
5659 unsigned int sh = (i8 & 0x30) >> 4;
05413229 5660
c19d1205
ZW		 5661 func (stream, ", %s", arm_regnames[Rm]);
5662 if (sh)
5663 func (stream, ", lsl #%u", sh);
5664 func (stream, "]");
5665 break;
5666 }
5667 else switch (op)
5668 {
05413229 5669 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 5670 offset = i8;
5671 break;
5672
05413229 5673 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 5674 offset = -i8;
5675 break;
5676
05413229 5677 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 5678 offset = i8;
5679 writeback = TRUE;
5680 break;
5681
05413229 5682 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 5683 offset = -i8;
5684 writeback = TRUE;
5685 break;
5686
05413229 5687 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 5688 offset = i8;
5689 postind = TRUE;
5690 break;
5691
05413229 5692 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 5693 offset = -i8;
5694 postind = TRUE;
5695 break;
5696
5697 default:
5698 func (stream, ", <undefined>]");
5699 goto skip;
5700 }
5701
5702 if (postind)
d908c8af 5703 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 5704 else
5705 {
5706 if (offset)
d908c8af 5707 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 5708 func (stream, writeback ? "]!" : "]");
5709 }
5710
5711 if (Rn == 15)
5712 {
5713 func (stream, "\t; ");
5714 info->print_address_func (((pc + 4) & ~3) + offset, info);
5715 }
5716 }
5717 skip:
5718 break;
5719
5720 case 'A':
5721 {
c1e26897
NC		 5722 unsigned int U = ! NEGATIVE_BIT_SET;
5723 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 5724 unsigned int Rn = (given & 0x000f0000) >> 16;
5725 unsigned int off = (given & 0x000000ff);
5726
5727 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 5728
5729 if (PRE_BIT_SET)
c19d1205
ZW		 5730 {
5731 if (off || !U)
05413229
NC		 5732 {
5733 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
fe50e98c 5734 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 5735 }
c19d1205
ZW		 5736 func (stream, "]");
5737 if (W)
5738 func (stream, "!");
5739 }
5740 else
5741 {
5742 func (stream, "], ");
5743 if (W)
05413229
NC		 5744 {
5745 func (stream, "#%c%u", U ? '+' : '-', off * 4);
fe50e98c 5746 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 5747 }
c19d1205 5748 else
fe56b6ce
NC		 5749 {
5750 func (stream, "{%u}", off);
5751 value_in_comment = off;
5752 }
c19d1205
ZW		 5753 }
5754 }
5755 break;
5756
5757 case 'w':
5758 {
5759 unsigned int Sbit = (given & 0x01000000) >> 24;
5760 unsigned int type = (given & 0x00600000) >> 21;
05413229 5761
c19d1205
ZW		 5762 switch (type)
5763 {
5764 case 0: func (stream, Sbit ? "sb" : "b"); break;
5765 case 1: func (stream, Sbit ? "sh" : "h"); break;
5766 case 2:
5767 if (Sbit)
5768 func (stream, "??");
5769 break;
5770 case 3:
5771 func (stream, "??");
5772 break;
5773 }
5774 }
5775 break;
5776
5777 case 'm':
5778 {
5779 int started = 0;
5780 int reg;
5781
5782 func (stream, "{");
5783 for (reg = 0; reg < 16; reg++)
5784 if ((given & (1 << reg)) != 0)
5785 {
5786 if (started)
5787 func (stream, ", ");
5788 started = 1;
5789 func (stream, "%s", arm_regnames[reg]);
5790 }
5791 func (stream, "}");
5792 }
5793 break;
5794
5795 case 'E':
5796 {
5797 unsigned int msb = (given & 0x0000001f);
5798 unsigned int lsb = 0;
fe56b6ce 5799
c19d1205
ZW		 5800 lsb |= (given & 0x000000c0u) >> 6;
5801 lsb |= (given & 0x00007000u) >> 10;
5802 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
5803 }
5804 break;
5805
5806 case 'F':
5807 {
5808 unsigned int width = (given & 0x0000001f) + 1;
5809 unsigned int lsb = 0;
fe56b6ce 5810
c19d1205
ZW		 5811 lsb |= (given & 0x000000c0u) >> 6;
5812 lsb |= (given & 0x00007000u) >> 10;
5813 func (stream, "#%u, #%u", lsb, width);
5814 }
5815 break;
5816
5817 case 'b':
5818 {
5819 unsigned int S = (given & 0x04000000u) >> 26;
5820 unsigned int J1 = (given & 0x00002000u) >> 13;
5821 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 5822 bfd_vma offset = 0;
c19d1205
ZW		 5823
5824 offset |= !S << 20;
5825 offset |= J2 << 19;
5826 offset |= J1 << 18;
5827 offset |= (given & 0x003f0000) >> 4;
5828 offset |= (given & 0x000007ff) << 1;
5829 offset -= (1 << 20);
5830
5831 info->print_address_func (pc + 4 + offset, info);
5832 }
5833 break;
5834
5835 case 'B':
5836 {
5837 unsigned int S = (given & 0x04000000u) >> 26;
5838 unsigned int I1 = (given & 0x00002000u) >> 13;
5839 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 5840 bfd_vma offset = 0;
c19d1205
ZW		 5841
5842 offset |= !S << 24;
5843 offset |= !(I1 ^ S) << 23;
5844 offset |= !(I2 ^ S) << 22;
5845 offset |= (given & 0x03ff0000u) >> 4;
5846 offset |= (given & 0x000007ffu) << 1;
5847 offset -= (1 << 24);
36b0c57d 5848 offset += pc + 4;
c19d1205 5849
36b0c57d
PB		 5850 /* BLX target addresses are always word aligned. */
5851 if ((given & 0x00001000u) == 0)
5852 offset &= ~2u;
5853
5854 info->print_address_func (offset, info);
c19d1205
ZW		 5855 }
5856 break;
5857
5858 case 's':
5859 {
5860 unsigned int shift = 0;
fe56b6ce 5861
c19d1205
ZW		 5862 shift |= (given & 0x000000c0u) >> 6;
5863 shift |= (given & 0x00007000u) >> 10;
c1e26897 5864 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 5865 func (stream, ", asr #%u", shift);
5866 else if (shift)
5867 func (stream, ", lsl #%u", shift);
5868 /* else print nothing - lsl #0 */
5869 }
5870 break;
5871
5872 case 'R':
5873 {
5874 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 5875
c19d1205
ZW		 5876 if (rot)
5877 func (stream, ", ror #%u", rot * 8);
5878 }
5879 break;
5880
62b3e311 5881 case 'U':
43e65147 5882 if ((given & 0xf0) == 0x60)
62b3e311 5883 {
52e7f43d
RE		 5884 switch (given & 0xf)
5885 {
5886 case 0xf: func (stream, "sy"); break;
5887 default:
5888 func (stream, "#%d", (int) given & 0xf);
5889 break;
5890 }
62b3e311 5891 }
43e65147 5892 else
52e7f43d 5893 {
e797f7e0
MGD		 5894 const char * opt = data_barrier_option (given & 0xf);
5895 if (opt != NULL)
5896 func (stream, "%s", opt);
5897 else
5898 func (stream, "#%d", (int) given & 0xf);
52e7f43d 5899 }
62b3e311
PB		 5900 break;
5901
5902 case 'C':
5903 if ((given & 0xff) == 0)
5904 {
5905 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
5906 if (given & 0x800)
5907 func (stream, "f");
5908 if (given & 0x400)
5909 func (stream, "s");
5910 if (given & 0x200)
5911 func (stream, "x");
5912 if (given & 0x100)
5913 func (stream, "c");
5914 }
90ec0d68
MGD		 5915 else if ((given & 0x20) == 0x20)
5916 {
5917 char const* name;
5918 unsigned sysm = (given & 0xf00) >> 8;
5919
5920 sysm |= (given & 0x30);
5921 sysm |= (given & 0x00100000) >> 14;
5922 name = banked_regname (sysm);
43e65147 5923
90ec0d68
MGD		 5924 if (name != NULL)
5925 func (stream, "%s", name);
5926 else
d908c8af 5927 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 5928 }
62b3e311
PB		 5929 else
5930 {
d908c8af 5931 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 5932 }
5933 break;
5934
5935 case 'D':
90ec0d68
MGD		 5936 if (((given & 0xff) == 0)
5937 || ((given & 0x20) == 0x20))
5938 {
5939 char const* name;
5940 unsigned sm = (given & 0xf0000) >> 16;
5941
5942 sm |= (given & 0x30);
5943 sm |= (given & 0x00100000) >> 14;
5944 name = banked_regname (sm);
5945
5946 if (name != NULL)
5947 func (stream, "%s", name);
5948 else
d908c8af 5949 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 5950 }
62b3e311 5951 else
d908c8af 5952 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 5953 break;
5954
c19d1205
ZW		 5955 case '0': case '1': case '2': case '3': case '4':
5956 case '5': case '6': case '7': case '8': case '9':
5957 {
16980d0b
JB		 5958 int width;
5959 unsigned long val;
c19d1205 5960
16980d0b 5961 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 5962
c19d1205
ZW		 5963 switch (*c)
5964 {
05413229
NC		 5965 case 'd':
5966 func (stream, "%lu", val);
5967 value_in_comment = val;
5968 break;
ff4a8d2b 5969
f0fba320
RL		 5970 case 'D':
5971 func (stream, "%lu", val + 1);
5972 value_in_comment = val + 1;
5973 break;
5974
05413229
NC		 5975 case 'W':
5976 func (stream, "%lu", val * 4);
5977 value_in_comment = val * 4;
5978 break;
ff4a8d2b 5979
dd5181d5
KT		 5980 case 'S':
5981 if (val == 13)
5982 is_unpredictable = TRUE;
5983 /* Fall through. */
ff4a8d2b
NC		 5984 case 'R':
5985 if (val == 15)
5986 is_unpredictable = TRUE;
5987 /* Fall through. */
5988 case 'r':
5989 func (stream, "%s", arm_regnames[val]);
5990 break;
c19d1205
ZW		 5991
5992 case 'c':
c22aaad1 5993 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 5994 break;
5995
5996 case '\'':
c19d1205 5997 c++;
16980d0b
JB		 5998 if (val == ((1ul << width) - 1))
5999 func (stream, "%c", *c);
c19d1205 6000 break;
43e65147 6001
c19d1205 6002 case '`':
c19d1205 6003 c++;
16980d0b
JB		 6004 if (val == 0)
6005 func (stream, "%c", *c);
c19d1205
ZW		 6006 break;
6007
6008 case '?':
fe56b6ce 6009 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 6010 c += 1 << width;
c19d1205 6011 break;
43e65147 6012
0bb027fd
RR		 6013 case 'x':
6014 func (stream, "0x%lx", val & 0xffffffffUL);
6015 break;
c19d1205
ZW		 6016
6017 default:
6018 abort ();
6019 }
6020 }
6021 break;
6022
32a94698
NC		 6023 case 'L':
6024 /* PR binutils/12534
6025 If we have a PC relative offset in an LDRD or STRD
6026 instructions then display the decoded address. */
6027 if (((given >> 16) & 0xf) == 0xf)
6028 {
6029 bfd_vma offset = (given & 0xff) * 4;
6030
6031 if ((given & (1 << 23)) == 0)
6032 offset = - offset;
6033 func (stream, "\t; ");
6034 info->print_address_func ((pc & ~3) + 4 + offset, info);
6035 }
6036 break;
6037
c19d1205
ZW		 6038 default:
6039 abort ();
6040 }
6041 }
05413229
NC		 6042
6043 if (value_in_comment > 32 || value_in_comment < -16)
6044 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 6045
6046 if (is_unpredictable)
6047 func (stream, UNPREDICTABLE_INSTRUCTION);
6048
4a5329c6 6049 return;
c19d1205 6050 }
252b5132 6051
58efb6c0 6052 /* No match. */
252b5132
RH		 6053 abort ();
6054}
6055
e821645d
DJ		 6056/* Print data bytes on INFO->STREAM. */
6057
6058static void
fe56b6ce
NC		 6059print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
6060 struct disassemble_info *info,
e821645d
DJ		 6061 long given)
6062{
6063 switch (info->bytes_per_chunk)
6064 {
6065 case 1:
6066 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
6067 break;
6068 case 2:
6069 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
6070 break;
6071 case 4:
6072 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
6073 break;
6074 default:
6075 abort ();
6076 }
6077}
6078
22a398e1 6079/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 6080 being displayed in symbol relative addresses.
6081
6082 Also disallow private symbol, with __tagsym$$ prefix,
6083 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 6084
6085bfd_boolean
6086arm_symbol_is_valid (asymbol * sym,
6087 struct disassemble_info * info ATTRIBUTE_UNUSED)
6088{
6089 const char * name;
43e65147 6090
22a398e1
NC		 6091 if (sym == NULL)
6092 return FALSE;
6093
6094 name = bfd_asymbol_name (sym);
6095
d8282f0e 6096 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 6097}
6098
65b48a81 6099/* Parse the string of disassembler options. */
baf0cc5e 6100
65b48a81 6101static void
f995bbe8 6102parse_arm_disassembler_options (const char *options)
dd92f639 6103{
f995bbe8 6104 const char *opt;
b34976b6 6105
65b48a81 6106 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
dd92f639 6107 {
65b48a81
PB		 6108 if (CONST_STRNEQ (opt, "reg-names-"))
6109 {
6110 unsigned int i;
6111 for (i = 0; i < NUM_ARM_OPTIONS; i++)
6112 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
6113 {
6114 regname_selected = i;
6115 break;
6116 }
b34976b6 6117
65b48a81
PB		 6118 if (i >= NUM_ARM_OPTIONS)
6119 fprintf (stderr, _("Unrecognised register name set: %s\n"), opt);
6120 }
6121 else if (CONST_STRNEQ (opt, "force-thumb"))
6122 force_thumb = 1;
6123 else if (CONST_STRNEQ (opt, "no-force-thumb"))
6124 force_thumb = 0;
6125 else
6126 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), opt);
dd92f639 6127 }
b34976b6 6128
dd92f639
NC		 6129 return;
6130}
6131
5bc5ae88
RL		 6132static bfd_boolean
6133mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6134 enum map_type *map_symbol);
6135
c22aaad1
PB		 6136/* Search back through the insn stream to determine if this instruction is
6137 conditionally executed. */
fe56b6ce 6138
c22aaad1 6139static void
fe56b6ce
NC		 6140find_ifthen_state (bfd_vma pc,
6141 struct disassemble_info *info,
c22aaad1
PB		 6142 bfd_boolean little)
6143{
6144 unsigned char b[2];
6145 unsigned int insn;
6146 int status;
6147 /* COUNT is twice the number of instructions seen. It will be odd if we
6148 just crossed an instruction boundary. */
6149 int count;
6150 int it_count;
6151 unsigned int seen_it;
6152 bfd_vma addr;
6153
6154 ifthen_address = pc;
6155 ifthen_state = 0;
6156
6157 addr = pc;
6158 count = 1;
6159 it_count = 0;
6160 seen_it = 0;
6161 /* Scan backwards looking for IT instructions, keeping track of where
6162 instruction boundaries are. We don't know if something is actually an
6163 IT instruction until we find a definite instruction boundary. */
6164 for (;;)
6165 {
fe56b6ce 6166 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 6167 {
6168 /* A symbol must be on an instruction boundary, and will not
6169 be within an IT block. */
6170 if (seen_it && (count & 1))
6171 break;
6172
6173 return;
6174 }
6175 addr -= 2;
fe56b6ce 6176 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 6177 if (status)
6178 return;
6179
6180 if (little)
6181 insn = (b[0]) | (b[1] << 8);
6182 else
6183 insn = (b[1]) | (b[0] << 8);
6184 if (seen_it)
6185 {
6186 if ((insn & 0xf800) < 0xe800)
6187 {
6188 /* Addr + 2 is an instruction boundary. See if this matches
6189 the expected boundary based on the position of the last
6190 IT candidate. */
6191 if (count & 1)
6192 break;
6193 seen_it = 0;
6194 }
6195 }
6196 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
6197 {
5bc5ae88
RL		 6198 enum map_type type = MAP_ARM;
6199 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
6200
6201 if (!found || (found && type == MAP_THUMB))
6202 {
6203 /* This could be an IT instruction. */
6204 seen_it = insn;
6205 it_count = count >> 1;
6206 }
c22aaad1
PB		 6207 }
6208 if ((insn & 0xf800) >= 0xe800)
6209 count++;
6210 else
6211 count = (count + 2) | 1;
6212 /* IT blocks contain at most 4 instructions. */
6213 if (count >= 8 && !seen_it)
6214 return;
6215 }
6216 /* We found an IT instruction. */
6217 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
6218 if ((ifthen_state & 0xf) == 0)
6219 ifthen_state = 0;
6220}
6221
b0e28b39
DJ		 6222/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
6223 mapping symbol. */
6224
6225static int
6226is_mapping_symbol (struct disassemble_info *info, int n,
6227 enum map_type *map_type)
6228{
6229 const char *name;
6230
6231 name = bfd_asymbol_name (info->symtab[n]);
6232 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
6233 && (name[2] == 0 || name[2] == '.'))
6234 {
6235 *map_type = ((name[1] == 'a') ? MAP_ARM
6236 : (name[1] == 't') ? MAP_THUMB
6237 : MAP_DATA);
6238 return TRUE;
6239 }
6240
6241 return FALSE;
6242}
6243
6244/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
6245 Returns nonzero if *MAP_TYPE was set. */
6246
6247static int
6248get_map_sym_type (struct disassemble_info *info,
6249 int n,
6250 enum map_type *map_type)
6251{
6252 /* If the symbol is in a different section, ignore it. */
6253 if (info->section != NULL && info->section != info->symtab[n]->section)
6254 return FALSE;
6255
6256 return is_mapping_symbol (info, n, map_type);
6257}
6258
6259/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 6260 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 6261
6262static int
fe56b6ce
NC		 6263get_sym_code_type (struct disassemble_info *info,
6264 int n,
e821645d 6265 enum map_type *map_type)
2087ad84
PB		 6266{
6267 elf_symbol_type *es;
6268 unsigned int type;
b0e28b39
DJ		 6269
6270 /* If the symbol is in a different section, ignore it. */
6271 if (info->section != NULL && info->section != info->symtab[n]->section)
6272 return FALSE;
2087ad84 6273
e821645d 6274 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 6275 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6276
6277 /* If the symbol has function type then use that. */
34e77a92 6278 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 6279 {
39d911fc
TP		 6280 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6281 == ST_BRANCH_TO_THUMB)
35fc36a8
RS		 6282 *map_type = MAP_THUMB;
6283 else
6284 *map_type = MAP_ARM;
2087ad84
PB		 6285 return TRUE;
6286 }
6287
2087ad84
PB		 6288 return FALSE;
6289}
6290
5bc5ae88
RL		 6291/* Search the mapping symbol state for instruction at pc. This is only
6292 applicable for elf target.
6293
6294 There is an assumption Here, info->private_data contains the correct AND
6295 up-to-date information about current scan process. The information will be
6296 used to speed this search process.
6297
6298 Return TRUE if the mapping state can be determined, and map_symbol
6299 will be updated accordingly. Otherwise, return FALSE. */
6300
6301static bfd_boolean
6302mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6303 enum map_type *map_symbol)
6304{
6305 bfd_vma addr;
6306 int n, start = 0;
6307 bfd_boolean found = FALSE;
6308 enum map_type type = MAP_ARM;
6309 struct arm_private_data *private_data;
6310
6311 if (info->private_data == NULL || info->symtab_size == 0
6312 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
6313 return FALSE;
6314
6315 private_data = info->private_data;
6316 if (pc == 0)
6317 start = 0;
6318 else
6319 start = private_data->last_mapping_sym;
6320
6321 start = (start == -1)? 0 : start;
6322 addr = bfd_asymbol_value (info->symtab[start]);
6323
6324 if (pc >= addr)
6325 {
6326 if (get_map_sym_type (info, start, &type))
6327 found = TRUE;
6328 }
6329 else
6330 {
6331 for (n = start - 1; n >= 0; n--)
6332 {
6333 if (get_map_sym_type (info, n, &type))
6334 {
6335 found = TRUE;
6336 break;
6337 }
6338 }
6339 }
6340
6341 /* No mapping symbols were found. A leading $d may be
6342 omitted for sections which start with data; but for
6343 compatibility with legacy and stripped binaries, only
6344 assume the leading $d if there is at least one mapping
6345 symbol in the file. */
6346 if (!found && private_data->has_mapping_symbols == 1)
6347 {
6348 type = MAP_DATA;
6349 found = TRUE;
6350 }
6351
6352 *map_symbol = type;
6353 return found;
6354}
6355
0313a2b8
NC		 6356/* Given a bfd_mach_arm_XXX value, this function fills in the fields
6357 of the supplied arm_feature_set structure with bitmasks indicating
6358 the support base architectures and coprocessor extensions.
6359
6360 FIXME: This could more efficiently implemented as a constant array,
6361 although it would also be less robust. */
6362
6363static void
6364select_arm_features (unsigned long mach,
6365 arm_feature_set * features)
6366{
1af1dd51
MW		 6367#undef ARM_SET_FEATURES
6368#define ARM_SET_FEATURES(FSET) \
6369 { \
6370 const arm_feature_set fset = FSET; \
6371 arm_feature_set tmp = ARM_FEATURE (0, 0, FPU_FPA) ; \
6372 ARM_MERGE_FEATURE_SETS (*features, tmp, fset); \
6373 }
823d2571 6374
0313a2b8
NC		 6375 switch (mach)
6376 {
1af1dd51
MW		 6377 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
6378 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
6379 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
6380 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
6381 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
6382 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
6383 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
6384 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
6385 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
6386 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
6387 case bfd_mach_arm_ep9312:
6388 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
6389 ARM_CEXT_MAVERICK | FPU_MAVERICK));
6390 break;
6391 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
6392 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
0313a2b8
NC		 6393 /* If the machine type is unknown allow all
6394 architecture types and all extensions. */
1af1dd51 6395 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
0313a2b8
NC		 6396 default:
6397 abort ();
6398 }
1af1dd51
MW		 6399
6400#undef ARM_SET_FEATURES
0313a2b8
NC		 6401}
6402
6403
58efb6c0
NC		 6404/* NOTE: There are no checks in these routines that
6405 the relevant number of data bytes exist. */
baf0cc5e 6406
58efb6c0 6407static int
4a5329c6 6408print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 6409{
c19d1205
ZW		 6410 unsigned char b[4];
6411 long given;
6412 int status;
e821645d 6413 int is_thumb = FALSE;
b0e28b39 6414 int is_data = FALSE;
bd2e2557 6415 int little_code;
e821645d 6416 unsigned int size = 4;
4a5329c6 6417 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 6418 bfd_boolean found = FALSE;
b0e28b39 6419 struct arm_private_data *private_data;
58efb6c0 6420
dd92f639
NC		 6421 if (info->disassembler_options)
6422 {
65b48a81 6423 parse_arm_disassembler_options (info->disassembler_options);
b34976b6 6424
58efb6c0 6425 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 6426 info->disassembler_options = NULL;
6427 }
b34976b6 6428
0313a2b8
NC		 6429 /* PR 10288: Control which instructions will be disassembled. */
6430 if (info->private_data == NULL)
6431 {
b0e28b39 6432 static struct arm_private_data private;
0313a2b8
NC		 6433
6434 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
6435 /* If the user did not use the -m command line switch then default to
6436 disassembling all types of ARM instruction.
43e65147 6437
0313a2b8
NC		 6438 The info->mach value has to be ignored as this will be based on
6439 the default archictecture for the target and/or hints in the notes
6440 section, but it will never be greater than the current largest arm
6441 machine value (iWMMXt2), which is only equivalent to the V5TE
6442 architecture. ARM architectures have advanced beyond the machine
6443 value encoding, and these newer architectures would be ignored if
6444 the machine value was used.
6445
6446 Ie the -m switch is used to restrict which instructions will be
6447 disassembled. If it is necessary to use the -m switch to tell
6448 objdump that an ARM binary is being disassembled, eg because the
6449 input is a raw binary file, but it is also desired to disassemble
6450 all ARM instructions then use "-marm". This will select the
6451 "unknown" arm architecture which is compatible with any ARM
6452 instruction. */
6453 info->mach = bfd_mach_arm_unknown;
6454
6455 /* Compute the architecture bitmask from the machine number.
6456 Note: This assumes that the machine number will not change
6457 during disassembly.... */
b0e28b39 6458 select_arm_features (info->mach, & private.features);
0313a2b8 6459
b0e28b39 6460 private.has_mapping_symbols = -1;
1fbaefec
PB		 6461 private.last_mapping_sym = -1;
6462 private.last_mapping_addr = 0;
b0e28b39
DJ		 6463
6464 info->private_data = & private;
0313a2b8 6465 }
b0e28b39
DJ		 6466
6467 private_data = info->private_data;
6468
bd2e2557
SS		 6469 /* Decide if our code is going to be little-endian, despite what the
6470 function argument might say. */
6471 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
6472
b0e28b39
DJ		 6473 /* For ELF, consult the symbol table to determine what kind of code
6474 or data we have. */
8977d4b2 6475 if (info->symtab_size != 0
e821645d
DJ		 6476 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
6477 {
6478 bfd_vma addr;
b0e28b39 6479 int n, start;
e821645d 6480 int last_sym = -1;
b0e28b39 6481 enum map_type type = MAP_ARM;
e821645d 6482
e821645d
DJ		 6483 /* Start scanning at the start of the function, or wherever
6484 we finished last time. */
6750a3a7
NC		 6485 /* PR 14006. When the address is 0 we are either at the start of the
6486 very first function, or else the first function in a new, unlinked
838441e4 6487 executable section (eg because of -ffunction-sections). Either way
6750a3a7
NC		 6488 start scanning from the beginning of the symbol table, not where we
6489 left off last time. */
6490 if (pc == 0)
6491 start = 0;
6492 else
6493 {
6494 start = info->symtab_pos + 1;
6495 if (start < private_data->last_mapping_sym)
6496 start = private_data->last_mapping_sym;
6497 }
b0e28b39 6498 found = FALSE;
e821645d 6499
b0e28b39
DJ		 6500 /* First, look for mapping symbols. */
6501 if (private_data->has_mapping_symbols != 0)
e821645d 6502 {
b0e28b39
DJ		 6503 /* Scan up to the location being disassembled. */
6504 for (n = start; n < info->symtab_size; n++)
6505 {
6506 addr = bfd_asymbol_value (info->symtab[n]);
6507 if (addr > pc)
6508 break;
6509 if (get_map_sym_type (info, n, &type))
6510 {
6511 last_sym = n;
6512 found = TRUE;
6513 }
6514 }
6515
6516 if (!found)
6517 {
6518 /* No mapping symbol found at this address. Look backwards
cc643b88 6519 for a preceding one. */
b0e28b39
DJ		 6520 for (n = start - 1; n >= 0; n--)
6521 {
6522 if (get_map_sym_type (info, n, &type))
6523 {
6524 last_sym = n;
6525 found = TRUE;
6526 break;
6527 }
6528 }
6529 }
6530
6531 if (found)
6532 private_data->has_mapping_symbols = 1;
6533
6534 /* No mapping symbols were found. A leading $d may be
6535 omitted for sections which start with data; but for
6536 compatibility with legacy and stripped binaries, only
6537 assume the leading $d if there is at least one mapping
6538 symbol in the file. */
6539 if (!found && private_data->has_mapping_symbols == -1)
e821645d 6540 {
b0e28b39
DJ		 6541 /* Look for mapping symbols, in any section. */
6542 for (n = 0; n < info->symtab_size; n++)
6543 if (is_mapping_symbol (info, n, &type))
6544 {
6545 private_data->has_mapping_symbols = 1;
6546 break;
6547 }
6548 if (private_data->has_mapping_symbols == -1)
6549 private_data->has_mapping_symbols = 0;
6550 }
6551
6552 if (!found && private_data->has_mapping_symbols == 1)
6553 {
6554 type = MAP_DATA;
e821645d
DJ		 6555 found = TRUE;
6556 }
6557 }
6558
b0e28b39
DJ		 6559 /* Next search for function symbols to separate ARM from Thumb
6560 in binaries without mapping symbols. */
e821645d
DJ		 6561 if (!found)
6562 {
b0e28b39
DJ		 6563 /* Scan up to the location being disassembled. */
6564 for (n = start; n < info->symtab_size; n++)
e821645d 6565 {
b0e28b39
DJ		 6566 addr = bfd_asymbol_value (info->symtab[n]);
6567 if (addr > pc)
6568 break;
6569 if (get_sym_code_type (info, n, &type))
e821645d
DJ		 6570 {
6571 last_sym = n;
6572 found = TRUE;
b0e28b39
DJ		 6573 }
6574 }
6575
6576 if (!found)
6577 {
6578 /* No mapping symbol found at this address. Look backwards
cc643b88 6579 for a preceding one. */
b0e28b39
DJ		 6580 for (n = start - 1; n >= 0; n--)
6581 {
6582 if (get_sym_code_type (info, n, &type))
6583 {
6584 last_sym = n;
6585 found = TRUE;
6586 break;
6587 }
e821645d
DJ		 6588 }
6589 }
6590 }
6591
1fbaefec
PB		 6592 private_data->last_mapping_sym = last_sym;
6593 private_data->last_type = type;
6594 is_thumb = (private_data->last_type == MAP_THUMB);
6595 is_data = (private_data->last_type == MAP_DATA);
b34976b6 6596
e821645d
DJ		 6597 /* Look a little bit ahead to see if we should print out
6598 two or four bytes of data. If there's a symbol,
6599 mapping or otherwise, after two bytes then don't
6600 print more. */
6601 if (is_data)
6602 {
6603 size = 4 - (pc & 3);
6604 for (n = last_sym + 1; n < info->symtab_size; n++)
6605 {
6606 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 6607 if (addr > pc
6608 && (info->section == NULL
6609 || info->section == info->symtab[n]->section))
e821645d
DJ		 6610 {
6611 if (addr - pc < size)
6612 size = addr - pc;
6613 break;
6614 }
6615 }
6616 /* If the next symbol is after three bytes, we need to
6617 print only part of the data, so that we can use either
6618 .byte or .short. */
6619 if (size == 3)
6620 size = (pc & 1) ? 1 : 2;
6621 }
6622 }
6623
6624 if (info->symbols != NULL)
252b5132 6625 {
5876e06d
NC		 6626 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
6627 {
2f0ca46a 6628 coff_symbol_type * cs;
b34976b6 6629
5876e06d
NC		 6630 cs = coffsymbol (*info->symbols);
6631 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
6632 || cs->native->u.syment.n_sclass == C_THUMBSTAT
6633 || cs->native->u.syment.n_sclass == C_THUMBLABEL
6634 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
6635 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
6636 }
e821645d
DJ		 6637 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
6638 && !found)
5876e06d 6639 {
2087ad84
PB		 6640 /* If no mapping symbol has been found then fall back to the type
6641 of the function symbol. */
e821645d
DJ		 6642 elf_symbol_type * es;
6643 unsigned int type;
2087ad84 6644
e821645d
DJ		 6645 es = *(elf_symbol_type **)(info->symbols);
6646 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 6647
39d911fc
TP		 6648 is_thumb =
6649 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6650 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
5876e06d 6651 }
e49d43ff
TG		 6652 else if (bfd_asymbol_flavour (*info->symbols)
6653 == bfd_target_mach_o_flavour)
6654 {
6655 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
6656
6657 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
6658 }
5876e06d 6659 }
b34976b6 6660
e821645d
DJ		 6661 if (force_thumb)
6662 is_thumb = TRUE;
6663
b8f9ee44
CL		 6664 if (is_data)
6665 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6666 else
6667 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6668
c19d1205 6669 info->bytes_per_line = 4;
252b5132 6670
1316c8b3
NC		 6671 /* PR 10263: Disassemble data if requested to do so by the user. */
6672 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 6673 {
6674 int i;
6675
1316c8b3 6676 /* Size was already set above. */
e821645d
DJ		 6677 info->bytes_per_chunk = size;
6678 printer = print_insn_data;
6679
fe56b6ce 6680 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 6681 given = 0;
6682 if (little)
6683 for (i = size - 1; i >= 0; i--)
6684 given = b[i] | (given << 8);
6685 else
6686 for (i = 0; i < (int) size; i++)
6687 given = b[i] | (given << 8);
6688 }
6689 else if (!is_thumb)
252b5132 6690 {
c19d1205
ZW		 6691 /* In ARM mode endianness is a straightforward issue: the instruction
6692 is four bytes long and is either ordered 0123 or 3210. */
6693 printer = print_insn_arm;
6694 info->bytes_per_chunk = 4;
4a5329c6 6695 size = 4;
c19d1205 6696
0313a2b8 6697 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 6698 if (little_code)
c19d1205
ZW		 6699 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
6700 else
6701 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
252b5132 6702 }
58efb6c0 6703 else
252b5132 6704 {
c19d1205
ZW		 6705 /* In Thumb mode we have the additional wrinkle of two
6706 instruction lengths. Fortunately, the bits that determine
6707 the length of the current instruction are always to be found
6708 in the first two bytes. */
4a5329c6 6709 printer = print_insn_thumb16;
c19d1205 6710 info->bytes_per_chunk = 2;
4a5329c6
ZW		 6711 size = 2;
6712
fe56b6ce 6713 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 6714 if (little_code)
9a2ff3f5
AM		 6715 given = (b[0]) | (b[1] << 8);
6716 else
6717 given = (b[1]) | (b[0] << 8);
6718
c19d1205 6719 if (!status)
252b5132 6720 {
c19d1205
ZW		 6721 /* These bit patterns signal a four-byte Thumb
6722 instruction. */
6723 if ((given & 0xF800) == 0xF800
6724 || (given & 0xF800) == 0xF000
6725 || (given & 0xF800) == 0xE800)
252b5132 6726 {
0313a2b8 6727 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 6728 if (little_code)
c19d1205 6729 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 6730 else
c19d1205
ZW		 6731 given = (b[1]) | (b[0] << 8) | (given << 16);
6732
6733 printer = print_insn_thumb32;
4a5329c6 6734 size = 4;
252b5132 6735 }
252b5132 6736 }
c22aaad1
PB		 6737
6738 if (ifthen_address != pc)
0313a2b8 6739 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 6740
6741 if (ifthen_state)
6742 {
6743 if ((ifthen_state & 0xf) == 0x8)
6744 ifthen_next_state = 0;
6745 else
6746 ifthen_next_state = (ifthen_state & 0xe0)
6747 | ((ifthen_state & 0xf) << 1);
6748 }
252b5132 6749 }
b34976b6 6750
c19d1205
ZW		 6751 if (status)
6752 {
6753 info->memory_error_func (status, pc, info);
6754 return -1;
6755 }
6a56ec7e
NC		 6756 if (info->flags & INSN_HAS_RELOC)
6757 /* If the instruction has a reloc associated with it, then
6758 the offset field in the instruction will actually be the
6759 addend for the reloc. (We are using REL type relocs).
6760 In such cases, we can ignore the pc when computing
6761 addresses, since the addend is not currently pc-relative. */
6762 pc = 0;
b34976b6 6763
4a5329c6 6764 printer (pc, info, given);
c22aaad1
PB		 6765
6766 if (is_thumb)
6767 {
6768 ifthen_state = ifthen_next_state;
6769 ifthen_address += size;
6770 }
4a5329c6 6771 return size;
252b5132
RH		 6772}
6773
6774int
4a5329c6 6775print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 6776{
bd2e2557
SS		 6777 /* Detect BE8-ness and record it in the disassembler info. */
6778 if (info->flavour == bfd_target_elf_flavour
6779 && info->section != NULL
6780 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
6781 info->endian_code = BFD_ENDIAN_LITTLE;
6782
b34976b6 6783 return print_insn (pc, info, FALSE);
58efb6c0 6784}
01c7f630 6785
58efb6c0 6786int
4a5329c6 6787print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 6788{
b34976b6 6789 return print_insn (pc, info, TRUE);
58efb6c0 6790}
252b5132 6791
65b48a81
PB		 6792const disasm_options_t *
6793disassembler_options_arm (void)
6794{
6795 static disasm_options_t *opts = NULL;
6796
6797 if (opts == NULL)
6798 {
6799 unsigned int i;
6800 opts = XNEW (disasm_options_t);
6801 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
6802 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
6803 for (i = 0; i < NUM_ARM_OPTIONS; i++)
6804 {
6805 opts->name[i] = regnames[i].name;
6806 if (regnames[i].description != NULL)
6807 opts->description[i] = _(regnames[i].description);
6808 else
6809 opts->description[i] = NULL;
6810 }
6811 /* The array we return must be NULL terminated. */
6812 opts->name[i] = NULL;
6813 opts->description[i] = NULL;
6814 }
6815
6816 return opts;
6817}
6818
58efb6c0 6819void
4a5329c6 6820print_arm_disassembler_options (FILE *stream)
58efb6c0 6821{
65b48a81 6822 unsigned int i, max_len = 0;
58efb6c0
NC		 6823 fprintf (stream, _("\n\
6824The following ARM specific disassembler options are supported for use with\n\
6825the -M switch:\n"));
b34976b6 6826
65b48a81
PB		 6827 for (i = 0; i < NUM_ARM_OPTIONS; i++)
6828 {
6829 unsigned int len = strlen (regnames[i].name);
6830 if (max_len < len)
6831 max_len = len;
6832 }
58efb6c0 6833
65b48a81
PB		 6834 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
6835 fprintf (stream, " %s%*c %s\n",
6836 regnames[i].name,
6837 (int)(max_len - strlen (regnames[i].name)), ' ',
6838 _(regnames[i].description));
252b5132 6839}
GDB Binutils - Deliverables
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