projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH 49/57][Arm][OBJDUMP] Add support for MVE complex number instructions
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
CommitLineData
252b5132 1/* Instruction printing code for the ARM
82704155 2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
143275ea 24#include <assert.h>
2fbad815 25
6394c606 26#include "disassemble.h"
2fbad815 27#include "opcode/arm.h"
252b5132 28#include "opintl.h"
31e0f3cd 29#include "safe-ctype.h"
65b48a81 30#include "libiberty.h"
0dbde4cf 31#include "floatformat.h"
252b5132 32
baf0cc5e 33/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 34#include "coff/internal.h"
35#include "libcoff.h"
2d5d5a8f 36#include "bfd.h"
252b5132
RH		 37#include "elf-bfd.h"
38#include "elf/internal.h"
39#include "elf/arm.h"
e49d43ff 40#include "mach-o.h"
252b5132 41
6b5d3a4d 42/* FIXME: Belongs in global header. */
01c7f630 43#ifndef strneq
58efb6c0
NC		 44#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
45#endif
46
1fbaefec
PB		 47/* Cached mapping symbol state. */
48enum map_type
49{
50 MAP_ARM,
51 MAP_THUMB,
52 MAP_DATA
53};
54
b0e28b39
DJ		 55struct arm_private_data
56{
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features;
59
1fbaefec
PB		 60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type;
62
63 /* Tracking symbol table information */
64 int last_mapping_sym;
796d6298
TC		 65
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset;
1fbaefec 68 bfd_vma last_mapping_addr;
b0e28b39
DJ		 69};
70
73cd51e5
AV		 71enum mve_instructions
72{
143275ea
AV		 73 MVE_VPST,
74 MVE_VPT_FP_T1,
75 MVE_VPT_FP_T2,
76 MVE_VPT_VEC_T1,
77 MVE_VPT_VEC_T2,
78 MVE_VPT_VEC_T3,
79 MVE_VPT_VEC_T4,
80 MVE_VPT_VEC_T5,
81 MVE_VPT_VEC_T6,
82 MVE_VCMP_FP_T1,
83 MVE_VCMP_FP_T2,
84 MVE_VCMP_VEC_T1,
85 MVE_VCMP_VEC_T2,
86 MVE_VCMP_VEC_T3,
87 MVE_VCMP_VEC_T4,
88 MVE_VCMP_VEC_T5,
89 MVE_VCMP_VEC_T6,
9743db03
AV		 90 MVE_VDUP,
91 MVE_VEOR,
92 MVE_VFMAS_FP_SCALAR,
93 MVE_VFMA_FP_SCALAR,
94 MVE_VFMA_FP,
95 MVE_VFMS_FP,
96 MVE_VHADD_T1,
97 MVE_VHADD_T2,
98 MVE_VHSUB_T1,
99 MVE_VHSUB_T2,
100 MVE_VRHADD,
04d54ace
AV		 101 MVE_VLD2,
102 MVE_VLD4,
103 MVE_VST2,
104 MVE_VST4,
aef6d006
AV		 105 MVE_VLDRB_T1,
106 MVE_VLDRH_T2,
107 MVE_VLDRB_T5,
108 MVE_VLDRH_T6,
109 MVE_VLDRW_T7,
110 MVE_VSTRB_T1,
111 MVE_VSTRH_T2,
112 MVE_VSTRB_T5,
113 MVE_VSTRH_T6,
114 MVE_VSTRW_T7,
ef1576a1
AV		 115 MVE_VLDRB_GATHER_T1,
116 MVE_VLDRH_GATHER_T2,
117 MVE_VLDRW_GATHER_T3,
118 MVE_VLDRD_GATHER_T4,
119 MVE_VLDRW_GATHER_T5,
120 MVE_VLDRD_GATHER_T6,
121 MVE_VSTRB_SCATTER_T1,
122 MVE_VSTRH_SCATTER_T2,
123 MVE_VSTRW_SCATTER_T3,
124 MVE_VSTRD_SCATTER_T4,
125 MVE_VSTRW_SCATTER_T5,
126 MVE_VSTRD_SCATTER_T6,
bf0b396d
AV		 127 MVE_VCVT_FP_FIX_VEC,
128 MVE_VCVT_BETWEEN_FP_INT,
129 MVE_VCVT_FP_HALF_FP,
130 MVE_VCVT_FROM_FP_TO_INT,
131 MVE_VRINT_FP,
c507f10b
AV		 132 MVE_VMOV_HFP_TO_GP,
133 MVE_VMOV_GP_TO_VEC_LANE,
134 MVE_VMOV_IMM_TO_VEC,
135 MVE_VMOV_VEC_TO_VEC,
136 MVE_VMOV2_VEC_LANE_TO_GP,
137 MVE_VMOV2_GP_TO_VEC_LANE,
138 MVE_VMOV_VEC_LANE_TO_GP,
139 MVE_VMVN_IMM,
140 MVE_VMVN_REG,
141 MVE_VORR_IMM,
142 MVE_VORR_REG,
143 MVE_VORN,
144 MVE_VBIC_IMM,
145 MVE_VBIC_REG,
146 MVE_VMOVX,
14925797
AV		 147 MVE_VMOVL,
148 MVE_VMOVN,
149 MVE_VMULL_INT,
150 MVE_VMULL_POLY,
151 MVE_VQDMULL_T1,
152 MVE_VQDMULL_T2,
153 MVE_VQMOVN,
154 MVE_VQMOVUN,
d3b63143
AV		 155 MVE_VADDV,
156 MVE_VMLADAV_T1,
157 MVE_VMLADAV_T2,
158 MVE_VMLALDAV,
159 MVE_VMLAS,
160 MVE_VADDLV,
161 MVE_VMLSDAV_T1,
162 MVE_VMLSDAV_T2,
163 MVE_VMLSLDAV,
164 MVE_VRMLALDAVH,
165 MVE_VRMLSLDAVH,
166 MVE_VQDMLADH,
167 MVE_VQRDMLADH,
168 MVE_VQDMLAH,
169 MVE_VQRDMLAH,
170 MVE_VQDMLASH,
171 MVE_VQRDMLASH,
172 MVE_VQDMLSDH,
173 MVE_VQRDMLSDH,
174 MVE_VQDMULH_T1,
175 MVE_VQRDMULH_T2,
176 MVE_VQDMULH_T3,
177 MVE_VQRDMULH_T4,
1c8f2df8
AV		 178 MVE_VDDUP,
179 MVE_VDWDUP,
180 MVE_VIWDUP,
181 MVE_VIDUP,
897b9bbc
AV		 182 MVE_VCADD_FP,
183 MVE_VCADD_VEC,
184 MVE_VHCADD,
185 MVE_VCMLA_FP,
186 MVE_VCMUL_FP,
73cd51e5
AV		 187 MVE_NONE
188};
189
190enum mve_unpredictable
191{
192 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
193 */
143275ea
AV		 194 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and
195 fcB = 1 (vpt). */
196 UNPRED_R13, /* Unpredictable because r13 (sp) or
197 r15 (sp) used. */
9743db03 198 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
04d54ace
AV		 199 UNPRED_Q_GT_4, /* Unpredictable because
200 vec reg start > 4 (vld4/st4). */
201 UNPRED_Q_GT_6, /* Unpredictable because
202 vec reg start > 6 (vld2/st2). */
203 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
204 and WB bit = 1. */
ef1576a1
AV		 205 UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are
206 equal. */
207 UNPRED_OS, /* Unpredictable because offset scaled == 1. */
bf0b396d
AV		 208 UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the
209 same. */
c507f10b
AV		 210 UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and
211 size = 1. */
212 UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and
213 size = 2. */
73cd51e5
AV		 214 UNPRED_NONE /* No unpredictable behavior. */
215};
216
217enum mve_undefined
218{
bf0b396d 219 UNDEF_SIZE_0, /* undefined because size == 0. */
c507f10b 220 UNDEF_SIZE_2, /* undefined because size == 2. */
aef6d006
AV		 221 UNDEF_SIZE_3, /* undefined because size == 3. */
222 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
ef1576a1
AV		 223 UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
224 UNDEF_SIZE_NOT_3, /* undefined because size != 3. */
225 UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and
226 size == 0. */
227 UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and
228 size == 1. */
229 UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
bf0b396d
AV		 230 UNDEF_VCVT_IMM6, /* imm6 < 32. */
231 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
c507f10b
AV		 232 UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and
233 op1 == (0 or 1). */
234 UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and
235 op2 == 0 and op1 == (0 or 1). */
236 UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode
237 in {0xx1, x0x1}. */
d3b63143 238 UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */
73cd51e5
AV		 239 UNDEF_NONE /* no undefined behavior. */
240};
241
6b5d3a4d
ZW		 242struct opcode32
243{
823d2571
TG		 244 arm_feature_set arch; /* Architecture defining this insn. */
245 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 246 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 247 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 248};
249
73cd51e5
AV		 250/* MVE opcodes. */
251
252struct mopcode32
253{
254 arm_feature_set arch; /* Architecture defining this insn. */
255 enum mve_instructions mve_op; /* Specific mve instruction for faster
256 decoding. */
257 unsigned long value; /* If arch is 0 then value is a sentinel. */
258 unsigned long mask; /* Recognise insn if (op & mask) == value. */
259 const char * assembler; /* How to disassemble this insn. */
260};
261
6b0dd094
AV		 262enum isa {
263 ANY,
264 T32,
265 ARM
266};
267
268
269/* Shared (between Arm and Thumb mode) opcode. */
270struct sopcode32
271{
272 enum isa isa; /* Execution mode instruction availability. */
273 arm_feature_set arch; /* Architecture defining this insn. */
274 unsigned long value; /* If arch is 0 then value is a sentinel. */
275 unsigned long mask; /* Recognise insn if (op & mask) == value. */
276 const char * assembler; /* How to disassemble this insn. */
277};
278
6b5d3a4d
ZW		 279struct opcode16
280{
823d2571 281 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 282 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 283 const char *assembler; /* How to disassemble this insn. */
284};
b7693d02 285
8f06b2d8 286/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 287
2fbad815 288 %% %
4a5329c6 289
c22aaad1 290 %c print condition code (always bits 28-31 in ARM mode)
37b37b2d 291 %q print shifter argument
e2efe87d
MGD		 292 %u print condition code (unconditional in ARM mode,
293 UNPREDICTABLE if not AL in Thumb)
4a5329c6 294 %A print address for ldc/stc/ldf/stf instruction
16980d0b 295 %B print vstm/vldm register list
efd6b359 296 %C print vscclrm register list
4a5329c6 297 %I print cirrus signed shift immediate: bits 0..3|4..6
32c36c3c
AV		 298 %J print register for VLDR instruction
299 %K print address for VLDR instruction
4a5329c6
ZW		 300 %F print the COUNT field of a LFM/SFM instruction.
301 %P print floating point precision in arithmetic insn
302 %Q print floating point precision in ldf/stf insn
303 %R print floating point rounding mode
304
33399f07 305 %<bitfield>c print as a condition code (for vsel)
4a5329c6 306 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 307 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
308 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 309 %<bitfield>d print the bitfield in decimal
16980d0b 310 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 311 %<bitfield>x print the bitfield in hex
312 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 313 %<bitfield>f print a floating point constant if >7 else a
314 floating point register
4a5329c6
ZW		 315 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
316 %<bitfield>g print as an iWMMXt 64-bit register
317 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 318 %<bitfield>D print as a NEON D register
319 %<bitfield>Q print as a NEON Q register
c28eeff2 320 %<bitfield>V print as a NEON D or Q register
6f1c2142 321 %<bitfield>E print a quarter-float immediate value
4a5329c6 322
16980d0b 323 %y<code> print a single precision VFP reg.
2fbad815 324 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 325 %z<code> print a double precision VFP reg
2fbad815 326 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 327
16980d0b
JB		 328 %<bitfield>'c print specified char iff bitfield is all ones
329 %<bitfield>`c print specified char iff bitfield is all zeroes
330 %<bitfield>?ab... select from array of values in big endian order
43e65147 331
2fbad815 332 %L print as an iWMMXt N/M width field.
4a5329c6 333 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 334 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 335 versions.
336 %i print 5-bit immediate in bits 8,3..0
337 (print "32" when 0)
fe56b6ce 338 %r print register offset address for wldt/wstr instruction. */
2fbad815 339
21d799b5 340enum opcode_sentinel_enum
05413229
NC		 341{
342 SENTINEL_IWMMXT_START = 1,
343 SENTINEL_IWMMXT_END,
344 SENTINEL_GENERIC_START
345} opcode_sentinels;
346
aefd8a40 347#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
0b347048
TC		 348#define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
349#define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
c1e26897 350#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 351
8f06b2d8 352/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 353
6b0dd094 354static const struct sopcode32 coprocessor_opcodes[] =
2fbad815 355{
2fbad815 356 /* XScale instructions. */
6b0dd094 357 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 358 0x0e200010, 0x0fff0ff0,
359 "mia%c\tacc0, %0-3r, %12-15r"},
6b0dd094 360 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 361 0x0e280010, 0x0fff0ff0,
362 "miaph%c\tacc0, %0-3r, %12-15r"},
6b0dd094 363 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 364 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
6b0dd094 365 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 366 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
6b0dd094 367 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 368 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 369
2fbad815 370 /* Intel Wireless MMX technology instructions. */
6b0dd094
AV		 371 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
372 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
823d2571 373 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
6b0dd094 374 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 375 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
6b0dd094 376 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 377 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
6b0dd094 378 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 379 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
6b0dd094 380 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 381 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
6b0dd094 382 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 383 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
6b0dd094 384 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 385 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
6b0dd094 386 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 387 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 388 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 389 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 390 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 391 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 392 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 393 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
6b0dd094 394 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 395 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
6b0dd094 396 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 397 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
6b0dd094 398 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 399 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
6b0dd094 400 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 401 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
6b0dd094 402 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 403 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 404 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 405 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 406 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 407 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 408 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 409 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 410 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 411 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 412 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 413 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
6b0dd094 414 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 415 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 416 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 417 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 418 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 419 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 420 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 421 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 422 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 423 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 424 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 425 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 426 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 427 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
6b0dd094 428 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 429 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
6b0dd094 430 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 431 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
6b0dd094 432 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 433 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 434 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 435 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 436 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 437 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 438 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 439 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 440 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 441 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
6b0dd094 442 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 443 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 444 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 445 0x0e800120, 0x0f800ff0,
446 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 447 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 448 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 449 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 450 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 451 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 452 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 453 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 454 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 455 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 456 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 457 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 458 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 459 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 460 0x0e8000a0, 0x0f800ff0,
461 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 462 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 463 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 464 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 465 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 466 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 467 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 468 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 469 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 470 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 471 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 472 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 473 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 474 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 475 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 476 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 477 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 478 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 479 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
6b0dd094 480 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 481 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 482 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 483 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 484 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 485 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 486 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 487 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 488 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 489 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 490 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 491 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 492 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 493 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 494 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 495 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 496 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 497 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 498 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 499 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
6b0dd094 500 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 501 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
6b0dd094 502 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 503 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
6b0dd094 504 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 505 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 506 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 507 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 508 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 509 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 510 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 511 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
6b0dd094 512 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 513 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
6b0dd094 514 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 515 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
6b0dd094 516 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 517 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 518 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 519 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 520 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 521 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 522 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 523 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 524 {ANY, ARM_FEATURE_CORE_LOW (0),
823d2571 525 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 526
fe56b6ce 527 /* Floating point coprocessor (FPA) instructions. */
6b0dd094 528 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 529 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 530 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 531 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 532 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 533 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 534 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 535 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 536 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 537 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 538 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 539 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 540 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 541 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 542 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 543 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 544 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 545 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 546 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 547 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 548 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 549 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 550 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 551 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 552 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 553 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 554 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 555 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 556 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 557 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 558 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 559 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 560 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 561 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 562 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 563 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
6b0dd094 564 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 565 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
6b0dd094 566 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 567 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 568 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 569 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
6b0dd094 570 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 571 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
6b0dd094 572 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 573 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
6b0dd094 574 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 575 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
6b0dd094 576 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 577 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 578 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 579 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 580 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 581 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 582 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 583 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 584 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 585 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
6b0dd094 586 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 587 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
6b0dd094 588 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 589 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
6b0dd094 590 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 591 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
6b0dd094 592 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 593 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
6b0dd094 594 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 595 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
6b0dd094 596 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 597 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
6b0dd094 598 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 599 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
6b0dd094 600 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 601 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
6b0dd094 602 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 603 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
6b0dd094 604 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 605 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
6b0dd094 606 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 607 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
6b0dd094 608 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 609 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
6b0dd094 610 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 611 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
6b0dd094 612 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 613 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 614
efd6b359
AV		 615 /* Armv8.1-M Mainline instructions. */
616 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
617 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
618 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
619 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
620
16a1fa25 621 /* ARMv8-M Mainline Security Extensions instructions. */
6b0dd094 622 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25 623 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
6b0dd094 624 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25
TP		 625 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
626
fe56b6ce 627 /* Register load/store. */
6b0dd094 628 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 629 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
6b0dd094 630 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 631 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
6b0dd094 632 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 633 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
6b0dd094 634 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 635 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
6b0dd094 636 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 637 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
6b0dd094 638 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 639 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
6b0dd094 640 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 641 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
6b0dd094 642 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 643 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
6b0dd094 644 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 645 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
6b0dd094 646 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 647 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
6b0dd094 648 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 649 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
6b0dd094 650 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 651 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
6b0dd094 652 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 653 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
6b0dd094 654 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 655 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
6b0dd094 656 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 657 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
6b0dd094 658 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 659 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
32c36c3c
AV		 660 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
661 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
662 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
663 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
823d2571 664
6b0dd094 665 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 666 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 667 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 668 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 669 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 670 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
6b0dd094 671 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 672 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 673
fe56b6ce 674 /* Data transfer between ARM and NEON registers. */
6b0dd094 675 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 676 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
6b0dd094 677 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 678 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
6b0dd094 679 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 680 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
6b0dd094 681 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 682 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
6b0dd094 683 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 684 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
6b0dd094 685 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 686 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
6b0dd094 687 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 688 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
6b0dd094 689 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 690 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 691 /* Half-precision conversion instructions. */
6b0dd094 692 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 693 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
6b0dd094 694 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 695 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
6b0dd094 696 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 697 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
6b0dd094 698 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 699 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 700
fe56b6ce 701 /* Floating point coprocessor (VFP) instructions. */
6b0dd094 702 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 703 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
6b0dd094 704 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 705 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
6b0dd094 706 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 707 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
6b0dd094 708 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 709 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
6b0dd094 710 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 711 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
6b0dd094 712 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 713 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
6b0dd094 714 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 715 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
6b0dd094 716 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 717 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
6b0dd094 718 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 719 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
6b0dd094 720 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 721 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
6b0dd094 722 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 723 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
6b0dd094 724 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 725 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
6b0dd094 726 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 727 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
6b0dd094 728 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 729 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
6b0dd094 730 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 731 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
6b0dd094 732 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 733 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
6b0dd094 734 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 735 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
6b0dd094 736 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 737 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
6b0dd094 738 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 739 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
6b0dd094 740 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 741 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
6b0dd094 742 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 743 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
6b0dd094 744 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 745 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
6b0dd094 746 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 747 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
6b0dd094 748 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 749 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
6b0dd094 750 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 751 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
6b0dd094 752 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 753 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
6b0dd094 754 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 755 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
6b0dd094 756 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 757 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
6b0dd094 758 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 759 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
6b0dd094 760 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 761 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
6b0dd094 762 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 763 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
6b0dd094 764 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 765 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
6b0dd094 766 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 767 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
6b0dd094 768 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 769 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
6b0dd094 770 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 771 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
6b0dd094 772 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 773 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
6b0dd094 774 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 775 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
6b0dd094 776 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 777 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
6b0dd094 778 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 779 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
6b0dd094 780 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 781 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 782 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 783 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
6b0dd094 784 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 785 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
6b0dd094 786 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 787 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
6b0dd094 788 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 789 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
6b0dd094 790 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 791 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
6b0dd094 792 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 793 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
6b0dd094 794 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6f1c2142 795 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
6b0dd094 796 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6f1c2142 797 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
6b0dd094 798 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 799 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
6b0dd094 800 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 801 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
6b0dd094 802 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 803 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
6b0dd094 804 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 805 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 806 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 807 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 808 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 809 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 810 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 811 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 812 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 813 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 814 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 815 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 816 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 817 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 818 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 819 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 820 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 821 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 822 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 823 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 824 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 825 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 826 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 827 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 828 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 829 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
6b0dd094 830 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 831 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
6b0dd094 832 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 833 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
6b0dd094 834 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 835 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
6b0dd094 836 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 837 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
6b0dd094 838 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 839 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 840
841 /* Cirrus coprocessor instructions. */
6b0dd094 842 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 843 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 844 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 845 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 846 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 847 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 848 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 849 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 850 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 851 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 852 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 853 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 854 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 855 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 856 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 857 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 858 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 859 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 860 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 861 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 862 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 863 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 864 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 865 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 866 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 867 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 868 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 869 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 870 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 871 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 872 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 873 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 874 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 875 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
6b0dd094 876 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 877 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
6b0dd094 878 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 879 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
6b0dd094 880 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 881 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
6b0dd094 882 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 883 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
6b0dd094 884 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 885 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
6b0dd094 886 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 887 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 888 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 889 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
6b0dd094 890 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 891 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 892 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 893 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
6b0dd094 894 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 895 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 896 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 897 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 898 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 899 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 900 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 901 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 902 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 903 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 904 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 905 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 906 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 907 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 908 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 909 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 910 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 911 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
6b0dd094 912 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 913 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
6b0dd094 914 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 915 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
6b0dd094 916 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 917 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
6b0dd094 918 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 919 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 920 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 921 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 922 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 923 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
6b0dd094 924 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 925 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
6b0dd094 926 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 927 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
6b0dd094 928 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 929 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
6b0dd094 930 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 931 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
6b0dd094 932 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 933 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
6b0dd094 934 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 935 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 936 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 937 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 938 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 939 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 940 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 941 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 942 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 943 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
6b0dd094 944 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 945 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
6b0dd094 946 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 947 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
6b0dd094 948 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 949 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
6b0dd094 950 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 951 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
6b0dd094 952 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 953 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
6b0dd094 954 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 955 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 956 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 957 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 958 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 959 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 960 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 961 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 962 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 963 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 964 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 965 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 966 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 967 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 968 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 969 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 970 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 971 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 972 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 973 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 974 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 975 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 976 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 977 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 978 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 979 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 980 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 981 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 982 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 983 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 984 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 985 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 986 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 987 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 988 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 989 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 990 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 991 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 992 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 993 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 994 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 995 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 996 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 997 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 998 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 999 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1000 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1001 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1002 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1003 0x0e000600, 0x0ff00f10,
1004 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1005 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1006 0x0e100600, 0x0ff00f10,
1007 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1008 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1009 0x0e200600, 0x0ff00f10,
1010 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1011 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1012 0x0e300600, 0x0ff00f10,
1013 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 1014
62f3b8c8 1015 /* VFP Fused multiply add instructions. */
6b0dd094 1016 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1017 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1018 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1019 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1020 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1021 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1022 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1023 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
6b0dd094 1024 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1025 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1026 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1027 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1028 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1029 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1030 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1031 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 1032
33399f07 1033 /* FP v5. */
6b0dd094 1034 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1035 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
6b0dd094 1036 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1037 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
6b0dd094 1038 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1039 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1040 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1041 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1042 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1043 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1044 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1045 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1046 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1047 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
6b0dd094 1048 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1049 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
6b0dd094 1050 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1051 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
6b0dd094 1052 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1053 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
6b0dd094 1054 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1055 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
6b0dd094 1056 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1057 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 1058
05413229 1059 /* Generic coprocessor instructions. */
6b0dd094
AV		 1060 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
1061 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
823d2571 1062 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
6b0dd094 1063 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
823d2571
TG		 1064 0x0c500000, 0x0ff00000,
1065 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
6b0dd094 1066 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1067 0x0e000000, 0x0f000010,
1068 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1069 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1070 0x0e10f010, 0x0f10f010,
1071 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1072 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1073 0x0e100010, 0x0f100010,
1074 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1075 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1076 0x0e000010, 0x0f100010,
1077 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1078 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571 1079 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 1080 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571 1081 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
2fbad815 1082
05413229 1083 /* V6 coprocessor instructions. */
6b0dd094 1084 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
823d2571
TG		 1085 0xfc500000, 0xfff00000,
1086 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
6b0dd094 1087 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
823d2571
TG		 1088 0xfc400000, 0xfff00000,
1089 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
8f06b2d8 1090
c28eeff2 1091 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
6b0dd094 1092 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1093 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1094 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1095 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1096 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1097 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1098 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1099 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1100 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1101 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1102 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1103 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1104 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1105 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
6b0dd094 1106 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1107 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
6b0dd094 1108 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1109 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
6b0dd094 1110 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1111 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
c28eeff2 1112
c604a79a 1113 /* Dot Product instructions in the space of coprocessor 13. */
6b0dd094 1114 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a 1115 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
6b0dd094 1116 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a
JW		 1117 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1118
dec41383 1119 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
6b0dd094 1120 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1121 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1122 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1123 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1124 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1125 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1126 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1127 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1128 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1129 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1130 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1131 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1132 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1133 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
6b0dd094 1134 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383
JW		 1135 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1136
05413229 1137 /* V5 coprocessor instructions. */
6b0dd094 1138 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571 1139 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 1140 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571 1141 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 1142 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1143 0xfe000000, 0xff000010,
1144 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1145 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1146 0xfe000010, 0xff100010,
1147 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1148 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1149 0xfe100010, 0xff100010,
1150 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1151
b0c11777
RL		 1152 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1153 cp_num: bit <11:8> == 0b1001.
1154 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
6b0dd094 1155 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1156 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
6b0dd094 1157 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1158 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
6b0dd094 1159 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1160 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
6b0dd094 1161 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1162 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
6b0dd094 1163 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1164 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 1165 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1166 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
6b0dd094 1167 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1168 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
6b0dd094 1169 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1170 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
6b0dd094 1171 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1172 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
6b0dd094 1173 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1174 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
6b0dd094 1175 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1176 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1177 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1178 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1179 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1180 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1181 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1182 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1183 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1184 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
6b0dd094 1185 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1186 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
6b0dd094 1187 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1188 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
6b0dd094 1189 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1190 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
6b0dd094 1191 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1192 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1193 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1194 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1195 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1196 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1197 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1198 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1199 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1200 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
6b0dd094 1201 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1202 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
6b0dd094 1203 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1204 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
6b0dd094 1205 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1206 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1207 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1208 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
6b0dd094 1209 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1210 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1211 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1212 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1213 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1214 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1215 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1216 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
6b0dd094 1217 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1218 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
6b0dd094 1219 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1220 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
6b0dd094 1221 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1222 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
6b0dd094 1223 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777
RL		 1224 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1225
49e8a725 1226 /* ARMv8.3 javascript conversion instruction. */
6b0dd094 1227 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
49e8a725
SN		 1228 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1229
6b0dd094 1230 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 1231};
1232
16980d0b
JB		 1233/* Neon opcode table: This does not encode the top byte -- that is
1234 checked by the print_insn_neon routine, as it depends on whether we are
1235 doing thumb32 or arm32 disassembly. */
1236
1237/* print_insn_neon recognizes the following format control codes:
1238
1239 %% %
1240
c22aaad1 1241 %c print condition code
e2efe87d
MGD		 1242 %u print condition code (unconditional in ARM mode,
1243 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 1244 %A print v{st,ld}[1234] operands
1245 %B print v{st,ld}[1234] any one operands
1246 %C print v{st,ld}[1234] single->all operands
1247 %D print scalar
1248 %E print vmov, vmvn, vorr, vbic encoded constant
1249 %F print vtbl,vtbx register list
1250
1251 %<bitfield>r print as an ARM register
1252 %<bitfield>d print the bitfield in decimal
1253 %<bitfield>e print the 2^N - bitfield in decimal
1254 %<bitfield>D print as a NEON D register
1255 %<bitfield>Q print as a NEON Q register
1256 %<bitfield>R print as a NEON D or Q register
1257 %<bitfield>Sn print byte scaled width limited by n
1258 %<bitfield>Tn print short scaled width limited by n
1259 %<bitfield>Un print long scaled width limited by n
43e65147 1260
16980d0b
JB		 1261 %<bitfield>'c print specified char iff bitfield is all ones
1262 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1263 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1264
1265static const struct opcode32 neon_opcodes[] =
1266{
fe56b6ce 1267 /* Extract. */
823d2571
TG		 1268 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1269 0xf2b00840, 0xffb00850,
1270 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1271 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1272 0xf2b00000, 0xffb00810,
1273 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 1274
9743db03
AV		 1275 /* Data transfer between ARM and NEON registers. */
1276 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1277 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1278 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1279 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1280 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1281 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1282 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1283 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1284 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1285 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1286 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1287 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1288
fe56b6ce 1289 /* Move data element to all lanes. */
823d2571
TG		 1290 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1291 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1292 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1293 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1294 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1295 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 1296
fe56b6ce 1297 /* Table lookup. */
823d2571
TG		 1298 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1299 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1300 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1301 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1302
8e79c3df 1303 /* Half-precision conversions. */
823d2571
TG		 1304 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1305 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1306 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1307 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1308
1309 /* NEON fused multiply add instructions. */
823d2571 1310 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1311 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1312 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1313 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1314 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1315 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1316 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1317 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1318
fe56b6ce 1319 /* Two registers, miscellaneous. */
823d2571
TG		 1320 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1321 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1322 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1323 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1324 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1325 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1326 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1327 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1328 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1329 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1330 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1331 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1332 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1333 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1334 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1335 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1336 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1337 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1338 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1339 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1340 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1341 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1342 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1343 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1344 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1345 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1346 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1347 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1348 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1349 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1350 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1351 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1352 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1353 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1354 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1355 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1356 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1357 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1358 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1359 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1360 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1361 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1362 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1363 0xf3b20300, 0xffb30fd0,
1364 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1365 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1366 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1367 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1368 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1369 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1370 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1371 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1372 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1373 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1374 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1375 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1376 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1377 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1378 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1379 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1380 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1381 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1382 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1383 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1384 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1385 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1386 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1387 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1388 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1389 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1390 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1391 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1392 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1393 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1394 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1395 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1396 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1397 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1398 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1399 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1400 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1401 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1402 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1403 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1404 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1405 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1406 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1407 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1408 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1409 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1410 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1411 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301 1412 0xf3bb0600, 0xffbf0e10,
823d2571 1413 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1414 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1415 0xf3b70600, 0xffbf0e10,
1416 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
16980d0b 1417
fe56b6ce 1418 /* Three registers of the same length. */
823d2571
TG		 1419 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1420 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1421 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1422 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1423 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1424 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1425 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1426 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1427 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1428 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1429 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1430 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1431 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1432 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1433 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1434 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1435 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1436 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1437 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1438 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1439 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1440 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1441 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1442 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1443 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1444 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1445 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1446 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1447 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1448 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1449 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1450 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1451 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1452 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1453 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1454 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1456 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1457 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1458 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1459 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1460 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1462 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1463 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1464 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1466 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1467 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1468 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1470 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1471 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1472 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1474 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1475 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1476 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1478 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1479 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1480 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1482 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1483 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1484 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1486 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1487 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1488 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1489 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1490 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1491 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1492 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1494 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1495 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1496 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1498 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1499 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1500 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1502 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1503 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1504 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1506 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1507 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1508 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1510 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1511 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1512 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1514 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1515 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1516 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1517 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1518 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1519 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1520 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1521 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1522 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1523 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1524 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1525 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1526 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1527 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1528 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1530 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1531 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1532 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1533 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1534 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1535 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1536 0xf2000b00, 0xff800f10,
1537 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1538 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1539 0xf2000b10, 0xff800f10,
1540 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1541 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1542 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1543 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1544 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1545 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1546 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1547 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1548 0xf3000b00, 0xff800f10,
1549 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1550 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1551 0xf2000000, 0xfe800f10,
1552 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1553 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1554 0xf2000010, 0xfe800f10,
1555 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1556 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1557 0xf2000100, 0xfe800f10,
1558 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1559 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1560 0xf2000200, 0xfe800f10,
1561 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1562 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1563 0xf2000210, 0xfe800f10,
1564 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1565 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1566 0xf2000300, 0xfe800f10,
1567 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1568 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1569 0xf2000310, 0xfe800f10,
1570 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1571 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1572 0xf2000400, 0xfe800f10,
1573 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1574 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1575 0xf2000410, 0xfe800f10,
1576 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1577 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1578 0xf2000500, 0xfe800f10,
1579 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1580 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1581 0xf2000510, 0xfe800f10,
1582 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1583 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1584 0xf2000600, 0xfe800f10,
1585 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1586 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1587 0xf2000610, 0xfe800f10,
1588 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1589 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1590 0xf2000700, 0xfe800f10,
1591 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1592 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1593 0xf2000710, 0xfe800f10,
1594 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1595 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1596 0xf2000910, 0xfe800f10,
1597 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1598 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1599 0xf2000a00, 0xfe800f10,
1600 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1601 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1602 0xf2000a10, 0xfe800f10,
1603 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1604 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1605 0xf3000b10, 0xff800f10,
1606 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1607 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1608 0xf3000c10, 0xff800f10,
1609 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1610
fe56b6ce 1611 /* One register and an immediate value. */
823d2571
TG		 1612 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1613 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1614 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1615 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1616 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1617 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1618 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1619 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1621 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1622 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1623 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1624 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1625 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1626 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1627 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1628 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1629 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1630 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1631 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1632 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1633 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1634 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1635 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1636 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1637 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1638
fe56b6ce 1639 /* Two registers and a shift amount. */
823d2571
TG		 1640 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1641 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1642 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1643 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1644 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1645 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1646 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1647 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1648 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1649 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1650 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1651 0xf2880950, 0xfeb80fd0,
1652 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1653 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1654 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1655 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1656 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1658 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1659 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1660 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1661 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1662 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1663 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1664 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1665 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1666 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1667 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1668 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1669 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1670 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1671 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1672 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1673 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1674 0xf2900950, 0xfeb00fd0,
1675 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1676 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1677 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1678 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1679 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1680 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1681 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1682 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1683 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1685 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1687 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1688 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1689 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1691 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1692 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1693 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1694 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1695 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1696 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1697 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1698 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1699 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1700 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1701 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1702 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1703 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1704 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1705 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1706 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1707 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1708 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1709 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1710 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1711 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1712 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1713 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1714 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1715 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1716 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1717 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1718 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1719 0xf2a00950, 0xfea00fd0,
1720 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1721 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1722 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1723 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1724 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1725 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1726 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1727 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1728 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1729 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1730 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1731 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1732 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1733 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1734 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1735 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1736 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1737 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1738 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1739 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1740 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1741 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1742 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1743 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1744 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1745 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1746 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1747 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1748 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1749 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1750 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1751 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1752 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1753 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1754 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1755 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1756 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1757 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1758 0xf2a00e10, 0xfea00e90,
1759 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
cc933301
JW		 1760 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1761 0xf2a00c10, 0xfea00e90,
1762 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 1763
fe56b6ce 1764 /* Three registers of different lengths. */
823d2571
TG		 1765 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1766 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1767 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1768 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1769 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1770 0xf2800400, 0xff800f50,
1771 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1772 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1773 0xf2800600, 0xff800f50,
1774 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1775 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1776 0xf2800900, 0xff800f50,
1777 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1778 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1779 0xf2800b00, 0xff800f50,
1780 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1781 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1782 0xf2800d00, 0xff800f50,
1783 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1784 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1785 0xf3800400, 0xff800f50,
1786 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1787 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1788 0xf3800600, 0xff800f50,
1789 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1790 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1791 0xf2800000, 0xfe800f50,
1792 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1793 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1794 0xf2800100, 0xfe800f50,
1795 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1796 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1797 0xf2800200, 0xfe800f50,
1798 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1799 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1800 0xf2800300, 0xfe800f50,
1801 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1802 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1803 0xf2800500, 0xfe800f50,
1804 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1805 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1806 0xf2800700, 0xfe800f50,
1807 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1808 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1809 0xf2800800, 0xfe800f50,
1810 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1811 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1812 0xf2800a00, 0xfe800f50,
1813 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1814 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1815 0xf2800c00, 0xfe800f50,
1816 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 1817
fe56b6ce 1818 /* Two registers and a scalar. */
823d2571
TG		 1819 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1820 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1821 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1822 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1823 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1824 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1825 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1826 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1827 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1828 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1829 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1830 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1831 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1832 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1833 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1834 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1835 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1836 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1837 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1838 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1839 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1840 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1841 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1842 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1843 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1844 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1845 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1846 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1847 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1848 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1849 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1850 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1851 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1852 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1853 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1854 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1855 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1856 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1857 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1858 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1859 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1860 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1861 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1862 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1863 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1864 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1865 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1866 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1867 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1868 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1869 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1870 0xf2800240, 0xfe800f50,
1871 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1872 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1873 0xf2800640, 0xfe800f50,
1874 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1875 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1876 0xf2800a40, 0xfe800f50,
1877 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 1878 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1879 0xf2800e40, 0xff800f50,
1880 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1881 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1882 0xf2800f40, 0xff800f50,
1883 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1884 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1885 0xf3800e40, 0xff800f50,
1886 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1887 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1888 0xf3800f40, 0xff800f50,
1889 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1890 },
16980d0b 1891
fe56b6ce 1892 /* Element and structure load/store. */
823d2571
TG		 1893 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1894 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1895 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1896 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1897 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1898 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1899 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1900 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1901 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1902 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1903 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1904 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1905 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1906 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1907 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1908 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1909 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1910 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1911 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1912 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1913 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1914 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1915 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1916 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1917 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1918 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1919 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1920 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1921 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1922 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1923 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1924 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1925 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1926 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1927 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1928 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1929 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1930 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1931
1932 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 1933};
1934
73cd51e5
AV		 1935/* mve opcode table. */
1936
1937/* print_insn_mve recognizes the following format control codes:
1938
1939 %% %
1940
ef1576a1
AV		 1941 %a print '+' or '-' or imm offset in vldr[bhwd] and
1942 vstr[bhwd]
9743db03 1943 %c print condition code
aef6d006
AV		 1944 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
1945 %u print 'U' (unsigned) or 'S' for various mve instructions
143275ea 1946 %i print MVE predicate(s) for vpt and vpst
bf0b396d 1947 %m print rounding mode for vcvt and vrint
143275ea 1948 %n print vector comparison code for predicated instruction
bf0b396d 1949 %s print size for various vcvt instructions
143275ea
AV		 1950 %v print vector predicate for instruction in predicated
1951 block
ef1576a1 1952 %o print offset scaled for vldr[hwd] and vstr[hwd]
04d54ace
AV		 1953 %w print writeback mode for MVE v{st,ld}[24]
1954 %B print v{st,ld}[24] any one operands
c507f10b
AV		 1955 %E print vmov, vmvn, vorr, vbic encoded constant
1956 %N print generic index for vmov
14925797 1957 %T print bottom ('b') or top ('t') of source register
d3b63143 1958 %X print exchange field in vmla* instructions
04d54ace 1959
9743db03 1960 %<bitfield>r print as an ARM register
04d54ace 1961 %<bitfield>d print the bitfield in decimal
d3b63143 1962 %<bitfield>A print accumulate or not
143275ea 1963 %<bitfield>Q print as a MVE Q register
c507f10b 1964 %<bitfield>F print as a MVE S register
143275ea
AV		 1965 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
1966 UNPREDICTABLE
1967 %<bitfield>s print size for vector predicate & non VMOV instructions
ef1576a1 1968 %<bitfield>i print immediate for vstr/vldr reg +/- imm
1c8f2df8 1969 %<bitfield>h print high half of 64-bit destination reg
bf0b396d 1970 %<bitfield>k print immediate for vector conversion instruction
1c8f2df8 1971 %<bitfield>l print low half of 64-bit destination reg
897b9bbc 1972 %<bitfield>o print rotate value for vcmul
1c8f2df8 1973 %<bitfield>u print immediate value for vddup/vdwdup
c507f10b 1974 %<bitfield>x print the bitfield in hex.
1c8f2df8 1975 */
73cd51e5
AV		 1976
1977static const struct mopcode32 mve_opcodes[] =
1978{
143275ea
AV		 1979 /* MVE. */
1980
1981 {ARM_FEATURE_COPROC (FPU_MVE),
1982 MVE_VPST,
1983 0xfe310f4d, 0xffbf1fff,
1984 "vpst%i"
1985 },
1986
1987 /* Floating point VPT T1. */
1988 {ARM_FEATURE_COPROC (FPU_MVE_FP),
1989 MVE_VPT_FP_T1,
1990 0xee310f00, 0xefb10f50,
1991 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
1992 /* Floating point VPT T2. */
1993 {ARM_FEATURE_COPROC (FPU_MVE_FP),
1994 MVE_VPT_FP_T2,
1995 0xee310f40, 0xefb10f50,
1996 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
1997
1998 /* Vector VPT T1. */
1999 {ARM_FEATURE_COPROC (FPU_MVE),
2000 MVE_VPT_VEC_T1,
2001 0xfe010f00, 0xff811f51,
2002 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2003 /* Vector VPT T2. */
2004 {ARM_FEATURE_COPROC (FPU_MVE),
2005 MVE_VPT_VEC_T2,
2006 0xfe010f01, 0xff811f51,
2007 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2008 /* Vector VPT T3. */
2009 {ARM_FEATURE_COPROC (FPU_MVE),
2010 MVE_VPT_VEC_T3,
2011 0xfe011f00, 0xff811f50,
2012 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2013 /* Vector VPT T4. */
2014 {ARM_FEATURE_COPROC (FPU_MVE),
2015 MVE_VPT_VEC_T4,
2016 0xfe010f40, 0xff811f70,
2017 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2018 /* Vector VPT T5. */
2019 {ARM_FEATURE_COPROC (FPU_MVE),
2020 MVE_VPT_VEC_T5,
2021 0xfe010f60, 0xff811f70,
2022 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2023 /* Vector VPT T6. */
2024 {ARM_FEATURE_COPROC (FPU_MVE),
2025 MVE_VPT_VEC_T6,
2026 0xfe011f40, 0xff811f50,
2027 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2028
c507f10b
AV		 2029 /* Vector VBIC immediate. */
2030 {ARM_FEATURE_COPROC (FPU_MVE),
2031 MVE_VBIC_IMM,
2032 0xef800070, 0xefb81070,
2033 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2034
2035 /* Vector VBIC register. */
2036 {ARM_FEATURE_COPROC (FPU_MVE),
2037 MVE_VBIC_REG,
2038 0xef100150, 0xffb11f51,
2039 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2040
d3b63143
AV		 2041 /* Vector VADDLV. */
2042 {ARM_FEATURE_COPROC (FPU_MVE),
2043 MVE_VADDLV,
2044 0xee890f00, 0xef8f1fd1,
2045 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2046
2047 /* Vector VADDV. */
2048 {ARM_FEATURE_COPROC (FPU_MVE),
2049 MVE_VADDV,
2050 0xeef10f00, 0xeff31fd1,
2051 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2052
897b9bbc
AV		 2053 /* Vector VCADD floating point. */
2054 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2055 MVE_VCADD_FP,
2056 0xfc800840, 0xfea11f51,
2057 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2058
2059 /* Vector VCADD. */
2060 {ARM_FEATURE_COPROC (FPU_MVE),
2061 MVE_VCADD_VEC,
2062 0xfe000f00, 0xff810f51,
2063 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2064
2065 /* Vector VCMLA. */
2066 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2067 MVE_VCMLA_FP,
2068 0xfc200840, 0xfe211f51,
2069 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2070
143275ea
AV		 2071 /* Vector VCMP floating point T1. */
2072 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2073 MVE_VCMP_FP_T1,
2074 0xee310f00, 0xeff1ef50,
2075 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2076
2077 /* Vector VCMP floating point T2. */
2078 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2079 MVE_VCMP_FP_T2,
2080 0xee310f40, 0xeff1ef50,
2081 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2082
2083 /* Vector VCMP T1. */
2084 {ARM_FEATURE_COPROC (FPU_MVE),
2085 MVE_VCMP_VEC_T1,
2086 0xfe010f00, 0xffc1ff51,
2087 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2088 /* Vector VCMP T2. */
2089 {ARM_FEATURE_COPROC (FPU_MVE),
2090 MVE_VCMP_VEC_T2,
2091 0xfe010f01, 0xffc1ff51,
2092 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2093 /* Vector VCMP T3. */
2094 {ARM_FEATURE_COPROC (FPU_MVE),
2095 MVE_VCMP_VEC_T3,
2096 0xfe011f00, 0xffc1ff50,
2097 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2098 /* Vector VCMP T4. */
2099 {ARM_FEATURE_COPROC (FPU_MVE),
2100 MVE_VCMP_VEC_T4,
2101 0xfe010f40, 0xffc1ff70,
2102 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2103 /* Vector VCMP T5. */
2104 {ARM_FEATURE_COPROC (FPU_MVE),
2105 MVE_VCMP_VEC_T5,
2106 0xfe010f60, 0xffc1ff70,
2107 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2108 /* Vector VCMP T6. */
2109 {ARM_FEATURE_COPROC (FPU_MVE),
2110 MVE_VCMP_VEC_T6,
2111 0xfe011f40, 0xffc1ff50,
2112 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2113
9743db03
AV		 2114 /* Vector VDUP. */
2115 {ARM_FEATURE_COPROC (FPU_MVE),
2116 MVE_VDUP,
2117 0xeea00b10, 0xffb10f5f,
2118 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2119
2120 /* Vector VEOR. */
2121 {ARM_FEATURE_COPROC (FPU_MVE),
2122 MVE_VEOR,
2123 0xff000150, 0xffd11f51,
2124 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2125
2126 /* Vector VFMA, vector * scalar. */
2127 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2128 MVE_VFMA_FP_SCALAR,
2129 0xee310e40, 0xefb11f70,
2130 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2131
2132 /* Vector VFMA floating point. */
2133 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2134 MVE_VFMA_FP,
2135 0xef000c50, 0xffa11f51,
2136 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2137
2138 /* Vector VFMS floating point. */
2139 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2140 MVE_VFMS_FP,
2141 0xef200c50, 0xffa11f51,
2142 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2143
2144 /* Vector VFMAS, vector * scalar. */
2145 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2146 MVE_VFMAS_FP_SCALAR,
2147 0xee311e40, 0xefb11f70,
2148 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2149
2150 /* Vector VHADD T1. */
2151 {ARM_FEATURE_COPROC (FPU_MVE),
2152 MVE_VHADD_T1,
2153 0xef000040, 0xef811f51,
2154 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2155
2156 /* Vector VHADD T2. */
2157 {ARM_FEATURE_COPROC (FPU_MVE),
2158 MVE_VHADD_T2,
2159 0xee000f40, 0xef811f70,
2160 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2161
2162 /* Vector VHSUB T1. */
2163 {ARM_FEATURE_COPROC (FPU_MVE),
2164 MVE_VHSUB_T1,
2165 0xef000240, 0xef811f51,
2166 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2167
2168 /* Vector VHSUB T2. */
2169 {ARM_FEATURE_COPROC (FPU_MVE),
2170 MVE_VHSUB_T2,
2171 0xee001f40, 0xef811f70,
2172 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2173
897b9bbc
AV		 2174 /* Vector VCMUL. */
2175 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2176 MVE_VCMUL_FP,
2177 0xee300e00, 0xefb10f50,
2178 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2179
9743db03
AV		 2180 /* Vector VDUP. */
2181 {ARM_FEATURE_COPROC (FPU_MVE),
2182 MVE_VDUP,
2183 0xeea00b10, 0xffb10f5f,
2184 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2185
2186 /* Vector VRHADD. */
2187 {ARM_FEATURE_COPROC (FPU_MVE),
2188 MVE_VRHADD,
2189 0xef000140, 0xef811f51,
2190 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2191
bf0b396d
AV		 2192 /* Vector VCVT. */
2193 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2194 MVE_VCVT_FP_FIX_VEC,
2195 0xef800c50, 0xef801cd1,
2196 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2197
2198 /* Vector VCVT. */
2199 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2200 MVE_VCVT_BETWEEN_FP_INT,
2201 0xffb30640, 0xffb31e51,
2202 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2203
2204 /* Vector VCVT between single and half-precision float, bottom half. */
2205 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2206 MVE_VCVT_FP_HALF_FP,
2207 0xee3f0e01, 0xefbf1fd1,
2208 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2209
2210 /* Vector VCVT between single and half-precision float, top half. */
2211 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2212 MVE_VCVT_FP_HALF_FP,
2213 0xee3f1e01, 0xefbf1fd1,
2214 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2215
2216 /* Vector VCVT. */
2217 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2218 MVE_VCVT_FROM_FP_TO_INT,
2219 0xffb30040, 0xffb31c51,
2220 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2221
1c8f2df8
AV		 2222 /* Vector VDDUP. */
2223 {ARM_FEATURE_COPROC (FPU_MVE),
2224 MVE_VDDUP,
2225 0xee011f6e, 0xff811f7e,
2226 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2227
2228 /* Vector VDWDUP. */
2229 {ARM_FEATURE_COPROC (FPU_MVE),
2230 MVE_VDWDUP,
2231 0xee011f60, 0xff811f70,
2232 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2233
897b9bbc
AV		 2234 /* Vector VHCADD. */
2235 {ARM_FEATURE_COPROC (FPU_MVE),
2236 MVE_VHCADD,
2237 0xee000f00, 0xff810f51,
2238 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2239
1c8f2df8
AV		 2240 /* Vector VIWDUP. */
2241 {ARM_FEATURE_COPROC (FPU_MVE),
2242 MVE_VIWDUP,
2243 0xee010f60, 0xff811f70,
2244 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2245
2246 /* Vector VIDUP. */
2247 {ARM_FEATURE_COPROC (FPU_MVE),
2248 MVE_VIDUP,
2249 0xee010f6e, 0xff811f7e,
2250 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2251
04d54ace
AV		 2252 /* Vector VLD2. */
2253 {ARM_FEATURE_COPROC (FPU_MVE),
2254 MVE_VLD2,
2255 0xfc901e00, 0xff901e5f,
2256 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2257
2258 /* Vector VLD4. */
2259 {ARM_FEATURE_COPROC (FPU_MVE),
2260 MVE_VLD4,
2261 0xfc901e01, 0xff901e1f,
2262 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2263
ef1576a1
AV		 2264 /* Vector VLDRB gather load. */
2265 {ARM_FEATURE_COPROC (FPU_MVE),
2266 MVE_VLDRB_GATHER_T1,
2267 0xec900e00, 0xefb01e50,
2268 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2269
2270 /* Vector VLDRH gather load. */
2271 {ARM_FEATURE_COPROC (FPU_MVE),
2272 MVE_VLDRH_GATHER_T2,
2273 0xec900e10, 0xefb01e50,
2274 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2275
2276 /* Vector VLDRW gather load. */
2277 {ARM_FEATURE_COPROC (FPU_MVE),
2278 MVE_VLDRW_GATHER_T3,
2279 0xfc900f40, 0xffb01fd0,
2280 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2281
2282 /* Vector VLDRD gather load. */
2283 {ARM_FEATURE_COPROC (FPU_MVE),
2284 MVE_VLDRD_GATHER_T4,
2285 0xec900fd0, 0xefb01fd0,
2286 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2287
2288 /* Vector VLDRW gather load. */
2289 {ARM_FEATURE_COPROC (FPU_MVE),
2290 MVE_VLDRW_GATHER_T5,
2291 0xfd101e00, 0xff111f00,
2292 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2293
2294 /* Vector VLDRD gather load, variant T6. */
2295 {ARM_FEATURE_COPROC (FPU_MVE),
2296 MVE_VLDRD_GATHER_T6,
2297 0xfd101f00, 0xff111f00,
2298 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2299
aef6d006
AV		 2300 /* Vector VLDRB. */
2301 {ARM_FEATURE_COPROC (FPU_MVE),
2302 MVE_VLDRB_T1,
2303 0xec100e00, 0xee581e00,
2304 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2305
2306 /* Vector VLDRH. */
2307 {ARM_FEATURE_COPROC (FPU_MVE),
2308 MVE_VLDRH_T2,
2309 0xec180e00, 0xee581e00,
2310 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2311
2312 /* Vector VLDRB unsigned, variant T5. */
2313 {ARM_FEATURE_COPROC (FPU_MVE),
2314 MVE_VLDRB_T5,
2315 0xec101e00, 0xfe101f80,
2316 "vldrb%v.u8\t%13-15,22Q, %d"},
2317
2318 /* Vector VLDRH unsigned, variant T6. */
2319 {ARM_FEATURE_COPROC (FPU_MVE),
2320 MVE_VLDRH_T6,
2321 0xec101e80, 0xfe101f80,
2322 "vldrh%v.u16\t%13-15,22Q, %d"},
2323
2324 /* Vector VLDRW unsigned, variant T7. */
2325 {ARM_FEATURE_COPROC (FPU_MVE),
2326 MVE_VLDRW_T7,
2327 0xec101f00, 0xfe101f80,
2328 "vldrw%v.u32\t%13-15,22Q, %d"},
2329
d3b63143
AV		 2330 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2331 opcode aliasing. */
2332 {ARM_FEATURE_COPROC (FPU_MVE),
2333 MVE_VMLALDAV,
2334 0xee801e00, 0xef801f51,
2335 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2336
2337 {ARM_FEATURE_COPROC (FPU_MVE),
2338 MVE_VMLALDAV,
2339 0xee800e00, 0xef801f51,
2340 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2341
2342 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2343 {ARM_FEATURE_COPROC (FPU_MVE),
2344 MVE_VMLADAV_T1,
2345 0xeef00e00, 0xeff01f51,
2346 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2347
2348 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2349 {ARM_FEATURE_COPROC (FPU_MVE),
2350 MVE_VMLADAV_T2,
2351 0xeef00f00, 0xeff11f51,
2352 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2353
2354 /* Vector VMLADAV T1 variant. */
2355 {ARM_FEATURE_COPROC (FPU_MVE),
2356 MVE_VMLADAV_T1,
2357 0xeef01e00, 0xeff01f51,
2358 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2359
2360 /* Vector VMLADAV T2 variant. */
2361 {ARM_FEATURE_COPROC (FPU_MVE),
2362 MVE_VMLADAV_T2,
2363 0xeef01f00, 0xeff11f51,
2364 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2365
2366 /* Vector VMLAS. */
2367 {ARM_FEATURE_COPROC (FPU_MVE),
2368 MVE_VMLAS,
2369 0xee011e40, 0xef811f70,
2370 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2371
2372 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2373 opcode aliasing. */
2374 {ARM_FEATURE_COPROC (FPU_MVE),
2375 MVE_VRMLSLDAVH,
2376 0xfe800e01, 0xff810f51,
2377 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2378
2379 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2380 opcdoe aliasing. */
2381 {ARM_FEATURE_COPROC (FPU_MVE),
2382 MVE_VMLSLDAV,
2383 0xee800e01, 0xff800f51,
2384 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2385
2386 /* Vector VMLSDAV T1 Variant. */
2387 {ARM_FEATURE_COPROC (FPU_MVE),
2388 MVE_VMLSDAV_T1,
2389 0xeef00e01, 0xfff00f51,
2390 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2391
2392 /* Vector VMLSDAV T2 Variant. */
2393 {ARM_FEATURE_COPROC (FPU_MVE),
2394 MVE_VMLSDAV_T2,
2395 0xfef00e01, 0xfff10f51,
2396 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2397
c507f10b
AV		 2398 /* Vector VMOV between gpr and half precision register, op == 0. */
2399 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2400 MVE_VMOV_HFP_TO_GP,
2401 0xee000910, 0xfff00f7f,
2402 "vmov.f16\t%7,16-19F, %12-15r"},
2403
2404 /* Vector VMOV between gpr and half precision register, op == 1. */
2405 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2406 MVE_VMOV_HFP_TO_GP,
2407 0xee100910, 0xfff00f7f,
2408 "vmov.f16\t%12-15r, %7,16-19F"},
2409
2410 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2411 MVE_VMOV_GP_TO_VEC_LANE,
2412 0xee000b10, 0xff900f1f,
2413 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2414
2415 /* Vector VORR immediate to vector.
2416 NOTE: MVE_VORR_IMM must appear in the table
2417 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2418 {ARM_FEATURE_COPROC (FPU_MVE),
2419 MVE_VORR_IMM,
2420 0xef800050, 0xefb810f0,
2421 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2422
2423 /* Vector VMOV immediate to vector,
2424 cmode == 11x1 -> VMVN which is UNDEFINED
2425 for such a cmode. */
2426 {ARM_FEATURE_COPROC (FPU_MVE),
2427 MVE_VMVN_IMM, 0xef800d50, 0xefb81dd0, UNDEFINED_INSTRUCTION},
2428
2429 /* Vector VMOV immediate to vector. */
2430 {ARM_FEATURE_COPROC (FPU_MVE),
2431 MVE_VMOV_IMM_TO_VEC,
2432 0xef800050, 0xefb810d0,
2433 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2434
2435 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2436 {ARM_FEATURE_COPROC (FPU_MVE),
2437 MVE_VMOV2_VEC_LANE_TO_GP,
2438 0xec000f00, 0xffb01ff0,
2439 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2440
2441 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2442 {ARM_FEATURE_COPROC (FPU_MVE),
2443 MVE_VMOV2_VEC_LANE_TO_GP,
2444 0xec000f10, 0xffb01ff0,
2445 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2446
2447 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2448 {ARM_FEATURE_COPROC (FPU_MVE),
2449 MVE_VMOV2_GP_TO_VEC_LANE,
2450 0xec100f00, 0xffb01ff0,
2451 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2452
2453 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2454 {ARM_FEATURE_COPROC (FPU_MVE),
2455 MVE_VMOV2_GP_TO_VEC_LANE,
2456 0xec100f10, 0xffb01ff0,
2457 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2458
2459 /* Vector VMOV Vector lane to gpr. */
2460 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2461 MVE_VMOV_VEC_LANE_TO_GP,
2462 0xee100b10, 0xff100f1f,
2463 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2464
14925797
AV		 2465 /* Vector VMOVL long. */
2466 {ARM_FEATURE_COPROC (FPU_MVE),
2467 MVE_VMOVL,
2468 0xeea00f40, 0xefa70fd1,
2469 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2470
2471 /* Vector VMOV and narrow. */
2472 {ARM_FEATURE_COPROC (FPU_MVE),
2473 MVE_VMOVN,
2474 0xfe310e81, 0xffb30fd1,
2475 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2476
c507f10b
AV		 2477 /* Floating point move extract. */
2478 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2479 MVE_VMOVX,
2480 0xfeb00a40, 0xffbf0fd0,
2481 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2482
14925797
AV		 2483 /* Vector VMULL integer. */
2484 {ARM_FEATURE_COPROC (FPU_MVE),
2485 MVE_VMULL_INT,
2486 0xee010e00, 0xef810f51,
2487 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2488
2489 /* Vector VMULL polynomial. */
2490 {ARM_FEATURE_COPROC (FPU_MVE),
2491 MVE_VMULL_POLY,
2492 0xee310e00, 0xefb10f51,
2493 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2494
c507f10b
AV		 2495 /* Vector VMVN immediate to vector. */
2496 {ARM_FEATURE_COPROC (FPU_MVE),
2497 MVE_VMVN_IMM,
2498 0xef800070, 0xefb810f0,
2499 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2500
2501 /* Vector VMVN register. */
2502 {ARM_FEATURE_COPROC (FPU_MVE),
2503 MVE_VMVN_REG,
2504 0xffb005c0, 0xffbf1fd1,
2505 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2506
2507 /* Vector VORN, vector bitwise or not. */
2508 {ARM_FEATURE_COPROC (FPU_MVE),
2509 MVE_VORN,
2510 0xef300150, 0xffb11f51,
2511 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2512
2513 /* Vector VORR register. */
2514 {ARM_FEATURE_COPROC (FPU_MVE),
2515 MVE_VORR_REG,
2516 0xef200150, 0xffb11f51,
2517 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2518
14925797
AV		 2519 /* Vector VQDMULL T1 variant. */
2520 {ARM_FEATURE_COPROC (FPU_MVE),
2521 MVE_VQDMULL_T1,
2522 0xee300f01, 0xefb10f51,
2523 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2524
2525 /* Vector VQDMULL T2 variant. */
2526 {ARM_FEATURE_COPROC (FPU_MVE),
2527 MVE_VQDMULL_T2,
2528 0xee300f60, 0xefb10f70,
2529 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2530
2531 /* Vector VQMOVN. */
2532 {ARM_FEATURE_COPROC (FPU_MVE),
2533 MVE_VQMOVN,
2534 0xee330e01, 0xefb30fd1,
2535 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
2536
2537 /* Vector VQMOVUN. */
2538 {ARM_FEATURE_COPROC (FPU_MVE),
2539 MVE_VQMOVUN,
2540 0xee310e81, 0xffb30fd1,
2541 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2542
d3b63143
AV		 2543 /* Vector VQDMLADH. */
2544 {ARM_FEATURE_COPROC (FPU_MVE),
2545 MVE_VQDMLADH,
2546 0xee000e00, 0xff810f51,
2547 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2548
2549 /* Vector VQRDMLADH. */
2550 {ARM_FEATURE_COPROC (FPU_MVE),
2551 MVE_VQRDMLADH,
2552 0xee000e01, 0xff810f51,
2553 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2554
2555 /* Vector VQDMLAH. */
2556 {ARM_FEATURE_COPROC (FPU_MVE),
2557 MVE_VQDMLAH,
2558 0xee000e60, 0xef811f70,
2559 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2560
2561 /* Vector VQRDMLAH. */
2562 {ARM_FEATURE_COPROC (FPU_MVE),
2563 MVE_VQRDMLAH,
2564 0xee000e40, 0xef811f70,
2565 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2566
2567 /* Vector VQDMLASH. */
2568 {ARM_FEATURE_COPROC (FPU_MVE),
2569 MVE_VQDMLASH,
2570 0xee001e60, 0xef811f70,
2571 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2572
2573 /* Vector VQRDMLASH. */
2574 {ARM_FEATURE_COPROC (FPU_MVE),
2575 MVE_VQRDMLASH,
2576 0xee001e40, 0xef811f70,
2577 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2578
2579 /* Vector VQDMLSDH. */
2580 {ARM_FEATURE_COPROC (FPU_MVE),
2581 MVE_VQDMLSDH,
2582 0xfe000e00, 0xff810f51,
2583 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2584
2585 /* Vector VQRDMLSDH. */
2586 {ARM_FEATURE_COPROC (FPU_MVE),
2587 MVE_VQRDMLSDH,
2588 0xfe000e01, 0xff810f51,
2589 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2590
2591 /* Vector VQDMULH T1 variant. */
2592 {ARM_FEATURE_COPROC (FPU_MVE),
2593 MVE_VQDMULH_T1,
2594 0xef000b40, 0xff811f51,
2595 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2596
2597 /* Vector VQRDMULH T2 variant. */
2598 {ARM_FEATURE_COPROC (FPU_MVE),
2599 MVE_VQRDMULH_T2,
2600 0xff000b40, 0xff811f51,
2601 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2602
2603 /* Vector VQDMULH T3 variant. */
2604 {ARM_FEATURE_COPROC (FPU_MVE),
2605 MVE_VQDMULH_T3,
2606 0xee010e60, 0xff811f70,
2607 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2608
2609 /* Vector VQRDMULH T4 variant. */
2610 {ARM_FEATURE_COPROC (FPU_MVE),
2611 MVE_VQRDMULH_T4,
2612 0xfe010e60, 0xff811f70,
2613 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2614
bf0b396d
AV		 2615 /* Vector VRINT floating point. */
2616 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2617 MVE_VRINT_FP,
2618 0xffb20440, 0xffb31c51,
2619 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2620
d3b63143
AV		 2621 /* Vector VRMLALDAVH. */
2622 {ARM_FEATURE_COPROC (FPU_MVE),
2623 MVE_VRMLALDAVH,
2624 0xee800f00, 0xef811f51,
2625 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2626
2627 /* Vector VRMLALDAVH. */
2628 {ARM_FEATURE_COPROC (FPU_MVE),
2629 MVE_VRMLALDAVH,
2630 0xee801f00, 0xef811f51,
2631 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2632
04d54ace
AV		 2633 /* Vector VST2 no writeback. */
2634 {ARM_FEATURE_COPROC (FPU_MVE),
2635 MVE_VST2,
2636 0xfc801e00, 0xffb01e5f,
2637 "vst2%5d.%7-8s\t%B, [%16-19r]"},
2638
2639 /* Vector VST2 writeback. */
2640 {ARM_FEATURE_COPROC (FPU_MVE),
2641 MVE_VST2,
2642 0xfca01e00, 0xffb01e5f,
2643 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
2644
2645 /* Vector VST4 no writeback. */
2646 {ARM_FEATURE_COPROC (FPU_MVE),
2647 MVE_VST4,
2648 0xfc801e01, 0xffb01e1f,
2649 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
2650
2651 /* Vector VST4 writeback. */
2652 {ARM_FEATURE_COPROC (FPU_MVE),
2653 MVE_VST4,
2654 0xfca01e01, 0xffb01e1f,
2655 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
2656
ef1576a1
AV		 2657 /* Vector VSTRB scatter store, T1 variant. */
2658 {ARM_FEATURE_COPROC (FPU_MVE),
2659 MVE_VSTRB_SCATTER_T1,
2660 0xec800e00, 0xffb01e50,
2661 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2662
2663 /* Vector VSTRH scatter store, T2 variant. */
2664 {ARM_FEATURE_COPROC (FPU_MVE),
2665 MVE_VSTRH_SCATTER_T2,
2666 0xec800e10, 0xffb01e50,
2667 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2668
2669 /* Vector VSTRW scatter store, T3 variant. */
2670 {ARM_FEATURE_COPROC (FPU_MVE),
2671 MVE_VSTRW_SCATTER_T3,
2672 0xec800e40, 0xffb01e50,
2673 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2674
2675 /* Vector VSTRD scatter store, T4 variant. */
2676 {ARM_FEATURE_COPROC (FPU_MVE),
2677 MVE_VSTRD_SCATTER_T4,
2678 0xec800fd0, 0xffb01fd0,
2679 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2680
2681 /* Vector VSTRW scatter store, T5 variant. */
2682 {ARM_FEATURE_COPROC (FPU_MVE),
2683 MVE_VSTRW_SCATTER_T5,
2684 0xfd001e00, 0xff111f00,
2685 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2686
2687 /* Vector VSTRD scatter store, T6 variant. */
2688 {ARM_FEATURE_COPROC (FPU_MVE),
2689 MVE_VSTRD_SCATTER_T6,
2690 0xfd001f00, 0xff111f00,
2691 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2692
aef6d006
AV		 2693 /* Vector VSTRB. */
2694 {ARM_FEATURE_COPROC (FPU_MVE),
2695 MVE_VSTRB_T1,
2696 0xec000e00, 0xfe581e00,
2697 "vstrb%v.%7-8s\t%13-15Q, %d"},
2698
2699 /* Vector VSTRH. */
2700 {ARM_FEATURE_COPROC (FPU_MVE),
2701 MVE_VSTRH_T2,
2702 0xec080e00, 0xfe581e00,
2703 "vstrh%v.%7-8s\t%13-15Q, %d"},
2704
2705 /* Vector VSTRB variant T5. */
2706 {ARM_FEATURE_COPROC (FPU_MVE),
2707 MVE_VSTRB_T5,
2708 0xec001e00, 0xfe101f80,
2709 "vstrb%v.8\t%13-15,22Q, %d"},
2710
2711 /* Vector VSTRH variant T6. */
2712 {ARM_FEATURE_COPROC (FPU_MVE),
2713 MVE_VSTRH_T6,
2714 0xec001e80, 0xfe101f80,
2715 "vstrh%v.16\t%13-15,22Q, %d"},
2716
2717 /* Vector VSTRW variant T7. */
2718 {ARM_FEATURE_COPROC (FPU_MVE),
2719 MVE_VSTRW_T7,
2720 0xec001f00, 0xfe101f80,
2721 "vstrw%v.32\t%13-15,22Q, %d"},
2722
143275ea
AV		 2723 {ARM_FEATURE_CORE_LOW (0),
2724 MVE_NONE,
2725 0x00000000, 0x00000000, 0}
73cd51e5
AV		 2726};
2727
8f06b2d8
PB		 2728/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
2729 ordered: they must be searched linearly from the top to obtain a correct
2730 match. */
2731
2732/* print_insn_arm recognizes the following format control codes:
2733
2734 %% %
2735
2736 %a print address for ldr/str instruction
2737 %s print address for ldr/str halfword/signextend instruction
c1e26897 2738 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 2739 %b print branch destination
2740 %c print condition code (always bits 28-31)
2741 %m print register mask for ldm/stm instruction
2742 %o print operand2 (immediate or register + shift)
2743 %p print 'p' iff bits 12-15 are 15
2744 %t print 't' iff bit 21 set and bit 24 clear
2745 %B print arm BLX(1) destination
2746 %C print the PSR sub type.
62b3e311
PB		 2747 %U print barrier type.
2748 %P print address for pli instruction.
8f06b2d8
PB		 2749
2750 %<bitfield>r print as an ARM register
9eb6c0f1 2751 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 2752 %<bitfield>R as %r but r15 is UNPREDICTABLE
2753 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
2754 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 2755 %<bitfield>d print the bitfield in decimal
43e65147 2756 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 2757 %<bitfield>x print the bitfield in hex
2758 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 2759
16980d0b
JB		 2760 %<bitfield>'c print specified char iff bitfield is all ones
2761 %<bitfield>`c print specified char iff bitfield is all zeroes
2762 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 2763
8f06b2d8
PB		 2764 %e print arm SMI operand (bits 0..7,8..19).
2765 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 2766 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
2767 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 2768
8f06b2d8
PB		 2769static const struct opcode32 arm_opcodes[] =
2770{
2771 /* ARM instructions. */
823d2571
TG		 2772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2773 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
2774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2775 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
2776
2777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
2778 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
2779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
2780 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
2781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
2782 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
2784 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
2785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
2786 0x00800090, 0x0fa000f0,
2787 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
2789 0x00a00090, 0x0fa000f0,
2790 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 2791
105bde57 2792 /* V8.2 RAS extension instructions. */
4d1464f2 2793 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 2794 0xe320f010, 0xffffffff, "esb"},
2795
53c4b28b 2796 /* V8 instructions. */
823d2571
TG		 2797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2798 0x0320f005, 0x0fffffff, "sevl"},
f7dd2fb2
TC		 2799 /* Defined in V8 but is in NOP space so available to all arch. */
2800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
823d2571 2801 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
4ed7ed8d 2802 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 2803 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 2804 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 2805 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2807 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
2808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2809 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 2810 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2811 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 2812 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2813 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 2814 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2815 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 2816 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2817 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 2818 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2819 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 2820 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2821 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 2822 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2823 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 2824 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2825 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 2826 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2827 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 2828 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 2829 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 2830 /* CRC32 instructions. */
823d2571
TG		 2831 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2832 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
2833 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2834 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
2835 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2836 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
2837 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2838 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
2839 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2840 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
2841 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2842 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 2843
ddfded2f
MW		 2844 /* Privileged Access Never extension instructions. */
2845 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
2846 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
2847
90ec0d68 2848 /* Virtualization Extension instructions. */
823d2571
TG		 2849 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
2850 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 2851
eea54501 2852 /* Integer Divide Extension instructions. */
823d2571
TG		 2853 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
2854 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
2855 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
2856 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 2857
60e5ef9f 2858 /* MP Extension instructions. */
823d2571 2859 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 2860
c597cc3d
SD		 2861 /* Speculation Barriers. */
2862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
2863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
2864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
2865
62b3e311 2866 /* V7 instructions. */
823d2571
TG		 2867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
2868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
2869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
2870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
2871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
2872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
2873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a
AV		 2874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2875 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
62b3e311 2876
c19d1205 2877 /* ARM V6T2 instructions. */
823d2571
TG		 2878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2879 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
2880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2881 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
2882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2883 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2885 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
2886
2887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2888 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
2889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2890 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
2891
ff8646ee 2892 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 2893 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 2894 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2895 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
2896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2897 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
2898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2899 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 2900
f4c65163 2901 /* ARM Security extension instructions. */
823d2571
TG		 2902 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
2903 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 2904
8f06b2d8 2905 /* ARM V6K instructions. */
823d2571
TG		 2906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2907 0xf57ff01f, 0xffffffff, "clrex"},
2908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2909 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
2910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2911 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
2912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2913 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
2914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2915 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
2916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2917 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
2918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2919 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 2920
7fadb25d
SD		 2921 /* ARMv8.5-A instructions. */
2922 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
2923
8f06b2d8 2924 /* ARM V6K NOP hints. */
823d2571
TG		 2925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2926 0x0320f001, 0x0fffffff, "yield%c"},
2927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2928 0x0320f002, 0x0fffffff, "wfe%c"},
2929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2930 0x0320f003, 0x0fffffff, "wfi%c"},
2931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2932 0x0320f004, 0x0fffffff, "sev%c"},
2933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
2934 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 2935
fe56b6ce 2936 /* ARM V6 instructions. */
823d2571
TG		 2937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2938 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
2939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2940 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
2941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2942 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
2943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2944 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
2945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2946 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
2947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2948 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
2949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2950 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
2951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2952 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
2953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2954 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
2955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2956 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
2957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2958 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
2959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2960 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
2961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2962 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
2963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2964 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
2965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2966 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
2967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2968 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
2969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2970 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
2971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2972 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
2973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2974 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
2975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2976 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
2977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2978 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
2979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2980 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
2981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2982 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
2983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2984 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
2985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2986 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
2987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2988 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
2989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2990 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
2991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2992 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
2993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2994 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
2995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2996 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
2997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2998 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
2999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3000 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3002 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3004 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3006 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3008 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3010 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3012 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3014 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3016 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3018 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3020 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3022 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3024 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3026 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3028 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3030 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3032 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3034 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3036 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3038 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3040 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3042 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3044 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3046 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3048 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3050 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3052 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3054 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3056 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3058 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3060 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3062 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3064 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3066 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3068 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3070 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3072 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3074 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3076 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3078 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3080 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3082 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3084 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3086 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3088 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3090 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3092 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3094 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3096 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3098 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3100 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3102 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3104 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3106 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3108 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3110 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3112 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3114 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3116 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3118 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3120 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3122 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3124 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
3125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3126 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3128 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3130 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3132 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3134 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
3135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3136 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
3137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3138 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
3139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3140 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
3141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3142 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3144 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3146 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3148 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3150 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
3151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3152 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3154 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3156 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
3157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3158 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
3159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3160 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
3161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3162 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
3163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3164 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
3165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3166 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
3167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3168 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
3169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3170 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
3171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3172 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3174 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
3175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3176 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
3177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3178 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
3179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3180 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 3181
8f06b2d8 3182 /* V5J instruction. */
823d2571
TG		 3183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
3184 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 3185
8f06b2d8 3186 /* V5 Instructions. */
823d2571
TG		 3187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3188 0xe1200070, 0xfff000f0,
3189 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
3190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3191 0xfa000000, 0xfe000000, "blx\t%B"},
3192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3193 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
3194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3195 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
3196
3197 /* V5E "El Segundo" Instructions. */
3198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3199 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
3200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3201 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
3202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3203 0xf450f000, 0xfc70f000, "pld\t%a"},
3204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3205 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3207 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3209 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3210 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3211 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
3212
3213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3214 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3216 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
3217
3218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3219 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3221 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3223 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3225 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3226
3227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3228 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
3229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3230 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
3231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3232 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
3233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3234 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
3235
3236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3237 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
3238 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3239 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
3240
3241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3242 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
3243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3244 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
3245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3246 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
3247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3248 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 3249
8f06b2d8 3250 /* ARM Instructions. */
823d2571
TG		 3251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3252 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
3253
3254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3255 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
3256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3257 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
3258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3259 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
3260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3261 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
3262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3263 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
3264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3265 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
3266
3267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3268 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
3269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3270 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
3271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3272 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
3273 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3274 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
3275
3276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3277 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
3278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3279 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
3280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3281 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
3282 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3283 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
3284
3285 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3286 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
3287 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3288 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
3289 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3290 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
3291
3292 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3293 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
3294 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3295 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
3296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3297 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
3298
3299 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3300 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
3301 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3302 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
3303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3304 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
3305
3306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3307 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3309 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3310 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3311 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
3312
3313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3314 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
3315 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3316 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
3317 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3318 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
3319
3320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3321 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
3322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3323 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
3324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3325 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
3326
3327 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3328 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3329 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3330 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3331 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3332 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
3333
3334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3335 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3337 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3339 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
3340
3341 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
3342 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
3343 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
3344 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
3345 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
3346 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
3347
3348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3349 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
3350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3351 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
3352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3353 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
3354
3355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 3356 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 3357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 3358 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 3359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 3360 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
823d2571
TG		 3361
3362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3363 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
3364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3365 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
3366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3367 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
3368
3369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3370 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
3371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3372 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
3373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3374 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
3375
3376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3377 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
3378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3379 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
3380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3381 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
3382
3383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3384 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
3385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3386 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
3387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3388 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
3389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3390 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
3391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3392 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
3393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3394 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
3395 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3396 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
3397
3398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3399 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
3400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3401 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
3402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3403 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
3404
3405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3406 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
3407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3408 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
3409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3410 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
3411
3412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3413 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
3414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3415 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
3416
3417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3418 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
3419
3420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3421 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
3422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3423 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
3424
3425 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3426 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3427 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3428 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3429 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3430 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3431 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3432 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3433 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3434 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3435 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3436 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3437 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3438 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3439 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3440 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3441 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3442 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3443 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3444 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3446 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3447 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3448 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3450 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3451 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3452 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3453 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3454 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3455 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3456 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3457 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3458 0x092d0000, 0x0fff0000, "push%c\t%m"},
3459 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3460 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
3461 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3462 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3463
3464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3465 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3467 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3469 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3471 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3473 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3475 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3476 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3477 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3478 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3479 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3480 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3481 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3482 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3483 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3485 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3487 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3489 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3490 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3491 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3493 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3495 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3497 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
3498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3499 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
3500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3501 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3502
3503 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3504 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
3505 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3506 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 3507
3508 /* The rest. */
4ab90a7a
AV		 3509 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3510 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 3511 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3512 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3513 {ARM_FEATURE_CORE_LOW (0),
3514 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 3515};
3516
3517/* print_insn_thumb16 recognizes the following format control codes:
3518
3519 %S print Thumb register (bits 3..5 as high number if bit 6 set)
3520 %D print Thumb register (bits 0..2 as high number if bit 7 set)
3521 %<bitfield>I print bitfield as a signed decimal
3522 (top bit of range being the sign bit)
3523 %N print Thumb register mask (with LR)
3524 %O print Thumb register mask (with PC)
3525 %M print Thumb register mask
3526 %b print CZB's 6-bit unsigned branch destination
3527 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 3528 %c print the condition code
3529 %C print the condition code, or "s" if not conditional
3530 %x print warning if conditional an not at end of IT block"
3531 %X print "\t; unpredictable <IT:code>" if conditional
3532 %I print IT instruction suffix and operands
4547cb56 3533 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 3534 %<bitfield>r print bitfield as an ARM register
3535 %<bitfield>d print bitfield as a decimal
3536 %<bitfield>H print (bitfield * 2) as a decimal
3537 %<bitfield>W print (bitfield * 4) as a decimal
3538 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
3539 %<bitfield>B print Thumb branch destination (signed displacement)
3540 %<bitfield>c print bitfield as a condition code
3541 %<bitnum>'c print specified char iff bit is one
3542 %<bitnum>?ab print a if bit is one else print b. */
3543
3544static const struct opcode16 thumb_opcodes[] =
3545{
3546 /* Thumb instructions. */
3547
16a1fa25
TP		 3548 /* ARMv8-M Security Extensions instructions. */
3549 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
e207bc53 3550 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
16a1fa25 3551
53c4b28b 3552 /* ARM V8 instructions. */
823d2571
TG		 3553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
3554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
ddfded2f 3555 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
53c4b28b 3556
8f06b2d8 3557 /* ARM V6K no-argument instructions. */
823d2571
TG		 3558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
3559 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
3560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
3561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
3562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
3563 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 3564
3565 /* ARM V6T2 instructions. */
ff8646ee
TP		 3566 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3567 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
3568 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3569 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 3570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 3571
3572 /* ARM V6. */
823d2571
TG		 3573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
3574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
3575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
3576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
3577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
3578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
3579 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
3580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
3581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
3582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
3583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 3584
3585 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 3586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
3587 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 3588 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 3589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
3590 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 3591 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 3592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3593 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 3594 /* Format 4. */
823d2571
TG		 3595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
3596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
3597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
3598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
3599 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
3600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
3601 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
3602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
3603 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
3604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
3605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
3606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
3607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
3608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
3609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
3610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 3611 /* format 13 */
823d2571
TG		 3612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
3613 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 3614 /* format 5 */
823d2571
TG		 3615 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
3616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
3617 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
3618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 3619 /* format 14 */
823d2571
TG		 3620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
3621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 3622 /* format 2 */
823d2571
TG		 3623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3624 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
3625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3626 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
3627 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3628 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
3629 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3630 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 3631 /* format 8 */
823d2571
TG		 3632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3633 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
3634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3635 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
3636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3637 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 3638 /* format 7 */
823d2571
TG		 3639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3640 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
3641 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3642 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 3643 /* format 1 */
823d2571
TG		 3644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
3645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3646 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
3647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
3648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 3649 /* format 3 */
823d2571
TG		 3650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
3651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
3652 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
3653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 3654 /* format 6 */
823d2571
TG		 3655 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
3656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3657 0x4800, 0xF800,
3658 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 3659 /* format 9 */
823d2571
TG		 3660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3661 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
3662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3663 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
3664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3665 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
3666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3667 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 3668 /* format 10 */
823d2571
TG		 3669 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3670 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
3671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3672 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 3673 /* format 11 */
823d2571
TG		 3674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3675 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
3676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3677 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 3678 /* format 12 */
823d2571
TG		 3679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3680 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
3681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3682 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 3683 /* format 15 */
823d2571
TG		 3684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
3685 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 3686 /* format 17 */
823d2571 3687 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 3688 /* format 16 */
823d2571
TG		 3689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
3690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
3691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 3692 /* format 18 */
823d2571 3693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 3694
3695 /* The E800 .. FFFF range is unconditionally redirected to the
3696 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
3697 are processed via that table. Thus, we can never encounter a
3698 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 3699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
3700 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 3701};
3702
3703/* Thumb32 opcodes use the same table structure as the ARM opcodes.
3704 We adopt the convention that hw1 is the high 16 bits of .value and
3705 .mask, hw2 the low 16 bits.
3706
3707 print_insn_thumb32 recognizes the following format control codes:
3708
3709 %% %
3710
3711 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
3712 %M print a modified 12-bit immediate (same location)
3713 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
3714 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 3715 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 3716 %S print a possibly-shifted Rm
3717
32a94698 3718 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 3719 %a print the address of a plain load/store
3720 %w print the width and signedness of a core load/store
3721 %m print register mask for ldm/stm
4b5a202f 3722 %n print register mask for clrm
8f06b2d8
PB		 3723
3724 %E print the lsb and width fields of a bfc/bfi instruction
3725 %F print the lsb and width fields of a sbfx/ubfx instruction
e12437dc 3726 %G print a fallback offset for Branch Future instructions
e5d6e09e 3727 %W print an offset for BF instruction
1caf72a5 3728 %Y print an offset for BFL instruction
1889da70 3729 %Z print an offset for BFCSEL instruction
60f993ce
AV		 3730 %Q print an offset for Low Overhead Loop instructions
3731 %P print an offset for Low Overhead Loop end instructions
8f06b2d8
PB		 3732 %b print a conditional branch offset
3733 %B print an unconditional branch offset
3734 %s print the shift field of an SSAT instruction
3735 %R print the rotation field of an SXT instruction
62b3e311
PB		 3736 %U print barrier type.
3737 %P print address for pli instruction.
c22aaad1
PB		 3738 %c print the condition code
3739 %x print warning if conditional an not at end of IT block"
3740 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 3741
3742 %<bitfield>d print bitfield in decimal
f0fba320 3743 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 3744 %<bitfield>W print bitfield*4 in decimal
3745 %<bitfield>r print bitfield as an ARM register
dd5181d5 3746 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
f1c7f421 3747 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
8f06b2d8
PB		 3748 %<bitfield>c print bitfield as a condition code
3749
16980d0b
JB		 3750 %<bitfield>'c print specified char iff bitfield is all ones
3751 %<bitfield>`c print specified char iff bitfield is all zeroes
3752 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 3753
3754 With one exception at the bottom (done because BL and BLX(1) need
3755 to come dead last), this table was machine-sorted first in
3756 decreasing order of number of bits set in the mask, then in
3757 increasing numeric order of mask, then in increasing numeric order
3758 of opcode. This order is not the clearest for a human reader, but
3759 is guaranteed never to catch a special-case bit pattern with a more
3760 general mask, which is important, because this instruction encoding
3761 makes heavy use of special-case bit patterns. */
3762static const struct opcode32 thumb32_opcodes[] =
3763{
4b5a202f
AV		 3764 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
3765 instructions. */
60f993ce
AV		 3766 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3767 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
3768 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3769 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
3770 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3771 0xf02fc001, 0xfffff001, "le\t%P"},
3772 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3773 0xf00fc001, 0xfffff001, "le\tlr, %P"},
3774
4389b29a
AV		 3775 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3776 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
f1c7f421
AV		 3777 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3778 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
65d1bc05
AV		 3779 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3780 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
f1c7f421
AV		 3781 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3782 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
f6b2b12d
AV		 3783 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3784 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4389b29a 3785
4b5a202f
AV		 3786 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3787 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4389b29a 3788
16a1fa25
TP		 3789 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
3790 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4ed7ed8d
TP		 3791 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3792 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
3793 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3794 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
16a1fa25
TP		 3795 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3796 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
3797 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3798 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4ed7ed8d 3799
105bde57 3800 /* ARM V8.2 RAS extension instructions. */
4d1464f2 3801 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 3802 0xf3af8010, 0xffffffff, "esb"},
3803
53c4b28b 3804 /* V8 instructions. */
823d2571
TG		 3805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3806 0xf3af8005, 0xffffffff, "sevl%c.w"},
3807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3808 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
3809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3810 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
3811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3812 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
3813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3814 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
3815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3816 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
3817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3818 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
3819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3820 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
3821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3822 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
3823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3824 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3826 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3828 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
3829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3830 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3832 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3834 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3836 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 3837
dd5181d5 3838 /* CRC32 instructions. */
823d2571 3839 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 3840 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
823d2571 3841 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 3842 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
823d2571 3843 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 3844 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
823d2571 3845 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 3846 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
823d2571 3847 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 3848 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
823d2571 3849 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 3850 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
dd5181d5 3851
c597cc3d
SD		 3852 /* Speculation Barriers. */
3853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
3854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
3855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
3856
62b3e311 3857 /* V7 instructions. */
823d2571
TG		 3858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
3859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
3860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
3861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
3862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
3863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
3864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
3865 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
3866 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
3867 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
3868 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 3869
90ec0d68 3870 /* Virtualization Extension instructions. */
823d2571 3871 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 3872 /* We skip ERET as that is SUBS pc, lr, #0. */
3873
60e5ef9f 3874 /* MP Extension instructions. */
823d2571 3875 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 3876
f4c65163 3877 /* Security extension instructions. */
823d2571 3878 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 3879
7fadb25d
SD		 3880 /* ARMv8.5-A instructions. */
3881 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
3882
8f06b2d8 3883 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 3884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
3885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
3886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
3887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
3888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
3889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3890 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
3891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
3892
ff8646ee 3893 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3894 0xf3bf8f2f, 0xffffffff, "clrex%c"},
3895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3896 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
3897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3898 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
3899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3900 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
3901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3902 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
3903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3904 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
3905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3906 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
3907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3908 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
3909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3910 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
3911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3912 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
3913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3914 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
3915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3916 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
3917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3918 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
3919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3920 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 3921 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 3922 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 3923 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3924 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
3925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3926 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
3927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3928 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
3929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3930 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
3931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3932 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
3933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3934 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
3935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3936 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
3937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3938 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
3939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3940 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 3941 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3942 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
3943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3944 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
3945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3946 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
3947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3948 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
3949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3950 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
3951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3952 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
3953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3954 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
3955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3956 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
3957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3958 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
3959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3960 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
3961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3962 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
3963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3964 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
3965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3966 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
3967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3968 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
3969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3970 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
3971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3972 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
3973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3974 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
3975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3976 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
3977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3978 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
3979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3980 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
3981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3982 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
3983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3984 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
3985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3986 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
3987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3988 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
3989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3990 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
3991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3992 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
3993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3994 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
3995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3996 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
3997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3998 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
3999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4000 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4002 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4004 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4006 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4008 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4010 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4012 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4014 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4016 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4018 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4020 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4022 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4024 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4026 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4028 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4030 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4032 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4034 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4036 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4038 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4040 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4042 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4044 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4046 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4048 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 4049 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4050 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 4052 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 4053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4054 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4056 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4058 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4060 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4062 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4064 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4066 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4068 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4070 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4072 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4074 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4076 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4078 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4080 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4082 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4084 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4086 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4088 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4090 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4092 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4094 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4096 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4098 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4100 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4102 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4104 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4106 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4108 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4110 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4112 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4114 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4116 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 4117 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4118 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
4119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4120 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
4121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4122 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
4123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4124 0xf810f000, 0xff70f000, "pld%c\t%a"},
4125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4126 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4128 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4130 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4132 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4134 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4136 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4138 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4140 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
4141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4142 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
4143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4144 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
4145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4146 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
4147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4148 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
4149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4150 0xfb100000, 0xfff000c0,
4151 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4153 0xfbc00080, 0xfff000c0,
4154 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
4155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4156 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
4157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4158 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
4159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 4160 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 4161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4162 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
4163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4164 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 4165 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4166 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
4167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4168 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 4169 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4170 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
4171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4172 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
4173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4174 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
4175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4176 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
4177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4178 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
4179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4180 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
4181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4182 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
4183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4184 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
4185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4186 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
4187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4188 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
4189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4190 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 4191 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4192 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
4193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4194 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
4195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4196 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
4197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4198 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
4199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4200 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
4201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4202 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
4203 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4204 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
4205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4206 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
4207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4208 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
4209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4210 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
4211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4212 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
4213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4214 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
4215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4216 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
4217 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4218 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
4219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4220 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
4221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4222 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
4223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4224 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
4225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4226 0xe9400000, 0xff500000,
4227 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4229 0xe9500000, 0xff500000,
4230 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4232 0xe8600000, 0xff700000,
4233 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4235 0xe8700000, 0xff700000,
4236 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4238 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
4239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4240 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 4241
4242 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 4243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4244 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
4245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4246 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
4247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4248 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
4249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4250 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 4251
8f06b2d8 4252 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 4253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4254 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
4255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4256 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 4257
4258 /* Fallback. */
823d2571
TG		 4259 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4260 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4261 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 4262};
ff4a8d2b 4263
8f06b2d8
PB		 4264static const char *const arm_conditional[] =
4265{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 4266 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 4267
4268static const char *const arm_fp_const[] =
4269{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
4270
4271static const char *const arm_shift[] =
4272{"lsl", "lsr", "asr", "ror"};
4273
4274typedef struct
4275{
4276 const char *name;
4277 const char *description;
4278 const char *reg_names[16];
4279}
4280arm_regname;
4281
4282static const arm_regname regnames[] =
4283{
65b48a81 4284 { "reg-names-raw", N_("Select raw register names"),
8f06b2d8 4285 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
65b48a81 4286 { "reg-names-gcc", N_("Select register names used by GCC"),
8f06b2d8 4287 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 4288 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
8f06b2d8 4289 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65b48a81
PB		 4290 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
4291 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
4292 { "reg-names-apcs", N_("Select register names used in the APCS"),
8f06b2d8 4293 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 4294 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
8f06b2d8 4295 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
65b48a81
PB		 4296 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
4297 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
8f06b2d8
PB		 4298};
4299
4300static const char *const iwmmxt_wwnames[] =
4301{"b", "h", "w", "d"};
4302
4303static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 4304{"b", "bus", "bc", "bss",
4305 "h", "hus", "hc", "hss",
4306 "w", "wus", "wc", "wss",
4307 "d", "dus", "dc", "dss"
8f06b2d8
PB		 4308};
4309
4310static const char *const iwmmxt_regnames[] =
4311{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
4312 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
4313};
4314
4315static const char *const iwmmxt_cregnames[] =
4316{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
4317 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
4318};
4319
143275ea
AV		 4320static const char *const vec_condnames[] =
4321{ "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
4322};
4323
4324static const char *const mve_predicatenames[] =
4325{ "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
4326 "eee", "ee", "eet", "e", "ett", "et", "ete"
4327};
4328
4329/* Names for 2-bit size field for mve vector isntructions. */
4330static const char *const mve_vec_sizename[] =
4331 { "8", "16", "32", "64"};
4332
4333/* Indicates whether we are processing a then predicate,
4334 else predicate or none at all. */
4335enum vpt_pred_state
4336{
4337 PRED_NONE,
4338 PRED_THEN,
4339 PRED_ELSE
4340};
4341
4342/* Information used to process a vpt block and subsequent instructions. */
4343struct vpt_block
4344{
4345 /* Are we in a vpt block. */
4346 bfd_boolean in_vpt_block;
4347
4348 /* Next predicate state if in vpt block. */
4349 enum vpt_pred_state next_pred_state;
4350
4351 /* Mask from vpt/vpst instruction. */
4352 long predicate_mask;
4353
4354 /* Instruction number in vpt block. */
4355 long current_insn_num;
4356
4357 /* Number of instructions in vpt block.. */
4358 long num_pred_insn;
4359};
4360
4361static struct vpt_block vpt_block_state =
4362{
4363 FALSE,
4364 PRED_NONE,
4365 0,
4366 0,
4367 0
4368};
4369
8f06b2d8
PB		 4370/* Default to GCC register name set. */
4371static unsigned int regname_selected = 1;
4372
65b48a81 4373#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
8f06b2d8
PB		 4374#define arm_regnames regnames[regname_selected].reg_names
4375
4376static bfd_boolean force_thumb = FALSE;
4377
c22aaad1
PB		 4378/* Current IT instruction state. This contains the same state as the IT
4379 bits in the CPSR. */
4380static unsigned int ifthen_state;
4381/* IT state for the next instruction. */
4382static unsigned int ifthen_next_state;
4383/* The address of the insn for which the IT state is valid. */
4384static bfd_vma ifthen_address;
4385#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 4386/* Indicates that the current Conditional state is unconditional or outside
4387 an IT block. */
4388#define COND_UNCOND 16
c22aaad1 4389
8f06b2d8
PB		 4390\f
4391/* Functions. */
143275ea
AV		 4392/* Extract the predicate mask for a VPT or VPST instruction.
4393 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
4394
4395static long
4396mve_extract_pred_mask (long given)
4397{
4398 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
4399}
4400
4401/* Return the number of instructions in a MVE predicate block. */
4402static long
4403num_instructions_vpt_block (long given)
4404{
4405 long mask = mve_extract_pred_mask (given);
4406 if (mask == 0)
4407 return 0;
4408
4409 if (mask == 8)
4410 return 1;
4411
4412 if ((mask & 7) == 4)
4413 return 2;
4414
4415 if ((mask & 3) == 2)
4416 return 3;
4417
4418 if ((mask & 1) == 1)
4419 return 4;
4420
4421 return 0;
4422}
4423
4424static void
4425mark_outside_vpt_block (void)
4426{
4427 vpt_block_state.in_vpt_block = FALSE;
4428 vpt_block_state.next_pred_state = PRED_NONE;
4429 vpt_block_state.predicate_mask = 0;
4430 vpt_block_state.current_insn_num = 0;
4431 vpt_block_state.num_pred_insn = 0;
4432}
4433
4434static void
4435mark_inside_vpt_block (long given)
4436{
4437 vpt_block_state.in_vpt_block = TRUE;
4438 vpt_block_state.next_pred_state = PRED_THEN;
4439 vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
4440 vpt_block_state.current_insn_num = 0;
4441 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
4442 assert (vpt_block_state.num_pred_insn >= 1);
4443}
4444
4445static enum vpt_pred_state
4446invert_next_predicate_state (enum vpt_pred_state astate)
4447{
4448 if (astate == PRED_THEN)
4449 return PRED_ELSE;
4450 else if (astate == PRED_ELSE)
4451 return PRED_THEN;
4452 else
4453 return PRED_NONE;
4454}
4455
4456static enum vpt_pred_state
4457update_next_predicate_state (void)
4458{
4459 long pred_mask = vpt_block_state.predicate_mask;
4460 long mask_for_insn = 0;
4461
4462 switch (vpt_block_state.current_insn_num)
4463 {
4464 case 1:
4465 mask_for_insn = 8;
4466 break;
4467
4468 case 2:
4469 mask_for_insn = 4;
4470 break;
4471
4472 case 3:
4473 mask_for_insn = 2;
4474 break;
4475
4476 case 4:
4477 return PRED_NONE;
4478 }
4479
4480 if (pred_mask & mask_for_insn)
4481 return invert_next_predicate_state (vpt_block_state.next_pred_state);
4482 else
4483 return vpt_block_state.next_pred_state;
4484}
4485
4486static void
4487update_vpt_block_state (void)
4488{
4489 vpt_block_state.current_insn_num++;
4490 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
4491 {
4492 /* No more instructions to process in vpt block. */
4493 mark_outside_vpt_block ();
4494 return;
4495 }
4496
4497 vpt_block_state.next_pred_state = update_next_predicate_state ();
4498}
8f06b2d8 4499
16980d0b
JB		 4500/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
4501 Returns pointer to following character of the format string and
4502 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 4503 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 4504
4505static const char *
fe56b6ce
NC		 4506arm_decode_bitfield (const char *ptr,
4507 unsigned long insn,
4508 unsigned long *valuep,
4509 int *widthp)
16980d0b
JB		 4510{
4511 unsigned long value = 0;
4512 int width = 0;
43e65147
L		 4513
4514 do
16980d0b
JB		 4515 {
4516 int start, end;
4517 int bits;
4518
4519 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
4520 start = start * 10 + *ptr - '0';
4521 if (*ptr == '-')
4522 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
4523 end = end * 10 + *ptr - '0';
4524 else
4525 end = start;
4526 bits = end - start;
4527 if (bits < 0)
4528 abort ();
4529 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
4530 width += bits + 1;
4531 }
4532 while (*ptr++ == ',');
4533 *valuep = value;
4534 if (widthp)
4535 *widthp = width;
4536 return ptr - 1;
4537}
4538
8f06b2d8 4539static void
37b37b2d 4540arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 4541 bfd_boolean print_shift)
8f06b2d8
PB		 4542{
4543 func (stream, "%s", arm_regnames[given & 0xf]);
4544
4545 if ((given & 0xff0) != 0)
4546 {
4547 if ((given & 0x10) == 0)
4548 {
4549 int amount = (given & 0xf80) >> 7;
4550 int shift = (given & 0x60) >> 5;
4551
4552 if (amount == 0)
4553 {
4554 if (shift == 3)
4555 {
4556 func (stream, ", rrx");
4557 return;
4558 }
4559
4560 amount = 32;
4561 }
4562
37b37b2d
RE		 4563 if (print_shift)
4564 func (stream, ", %s #%d", arm_shift[shift], amount);
4565 else
4566 func (stream, ", #%d", amount);
8f06b2d8 4567 }
74bdfecf 4568 else if ((given & 0x80) == 0x80)
aefd8a40 4569 func (stream, "\t; <illegal shifter operand>");
37b37b2d 4570 else if (print_shift)
8f06b2d8
PB		 4571 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
4572 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 4573 else
4574 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 4575 }
4576}
4577
73cd51e5
AV		 4578/* Return TRUE if the MATCHED_INSN can be inside an IT block. */
4579
4580static bfd_boolean
4581is_mve_okay_in_it (enum mve_instructions matched_insn)
4582{
c507f10b
AV		 4583 switch (matched_insn)
4584 {
4585 case MVE_VMOV_GP_TO_VEC_LANE:
4586 case MVE_VMOV2_VEC_LANE_TO_GP:
4587 case MVE_VMOV2_GP_TO_VEC_LANE:
4588 case MVE_VMOV_VEC_LANE_TO_GP:
4589 return TRUE;
4590 default:
4591 return FALSE;
4592 }
73cd51e5
AV		 4593}
4594
4595static bfd_boolean
4596is_mve_architecture (struct disassemble_info *info)
4597{
4598 struct arm_private_data *private_data = info->private_data;
4599 arm_feature_set allowed_arches = private_data->features;
4600
4601 arm_feature_set arm_ext_v8_1m_main
4602 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
4603
4604 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
4605 && !ARM_CPU_IS_ANY (allowed_arches))
4606 return TRUE;
4607 else
4608 return FALSE;
4609}
4610
143275ea
AV		 4611static bfd_boolean
4612is_vpt_instruction (long given)
4613{
4614
4615 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
4616 if ((given & 0x0040e000) == 0)
4617 return FALSE;
4618
4619 /* VPT floating point T1 variant. */
4620 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
4621 /* VPT floating point T2 variant. */
4622 || ((given & 0xefb10f50) == 0xee310f40)
4623 /* VPT vector T1 variant. */
4624 || ((given & 0xff811f51) == 0xfe010f00)
4625 /* VPT vector T2 variant. */
4626 || ((given & 0xff811f51) == 0xfe010f01
4627 && ((given & 0x300000) != 0x300000))
4628 /* VPT vector T3 variant. */
4629 || ((given & 0xff811f50) == 0xfe011f00)
4630 /* VPT vector T4 variant. */
4631 || ((given & 0xff811f70) == 0xfe010f40)
4632 /* VPT vector T5 variant. */
4633 || ((given & 0xff811f70) == 0xfe010f60)
4634 /* VPT vector T6 variant. */
4635 || ((given & 0xff811f50) == 0xfe011f40)
4636 /* VPST vector T variant. */
4637 || ((given & 0xffbf1fff) == 0xfe310f4d))
4638 return TRUE;
4639 else
4640 return FALSE;
4641}
4642
73cd51e5
AV		 4643/* Decode a bitfield from opcode GIVEN, with starting bitfield = START
4644 and ending bitfield = END. END must be greater than START. */
4645
4646static unsigned long
4647arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
4648{
4649 int bits = end - start;
4650
4651 if (bits < 0)
4652 abort ();
4653
4654 return ((given >> start) & ((2ul << bits) - 1));
4655}
4656
4657/* Decode a bitfield from opcode GIVEN, with multiple bitfields:
4658 START:END and START2:END2. END/END2 must be greater than
4659 START/START2. */
4660
4661static unsigned long
4662arm_decode_field_multiple (unsigned long given, unsigned int start,
4663 unsigned int end, unsigned int start2,
4664 unsigned int end2)
4665{
4666 int bits = end - start;
4667 int bits2 = end2 - start2;
4668 unsigned long value = 0;
4669 int width = 0;
4670
4671 if (bits2 < 0)
4672 abort ();
4673
4674 value = arm_decode_field (given, start, end);
4675 width += bits + 1;
4676
4677 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
4678 return value;
4679}
4680
4681/* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
4682 This helps us decode instructions that change mnemonic depending on specific
4683 operand values/encodings. */
4684
4685static bfd_boolean
4686is_mve_encoding_conflict (unsigned long given,
4687 enum mve_instructions matched_insn)
4688{
143275ea
AV		 4689 switch (matched_insn)
4690 {
4691 case MVE_VPST:
4692 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4693 return TRUE;
4694 else
4695 return FALSE;
4696
4697 case MVE_VPT_FP_T1:
4698 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4699 return TRUE;
4700 if ((arm_decode_field (given, 12, 12) == 0)
4701 && (arm_decode_field (given, 0, 0) == 1))
4702 return TRUE;
4703 return FALSE;
4704
4705 case MVE_VPT_FP_T2:
4706 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4707 return TRUE;
4708 if (arm_decode_field (given, 0, 3) == 0xd)
4709 return TRUE;
4710 return FALSE;
4711
4712 case MVE_VPT_VEC_T1:
4713 case MVE_VPT_VEC_T2:
4714 case MVE_VPT_VEC_T3:
4715 case MVE_VPT_VEC_T4:
4716 case MVE_VPT_VEC_T5:
4717 case MVE_VPT_VEC_T6:
4718 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4719 return TRUE;
4720 if (arm_decode_field (given, 20, 21) == 3)
4721 return TRUE;
4722 return FALSE;
4723
4724 case MVE_VCMP_FP_T1:
4725 if ((arm_decode_field (given, 12, 12) == 0)
4726 && (arm_decode_field (given, 0, 0) == 1))
4727 return TRUE;
4728 else
4729 return FALSE;
4730
4731 case MVE_VCMP_FP_T2:
4732 if (arm_decode_field (given, 0, 3) == 0xd)
4733 return TRUE;
4734 else
4735 return FALSE;
4736
897b9bbc
AV		 4737 case MVE_VCADD_VEC:
4738 case MVE_VHCADD:
1c8f2df8
AV		 4739 case MVE_VDDUP:
4740 case MVE_VIDUP:
d3b63143
AV		 4741 case MVE_VQRDMLADH:
4742 case MVE_VQDMLAH:
4743 case MVE_VQRDMLAH:
4744 case MVE_VQDMLASH:
4745 case MVE_VQRDMLASH:
4746 case MVE_VQDMLSDH:
4747 case MVE_VQRDMLSDH:
4748 case MVE_VQDMULH_T3:
4749 case MVE_VQRDMULH_T4:
4750 case MVE_VQDMLADH:
4751 case MVE_VMLAS:
14925797 4752 case MVE_VMULL_INT:
9743db03
AV		 4753 case MVE_VHADD_T2:
4754 case MVE_VHSUB_T2:
143275ea
AV		 4755 case MVE_VCMP_VEC_T1:
4756 case MVE_VCMP_VEC_T2:
4757 case MVE_VCMP_VEC_T3:
4758 case MVE_VCMP_VEC_T4:
4759 case MVE_VCMP_VEC_T5:
4760 case MVE_VCMP_VEC_T6:
4761 if (arm_decode_field (given, 20, 21) == 3)
4762 return TRUE;
4763 else
4764 return FALSE;
4765
04d54ace
AV		 4766 case MVE_VLD2:
4767 case MVE_VLD4:
4768 case MVE_VST2:
4769 case MVE_VST4:
4770 if (arm_decode_field (given, 7, 8) == 3)
4771 return TRUE;
4772 else
4773 return FALSE;
4774
aef6d006
AV		 4775 case MVE_VSTRB_T1:
4776 case MVE_VSTRH_T2:
4777 if ((arm_decode_field (given, 24, 24) == 0)
4778 && (arm_decode_field (given, 21, 21) == 0))
4779 {
4780 return TRUE;
4781 }
4782 else if ((arm_decode_field (given, 7, 8) == 3))
4783 return TRUE;
4784 else
4785 return FALSE;
4786
4787 case MVE_VSTRB_T5:
4788 case MVE_VSTRH_T6:
4789 case MVE_VSTRW_T7:
4790 if ((arm_decode_field (given, 24, 24) == 0)
4791 && (arm_decode_field (given, 21, 21) == 0))
4792 {
4793 return TRUE;
4794 }
4795 else
4796 return FALSE;
4797
bf0b396d
AV		 4798 case MVE_VCVT_FP_FIX_VEC:
4799 return (arm_decode_field (given, 16, 21) & 0x38) == 0;
4800
c507f10b
AV		 4801 case MVE_VBIC_IMM:
4802 case MVE_VORR_IMM:
4803 {
4804 unsigned long cmode = arm_decode_field (given, 8, 11);
4805
4806 if ((cmode & 1) == 0)
4807 return TRUE;
4808 else if ((cmode & 0xc) == 0xc)
4809 return TRUE;
4810 else
4811 return FALSE;
4812 }
4813
4814 case MVE_VMVN_IMM:
4815 {
4816 unsigned long cmode = arm_decode_field (given, 8, 11);
4817
4818 if ((cmode & 9) == 1)
4819 return TRUE;
4820 else if ((cmode & 5) == 1)
4821 return TRUE;
4822 else if ((cmode & 0xe) == 0xe)
4823 return TRUE;
4824 else
4825 return FALSE;
4826 }
4827
4828 case MVE_VMOV_IMM_TO_VEC:
4829 if ((arm_decode_field (given, 5, 5) == 1)
4830 && (arm_decode_field (given, 8, 11) != 0xe))
4831 return TRUE;
4832 else
4833 return FALSE;
4834
14925797
AV		 4835 case MVE_VMOVL:
4836 {
4837 unsigned long size = arm_decode_field (given, 19, 20);
4838 if ((size == 0) || (size == 3))
4839 return TRUE;
4840 else
4841 return FALSE;
4842 }
4843
d3b63143 4844 case MVE_VADDV:
14925797
AV		 4845 case MVE_VMOVN:
4846 case MVE_VQMOVUN:
4847 case MVE_VQMOVN:
4848 if (arm_decode_field (given, 18, 19) == 3)
4849 return TRUE;
4850 else
4851 return FALSE;
4852
d3b63143
AV		 4853 case MVE_VMLSLDAV:
4854 case MVE_VRMLSLDAVH:
4855 case MVE_VMLALDAV:
4856 case MVE_VADDLV:
4857 if (arm_decode_field (given, 20, 22) == 7)
4858 return TRUE;
4859 else
4860 return FALSE;
4861
4862 case MVE_VRMLALDAVH:
4863 if ((arm_decode_field (given, 20, 22) & 6) == 6)
4864 return TRUE;
4865 else
4866 return FALSE;
4867
1c8f2df8
AV		 4868 case MVE_VDWDUP:
4869 case MVE_VIWDUP:
4870 if ((arm_decode_field (given, 20, 21) == 3)
4871 || (arm_decode_field (given, 1, 3) == 7))
4872 return TRUE;
4873 else
4874 return FALSE;
4875
143275ea
AV		 4876 default:
4877 return FALSE;
4878
4879 }
73cd51e5
AV		 4880}
4881
aef6d006
AV		 4882static void
4883print_mve_vld_str_addr (struct disassemble_info *info,
4884 unsigned long given,
4885 enum mve_instructions matched_insn)
4886{
4887 void *stream = info->stream;
4888 fprintf_ftype func = info->fprintf_func;
4889
4890 unsigned long p, w, gpr, imm, add, mod_imm;
4891
4892 imm = arm_decode_field (given, 0, 6);
4893 mod_imm = imm;
4894
4895 switch (matched_insn)
4896 {
4897 case MVE_VLDRB_T1:
4898 case MVE_VSTRB_T1:
4899 gpr = arm_decode_field (given, 16, 18);
4900 break;
4901
4902 case MVE_VLDRH_T2:
4903 case MVE_VSTRH_T2:
4904 gpr = arm_decode_field (given, 16, 18);
4905 mod_imm = imm << 1;
4906 break;
4907
4908 case MVE_VLDRH_T6:
4909 case MVE_VSTRH_T6:
4910 gpr = arm_decode_field (given, 16, 19);
4911 mod_imm = imm << 1;
4912 break;
4913
4914 case MVE_VLDRW_T7:
4915 case MVE_VSTRW_T7:
4916 gpr = arm_decode_field (given, 16, 19);
4917 mod_imm = imm << 2;
4918 break;
4919
4920 case MVE_VLDRB_T5:
4921 case MVE_VSTRB_T5:
4922 gpr = arm_decode_field (given, 16, 19);
4923 break;
4924
4925 default:
4926 return;
4927 }
4928
4929 p = arm_decode_field (given, 24, 24);
4930 w = arm_decode_field (given, 21, 21);
4931
4932 add = arm_decode_field (given, 23, 23);
4933
4934 char * add_sub;
4935
4936 /* Don't print anything for '+' as it is implied. */
4937 if (add == 1)
4938 add_sub = "";
4939 else
4940 add_sub = "-";
4941
4942 if (p == 1)
4943 {
4944 /* Offset mode. */
4945 if (w == 0)
4946 func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm);
4947 /* Pre-indexed mode. */
4948 else
4949 func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm);
4950 }
4951 else if ((p == 0) && (w == 1))
4952 /* Post-index mode. */
4953 func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm);
4954}
4955
73cd51e5
AV		 4956/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
4957 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
4958 this encoding is undefined. */
4959
4960static bfd_boolean
4961is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
4962 enum mve_undefined *undefined_code)
4963{
4964 *undefined_code = UNDEF_NONE;
4965
9743db03
AV		 4966 switch (matched_insn)
4967 {
4968 case MVE_VDUP:
4969 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
4970 {
4971 *undefined_code = UNDEF_SIZE_3;
4972 return TRUE;
4973 }
4974 else
4975 return FALSE;
4976
d3b63143
AV		 4977 case MVE_VQDMULH_T1:
4978 case MVE_VQRDMULH_T2:
9743db03
AV		 4979 case MVE_VRHADD:
4980 case MVE_VHADD_T1:
4981 case MVE_VHSUB_T1:
4982 if (arm_decode_field (given, 20, 21) == 3)
4983 {
4984 *undefined_code = UNDEF_SIZE_3;
4985 return TRUE;
4986 }
4987 else
4988 return FALSE;
4989
aef6d006
AV		 4990 case MVE_VLDRB_T1:
4991 if (arm_decode_field (given, 7, 8) == 3)
4992 {
4993 *undefined_code = UNDEF_SIZE_3;
4994 return TRUE;
4995 }
4996 else
4997 return FALSE;
4998
4999 case MVE_VLDRH_T2:
5000 if (arm_decode_field (given, 7, 8) <= 1)
5001 {
5002 *undefined_code = UNDEF_SIZE_LE_1;
5003 return TRUE;
5004 }
5005 else
5006 return FALSE;
5007
5008 case MVE_VSTRB_T1:
5009 if ((arm_decode_field (given, 7, 8) == 0))
5010 {
5011 *undefined_code = UNDEF_SIZE_0;
5012 return TRUE;
5013 }
5014 else
5015 return FALSE;
5016
5017 case MVE_VSTRH_T2:
5018 if ((arm_decode_field (given, 7, 8) <= 1))
5019 {
5020 *undefined_code = UNDEF_SIZE_LE_1;
5021 return TRUE;
5022 }
5023 else
5024 return FALSE;
5025
ef1576a1
AV		 5026 case MVE_VLDRB_GATHER_T1:
5027 if (arm_decode_field (given, 7, 8) == 3)
5028 {
5029 *undefined_code = UNDEF_SIZE_3;
5030 return TRUE;
5031 }
5032 else if ((arm_decode_field (given, 28, 28) == 0)
5033 && (arm_decode_field (given, 7, 8) == 0))
5034 {
5035 *undefined_code = UNDEF_NOT_UNS_SIZE_0;
5036 return TRUE;
5037 }
5038 else
5039 return FALSE;
5040
5041 case MVE_VLDRH_GATHER_T2:
5042 if (arm_decode_field (given, 7, 8) == 3)
5043 {
5044 *undefined_code = UNDEF_SIZE_3;
5045 return TRUE;
5046 }
5047 else if ((arm_decode_field (given, 28, 28) == 0)
5048 && (arm_decode_field (given, 7, 8) == 1))
5049 {
5050 *undefined_code = UNDEF_NOT_UNS_SIZE_1;
5051 return TRUE;
5052 }
5053 else if (arm_decode_field (given, 7, 8) == 0)
5054 {
5055 *undefined_code = UNDEF_SIZE_0;
5056 return TRUE;
5057 }
5058 else
5059 return FALSE;
5060
5061 case MVE_VLDRW_GATHER_T3:
5062 if (arm_decode_field (given, 7, 8) != 2)
5063 {
5064 *undefined_code = UNDEF_SIZE_NOT_2;
5065 return TRUE;
5066 }
5067 else if (arm_decode_field (given, 28, 28) == 0)
5068 {
5069 *undefined_code = UNDEF_NOT_UNSIGNED;
5070 return TRUE;
5071 }
5072 else
5073 return FALSE;
5074
5075 case MVE_VLDRD_GATHER_T4:
5076 if (arm_decode_field (given, 7, 8) != 3)
5077 {
5078 *undefined_code = UNDEF_SIZE_NOT_3;
5079 return TRUE;
5080 }
5081 else if (arm_decode_field (given, 28, 28) == 0)
5082 {
5083 *undefined_code = UNDEF_NOT_UNSIGNED;
5084 return TRUE;
5085 }
5086 else
5087 return FALSE;
5088
5089 case MVE_VSTRB_SCATTER_T1:
5090 if (arm_decode_field (given, 7, 8) == 3)
5091 {
5092 *undefined_code = UNDEF_SIZE_3;
5093 return TRUE;
5094 }
5095 else
5096 return FALSE;
5097
5098 case MVE_VSTRH_SCATTER_T2:
5099 {
5100 unsigned long size = arm_decode_field (given, 7, 8);
5101 if (size == 3)
5102 {
5103 *undefined_code = UNDEF_SIZE_3;
5104 return TRUE;
5105 }
5106 else if (size == 0)
5107 {
5108 *undefined_code = UNDEF_SIZE_0;
5109 return TRUE;
5110 }
5111 else
5112 return FALSE;
5113 }
5114
5115 case MVE_VSTRW_SCATTER_T3:
5116 if (arm_decode_field (given, 7, 8) != 2)
5117 {
5118 *undefined_code = UNDEF_SIZE_NOT_2;
5119 return TRUE;
5120 }
5121 else
5122 return FALSE;
5123
5124 case MVE_VSTRD_SCATTER_T4:
5125 if (arm_decode_field (given, 7, 8) != 3)
5126 {
5127 *undefined_code = UNDEF_SIZE_NOT_3;
5128 return TRUE;
5129 }
5130 else
5131 return FALSE;
5132
bf0b396d
AV		 5133 case MVE_VCVT_FP_FIX_VEC:
5134 {
5135 unsigned long imm6 = arm_decode_field (given, 16, 21);
5136 if ((imm6 & 0x20) == 0)
5137 {
5138 *undefined_code = UNDEF_VCVT_IMM6;
5139 return TRUE;
5140 }
5141
5142 if ((arm_decode_field (given, 9, 9) == 0)
5143 && ((imm6 & 0x30) == 0x20))
5144 {
5145 *undefined_code = UNDEF_VCVT_FSI_IMM6;
5146 return TRUE;
5147 }
5148
5149 return FALSE;
5150 }
5151
5152 case MVE_VCVT_BETWEEN_FP_INT:
5153 case MVE_VCVT_FROM_FP_TO_INT:
5154 {
5155 unsigned long size = arm_decode_field (given, 18, 19);
5156 if (size == 0)
5157 {
5158 *undefined_code = UNDEF_SIZE_0;
5159 return TRUE;
5160 }
5161 else if (size == 3)
5162 {
5163 *undefined_code = UNDEF_SIZE_3;
5164 return TRUE;
5165 }
5166 else
5167 return FALSE;
5168 }
5169
c507f10b
AV		 5170 case MVE_VMOV_VEC_LANE_TO_GP:
5171 {
5172 unsigned long op1 = arm_decode_field (given, 21, 22);
5173 unsigned long op2 = arm_decode_field (given, 5, 6);
5174 unsigned long u = arm_decode_field (given, 23, 23);
5175
5176 if ((op2 == 0) && (u == 1))
5177 {
5178 if ((op1 == 0) || (op1 == 1))
5179 {
5180 *undefined_code = UNDEF_BAD_U_OP1_OP2;
5181 return TRUE;
5182 }
5183 else
5184 return FALSE;
5185 }
5186 else if (op2 == 2)
5187 {
5188 if ((op1 == 0) || (op1 == 1))
5189 {
5190 *undefined_code = UNDEF_BAD_OP1_OP2;
5191 return TRUE;
5192 }
5193 else
5194 return FALSE;
5195 }
5196
5197 return FALSE;
5198 }
5199
5200 case MVE_VMOV_GP_TO_VEC_LANE:
5201 if (arm_decode_field (given, 5, 6) == 2)
5202 {
5203 unsigned long op1 = arm_decode_field (given, 21, 22);
5204 if ((op1 == 0) || (op1 == 1))
5205 {
5206 *undefined_code = UNDEF_BAD_OP1_OP2;
5207 return TRUE;
5208 }
5209 else
5210 return FALSE;
5211 }
5212 else
5213 return FALSE;
5214
5215 case MVE_VMOV_IMM_TO_VEC:
5216 if (arm_decode_field (given, 5, 5) == 0)
5217 {
5218 unsigned long cmode = arm_decode_field (given, 8, 11);
5219
5220 if (((cmode & 9) == 1) || ((cmode & 5) == 1))
5221 {
5222 *undefined_code = UNDEF_OP_0_BAD_CMODE;
5223 return TRUE;
5224 }
5225 else
5226 return FALSE;
5227 }
5228 else
5229 return FALSE;
5230
14925797
AV		 5231 case MVE_VMOVN:
5232 if (arm_decode_field (given, 18, 19) == 2)
5233 {
5234 *undefined_code = UNDEF_SIZE_2;
5235 return TRUE;
5236 }
5237 else
5238 return FALSE;
5239
d3b63143
AV		 5240 case MVE_VRMLALDAVH:
5241 case MVE_VMLADAV_T1:
5242 case MVE_VMLADAV_T2:
5243 case MVE_VMLALDAV:
5244 if ((arm_decode_field (given, 28, 28) == 1)
5245 && (arm_decode_field (given, 12, 12) == 1))
5246 {
5247 *undefined_code = UNDEF_XCHG_UNS;
5248 return TRUE;
5249 }
5250 else
5251 return FALSE;
5252
9743db03
AV		 5253 default:
5254 return FALSE;
5255 }
73cd51e5
AV		 5256}
5257
5258/* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
5259 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
5260 why this encoding is unpredictable. */
5261
5262static bfd_boolean
5263is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
5264 enum mve_unpredictable *unpredictable_code)
5265{
5266 *unpredictable_code = UNPRED_NONE;
5267
143275ea
AV		 5268 switch (matched_insn)
5269 {
5270 case MVE_VCMP_FP_T2:
5271 case MVE_VPT_FP_T2:
5272 if ((arm_decode_field (given, 12, 12) == 0)
5273 && (arm_decode_field (given, 5, 5) == 1))
5274 {
5275 *unpredictable_code = UNPRED_FCA_0_FCB_1;
5276 return TRUE;
5277 }
5278 else
5279 return FALSE;
73cd51e5 5280
143275ea
AV		 5281 case MVE_VPT_VEC_T4:
5282 case MVE_VPT_VEC_T5:
5283 case MVE_VPT_VEC_T6:
5284 case MVE_VCMP_VEC_T4:
5285 case MVE_VCMP_VEC_T5:
5286 case MVE_VCMP_VEC_T6:
5287 if (arm_decode_field (given, 0, 3) == 0xd)
5288 {
5289 *unpredictable_code = UNPRED_R13;
5290 return TRUE;
5291 }
5292 else
5293 return FALSE;
c1e26897 5294
9743db03
AV		 5295 case MVE_VDUP:
5296 {
5297 unsigned long gpr = arm_decode_field (given, 12, 15);
5298 if (gpr == 0xd)
5299 {
5300 *unpredictable_code = UNPRED_R13;
5301 return TRUE;
5302 }
5303 else if (gpr == 0xf)
5304 {
5305 *unpredictable_code = UNPRED_R15;
5306 return TRUE;
5307 }
5308
5309 return FALSE;
5310 }
5311
d3b63143
AV		 5312 case MVE_VQDMLAH:
5313 case MVE_VQRDMLAH:
5314 case MVE_VQDMLASH:
5315 case MVE_VQRDMLASH:
5316 case MVE_VQDMULH_T3:
5317 case MVE_VQRDMULH_T4:
5318 case MVE_VMLAS:
9743db03
AV		 5319 case MVE_VFMA_FP_SCALAR:
5320 case MVE_VFMAS_FP_SCALAR:
5321 case MVE_VHADD_T2:
5322 case MVE_VHSUB_T2:
5323 {
5324 unsigned long gpr = arm_decode_field (given, 0, 3);
5325 if (gpr == 0xd)
5326 {
5327 *unpredictable_code = UNPRED_R13;
5328 return TRUE;
5329 }
5330 else if (gpr == 0xf)
5331 {
5332 *unpredictable_code = UNPRED_R15;
5333 return TRUE;
5334 }
5335
5336 return FALSE;
5337 }
5338
04d54ace
AV		 5339 case MVE_VLD2:
5340 case MVE_VST2:
5341 {
5342 unsigned long rn = arm_decode_field (given, 16, 19);
5343
5344 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
5345 {
5346 *unpredictable_code = UNPRED_R13_AND_WB;
5347 return TRUE;
5348 }
5349
5350 if (rn == 0xf)
5351 {
5352 *unpredictable_code = UNPRED_R15;
5353 return TRUE;
5354 }
5355
5356 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
5357 {
5358 *unpredictable_code = UNPRED_Q_GT_6;
5359 return TRUE;
5360 }
5361 else
5362 return FALSE;
5363 }
5364
5365 case MVE_VLD4:
5366 case MVE_VST4:
5367 {
5368 unsigned long rn = arm_decode_field (given, 16, 19);
5369
5370 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
5371 {
5372 *unpredictable_code = UNPRED_R13_AND_WB;
5373 return TRUE;
5374 }
5375
5376 if (rn == 0xf)
5377 {
5378 *unpredictable_code = UNPRED_R15;
5379 return TRUE;
5380 }
5381
5382 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
5383 {
5384 *unpredictable_code = UNPRED_Q_GT_4;
5385 return TRUE;
5386 }
5387 else
5388 return FALSE;
5389 }
5390
aef6d006
AV		 5391 case MVE_VLDRB_T5:
5392 case MVE_VLDRH_T6:
5393 case MVE_VLDRW_T7:
5394 case MVE_VSTRB_T5:
5395 case MVE_VSTRH_T6:
5396 case MVE_VSTRW_T7:
5397 {
5398 unsigned long rn = arm_decode_field (given, 16, 19);
5399
5400 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
5401 {
5402 *unpredictable_code = UNPRED_R13_AND_WB;
5403 return TRUE;
5404 }
5405 else if (rn == 0xf)
5406 {
5407 *unpredictable_code = UNPRED_R15;
5408 return TRUE;
5409 }
5410 else
5411 return FALSE;
5412 }
5413
ef1576a1
AV		 5414 case MVE_VLDRB_GATHER_T1:
5415 if (arm_decode_field (given, 0, 0) == 1)
5416 {
5417 *unpredictable_code = UNPRED_OS;
5418 return TRUE;
5419 }
5420
5421 /* fall through. */
5422 /* To handle common code with T2-T4 variants. */
5423 case MVE_VLDRH_GATHER_T2:
5424 case MVE_VLDRW_GATHER_T3:
5425 case MVE_VLDRD_GATHER_T4:
5426 {
5427 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5428 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
5429
5430 if (qd == qm)
5431 {
5432 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
5433 return TRUE;
5434 }
5435
5436 if (arm_decode_field (given, 16, 19) == 0xf)
5437 {
5438 *unpredictable_code = UNPRED_R15;
5439 return TRUE;
5440 }
5441
5442 return FALSE;
5443 }
5444
5445 case MVE_VLDRW_GATHER_T5:
5446 case MVE_VLDRD_GATHER_T6:
5447 {
5448 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5449 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
5450
5451 if (qd == qm)
5452 {
5453 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
5454 return TRUE;
5455 }
5456 else
5457 return FALSE;
5458 }
5459
5460 case MVE_VSTRB_SCATTER_T1:
5461 if (arm_decode_field (given, 16, 19) == 0xf)
5462 {
5463 *unpredictable_code = UNPRED_R15;
5464 return TRUE;
5465 }
5466 else if (arm_decode_field (given, 0, 0) == 1)
5467 {
5468 *unpredictable_code = UNPRED_OS;
5469 return TRUE;
5470 }
5471 else
5472 return FALSE;
5473
5474 case MVE_VSTRH_SCATTER_T2:
5475 case MVE_VSTRW_SCATTER_T3:
5476 case MVE_VSTRD_SCATTER_T4:
5477 if (arm_decode_field (given, 16, 19) == 0xf)
5478 {
5479 *unpredictable_code = UNPRED_R15;
5480 return TRUE;
5481 }
5482 else
5483 return FALSE;
5484
c507f10b
AV		 5485 case MVE_VMOV2_VEC_LANE_TO_GP:
5486 case MVE_VMOV2_GP_TO_VEC_LANE:
bf0b396d
AV		 5487 case MVE_VCVT_BETWEEN_FP_INT:
5488 case MVE_VCVT_FROM_FP_TO_INT:
5489 {
5490 unsigned long rt = arm_decode_field (given, 0, 3);
5491 unsigned long rt2 = arm_decode_field (given, 16, 19);
5492
5493 if ((rt == 0xd) || (rt2 == 0xd))
5494 {
5495 *unpredictable_code = UNPRED_R13;
5496 return TRUE;
5497 }
5498 else if ((rt == 0xf) || (rt2 == 0xf))
5499 {
5500 *unpredictable_code = UNPRED_R15;
5501 return TRUE;
5502 }
5503 else if (rt == rt2)
5504 {
5505 *unpredictable_code = UNPRED_GP_REGS_EQUAL;
5506 return TRUE;
5507 }
5508
5509 return FALSE;
5510 }
5511
c507f10b
AV		 5512 case MVE_VMOV_HFP_TO_GP:
5513 case MVE_VMOV_GP_TO_VEC_LANE:
5514 case MVE_VMOV_VEC_LANE_TO_GP:
5515 {
5516 unsigned long rda = arm_decode_field (given, 12, 15);
5517 if (rda == 0xd)
5518 {
5519 *unpredictable_code = UNPRED_R13;
5520 return TRUE;
5521 }
5522 else if (rda == 0xf)
5523 {
5524 *unpredictable_code = UNPRED_R15;
5525 return TRUE;
5526 }
5527
5528 return FALSE;
5529 }
5530
d3b63143
AV		 5531 case MVE_VQRDMLADH:
5532 case MVE_VQDMLSDH:
5533 case MVE_VQRDMLSDH:
5534 case MVE_VQDMLADH:
14925797
AV		 5535 case MVE_VMULL_INT:
5536 {
5537 unsigned long Qd;
5538 unsigned long Qm;
5539 unsigned long Qn;
5540
5541 if (arm_decode_field (given, 20, 21) == 2)
5542 {
5543 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5544 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
5545 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
5546
5547 if ((Qd == Qn) || (Qd == Qm))
5548 {
5549 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
5550 return TRUE;
5551 }
5552 else
5553 return FALSE;
5554 }
5555 else
5556 return FALSE;
5557 }
5558
897b9bbc 5559 case MVE_VCMUL_FP:
14925797
AV		 5560 case MVE_VQDMULL_T1:
5561 {
5562 unsigned long Qd;
5563 unsigned long Qm;
5564 unsigned long Qn;
5565
5566 if (arm_decode_field (given, 28, 28) == 1)
5567 {
5568 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5569 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
5570 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
5571
5572 if ((Qd == Qn) || (Qd == Qm))
5573 {
5574 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
5575 return TRUE;
5576 }
5577 else
5578 return FALSE;
5579 }
5580 else
5581 return FALSE;
5582 }
5583
5584 case MVE_VQDMULL_T2:
5585 {
5586 unsigned long gpr = arm_decode_field (given, 0, 3);
5587 if (gpr == 0xd)
5588 {
5589 *unpredictable_code = UNPRED_R13;
5590 return TRUE;
5591 }
5592 else if (gpr == 0xf)
5593 {
5594 *unpredictable_code = UNPRED_R15;
5595 return TRUE;
5596 }
5597
5598 if (arm_decode_field (given, 28, 28) == 1)
5599 {
5600 unsigned long Qd
5601 = arm_decode_field_multiple (given, 13, 15, 22, 22);
5602 unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
5603
5604 if ((Qd == Qn))
5605 {
5606 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
5607 return TRUE;
5608 }
5609 else
5610 return FALSE;
5611 }
5612
5613 return FALSE;
5614 }
5615
d3b63143
AV		 5616 case MVE_VMLSLDAV:
5617 case MVE_VRMLSLDAVH:
5618 case MVE_VMLALDAV:
5619 case MVE_VADDLV:
5620 if (arm_decode_field (given, 20, 22) == 6)
5621 {
5622 *unpredictable_code = UNPRED_R13;
5623 return TRUE;
5624 }
5625 else
5626 return FALSE;
5627
1c8f2df8
AV		 5628 case MVE_VDWDUP:
5629 case MVE_VIWDUP:
5630 if (arm_decode_field (given, 1, 3) == 6)
5631 {
5632 *unpredictable_code = UNPRED_R13;
5633 return TRUE;
5634 }
5635 else
5636 return FALSE;
5637
897b9bbc
AV		 5638 case MVE_VCADD_VEC:
5639 case MVE_VHCADD:
5640 {
5641 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5642 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
5643 if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
5644 {
5645 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
5646 return TRUE;
5647 }
5648 else
5649 return FALSE;
5650 }
5651
5652 case MVE_VCADD_FP:
5653 {
5654 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5655 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
5656 if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
5657 {
5658 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
5659 return TRUE;
5660 }
5661 else
5662 return FALSE;
5663 }
5664
5665 case MVE_VCMLA_FP:
5666 {
5667 unsigned long Qda;
5668 unsigned long Qm;
5669 unsigned long Qn;
5670
5671 if (arm_decode_field (given, 20, 20) == 1)
5672 {
5673 Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
5674 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
5675 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
5676
5677 if ((Qda == Qn) || (Qda == Qm))
5678 {
5679 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
5680 return TRUE;
5681 }
5682 else
5683 return FALSE;
5684 }
5685 else
5686 return FALSE;
5687
5688 }
5689
143275ea
AV		 5690 default:
5691 return FALSE;
5692 }
5693}
c1e26897 5694
c507f10b
AV		 5695static void
5696print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
5697{
5698 unsigned long op1 = arm_decode_field (given, 21, 22);
5699 unsigned long op2 = arm_decode_field (given, 5, 6);
5700 unsigned long h = arm_decode_field (given, 16, 16);
5701 unsigned long index, esize, targetBeat, idx;
5702 void *stream = info->stream;
5703 fprintf_ftype func = info->fprintf_func;
5704
5705 if ((op1 & 0x2) == 0x2)
5706 {
5707 index = op2;
5708 esize = 8;
5709 }
5710 else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
5711 {
5712 index = op2 >> 1;
5713 esize = 16;
5714 }
5715 else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
5716 {
5717 index = 0;
5718 esize = 32;
5719 }
5720 else
5721 {
5722 func (stream, "<undefined index>");
5723 return;
5724 }
5725
5726 targetBeat = (op1 & 0x1) | (h << 1);
5727 idx = index + targetBeat * (32/esize);
5728
5729 func (stream, "%lu", idx);
5730}
5731
5732/* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
5733 in length and integer of floating-point type. */
5734static void
5735print_simd_imm8 (struct disassemble_info *info, unsigned long given,
5736 unsigned int ibit_loc, const struct mopcode32 *insn)
5737{
5738 int bits = 0;
5739 int cmode = (given >> 8) & 0xf;
5740 int op = (given >> 5) & 0x1;
5741 unsigned long value = 0, hival = 0;
5742 unsigned shift;
5743 int size = 0;
5744 int isfloat = 0;
5745 void *stream = info->stream;
5746 fprintf_ftype func = info->fprintf_func;
5747
5748 /* On Neon the 'i' bit is at bit 24, on mve it is
5749 at bit 28. */
5750 bits |= ((given >> ibit_loc) & 1) << 7;
5751 bits |= ((given >> 16) & 7) << 4;
5752 bits |= ((given >> 0) & 15) << 0;
5753
5754 if (cmode < 8)
5755 {
5756 shift = (cmode >> 1) & 3;
5757 value = (unsigned long) bits << (8 * shift);
5758 size = 32;
5759 }
5760 else if (cmode < 12)
5761 {
5762 shift = (cmode >> 1) & 1;
5763 value = (unsigned long) bits << (8 * shift);
5764 size = 16;
5765 }
5766 else if (cmode < 14)
5767 {
5768 shift = (cmode & 1) + 1;
5769 value = (unsigned long) bits << (8 * shift);
5770 value |= (1ul << (8 * shift)) - 1;
5771 size = 32;
5772 }
5773 else if (cmode == 14)
5774 {
5775 if (op)
5776 {
5777 /* Bit replication into bytes. */
5778 int ix;
5779 unsigned long mask;
5780
5781 value = 0;
5782 hival = 0;
5783 for (ix = 7; ix >= 0; ix--)
5784 {
5785 mask = ((bits >> ix) & 1) ? 0xff : 0;
5786 if (ix <= 3)
5787 value = (value << 8) | mask;
5788 else
5789 hival = (hival << 8) | mask;
5790 }
5791 size = 64;
5792 }
5793 else
5794 {
5795 /* Byte replication. */
5796 value = (unsigned long) bits;
5797 size = 8;
5798 }
5799 }
5800 else if (!op)
5801 {
5802 /* Floating point encoding. */
5803 int tmp;
5804
5805 value = (unsigned long) (bits & 0x7f) << 19;
5806 value |= (unsigned long) (bits & 0x80) << 24;
5807 tmp = bits & 0x40 ? 0x3c : 0x40;
5808 value |= (unsigned long) tmp << 24;
5809 size = 32;
5810 isfloat = 1;
5811 }
5812 else
5813 {
5814 func (stream, "<illegal constant %.8x:%x:%x>",
5815 bits, cmode, op);
5816 size = 32;
5817 return;
5818 }
5819
5820 // printU determines whether the immediate value should be printed as
5821 // unsigned.
5822 unsigned printU = 0;
5823 switch (insn->mve_op)
5824 {
5825 default:
5826 break;
5827 // We want this for instructions that don't have a 'signed' type
5828 case MVE_VBIC_IMM:
5829 case MVE_VORR_IMM:
5830 case MVE_VMVN_IMM:
5831 case MVE_VMOV_IMM_TO_VEC:
5832 printU = 1;
5833 break;
5834 }
5835 switch (size)
5836 {
5837 case 8:
5838 func (stream, "#%ld\t; 0x%.2lx", value, value);
5839 break;
5840
5841 case 16:
5842 func (stream,
5843 printU
5844 ? "#%lu\t; 0x%.4lx"
5845 : "#%ld\t; 0x%.4lx", value, value);
5846 break;
5847
5848 case 32:
5849 if (isfloat)
5850 {
5851 unsigned char valbytes[4];
5852 double fvalue;
5853
5854 /* Do this a byte at a time so we don't have to
5855 worry about the host's endianness. */
5856 valbytes[0] = value & 0xff;
5857 valbytes[1] = (value >> 8) & 0xff;
5858 valbytes[2] = (value >> 16) & 0xff;
5859 valbytes[3] = (value >> 24) & 0xff;
5860
5861 floatformat_to_double
5862 (& floatformat_ieee_single_little, valbytes,
5863 & fvalue);
5864
5865 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
5866 value);
5867 }
5868 else
5869 func (stream,
5870 printU
5871 ? "#%lu\t; 0x%.8lx"
5872 : "#%ld\t; 0x%.8lx",
5873 (long) (((value & 0x80000000L) != 0)
5874 && !printU
5875 ? value | ~0xffffffffL : value),
5876 value);
5877 break;
5878
5879 case 64:
5880 func (stream, "#0x%.8lx%.8lx", hival, value);
5881 break;
5882
5883 default:
5884 abort ();
5885 }
5886
5887}
5888
73cd51e5
AV		 5889static void
5890print_mve_undefined (struct disassemble_info *info,
5891 enum mve_undefined undefined_code)
5892{
5893 void *stream = info->stream;
5894 fprintf_ftype func = info->fprintf_func;
5895
5896 func (stream, "\t\tundefined instruction: ");
5897
5898 switch (undefined_code)
5899 {
aef6d006
AV		 5900 case UNDEF_SIZE_0:
5901 func (stream, "size equals zero");
5902 break;
5903
c507f10b
AV		 5904 case UNDEF_SIZE_2:
5905 func (stream, "size equals two");
5906 break;
5907
9743db03
AV		 5908 case UNDEF_SIZE_3:
5909 func (stream, "size equals three");
5910 break;
5911
aef6d006
AV		 5912 case UNDEF_SIZE_LE_1:
5913 func (stream, "size <= 1");
5914 break;
5915
ef1576a1
AV		 5916 case UNDEF_SIZE_NOT_2:
5917 func (stream, "size not equal to 2");
5918 break;
5919
5920 case UNDEF_SIZE_NOT_3:
5921 func (stream, "size not equal to 3");
5922 break;
5923
5924 case UNDEF_NOT_UNS_SIZE_0:
5925 func (stream, "not unsigned and size = zero");
5926 break;
5927
5928 case UNDEF_NOT_UNS_SIZE_1:
5929 func (stream, "not unsigned and size = one");
5930 break;
5931
5932 case UNDEF_NOT_UNSIGNED:
5933 func (stream, "not unsigned");
5934 break;
5935
bf0b396d
AV		 5936 case UNDEF_VCVT_IMM6:
5937 func (stream, "invalid imm6");
5938 break;
5939
5940 case UNDEF_VCVT_FSI_IMM6:
5941 func (stream, "fsi = 0 and invalid imm6");
5942 break;
5943
c507f10b
AV		 5944 case UNDEF_BAD_OP1_OP2:
5945 func (stream, "bad size with op2 = 2 and op1 = 0 or 1");
5946 break;
5947
5948 case UNDEF_BAD_U_OP1_OP2:
5949 func (stream, "unsigned with op2 = 0 and op1 = 0 or 1");
5950 break;
5951
5952 case UNDEF_OP_0_BAD_CMODE:
5953 func (stream, "op field equal 0 and bad cmode");
5954 break;
5955
d3b63143
AV		 5956 case UNDEF_XCHG_UNS:
5957 func (stream, "exchange and unsigned together");
5958 break;
5959
73cd51e5
AV		 5960 case UNDEF_NONE:
5961 break;
5962 }
5963
5964}
5965
5966static void
5967print_mve_unpredictable (struct disassemble_info *info,
5968 enum mve_unpredictable unpredict_code)
5969{
5970 void *stream = info->stream;
5971 fprintf_ftype func = info->fprintf_func;
5972
5973 func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
5974
5975 switch (unpredict_code)
5976 {
5977 case UNPRED_IT_BLOCK:
5978 func (stream, "mve instruction in it block");
5979 break;
5980
143275ea
AV		 5981 case UNPRED_FCA_0_FCB_1:
5982 func (stream, "condition bits, fca = 0 and fcb = 1");
5983 break;
5984
5985 case UNPRED_R13:
5986 func (stream, "use of r13 (sp)");
5987 break;
5988
9743db03
AV		 5989 case UNPRED_R15:
5990 func (stream, "use of r15 (pc)");
5991 break;
5992
04d54ace
AV		 5993 case UNPRED_Q_GT_4:
5994 func (stream, "start register block > r4");
5995 break;
5996
5997 case UNPRED_Q_GT_6:
5998 func (stream, "start register block > r6");
5999 break;
6000
6001 case UNPRED_R13_AND_WB:
6002 func (stream, "use of r13 and write back");
6003 break;
6004
ef1576a1
AV		 6005 case UNPRED_Q_REGS_EQUAL:
6006 func (stream,
6007 "same vector register used for destination and other operand");
6008 break;
6009
6010 case UNPRED_OS:
6011 func (stream, "use of offset scaled");
6012 break;
6013
bf0b396d
AV		 6014 case UNPRED_GP_REGS_EQUAL:
6015 func (stream, "same general-purpose register used for both operands");
6016 break;
6017
c507f10b
AV		 6018 case UNPRED_Q_REGS_EQ_AND_SIZE_1:
6019 func (stream, "use of identical q registers and size = 1");
6020 break;
6021
6022 case UNPRED_Q_REGS_EQ_AND_SIZE_2:
6023 func (stream, "use of identical q registers and size = 1");
6024 break;
6025
73cd51e5
AV		 6026 case UNPRED_NONE:
6027 break;
6028 }
6029}
6030
04d54ace
AV		 6031/* Print register block operand for mve vld2/vld4/vst2/vld4. */
6032
6033static void
6034print_mve_register_blocks (struct disassemble_info *info,
6035 unsigned long given,
6036 enum mve_instructions matched_insn)
6037{
6038 void *stream = info->stream;
6039 fprintf_ftype func = info->fprintf_func;
6040
6041 unsigned long q_reg_start = arm_decode_field_multiple (given,
6042 13, 15,
6043 22, 22);
6044 switch (matched_insn)
6045 {
6046 case MVE_VLD2:
6047 case MVE_VST2:
6048 if (q_reg_start <= 6)
6049 func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
6050 else
6051 func (stream, "<illegal reg q%ld>", q_reg_start);
6052 break;
6053
6054 case MVE_VLD4:
6055 case MVE_VST4:
6056 if (q_reg_start <= 4)
6057 func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
6058 q_reg_start + 1, q_reg_start + 2,
6059 q_reg_start + 3);
6060 else
6061 func (stream, "<illegal reg q%ld>", q_reg_start);
6062 break;
6063
6064 default:
6065 break;
6066 }
6067}
6068
bf0b396d
AV		 6069static void
6070print_mve_rounding_mode (struct disassemble_info *info,
6071 unsigned long given,
6072 enum mve_instructions matched_insn)
6073{
6074 void *stream = info->stream;
6075 fprintf_ftype func = info->fprintf_func;
6076
6077 switch (matched_insn)
6078 {
6079 case MVE_VCVT_FROM_FP_TO_INT:
6080 {
6081 switch (arm_decode_field (given, 8, 9))
6082 {
6083 case 0:
6084 func (stream, "a");
6085 break;
6086
6087 case 1:
6088 func (stream, "n");
6089 break;
6090
6091 case 2:
6092 func (stream, "p");
6093 break;
6094
6095 case 3:
6096 func (stream, "m");
6097 break;
6098
6099 default:
6100 break;
6101 }
6102 }
6103 break;
6104
6105 case MVE_VRINT_FP:
6106 {
6107 switch (arm_decode_field (given, 7, 9))
6108 {
6109 case 0:
6110 func (stream, "n");
6111 break;
6112
6113 case 1:
6114 func (stream, "x");
6115 break;
6116
6117 case 2:
6118 func (stream, "a");
6119 break;
6120
6121 case 3:
6122 func (stream, "z");
6123 break;
6124
6125 case 5:
6126 func (stream, "m");
6127 break;
6128
6129 case 7:
6130 func (stream, "p");
6131
6132 case 4:
6133 case 6:
6134 default:
6135 break;
6136 }
6137 }
6138 break;
6139
6140 default:
6141 break;
6142 }
6143}
6144
6145static void
6146print_mve_vcvt_size (struct disassemble_info *info,
6147 unsigned long given,
6148 enum mve_instructions matched_insn)
6149{
6150 unsigned long mode = 0;
6151 void *stream = info->stream;
6152 fprintf_ftype func = info->fprintf_func;
6153
6154 switch (matched_insn)
6155 {
6156 case MVE_VCVT_FP_FIX_VEC:
6157 {
6158 mode = (((given & 0x200) >> 7)
6159 | ((given & 0x10000000) >> 27)
6160 | ((given & 0x100) >> 8));
6161
6162 switch (mode)
6163 {
6164 case 0:
6165 func (stream, "f16.s16");
6166 break;
6167
6168 case 1:
6169 func (stream, "s16.f16");
6170 break;
6171
6172 case 2:
6173 func (stream, "f16.u16");
6174 break;
6175
6176 case 3:
6177 func (stream, "u16.f16");
6178 break;
6179
6180 case 4:
6181 func (stream, "f32.s32");
6182 break;
6183
6184 case 5:
6185 func (stream, "s32.f32");
6186 break;
6187
6188 case 6:
6189 func (stream, "f32.u32");
6190 break;
6191
6192 case 7:
6193 func (stream, "u32.f32");
6194 break;
6195
6196 default:
6197 break;
6198 }
6199 break;
6200 }
6201 case MVE_VCVT_BETWEEN_FP_INT:
6202 {
6203 unsigned long size = arm_decode_field (given, 18, 19);
6204 unsigned long op = arm_decode_field (given, 7, 8);
6205
6206 if (size == 1)
6207 {
6208 switch (op)
6209 {
6210 case 0:
6211 func (stream, "f16.s16");
6212 break;
6213
6214 case 1:
6215 func (stream, "f16.u16");
6216 break;
6217
6218 case 2:
6219 func (stream, "s16.f16");
6220 break;
6221
6222 case 3:
6223 func (stream, "u16.f16");
6224 break;
6225
6226 default:
6227 break;
6228 }
6229 }
6230 else if (size == 2)
6231 {
6232 switch (op)
6233 {
6234 case 0:
6235 func (stream, "f32.s32");
6236 break;
6237
6238 case 1:
6239 func (stream, "f32.u32");
6240 break;
6241
6242 case 2:
6243 func (stream, "s32.f32");
6244 break;
6245
6246 case 3:
6247 func (stream, "u32.f32");
6248 break;
6249 }
6250 }
6251 }
6252 break;
6253
6254 case MVE_VCVT_FP_HALF_FP:
6255 {
6256 unsigned long op = arm_decode_field (given, 28, 28);
6257 if (op == 0)
6258 func (stream, "f16.f32");
6259 else if (op == 1)
6260 func (stream, "f32.f16");
6261 }
6262 break;
6263
6264 case MVE_VCVT_FROM_FP_TO_INT:
6265 {
6266 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
6267
6268 switch (size)
6269 {
6270 case 2:
6271 func (stream, "s16.f16");
6272 break;
6273
6274 case 3:
6275 func (stream, "u16.f16");
6276 break;
6277
6278 case 4:
6279 func (stream, "s32.f32");
6280 break;
6281
6282 case 5:
6283 func (stream, "u32.f32");
6284 break;
6285
6286 default:
6287 break;
6288 }
6289 }
6290 break;
6291
6292 default:
6293 break;
6294 }
6295}
6296
897b9bbc
AV		 6297static void
6298print_mve_rotate (struct disassemble_info *info, unsigned long rot,
6299 unsigned long rot_width)
6300{
6301 void *stream = info->stream;
6302 fprintf_ftype func = info->fprintf_func;
6303
6304 if (rot_width == 1)
6305 {
6306 switch (rot)
6307 {
6308 case 0:
6309 func (stream, "90");
6310 break;
6311 case 1:
6312 func (stream, "270");
6313 break;
6314 default:
6315 break;
6316 }
6317 }
6318 else if (rot_width == 2)
6319 {
6320 switch (rot)
6321 {
6322 case 0:
6323 func (stream, "0");
6324 break;
6325 case 1:
6326 func (stream, "90");
6327 break;
6328 case 2:
6329 func (stream, "180");
6330 break;
6331 case 3:
6332 func (stream, "270");
6333 break;
6334 default:
6335 break;
6336 }
6337 }
6338}
6339
143275ea
AV		 6340static void
6341print_instruction_predicate (struct disassemble_info *info)
6342{
6343 void *stream = info->stream;
6344 fprintf_ftype func = info->fprintf_func;
6345
6346 if (vpt_block_state.next_pred_state == PRED_THEN)
6347 func (stream, "t");
6348 else if (vpt_block_state.next_pred_state == PRED_ELSE)
6349 func (stream, "e");
6350}
6351
6352static void
6353print_mve_size (struct disassemble_info *info,
6354 unsigned long size,
6355 enum mve_instructions matched_insn)
6356{
6357 void *stream = info->stream;
6358 fprintf_ftype func = info->fprintf_func;
6359
6360 switch (matched_insn)
6361 {
d3b63143 6362 case MVE_VADDV:
897b9bbc 6363 case MVE_VCADD_VEC:
143275ea
AV		 6364 case MVE_VCMP_VEC_T1:
6365 case MVE_VCMP_VEC_T2:
6366 case MVE_VCMP_VEC_T3:
6367 case MVE_VCMP_VEC_T4:
6368 case MVE_VCMP_VEC_T5:
6369 case MVE_VCMP_VEC_T6:
1c8f2df8
AV		 6370 case MVE_VDDUP:
6371 case MVE_VDWDUP:
9743db03
AV		 6372 case MVE_VHADD_T1:
6373 case MVE_VHADD_T2:
897b9bbc 6374 case MVE_VHCADD:
9743db03
AV		 6375 case MVE_VHSUB_T1:
6376 case MVE_VHSUB_T2:
1c8f2df8
AV		 6377 case MVE_VIDUP:
6378 case MVE_VIWDUP:
04d54ace
AV		 6379 case MVE_VLD2:
6380 case MVE_VLD4:
ef1576a1
AV		 6381 case MVE_VLDRB_GATHER_T1:
6382 case MVE_VLDRH_GATHER_T2:
6383 case MVE_VLDRW_GATHER_T3:
6384 case MVE_VLDRD_GATHER_T4:
aef6d006
AV		 6385 case MVE_VLDRB_T1:
6386 case MVE_VLDRH_T2:
d3b63143 6387 case MVE_VMLAS:
143275ea
AV		 6388 case MVE_VPT_VEC_T1:
6389 case MVE_VPT_VEC_T2:
6390 case MVE_VPT_VEC_T3:
6391 case MVE_VPT_VEC_T4:
6392 case MVE_VPT_VEC_T5:
6393 case MVE_VPT_VEC_T6:
d3b63143
AV		 6394 case MVE_VQDMLADH:
6395 case MVE_VQRDMLADH:
6396 case MVE_VQDMLAH:
6397 case MVE_VQRDMLAH:
6398 case MVE_VQDMLASH:
6399 case MVE_VQRDMLASH:
6400 case MVE_VQDMLSDH:
6401 case MVE_VQRDMLSDH:
6402 case MVE_VQDMULH_T1:
6403 case MVE_VQRDMULH_T2:
6404 case MVE_VQDMULH_T3:
6405 case MVE_VQRDMULH_T4:
9743db03 6406 case MVE_VRHADD:
bf0b396d 6407 case MVE_VRINT_FP:
04d54ace
AV		 6408 case MVE_VST2:
6409 case MVE_VST4:
ef1576a1
AV		 6410 case MVE_VSTRB_SCATTER_T1:
6411 case MVE_VSTRH_SCATTER_T2:
6412 case MVE_VSTRW_SCATTER_T3:
aef6d006
AV		 6413 case MVE_VSTRB_T1:
6414 case MVE_VSTRH_T2:
143275ea
AV		 6415 if (size <= 3)
6416 func (stream, "%s", mve_vec_sizename[size]);
6417 else
6418 func (stream, "<undef size>");
6419 break;
6420
6421 case MVE_VCMP_FP_T1:
6422 case MVE_VCMP_FP_T2:
9743db03
AV		 6423 case MVE_VFMA_FP_SCALAR:
6424 case MVE_VFMA_FP:
6425 case MVE_VFMS_FP:
6426 case MVE_VFMAS_FP_SCALAR:
143275ea
AV		 6427 case MVE_VPT_FP_T1:
6428 case MVE_VPT_FP_T2:
6429 if (size == 0)
6430 func (stream, "32");
6431 else if (size == 1)
6432 func (stream, "16");
6433 break;
6434
897b9bbc
AV		 6435 case MVE_VCADD_FP:
6436 case MVE_VCMLA_FP:
6437 case MVE_VCMUL_FP:
d3b63143
AV		 6438 case MVE_VMLADAV_T1:
6439 case MVE_VMLALDAV:
6440 case MVE_VMLSDAV_T1:
6441 case MVE_VMLSLDAV:
14925797
AV		 6442 case MVE_VMOVN:
6443 case MVE_VQDMULL_T1:
6444 case MVE_VQDMULL_T2:
6445 case MVE_VQMOVN:
6446 case MVE_VQMOVUN:
6447 if (size == 0)
6448 func (stream, "16");
6449 else if (size == 1)
6450 func (stream, "32");
6451 break;
6452
6453 case MVE_VMOVL:
6454 if (size == 1)
6455 func (stream, "8");
6456 else if (size == 2)
6457 func (stream, "16");
6458 break;
6459
9743db03
AV		 6460 case MVE_VDUP:
6461 switch (size)
6462 {
6463 case 0:
6464 func (stream, "32");
6465 break;
6466 case 1:
6467 func (stream, "16");
6468 break;
6469 case 2:
6470 func (stream, "8");
6471 break;
6472 default:
6473 break;
6474 }
6475 break;
6476
c507f10b
AV		 6477 case MVE_VMOV_GP_TO_VEC_LANE:
6478 case MVE_VMOV_VEC_LANE_TO_GP:
6479 switch (size)
6480 {
6481 case 0: case 4:
6482 func (stream, "32");
6483 break;
6484
6485 case 1: case 3:
6486 case 5: case 7:
6487 func (stream, "16");
6488 break;
6489
6490 case 8: case 9: case 10: case 11:
6491 case 12: case 13: case 14: case 15:
6492 func (stream, "8");
6493 break;
6494
6495 default:
6496 break;
6497 }
6498 break;
6499
6500 case MVE_VMOV_IMM_TO_VEC:
6501 switch (size)
6502 {
6503 case 0: case 4: case 8:
6504 case 12: case 24: case 26:
6505 func (stream, "i32");
6506 break;
6507 case 16: case 20:
6508 func (stream, "i16");
6509 break;
6510 case 28:
6511 func (stream, "i8");
6512 break;
6513 case 29:
6514 func (stream, "i64");
6515 break;
6516 case 30:
6517 func (stream, "f32");
6518 break;
6519 default:
6520 break;
6521 }
6522 break;
6523
14925797
AV		 6524 case MVE_VMULL_POLY:
6525 if (size == 0)
6526 func (stream, "p8");
6527 else if (size == 1)
6528 func (stream, "p16");
6529 break;
6530
c507f10b
AV		 6531 case MVE_VMVN_IMM:
6532 switch (size)
6533 {
6534 case 0: case 2: case 4:
6535 case 6: case 12: case 13:
6536 func (stream, "32");
6537 break;
6538
6539 case 8: case 10:
6540 func (stream, "16");
6541 break;
6542
6543 default:
6544 break;
6545 }
6546 break;
6547
6548 case MVE_VBIC_IMM:
6549 case MVE_VORR_IMM:
6550 switch (size)
6551 {
6552 case 1: case 3:
6553 case 5: case 7:
6554 func (stream, "32");
6555 break;
6556
6557 case 9: case 11:
6558 func (stream, "16");
6559 break;
6560
6561 default:
6562 break;
6563 }
6564 break;
6565
143275ea
AV		 6566 default:
6567 break;
6568 }
6569}
6570
6571static void
6572print_vec_condition (struct disassemble_info *info, long given,
6573 enum mve_instructions matched_insn)
6574{
6575 void *stream = info->stream;
6576 fprintf_ftype func = info->fprintf_func;
6577 long vec_cond = 0;
6578
6579 switch (matched_insn)
6580 {
6581 case MVE_VPT_FP_T1:
6582 case MVE_VCMP_FP_T1:
6583 vec_cond = (((given & 0x1000) >> 10)
6584 | ((given & 1) << 1)
6585 | ((given & 0x0080) >> 7));
6586 func (stream, "%s",vec_condnames[vec_cond]);
6587 break;
6588
6589 case MVE_VPT_FP_T2:
6590 case MVE_VCMP_FP_T2:
6591 vec_cond = (((given & 0x1000) >> 10)
6592 | ((given & 0x0020) >> 4)
6593 | ((given & 0x0080) >> 7));
6594 func (stream, "%s",vec_condnames[vec_cond]);
6595 break;
6596
6597 case MVE_VPT_VEC_T1:
6598 case MVE_VCMP_VEC_T1:
6599 vec_cond = (given & 0x0080) >> 7;
6600 func (stream, "%s",vec_condnames[vec_cond]);
6601 break;
6602
6603 case MVE_VPT_VEC_T2:
6604 case MVE_VCMP_VEC_T2:
6605 vec_cond = 2 | ((given & 0x0080) >> 7);
6606 func (stream, "%s",vec_condnames[vec_cond]);
6607 break;
6608
6609 case MVE_VPT_VEC_T3:
6610 case MVE_VCMP_VEC_T3:
6611 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
6612 func (stream, "%s",vec_condnames[vec_cond]);
6613 break;
6614
6615 case MVE_VPT_VEC_T4:
6616 case MVE_VCMP_VEC_T4:
6617 vec_cond = (given & 0x0080) >> 7;
6618 func (stream, "%s",vec_condnames[vec_cond]);
6619 break;
6620
6621 case MVE_VPT_VEC_T5:
6622 case MVE_VCMP_VEC_T5:
6623 vec_cond = 2 | ((given & 0x0080) >> 7);
6624 func (stream, "%s",vec_condnames[vec_cond]);
6625 break;
6626
6627 case MVE_VPT_VEC_T6:
6628 case MVE_VCMP_VEC_T6:
6629 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
6630 func (stream, "%s",vec_condnames[vec_cond]);
6631 break;
6632
6633 case MVE_NONE:
6634 case MVE_VPST:
6635 default:
6636 break;
6637 }
6638}
6639
6640#define W_BIT 21
6641#define I_BIT 22
6642#define U_BIT 23
6643#define P_BIT 24
6644
6645#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
6646#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
6647#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
6648#define PRE_BIT_SET (given & (1 << P_BIT))
6649
6650
8f06b2d8
PB		 6651/* Print one coprocessor instruction on INFO->STREAM.
6652 Return TRUE if the instuction matched, FALSE if this is not a
6653 recognised coprocessor instruction. */
6654
6655static bfd_boolean
fe56b6ce
NC		 6656print_insn_coprocessor (bfd_vma pc,
6657 struct disassemble_info *info,
6658 long given,
8f06b2d8
PB		 6659 bfd_boolean thumb)
6660{
6b0dd094 6661 const struct sopcode32 *insn;
8f06b2d8
PB		 6662 void *stream = info->stream;
6663 fprintf_ftype func = info->fprintf_func;
6664 unsigned long mask;
2edcd244 6665 unsigned long value = 0;
c22aaad1 6666 int cond;
8afc7bea 6667 int cp_num;
823d2571
TG		 6668 struct arm_private_data *private_data = info->private_data;
6669 arm_feature_set allowed_arches = ARM_ARCH_NONE;
32c36c3c
AV		 6670 arm_feature_set arm_ext_v8_1m_main =
6671 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
823d2571 6672
5b616bef 6673 allowed_arches = private_data->features;
8f06b2d8
PB		 6674
6675 for (insn = coprocessor_opcodes; insn->assembler; insn++)
6676 {
ff4a8d2b
NC		 6677 unsigned long u_reg = 16;
6678 bfd_boolean is_unpredictable = FALSE;
05413229 6679 signed long value_in_comment = 0;
0313a2b8
NC		 6680 const char *c;
6681
823d2571 6682 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 6683 switch (insn->value)
6684 {
6685 case SENTINEL_IWMMXT_START:
6686 if (info->mach != bfd_mach_arm_XScale
6687 && info->mach != bfd_mach_arm_iWMMXt
6688 && info->mach != bfd_mach_arm_iWMMXt2)
6689 do
6690 insn++;
823d2571
TG		 6691 while ((! ARM_FEATURE_ZERO (insn->arch))
6692 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 6693 continue;
6694
6695 case SENTINEL_IWMMXT_END:
6696 continue;
6697
6698 case SENTINEL_GENERIC_START:
5b616bef 6699 allowed_arches = private_data->features;
05413229
NC		 6700 continue;
6701
6702 default:
6703 abort ();
6704 }
8f06b2d8
PB		 6705
6706 mask = insn->mask;
6707 value = insn->value;
8afc7bea
RL		 6708 cp_num = (given >> 8) & 0xf;
6709
8f06b2d8
PB		 6710 if (thumb)
6711 {
6712 /* The high 4 bits are 0xe for Arm conditional instructions, and
6713 0xe for arm unconditional instructions. The rest of the
6714 encoding is the same. */
6715 mask |= 0xf0000000;
6716 value |= 0xe0000000;
c22aaad1
PB		 6717 if (ifthen_state)
6718 cond = IFTHEN_COND;
6719 else
e2efe87d 6720 cond = COND_UNCOND;
8f06b2d8
PB		 6721 }
6722 else
6723 {
6724 /* Only match unconditional instuctions against unconditional
6725 patterns. */
6726 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 6727 {
6728 mask |= 0xf0000000;
e2efe87d 6729 cond = COND_UNCOND;
c22aaad1
PB		 6730 }
6731 else
6732 {
6733 cond = (given >> 28) & 0xf;
6734 if (cond == 0xe)
e2efe87d 6735 cond = COND_UNCOND;
c22aaad1 6736 }
8f06b2d8 6737 }
823d2571 6738
6b0dd094
AV		 6739 if ((insn->isa == T32 && !thumb)
6740 || (insn->isa == ARM && thumb))
6741 continue;
6742
0313a2b8
NC		 6743 if ((given & mask) != value)
6744 continue;
8f06b2d8 6745
823d2571 6746 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 6747 continue;
6748
8afc7bea
RL		 6749 if (insn->value == 0xfe000010 /* mcr2 */
6750 || insn->value == 0xfe100010 /* mrc2 */
6751 || insn->value == 0xfc100000 /* ldc2 */
6752 || insn->value == 0xfc000000) /* stc2 */
6753 {
b0c11777 6754 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 6755 is_unpredictable = TRUE;
f08d8ce3
AV		 6756
6757 /* Armv8.1-M Mainline FP & MVE instructions. */
6758 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
6759 && !ARM_CPU_IS_ANY (allowed_arches)
6760 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
6761 continue;
6762
8afc7bea
RL		 6763 }
6764 else if (insn->value == 0x0e000000 /* cdp */
6765 || insn->value == 0xfe000000 /* cdp2 */
6766 || insn->value == 0x0e000010 /* mcr */
6767 || insn->value == 0x0e100010 /* mrc */
6768 || insn->value == 0x0c100000 /* ldc */
6769 || insn->value == 0x0c000000) /* stc */
6770 {
6771 /* Floating-point instructions. */
b0c11777 6772 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 6773 continue;
32c36c3c
AV		 6774
6775 /* Armv8.1-M Mainline FP & MVE instructions. */
6776 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
6777 && !ARM_CPU_IS_ANY (allowed_arches)
6778 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
6779 continue;
8afc7bea 6780 }
aef6d006
AV		 6781 else if ((insn->value == 0xec100f80 /* vldr (system register) */
6782 || insn->value == 0xec000f80) /* vstr (system register) */
6783 && arm_decode_field (given, 24, 24) == 0
6784 && arm_decode_field (given, 21, 21) == 0)
6785 /* If the P and W bits are both 0 then these encodings match the MVE
6786 VLDR and VSTR instructions, these are in a different table, so we
6787 don't let it match here. */
6788 continue;
6789
0313a2b8
NC		 6790 for (c = insn->assembler; *c; c++)
6791 {
6792 if (*c == '%')
8f06b2d8 6793 {
32c36c3c
AV		 6794 const char mod = *++c;
6795 switch (mod)
8f06b2d8 6796 {
0313a2b8
NC		 6797 case '%':
6798 func (stream, "%%");
6799 break;
6800
6801 case 'A':
32c36c3c 6802 case 'K':
05413229 6803 {
79862e45 6804 int rn = (given >> 16) & 0xf;
b0c11777 6805 bfd_vma offset = given & 0xff;
0313a2b8 6806
32c36c3c
AV		 6807 if (mod == 'K')
6808 offset = given & 0x7f;
6809
05413229 6810 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 6811
79862e45
DJ		 6812 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
6813 {
6814 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 6815 if (cp_num == 9)
6816 /* vldr.16/vstr.16 will shift the address
6817 left by 1 bit only. */
6818 offset = offset * 2;
6819 else
6820 offset = offset * 4;
6821
79862e45
DJ		 6822 if (NEGATIVE_BIT_SET)
6823 offset = - offset;
6824 if (rn != 15)
6825 value_in_comment = offset;
6826 }
6827
c1e26897 6828 if (PRE_BIT_SET)
05413229
NC		 6829 {
6830 if (offset)
fe56b6ce 6831 func (stream, ", #%d]%s",
d908c8af 6832 (int) offset,
c1e26897 6833 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 6834 else if (NEGATIVE_BIT_SET)
6835 func (stream, ", #-0]");
05413229
NC		 6836 else
6837 func (stream, "]");
6838 }
6839 else
6840 {
0313a2b8 6841 func (stream, "]");
8f06b2d8 6842
c1e26897 6843 if (WRITEBACK_BIT_SET)
05413229
NC		 6844 {
6845 if (offset)
d908c8af 6846 func (stream, ", #%d", (int) offset);
26d97720
NS		 6847 else if (NEGATIVE_BIT_SET)
6848 func (stream, ", #-0");
05413229
NC		 6849 }
6850 else
fe56b6ce 6851 {
26d97720
NS		 6852 func (stream, ", {%s%d}",
6853 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 6854 (int) offset);
fe56b6ce
NC		 6855 value_in_comment = offset;
6856 }
05413229 6857 }
79862e45
DJ		 6858 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
6859 {
6860 func (stream, "\t; ");
6844b2c2
MGD		 6861 /* For unaligned PCs, apply off-by-alignment
6862 correction. */
43e65147 6863 info->print_address_func (offset + pc
6844b2c2
MGD		 6864 + info->bytes_per_chunk * 2
6865 - (pc & 3),
dffaa15c 6866 info);
79862e45 6867 }
05413229 6868 }
0313a2b8 6869 break;
8f06b2d8 6870
0313a2b8
NC		 6871 case 'B':
6872 {
6873 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
6874 int offset = (given >> 1) & 0x3f;
6875
6876 if (offset == 1)
6877 func (stream, "{d%d}", regno);
6878 else if (regno + offset > 32)
6879 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
6880 else
6881 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
6882 }
6883 break;
8f06b2d8 6884
efd6b359
AV		 6885 case 'C':
6886 {
6887 bfd_boolean single = ((given >> 8) & 1) == 0;
6888 char reg_prefix = single ? 's' : 'd';
6889 int Dreg = (given >> 22) & 0x1;
6890 int Vdreg = (given >> 12) & 0xf;
6891 int reg = single ? ((Vdreg << 1) | Dreg)
6892 : ((Dreg << 4) | Vdreg);
6893 int num = (given >> (single ? 0 : 1)) & 0x7f;
6894 int maxreg = single ? 31 : 15;
6895 int topreg = reg + num - 1;
6896
6897 if (!num)
6898 func (stream, "{VPR}");
6899 else if (num == 1)
6900 func (stream, "{%c%d, VPR}", reg_prefix, reg);
6901 else if (topreg > maxreg)
6902 func (stream, "{%c%d-<overflow reg d%d, VPR}",
6903 reg_prefix, reg, single ? topreg >> 1 : topreg);
6904 else
6905 func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
6906 reg_prefix, topreg);
6907 }
6908 break;
6909
e2efe87d
MGD		 6910 case 'u':
6911 if (cond != COND_UNCOND)
6912 is_unpredictable = TRUE;
6913
6914 /* Fall through. */
0313a2b8 6915 case 'c':
b0c11777
RL		 6916 if (cond != COND_UNCOND && cp_num == 9)
6917 is_unpredictable = TRUE;
6918
0313a2b8
NC		 6919 func (stream, "%s", arm_conditional[cond]);
6920 break;
8f06b2d8 6921
0313a2b8
NC		 6922 case 'I':
6923 /* Print a Cirrus/DSP shift immediate. */
6924 /* Immediates are 7bit signed ints with bits 0..3 in
6925 bits 0..3 of opcode and bits 4..6 in bits 5..7
6926 of opcode. */
6927 {
6928 int imm;
8f06b2d8 6929
0313a2b8 6930 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 6931
0313a2b8
NC		 6932 /* Is ``imm'' a negative number? */
6933 if (imm & 0x40)
24b4cf66 6934 imm -= 0x80;
8f06b2d8 6935
0313a2b8
NC		 6936 func (stream, "%d", imm);
6937 }
6938
6939 break;
8f06b2d8 6940
32c36c3c
AV		 6941 case 'J':
6942 {
73cd51e5
AV		 6943 unsigned long regno
6944 = arm_decode_field_multiple (given, 13, 15, 22, 22);
32c36c3c
AV		 6945
6946 switch (regno)
6947 {
6948 case 0x1:
6949 func (stream, "FPSCR");
6950 break;
6951 case 0x2:
6952 func (stream, "FPSCR_nzcvqc");
6953 break;
6954 case 0xc:
6955 func (stream, "VPR");
6956 break;
6957 case 0xd:
6958 func (stream, "P0");
6959 break;
6960 case 0xe:
6961 func (stream, "FPCXTNS");
6962 break;
6963 case 0xf:
6964 func (stream, "FPCXTS");
6965 break;
6966 default:
73cd51e5 6967 func (stream, "<invalid reg %lu>", regno);
32c36c3c
AV		 6968 break;
6969 }
6970 }
6971 break;
6972
0313a2b8
NC		 6973 case 'F':
6974 switch (given & 0x00408000)
6975 {
6976 case 0:
6977 func (stream, "4");
6978 break;
6979 case 0x8000:
6980 func (stream, "1");
6981 break;
6982 case 0x00400000:
6983 func (stream, "2");
8f06b2d8 6984 break;
0313a2b8
NC		 6985 default:
6986 func (stream, "3");
6987 }
6988 break;
8f06b2d8 6989
0313a2b8
NC		 6990 case 'P':
6991 switch (given & 0x00080080)
6992 {
6993 case 0:
6994 func (stream, "s");
6995 break;
6996 case 0x80:
6997 func (stream, "d");
6998 break;
6999 case 0x00080000:
7000 func (stream, "e");
7001 break;
7002 default:
7003 func (stream, _("<illegal precision>"));
8f06b2d8 7004 break;
0313a2b8
NC		 7005 }
7006 break;
8f06b2d8 7007
0313a2b8
NC		 7008 case 'Q':
7009 switch (given & 0x00408000)
7010 {
7011 case 0:
7012 func (stream, "s");
8f06b2d8 7013 break;
0313a2b8
NC		 7014 case 0x8000:
7015 func (stream, "d");
8f06b2d8 7016 break;
0313a2b8
NC		 7017 case 0x00400000:
7018 func (stream, "e");
7019 break;
7020 default:
7021 func (stream, "p");
8f06b2d8 7022 break;
0313a2b8
NC		 7023 }
7024 break;
8f06b2d8 7025
0313a2b8
NC		 7026 case 'R':
7027 switch (given & 0x60)
7028 {
7029 case 0:
7030 break;
7031 case 0x20:
7032 func (stream, "p");
7033 break;
7034 case 0x40:
7035 func (stream, "m");
7036 break;
7037 default:
7038 func (stream, "z");
7039 break;
7040 }
7041 break;
16980d0b 7042
0313a2b8
NC		 7043 case '0': case '1': case '2': case '3': case '4':
7044 case '5': case '6': case '7': case '8': case '9':
7045 {
7046 int width;
8f06b2d8 7047
0313a2b8 7048 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 7049
0313a2b8
NC		 7050 switch (*c)
7051 {
ff4a8d2b
NC		 7052 case 'R':
7053 if (value == 15)
7054 is_unpredictable = TRUE;
7055 /* Fall through. */
0313a2b8 7056 case 'r':
ff4a8d2b
NC		 7057 if (c[1] == 'u')
7058 {
7059 /* Eat the 'u' character. */
7060 ++ c;
7061
7062 if (u_reg == value)
7063 is_unpredictable = TRUE;
7064 u_reg = value;
7065 }
0313a2b8
NC		 7066 func (stream, "%s", arm_regnames[value]);
7067 break;
c28eeff2
SN		 7068 case 'V':
7069 if (given & (1 << 6))
7070 goto Q;
7071 /* FALLTHROUGH */
0313a2b8
NC		 7072 case 'D':
7073 func (stream, "d%ld", value);
7074 break;
7075 case 'Q':
c28eeff2 7076 Q:
0313a2b8
NC		 7077 if (value & 1)
7078 func (stream, "<illegal reg q%ld.5>", value >> 1);
7079 else
7080 func (stream, "q%ld", value >> 1);
7081 break;
7082 case 'd':
7083 func (stream, "%ld", value);
05413229 7084 value_in_comment = value;
0313a2b8 7085 break;
6f1c2142
AM		 7086 case 'E':
7087 {
7088 /* Converts immediate 8 bit back to float value. */
7089 unsigned floatVal = (value & 0x80) << 24
7090 | (value & 0x3F) << 19
7091 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
7092
7093 /* Quarter float have a maximum value of 31.0.
7094 Get floating point value multiplied by 1e7.
7095 The maximum value stays in limit of a 32-bit int. */
7096 unsigned decVal =
7097 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
7098 (16 + (value & 0xF));
7099
7100 if (!(decVal % 1000000))
7101 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
7102 floatVal, value & 0x80 ? '-' : ' ',
7103 decVal / 10000000,
7104 decVal % 10000000 / 1000000);
7105 else if (!(decVal % 10000))
7106 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
7107 floatVal, value & 0x80 ? '-' : ' ',
7108 decVal / 10000000,
7109 decVal % 10000000 / 10000);
7110 else
7111 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
7112 floatVal, value & 0x80 ? '-' : ' ',
7113 decVal / 10000000, decVal % 10000000);
7114 break;
7115 }
0313a2b8
NC		 7116 case 'k':
7117 {
7118 int from = (given & (1 << 7)) ? 32 : 16;
7119 func (stream, "%ld", from - value);
7120 }
7121 break;
8f06b2d8 7122
0313a2b8
NC		 7123 case 'f':
7124 if (value > 7)
7125 func (stream, "#%s", arm_fp_const[value & 7]);
7126 else
7127 func (stream, "f%ld", value);
7128 break;
4146fd53 7129
0313a2b8
NC		 7130 case 'w':
7131 if (width == 2)
7132 func (stream, "%s", iwmmxt_wwnames[value]);
7133 else
7134 func (stream, "%s", iwmmxt_wwssnames[value]);
7135 break;
4146fd53 7136
0313a2b8
NC		 7137 case 'g':
7138 func (stream, "%s", iwmmxt_regnames[value]);
7139 break;
7140 case 'G':
7141 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 7142 break;
8f06b2d8 7143
0313a2b8 7144 case 'x':
d1aaab3c 7145 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 7146 break;
8f06b2d8 7147
33399f07
MGD		 7148 case 'c':
7149 switch (value)
7150 {
7151 case 0:
7152 func (stream, "eq");
7153 break;
7154
7155 case 1:
7156 func (stream, "vs");
7157 break;
7158
7159 case 2:
7160 func (stream, "ge");
7161 break;
7162
7163 case 3:
7164 func (stream, "gt");
7165 break;
7166
7167 default:
7168 func (stream, "??");
7169 break;
7170 }
7171 break;
7172
0313a2b8
NC		 7173 case '`':
7174 c++;
7175 if (value == 0)
7176 func (stream, "%c", *c);
7177 break;
7178 case '\'':
7179 c++;
7180 if (value == ((1ul << width) - 1))
7181 func (stream, "%c", *c);
7182 break;
7183 case '?':
fe56b6ce 7184 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 7185 c += 1 << width;
7186 break;
7187 default:
7188 abort ();
7189 }
dffaa15c
AM		 7190 }
7191 break;
0313a2b8 7192
dffaa15c
AM		 7193 case 'y':
7194 case 'z':
7195 {
7196 int single = *c++ == 'y';
7197 int regno;
8f06b2d8 7198
dffaa15c
AM		 7199 switch (*c)
7200 {
7201 case '4': /* Sm pair */
7202 case '0': /* Sm, Dm */
7203 regno = given & 0x0000000f;
7204 if (single)
7205 {
7206 regno <<= 1;
7207 regno += (given >> 5) & 1;
7208 }
7209 else
7210 regno += ((given >> 5) & 1) << 4;
7211 break;
8f06b2d8 7212
dffaa15c
AM		 7213 case '1': /* Sd, Dd */
7214 regno = (given >> 12) & 0x0000000f;
7215 if (single)
7216 {
7217 regno <<= 1;
7218 regno += (given >> 22) & 1;
7219 }
7220 else
7221 regno += ((given >> 22) & 1) << 4;
7222 break;
7df76b80 7223
dffaa15c
AM		 7224 case '2': /* Sn, Dn */
7225 regno = (given >> 16) & 0x0000000f;
7226 if (single)
7227 {
7228 regno <<= 1;
7229 regno += (given >> 7) & 1;
7230 }
7231 else
7232 regno += ((given >> 7) & 1) << 4;
7233 break;
a7f8487e 7234
dffaa15c
AM		 7235 case '3': /* List */
7236 func (stream, "{");
7237 regno = (given >> 12) & 0x0000000f;
7238 if (single)
7239 {
7240 regno <<= 1;
7241 regno += (given >> 22) & 1;
7242 }
7243 else
7244 regno += ((given >> 22) & 1) << 4;
7245 break;
a7f8487e 7246
dffaa15c
AM		 7247 default:
7248 abort ();
7249 }
0313a2b8 7250
dffaa15c 7251 func (stream, "%c%d", single ? 's' : 'd', regno);
a7f8487e 7252
dffaa15c
AM		 7253 if (*c == '3')
7254 {
7255 int count = given & 0xff;
b34976b6 7256
dffaa15c
AM		 7257 if (single == 0)
7258 count >>= 1;
0313a2b8 7259
dffaa15c
AM		 7260 if (--count)
7261 {
7262 func (stream, "-%c%d",
7263 single ? 's' : 'd',
7264 regno + count);
7265 }
0313a2b8 7266
dffaa15c 7267 func (stream, "}");
0313a2b8 7268 }
dffaa15c
AM		 7269 else if (*c == '4')
7270 func (stream, ", %c%d", single ? 's' : 'd',
7271 regno + 1);
7272 }
7273 break;
b34976b6 7274
dffaa15c
AM		 7275 case 'L':
7276 switch (given & 0x00400100)
0313a2b8 7277 {
dffaa15c
AM		 7278 case 0x00000000: func (stream, "b"); break;
7279 case 0x00400000: func (stream, "h"); break;
7280 case 0x00000100: func (stream, "w"); break;
7281 case 0x00400100: func (stream, "d"); break;
7282 default:
7283 break;
0313a2b8 7284 }
dffaa15c 7285 break;
2d447fca 7286
dffaa15c
AM		 7287 case 'Z':
7288 {
7289 /* given (20, 23) | given (0, 3) */
7290 value = ((given >> 16) & 0xf0) | (given & 0xf);
7291 func (stream, "%d", (int) value);
7292 }
7293 break;
0313a2b8 7294
dffaa15c
AM		 7295 case 'l':
7296 /* This is like the 'A' operator, except that if
7297 the width field "M" is zero, then the offset is
7298 *not* multiplied by four. */
7299 {
7300 int offset = given & 0xff;
7301 int multiplier = (given & 0x00000100) ? 4 : 1;
0313a2b8 7302
dffaa15c 7303 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
05413229 7304
dffaa15c
AM		 7305 if (multiplier > 1)
7306 {
7307 value_in_comment = offset * multiplier;
7308 if (NEGATIVE_BIT_SET)
7309 value_in_comment = - value_in_comment;
7310 }
0313a2b8 7311
dffaa15c
AM		 7312 if (offset)
7313 {
7314 if (PRE_BIT_SET)
7315 func (stream, ", #%s%d]%s",
7316 NEGATIVE_BIT_SET ? "-" : "",
7317 offset * multiplier,
7318 WRITEBACK_BIT_SET ? "!" : "");
7319 else
7320 func (stream, "], #%s%d",
7321 NEGATIVE_BIT_SET ? "-" : "",
7322 offset * multiplier);
7323 }
7324 else
7325 func (stream, "]");
7326 }
7327 break;
2d447fca 7328
dffaa15c
AM		 7329 case 'r':
7330 {
7331 int imm4 = (given >> 4) & 0xf;
7332 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
7333 int ubit = ! NEGATIVE_BIT_SET;
7334 const char *rm = arm_regnames [given & 0xf];
7335 const char *rn = arm_regnames [(given >> 16) & 0xf];
0313a2b8 7336
dffaa15c
AM		 7337 switch (puw_bits)
7338 {
7339 case 1:
7340 case 3:
7341 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
7342 if (imm4)
7343 func (stream, ", lsl #%d", imm4);
7344 break;
0313a2b8 7345
dffaa15c
AM		 7346 case 4:
7347 case 5:
7348 case 6:
7349 case 7:
7350 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
7351 if (imm4 > 0)
7352 func (stream, ", lsl #%d", imm4);
7353 func (stream, "]");
7354 if (puw_bits == 5 || puw_bits == 7)
7355 func (stream, "!");
7356 break;
2d447fca 7357
dffaa15c
AM		 7358 default:
7359 func (stream, "INVALID");
7360 }
7361 }
7362 break;
0313a2b8 7363
dffaa15c
AM		 7364 case 'i':
7365 {
7366 long imm5;
7367 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
7368 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
0313a2b8 7369 }
dffaa15c
AM		 7370 break;
7371
7372 default:
7373 abort ();
252b5132 7374 }
252b5132 7375 }
0313a2b8
NC		 7376 else
7377 func (stream, "%c", *c);
252b5132 7378 }
05413229
NC		 7379
7380 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 7381 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 7382
ff4a8d2b
NC		 7383 if (is_unpredictable)
7384 func (stream, UNPREDICTABLE_INSTRUCTION);
7385
0313a2b8 7386 return TRUE;
252b5132 7387 }
8f06b2d8 7388 return FALSE;
252b5132
RH		 7389}
7390
05413229
NC		 7391/* Decodes and prints ARM addressing modes. Returns the offset
7392 used in the address, if any, if it is worthwhile printing the
7393 offset as a hexadecimal value in a comment at the end of the
7394 line of disassembly. */
7395
7396static signed long
62b3e311
PB		 7397print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
7398{
7399 void *stream = info->stream;
7400 fprintf_ftype func = info->fprintf_func;
f8b960bc 7401 bfd_vma offset = 0;
62b3e311
PB		 7402
7403 if (((given & 0x000f0000) == 0x000f0000)
7404 && ((given & 0x02000000) == 0))
7405 {
05413229 7406 offset = given & 0xfff;
62b3e311
PB		 7407
7408 func (stream, "[pc");
7409
c1e26897 7410 if (PRE_BIT_SET)
62b3e311 7411 {
26d97720
NS		 7412 /* Pre-indexed. Elide offset of positive zero when
7413 non-writeback. */
7414 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 7415 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 7416
7417 if (NEGATIVE_BIT_SET)
7418 offset = -offset;
62b3e311
PB		 7419
7420 offset += pc + 8;
7421
7422 /* Cope with the possibility of write-back
7423 being used. Probably a very dangerous thing
7424 for the programmer to do, but who are we to
7425 argue ? */
26d97720 7426 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 7427 }
c1e26897 7428 else /* Post indexed. */
62b3e311 7429 {
d908c8af 7430 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 7431
c1e26897 7432 /* Ie ignore the offset. */
62b3e311
PB		 7433 offset = pc + 8;
7434 }
7435
7436 func (stream, "\t; ");
7437 info->print_address_func (offset, info);
05413229 7438 offset = 0;
62b3e311
PB		 7439 }
7440 else
7441 {
7442 func (stream, "[%s",
7443 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 7444
7445 if (PRE_BIT_SET)
62b3e311
PB		 7446 {
7447 if ((given & 0x02000000) == 0)
7448 {
26d97720 7449 /* Elide offset of positive zero when non-writeback. */
05413229 7450 offset = given & 0xfff;
26d97720 7451 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 7452 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 7453 }
7454 else
7455 {
26d97720 7456 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 7457 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 7458 }
7459
7460 func (stream, "]%s",
c1e26897 7461 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 7462 }
7463 else
7464 {
7465 if ((given & 0x02000000) == 0)
7466 {
26d97720 7467 /* Always show offset. */
05413229 7468 offset = given & 0xfff;
26d97720 7469 func (stream, "], #%s%d",
d908c8af 7470 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 7471 }
7472 else
7473 {
7474 func (stream, "], %s",
c1e26897 7475 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 7476 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 7477 }
7478 }
84919466
MR		 7479 if (NEGATIVE_BIT_SET)
7480 offset = -offset;
62b3e311 7481 }
05413229
NC		 7482
7483 return (signed long) offset;
62b3e311
PB		 7484}
7485
16980d0b
JB		 7486/* Print one neon instruction on INFO->STREAM.
7487 Return TRUE if the instuction matched, FALSE if this is not a
7488 recognised neon instruction. */
7489
7490static bfd_boolean
7491print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
7492{
7493 const struct opcode32 *insn;
7494 void *stream = info->stream;
7495 fprintf_ftype func = info->fprintf_func;
7496
7497 if (thumb)
7498 {
7499 if ((given & 0xef000000) == 0xef000000)
7500 {
0313a2b8 7501 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 7502 unsigned long bit28 = given & (1 << 28);
7503
7504 given &= 0x00ffffff;
7505 if (bit28)
7506 given |= 0xf3000000;
7507 else
7508 given |= 0xf2000000;
7509 }
7510 else if ((given & 0xff000000) == 0xf9000000)
7511 given ^= 0xf9000000 ^ 0xf4000000;
9743db03
AV		 7512 /* vdup is also a valid neon instruction. */
7513 else if ((given & 0xff910f5f) != 0xee800b10)
16980d0b
JB		 7514 return FALSE;
7515 }
43e65147 7516
16980d0b
JB		 7517 for (insn = neon_opcodes; insn->assembler; insn++)
7518 {
7519 if ((given & insn->mask) == insn->value)
7520 {
05413229 7521 signed long value_in_comment = 0;
e2efe87d 7522 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 7523 const char *c;
7524
7525 for (c = insn->assembler; *c; c++)
7526 {
7527 if (*c == '%')
7528 {
7529 switch (*++c)
7530 {
7531 case '%':
7532 func (stream, "%%");
7533 break;
7534
e2efe87d
MGD		 7535 case 'u':
7536 if (thumb && ifthen_state)
7537 is_unpredictable = TRUE;
7538
7539 /* Fall through. */
c22aaad1
PB		 7540 case 'c':
7541 if (thumb && ifthen_state)
7542 func (stream, "%s", arm_conditional[IFTHEN_COND]);
7543 break;
7544
16980d0b
JB		 7545 case 'A':
7546 {
43e65147 7547 static const unsigned char enc[16] =
16980d0b
JB		 7548 {
7549 0x4, 0x14, /* st4 0,1 */
7550 0x4, /* st1 2 */
7551 0x4, /* st2 3 */
7552 0x3, /* st3 4 */
7553 0x13, /* st3 5 */
7554 0x3, /* st1 6 */
7555 0x1, /* st1 7 */
7556 0x2, /* st2 8 */
7557 0x12, /* st2 9 */
7558 0x2, /* st1 10 */
7559 0, 0, 0, 0, 0
7560 };
7561 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
7562 int rn = ((given >> 16) & 0xf);
7563 int rm = ((given >> 0) & 0xf);
7564 int align = ((given >> 4) & 0x3);
7565 int type = ((given >> 8) & 0xf);
7566 int n = enc[type] & 0xf;
7567 int stride = (enc[type] >> 4) + 1;
7568 int ix;
43e65147 7569
16980d0b
JB		 7570 func (stream, "{");
7571 if (stride > 1)
7572 for (ix = 0; ix != n; ix++)
7573 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
7574 else if (n == 1)
7575 func (stream, "d%d", rd);
7576 else
7577 func (stream, "d%d-d%d", rd, rd + n - 1);
7578 func (stream, "}, [%s", arm_regnames[rn]);
7579 if (align)
8e560766 7580 func (stream, " :%d", 32 << align);
16980d0b
JB		 7581 func (stream, "]");
7582 if (rm == 0xd)
7583 func (stream, "!");
7584 else if (rm != 0xf)
7585 func (stream, ", %s", arm_regnames[rm]);
7586 }
7587 break;
43e65147 7588
16980d0b
JB		 7589 case 'B':
7590 {
7591 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
7592 int rn = ((given >> 16) & 0xf);
7593 int rm = ((given >> 0) & 0xf);
7594 int idx_align = ((given >> 4) & 0xf);
7595 int align = 0;
7596 int size = ((given >> 10) & 0x3);
7597 int idx = idx_align >> (size + 1);
7598 int length = ((given >> 8) & 3) + 1;
7599 int stride = 1;
7600 int i;
7601
7602 if (length > 1 && size > 0)
7603 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 7604
16980d0b
JB		 7605 switch (length)
7606 {
7607 case 1:
7608 {
7609 int amask = (1 << size) - 1;
7610 if ((idx_align & (1 << size)) != 0)
7611 return FALSE;
7612 if (size > 0)
7613 {
7614 if ((idx_align & amask) == amask)
7615 align = 8 << size;
7616 else if ((idx_align & amask) != 0)
7617 return FALSE;
7618 }
7619 }
7620 break;
43e65147 7621
16980d0b
JB		 7622 case 2:
7623 if (size == 2 && (idx_align & 2) != 0)
7624 return FALSE;
7625 align = (idx_align & 1) ? 16 << size : 0;
7626 break;
43e65147 7627
16980d0b
JB		 7628 case 3:
7629 if ((size == 2 && (idx_align & 3) != 0)
7630 || (idx_align & 1) != 0)
7631 return FALSE;
7632 break;
43e65147 7633
16980d0b
JB		 7634 case 4:
7635 if (size == 2)
7636 {
7637 if ((idx_align & 3) == 3)
7638 return FALSE;
7639 align = (idx_align & 3) * 64;
7640 }
7641 else
7642 align = (idx_align & 1) ? 32 << size : 0;
7643 break;
43e65147 7644
16980d0b
JB		 7645 default:
7646 abort ();
7647 }
43e65147 7648
16980d0b
JB		 7649 func (stream, "{");
7650 for (i = 0; i < length; i++)
7651 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
7652 rd + i * stride, idx);
7653 func (stream, "}, [%s", arm_regnames[rn]);
7654 if (align)
8e560766 7655 func (stream, " :%d", align);
16980d0b
JB		 7656 func (stream, "]");
7657 if (rm == 0xd)
7658 func (stream, "!");
7659 else if (rm != 0xf)
7660 func (stream, ", %s", arm_regnames[rm]);
7661 }
7662 break;
43e65147 7663
16980d0b
JB		 7664 case 'C':
7665 {
7666 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
7667 int rn = ((given >> 16) & 0xf);
7668 int rm = ((given >> 0) & 0xf);
7669 int align = ((given >> 4) & 0x1);
7670 int size = ((given >> 6) & 0x3);
7671 int type = ((given >> 8) & 0x3);
7672 int n = type + 1;
7673 int stride = ((given >> 5) & 0x1);
7674 int ix;
43e65147 7675
16980d0b
JB		 7676 if (stride && (n == 1))
7677 n++;
7678 else
7679 stride++;
43e65147 7680
16980d0b
JB		 7681 func (stream, "{");
7682 if (stride > 1)
7683 for (ix = 0; ix != n; ix++)
7684 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
7685 else if (n == 1)
7686 func (stream, "d%d[]", rd);
7687 else
7688 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
7689 func (stream, "}, [%s", arm_regnames[rn]);
7690 if (align)
7691 {
91d6fa6a 7692 align = (8 * (type + 1)) << size;
16980d0b
JB		 7693 if (type == 3)
7694 align = (size > 1) ? align >> 1 : align;
7695 if (type == 2 || (type == 0 && !size))
8e560766 7696 func (stream, " :<bad align %d>", align);
16980d0b 7697 else
8e560766 7698 func (stream, " :%d", align);
16980d0b
JB		 7699 }
7700 func (stream, "]");
7701 if (rm == 0xd)
7702 func (stream, "!");
7703 else if (rm != 0xf)
7704 func (stream, ", %s", arm_regnames[rm]);
7705 }
7706 break;
43e65147 7707
16980d0b
JB		 7708 case 'D':
7709 {
7710 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
7711 int size = (given >> 20) & 3;
7712 int reg = raw_reg & ((4 << size) - 1);
7713 int ix = raw_reg >> size >> 2;
43e65147 7714
16980d0b
JB		 7715 func (stream, "d%d[%d]", reg, ix);
7716 }
7717 break;
43e65147 7718
16980d0b 7719 case 'E':
fe56b6ce 7720 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 7721 {
7722 int bits = 0;
7723 int cmode = (given >> 8) & 0xf;
7724 int op = (given >> 5) & 0x1;
7725 unsigned long value = 0, hival = 0;
7726 unsigned shift;
7727 int size = 0;
0dbde4cf 7728 int isfloat = 0;
43e65147 7729
16980d0b
JB		 7730 bits |= ((given >> 24) & 1) << 7;
7731 bits |= ((given >> 16) & 7) << 4;
7732 bits |= ((given >> 0) & 15) << 0;
43e65147 7733
16980d0b
JB		 7734 if (cmode < 8)
7735 {
7736 shift = (cmode >> 1) & 3;
fe56b6ce 7737 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 7738 size = 32;
7739 }
7740 else if (cmode < 12)
7741 {
7742 shift = (cmode >> 1) & 1;
fe56b6ce 7743 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 7744 size = 16;
7745 }
7746 else if (cmode < 14)
7747 {
7748 shift = (cmode & 1) + 1;
fe56b6ce 7749 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 7750 value |= (1ul << (8 * shift)) - 1;
7751 size = 32;
7752 }
7753 else if (cmode == 14)
7754 {
7755 if (op)
7756 {
fe56b6ce 7757 /* Bit replication into bytes. */
16980d0b
JB		 7758 int ix;
7759 unsigned long mask;
43e65147 7760
16980d0b
JB		 7761 value = 0;
7762 hival = 0;
7763 for (ix = 7; ix >= 0; ix--)
7764 {
7765 mask = ((bits >> ix) & 1) ? 0xff : 0;
7766 if (ix <= 3)
7767 value = (value << 8) | mask;
7768 else
7769 hival = (hival << 8) | mask;
7770 }
7771 size = 64;
7772 }
7773 else
7774 {
fe56b6ce
NC		 7775 /* Byte replication. */
7776 value = (unsigned long) bits;
16980d0b
JB		 7777 size = 8;
7778 }
7779 }
7780 else if (!op)
7781 {
fe56b6ce 7782 /* Floating point encoding. */
16980d0b 7783 int tmp;
43e65147 7784
fe56b6ce
NC		 7785 value = (unsigned long) (bits & 0x7f) << 19;
7786 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 7787 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 7788 value |= (unsigned long) tmp << 24;
16980d0b 7789 size = 32;
0dbde4cf 7790 isfloat = 1;
16980d0b
JB		 7791 }
7792 else
7793 {
7794 func (stream, "<illegal constant %.8x:%x:%x>",
7795 bits, cmode, op);
7796 size = 32;
7797 break;
7798 }
7799 switch (size)
7800 {
7801 case 8:
7802 func (stream, "#%ld\t; 0x%.2lx", value, value);
7803 break;
43e65147 7804
16980d0b
JB		 7805 case 16:
7806 func (stream, "#%ld\t; 0x%.4lx", value, value);
7807 break;
7808
7809 case 32:
0dbde4cf
JB		 7810 if (isfloat)
7811 {
7812 unsigned char valbytes[4];
7813 double fvalue;
43e65147 7814
0dbde4cf
JB		 7815 /* Do this a byte at a time so we don't have to
7816 worry about the host's endianness. */
7817 valbytes[0] = value & 0xff;
7818 valbytes[1] = (value >> 8) & 0xff;
7819 valbytes[2] = (value >> 16) & 0xff;
7820 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 7821
7822 floatformat_to_double
c1e26897
NC		 7823 (& floatformat_ieee_single_little, valbytes,
7824 & fvalue);
43e65147 7825
0dbde4cf
JB		 7826 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
7827 value);
7828 }
7829 else
4e9d3b81 7830 func (stream, "#%ld\t; 0x%.8lx",
43e65147 7831 (long) (((value & 0x80000000L) != 0)
9d82ec38 7832 ? value | ~0xffffffffL : value),
c1e26897 7833 value);
16980d0b
JB		 7834 break;
7835
7836 case 64:
7837 func (stream, "#0x%.8lx%.8lx", hival, value);
7838 break;
43e65147 7839
16980d0b
JB		 7840 default:
7841 abort ();
7842 }
7843 }
7844 break;
43e65147 7845
16980d0b
JB		 7846 case 'F':
7847 {
7848 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
7849 int num = (given >> 8) & 0x3;
43e65147 7850
16980d0b
JB		 7851 if (!num)
7852 func (stream, "{d%d}", regno);
7853 else if (num + regno >= 32)
7854 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
7855 else
7856 func (stream, "{d%d-d%d}", regno, regno + num);
7857 }
7858 break;
7e8e6784 7859
16980d0b
JB		 7860
7861 case '0': case '1': case '2': case '3': case '4':
7862 case '5': case '6': case '7': case '8': case '9':
7863 {
7864 int width;
7865 unsigned long value;
7866
7867 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 7868
16980d0b
JB		 7869 switch (*c)
7870 {
7871 case 'r':
7872 func (stream, "%s", arm_regnames[value]);
7873 break;
7874 case 'd':
7875 func (stream, "%ld", value);
05413229 7876 value_in_comment = value;
16980d0b
JB		 7877 break;
7878 case 'e':
7879 func (stream, "%ld", (1ul << width) - value);
7880 break;
43e65147 7881
16980d0b
JB		 7882 case 'S':
7883 case 'T':
7884 case 'U':
05413229 7885 /* Various width encodings. */
16980d0b
JB		 7886 {
7887 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
7888 int limit;
7889 unsigned low, high;
7890
7891 c++;
7892 if (*c >= '0' && *c <= '9')
7893 limit = *c - '0';
7894 else if (*c >= 'a' && *c <= 'f')
7895 limit = *c - 'a' + 10;
7896 else
7897 abort ();
7898 low = limit >> 2;
7899 high = limit & 3;
7900
7901 if (value < low || value > high)
7902 func (stream, "<illegal width %d>", base << value);
7903 else
7904 func (stream, "%d", base << value);
7905 }
7906 break;
7907 case 'R':
7908 if (given & (1 << 6))
7909 goto Q;
7910 /* FALLTHROUGH */
7911 case 'D':
7912 func (stream, "d%ld", value);
7913 break;
7914 case 'Q':
7915 Q:
7916 if (value & 1)
7917 func (stream, "<illegal reg q%ld.5>", value >> 1);
7918 else
7919 func (stream, "q%ld", value >> 1);
7920 break;
43e65147 7921
16980d0b
JB		 7922 case '`':
7923 c++;
7924 if (value == 0)
7925 func (stream, "%c", *c);
7926 break;
7927 case '\'':
7928 c++;
7929 if (value == ((1ul << width) - 1))
7930 func (stream, "%c", *c);
7931 break;
7932 case '?':
fe56b6ce 7933 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 7934 c += 1 << width;
7935 break;
7936 default:
7937 abort ();
7938 }
16980d0b 7939 }
dffaa15c
AM		 7940 break;
7941
7942 default:
7943 abort ();
16980d0b
JB		 7944 }
7945 }
7946 else
7947 func (stream, "%c", *c);
7948 }
05413229
NC		 7949
7950 if (value_in_comment > 32 || value_in_comment < -16)
7951 func (stream, "\t; 0x%lx", value_in_comment);
7952
e2efe87d
MGD		 7953 if (is_unpredictable)
7954 func (stream, UNPREDICTABLE_INSTRUCTION);
7955
16980d0b
JB		 7956 return TRUE;
7957 }
7958 }
7959 return FALSE;
7960}
7961
73cd51e5
AV		 7962/* Print one mve instruction on INFO->STREAM.
7963 Return TRUE if the instuction matched, FALSE if this is not a
7964 recognised mve instruction. */
7965
7966static bfd_boolean
7967print_insn_mve (struct disassemble_info *info, long given)
7968{
7969 const struct mopcode32 *insn;
7970 void *stream = info->stream;
7971 fprintf_ftype func = info->fprintf_func;
7972
7973 for (insn = mve_opcodes; insn->assembler; insn++)
7974 {
7975 if (((given & insn->mask) == insn->value)
7976 && !is_mve_encoding_conflict (given, insn->mve_op))
7977 {
7978 signed long value_in_comment = 0;
7979 bfd_boolean is_unpredictable = FALSE;
7980 bfd_boolean is_undefined = FALSE;
7981 const char *c;
7982 enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
7983 enum mve_undefined undefined_cond = UNDEF_NONE;
7984
7985 /* Most vector mve instruction are illegal in a it block.
7986 There are a few exceptions; check for them. */
7987 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
7988 {
7989 is_unpredictable = TRUE;
7990 unpredictable_cond = UNPRED_IT_BLOCK;
7991 }
7992 else if (is_mve_unpredictable (given, insn->mve_op,
7993 &unpredictable_cond))
7994 is_unpredictable = TRUE;
7995
7996 if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
7997 is_undefined = TRUE;
7998
7999 for (c = insn->assembler; *c; c++)
8000 {
8001 if (*c == '%')
8002 {
8003 switch (*++c)
8004 {
8005 case '%':
8006 func (stream, "%%");
8007 break;
8008
ef1576a1
AV		 8009 case 'a':
8010 /* Don't print anything for '+' as it is implied. */
8011 if (arm_decode_field (given, 23, 23) == 0)
8012 func (stream, "-");
8013 break;
8014
143275ea
AV		 8015 case 'c':
8016 if (ifthen_state)
8017 func (stream, "%s", arm_conditional[IFTHEN_COND]);
8018 break;
8019
aef6d006
AV		 8020 case 'd':
8021 print_mve_vld_str_addr (info, given, insn->mve_op);
8022 break;
8023
143275ea
AV		 8024 case 'i':
8025 {
8026 long mve_mask = mve_extract_pred_mask (given);
8027 func (stream, "%s", mve_predicatenames[mve_mask]);
8028 }
8029 break;
8030
8031 case 'n':
8032 print_vec_condition (info, given, insn->mve_op);
8033 break;
8034
ef1576a1
AV		 8035 case 'o':
8036 if (arm_decode_field (given, 0, 0) == 1)
8037 {
8038 unsigned long size
8039 = arm_decode_field (given, 4, 4)
8040 | (arm_decode_field (given, 6, 6) << 1);
8041
8042 func (stream, ", uxtw #%lu", size);
8043 }
8044 break;
8045
bf0b396d
AV		 8046 case 'm':
8047 print_mve_rounding_mode (info, given, insn->mve_op);
8048 break;
8049
8050 case 's':
8051 print_mve_vcvt_size (info, given, insn->mve_op);
8052 break;
8053
aef6d006
AV		 8054 case 'u':
8055 {
c507f10b
AV		 8056 unsigned long op1 = arm_decode_field (given, 21, 22);
8057
8058 if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
8059 {
8060 /* Check for signed. */
8061 if (arm_decode_field (given, 23, 23) == 0)
8062 {
8063 /* We don't print 's' for S32. */
8064 if ((arm_decode_field (given, 5, 6) == 0)
8065 && ((op1 == 0) || (op1 == 1)))
8066 ;
8067 else
8068 func (stream, "s");
8069 }
8070 else
8071 func (stream, "u");
8072 }
aef6d006 8073 else
c507f10b
AV		 8074 {
8075 if (arm_decode_field (given, 28, 28) == 0)
8076 func (stream, "s");
8077 else
8078 func (stream, "u");
8079 }
aef6d006 8080 }
ef1576a1 8081 break;
aef6d006 8082
143275ea
AV		 8083 case 'v':
8084 print_instruction_predicate (info);
8085 break;
8086
04d54ace
AV		 8087 case 'w':
8088 if (arm_decode_field (given, 21, 21) == 1)
8089 func (stream, "!");
8090 break;
8091
8092 case 'B':
8093 print_mve_register_blocks (info, given, insn->mve_op);
8094 break;
8095
c507f10b
AV		 8096 case 'E':
8097 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
8098
8099 print_simd_imm8 (info, given, 28, insn);
8100 break;
8101
8102 case 'N':
8103 print_mve_vmov_index (info, given);
8104 break;
8105
14925797
AV		 8106 case 'T':
8107 if (arm_decode_field (given, 12, 12) == 0)
8108 func (stream, "b");
8109 else
8110 func (stream, "t");
8111 break;
8112
d3b63143
AV		 8113 case 'X':
8114 if (arm_decode_field (given, 12, 12) == 1)
8115 func (stream, "x");
8116 break;
8117
143275ea
AV		 8118 case '0': case '1': case '2': case '3': case '4':
8119 case '5': case '6': case '7': case '8': case '9':
8120 {
8121 int width;
8122 unsigned long value;
8123
8124 c = arm_decode_bitfield (c, given, &value, &width);
8125
8126 switch (*c)
8127 {
8128 case 'Z':
8129 if (value == 13)
8130 is_unpredictable = TRUE;
8131 else if (value == 15)
8132 func (stream, "zr");
8133 else
8134 func (stream, "%s", arm_regnames[value]);
8135 break;
8136 case 's':
8137 print_mve_size (info,
8138 value,
8139 insn->mve_op);
8140 break;
d3b63143
AV		 8141 case 'A':
8142 if (value == 1)
8143 func (stream, "a");
8144 break;
1c8f2df8
AV		 8145 case 'h':
8146 {
8147 unsigned int odd_reg = (value << 1) | 1;
8148 func (stream, "%s", arm_regnames[odd_reg]);
8149 }
8150 break;
ef1576a1
AV		 8151 case 'i':
8152 {
8153 unsigned long imm
8154 = arm_decode_field (given, 0, 6);
8155 unsigned long mod_imm = imm;
8156
8157 switch (insn->mve_op)
8158 {
8159 case MVE_VLDRW_GATHER_T5:
8160 case MVE_VSTRW_SCATTER_T5:
8161 mod_imm = mod_imm << 2;
8162 break;
8163 case MVE_VSTRD_SCATTER_T6:
8164 case MVE_VLDRD_GATHER_T6:
8165 mod_imm = mod_imm << 3;
8166 break;
8167
8168 default:
8169 break;
8170 }
8171
8172 func (stream, "%lu", mod_imm);
8173 }
8174 break;
bf0b396d
AV		 8175 case 'k':
8176 func (stream, "%lu", 64 - value);
8177 break;
1c8f2df8
AV		 8178 case 'l':
8179 {
8180 unsigned int even_reg = value << 1;
8181 func (stream, "%s", arm_regnames[even_reg]);
8182 }
8183 break;
8184 case 'u':
8185 switch (value)
8186 {
8187 case 0:
8188 func (stream, "1");
8189 break;
8190 case 1:
8191 func (stream, "2");
8192 break;
8193 case 2:
8194 func (stream, "4");
8195 break;
8196 case 3:
8197 func (stream, "8");
8198 break;
8199 default:
8200 break;
8201 }
8202 break;
897b9bbc
AV		 8203 case 'o':
8204 print_mve_rotate (info, value, width);
8205 break;
9743db03
AV		 8206 case 'r':
8207 func (stream, "%s", arm_regnames[value]);
8208 break;
04d54ace
AV		 8209 case 'd':
8210 func (stream, "%ld", value);
8211 value_in_comment = value;
8212 break;
c507f10b
AV		 8213 case 'F':
8214 func (stream, "s%ld", value);
8215 break;
143275ea
AV		 8216 case 'Q':
8217 if (value & 0x8)
8218 func (stream, "<illegal reg q%ld.5>", value);
8219 else
8220 func (stream, "q%ld", value);
8221 break;
c507f10b
AV		 8222 case 'x':
8223 func (stream, "0x%08lx", value);
8224 break;
143275ea
AV		 8225 default:
8226 abort ();
8227 }
8228 break;
8229 default:
8230 abort ();
8231 }
73cd51e5
AV		 8232 }
8233 }
8234 else
8235 func (stream, "%c", *c);
8236 }
8237
8238 if (value_in_comment > 32 || value_in_comment < -16)
8239 func (stream, "\t; 0x%lx", value_in_comment);
8240
8241 if (is_unpredictable)
8242 print_mve_unpredictable (info, unpredictable_cond);
8243
8244 if (is_undefined)
8245 print_mve_undefined (info, undefined_cond);
8246
143275ea
AV		 8247 if ((vpt_block_state.in_vpt_block == FALSE)
8248 && !ifthen_state
8249 && (is_vpt_instruction (given) == TRUE))
8250 mark_inside_vpt_block (given);
8251 else if (vpt_block_state.in_vpt_block == TRUE)
8252 update_vpt_block_state ();
8253
73cd51e5
AV		 8254 return TRUE;
8255 }
8256 }
8257 return FALSE;
8258}
8259
8260
90ec0d68
MGD		 8261/* Return the name of a v7A special register. */
8262
43e65147 8263static const char *
90ec0d68
MGD		 8264banked_regname (unsigned reg)
8265{
8266 switch (reg)
8267 {
8268 case 15: return "CPSR";
43e65147 8269 case 32: return "R8_usr";
90ec0d68
MGD		 8270 case 33: return "R9_usr";
8271 case 34: return "R10_usr";
8272 case 35: return "R11_usr";
8273 case 36: return "R12_usr";
8274 case 37: return "SP_usr";
8275 case 38: return "LR_usr";
43e65147 8276 case 40: return "R8_fiq";
90ec0d68
MGD		 8277 case 41: return "R9_fiq";
8278 case 42: return "R10_fiq";
8279 case 43: return "R11_fiq";
8280 case 44: return "R12_fiq";
8281 case 45: return "SP_fiq";
8282 case 46: return "LR_fiq";
8283 case 48: return "LR_irq";
8284 case 49: return "SP_irq";
8285 case 50: return "LR_svc";
8286 case 51: return "SP_svc";
8287 case 52: return "LR_abt";
8288 case 53: return "SP_abt";
8289 case 54: return "LR_und";
8290 case 55: return "SP_und";
8291 case 60: return "LR_mon";
8292 case 61: return "SP_mon";
8293 case 62: return "ELR_hyp";
8294 case 63: return "SP_hyp";
8295 case 79: return "SPSR";
8296 case 110: return "SPSR_fiq";
8297 case 112: return "SPSR_irq";
8298 case 114: return "SPSR_svc";
8299 case 116: return "SPSR_abt";
8300 case 118: return "SPSR_und";
8301 case 124: return "SPSR_mon";
8302 case 126: return "SPSR_hyp";
8303 default: return NULL;
8304 }
8305}
8306
e797f7e0
MGD		 8307/* Return the name of the DMB/DSB option. */
8308static const char *
8309data_barrier_option (unsigned option)
8310{
8311 switch (option & 0xf)
8312 {
8313 case 0xf: return "sy";
8314 case 0xe: return "st";
8315 case 0xd: return "ld";
8316 case 0xb: return "ish";
8317 case 0xa: return "ishst";
8318 case 0x9: return "ishld";
8319 case 0x7: return "un";
8320 case 0x6: return "unst";
8321 case 0x5: return "nshld";
8322 case 0x3: return "osh";
8323 case 0x2: return "oshst";
8324 case 0x1: return "oshld";
8325 default: return NULL;
8326 }
8327}
8328
4a5329c6
ZW		 8329/* Print one ARM instruction from PC on INFO->STREAM. */
8330
8331static void
8332print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 8333{
6b5d3a4d 8334 const struct opcode32 *insn;
6a51a8a8 8335 void *stream = info->stream;
6b5d3a4d 8336 fprintf_ftype func = info->fprintf_func;
b0e28b39 8337 struct arm_private_data *private_data = info->private_data;
252b5132 8338
16980d0b
JB		 8339 if (print_insn_coprocessor (pc, info, given, FALSE))
8340 return;
8341
8342 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 8343 return;
8344
252b5132
RH		 8345 for (insn = arm_opcodes; insn->assembler; insn++)
8346 {
0313a2b8
NC		 8347 if ((given & insn->mask) != insn->value)
8348 continue;
823d2571
TG		 8349
8350 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 8351 continue;
8352
8353 /* Special case: an instruction with all bits set in the condition field
8354 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
8355 or by the catchall at the end of the table. */
8356 if ((given & 0xF0000000) != 0xF0000000
8357 || (insn->mask & 0xF0000000) == 0xF0000000
8358 || (insn->mask == 0 && insn->value == 0))
252b5132 8359 {
ff4a8d2b
NC		 8360 unsigned long u_reg = 16;
8361 unsigned long U_reg = 16;
ab8e2090 8362 bfd_boolean is_unpredictable = FALSE;
05413229 8363 signed long value_in_comment = 0;
6b5d3a4d 8364 const char *c;
b34976b6 8365
252b5132
RH		 8366 for (c = insn->assembler; *c; c++)
8367 {
8368 if (*c == '%')
8369 {
c1e26897
NC		 8370 bfd_boolean allow_unpredictable = FALSE;
8371
252b5132
RH		 8372 switch (*++c)
8373 {
8374 case '%':
8375 func (stream, "%%");
8376 break;
8377
8378 case 'a':
05413229 8379 value_in_comment = print_arm_address (pc, info, given);
62b3e311 8380 break;
252b5132 8381
62b3e311
PB		 8382 case 'P':
8383 /* Set P address bit and use normal address
8384 printing routine. */
c1e26897 8385 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 8386 break;
8387
c1e26897
NC		 8388 case 'S':
8389 allow_unpredictable = TRUE;
1a0670f3 8390 /* Fall through. */
252b5132
RH		 8391 case 's':
8392 if ((given & 0x004f0000) == 0x004f0000)
8393 {
58efb6c0 8394 /* PC relative with immediate offset. */
f8b960bc 8395 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 8396
aefd8a40
NC		 8397 if (PRE_BIT_SET)
8398 {
26d97720
NS		 8399 /* Elide positive zero offset. */
8400 if (offset || NEGATIVE_BIT_SET)
8401 func (stream, "[pc, #%s%d]\t; ",
d908c8af 8402 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 8403 else
26d97720
NS		 8404 func (stream, "[pc]\t; ");
8405 if (NEGATIVE_BIT_SET)
8406 offset = -offset;
aefd8a40
NC		 8407 info->print_address_func (offset + pc + 8, info);
8408 }
8409 else
8410 {
26d97720
NS		 8411 /* Always show the offset. */
8412 func (stream, "[pc], #%s%d",
d908c8af 8413 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 8414 if (! allow_unpredictable)
8415 is_unpredictable = TRUE;
aefd8a40 8416 }
252b5132
RH		 8417 }
8418 else
8419 {
fe56b6ce
NC		 8420 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
8421
b34976b6 8422 func (stream, "[%s",
252b5132 8423 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 8424
c1e26897 8425 if (PRE_BIT_SET)
252b5132 8426 {
c1e26897 8427 if (IMMEDIATE_BIT_SET)
252b5132 8428 {
26d97720
NS		 8429 /* Elide offset for non-writeback
8430 positive zero. */
8431 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
8432 || offset)
8433 func (stream, ", #%s%d",
8434 NEGATIVE_BIT_SET ? "-" : "", offset);
8435
8436 if (NEGATIVE_BIT_SET)
8437 offset = -offset;
945ee430 8438
fe56b6ce 8439 value_in_comment = offset;
252b5132 8440 }
945ee430 8441 else
ff4a8d2b
NC		 8442 {
8443 /* Register Offset or Register Pre-Indexed. */
8444 func (stream, ", %s%s",
8445 NEGATIVE_BIT_SET ? "-" : "",
8446 arm_regnames[given & 0xf]);
8447
8448 /* Writing back to the register that is the source/
8449 destination of the load/store is unpredictable. */
8450 if (! allow_unpredictable
8451 && WRITEBACK_BIT_SET
8452 && ((given & 0xf) == ((given >> 12) & 0xf)))
8453 is_unpredictable = TRUE;
8454 }
252b5132 8455
b34976b6 8456 func (stream, "]%s",
c1e26897 8457 WRITEBACK_BIT_SET ? "!" : "");
252b5132 8458 }
945ee430 8459 else
252b5132 8460 {
c1e26897 8461 if (IMMEDIATE_BIT_SET)
252b5132 8462 {
945ee430 8463 /* Immediate Post-indexed. */
aefd8a40 8464 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 8465 func (stream, "], #%s%d",
8466 NEGATIVE_BIT_SET ? "-" : "", offset);
8467 if (NEGATIVE_BIT_SET)
8468 offset = -offset;
fe56b6ce 8469 value_in_comment = offset;
252b5132 8470 }
945ee430 8471 else
ff4a8d2b
NC		 8472 {
8473 /* Register Post-indexed. */
8474 func (stream, "], %s%s",
8475 NEGATIVE_BIT_SET ? "-" : "",
8476 arm_regnames[given & 0xf]);
8477
8478 /* Writing back to the register that is the source/
8479 destination of the load/store is unpredictable. */
8480 if (! allow_unpredictable
8481 && (given & 0xf) == ((given >> 12) & 0xf))
8482 is_unpredictable = TRUE;
8483 }
c1e26897 8484
07a28fab
NC		 8485 if (! allow_unpredictable)
8486 {
8487 /* Writeback is automatically implied by post- addressing.
8488 Setting the W bit is unnecessary and ARM specify it as
8489 being unpredictable. */
8490 if (WRITEBACK_BIT_SET
8491 /* Specifying the PC register as the post-indexed
8492 registers is also unpredictable. */
ab8e2090
NC		 8493 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
8494 is_unpredictable = TRUE;
07a28fab 8495 }
252b5132
RH		 8496 }
8497 }
8498 break;
b34976b6 8499
252b5132 8500 case 'b':
6b5d3a4d 8501 {
f8b960bc 8502 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
05413229 8503 info->print_address_func (disp * 4 + pc + 8, info);
6b5d3a4d 8504 }
252b5132
RH		 8505 break;
8506
8507 case 'c':
c22aaad1
PB		 8508 if (((given >> 28) & 0xf) != 0xe)
8509 func (stream, "%s",
8510 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 8511 break;
8512
8513 case 'm':
8514 {
8515 int started = 0;
8516 int reg;
8517
8518 func (stream, "{");
8519 for (reg = 0; reg < 16; reg++)
8520 if ((given & (1 << reg)) != 0)
8521 {
8522 if (started)
8523 func (stream, ", ");
8524 started = 1;
8525 func (stream, "%s", arm_regnames[reg]);
8526 }
8527 func (stream, "}");
ab8e2090
NC		 8528 if (! started)
8529 is_unpredictable = TRUE;
252b5132
RH		 8530 }
8531 break;
8532
37b37b2d 8533 case 'q':
78c66db8 8534 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 8535 break;
8536
252b5132
RH		 8537 case 'o':
8538 if ((given & 0x02000000) != 0)
8539 {
a415b1cd
JB		 8540 unsigned int rotate = (given & 0xf00) >> 7;
8541 unsigned int immed = (given & 0xff);
8542 unsigned int a, i;
8543
8544 a = (((immed << (32 - rotate))
8545 | (immed >> rotate)) & 0xffffffff);
8546 /* If there is another encoding with smaller rotate,
8547 the rotate should be specified directly. */
8548 for (i = 0; i < 32; i += 2)
8549 if ((a << i | a >> (32 - i)) <= 0xff)
8550 break;
8551
8552 if (i != rotate)
8553 func (stream, "#%d, %d", immed, rotate);
8554 else
8555 func (stream, "#%d", a);
8556 value_in_comment = a;
252b5132
RH		 8557 }
8558 else
78c66db8 8559 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 8560 break;
8561
8562 case 'p':
8563 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 8564 {
823d2571
TG		 8565 arm_feature_set arm_ext_v6 =
8566 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
8567
aefd8a40
NC		 8568 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
8569 mechanism for setting PSR flag bits. They are
8570 obsolete in V6 onwards. */
823d2571
TG		 8571 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
8572 arm_ext_v6))
aefd8a40 8573 func (stream, "p");
4ab90a7a
AV		 8574 else
8575 is_unpredictable = TRUE;
aefd8a40 8576 }
252b5132
RH		 8577 break;
8578
8579 case 't':
8580 if ((given & 0x01200000) == 0x00200000)
8581 func (stream, "t");
8582 break;
8583
252b5132 8584 case 'A':
05413229
NC		 8585 {
8586 int offset = given & 0xff;
f02232aa 8587
05413229 8588 value_in_comment = offset * 4;
c1e26897 8589 if (NEGATIVE_BIT_SET)
05413229 8590 value_in_comment = - value_in_comment;
f02232aa 8591
05413229 8592 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 8593
c1e26897 8594 if (PRE_BIT_SET)
05413229
NC		 8595 {
8596 if (offset)
fe56b6ce 8597 func (stream, ", #%d]%s",
d908c8af 8598 (int) value_in_comment,
c1e26897 8599 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 8600 else
8601 func (stream, "]");
8602 }
8603 else
8604 {
8605 func (stream, "]");
f02232aa 8606
c1e26897 8607 if (WRITEBACK_BIT_SET)
05413229
NC		 8608 {
8609 if (offset)
d908c8af 8610 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 8611 }
8612 else
fe56b6ce 8613 {
d908c8af 8614 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 8615 value_in_comment = offset;
8616 }
05413229
NC		 8617 }
8618 }
252b5132
RH		 8619 break;
8620
077b8428
NC		 8621 case 'B':
8622 /* Print ARM V5 BLX(1) address: pc+25 bits. */
8623 {
8624 bfd_vma address;
8625 bfd_vma offset = 0;
b34976b6 8626
c1e26897 8627 if (! NEGATIVE_BIT_SET)
077b8428
NC		 8628 /* Is signed, hi bits should be ones. */
8629 offset = (-1) ^ 0x00ffffff;
8630
8631 /* Offset is (SignExtend(offset field)<<2). */
8632 offset += given & 0x00ffffff;
8633 offset <<= 2;
8634 address = offset + pc + 8;
b34976b6 8635
8f06b2d8
PB		 8636 if (given & 0x01000000)
8637 /* H bit allows addressing to 2-byte boundaries. */
8638 address += 2;
b1ee46c5 8639
8f06b2d8 8640 info->print_address_func (address, info);
b1ee46c5 8641 }
b1ee46c5
AH		 8642 break;
8643
252b5132 8644 case 'C':
90ec0d68
MGD		 8645 if ((given & 0x02000200) == 0x200)
8646 {
8647 const char * name;
8648 unsigned sysm = (given & 0x004f0000) >> 16;
8649
8650 sysm |= (given & 0x300) >> 4;
8651 name = banked_regname (sysm);
8652
8653 if (name != NULL)
8654 func (stream, "%s", name);
8655 else
d908c8af 8656 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 8657 }
8658 else
8659 {
43e65147 8660 func (stream, "%cPSR_",
90ec0d68
MGD		 8661 (given & 0x00400000) ? 'S' : 'C');
8662 if (given & 0x80000)
8663 func (stream, "f");
8664 if (given & 0x40000)
8665 func (stream, "s");
8666 if (given & 0x20000)
8667 func (stream, "x");
8668 if (given & 0x10000)
8669 func (stream, "c");
8670 }
252b5132
RH		 8671 break;
8672
62b3e311 8673 case 'U':
43e65147 8674 if ((given & 0xf0) == 0x60)
62b3e311 8675 {
52e7f43d
RE		 8676 switch (given & 0xf)
8677 {
8678 case 0xf: func (stream, "sy"); break;
8679 default:
8680 func (stream, "#%d", (int) given & 0xf);
8681 break;
8682 }
43e65147
L		 8683 }
8684 else
52e7f43d 8685 {
e797f7e0
MGD		 8686 const char * opt = data_barrier_option (given & 0xf);
8687 if (opt != NULL)
8688 func (stream, "%s", opt);
8689 else
52e7f43d 8690 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 8691 }
8692 break;
8693
b34976b6 8694 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 8695 case '5': case '6': case '7': case '8': case '9':
8696 {
16980d0b
JB		 8697 int width;
8698 unsigned long value;
252b5132 8699
16980d0b 8700 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 8701
252b5132
RH		 8702 switch (*c)
8703 {
ab8e2090
NC		 8704 case 'R':
8705 if (value == 15)
8706 is_unpredictable = TRUE;
8707 /* Fall through. */
16980d0b 8708 case 'r':
9eb6c0f1
MGD		 8709 case 'T':
8710 /* We want register + 1 when decoding T. */
8711 if (*c == 'T')
8712 ++value;
8713
ff4a8d2b
NC		 8714 if (c[1] == 'u')
8715 {
8716 /* Eat the 'u' character. */
8717 ++ c;
8718
8719 if (u_reg == value)
8720 is_unpredictable = TRUE;
8721 u_reg = value;
8722 }
8723 if (c[1] == 'U')
8724 {
8725 /* Eat the 'U' character. */
8726 ++ c;
8727
8728 if (U_reg == value)
8729 is_unpredictable = TRUE;
8730 U_reg = value;
8731 }
16980d0b
JB		 8732 func (stream, "%s", arm_regnames[value]);
8733 break;
8734 case 'd':
8735 func (stream, "%ld", value);
05413229 8736 value_in_comment = value;
16980d0b
JB		 8737 break;
8738 case 'b':
8739 func (stream, "%ld", value * 8);
05413229 8740 value_in_comment = value * 8;
16980d0b
JB		 8741 break;
8742 case 'W':
8743 func (stream, "%ld", value + 1);
05413229 8744 value_in_comment = value + 1;
16980d0b
JB		 8745 break;
8746 case 'x':
8747 func (stream, "0x%08lx", value);
8748
8749 /* Some SWI instructions have special
8750 meanings. */
8751 if ((given & 0x0fffffff) == 0x0FF00000)
8752 func (stream, "\t; IMB");
8753 else if ((given & 0x0fffffff) == 0x0FF00001)
8754 func (stream, "\t; IMBRange");
8755 break;
8756 case 'X':
8757 func (stream, "%01lx", value & 0xf);
05413229 8758 value_in_comment = value;
252b5132
RH		 8759 break;
8760 case '`':
8761 c++;
16980d0b 8762 if (value == 0)
252b5132
RH		 8763 func (stream, "%c", *c);
8764 break;
8765 case '\'':
8766 c++;
16980d0b 8767 if (value == ((1ul << width) - 1))
252b5132
RH		 8768 func (stream, "%c", *c);
8769 break;
8770 case '?':
fe56b6ce 8771 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 8772 c += 1 << width;
252b5132
RH		 8773 break;
8774 default:
8775 abort ();
8776 }
dffaa15c
AM		 8777 }
8778 break;
0dd132b6 8779
dffaa15c
AM		 8780 case 'e':
8781 {
8782 int imm;
0dd132b6 8783
dffaa15c
AM		 8784 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
8785 func (stream, "%d", imm);
8786 value_in_comment = imm;
8787 }
8788 break;
fe56b6ce 8789
dffaa15c
AM		 8790 case 'E':
8791 /* LSB and WIDTH fields of BFI or BFC. The machine-
8792 language instruction encodes LSB and MSB. */
8793 {
8794 long msb = (given & 0x001f0000) >> 16;
8795 long lsb = (given & 0x00000f80) >> 7;
8796 long w = msb - lsb + 1;
0a003adc 8797
dffaa15c
AM		 8798 if (w > 0)
8799 func (stream, "#%lu, #%lu", lsb, w);
8800 else
8801 func (stream, "(invalid: %lu:%lu)", lsb, msb);
8802 }
8803 break;
90ec0d68 8804
dffaa15c
AM		 8805 case 'R':
8806 /* Get the PSR/banked register name. */
8807 {
8808 const char * name;
8809 unsigned sysm = (given & 0x004f0000) >> 16;
90ec0d68 8810
dffaa15c
AM		 8811 sysm |= (given & 0x300) >> 4;
8812 name = banked_regname (sysm);
90ec0d68 8813
dffaa15c
AM		 8814 if (name != NULL)
8815 func (stream, "%s", name);
8816 else
8817 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
8818 }
8819 break;
fe56b6ce 8820
dffaa15c
AM		 8821 case 'V':
8822 /* 16-bit unsigned immediate from a MOVT or MOVW
8823 instruction, encoded in bits 0:11 and 15:19. */
8824 {
8825 long hi = (given & 0x000f0000) >> 4;
8826 long lo = (given & 0x00000fff);
8827 long imm16 = hi | lo;
0a003adc 8828
dffaa15c
AM		 8829 func (stream, "#%lu", imm16);
8830 value_in_comment = imm16;
252b5132 8831 }
dffaa15c
AM		 8832 break;
8833
8834 default:
8835 abort ();
252b5132
RH		 8836 }
8837 }
8838 else
8839 func (stream, "%c", *c);
8840 }
05413229
NC		 8841
8842 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 8843 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 8844
8845 if (is_unpredictable)
8846 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 8847
4a5329c6 8848 return;
252b5132
RH		 8849 }
8850 }
0b347048
TC		 8851 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
8852 return;
252b5132
RH		 8853}
8854
4a5329c6 8855/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 8856
4a5329c6
ZW		 8857static void
8858print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 8859{
6b5d3a4d 8860 const struct opcode16 *insn;
6a51a8a8
AM		 8861 void *stream = info->stream;
8862 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 8863
8864 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 8865 if ((given & insn->mask) == insn->value)
8866 {
05413229 8867 signed long value_in_comment = 0;
6b5d3a4d 8868 const char *c = insn->assembler;
05413229 8869
c19d1205
ZW		 8870 for (; *c; c++)
8871 {
8872 int domaskpc = 0;
8873 int domasklr = 0;
8874
8875 if (*c != '%')
8876 {
8877 func (stream, "%c", *c);
8878 continue;
8879 }
252b5132 8880
c19d1205
ZW		 8881 switch (*++c)
8882 {
8883 case '%':
8884 func (stream, "%%");
8885 break;
b34976b6 8886
c22aaad1
PB		 8887 case 'c':
8888 if (ifthen_state)
8889 func (stream, "%s", arm_conditional[IFTHEN_COND]);
8890 break;
8891
8892 case 'C':
8893 if (ifthen_state)
8894 func (stream, "%s", arm_conditional[IFTHEN_COND]);
8895 else
8896 func (stream, "s");
8897 break;
8898
8899 case 'I':
8900 {
8901 unsigned int tmp;
8902
8903 ifthen_next_state = given & 0xff;
8904 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
8905 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
8906 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
8907 }
8908 break;
8909
8910 case 'x':
8911 if (ifthen_next_state)
8912 func (stream, "\t; unpredictable branch in IT block\n");
8913 break;
8914
8915 case 'X':
8916 if (ifthen_state)
8917 func (stream, "\t; unpredictable <IT:%s>",
8918 arm_conditional[IFTHEN_COND]);
8919 break;
8920
c19d1205
ZW		 8921 case 'S':
8922 {
8923 long reg;
8924
8925 reg = (given >> 3) & 0x7;
8926 if (given & (1 << 6))
8927 reg += 8;
4f3c3dbb 8928
c19d1205
ZW		 8929 func (stream, "%s", arm_regnames[reg]);
8930 }
8931 break;
baf0cc5e 8932
c19d1205 8933 case 'D':
4f3c3dbb 8934 {
c19d1205
ZW		 8935 long reg;
8936
8937 reg = given & 0x7;
8938 if (given & (1 << 7))
8939 reg += 8;
8940
8941 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 8942 }
c19d1205
ZW		 8943 break;
8944
8945 case 'N':
8946 if (given & (1 << 8))
8947 domasklr = 1;
8948 /* Fall through. */
8949 case 'O':
8950 if (*c == 'O' && (given & (1 << 8)))
8951 domaskpc = 1;
8952 /* Fall through. */
8953 case 'M':
8954 {
8955 int started = 0;
8956 int reg;
8957
8958 func (stream, "{");
8959
8960 /* It would be nice if we could spot
8961 ranges, and generate the rS-rE format: */
8962 for (reg = 0; (reg < 8); reg++)
8963 if ((given & (1 << reg)) != 0)
8964 {
8965 if (started)
8966 func (stream, ", ");
8967 started = 1;
8968 func (stream, "%s", arm_regnames[reg]);
8969 }
8970
8971 if (domasklr)
8972 {
8973 if (started)
8974 func (stream, ", ");
8975 started = 1;
d908c8af 8976 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 8977 }
8978
8979 if (domaskpc)
8980 {
8981 if (started)
8982 func (stream, ", ");
d908c8af 8983 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 8984 }
8985
8986 func (stream, "}");
8987 }
8988 break;
8989
4547cb56
NC		 8990 case 'W':
8991 /* Print writeback indicator for a LDMIA. We are doing a
8992 writeback if the base register is not in the register
8993 mask. */
8994 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
8995 func (stream, "!");
dffaa15c 8996 break;
4547cb56 8997
c19d1205
ZW		 8998 case 'b':
8999 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
9000 {
9001 bfd_vma address = (pc + 4
9002 + ((given & 0x00f8) >> 2)
9003 + ((given & 0x0200) >> 3));
9004 info->print_address_func (address, info);
9005 }
9006 break;
9007
9008 case 's':
9009 /* Right shift immediate -- bits 6..10; 1-31 print
9010 as themselves, 0 prints as 32. */
9011 {
9012 long imm = (given & 0x07c0) >> 6;
9013 if (imm == 0)
9014 imm = 32;
0fd3a477 9015 func (stream, "#%ld", imm);
c19d1205
ZW		 9016 }
9017 break;
9018
9019 case '0': case '1': case '2': case '3': case '4':
9020 case '5': case '6': case '7': case '8': case '9':
9021 {
9022 int bitstart = *c++ - '0';
9023 int bitend = 0;
9024
9025 while (*c >= '0' && *c <= '9')
9026 bitstart = (bitstart * 10) + *c++ - '0';
9027
9028 switch (*c)
9029 {
9030 case '-':
9031 {
f8b960bc 9032 bfd_vma reg;
c19d1205
ZW		 9033
9034 c++;
9035 while (*c >= '0' && *c <= '9')
9036 bitend = (bitend * 10) + *c++ - '0';
9037 if (!bitend)
9038 abort ();
9039 reg = given >> bitstart;
9040 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 9041
c19d1205
ZW		 9042 switch (*c)
9043 {
9044 case 'r':
9045 func (stream, "%s", arm_regnames[reg]);
9046 break;
9047
9048 case 'd':
d908c8af 9049 func (stream, "%ld", (long) reg);
05413229 9050 value_in_comment = reg;
c19d1205
ZW		 9051 break;
9052
9053 case 'H':
d908c8af 9054 func (stream, "%ld", (long) (reg << 1));
05413229 9055 value_in_comment = reg << 1;
c19d1205
ZW		 9056 break;
9057
9058 case 'W':
d908c8af 9059 func (stream, "%ld", (long) (reg << 2));
05413229 9060 value_in_comment = reg << 2;
c19d1205
ZW		 9061 break;
9062
9063 case 'a':
9064 /* PC-relative address -- the bottom two
9065 bits of the address are dropped
9066 before the calculation. */
9067 info->print_address_func
9068 (((pc + 4) & ~3) + (reg << 2), info);
05413229 9069 value_in_comment = 0;
c19d1205
ZW		 9070 break;
9071
9072 case 'x':
d908c8af 9073 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 9074 break;
9075
c19d1205
ZW		 9076 case 'B':
9077 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6b5d3a4d 9078 info->print_address_func (reg * 2 + pc + 4, info);
05413229 9079 value_in_comment = 0;
c19d1205
ZW		 9080 break;
9081
9082 case 'c':
c22aaad1 9083 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 9084 break;
9085
9086 default:
9087 abort ();
9088 }
9089 }
9090 break;
9091
9092 case '\'':
9093 c++;
9094 if ((given & (1 << bitstart)) != 0)
9095 func (stream, "%c", *c);
9096 break;
9097
9098 case '?':
9099 ++c;
9100 if ((given & (1 << bitstart)) != 0)
9101 func (stream, "%c", *c++);
9102 else
9103 func (stream, "%c", *++c);
9104 break;
9105
9106 default:
9107 abort ();
9108 }
9109 }
9110 break;
9111
9112 default:
9113 abort ();
9114 }
9115 }
05413229
NC		 9116
9117 if (value_in_comment > 32 || value_in_comment < -16)
9118 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 9119 return;
c19d1205
ZW		 9120 }
9121
9122 /* No match. */
0b347048
TC		 9123 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
9124 return;
c19d1205
ZW		 9125}
9126
62b3e311 9127/* Return the name of an V7M special register. */
fe56b6ce 9128
62b3e311
PB		 9129static const char *
9130psr_name (int regno)
9131{
9132 switch (regno)
9133 {
1a336194
TP		 9134 case 0x0: return "APSR";
9135 case 0x1: return "IAPSR";
9136 case 0x2: return "EAPSR";
9137 case 0x3: return "PSR";
9138 case 0x5: return "IPSR";
9139 case 0x6: return "EPSR";
9140 case 0x7: return "IEPSR";
9141 case 0x8: return "MSP";
9142 case 0x9: return "PSP";
9143 case 0xa: return "MSPLIM";
9144 case 0xb: return "PSPLIM";
9145 case 0x10: return "PRIMASK";
9146 case 0x11: return "BASEPRI";
9147 case 0x12: return "BASEPRI_MAX";
9148 case 0x13: return "FAULTMASK";
9149 case 0x14: return "CONTROL";
16a1fa25
TP		 9150 case 0x88: return "MSP_NS";
9151 case 0x89: return "PSP_NS";
1a336194
TP		 9152 case 0x8a: return "MSPLIM_NS";
9153 case 0x8b: return "PSPLIM_NS";
9154 case 0x90: return "PRIMASK_NS";
9155 case 0x91: return "BASEPRI_NS";
9156 case 0x93: return "FAULTMASK_NS";
9157 case 0x94: return "CONTROL_NS";
9158 case 0x98: return "SP_NS";
62b3e311
PB		 9159 default: return "<unknown>";
9160 }
9161}
9162
4a5329c6
ZW		 9163/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
9164
9165static void
9166print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 9167{
6b5d3a4d 9168 const struct opcode32 *insn;
c19d1205
ZW		 9169 void *stream = info->stream;
9170 fprintf_ftype func = info->fprintf_func;
73cd51e5 9171 bfd_boolean is_mve = is_mve_architecture (info);
c19d1205 9172
16980d0b
JB		 9173 if (print_insn_coprocessor (pc, info, given, TRUE))
9174 return;
9175
73cd51e5
AV		 9176 if ((is_mve == FALSE) && print_insn_neon (info, given, TRUE))
9177 return;
9178
9179 if (is_mve && print_insn_mve (info, given))
8f06b2d8
PB		 9180 return;
9181
c19d1205
ZW		 9182 for (insn = thumb32_opcodes; insn->assembler; insn++)
9183 if ((given & insn->mask) == insn->value)
9184 {
4b5a202f 9185 bfd_boolean is_clrm = FALSE;
ff4a8d2b 9186 bfd_boolean is_unpredictable = FALSE;
05413229 9187 signed long value_in_comment = 0;
6b5d3a4d 9188 const char *c = insn->assembler;
05413229 9189
c19d1205
ZW		 9190 for (; *c; c++)
9191 {
9192 if (*c != '%')
9193 {
9194 func (stream, "%c", *c);
9195 continue;
9196 }
9197
9198 switch (*++c)
9199 {
9200 case '%':
9201 func (stream, "%%");
9202 break;
9203
c22aaad1
PB		 9204 case 'c':
9205 if (ifthen_state)
9206 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9207 break;
9208
9209 case 'x':
9210 if (ifthen_next_state)
9211 func (stream, "\t; unpredictable branch in IT block\n");
9212 break;
9213
9214 case 'X':
9215 if (ifthen_state)
9216 func (stream, "\t; unpredictable <IT:%s>",
9217 arm_conditional[IFTHEN_COND]);
9218 break;
9219
c19d1205
ZW		 9220 case 'I':
9221 {
9222 unsigned int imm12 = 0;
fe56b6ce 9223
c19d1205
ZW		 9224 imm12 |= (given & 0x000000ffu);
9225 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 9226 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 9227 func (stream, "#%u", imm12);
9228 value_in_comment = imm12;
c19d1205
ZW		 9229 }
9230 break;
9231
9232 case 'M':
9233 {
9234 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 9235
c19d1205
ZW		 9236 bits |= (given & 0x000000ffu);
9237 bits |= (given & 0x00007000u) >> 4;
9238 bits |= (given & 0x04000000u) >> 15;
9239 imm8 = (bits & 0x0ff);
9240 mod = (bits & 0xf00) >> 8;
9241 switch (mod)
9242 {
9243 case 0: imm = imm8; break;
c1e26897
NC		 9244 case 1: imm = ((imm8 << 16) | imm8); break;
9245 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
9246 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 9247 default:
9248 mod = (bits & 0xf80) >> 7;
9249 imm8 = (bits & 0x07f) | 0x80;
9250 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
9251 }
fe56b6ce
NC		 9252 func (stream, "#%u", imm);
9253 value_in_comment = imm;
c19d1205
ZW		 9254 }
9255 break;
43e65147 9256
c19d1205
ZW		 9257 case 'J':
9258 {
9259 unsigned int imm = 0;
fe56b6ce 9260
c19d1205
ZW		 9261 imm |= (given & 0x000000ffu);
9262 imm |= (given & 0x00007000u) >> 4;
9263 imm |= (given & 0x04000000u) >> 15;
9264 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 9265 func (stream, "#%u", imm);
9266 value_in_comment = imm;
c19d1205
ZW		 9267 }
9268 break;
9269
9270 case 'K':
9271 {
9272 unsigned int imm = 0;
fe56b6ce 9273
c19d1205
ZW		 9274 imm |= (given & 0x000f0000u) >> 16;
9275 imm |= (given & 0x00000ff0u) >> 0;
9276 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 9277 func (stream, "#%u", imm);
9278 value_in_comment = imm;
c19d1205
ZW		 9279 }
9280 break;
9281
74db7efb
NC		 9282 case 'H':
9283 {
9284 unsigned int imm = 0;
9285
9286 imm |= (given & 0x000f0000u) >> 4;
9287 imm |= (given & 0x00000fffu) >> 0;
9288 func (stream, "#%u", imm);
9289 value_in_comment = imm;
9290 }
9291 break;
9292
90ec0d68
MGD		 9293 case 'V':
9294 {
9295 unsigned int imm = 0;
9296
9297 imm |= (given & 0x00000fffu);
9298 imm |= (given & 0x000f0000u) >> 4;
9299 func (stream, "#%u", imm);
9300 value_in_comment = imm;
9301 }
9302 break;
9303
c19d1205
ZW		 9304 case 'S':
9305 {
9306 unsigned int reg = (given & 0x0000000fu);
9307 unsigned int stp = (given & 0x00000030u) >> 4;
9308 unsigned int imm = 0;
9309 imm |= (given & 0x000000c0u) >> 6;
9310 imm |= (given & 0x00007000u) >> 10;
9311
9312 func (stream, "%s", arm_regnames[reg]);
9313 switch (stp)
9314 {
9315 case 0:
9316 if (imm > 0)
9317 func (stream, ", lsl #%u", imm);
9318 break;
9319
9320 case 1:
9321 if (imm == 0)
9322 imm = 32;
9323 func (stream, ", lsr #%u", imm);
9324 break;
9325
9326 case 2:
9327 if (imm == 0)
9328 imm = 32;
9329 func (stream, ", asr #%u", imm);
9330 break;
9331
9332 case 3:
9333 if (imm == 0)
9334 func (stream, ", rrx");
9335 else
9336 func (stream, ", ror #%u", imm);
9337 }
9338 }
9339 break;
9340
9341 case 'a':
9342 {
9343 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 9344 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 9345 unsigned int op = (given & 0x00000f00) >> 8;
9346 unsigned int i12 = (given & 0x00000fff);
9347 unsigned int i8 = (given & 0x000000ff);
9348 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 9349 bfd_vma offset = 0;
c19d1205
ZW		 9350
9351 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 9352 if (U) /* 12-bit positive immediate offset. */
9353 {
9354 offset = i12;
9355 if (Rn != 15)
9356 value_in_comment = offset;
9357 }
9358 else if (Rn == 15) /* 12-bit negative immediate offset. */
9359 offset = - (int) i12;
9360 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 9361 {
9362 unsigned int Rm = (i8 & 0x0f);
9363 unsigned int sh = (i8 & 0x30) >> 4;
05413229 9364
c19d1205
ZW		 9365 func (stream, ", %s", arm_regnames[Rm]);
9366 if (sh)
9367 func (stream, ", lsl #%u", sh);
9368 func (stream, "]");
9369 break;
9370 }
9371 else switch (op)
9372 {
05413229 9373 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 9374 offset = i8;
9375 break;
9376
05413229 9377 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 9378 offset = -i8;
9379 break;
9380
05413229 9381 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 9382 offset = i8;
9383 writeback = TRUE;
9384 break;
9385
05413229 9386 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 9387 offset = -i8;
9388 writeback = TRUE;
9389 break;
9390
05413229 9391 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 9392 offset = i8;
9393 postind = TRUE;
9394 break;
9395
05413229 9396 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 9397 offset = -i8;
9398 postind = TRUE;
9399 break;
9400
9401 default:
9402 func (stream, ", <undefined>]");
9403 goto skip;
9404 }
9405
9406 if (postind)
d908c8af 9407 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 9408 else
9409 {
9410 if (offset)
d908c8af 9411 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 9412 func (stream, writeback ? "]!" : "]");
9413 }
9414
9415 if (Rn == 15)
9416 {
9417 func (stream, "\t; ");
9418 info->print_address_func (((pc + 4) & ~3) + offset, info);
9419 }
9420 }
9421 skip:
9422 break;
9423
9424 case 'A':
9425 {
c1e26897
NC		 9426 unsigned int U = ! NEGATIVE_BIT_SET;
9427 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 9428 unsigned int Rn = (given & 0x000f0000) >> 16;
9429 unsigned int off = (given & 0x000000ff);
9430
9431 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 9432
9433 if (PRE_BIT_SET)
c19d1205
ZW		 9434 {
9435 if (off || !U)
05413229
NC		 9436 {
9437 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
fe50e98c 9438 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 9439 }
c19d1205
ZW		 9440 func (stream, "]");
9441 if (W)
9442 func (stream, "!");
9443 }
9444 else
9445 {
9446 func (stream, "], ");
9447 if (W)
05413229
NC		 9448 {
9449 func (stream, "#%c%u", U ? '+' : '-', off * 4);
fe50e98c 9450 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 9451 }
c19d1205 9452 else
fe56b6ce
NC		 9453 {
9454 func (stream, "{%u}", off);
9455 value_in_comment = off;
9456 }
c19d1205
ZW		 9457 }
9458 }
9459 break;
9460
9461 case 'w':
9462 {
9463 unsigned int Sbit = (given & 0x01000000) >> 24;
9464 unsigned int type = (given & 0x00600000) >> 21;
05413229 9465
c19d1205
ZW		 9466 switch (type)
9467 {
9468 case 0: func (stream, Sbit ? "sb" : "b"); break;
9469 case 1: func (stream, Sbit ? "sh" : "h"); break;
9470 case 2:
9471 if (Sbit)
9472 func (stream, "??");
9473 break;
9474 case 3:
9475 func (stream, "??");
9476 break;
9477 }
9478 }
9479 break;
9480
4b5a202f
AV		 9481 case 'n':
9482 is_clrm = TRUE;
9483 /* Fall through. */
c19d1205
ZW		 9484 case 'm':
9485 {
9486 int started = 0;
9487 int reg;
9488
9489 func (stream, "{");
9490 for (reg = 0; reg < 16; reg++)
9491 if ((given & (1 << reg)) != 0)
9492 {
9493 if (started)
9494 func (stream, ", ");
9495 started = 1;
4b5a202f
AV		 9496 if (is_clrm && reg == 13)
9497 func (stream, "(invalid: %s)", arm_regnames[reg]);
9498 else if (is_clrm && reg == 15)
9499 func (stream, "%s", "APSR");
9500 else
9501 func (stream, "%s", arm_regnames[reg]);
c19d1205
ZW		 9502 }
9503 func (stream, "}");
9504 }
9505 break;
9506
9507 case 'E':
9508 {
9509 unsigned int msb = (given & 0x0000001f);
9510 unsigned int lsb = 0;
fe56b6ce 9511
c19d1205
ZW		 9512 lsb |= (given & 0x000000c0u) >> 6;
9513 lsb |= (given & 0x00007000u) >> 10;
9514 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
9515 }
9516 break;
9517
9518 case 'F':
9519 {
9520 unsigned int width = (given & 0x0000001f) + 1;
9521 unsigned int lsb = 0;
fe56b6ce 9522
c19d1205
ZW		 9523 lsb |= (given & 0x000000c0u) >> 6;
9524 lsb |= (given & 0x00007000u) >> 10;
9525 func (stream, "#%u, #%u", lsb, width);
9526 }
9527 break;
9528
e12437dc
AV		 9529 case 'G':
9530 {
9531 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
9532 func (stream, "%x", boff);
9533 }
9534 break;
9535
e5d6e09e
AV		 9536 case 'W':
9537 {
9538 unsigned int immA = (given & 0x001f0000u) >> 16;
9539 unsigned int immB = (given & 0x000007feu) >> 1;
9540 unsigned int immC = (given & 0x00000800u) >> 11;
9541 bfd_vma offset = 0;
9542
9543 offset |= immA << 12;
9544 offset |= immB << 2;
9545 offset |= immC << 1;
9546 /* Sign extend. */
9547 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
9548
9549 info->print_address_func (pc + 4 + offset, info);
9550 }
9551 break;
9552
1caf72a5
AV		 9553 case 'Y':
9554 {
9555 unsigned int immA = (given & 0x007f0000u) >> 16;
9556 unsigned int immB = (given & 0x000007feu) >> 1;
9557 unsigned int immC = (given & 0x00000800u) >> 11;
9558 bfd_vma offset = 0;
9559
9560 offset |= immA << 12;
9561 offset |= immB << 2;
9562 offset |= immC << 1;
9563 /* Sign extend. */
9564 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
9565
9566 info->print_address_func (pc + 4 + offset, info);
9567 }
9568 break;
9569
1889da70
AV		 9570 case 'Z':
9571 {
9572 unsigned int immA = (given & 0x00010000u) >> 16;
9573 unsigned int immB = (given & 0x000007feu) >> 1;
9574 unsigned int immC = (given & 0x00000800u) >> 11;
9575 bfd_vma offset = 0;
9576
9577 offset |= immA << 12;
9578 offset |= immB << 2;
9579 offset |= immC << 1;
9580 /* Sign extend. */
9581 offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
9582
9583 info->print_address_func (pc + 4 + offset, info);
f6b2b12d
AV		 9584
9585 unsigned int T = (given & 0x00020000u) >> 17;
9586 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
9587 unsigned int boffset = (T == 1) ? 4 : 2;
9588 func (stream, ", ");
9589 func (stream, "%x", endoffset + boffset);
1889da70
AV		 9590 }
9591 break;
9592
60f993ce
AV		 9593 case 'Q':
9594 {
9595 unsigned int immh = (given & 0x000007feu) >> 1;
9596 unsigned int imml = (given & 0x00000800u) >> 11;
9597 bfd_vma imm32 = 0;
9598
9599 imm32 |= immh << 2;
9600 imm32 |= imml << 1;
9601
9602 info->print_address_func (pc + 4 + imm32, info);
9603 }
9604 break;
9605
9606 case 'P':
9607 {
9608 unsigned int immh = (given & 0x000007feu) >> 1;
9609 unsigned int imml = (given & 0x00000800u) >> 11;
9610 bfd_vma imm32 = 0;
9611
9612 imm32 |= immh << 2;
9613 imm32 |= imml << 1;
9614
9615 info->print_address_func (pc + 4 - imm32, info);
9616 }
9617 break;
9618
c19d1205
ZW		 9619 case 'b':
9620 {
9621 unsigned int S = (given & 0x04000000u) >> 26;
9622 unsigned int J1 = (given & 0x00002000u) >> 13;
9623 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 9624 bfd_vma offset = 0;
c19d1205
ZW		 9625
9626 offset |= !S << 20;
9627 offset |= J2 << 19;
9628 offset |= J1 << 18;
9629 offset |= (given & 0x003f0000) >> 4;
9630 offset |= (given & 0x000007ff) << 1;
9631 offset -= (1 << 20);
9632
9633 info->print_address_func (pc + 4 + offset, info);
9634 }
9635 break;
9636
9637 case 'B':
9638 {
9639 unsigned int S = (given & 0x04000000u) >> 26;
9640 unsigned int I1 = (given & 0x00002000u) >> 13;
9641 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 9642 bfd_vma offset = 0;
c19d1205
ZW		 9643
9644 offset |= !S << 24;
9645 offset |= !(I1 ^ S) << 23;
9646 offset |= !(I2 ^ S) << 22;
9647 offset |= (given & 0x03ff0000u) >> 4;
9648 offset |= (given & 0x000007ffu) << 1;
9649 offset -= (1 << 24);
36b0c57d 9650 offset += pc + 4;
c19d1205 9651
36b0c57d
PB		 9652 /* BLX target addresses are always word aligned. */
9653 if ((given & 0x00001000u) == 0)
9654 offset &= ~2u;
9655
9656 info->print_address_func (offset, info);
c19d1205
ZW		 9657 }
9658 break;
9659
9660 case 's':
9661 {
9662 unsigned int shift = 0;
fe56b6ce 9663
c19d1205
ZW		 9664 shift |= (given & 0x000000c0u) >> 6;
9665 shift |= (given & 0x00007000u) >> 10;
c1e26897 9666 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 9667 func (stream, ", asr #%u", shift);
9668 else if (shift)
9669 func (stream, ", lsl #%u", shift);
9670 /* else print nothing - lsl #0 */
9671 }
9672 break;
9673
9674 case 'R':
9675 {
9676 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 9677
c19d1205
ZW		 9678 if (rot)
9679 func (stream, ", ror #%u", rot * 8);
9680 }
9681 break;
9682
62b3e311 9683 case 'U':
43e65147 9684 if ((given & 0xf0) == 0x60)
62b3e311 9685 {
52e7f43d
RE		 9686 switch (given & 0xf)
9687 {
9688 case 0xf: func (stream, "sy"); break;
9689 default:
9690 func (stream, "#%d", (int) given & 0xf);
9691 break;
9692 }
62b3e311 9693 }
43e65147 9694 else
52e7f43d 9695 {
e797f7e0
MGD		 9696 const char * opt = data_barrier_option (given & 0xf);
9697 if (opt != NULL)
9698 func (stream, "%s", opt);
9699 else
9700 func (stream, "#%d", (int) given & 0xf);
52e7f43d 9701 }
62b3e311
PB		 9702 break;
9703
9704 case 'C':
9705 if ((given & 0xff) == 0)
9706 {
9707 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
9708 if (given & 0x800)
9709 func (stream, "f");
9710 if (given & 0x400)
9711 func (stream, "s");
9712 if (given & 0x200)
9713 func (stream, "x");
9714 if (given & 0x100)
9715 func (stream, "c");
9716 }
90ec0d68
MGD		 9717 else if ((given & 0x20) == 0x20)
9718 {
9719 char const* name;
9720 unsigned sysm = (given & 0xf00) >> 8;
9721
9722 sysm |= (given & 0x30);
9723 sysm |= (given & 0x00100000) >> 14;
9724 name = banked_regname (sysm);
43e65147 9725
90ec0d68
MGD		 9726 if (name != NULL)
9727 func (stream, "%s", name);
9728 else
d908c8af 9729 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 9730 }
62b3e311
PB		 9731 else
9732 {
d908c8af 9733 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 9734 }
9735 break;
9736
9737 case 'D':
90ec0d68
MGD		 9738 if (((given & 0xff) == 0)
9739 || ((given & 0x20) == 0x20))
9740 {
9741 char const* name;
9742 unsigned sm = (given & 0xf0000) >> 16;
9743
9744 sm |= (given & 0x30);
9745 sm |= (given & 0x00100000) >> 14;
9746 name = banked_regname (sm);
9747
9748 if (name != NULL)
9749 func (stream, "%s", name);
9750 else
d908c8af 9751 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 9752 }
62b3e311 9753 else
d908c8af 9754 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 9755 break;
9756
c19d1205
ZW		 9757 case '0': case '1': case '2': case '3': case '4':
9758 case '5': case '6': case '7': case '8': case '9':
9759 {
16980d0b
JB		 9760 int width;
9761 unsigned long val;
c19d1205 9762
16980d0b 9763 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 9764
c19d1205
ZW		 9765 switch (*c)
9766 {
05413229
NC		 9767 case 'd':
9768 func (stream, "%lu", val);
9769 value_in_comment = val;
9770 break;
ff4a8d2b 9771
f0fba320
RL		 9772 case 'D':
9773 func (stream, "%lu", val + 1);
9774 value_in_comment = val + 1;
9775 break;
9776
05413229
NC		 9777 case 'W':
9778 func (stream, "%lu", val * 4);
9779 value_in_comment = val * 4;
9780 break;
ff4a8d2b 9781
f1c7f421
AV		 9782 case 'S':
9783 if (val == 13)
9784 is_unpredictable = TRUE;
9785 /* Fall through. */
ff4a8d2b
NC		 9786 case 'R':
9787 if (val == 15)
9788 is_unpredictable = TRUE;
9789 /* Fall through. */
9790 case 'r':
9791 func (stream, "%s", arm_regnames[val]);
9792 break;
c19d1205
ZW		 9793
9794 case 'c':
c22aaad1 9795 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 9796 break;
9797
9798 case '\'':
c19d1205 9799 c++;
16980d0b
JB		 9800 if (val == ((1ul << width) - 1))
9801 func (stream, "%c", *c);
c19d1205 9802 break;
43e65147 9803
c19d1205 9804 case '`':
c19d1205 9805 c++;
16980d0b
JB		 9806 if (val == 0)
9807 func (stream, "%c", *c);
c19d1205
ZW		 9808 break;
9809
9810 case '?':
fe56b6ce 9811 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 9812 c += 1 << width;
c19d1205 9813 break;
43e65147 9814
0bb027fd
RR		 9815 case 'x':
9816 func (stream, "0x%lx", val & 0xffffffffUL);
9817 break;
c19d1205
ZW		 9818
9819 default:
9820 abort ();
9821 }
9822 }
9823 break;
9824
32a94698
NC		 9825 case 'L':
9826 /* PR binutils/12534
9827 If we have a PC relative offset in an LDRD or STRD
9828 instructions then display the decoded address. */
9829 if (((given >> 16) & 0xf) == 0xf)
9830 {
9831 bfd_vma offset = (given & 0xff) * 4;
9832
9833 if ((given & (1 << 23)) == 0)
9834 offset = - offset;
9835 func (stream, "\t; ");
9836 info->print_address_func ((pc & ~3) + 4 + offset, info);
9837 }
9838 break;
9839
c19d1205
ZW		 9840 default:
9841 abort ();
9842 }
9843 }
05413229
NC		 9844
9845 if (value_in_comment > 32 || value_in_comment < -16)
9846 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 9847
9848 if (is_unpredictable)
9849 func (stream, UNPREDICTABLE_INSTRUCTION);
9850
4a5329c6 9851 return;
c19d1205 9852 }
252b5132 9853
58efb6c0 9854 /* No match. */
0b347048
TC		 9855 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
9856 return;
252b5132
RH		 9857}
9858
e821645d
DJ		 9859/* Print data bytes on INFO->STREAM. */
9860
9861static void
fe56b6ce
NC		 9862print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
9863 struct disassemble_info *info,
e821645d
DJ		 9864 long given)
9865{
9866 switch (info->bytes_per_chunk)
9867 {
9868 case 1:
9869 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
9870 break;
9871 case 2:
9872 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
9873 break;
9874 case 4:
9875 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
9876 break;
9877 default:
9878 abort ();
9879 }
9880}
9881
22a398e1 9882/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 9883 being displayed in symbol relative addresses.
9884
9885 Also disallow private symbol, with __tagsym$$ prefix,
9886 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 9887
9888bfd_boolean
9889arm_symbol_is_valid (asymbol * sym,
9890 struct disassemble_info * info ATTRIBUTE_UNUSED)
9891{
9892 const char * name;
43e65147 9893
22a398e1
NC		 9894 if (sym == NULL)
9895 return FALSE;
9896
9897 name = bfd_asymbol_name (sym);
9898
d8282f0e 9899 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 9900}
9901
65b48a81 9902/* Parse the string of disassembler options. */
baf0cc5e 9903
65b48a81 9904static void
f995bbe8 9905parse_arm_disassembler_options (const char *options)
dd92f639 9906{
f995bbe8 9907 const char *opt;
b34976b6 9908
65b48a81 9909 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
dd92f639 9910 {
65b48a81
PB		 9911 if (CONST_STRNEQ (opt, "reg-names-"))
9912 {
9913 unsigned int i;
9914 for (i = 0; i < NUM_ARM_OPTIONS; i++)
9915 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
9916 {
9917 regname_selected = i;
9918 break;
9919 }
b34976b6 9920
65b48a81 9921 if (i >= NUM_ARM_OPTIONS)
a6743a54
AM		 9922 /* xgettext: c-format */
9923 opcodes_error_handler (_("unrecognised register name set: %s"),
9924 opt);
65b48a81
PB		 9925 }
9926 else if (CONST_STRNEQ (opt, "force-thumb"))
9927 force_thumb = 1;
9928 else if (CONST_STRNEQ (opt, "no-force-thumb"))
9929 force_thumb = 0;
9930 else
a6743a54
AM		 9931 /* xgettext: c-format */
9932 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
dd92f639 9933 }
b34976b6 9934
dd92f639
NC		 9935 return;
9936}
9937
5bc5ae88
RL		 9938static bfd_boolean
9939mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
9940 enum map_type *map_symbol);
9941
c22aaad1
PB		 9942/* Search back through the insn stream to determine if this instruction is
9943 conditionally executed. */
fe56b6ce 9944
c22aaad1 9945static void
fe56b6ce
NC		 9946find_ifthen_state (bfd_vma pc,
9947 struct disassemble_info *info,
c22aaad1
PB		 9948 bfd_boolean little)
9949{
9950 unsigned char b[2];
9951 unsigned int insn;
9952 int status;
9953 /* COUNT is twice the number of instructions seen. It will be odd if we
9954 just crossed an instruction boundary. */
9955 int count;
9956 int it_count;
9957 unsigned int seen_it;
9958 bfd_vma addr;
9959
9960 ifthen_address = pc;
9961 ifthen_state = 0;
9962
9963 addr = pc;
9964 count = 1;
9965 it_count = 0;
9966 seen_it = 0;
9967 /* Scan backwards looking for IT instructions, keeping track of where
9968 instruction boundaries are. We don't know if something is actually an
9969 IT instruction until we find a definite instruction boundary. */
9970 for (;;)
9971 {
fe56b6ce 9972 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 9973 {
9974 /* A symbol must be on an instruction boundary, and will not
9975 be within an IT block. */
9976 if (seen_it && (count & 1))
9977 break;
9978
9979 return;
9980 }
9981 addr -= 2;
fe56b6ce 9982 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 9983 if (status)
9984 return;
9985
9986 if (little)
9987 insn = (b[0]) | (b[1] << 8);
9988 else
9989 insn = (b[1]) | (b[0] << 8);
9990 if (seen_it)
9991 {
9992 if ((insn & 0xf800) < 0xe800)
9993 {
9994 /* Addr + 2 is an instruction boundary. See if this matches
9995 the expected boundary based on the position of the last
9996 IT candidate. */
9997 if (count & 1)
9998 break;
9999 seen_it = 0;
10000 }
10001 }
10002 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
10003 {
5bc5ae88
RL		 10004 enum map_type type = MAP_ARM;
10005 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
10006
10007 if (!found || (found && type == MAP_THUMB))
10008 {
10009 /* This could be an IT instruction. */
10010 seen_it = insn;
10011 it_count = count >> 1;
10012 }
c22aaad1
PB		 10013 }
10014 if ((insn & 0xf800) >= 0xe800)
10015 count++;
10016 else
10017 count = (count + 2) | 1;
10018 /* IT blocks contain at most 4 instructions. */
10019 if (count >= 8 && !seen_it)
10020 return;
10021 }
10022 /* We found an IT instruction. */
10023 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
10024 if ((ifthen_state & 0xf) == 0)
10025 ifthen_state = 0;
10026}
10027
b0e28b39
DJ		 10028/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
10029 mapping symbol. */
10030
10031static int
10032is_mapping_symbol (struct disassemble_info *info, int n,
10033 enum map_type *map_type)
10034{
10035 const char *name;
10036
10037 name = bfd_asymbol_name (info->symtab[n]);
10038 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
10039 && (name[2] == 0 || name[2] == '.'))
10040 {
10041 *map_type = ((name[1] == 'a') ? MAP_ARM
10042 : (name[1] == 't') ? MAP_THUMB
10043 : MAP_DATA);
10044 return TRUE;
10045 }
10046
10047 return FALSE;
10048}
10049
10050/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
10051 Returns nonzero if *MAP_TYPE was set. */
10052
10053static int
10054get_map_sym_type (struct disassemble_info *info,
10055 int n,
10056 enum map_type *map_type)
10057{
10058 /* If the symbol is in a different section, ignore it. */
10059 if (info->section != NULL && info->section != info->symtab[n]->section)
10060 return FALSE;
10061
10062 return is_mapping_symbol (info, n, map_type);
10063}
10064
10065/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 10066 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 10067
10068static int
fe56b6ce
NC		 10069get_sym_code_type (struct disassemble_info *info,
10070 int n,
e821645d 10071 enum map_type *map_type)
2087ad84
PB		 10072{
10073 elf_symbol_type *es;
10074 unsigned int type;
b0e28b39
DJ		 10075
10076 /* If the symbol is in a different section, ignore it. */
10077 if (info->section != NULL && info->section != info->symtab[n]->section)
10078 return FALSE;
2087ad84 10079
e821645d 10080 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 10081 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
10082
10083 /* If the symbol has function type then use that. */
34e77a92 10084 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 10085 {
39d911fc
TP		 10086 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
10087 == ST_BRANCH_TO_THUMB)
35fc36a8
RS		 10088 *map_type = MAP_THUMB;
10089 else
10090 *map_type = MAP_ARM;
2087ad84
PB		 10091 return TRUE;
10092 }
10093
2087ad84
PB		 10094 return FALSE;
10095}
10096
5bc5ae88
RL		 10097/* Search the mapping symbol state for instruction at pc. This is only
10098 applicable for elf target.
10099
10100 There is an assumption Here, info->private_data contains the correct AND
10101 up-to-date information about current scan process. The information will be
10102 used to speed this search process.
10103
10104 Return TRUE if the mapping state can be determined, and map_symbol
10105 will be updated accordingly. Otherwise, return FALSE. */
10106
10107static bfd_boolean
10108mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
10109 enum map_type *map_symbol)
10110{
796d6298
TC		 10111 bfd_vma addr, section_vma = 0;
10112 int n, last_sym = -1;
5bc5ae88 10113 bfd_boolean found = FALSE;
796d6298
TC		 10114 bfd_boolean can_use_search_opt_p = FALSE;
10115
10116 /* Default to DATA. A text section is required by the ABI to contain an
10117 INSN mapping symbol at the start. A data section has no such
10118 requirement, hence if no mapping symbol is found the section must
10119 contain only data. This however isn't very useful if the user has
10120 fully stripped the binaries. If this is the case use the section
10121 attributes to determine the default. If we have no section default to
10122 INSN as well, as we may be disassembling some raw bytes on a baremetal
10123 HEX file or similar. */
10124 enum map_type type = MAP_DATA;
10125 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
10126 type = MAP_ARM;
5bc5ae88
RL		 10127 struct arm_private_data *private_data;
10128
796d6298 10129 if (info->private_data == NULL
5bc5ae88
RL		 10130 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
10131 return FALSE;
10132
10133 private_data = info->private_data;
5bc5ae88 10134
796d6298
TC		 10135 /* First, look for mapping symbols. */
10136 if (info->symtab_size != 0)
10137 {
10138 if (pc <= private_data->last_mapping_addr)
10139 private_data->last_mapping_sym = -1;
10140
10141 /* Start scanning at the start of the function, or wherever
10142 we finished last time. */
10143 n = info->symtab_pos + 1;
10144
10145 /* If the last stop offset is different from the current one it means we
10146 are disassembling a different glob of bytes. As such the optimization
10147 would not be safe and we should start over. */
10148 can_use_search_opt_p
10149 = private_data->last_mapping_sym >= 0
10150 && info->stop_offset == private_data->last_stop_offset;
10151
10152 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
10153 n = private_data->last_mapping_sym;
10154
10155 /* Look down while we haven't passed the location being disassembled.
10156 The reason for this is that there's no defined order between a symbol
10157 and an mapping symbol that may be at the same address. We may have to
10158 look at least one position ahead. */
10159 for (; n < info->symtab_size; n++)
10160 {
10161 addr = bfd_asymbol_value (info->symtab[n]);
10162 if (addr > pc)
10163 break;
10164 if (get_map_sym_type (info, n, &type))
10165 {
10166 last_sym = n;
10167 found = TRUE;
10168 }
10169 }
5bc5ae88 10170
796d6298
TC		 10171 if (!found)
10172 {
10173 n = info->symtab_pos;
10174 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
10175 n = private_data->last_mapping_sym;
10176
10177 /* No mapping symbol found at this address. Look backwards
10178 for a preceeding one, but don't go pass the section start
10179 otherwise a data section with no mapping symbol can pick up
10180 a text mapping symbol of a preceeding section. The documentation
10181 says section can be NULL, in which case we will seek up all the
10182 way to the top. */
10183 if (info->section)
10184 section_vma = info->section->vma;
10185
10186 for (; n >= 0; n--)
10187 {
10188 addr = bfd_asymbol_value (info->symtab[n]);
10189 if (addr < section_vma)
10190 break;
10191
10192 if (get_map_sym_type (info, n, &type))
10193 {
10194 last_sym = n;
10195 found = TRUE;
10196 break;
10197 }
10198 }
10199 }
10200 }
10201
10202 /* If no mapping symbol was found, try looking up without a mapping
10203 symbol. This is done by walking up from the current PC to the nearest
10204 symbol. We don't actually have to loop here since symtab_pos will
10205 contain the nearest symbol already. */
10206 if (!found)
5bc5ae88 10207 {
796d6298
TC		 10208 n = info->symtab_pos;
10209 if (n >= 0 && get_sym_code_type (info, n, &type))
5bc5ae88 10210 {
796d6298
TC		 10211 last_sym = n;
10212 found = TRUE;
5bc5ae88
RL		 10213 }
10214 }
10215
796d6298
TC		 10216 private_data->last_mapping_sym = last_sym;
10217 private_data->last_type = type;
10218 private_data->last_stop_offset = info->stop_offset;
5bc5ae88
RL		 10219
10220 *map_symbol = type;
10221 return found;
10222}
10223
0313a2b8
NC		 10224/* Given a bfd_mach_arm_XXX value, this function fills in the fields
10225 of the supplied arm_feature_set structure with bitmasks indicating
c0c468d5 10226 the supported base architectures and coprocessor extensions.
0313a2b8
NC		 10227
10228 FIXME: This could more efficiently implemented as a constant array,
10229 although it would also be less robust. */
10230
10231static void
10232select_arm_features (unsigned long mach,
10233 arm_feature_set * features)
10234{
c0c468d5
TP		 10235 arm_feature_set arch_fset;
10236 const arm_feature_set fpu_any = FPU_ANY;
10237
1af1dd51
MW		 10238#undef ARM_SET_FEATURES
10239#define ARM_SET_FEATURES(FSET) \
10240 { \
10241 const arm_feature_set fset = FSET; \
c0c468d5 10242 arch_fset = fset; \
1af1dd51 10243 }
823d2571 10244
c0c468d5
TP		 10245 /* When several architecture versions share the same bfd_mach_arm_XXX value
10246 the most featureful is chosen. */
0313a2b8
NC		 10247 switch (mach)
10248 {
c0c468d5
TP		 10249 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
10250 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
10251 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
10252 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
10253 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
10254 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
10255 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
10256 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
10257 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
10258 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
1af1dd51 10259 case bfd_mach_arm_ep9312:
c0c468d5
TP		 10260 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
10261 ARM_CEXT_MAVERICK | FPU_MAVERICK));
1af1dd51 10262 break;
c0c468d5
TP		 10263 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
10264 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
10265 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
10266 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
10267 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
10268 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
10269 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
10270 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
10271 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
10272 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
10273 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
10274 case bfd_mach_arm_8:
10275 {
0632eeea
SD		 10276 /* Add bits for extensions that Armv8.5-A recognizes. */
10277 arm_feature_set armv8_5_ext_fset
10278 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
10279 ARM_SET_FEATURES (ARM_ARCH_V8_5A);
10280 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset);
c0c468d5
TP		 10281 break;
10282 }
10283 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
10284 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
10285 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
73cd51e5
AV		 10286 case bfd_mach_arm_8_1M_MAIN:
10287 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
10288 force_thumb = 1;
10289 break;
c0c468d5
TP		 10290 /* If the machine type is unknown allow all architecture types and all
10291 extensions. */
10292 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
0313a2b8
NC		 10293 default:
10294 abort ();
10295 }
1af1dd51 10296#undef ARM_SET_FEATURES
c0c468d5
TP		 10297
10298 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
10299 and thus on bfd_mach_arm_XXX value. Therefore for a given
10300 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
10301 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
0313a2b8
NC		 10302}
10303
10304
58efb6c0
NC		 10305/* NOTE: There are no checks in these routines that
10306 the relevant number of data bytes exist. */
baf0cc5e 10307
58efb6c0 10308static int
4a5329c6 10309print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 10310{
c19d1205
ZW		 10311 unsigned char b[4];
10312 long given;
10313 int status;
e821645d 10314 int is_thumb = FALSE;
b0e28b39 10315 int is_data = FALSE;
bd2e2557 10316 int little_code;
e821645d 10317 unsigned int size = 4;
4a5329c6 10318 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 10319 bfd_boolean found = FALSE;
b0e28b39 10320 struct arm_private_data *private_data;
58efb6c0 10321
dd92f639
NC		 10322 if (info->disassembler_options)
10323 {
65b48a81 10324 parse_arm_disassembler_options (info->disassembler_options);
b34976b6 10325
58efb6c0 10326 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 10327 info->disassembler_options = NULL;
10328 }
b34976b6 10329
0313a2b8
NC		 10330 /* PR 10288: Control which instructions will be disassembled. */
10331 if (info->private_data == NULL)
10332 {
b0e28b39 10333 static struct arm_private_data private;
0313a2b8
NC		 10334
10335 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
10336 /* If the user did not use the -m command line switch then default to
10337 disassembling all types of ARM instruction.
43e65147 10338
0313a2b8
NC		 10339 The info->mach value has to be ignored as this will be based on
10340 the default archictecture for the target and/or hints in the notes
10341 section, but it will never be greater than the current largest arm
10342 machine value (iWMMXt2), which is only equivalent to the V5TE
10343 architecture. ARM architectures have advanced beyond the machine
10344 value encoding, and these newer architectures would be ignored if
10345 the machine value was used.
10346
10347 Ie the -m switch is used to restrict which instructions will be
10348 disassembled. If it is necessary to use the -m switch to tell
10349 objdump that an ARM binary is being disassembled, eg because the
10350 input is a raw binary file, but it is also desired to disassemble
10351 all ARM instructions then use "-marm". This will select the
10352 "unknown" arm architecture which is compatible with any ARM
10353 instruction. */
10354 info->mach = bfd_mach_arm_unknown;
10355
10356 /* Compute the architecture bitmask from the machine number.
10357 Note: This assumes that the machine number will not change
10358 during disassembly.... */
b0e28b39 10359 select_arm_features (info->mach, & private.features);
0313a2b8 10360
1fbaefec
PB		 10361 private.last_mapping_sym = -1;
10362 private.last_mapping_addr = 0;
796d6298 10363 private.last_stop_offset = 0;
b0e28b39
DJ		 10364
10365 info->private_data = & private;
0313a2b8 10366 }
b0e28b39
DJ		 10367
10368 private_data = info->private_data;
10369
bd2e2557
SS		 10370 /* Decide if our code is going to be little-endian, despite what the
10371 function argument might say. */
10372 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
10373
b0e28b39
DJ		 10374 /* For ELF, consult the symbol table to determine what kind of code
10375 or data we have. */
8977d4b2 10376 if (info->symtab_size != 0
e821645d
DJ		 10377 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
10378 {
10379 bfd_vma addr;
796d6298 10380 int n;
e821645d 10381 int last_sym = -1;
b0e28b39 10382 enum map_type type = MAP_ARM;
e821645d 10383
796d6298
TC		 10384 found = mapping_symbol_for_insn (pc, info, &type);
10385 last_sym = private_data->last_mapping_sym;
e821645d 10386
1fbaefec
PB		 10387 is_thumb = (private_data->last_type == MAP_THUMB);
10388 is_data = (private_data->last_type == MAP_DATA);
b34976b6 10389
e821645d
DJ		 10390 /* Look a little bit ahead to see if we should print out
10391 two or four bytes of data. If there's a symbol,
10392 mapping or otherwise, after two bytes then don't
10393 print more. */
10394 if (is_data)
10395 {
10396 size = 4 - (pc & 3);
10397 for (n = last_sym + 1; n < info->symtab_size; n++)
10398 {
10399 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 10400 if (addr > pc
10401 && (info->section == NULL
10402 || info->section == info->symtab[n]->section))
e821645d
DJ		 10403 {
10404 if (addr - pc < size)
10405 size = addr - pc;
10406 break;
10407 }
10408 }
10409 /* If the next symbol is after three bytes, we need to
10410 print only part of the data, so that we can use either
10411 .byte or .short. */
10412 if (size == 3)
10413 size = (pc & 1) ? 1 : 2;
10414 }
10415 }
10416
10417 if (info->symbols != NULL)
252b5132 10418 {
5876e06d
NC		 10419 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
10420 {
2f0ca46a 10421 coff_symbol_type * cs;
b34976b6 10422
5876e06d
NC		 10423 cs = coffsymbol (*info->symbols);
10424 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
10425 || cs->native->u.syment.n_sclass == C_THUMBSTAT
10426 || cs->native->u.syment.n_sclass == C_THUMBLABEL
10427 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
10428 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
10429 }
e821645d
DJ		 10430 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
10431 && !found)
5876e06d 10432 {
2087ad84
PB		 10433 /* If no mapping symbol has been found then fall back to the type
10434 of the function symbol. */
e821645d
DJ		 10435 elf_symbol_type * es;
10436 unsigned int type;
2087ad84 10437
e821645d
DJ		 10438 es = *(elf_symbol_type **)(info->symbols);
10439 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 10440
39d911fc
TP		 10441 is_thumb =
10442 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
10443 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
5876e06d 10444 }
e49d43ff
TG		 10445 else if (bfd_asymbol_flavour (*info->symbols)
10446 == bfd_target_mach_o_flavour)
10447 {
10448 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
10449
10450 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
10451 }
5876e06d 10452 }
b34976b6 10453
e821645d
DJ		 10454 if (force_thumb)
10455 is_thumb = TRUE;
10456
b8f9ee44
CL		 10457 if (is_data)
10458 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
10459 else
10460 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
10461
c19d1205 10462 info->bytes_per_line = 4;
252b5132 10463
1316c8b3
NC		 10464 /* PR 10263: Disassemble data if requested to do so by the user. */
10465 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 10466 {
10467 int i;
10468
1316c8b3 10469 /* Size was already set above. */
e821645d
DJ		 10470 info->bytes_per_chunk = size;
10471 printer = print_insn_data;
10472
fe56b6ce 10473 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 10474 given = 0;
10475 if (little)
10476 for (i = size - 1; i >= 0; i--)
10477 given = b[i] | (given << 8);
10478 else
10479 for (i = 0; i < (int) size; i++)
10480 given = b[i] | (given << 8);
10481 }
10482 else if (!is_thumb)
252b5132 10483 {
c19d1205
ZW		 10484 /* In ARM mode endianness is a straightforward issue: the instruction
10485 is four bytes long and is either ordered 0123 or 3210. */
10486 printer = print_insn_arm;
10487 info->bytes_per_chunk = 4;
4a5329c6 10488 size = 4;
c19d1205 10489
0313a2b8 10490 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 10491 if (little_code)
c19d1205
ZW		 10492 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
10493 else
10494 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
252b5132 10495 }
58efb6c0 10496 else
252b5132 10497 {
c19d1205
ZW		 10498 /* In Thumb mode we have the additional wrinkle of two
10499 instruction lengths. Fortunately, the bits that determine
10500 the length of the current instruction are always to be found
10501 in the first two bytes. */
4a5329c6 10502 printer = print_insn_thumb16;
c19d1205 10503 info->bytes_per_chunk = 2;
4a5329c6
ZW		 10504 size = 2;
10505
fe56b6ce 10506 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 10507 if (little_code)
9a2ff3f5
AM		 10508 given = (b[0]) | (b[1] << 8);
10509 else
10510 given = (b[1]) | (b[0] << 8);
10511
c19d1205 10512 if (!status)
252b5132 10513 {
c19d1205
ZW		 10514 /* These bit patterns signal a four-byte Thumb
10515 instruction. */
10516 if ((given & 0xF800) == 0xF800
10517 || (given & 0xF800) == 0xF000
10518 || (given & 0xF800) == 0xE800)
252b5132 10519 {
0313a2b8 10520 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 10521 if (little_code)
c19d1205 10522 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 10523 else
c19d1205
ZW		 10524 given = (b[1]) | (b[0] << 8) | (given << 16);
10525
10526 printer = print_insn_thumb32;
4a5329c6 10527 size = 4;
252b5132 10528 }
252b5132 10529 }
c22aaad1
PB		 10530
10531 if (ifthen_address != pc)
0313a2b8 10532 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 10533
10534 if (ifthen_state)
10535 {
10536 if ((ifthen_state & 0xf) == 0x8)
10537 ifthen_next_state = 0;
10538 else
10539 ifthen_next_state = (ifthen_state & 0xe0)
10540 | ((ifthen_state & 0xf) << 1);
10541 }
252b5132 10542 }
b34976b6 10543
c19d1205
ZW		 10544 if (status)
10545 {
10546 info->memory_error_func (status, pc, info);
10547 return -1;
10548 }
6a56ec7e
NC		 10549 if (info->flags & INSN_HAS_RELOC)
10550 /* If the instruction has a reloc associated with it, then
10551 the offset field in the instruction will actually be the
10552 addend for the reloc. (We are using REL type relocs).
10553 In such cases, we can ignore the pc when computing
10554 addresses, since the addend is not currently pc-relative. */
10555 pc = 0;
b34976b6 10556
4a5329c6 10557 printer (pc, info, given);
c22aaad1
PB		 10558
10559 if (is_thumb)
10560 {
10561 ifthen_state = ifthen_next_state;
10562 ifthen_address += size;
10563 }
4a5329c6 10564 return size;
252b5132
RH		 10565}
10566
10567int
4a5329c6 10568print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 10569{
bd2e2557
SS		 10570 /* Detect BE8-ness and record it in the disassembler info. */
10571 if (info->flavour == bfd_target_elf_flavour
10572 && info->section != NULL
10573 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
10574 info->endian_code = BFD_ENDIAN_LITTLE;
10575
b34976b6 10576 return print_insn (pc, info, FALSE);
58efb6c0 10577}
01c7f630 10578
58efb6c0 10579int
4a5329c6 10580print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 10581{
b34976b6 10582 return print_insn (pc, info, TRUE);
58efb6c0 10583}
252b5132 10584
471b9d15 10585const disasm_options_and_args_t *
65b48a81
PB		 10586disassembler_options_arm (void)
10587{
471b9d15 10588 static disasm_options_and_args_t *opts_and_args;
65b48a81 10589
471b9d15 10590 if (opts_and_args == NULL)
65b48a81 10591 {
471b9d15 10592 disasm_options_t *opts;
65b48a81 10593 unsigned int i;
471b9d15
MR		 10594
10595 opts_and_args = XNEW (disasm_options_and_args_t);
10596 opts_and_args->args = NULL;
10597
10598 opts = &opts_and_args->options;
65b48a81
PB		 10599 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
10600 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
471b9d15 10601 opts->arg = NULL;
65b48a81
PB		 10602 for (i = 0; i < NUM_ARM_OPTIONS; i++)
10603 {
10604 opts->name[i] = regnames[i].name;
10605 if (regnames[i].description != NULL)
10606 opts->description[i] = _(regnames[i].description);
10607 else
10608 opts->description[i] = NULL;
10609 }
10610 /* The array we return must be NULL terminated. */
10611 opts->name[i] = NULL;
10612 opts->description[i] = NULL;
10613 }
10614
471b9d15 10615 return opts_and_args;
65b48a81
PB		 10616}
10617
58efb6c0 10618void
4a5329c6 10619print_arm_disassembler_options (FILE *stream)
58efb6c0 10620{
65b48a81 10621 unsigned int i, max_len = 0;
58efb6c0
NC		 10622 fprintf (stream, _("\n\
10623The following ARM specific disassembler options are supported for use with\n\
10624the -M switch:\n"));
b34976b6 10625
65b48a81
PB		 10626 for (i = 0; i < NUM_ARM_OPTIONS; i++)
10627 {
10628 unsigned int len = strlen (regnames[i].name);
10629 if (max_len < len)
10630 max_len = len;
10631 }
58efb6c0 10632
65b48a81
PB		 10633 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
10634 fprintf (stream, " %s%*c %s\n",
10635 regnames[i].name,
10636 (int)(max_len - strlen (regnames[i].name)), ' ',
10637 _(regnames[i].description));
252b5132 10638}
GDB Binutils - Deliverables
This page took 2.621835 seconds and 4 git commands to generate.