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document --disassembler-options=force-thumb
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
CommitLineData
252b5132 1/* Instruction printing code for the ARM
dd92f639 2 Copyright (C) 1994, 95, 96, 97, 98, 1999 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
6This file is part of libopcodes.
7
8This program is free software; you can redistribute it and/or modify it under
9the terms of the GNU General Public License as published by the Free
10Software Foundation; either version 2 of the License, or (at your option)
11any later version.
12
13This program is distributed in the hope that it will be useful, but WITHOUT
14ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16more details.
17
18You should have received a copy of the GNU General Public License
19along with this program; if not, write to the Free Software
20Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21
cb6a5892 22#include "sysdep.h"
252b5132
RH		 23#include "dis-asm.h"
24#define DEFINE_TABLE
25#include "arm-opc.h"
26#include "coff/internal.h"
27#include "libcoff.h"
28#include "opintl.h"
29
30/* FIXME: This shouldn't be done here */
31#include "elf-bfd.h"
32#include "elf/internal.h"
33#include "elf/arm.h"
34
5876e06d 35static char * arm_conditional[] =
252b5132
RH		 36{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
37 "hi", "ls", "ge", "lt", "gt", "le", "", "nv"};
38
5876e06d 39static char * arm_regnames_raw[] =
252b5132 40{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
dd92f639
NC		 41 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"};
42
5876e06d 43static char * arm_regnames_standard[] =
dd92f639
NC		 44{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
45 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc"};
46
5876e06d 47static char * arm_regnames_apcs[] =
dd92f639
NC		 48{"a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4",
49 "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc"};
50
51/* Choose which register name set to use. */
5876e06d 52static char ** arm_regnames = arm_regnames_standard;
252b5132 53
5876e06d 54static char * arm_fp_const[] =
252b5132
RH		 55{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
56
5876e06d 57static char * arm_shift[] =
252b5132
RH		 58{"lsl", "lsr", "asr", "ror"};
59
5876e06d
NC		 60static int print_insn_arm
61 PARAMS ((bfd_vma, struct disassemble_info *, long));
252b5132
RH		 62
63static void
64arm_decode_shift (given, func, stream)
65 long given;
66 fprintf_ftype func;
5876e06d 67 void * stream;
252b5132
RH		 68{
69 func (stream, "%s", arm_regnames[given & 0xf]);
5876e06d 70
252b5132
RH		 71 if ((given & 0xff0) != 0)
72 {
73 if ((given & 0x10) == 0)
74 {
75 int amount = (given & 0xf80) >> 7;
76 int shift = (given & 0x60) >> 5;
5876e06d 77
252b5132
RH		 78 if (amount == 0)
79 {
80 if (shift == 3)
81 {
82 func (stream, ", rrx");
83 return;
84 }
5876e06d 85
252b5132
RH		 86 amount = 32;
87 }
5876e06d 88
252b5132
RH		 89 func (stream, ", %s #%d", arm_shift[shift], amount);
90 }
91 else
92 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
93 arm_regnames[(given & 0xf00) >> 8]);
94 }
95}
96
97/* Print one instruction from PC on INFO->STREAM.
98 Return the size of the instruction (always 4 on ARM). */
99
100static int
101print_insn_arm (pc, info, given)
5876e06d
NC		 102 bfd_vma pc;
103 struct disassemble_info * info;
104 long given;
252b5132
RH		 105{
106 struct arm_opcode * insn;
107 void * stream = info->stream;
108 fprintf_ftype func = info->fprintf_func;
109
110 for (insn = arm_opcodes; insn->assembler; insn++)
111 {
112 if ((given & insn->mask) == insn->value)
113 {
114 char * c;
115
116 for (c = insn->assembler; *c; c++)
117 {
118 if (*c == '%')
119 {
120 switch (*++c)
121 {
122 case '%':
123 func (stream, "%%");
124 break;
125
126 case 'a':
127 if (((given & 0x000f0000) == 0x000f0000)
128 && ((given & 0x02000000) == 0))
129 {
130 int offset = given & 0xfff;
131
132 func (stream, "[pc");
133
134 if (given & 0x01000000)
135 {
136 if ((given & 0x00800000) == 0)
137 offset = - offset;
138
139 /* pre-indexed */
140 func (stream, ", #%x]", offset);
141
142 offset += pc + 8;
143
144 /* Cope with the possibility of write-back being used.
145 Probably a very dangerous thing for the programmer
146 to do, but who are we to argue ? */
147 if (given & 0x00200000)
148 func (stream, "!");
149 }
150 else
151 {
152 /* post indexed */
153 func (stream, "], #%x", offset);
154
155 offset = pc + 8; /* ie ignore the offset */
156 }
157
158 func (stream, "\t; ");
159 info->print_address_func (offset, info);
160 }
161 else
162 {
163 func (stream, "[%s",
164 arm_regnames[(given >> 16) & 0xf]);
165 if ((given & 0x01000000) != 0)
166 {
167 if ((given & 0x02000000) == 0)
168 {
169 int offset = given & 0xfff;
170 if (offset)
171 func (stream, ", %s#%d",
172 (((given & 0x00800000) == 0)
173 ? "-" : ""), offset);
174 }
175 else
176 {
177 func (stream, ", %s",
178 (((given & 0x00800000) == 0)
179 ? "-" : ""));
180 arm_decode_shift (given, func, stream);
181 }
182
183 func (stream, "]%s",
184 ((given & 0x00200000) != 0) ? "!" : "");
185 }
186 else
187 {
188 if ((given & 0x02000000) == 0)
189 {
190 int offset = given & 0xfff;
191 if (offset)
192 func (stream, "], %s#%d",
193 (((given & 0x00800000) == 0)
194 ? "-" : ""), offset);
195 else
196 func (stream, "]");
197 }
198 else
199 {
200 func (stream, "], %s",
201 (((given & 0x00800000) == 0)
202 ? "-" : ""));
203 arm_decode_shift (given, func, stream);
204 }
205 }
206 }
207 break;
208
209 case 's':
210 if ((given & 0x004f0000) == 0x004f0000)
211 {
212 /* PC relative with immediate offset */
213 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
886796f9 214
252b5132
RH		 215 if ((given & 0x00800000) == 0)
216 offset = -offset;
886796f9
NC		 217
218 func (stream, "[pc, #%x]\t; ", offset);
219
252b5132
RH		 220 (*info->print_address_func)
221 (offset + pc + 8, info);
222 }
223 else
224 {
225 func (stream, "[%s",
226 arm_regnames[(given >> 16) & 0xf]);
227 if ((given & 0x01000000) != 0)
228 {
229 /* pre-indexed */
230 if ((given & 0x00400000) == 0x00400000)
231 {
232 /* immediate */
233 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
234 if (offset)
235 func (stream, ", %s#%d",
236 (((given & 0x00800000) == 0)
237 ? "-" : ""), offset);
238 }
239 else
240 {
241 /* register */
242 func (stream, ", %s%s",
243 (((given & 0x00800000) == 0)
244 ? "-" : ""),
245 arm_regnames[given & 0xf]);
246 }
247
248 func (stream, "]%s",
249 ((given & 0x00200000) != 0) ? "!" : "");
250 }
251 else
252 {
253 /* post-indexed */
254 if ((given & 0x00400000) == 0x00400000)
255 {
256 /* immediate */
257 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
258 if (offset)
259 func (stream, "], %s#%d",
260 (((given & 0x00800000) == 0)
261 ? "-" : ""), offset);
262 else
263 func (stream, "]");
264 }
265 else
266 {
267 /* register */
268 func (stream, "], %s%s",
269 (((given & 0x00800000) == 0)
270 ? "-" : ""),
271 arm_regnames[given & 0xf]);
272 }
273 }
274 }
275 break;
276
277 case 'b':
278 (*info->print_address_func)
279 (BDISP (given) * 4 + pc + 8, info);
280 break;
281
282 case 'c':
283 func (stream, "%s",
284 arm_conditional [(given >> 28) & 0xf]);
285 break;
286
287 case 'm':
288 {
289 int started = 0;
290 int reg;
291
292 func (stream, "{");
293 for (reg = 0; reg < 16; reg++)
294 if ((given & (1 << reg)) != 0)
295 {
296 if (started)
297 func (stream, ", ");
298 started = 1;
299 func (stream, "%s", arm_regnames[reg]);
300 }
301 func (stream, "}");
302 }
303 break;
304
305 case 'o':
306 if ((given & 0x02000000) != 0)
307 {
308 int rotate = (given & 0xf00) >> 7;
309 int immed = (given & 0xff);
9f20bbfd
NC		 310 immed = (((immed << (32 - rotate))
311 | (immed >> rotate)) & 0xffffffff);
312 func (stream, "#%d\t; 0x%x", immed, immed);
252b5132
RH		 313 }
314 else
315 arm_decode_shift (given, func, stream);
316 break;
317
318 case 'p':
319 if ((given & 0x0000f000) == 0x0000f000)
320 func (stream, "p");
321 break;
322
323 case 't':
324 if ((given & 0x01200000) == 0x00200000)
325 func (stream, "t");
326 break;
327
328 case 'h':
329 if ((given & 0x00000020) == 0x00000020)
330 func (stream, "h");
331 else
332 func (stream, "b");
333 break;
334
335 case 'A':
336 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
337 if ((given & 0x01000000) != 0)
338 {
339 int offset = given & 0xff;
340 if (offset)
341 func (stream, ", %s#%d]%s",
342 ((given & 0x00800000) == 0 ? "-" : ""),
343 offset * 4,
344 ((given & 0x00200000) != 0 ? "!" : ""));
345 else
346 func (stream, "]");
347 }
348 else
349 {
350 int offset = given & 0xff;
351 if (offset)
352 func (stream, "], %s#%d",
353 ((given & 0x00800000) == 0 ? "-" : ""),
354 offset * 4);
355 else
356 func (stream, "]");
357 }
358 break;
359
360 case 'C':
361 switch (given & 0x00090000)
362 {
363 default:
364 func (stream, "_???");
365 break;
366 case 0x90000:
367 func (stream, "_all");
368 break;
369 case 0x10000:
370 func (stream, "_ctl");
371 break;
372 case 0x80000:
373 func (stream, "_flg");
374 break;
375 }
376 break;
377
378 case 'F':
379 switch (given & 0x00408000)
380 {
381 case 0:
382 func (stream, "4");
383 break;
384 case 0x8000:
385 func (stream, "1");
386 break;
387 case 0x00400000:
388 func (stream, "2");
389 break;
390 default:
391 func (stream, "3");
392 }
393 break;
394
395 case 'P':
396 switch (given & 0x00080080)
397 {
398 case 0:
399 func (stream, "s");
400 break;
401 case 0x80:
402 func (stream, "d");
403 break;
404 case 0x00080000:
405 func (stream, "e");
406 break;
407 default:
408 func (stream, _("<illegal precision>"));
409 break;
410 }
411 break;
412 case 'Q':
413 switch (given & 0x00408000)
414 {
415 case 0:
416 func (stream, "s");
417 break;
418 case 0x8000:
419 func (stream, "d");
420 break;
421 case 0x00400000:
422 func (stream, "e");
423 break;
424 default:
425 func (stream, "p");
426 break;
427 }
428 break;
429 case 'R':
430 switch (given & 0x60)
431 {
432 case 0:
433 break;
434 case 0x20:
435 func (stream, "p");
436 break;
437 case 0x40:
438 func (stream, "m");
439 break;
440 default:
441 func (stream, "z");
442 break;
443 }
444 break;
445
446 case '0': case '1': case '2': case '3': case '4':
447 case '5': case '6': case '7': case '8': case '9':
448 {
449 int bitstart = *c++ - '0';
450 int bitend = 0;
451 while (*c >= '0' && *c <= '9')
452 bitstart = (bitstart * 10) + *c++ - '0';
453
454 switch (*c)
455 {
456 case '-':
457 c++;
458 while (*c >= '0' && *c <= '9')
459 bitend = (bitend * 10) + *c++ - '0';
460 if (!bitend)
461 abort ();
462 switch (*c)
463 {
464 case 'r':
465 {
466 long reg;
467 reg = given >> bitstart;
468 reg &= (2 << (bitend - bitstart)) - 1;
469 func (stream, "%s", arm_regnames[reg]);
470 }
471 break;
472 case 'd':
473 {
474 long reg;
475 reg = given >> bitstart;
476 reg &= (2 << (bitend - bitstart)) - 1;
477 func (stream, "%d", reg);
478 }
479 break;
480 case 'x':
481 {
482 long reg;
483 reg = given >> bitstart;
484 reg &= (2 << (bitend - bitstart)) - 1;
485 func (stream, "0x%08x", reg);
5876e06d
NC		 486
487 /* Some SWI instructions have special meanings. */
488 if ((given & 0x0fffffff) == 0x0FF00000)
489 func (stream, "\t; IMB");
490 else if ((given & 0x0fffffff) == 0x0FF00001)
491 func (stream, "\t; IMBRange");
252b5132
RH		 492 }
493 break;
cfbd315c
DL		 494 case 'X':
495 {
496 long reg;
497 reg = given >> bitstart;
498 reg &= (2 << (bitend - bitstart)) - 1;
499 func (stream, "%01x", reg & 0xf);
500 }
501 break;
252b5132
RH		 502 case 'f':
503 {
504 long reg;
505 reg = given >> bitstart;
506 reg &= (2 << (bitend - bitstart)) - 1;
507 if (reg > 7)
508 func (stream, "#%s",
509 arm_fp_const[reg & 7]);
510 else
511 func (stream, "f%d", reg);
512 }
513 break;
514 default:
515 abort ();
516 }
517 break;
518 case '`':
519 c++;
520 if ((given & (1 << bitstart)) == 0)
521 func (stream, "%c", *c);
522 break;
523 case '\'':
524 c++;
525 if ((given & (1 << bitstart)) != 0)
526 func (stream, "%c", *c);
527 break;
528 case '?':
529 ++c;
530 if ((given & (1 << bitstart)) != 0)
531 func (stream, "%c", *c++);
532 else
533 func (stream, "%c", *++c);
534 break;
535 default:
536 abort ();
537 }
538 break;
539
540 default:
541 abort ();
542 }
543 }
544 }
545 else
546 func (stream, "%c", *c);
547 }
548 return 4;
549 }
550 }
551 abort ();
552}
553
554/* Print one instruction from PC on INFO->STREAM.
555 Return the size of the instruction. */
556
557static int
558print_insn_thumb (pc, info, given)
5876e06d
NC		 559 bfd_vma pc;
560 struct disassemble_info * info;
561 long given;
252b5132 562{
5876e06d
NC		 563 struct thumb_opcode * insn;
564 void * stream = info->stream;
565 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 566
567 for (insn = thumb_opcodes; insn->assembler; insn++)
568 {
569 if ((given & insn->mask) == insn->value)
570 {
5876e06d 571 char * c = insn->assembler;
252b5132
RH		 572
573 /* Special processing for Thumb 2 instruction BL sequence: */
574 if (!*c) /* check for empty (not NULL) assembler string */
575 {
576 info->bytes_per_chunk = 4;
577 info->bytes_per_line = 4;
578
579 func (stream, "%04x\tbl\t", given & 0xffff);
580 (*info->print_address_func)
581 (BDISP23 (given) * 2 + pc + 4, info);
582 return 4;
583 }
584 else
585 {
586 info->bytes_per_chunk = 2;
587 info->bytes_per_line = 4;
588
589 given &= 0xffff;
590 func (stream, "%04x\t", given);
5876e06d 591
252b5132
RH		 592 for (; *c; c++)
593 {
594 if (*c == '%')
595 {
596 int domaskpc = 0;
597 int domasklr = 0;
5876e06d 598
252b5132
RH		 599 switch (*++c)
600 {
601 case '%':
602 func (stream, "%%");
603 break;
604
605 case 'S':
606 {
607 long reg;
608 reg = (given >> 3) & 0x7;
609 if (given & (1 << 6))
610 reg += 8;
611 func (stream, "%s", arm_regnames[reg]);
612 }
613 break;
614
615 case 'D':
616 {
617 long reg;
5876e06d 618
252b5132
RH		 619 reg = given & 0x7;
620 if (given & (1 << 7))
621 reg += 8;
622 func (stream, "%s", arm_regnames[reg]);
623 }
624 break;
625
626 case 'T':
627 func (stream, "%s",
628 arm_conditional [(given >> 8) & 0xf]);
629 break;
630
631 case 'N':
632 if (given & (1 << 8))
633 domasklr = 1;
634 /* fall through */
635 case 'O':
636 if (*c == 'O' && (given & (1 << 8)))
637 domaskpc = 1;
638 /* fall through */
639 case 'M':
640 {
641 int started = 0;
642 int reg;
5876e06d 643
252b5132
RH		 644 func (stream, "{");
645 /* It would be nice if we could spot
646 ranges, and generate the rS-rE format: */
647 for (reg = 0; (reg < 8); reg++)
648 if ((given & (1 << reg)) != 0)
649 {
650 if (started)
651 func (stream, ", ");
652 started = 1;
653 func (stream, "%s", arm_regnames[reg]);
654 }
655
656 if (domasklr)
657 {
658 if (started)
659 func (stream, ", ");
660 started = 1;
661 func (stream, "lr");
662 }
663
664 if (domaskpc)
665 {
666 if (started)
667 func (stream, ", ");
668 func (stream, "pc");
669 }
670
671 func (stream, "}");
672 }
673 break;
674
675
676 case '0': case '1': case '2': case '3': case '4':
677 case '5': case '6': case '7': case '8': case '9':
678 {
679 int bitstart = *c++ - '0';
680 int bitend = 0;
5876e06d 681
252b5132
RH		 682 while (*c >= '0' && *c <= '9')
683 bitstart = (bitstart * 10) + *c++ - '0';
684
685 switch (*c)
686 {
687 case '-':
688 {
689 long reg;
5876e06d 690
252b5132
RH		 691 c++;
692 while (*c >= '0' && *c <= '9')
693 bitend = (bitend * 10) + *c++ - '0';
694 if (!bitend)
695 abort ();
696 reg = given >> bitstart;
697 reg &= (2 << (bitend - bitstart)) - 1;
698 switch (*c)
699 {
700 case 'r':
701 func (stream, "%s", arm_regnames[reg]);
702 break;
703
704 case 'd':
705 func (stream, "%d", reg);
706 break;
707
708 case 'H':
709 func (stream, "%d", reg << 1);
710 break;
711
712 case 'W':
713 func (stream, "%d", reg << 2);
714 break;
715
716 case 'a':
717 /* PC-relative address -- the bottom two
718 bits of the address are dropped before
719 the calculation. */
720 info->print_address_func
721 (((pc + 4) & ~3) + (reg << 2), info);
722 break;
723
724 case 'x':
725 func (stream, "0x%04x", reg);
726 break;
727
728 case 'I':
729 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
730 func (stream, "%d", reg);
731 break;
732
733 case 'B':
734 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
735 (*info->print_address_func)
736 (reg * 2 + pc + 4, info);
737 break;
738
739 default:
5876e06d 740 abort ();
252b5132
RH		 741 }
742 }
743 break;
744
745 case '\'':
746 c++;
747 if ((given & (1 << bitstart)) != 0)
748 func (stream, "%c", *c);
749 break;
750
751 case '?':
752 ++c;
753 if ((given & (1 << bitstart)) != 0)
754 func (stream, "%c", *c++);
755 else
756 func (stream, "%c", *++c);
757 break;
758
759 default:
5876e06d 760 abort ();
252b5132
RH		 761 }
762 }
763 break;
764
765 default:
766 abort ();
767 }
768 }
769 else
770 func (stream, "%c", *c);
771 }
772 }
773 return 2;
774 }
775 }
776
777 /* no match */
778 abort ();
779}
780
dd92f639
NC		 781/* Select a different register name set.
782 Returns true if the name set selected is the APCS name set. */
783int
784arm_toggle_regnames ()
785{
786 if (arm_regnames == arm_regnames_standard)
787 arm_regnames = arm_regnames_apcs;
788 else
789 arm_regnames = arm_regnames_standard;
790
791 return arm_regnames == arm_regnames_apcs;
792}
793
794static void
795parse_disassembler_options (options)
796 char * options;
797{
798 if (options == NULL)
799 return;
800
801 if (strncmp (options, "reg-names-", 10) == 0)
802 {
803 options += 10;
804
805 if (strcmp (options, "std") == 0)
806 arm_regnames = arm_regnames_standard;
807 else if (strcmp (options, "apcs") == 0)
808 arm_regnames = arm_regnames_apcs;
809 else if (strcmp (options, "raw") == 0)
810 arm_regnames = arm_regnames_raw;
811 else
812 fprintf (stderr, "Unrecognised register name set: %s\n", options);
813 }
814 else
815 fprintf (stderr, "Unrecognised disassembler option: %s\n", options);
816
817 return;
818}
819
252b5132
RH		 820/* NOTE: There are no checks in these routines that the relevant number of data bytes exist */
821
822int
823print_insn_big_arm (pc, info)
824 bfd_vma pc;
5876e06d 825 struct disassemble_info * info;
252b5132
RH		 826{
827 unsigned char b[4];
828 long given;
829 int status;
5876e06d
NC		 830 coff_symbol_type * cs;
831 elf_symbol_type * es;
252b5132
RH		 832 int is_thumb;
833
dd92f639
NC		 834 if (info->disassembler_options)
835 {
836 parse_disassembler_options (info->disassembler_options);
837
838 /* To avoid repeated parsing of this option, we remove it here. */
839 info->disassembler_options = NULL;
840 }
841
252b5132
RH		 842 is_thumb = false;
843 if (info->symbols != NULL)
844 {
5876e06d
NC		 845 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
846 {
847 cs = coffsymbol (*info->symbols);
848 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
849 || cs->native->u.syment.n_sclass == C_THUMBSTAT
850 || cs->native->u.syment.n_sclass == C_THUMBLABEL
851 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
852 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
853 }
854 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour)
855 {
856 es = *(elf_symbol_type **)(info->symbols);
857 is_thumb = ELF_ST_TYPE (es->internal_elf_sym.st_info) ==
858 STT_ARM_TFUNC;
859 }
860 }
252b5132
RH		 861
862 info->bytes_per_chunk = 4;
863 info->display_endian = BFD_ENDIAN_BIG;
864
865 /* Always fetch word aligned values. */
866
867 status = (*info->read_memory_func) (pc & ~ 0x3, (bfd_byte *) &b[0], 4, info);
868 if (status != 0)
869 {
870 (*info->memory_error_func) (status, pc, info);
871 return -1;
872 }
873
874 if (is_thumb)
875 {
876 if (pc & 0x2)
877 {
878 given = (b[2] << 8) | b[3];
879
880 status = info->read_memory_func ((pc + 4) & ~ 0x3, (bfd_byte *) b, 4, info);
881 if (status != 0)
882 {
883 info->memory_error_func (status, pc + 4, info);
884 return -1;
885 }
886
887 given |= (b[0] << 24) | (b[1] << 16);
888 }
889 else
5876e06d 890 given = (b[0] << 8) | b[1] | (b[2] << 24) | (b[3] << 16);
252b5132
RH		 891 }
892 else
5876e06d 893 given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]);
252b5132
RH		 894
895 if (is_thumb)
5876e06d 896 status = print_insn_thumb (pc, info, given);
252b5132 897 else
5876e06d 898 status = print_insn_arm (pc, info, given);
252b5132
RH		 899
900 return status;
901}
902
903int
904print_insn_little_arm (pc, info)
905 bfd_vma pc;
906 struct disassemble_info * info;
907{
908 unsigned char b[4];
909 long given;
910 int status;
5876e06d
NC		 911 coff_symbol_type * cs;
912 elf_symbol_type * es;
252b5132
RH		 913 int is_thumb;
914
dd92f639
NC		 915 if (info->disassembler_options)
916 {
917 parse_disassembler_options (info->disassembler_options);
918
919 /* To avoid repeated parsing of this option, we remove it here. */
920 info->disassembler_options = NULL;
921 }
922
252b5132 923 is_thumb = false;
5876e06d 924
252b5132
RH		 925 if (info->symbols != NULL)
926 {
5876e06d
NC		 927 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
928 {
929 cs = coffsymbol (*info->symbols);
930 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
931 || cs->native->u.syment.n_sclass == C_THUMBSTAT
932 || cs->native->u.syment.n_sclass == C_THUMBLABEL
933 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
934 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
935 }
936 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour)
937 {
938 es = *(elf_symbol_type **)(info->symbols);
939 is_thumb = ELF_ST_TYPE (es->internal_elf_sym.st_info) ==
940 STT_ARM_TFUNC;
941 }
942 }
252b5132 943
252b5132
RH		 944 info->bytes_per_chunk = 4;
945 info->display_endian = BFD_ENDIAN_LITTLE;
946
947 status = (*info->read_memory_func) (pc, (bfd_byte *) &b[0], 4, info);
948 if (status != 0 && is_thumb)
949 {
950 info->bytes_per_chunk = 2;
951
952 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
953 b[3] = b[2] = 0;
954 }
955 if (status != 0)
956 {
957 (*info->memory_error_func) (status, pc, info);
958 return -1;
959 }
960
961 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
962
963 if (is_thumb)
5876e06d 964 status = print_insn_thumb (pc, info, given);
252b5132 965 else
5876e06d 966 status = print_insn_arm (pc, info, given);
252b5132
RH		 967
968 return status;
969}
GDB Binutils - Deliverables
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