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[ARC] Dynamic relocs verification for dynindx == -1.
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
CommitLineData
252b5132 1/* Instruction printing code for the ARM
6f2750fe 2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
2fbad815 24
252b5132 25#include "dis-asm.h"
2fbad815 26#include "opcode/arm.h"
252b5132 27#include "opintl.h"
31e0f3cd 28#include "safe-ctype.h"
0dbde4cf 29#include "floatformat.h"
252b5132 30
baf0cc5e 31/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 32#include "coff/internal.h"
33#include "libcoff.h"
252b5132
RH		 34#include "elf-bfd.h"
35#include "elf/internal.h"
36#include "elf/arm.h"
e49d43ff 37#include "mach-o.h"
252b5132 38
6b5d3a4d 39/* FIXME: Belongs in global header. */
01c7f630 40#ifndef strneq
58efb6c0
NC		 41#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
42#endif
43
44#ifndef NUM_ELEM
45#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
01c7f630
NC		 46#endif
47
1fbaefec
PB		 48/* Cached mapping symbol state. */
49enum map_type
50{
51 MAP_ARM,
52 MAP_THUMB,
53 MAP_DATA
54};
55
b0e28b39
DJ		 56struct arm_private_data
57{
58 /* The features to use when disassembling optional instructions. */
59 arm_feature_set features;
60
61 /* Whether any mapping symbols are present in the provided symbol
62 table. -1 if we do not know yet, otherwise 0 or 1. */
63 int has_mapping_symbols;
1fbaefec
PB		 64
65 /* Track the last type (although this doesn't seem to be useful) */
66 enum map_type last_type;
67
68 /* Tracking symbol table information */
69 int last_mapping_sym;
70 bfd_vma last_mapping_addr;
b0e28b39
DJ		 71};
72
6b5d3a4d
ZW		 73struct opcode32
74{
823d2571
TG		 75 arm_feature_set arch; /* Architecture defining this insn. */
76 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 77 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 78 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 79};
80
81struct opcode16
82{
823d2571 83 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 84 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 85 const char *assembler; /* How to disassemble this insn. */
86};
b7693d02 87
8f06b2d8 88/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 89
2fbad815 90 %% %
4a5329c6 91
c22aaad1 92 %c print condition code (always bits 28-31 in ARM mode)
37b37b2d 93 %q print shifter argument
e2efe87d
MGD		 94 %u print condition code (unconditional in ARM mode,
95 UNPREDICTABLE if not AL in Thumb)
4a5329c6 96 %A print address for ldc/stc/ldf/stf instruction
16980d0b 97 %B print vstm/vldm register list
4a5329c6 98 %I print cirrus signed shift immediate: bits 0..3|4..6
4a5329c6
ZW		 99 %F print the COUNT field of a LFM/SFM instruction.
100 %P print floating point precision in arithmetic insn
101 %Q print floating point precision in ldf/stf insn
102 %R print floating point rounding mode
103
33399f07 104 %<bitfield>c print as a condition code (for vsel)
4a5329c6 105 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 106 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
107 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 108 %<bitfield>d print the bitfield in decimal
16980d0b 109 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 110 %<bitfield>x print the bitfield in hex
111 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 112 %<bitfield>f print a floating point constant if >7 else a
113 floating point register
4a5329c6
ZW		 114 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
115 %<bitfield>g print as an iWMMXt 64-bit register
116 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 117 %<bitfield>D print as a NEON D register
118 %<bitfield>Q print as a NEON Q register
6f1c2142 119 %<bitfield>E print a quarter-float immediate value
4a5329c6 120
16980d0b 121 %y<code> print a single precision VFP reg.
2fbad815 122 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 123 %z<code> print a double precision VFP reg
2fbad815 124 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 125
16980d0b
JB		 126 %<bitfield>'c print specified char iff bitfield is all ones
127 %<bitfield>`c print specified char iff bitfield is all zeroes
128 %<bitfield>?ab... select from array of values in big endian order
43e65147 129
2fbad815 130 %L print as an iWMMXt N/M width field.
4a5329c6 131 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 132 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 133 versions.
134 %i print 5-bit immediate in bits 8,3..0
135 (print "32" when 0)
fe56b6ce 136 %r print register offset address for wldt/wstr instruction. */
2fbad815 137
21d799b5 138enum opcode_sentinel_enum
05413229
NC		 139{
140 SENTINEL_IWMMXT_START = 1,
141 SENTINEL_IWMMXT_END,
142 SENTINEL_GENERIC_START
143} opcode_sentinels;
144
aefd8a40 145#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
c1e26897 146#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 147
8f06b2d8 148/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 149
8f06b2d8 150static const struct opcode32 coprocessor_opcodes[] =
2fbad815 151{
2fbad815 152 /* XScale instructions. */
823d2571
TG		 153 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
154 0x0e200010, 0x0fff0ff0,
155 "mia%c\tacc0, %0-3r, %12-15r"},
156 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
157 0x0e280010, 0x0fff0ff0,
158 "miaph%c\tacc0, %0-3r, %12-15r"},
159 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
160 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
161 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
162 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
163 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
164 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 165
2fbad815 166 /* Intel Wireless MMX technology instructions. */
823d2571
TG		 167 {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
168 {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
169 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
170 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
171 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
172 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
173 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
174 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
175 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
176 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
177 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
178 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
179 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
180 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
181 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
182 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
183 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
184 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
185 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
186 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
187 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
188 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
189 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
190 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
191 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
192 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
193 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
194 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
195 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
196 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
197 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
198 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
199 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
200 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
201 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
202 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
203 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
204 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
205 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
206 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
207 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
208 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
209 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
210 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
211 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
212 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
213 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
214 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
215 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
216 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
217 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
218 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
219 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
220 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
221 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
222 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
223 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
224 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
225 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
226 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
227 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
228 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
229 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
230 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
231 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
232 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
233 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
234 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
235 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
236 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
237 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
238 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
239 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
240 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
241 0x0e800120, 0x0f800ff0,
242 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
243 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
244 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
245 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
246 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
247 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
248 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
249 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
250 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
251 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
252 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
253 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
254 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
255 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
256 0x0e8000a0, 0x0f800ff0,
257 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
258 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
259 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
260 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
261 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
262 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
263 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
264 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
265 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
266 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
267 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
268 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
269 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
270 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
271 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
272 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
273 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
274 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
275 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
276 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
277 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
278 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
279 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
280 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
281 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
282 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
283 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
284 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
285 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
286 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
287 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
288 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
289 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
290 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
291 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
292 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
293 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
294 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
295 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
296 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
297 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
298 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
299 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
300 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
301 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
302 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
303 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
304 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
305 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
306 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
307 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
308 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
309 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
310 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
311 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
312 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
313 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
314 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
315 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
316 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
317 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
318 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
319 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
320 {ARM_FEATURE_CORE_LOW (0),
321 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 322
fe56b6ce 323 /* Floating point coprocessor (FPA) instructions. */
823d2571
TG		 324 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
325 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
326 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
327 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
328 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
329 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
330 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
331 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
332 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
333 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
334 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
335 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
336 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
337 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
338 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
339 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
340 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
341 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
342 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
343 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
344 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
345 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
346 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
347 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
348 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
349 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
350 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
351 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
352 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
353 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
354 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
355 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
356 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
357 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
358 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
359 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
360 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
361 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
362 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
363 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
364 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
365 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
366 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
367 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
368 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
369 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
370 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
371 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
372 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
373 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
374 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
375 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
376 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
377 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
378 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
379 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
380 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
381 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
382 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
383 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
384 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
385 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
386 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
387 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
388 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
389 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
390 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
391 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
392 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
393 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
394 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
395 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
396 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
397 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
398 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
399 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
400 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
401 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
402 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
403 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
404 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
405 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
406 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
407 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
408 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
409 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 410
fe56b6ce 411 /* Register load/store. */
823d2571
TG		 412 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
413 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
414 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
415 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
416 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
417 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
418 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
419 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
420 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
421 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
422 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
423 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
424 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
425 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
426 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
427 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
428 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
429 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
430 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
431 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
432 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
433 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
434 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
435 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
436 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
437 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
438 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
439 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
440 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
441 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
442 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
443 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
444
445 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
446 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
447 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
448 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
449 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
450 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
451 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
452 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 453
fe56b6ce 454 /* Data transfer between ARM and NEON registers. */
823d2571
TG		 455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
456 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
457 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
458 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
459 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
460 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
462 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
464 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
466 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
468 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
470 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
472 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
474 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
476 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
478 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
480 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
482 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 483 /* Half-precision conversion instructions. */
823d2571
TG		 484 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
485 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
486 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
487 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
488 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
489 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
490 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
491 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 492
fe56b6ce 493 /* Floating point coprocessor (VFP) instructions. */
823d2571
TG		 494 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
495 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
496 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
497 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
498 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
499 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
500 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
501 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
502 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
503 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
504 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
505 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
506 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
507 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
508 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
509 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
510 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
511 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
512 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
513 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
514 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
515 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
516 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
517 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
518 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
519 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
520 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
521 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
522 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
523 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
524 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
525 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
526 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
527 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
528 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
529 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
530 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
531 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
532 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
533 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
534 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
535 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
536 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
537 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
538 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
539 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
540 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
541 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
542 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
543 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
544 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
545 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
546 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
547 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
548 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
549 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
550 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
551 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
552 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
553 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
554 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
555 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
556 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
557 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
558 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
559 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
560 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
561 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
562 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
563 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
564 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
565 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
566 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
567 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
568 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
569 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
570 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
571 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
572 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
573 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
574 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
575 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
576 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
577 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
578 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
579 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
580 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
581 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
582 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6f1c2142 583 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
823d2571 584 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6f1c2142 585 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
823d2571
TG		 586 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
587 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
588 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
589 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
590 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
591 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
592 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
593 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
594 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
595 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
596 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
597 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
598 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
599 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
600 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
601 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
602 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
603 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
604 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
605 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
606 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
607 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
608 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
609 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
610 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
611 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
612 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
613 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
614 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
615 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
616 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
617 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
618 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
619 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
620 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
621 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
622 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
623 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
624 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
625 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
626 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
627 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 628
629 /* Cirrus coprocessor instructions. */
823d2571
TG		 630 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
631 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
632 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
633 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
634 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
635 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
636 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
637 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
638 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
639 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
640 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
641 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
642 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
643 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
644 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
645 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
646 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
647 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
648 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
649 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
650 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
651 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
652 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
653 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
654 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
655 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
656 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
657 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
658 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
659 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
660 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
661 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
662 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
663 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
664 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
665 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
666 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
667 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
668 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
669 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
670 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
671 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
672 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
673 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
674 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
675 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
676 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
677 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
678 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
679 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
680 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
681 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
682 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
683 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
684 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
685 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
686 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
687 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
688 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
689 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
690 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
691 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
692 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
693 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
694 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
695 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
696 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
697 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
698 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
699 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
700 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
701 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
702 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
703 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
704 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
705 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
706 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
707 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
708 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
709 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
710 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
711 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
712 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
713 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
714 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
715 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
716 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
717 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
718 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
719 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
720 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
721 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
722 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
723 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
724 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
725 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
726 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
727 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
728 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
729 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
730 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
731 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
732 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
733 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
734 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
735 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
736 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
737 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
738 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
739 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
740 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
741 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
742 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
743 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
744 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
745 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
746 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
747 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
748 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
749 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
750 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
751 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
752 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
753 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
754 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
755 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
756 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
757 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
758 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
759 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
760 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
761 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
762 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
763 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
764 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
765 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
766 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
767 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
768 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
769 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
770 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
771 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
772 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
773 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
774 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
775 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
776 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
777 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
778 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
779 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
780 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
781 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
782 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
783 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
784 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
785 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
786 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
787 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
788 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
789 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
790 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
791 0x0e000600, 0x0ff00f10,
792 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
793 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
794 0x0e100600, 0x0ff00f10,
795 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
796 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
797 0x0e200600, 0x0ff00f10,
798 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
799 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
800 0x0e300600, 0x0ff00f10,
801 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 802
62f3b8c8 803 /* VFP Fused multiply add instructions. */
823d2571
TG		 804 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
805 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
806 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
807 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
808 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
809 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
810 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
811 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
812 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
813 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
814 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
815 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
816 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
817 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
818 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
819 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 820
33399f07 821 /* FP v5. */
823d2571 822 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 823 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
823d2571 824 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 825 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
823d2571 826 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 827 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
823d2571 828 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 829 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
823d2571 830 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 831 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
823d2571 832 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 833 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
823d2571
TG		 834 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
835 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
836 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
837 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
838 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
839 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
840 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
841 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
842 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 843 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
823d2571 844 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 845 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 846
05413229 847 /* Generic coprocessor instructions. */
823d2571
TG		 848 {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
850 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
852 0x0c500000, 0x0ff00000,
853 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
855 0x0e000000, 0x0f000010,
856 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
858 0x0e10f010, 0x0f10f010,
859 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
861 0x0e100010, 0x0f100010,
862 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
864 0x0e000010, 0x0f100010,
865 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
867 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
869 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
2fbad815 870
05413229 871 /* V6 coprocessor instructions. */
823d2571
TG		 872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
873 0xfc500000, 0xfff00000,
874 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
876 0xfc400000, 0xfff00000,
877 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
8f06b2d8 878
05413229 879 /* V5 coprocessor instructions. */
823d2571
TG		 880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
881 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
883 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
885 0xfe000000, 0xff000010,
886 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
888 0xfe000010, 0xff100010,
889 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
891 0xfe100010, 0xff100010,
892 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
893
b0c11777
RL		 894 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
895 cp_num: bit <11:8> == 0b1001.
896 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
897 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
898 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
899 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
900 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
901 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
902 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
903 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
904 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
905 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
906 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
907 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
908 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
909 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
910 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
911 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
912 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
913 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
914 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
915 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
916 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
917 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
918 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
919 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
920 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
921 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
922 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
923 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
924 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
925 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
926 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
927 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
928 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
929 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
930 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
931 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
932 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
933 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
934 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
935 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
936 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
937 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
938 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
939 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
940 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
941 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
942 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
943 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
944 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
945 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
946 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
947 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
948 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
949 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
950 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
951 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
952 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
953 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
954 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
955 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
956 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
957 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
958 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
959 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
960 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
961 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
962 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
963 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
964 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
965 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
966 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
967
823d2571 968 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 969};
970
16980d0b
JB		 971/* Neon opcode table: This does not encode the top byte -- that is
972 checked by the print_insn_neon routine, as it depends on whether we are
973 doing thumb32 or arm32 disassembly. */
974
975/* print_insn_neon recognizes the following format control codes:
976
977 %% %
978
c22aaad1 979 %c print condition code
e2efe87d
MGD		 980 %u print condition code (unconditional in ARM mode,
981 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 982 %A print v{st,ld}[1234] operands
983 %B print v{st,ld}[1234] any one operands
984 %C print v{st,ld}[1234] single->all operands
985 %D print scalar
986 %E print vmov, vmvn, vorr, vbic encoded constant
987 %F print vtbl,vtbx register list
988
989 %<bitfield>r print as an ARM register
990 %<bitfield>d print the bitfield in decimal
991 %<bitfield>e print the 2^N - bitfield in decimal
992 %<bitfield>D print as a NEON D register
993 %<bitfield>Q print as a NEON Q register
994 %<bitfield>R print as a NEON D or Q register
995 %<bitfield>Sn print byte scaled width limited by n
996 %<bitfield>Tn print short scaled width limited by n
997 %<bitfield>Un print long scaled width limited by n
43e65147 998
16980d0b
JB		 999 %<bitfield>'c print specified char iff bitfield is all ones
1000 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1001 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1002
1003static const struct opcode32 neon_opcodes[] =
1004{
fe56b6ce 1005 /* Extract. */
823d2571
TG		 1006 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1007 0xf2b00840, 0xffb00850,
1008 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1009 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1010 0xf2b00000, 0xffb00810,
1011 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 1012
fe56b6ce 1013 /* Move data element to all lanes. */
823d2571
TG		 1014 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1015 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1016 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1017 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1018 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1019 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 1020
fe56b6ce 1021 /* Table lookup. */
823d2571
TG		 1022 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1023 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1024 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1025 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1026
8e79c3df 1027 /* Half-precision conversions. */
823d2571
TG		 1028 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1029 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1030 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1031 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1032
1033 /* NEON fused multiply add instructions. */
823d2571 1034 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1035 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1036 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1037 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1038 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1039 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1040 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1041 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1042
fe56b6ce 1043 /* Two registers, miscellaneous. */
823d2571
TG		 1044 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1045 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1046 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1047 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1048 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1049 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1050 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1051 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1052 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1053 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1054 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1055 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1056 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1057 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1058 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1059 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1060 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1061 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1062 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1063 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1064 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1065 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1066 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1067 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1068 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1069 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1070 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1071 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1072 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1073 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1074 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1075 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1076 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1077 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1078 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1079 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1080 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1081 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1082 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1083 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1084 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1085 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1086 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1087 0xf3b20300, 0xffb30fd0,
1088 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1089 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1090 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1091 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1092 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1093 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1094 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1095 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1096 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1097 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1098 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1099 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1100 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1101 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1102 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1103 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1104 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1105 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1106 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1107 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1108 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1109 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1110 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1111 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1112 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1113 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1114 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1115 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1116 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1117 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1118 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1119 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1120 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1121 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1122 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1123 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1124 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1125 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1126 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1127 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1128 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1129 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1130 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1131 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1132 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1133 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1134 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1135 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301 1136 0xf3bb0600, 0xffbf0e10,
823d2571 1137 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1138 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1139 0xf3b70600, 0xffbf0e10,
1140 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
16980d0b 1141
fe56b6ce 1142 /* Three registers of the same length. */
823d2571
TG		 1143 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1144 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1145 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1146 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1147 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1148 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1149 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1150 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1151 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1152 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1153 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1154 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1155 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1156 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1157 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1158 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1159 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1160 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1161 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1162 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1163 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1164 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1165 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1166 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1167 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1168 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1169 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1170 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1171 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1172 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1173 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1174 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1175 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1176 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1177 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1178 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1179 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1180 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1181 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1182 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1183 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1184 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1185 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1186 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1187 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1188 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1189 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1190 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1191 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1192 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1193 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1194 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1195 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1196 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1197 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1198 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1199 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1200 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1201 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1202 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1203 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1204 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1205 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1206 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1207 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1208 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1209 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1210 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1211 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1212 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1213 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1214 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1215 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1216 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1217 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1218 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1219 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1220 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1221 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1222 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1223 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1224 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1225 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1226 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1227 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1228 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1229 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1230 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1231 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1232 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1233 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1234 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1235 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1236 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1237 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1238 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1239 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1240 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1241 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1242 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1243 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1244 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1245 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1246 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1247 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1248 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1249 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1250 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1251 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1252 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1253 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1254 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1255 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1256 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1257 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1258 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1259 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1260 0xf2000b00, 0xff800f10,
1261 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1262 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1263 0xf2000b10, 0xff800f10,
1264 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1265 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1266 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1267 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1268 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1269 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1270 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1271 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1272 0xf3000b00, 0xff800f10,
1273 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1274 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1275 0xf2000000, 0xfe800f10,
1276 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1277 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1278 0xf2000010, 0xfe800f10,
1279 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1280 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1281 0xf2000100, 0xfe800f10,
1282 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1283 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1284 0xf2000200, 0xfe800f10,
1285 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1286 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1287 0xf2000210, 0xfe800f10,
1288 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1289 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1290 0xf2000300, 0xfe800f10,
1291 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1292 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1293 0xf2000310, 0xfe800f10,
1294 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1295 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1296 0xf2000400, 0xfe800f10,
1297 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1298 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1299 0xf2000410, 0xfe800f10,
1300 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1301 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1302 0xf2000500, 0xfe800f10,
1303 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1304 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1305 0xf2000510, 0xfe800f10,
1306 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1307 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1308 0xf2000600, 0xfe800f10,
1309 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1310 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1311 0xf2000610, 0xfe800f10,
1312 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1313 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1314 0xf2000700, 0xfe800f10,
1315 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1316 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1317 0xf2000710, 0xfe800f10,
1318 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1319 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1320 0xf2000910, 0xfe800f10,
1321 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1322 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1323 0xf2000a00, 0xfe800f10,
1324 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1325 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1326 0xf2000a10, 0xfe800f10,
1327 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1328 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1329 0xf3000b10, 0xff800f10,
1330 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1331 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1332 0xf3000c10, 0xff800f10,
1333 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1334
fe56b6ce 1335 /* One register and an immediate value. */
823d2571
TG		 1336 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1337 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1338 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1339 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1340 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1341 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1342 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1343 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1344 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1345 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1346 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1347 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1348 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1349 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1350 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1351 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1352 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1353 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1354 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1355 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1356 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1357 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1358 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1359 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1360 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1361 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1362
fe56b6ce 1363 /* Two registers and a shift amount. */
823d2571
TG		 1364 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1365 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1366 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1367 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1368 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1369 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1370 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1371 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1372 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1373 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1374 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1375 0xf2880950, 0xfeb80fd0,
1376 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1377 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1378 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1379 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1380 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1381 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1382 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1383 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1384 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1385 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1386 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1387 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1388 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1389 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1390 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1391 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1392 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1393 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1394 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1395 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1396 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1397 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1398 0xf2900950, 0xfeb00fd0,
1399 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1400 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1401 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1402 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1403 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1404 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1405 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1406 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1407 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1408 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1409 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1410 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1411 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1412 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1413 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1414 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1415 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1416 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1417 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1418 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1419 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1420 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1421 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1422 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1423 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1424 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1425 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1426 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1427 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1428 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1429 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1430 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1431 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1432 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1433 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1434 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1435 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1436 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1437 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1438 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1439 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1440 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1441 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1442 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1443 0xf2a00950, 0xfea00fd0,
1444 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1445 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1446 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1447 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1448 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1449 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1450 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1451 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1452 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1453 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1454 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1456 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1457 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1458 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1459 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1460 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1462 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1464 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1466 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1468 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1470 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1472 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1474 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1476 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1478 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1480 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1482 0xf2a00e10, 0xfea00e90,
1483 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
cc933301
JW		 1484 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1485 0xf2a00c10, 0xfea00e90,
1486 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 1487
fe56b6ce 1488 /* Three registers of different lengths. */
823d2571
TG		 1489 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1490 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1492 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1494 0xf2800400, 0xff800f50,
1495 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1496 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1497 0xf2800600, 0xff800f50,
1498 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1499 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1500 0xf2800900, 0xff800f50,
1501 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1502 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1503 0xf2800b00, 0xff800f50,
1504 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506 0xf2800d00, 0xff800f50,
1507 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1508 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1509 0xf3800400, 0xff800f50,
1510 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1511 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1512 0xf3800600, 0xff800f50,
1513 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1514 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1515 0xf2800000, 0xfe800f50,
1516 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1517 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1518 0xf2800100, 0xfe800f50,
1519 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1520 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1521 0xf2800200, 0xfe800f50,
1522 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1523 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1524 0xf2800300, 0xfe800f50,
1525 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1526 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1527 0xf2800500, 0xfe800f50,
1528 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1530 0xf2800700, 0xfe800f50,
1531 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1532 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1533 0xf2800800, 0xfe800f50,
1534 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1535 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1536 0xf2800a00, 0xfe800f50,
1537 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1538 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1539 0xf2800c00, 0xfe800f50,
1540 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 1541
fe56b6ce 1542 /* Two registers and a scalar. */
823d2571
TG		 1543 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1544 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1545 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1546 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1547 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1548 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1549 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1550 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1551 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1552 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1553 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1554 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1555 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1556 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1557 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1558 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1559 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1560 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1561 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1562 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1564 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1565 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1566 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1567 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1568 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1569 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1570 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1571 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1572 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1573 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1574 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1576 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1577 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1578 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1579 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1580 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1581 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1582 0xf2800240, 0xfe800f50,
1583 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1584 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1585 0xf2800640, 0xfe800f50,
1586 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1587 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1588 0xf2800a40, 0xfe800f50,
1589 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 1590 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1591 0xf2800e40, 0xff800f50,
1592 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1594 0xf2800f40, 0xff800f50,
1595 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1596 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1597 0xf3800e40, 0xff800f50,
1598 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1599 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1600 0xf3800f40, 0xff800f50,
1601 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1602 },
16980d0b 1603
fe56b6ce 1604 /* Element and structure load/store. */
823d2571
TG		 1605 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1606 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1607 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1608 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1609 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1610 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1611 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1612 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1613 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1614 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1615 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1616 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1618 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1619 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1620 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1621 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1622 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1623 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1624 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1625 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1626 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1627 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1628 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1630 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1631 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1632 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1633 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1634 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1635 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1636 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1638 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1639 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1640 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1642 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1643
1644 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 1645};
1646
8f06b2d8
PB		 1647/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
1648 ordered: they must be searched linearly from the top to obtain a correct
1649 match. */
1650
1651/* print_insn_arm recognizes the following format control codes:
1652
1653 %% %
1654
1655 %a print address for ldr/str instruction
1656 %s print address for ldr/str halfword/signextend instruction
c1e26897 1657 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 1658 %b print branch destination
1659 %c print condition code (always bits 28-31)
1660 %m print register mask for ldm/stm instruction
1661 %o print operand2 (immediate or register + shift)
1662 %p print 'p' iff bits 12-15 are 15
1663 %t print 't' iff bit 21 set and bit 24 clear
1664 %B print arm BLX(1) destination
1665 %C print the PSR sub type.
62b3e311
PB		 1666 %U print barrier type.
1667 %P print address for pli instruction.
8f06b2d8
PB		 1668
1669 %<bitfield>r print as an ARM register
9eb6c0f1 1670 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 1671 %<bitfield>R as %r but r15 is UNPREDICTABLE
1672 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1673 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 1674 %<bitfield>d print the bitfield in decimal
43e65147 1675 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 1676 %<bitfield>x print the bitfield in hex
1677 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 1678
16980d0b
JB		 1679 %<bitfield>'c print specified char iff bitfield is all ones
1680 %<bitfield>`c print specified char iff bitfield is all zeroes
1681 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 1682
8f06b2d8
PB		 1683 %e print arm SMI operand (bits 0..7,8..19).
1684 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 1685 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
1686 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 1687
8f06b2d8
PB		 1688static const struct opcode32 arm_opcodes[] =
1689{
1690 /* ARM instructions. */
823d2571
TG		 1691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1692 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1694 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1695
1696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
1697 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1699 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1701 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
1703 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1705 0x00800090, 0x0fa000f0,
1706 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1708 0x00a00090, 0x0fa000f0,
1709 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 1710
105bde57
MW		 1711 /* V8.2 RAS extension instructions. */
1712 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A),
1713 0xe320f010, 0xffffffff, "esb"},
1714
53c4b28b 1715 /* V8 instructions. */
823d2571
TG		 1716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1717 0x0320f005, 0x0fffffff, "sevl"},
1718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1719 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
4ed7ed8d 1720 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 1721 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1722 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 1723 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1725 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1727 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 1728 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1729 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1730 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1731 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1732 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1733 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1734 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1735 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1736 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1737 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1738 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1739 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1740 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1741 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1742 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1743 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1744 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1745 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1746 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 1747 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 1748 /* CRC32 instructions. */
823d2571
TG		 1749 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1750 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
1751 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1752 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
1753 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1754 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
1755 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1756 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
1757 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1758 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
1759 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1760 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 1761
ddfded2f
MW		 1762 /* Privileged Access Never extension instructions. */
1763 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
1764 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
1765
90ec0d68 1766 /* Virtualization Extension instructions. */
823d2571
TG		 1767 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
1768 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 1769
eea54501 1770 /* Integer Divide Extension instructions. */
823d2571
TG		 1771 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1772 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1773 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1774 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 1775
60e5ef9f 1776 /* MP Extension instructions. */
823d2571 1777 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 1778
62b3e311 1779 /* V7 instructions. */
823d2571
TG		 1780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
1781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
1783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
1784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a
AV		 1787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
1788 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
62b3e311 1789
c19d1205 1790 /* ARM V6T2 instructions. */
823d2571
TG		 1791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1792 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1794 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1796 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1798 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
1799
1800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1801 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
1802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1803 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1804
ff8646ee 1805 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 1806 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 1807 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 1808 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1810 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1812 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 1813
f4c65163 1814 /* ARM Security extension instructions. */
823d2571
TG		 1815 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
1816 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 1817
8f06b2d8 1818 /* ARM V6K instructions. */
823d2571
TG		 1819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1820 0xf57ff01f, 0xffffffff, "clrex"},
1821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1822 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1824 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1826 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1828 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1830 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1832 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 1833
8f06b2d8 1834 /* ARM V6K NOP hints. */
823d2571
TG		 1835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1836 0x0320f001, 0x0fffffff, "yield%c"},
1837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1838 0x0320f002, 0x0fffffff, "wfe%c"},
1839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1840 0x0320f003, 0x0fffffff, "wfi%c"},
1841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1842 0x0320f004, 0x0fffffff, "sev%c"},
1843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1844 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 1845
fe56b6ce 1846 /* ARM V6 instructions. */
823d2571
TG		 1847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1848 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
1849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1850 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
1851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1852 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
1853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1854 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
1855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1856 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
1857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1858 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
1859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1860 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
1861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1862 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
1863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1864 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
1865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1866 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
1867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1868 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
1869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1870 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
1871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1872 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
1873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1874 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
1875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1876 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
1877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1878 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
1879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1880 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
1881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1882 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
1883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1884 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
1885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1886 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
1887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1888 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
1889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1890 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
1891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1892 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
1893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1894 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
1895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1896 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
1897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1898 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
1899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1900 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
1901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1902 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
1903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1904 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
1905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1906 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
1907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1908 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
1909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1910 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
1911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1912 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
1913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1914 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
1915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1916 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
1917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1918 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
1919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1920 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
1921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1922 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
1923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1924 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
1925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1926 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
1927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1928 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
1929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1930 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
1931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1932 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
1933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1934 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
1935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1936 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
1937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1938 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
1939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1940 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
1941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1942 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
1943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1944 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
1945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1946 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
1947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1948 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
1949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1950 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
1951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1952 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
1953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1954 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
1955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1956 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
1957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1958 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
1959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1960 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
1961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1962 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
1963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1964 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
1965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1966 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
1967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1968 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
1969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1970 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
1971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1972 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
1973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1974 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
1975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1976 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
1977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1978 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
1979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1980 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
1981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1982 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
1983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1984 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
1985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1986 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
1987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1988 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
1989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1990 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
1991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1992 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
1993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1994 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
1995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1996 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
1997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1998 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2000 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2002 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2004 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
2005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2006 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2008 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2010 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2012 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
2013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2014 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2016 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2018 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2020 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
2021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2022 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2024 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2026 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2028 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
2029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2030 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2032 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2034 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
2035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2036 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
2037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2038 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2040 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2042 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2044 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
2045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2046 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
2047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2048 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
2049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2050 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
2051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2052 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2054 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2056 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2058 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2060 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
2061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2062 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2064 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2066 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
2067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2068 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
2069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2070 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
2071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2072 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
2073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2074 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
2075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2076 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
2077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2078 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
2079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2080 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
2081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2082 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2084 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
2085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2086 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
2087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2088 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
2089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2090 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 2091
8f06b2d8 2092 /* V5J instruction. */
823d2571
TG		 2093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
2094 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 2095
8f06b2d8 2096 /* V5 Instructions. */
823d2571
TG		 2097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2098 0xe1200070, 0xfff000f0,
2099 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
2100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2101 0xfa000000, 0xfe000000, "blx\t%B"},
2102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2103 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
2104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2105 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
2106
2107 /* V5E "El Segundo" Instructions. */
2108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2109 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
2110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2111 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
2112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2113 0xf450f000, 0xfc70f000, "pld\t%a"},
2114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2115 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2117 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2119 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2121 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
2122
2123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2124 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2126 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
2127
2128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2129 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2131 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2133 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2135 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2136
2137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2138 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2140 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2142 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2144 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2145
2146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2147 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2149 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2150
2151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2152 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
2153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2154 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2156 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
2157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2158 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 2159
8f06b2d8 2160 /* ARM Instructions. */
823d2571
TG		 2161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2162 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2163
2164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2165 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2167 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2169 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2171 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2173 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2175 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2176
2177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2178 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2180 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2182 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2184 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2185
2186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2187 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2189 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2191 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2193 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2194
2195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2196 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2198 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2200 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2201
2202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2203 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2205 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2207 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2208
2209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2210 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2212 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2214 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2215
2216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2217 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2219 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2221 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2222
2223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2224 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2226 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2228 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2229
2230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2231 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2233 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2235 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2236
2237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2238 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2240 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2242 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2243
2244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2245 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2247 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2249 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2250
2251 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2252 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2254 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2256 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2257
2258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2259 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2261 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2263 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2264
2265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2266 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 2267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2268 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 2269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a
AV		 2270 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
2271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2272 0x0130f000, 0x0ff0f010, "bx%c\t%0-3r"},
823d2571
TG		 2273
2274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2275 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2277 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2279 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2280
2281 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2282 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2283 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2284 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2285 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2286 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2287
2288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2289 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2291 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2292 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2293 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2294
2295 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2296 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2297 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2298 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2299 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2300 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2301 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2302 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2304 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2305 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2306 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2307 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2308 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2309
2310 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2311 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2313 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2315 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2316
2317 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2318 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2320 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2322 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2323
2324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2325 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2327 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2328
2329 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2330 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2331
2332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2333 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2335 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2336
2337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2338 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2339 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2340 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2341 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2342 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2343 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2344 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2345 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2346 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2348 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2350 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2352 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2354 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2356 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2358 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2360 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2362 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2364 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2366 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2368 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2370 0x092d0000, 0x0fff0000, "push%c\t%m"},
2371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2372 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2374 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2375
2376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2377 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2379 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2381 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2383 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2385 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2387 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2389 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2391 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2393 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2395 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2397 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2399 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2401 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2403 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2405 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2407 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2409 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2411 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2413 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2414
2415 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2416 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2418 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 2419
2420 /* The rest. */
4ab90a7a
AV		 2421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2422 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 2423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2424 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2425 {ARM_FEATURE_CORE_LOW (0),
2426 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 2427};
2428
2429/* print_insn_thumb16 recognizes the following format control codes:
2430
2431 %S print Thumb register (bits 3..5 as high number if bit 6 set)
2432 %D print Thumb register (bits 0..2 as high number if bit 7 set)
2433 %<bitfield>I print bitfield as a signed decimal
2434 (top bit of range being the sign bit)
2435 %N print Thumb register mask (with LR)
2436 %O print Thumb register mask (with PC)
2437 %M print Thumb register mask
2438 %b print CZB's 6-bit unsigned branch destination
2439 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 2440 %c print the condition code
2441 %C print the condition code, or "s" if not conditional
2442 %x print warning if conditional an not at end of IT block"
2443 %X print "\t; unpredictable <IT:code>" if conditional
2444 %I print IT instruction suffix and operands
4547cb56 2445 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 2446 %<bitfield>r print bitfield as an ARM register
2447 %<bitfield>d print bitfield as a decimal
2448 %<bitfield>H print (bitfield * 2) as a decimal
2449 %<bitfield>W print (bitfield * 4) as a decimal
2450 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
2451 %<bitfield>B print Thumb branch destination (signed displacement)
2452 %<bitfield>c print bitfield as a condition code
2453 %<bitnum>'c print specified char iff bit is one
2454 %<bitnum>?ab print a if bit is one else print b. */
2455
2456static const struct opcode16 thumb_opcodes[] =
2457{
2458 /* Thumb instructions. */
2459
53c4b28b 2460 /* ARM V8 instructions. */
823d2571
TG		 2461 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
2462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
ddfded2f 2463 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
53c4b28b 2464
8f06b2d8 2465 /* ARM V6K no-argument instructions. */
823d2571
TG		 2466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2467 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2469 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2471 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 2472
2473 /* ARM V6T2 instructions. */
ff8646ee
TP		 2474 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2475 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2476 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2477 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 2478 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 2479
2480 /* ARM V6. */
823d2571
TG		 2481 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2482 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2483 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2485 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2489 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2490 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 2492
2493 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 2494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2495 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 2496 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 2497 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2498 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 2499 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 2500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2501 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 2502 /* Format 4. */
823d2571
TG		 2503 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2504 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2505 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2507 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2509 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2510 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2511 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2513 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2515 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2517 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2518 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 2519 /* format 13 */
823d2571
TG		 2520 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2521 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 2522 /* format 5 */
823d2571
TG		 2523 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
2524 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
2525 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2526 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 2527 /* format 14 */
823d2571
TG		 2528 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
2529 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 2530 /* format 2 */
823d2571
TG		 2531 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2532 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2533 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2534 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2535 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2536 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2537 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2538 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 2539 /* format 8 */
823d2571
TG		 2540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2541 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2543 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2545 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2546 /* format 7 */
823d2571
TG		 2547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2548 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2550 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2551 /* format 1 */
823d2571
TG		 2552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2554 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2555 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 2557 /* format 3 */
823d2571
TG		 2558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2559 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 2562 /* format 6 */
823d2571
TG		 2563 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2565 0x4800, 0xF800,
2566 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 2567 /* format 9 */
823d2571
TG		 2568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2569 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2571 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2573 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2575 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 2576 /* format 10 */
823d2571
TG		 2577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2578 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2579 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2580 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 2581 /* format 11 */
823d2571
TG		 2582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2583 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2585 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 2586 /* format 12 */
823d2571
TG		 2587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2588 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2590 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 2591 /* format 15 */
823d2571
TG		 2592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 2594 /* format 17 */
823d2571 2595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 2596 /* format 16 */
823d2571
TG		 2597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
2599 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 2600 /* format 18 */
823d2571 2601 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 2602
2603 /* The E800 .. FFFF range is unconditionally redirected to the
2604 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2605 are processed via that table. Thus, we can never encounter a
2606 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 2607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
2608 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 2609};
2610
2611/* Thumb32 opcodes use the same table structure as the ARM opcodes.
2612 We adopt the convention that hw1 is the high 16 bits of .value and
2613 .mask, hw2 the low 16 bits.
2614
2615 print_insn_thumb32 recognizes the following format control codes:
2616
2617 %% %
2618
2619 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2620 %M print a modified 12-bit immediate (same location)
2621 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2622 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 2623 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 2624 %S print a possibly-shifted Rm
2625
32a94698 2626 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 2627 %a print the address of a plain load/store
2628 %w print the width and signedness of a core load/store
2629 %m print register mask for ldm/stm
2630
2631 %E print the lsb and width fields of a bfc/bfi instruction
2632 %F print the lsb and width fields of a sbfx/ubfx instruction
2633 %b print a conditional branch offset
2634 %B print an unconditional branch offset
2635 %s print the shift field of an SSAT instruction
2636 %R print the rotation field of an SXT instruction
62b3e311
PB		 2637 %U print barrier type.
2638 %P print address for pli instruction.
c22aaad1
PB		 2639 %c print the condition code
2640 %x print warning if conditional an not at end of IT block"
2641 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 2642
2643 %<bitfield>d print bitfield in decimal
f0fba320 2644 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 2645 %<bitfield>W print bitfield*4 in decimal
2646 %<bitfield>r print bitfield as an ARM register
dd5181d5
KT		 2647 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
2648 %<bitfield>S as %<>R but r13 is UNPREDICTABLE
8f06b2d8
PB		 2649 %<bitfield>c print bitfield as a condition code
2650
16980d0b
JB		 2651 %<bitfield>'c print specified char iff bitfield is all ones
2652 %<bitfield>`c print specified char iff bitfield is all zeroes
2653 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 2654
2655 With one exception at the bottom (done because BL and BLX(1) need
2656 to come dead last), this table was machine-sorted first in
2657 decreasing order of number of bits set in the mask, then in
2658 increasing numeric order of mask, then in increasing numeric order
2659 of opcode. This order is not the clearest for a human reader, but
2660 is guaranteed never to catch a special-case bit pattern with a more
2661 general mask, which is important, because this instruction encoding
2662 makes heavy use of special-case bit patterns. */
2663static const struct opcode32 thumb32_opcodes[] =
2664{
4ed7ed8d
TP		 2665 /* V8-M instructions. */
2666 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2667 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
2668 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2669 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
2670
105bde57
MW		 2671 /* ARM V8.2 RAS extension instructions. */
2672 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A),
2673 0xf3af8010, 0xffffffff, "esb"},
2674
53c4b28b 2675 /* V8 instructions. */
823d2571
TG		 2676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2677 0xf3af8005, 0xffffffff, "sevl%c.w"},
2678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2679 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2681 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2683 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
2684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2685 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
2686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2687 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
2688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2689 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
2690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2691 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
2692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2693 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
2694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2695 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2697 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2699 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
2700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2701 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2703 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2705 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2707 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 2708
dd5181d5 2709 /* CRC32 instructions. */
823d2571
TG		 2710 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2711 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"},
2712 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2713 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"},
2714 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2715 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"},
2716 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2717 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"},
2718 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2719 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"},
2720 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2721 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"},
dd5181d5 2722
62b3e311 2723 /* V7 instructions. */
823d2571
TG		 2724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
2725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
2726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
2727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
2728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
2729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
2730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
2731 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2732 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
2733 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2734 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 2735
90ec0d68 2736 /* Virtualization Extension instructions. */
823d2571 2737 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 2738 /* We skip ERET as that is SUBS pc, lr, #0. */
2739
60e5ef9f 2740 /* MP Extension instructions. */
823d2571 2741 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 2742
f4c65163 2743 /* Security extension instructions. */
823d2571 2744 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 2745
8f06b2d8 2746 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 2747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
2748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
2749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
2752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2753 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
2754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
2755
ff8646ee 2756 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2757 0xf3bf8f2f, 0xffffffff, "clrex%c"},
2758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2759 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
2760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2761 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
2762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2763 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
2764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2765 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
2766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2767 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
2768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2769 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
2770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2771 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
2772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2773 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
2774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2775 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
2776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2777 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
2778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2779 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
2780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2781 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
2782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2783 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 2784 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 2785 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 2786 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2787 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
2788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2789 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
2790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2791 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
2792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2793 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
2794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2795 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
2796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2797 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
2798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2799 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
2800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2801 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
2802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2803 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 2804 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2805 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
2806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2807 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
2808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2809 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
2810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2811 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
2812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2813 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
2814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2815 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
2816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2817 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
2818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2819 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
2820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2821 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
2822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2823 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
2824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2825 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
2826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2827 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
2828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2829 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
2830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2831 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
2832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2833 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
2834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2835 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
2836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2837 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
2838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2839 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
2840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2841 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
2842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2843 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
2844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2845 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
2846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2847 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
2848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2849 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
2850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2851 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
2852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2853 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
2854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2855 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
2856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2857 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
2858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2859 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
2860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2861 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
2862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2863 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
2864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2865 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
2866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2867 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
2868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2869 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
2870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2871 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
2872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2873 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
2874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2875 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
2876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2877 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
2878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2879 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
2880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2881 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
2882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2883 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
2884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2885 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
2886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2887 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
2888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2889 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
2890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2891 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
2892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2893 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
2894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2895 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
2896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2897 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
2898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2899 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
2900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2901 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
2902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2903 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
2904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2905 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2907 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2909 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2911 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 2912 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2913 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
2914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 2915 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 2916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2917 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
2918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2919 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
2920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2921 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2923 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
2924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2925 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
2926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2927 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2929 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2931 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2933 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2935 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2937 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2939 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2941 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
2942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2943 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
2944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2945 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
2946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2947 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
2948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2949 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
2950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2951 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
2952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2953 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
2954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2955 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
2956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2957 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
2958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2959 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
2960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2961 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
2962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2963 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
2964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2965 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2967 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
2968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2969 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2971 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2973 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2975 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2977 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
2978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2979 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 2980 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2981 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
2982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2983 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
2984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2985 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
2986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2987 0xf810f000, 0xff70f000, "pld%c\t%a"},
2988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2989 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2991 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2993 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2995 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2997 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
2998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2999 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3001 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3003 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
3004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3005 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
3006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3007 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
3008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3009 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
3010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3011 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
3012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3013 0xfb100000, 0xfff000c0,
3014 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3016 0xfbc00080, 0xfff000c0,
3017 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
3018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3019 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
3020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3021 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
3022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 3023 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 3024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3025 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
3026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3027 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 3028 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3029 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
3030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3031 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 3032 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3033 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
3034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3035 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
3036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3037 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
3038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3039 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
3040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3041 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
3042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3043 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
3044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3045 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
3046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3047 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
3048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3049 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
3050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3051 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
3052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3053 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 3054 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3055 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
3056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3057 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
3058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3059 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
3060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3061 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
3062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3063 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
3064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3065 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
3066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3067 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
3068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3069 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
3070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3071 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
3072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3073 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
3074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3075 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
3076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3077 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
3078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3079 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
3080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3081 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
3082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3083 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
3084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3085 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
3086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3087 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
3088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3089 0xe9400000, 0xff500000,
3090 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3092 0xe9500000, 0xff500000,
3093 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3095 0xe8600000, 0xff700000,
3096 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3098 0xe8700000, 0xff700000,
3099 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3101 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
3102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3103 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 3104
3105 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 3106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3107 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
3108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3109 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
3110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3111 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
3112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3113 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 3114
8f06b2d8 3115 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 3116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3117 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
3118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3119 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 3120
3121 /* Fallback. */
823d2571
TG		 3122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3123 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3124 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 3125};
ff4a8d2b 3126
8f06b2d8
PB		 3127static const char *const arm_conditional[] =
3128{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 3129 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 3130
3131static const char *const arm_fp_const[] =
3132{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3133
3134static const char *const arm_shift[] =
3135{"lsl", "lsr", "asr", "ror"};
3136
3137typedef struct
3138{
3139 const char *name;
3140 const char *description;
3141 const char *reg_names[16];
3142}
3143arm_regname;
3144
3145static const arm_regname regnames[] =
3146{
3147 { "raw" , "Select raw register names",
3148 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
3149 { "gcc", "Select register names used by GCC",
3150 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
3151 { "std", "Select register names used in ARM's ISA documentation",
3152 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
3153 { "apcs", "Select register names used in the APCS",
3154 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
3155 { "atpcs", "Select register names used in the ATPCS",
3156 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
3157 { "special-atpcs", "Select special register names used in the ATPCS",
3158 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
3159};
3160
3161static const char *const iwmmxt_wwnames[] =
3162{"b", "h", "w", "d"};
3163
3164static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 3165{"b", "bus", "bc", "bss",
3166 "h", "hus", "hc", "hss",
3167 "w", "wus", "wc", "wss",
3168 "d", "dus", "dc", "dss"
8f06b2d8
PB		 3169};
3170
3171static const char *const iwmmxt_regnames[] =
3172{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3173 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3174};
3175
3176static const char *const iwmmxt_cregnames[] =
3177{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3178 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3179};
3180
3181/* Default to GCC register name set. */
3182static unsigned int regname_selected = 1;
3183
3184#define NUM_ARM_REGNAMES NUM_ELEM (regnames)
3185#define arm_regnames regnames[regname_selected].reg_names
3186
3187static bfd_boolean force_thumb = FALSE;
3188
c22aaad1
PB		 3189/* Current IT instruction state. This contains the same state as the IT
3190 bits in the CPSR. */
3191static unsigned int ifthen_state;
3192/* IT state for the next instruction. */
3193static unsigned int ifthen_next_state;
3194/* The address of the insn for which the IT state is valid. */
3195static bfd_vma ifthen_address;
3196#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 3197/* Indicates that the current Conditional state is unconditional or outside
3198 an IT block. */
3199#define COND_UNCOND 16
c22aaad1 3200
8f06b2d8
PB		 3201\f
3202/* Functions. */
3203int
3204get_arm_regname_num_options (void)
3205{
3206 return NUM_ARM_REGNAMES;
3207}
3208
3209int
3210set_arm_regname_option (int option)
3211{
3212 int old = regname_selected;
3213 regname_selected = option;
3214 return old;
3215}
3216
3217int
fe56b6ce
NC		 3218get_arm_regnames (int option,
3219 const char **setname,
3220 const char **setdescription,
8f06b2d8
PB		 3221 const char *const **register_names)
3222{
3223 *setname = regnames[option].name;
3224 *setdescription = regnames[option].description;
3225 *register_names = regnames[option].reg_names;
3226 return 16;
3227}
3228
16980d0b
JB		 3229/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3230 Returns pointer to following character of the format string and
3231 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 3232 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 3233
3234static const char *
fe56b6ce
NC		 3235arm_decode_bitfield (const char *ptr,
3236 unsigned long insn,
3237 unsigned long *valuep,
3238 int *widthp)
16980d0b
JB		 3239{
3240 unsigned long value = 0;
3241 int width = 0;
43e65147
L		 3242
3243 do
16980d0b
JB		 3244 {
3245 int start, end;
3246 int bits;
3247
3248 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3249 start = start * 10 + *ptr - '0';
3250 if (*ptr == '-')
3251 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3252 end = end * 10 + *ptr - '0';
3253 else
3254 end = start;
3255 bits = end - start;
3256 if (bits < 0)
3257 abort ();
3258 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3259 width += bits + 1;
3260 }
3261 while (*ptr++ == ',');
3262 *valuep = value;
3263 if (widthp)
3264 *widthp = width;
3265 return ptr - 1;
3266}
3267
8f06b2d8 3268static void
37b37b2d 3269arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 3270 bfd_boolean print_shift)
8f06b2d8
PB		 3271{
3272 func (stream, "%s", arm_regnames[given & 0xf]);
3273
3274 if ((given & 0xff0) != 0)
3275 {
3276 if ((given & 0x10) == 0)
3277 {
3278 int amount = (given & 0xf80) >> 7;
3279 int shift = (given & 0x60) >> 5;
3280
3281 if (amount == 0)
3282 {
3283 if (shift == 3)
3284 {
3285 func (stream, ", rrx");
3286 return;
3287 }
3288
3289 amount = 32;
3290 }
3291
37b37b2d
RE		 3292 if (print_shift)
3293 func (stream, ", %s #%d", arm_shift[shift], amount);
3294 else
3295 func (stream, ", #%d", amount);
8f06b2d8 3296 }
74bdfecf 3297 else if ((given & 0x80) == 0x80)
aefd8a40 3298 func (stream, "\t; <illegal shifter operand>");
37b37b2d 3299 else if (print_shift)
8f06b2d8
PB		 3300 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3301 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 3302 else
3303 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 3304 }
3305}
3306
c1e26897
NC		 3307#define W_BIT 21
3308#define I_BIT 22
3309#define U_BIT 23
3310#define P_BIT 24
3311
3312#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
3313#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
3314#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
3315#define PRE_BIT_SET (given & (1 << P_BIT))
3316
8f06b2d8
PB		 3317/* Print one coprocessor instruction on INFO->STREAM.
3318 Return TRUE if the instuction matched, FALSE if this is not a
3319 recognised coprocessor instruction. */
3320
3321static bfd_boolean
fe56b6ce
NC		 3322print_insn_coprocessor (bfd_vma pc,
3323 struct disassemble_info *info,
3324 long given,
8f06b2d8
PB		 3325 bfd_boolean thumb)
3326{
3327 const struct opcode32 *insn;
3328 void *stream = info->stream;
3329 fprintf_ftype func = info->fprintf_func;
3330 unsigned long mask;
2edcd244 3331 unsigned long value = 0;
c22aaad1 3332 int cond;
8afc7bea 3333 int cp_num;
823d2571
TG		 3334 struct arm_private_data *private_data = info->private_data;
3335 arm_feature_set allowed_arches = ARM_ARCH_NONE;
3336
3337 ARM_FEATURE_COPY (allowed_arches, private_data->features);
8f06b2d8
PB		 3338
3339 for (insn = coprocessor_opcodes; insn->assembler; insn++)
3340 {
ff4a8d2b
NC		 3341 unsigned long u_reg = 16;
3342 bfd_boolean is_unpredictable = FALSE;
05413229 3343 signed long value_in_comment = 0;
0313a2b8
NC		 3344 const char *c;
3345
823d2571 3346 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 3347 switch (insn->value)
3348 {
3349 case SENTINEL_IWMMXT_START:
3350 if (info->mach != bfd_mach_arm_XScale
3351 && info->mach != bfd_mach_arm_iWMMXt
3352 && info->mach != bfd_mach_arm_iWMMXt2)
3353 do
3354 insn++;
823d2571
TG		 3355 while ((! ARM_FEATURE_ZERO (insn->arch))
3356 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 3357 continue;
3358
3359 case SENTINEL_IWMMXT_END:
3360 continue;
3361
3362 case SENTINEL_GENERIC_START:
823d2571 3363 ARM_FEATURE_COPY (allowed_arches, private_data->features);
05413229
NC		 3364 continue;
3365
3366 default:
3367 abort ();
3368 }
8f06b2d8
PB		 3369
3370 mask = insn->mask;
3371 value = insn->value;
8afc7bea
RL		 3372 cp_num = (given >> 8) & 0xf;
3373
8f06b2d8
PB		 3374 if (thumb)
3375 {
3376 /* The high 4 bits are 0xe for Arm conditional instructions, and
3377 0xe for arm unconditional instructions. The rest of the
3378 encoding is the same. */
3379 mask |= 0xf0000000;
3380 value |= 0xe0000000;
c22aaad1
PB		 3381 if (ifthen_state)
3382 cond = IFTHEN_COND;
3383 else
e2efe87d 3384 cond = COND_UNCOND;
8f06b2d8
PB		 3385 }
3386 else
3387 {
3388 /* Only match unconditional instuctions against unconditional
3389 patterns. */
3390 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 3391 {
3392 mask |= 0xf0000000;
e2efe87d 3393 cond = COND_UNCOND;
c22aaad1
PB		 3394 }
3395 else
3396 {
3397 cond = (given >> 28) & 0xf;
3398 if (cond == 0xe)
e2efe87d 3399 cond = COND_UNCOND;
c22aaad1 3400 }
8f06b2d8 3401 }
823d2571 3402
0313a2b8
NC		 3403 if ((given & mask) != value)
3404 continue;
8f06b2d8 3405
823d2571 3406 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 3407 continue;
3408
8afc7bea
RL		 3409 if (insn->value == 0xfe000010 /* mcr2 */
3410 || insn->value == 0xfe100010 /* mrc2 */
3411 || insn->value == 0xfc100000 /* ldc2 */
3412 || insn->value == 0xfc000000) /* stc2 */
3413 {
b0c11777 3414 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea
RL		 3415 is_unpredictable = TRUE;
3416 }
3417 else if (insn->value == 0x0e000000 /* cdp */
3418 || insn->value == 0xfe000000 /* cdp2 */
3419 || insn->value == 0x0e000010 /* mcr */
3420 || insn->value == 0x0e100010 /* mrc */
3421 || insn->value == 0x0c100000 /* ldc */
3422 || insn->value == 0x0c000000) /* stc */
3423 {
3424 /* Floating-point instructions. */
b0c11777 3425 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea
RL		 3426 continue;
3427 }
3428
0313a2b8
NC		 3429 for (c = insn->assembler; *c; c++)
3430 {
3431 if (*c == '%')
8f06b2d8 3432 {
0313a2b8 3433 switch (*++c)
8f06b2d8 3434 {
0313a2b8
NC		 3435 case '%':
3436 func (stream, "%%");
3437 break;
3438
3439 case 'A':
05413229 3440 {
79862e45 3441 int rn = (given >> 16) & 0xf;
b0c11777 3442 bfd_vma offset = given & 0xff;
0313a2b8 3443
05413229 3444 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 3445
79862e45
DJ		 3446 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
3447 {
3448 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 3449 if (cp_num == 9)
3450 /* vldr.16/vstr.16 will shift the address
3451 left by 1 bit only. */
3452 offset = offset * 2;
3453 else
3454 offset = offset * 4;
3455
79862e45
DJ		 3456 if (NEGATIVE_BIT_SET)
3457 offset = - offset;
3458 if (rn != 15)
3459 value_in_comment = offset;
3460 }
3461
c1e26897 3462 if (PRE_BIT_SET)
05413229
NC		 3463 {
3464 if (offset)
fe56b6ce 3465 func (stream, ", #%d]%s",
d908c8af 3466 (int) offset,
c1e26897 3467 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 3468 else if (NEGATIVE_BIT_SET)
3469 func (stream, ", #-0]");
05413229
NC		 3470 else
3471 func (stream, "]");
3472 }
3473 else
3474 {
0313a2b8 3475 func (stream, "]");
8f06b2d8 3476
c1e26897 3477 if (WRITEBACK_BIT_SET)
05413229
NC		 3478 {
3479 if (offset)
d908c8af 3480 func (stream, ", #%d", (int) offset);
26d97720
NS		 3481 else if (NEGATIVE_BIT_SET)
3482 func (stream, ", #-0");
05413229
NC		 3483 }
3484 else
fe56b6ce 3485 {
26d97720
NS		 3486 func (stream, ", {%s%d}",
3487 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 3488 (int) offset);
fe56b6ce
NC		 3489 value_in_comment = offset;
3490 }
05413229 3491 }
79862e45
DJ		 3492 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
3493 {
3494 func (stream, "\t; ");
6844b2c2
MGD		 3495 /* For unaligned PCs, apply off-by-alignment
3496 correction. */
43e65147 3497 info->print_address_func (offset + pc
6844b2c2
MGD		 3498 + info->bytes_per_chunk * 2
3499 - (pc & 3),
3500 info);
79862e45 3501 }
05413229 3502 }
0313a2b8 3503 break;
8f06b2d8 3504
0313a2b8
NC		 3505 case 'B':
3506 {
3507 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
3508 int offset = (given >> 1) & 0x3f;
3509
3510 if (offset == 1)
3511 func (stream, "{d%d}", regno);
3512 else if (regno + offset > 32)
3513 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
3514 else
3515 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
3516 }
3517 break;
8f06b2d8 3518
e2efe87d
MGD		 3519 case 'u':
3520 if (cond != COND_UNCOND)
3521 is_unpredictable = TRUE;
3522
3523 /* Fall through. */
0313a2b8 3524 case 'c':
b0c11777
RL		 3525 if (cond != COND_UNCOND && cp_num == 9)
3526 is_unpredictable = TRUE;
3527
0313a2b8
NC		 3528 func (stream, "%s", arm_conditional[cond]);
3529 break;
8f06b2d8 3530
0313a2b8
NC		 3531 case 'I':
3532 /* Print a Cirrus/DSP shift immediate. */
3533 /* Immediates are 7bit signed ints with bits 0..3 in
3534 bits 0..3 of opcode and bits 4..6 in bits 5..7
3535 of opcode. */
3536 {
3537 int imm;
8f06b2d8 3538
0313a2b8 3539 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 3540
0313a2b8
NC		 3541 /* Is ``imm'' a negative number? */
3542 if (imm & 0x40)
24b4cf66 3543 imm -= 0x80;
8f06b2d8 3544
0313a2b8
NC		 3545 func (stream, "%d", imm);
3546 }
3547
3548 break;
8f06b2d8 3549
0313a2b8
NC		 3550 case 'F':
3551 switch (given & 0x00408000)
3552 {
3553 case 0:
3554 func (stream, "4");
3555 break;
3556 case 0x8000:
3557 func (stream, "1");
3558 break;
3559 case 0x00400000:
3560 func (stream, "2");
8f06b2d8 3561 break;
0313a2b8
NC		 3562 default:
3563 func (stream, "3");
3564 }
3565 break;
8f06b2d8 3566
0313a2b8
NC		 3567 case 'P':
3568 switch (given & 0x00080080)
3569 {
3570 case 0:
3571 func (stream, "s");
3572 break;
3573 case 0x80:
3574 func (stream, "d");
3575 break;
3576 case 0x00080000:
3577 func (stream, "e");
3578 break;
3579 default:
3580 func (stream, _("<illegal precision>"));
8f06b2d8 3581 break;
0313a2b8
NC		 3582 }
3583 break;
8f06b2d8 3584
0313a2b8
NC		 3585 case 'Q':
3586 switch (given & 0x00408000)
3587 {
3588 case 0:
3589 func (stream, "s");
8f06b2d8 3590 break;
0313a2b8
NC		 3591 case 0x8000:
3592 func (stream, "d");
8f06b2d8 3593 break;
0313a2b8
NC		 3594 case 0x00400000:
3595 func (stream, "e");
3596 break;
3597 default:
3598 func (stream, "p");
8f06b2d8 3599 break;
0313a2b8
NC		 3600 }
3601 break;
8f06b2d8 3602
0313a2b8
NC		 3603 case 'R':
3604 switch (given & 0x60)
3605 {
3606 case 0:
3607 break;
3608 case 0x20:
3609 func (stream, "p");
3610 break;
3611 case 0x40:
3612 func (stream, "m");
3613 break;
3614 default:
3615 func (stream, "z");
3616 break;
3617 }
3618 break;
16980d0b 3619
0313a2b8
NC		 3620 case '0': case '1': case '2': case '3': case '4':
3621 case '5': case '6': case '7': case '8': case '9':
3622 {
3623 int width;
8f06b2d8 3624
0313a2b8 3625 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 3626
0313a2b8
NC		 3627 switch (*c)
3628 {
ff4a8d2b
NC		 3629 case 'R':
3630 if (value == 15)
3631 is_unpredictable = TRUE;
3632 /* Fall through. */
0313a2b8 3633 case 'r':
ff4a8d2b
NC		 3634 if (c[1] == 'u')
3635 {
3636 /* Eat the 'u' character. */
3637 ++ c;
3638
3639 if (u_reg == value)
3640 is_unpredictable = TRUE;
3641 u_reg = value;
3642 }
0313a2b8
NC		 3643 func (stream, "%s", arm_regnames[value]);
3644 break;
3645 case 'D':
3646 func (stream, "d%ld", value);
3647 break;
3648 case 'Q':
3649 if (value & 1)
3650 func (stream, "<illegal reg q%ld.5>", value >> 1);
3651 else
3652 func (stream, "q%ld", value >> 1);
3653 break;
3654 case 'd':
3655 func (stream, "%ld", value);
05413229 3656 value_in_comment = value;
0313a2b8 3657 break;
6f1c2142
AM		 3658 case 'E':
3659 {
3660 /* Converts immediate 8 bit back to float value. */
3661 unsigned floatVal = (value & 0x80) << 24
3662 | (value & 0x3F) << 19
3663 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
3664
3665 /* Quarter float have a maximum value of 31.0.
3666 Get floating point value multiplied by 1e7.
3667 The maximum value stays in limit of a 32-bit int. */
3668 unsigned decVal =
3669 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
3670 (16 + (value & 0xF));
3671
3672 if (!(decVal % 1000000))
3673 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
3674 floatVal, value & 0x80 ? '-' : ' ',
3675 decVal / 10000000,
3676 decVal % 10000000 / 1000000);
3677 else if (!(decVal % 10000))
3678 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
3679 floatVal, value & 0x80 ? '-' : ' ',
3680 decVal / 10000000,
3681 decVal % 10000000 / 10000);
3682 else
3683 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
3684 floatVal, value & 0x80 ? '-' : ' ',
3685 decVal / 10000000, decVal % 10000000);
3686 break;
3687 }
0313a2b8
NC		 3688 case 'k':
3689 {
3690 int from = (given & (1 << 7)) ? 32 : 16;
3691 func (stream, "%ld", from - value);
3692 }
3693 break;
8f06b2d8 3694
0313a2b8
NC		 3695 case 'f':
3696 if (value > 7)
3697 func (stream, "#%s", arm_fp_const[value & 7]);
3698 else
3699 func (stream, "f%ld", value);
3700 break;
4146fd53 3701
0313a2b8
NC		 3702 case 'w':
3703 if (width == 2)
3704 func (stream, "%s", iwmmxt_wwnames[value]);
3705 else
3706 func (stream, "%s", iwmmxt_wwssnames[value]);
3707 break;
4146fd53 3708
0313a2b8
NC		 3709 case 'g':
3710 func (stream, "%s", iwmmxt_regnames[value]);
3711 break;
3712 case 'G':
3713 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 3714 break;
8f06b2d8 3715
0313a2b8 3716 case 'x':
d1aaab3c 3717 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 3718 break;
8f06b2d8 3719
33399f07
MGD		 3720 case 'c':
3721 switch (value)
3722 {
3723 case 0:
3724 func (stream, "eq");
3725 break;
3726
3727 case 1:
3728 func (stream, "vs");
3729 break;
3730
3731 case 2:
3732 func (stream, "ge");
3733 break;
3734
3735 case 3:
3736 func (stream, "gt");
3737 break;
3738
3739 default:
3740 func (stream, "??");
3741 break;
3742 }
3743 break;
3744
0313a2b8
NC		 3745 case '`':
3746 c++;
3747 if (value == 0)
3748 func (stream, "%c", *c);
3749 break;
3750 case '\'':
3751 c++;
3752 if (value == ((1ul << width) - 1))
3753 func (stream, "%c", *c);
3754 break;
3755 case '?':
fe56b6ce 3756 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 3757 c += 1 << width;
3758 break;
3759 default:
3760 abort ();
3761 }
3762 break;
8f06b2d8 3763
0313a2b8
NC		 3764 case 'y':
3765 case 'z':
3766 {
3767 int single = *c++ == 'y';
3768 int regno;
3769
3770 switch (*c)
3771 {
3772 case '4': /* Sm pair */
3773 case '0': /* Sm, Dm */
3774 regno = given & 0x0000000f;
3775 if (single)
3776 {
3777 regno <<= 1;
3778 regno += (given >> 5) & 1;
16980d0b 3779 }
0313a2b8
NC		 3780 else
3781 regno += ((given >> 5) & 1) << 4;
3782 break;
8f06b2d8 3783
0313a2b8
NC		 3784 case '1': /* Sd, Dd */
3785 regno = (given >> 12) & 0x0000000f;
3786 if (single)
3787 {
3788 regno <<= 1;
3789 regno += (given >> 22) & 1;
3790 }
3791 else
3792 regno += ((given >> 22) & 1) << 4;
3793 break;
8f06b2d8 3794
0313a2b8
NC		 3795 case '2': /* Sn, Dn */
3796 regno = (given >> 16) & 0x0000000f;
3797 if (single)
8f06b2d8 3798 {
0313a2b8
NC		 3799 regno <<= 1;
3800 regno += (given >> 7) & 1;
8f06b2d8 3801 }
0313a2b8
NC		 3802 else
3803 regno += ((given >> 7) & 1) << 4;
3804 break;
7df76b80 3805
0313a2b8
NC		 3806 case '3': /* List */
3807 func (stream, "{");
3808 regno = (given >> 12) & 0x0000000f;
3809 if (single)
3810 {
3811 regno <<= 1;
3812 regno += (given >> 22) & 1;
3813 }
3814 else
3815 regno += ((given >> 22) & 1) << 4;
3816 break;
a7f8487e 3817
0313a2b8
NC		 3818 default:
3819 abort ();
8f06b2d8 3820 }
a7f8487e 3821
0313a2b8
NC		 3822 func (stream, "%c%d", single ? 's' : 'd', regno);
3823
3824 if (*c == '3')
8f06b2d8 3825 {
0313a2b8 3826 int count = given & 0xff;
a7f8487e 3827
0313a2b8
NC		 3828 if (single == 0)
3829 count >>= 1;
b34976b6 3830
0313a2b8 3831 if (--count)
8f06b2d8 3832 {
0313a2b8
NC		 3833 func (stream, "-%c%d",
3834 single ? 's' : 'd',
3835 regno + count);
8f06b2d8 3836 }
0313a2b8
NC		 3837
3838 func (stream, "}");
8f06b2d8 3839 }
0313a2b8
NC		 3840 else if (*c == '4')
3841 func (stream, ", %c%d", single ? 's' : 'd',
3842 regno + 1);
3843 }
3844 break;
3845
3846 case 'L':
3847 switch (given & 0x00400100)
3848 {
3849 case 0x00000000: func (stream, "b"); break;
3850 case 0x00400000: func (stream, "h"); break;
3851 case 0x00000100: func (stream, "w"); break;
3852 case 0x00400100: func (stream, "d"); break;
3853 default:
8f06b2d8 3854 break;
0313a2b8
NC		 3855 }
3856 break;
b34976b6 3857
0313a2b8
NC		 3858 case 'Z':
3859 {
0313a2b8
NC		 3860 /* given (20, 23) | given (0, 3) */
3861 value = ((given >> 16) & 0xf0) | (given & 0xf);
d908c8af 3862 func (stream, "%d", (int) value);
0313a2b8
NC		 3863 }
3864 break;
2d447fca 3865
0313a2b8
NC		 3866 case 'l':
3867 /* This is like the 'A' operator, except that if
3868 the width field "M" is zero, then the offset is
3869 *not* multiplied by four. */
3870 {
3871 int offset = given & 0xff;
3872 int multiplier = (given & 0x00000100) ? 4 : 1;
3873
3874 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3875
05413229
NC		 3876 if (multiplier > 1)
3877 {
3878 value_in_comment = offset * multiplier;
c1e26897 3879 if (NEGATIVE_BIT_SET)
05413229
NC		 3880 value_in_comment = - value_in_comment;
3881 }
3882
0313a2b8
NC		 3883 if (offset)
3884 {
c1e26897 3885 if (PRE_BIT_SET)
0313a2b8 3886 func (stream, ", #%s%d]%s",
c1e26897 3887 NEGATIVE_BIT_SET ? "-" : "",
0313a2b8 3888 offset * multiplier,
c1e26897 3889 WRITEBACK_BIT_SET ? "!" : "");
0313a2b8
NC		 3890 else
3891 func (stream, "], #%s%d",
c1e26897 3892 NEGATIVE_BIT_SET ? "-" : "",
0313a2b8 3893 offset * multiplier);
2d447fca 3894 }
0313a2b8
NC		 3895 else
3896 func (stream, "]");
3897 }
3898 break;
3899
3900 case 'r':
3901 {
3902 int imm4 = (given >> 4) & 0xf;
c1e26897
NC		 3903 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
3904 int ubit = ! NEGATIVE_BIT_SET;
0313a2b8
NC		 3905 const char *rm = arm_regnames [given & 0xf];
3906 const char *rn = arm_regnames [(given >> 16) & 0xf];
2d447fca 3907
0313a2b8 3908 switch (puw_bits)
2d447fca 3909 {
0313a2b8
NC		 3910 case 1:
3911 case 3:
3912 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
3913 if (imm4)
3914 func (stream, ", lsl #%d", imm4);
3915 break;
3916
3917 case 4:
3918 case 5:
3919 case 6:
3920 case 7:
3921 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
3922 if (imm4 > 0)
3923 func (stream, ", lsl #%d", imm4);
3924 func (stream, "]");
3925 if (puw_bits == 5 || puw_bits == 7)
3926 func (stream, "!");
3927 break;
3928
3929 default:
3930 func (stream, "INVALID");
2d447fca 3931 }
0313a2b8
NC		 3932 }
3933 break;
2d447fca 3934
0313a2b8
NC		 3935 case 'i':
3936 {
3937 long imm5;
3938 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
3939 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
8f06b2d8 3940 }
0313a2b8
NC		 3941 break;
3942
3943 default:
3944 abort ();
3945 }
252b5132 3946 }
252b5132 3947 }
0313a2b8
NC		 3948 else
3949 func (stream, "%c", *c);
252b5132 3950 }
05413229
NC		 3951
3952 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 3953 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 3954
ff4a8d2b
NC		 3955 if (is_unpredictable)
3956 func (stream, UNPREDICTABLE_INSTRUCTION);
3957
0313a2b8 3958 return TRUE;
252b5132 3959 }
8f06b2d8 3960 return FALSE;
252b5132
RH		 3961}
3962
05413229
NC		 3963/* Decodes and prints ARM addressing modes. Returns the offset
3964 used in the address, if any, if it is worthwhile printing the
3965 offset as a hexadecimal value in a comment at the end of the
3966 line of disassembly. */
3967
3968static signed long
62b3e311
PB		 3969print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
3970{
3971 void *stream = info->stream;
3972 fprintf_ftype func = info->fprintf_func;
f8b960bc 3973 bfd_vma offset = 0;
62b3e311
PB		 3974
3975 if (((given & 0x000f0000) == 0x000f0000)
3976 && ((given & 0x02000000) == 0))
3977 {
05413229 3978 offset = given & 0xfff;
62b3e311
PB		 3979
3980 func (stream, "[pc");
3981
c1e26897 3982 if (PRE_BIT_SET)
62b3e311 3983 {
26d97720
NS		 3984 /* Pre-indexed. Elide offset of positive zero when
3985 non-writeback. */
3986 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 3987 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 3988
3989 if (NEGATIVE_BIT_SET)
3990 offset = -offset;
62b3e311
PB		 3991
3992 offset += pc + 8;
3993
3994 /* Cope with the possibility of write-back
3995 being used. Probably a very dangerous thing
3996 for the programmer to do, but who are we to
3997 argue ? */
26d97720 3998 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 3999 }
c1e26897 4000 else /* Post indexed. */
62b3e311 4001 {
d908c8af 4002 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 4003
c1e26897 4004 /* Ie ignore the offset. */
62b3e311
PB		 4005 offset = pc + 8;
4006 }
4007
4008 func (stream, "\t; ");
4009 info->print_address_func (offset, info);
05413229 4010 offset = 0;
62b3e311
PB		 4011 }
4012 else
4013 {
4014 func (stream, "[%s",
4015 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 4016
4017 if (PRE_BIT_SET)
62b3e311
PB		 4018 {
4019 if ((given & 0x02000000) == 0)
4020 {
26d97720 4021 /* Elide offset of positive zero when non-writeback. */
05413229 4022 offset = given & 0xfff;
26d97720 4023 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 4024 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 4025 }
4026 else
4027 {
26d97720 4028 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 4029 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 4030 }
4031
4032 func (stream, "]%s",
c1e26897 4033 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 4034 }
4035 else
4036 {
4037 if ((given & 0x02000000) == 0)
4038 {
26d97720 4039 /* Always show offset. */
05413229 4040 offset = given & 0xfff;
26d97720 4041 func (stream, "], #%s%d",
d908c8af 4042 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 4043 }
4044 else
4045 {
4046 func (stream, "], %s",
c1e26897 4047 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 4048 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 4049 }
4050 }
84919466
MR		 4051 if (NEGATIVE_BIT_SET)
4052 offset = -offset;
62b3e311 4053 }
05413229
NC		 4054
4055 return (signed long) offset;
62b3e311
PB		 4056}
4057
16980d0b
JB		 4058/* Print one neon instruction on INFO->STREAM.
4059 Return TRUE if the instuction matched, FALSE if this is not a
4060 recognised neon instruction. */
4061
4062static bfd_boolean
4063print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
4064{
4065 const struct opcode32 *insn;
4066 void *stream = info->stream;
4067 fprintf_ftype func = info->fprintf_func;
4068
4069 if (thumb)
4070 {
4071 if ((given & 0xef000000) == 0xef000000)
4072 {
0313a2b8 4073 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 4074 unsigned long bit28 = given & (1 << 28);
4075
4076 given &= 0x00ffffff;
4077 if (bit28)
4078 given |= 0xf3000000;
4079 else
4080 given |= 0xf2000000;
4081 }
4082 else if ((given & 0xff000000) == 0xf9000000)
4083 given ^= 0xf9000000 ^ 0xf4000000;
4084 else
4085 return FALSE;
4086 }
43e65147 4087
16980d0b
JB		 4088 for (insn = neon_opcodes; insn->assembler; insn++)
4089 {
4090 if ((given & insn->mask) == insn->value)
4091 {
05413229 4092 signed long value_in_comment = 0;
e2efe87d 4093 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 4094 const char *c;
4095
4096 for (c = insn->assembler; *c; c++)
4097 {
4098 if (*c == '%')
4099 {
4100 switch (*++c)
4101 {
4102 case '%':
4103 func (stream, "%%");
4104 break;
4105
e2efe87d
MGD		 4106 case 'u':
4107 if (thumb && ifthen_state)
4108 is_unpredictable = TRUE;
4109
4110 /* Fall through. */
c22aaad1
PB		 4111 case 'c':
4112 if (thumb && ifthen_state)
4113 func (stream, "%s", arm_conditional[IFTHEN_COND]);
4114 break;
4115
16980d0b
JB		 4116 case 'A':
4117 {
43e65147 4118 static const unsigned char enc[16] =
16980d0b
JB		 4119 {
4120 0x4, 0x14, /* st4 0,1 */
4121 0x4, /* st1 2 */
4122 0x4, /* st2 3 */
4123 0x3, /* st3 4 */
4124 0x13, /* st3 5 */
4125 0x3, /* st1 6 */
4126 0x1, /* st1 7 */
4127 0x2, /* st2 8 */
4128 0x12, /* st2 9 */
4129 0x2, /* st1 10 */
4130 0, 0, 0, 0, 0
4131 };
4132 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4133 int rn = ((given >> 16) & 0xf);
4134 int rm = ((given >> 0) & 0xf);
4135 int align = ((given >> 4) & 0x3);
4136 int type = ((given >> 8) & 0xf);
4137 int n = enc[type] & 0xf;
4138 int stride = (enc[type] >> 4) + 1;
4139 int ix;
43e65147 4140
16980d0b
JB		 4141 func (stream, "{");
4142 if (stride > 1)
4143 for (ix = 0; ix != n; ix++)
4144 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
4145 else if (n == 1)
4146 func (stream, "d%d", rd);
4147 else
4148 func (stream, "d%d-d%d", rd, rd + n - 1);
4149 func (stream, "}, [%s", arm_regnames[rn]);
4150 if (align)
8e560766 4151 func (stream, " :%d", 32 << align);
16980d0b
JB		 4152 func (stream, "]");
4153 if (rm == 0xd)
4154 func (stream, "!");
4155 else if (rm != 0xf)
4156 func (stream, ", %s", arm_regnames[rm]);
4157 }
4158 break;
43e65147 4159
16980d0b
JB		 4160 case 'B':
4161 {
4162 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4163 int rn = ((given >> 16) & 0xf);
4164 int rm = ((given >> 0) & 0xf);
4165 int idx_align = ((given >> 4) & 0xf);
4166 int align = 0;
4167 int size = ((given >> 10) & 0x3);
4168 int idx = idx_align >> (size + 1);
4169 int length = ((given >> 8) & 3) + 1;
4170 int stride = 1;
4171 int i;
4172
4173 if (length > 1 && size > 0)
4174 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 4175
16980d0b
JB		 4176 switch (length)
4177 {
4178 case 1:
4179 {
4180 int amask = (1 << size) - 1;
4181 if ((idx_align & (1 << size)) != 0)
4182 return FALSE;
4183 if (size > 0)
4184 {
4185 if ((idx_align & amask) == amask)
4186 align = 8 << size;
4187 else if ((idx_align & amask) != 0)
4188 return FALSE;
4189 }
4190 }
4191 break;
43e65147 4192
16980d0b
JB		 4193 case 2:
4194 if (size == 2 && (idx_align & 2) != 0)
4195 return FALSE;
4196 align = (idx_align & 1) ? 16 << size : 0;
4197 break;
43e65147 4198
16980d0b
JB		 4199 case 3:
4200 if ((size == 2 && (idx_align & 3) != 0)
4201 || (idx_align & 1) != 0)
4202 return FALSE;
4203 break;
43e65147 4204
16980d0b
JB		 4205 case 4:
4206 if (size == 2)
4207 {
4208 if ((idx_align & 3) == 3)
4209 return FALSE;
4210 align = (idx_align & 3) * 64;
4211 }
4212 else
4213 align = (idx_align & 1) ? 32 << size : 0;
4214 break;
43e65147 4215
16980d0b
JB		 4216 default:
4217 abort ();
4218 }
43e65147 4219
16980d0b
JB		 4220 func (stream, "{");
4221 for (i = 0; i < length; i++)
4222 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
4223 rd + i * stride, idx);
4224 func (stream, "}, [%s", arm_regnames[rn]);
4225 if (align)
8e560766 4226 func (stream, " :%d", align);
16980d0b
JB		 4227 func (stream, "]");
4228 if (rm == 0xd)
4229 func (stream, "!");
4230 else if (rm != 0xf)
4231 func (stream, ", %s", arm_regnames[rm]);
4232 }
4233 break;
43e65147 4234
16980d0b
JB		 4235 case 'C':
4236 {
4237 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4238 int rn = ((given >> 16) & 0xf);
4239 int rm = ((given >> 0) & 0xf);
4240 int align = ((given >> 4) & 0x1);
4241 int size = ((given >> 6) & 0x3);
4242 int type = ((given >> 8) & 0x3);
4243 int n = type + 1;
4244 int stride = ((given >> 5) & 0x1);
4245 int ix;
43e65147 4246
16980d0b
JB		 4247 if (stride && (n == 1))
4248 n++;
4249 else
4250 stride++;
43e65147 4251
16980d0b
JB		 4252 func (stream, "{");
4253 if (stride > 1)
4254 for (ix = 0; ix != n; ix++)
4255 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
4256 else if (n == 1)
4257 func (stream, "d%d[]", rd);
4258 else
4259 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
4260 func (stream, "}, [%s", arm_regnames[rn]);
4261 if (align)
4262 {
91d6fa6a 4263 align = (8 * (type + 1)) << size;
16980d0b
JB		 4264 if (type == 3)
4265 align = (size > 1) ? align >> 1 : align;
4266 if (type == 2 || (type == 0 && !size))
8e560766 4267 func (stream, " :<bad align %d>", align);
16980d0b 4268 else
8e560766 4269 func (stream, " :%d", align);
16980d0b
JB		 4270 }
4271 func (stream, "]");
4272 if (rm == 0xd)
4273 func (stream, "!");
4274 else if (rm != 0xf)
4275 func (stream, ", %s", arm_regnames[rm]);
4276 }
4277 break;
43e65147 4278
16980d0b
JB		 4279 case 'D':
4280 {
4281 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
4282 int size = (given >> 20) & 3;
4283 int reg = raw_reg & ((4 << size) - 1);
4284 int ix = raw_reg >> size >> 2;
43e65147 4285
16980d0b
JB		 4286 func (stream, "d%d[%d]", reg, ix);
4287 }
4288 break;
43e65147 4289
16980d0b 4290 case 'E':
fe56b6ce 4291 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 4292 {
4293 int bits = 0;
4294 int cmode = (given >> 8) & 0xf;
4295 int op = (given >> 5) & 0x1;
4296 unsigned long value = 0, hival = 0;
4297 unsigned shift;
4298 int size = 0;
0dbde4cf 4299 int isfloat = 0;
43e65147 4300
16980d0b
JB		 4301 bits |= ((given >> 24) & 1) << 7;
4302 bits |= ((given >> 16) & 7) << 4;
4303 bits |= ((given >> 0) & 15) << 0;
43e65147 4304
16980d0b
JB		 4305 if (cmode < 8)
4306 {
4307 shift = (cmode >> 1) & 3;
fe56b6ce 4308 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4309 size = 32;
4310 }
4311 else if (cmode < 12)
4312 {
4313 shift = (cmode >> 1) & 1;
fe56b6ce 4314 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4315 size = 16;
4316 }
4317 else if (cmode < 14)
4318 {
4319 shift = (cmode & 1) + 1;
fe56b6ce 4320 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4321 value |= (1ul << (8 * shift)) - 1;
4322 size = 32;
4323 }
4324 else if (cmode == 14)
4325 {
4326 if (op)
4327 {
fe56b6ce 4328 /* Bit replication into bytes. */
16980d0b
JB		 4329 int ix;
4330 unsigned long mask;
43e65147 4331
16980d0b
JB		 4332 value = 0;
4333 hival = 0;
4334 for (ix = 7; ix >= 0; ix--)
4335 {
4336 mask = ((bits >> ix) & 1) ? 0xff : 0;
4337 if (ix <= 3)
4338 value = (value << 8) | mask;
4339 else
4340 hival = (hival << 8) | mask;
4341 }
4342 size = 64;
4343 }
4344 else
4345 {
fe56b6ce
NC		 4346 /* Byte replication. */
4347 value = (unsigned long) bits;
16980d0b
JB		 4348 size = 8;
4349 }
4350 }
4351 else if (!op)
4352 {
fe56b6ce 4353 /* Floating point encoding. */
16980d0b 4354 int tmp;
43e65147 4355
fe56b6ce
NC		 4356 value = (unsigned long) (bits & 0x7f) << 19;
4357 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 4358 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 4359 value |= (unsigned long) tmp << 24;
16980d0b 4360 size = 32;
0dbde4cf 4361 isfloat = 1;
16980d0b
JB		 4362 }
4363 else
4364 {
4365 func (stream, "<illegal constant %.8x:%x:%x>",
4366 bits, cmode, op);
4367 size = 32;
4368 break;
4369 }
4370 switch (size)
4371 {
4372 case 8:
4373 func (stream, "#%ld\t; 0x%.2lx", value, value);
4374 break;
43e65147 4375
16980d0b
JB		 4376 case 16:
4377 func (stream, "#%ld\t; 0x%.4lx", value, value);
4378 break;
4379
4380 case 32:
0dbde4cf
JB		 4381 if (isfloat)
4382 {
4383 unsigned char valbytes[4];
4384 double fvalue;
43e65147 4385
0dbde4cf
JB		 4386 /* Do this a byte at a time so we don't have to
4387 worry about the host's endianness. */
4388 valbytes[0] = value & 0xff;
4389 valbytes[1] = (value >> 8) & 0xff;
4390 valbytes[2] = (value >> 16) & 0xff;
4391 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 4392
4393 floatformat_to_double
c1e26897
NC		 4394 (& floatformat_ieee_single_little, valbytes,
4395 & fvalue);
43e65147 4396
0dbde4cf
JB		 4397 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
4398 value);
4399 }
4400 else
4e9d3b81 4401 func (stream, "#%ld\t; 0x%.8lx",
43e65147 4402 (long) (((value & 0x80000000L) != 0)
9d82ec38 4403 ? value | ~0xffffffffL : value),
c1e26897 4404 value);
16980d0b
JB		 4405 break;
4406
4407 case 64:
4408 func (stream, "#0x%.8lx%.8lx", hival, value);
4409 break;
43e65147 4410
16980d0b
JB		 4411 default:
4412 abort ();
4413 }
4414 }
4415 break;
43e65147 4416
16980d0b
JB		 4417 case 'F':
4418 {
4419 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
4420 int num = (given >> 8) & 0x3;
43e65147 4421
16980d0b
JB		 4422 if (!num)
4423 func (stream, "{d%d}", regno);
4424 else if (num + regno >= 32)
4425 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
4426 else
4427 func (stream, "{d%d-d%d}", regno, regno + num);
4428 }
4429 break;
7e8e6784 4430
16980d0b
JB		 4431
4432 case '0': case '1': case '2': case '3': case '4':
4433 case '5': case '6': case '7': case '8': case '9':
4434 {
4435 int width;
4436 unsigned long value;
4437
4438 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 4439
16980d0b
JB		 4440 switch (*c)
4441 {
4442 case 'r':
4443 func (stream, "%s", arm_regnames[value]);
4444 break;
4445 case 'd':
4446 func (stream, "%ld", value);
05413229 4447 value_in_comment = value;
16980d0b
JB		 4448 break;
4449 case 'e':
4450 func (stream, "%ld", (1ul << width) - value);
4451 break;
43e65147 4452
16980d0b
JB		 4453 case 'S':
4454 case 'T':
4455 case 'U':
05413229 4456 /* Various width encodings. */
16980d0b
JB		 4457 {
4458 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
4459 int limit;
4460 unsigned low, high;
4461
4462 c++;
4463 if (*c >= '0' && *c <= '9')
4464 limit = *c - '0';
4465 else if (*c >= 'a' && *c <= 'f')
4466 limit = *c - 'a' + 10;
4467 else
4468 abort ();
4469 low = limit >> 2;
4470 high = limit & 3;
4471
4472 if (value < low || value > high)
4473 func (stream, "<illegal width %d>", base << value);
4474 else
4475 func (stream, "%d", base << value);
4476 }
4477 break;
4478 case 'R':
4479 if (given & (1 << 6))
4480 goto Q;
4481 /* FALLTHROUGH */
4482 case 'D':
4483 func (stream, "d%ld", value);
4484 break;
4485 case 'Q':
4486 Q:
4487 if (value & 1)
4488 func (stream, "<illegal reg q%ld.5>", value >> 1);
4489 else
4490 func (stream, "q%ld", value >> 1);
4491 break;
43e65147 4492
16980d0b
JB		 4493 case '`':
4494 c++;
4495 if (value == 0)
4496 func (stream, "%c", *c);
4497 break;
4498 case '\'':
4499 c++;
4500 if (value == ((1ul << width) - 1))
4501 func (stream, "%c", *c);
4502 break;
4503 case '?':
fe56b6ce 4504 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 4505 c += 1 << width;
4506 break;
4507 default:
4508 abort ();
4509 }
4510 break;
4511
4512 default:
4513 abort ();
4514 }
4515 }
4516 }
4517 else
4518 func (stream, "%c", *c);
4519 }
05413229
NC		 4520
4521 if (value_in_comment > 32 || value_in_comment < -16)
4522 func (stream, "\t; 0x%lx", value_in_comment);
4523
e2efe87d
MGD		 4524 if (is_unpredictable)
4525 func (stream, UNPREDICTABLE_INSTRUCTION);
4526
16980d0b
JB		 4527 return TRUE;
4528 }
4529 }
4530 return FALSE;
4531}
4532
90ec0d68
MGD		 4533/* Return the name of a v7A special register. */
4534
43e65147 4535static const char *
90ec0d68
MGD		 4536banked_regname (unsigned reg)
4537{
4538 switch (reg)
4539 {
4540 case 15: return "CPSR";
43e65147 4541 case 32: return "R8_usr";
90ec0d68
MGD		 4542 case 33: return "R9_usr";
4543 case 34: return "R10_usr";
4544 case 35: return "R11_usr";
4545 case 36: return "R12_usr";
4546 case 37: return "SP_usr";
4547 case 38: return "LR_usr";
43e65147 4548 case 40: return "R8_fiq";
90ec0d68
MGD		 4549 case 41: return "R9_fiq";
4550 case 42: return "R10_fiq";
4551 case 43: return "R11_fiq";
4552 case 44: return "R12_fiq";
4553 case 45: return "SP_fiq";
4554 case 46: return "LR_fiq";
4555 case 48: return "LR_irq";
4556 case 49: return "SP_irq";
4557 case 50: return "LR_svc";
4558 case 51: return "SP_svc";
4559 case 52: return "LR_abt";
4560 case 53: return "SP_abt";
4561 case 54: return "LR_und";
4562 case 55: return "SP_und";
4563 case 60: return "LR_mon";
4564 case 61: return "SP_mon";
4565 case 62: return "ELR_hyp";
4566 case 63: return "SP_hyp";
4567 case 79: return "SPSR";
4568 case 110: return "SPSR_fiq";
4569 case 112: return "SPSR_irq";
4570 case 114: return "SPSR_svc";
4571 case 116: return "SPSR_abt";
4572 case 118: return "SPSR_und";
4573 case 124: return "SPSR_mon";
4574 case 126: return "SPSR_hyp";
4575 default: return NULL;
4576 }
4577}
4578
e797f7e0
MGD		 4579/* Return the name of the DMB/DSB option. */
4580static const char *
4581data_barrier_option (unsigned option)
4582{
4583 switch (option & 0xf)
4584 {
4585 case 0xf: return "sy";
4586 case 0xe: return "st";
4587 case 0xd: return "ld";
4588 case 0xb: return "ish";
4589 case 0xa: return "ishst";
4590 case 0x9: return "ishld";
4591 case 0x7: return "un";
4592 case 0x6: return "unst";
4593 case 0x5: return "nshld";
4594 case 0x3: return "osh";
4595 case 0x2: return "oshst";
4596 case 0x1: return "oshld";
4597 default: return NULL;
4598 }
4599}
4600
4a5329c6
ZW		 4601/* Print one ARM instruction from PC on INFO->STREAM. */
4602
4603static void
4604print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 4605{
6b5d3a4d 4606 const struct opcode32 *insn;
6a51a8a8 4607 void *stream = info->stream;
6b5d3a4d 4608 fprintf_ftype func = info->fprintf_func;
b0e28b39 4609 struct arm_private_data *private_data = info->private_data;
252b5132 4610
16980d0b
JB		 4611 if (print_insn_coprocessor (pc, info, given, FALSE))
4612 return;
4613
4614 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 4615 return;
4616
252b5132
RH		 4617 for (insn = arm_opcodes; insn->assembler; insn++)
4618 {
0313a2b8
NC		 4619 if ((given & insn->mask) != insn->value)
4620 continue;
823d2571
TG		 4621
4622 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 4623 continue;
4624
4625 /* Special case: an instruction with all bits set in the condition field
4626 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
4627 or by the catchall at the end of the table. */
4628 if ((given & 0xF0000000) != 0xF0000000
4629 || (insn->mask & 0xF0000000) == 0xF0000000
4630 || (insn->mask == 0 && insn->value == 0))
252b5132 4631 {
ff4a8d2b
NC		 4632 unsigned long u_reg = 16;
4633 unsigned long U_reg = 16;
ab8e2090 4634 bfd_boolean is_unpredictable = FALSE;
05413229 4635 signed long value_in_comment = 0;
6b5d3a4d 4636 const char *c;
b34976b6 4637
252b5132
RH		 4638 for (c = insn->assembler; *c; c++)
4639 {
4640 if (*c == '%')
4641 {
c1e26897
NC		 4642 bfd_boolean allow_unpredictable = FALSE;
4643
252b5132
RH		 4644 switch (*++c)
4645 {
4646 case '%':
4647 func (stream, "%%");
4648 break;
4649
4650 case 'a':
05413229 4651 value_in_comment = print_arm_address (pc, info, given);
62b3e311 4652 break;
252b5132 4653
62b3e311
PB		 4654 case 'P':
4655 /* Set P address bit and use normal address
4656 printing routine. */
c1e26897 4657 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 4658 break;
4659
c1e26897
NC		 4660 case 'S':
4661 allow_unpredictable = TRUE;
252b5132
RH		 4662 case 's':
4663 if ((given & 0x004f0000) == 0x004f0000)
4664 {
58efb6c0 4665 /* PC relative with immediate offset. */
f8b960bc 4666 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 4667
aefd8a40
NC		 4668 if (PRE_BIT_SET)
4669 {
26d97720
NS		 4670 /* Elide positive zero offset. */
4671 if (offset || NEGATIVE_BIT_SET)
4672 func (stream, "[pc, #%s%d]\t; ",
d908c8af 4673 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 4674 else
26d97720
NS		 4675 func (stream, "[pc]\t; ");
4676 if (NEGATIVE_BIT_SET)
4677 offset = -offset;
aefd8a40
NC		 4678 info->print_address_func (offset + pc + 8, info);
4679 }
4680 else
4681 {
26d97720
NS		 4682 /* Always show the offset. */
4683 func (stream, "[pc], #%s%d",
d908c8af 4684 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 4685 if (! allow_unpredictable)
4686 is_unpredictable = TRUE;
aefd8a40 4687 }
252b5132
RH		 4688 }
4689 else
4690 {
fe56b6ce
NC		 4691 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
4692
b34976b6 4693 func (stream, "[%s",
252b5132 4694 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 4695
c1e26897 4696 if (PRE_BIT_SET)
252b5132 4697 {
c1e26897 4698 if (IMMEDIATE_BIT_SET)
252b5132 4699 {
26d97720
NS		 4700 /* Elide offset for non-writeback
4701 positive zero. */
4702 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
4703 || offset)
4704 func (stream, ", #%s%d",
4705 NEGATIVE_BIT_SET ? "-" : "", offset);
4706
4707 if (NEGATIVE_BIT_SET)
4708 offset = -offset;
945ee430 4709
fe56b6ce 4710 value_in_comment = offset;
252b5132 4711 }
945ee430 4712 else
ff4a8d2b
NC		 4713 {
4714 /* Register Offset or Register Pre-Indexed. */
4715 func (stream, ", %s%s",
4716 NEGATIVE_BIT_SET ? "-" : "",
4717 arm_regnames[given & 0xf]);
4718
4719 /* Writing back to the register that is the source/
4720 destination of the load/store is unpredictable. */
4721 if (! allow_unpredictable
4722 && WRITEBACK_BIT_SET
4723 && ((given & 0xf) == ((given >> 12) & 0xf)))
4724 is_unpredictable = TRUE;
4725 }
252b5132 4726
b34976b6 4727 func (stream, "]%s",
c1e26897 4728 WRITEBACK_BIT_SET ? "!" : "");
252b5132 4729 }
945ee430 4730 else
252b5132 4731 {
c1e26897 4732 if (IMMEDIATE_BIT_SET)
252b5132 4733 {
945ee430 4734 /* Immediate Post-indexed. */
aefd8a40 4735 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 4736 func (stream, "], #%s%d",
4737 NEGATIVE_BIT_SET ? "-" : "", offset);
4738 if (NEGATIVE_BIT_SET)
4739 offset = -offset;
fe56b6ce 4740 value_in_comment = offset;
252b5132 4741 }
945ee430 4742 else
ff4a8d2b
NC		 4743 {
4744 /* Register Post-indexed. */
4745 func (stream, "], %s%s",
4746 NEGATIVE_BIT_SET ? "-" : "",
4747 arm_regnames[given & 0xf]);
4748
4749 /* Writing back to the register that is the source/
4750 destination of the load/store is unpredictable. */
4751 if (! allow_unpredictable
4752 && (given & 0xf) == ((given >> 12) & 0xf))
4753 is_unpredictable = TRUE;
4754 }
c1e26897 4755
07a28fab
NC		 4756 if (! allow_unpredictable)
4757 {
4758 /* Writeback is automatically implied by post- addressing.
4759 Setting the W bit is unnecessary and ARM specify it as
4760 being unpredictable. */
4761 if (WRITEBACK_BIT_SET
4762 /* Specifying the PC register as the post-indexed
4763 registers is also unpredictable. */
ab8e2090
NC		 4764 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
4765 is_unpredictable = TRUE;
07a28fab 4766 }
252b5132
RH		 4767 }
4768 }
4769 break;
b34976b6 4770
252b5132 4771 case 'b':
6b5d3a4d 4772 {
f8b960bc 4773 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
05413229 4774 info->print_address_func (disp * 4 + pc + 8, info);
6b5d3a4d 4775 }
252b5132
RH		 4776 break;
4777
4778 case 'c':
c22aaad1
PB		 4779 if (((given >> 28) & 0xf) != 0xe)
4780 func (stream, "%s",
4781 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 4782 break;
4783
4784 case 'm':
4785 {
4786 int started = 0;
4787 int reg;
4788
4789 func (stream, "{");
4790 for (reg = 0; reg < 16; reg++)
4791 if ((given & (1 << reg)) != 0)
4792 {
4793 if (started)
4794 func (stream, ", ");
4795 started = 1;
4796 func (stream, "%s", arm_regnames[reg]);
4797 }
4798 func (stream, "}");
ab8e2090
NC		 4799 if (! started)
4800 is_unpredictable = TRUE;
252b5132
RH		 4801 }
4802 break;
4803
37b37b2d 4804 case 'q':
78c66db8 4805 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 4806 break;
4807
252b5132
RH		 4808 case 'o':
4809 if ((given & 0x02000000) != 0)
4810 {
a415b1cd
JB		 4811 unsigned int rotate = (given & 0xf00) >> 7;
4812 unsigned int immed = (given & 0xff);
4813 unsigned int a, i;
4814
4815 a = (((immed << (32 - rotate))
4816 | (immed >> rotate)) & 0xffffffff);
4817 /* If there is another encoding with smaller rotate,
4818 the rotate should be specified directly. */
4819 for (i = 0; i < 32; i += 2)
4820 if ((a << i | a >> (32 - i)) <= 0xff)
4821 break;
4822
4823 if (i != rotate)
4824 func (stream, "#%d, %d", immed, rotate);
4825 else
4826 func (stream, "#%d", a);
4827 value_in_comment = a;
252b5132
RH		 4828 }
4829 else
78c66db8 4830 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 4831 break;
4832
4833 case 'p':
4834 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 4835 {
823d2571
TG		 4836 arm_feature_set arm_ext_v6 =
4837 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
4838
aefd8a40
NC		 4839 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
4840 mechanism for setting PSR flag bits. They are
4841 obsolete in V6 onwards. */
823d2571
TG		 4842 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
4843 arm_ext_v6))
aefd8a40 4844 func (stream, "p");
4ab90a7a
AV		 4845 else
4846 is_unpredictable = TRUE;
aefd8a40 4847 }
252b5132
RH		 4848 break;
4849
4850 case 't':
4851 if ((given & 0x01200000) == 0x00200000)
4852 func (stream, "t");
4853 break;
4854
252b5132 4855 case 'A':
05413229
NC		 4856 {
4857 int offset = given & 0xff;
f02232aa 4858
05413229 4859 value_in_comment = offset * 4;
c1e26897 4860 if (NEGATIVE_BIT_SET)
05413229 4861 value_in_comment = - value_in_comment;
f02232aa 4862
05413229 4863 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 4864
c1e26897 4865 if (PRE_BIT_SET)
05413229
NC		 4866 {
4867 if (offset)
fe56b6ce 4868 func (stream, ", #%d]%s",
d908c8af 4869 (int) value_in_comment,
c1e26897 4870 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 4871 else
4872 func (stream, "]");
4873 }
4874 else
4875 {
4876 func (stream, "]");
f02232aa 4877
c1e26897 4878 if (WRITEBACK_BIT_SET)
05413229
NC		 4879 {
4880 if (offset)
d908c8af 4881 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 4882 }
4883 else
fe56b6ce 4884 {
d908c8af 4885 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 4886 value_in_comment = offset;
4887 }
05413229
NC		 4888 }
4889 }
252b5132
RH		 4890 break;
4891
077b8428
NC		 4892 case 'B':
4893 /* Print ARM V5 BLX(1) address: pc+25 bits. */
4894 {
4895 bfd_vma address;
4896 bfd_vma offset = 0;
b34976b6 4897
c1e26897 4898 if (! NEGATIVE_BIT_SET)
077b8428
NC		 4899 /* Is signed, hi bits should be ones. */
4900 offset = (-1) ^ 0x00ffffff;
4901
4902 /* Offset is (SignExtend(offset field)<<2). */
4903 offset += given & 0x00ffffff;
4904 offset <<= 2;
4905 address = offset + pc + 8;
b34976b6 4906
8f06b2d8
PB		 4907 if (given & 0x01000000)
4908 /* H bit allows addressing to 2-byte boundaries. */
4909 address += 2;
b1ee46c5 4910
8f06b2d8 4911 info->print_address_func (address, info);
b1ee46c5 4912 }
b1ee46c5
AH		 4913 break;
4914
252b5132 4915 case 'C':
90ec0d68
MGD		 4916 if ((given & 0x02000200) == 0x200)
4917 {
4918 const char * name;
4919 unsigned sysm = (given & 0x004f0000) >> 16;
4920
4921 sysm |= (given & 0x300) >> 4;
4922 name = banked_regname (sysm);
4923
4924 if (name != NULL)
4925 func (stream, "%s", name);
4926 else
d908c8af 4927 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 4928 }
4929 else
4930 {
43e65147 4931 func (stream, "%cPSR_",
90ec0d68
MGD		 4932 (given & 0x00400000) ? 'S' : 'C');
4933 if (given & 0x80000)
4934 func (stream, "f");
4935 if (given & 0x40000)
4936 func (stream, "s");
4937 if (given & 0x20000)
4938 func (stream, "x");
4939 if (given & 0x10000)
4940 func (stream, "c");
4941 }
252b5132
RH		 4942 break;
4943
62b3e311 4944 case 'U':
43e65147 4945 if ((given & 0xf0) == 0x60)
62b3e311 4946 {
52e7f43d
RE		 4947 switch (given & 0xf)
4948 {
4949 case 0xf: func (stream, "sy"); break;
4950 default:
4951 func (stream, "#%d", (int) given & 0xf);
4952 break;
4953 }
43e65147
L		 4954 }
4955 else
52e7f43d 4956 {
e797f7e0
MGD		 4957 const char * opt = data_barrier_option (given & 0xf);
4958 if (opt != NULL)
4959 func (stream, "%s", opt);
4960 else
52e7f43d 4961 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 4962 }
4963 break;
4964
b34976b6 4965 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 4966 case '5': case '6': case '7': case '8': case '9':
4967 {
16980d0b
JB		 4968 int width;
4969 unsigned long value;
252b5132 4970
16980d0b 4971 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 4972
252b5132
RH		 4973 switch (*c)
4974 {
ab8e2090
NC		 4975 case 'R':
4976 if (value == 15)
4977 is_unpredictable = TRUE;
4978 /* Fall through. */
16980d0b 4979 case 'r':
9eb6c0f1
MGD		 4980 case 'T':
4981 /* We want register + 1 when decoding T. */
4982 if (*c == 'T')
4983 ++value;
4984
ff4a8d2b
NC		 4985 if (c[1] == 'u')
4986 {
4987 /* Eat the 'u' character. */
4988 ++ c;
4989
4990 if (u_reg == value)
4991 is_unpredictable = TRUE;
4992 u_reg = value;
4993 }
4994 if (c[1] == 'U')
4995 {
4996 /* Eat the 'U' character. */
4997 ++ c;
4998
4999 if (U_reg == value)
5000 is_unpredictable = TRUE;
5001 U_reg = value;
5002 }
16980d0b
JB		 5003 func (stream, "%s", arm_regnames[value]);
5004 break;
5005 case 'd':
5006 func (stream, "%ld", value);
05413229 5007 value_in_comment = value;
16980d0b
JB		 5008 break;
5009 case 'b':
5010 func (stream, "%ld", value * 8);
05413229 5011 value_in_comment = value * 8;
16980d0b
JB		 5012 break;
5013 case 'W':
5014 func (stream, "%ld", value + 1);
05413229 5015 value_in_comment = value + 1;
16980d0b
JB		 5016 break;
5017 case 'x':
5018 func (stream, "0x%08lx", value);
5019
5020 /* Some SWI instructions have special
5021 meanings. */
5022 if ((given & 0x0fffffff) == 0x0FF00000)
5023 func (stream, "\t; IMB");
5024 else if ((given & 0x0fffffff) == 0x0FF00001)
5025 func (stream, "\t; IMBRange");
5026 break;
5027 case 'X':
5028 func (stream, "%01lx", value & 0xf);
05413229 5029 value_in_comment = value;
252b5132
RH		 5030 break;
5031 case '`':
5032 c++;
16980d0b 5033 if (value == 0)
252b5132
RH		 5034 func (stream, "%c", *c);
5035 break;
5036 case '\'':
5037 c++;
16980d0b 5038 if (value == ((1ul << width) - 1))
252b5132
RH		 5039 func (stream, "%c", *c);
5040 break;
5041 case '?':
fe56b6ce 5042 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 5043 c += 1 << width;
252b5132
RH		 5044 break;
5045 default:
5046 abort ();
5047 }
5048 break;
5049
0dd132b6
NC		 5050 case 'e':
5051 {
5052 int imm;
5053
5054 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
5055 func (stream, "%d", imm);
fe56b6ce 5056 value_in_comment = imm;
0dd132b6
NC		 5057 }
5058 break;
5059
0a003adc
ZW		 5060 case 'E':
5061 /* LSB and WIDTH fields of BFI or BFC. The machine-
5062 language instruction encodes LSB and MSB. */
5063 {
5064 long msb = (given & 0x001f0000) >> 16;
5065 long lsb = (given & 0x00000f80) >> 7;
91d6fa6a 5066 long w = msb - lsb + 1;
fe56b6ce 5067
91d6fa6a
NC		 5068 if (w > 0)
5069 func (stream, "#%lu, #%lu", lsb, w);
0a003adc
ZW		 5070 else
5071 func (stream, "(invalid: %lu:%lu)", lsb, msb);
5072 }
5073 break;
5074
90ec0d68
MGD		 5075 case 'R':
5076 /* Get the PSR/banked register name. */
5077 {
5078 const char * name;
5079 unsigned sysm = (given & 0x004f0000) >> 16;
5080
5081 sysm |= (given & 0x300) >> 4;
5082 name = banked_regname (sysm);
5083
5084 if (name != NULL)
5085 func (stream, "%s", name);
5086 else
d908c8af 5087 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 5088 }
5089 break;
5090
0a003adc
ZW		 5091 case 'V':
5092 /* 16-bit unsigned immediate from a MOVT or MOVW
5093 instruction, encoded in bits 0:11 and 15:19. */
5094 {
5095 long hi = (given & 0x000f0000) >> 4;
5096 long lo = (given & 0x00000fff);
5097 long imm16 = hi | lo;
fe56b6ce
NC		 5098
5099 func (stream, "#%lu", imm16);
5100 value_in_comment = imm16;
0a003adc
ZW		 5101 }
5102 break;
5103
252b5132
RH		 5104 default:
5105 abort ();
5106 }
5107 }
5108 }
5109 else
5110 func (stream, "%c", *c);
5111 }
05413229
NC		 5112
5113 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 5114 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 5115
5116 if (is_unpredictable)
5117 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 5118
4a5329c6 5119 return;
252b5132
RH		 5120 }
5121 }
5122 abort ();
5123}
5124
4a5329c6 5125/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 5126
4a5329c6
ZW		 5127static void
5128print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 5129{
6b5d3a4d 5130 const struct opcode16 *insn;
6a51a8a8
AM		 5131 void *stream = info->stream;
5132 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 5133
5134 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 5135 if ((given & insn->mask) == insn->value)
5136 {
05413229 5137 signed long value_in_comment = 0;
6b5d3a4d 5138 const char *c = insn->assembler;
05413229 5139
c19d1205
ZW		 5140 for (; *c; c++)
5141 {
5142 int domaskpc = 0;
5143 int domasklr = 0;
5144
5145 if (*c != '%')
5146 {
5147 func (stream, "%c", *c);
5148 continue;
5149 }
252b5132 5150
c19d1205
ZW		 5151 switch (*++c)
5152 {
5153 case '%':
5154 func (stream, "%%");
5155 break;
b34976b6 5156
c22aaad1
PB		 5157 case 'c':
5158 if (ifthen_state)
5159 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5160 break;
5161
5162 case 'C':
5163 if (ifthen_state)
5164 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5165 else
5166 func (stream, "s");
5167 break;
5168
5169 case 'I':
5170 {
5171 unsigned int tmp;
5172
5173 ifthen_next_state = given & 0xff;
5174 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
5175 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
5176 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
5177 }
5178 break;
5179
5180 case 'x':
5181 if (ifthen_next_state)
5182 func (stream, "\t; unpredictable branch in IT block\n");
5183 break;
5184
5185 case 'X':
5186 if (ifthen_state)
5187 func (stream, "\t; unpredictable <IT:%s>",
5188 arm_conditional[IFTHEN_COND]);
5189 break;
5190
c19d1205
ZW		 5191 case 'S':
5192 {
5193 long reg;
5194
5195 reg = (given >> 3) & 0x7;
5196 if (given & (1 << 6))
5197 reg += 8;
4f3c3dbb 5198
c19d1205
ZW		 5199 func (stream, "%s", arm_regnames[reg]);
5200 }
5201 break;
baf0cc5e 5202
c19d1205 5203 case 'D':
4f3c3dbb 5204 {
c19d1205
ZW		 5205 long reg;
5206
5207 reg = given & 0x7;
5208 if (given & (1 << 7))
5209 reg += 8;
5210
5211 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 5212 }
c19d1205
ZW		 5213 break;
5214
5215 case 'N':
5216 if (given & (1 << 8))
5217 domasklr = 1;
5218 /* Fall through. */
5219 case 'O':
5220 if (*c == 'O' && (given & (1 << 8)))
5221 domaskpc = 1;
5222 /* Fall through. */
5223 case 'M':
5224 {
5225 int started = 0;
5226 int reg;
5227
5228 func (stream, "{");
5229
5230 /* It would be nice if we could spot
5231 ranges, and generate the rS-rE format: */
5232 for (reg = 0; (reg < 8); reg++)
5233 if ((given & (1 << reg)) != 0)
5234 {
5235 if (started)
5236 func (stream, ", ");
5237 started = 1;
5238 func (stream, "%s", arm_regnames[reg]);
5239 }
5240
5241 if (domasklr)
5242 {
5243 if (started)
5244 func (stream, ", ");
5245 started = 1;
d908c8af 5246 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 5247 }
5248
5249 if (domaskpc)
5250 {
5251 if (started)
5252 func (stream, ", ");
d908c8af 5253 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 5254 }
5255
5256 func (stream, "}");
5257 }
5258 break;
5259
4547cb56
NC		 5260 case 'W':
5261 /* Print writeback indicator for a LDMIA. We are doing a
5262 writeback if the base register is not in the register
5263 mask. */
5264 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
5265 func (stream, "!");
5266 break;
5267
c19d1205
ZW		 5268 case 'b':
5269 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
5270 {
5271 bfd_vma address = (pc + 4
5272 + ((given & 0x00f8) >> 2)
5273 + ((given & 0x0200) >> 3));
5274 info->print_address_func (address, info);
5275 }
5276 break;
5277
5278 case 's':
5279 /* Right shift immediate -- bits 6..10; 1-31 print
5280 as themselves, 0 prints as 32. */
5281 {
5282 long imm = (given & 0x07c0) >> 6;
5283 if (imm == 0)
5284 imm = 32;
0fd3a477 5285 func (stream, "#%ld", imm);
c19d1205
ZW		 5286 }
5287 break;
5288
5289 case '0': case '1': case '2': case '3': case '4':
5290 case '5': case '6': case '7': case '8': case '9':
5291 {
5292 int bitstart = *c++ - '0';
5293 int bitend = 0;
5294
5295 while (*c >= '0' && *c <= '9')
5296 bitstart = (bitstart * 10) + *c++ - '0';
5297
5298 switch (*c)
5299 {
5300 case '-':
5301 {
f8b960bc 5302 bfd_vma reg;
c19d1205
ZW		 5303
5304 c++;
5305 while (*c >= '0' && *c <= '9')
5306 bitend = (bitend * 10) + *c++ - '0';
5307 if (!bitend)
5308 abort ();
5309 reg = given >> bitstart;
5310 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 5311
c19d1205
ZW		 5312 switch (*c)
5313 {
5314 case 'r':
5315 func (stream, "%s", arm_regnames[reg]);
5316 break;
5317
5318 case 'd':
d908c8af 5319 func (stream, "%ld", (long) reg);
05413229 5320 value_in_comment = reg;
c19d1205
ZW		 5321 break;
5322
5323 case 'H':
d908c8af 5324 func (stream, "%ld", (long) (reg << 1));
05413229 5325 value_in_comment = reg << 1;
c19d1205
ZW		 5326 break;
5327
5328 case 'W':
d908c8af 5329 func (stream, "%ld", (long) (reg << 2));
05413229 5330 value_in_comment = reg << 2;
c19d1205
ZW		 5331 break;
5332
5333 case 'a':
5334 /* PC-relative address -- the bottom two
5335 bits of the address are dropped
5336 before the calculation. */
5337 info->print_address_func
5338 (((pc + 4) & ~3) + (reg << 2), info);
05413229 5339 value_in_comment = 0;
c19d1205
ZW		 5340 break;
5341
5342 case 'x':
d908c8af 5343 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 5344 break;
5345
c19d1205
ZW		 5346 case 'B':
5347 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6b5d3a4d 5348 info->print_address_func (reg * 2 + pc + 4, info);
05413229 5349 value_in_comment = 0;
c19d1205
ZW		 5350 break;
5351
5352 case 'c':
c22aaad1 5353 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 5354 break;
5355
5356 default:
5357 abort ();
5358 }
5359 }
5360 break;
5361
5362 case '\'':
5363 c++;
5364 if ((given & (1 << bitstart)) != 0)
5365 func (stream, "%c", *c);
5366 break;
5367
5368 case '?':
5369 ++c;
5370 if ((given & (1 << bitstart)) != 0)
5371 func (stream, "%c", *c++);
5372 else
5373 func (stream, "%c", *++c);
5374 break;
5375
5376 default:
5377 abort ();
5378 }
5379 }
5380 break;
5381
5382 default:
5383 abort ();
5384 }
5385 }
05413229
NC		 5386
5387 if (value_in_comment > 32 || value_in_comment < -16)
5388 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 5389 return;
c19d1205
ZW		 5390 }
5391
5392 /* No match. */
5393 abort ();
5394}
5395
62b3e311 5396/* Return the name of an V7M special register. */
fe56b6ce 5397
62b3e311
PB		 5398static const char *
5399psr_name (int regno)
5400{
5401 switch (regno)
5402 {
5403 case 0: return "APSR";
5404 case 1: return "IAPSR";
5405 case 2: return "EAPSR";
5406 case 3: return "PSR";
5407 case 5: return "IPSR";
5408 case 6: return "EPSR";
5409 case 7: return "IEPSR";
5410 case 8: return "MSP";
5411 case 9: return "PSP";
5412 case 16: return "PRIMASK";
5413 case 17: return "BASEPRI";
00bbc0bd 5414 case 18: return "BASEPRI_MAX";
62b3e311
PB		 5415 case 19: return "FAULTMASK";
5416 case 20: return "CONTROL";
5417 default: return "<unknown>";
5418 }
5419}
5420
4a5329c6
ZW		 5421/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
5422
5423static void
5424print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 5425{
6b5d3a4d 5426 const struct opcode32 *insn;
c19d1205
ZW		 5427 void *stream = info->stream;
5428 fprintf_ftype func = info->fprintf_func;
5429
16980d0b
JB		 5430 if (print_insn_coprocessor (pc, info, given, TRUE))
5431 return;
5432
5433 if (print_insn_neon (info, given, TRUE))
8f06b2d8
PB		 5434 return;
5435
c19d1205
ZW		 5436 for (insn = thumb32_opcodes; insn->assembler; insn++)
5437 if ((given & insn->mask) == insn->value)
5438 {
ff4a8d2b 5439 bfd_boolean is_unpredictable = FALSE;
05413229 5440 signed long value_in_comment = 0;
6b5d3a4d 5441 const char *c = insn->assembler;
05413229 5442
c19d1205
ZW		 5443 for (; *c; c++)
5444 {
5445 if (*c != '%')
5446 {
5447 func (stream, "%c", *c);
5448 continue;
5449 }
5450
5451 switch (*++c)
5452 {
5453 case '%':
5454 func (stream, "%%");
5455 break;
5456
c22aaad1
PB		 5457 case 'c':
5458 if (ifthen_state)
5459 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5460 break;
5461
5462 case 'x':
5463 if (ifthen_next_state)
5464 func (stream, "\t; unpredictable branch in IT block\n");
5465 break;
5466
5467 case 'X':
5468 if (ifthen_state)
5469 func (stream, "\t; unpredictable <IT:%s>",
5470 arm_conditional[IFTHEN_COND]);
5471 break;
5472
c19d1205
ZW		 5473 case 'I':
5474 {
5475 unsigned int imm12 = 0;
fe56b6ce 5476
c19d1205
ZW		 5477 imm12 |= (given & 0x000000ffu);
5478 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 5479 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 5480 func (stream, "#%u", imm12);
5481 value_in_comment = imm12;
c19d1205
ZW		 5482 }
5483 break;
5484
5485 case 'M':
5486 {
5487 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 5488
c19d1205
ZW		 5489 bits |= (given & 0x000000ffu);
5490 bits |= (given & 0x00007000u) >> 4;
5491 bits |= (given & 0x04000000u) >> 15;
5492 imm8 = (bits & 0x0ff);
5493 mod = (bits & 0xf00) >> 8;
5494 switch (mod)
5495 {
5496 case 0: imm = imm8; break;
c1e26897
NC		 5497 case 1: imm = ((imm8 << 16) | imm8); break;
5498 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
5499 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 5500 default:
5501 mod = (bits & 0xf80) >> 7;
5502 imm8 = (bits & 0x07f) | 0x80;
5503 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
5504 }
fe56b6ce
NC		 5505 func (stream, "#%u", imm);
5506 value_in_comment = imm;
c19d1205
ZW		 5507 }
5508 break;
43e65147 5509
c19d1205
ZW		 5510 case 'J':
5511 {
5512 unsigned int imm = 0;
fe56b6ce 5513
c19d1205
ZW		 5514 imm |= (given & 0x000000ffu);
5515 imm |= (given & 0x00007000u) >> 4;
5516 imm |= (given & 0x04000000u) >> 15;
5517 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 5518 func (stream, "#%u", imm);
5519 value_in_comment = imm;
c19d1205
ZW		 5520 }
5521 break;
5522
5523 case 'K':
5524 {
5525 unsigned int imm = 0;
fe56b6ce 5526
c19d1205
ZW		 5527 imm |= (given & 0x000f0000u) >> 16;
5528 imm |= (given & 0x00000ff0u) >> 0;
5529 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 5530 func (stream, "#%u", imm);
5531 value_in_comment = imm;
c19d1205
ZW		 5532 }
5533 break;
5534
74db7efb
NC		 5535 case 'H':
5536 {
5537 unsigned int imm = 0;
5538
5539 imm |= (given & 0x000f0000u) >> 4;
5540 imm |= (given & 0x00000fffu) >> 0;
5541 func (stream, "#%u", imm);
5542 value_in_comment = imm;
5543 }
5544 break;
5545
90ec0d68
MGD		 5546 case 'V':
5547 {
5548 unsigned int imm = 0;
5549
5550 imm |= (given & 0x00000fffu);
5551 imm |= (given & 0x000f0000u) >> 4;
5552 func (stream, "#%u", imm);
5553 value_in_comment = imm;
5554 }
5555 break;
5556
c19d1205
ZW		 5557 case 'S':
5558 {
5559 unsigned int reg = (given & 0x0000000fu);
5560 unsigned int stp = (given & 0x00000030u) >> 4;
5561 unsigned int imm = 0;
5562 imm |= (given & 0x000000c0u) >> 6;
5563 imm |= (given & 0x00007000u) >> 10;
5564
5565 func (stream, "%s", arm_regnames[reg]);
5566 switch (stp)
5567 {
5568 case 0:
5569 if (imm > 0)
5570 func (stream, ", lsl #%u", imm);
5571 break;
5572
5573 case 1:
5574 if (imm == 0)
5575 imm = 32;
5576 func (stream, ", lsr #%u", imm);
5577 break;
5578
5579 case 2:
5580 if (imm == 0)
5581 imm = 32;
5582 func (stream, ", asr #%u", imm);
5583 break;
5584
5585 case 3:
5586 if (imm == 0)
5587 func (stream, ", rrx");
5588 else
5589 func (stream, ", ror #%u", imm);
5590 }
5591 }
5592 break;
5593
5594 case 'a':
5595 {
5596 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 5597 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 5598 unsigned int op = (given & 0x00000f00) >> 8;
5599 unsigned int i12 = (given & 0x00000fff);
5600 unsigned int i8 = (given & 0x000000ff);
5601 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 5602 bfd_vma offset = 0;
c19d1205
ZW		 5603
5604 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 5605 if (U) /* 12-bit positive immediate offset. */
5606 {
5607 offset = i12;
5608 if (Rn != 15)
5609 value_in_comment = offset;
5610 }
5611 else if (Rn == 15) /* 12-bit negative immediate offset. */
5612 offset = - (int) i12;
5613 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 5614 {
5615 unsigned int Rm = (i8 & 0x0f);
5616 unsigned int sh = (i8 & 0x30) >> 4;
05413229 5617
c19d1205
ZW		 5618 func (stream, ", %s", arm_regnames[Rm]);
5619 if (sh)
5620 func (stream, ", lsl #%u", sh);
5621 func (stream, "]");
5622 break;
5623 }
5624 else switch (op)
5625 {
05413229 5626 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 5627 offset = i8;
5628 break;
5629
05413229 5630 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 5631 offset = -i8;
5632 break;
5633
05413229 5634 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 5635 offset = i8;
5636 writeback = TRUE;
5637 break;
5638
05413229 5639 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 5640 offset = -i8;
5641 writeback = TRUE;
5642 break;
5643
05413229 5644 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 5645 offset = i8;
5646 postind = TRUE;
5647 break;
5648
05413229 5649 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 5650 offset = -i8;
5651 postind = TRUE;
5652 break;
5653
5654 default:
5655 func (stream, ", <undefined>]");
5656 goto skip;
5657 }
5658
5659 if (postind)
d908c8af 5660 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 5661 else
5662 {
5663 if (offset)
d908c8af 5664 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 5665 func (stream, writeback ? "]!" : "]");
5666 }
5667
5668 if (Rn == 15)
5669 {
5670 func (stream, "\t; ");
5671 info->print_address_func (((pc + 4) & ~3) + offset, info);
5672 }
5673 }
5674 skip:
5675 break;
5676
5677 case 'A':
5678 {
c1e26897
NC		 5679 unsigned int U = ! NEGATIVE_BIT_SET;
5680 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 5681 unsigned int Rn = (given & 0x000f0000) >> 16;
5682 unsigned int off = (given & 0x000000ff);
5683
5684 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 5685
5686 if (PRE_BIT_SET)
c19d1205
ZW		 5687 {
5688 if (off || !U)
05413229
NC		 5689 {
5690 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
5691 value_in_comment = off * 4 * U ? 1 : -1;
5692 }
c19d1205
ZW		 5693 func (stream, "]");
5694 if (W)
5695 func (stream, "!");
5696 }
5697 else
5698 {
5699 func (stream, "], ");
5700 if (W)
05413229
NC		 5701 {
5702 func (stream, "#%c%u", U ? '+' : '-', off * 4);
5703 value_in_comment = off * 4 * U ? 1 : -1;
5704 }
c19d1205 5705 else
fe56b6ce
NC		 5706 {
5707 func (stream, "{%u}", off);
5708 value_in_comment = off;
5709 }
c19d1205
ZW		 5710 }
5711 }
5712 break;
5713
5714 case 'w':
5715 {
5716 unsigned int Sbit = (given & 0x01000000) >> 24;
5717 unsigned int type = (given & 0x00600000) >> 21;
05413229 5718
c19d1205
ZW		 5719 switch (type)
5720 {
5721 case 0: func (stream, Sbit ? "sb" : "b"); break;
5722 case 1: func (stream, Sbit ? "sh" : "h"); break;
5723 case 2:
5724 if (Sbit)
5725 func (stream, "??");
5726 break;
5727 case 3:
5728 func (stream, "??");
5729 break;
5730 }
5731 }
5732 break;
5733
5734 case 'm':
5735 {
5736 int started = 0;
5737 int reg;
5738
5739 func (stream, "{");
5740 for (reg = 0; reg < 16; reg++)
5741 if ((given & (1 << reg)) != 0)
5742 {
5743 if (started)
5744 func (stream, ", ");
5745 started = 1;
5746 func (stream, "%s", arm_regnames[reg]);
5747 }
5748 func (stream, "}");
5749 }
5750 break;
5751
5752 case 'E':
5753 {
5754 unsigned int msb = (given & 0x0000001f);
5755 unsigned int lsb = 0;
fe56b6ce 5756
c19d1205
ZW		 5757 lsb |= (given & 0x000000c0u) >> 6;
5758 lsb |= (given & 0x00007000u) >> 10;
5759 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
5760 }
5761 break;
5762
5763 case 'F':
5764 {
5765 unsigned int width = (given & 0x0000001f) + 1;
5766 unsigned int lsb = 0;
fe56b6ce 5767
c19d1205
ZW		 5768 lsb |= (given & 0x000000c0u) >> 6;
5769 lsb |= (given & 0x00007000u) >> 10;
5770 func (stream, "#%u, #%u", lsb, width);
5771 }
5772 break;
5773
5774 case 'b':
5775 {
5776 unsigned int S = (given & 0x04000000u) >> 26;
5777 unsigned int J1 = (given & 0x00002000u) >> 13;
5778 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 5779 bfd_vma offset = 0;
c19d1205
ZW		 5780
5781 offset |= !S << 20;
5782 offset |= J2 << 19;
5783 offset |= J1 << 18;
5784 offset |= (given & 0x003f0000) >> 4;
5785 offset |= (given & 0x000007ff) << 1;
5786 offset -= (1 << 20);
5787
5788 info->print_address_func (pc + 4 + offset, info);
5789 }
5790 break;
5791
5792 case 'B':
5793 {
5794 unsigned int S = (given & 0x04000000u) >> 26;
5795 unsigned int I1 = (given & 0x00002000u) >> 13;
5796 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 5797 bfd_vma offset = 0;
c19d1205
ZW		 5798
5799 offset |= !S << 24;
5800 offset |= !(I1 ^ S) << 23;
5801 offset |= !(I2 ^ S) << 22;
5802 offset |= (given & 0x03ff0000u) >> 4;
5803 offset |= (given & 0x000007ffu) << 1;
5804 offset -= (1 << 24);
36b0c57d 5805 offset += pc + 4;
c19d1205 5806
36b0c57d
PB		 5807 /* BLX target addresses are always word aligned. */
5808 if ((given & 0x00001000u) == 0)
5809 offset &= ~2u;
5810
5811 info->print_address_func (offset, info);
c19d1205
ZW		 5812 }
5813 break;
5814
5815 case 's':
5816 {
5817 unsigned int shift = 0;
fe56b6ce 5818
c19d1205
ZW		 5819 shift |= (given & 0x000000c0u) >> 6;
5820 shift |= (given & 0x00007000u) >> 10;
c1e26897 5821 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 5822 func (stream, ", asr #%u", shift);
5823 else if (shift)
5824 func (stream, ", lsl #%u", shift);
5825 /* else print nothing - lsl #0 */
5826 }
5827 break;
5828
5829 case 'R':
5830 {
5831 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 5832
c19d1205
ZW		 5833 if (rot)
5834 func (stream, ", ror #%u", rot * 8);
5835 }
5836 break;
5837
62b3e311 5838 case 'U':
43e65147 5839 if ((given & 0xf0) == 0x60)
62b3e311 5840 {
52e7f43d
RE		 5841 switch (given & 0xf)
5842 {
5843 case 0xf: func (stream, "sy"); break;
5844 default:
5845 func (stream, "#%d", (int) given & 0xf);
5846 break;
5847 }
62b3e311 5848 }
43e65147 5849 else
52e7f43d 5850 {
e797f7e0
MGD		 5851 const char * opt = data_barrier_option (given & 0xf);
5852 if (opt != NULL)
5853 func (stream, "%s", opt);
5854 else
5855 func (stream, "#%d", (int) given & 0xf);
52e7f43d 5856 }
62b3e311
PB		 5857 break;
5858
5859 case 'C':
5860 if ((given & 0xff) == 0)
5861 {
5862 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
5863 if (given & 0x800)
5864 func (stream, "f");
5865 if (given & 0x400)
5866 func (stream, "s");
5867 if (given & 0x200)
5868 func (stream, "x");
5869 if (given & 0x100)
5870 func (stream, "c");
5871 }
90ec0d68
MGD		 5872 else if ((given & 0x20) == 0x20)
5873 {
5874 char const* name;
5875 unsigned sysm = (given & 0xf00) >> 8;
5876
5877 sysm |= (given & 0x30);
5878 sysm |= (given & 0x00100000) >> 14;
5879 name = banked_regname (sysm);
43e65147 5880
90ec0d68
MGD		 5881 if (name != NULL)
5882 func (stream, "%s", name);
5883 else
d908c8af 5884 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 5885 }
62b3e311
PB		 5886 else
5887 {
d908c8af 5888 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 5889 }
5890 break;
5891
5892 case 'D':
90ec0d68
MGD		 5893 if (((given & 0xff) == 0)
5894 || ((given & 0x20) == 0x20))
5895 {
5896 char const* name;
5897 unsigned sm = (given & 0xf0000) >> 16;
5898
5899 sm |= (given & 0x30);
5900 sm |= (given & 0x00100000) >> 14;
5901 name = banked_regname (sm);
5902
5903 if (name != NULL)
5904 func (stream, "%s", name);
5905 else
d908c8af 5906 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 5907 }
62b3e311 5908 else
d908c8af 5909 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 5910 break;
5911
c19d1205
ZW		 5912 case '0': case '1': case '2': case '3': case '4':
5913 case '5': case '6': case '7': case '8': case '9':
5914 {
16980d0b
JB		 5915 int width;
5916 unsigned long val;
c19d1205 5917
16980d0b 5918 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 5919
c19d1205
ZW		 5920 switch (*c)
5921 {
05413229
NC		 5922 case 'd':
5923 func (stream, "%lu", val);
5924 value_in_comment = val;
5925 break;
ff4a8d2b 5926
f0fba320
RL		 5927 case 'D':
5928 func (stream, "%lu", val + 1);
5929 value_in_comment = val + 1;
5930 break;
5931
05413229
NC		 5932 case 'W':
5933 func (stream, "%lu", val * 4);
5934 value_in_comment = val * 4;
5935 break;
ff4a8d2b 5936
dd5181d5
KT		 5937 case 'S':
5938 if (val == 13)
5939 is_unpredictable = TRUE;
5940 /* Fall through. */
ff4a8d2b
NC		 5941 case 'R':
5942 if (val == 15)
5943 is_unpredictable = TRUE;
5944 /* Fall through. */
5945 case 'r':
5946 func (stream, "%s", arm_regnames[val]);
5947 break;
c19d1205
ZW		 5948
5949 case 'c':
c22aaad1 5950 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 5951 break;
5952
5953 case '\'':
c19d1205 5954 c++;
16980d0b
JB		 5955 if (val == ((1ul << width) - 1))
5956 func (stream, "%c", *c);
c19d1205 5957 break;
43e65147 5958
c19d1205 5959 case '`':
c19d1205 5960 c++;
16980d0b
JB		 5961 if (val == 0)
5962 func (stream, "%c", *c);
c19d1205
ZW		 5963 break;
5964
5965 case '?':
fe56b6ce 5966 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 5967 c += 1 << width;
c19d1205 5968 break;
43e65147 5969
0bb027fd
RR		 5970 case 'x':
5971 func (stream, "0x%lx", val & 0xffffffffUL);
5972 break;
c19d1205
ZW		 5973
5974 default:
5975 abort ();
5976 }
5977 }
5978 break;
5979
32a94698
NC		 5980 case 'L':
5981 /* PR binutils/12534
5982 If we have a PC relative offset in an LDRD or STRD
5983 instructions then display the decoded address. */
5984 if (((given >> 16) & 0xf) == 0xf)
5985 {
5986 bfd_vma offset = (given & 0xff) * 4;
5987
5988 if ((given & (1 << 23)) == 0)
5989 offset = - offset;
5990 func (stream, "\t; ");
5991 info->print_address_func ((pc & ~3) + 4 + offset, info);
5992 }
5993 break;
5994
c19d1205
ZW		 5995 default:
5996 abort ();
5997 }
5998 }
05413229
NC		 5999
6000 if (value_in_comment > 32 || value_in_comment < -16)
6001 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 6002
6003 if (is_unpredictable)
6004 func (stream, UNPREDICTABLE_INSTRUCTION);
6005
4a5329c6 6006 return;
c19d1205 6007 }
252b5132 6008
58efb6c0 6009 /* No match. */
252b5132
RH		 6010 abort ();
6011}
6012
e821645d
DJ		 6013/* Print data bytes on INFO->STREAM. */
6014
6015static void
fe56b6ce
NC		 6016print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
6017 struct disassemble_info *info,
e821645d
DJ		 6018 long given)
6019{
6020 switch (info->bytes_per_chunk)
6021 {
6022 case 1:
6023 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
6024 break;
6025 case 2:
6026 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
6027 break;
6028 case 4:
6029 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
6030 break;
6031 default:
6032 abort ();
6033 }
6034}
6035
22a398e1 6036/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 6037 being displayed in symbol relative addresses.
6038
6039 Also disallow private symbol, with __tagsym$$ prefix,
6040 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 6041
6042bfd_boolean
6043arm_symbol_is_valid (asymbol * sym,
6044 struct disassemble_info * info ATTRIBUTE_UNUSED)
6045{
6046 const char * name;
43e65147 6047
22a398e1
NC		 6048 if (sym == NULL)
6049 return FALSE;
6050
6051 name = bfd_asymbol_name (sym);
6052
d8282f0e 6053 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 6054}
6055
58efb6c0 6056/* Parse an individual disassembler option. */
baf0cc5e 6057
a3d9c82d 6058void
4a5329c6 6059parse_arm_disassembler_option (char *option)
dd92f639 6060{
01c7f630 6061 if (option == NULL)
dd92f639 6062 return;
b34976b6 6063
0112cd26 6064 if (CONST_STRNEQ (option, "reg-names-"))
dd92f639 6065 {
58efb6c0 6066 int i;
b34976b6 6067
01c7f630 6068 option += 10;
58efb6c0
NC		 6069
6070 for (i = NUM_ARM_REGNAMES; i--;)
31e0f3cd 6071 if (strneq (option, regnames[i].name, strlen (regnames[i].name)))
58efb6c0
NC		 6072 {
6073 regname_selected = i;
6074 break;
6075 }
b34976b6 6076
58efb6c0 6077 if (i < 0)
31e0f3cd 6078 /* XXX - should break 'option' at following delimiter. */
58efb6c0 6079 fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
dd92f639 6080 }
0112cd26 6081 else if (CONST_STRNEQ (option, "force-thumb"))
01c7f630 6082 force_thumb = 1;
0112cd26 6083 else if (CONST_STRNEQ (option, "no-force-thumb"))
01c7f630 6084 force_thumb = 0;
dd92f639 6085 else
31e0f3cd 6086 /* XXX - should break 'option' at following delimiter. */
58efb6c0 6087 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
b34976b6 6088
dd92f639
NC		 6089 return;
6090}
6091
31e0f3cd
NC		 6092/* Parse the string of disassembler options, spliting it at whitespaces
6093 or commas. (Whitespace separators supported for backwards compatibility). */
baf0cc5e 6094
01c7f630 6095static void
4a5329c6 6096parse_disassembler_options (char *options)
01c7f630 6097{
01c7f630
NC		 6098 if (options == NULL)
6099 return;
6100
31e0f3cd 6101 while (*options)
01c7f630 6102 {
31e0f3cd
NC		 6103 parse_arm_disassembler_option (options);
6104
6105 /* Skip forward to next seperator. */
6106 while ((*options) && (! ISSPACE (*options)) && (*options != ','))
6107 ++ options;
6108 /* Skip forward past seperators. */
6109 while (ISSPACE (*options) || (*options == ','))
43e65147 6110 ++ options;
01c7f630 6111 }
01c7f630
NC		 6112}
6113
5bc5ae88
RL		 6114static bfd_boolean
6115mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6116 enum map_type *map_symbol);
6117
c22aaad1
PB		 6118/* Search back through the insn stream to determine if this instruction is
6119 conditionally executed. */
fe56b6ce 6120
c22aaad1 6121static void
fe56b6ce
NC		 6122find_ifthen_state (bfd_vma pc,
6123 struct disassemble_info *info,
c22aaad1
PB		 6124 bfd_boolean little)
6125{
6126 unsigned char b[2];
6127 unsigned int insn;
6128 int status;
6129 /* COUNT is twice the number of instructions seen. It will be odd if we
6130 just crossed an instruction boundary. */
6131 int count;
6132 int it_count;
6133 unsigned int seen_it;
6134 bfd_vma addr;
6135
6136 ifthen_address = pc;
6137 ifthen_state = 0;
6138
6139 addr = pc;
6140 count = 1;
6141 it_count = 0;
6142 seen_it = 0;
6143 /* Scan backwards looking for IT instructions, keeping track of where
6144 instruction boundaries are. We don't know if something is actually an
6145 IT instruction until we find a definite instruction boundary. */
6146 for (;;)
6147 {
fe56b6ce 6148 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 6149 {
6150 /* A symbol must be on an instruction boundary, and will not
6151 be within an IT block. */
6152 if (seen_it && (count & 1))
6153 break;
6154
6155 return;
6156 }
6157 addr -= 2;
fe56b6ce 6158 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 6159 if (status)
6160 return;
6161
6162 if (little)
6163 insn = (b[0]) | (b[1] << 8);
6164 else
6165 insn = (b[1]) | (b[0] << 8);
6166 if (seen_it)
6167 {
6168 if ((insn & 0xf800) < 0xe800)
6169 {
6170 /* Addr + 2 is an instruction boundary. See if this matches
6171 the expected boundary based on the position of the last
6172 IT candidate. */
6173 if (count & 1)
6174 break;
6175 seen_it = 0;
6176 }
6177 }
6178 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
6179 {
5bc5ae88
RL		 6180 enum map_type type = MAP_ARM;
6181 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
6182
6183 if (!found || (found && type == MAP_THUMB))
6184 {
6185 /* This could be an IT instruction. */
6186 seen_it = insn;
6187 it_count = count >> 1;
6188 }
c22aaad1
PB		 6189 }
6190 if ((insn & 0xf800) >= 0xe800)
6191 count++;
6192 else
6193 count = (count + 2) | 1;
6194 /* IT blocks contain at most 4 instructions. */
6195 if (count >= 8 && !seen_it)
6196 return;
6197 }
6198 /* We found an IT instruction. */
6199 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
6200 if ((ifthen_state & 0xf) == 0)
6201 ifthen_state = 0;
6202}
6203
b0e28b39
DJ		 6204/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
6205 mapping symbol. */
6206
6207static int
6208is_mapping_symbol (struct disassemble_info *info, int n,
6209 enum map_type *map_type)
6210{
6211 const char *name;
6212
6213 name = bfd_asymbol_name (info->symtab[n]);
6214 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
6215 && (name[2] == 0 || name[2] == '.'))
6216 {
6217 *map_type = ((name[1] == 'a') ? MAP_ARM
6218 : (name[1] == 't') ? MAP_THUMB
6219 : MAP_DATA);
6220 return TRUE;
6221 }
6222
6223 return FALSE;
6224}
6225
6226/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
6227 Returns nonzero if *MAP_TYPE was set. */
6228
6229static int
6230get_map_sym_type (struct disassemble_info *info,
6231 int n,
6232 enum map_type *map_type)
6233{
6234 /* If the symbol is in a different section, ignore it. */
6235 if (info->section != NULL && info->section != info->symtab[n]->section)
6236 return FALSE;
6237
6238 return is_mapping_symbol (info, n, map_type);
6239}
6240
6241/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 6242 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 6243
6244static int
fe56b6ce
NC		 6245get_sym_code_type (struct disassemble_info *info,
6246 int n,
e821645d 6247 enum map_type *map_type)
2087ad84
PB		 6248{
6249 elf_symbol_type *es;
6250 unsigned int type;
b0e28b39
DJ		 6251
6252 /* If the symbol is in a different section, ignore it. */
6253 if (info->section != NULL && info->section != info->symtab[n]->section)
6254 return FALSE;
2087ad84 6255
e821645d 6256 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 6257 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6258
6259 /* If the symbol has function type then use that. */
34e77a92 6260 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 6261 {
35fc36a8
RS		 6262 if (ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym) == ST_BRANCH_TO_THUMB)
6263 *map_type = MAP_THUMB;
6264 else
6265 *map_type = MAP_ARM;
2087ad84
PB		 6266 return TRUE;
6267 }
6268
2087ad84
PB		 6269 return FALSE;
6270}
6271
5bc5ae88
RL		 6272/* Search the mapping symbol state for instruction at pc. This is only
6273 applicable for elf target.
6274
6275 There is an assumption Here, info->private_data contains the correct AND
6276 up-to-date information about current scan process. The information will be
6277 used to speed this search process.
6278
6279 Return TRUE if the mapping state can be determined, and map_symbol
6280 will be updated accordingly. Otherwise, return FALSE. */
6281
6282static bfd_boolean
6283mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6284 enum map_type *map_symbol)
6285{
6286 bfd_vma addr;
6287 int n, start = 0;
6288 bfd_boolean found = FALSE;
6289 enum map_type type = MAP_ARM;
6290 struct arm_private_data *private_data;
6291
6292 if (info->private_data == NULL || info->symtab_size == 0
6293 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
6294 return FALSE;
6295
6296 private_data = info->private_data;
6297 if (pc == 0)
6298 start = 0;
6299 else
6300 start = private_data->last_mapping_sym;
6301
6302 start = (start == -1)? 0 : start;
6303 addr = bfd_asymbol_value (info->symtab[start]);
6304
6305 if (pc >= addr)
6306 {
6307 if (get_map_sym_type (info, start, &type))
6308 found = TRUE;
6309 }
6310 else
6311 {
6312 for (n = start - 1; n >= 0; n--)
6313 {
6314 if (get_map_sym_type (info, n, &type))
6315 {
6316 found = TRUE;
6317 break;
6318 }
6319 }
6320 }
6321
6322 /* No mapping symbols were found. A leading $d may be
6323 omitted for sections which start with data; but for
6324 compatibility with legacy and stripped binaries, only
6325 assume the leading $d if there is at least one mapping
6326 symbol in the file. */
6327 if (!found && private_data->has_mapping_symbols == 1)
6328 {
6329 type = MAP_DATA;
6330 found = TRUE;
6331 }
6332
6333 *map_symbol = type;
6334 return found;
6335}
6336
0313a2b8
NC		 6337/* Given a bfd_mach_arm_XXX value, this function fills in the fields
6338 of the supplied arm_feature_set structure with bitmasks indicating
6339 the support base architectures and coprocessor extensions.
6340
6341 FIXME: This could more efficiently implemented as a constant array,
6342 although it would also be less robust. */
6343
6344static void
6345select_arm_features (unsigned long mach,
6346 arm_feature_set * features)
6347{
1af1dd51
MW		 6348#undef ARM_SET_FEATURES
6349#define ARM_SET_FEATURES(FSET) \
6350 { \
6351 const arm_feature_set fset = FSET; \
6352 arm_feature_set tmp = ARM_FEATURE (0, 0, FPU_FPA) ; \
6353 ARM_MERGE_FEATURE_SETS (*features, tmp, fset); \
6354 }
823d2571 6355
0313a2b8
NC		 6356 switch (mach)
6357 {
1af1dd51
MW		 6358 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
6359 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
6360 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
6361 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
6362 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
6363 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
6364 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
6365 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
6366 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
6367 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
6368 case bfd_mach_arm_ep9312:
6369 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
6370 ARM_CEXT_MAVERICK | FPU_MAVERICK));
6371 break;
6372 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
6373 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
0313a2b8
NC		 6374 /* If the machine type is unknown allow all
6375 architecture types and all extensions. */
1af1dd51 6376 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
0313a2b8
NC		 6377 default:
6378 abort ();
6379 }
1af1dd51
MW		 6380
6381#undef ARM_SET_FEATURES
0313a2b8
NC		 6382}
6383
6384
58efb6c0
NC		 6385/* NOTE: There are no checks in these routines that
6386 the relevant number of data bytes exist. */
baf0cc5e 6387
58efb6c0 6388static int
4a5329c6 6389print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 6390{
c19d1205
ZW		 6391 unsigned char b[4];
6392 long given;
6393 int status;
e821645d 6394 int is_thumb = FALSE;
b0e28b39 6395 int is_data = FALSE;
bd2e2557 6396 int little_code;
e821645d 6397 unsigned int size = 4;
4a5329c6 6398 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 6399 bfd_boolean found = FALSE;
b0e28b39 6400 struct arm_private_data *private_data;
58efb6c0 6401
dd92f639
NC		 6402 if (info->disassembler_options)
6403 {
6404 parse_disassembler_options (info->disassembler_options);
b34976b6 6405
58efb6c0 6406 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 6407 info->disassembler_options = NULL;
6408 }
b34976b6 6409
0313a2b8
NC		 6410 /* PR 10288: Control which instructions will be disassembled. */
6411 if (info->private_data == NULL)
6412 {
b0e28b39 6413 static struct arm_private_data private;
0313a2b8
NC		 6414
6415 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
6416 /* If the user did not use the -m command line switch then default to
6417 disassembling all types of ARM instruction.
43e65147 6418
0313a2b8
NC		 6419 The info->mach value has to be ignored as this will be based on
6420 the default archictecture for the target and/or hints in the notes
6421 section, but it will never be greater than the current largest arm
6422 machine value (iWMMXt2), which is only equivalent to the V5TE
6423 architecture. ARM architectures have advanced beyond the machine
6424 value encoding, and these newer architectures would be ignored if
6425 the machine value was used.
6426
6427 Ie the -m switch is used to restrict which instructions will be
6428 disassembled. If it is necessary to use the -m switch to tell
6429 objdump that an ARM binary is being disassembled, eg because the
6430 input is a raw binary file, but it is also desired to disassemble
6431 all ARM instructions then use "-marm". This will select the
6432 "unknown" arm architecture which is compatible with any ARM
6433 instruction. */
6434 info->mach = bfd_mach_arm_unknown;
6435
6436 /* Compute the architecture bitmask from the machine number.
6437 Note: This assumes that the machine number will not change
6438 during disassembly.... */
b0e28b39 6439 select_arm_features (info->mach, & private.features);
0313a2b8 6440
b0e28b39 6441 private.has_mapping_symbols = -1;
1fbaefec
PB		 6442 private.last_mapping_sym = -1;
6443 private.last_mapping_addr = 0;
b0e28b39
DJ		 6444
6445 info->private_data = & private;
0313a2b8 6446 }
b0e28b39
DJ		 6447
6448 private_data = info->private_data;
6449
bd2e2557
SS		 6450 /* Decide if our code is going to be little-endian, despite what the
6451 function argument might say. */
6452 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
6453
b0e28b39
DJ		 6454 /* For ELF, consult the symbol table to determine what kind of code
6455 or data we have. */
8977d4b2 6456 if (info->symtab_size != 0
e821645d
DJ		 6457 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
6458 {
6459 bfd_vma addr;
b0e28b39 6460 int n, start;
e821645d 6461 int last_sym = -1;
b0e28b39 6462 enum map_type type = MAP_ARM;
e821645d 6463
e821645d
DJ		 6464 /* Start scanning at the start of the function, or wherever
6465 we finished last time. */
6750a3a7
NC		 6466 /* PR 14006. When the address is 0 we are either at the start of the
6467 very first function, or else the first function in a new, unlinked
6468 executable section (eg because uf -ffunction-sections). Either way
6469 start scanning from the beginning of the symbol table, not where we
6470 left off last time. */
6471 if (pc == 0)
6472 start = 0;
6473 else
6474 {
6475 start = info->symtab_pos + 1;
6476 if (start < private_data->last_mapping_sym)
6477 start = private_data->last_mapping_sym;
6478 }
b0e28b39 6479 found = FALSE;
e821645d 6480
b0e28b39
DJ		 6481 /* First, look for mapping symbols. */
6482 if (private_data->has_mapping_symbols != 0)
e821645d 6483 {
b0e28b39
DJ		 6484 /* Scan up to the location being disassembled. */
6485 for (n = start; n < info->symtab_size; n++)
6486 {
6487 addr = bfd_asymbol_value (info->symtab[n]);
6488 if (addr > pc)
6489 break;
6490 if (get_map_sym_type (info, n, &type))
6491 {
6492 last_sym = n;
6493 found = TRUE;
6494 }
6495 }
6496
6497 if (!found)
6498 {
6499 /* No mapping symbol found at this address. Look backwards
cc643b88 6500 for a preceding one. */
b0e28b39
DJ		 6501 for (n = start - 1; n >= 0; n--)
6502 {
6503 if (get_map_sym_type (info, n, &type))
6504 {
6505 last_sym = n;
6506 found = TRUE;
6507 break;
6508 }
6509 }
6510 }
6511
6512 if (found)
6513 private_data->has_mapping_symbols = 1;
6514
6515 /* No mapping symbols were found. A leading $d may be
6516 omitted for sections which start with data; but for
6517 compatibility with legacy and stripped binaries, only
6518 assume the leading $d if there is at least one mapping
6519 symbol in the file. */
6520 if (!found && private_data->has_mapping_symbols == -1)
e821645d 6521 {
b0e28b39
DJ		 6522 /* Look for mapping symbols, in any section. */
6523 for (n = 0; n < info->symtab_size; n++)
6524 if (is_mapping_symbol (info, n, &type))
6525 {
6526 private_data->has_mapping_symbols = 1;
6527 break;
6528 }
6529 if (private_data->has_mapping_symbols == -1)
6530 private_data->has_mapping_symbols = 0;
6531 }
6532
6533 if (!found && private_data->has_mapping_symbols == 1)
6534 {
6535 type = MAP_DATA;
e821645d
DJ		 6536 found = TRUE;
6537 }
6538 }
6539
b0e28b39
DJ		 6540 /* Next search for function symbols to separate ARM from Thumb
6541 in binaries without mapping symbols. */
e821645d
DJ		 6542 if (!found)
6543 {
b0e28b39
DJ		 6544 /* Scan up to the location being disassembled. */
6545 for (n = start; n < info->symtab_size; n++)
e821645d 6546 {
b0e28b39
DJ		 6547 addr = bfd_asymbol_value (info->symtab[n]);
6548 if (addr > pc)
6549 break;
6550 if (get_sym_code_type (info, n, &type))
e821645d
DJ		 6551 {
6552 last_sym = n;
6553 found = TRUE;
b0e28b39
DJ		 6554 }
6555 }
6556
6557 if (!found)
6558 {
6559 /* No mapping symbol found at this address. Look backwards
cc643b88 6560 for a preceding one. */
b0e28b39
DJ		 6561 for (n = start - 1; n >= 0; n--)
6562 {
6563 if (get_sym_code_type (info, n, &type))
6564 {
6565 last_sym = n;
6566 found = TRUE;
6567 break;
6568 }
e821645d
DJ		 6569 }
6570 }
6571 }
6572
1fbaefec
PB		 6573 private_data->last_mapping_sym = last_sym;
6574 private_data->last_type = type;
6575 is_thumb = (private_data->last_type == MAP_THUMB);
6576 is_data = (private_data->last_type == MAP_DATA);
b34976b6 6577
e821645d
DJ		 6578 /* Look a little bit ahead to see if we should print out
6579 two or four bytes of data. If there's a symbol,
6580 mapping or otherwise, after two bytes then don't
6581 print more. */
6582 if (is_data)
6583 {
6584 size = 4 - (pc & 3);
6585 for (n = last_sym + 1; n < info->symtab_size; n++)
6586 {
6587 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 6588 if (addr > pc
6589 && (info->section == NULL
6590 || info->section == info->symtab[n]->section))
e821645d
DJ		 6591 {
6592 if (addr - pc < size)
6593 size = addr - pc;
6594 break;
6595 }
6596 }
6597 /* If the next symbol is after three bytes, we need to
6598 print only part of the data, so that we can use either
6599 .byte or .short. */
6600 if (size == 3)
6601 size = (pc & 1) ? 1 : 2;
6602 }
6603 }
6604
6605 if (info->symbols != NULL)
252b5132 6606 {
5876e06d
NC		 6607 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
6608 {
2f0ca46a 6609 coff_symbol_type * cs;
b34976b6 6610
5876e06d
NC		 6611 cs = coffsymbol (*info->symbols);
6612 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
6613 || cs->native->u.syment.n_sclass == C_THUMBSTAT
6614 || cs->native->u.syment.n_sclass == C_THUMBLABEL
6615 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
6616 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
6617 }
e821645d
DJ		 6618 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
6619 && !found)
5876e06d 6620 {
2087ad84
PB		 6621 /* If no mapping symbol has been found then fall back to the type
6622 of the function symbol. */
e821645d
DJ		 6623 elf_symbol_type * es;
6624 unsigned int type;
2087ad84 6625
e821645d
DJ		 6626 es = *(elf_symbol_type **)(info->symbols);
6627 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 6628
35fc36a8
RS		 6629 is_thumb = ((ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym)
6630 == ST_BRANCH_TO_THUMB)
6631 || type == STT_ARM_16BIT);
5876e06d 6632 }
e49d43ff
TG		 6633 else if (bfd_asymbol_flavour (*info->symbols)
6634 == bfd_target_mach_o_flavour)
6635 {
6636 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
6637
6638 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
6639 }
5876e06d 6640 }
b34976b6 6641
e821645d
DJ		 6642 if (force_thumb)
6643 is_thumb = TRUE;
6644
b8f9ee44
CL		 6645 if (is_data)
6646 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6647 else
6648 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6649
c19d1205 6650 info->bytes_per_line = 4;
252b5132 6651
1316c8b3
NC		 6652 /* PR 10263: Disassemble data if requested to do so by the user. */
6653 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 6654 {
6655 int i;
6656
1316c8b3 6657 /* Size was already set above. */
e821645d
DJ		 6658 info->bytes_per_chunk = size;
6659 printer = print_insn_data;
6660
fe56b6ce 6661 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 6662 given = 0;
6663 if (little)
6664 for (i = size - 1; i >= 0; i--)
6665 given = b[i] | (given << 8);
6666 else
6667 for (i = 0; i < (int) size; i++)
6668 given = b[i] | (given << 8);
6669 }
6670 else if (!is_thumb)
252b5132 6671 {
c19d1205
ZW		 6672 /* In ARM mode endianness is a straightforward issue: the instruction
6673 is four bytes long and is either ordered 0123 or 3210. */
6674 printer = print_insn_arm;
6675 info->bytes_per_chunk = 4;
4a5329c6 6676 size = 4;
c19d1205 6677
0313a2b8 6678 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 6679 if (little_code)
c19d1205
ZW		 6680 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
6681 else
6682 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
252b5132 6683 }
58efb6c0 6684 else
252b5132 6685 {
c19d1205
ZW		 6686 /* In Thumb mode we have the additional wrinkle of two
6687 instruction lengths. Fortunately, the bits that determine
6688 the length of the current instruction are always to be found
6689 in the first two bytes. */
4a5329c6 6690 printer = print_insn_thumb16;
c19d1205 6691 info->bytes_per_chunk = 2;
4a5329c6
ZW		 6692 size = 2;
6693
fe56b6ce 6694 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 6695 if (little_code)
9a2ff3f5
AM		 6696 given = (b[0]) | (b[1] << 8);
6697 else
6698 given = (b[1]) | (b[0] << 8);
6699
c19d1205 6700 if (!status)
252b5132 6701 {
c19d1205
ZW		 6702 /* These bit patterns signal a four-byte Thumb
6703 instruction. */
6704 if ((given & 0xF800) == 0xF800
6705 || (given & 0xF800) == 0xF000
6706 || (given & 0xF800) == 0xE800)
252b5132 6707 {
0313a2b8 6708 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 6709 if (little_code)
c19d1205 6710 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 6711 else
c19d1205
ZW		 6712 given = (b[1]) | (b[0] << 8) | (given << 16);
6713
6714 printer = print_insn_thumb32;
4a5329c6 6715 size = 4;
252b5132 6716 }
252b5132 6717 }
c22aaad1
PB		 6718
6719 if (ifthen_address != pc)
0313a2b8 6720 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 6721
6722 if (ifthen_state)
6723 {
6724 if ((ifthen_state & 0xf) == 0x8)
6725 ifthen_next_state = 0;
6726 else
6727 ifthen_next_state = (ifthen_state & 0xe0)
6728 | ((ifthen_state & 0xf) << 1);
6729 }
252b5132 6730 }
b34976b6 6731
c19d1205
ZW		 6732 if (status)
6733 {
6734 info->memory_error_func (status, pc, info);
6735 return -1;
6736 }
6a56ec7e
NC		 6737 if (info->flags & INSN_HAS_RELOC)
6738 /* If the instruction has a reloc associated with it, then
6739 the offset field in the instruction will actually be the
6740 addend for the reloc. (We are using REL type relocs).
6741 In such cases, we can ignore the pc when computing
6742 addresses, since the addend is not currently pc-relative. */
6743 pc = 0;
b34976b6 6744
4a5329c6 6745 printer (pc, info, given);
c22aaad1
PB		 6746
6747 if (is_thumb)
6748 {
6749 ifthen_state = ifthen_next_state;
6750 ifthen_address += size;
6751 }
4a5329c6 6752 return size;
252b5132
RH		 6753}
6754
6755int
4a5329c6 6756print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 6757{
bd2e2557
SS		 6758 /* Detect BE8-ness and record it in the disassembler info. */
6759 if (info->flavour == bfd_target_elf_flavour
6760 && info->section != NULL
6761 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
6762 info->endian_code = BFD_ENDIAN_LITTLE;
6763
b34976b6 6764 return print_insn (pc, info, FALSE);
58efb6c0 6765}
01c7f630 6766
58efb6c0 6767int
4a5329c6 6768print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 6769{
b34976b6 6770 return print_insn (pc, info, TRUE);
58efb6c0 6771}
252b5132 6772
58efb6c0 6773void
4a5329c6 6774print_arm_disassembler_options (FILE *stream)
58efb6c0
NC		 6775{
6776 int i;
252b5132 6777
58efb6c0
NC		 6778 fprintf (stream, _("\n\
6779The following ARM specific disassembler options are supported for use with\n\
6780the -M switch:\n"));
b34976b6 6781
58efb6c0
NC		 6782 for (i = NUM_ARM_REGNAMES; i--;)
6783 fprintf (stream, " reg-names-%s %*c%s\n",
6784 regnames[i].name,
d5b2f4d6 6785 (int)(14 - strlen (regnames[i].name)), ' ',
58efb6c0
NC		 6786 regnames[i].description);
6787
6788 fprintf (stream, " force-thumb Assume all insns are Thumb insns\n");
cc643b88 6789 fprintf (stream, " no-force-thumb Examine preceding label to determine an insn's type\n\n");
252b5132 6790}
GDB Binutils - Deliverables
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