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[PATCH 51/57][Arm][OBJDUMP] Add support for MVE instructions: lctp, letp, wlstp and...
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
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252b5132 1/* Instruction printing code for the ARM
82704155 2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
143275ea 24#include <assert.h>
2fbad815 25
6394c606 26#include "disassemble.h"
2fbad815 27#include "opcode/arm.h"
252b5132 28#include "opintl.h"
31e0f3cd 29#include "safe-ctype.h"
65b48a81 30#include "libiberty.h"
0dbde4cf 31#include "floatformat.h"
252b5132 32
baf0cc5e 33/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 34#include "coff/internal.h"
35#include "libcoff.h"
2d5d5a8f 36#include "bfd.h"
252b5132
RH		 37#include "elf-bfd.h"
38#include "elf/internal.h"
39#include "elf/arm.h"
e49d43ff 40#include "mach-o.h"
252b5132 41
6b5d3a4d 42/* FIXME: Belongs in global header. */
01c7f630 43#ifndef strneq
58efb6c0
NC		 44#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
45#endif
46
1fbaefec
PB		 47/* Cached mapping symbol state. */
48enum map_type
49{
50 MAP_ARM,
51 MAP_THUMB,
52 MAP_DATA
53};
54
b0e28b39
DJ		 55struct arm_private_data
56{
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features;
59
1fbaefec
PB		 60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type;
62
63 /* Tracking symbol table information */
64 int last_mapping_sym;
796d6298
TC		 65
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset;
1fbaefec 68 bfd_vma last_mapping_addr;
b0e28b39
DJ		 69};
70
73cd51e5
AV		 71enum mve_instructions
72{
143275ea
AV		 73 MVE_VPST,
74 MVE_VPT_FP_T1,
75 MVE_VPT_FP_T2,
76 MVE_VPT_VEC_T1,
77 MVE_VPT_VEC_T2,
78 MVE_VPT_VEC_T3,
79 MVE_VPT_VEC_T4,
80 MVE_VPT_VEC_T5,
81 MVE_VPT_VEC_T6,
82 MVE_VCMP_FP_T1,
83 MVE_VCMP_FP_T2,
84 MVE_VCMP_VEC_T1,
85 MVE_VCMP_VEC_T2,
86 MVE_VCMP_VEC_T3,
87 MVE_VCMP_VEC_T4,
88 MVE_VCMP_VEC_T5,
89 MVE_VCMP_VEC_T6,
9743db03
AV		 90 MVE_VDUP,
91 MVE_VEOR,
92 MVE_VFMAS_FP_SCALAR,
93 MVE_VFMA_FP_SCALAR,
94 MVE_VFMA_FP,
95 MVE_VFMS_FP,
96 MVE_VHADD_T1,
97 MVE_VHADD_T2,
98 MVE_VHSUB_T1,
99 MVE_VHSUB_T2,
100 MVE_VRHADD,
04d54ace
AV		 101 MVE_VLD2,
102 MVE_VLD4,
103 MVE_VST2,
104 MVE_VST4,
aef6d006
AV		 105 MVE_VLDRB_T1,
106 MVE_VLDRH_T2,
107 MVE_VLDRB_T5,
108 MVE_VLDRH_T6,
109 MVE_VLDRW_T7,
110 MVE_VSTRB_T1,
111 MVE_VSTRH_T2,
112 MVE_VSTRB_T5,
113 MVE_VSTRH_T6,
114 MVE_VSTRW_T7,
ef1576a1
AV		 115 MVE_VLDRB_GATHER_T1,
116 MVE_VLDRH_GATHER_T2,
117 MVE_VLDRW_GATHER_T3,
118 MVE_VLDRD_GATHER_T4,
119 MVE_VLDRW_GATHER_T5,
120 MVE_VLDRD_GATHER_T6,
121 MVE_VSTRB_SCATTER_T1,
122 MVE_VSTRH_SCATTER_T2,
123 MVE_VSTRW_SCATTER_T3,
124 MVE_VSTRD_SCATTER_T4,
125 MVE_VSTRW_SCATTER_T5,
126 MVE_VSTRD_SCATTER_T6,
bf0b396d
AV		 127 MVE_VCVT_FP_FIX_VEC,
128 MVE_VCVT_BETWEEN_FP_INT,
129 MVE_VCVT_FP_HALF_FP,
130 MVE_VCVT_FROM_FP_TO_INT,
131 MVE_VRINT_FP,
c507f10b
AV		 132 MVE_VMOV_HFP_TO_GP,
133 MVE_VMOV_GP_TO_VEC_LANE,
134 MVE_VMOV_IMM_TO_VEC,
135 MVE_VMOV_VEC_TO_VEC,
136 MVE_VMOV2_VEC_LANE_TO_GP,
137 MVE_VMOV2_GP_TO_VEC_LANE,
138 MVE_VMOV_VEC_LANE_TO_GP,
139 MVE_VMVN_IMM,
140 MVE_VMVN_REG,
141 MVE_VORR_IMM,
142 MVE_VORR_REG,
143 MVE_VORN,
144 MVE_VBIC_IMM,
145 MVE_VBIC_REG,
146 MVE_VMOVX,
14925797
AV		 147 MVE_VMOVL,
148 MVE_VMOVN,
149 MVE_VMULL_INT,
150 MVE_VMULL_POLY,
151 MVE_VQDMULL_T1,
152 MVE_VQDMULL_T2,
153 MVE_VQMOVN,
154 MVE_VQMOVUN,
d3b63143
AV		 155 MVE_VADDV,
156 MVE_VMLADAV_T1,
157 MVE_VMLADAV_T2,
158 MVE_VMLALDAV,
159 MVE_VMLAS,
160 MVE_VADDLV,
161 MVE_VMLSDAV_T1,
162 MVE_VMLSDAV_T2,
163 MVE_VMLSLDAV,
164 MVE_VRMLALDAVH,
165 MVE_VRMLSLDAVH,
166 MVE_VQDMLADH,
167 MVE_VQRDMLADH,
168 MVE_VQDMLAH,
169 MVE_VQRDMLAH,
170 MVE_VQDMLASH,
171 MVE_VQRDMLASH,
172 MVE_VQDMLSDH,
173 MVE_VQRDMLSDH,
174 MVE_VQDMULH_T1,
175 MVE_VQRDMULH_T2,
176 MVE_VQDMULH_T3,
177 MVE_VQRDMULH_T4,
1c8f2df8
AV		 178 MVE_VDDUP,
179 MVE_VDWDUP,
180 MVE_VIWDUP,
181 MVE_VIDUP,
897b9bbc
AV		 182 MVE_VCADD_FP,
183 MVE_VCADD_VEC,
184 MVE_VHCADD,
185 MVE_VCMLA_FP,
186 MVE_VCMUL_FP,
ed63aa17
AV		 187 MVE_VQRSHL_T1,
188 MVE_VQRSHL_T2,
189 MVE_VQRSHRN,
190 MVE_VQRSHRUN,
191 MVE_VQSHL_T1,
192 MVE_VQSHL_T2,
193 MVE_VQSHLU_T3,
194 MVE_VQSHL_T4,
195 MVE_VQSHRN,
196 MVE_VQSHRUN,
197 MVE_VRSHL_T1,
198 MVE_VRSHL_T2,
199 MVE_VRSHR,
200 MVE_VRSHRN,
201 MVE_VSHL_T1,
202 MVE_VSHL_T2,
203 MVE_VSHL_T3,
204 MVE_VSHLC,
205 MVE_VSHLL_T1,
206 MVE_VSHLL_T2,
207 MVE_VSHR,
208 MVE_VSHRN,
209 MVE_VSLI,
210 MVE_VSRI,
73cd51e5
AV		 211 MVE_NONE
212};
213
214enum mve_unpredictable
215{
216 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
217 */
143275ea
AV		 218 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and
219 fcB = 1 (vpt). */
220 UNPRED_R13, /* Unpredictable because r13 (sp) or
221 r15 (sp) used. */
9743db03 222 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
04d54ace
AV		 223 UNPRED_Q_GT_4, /* Unpredictable because
224 vec reg start > 4 (vld4/st4). */
225 UNPRED_Q_GT_6, /* Unpredictable because
226 vec reg start > 6 (vld2/st2). */
227 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
228 and WB bit = 1. */
ef1576a1
AV		 229 UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are
230 equal. */
231 UNPRED_OS, /* Unpredictable because offset scaled == 1. */
bf0b396d
AV		 232 UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the
233 same. */
c507f10b
AV		 234 UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and
235 size = 1. */
236 UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and
237 size = 2. */
73cd51e5
AV		 238 UNPRED_NONE /* No unpredictable behavior. */
239};
240
241enum mve_undefined
242{
ed63aa17 243 UNDEF_SIZE, /* undefined size. */
bf0b396d 244 UNDEF_SIZE_0, /* undefined because size == 0. */
c507f10b 245 UNDEF_SIZE_2, /* undefined because size == 2. */
aef6d006
AV		 246 UNDEF_SIZE_3, /* undefined because size == 3. */
247 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
ef1576a1
AV		 248 UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
249 UNDEF_SIZE_NOT_3, /* undefined because size != 3. */
250 UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and
251 size == 0. */
252 UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and
253 size == 1. */
254 UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
bf0b396d
AV		 255 UNDEF_VCVT_IMM6, /* imm6 < 32. */
256 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
c507f10b
AV		 257 UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and
258 op1 == (0 or 1). */
259 UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and
260 op2 == 0 and op1 == (0 or 1). */
261 UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode
262 in {0xx1, x0x1}. */
d3b63143 263 UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */
73cd51e5
AV		 264 UNDEF_NONE /* no undefined behavior. */
265};
266
6b5d3a4d
ZW		 267struct opcode32
268{
823d2571
TG		 269 arm_feature_set arch; /* Architecture defining this insn. */
270 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 271 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 272 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 273};
274
73cd51e5
AV		 275/* MVE opcodes. */
276
277struct mopcode32
278{
279 arm_feature_set arch; /* Architecture defining this insn. */
280 enum mve_instructions mve_op; /* Specific mve instruction for faster
281 decoding. */
282 unsigned long value; /* If arch is 0 then value is a sentinel. */
283 unsigned long mask; /* Recognise insn if (op & mask) == value. */
284 const char * assembler; /* How to disassemble this insn. */
285};
286
6b0dd094
AV		 287enum isa {
288 ANY,
289 T32,
290 ARM
291};
292
293
294/* Shared (between Arm and Thumb mode) opcode. */
295struct sopcode32
296{
297 enum isa isa; /* Execution mode instruction availability. */
298 arm_feature_set arch; /* Architecture defining this insn. */
299 unsigned long value; /* If arch is 0 then value is a sentinel. */
300 unsigned long mask; /* Recognise insn if (op & mask) == value. */
301 const char * assembler; /* How to disassemble this insn. */
302};
303
6b5d3a4d
ZW		 304struct opcode16
305{
823d2571 306 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 307 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 308 const char *assembler; /* How to disassemble this insn. */
309};
b7693d02 310
8f06b2d8 311/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 312
2fbad815 313 %% %
4a5329c6 314
c22aaad1 315 %c print condition code (always bits 28-31 in ARM mode)
37b37b2d 316 %q print shifter argument
e2efe87d
MGD		 317 %u print condition code (unconditional in ARM mode,
318 UNPREDICTABLE if not AL in Thumb)
4a5329c6 319 %A print address for ldc/stc/ldf/stf instruction
16980d0b 320 %B print vstm/vldm register list
efd6b359 321 %C print vscclrm register list
4a5329c6 322 %I print cirrus signed shift immediate: bits 0..3|4..6
32c36c3c
AV		 323 %J print register for VLDR instruction
324 %K print address for VLDR instruction
4a5329c6
ZW		 325 %F print the COUNT field of a LFM/SFM instruction.
326 %P print floating point precision in arithmetic insn
327 %Q print floating point precision in ldf/stf insn
328 %R print floating point rounding mode
329
33399f07 330 %<bitfield>c print as a condition code (for vsel)
4a5329c6 331 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 332 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
333 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 334 %<bitfield>d print the bitfield in decimal
16980d0b 335 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 336 %<bitfield>x print the bitfield in hex
337 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 338 %<bitfield>f print a floating point constant if >7 else a
339 floating point register
4a5329c6
ZW		 340 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
341 %<bitfield>g print as an iWMMXt 64-bit register
342 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 343 %<bitfield>D print as a NEON D register
344 %<bitfield>Q print as a NEON Q register
c28eeff2 345 %<bitfield>V print as a NEON D or Q register
6f1c2142 346 %<bitfield>E print a quarter-float immediate value
4a5329c6 347
16980d0b 348 %y<code> print a single precision VFP reg.
2fbad815 349 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 350 %z<code> print a double precision VFP reg
2fbad815 351 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 352
16980d0b
JB		 353 %<bitfield>'c print specified char iff bitfield is all ones
354 %<bitfield>`c print specified char iff bitfield is all zeroes
355 %<bitfield>?ab... select from array of values in big endian order
43e65147 356
2fbad815 357 %L print as an iWMMXt N/M width field.
4a5329c6 358 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 359 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 360 versions.
361 %i print 5-bit immediate in bits 8,3..0
362 (print "32" when 0)
fe56b6ce 363 %r print register offset address for wldt/wstr instruction. */
2fbad815 364
21d799b5 365enum opcode_sentinel_enum
05413229
NC		 366{
367 SENTINEL_IWMMXT_START = 1,
368 SENTINEL_IWMMXT_END,
369 SENTINEL_GENERIC_START
370} opcode_sentinels;
371
aefd8a40 372#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
0b347048
TC		 373#define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
374#define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
c1e26897 375#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 376
8f06b2d8 377/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 378
6b0dd094 379static const struct sopcode32 coprocessor_opcodes[] =
2fbad815 380{
2fbad815 381 /* XScale instructions. */
6b0dd094 382 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 383 0x0e200010, 0x0fff0ff0,
384 "mia%c\tacc0, %0-3r, %12-15r"},
6b0dd094 385 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 386 0x0e280010, 0x0fff0ff0,
387 "miaph%c\tacc0, %0-3r, %12-15r"},
6b0dd094 388 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 389 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
6b0dd094 390 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 391 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
6b0dd094 392 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 393 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 394
2fbad815 395 /* Intel Wireless MMX technology instructions. */
6b0dd094
AV		 396 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
397 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
823d2571 398 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
6b0dd094 399 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 400 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
6b0dd094 401 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 402 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
6b0dd094 403 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 404 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
6b0dd094 405 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 406 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
6b0dd094 407 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 408 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
6b0dd094 409 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 410 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
6b0dd094 411 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 412 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 413 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 414 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 415 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 416 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 417 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 418 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
6b0dd094 419 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 420 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
6b0dd094 421 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 422 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
6b0dd094 423 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 424 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
6b0dd094 425 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 426 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
6b0dd094 427 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 428 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 429 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 430 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 431 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 432 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 433 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 434 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 435 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 436 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 437 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 438 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
6b0dd094 439 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 440 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 441 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 442 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 443 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 444 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 445 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 446 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 447 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 448 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 449 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 450 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 451 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 452 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
6b0dd094 453 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 454 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
6b0dd094 455 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 456 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
6b0dd094 457 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 458 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 459 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 460 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 461 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 462 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 463 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 464 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 465 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 466 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
6b0dd094 467 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 468 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 469 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 470 0x0e800120, 0x0f800ff0,
471 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 472 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 473 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 474 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 475 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 476 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 477 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 478 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 479 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 480 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 481 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 482 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 483 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 484 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 485 0x0e8000a0, 0x0f800ff0,
486 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 487 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 488 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 489 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 490 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 491 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 492 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 493 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 494 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 495 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 496 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 497 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 498 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 499 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 500 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 501 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 502 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 503 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 504 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
6b0dd094 505 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 506 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 507 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 508 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 509 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 510 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 511 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 512 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 513 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 514 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 515 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 516 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 517 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 518 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 519 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 520 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 521 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 522 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 523 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 524 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
6b0dd094 525 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 526 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
6b0dd094 527 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 528 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
6b0dd094 529 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 530 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 531 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 532 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 533 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 534 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 535 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 536 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
6b0dd094 537 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 538 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
6b0dd094 539 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 540 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
6b0dd094 541 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 542 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 543 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 544 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 545 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 546 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 547 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 548 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 549 {ANY, ARM_FEATURE_CORE_LOW (0),
823d2571 550 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 551
fe56b6ce 552 /* Floating point coprocessor (FPA) instructions. */
6b0dd094 553 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 554 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 555 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 556 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 557 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 558 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 559 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 560 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 561 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 562 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 563 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 564 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 565 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 566 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 567 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 568 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 569 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 570 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 571 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 572 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 573 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 574 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 575 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 576 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 577 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 578 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 579 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 580 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 581 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 582 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 583 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 584 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 585 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 586 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 587 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 588 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
6b0dd094 589 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 590 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
6b0dd094 591 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 592 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 593 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 594 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
6b0dd094 595 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 596 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
6b0dd094 597 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 598 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
6b0dd094 599 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 600 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
6b0dd094 601 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 602 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 603 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 604 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 605 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 606 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 607 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 608 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 609 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 610 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
6b0dd094 611 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 612 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
6b0dd094 613 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 614 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
6b0dd094 615 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 616 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
6b0dd094 617 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 618 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
6b0dd094 619 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 620 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
6b0dd094 621 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 622 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
6b0dd094 623 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 624 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
6b0dd094 625 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 626 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
6b0dd094 627 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 628 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
6b0dd094 629 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 630 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
6b0dd094 631 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 632 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
6b0dd094 633 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 634 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
6b0dd094 635 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 636 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
6b0dd094 637 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 638 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 639
efd6b359
AV		 640 /* Armv8.1-M Mainline instructions. */
641 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
642 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
643 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
644 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
645
16a1fa25 646 /* ARMv8-M Mainline Security Extensions instructions. */
6b0dd094 647 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25 648 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
6b0dd094 649 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25
TP		 650 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
651
fe56b6ce 652 /* Register load/store. */
6b0dd094 653 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 654 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
6b0dd094 655 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 656 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
6b0dd094 657 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 658 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
6b0dd094 659 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 660 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
6b0dd094 661 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 662 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
6b0dd094 663 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 664 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
6b0dd094 665 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 666 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
6b0dd094 667 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 668 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
6b0dd094 669 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 670 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
6b0dd094 671 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 672 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
6b0dd094 673 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 674 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
6b0dd094 675 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 676 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
6b0dd094 677 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 678 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
6b0dd094 679 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 680 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
6b0dd094 681 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 682 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
6b0dd094 683 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 684 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
32c36c3c
AV		 685 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
686 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
687 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
688 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
823d2571 689
6b0dd094 690 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 691 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 692 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 693 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 694 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 695 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
6b0dd094 696 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 697 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 698
fe56b6ce 699 /* Data transfer between ARM and NEON registers. */
6b0dd094 700 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 701 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
6b0dd094 702 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 703 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
6b0dd094 704 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 705 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
6b0dd094 706 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 707 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
6b0dd094 708 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 709 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
6b0dd094 710 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 711 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
6b0dd094 712 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 713 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
6b0dd094 714 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 715 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 716 /* Half-precision conversion instructions. */
6b0dd094 717 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 718 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
6b0dd094 719 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 720 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
6b0dd094 721 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 722 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
6b0dd094 723 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 724 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 725
fe56b6ce 726 /* Floating point coprocessor (VFP) instructions. */
6b0dd094 727 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 728 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
6b0dd094 729 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 730 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
6b0dd094 731 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 732 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
6b0dd094 733 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 734 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
6b0dd094 735 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 736 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
6b0dd094 737 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 738 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
6b0dd094 739 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 740 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
6b0dd094 741 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 742 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
6b0dd094 743 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 744 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
6b0dd094 745 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 746 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
6b0dd094 747 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 748 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
6b0dd094 749 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 750 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
6b0dd094 751 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 752 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
6b0dd094 753 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 754 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
6b0dd094 755 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 756 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
6b0dd094 757 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 758 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
6b0dd094 759 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 760 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
6b0dd094 761 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 762 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
6b0dd094 763 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 764 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
6b0dd094 765 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 766 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
6b0dd094 767 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 768 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
6b0dd094 769 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 770 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
6b0dd094 771 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 772 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
6b0dd094 773 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 774 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
6b0dd094 775 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 776 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
6b0dd094 777 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 778 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
6b0dd094 779 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 780 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
6b0dd094 781 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 782 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
6b0dd094 783 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 784 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
6b0dd094 785 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 786 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
6b0dd094 787 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 788 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
6b0dd094 789 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 790 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
6b0dd094 791 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 792 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
6b0dd094 793 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 794 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
6b0dd094 795 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 796 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
6b0dd094 797 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 798 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
6b0dd094 799 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 800 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
6b0dd094 801 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 802 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
6b0dd094 803 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 804 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
6b0dd094 805 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 806 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 807 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 808 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
6b0dd094 809 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 810 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
6b0dd094 811 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 812 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
6b0dd094 813 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 814 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
6b0dd094 815 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 816 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
6b0dd094 817 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 818 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
6b0dd094 819 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6f1c2142 820 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
6b0dd094 821 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6f1c2142 822 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
6b0dd094 823 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 824 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
6b0dd094 825 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 826 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
6b0dd094 827 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 828 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
6b0dd094 829 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 830 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 831 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 832 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 833 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 834 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 835 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 836 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 837 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 838 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 839 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 840 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 841 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 842 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 843 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 844 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 845 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 846 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 847 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 848 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 849 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 850 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 851 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 852 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 853 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 854 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
6b0dd094 855 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 856 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
6b0dd094 857 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 858 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
6b0dd094 859 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 860 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
6b0dd094 861 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 862 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
6b0dd094 863 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 864 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 865
866 /* Cirrus coprocessor instructions. */
6b0dd094 867 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 868 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 869 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 870 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 871 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 872 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 873 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 874 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 875 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 876 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 877 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 878 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 879 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 880 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 881 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 882 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 883 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 884 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 885 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 886 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 887 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 888 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 889 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 890 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 891 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 892 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 893 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 894 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 895 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 896 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 897 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 898 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 899 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 900 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
6b0dd094 901 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 902 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
6b0dd094 903 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 904 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
6b0dd094 905 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 906 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
6b0dd094 907 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 908 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
6b0dd094 909 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 910 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
6b0dd094 911 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 912 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 913 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 914 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
6b0dd094 915 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 916 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 917 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 918 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
6b0dd094 919 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 920 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 921 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 922 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 923 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 924 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 925 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 926 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 927 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 928 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 929 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 930 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 931 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 932 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 933 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 934 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 935 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 936 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
6b0dd094 937 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 938 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
6b0dd094 939 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 940 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
6b0dd094 941 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 942 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
6b0dd094 943 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 944 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 945 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 946 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 947 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 948 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
6b0dd094 949 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 950 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
6b0dd094 951 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 952 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
6b0dd094 953 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 954 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
6b0dd094 955 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 956 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
6b0dd094 957 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 958 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
6b0dd094 959 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 960 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 961 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 962 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 963 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 964 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 965 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 966 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 967 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 968 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
6b0dd094 969 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 970 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
6b0dd094 971 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 972 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
6b0dd094 973 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 974 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
6b0dd094 975 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 976 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
6b0dd094 977 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 978 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
6b0dd094 979 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 980 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 981 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 982 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 983 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 984 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 985 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 986 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 987 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 988 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 989 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 990 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 991 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 992 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 993 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 994 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 995 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 996 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 997 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 998 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 999 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1000 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1001 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1002 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1003 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1004 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 1005 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1006 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 1007 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1008 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 1009 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1010 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 1011 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1012 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1013 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1014 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1015 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1016 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1017 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1018 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1019 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1020 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1021 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1022 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1023 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1024 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1025 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1026 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1027 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1028 0x0e000600, 0x0ff00f10,
1029 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1030 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1031 0x0e100600, 0x0ff00f10,
1032 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1033 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1034 0x0e200600, 0x0ff00f10,
1035 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1036 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1037 0x0e300600, 0x0ff00f10,
1038 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 1039
62f3b8c8 1040 /* VFP Fused multiply add instructions. */
6b0dd094 1041 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1042 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1043 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1044 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1045 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1046 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1047 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1048 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
6b0dd094 1049 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1050 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1051 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1052 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1053 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1054 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1055 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1056 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 1057
33399f07 1058 /* FP v5. */
6b0dd094 1059 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1060 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
6b0dd094 1061 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1062 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
6b0dd094 1063 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1064 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1065 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1066 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1067 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1068 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1069 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1070 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1071 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1072 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
6b0dd094 1073 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1074 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
6b0dd094 1075 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1076 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
6b0dd094 1077 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1078 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
6b0dd094 1079 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1080 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
6b0dd094 1081 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1082 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 1083
05413229 1084 /* Generic coprocessor instructions. */
6b0dd094
AV		 1085 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
1086 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
823d2571 1087 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
6b0dd094 1088 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
823d2571
TG		 1089 0x0c500000, 0x0ff00000,
1090 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
6b0dd094 1091 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1092 0x0e000000, 0x0f000010,
1093 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1094 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1095 0x0e10f010, 0x0f10f010,
1096 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1097 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1098 0x0e100010, 0x0f100010,
1099 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1100 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1101 0x0e000010, 0x0f100010,
1102 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1103 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571 1104 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 1105 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571 1106 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
2fbad815 1107
05413229 1108 /* V6 coprocessor instructions. */
6b0dd094 1109 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
823d2571
TG		 1110 0xfc500000, 0xfff00000,
1111 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
6b0dd094 1112 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
823d2571
TG		 1113 0xfc400000, 0xfff00000,
1114 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
8f06b2d8 1115
c28eeff2 1116 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
6b0dd094 1117 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1118 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1119 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1120 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1121 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1122 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1123 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1124 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1125 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1126 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1127 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1128 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1129 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1130 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
6b0dd094 1131 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1132 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
6b0dd094 1133 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1134 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
6b0dd094 1135 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1136 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
c28eeff2 1137
c604a79a 1138 /* Dot Product instructions in the space of coprocessor 13. */
6b0dd094 1139 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a 1140 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
6b0dd094 1141 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a
JW		 1142 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1143
dec41383 1144 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
6b0dd094 1145 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1146 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1147 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1148 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1149 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1150 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1151 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1152 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1153 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1154 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1155 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1156 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1157 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1158 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
6b0dd094 1159 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383
JW		 1160 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1161
05413229 1162 /* V5 coprocessor instructions. */
6b0dd094 1163 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571 1164 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 1165 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571 1166 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 1167 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1168 0xfe000000, 0xff000010,
1169 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1170 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1171 0xfe000010, 0xff100010,
1172 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1173 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1174 0xfe100010, 0xff100010,
1175 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1176
b0c11777
RL		 1177 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1178 cp_num: bit <11:8> == 0b1001.
1179 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
6b0dd094 1180 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1181 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
6b0dd094 1182 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1183 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
6b0dd094 1184 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1185 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
6b0dd094 1186 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1187 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
6b0dd094 1188 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1189 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 1190 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1191 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
6b0dd094 1192 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1193 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
6b0dd094 1194 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1195 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
6b0dd094 1196 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1197 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
6b0dd094 1198 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1199 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
6b0dd094 1200 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1201 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1202 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1203 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1204 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1205 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1206 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1207 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1208 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1209 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
6b0dd094 1210 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1211 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
6b0dd094 1212 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1213 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
6b0dd094 1214 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1215 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
6b0dd094 1216 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1217 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1218 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1219 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1220 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1221 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1222 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1223 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1224 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1225 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
6b0dd094 1226 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1227 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
6b0dd094 1228 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1229 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
6b0dd094 1230 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1231 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1232 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1233 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
6b0dd094 1234 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1235 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1236 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1237 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1238 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1239 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1240 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1241 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
6b0dd094 1242 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1243 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
6b0dd094 1244 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1245 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
6b0dd094 1246 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1247 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
6b0dd094 1248 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777
RL		 1249 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1250
49e8a725 1251 /* ARMv8.3 javascript conversion instruction. */
6b0dd094 1252 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
49e8a725
SN		 1253 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1254
6b0dd094 1255 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 1256};
1257
16980d0b
JB		 1258/* Neon opcode table: This does not encode the top byte -- that is
1259 checked by the print_insn_neon routine, as it depends on whether we are
1260 doing thumb32 or arm32 disassembly. */
1261
1262/* print_insn_neon recognizes the following format control codes:
1263
1264 %% %
1265
c22aaad1 1266 %c print condition code
e2efe87d
MGD		 1267 %u print condition code (unconditional in ARM mode,
1268 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 1269 %A print v{st,ld}[1234] operands
1270 %B print v{st,ld}[1234] any one operands
1271 %C print v{st,ld}[1234] single->all operands
1272 %D print scalar
1273 %E print vmov, vmvn, vorr, vbic encoded constant
1274 %F print vtbl,vtbx register list
1275
1276 %<bitfield>r print as an ARM register
1277 %<bitfield>d print the bitfield in decimal
1278 %<bitfield>e print the 2^N - bitfield in decimal
1279 %<bitfield>D print as a NEON D register
1280 %<bitfield>Q print as a NEON Q register
1281 %<bitfield>R print as a NEON D or Q register
1282 %<bitfield>Sn print byte scaled width limited by n
1283 %<bitfield>Tn print short scaled width limited by n
1284 %<bitfield>Un print long scaled width limited by n
43e65147 1285
16980d0b
JB		 1286 %<bitfield>'c print specified char iff bitfield is all ones
1287 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1288 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1289
1290static const struct opcode32 neon_opcodes[] =
1291{
fe56b6ce 1292 /* Extract. */
823d2571
TG		 1293 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1294 0xf2b00840, 0xffb00850,
1295 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1296 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1297 0xf2b00000, 0xffb00810,
1298 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 1299
9743db03
AV		 1300 /* Data transfer between ARM and NEON registers. */
1301 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1302 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1303 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1304 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1305 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1306 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1307 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1308 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1309 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1310 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1311 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1312 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1313
fe56b6ce 1314 /* Move data element to all lanes. */
823d2571
TG		 1315 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1316 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1317 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1318 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1319 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1320 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 1321
fe56b6ce 1322 /* Table lookup. */
823d2571
TG		 1323 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1324 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1325 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1326 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1327
8e79c3df 1328 /* Half-precision conversions. */
823d2571
TG		 1329 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1330 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1331 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1332 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1333
1334 /* NEON fused multiply add instructions. */
823d2571 1335 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1336 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1337 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1338 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1339 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1340 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1341 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1342 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1343
fe56b6ce 1344 /* Two registers, miscellaneous. */
823d2571
TG		 1345 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1346 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1347 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1348 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1349 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1350 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1351 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1352 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1353 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1354 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1355 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1356 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1357 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1358 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1359 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1360 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1361 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1362 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1363 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1364 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1365 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1366 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1367 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1368 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1369 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1370 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1371 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1372 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1373 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1374 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1375 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1376 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1377 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1378 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1379 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1380 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1381 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1382 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1383 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1384 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1385 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1386 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1387 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1388 0xf3b20300, 0xffb30fd0,
1389 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1390 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1391 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1392 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1393 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1394 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1395 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1396 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1397 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1398 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1399 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1400 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1401 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1402 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1403 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1404 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1405 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1406 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1407 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1408 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1409 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1410 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1411 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1412 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1413 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1414 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1415 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1416 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1417 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1418 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1419 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1420 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1421 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1422 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1423 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1424 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1425 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1426 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1427 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1428 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1429 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1430 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1431 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1432 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1433 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1434 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1435 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1436 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301 1437 0xf3bb0600, 0xffbf0e10,
823d2571 1438 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1439 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1440 0xf3b70600, 0xffbf0e10,
1441 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
16980d0b 1442
fe56b6ce 1443 /* Three registers of the same length. */
823d2571
TG		 1444 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1445 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1446 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1447 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1448 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1449 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1450 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1451 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1452 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1453 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1454 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1455 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1456 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1457 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1458 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1459 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1460 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1461 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1462 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1463 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1464 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1465 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1466 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1467 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1468 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1469 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1470 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1471 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1473 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1474 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1475 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1477 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1478 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1479 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1481 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1482 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1483 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1484 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1485 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1487 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1488 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1489 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1490 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1491 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1492 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1493 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1494 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1495 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1496 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1497 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1498 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1499 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1500 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1501 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1502 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1503 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1504 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1505 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1506 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1507 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1508 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1509 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1510 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1511 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1512 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1513 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1514 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1515 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1516 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1517 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1518 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1519 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1520 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1521 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1522 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1523 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1524 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1525 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1526 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1527 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1528 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1529 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1530 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1531 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1532 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1533 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1534 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1535 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1536 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1537 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1538 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1539 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1541 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1542 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1543 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1544 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1545 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1546 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1547 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1548 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1549 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1550 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1551 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1552 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1553 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1554 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1555 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1556 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1557 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1558 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1559 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1560 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1561 0xf2000b00, 0xff800f10,
1562 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1564 0xf2000b10, 0xff800f10,
1565 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1566 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1567 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1568 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1569 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1570 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1571 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1572 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1573 0xf3000b00, 0xff800f10,
1574 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1576 0xf2000000, 0xfe800f10,
1577 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1578 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1579 0xf2000010, 0xfe800f10,
1580 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1581 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1582 0xf2000100, 0xfe800f10,
1583 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1584 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1585 0xf2000200, 0xfe800f10,
1586 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1587 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1588 0xf2000210, 0xfe800f10,
1589 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1590 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1591 0xf2000300, 0xfe800f10,
1592 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1594 0xf2000310, 0xfe800f10,
1595 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1596 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1597 0xf2000400, 0xfe800f10,
1598 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1599 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1600 0xf2000410, 0xfe800f10,
1601 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1602 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1603 0xf2000500, 0xfe800f10,
1604 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1605 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1606 0xf2000510, 0xfe800f10,
1607 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1608 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1609 0xf2000600, 0xfe800f10,
1610 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1611 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1612 0xf2000610, 0xfe800f10,
1613 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1614 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1615 0xf2000700, 0xfe800f10,
1616 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1618 0xf2000710, 0xfe800f10,
1619 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1621 0xf2000910, 0xfe800f10,
1622 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1623 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1624 0xf2000a00, 0xfe800f10,
1625 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1626 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1627 0xf2000a10, 0xfe800f10,
1628 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1630 0xf3000b10, 0xff800f10,
1631 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1632 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1633 0xf3000c10, 0xff800f10,
1634 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1635
fe56b6ce 1636 /* One register and an immediate value. */
823d2571
TG		 1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1638 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1639 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1640 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1642 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1643 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1644 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1646 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1647 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1648 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1650 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1651 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1652 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1653 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1654 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1655 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1656 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1658 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1659 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1660 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1661 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1662 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1663
fe56b6ce 1664 /* Two registers and a shift amount. */
823d2571
TG		 1665 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1666 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1667 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1668 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1669 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1670 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1671 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1672 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1673 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1674 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1675 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1676 0xf2880950, 0xfeb80fd0,
1677 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1678 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1679 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1680 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1681 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1682 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1683 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1685 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1687 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1688 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1689 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1691 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1692 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1693 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1694 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1695 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1696 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1697 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1698 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1699 0xf2900950, 0xfeb00fd0,
1700 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1701 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1702 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1703 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1704 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1705 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1706 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1707 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1708 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1709 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1710 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1711 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1712 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1713 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1714 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1715 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1716 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1717 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1718 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1719 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1720 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1721 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1722 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1723 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1724 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1725 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1726 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1727 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1728 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1729 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1730 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1731 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1732 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1733 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1734 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1735 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1736 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1737 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1738 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1739 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1740 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1741 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1742 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1743 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1744 0xf2a00950, 0xfea00fd0,
1745 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1746 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1747 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1748 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1749 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1750 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1751 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1753 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1754 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1755 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1756 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1757 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1758 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1759 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1760 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1761 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1762 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1763 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1764 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1765 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1766 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1767 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1768 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1769 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1770 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1771 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1772 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1773 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1774 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1775 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1776 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1777 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1778 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1779 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1780 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1781 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1782 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1783 0xf2a00e10, 0xfea00e90,
1784 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
cc933301
JW		 1785 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1786 0xf2a00c10, 0xfea00e90,
1787 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 1788
fe56b6ce 1789 /* Three registers of different lengths. */
823d2571
TG		 1790 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1791 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1792 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1793 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1794 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1795 0xf2800400, 0xff800f50,
1796 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1797 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1798 0xf2800600, 0xff800f50,
1799 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1800 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1801 0xf2800900, 0xff800f50,
1802 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1803 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1804 0xf2800b00, 0xff800f50,
1805 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1806 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1807 0xf2800d00, 0xff800f50,
1808 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1809 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1810 0xf3800400, 0xff800f50,
1811 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1812 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1813 0xf3800600, 0xff800f50,
1814 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1815 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1816 0xf2800000, 0xfe800f50,
1817 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1818 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1819 0xf2800100, 0xfe800f50,
1820 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1821 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1822 0xf2800200, 0xfe800f50,
1823 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1824 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1825 0xf2800300, 0xfe800f50,
1826 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1827 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1828 0xf2800500, 0xfe800f50,
1829 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1830 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1831 0xf2800700, 0xfe800f50,
1832 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1833 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1834 0xf2800800, 0xfe800f50,
1835 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1836 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1837 0xf2800a00, 0xfe800f50,
1838 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1839 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1840 0xf2800c00, 0xfe800f50,
1841 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 1842
fe56b6ce 1843 /* Two registers and a scalar. */
823d2571
TG		 1844 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1845 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1846 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1847 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1848 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1849 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1850 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1851 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1852 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1853 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1854 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1855 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1856 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1857 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1858 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1859 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1860 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1861 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1862 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1863 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1864 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1865 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1866 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1867 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1868 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1869 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1870 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1871 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1872 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1873 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1874 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1875 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1876 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1877 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1878 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1879 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1880 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1881 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1882 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1883 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1884 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1885 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1886 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1887 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1888 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1889 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1890 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1891 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1892 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1893 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1894 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1895 0xf2800240, 0xfe800f50,
1896 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1897 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1898 0xf2800640, 0xfe800f50,
1899 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1900 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1901 0xf2800a40, 0xfe800f50,
1902 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 1903 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1904 0xf2800e40, 0xff800f50,
1905 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1906 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1907 0xf2800f40, 0xff800f50,
1908 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1909 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1910 0xf3800e40, 0xff800f50,
1911 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1912 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1913 0xf3800f40, 0xff800f50,
1914 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1915 },
16980d0b 1916
fe56b6ce 1917 /* Element and structure load/store. */
823d2571
TG		 1918 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1919 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1920 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1921 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1922 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1923 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1924 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1925 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1926 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1927 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1928 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1929 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1930 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1931 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1932 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1933 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1934 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1935 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1936 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1937 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1938 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1939 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1940 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1941 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1942 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1943 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1944 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1945 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1946 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1947 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1948 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1949 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1950 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1951 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1952 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1953 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1954 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1955 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1956
1957 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 1958};
1959
73cd51e5
AV		 1960/* mve opcode table. */
1961
1962/* print_insn_mve recognizes the following format control codes:
1963
1964 %% %
1965
ef1576a1
AV		 1966 %a print '+' or '-' or imm offset in vldr[bhwd] and
1967 vstr[bhwd]
9743db03 1968 %c print condition code
aef6d006
AV		 1969 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
1970 %u print 'U' (unsigned) or 'S' for various mve instructions
143275ea 1971 %i print MVE predicate(s) for vpt and vpst
bf0b396d 1972 %m print rounding mode for vcvt and vrint
143275ea 1973 %n print vector comparison code for predicated instruction
bf0b396d 1974 %s print size for various vcvt instructions
143275ea
AV		 1975 %v print vector predicate for instruction in predicated
1976 block
ef1576a1 1977 %o print offset scaled for vldr[hwd] and vstr[hwd]
04d54ace
AV		 1978 %w print writeback mode for MVE v{st,ld}[24]
1979 %B print v{st,ld}[24] any one operands
c507f10b
AV		 1980 %E print vmov, vmvn, vorr, vbic encoded constant
1981 %N print generic index for vmov
14925797 1982 %T print bottom ('b') or top ('t') of source register
d3b63143 1983 %X print exchange field in vmla* instructions
04d54ace 1984
9743db03 1985 %<bitfield>r print as an ARM register
04d54ace 1986 %<bitfield>d print the bitfield in decimal
d3b63143 1987 %<bitfield>A print accumulate or not
143275ea 1988 %<bitfield>Q print as a MVE Q register
c507f10b 1989 %<bitfield>F print as a MVE S register
143275ea
AV		 1990 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
1991 UNPREDICTABLE
1992 %<bitfield>s print size for vector predicate & non VMOV instructions
ef1576a1 1993 %<bitfield>i print immediate for vstr/vldr reg +/- imm
1c8f2df8 1994 %<bitfield>h print high half of 64-bit destination reg
bf0b396d 1995 %<bitfield>k print immediate for vector conversion instruction
1c8f2df8 1996 %<bitfield>l print low half of 64-bit destination reg
897b9bbc 1997 %<bitfield>o print rotate value for vcmul
1c8f2df8 1998 %<bitfield>u print immediate value for vddup/vdwdup
c507f10b 1999 %<bitfield>x print the bitfield in hex.
1c8f2df8 2000 */
73cd51e5
AV		 2001
2002static const struct mopcode32 mve_opcodes[] =
2003{
143275ea
AV		 2004 /* MVE. */
2005
2006 {ARM_FEATURE_COPROC (FPU_MVE),
2007 MVE_VPST,
2008 0xfe310f4d, 0xffbf1fff,
2009 "vpst%i"
2010 },
2011
2012 /* Floating point VPT T1. */
2013 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2014 MVE_VPT_FP_T1,
2015 0xee310f00, 0xefb10f50,
2016 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2017 /* Floating point VPT T2. */
2018 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2019 MVE_VPT_FP_T2,
2020 0xee310f40, 0xefb10f50,
2021 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2022
2023 /* Vector VPT T1. */
2024 {ARM_FEATURE_COPROC (FPU_MVE),
2025 MVE_VPT_VEC_T1,
2026 0xfe010f00, 0xff811f51,
2027 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2028 /* Vector VPT T2. */
2029 {ARM_FEATURE_COPROC (FPU_MVE),
2030 MVE_VPT_VEC_T2,
2031 0xfe010f01, 0xff811f51,
2032 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2033 /* Vector VPT T3. */
2034 {ARM_FEATURE_COPROC (FPU_MVE),
2035 MVE_VPT_VEC_T3,
2036 0xfe011f00, 0xff811f50,
2037 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2038 /* Vector VPT T4. */
2039 {ARM_FEATURE_COPROC (FPU_MVE),
2040 MVE_VPT_VEC_T4,
2041 0xfe010f40, 0xff811f70,
2042 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2043 /* Vector VPT T5. */
2044 {ARM_FEATURE_COPROC (FPU_MVE),
2045 MVE_VPT_VEC_T5,
2046 0xfe010f60, 0xff811f70,
2047 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2048 /* Vector VPT T6. */
2049 {ARM_FEATURE_COPROC (FPU_MVE),
2050 MVE_VPT_VEC_T6,
2051 0xfe011f40, 0xff811f50,
2052 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2053
c507f10b
AV		 2054 /* Vector VBIC immediate. */
2055 {ARM_FEATURE_COPROC (FPU_MVE),
2056 MVE_VBIC_IMM,
2057 0xef800070, 0xefb81070,
2058 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2059
2060 /* Vector VBIC register. */
2061 {ARM_FEATURE_COPROC (FPU_MVE),
2062 MVE_VBIC_REG,
2063 0xef100150, 0xffb11f51,
2064 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2065
d3b63143
AV		 2066 /* Vector VADDLV. */
2067 {ARM_FEATURE_COPROC (FPU_MVE),
2068 MVE_VADDLV,
2069 0xee890f00, 0xef8f1fd1,
2070 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2071
2072 /* Vector VADDV. */
2073 {ARM_FEATURE_COPROC (FPU_MVE),
2074 MVE_VADDV,
2075 0xeef10f00, 0xeff31fd1,
2076 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2077
897b9bbc
AV		 2078 /* Vector VCADD floating point. */
2079 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2080 MVE_VCADD_FP,
2081 0xfc800840, 0xfea11f51,
2082 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2083
2084 /* Vector VCADD. */
2085 {ARM_FEATURE_COPROC (FPU_MVE),
2086 MVE_VCADD_VEC,
2087 0xfe000f00, 0xff810f51,
2088 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2089
2090 /* Vector VCMLA. */
2091 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2092 MVE_VCMLA_FP,
2093 0xfc200840, 0xfe211f51,
2094 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2095
143275ea
AV		 2096 /* Vector VCMP floating point T1. */
2097 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2098 MVE_VCMP_FP_T1,
2099 0xee310f00, 0xeff1ef50,
2100 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2101
2102 /* Vector VCMP floating point T2. */
2103 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2104 MVE_VCMP_FP_T2,
2105 0xee310f40, 0xeff1ef50,
2106 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2107
2108 /* Vector VCMP T1. */
2109 {ARM_FEATURE_COPROC (FPU_MVE),
2110 MVE_VCMP_VEC_T1,
2111 0xfe010f00, 0xffc1ff51,
2112 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2113 /* Vector VCMP T2. */
2114 {ARM_FEATURE_COPROC (FPU_MVE),
2115 MVE_VCMP_VEC_T2,
2116 0xfe010f01, 0xffc1ff51,
2117 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2118 /* Vector VCMP T3. */
2119 {ARM_FEATURE_COPROC (FPU_MVE),
2120 MVE_VCMP_VEC_T3,
2121 0xfe011f00, 0xffc1ff50,
2122 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2123 /* Vector VCMP T4. */
2124 {ARM_FEATURE_COPROC (FPU_MVE),
2125 MVE_VCMP_VEC_T4,
2126 0xfe010f40, 0xffc1ff70,
2127 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2128 /* Vector VCMP T5. */
2129 {ARM_FEATURE_COPROC (FPU_MVE),
2130 MVE_VCMP_VEC_T5,
2131 0xfe010f60, 0xffc1ff70,
2132 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2133 /* Vector VCMP T6. */
2134 {ARM_FEATURE_COPROC (FPU_MVE),
2135 MVE_VCMP_VEC_T6,
2136 0xfe011f40, 0xffc1ff50,
2137 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2138
9743db03
AV		 2139 /* Vector VDUP. */
2140 {ARM_FEATURE_COPROC (FPU_MVE),
2141 MVE_VDUP,
2142 0xeea00b10, 0xffb10f5f,
2143 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2144
2145 /* Vector VEOR. */
2146 {ARM_FEATURE_COPROC (FPU_MVE),
2147 MVE_VEOR,
2148 0xff000150, 0xffd11f51,
2149 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2150
2151 /* Vector VFMA, vector * scalar. */
2152 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2153 MVE_VFMA_FP_SCALAR,
2154 0xee310e40, 0xefb11f70,
2155 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2156
2157 /* Vector VFMA floating point. */
2158 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2159 MVE_VFMA_FP,
2160 0xef000c50, 0xffa11f51,
2161 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2162
2163 /* Vector VFMS floating point. */
2164 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2165 MVE_VFMS_FP,
2166 0xef200c50, 0xffa11f51,
2167 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2168
2169 /* Vector VFMAS, vector * scalar. */
2170 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2171 MVE_VFMAS_FP_SCALAR,
2172 0xee311e40, 0xefb11f70,
2173 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2174
2175 /* Vector VHADD T1. */
2176 {ARM_FEATURE_COPROC (FPU_MVE),
2177 MVE_VHADD_T1,
2178 0xef000040, 0xef811f51,
2179 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2180
2181 /* Vector VHADD T2. */
2182 {ARM_FEATURE_COPROC (FPU_MVE),
2183 MVE_VHADD_T2,
2184 0xee000f40, 0xef811f70,
2185 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2186
2187 /* Vector VHSUB T1. */
2188 {ARM_FEATURE_COPROC (FPU_MVE),
2189 MVE_VHSUB_T1,
2190 0xef000240, 0xef811f51,
2191 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2192
2193 /* Vector VHSUB T2. */
2194 {ARM_FEATURE_COPROC (FPU_MVE),
2195 MVE_VHSUB_T2,
2196 0xee001f40, 0xef811f70,
2197 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2198
897b9bbc
AV		 2199 /* Vector VCMUL. */
2200 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2201 MVE_VCMUL_FP,
2202 0xee300e00, 0xefb10f50,
2203 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2204
9743db03
AV		 2205 /* Vector VDUP. */
2206 {ARM_FEATURE_COPROC (FPU_MVE),
2207 MVE_VDUP,
2208 0xeea00b10, 0xffb10f5f,
2209 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2210
2211 /* Vector VRHADD. */
2212 {ARM_FEATURE_COPROC (FPU_MVE),
2213 MVE_VRHADD,
2214 0xef000140, 0xef811f51,
2215 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2216
bf0b396d
AV		 2217 /* Vector VCVT. */
2218 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2219 MVE_VCVT_FP_FIX_VEC,
2220 0xef800c50, 0xef801cd1,
2221 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2222
2223 /* Vector VCVT. */
2224 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2225 MVE_VCVT_BETWEEN_FP_INT,
2226 0xffb30640, 0xffb31e51,
2227 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2228
2229 /* Vector VCVT between single and half-precision float, bottom half. */
2230 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2231 MVE_VCVT_FP_HALF_FP,
2232 0xee3f0e01, 0xefbf1fd1,
2233 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2234
2235 /* Vector VCVT between single and half-precision float, top half. */
2236 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2237 MVE_VCVT_FP_HALF_FP,
2238 0xee3f1e01, 0xefbf1fd1,
2239 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2240
2241 /* Vector VCVT. */
2242 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2243 MVE_VCVT_FROM_FP_TO_INT,
2244 0xffb30040, 0xffb31c51,
2245 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2246
1c8f2df8
AV		 2247 /* Vector VDDUP. */
2248 {ARM_FEATURE_COPROC (FPU_MVE),
2249 MVE_VDDUP,
2250 0xee011f6e, 0xff811f7e,
2251 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2252
2253 /* Vector VDWDUP. */
2254 {ARM_FEATURE_COPROC (FPU_MVE),
2255 MVE_VDWDUP,
2256 0xee011f60, 0xff811f70,
2257 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2258
897b9bbc
AV		 2259 /* Vector VHCADD. */
2260 {ARM_FEATURE_COPROC (FPU_MVE),
2261 MVE_VHCADD,
2262 0xee000f00, 0xff810f51,
2263 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2264
1c8f2df8
AV		 2265 /* Vector VIWDUP. */
2266 {ARM_FEATURE_COPROC (FPU_MVE),
2267 MVE_VIWDUP,
2268 0xee010f60, 0xff811f70,
2269 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2270
2271 /* Vector VIDUP. */
2272 {ARM_FEATURE_COPROC (FPU_MVE),
2273 MVE_VIDUP,
2274 0xee010f6e, 0xff811f7e,
2275 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2276
04d54ace
AV		 2277 /* Vector VLD2. */
2278 {ARM_FEATURE_COPROC (FPU_MVE),
2279 MVE_VLD2,
2280 0xfc901e00, 0xff901e5f,
2281 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2282
2283 /* Vector VLD4. */
2284 {ARM_FEATURE_COPROC (FPU_MVE),
2285 MVE_VLD4,
2286 0xfc901e01, 0xff901e1f,
2287 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2288
ef1576a1
AV		 2289 /* Vector VLDRB gather load. */
2290 {ARM_FEATURE_COPROC (FPU_MVE),
2291 MVE_VLDRB_GATHER_T1,
2292 0xec900e00, 0xefb01e50,
2293 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2294
2295 /* Vector VLDRH gather load. */
2296 {ARM_FEATURE_COPROC (FPU_MVE),
2297 MVE_VLDRH_GATHER_T2,
2298 0xec900e10, 0xefb01e50,
2299 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2300
2301 /* Vector VLDRW gather load. */
2302 {ARM_FEATURE_COPROC (FPU_MVE),
2303 MVE_VLDRW_GATHER_T3,
2304 0xfc900f40, 0xffb01fd0,
2305 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2306
2307 /* Vector VLDRD gather load. */
2308 {ARM_FEATURE_COPROC (FPU_MVE),
2309 MVE_VLDRD_GATHER_T4,
2310 0xec900fd0, 0xefb01fd0,
2311 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2312
2313 /* Vector VLDRW gather load. */
2314 {ARM_FEATURE_COPROC (FPU_MVE),
2315 MVE_VLDRW_GATHER_T5,
2316 0xfd101e00, 0xff111f00,
2317 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2318
2319 /* Vector VLDRD gather load, variant T6. */
2320 {ARM_FEATURE_COPROC (FPU_MVE),
2321 MVE_VLDRD_GATHER_T6,
2322 0xfd101f00, 0xff111f00,
2323 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2324
aef6d006
AV		 2325 /* Vector VLDRB. */
2326 {ARM_FEATURE_COPROC (FPU_MVE),
2327 MVE_VLDRB_T1,
2328 0xec100e00, 0xee581e00,
2329 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2330
2331 /* Vector VLDRH. */
2332 {ARM_FEATURE_COPROC (FPU_MVE),
2333 MVE_VLDRH_T2,
2334 0xec180e00, 0xee581e00,
2335 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2336
2337 /* Vector VLDRB unsigned, variant T5. */
2338 {ARM_FEATURE_COPROC (FPU_MVE),
2339 MVE_VLDRB_T5,
2340 0xec101e00, 0xfe101f80,
2341 "vldrb%v.u8\t%13-15,22Q, %d"},
2342
2343 /* Vector VLDRH unsigned, variant T6. */
2344 {ARM_FEATURE_COPROC (FPU_MVE),
2345 MVE_VLDRH_T6,
2346 0xec101e80, 0xfe101f80,
2347 "vldrh%v.u16\t%13-15,22Q, %d"},
2348
2349 /* Vector VLDRW unsigned, variant T7. */
2350 {ARM_FEATURE_COPROC (FPU_MVE),
2351 MVE_VLDRW_T7,
2352 0xec101f00, 0xfe101f80,
2353 "vldrw%v.u32\t%13-15,22Q, %d"},
2354
d3b63143
AV		 2355 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2356 opcode aliasing. */
2357 {ARM_FEATURE_COPROC (FPU_MVE),
2358 MVE_VMLALDAV,
2359 0xee801e00, 0xef801f51,
2360 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2361
2362 {ARM_FEATURE_COPROC (FPU_MVE),
2363 MVE_VMLALDAV,
2364 0xee800e00, 0xef801f51,
2365 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2366
2367 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2368 {ARM_FEATURE_COPROC (FPU_MVE),
2369 MVE_VMLADAV_T1,
2370 0xeef00e00, 0xeff01f51,
2371 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2372
2373 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2374 {ARM_FEATURE_COPROC (FPU_MVE),
2375 MVE_VMLADAV_T2,
2376 0xeef00f00, 0xeff11f51,
2377 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2378
2379 /* Vector VMLADAV T1 variant. */
2380 {ARM_FEATURE_COPROC (FPU_MVE),
2381 MVE_VMLADAV_T1,
2382 0xeef01e00, 0xeff01f51,
2383 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2384
2385 /* Vector VMLADAV T2 variant. */
2386 {ARM_FEATURE_COPROC (FPU_MVE),
2387 MVE_VMLADAV_T2,
2388 0xeef01f00, 0xeff11f51,
2389 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2390
2391 /* Vector VMLAS. */
2392 {ARM_FEATURE_COPROC (FPU_MVE),
2393 MVE_VMLAS,
2394 0xee011e40, 0xef811f70,
2395 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2396
2397 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2398 opcode aliasing. */
2399 {ARM_FEATURE_COPROC (FPU_MVE),
2400 MVE_VRMLSLDAVH,
2401 0xfe800e01, 0xff810f51,
2402 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2403
2404 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2405 opcdoe aliasing. */
2406 {ARM_FEATURE_COPROC (FPU_MVE),
2407 MVE_VMLSLDAV,
2408 0xee800e01, 0xff800f51,
2409 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2410
2411 /* Vector VMLSDAV T1 Variant. */
2412 {ARM_FEATURE_COPROC (FPU_MVE),
2413 MVE_VMLSDAV_T1,
2414 0xeef00e01, 0xfff00f51,
2415 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2416
2417 /* Vector VMLSDAV T2 Variant. */
2418 {ARM_FEATURE_COPROC (FPU_MVE),
2419 MVE_VMLSDAV_T2,
2420 0xfef00e01, 0xfff10f51,
2421 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2422
c507f10b
AV		 2423 /* Vector VMOV between gpr and half precision register, op == 0. */
2424 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2425 MVE_VMOV_HFP_TO_GP,
2426 0xee000910, 0xfff00f7f,
2427 "vmov.f16\t%7,16-19F, %12-15r"},
2428
2429 /* Vector VMOV between gpr and half precision register, op == 1. */
2430 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2431 MVE_VMOV_HFP_TO_GP,
2432 0xee100910, 0xfff00f7f,
2433 "vmov.f16\t%12-15r, %7,16-19F"},
2434
2435 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2436 MVE_VMOV_GP_TO_VEC_LANE,
2437 0xee000b10, 0xff900f1f,
2438 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2439
2440 /* Vector VORR immediate to vector.
2441 NOTE: MVE_VORR_IMM must appear in the table
2442 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2443 {ARM_FEATURE_COPROC (FPU_MVE),
2444 MVE_VORR_IMM,
2445 0xef800050, 0xefb810f0,
2446 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2447
ed63aa17
AV		 2448 /* Vector VQSHL T2 Variant.
2449 NOTE: MVE_VQSHL_T2 must appear in the table before
2450 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2451 {ARM_FEATURE_COPROC (FPU_MVE),
2452 MVE_VQSHL_T2,
2453 0xef800750, 0xef801fd1,
2454 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2455
2456 /* Vector VQSHLU T3 Variant
2457 NOTE: MVE_VQSHL_T2 must appear in the table before
2458 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2459
2460 {ARM_FEATURE_COPROC (FPU_MVE),
2461 MVE_VQSHLU_T3,
2462 0xff800650, 0xff801fd1,
2463 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2464
2465 /* Vector VRSHR
2466 NOTE: MVE_VRSHR must appear in the table before
2467 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2468 {ARM_FEATURE_COPROC (FPU_MVE),
2469 MVE_VRSHR,
2470 0xef800250, 0xef801fd1,
2471 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2472
2473 /* Vector VSHL.
2474 NOTE: MVE_VSHL must appear in the table before
2475 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2476 {ARM_FEATURE_COPROC (FPU_MVE),
2477 MVE_VSHL_T1,
2478 0xef800550, 0xff801fd1,
2479 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2480
2481 /* Vector VSHR
2482 NOTE: MVE_VSHR must appear in the table before
2483 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2484 {ARM_FEATURE_COPROC (FPU_MVE),
2485 MVE_VSHR,
2486 0xef800050, 0xef801fd1,
2487 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2488
2489 /* Vector VSLI
2490 NOTE: MVE_VSLI must appear in the table before
2491 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2492 {ARM_FEATURE_COPROC (FPU_MVE),
2493 MVE_VSLI,
2494 0xff800550, 0xff801fd1,
2495 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2496
2497 /* Vector VSRI
2498 NOTE: MVE_VSRI must appear in the table before
2499 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2500 {ARM_FEATURE_COPROC (FPU_MVE),
2501 MVE_VSRI,
2502 0xff800450, 0xff801fd1,
2503 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2504
c507f10b
AV		 2505 /* Vector VMOV immediate to vector,
2506 cmode == 11x1 -> VMVN which is UNDEFINED
2507 for such a cmode. */
2508 {ARM_FEATURE_COPROC (FPU_MVE),
2509 MVE_VMVN_IMM, 0xef800d50, 0xefb81dd0, UNDEFINED_INSTRUCTION},
2510
2511 /* Vector VMOV immediate to vector. */
2512 {ARM_FEATURE_COPROC (FPU_MVE),
2513 MVE_VMOV_IMM_TO_VEC,
2514 0xef800050, 0xefb810d0,
2515 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2516
2517 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2518 {ARM_FEATURE_COPROC (FPU_MVE),
2519 MVE_VMOV2_VEC_LANE_TO_GP,
2520 0xec000f00, 0xffb01ff0,
2521 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2522
2523 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2524 {ARM_FEATURE_COPROC (FPU_MVE),
2525 MVE_VMOV2_VEC_LANE_TO_GP,
2526 0xec000f10, 0xffb01ff0,
2527 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2528
2529 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2530 {ARM_FEATURE_COPROC (FPU_MVE),
2531 MVE_VMOV2_GP_TO_VEC_LANE,
2532 0xec100f00, 0xffb01ff0,
2533 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2534
2535 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2536 {ARM_FEATURE_COPROC (FPU_MVE),
2537 MVE_VMOV2_GP_TO_VEC_LANE,
2538 0xec100f10, 0xffb01ff0,
2539 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2540
2541 /* Vector VMOV Vector lane to gpr. */
2542 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2543 MVE_VMOV_VEC_LANE_TO_GP,
2544 0xee100b10, 0xff100f1f,
2545 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2546
ed63aa17
AV		 2547 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
2548 to instruction opcode aliasing. */
2549 {ARM_FEATURE_COPROC (FPU_MVE),
2550 MVE_VSHLL_T1,
2551 0xeea00f40, 0xefa00fd1,
2552 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2553
14925797
AV		 2554 /* Vector VMOVL long. */
2555 {ARM_FEATURE_COPROC (FPU_MVE),
2556 MVE_VMOVL,
2557 0xeea00f40, 0xefa70fd1,
2558 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2559
2560 /* Vector VMOV and narrow. */
2561 {ARM_FEATURE_COPROC (FPU_MVE),
2562 MVE_VMOVN,
2563 0xfe310e81, 0xffb30fd1,
2564 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2565
c507f10b
AV		 2566 /* Floating point move extract. */
2567 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2568 MVE_VMOVX,
2569 0xfeb00a40, 0xffbf0fd0,
2570 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2571
14925797
AV		 2572 /* Vector VMULL integer. */
2573 {ARM_FEATURE_COPROC (FPU_MVE),
2574 MVE_VMULL_INT,
2575 0xee010e00, 0xef810f51,
2576 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2577
2578 /* Vector VMULL polynomial. */
2579 {ARM_FEATURE_COPROC (FPU_MVE),
2580 MVE_VMULL_POLY,
2581 0xee310e00, 0xefb10f51,
2582 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2583
c507f10b
AV		 2584 /* Vector VMVN immediate to vector. */
2585 {ARM_FEATURE_COPROC (FPU_MVE),
2586 MVE_VMVN_IMM,
2587 0xef800070, 0xefb810f0,
2588 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2589
2590 /* Vector VMVN register. */
2591 {ARM_FEATURE_COPROC (FPU_MVE),
2592 MVE_VMVN_REG,
2593 0xffb005c0, 0xffbf1fd1,
2594 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2595
2596 /* Vector VORN, vector bitwise or not. */
2597 {ARM_FEATURE_COPROC (FPU_MVE),
2598 MVE_VORN,
2599 0xef300150, 0xffb11f51,
2600 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2601
2602 /* Vector VORR register. */
2603 {ARM_FEATURE_COPROC (FPU_MVE),
2604 MVE_VORR_REG,
2605 0xef200150, 0xffb11f51,
2606 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2607
14925797
AV		 2608 /* Vector VQDMULL T1 variant. */
2609 {ARM_FEATURE_COPROC (FPU_MVE),
2610 MVE_VQDMULL_T1,
2611 0xee300f01, 0xefb10f51,
2612 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2613
2614 /* Vector VQDMULL T2 variant. */
2615 {ARM_FEATURE_COPROC (FPU_MVE),
2616 MVE_VQDMULL_T2,
2617 0xee300f60, 0xefb10f70,
2618 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2619
2620 /* Vector VQMOVN. */
2621 {ARM_FEATURE_COPROC (FPU_MVE),
2622 MVE_VQMOVN,
2623 0xee330e01, 0xefb30fd1,
2624 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
2625
2626 /* Vector VQMOVUN. */
2627 {ARM_FEATURE_COPROC (FPU_MVE),
2628 MVE_VQMOVUN,
2629 0xee310e81, 0xffb30fd1,
2630 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2631
d3b63143
AV		 2632 /* Vector VQDMLADH. */
2633 {ARM_FEATURE_COPROC (FPU_MVE),
2634 MVE_VQDMLADH,
2635 0xee000e00, 0xff810f51,
2636 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2637
2638 /* Vector VQRDMLADH. */
2639 {ARM_FEATURE_COPROC (FPU_MVE),
2640 MVE_VQRDMLADH,
2641 0xee000e01, 0xff810f51,
2642 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2643
2644 /* Vector VQDMLAH. */
2645 {ARM_FEATURE_COPROC (FPU_MVE),
2646 MVE_VQDMLAH,
2647 0xee000e60, 0xef811f70,
2648 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2649
2650 /* Vector VQRDMLAH. */
2651 {ARM_FEATURE_COPROC (FPU_MVE),
2652 MVE_VQRDMLAH,
2653 0xee000e40, 0xef811f70,
2654 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2655
2656 /* Vector VQDMLASH. */
2657 {ARM_FEATURE_COPROC (FPU_MVE),
2658 MVE_VQDMLASH,
2659 0xee001e60, 0xef811f70,
2660 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2661
2662 /* Vector VQRDMLASH. */
2663 {ARM_FEATURE_COPROC (FPU_MVE),
2664 MVE_VQRDMLASH,
2665 0xee001e40, 0xef811f70,
2666 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2667
2668 /* Vector VQDMLSDH. */
2669 {ARM_FEATURE_COPROC (FPU_MVE),
2670 MVE_VQDMLSDH,
2671 0xfe000e00, 0xff810f51,
2672 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2673
2674 /* Vector VQRDMLSDH. */
2675 {ARM_FEATURE_COPROC (FPU_MVE),
2676 MVE_VQRDMLSDH,
2677 0xfe000e01, 0xff810f51,
2678 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2679
2680 /* Vector VQDMULH T1 variant. */
2681 {ARM_FEATURE_COPROC (FPU_MVE),
2682 MVE_VQDMULH_T1,
2683 0xef000b40, 0xff811f51,
2684 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2685
2686 /* Vector VQRDMULH T2 variant. */
2687 {ARM_FEATURE_COPROC (FPU_MVE),
2688 MVE_VQRDMULH_T2,
2689 0xff000b40, 0xff811f51,
2690 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2691
2692 /* Vector VQDMULH T3 variant. */
2693 {ARM_FEATURE_COPROC (FPU_MVE),
2694 MVE_VQDMULH_T3,
2695 0xee010e60, 0xff811f70,
2696 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2697
2698 /* Vector VQRDMULH T4 variant. */
2699 {ARM_FEATURE_COPROC (FPU_MVE),
2700 MVE_VQRDMULH_T4,
2701 0xfe010e60, 0xff811f70,
2702 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2703
ed63aa17
AV		 2704 /* Vector VQRSHL T1 variant. */
2705 {ARM_FEATURE_COPROC (FPU_MVE),
2706 MVE_VQRSHL_T1,
2707 0xef000550, 0xef811f51,
2708 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
2709
2710 /* Vector VQRSHL T2 variant. */
2711 {ARM_FEATURE_COPROC (FPU_MVE),
2712 MVE_VQRSHL_T2,
2713 0xee331ee0, 0xefb31ff0,
2714 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
2715
2716 /* Vector VQRSHRN. */
2717 {ARM_FEATURE_COPROC (FPU_MVE),
2718 MVE_VQRSHRN,
2719 0xee800f41, 0xefa00fd1,
2720 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2721
2722 /* Vector VQRSHRUN. */
2723 {ARM_FEATURE_COPROC (FPU_MVE),
2724 MVE_VQRSHRUN,
2725 0xfe800fc0, 0xffa00fd1,
2726 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2727
2728 /* Vector VQSHL T1 Variant. */
2729 {ARM_FEATURE_COPROC (FPU_MVE),
2730 MVE_VQSHL_T1,
2731 0xee311ee0, 0xefb31ff0,
2732 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
2733
2734 /* Vector VQSHL T4 Variant. */
2735 {ARM_FEATURE_COPROC (FPU_MVE),
2736 MVE_VQSHL_T4,
2737 0xef000450, 0xef811f51,
2738 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
2739
2740 /* Vector VQSHRN. */
2741 {ARM_FEATURE_COPROC (FPU_MVE),
2742 MVE_VQSHRN,
2743 0xee800f40, 0xefa00fd1,
2744 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2745
2746 /* Vector VQSHRUN. */
2747 {ARM_FEATURE_COPROC (FPU_MVE),
2748 MVE_VQSHRUN,
2749 0xee800fc0, 0xffa00fd1,
2750 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2751
bf0b396d
AV		 2752 /* Vector VRINT floating point. */
2753 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2754 MVE_VRINT_FP,
2755 0xffb20440, 0xffb31c51,
2756 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2757
d3b63143
AV		 2758 /* Vector VRMLALDAVH. */
2759 {ARM_FEATURE_COPROC (FPU_MVE),
2760 MVE_VRMLALDAVH,
2761 0xee800f00, 0xef811f51,
2762 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2763
2764 /* Vector VRMLALDAVH. */
2765 {ARM_FEATURE_COPROC (FPU_MVE),
2766 MVE_VRMLALDAVH,
2767 0xee801f00, 0xef811f51,
2768 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2769
ed63aa17
AV		 2770 /* Vector VRSHL T1 Variant. */
2771 {ARM_FEATURE_COPROC (FPU_MVE),
2772 MVE_VRSHL_T1,
2773 0xef000540, 0xef811f51,
2774 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
2775
2776 /* Vector VRSHL T2 Variant. */
2777 {ARM_FEATURE_COPROC (FPU_MVE),
2778 MVE_VRSHL_T2,
2779 0xee331e60, 0xefb31ff0,
2780 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
2781
2782 /* Vector VRSHRN. */
2783 {ARM_FEATURE_COPROC (FPU_MVE),
2784 MVE_VRSHRN,
2785 0xfe800fc1, 0xffa00fd1,
2786 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2787
2788 /* Vector VSHL T2 Variant. */
2789 {ARM_FEATURE_COPROC (FPU_MVE),
2790 MVE_VSHL_T2,
2791 0xee311e60, 0xefb31ff0,
2792 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
2793
2794 /* Vector VSHL T3 Variant. */
2795 {ARM_FEATURE_COPROC (FPU_MVE),
2796 MVE_VSHL_T3,
2797 0xef000440, 0xef811f51,
2798 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
2799
2800 /* Vector VSHLC. */
2801 {ARM_FEATURE_COPROC (FPU_MVE),
2802 MVE_VSHLC,
2803 0xeea00fc0, 0xffa01ff0,
2804 "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
2805
2806 /* Vector VSHLL T2 Variant. */
2807 {ARM_FEATURE_COPROC (FPU_MVE),
2808 MVE_VSHLL_T2,
2809 0xee310e01, 0xefb30fd1,
2810 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
2811
2812 /* Vector VSHRN. */
2813 {ARM_FEATURE_COPROC (FPU_MVE),
2814 MVE_VSHRN,
2815 0xee800fc1, 0xffa00fd1,
2816 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2817
04d54ace
AV		 2818 /* Vector VST2 no writeback. */
2819 {ARM_FEATURE_COPROC (FPU_MVE),
2820 MVE_VST2,
2821 0xfc801e00, 0xffb01e5f,
2822 "vst2%5d.%7-8s\t%B, [%16-19r]"},
2823
2824 /* Vector VST2 writeback. */
2825 {ARM_FEATURE_COPROC (FPU_MVE),
2826 MVE_VST2,
2827 0xfca01e00, 0xffb01e5f,
2828 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
2829
2830 /* Vector VST4 no writeback. */
2831 {ARM_FEATURE_COPROC (FPU_MVE),
2832 MVE_VST4,
2833 0xfc801e01, 0xffb01e1f,
2834 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
2835
2836 /* Vector VST4 writeback. */
2837 {ARM_FEATURE_COPROC (FPU_MVE),
2838 MVE_VST4,
2839 0xfca01e01, 0xffb01e1f,
2840 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
2841
ef1576a1
AV		 2842 /* Vector VSTRB scatter store, T1 variant. */
2843 {ARM_FEATURE_COPROC (FPU_MVE),
2844 MVE_VSTRB_SCATTER_T1,
2845 0xec800e00, 0xffb01e50,
2846 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2847
2848 /* Vector VSTRH scatter store, T2 variant. */
2849 {ARM_FEATURE_COPROC (FPU_MVE),
2850 MVE_VSTRH_SCATTER_T2,
2851 0xec800e10, 0xffb01e50,
2852 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2853
2854 /* Vector VSTRW scatter store, T3 variant. */
2855 {ARM_FEATURE_COPROC (FPU_MVE),
2856 MVE_VSTRW_SCATTER_T3,
2857 0xec800e40, 0xffb01e50,
2858 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2859
2860 /* Vector VSTRD scatter store, T4 variant. */
2861 {ARM_FEATURE_COPROC (FPU_MVE),
2862 MVE_VSTRD_SCATTER_T4,
2863 0xec800fd0, 0xffb01fd0,
2864 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2865
2866 /* Vector VSTRW scatter store, T5 variant. */
2867 {ARM_FEATURE_COPROC (FPU_MVE),
2868 MVE_VSTRW_SCATTER_T5,
2869 0xfd001e00, 0xff111f00,
2870 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2871
2872 /* Vector VSTRD scatter store, T6 variant. */
2873 {ARM_FEATURE_COPROC (FPU_MVE),
2874 MVE_VSTRD_SCATTER_T6,
2875 0xfd001f00, 0xff111f00,
2876 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2877
aef6d006
AV		 2878 /* Vector VSTRB. */
2879 {ARM_FEATURE_COPROC (FPU_MVE),
2880 MVE_VSTRB_T1,
2881 0xec000e00, 0xfe581e00,
2882 "vstrb%v.%7-8s\t%13-15Q, %d"},
2883
2884 /* Vector VSTRH. */
2885 {ARM_FEATURE_COPROC (FPU_MVE),
2886 MVE_VSTRH_T2,
2887 0xec080e00, 0xfe581e00,
2888 "vstrh%v.%7-8s\t%13-15Q, %d"},
2889
2890 /* Vector VSTRB variant T5. */
2891 {ARM_FEATURE_COPROC (FPU_MVE),
2892 MVE_VSTRB_T5,
2893 0xec001e00, 0xfe101f80,
2894 "vstrb%v.8\t%13-15,22Q, %d"},
2895
2896 /* Vector VSTRH variant T6. */
2897 {ARM_FEATURE_COPROC (FPU_MVE),
2898 MVE_VSTRH_T6,
2899 0xec001e80, 0xfe101f80,
2900 "vstrh%v.16\t%13-15,22Q, %d"},
2901
2902 /* Vector VSTRW variant T7. */
2903 {ARM_FEATURE_COPROC (FPU_MVE),
2904 MVE_VSTRW_T7,
2905 0xec001f00, 0xfe101f80,
2906 "vstrw%v.32\t%13-15,22Q, %d"},
2907
143275ea
AV		 2908 {ARM_FEATURE_CORE_LOW (0),
2909 MVE_NONE,
2910 0x00000000, 0x00000000, 0}
73cd51e5
AV		 2911};
2912
8f06b2d8
PB		 2913/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
2914 ordered: they must be searched linearly from the top to obtain a correct
2915 match. */
2916
2917/* print_insn_arm recognizes the following format control codes:
2918
2919 %% %
2920
2921 %a print address for ldr/str instruction
2922 %s print address for ldr/str halfword/signextend instruction
c1e26897 2923 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 2924 %b print branch destination
2925 %c print condition code (always bits 28-31)
2926 %m print register mask for ldm/stm instruction
2927 %o print operand2 (immediate or register + shift)
2928 %p print 'p' iff bits 12-15 are 15
2929 %t print 't' iff bit 21 set and bit 24 clear
2930 %B print arm BLX(1) destination
2931 %C print the PSR sub type.
62b3e311
PB		 2932 %U print barrier type.
2933 %P print address for pli instruction.
8f06b2d8
PB		 2934
2935 %<bitfield>r print as an ARM register
9eb6c0f1 2936 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 2937 %<bitfield>R as %r but r15 is UNPREDICTABLE
2938 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
2939 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 2940 %<bitfield>d print the bitfield in decimal
43e65147 2941 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 2942 %<bitfield>x print the bitfield in hex
2943 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 2944
16980d0b
JB		 2945 %<bitfield>'c print specified char iff bitfield is all ones
2946 %<bitfield>`c print specified char iff bitfield is all zeroes
2947 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 2948
8f06b2d8
PB		 2949 %e print arm SMI operand (bits 0..7,8..19).
2950 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 2951 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
2952 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 2953
8f06b2d8
PB		 2954static const struct opcode32 arm_opcodes[] =
2955{
2956 /* ARM instructions. */
823d2571
TG		 2957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2958 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
2959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2960 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
2961
2962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
2963 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
2964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
2965 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
2966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
2967 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
2969 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
2970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
2971 0x00800090, 0x0fa000f0,
2972 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
2974 0x00a00090, 0x0fa000f0,
2975 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 2976
105bde57 2977 /* V8.2 RAS extension instructions. */
4d1464f2 2978 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 2979 0xe320f010, 0xffffffff, "esb"},
2980
53c4b28b 2981 /* V8 instructions. */
823d2571
TG		 2982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2983 0x0320f005, 0x0fffffff, "sevl"},
f7dd2fb2
TC		 2984 /* Defined in V8 but is in NOP space so available to all arch. */
2985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
823d2571 2986 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
4ed7ed8d 2987 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 2988 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 2989 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 2990 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2992 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
2993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2994 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 2995 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2996 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 2997 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 2998 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 2999 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3000 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3001 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3002 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3003 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3004 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3005 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3006 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3007 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3008 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3009 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3010 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3011 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3012 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3013 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 3014 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 3015 /* CRC32 instructions. */
823d2571
TG		 3016 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3017 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
3018 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3019 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
3020 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3021 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
3022 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3023 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
3024 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3025 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
3026 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3027 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 3028
ddfded2f
MW		 3029 /* Privileged Access Never extension instructions. */
3030 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
3031 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
3032
90ec0d68 3033 /* Virtualization Extension instructions. */
823d2571
TG		 3034 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
3035 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 3036
eea54501 3037 /* Integer Divide Extension instructions. */
823d2571
TG		 3038 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3039 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3040 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3041 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 3042
60e5ef9f 3043 /* MP Extension instructions. */
823d2571 3044 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 3045
c597cc3d
SD		 3046 /* Speculation Barriers. */
3047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
3048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
3049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
3050
62b3e311 3051 /* V7 instructions. */
823d2571
TG		 3052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
3053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
3054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a
AV		 3059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3060 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
62b3e311 3061
c19d1205 3062 /* ARM V6T2 instructions. */
823d2571
TG		 3063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3064 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3066 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3068 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3070 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3071
3072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3073 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
3074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3075 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3076
ff8646ee 3077 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 3078 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 3079 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3080 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3082 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3084 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 3085
f4c65163 3086 /* ARM Security extension instructions. */
823d2571
TG		 3087 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
3088 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 3089
8f06b2d8 3090 /* ARM V6K instructions. */
823d2571
TG		 3091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3092 0xf57ff01f, 0xffffffff, "clrex"},
3093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3094 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3096 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3098 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3100 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3102 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3104 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 3105
7fadb25d
SD		 3106 /* ARMv8.5-A instructions. */
3107 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
3108
8f06b2d8 3109 /* ARM V6K NOP hints. */
823d2571
TG		 3110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3111 0x0320f001, 0x0fffffff, "yield%c"},
3112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3113 0x0320f002, 0x0fffffff, "wfe%c"},
3114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3115 0x0320f003, 0x0fffffff, "wfi%c"},
3116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3117 0x0320f004, 0x0fffffff, "sev%c"},
3118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3119 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 3120
fe56b6ce 3121 /* ARM V6 instructions. */
823d2571
TG		 3122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3123 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
3124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3125 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
3126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3127 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
3128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3129 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
3130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3131 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
3132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3133 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3135 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
3136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3137 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
3138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3139 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
3140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3141 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
3142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3143 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3145 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3147 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3149 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3151 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3153 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3155 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3157 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3159 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3161 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3163 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3165 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3167 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3169 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3171 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3173 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3175 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3177 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3179 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3181 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3183 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3185 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3187 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3189 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3191 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3193 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3195 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3196 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3197 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3199 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3201 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3203 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3205 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3207 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3209 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3210 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3211 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3212 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3213 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3215 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3217 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3219 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3221 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3223 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3225 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3227 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3229 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3231 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3233 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3235 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3237 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3238 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3239 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3240 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3241 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3243 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3245 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3247 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3249 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3251 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3252 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3253 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3255 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3257 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3259 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3261 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3263 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3265 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3266 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3267 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3269 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3271 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3273 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3275 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3277 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3279 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3281 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3282 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3283 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3285 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3287 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3289 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3291 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3292 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3293 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3294 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3295 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3297 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3299 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3301 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3302 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3303 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3304 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3305 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3307 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3309 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
3310 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3311 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3313 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3315 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3317 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3319 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
3320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3321 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
3322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3323 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
3324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3325 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
3326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3327 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3329 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3331 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3333 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3335 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
3336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3337 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3339 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3341 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
3342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3343 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
3344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3345 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
3346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3347 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
3348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3349 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
3350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3351 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
3352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3353 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
3354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3355 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
3356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3357 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3359 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
3360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3361 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
3362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3363 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
3364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3365 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 3366
8f06b2d8 3367 /* V5J instruction. */
823d2571
TG		 3368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
3369 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 3370
8f06b2d8 3371 /* V5 Instructions. */
823d2571
TG		 3372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3373 0xe1200070, 0xfff000f0,
3374 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
3375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3376 0xfa000000, 0xfe000000, "blx\t%B"},
3377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3378 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
3379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3380 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
3381
3382 /* V5E "El Segundo" Instructions. */
3383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3384 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
3385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3386 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
3387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3388 0xf450f000, 0xfc70f000, "pld\t%a"},
3389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3390 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3392 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3394 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3395 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3396 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
3397
3398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3399 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3401 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
3402
3403 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3404 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3406 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3408 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3410 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3411
3412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3413 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
3414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3415 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
3416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3417 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
3418 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3419 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
3420
3421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3422 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
3423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3424 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
3425
3426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3427 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
3428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3429 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
3430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3431 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
3432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3433 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 3434
8f06b2d8 3435 /* ARM Instructions. */
823d2571
TG		 3436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3437 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
3438
3439 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3440 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
3441 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3442 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
3443 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3444 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
3445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3446 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
3447 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3448 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
3449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3450 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
3451
3452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3453 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
3454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3455 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
3456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3457 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
3458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3459 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
3460
3461 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3462 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
3463 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3464 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
3465 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3466 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
3467 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3468 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
3469
3470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3471 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
3472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3473 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
3474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3475 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
3476
3477 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3478 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
3479 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3480 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
3481 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3482 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
3483
3484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3485 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
3486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3487 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
3488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3489 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
3490
3491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3492 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3494 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3495 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3496 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
3497
3498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3499 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
3500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3501 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
3502 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3503 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
3504
3505 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3506 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
3507 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3508 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
3509 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3510 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
3511
3512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3513 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3515 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3517 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
3518
3519 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3520 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3521 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3522 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3523 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3524 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
3525
3526 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
3527 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
3528 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
3529 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
3530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
3531 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
3532
3533 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3534 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
3535 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3536 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
3537 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3538 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
3539
3540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 3541 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 3542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 3543 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 3544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 3545 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
823d2571
TG		 3546
3547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3548 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
3549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3550 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
3551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3552 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
3553
3554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3555 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
3556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3557 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
3558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3559 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
3560
3561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3562 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
3563 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3564 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
3565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3566 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
3567
3568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3569 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
3570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3571 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
3572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3573 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
3574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3575 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
3576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3577 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
3578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3579 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
3580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3581 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
3582
3583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3584 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
3585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3586 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
3587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3588 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
3589
3590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3591 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
3592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3593 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
3594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3595 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
3596
3597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3598 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
3599 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3600 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
3601
3602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3603 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
3604
3605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3606 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
3607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3608 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
3609
3610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3611 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3613 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3615 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3617 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3619 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3621 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3622 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3623 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3625 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3627 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3629 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3631 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3633 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3635 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3637 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3639 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3641 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3643 0x092d0000, 0x0fff0000, "push%c\t%m"},
3644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3645 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
3646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3647 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3648
3649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3650 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3652 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3654 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3656 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3657 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3658 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3660 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3662 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3664 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3666 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3667 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3668 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3669 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3670 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3672 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3673 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3674 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3676 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3678 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3680 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3682 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
3683 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3684 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
3685 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3686 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3687
3688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3689 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
3690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3691 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 3692
3693 /* The rest. */
4ab90a7a
AV		 3694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3695 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 3696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3697 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3698 {ARM_FEATURE_CORE_LOW (0),
3699 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 3700};
3701
3702/* print_insn_thumb16 recognizes the following format control codes:
3703
3704 %S print Thumb register (bits 3..5 as high number if bit 6 set)
3705 %D print Thumb register (bits 0..2 as high number if bit 7 set)
3706 %<bitfield>I print bitfield as a signed decimal
3707 (top bit of range being the sign bit)
3708 %N print Thumb register mask (with LR)
3709 %O print Thumb register mask (with PC)
3710 %M print Thumb register mask
3711 %b print CZB's 6-bit unsigned branch destination
3712 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 3713 %c print the condition code
3714 %C print the condition code, or "s" if not conditional
3715 %x print warning if conditional an not at end of IT block"
3716 %X print "\t; unpredictable <IT:code>" if conditional
3717 %I print IT instruction suffix and operands
4547cb56 3718 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 3719 %<bitfield>r print bitfield as an ARM register
3720 %<bitfield>d print bitfield as a decimal
3721 %<bitfield>H print (bitfield * 2) as a decimal
3722 %<bitfield>W print (bitfield * 4) as a decimal
3723 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
3724 %<bitfield>B print Thumb branch destination (signed displacement)
3725 %<bitfield>c print bitfield as a condition code
3726 %<bitnum>'c print specified char iff bit is one
3727 %<bitnum>?ab print a if bit is one else print b. */
3728
3729static const struct opcode16 thumb_opcodes[] =
3730{
3731 /* Thumb instructions. */
3732
16a1fa25
TP		 3733 /* ARMv8-M Security Extensions instructions. */
3734 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
e207bc53 3735 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
16a1fa25 3736
53c4b28b 3737 /* ARM V8 instructions. */
823d2571
TG		 3738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
3739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
ddfded2f 3740 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
53c4b28b 3741
8f06b2d8 3742 /* ARM V6K no-argument instructions. */
823d2571
TG		 3743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
3744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
3745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
3746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
3747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
3748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 3749
3750 /* ARM V6T2 instructions. */
ff8646ee
TP		 3751 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3752 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
3753 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3754 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 3755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 3756
3757 /* ARM V6. */
823d2571
TG		 3758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
3759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
3760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
3761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
3762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
3763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
3764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
3765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
3766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
3767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
3768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 3769
3770 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 3771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
3772 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 3773 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 3774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
3775 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 3776 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 3777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3778 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 3779 /* Format 4. */
823d2571
TG		 3780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
3781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
3782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
3783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
3784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
3785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
3786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
3787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
3788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
3789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
3790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
3791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
3792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
3793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
3794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
3795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 3796 /* format 13 */
823d2571
TG		 3797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
3798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 3799 /* format 5 */
823d2571
TG		 3800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
3801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
3802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
3803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 3804 /* format 14 */
823d2571
TG		 3805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
3806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 3807 /* format 2 */
823d2571
TG		 3808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3809 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
3810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3811 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
3812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3813 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
3814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3815 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 3816 /* format 8 */
823d2571
TG		 3817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3818 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
3819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3820 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
3821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3822 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 3823 /* format 7 */
823d2571
TG		 3824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3825 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
3826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3827 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 3828 /* format 1 */
823d2571
TG		 3829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
3830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3831 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
3832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
3833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 3834 /* format 3 */
823d2571
TG		 3835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
3836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
3837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
3838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 3839 /* format 6 */
823d2571
TG		 3840 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
3841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3842 0x4800, 0xF800,
3843 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 3844 /* format 9 */
823d2571
TG		 3845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3846 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
3847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3848 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
3849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3850 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
3851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3852 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 3853 /* format 10 */
823d2571
TG		 3854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3855 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
3856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3857 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 3858 /* format 11 */
823d2571
TG		 3859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3860 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
3861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3862 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 3863 /* format 12 */
823d2571
TG		 3864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3865 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
3866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3867 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 3868 /* format 15 */
823d2571
TG		 3869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
3870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 3871 /* format 17 */
823d2571 3872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 3873 /* format 16 */
823d2571
TG		 3874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
3875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
3876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 3877 /* format 18 */
823d2571 3878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 3879
3880 /* The E800 .. FFFF range is unconditionally redirected to the
3881 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
3882 are processed via that table. Thus, we can never encounter a
3883 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 3884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
3885 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 3886};
3887
3888/* Thumb32 opcodes use the same table structure as the ARM opcodes.
3889 We adopt the convention that hw1 is the high 16 bits of .value and
3890 .mask, hw2 the low 16 bits.
3891
3892 print_insn_thumb32 recognizes the following format control codes:
3893
3894 %% %
3895
3896 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
3897 %M print a modified 12-bit immediate (same location)
3898 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
3899 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 3900 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 3901 %S print a possibly-shifted Rm
3902
32a94698 3903 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 3904 %a print the address of a plain load/store
3905 %w print the width and signedness of a core load/store
3906 %m print register mask for ldm/stm
4b5a202f 3907 %n print register mask for clrm
8f06b2d8
PB		 3908
3909 %E print the lsb and width fields of a bfc/bfi instruction
3910 %F print the lsb and width fields of a sbfx/ubfx instruction
e12437dc 3911 %G print a fallback offset for Branch Future instructions
e5d6e09e 3912 %W print an offset for BF instruction
1caf72a5 3913 %Y print an offset for BFL instruction
1889da70 3914 %Z print an offset for BFCSEL instruction
60f993ce
AV		 3915 %Q print an offset for Low Overhead Loop instructions
3916 %P print an offset for Low Overhead Loop end instructions
8f06b2d8
PB		 3917 %b print a conditional branch offset
3918 %B print an unconditional branch offset
3919 %s print the shift field of an SSAT instruction
3920 %R print the rotation field of an SXT instruction
62b3e311
PB		 3921 %U print barrier type.
3922 %P print address for pli instruction.
c22aaad1
PB		 3923 %c print the condition code
3924 %x print warning if conditional an not at end of IT block"
3925 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 3926
3927 %<bitfield>d print bitfield in decimal
f0fba320 3928 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 3929 %<bitfield>W print bitfield*4 in decimal
3930 %<bitfield>r print bitfield as an ARM register
dd5181d5 3931 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
f1c7f421 3932 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
8f06b2d8
PB		 3933 %<bitfield>c print bitfield as a condition code
3934
16980d0b
JB		 3935 %<bitfield>'c print specified char iff bitfield is all ones
3936 %<bitfield>`c print specified char iff bitfield is all zeroes
3937 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 3938
3939 With one exception at the bottom (done because BL and BLX(1) need
3940 to come dead last), this table was machine-sorted first in
3941 decreasing order of number of bits set in the mask, then in
3942 increasing numeric order of mask, then in increasing numeric order
3943 of opcode. This order is not the clearest for a human reader, but
3944 is guaranteed never to catch a special-case bit pattern with a more
3945 general mask, which is important, because this instruction encoding
3946 makes heavy use of special-case bit patterns. */
3947static const struct opcode32 thumb32_opcodes[] =
3948{
4b5a202f
AV		 3949 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
3950 instructions. */
60f993ce 3951 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
d052b9b7 3952 0xf00fe001, 0xffffffff, "lctp%c"},
60f993ce
AV		 3953 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3954 0xf02fc001, 0xfffff001, "le\t%P"},
3955 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3956 0xf00fc001, 0xfffff001, "le\tlr, %P"},
d052b9b7
AV		 3957 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3958 0xf01fc001, 0xfffff001, "letp\tlr, %P"},
3959 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3960 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
3961 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3962 0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
3963 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3964 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
3965 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3966 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
60f993ce 3967
4389b29a
AV		 3968 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3969 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
f1c7f421
AV		 3970 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3971 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
65d1bc05
AV		 3972 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3973 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
f1c7f421
AV		 3974 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3975 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
f6b2b12d
AV		 3976 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3977 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4389b29a 3978
4b5a202f
AV		 3979 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3980 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4389b29a 3981
16a1fa25
TP		 3982 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
3983 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4ed7ed8d
TP		 3984 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3985 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
3986 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3987 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
16a1fa25
TP		 3988 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3989 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
3990 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
3991 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4ed7ed8d 3992
105bde57 3993 /* ARM V8.2 RAS extension instructions. */
4d1464f2 3994 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 3995 0xf3af8010, 0xffffffff, "esb"},
3996
53c4b28b 3997 /* V8 instructions. */
823d2571
TG		 3998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3999 0xf3af8005, 0xffffffff, "sevl%c.w"},
4000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4001 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4003 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4005 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4007 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4009 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4011 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4013 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4015 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4017 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4019 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4021 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4023 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4025 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4027 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4029 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 4030
dd5181d5 4031 /* CRC32 instructions. */
823d2571 4032 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4033 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
823d2571 4034 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4035 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
823d2571 4036 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4037 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
823d2571 4038 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4039 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
823d2571 4040 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4041 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
823d2571 4042 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4043 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
dd5181d5 4044
c597cc3d
SD		 4045 /* Speculation Barriers. */
4046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
4047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
4048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
4049
62b3e311 4050 /* V7 instructions. */
823d2571
TG		 4051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
4053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4058 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4059 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4060 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4061 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 4062
90ec0d68 4063 /* Virtualization Extension instructions. */
823d2571 4064 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 4065 /* We skip ERET as that is SUBS pc, lr, #0. */
4066
60e5ef9f 4067 /* MP Extension instructions. */
823d2571 4068 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 4069
f4c65163 4070 /* Security extension instructions. */
823d2571 4071 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 4072
7fadb25d
SD		 4073 /* ARMv8.5-A instructions. */
4074 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
4075
8f06b2d8 4076 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 4077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
4078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
4079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
4082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4083 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
4084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4085
ff8646ee 4086 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4087 0xf3bf8f2f, 0xffffffff, "clrex%c"},
4088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4089 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
4090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4091 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
4092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4093 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4095 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4097 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4099 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4101 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
4102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4103 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4105 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
4106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4107 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
4108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4109 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
4110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4111 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
4112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4113 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 4114 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 4115 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 4116 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4117 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4119 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
4120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4121 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
4122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4123 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4125 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4127 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4129 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4131 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4133 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 4134 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4135 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4137 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4139 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4141 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4143 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4145 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4147 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4149 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4151 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4153 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4155 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4157 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4159 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4161 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4163 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4165 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4167 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4169 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4171 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4173 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4175 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4177 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4179 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4181 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4183 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4185 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4187 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4189 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4191 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4193 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4195 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4196 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4197 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4199 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4201 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4203 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4205 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4207 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4209 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4210 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4211 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4212 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4213 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4215 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4217 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4219 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4221 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4223 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4225 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4227 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4229 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4231 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4233 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4235 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4237 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4238 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4239 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4240 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4241 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 4242 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4243 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 4245 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 4246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4247 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4249 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4251 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4252 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4253 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4255 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4257 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4259 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4261 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4263 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4265 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4266 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4267 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4269 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4271 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4273 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4275 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4277 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4279 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4281 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4282 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4283 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4285 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4287 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4289 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4291 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4292 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4293 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4294 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4295 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4297 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4299 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4301 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4302 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4303 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4304 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4305 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4307 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4309 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 4310 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4311 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
4312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4313 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
4314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4315 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
4316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4317 0xf810f000, 0xff70f000, "pld%c\t%a"},
4318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4319 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4321 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4323 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4325 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4327 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4329 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4331 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4333 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
4334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4335 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
4336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4337 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
4338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4339 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
4340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4341 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
4342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4343 0xfb100000, 0xfff000c0,
4344 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4345 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4346 0xfbc00080, 0xfff000c0,
4347 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
4348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4349 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
4350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4351 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
4352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 4353 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 4354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4355 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
4356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4357 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 4358 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4359 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
4360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4361 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 4362 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4363 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
4364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4365 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
4366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4367 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
4368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4369 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
4370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4371 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
4372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4373 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
4374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4375 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
4376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4377 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
4378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4379 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
4380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4381 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
4382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4383 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 4384 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4385 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
4386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4387 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
4388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4389 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
4390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4391 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
4392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4393 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
4394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4395 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
4396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4397 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
4398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4399 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
4400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4401 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
4402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4403 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
4404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4405 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
4406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4407 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
4408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4409 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
4410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4411 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
4412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4413 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
4414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4415 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
4416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4417 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
4418 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4419 0xe9400000, 0xff500000,
4420 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4422 0xe9500000, 0xff500000,
4423 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4425 0xe8600000, 0xff700000,
4426 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4427 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4428 0xe8700000, 0xff700000,
4429 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4431 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
4432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4433 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 4434
4435 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 4436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4437 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
4438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4439 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
4440 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4441 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
4442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4443 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 4444
8f06b2d8 4445 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 4446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4447 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
4448 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4449 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 4450
4451 /* Fallback. */
823d2571
TG		 4452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4453 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4454 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 4455};
ff4a8d2b 4456
8f06b2d8
PB		 4457static const char *const arm_conditional[] =
4458{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 4459 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 4460
4461static const char *const arm_fp_const[] =
4462{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
4463
4464static const char *const arm_shift[] =
4465{"lsl", "lsr", "asr", "ror"};
4466
4467typedef struct
4468{
4469 const char *name;
4470 const char *description;
4471 const char *reg_names[16];
4472}
4473arm_regname;
4474
4475static const arm_regname regnames[] =
4476{
65b48a81 4477 { "reg-names-raw", N_("Select raw register names"),
8f06b2d8 4478 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
65b48a81 4479 { "reg-names-gcc", N_("Select register names used by GCC"),
8f06b2d8 4480 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 4481 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
8f06b2d8 4482 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65b48a81
PB		 4483 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
4484 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
4485 { "reg-names-apcs", N_("Select register names used in the APCS"),
8f06b2d8 4486 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 4487 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
8f06b2d8 4488 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
65b48a81
PB		 4489 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
4490 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
8f06b2d8
PB		 4491};
4492
4493static const char *const iwmmxt_wwnames[] =
4494{"b", "h", "w", "d"};
4495
4496static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 4497{"b", "bus", "bc", "bss",
4498 "h", "hus", "hc", "hss",
4499 "w", "wus", "wc", "wss",
4500 "d", "dus", "dc", "dss"
8f06b2d8
PB		 4501};
4502
4503static const char *const iwmmxt_regnames[] =
4504{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
4505 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
4506};
4507
4508static const char *const iwmmxt_cregnames[] =
4509{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
4510 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
4511};
4512
143275ea
AV		 4513static const char *const vec_condnames[] =
4514{ "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
4515};
4516
4517static const char *const mve_predicatenames[] =
4518{ "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
4519 "eee", "ee", "eet", "e", "ett", "et", "ete"
4520};
4521
4522/* Names for 2-bit size field for mve vector isntructions. */
4523static const char *const mve_vec_sizename[] =
4524 { "8", "16", "32", "64"};
4525
4526/* Indicates whether we are processing a then predicate,
4527 else predicate or none at all. */
4528enum vpt_pred_state
4529{
4530 PRED_NONE,
4531 PRED_THEN,
4532 PRED_ELSE
4533};
4534
4535/* Information used to process a vpt block and subsequent instructions. */
4536struct vpt_block
4537{
4538 /* Are we in a vpt block. */
4539 bfd_boolean in_vpt_block;
4540
4541 /* Next predicate state if in vpt block. */
4542 enum vpt_pred_state next_pred_state;
4543
4544 /* Mask from vpt/vpst instruction. */
4545 long predicate_mask;
4546
4547 /* Instruction number in vpt block. */
4548 long current_insn_num;
4549
4550 /* Number of instructions in vpt block.. */
4551 long num_pred_insn;
4552};
4553
4554static struct vpt_block vpt_block_state =
4555{
4556 FALSE,
4557 PRED_NONE,
4558 0,
4559 0,
4560 0
4561};
4562
8f06b2d8
PB		 4563/* Default to GCC register name set. */
4564static unsigned int regname_selected = 1;
4565
65b48a81 4566#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
8f06b2d8
PB		 4567#define arm_regnames regnames[regname_selected].reg_names
4568
4569static bfd_boolean force_thumb = FALSE;
4570
c22aaad1
PB		 4571/* Current IT instruction state. This contains the same state as the IT
4572 bits in the CPSR. */
4573static unsigned int ifthen_state;
4574/* IT state for the next instruction. */
4575static unsigned int ifthen_next_state;
4576/* The address of the insn for which the IT state is valid. */
4577static bfd_vma ifthen_address;
4578#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 4579/* Indicates that the current Conditional state is unconditional or outside
4580 an IT block. */
4581#define COND_UNCOND 16
c22aaad1 4582
8f06b2d8
PB		 4583\f
4584/* Functions. */
143275ea
AV		 4585/* Extract the predicate mask for a VPT or VPST instruction.
4586 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
4587
4588static long
4589mve_extract_pred_mask (long given)
4590{
4591 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
4592}
4593
4594/* Return the number of instructions in a MVE predicate block. */
4595static long
4596num_instructions_vpt_block (long given)
4597{
4598 long mask = mve_extract_pred_mask (given);
4599 if (mask == 0)
4600 return 0;
4601
4602 if (mask == 8)
4603 return 1;
4604
4605 if ((mask & 7) == 4)
4606 return 2;
4607
4608 if ((mask & 3) == 2)
4609 return 3;
4610
4611 if ((mask & 1) == 1)
4612 return 4;
4613
4614 return 0;
4615}
4616
4617static void
4618mark_outside_vpt_block (void)
4619{
4620 vpt_block_state.in_vpt_block = FALSE;
4621 vpt_block_state.next_pred_state = PRED_NONE;
4622 vpt_block_state.predicate_mask = 0;
4623 vpt_block_state.current_insn_num = 0;
4624 vpt_block_state.num_pred_insn = 0;
4625}
4626
4627static void
4628mark_inside_vpt_block (long given)
4629{
4630 vpt_block_state.in_vpt_block = TRUE;
4631 vpt_block_state.next_pred_state = PRED_THEN;
4632 vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
4633 vpt_block_state.current_insn_num = 0;
4634 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
4635 assert (vpt_block_state.num_pred_insn >= 1);
4636}
4637
4638static enum vpt_pred_state
4639invert_next_predicate_state (enum vpt_pred_state astate)
4640{
4641 if (astate == PRED_THEN)
4642 return PRED_ELSE;
4643 else if (astate == PRED_ELSE)
4644 return PRED_THEN;
4645 else
4646 return PRED_NONE;
4647}
4648
4649static enum vpt_pred_state
4650update_next_predicate_state (void)
4651{
4652 long pred_mask = vpt_block_state.predicate_mask;
4653 long mask_for_insn = 0;
4654
4655 switch (vpt_block_state.current_insn_num)
4656 {
4657 case 1:
4658 mask_for_insn = 8;
4659 break;
4660
4661 case 2:
4662 mask_for_insn = 4;
4663 break;
4664
4665 case 3:
4666 mask_for_insn = 2;
4667 break;
4668
4669 case 4:
4670 return PRED_NONE;
4671 }
4672
4673 if (pred_mask & mask_for_insn)
4674 return invert_next_predicate_state (vpt_block_state.next_pred_state);
4675 else
4676 return vpt_block_state.next_pred_state;
4677}
4678
4679static void
4680update_vpt_block_state (void)
4681{
4682 vpt_block_state.current_insn_num++;
4683 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
4684 {
4685 /* No more instructions to process in vpt block. */
4686 mark_outside_vpt_block ();
4687 return;
4688 }
4689
4690 vpt_block_state.next_pred_state = update_next_predicate_state ();
4691}
8f06b2d8 4692
16980d0b
JB		 4693/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
4694 Returns pointer to following character of the format string and
4695 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 4696 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 4697
4698static const char *
fe56b6ce
NC		 4699arm_decode_bitfield (const char *ptr,
4700 unsigned long insn,
4701 unsigned long *valuep,
4702 int *widthp)
16980d0b
JB		 4703{
4704 unsigned long value = 0;
4705 int width = 0;
43e65147
L		 4706
4707 do
16980d0b
JB		 4708 {
4709 int start, end;
4710 int bits;
4711
4712 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
4713 start = start * 10 + *ptr - '0';
4714 if (*ptr == '-')
4715 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
4716 end = end * 10 + *ptr - '0';
4717 else
4718 end = start;
4719 bits = end - start;
4720 if (bits < 0)
4721 abort ();
4722 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
4723 width += bits + 1;
4724 }
4725 while (*ptr++ == ',');
4726 *valuep = value;
4727 if (widthp)
4728 *widthp = width;
4729 return ptr - 1;
4730}
4731
8f06b2d8 4732static void
37b37b2d 4733arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 4734 bfd_boolean print_shift)
8f06b2d8
PB		 4735{
4736 func (stream, "%s", arm_regnames[given & 0xf]);
4737
4738 if ((given & 0xff0) != 0)
4739 {
4740 if ((given & 0x10) == 0)
4741 {
4742 int amount = (given & 0xf80) >> 7;
4743 int shift = (given & 0x60) >> 5;
4744
4745 if (amount == 0)
4746 {
4747 if (shift == 3)
4748 {
4749 func (stream, ", rrx");
4750 return;
4751 }
4752
4753 amount = 32;
4754 }
4755
37b37b2d
RE		 4756 if (print_shift)
4757 func (stream, ", %s #%d", arm_shift[shift], amount);
4758 else
4759 func (stream, ", #%d", amount);
8f06b2d8 4760 }
74bdfecf 4761 else if ((given & 0x80) == 0x80)
aefd8a40 4762 func (stream, "\t; <illegal shifter operand>");
37b37b2d 4763 else if (print_shift)
8f06b2d8
PB		 4764 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
4765 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 4766 else
4767 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 4768 }
4769}
4770
73cd51e5
AV		 4771/* Return TRUE if the MATCHED_INSN can be inside an IT block. */
4772
4773static bfd_boolean
4774is_mve_okay_in_it (enum mve_instructions matched_insn)
4775{
c507f10b
AV		 4776 switch (matched_insn)
4777 {
4778 case MVE_VMOV_GP_TO_VEC_LANE:
4779 case MVE_VMOV2_VEC_LANE_TO_GP:
4780 case MVE_VMOV2_GP_TO_VEC_LANE:
4781 case MVE_VMOV_VEC_LANE_TO_GP:
4782 return TRUE;
4783 default:
4784 return FALSE;
4785 }
73cd51e5
AV		 4786}
4787
4788static bfd_boolean
4789is_mve_architecture (struct disassemble_info *info)
4790{
4791 struct arm_private_data *private_data = info->private_data;
4792 arm_feature_set allowed_arches = private_data->features;
4793
4794 arm_feature_set arm_ext_v8_1m_main
4795 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
4796
4797 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
4798 && !ARM_CPU_IS_ANY (allowed_arches))
4799 return TRUE;
4800 else
4801 return FALSE;
4802}
4803
143275ea
AV		 4804static bfd_boolean
4805is_vpt_instruction (long given)
4806{
4807
4808 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
4809 if ((given & 0x0040e000) == 0)
4810 return FALSE;
4811
4812 /* VPT floating point T1 variant. */
4813 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
4814 /* VPT floating point T2 variant. */
4815 || ((given & 0xefb10f50) == 0xee310f40)
4816 /* VPT vector T1 variant. */
4817 || ((given & 0xff811f51) == 0xfe010f00)
4818 /* VPT vector T2 variant. */
4819 || ((given & 0xff811f51) == 0xfe010f01
4820 && ((given & 0x300000) != 0x300000))
4821 /* VPT vector T3 variant. */
4822 || ((given & 0xff811f50) == 0xfe011f00)
4823 /* VPT vector T4 variant. */
4824 || ((given & 0xff811f70) == 0xfe010f40)
4825 /* VPT vector T5 variant. */
4826 || ((given & 0xff811f70) == 0xfe010f60)
4827 /* VPT vector T6 variant. */
4828 || ((given & 0xff811f50) == 0xfe011f40)
4829 /* VPST vector T variant. */
4830 || ((given & 0xffbf1fff) == 0xfe310f4d))
4831 return TRUE;
4832 else
4833 return FALSE;
4834}
4835
73cd51e5
AV		 4836/* Decode a bitfield from opcode GIVEN, with starting bitfield = START
4837 and ending bitfield = END. END must be greater than START. */
4838
4839static unsigned long
4840arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
4841{
4842 int bits = end - start;
4843
4844 if (bits < 0)
4845 abort ();
4846
4847 return ((given >> start) & ((2ul << bits) - 1));
4848}
4849
4850/* Decode a bitfield from opcode GIVEN, with multiple bitfields:
4851 START:END and START2:END2. END/END2 must be greater than
4852 START/START2. */
4853
4854static unsigned long
4855arm_decode_field_multiple (unsigned long given, unsigned int start,
4856 unsigned int end, unsigned int start2,
4857 unsigned int end2)
4858{
4859 int bits = end - start;
4860 int bits2 = end2 - start2;
4861 unsigned long value = 0;
4862 int width = 0;
4863
4864 if (bits2 < 0)
4865 abort ();
4866
4867 value = arm_decode_field (given, start, end);
4868 width += bits + 1;
4869
4870 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
4871 return value;
4872}
4873
4874/* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
4875 This helps us decode instructions that change mnemonic depending on specific
4876 operand values/encodings. */
4877
4878static bfd_boolean
4879is_mve_encoding_conflict (unsigned long given,
4880 enum mve_instructions matched_insn)
4881{
143275ea
AV		 4882 switch (matched_insn)
4883 {
4884 case MVE_VPST:
4885 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4886 return TRUE;
4887 else
4888 return FALSE;
4889
4890 case MVE_VPT_FP_T1:
4891 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4892 return TRUE;
4893 if ((arm_decode_field (given, 12, 12) == 0)
4894 && (arm_decode_field (given, 0, 0) == 1))
4895 return TRUE;
4896 return FALSE;
4897
4898 case MVE_VPT_FP_T2:
4899 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4900 return TRUE;
4901 if (arm_decode_field (given, 0, 3) == 0xd)
4902 return TRUE;
4903 return FALSE;
4904
4905 case MVE_VPT_VEC_T1:
4906 case MVE_VPT_VEC_T2:
4907 case MVE_VPT_VEC_T3:
4908 case MVE_VPT_VEC_T4:
4909 case MVE_VPT_VEC_T5:
4910 case MVE_VPT_VEC_T6:
4911 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
4912 return TRUE;
4913 if (arm_decode_field (given, 20, 21) == 3)
4914 return TRUE;
4915 return FALSE;
4916
4917 case MVE_VCMP_FP_T1:
4918 if ((arm_decode_field (given, 12, 12) == 0)
4919 && (arm_decode_field (given, 0, 0) == 1))
4920 return TRUE;
4921 else
4922 return FALSE;
4923
4924 case MVE_VCMP_FP_T2:
4925 if (arm_decode_field (given, 0, 3) == 0xd)
4926 return TRUE;
4927 else
4928 return FALSE;
4929
ed63aa17
AV		 4930 case MVE_VQRSHL_T1:
4931 case MVE_VQSHL_T4:
4932 case MVE_VRSHL_T1:
4933 case MVE_VSHL_T3:
897b9bbc
AV		 4934 case MVE_VCADD_VEC:
4935 case MVE_VHCADD:
1c8f2df8
AV		 4936 case MVE_VDDUP:
4937 case MVE_VIDUP:
d3b63143
AV		 4938 case MVE_VQRDMLADH:
4939 case MVE_VQDMLAH:
4940 case MVE_VQRDMLAH:
4941 case MVE_VQDMLASH:
4942 case MVE_VQRDMLASH:
4943 case MVE_VQDMLSDH:
4944 case MVE_VQRDMLSDH:
4945 case MVE_VQDMULH_T3:
4946 case MVE_VQRDMULH_T4:
4947 case MVE_VQDMLADH:
4948 case MVE_VMLAS:
14925797 4949 case MVE_VMULL_INT:
9743db03
AV		 4950 case MVE_VHADD_T2:
4951 case MVE_VHSUB_T2:
143275ea
AV		 4952 case MVE_VCMP_VEC_T1:
4953 case MVE_VCMP_VEC_T2:
4954 case MVE_VCMP_VEC_T3:
4955 case MVE_VCMP_VEC_T4:
4956 case MVE_VCMP_VEC_T5:
4957 case MVE_VCMP_VEC_T6:
4958 if (arm_decode_field (given, 20, 21) == 3)
4959 return TRUE;
4960 else
4961 return FALSE;
4962
04d54ace
AV		 4963 case MVE_VLD2:
4964 case MVE_VLD4:
4965 case MVE_VST2:
4966 case MVE_VST4:
4967 if (arm_decode_field (given, 7, 8) == 3)
4968 return TRUE;
4969 else
4970 return FALSE;
4971
aef6d006
AV		 4972 case MVE_VSTRB_T1:
4973 case MVE_VSTRH_T2:
4974 if ((arm_decode_field (given, 24, 24) == 0)
4975 && (arm_decode_field (given, 21, 21) == 0))
4976 {
4977 return TRUE;
4978 }
4979 else if ((arm_decode_field (given, 7, 8) == 3))
4980 return TRUE;
4981 else
4982 return FALSE;
4983
4984 case MVE_VSTRB_T5:
4985 case MVE_VSTRH_T6:
4986 case MVE_VSTRW_T7:
4987 if ((arm_decode_field (given, 24, 24) == 0)
4988 && (arm_decode_field (given, 21, 21) == 0))
4989 {
4990 return TRUE;
4991 }
4992 else
4993 return FALSE;
4994
bf0b396d
AV		 4995 case MVE_VCVT_FP_FIX_VEC:
4996 return (arm_decode_field (given, 16, 21) & 0x38) == 0;
4997
c507f10b
AV		 4998 case MVE_VBIC_IMM:
4999 case MVE_VORR_IMM:
5000 {
5001 unsigned long cmode = arm_decode_field (given, 8, 11);
5002
5003 if ((cmode & 1) == 0)
5004 return TRUE;
5005 else if ((cmode & 0xc) == 0xc)
5006 return TRUE;
5007 else
5008 return FALSE;
5009 }
5010
5011 case MVE_VMVN_IMM:
5012 {
5013 unsigned long cmode = arm_decode_field (given, 8, 11);
5014
5015 if ((cmode & 9) == 1)
5016 return TRUE;
5017 else if ((cmode & 5) == 1)
5018 return TRUE;
5019 else if ((cmode & 0xe) == 0xe)
5020 return TRUE;
5021 else
5022 return FALSE;
5023 }
5024
5025 case MVE_VMOV_IMM_TO_VEC:
5026 if ((arm_decode_field (given, 5, 5) == 1)
5027 && (arm_decode_field (given, 8, 11) != 0xe))
5028 return TRUE;
5029 else
5030 return FALSE;
5031
14925797
AV		 5032 case MVE_VMOVL:
5033 {
5034 unsigned long size = arm_decode_field (given, 19, 20);
5035 if ((size == 0) || (size == 3))
5036 return TRUE;
5037 else
5038 return FALSE;
5039 }
5040
ed63aa17
AV		 5041 case MVE_VQRSHL_T2:
5042 case MVE_VQSHL_T1:
5043 case MVE_VRSHL_T2:
5044 case MVE_VSHL_T2:
5045 case MVE_VSHLL_T2:
d3b63143 5046 case MVE_VADDV:
14925797
AV		 5047 case MVE_VMOVN:
5048 case MVE_VQMOVUN:
5049 case MVE_VQMOVN:
5050 if (arm_decode_field (given, 18, 19) == 3)
5051 return TRUE;
5052 else
5053 return FALSE;
5054
d3b63143
AV		 5055 case MVE_VMLSLDAV:
5056 case MVE_VRMLSLDAVH:
5057 case MVE_VMLALDAV:
5058 case MVE_VADDLV:
5059 if (arm_decode_field (given, 20, 22) == 7)
5060 return TRUE;
5061 else
5062 return FALSE;
5063
5064 case MVE_VRMLALDAVH:
5065 if ((arm_decode_field (given, 20, 22) & 6) == 6)
5066 return TRUE;
5067 else
5068 return FALSE;
5069
1c8f2df8
AV		 5070 case MVE_VDWDUP:
5071 case MVE_VIWDUP:
5072 if ((arm_decode_field (given, 20, 21) == 3)
5073 || (arm_decode_field (given, 1, 3) == 7))
5074 return TRUE;
5075 else
5076 return FALSE;
5077
ed63aa17
AV		 5078
5079 case MVE_VSHLL_T1:
5080 if (arm_decode_field (given, 16, 18) == 0)
5081 {
5082 unsigned long sz = arm_decode_field (given, 19, 20);
5083
5084 if ((sz == 1) || (sz == 2))
5085 return TRUE;
5086 else
5087 return FALSE;
5088 }
5089 else
5090 return FALSE;
5091
5092 case MVE_VQSHL_T2:
5093 case MVE_VQSHLU_T3:
5094 case MVE_VRSHR:
5095 case MVE_VSHL_T1:
5096 case MVE_VSHR:
5097 case MVE_VSLI:
5098 case MVE_VSRI:
5099 if (arm_decode_field (given, 19, 21) == 0)
5100 return TRUE;
5101 else
5102 return FALSE;
5103
143275ea
AV		 5104 default:
5105 return FALSE;
5106
5107 }
73cd51e5
AV		 5108}
5109
aef6d006
AV		 5110static void
5111print_mve_vld_str_addr (struct disassemble_info *info,
5112 unsigned long given,
5113 enum mve_instructions matched_insn)
5114{
5115 void *stream = info->stream;
5116 fprintf_ftype func = info->fprintf_func;
5117
5118 unsigned long p, w, gpr, imm, add, mod_imm;
5119
5120 imm = arm_decode_field (given, 0, 6);
5121 mod_imm = imm;
5122
5123 switch (matched_insn)
5124 {
5125 case MVE_VLDRB_T1:
5126 case MVE_VSTRB_T1:
5127 gpr = arm_decode_field (given, 16, 18);
5128 break;
5129
5130 case MVE_VLDRH_T2:
5131 case MVE_VSTRH_T2:
5132 gpr = arm_decode_field (given, 16, 18);
5133 mod_imm = imm << 1;
5134 break;
5135
5136 case MVE_VLDRH_T6:
5137 case MVE_VSTRH_T6:
5138 gpr = arm_decode_field (given, 16, 19);
5139 mod_imm = imm << 1;
5140 break;
5141
5142 case MVE_VLDRW_T7:
5143 case MVE_VSTRW_T7:
5144 gpr = arm_decode_field (given, 16, 19);
5145 mod_imm = imm << 2;
5146 break;
5147
5148 case MVE_VLDRB_T5:
5149 case MVE_VSTRB_T5:
5150 gpr = arm_decode_field (given, 16, 19);
5151 break;
5152
5153 default:
5154 return;
5155 }
5156
5157 p = arm_decode_field (given, 24, 24);
5158 w = arm_decode_field (given, 21, 21);
5159
5160 add = arm_decode_field (given, 23, 23);
5161
5162 char * add_sub;
5163
5164 /* Don't print anything for '+' as it is implied. */
5165 if (add == 1)
5166 add_sub = "";
5167 else
5168 add_sub = "-";
5169
5170 if (p == 1)
5171 {
5172 /* Offset mode. */
5173 if (w == 0)
5174 func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm);
5175 /* Pre-indexed mode. */
5176 else
5177 func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm);
5178 }
5179 else if ((p == 0) && (w == 1))
5180 /* Post-index mode. */
5181 func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm);
5182}
5183
73cd51e5
AV		 5184/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5185 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5186 this encoding is undefined. */
5187
5188static bfd_boolean
5189is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
5190 enum mve_undefined *undefined_code)
5191{
5192 *undefined_code = UNDEF_NONE;
5193
9743db03
AV		 5194 switch (matched_insn)
5195 {
5196 case MVE_VDUP:
5197 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
5198 {
5199 *undefined_code = UNDEF_SIZE_3;
5200 return TRUE;
5201 }
5202 else
5203 return FALSE;
5204
d3b63143
AV		 5205 case MVE_VQDMULH_T1:
5206 case MVE_VQRDMULH_T2:
9743db03
AV		 5207 case MVE_VRHADD:
5208 case MVE_VHADD_T1:
5209 case MVE_VHSUB_T1:
5210 if (arm_decode_field (given, 20, 21) == 3)
5211 {
5212 *undefined_code = UNDEF_SIZE_3;
5213 return TRUE;
5214 }
5215 else
5216 return FALSE;
5217
aef6d006
AV		 5218 case MVE_VLDRB_T1:
5219 if (arm_decode_field (given, 7, 8) == 3)
5220 {
5221 *undefined_code = UNDEF_SIZE_3;
5222 return TRUE;
5223 }
5224 else
5225 return FALSE;
5226
5227 case MVE_VLDRH_T2:
5228 if (arm_decode_field (given, 7, 8) <= 1)
5229 {
5230 *undefined_code = UNDEF_SIZE_LE_1;
5231 return TRUE;
5232 }
5233 else
5234 return FALSE;
5235
5236 case MVE_VSTRB_T1:
5237 if ((arm_decode_field (given, 7, 8) == 0))
5238 {
5239 *undefined_code = UNDEF_SIZE_0;
5240 return TRUE;
5241 }
5242 else
5243 return FALSE;
5244
5245 case MVE_VSTRH_T2:
5246 if ((arm_decode_field (given, 7, 8) <= 1))
5247 {
5248 *undefined_code = UNDEF_SIZE_LE_1;
5249 return TRUE;
5250 }
5251 else
5252 return FALSE;
5253
ef1576a1
AV		 5254 case MVE_VLDRB_GATHER_T1:
5255 if (arm_decode_field (given, 7, 8) == 3)
5256 {
5257 *undefined_code = UNDEF_SIZE_3;
5258 return TRUE;
5259 }
5260 else if ((arm_decode_field (given, 28, 28) == 0)
5261 && (arm_decode_field (given, 7, 8) == 0))
5262 {
5263 *undefined_code = UNDEF_NOT_UNS_SIZE_0;
5264 return TRUE;
5265 }
5266 else
5267 return FALSE;
5268
5269 case MVE_VLDRH_GATHER_T2:
5270 if (arm_decode_field (given, 7, 8) == 3)
5271 {
5272 *undefined_code = UNDEF_SIZE_3;
5273 return TRUE;
5274 }
5275 else if ((arm_decode_field (given, 28, 28) == 0)
5276 && (arm_decode_field (given, 7, 8) == 1))
5277 {
5278 *undefined_code = UNDEF_NOT_UNS_SIZE_1;
5279 return TRUE;
5280 }
5281 else if (arm_decode_field (given, 7, 8) == 0)
5282 {
5283 *undefined_code = UNDEF_SIZE_0;
5284 return TRUE;
5285 }
5286 else
5287 return FALSE;
5288
5289 case MVE_VLDRW_GATHER_T3:
5290 if (arm_decode_field (given, 7, 8) != 2)
5291 {
5292 *undefined_code = UNDEF_SIZE_NOT_2;
5293 return TRUE;
5294 }
5295 else if (arm_decode_field (given, 28, 28) == 0)
5296 {
5297 *undefined_code = UNDEF_NOT_UNSIGNED;
5298 return TRUE;
5299 }
5300 else
5301 return FALSE;
5302
5303 case MVE_VLDRD_GATHER_T4:
5304 if (arm_decode_field (given, 7, 8) != 3)
5305 {
5306 *undefined_code = UNDEF_SIZE_NOT_3;
5307 return TRUE;
5308 }
5309 else if (arm_decode_field (given, 28, 28) == 0)
5310 {
5311 *undefined_code = UNDEF_NOT_UNSIGNED;
5312 return TRUE;
5313 }
5314 else
5315 return FALSE;
5316
5317 case MVE_VSTRB_SCATTER_T1:
5318 if (arm_decode_field (given, 7, 8) == 3)
5319 {
5320 *undefined_code = UNDEF_SIZE_3;
5321 return TRUE;
5322 }
5323 else
5324 return FALSE;
5325
5326 case MVE_VSTRH_SCATTER_T2:
5327 {
5328 unsigned long size = arm_decode_field (given, 7, 8);
5329 if (size == 3)
5330 {
5331 *undefined_code = UNDEF_SIZE_3;
5332 return TRUE;
5333 }
5334 else if (size == 0)
5335 {
5336 *undefined_code = UNDEF_SIZE_0;
5337 return TRUE;
5338 }
5339 else
5340 return FALSE;
5341 }
5342
5343 case MVE_VSTRW_SCATTER_T3:
5344 if (arm_decode_field (given, 7, 8) != 2)
5345 {
5346 *undefined_code = UNDEF_SIZE_NOT_2;
5347 return TRUE;
5348 }
5349 else
5350 return FALSE;
5351
5352 case MVE_VSTRD_SCATTER_T4:
5353 if (arm_decode_field (given, 7, 8) != 3)
5354 {
5355 *undefined_code = UNDEF_SIZE_NOT_3;
5356 return TRUE;
5357 }
5358 else
5359 return FALSE;
5360
bf0b396d
AV		 5361 case MVE_VCVT_FP_FIX_VEC:
5362 {
5363 unsigned long imm6 = arm_decode_field (given, 16, 21);
5364 if ((imm6 & 0x20) == 0)
5365 {
5366 *undefined_code = UNDEF_VCVT_IMM6;
5367 return TRUE;
5368 }
5369
5370 if ((arm_decode_field (given, 9, 9) == 0)
5371 && ((imm6 & 0x30) == 0x20))
5372 {
5373 *undefined_code = UNDEF_VCVT_FSI_IMM6;
5374 return TRUE;
5375 }
5376
5377 return FALSE;
5378 }
5379
5380 case MVE_VCVT_BETWEEN_FP_INT:
5381 case MVE_VCVT_FROM_FP_TO_INT:
5382 {
5383 unsigned long size = arm_decode_field (given, 18, 19);
5384 if (size == 0)
5385 {
5386 *undefined_code = UNDEF_SIZE_0;
5387 return TRUE;
5388 }
5389 else if (size == 3)
5390 {
5391 *undefined_code = UNDEF_SIZE_3;
5392 return TRUE;
5393 }
5394 else
5395 return FALSE;
5396 }
5397
c507f10b
AV		 5398 case MVE_VMOV_VEC_LANE_TO_GP:
5399 {
5400 unsigned long op1 = arm_decode_field (given, 21, 22);
5401 unsigned long op2 = arm_decode_field (given, 5, 6);
5402 unsigned long u = arm_decode_field (given, 23, 23);
5403
5404 if ((op2 == 0) && (u == 1))
5405 {
5406 if ((op1 == 0) || (op1 == 1))
5407 {
5408 *undefined_code = UNDEF_BAD_U_OP1_OP2;
5409 return TRUE;
5410 }
5411 else
5412 return FALSE;
5413 }
5414 else if (op2 == 2)
5415 {
5416 if ((op1 == 0) || (op1 == 1))
5417 {
5418 *undefined_code = UNDEF_BAD_OP1_OP2;
5419 return TRUE;
5420 }
5421 else
5422 return FALSE;
5423 }
5424
5425 return FALSE;
5426 }
5427
5428 case MVE_VMOV_GP_TO_VEC_LANE:
5429 if (arm_decode_field (given, 5, 6) == 2)
5430 {
5431 unsigned long op1 = arm_decode_field (given, 21, 22);
5432 if ((op1 == 0) || (op1 == 1))
5433 {
5434 *undefined_code = UNDEF_BAD_OP1_OP2;
5435 return TRUE;
5436 }
5437 else
5438 return FALSE;
5439 }
5440 else
5441 return FALSE;
5442
5443 case MVE_VMOV_IMM_TO_VEC:
5444 if (arm_decode_field (given, 5, 5) == 0)
5445 {
5446 unsigned long cmode = arm_decode_field (given, 8, 11);
5447
5448 if (((cmode & 9) == 1) || ((cmode & 5) == 1))
5449 {
5450 *undefined_code = UNDEF_OP_0_BAD_CMODE;
5451 return TRUE;
5452 }
5453 else
5454 return FALSE;
5455 }
5456 else
5457 return FALSE;
5458
ed63aa17 5459 case MVE_VSHLL_T2:
14925797
AV		 5460 case MVE_VMOVN:
5461 if (arm_decode_field (given, 18, 19) == 2)
5462 {
5463 *undefined_code = UNDEF_SIZE_2;
5464 return TRUE;
5465 }
5466 else
5467 return FALSE;
5468
d3b63143
AV		 5469 case MVE_VRMLALDAVH:
5470 case MVE_VMLADAV_T1:
5471 case MVE_VMLADAV_T2:
5472 case MVE_VMLALDAV:
5473 if ((arm_decode_field (given, 28, 28) == 1)
5474 && (arm_decode_field (given, 12, 12) == 1))
5475 {
5476 *undefined_code = UNDEF_XCHG_UNS;
5477 return TRUE;
5478 }
5479 else
5480 return FALSE;
5481
ed63aa17
AV		 5482 case MVE_VQSHRN:
5483 case MVE_VQSHRUN:
5484 case MVE_VSHLL_T1:
5485 case MVE_VSHRN:
5486 {
5487 unsigned long sz = arm_decode_field (given, 19, 20);
5488 if (sz == 1)
5489 return FALSE;
5490 else if ((sz & 2) == 2)
5491 return FALSE;
5492 else
5493 {
5494 *undefined_code = UNDEF_SIZE;
5495 return TRUE;
5496 }
5497 }
5498 break;
5499
5500 case MVE_VQSHL_T2:
5501 case MVE_VQSHLU_T3:
5502 case MVE_VRSHR:
5503 case MVE_VSHL_T1:
5504 case MVE_VSHR:
5505 case MVE_VSLI:
5506 case MVE_VSRI:
5507 {
5508 unsigned long sz = arm_decode_field (given, 19, 21);
5509 if ((sz & 7) == 1)
5510 return FALSE;
5511 else if ((sz & 6) == 2)
5512 return FALSE;
5513 else if ((sz & 4) == 4)
5514 return FALSE;
5515 else
5516 {
5517 *undefined_code = UNDEF_SIZE;
5518 return TRUE;
5519 }
5520 }
5521
5522 case MVE_VQRSHRN:
5523 case MVE_VQRSHRUN:
5524 if (arm_decode_field (given, 19, 20) == 0)
5525 {
5526 *undefined_code = UNDEF_SIZE_0;
5527 return TRUE;
5528 }
5529 else
5530 return FALSE;
5531
9743db03
AV		 5532 default:
5533 return FALSE;
5534 }
73cd51e5
AV		 5535}
5536
5537/* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
5538 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
5539 why this encoding is unpredictable. */
5540
5541static bfd_boolean
5542is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
5543 enum mve_unpredictable *unpredictable_code)
5544{
5545 *unpredictable_code = UNPRED_NONE;
5546
143275ea
AV		 5547 switch (matched_insn)
5548 {
5549 case MVE_VCMP_FP_T2:
5550 case MVE_VPT_FP_T2:
5551 if ((arm_decode_field (given, 12, 12) == 0)
5552 && (arm_decode_field (given, 5, 5) == 1))
5553 {
5554 *unpredictable_code = UNPRED_FCA_0_FCB_1;
5555 return TRUE;
5556 }
5557 else
5558 return FALSE;
73cd51e5 5559
143275ea
AV		 5560 case MVE_VPT_VEC_T4:
5561 case MVE_VPT_VEC_T5:
5562 case MVE_VPT_VEC_T6:
5563 case MVE_VCMP_VEC_T4:
5564 case MVE_VCMP_VEC_T5:
5565 case MVE_VCMP_VEC_T6:
5566 if (arm_decode_field (given, 0, 3) == 0xd)
5567 {
5568 *unpredictable_code = UNPRED_R13;
5569 return TRUE;
5570 }
5571 else
5572 return FALSE;
c1e26897 5573
9743db03
AV		 5574 case MVE_VDUP:
5575 {
5576 unsigned long gpr = arm_decode_field (given, 12, 15);
5577 if (gpr == 0xd)
5578 {
5579 *unpredictable_code = UNPRED_R13;
5580 return TRUE;
5581 }
5582 else if (gpr == 0xf)
5583 {
5584 *unpredictable_code = UNPRED_R15;
5585 return TRUE;
5586 }
5587
5588 return FALSE;
5589 }
5590
ed63aa17
AV		 5591 case MVE_VQRSHL_T2:
5592 case MVE_VQSHL_T1:
5593 case MVE_VRSHL_T2:
5594 case MVE_VSHL_T2:
5595 case MVE_VSHLC:
d3b63143
AV		 5596 case MVE_VQDMLAH:
5597 case MVE_VQRDMLAH:
5598 case MVE_VQDMLASH:
5599 case MVE_VQRDMLASH:
5600 case MVE_VQDMULH_T3:
5601 case MVE_VQRDMULH_T4:
5602 case MVE_VMLAS:
9743db03
AV		 5603 case MVE_VFMA_FP_SCALAR:
5604 case MVE_VFMAS_FP_SCALAR:
5605 case MVE_VHADD_T2:
5606 case MVE_VHSUB_T2:
5607 {
5608 unsigned long gpr = arm_decode_field (given, 0, 3);
5609 if (gpr == 0xd)
5610 {
5611 *unpredictable_code = UNPRED_R13;
5612 return TRUE;
5613 }
5614 else if (gpr == 0xf)
5615 {
5616 *unpredictable_code = UNPRED_R15;
5617 return TRUE;
5618 }
5619
5620 return FALSE;
5621 }
5622
04d54ace
AV		 5623 case MVE_VLD2:
5624 case MVE_VST2:
5625 {
5626 unsigned long rn = arm_decode_field (given, 16, 19);
5627
5628 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
5629 {
5630 *unpredictable_code = UNPRED_R13_AND_WB;
5631 return TRUE;
5632 }
5633
5634 if (rn == 0xf)
5635 {
5636 *unpredictable_code = UNPRED_R15;
5637 return TRUE;
5638 }
5639
5640 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
5641 {
5642 *unpredictable_code = UNPRED_Q_GT_6;
5643 return TRUE;
5644 }
5645 else
5646 return FALSE;
5647 }
5648
5649 case MVE_VLD4:
5650 case MVE_VST4:
5651 {
5652 unsigned long rn = arm_decode_field (given, 16, 19);
5653
5654 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
5655 {
5656 *unpredictable_code = UNPRED_R13_AND_WB;
5657 return TRUE;
5658 }
5659
5660 if (rn == 0xf)
5661 {
5662 *unpredictable_code = UNPRED_R15;
5663 return TRUE;
5664 }
5665
5666 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
5667 {
5668 *unpredictable_code = UNPRED_Q_GT_4;
5669 return TRUE;
5670 }
5671 else
5672 return FALSE;
5673 }
5674
aef6d006
AV		 5675 case MVE_VLDRB_T5:
5676 case MVE_VLDRH_T6:
5677 case MVE_VLDRW_T7:
5678 case MVE_VSTRB_T5:
5679 case MVE_VSTRH_T6:
5680 case MVE_VSTRW_T7:
5681 {
5682 unsigned long rn = arm_decode_field (given, 16, 19);
5683
5684 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
5685 {
5686 *unpredictable_code = UNPRED_R13_AND_WB;
5687 return TRUE;
5688 }
5689 else if (rn == 0xf)
5690 {
5691 *unpredictable_code = UNPRED_R15;
5692 return TRUE;
5693 }
5694 else
5695 return FALSE;
5696 }
5697
ef1576a1
AV		 5698 case MVE_VLDRB_GATHER_T1:
5699 if (arm_decode_field (given, 0, 0) == 1)
5700 {
5701 *unpredictable_code = UNPRED_OS;
5702 return TRUE;
5703 }
5704
5705 /* fall through. */
5706 /* To handle common code with T2-T4 variants. */
5707 case MVE_VLDRH_GATHER_T2:
5708 case MVE_VLDRW_GATHER_T3:
5709 case MVE_VLDRD_GATHER_T4:
5710 {
5711 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5712 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
5713
5714 if (qd == qm)
5715 {
5716 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
5717 return TRUE;
5718 }
5719
5720 if (arm_decode_field (given, 16, 19) == 0xf)
5721 {
5722 *unpredictable_code = UNPRED_R15;
5723 return TRUE;
5724 }
5725
5726 return FALSE;
5727 }
5728
5729 case MVE_VLDRW_GATHER_T5:
5730 case MVE_VLDRD_GATHER_T6:
5731 {
5732 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5733 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
5734
5735 if (qd == qm)
5736 {
5737 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
5738 return TRUE;
5739 }
5740 else
5741 return FALSE;
5742 }
5743
5744 case MVE_VSTRB_SCATTER_T1:
5745 if (arm_decode_field (given, 16, 19) == 0xf)
5746 {
5747 *unpredictable_code = UNPRED_R15;
5748 return TRUE;
5749 }
5750 else if (arm_decode_field (given, 0, 0) == 1)
5751 {
5752 *unpredictable_code = UNPRED_OS;
5753 return TRUE;
5754 }
5755 else
5756 return FALSE;
5757
5758 case MVE_VSTRH_SCATTER_T2:
5759 case MVE_VSTRW_SCATTER_T3:
5760 case MVE_VSTRD_SCATTER_T4:
5761 if (arm_decode_field (given, 16, 19) == 0xf)
5762 {
5763 *unpredictable_code = UNPRED_R15;
5764 return TRUE;
5765 }
5766 else
5767 return FALSE;
5768
c507f10b
AV		 5769 case MVE_VMOV2_VEC_LANE_TO_GP:
5770 case MVE_VMOV2_GP_TO_VEC_LANE:
bf0b396d
AV		 5771 case MVE_VCVT_BETWEEN_FP_INT:
5772 case MVE_VCVT_FROM_FP_TO_INT:
5773 {
5774 unsigned long rt = arm_decode_field (given, 0, 3);
5775 unsigned long rt2 = arm_decode_field (given, 16, 19);
5776
5777 if ((rt == 0xd) || (rt2 == 0xd))
5778 {
5779 *unpredictable_code = UNPRED_R13;
5780 return TRUE;
5781 }
5782 else if ((rt == 0xf) || (rt2 == 0xf))
5783 {
5784 *unpredictable_code = UNPRED_R15;
5785 return TRUE;
5786 }
5787 else if (rt == rt2)
5788 {
5789 *unpredictable_code = UNPRED_GP_REGS_EQUAL;
5790 return TRUE;
5791 }
5792
5793 return FALSE;
5794 }
5795
c507f10b
AV		 5796 case MVE_VMOV_HFP_TO_GP:
5797 case MVE_VMOV_GP_TO_VEC_LANE:
5798 case MVE_VMOV_VEC_LANE_TO_GP:
5799 {
5800 unsigned long rda = arm_decode_field (given, 12, 15);
5801 if (rda == 0xd)
5802 {
5803 *unpredictable_code = UNPRED_R13;
5804 return TRUE;
5805 }
5806 else if (rda == 0xf)
5807 {
5808 *unpredictable_code = UNPRED_R15;
5809 return TRUE;
5810 }
5811
5812 return FALSE;
5813 }
5814
d3b63143
AV		 5815 case MVE_VQRDMLADH:
5816 case MVE_VQDMLSDH:
5817 case MVE_VQRDMLSDH:
5818 case MVE_VQDMLADH:
14925797
AV		 5819 case MVE_VMULL_INT:
5820 {
5821 unsigned long Qd;
5822 unsigned long Qm;
5823 unsigned long Qn;
5824
5825 if (arm_decode_field (given, 20, 21) == 2)
5826 {
5827 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5828 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
5829 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
5830
5831 if ((Qd == Qn) || (Qd == Qm))
5832 {
5833 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
5834 return TRUE;
5835 }
5836 else
5837 return FALSE;
5838 }
5839 else
5840 return FALSE;
5841 }
5842
897b9bbc 5843 case MVE_VCMUL_FP:
14925797
AV		 5844 case MVE_VQDMULL_T1:
5845 {
5846 unsigned long Qd;
5847 unsigned long Qm;
5848 unsigned long Qn;
5849
5850 if (arm_decode_field (given, 28, 28) == 1)
5851 {
5852 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5853 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
5854 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
5855
5856 if ((Qd == Qn) || (Qd == Qm))
5857 {
5858 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
5859 return TRUE;
5860 }
5861 else
5862 return FALSE;
5863 }
5864 else
5865 return FALSE;
5866 }
5867
5868 case MVE_VQDMULL_T2:
5869 {
5870 unsigned long gpr = arm_decode_field (given, 0, 3);
5871 if (gpr == 0xd)
5872 {
5873 *unpredictable_code = UNPRED_R13;
5874 return TRUE;
5875 }
5876 else if (gpr == 0xf)
5877 {
5878 *unpredictable_code = UNPRED_R15;
5879 return TRUE;
5880 }
5881
5882 if (arm_decode_field (given, 28, 28) == 1)
5883 {
5884 unsigned long Qd
5885 = arm_decode_field_multiple (given, 13, 15, 22, 22);
5886 unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
5887
5888 if ((Qd == Qn))
5889 {
5890 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
5891 return TRUE;
5892 }
5893 else
5894 return FALSE;
5895 }
5896
5897 return FALSE;
5898 }
5899
d3b63143
AV		 5900 case MVE_VMLSLDAV:
5901 case MVE_VRMLSLDAVH:
5902 case MVE_VMLALDAV:
5903 case MVE_VADDLV:
5904 if (arm_decode_field (given, 20, 22) == 6)
5905 {
5906 *unpredictable_code = UNPRED_R13;
5907 return TRUE;
5908 }
5909 else
5910 return FALSE;
5911
1c8f2df8
AV		 5912 case MVE_VDWDUP:
5913 case MVE_VIWDUP:
5914 if (arm_decode_field (given, 1, 3) == 6)
5915 {
5916 *unpredictable_code = UNPRED_R13;
5917 return TRUE;
5918 }
5919 else
5920 return FALSE;
5921
897b9bbc
AV		 5922 case MVE_VCADD_VEC:
5923 case MVE_VHCADD:
5924 {
5925 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5926 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
5927 if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
5928 {
5929 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
5930 return TRUE;
5931 }
5932 else
5933 return FALSE;
5934 }
5935
5936 case MVE_VCADD_FP:
5937 {
5938 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5939 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
5940 if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
5941 {
5942 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
5943 return TRUE;
5944 }
5945 else
5946 return FALSE;
5947 }
5948
5949 case MVE_VCMLA_FP:
5950 {
5951 unsigned long Qda;
5952 unsigned long Qm;
5953 unsigned long Qn;
5954
5955 if (arm_decode_field (given, 20, 20) == 1)
5956 {
5957 Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
5958 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
5959 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
5960
5961 if ((Qda == Qn) || (Qda == Qm))
5962 {
5963 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
5964 return TRUE;
5965 }
5966 else
5967 return FALSE;
5968 }
5969 else
5970 return FALSE;
5971
5972 }
5973
143275ea
AV		 5974 default:
5975 return FALSE;
5976 }
5977}
c1e26897 5978
c507f10b
AV		 5979static void
5980print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
5981{
5982 unsigned long op1 = arm_decode_field (given, 21, 22);
5983 unsigned long op2 = arm_decode_field (given, 5, 6);
5984 unsigned long h = arm_decode_field (given, 16, 16);
5985 unsigned long index, esize, targetBeat, idx;
5986 void *stream = info->stream;
5987 fprintf_ftype func = info->fprintf_func;
5988
5989 if ((op1 & 0x2) == 0x2)
5990 {
5991 index = op2;
5992 esize = 8;
5993 }
5994 else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
5995 {
5996 index = op2 >> 1;
5997 esize = 16;
5998 }
5999 else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
6000 {
6001 index = 0;
6002 esize = 32;
6003 }
6004 else
6005 {
6006 func (stream, "<undefined index>");
6007 return;
6008 }
6009
6010 targetBeat = (op1 & 0x1) | (h << 1);
6011 idx = index + targetBeat * (32/esize);
6012
6013 func (stream, "%lu", idx);
6014}
6015
6016/* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6017 in length and integer of floating-point type. */
6018static void
6019print_simd_imm8 (struct disassemble_info *info, unsigned long given,
6020 unsigned int ibit_loc, const struct mopcode32 *insn)
6021{
6022 int bits = 0;
6023 int cmode = (given >> 8) & 0xf;
6024 int op = (given >> 5) & 0x1;
6025 unsigned long value = 0, hival = 0;
6026 unsigned shift;
6027 int size = 0;
6028 int isfloat = 0;
6029 void *stream = info->stream;
6030 fprintf_ftype func = info->fprintf_func;
6031
6032 /* On Neon the 'i' bit is at bit 24, on mve it is
6033 at bit 28. */
6034 bits |= ((given >> ibit_loc) & 1) << 7;
6035 bits |= ((given >> 16) & 7) << 4;
6036 bits |= ((given >> 0) & 15) << 0;
6037
6038 if (cmode < 8)
6039 {
6040 shift = (cmode >> 1) & 3;
6041 value = (unsigned long) bits << (8 * shift);
6042 size = 32;
6043 }
6044 else if (cmode < 12)
6045 {
6046 shift = (cmode >> 1) & 1;
6047 value = (unsigned long) bits << (8 * shift);
6048 size = 16;
6049 }
6050 else if (cmode < 14)
6051 {
6052 shift = (cmode & 1) + 1;
6053 value = (unsigned long) bits << (8 * shift);
6054 value |= (1ul << (8 * shift)) - 1;
6055 size = 32;
6056 }
6057 else if (cmode == 14)
6058 {
6059 if (op)
6060 {
6061 /* Bit replication into bytes. */
6062 int ix;
6063 unsigned long mask;
6064
6065 value = 0;
6066 hival = 0;
6067 for (ix = 7; ix >= 0; ix--)
6068 {
6069 mask = ((bits >> ix) & 1) ? 0xff : 0;
6070 if (ix <= 3)
6071 value = (value << 8) | mask;
6072 else
6073 hival = (hival << 8) | mask;
6074 }
6075 size = 64;
6076 }
6077 else
6078 {
6079 /* Byte replication. */
6080 value = (unsigned long) bits;
6081 size = 8;
6082 }
6083 }
6084 else if (!op)
6085 {
6086 /* Floating point encoding. */
6087 int tmp;
6088
6089 value = (unsigned long) (bits & 0x7f) << 19;
6090 value |= (unsigned long) (bits & 0x80) << 24;
6091 tmp = bits & 0x40 ? 0x3c : 0x40;
6092 value |= (unsigned long) tmp << 24;
6093 size = 32;
6094 isfloat = 1;
6095 }
6096 else
6097 {
6098 func (stream, "<illegal constant %.8x:%x:%x>",
6099 bits, cmode, op);
6100 size = 32;
6101 return;
6102 }
6103
6104 // printU determines whether the immediate value should be printed as
6105 // unsigned.
6106 unsigned printU = 0;
6107 switch (insn->mve_op)
6108 {
6109 default:
6110 break;
6111 // We want this for instructions that don't have a 'signed' type
6112 case MVE_VBIC_IMM:
6113 case MVE_VORR_IMM:
6114 case MVE_VMVN_IMM:
6115 case MVE_VMOV_IMM_TO_VEC:
6116 printU = 1;
6117 break;
6118 }
6119 switch (size)
6120 {
6121 case 8:
6122 func (stream, "#%ld\t; 0x%.2lx", value, value);
6123 break;
6124
6125 case 16:
6126 func (stream,
6127 printU
6128 ? "#%lu\t; 0x%.4lx"
6129 : "#%ld\t; 0x%.4lx", value, value);
6130 break;
6131
6132 case 32:
6133 if (isfloat)
6134 {
6135 unsigned char valbytes[4];
6136 double fvalue;
6137
6138 /* Do this a byte at a time so we don't have to
6139 worry about the host's endianness. */
6140 valbytes[0] = value & 0xff;
6141 valbytes[1] = (value >> 8) & 0xff;
6142 valbytes[2] = (value >> 16) & 0xff;
6143 valbytes[3] = (value >> 24) & 0xff;
6144
6145 floatformat_to_double
6146 (& floatformat_ieee_single_little, valbytes,
6147 & fvalue);
6148
6149 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
6150 value);
6151 }
6152 else
6153 func (stream,
6154 printU
6155 ? "#%lu\t; 0x%.8lx"
6156 : "#%ld\t; 0x%.8lx",
6157 (long) (((value & 0x80000000L) != 0)
6158 && !printU
6159 ? value | ~0xffffffffL : value),
6160 value);
6161 break;
6162
6163 case 64:
6164 func (stream, "#0x%.8lx%.8lx", hival, value);
6165 break;
6166
6167 default:
6168 abort ();
6169 }
6170
6171}
6172
73cd51e5
AV		 6173static void
6174print_mve_undefined (struct disassemble_info *info,
6175 enum mve_undefined undefined_code)
6176{
6177 void *stream = info->stream;
6178 fprintf_ftype func = info->fprintf_func;
6179
6180 func (stream, "\t\tundefined instruction: ");
6181
6182 switch (undefined_code)
6183 {
ed63aa17
AV		 6184 case UNDEF_SIZE:
6185 func (stream, "illegal size");
6186 break;
6187
aef6d006
AV		 6188 case UNDEF_SIZE_0:
6189 func (stream, "size equals zero");
6190 break;
6191
c507f10b
AV		 6192 case UNDEF_SIZE_2:
6193 func (stream, "size equals two");
6194 break;
6195
9743db03
AV		 6196 case UNDEF_SIZE_3:
6197 func (stream, "size equals three");
6198 break;
6199
aef6d006
AV		 6200 case UNDEF_SIZE_LE_1:
6201 func (stream, "size <= 1");
6202 break;
6203
ef1576a1
AV		 6204 case UNDEF_SIZE_NOT_2:
6205 func (stream, "size not equal to 2");
6206 break;
6207
6208 case UNDEF_SIZE_NOT_3:
6209 func (stream, "size not equal to 3");
6210 break;
6211
6212 case UNDEF_NOT_UNS_SIZE_0:
6213 func (stream, "not unsigned and size = zero");
6214 break;
6215
6216 case UNDEF_NOT_UNS_SIZE_1:
6217 func (stream, "not unsigned and size = one");
6218 break;
6219
6220 case UNDEF_NOT_UNSIGNED:
6221 func (stream, "not unsigned");
6222 break;
6223
bf0b396d
AV		 6224 case UNDEF_VCVT_IMM6:
6225 func (stream, "invalid imm6");
6226 break;
6227
6228 case UNDEF_VCVT_FSI_IMM6:
6229 func (stream, "fsi = 0 and invalid imm6");
6230 break;
6231
c507f10b
AV		 6232 case UNDEF_BAD_OP1_OP2:
6233 func (stream, "bad size with op2 = 2 and op1 = 0 or 1");
6234 break;
6235
6236 case UNDEF_BAD_U_OP1_OP2:
6237 func (stream, "unsigned with op2 = 0 and op1 = 0 or 1");
6238 break;
6239
6240 case UNDEF_OP_0_BAD_CMODE:
6241 func (stream, "op field equal 0 and bad cmode");
6242 break;
6243
d3b63143
AV		 6244 case UNDEF_XCHG_UNS:
6245 func (stream, "exchange and unsigned together");
6246 break;
6247
73cd51e5
AV		 6248 case UNDEF_NONE:
6249 break;
6250 }
6251
6252}
6253
6254static void
6255print_mve_unpredictable (struct disassemble_info *info,
6256 enum mve_unpredictable unpredict_code)
6257{
6258 void *stream = info->stream;
6259 fprintf_ftype func = info->fprintf_func;
6260
6261 func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
6262
6263 switch (unpredict_code)
6264 {
6265 case UNPRED_IT_BLOCK:
6266 func (stream, "mve instruction in it block");
6267 break;
6268
143275ea
AV		 6269 case UNPRED_FCA_0_FCB_1:
6270 func (stream, "condition bits, fca = 0 and fcb = 1");
6271 break;
6272
6273 case UNPRED_R13:
6274 func (stream, "use of r13 (sp)");
6275 break;
6276
9743db03
AV		 6277 case UNPRED_R15:
6278 func (stream, "use of r15 (pc)");
6279 break;
6280
04d54ace
AV		 6281 case UNPRED_Q_GT_4:
6282 func (stream, "start register block > r4");
6283 break;
6284
6285 case UNPRED_Q_GT_6:
6286 func (stream, "start register block > r6");
6287 break;
6288
6289 case UNPRED_R13_AND_WB:
6290 func (stream, "use of r13 and write back");
6291 break;
6292
ef1576a1
AV		 6293 case UNPRED_Q_REGS_EQUAL:
6294 func (stream,
6295 "same vector register used for destination and other operand");
6296 break;
6297
6298 case UNPRED_OS:
6299 func (stream, "use of offset scaled");
6300 break;
6301
bf0b396d
AV		 6302 case UNPRED_GP_REGS_EQUAL:
6303 func (stream, "same general-purpose register used for both operands");
6304 break;
6305
c507f10b
AV		 6306 case UNPRED_Q_REGS_EQ_AND_SIZE_1:
6307 func (stream, "use of identical q registers and size = 1");
6308 break;
6309
6310 case UNPRED_Q_REGS_EQ_AND_SIZE_2:
6311 func (stream, "use of identical q registers and size = 1");
6312 break;
6313
73cd51e5
AV		 6314 case UNPRED_NONE:
6315 break;
6316 }
6317}
6318
04d54ace
AV		 6319/* Print register block operand for mve vld2/vld4/vst2/vld4. */
6320
6321static void
6322print_mve_register_blocks (struct disassemble_info *info,
6323 unsigned long given,
6324 enum mve_instructions matched_insn)
6325{
6326 void *stream = info->stream;
6327 fprintf_ftype func = info->fprintf_func;
6328
6329 unsigned long q_reg_start = arm_decode_field_multiple (given,
6330 13, 15,
6331 22, 22);
6332 switch (matched_insn)
6333 {
6334 case MVE_VLD2:
6335 case MVE_VST2:
6336 if (q_reg_start <= 6)
6337 func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
6338 else
6339 func (stream, "<illegal reg q%ld>", q_reg_start);
6340 break;
6341
6342 case MVE_VLD4:
6343 case MVE_VST4:
6344 if (q_reg_start <= 4)
6345 func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
6346 q_reg_start + 1, q_reg_start + 2,
6347 q_reg_start + 3);
6348 else
6349 func (stream, "<illegal reg q%ld>", q_reg_start);
6350 break;
6351
6352 default:
6353 break;
6354 }
6355}
6356
bf0b396d
AV		 6357static void
6358print_mve_rounding_mode (struct disassemble_info *info,
6359 unsigned long given,
6360 enum mve_instructions matched_insn)
6361{
6362 void *stream = info->stream;
6363 fprintf_ftype func = info->fprintf_func;
6364
6365 switch (matched_insn)
6366 {
6367 case MVE_VCVT_FROM_FP_TO_INT:
6368 {
6369 switch (arm_decode_field (given, 8, 9))
6370 {
6371 case 0:
6372 func (stream, "a");
6373 break;
6374
6375 case 1:
6376 func (stream, "n");
6377 break;
6378
6379 case 2:
6380 func (stream, "p");
6381 break;
6382
6383 case 3:
6384 func (stream, "m");
6385 break;
6386
6387 default:
6388 break;
6389 }
6390 }
6391 break;
6392
6393 case MVE_VRINT_FP:
6394 {
6395 switch (arm_decode_field (given, 7, 9))
6396 {
6397 case 0:
6398 func (stream, "n");
6399 break;
6400
6401 case 1:
6402 func (stream, "x");
6403 break;
6404
6405 case 2:
6406 func (stream, "a");
6407 break;
6408
6409 case 3:
6410 func (stream, "z");
6411 break;
6412
6413 case 5:
6414 func (stream, "m");
6415 break;
6416
6417 case 7:
6418 func (stream, "p");
6419
6420 case 4:
6421 case 6:
6422 default:
6423 break;
6424 }
6425 }
6426 break;
6427
6428 default:
6429 break;
6430 }
6431}
6432
6433static void
6434print_mve_vcvt_size (struct disassemble_info *info,
6435 unsigned long given,
6436 enum mve_instructions matched_insn)
6437{
6438 unsigned long mode = 0;
6439 void *stream = info->stream;
6440 fprintf_ftype func = info->fprintf_func;
6441
6442 switch (matched_insn)
6443 {
6444 case MVE_VCVT_FP_FIX_VEC:
6445 {
6446 mode = (((given & 0x200) >> 7)
6447 | ((given & 0x10000000) >> 27)
6448 | ((given & 0x100) >> 8));
6449
6450 switch (mode)
6451 {
6452 case 0:
6453 func (stream, "f16.s16");
6454 break;
6455
6456 case 1:
6457 func (stream, "s16.f16");
6458 break;
6459
6460 case 2:
6461 func (stream, "f16.u16");
6462 break;
6463
6464 case 3:
6465 func (stream, "u16.f16");
6466 break;
6467
6468 case 4:
6469 func (stream, "f32.s32");
6470 break;
6471
6472 case 5:
6473 func (stream, "s32.f32");
6474 break;
6475
6476 case 6:
6477 func (stream, "f32.u32");
6478 break;
6479
6480 case 7:
6481 func (stream, "u32.f32");
6482 break;
6483
6484 default:
6485 break;
6486 }
6487 break;
6488 }
6489 case MVE_VCVT_BETWEEN_FP_INT:
6490 {
6491 unsigned long size = arm_decode_field (given, 18, 19);
6492 unsigned long op = arm_decode_field (given, 7, 8);
6493
6494 if (size == 1)
6495 {
6496 switch (op)
6497 {
6498 case 0:
6499 func (stream, "f16.s16");
6500 break;
6501
6502 case 1:
6503 func (stream, "f16.u16");
6504 break;
6505
6506 case 2:
6507 func (stream, "s16.f16");
6508 break;
6509
6510 case 3:
6511 func (stream, "u16.f16");
6512 break;
6513
6514 default:
6515 break;
6516 }
6517 }
6518 else if (size == 2)
6519 {
6520 switch (op)
6521 {
6522 case 0:
6523 func (stream, "f32.s32");
6524 break;
6525
6526 case 1:
6527 func (stream, "f32.u32");
6528 break;
6529
6530 case 2:
6531 func (stream, "s32.f32");
6532 break;
6533
6534 case 3:
6535 func (stream, "u32.f32");
6536 break;
6537 }
6538 }
6539 }
6540 break;
6541
6542 case MVE_VCVT_FP_HALF_FP:
6543 {
6544 unsigned long op = arm_decode_field (given, 28, 28);
6545 if (op == 0)
6546 func (stream, "f16.f32");
6547 else if (op == 1)
6548 func (stream, "f32.f16");
6549 }
6550 break;
6551
6552 case MVE_VCVT_FROM_FP_TO_INT:
6553 {
6554 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
6555
6556 switch (size)
6557 {
6558 case 2:
6559 func (stream, "s16.f16");
6560 break;
6561
6562 case 3:
6563 func (stream, "u16.f16");
6564 break;
6565
6566 case 4:
6567 func (stream, "s32.f32");
6568 break;
6569
6570 case 5:
6571 func (stream, "u32.f32");
6572 break;
6573
6574 default:
6575 break;
6576 }
6577 }
6578 break;
6579
6580 default:
6581 break;
6582 }
6583}
6584
897b9bbc
AV		 6585static void
6586print_mve_rotate (struct disassemble_info *info, unsigned long rot,
6587 unsigned long rot_width)
6588{
6589 void *stream = info->stream;
6590 fprintf_ftype func = info->fprintf_func;
6591
6592 if (rot_width == 1)
6593 {
6594 switch (rot)
6595 {
6596 case 0:
6597 func (stream, "90");
6598 break;
6599 case 1:
6600 func (stream, "270");
6601 break;
6602 default:
6603 break;
6604 }
6605 }
6606 else if (rot_width == 2)
6607 {
6608 switch (rot)
6609 {
6610 case 0:
6611 func (stream, "0");
6612 break;
6613 case 1:
6614 func (stream, "90");
6615 break;
6616 case 2:
6617 func (stream, "180");
6618 break;
6619 case 3:
6620 func (stream, "270");
6621 break;
6622 default:
6623 break;
6624 }
6625 }
6626}
6627
143275ea
AV		 6628static void
6629print_instruction_predicate (struct disassemble_info *info)
6630{
6631 void *stream = info->stream;
6632 fprintf_ftype func = info->fprintf_func;
6633
6634 if (vpt_block_state.next_pred_state == PRED_THEN)
6635 func (stream, "t");
6636 else if (vpt_block_state.next_pred_state == PRED_ELSE)
6637 func (stream, "e");
6638}
6639
6640static void
6641print_mve_size (struct disassemble_info *info,
6642 unsigned long size,
6643 enum mve_instructions matched_insn)
6644{
6645 void *stream = info->stream;
6646 fprintf_ftype func = info->fprintf_func;
6647
6648 switch (matched_insn)
6649 {
d3b63143 6650 case MVE_VADDV:
897b9bbc 6651 case MVE_VCADD_VEC:
143275ea
AV		 6652 case MVE_VCMP_VEC_T1:
6653 case MVE_VCMP_VEC_T2:
6654 case MVE_VCMP_VEC_T3:
6655 case MVE_VCMP_VEC_T4:
6656 case MVE_VCMP_VEC_T5:
6657 case MVE_VCMP_VEC_T6:
1c8f2df8
AV		 6658 case MVE_VDDUP:
6659 case MVE_VDWDUP:
9743db03
AV		 6660 case MVE_VHADD_T1:
6661 case MVE_VHADD_T2:
897b9bbc 6662 case MVE_VHCADD:
9743db03
AV		 6663 case MVE_VHSUB_T1:
6664 case MVE_VHSUB_T2:
1c8f2df8
AV		 6665 case MVE_VIDUP:
6666 case MVE_VIWDUP:
04d54ace
AV		 6667 case MVE_VLD2:
6668 case MVE_VLD4:
ef1576a1
AV		 6669 case MVE_VLDRB_GATHER_T1:
6670 case MVE_VLDRH_GATHER_T2:
6671 case MVE_VLDRW_GATHER_T3:
6672 case MVE_VLDRD_GATHER_T4:
aef6d006
AV		 6673 case MVE_VLDRB_T1:
6674 case MVE_VLDRH_T2:
d3b63143 6675 case MVE_VMLAS:
143275ea
AV		 6676 case MVE_VPT_VEC_T1:
6677 case MVE_VPT_VEC_T2:
6678 case MVE_VPT_VEC_T3:
6679 case MVE_VPT_VEC_T4:
6680 case MVE_VPT_VEC_T5:
6681 case MVE_VPT_VEC_T6:
d3b63143
AV		 6682 case MVE_VQDMLADH:
6683 case MVE_VQRDMLADH:
6684 case MVE_VQDMLAH:
6685 case MVE_VQRDMLAH:
6686 case MVE_VQDMLASH:
6687 case MVE_VQRDMLASH:
6688 case MVE_VQDMLSDH:
6689 case MVE_VQRDMLSDH:
6690 case MVE_VQDMULH_T1:
6691 case MVE_VQRDMULH_T2:
6692 case MVE_VQDMULH_T3:
6693 case MVE_VQRDMULH_T4:
ed63aa17
AV		 6694 case MVE_VQRSHL_T1:
6695 case MVE_VQRSHL_T2:
6696 case MVE_VQSHL_T1:
6697 case MVE_VQSHL_T4:
9743db03 6698 case MVE_VRHADD:
bf0b396d 6699 case MVE_VRINT_FP:
ed63aa17
AV		 6700 case MVE_VRSHL_T1:
6701 case MVE_VRSHL_T2:
6702 case MVE_VSHL_T2:
6703 case MVE_VSHL_T3:
6704 case MVE_VSHLL_T2:
04d54ace
AV		 6705 case MVE_VST2:
6706 case MVE_VST4:
ef1576a1
AV		 6707 case MVE_VSTRB_SCATTER_T1:
6708 case MVE_VSTRH_SCATTER_T2:
6709 case MVE_VSTRW_SCATTER_T3:
aef6d006
AV		 6710 case MVE_VSTRB_T1:
6711 case MVE_VSTRH_T2:
143275ea
AV		 6712 if (size <= 3)
6713 func (stream, "%s", mve_vec_sizename[size]);
6714 else
6715 func (stream, "<undef size>");
6716 break;
6717
6718 case MVE_VCMP_FP_T1:
6719 case MVE_VCMP_FP_T2:
9743db03
AV		 6720 case MVE_VFMA_FP_SCALAR:
6721 case MVE_VFMA_FP:
6722 case MVE_VFMS_FP:
6723 case MVE_VFMAS_FP_SCALAR:
143275ea
AV		 6724 case MVE_VPT_FP_T1:
6725 case MVE_VPT_FP_T2:
6726 if (size == 0)
6727 func (stream, "32");
6728 else if (size == 1)
6729 func (stream, "16");
6730 break;
6731
897b9bbc
AV		 6732 case MVE_VCADD_FP:
6733 case MVE_VCMLA_FP:
6734 case MVE_VCMUL_FP:
d3b63143
AV		 6735 case MVE_VMLADAV_T1:
6736 case MVE_VMLALDAV:
6737 case MVE_VMLSDAV_T1:
6738 case MVE_VMLSLDAV:
14925797
AV		 6739 case MVE_VMOVN:
6740 case MVE_VQDMULL_T1:
6741 case MVE_VQDMULL_T2:
6742 case MVE_VQMOVN:
6743 case MVE_VQMOVUN:
6744 if (size == 0)
6745 func (stream, "16");
6746 else if (size == 1)
6747 func (stream, "32");
6748 break;
6749
6750 case MVE_VMOVL:
6751 if (size == 1)
6752 func (stream, "8");
6753 else if (size == 2)
6754 func (stream, "16");
6755 break;
6756
9743db03
AV		 6757 case MVE_VDUP:
6758 switch (size)
6759 {
6760 case 0:
6761 func (stream, "32");
6762 break;
6763 case 1:
6764 func (stream, "16");
6765 break;
6766 case 2:
6767 func (stream, "8");
6768 break;
6769 default:
6770 break;
6771 }
6772 break;
6773
c507f10b
AV		 6774 case MVE_VMOV_GP_TO_VEC_LANE:
6775 case MVE_VMOV_VEC_LANE_TO_GP:
6776 switch (size)
6777 {
6778 case 0: case 4:
6779 func (stream, "32");
6780 break;
6781
6782 case 1: case 3:
6783 case 5: case 7:
6784 func (stream, "16");
6785 break;
6786
6787 case 8: case 9: case 10: case 11:
6788 case 12: case 13: case 14: case 15:
6789 func (stream, "8");
6790 break;
6791
6792 default:
6793 break;
6794 }
6795 break;
6796
6797 case MVE_VMOV_IMM_TO_VEC:
6798 switch (size)
6799 {
6800 case 0: case 4: case 8:
6801 case 12: case 24: case 26:
6802 func (stream, "i32");
6803 break;
6804 case 16: case 20:
6805 func (stream, "i16");
6806 break;
6807 case 28:
6808 func (stream, "i8");
6809 break;
6810 case 29:
6811 func (stream, "i64");
6812 break;
6813 case 30:
6814 func (stream, "f32");
6815 break;
6816 default:
6817 break;
6818 }
6819 break;
6820
14925797
AV		 6821 case MVE_VMULL_POLY:
6822 if (size == 0)
6823 func (stream, "p8");
6824 else if (size == 1)
6825 func (stream, "p16");
6826 break;
6827
c507f10b
AV		 6828 case MVE_VMVN_IMM:
6829 switch (size)
6830 {
6831 case 0: case 2: case 4:
6832 case 6: case 12: case 13:
6833 func (stream, "32");
6834 break;
6835
6836 case 8: case 10:
6837 func (stream, "16");
6838 break;
6839
6840 default:
6841 break;
6842 }
6843 break;
6844
6845 case MVE_VBIC_IMM:
6846 case MVE_VORR_IMM:
6847 switch (size)
6848 {
6849 case 1: case 3:
6850 case 5: case 7:
6851 func (stream, "32");
6852 break;
6853
6854 case 9: case 11:
6855 func (stream, "16");
6856 break;
6857
6858 default:
6859 break;
6860 }
6861 break;
6862
ed63aa17
AV		 6863 case MVE_VQSHRN:
6864 case MVE_VQSHRUN:
6865 case MVE_VQRSHRN:
6866 case MVE_VQRSHRUN:
6867 case MVE_VRSHRN:
6868 case MVE_VSHRN:
6869 {
6870 switch (size)
6871 {
6872 case 1:
6873 func (stream, "16");
6874 break;
6875
6876 case 2: case 3:
6877 func (stream, "32");
6878 break;
6879
6880 default:
6881 break;
6882 }
6883 }
6884 break;
6885
6886 case MVE_VQSHL_T2:
6887 case MVE_VQSHLU_T3:
6888 case MVE_VRSHR:
6889 case MVE_VSHL_T1:
6890 case MVE_VSHLL_T1:
6891 case MVE_VSHR:
6892 case MVE_VSLI:
6893 case MVE_VSRI:
6894 {
6895 switch (size)
6896 {
6897 case 1:
6898 func (stream, "8");
6899 break;
6900
6901 case 2: case 3:
6902 func (stream, "16");
6903 break;
6904
6905 case 4: case 5: case 6: case 7:
6906 func (stream, "32");
6907 break;
6908
6909 default:
6910 break;
6911 }
6912 }
6913 break;
6914
143275ea
AV		 6915 default:
6916 break;
6917 }
6918}
6919
ed63aa17
AV		 6920static void
6921print_mve_shift_n (struct disassemble_info *info, long given,
6922 enum mve_instructions matched_insn)
6923{
6924 void *stream = info->stream;
6925 fprintf_ftype func = info->fprintf_func;
6926
6927 int startAt0
6928 = matched_insn == MVE_VQSHL_T2
6929 || matched_insn == MVE_VQSHLU_T3
6930 || matched_insn == MVE_VSHL_T1
6931 || matched_insn == MVE_VSHLL_T1
6932 || matched_insn == MVE_VSLI;
6933
6934 unsigned imm6 = (given & 0x3f0000) >> 16;
6935
6936 if (matched_insn == MVE_VSHLL_T1)
6937 imm6 &= 0x1f;
6938
6939 unsigned shiftAmount = 0;
6940 if ((imm6 & 0x20) != 0)
6941 shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
6942 else if ((imm6 & 0x10) != 0)
6943 shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
6944 else if ((imm6 & 0x08) != 0)
6945 shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
6946 else
6947 print_mve_undefined (info, UNDEF_SIZE_0);
6948
6949 func (stream, "%u", shiftAmount);
6950}
6951
143275ea
AV		 6952static void
6953print_vec_condition (struct disassemble_info *info, long given,
6954 enum mve_instructions matched_insn)
6955{
6956 void *stream = info->stream;
6957 fprintf_ftype func = info->fprintf_func;
6958 long vec_cond = 0;
6959
6960 switch (matched_insn)
6961 {
6962 case MVE_VPT_FP_T1:
6963 case MVE_VCMP_FP_T1:
6964 vec_cond = (((given & 0x1000) >> 10)
6965 | ((given & 1) << 1)
6966 | ((given & 0x0080) >> 7));
6967 func (stream, "%s",vec_condnames[vec_cond]);
6968 break;
6969
6970 case MVE_VPT_FP_T2:
6971 case MVE_VCMP_FP_T2:
6972 vec_cond = (((given & 0x1000) >> 10)
6973 | ((given & 0x0020) >> 4)
6974 | ((given & 0x0080) >> 7));
6975 func (stream, "%s",vec_condnames[vec_cond]);
6976 break;
6977
6978 case MVE_VPT_VEC_T1:
6979 case MVE_VCMP_VEC_T1:
6980 vec_cond = (given & 0x0080) >> 7;
6981 func (stream, "%s",vec_condnames[vec_cond]);
6982 break;
6983
6984 case MVE_VPT_VEC_T2:
6985 case MVE_VCMP_VEC_T2:
6986 vec_cond = 2 | ((given & 0x0080) >> 7);
6987 func (stream, "%s",vec_condnames[vec_cond]);
6988 break;
6989
6990 case MVE_VPT_VEC_T3:
6991 case MVE_VCMP_VEC_T3:
6992 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
6993 func (stream, "%s",vec_condnames[vec_cond]);
6994 break;
6995
6996 case MVE_VPT_VEC_T4:
6997 case MVE_VCMP_VEC_T4:
6998 vec_cond = (given & 0x0080) >> 7;
6999 func (stream, "%s",vec_condnames[vec_cond]);
7000 break;
7001
7002 case MVE_VPT_VEC_T5:
7003 case MVE_VCMP_VEC_T5:
7004 vec_cond = 2 | ((given & 0x0080) >> 7);
7005 func (stream, "%s",vec_condnames[vec_cond]);
7006 break;
7007
7008 case MVE_VPT_VEC_T6:
7009 case MVE_VCMP_VEC_T6:
7010 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
7011 func (stream, "%s",vec_condnames[vec_cond]);
7012 break;
7013
7014 case MVE_NONE:
7015 case MVE_VPST:
7016 default:
7017 break;
7018 }
7019}
7020
7021#define W_BIT 21
7022#define I_BIT 22
7023#define U_BIT 23
7024#define P_BIT 24
7025
7026#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
7027#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
7028#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
7029#define PRE_BIT_SET (given & (1 << P_BIT))
7030
7031
8f06b2d8
PB		 7032/* Print one coprocessor instruction on INFO->STREAM.
7033 Return TRUE if the instuction matched, FALSE if this is not a
7034 recognised coprocessor instruction. */
7035
7036static bfd_boolean
fe56b6ce
NC		 7037print_insn_coprocessor (bfd_vma pc,
7038 struct disassemble_info *info,
7039 long given,
8f06b2d8
PB		 7040 bfd_boolean thumb)
7041{
6b0dd094 7042 const struct sopcode32 *insn;
8f06b2d8
PB		 7043 void *stream = info->stream;
7044 fprintf_ftype func = info->fprintf_func;
7045 unsigned long mask;
2edcd244 7046 unsigned long value = 0;
c22aaad1 7047 int cond;
8afc7bea 7048 int cp_num;
823d2571
TG		 7049 struct arm_private_data *private_data = info->private_data;
7050 arm_feature_set allowed_arches = ARM_ARCH_NONE;
32c36c3c
AV		 7051 arm_feature_set arm_ext_v8_1m_main =
7052 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
823d2571 7053
5b616bef 7054 allowed_arches = private_data->features;
8f06b2d8
PB		 7055
7056 for (insn = coprocessor_opcodes; insn->assembler; insn++)
7057 {
ff4a8d2b
NC		 7058 unsigned long u_reg = 16;
7059 bfd_boolean is_unpredictable = FALSE;
05413229 7060 signed long value_in_comment = 0;
0313a2b8
NC		 7061 const char *c;
7062
823d2571 7063 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 7064 switch (insn->value)
7065 {
7066 case SENTINEL_IWMMXT_START:
7067 if (info->mach != bfd_mach_arm_XScale
7068 && info->mach != bfd_mach_arm_iWMMXt
7069 && info->mach != bfd_mach_arm_iWMMXt2)
7070 do
7071 insn++;
823d2571
TG		 7072 while ((! ARM_FEATURE_ZERO (insn->arch))
7073 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 7074 continue;
7075
7076 case SENTINEL_IWMMXT_END:
7077 continue;
7078
7079 case SENTINEL_GENERIC_START:
5b616bef 7080 allowed_arches = private_data->features;
05413229
NC		 7081 continue;
7082
7083 default:
7084 abort ();
7085 }
8f06b2d8
PB		 7086
7087 mask = insn->mask;
7088 value = insn->value;
8afc7bea
RL		 7089 cp_num = (given >> 8) & 0xf;
7090
8f06b2d8
PB		 7091 if (thumb)
7092 {
7093 /* The high 4 bits are 0xe for Arm conditional instructions, and
7094 0xe for arm unconditional instructions. The rest of the
7095 encoding is the same. */
7096 mask |= 0xf0000000;
7097 value |= 0xe0000000;
c22aaad1
PB		 7098 if (ifthen_state)
7099 cond = IFTHEN_COND;
7100 else
e2efe87d 7101 cond = COND_UNCOND;
8f06b2d8
PB		 7102 }
7103 else
7104 {
7105 /* Only match unconditional instuctions against unconditional
7106 patterns. */
7107 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 7108 {
7109 mask |= 0xf0000000;
e2efe87d 7110 cond = COND_UNCOND;
c22aaad1
PB		 7111 }
7112 else
7113 {
7114 cond = (given >> 28) & 0xf;
7115 if (cond == 0xe)
e2efe87d 7116 cond = COND_UNCOND;
c22aaad1 7117 }
8f06b2d8 7118 }
823d2571 7119
6b0dd094
AV		 7120 if ((insn->isa == T32 && !thumb)
7121 || (insn->isa == ARM && thumb))
7122 continue;
7123
0313a2b8
NC		 7124 if ((given & mask) != value)
7125 continue;
8f06b2d8 7126
823d2571 7127 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 7128 continue;
7129
8afc7bea
RL		 7130 if (insn->value == 0xfe000010 /* mcr2 */
7131 || insn->value == 0xfe100010 /* mrc2 */
7132 || insn->value == 0xfc100000 /* ldc2 */
7133 || insn->value == 0xfc000000) /* stc2 */
7134 {
b0c11777 7135 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 7136 is_unpredictable = TRUE;
f08d8ce3
AV		 7137
7138 /* Armv8.1-M Mainline FP & MVE instructions. */
7139 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
7140 && !ARM_CPU_IS_ANY (allowed_arches)
7141 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
7142 continue;
7143
8afc7bea
RL		 7144 }
7145 else if (insn->value == 0x0e000000 /* cdp */
7146 || insn->value == 0xfe000000 /* cdp2 */
7147 || insn->value == 0x0e000010 /* mcr */
7148 || insn->value == 0x0e100010 /* mrc */
7149 || insn->value == 0x0c100000 /* ldc */
7150 || insn->value == 0x0c000000) /* stc */
7151 {
7152 /* Floating-point instructions. */
b0c11777 7153 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 7154 continue;
32c36c3c
AV		 7155
7156 /* Armv8.1-M Mainline FP & MVE instructions. */
7157 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
7158 && !ARM_CPU_IS_ANY (allowed_arches)
7159 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
7160 continue;
8afc7bea 7161 }
aef6d006
AV		 7162 else if ((insn->value == 0xec100f80 /* vldr (system register) */
7163 || insn->value == 0xec000f80) /* vstr (system register) */
7164 && arm_decode_field (given, 24, 24) == 0
7165 && arm_decode_field (given, 21, 21) == 0)
7166 /* If the P and W bits are both 0 then these encodings match the MVE
7167 VLDR and VSTR instructions, these are in a different table, so we
7168 don't let it match here. */
7169 continue;
7170
0313a2b8
NC		 7171 for (c = insn->assembler; *c; c++)
7172 {
7173 if (*c == '%')
8f06b2d8 7174 {
32c36c3c
AV		 7175 const char mod = *++c;
7176 switch (mod)
8f06b2d8 7177 {
0313a2b8
NC		 7178 case '%':
7179 func (stream, "%%");
7180 break;
7181
7182 case 'A':
32c36c3c 7183 case 'K':
05413229 7184 {
79862e45 7185 int rn = (given >> 16) & 0xf;
b0c11777 7186 bfd_vma offset = given & 0xff;
0313a2b8 7187
32c36c3c
AV		 7188 if (mod == 'K')
7189 offset = given & 0x7f;
7190
05413229 7191 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 7192
79862e45
DJ		 7193 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
7194 {
7195 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 7196 if (cp_num == 9)
7197 /* vldr.16/vstr.16 will shift the address
7198 left by 1 bit only. */
7199 offset = offset * 2;
7200 else
7201 offset = offset * 4;
7202
79862e45
DJ		 7203 if (NEGATIVE_BIT_SET)
7204 offset = - offset;
7205 if (rn != 15)
7206 value_in_comment = offset;
7207 }
7208
c1e26897 7209 if (PRE_BIT_SET)
05413229
NC		 7210 {
7211 if (offset)
fe56b6ce 7212 func (stream, ", #%d]%s",
d908c8af 7213 (int) offset,
c1e26897 7214 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 7215 else if (NEGATIVE_BIT_SET)
7216 func (stream, ", #-0]");
05413229
NC		 7217 else
7218 func (stream, "]");
7219 }
7220 else
7221 {
0313a2b8 7222 func (stream, "]");
8f06b2d8 7223
c1e26897 7224 if (WRITEBACK_BIT_SET)
05413229
NC		 7225 {
7226 if (offset)
d908c8af 7227 func (stream, ", #%d", (int) offset);
26d97720
NS		 7228 else if (NEGATIVE_BIT_SET)
7229 func (stream, ", #-0");
05413229
NC		 7230 }
7231 else
fe56b6ce 7232 {
26d97720
NS		 7233 func (stream, ", {%s%d}",
7234 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 7235 (int) offset);
fe56b6ce
NC		 7236 value_in_comment = offset;
7237 }
05413229 7238 }
79862e45
DJ		 7239 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
7240 {
7241 func (stream, "\t; ");
6844b2c2
MGD		 7242 /* For unaligned PCs, apply off-by-alignment
7243 correction. */
43e65147 7244 info->print_address_func (offset + pc
6844b2c2
MGD		 7245 + info->bytes_per_chunk * 2
7246 - (pc & 3),
dffaa15c 7247 info);
79862e45 7248 }
05413229 7249 }
0313a2b8 7250 break;
8f06b2d8 7251
0313a2b8
NC		 7252 case 'B':
7253 {
7254 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
7255 int offset = (given >> 1) & 0x3f;
7256
7257 if (offset == 1)
7258 func (stream, "{d%d}", regno);
7259 else if (regno + offset > 32)
7260 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
7261 else
7262 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
7263 }
7264 break;
8f06b2d8 7265
efd6b359
AV		 7266 case 'C':
7267 {
7268 bfd_boolean single = ((given >> 8) & 1) == 0;
7269 char reg_prefix = single ? 's' : 'd';
7270 int Dreg = (given >> 22) & 0x1;
7271 int Vdreg = (given >> 12) & 0xf;
7272 int reg = single ? ((Vdreg << 1) | Dreg)
7273 : ((Dreg << 4) | Vdreg);
7274 int num = (given >> (single ? 0 : 1)) & 0x7f;
7275 int maxreg = single ? 31 : 15;
7276 int topreg = reg + num - 1;
7277
7278 if (!num)
7279 func (stream, "{VPR}");
7280 else if (num == 1)
7281 func (stream, "{%c%d, VPR}", reg_prefix, reg);
7282 else if (topreg > maxreg)
7283 func (stream, "{%c%d-<overflow reg d%d, VPR}",
7284 reg_prefix, reg, single ? topreg >> 1 : topreg);
7285 else
7286 func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
7287 reg_prefix, topreg);
7288 }
7289 break;
7290
e2efe87d
MGD		 7291 case 'u':
7292 if (cond != COND_UNCOND)
7293 is_unpredictable = TRUE;
7294
7295 /* Fall through. */
0313a2b8 7296 case 'c':
b0c11777
RL		 7297 if (cond != COND_UNCOND && cp_num == 9)
7298 is_unpredictable = TRUE;
7299
0313a2b8
NC		 7300 func (stream, "%s", arm_conditional[cond]);
7301 break;
8f06b2d8 7302
0313a2b8
NC		 7303 case 'I':
7304 /* Print a Cirrus/DSP shift immediate. */
7305 /* Immediates are 7bit signed ints with bits 0..3 in
7306 bits 0..3 of opcode and bits 4..6 in bits 5..7
7307 of opcode. */
7308 {
7309 int imm;
8f06b2d8 7310
0313a2b8 7311 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 7312
0313a2b8
NC		 7313 /* Is ``imm'' a negative number? */
7314 if (imm & 0x40)
24b4cf66 7315 imm -= 0x80;
8f06b2d8 7316
0313a2b8
NC		 7317 func (stream, "%d", imm);
7318 }
7319
7320 break;
8f06b2d8 7321
32c36c3c
AV		 7322 case 'J':
7323 {
73cd51e5
AV		 7324 unsigned long regno
7325 = arm_decode_field_multiple (given, 13, 15, 22, 22);
32c36c3c
AV		 7326
7327 switch (regno)
7328 {
7329 case 0x1:
7330 func (stream, "FPSCR");
7331 break;
7332 case 0x2:
7333 func (stream, "FPSCR_nzcvqc");
7334 break;
7335 case 0xc:
7336 func (stream, "VPR");
7337 break;
7338 case 0xd:
7339 func (stream, "P0");
7340 break;
7341 case 0xe:
7342 func (stream, "FPCXTNS");
7343 break;
7344 case 0xf:
7345 func (stream, "FPCXTS");
7346 break;
7347 default:
73cd51e5 7348 func (stream, "<invalid reg %lu>", regno);
32c36c3c
AV		 7349 break;
7350 }
7351 }
7352 break;
7353
0313a2b8
NC		 7354 case 'F':
7355 switch (given & 0x00408000)
7356 {
7357 case 0:
7358 func (stream, "4");
7359 break;
7360 case 0x8000:
7361 func (stream, "1");
7362 break;
7363 case 0x00400000:
7364 func (stream, "2");
8f06b2d8 7365 break;
0313a2b8
NC		 7366 default:
7367 func (stream, "3");
7368 }
7369 break;
8f06b2d8 7370
0313a2b8
NC		 7371 case 'P':
7372 switch (given & 0x00080080)
7373 {
7374 case 0:
7375 func (stream, "s");
7376 break;
7377 case 0x80:
7378 func (stream, "d");
7379 break;
7380 case 0x00080000:
7381 func (stream, "e");
7382 break;
7383 default:
7384 func (stream, _("<illegal precision>"));
8f06b2d8 7385 break;
0313a2b8
NC		 7386 }
7387 break;
8f06b2d8 7388
0313a2b8
NC		 7389 case 'Q':
7390 switch (given & 0x00408000)
7391 {
7392 case 0:
7393 func (stream, "s");
8f06b2d8 7394 break;
0313a2b8
NC		 7395 case 0x8000:
7396 func (stream, "d");
8f06b2d8 7397 break;
0313a2b8
NC		 7398 case 0x00400000:
7399 func (stream, "e");
7400 break;
7401 default:
7402 func (stream, "p");
8f06b2d8 7403 break;
0313a2b8
NC		 7404 }
7405 break;
8f06b2d8 7406
0313a2b8
NC		 7407 case 'R':
7408 switch (given & 0x60)
7409 {
7410 case 0:
7411 break;
7412 case 0x20:
7413 func (stream, "p");
7414 break;
7415 case 0x40:
7416 func (stream, "m");
7417 break;
7418 default:
7419 func (stream, "z");
7420 break;
7421 }
7422 break;
16980d0b 7423
0313a2b8
NC		 7424 case '0': case '1': case '2': case '3': case '4':
7425 case '5': case '6': case '7': case '8': case '9':
7426 {
7427 int width;
8f06b2d8 7428
0313a2b8 7429 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 7430
0313a2b8
NC		 7431 switch (*c)
7432 {
ff4a8d2b
NC		 7433 case 'R':
7434 if (value == 15)
7435 is_unpredictable = TRUE;
7436 /* Fall through. */
0313a2b8 7437 case 'r':
ff4a8d2b
NC		 7438 if (c[1] == 'u')
7439 {
7440 /* Eat the 'u' character. */
7441 ++ c;
7442
7443 if (u_reg == value)
7444 is_unpredictable = TRUE;
7445 u_reg = value;
7446 }
0313a2b8
NC		 7447 func (stream, "%s", arm_regnames[value]);
7448 break;
c28eeff2
SN		 7449 case 'V':
7450 if (given & (1 << 6))
7451 goto Q;
7452 /* FALLTHROUGH */
0313a2b8
NC		 7453 case 'D':
7454 func (stream, "d%ld", value);
7455 break;
7456 case 'Q':
c28eeff2 7457 Q:
0313a2b8
NC		 7458 if (value & 1)
7459 func (stream, "<illegal reg q%ld.5>", value >> 1);
7460 else
7461 func (stream, "q%ld", value >> 1);
7462 break;
7463 case 'd':
7464 func (stream, "%ld", value);
05413229 7465 value_in_comment = value;
0313a2b8 7466 break;
6f1c2142
AM		 7467 case 'E':
7468 {
7469 /* Converts immediate 8 bit back to float value. */
7470 unsigned floatVal = (value & 0x80) << 24
7471 | (value & 0x3F) << 19
7472 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
7473
7474 /* Quarter float have a maximum value of 31.0.
7475 Get floating point value multiplied by 1e7.
7476 The maximum value stays in limit of a 32-bit int. */
7477 unsigned decVal =
7478 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
7479 (16 + (value & 0xF));
7480
7481 if (!(decVal % 1000000))
7482 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
7483 floatVal, value & 0x80 ? '-' : ' ',
7484 decVal / 10000000,
7485 decVal % 10000000 / 1000000);
7486 else if (!(decVal % 10000))
7487 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
7488 floatVal, value & 0x80 ? '-' : ' ',
7489 decVal / 10000000,
7490 decVal % 10000000 / 10000);
7491 else
7492 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
7493 floatVal, value & 0x80 ? '-' : ' ',
7494 decVal / 10000000, decVal % 10000000);
7495 break;
7496 }
0313a2b8
NC		 7497 case 'k':
7498 {
7499 int from = (given & (1 << 7)) ? 32 : 16;
7500 func (stream, "%ld", from - value);
7501 }
7502 break;
8f06b2d8 7503
0313a2b8
NC		 7504 case 'f':
7505 if (value > 7)
7506 func (stream, "#%s", arm_fp_const[value & 7]);
7507 else
7508 func (stream, "f%ld", value);
7509 break;
4146fd53 7510
0313a2b8
NC		 7511 case 'w':
7512 if (width == 2)
7513 func (stream, "%s", iwmmxt_wwnames[value]);
7514 else
7515 func (stream, "%s", iwmmxt_wwssnames[value]);
7516 break;
4146fd53 7517
0313a2b8
NC		 7518 case 'g':
7519 func (stream, "%s", iwmmxt_regnames[value]);
7520 break;
7521 case 'G':
7522 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 7523 break;
8f06b2d8 7524
0313a2b8 7525 case 'x':
d1aaab3c 7526 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 7527 break;
8f06b2d8 7528
33399f07
MGD		 7529 case 'c':
7530 switch (value)
7531 {
7532 case 0:
7533 func (stream, "eq");
7534 break;
7535
7536 case 1:
7537 func (stream, "vs");
7538 break;
7539
7540 case 2:
7541 func (stream, "ge");
7542 break;
7543
7544 case 3:
7545 func (stream, "gt");
7546 break;
7547
7548 default:
7549 func (stream, "??");
7550 break;
7551 }
7552 break;
7553
0313a2b8
NC		 7554 case '`':
7555 c++;
7556 if (value == 0)
7557 func (stream, "%c", *c);
7558 break;
7559 case '\'':
7560 c++;
7561 if (value == ((1ul << width) - 1))
7562 func (stream, "%c", *c);
7563 break;
7564 case '?':
fe56b6ce 7565 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 7566 c += 1 << width;
7567 break;
7568 default:
7569 abort ();
7570 }
dffaa15c
AM		 7571 }
7572 break;
0313a2b8 7573
dffaa15c
AM		 7574 case 'y':
7575 case 'z':
7576 {
7577 int single = *c++ == 'y';
7578 int regno;
8f06b2d8 7579
dffaa15c
AM		 7580 switch (*c)
7581 {
7582 case '4': /* Sm pair */
7583 case '0': /* Sm, Dm */
7584 regno = given & 0x0000000f;
7585 if (single)
7586 {
7587 regno <<= 1;
7588 regno += (given >> 5) & 1;
7589 }
7590 else
7591 regno += ((given >> 5) & 1) << 4;
7592 break;
8f06b2d8 7593
dffaa15c
AM		 7594 case '1': /* Sd, Dd */
7595 regno = (given >> 12) & 0x0000000f;
7596 if (single)
7597 {
7598 regno <<= 1;
7599 regno += (given >> 22) & 1;
7600 }
7601 else
7602 regno += ((given >> 22) & 1) << 4;
7603 break;
7df76b80 7604
dffaa15c
AM		 7605 case '2': /* Sn, Dn */
7606 regno = (given >> 16) & 0x0000000f;
7607 if (single)
7608 {
7609 regno <<= 1;
7610 regno += (given >> 7) & 1;
7611 }
7612 else
7613 regno += ((given >> 7) & 1) << 4;
7614 break;
a7f8487e 7615
dffaa15c
AM		 7616 case '3': /* List */
7617 func (stream, "{");
7618 regno = (given >> 12) & 0x0000000f;
7619 if (single)
7620 {
7621 regno <<= 1;
7622 regno += (given >> 22) & 1;
7623 }
7624 else
7625 regno += ((given >> 22) & 1) << 4;
7626 break;
a7f8487e 7627
dffaa15c
AM		 7628 default:
7629 abort ();
7630 }
0313a2b8 7631
dffaa15c 7632 func (stream, "%c%d", single ? 's' : 'd', regno);
a7f8487e 7633
dffaa15c
AM		 7634 if (*c == '3')
7635 {
7636 int count = given & 0xff;
b34976b6 7637
dffaa15c
AM		 7638 if (single == 0)
7639 count >>= 1;
0313a2b8 7640
dffaa15c
AM		 7641 if (--count)
7642 {
7643 func (stream, "-%c%d",
7644 single ? 's' : 'd',
7645 regno + count);
7646 }
0313a2b8 7647
dffaa15c 7648 func (stream, "}");
0313a2b8 7649 }
dffaa15c
AM		 7650 else if (*c == '4')
7651 func (stream, ", %c%d", single ? 's' : 'd',
7652 regno + 1);
7653 }
7654 break;
b34976b6 7655
dffaa15c
AM		 7656 case 'L':
7657 switch (given & 0x00400100)
0313a2b8 7658 {
dffaa15c
AM		 7659 case 0x00000000: func (stream, "b"); break;
7660 case 0x00400000: func (stream, "h"); break;
7661 case 0x00000100: func (stream, "w"); break;
7662 case 0x00400100: func (stream, "d"); break;
7663 default:
7664 break;
0313a2b8 7665 }
dffaa15c 7666 break;
2d447fca 7667
dffaa15c
AM		 7668 case 'Z':
7669 {
7670 /* given (20, 23) | given (0, 3) */
7671 value = ((given >> 16) & 0xf0) | (given & 0xf);
7672 func (stream, "%d", (int) value);
7673 }
7674 break;
0313a2b8 7675
dffaa15c
AM		 7676 case 'l':
7677 /* This is like the 'A' operator, except that if
7678 the width field "M" is zero, then the offset is
7679 *not* multiplied by four. */
7680 {
7681 int offset = given & 0xff;
7682 int multiplier = (given & 0x00000100) ? 4 : 1;
0313a2b8 7683
dffaa15c 7684 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
05413229 7685
dffaa15c
AM		 7686 if (multiplier > 1)
7687 {
7688 value_in_comment = offset * multiplier;
7689 if (NEGATIVE_BIT_SET)
7690 value_in_comment = - value_in_comment;
7691 }
0313a2b8 7692
dffaa15c
AM		 7693 if (offset)
7694 {
7695 if (PRE_BIT_SET)
7696 func (stream, ", #%s%d]%s",
7697 NEGATIVE_BIT_SET ? "-" : "",
7698 offset * multiplier,
7699 WRITEBACK_BIT_SET ? "!" : "");
7700 else
7701 func (stream, "], #%s%d",
7702 NEGATIVE_BIT_SET ? "-" : "",
7703 offset * multiplier);
7704 }
7705 else
7706 func (stream, "]");
7707 }
7708 break;
2d447fca 7709
dffaa15c
AM		 7710 case 'r':
7711 {
7712 int imm4 = (given >> 4) & 0xf;
7713 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
7714 int ubit = ! NEGATIVE_BIT_SET;
7715 const char *rm = arm_regnames [given & 0xf];
7716 const char *rn = arm_regnames [(given >> 16) & 0xf];
0313a2b8 7717
dffaa15c
AM		 7718 switch (puw_bits)
7719 {
7720 case 1:
7721 case 3:
7722 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
7723 if (imm4)
7724 func (stream, ", lsl #%d", imm4);
7725 break;
0313a2b8 7726
dffaa15c
AM		 7727 case 4:
7728 case 5:
7729 case 6:
7730 case 7:
7731 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
7732 if (imm4 > 0)
7733 func (stream, ", lsl #%d", imm4);
7734 func (stream, "]");
7735 if (puw_bits == 5 || puw_bits == 7)
7736 func (stream, "!");
7737 break;
2d447fca 7738
dffaa15c
AM		 7739 default:
7740 func (stream, "INVALID");
7741 }
7742 }
7743 break;
0313a2b8 7744
dffaa15c
AM		 7745 case 'i':
7746 {
7747 long imm5;
7748 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
7749 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
0313a2b8 7750 }
dffaa15c
AM		 7751 break;
7752
7753 default:
7754 abort ();
252b5132 7755 }
252b5132 7756 }
0313a2b8
NC		 7757 else
7758 func (stream, "%c", *c);
252b5132 7759 }
05413229
NC		 7760
7761 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 7762 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 7763
ff4a8d2b
NC		 7764 if (is_unpredictable)
7765 func (stream, UNPREDICTABLE_INSTRUCTION);
7766
0313a2b8 7767 return TRUE;
252b5132 7768 }
8f06b2d8 7769 return FALSE;
252b5132
RH		 7770}
7771
05413229
NC		 7772/* Decodes and prints ARM addressing modes. Returns the offset
7773 used in the address, if any, if it is worthwhile printing the
7774 offset as a hexadecimal value in a comment at the end of the
7775 line of disassembly. */
7776
7777static signed long
62b3e311
PB		 7778print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
7779{
7780 void *stream = info->stream;
7781 fprintf_ftype func = info->fprintf_func;
f8b960bc 7782 bfd_vma offset = 0;
62b3e311
PB		 7783
7784 if (((given & 0x000f0000) == 0x000f0000)
7785 && ((given & 0x02000000) == 0))
7786 {
05413229 7787 offset = given & 0xfff;
62b3e311
PB		 7788
7789 func (stream, "[pc");
7790
c1e26897 7791 if (PRE_BIT_SET)
62b3e311 7792 {
26d97720
NS		 7793 /* Pre-indexed. Elide offset of positive zero when
7794 non-writeback. */
7795 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 7796 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 7797
7798 if (NEGATIVE_BIT_SET)
7799 offset = -offset;
62b3e311
PB		 7800
7801 offset += pc + 8;
7802
7803 /* Cope with the possibility of write-back
7804 being used. Probably a very dangerous thing
7805 for the programmer to do, but who are we to
7806 argue ? */
26d97720 7807 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 7808 }
c1e26897 7809 else /* Post indexed. */
62b3e311 7810 {
d908c8af 7811 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 7812
c1e26897 7813 /* Ie ignore the offset. */
62b3e311
PB		 7814 offset = pc + 8;
7815 }
7816
7817 func (stream, "\t; ");
7818 info->print_address_func (offset, info);
05413229 7819 offset = 0;
62b3e311
PB		 7820 }
7821 else
7822 {
7823 func (stream, "[%s",
7824 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 7825
7826 if (PRE_BIT_SET)
62b3e311
PB		 7827 {
7828 if ((given & 0x02000000) == 0)
7829 {
26d97720 7830 /* Elide offset of positive zero when non-writeback. */
05413229 7831 offset = given & 0xfff;
26d97720 7832 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 7833 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 7834 }
7835 else
7836 {
26d97720 7837 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 7838 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 7839 }
7840
7841 func (stream, "]%s",
c1e26897 7842 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 7843 }
7844 else
7845 {
7846 if ((given & 0x02000000) == 0)
7847 {
26d97720 7848 /* Always show offset. */
05413229 7849 offset = given & 0xfff;
26d97720 7850 func (stream, "], #%s%d",
d908c8af 7851 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 7852 }
7853 else
7854 {
7855 func (stream, "], %s",
c1e26897 7856 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 7857 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 7858 }
7859 }
84919466
MR		 7860 if (NEGATIVE_BIT_SET)
7861 offset = -offset;
62b3e311 7862 }
05413229
NC		 7863
7864 return (signed long) offset;
62b3e311
PB		 7865}
7866
16980d0b
JB		 7867/* Print one neon instruction on INFO->STREAM.
7868 Return TRUE if the instuction matched, FALSE if this is not a
7869 recognised neon instruction. */
7870
7871static bfd_boolean
7872print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
7873{
7874 const struct opcode32 *insn;
7875 void *stream = info->stream;
7876 fprintf_ftype func = info->fprintf_func;
7877
7878 if (thumb)
7879 {
7880 if ((given & 0xef000000) == 0xef000000)
7881 {
0313a2b8 7882 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 7883 unsigned long bit28 = given & (1 << 28);
7884
7885 given &= 0x00ffffff;
7886 if (bit28)
7887 given |= 0xf3000000;
7888 else
7889 given |= 0xf2000000;
7890 }
7891 else if ((given & 0xff000000) == 0xf9000000)
7892 given ^= 0xf9000000 ^ 0xf4000000;
9743db03
AV		 7893 /* vdup is also a valid neon instruction. */
7894 else if ((given & 0xff910f5f) != 0xee800b10)
16980d0b
JB		 7895 return FALSE;
7896 }
43e65147 7897
16980d0b
JB		 7898 for (insn = neon_opcodes; insn->assembler; insn++)
7899 {
7900 if ((given & insn->mask) == insn->value)
7901 {
05413229 7902 signed long value_in_comment = 0;
e2efe87d 7903 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 7904 const char *c;
7905
7906 for (c = insn->assembler; *c; c++)
7907 {
7908 if (*c == '%')
7909 {
7910 switch (*++c)
7911 {
7912 case '%':
7913 func (stream, "%%");
7914 break;
7915
e2efe87d
MGD		 7916 case 'u':
7917 if (thumb && ifthen_state)
7918 is_unpredictable = TRUE;
7919
7920 /* Fall through. */
c22aaad1
PB		 7921 case 'c':
7922 if (thumb && ifthen_state)
7923 func (stream, "%s", arm_conditional[IFTHEN_COND]);
7924 break;
7925
16980d0b
JB		 7926 case 'A':
7927 {
43e65147 7928 static const unsigned char enc[16] =
16980d0b
JB		 7929 {
7930 0x4, 0x14, /* st4 0,1 */
7931 0x4, /* st1 2 */
7932 0x4, /* st2 3 */
7933 0x3, /* st3 4 */
7934 0x13, /* st3 5 */
7935 0x3, /* st1 6 */
7936 0x1, /* st1 7 */
7937 0x2, /* st2 8 */
7938 0x12, /* st2 9 */
7939 0x2, /* st1 10 */
7940 0, 0, 0, 0, 0
7941 };
7942 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
7943 int rn = ((given >> 16) & 0xf);
7944 int rm = ((given >> 0) & 0xf);
7945 int align = ((given >> 4) & 0x3);
7946 int type = ((given >> 8) & 0xf);
7947 int n = enc[type] & 0xf;
7948 int stride = (enc[type] >> 4) + 1;
7949 int ix;
43e65147 7950
16980d0b
JB		 7951 func (stream, "{");
7952 if (stride > 1)
7953 for (ix = 0; ix != n; ix++)
7954 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
7955 else if (n == 1)
7956 func (stream, "d%d", rd);
7957 else
7958 func (stream, "d%d-d%d", rd, rd + n - 1);
7959 func (stream, "}, [%s", arm_regnames[rn]);
7960 if (align)
8e560766 7961 func (stream, " :%d", 32 << align);
16980d0b
JB		 7962 func (stream, "]");
7963 if (rm == 0xd)
7964 func (stream, "!");
7965 else if (rm != 0xf)
7966 func (stream, ", %s", arm_regnames[rm]);
7967 }
7968 break;
43e65147 7969
16980d0b
JB		 7970 case 'B':
7971 {
7972 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
7973 int rn = ((given >> 16) & 0xf);
7974 int rm = ((given >> 0) & 0xf);
7975 int idx_align = ((given >> 4) & 0xf);
7976 int align = 0;
7977 int size = ((given >> 10) & 0x3);
7978 int idx = idx_align >> (size + 1);
7979 int length = ((given >> 8) & 3) + 1;
7980 int stride = 1;
7981 int i;
7982
7983 if (length > 1 && size > 0)
7984 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 7985
16980d0b
JB		 7986 switch (length)
7987 {
7988 case 1:
7989 {
7990 int amask = (1 << size) - 1;
7991 if ((idx_align & (1 << size)) != 0)
7992 return FALSE;
7993 if (size > 0)
7994 {
7995 if ((idx_align & amask) == amask)
7996 align = 8 << size;
7997 else if ((idx_align & amask) != 0)
7998 return FALSE;
7999 }
8000 }
8001 break;
43e65147 8002
16980d0b
JB		 8003 case 2:
8004 if (size == 2 && (idx_align & 2) != 0)
8005 return FALSE;
8006 align = (idx_align & 1) ? 16 << size : 0;
8007 break;
43e65147 8008
16980d0b
JB		 8009 case 3:
8010 if ((size == 2 && (idx_align & 3) != 0)
8011 || (idx_align & 1) != 0)
8012 return FALSE;
8013 break;
43e65147 8014
16980d0b
JB		 8015 case 4:
8016 if (size == 2)
8017 {
8018 if ((idx_align & 3) == 3)
8019 return FALSE;
8020 align = (idx_align & 3) * 64;
8021 }
8022 else
8023 align = (idx_align & 1) ? 32 << size : 0;
8024 break;
43e65147 8025
16980d0b
JB		 8026 default:
8027 abort ();
8028 }
43e65147 8029
16980d0b
JB		 8030 func (stream, "{");
8031 for (i = 0; i < length; i++)
8032 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
8033 rd + i * stride, idx);
8034 func (stream, "}, [%s", arm_regnames[rn]);
8035 if (align)
8e560766 8036 func (stream, " :%d", align);
16980d0b
JB		 8037 func (stream, "]");
8038 if (rm == 0xd)
8039 func (stream, "!");
8040 else if (rm != 0xf)
8041 func (stream, ", %s", arm_regnames[rm]);
8042 }
8043 break;
43e65147 8044
16980d0b
JB		 8045 case 'C':
8046 {
8047 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8048 int rn = ((given >> 16) & 0xf);
8049 int rm = ((given >> 0) & 0xf);
8050 int align = ((given >> 4) & 0x1);
8051 int size = ((given >> 6) & 0x3);
8052 int type = ((given >> 8) & 0x3);
8053 int n = type + 1;
8054 int stride = ((given >> 5) & 0x1);
8055 int ix;
43e65147 8056
16980d0b
JB		 8057 if (stride && (n == 1))
8058 n++;
8059 else
8060 stride++;
43e65147 8061
16980d0b
JB		 8062 func (stream, "{");
8063 if (stride > 1)
8064 for (ix = 0; ix != n; ix++)
8065 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
8066 else if (n == 1)
8067 func (stream, "d%d[]", rd);
8068 else
8069 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
8070 func (stream, "}, [%s", arm_regnames[rn]);
8071 if (align)
8072 {
91d6fa6a 8073 align = (8 * (type + 1)) << size;
16980d0b
JB		 8074 if (type == 3)
8075 align = (size > 1) ? align >> 1 : align;
8076 if (type == 2 || (type == 0 && !size))
8e560766 8077 func (stream, " :<bad align %d>", align);
16980d0b 8078 else
8e560766 8079 func (stream, " :%d", align);
16980d0b
JB		 8080 }
8081 func (stream, "]");
8082 if (rm == 0xd)
8083 func (stream, "!");
8084 else if (rm != 0xf)
8085 func (stream, ", %s", arm_regnames[rm]);
8086 }
8087 break;
43e65147 8088
16980d0b
JB		 8089 case 'D':
8090 {
8091 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
8092 int size = (given >> 20) & 3;
8093 int reg = raw_reg & ((4 << size) - 1);
8094 int ix = raw_reg >> size >> 2;
43e65147 8095
16980d0b
JB		 8096 func (stream, "d%d[%d]", reg, ix);
8097 }
8098 break;
43e65147 8099
16980d0b 8100 case 'E':
fe56b6ce 8101 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 8102 {
8103 int bits = 0;
8104 int cmode = (given >> 8) & 0xf;
8105 int op = (given >> 5) & 0x1;
8106 unsigned long value = 0, hival = 0;
8107 unsigned shift;
8108 int size = 0;
0dbde4cf 8109 int isfloat = 0;
43e65147 8110
16980d0b
JB		 8111 bits |= ((given >> 24) & 1) << 7;
8112 bits |= ((given >> 16) & 7) << 4;
8113 bits |= ((given >> 0) & 15) << 0;
43e65147 8114
16980d0b
JB		 8115 if (cmode < 8)
8116 {
8117 shift = (cmode >> 1) & 3;
fe56b6ce 8118 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 8119 size = 32;
8120 }
8121 else if (cmode < 12)
8122 {
8123 shift = (cmode >> 1) & 1;
fe56b6ce 8124 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 8125 size = 16;
8126 }
8127 else if (cmode < 14)
8128 {
8129 shift = (cmode & 1) + 1;
fe56b6ce 8130 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 8131 value |= (1ul << (8 * shift)) - 1;
8132 size = 32;
8133 }
8134 else if (cmode == 14)
8135 {
8136 if (op)
8137 {
fe56b6ce 8138 /* Bit replication into bytes. */
16980d0b
JB		 8139 int ix;
8140 unsigned long mask;
43e65147 8141
16980d0b
JB		 8142 value = 0;
8143 hival = 0;
8144 for (ix = 7; ix >= 0; ix--)
8145 {
8146 mask = ((bits >> ix) & 1) ? 0xff : 0;
8147 if (ix <= 3)
8148 value = (value << 8) | mask;
8149 else
8150 hival = (hival << 8) | mask;
8151 }
8152 size = 64;
8153 }
8154 else
8155 {
fe56b6ce
NC		 8156 /* Byte replication. */
8157 value = (unsigned long) bits;
16980d0b
JB		 8158 size = 8;
8159 }
8160 }
8161 else if (!op)
8162 {
fe56b6ce 8163 /* Floating point encoding. */
16980d0b 8164 int tmp;
43e65147 8165
fe56b6ce
NC		 8166 value = (unsigned long) (bits & 0x7f) << 19;
8167 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 8168 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 8169 value |= (unsigned long) tmp << 24;
16980d0b 8170 size = 32;
0dbde4cf 8171 isfloat = 1;
16980d0b
JB		 8172 }
8173 else
8174 {
8175 func (stream, "<illegal constant %.8x:%x:%x>",
8176 bits, cmode, op);
8177 size = 32;
8178 break;
8179 }
8180 switch (size)
8181 {
8182 case 8:
8183 func (stream, "#%ld\t; 0x%.2lx", value, value);
8184 break;
43e65147 8185
16980d0b
JB		 8186 case 16:
8187 func (stream, "#%ld\t; 0x%.4lx", value, value);
8188 break;
8189
8190 case 32:
0dbde4cf
JB		 8191 if (isfloat)
8192 {
8193 unsigned char valbytes[4];
8194 double fvalue;
43e65147 8195
0dbde4cf
JB		 8196 /* Do this a byte at a time so we don't have to
8197 worry about the host's endianness. */
8198 valbytes[0] = value & 0xff;
8199 valbytes[1] = (value >> 8) & 0xff;
8200 valbytes[2] = (value >> 16) & 0xff;
8201 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 8202
8203 floatformat_to_double
c1e26897
NC		 8204 (& floatformat_ieee_single_little, valbytes,
8205 & fvalue);
43e65147 8206
0dbde4cf
JB		 8207 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
8208 value);
8209 }
8210 else
4e9d3b81 8211 func (stream, "#%ld\t; 0x%.8lx",
43e65147 8212 (long) (((value & 0x80000000L) != 0)
9d82ec38 8213 ? value | ~0xffffffffL : value),
c1e26897 8214 value);
16980d0b
JB		 8215 break;
8216
8217 case 64:
8218 func (stream, "#0x%.8lx%.8lx", hival, value);
8219 break;
43e65147 8220
16980d0b
JB		 8221 default:
8222 abort ();
8223 }
8224 }
8225 break;
43e65147 8226
16980d0b
JB		 8227 case 'F':
8228 {
8229 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
8230 int num = (given >> 8) & 0x3;
43e65147 8231
16980d0b
JB		 8232 if (!num)
8233 func (stream, "{d%d}", regno);
8234 else if (num + regno >= 32)
8235 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
8236 else
8237 func (stream, "{d%d-d%d}", regno, regno + num);
8238 }
8239 break;
7e8e6784 8240
16980d0b
JB		 8241
8242 case '0': case '1': case '2': case '3': case '4':
8243 case '5': case '6': case '7': case '8': case '9':
8244 {
8245 int width;
8246 unsigned long value;
8247
8248 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 8249
16980d0b
JB		 8250 switch (*c)
8251 {
8252 case 'r':
8253 func (stream, "%s", arm_regnames[value]);
8254 break;
8255 case 'd':
8256 func (stream, "%ld", value);
05413229 8257 value_in_comment = value;
16980d0b
JB		 8258 break;
8259 case 'e':
8260 func (stream, "%ld", (1ul << width) - value);
8261 break;
43e65147 8262
16980d0b
JB		 8263 case 'S':
8264 case 'T':
8265 case 'U':
05413229 8266 /* Various width encodings. */
16980d0b
JB		 8267 {
8268 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
8269 int limit;
8270 unsigned low, high;
8271
8272 c++;
8273 if (*c >= '0' && *c <= '9')
8274 limit = *c - '0';
8275 else if (*c >= 'a' && *c <= 'f')
8276 limit = *c - 'a' + 10;
8277 else
8278 abort ();
8279 low = limit >> 2;
8280 high = limit & 3;
8281
8282 if (value < low || value > high)
8283 func (stream, "<illegal width %d>", base << value);
8284 else
8285 func (stream, "%d", base << value);
8286 }
8287 break;
8288 case 'R':
8289 if (given & (1 << 6))
8290 goto Q;
8291 /* FALLTHROUGH */
8292 case 'D':
8293 func (stream, "d%ld", value);
8294 break;
8295 case 'Q':
8296 Q:
8297 if (value & 1)
8298 func (stream, "<illegal reg q%ld.5>", value >> 1);
8299 else
8300 func (stream, "q%ld", value >> 1);
8301 break;
43e65147 8302
16980d0b
JB		 8303 case '`':
8304 c++;
8305 if (value == 0)
8306 func (stream, "%c", *c);
8307 break;
8308 case '\'':
8309 c++;
8310 if (value == ((1ul << width) - 1))
8311 func (stream, "%c", *c);
8312 break;
8313 case '?':
fe56b6ce 8314 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 8315 c += 1 << width;
8316 break;
8317 default:
8318 abort ();
8319 }
16980d0b 8320 }
dffaa15c
AM		 8321 break;
8322
8323 default:
8324 abort ();
16980d0b
JB		 8325 }
8326 }
8327 else
8328 func (stream, "%c", *c);
8329 }
05413229
NC		 8330
8331 if (value_in_comment > 32 || value_in_comment < -16)
8332 func (stream, "\t; 0x%lx", value_in_comment);
8333
e2efe87d
MGD		 8334 if (is_unpredictable)
8335 func (stream, UNPREDICTABLE_INSTRUCTION);
8336
16980d0b
JB		 8337 return TRUE;
8338 }
8339 }
8340 return FALSE;
8341}
8342
73cd51e5
AV		 8343/* Print one mve instruction on INFO->STREAM.
8344 Return TRUE if the instuction matched, FALSE if this is not a
8345 recognised mve instruction. */
8346
8347static bfd_boolean
8348print_insn_mve (struct disassemble_info *info, long given)
8349{
8350 const struct mopcode32 *insn;
8351 void *stream = info->stream;
8352 fprintf_ftype func = info->fprintf_func;
8353
8354 for (insn = mve_opcodes; insn->assembler; insn++)
8355 {
8356 if (((given & insn->mask) == insn->value)
8357 && !is_mve_encoding_conflict (given, insn->mve_op))
8358 {
8359 signed long value_in_comment = 0;
8360 bfd_boolean is_unpredictable = FALSE;
8361 bfd_boolean is_undefined = FALSE;
8362 const char *c;
8363 enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
8364 enum mve_undefined undefined_cond = UNDEF_NONE;
8365
8366 /* Most vector mve instruction are illegal in a it block.
8367 There are a few exceptions; check for them. */
8368 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
8369 {
8370 is_unpredictable = TRUE;
8371 unpredictable_cond = UNPRED_IT_BLOCK;
8372 }
8373 else if (is_mve_unpredictable (given, insn->mve_op,
8374 &unpredictable_cond))
8375 is_unpredictable = TRUE;
8376
8377 if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
8378 is_undefined = TRUE;
8379
8380 for (c = insn->assembler; *c; c++)
8381 {
8382 if (*c == '%')
8383 {
8384 switch (*++c)
8385 {
8386 case '%':
8387 func (stream, "%%");
8388 break;
8389
ef1576a1
AV		 8390 case 'a':
8391 /* Don't print anything for '+' as it is implied. */
8392 if (arm_decode_field (given, 23, 23) == 0)
8393 func (stream, "-");
8394 break;
8395
143275ea
AV		 8396 case 'c':
8397 if (ifthen_state)
8398 func (stream, "%s", arm_conditional[IFTHEN_COND]);
8399 break;
8400
aef6d006
AV		 8401 case 'd':
8402 print_mve_vld_str_addr (info, given, insn->mve_op);
8403 break;
8404
143275ea
AV		 8405 case 'i':
8406 {
8407 long mve_mask = mve_extract_pred_mask (given);
8408 func (stream, "%s", mve_predicatenames[mve_mask]);
8409 }
8410 break;
8411
8412 case 'n':
8413 print_vec_condition (info, given, insn->mve_op);
8414 break;
8415
ef1576a1
AV		 8416 case 'o':
8417 if (arm_decode_field (given, 0, 0) == 1)
8418 {
8419 unsigned long size
8420 = arm_decode_field (given, 4, 4)
8421 | (arm_decode_field (given, 6, 6) << 1);
8422
8423 func (stream, ", uxtw #%lu", size);
8424 }
8425 break;
8426
bf0b396d
AV		 8427 case 'm':
8428 print_mve_rounding_mode (info, given, insn->mve_op);
8429 break;
8430
8431 case 's':
8432 print_mve_vcvt_size (info, given, insn->mve_op);
8433 break;
8434
aef6d006
AV		 8435 case 'u':
8436 {
c507f10b
AV		 8437 unsigned long op1 = arm_decode_field (given, 21, 22);
8438
8439 if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
8440 {
8441 /* Check for signed. */
8442 if (arm_decode_field (given, 23, 23) == 0)
8443 {
8444 /* We don't print 's' for S32. */
8445 if ((arm_decode_field (given, 5, 6) == 0)
8446 && ((op1 == 0) || (op1 == 1)))
8447 ;
8448 else
8449 func (stream, "s");
8450 }
8451 else
8452 func (stream, "u");
8453 }
aef6d006 8454 else
c507f10b
AV		 8455 {
8456 if (arm_decode_field (given, 28, 28) == 0)
8457 func (stream, "s");
8458 else
8459 func (stream, "u");
8460 }
aef6d006 8461 }
ef1576a1 8462 break;
aef6d006 8463
143275ea
AV		 8464 case 'v':
8465 print_instruction_predicate (info);
8466 break;
8467
04d54ace
AV		 8468 case 'w':
8469 if (arm_decode_field (given, 21, 21) == 1)
8470 func (stream, "!");
8471 break;
8472
8473 case 'B':
8474 print_mve_register_blocks (info, given, insn->mve_op);
8475 break;
8476
c507f10b
AV		 8477 case 'E':
8478 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
8479
8480 print_simd_imm8 (info, given, 28, insn);
8481 break;
8482
8483 case 'N':
8484 print_mve_vmov_index (info, given);
8485 break;
8486
14925797
AV		 8487 case 'T':
8488 if (arm_decode_field (given, 12, 12) == 0)
8489 func (stream, "b");
8490 else
8491 func (stream, "t");
8492 break;
8493
d3b63143
AV		 8494 case 'X':
8495 if (arm_decode_field (given, 12, 12) == 1)
8496 func (stream, "x");
8497 break;
8498
143275ea
AV		 8499 case '0': case '1': case '2': case '3': case '4':
8500 case '5': case '6': case '7': case '8': case '9':
8501 {
8502 int width;
8503 unsigned long value;
8504
8505 c = arm_decode_bitfield (c, given, &value, &width);
8506
8507 switch (*c)
8508 {
8509 case 'Z':
8510 if (value == 13)
8511 is_unpredictable = TRUE;
8512 else if (value == 15)
8513 func (stream, "zr");
8514 else
8515 func (stream, "%s", arm_regnames[value]);
8516 break;
8517 case 's':
8518 print_mve_size (info,
8519 value,
8520 insn->mve_op);
8521 break;
d3b63143
AV		 8522 case 'A':
8523 if (value == 1)
8524 func (stream, "a");
8525 break;
1c8f2df8
AV		 8526 case 'h':
8527 {
8528 unsigned int odd_reg = (value << 1) | 1;
8529 func (stream, "%s", arm_regnames[odd_reg]);
8530 }
8531 break;
ef1576a1
AV		 8532 case 'i':
8533 {
8534 unsigned long imm
8535 = arm_decode_field (given, 0, 6);
8536 unsigned long mod_imm = imm;
8537
8538 switch (insn->mve_op)
8539 {
8540 case MVE_VLDRW_GATHER_T5:
8541 case MVE_VSTRW_SCATTER_T5:
8542 mod_imm = mod_imm << 2;
8543 break;
8544 case MVE_VSTRD_SCATTER_T6:
8545 case MVE_VLDRD_GATHER_T6:
8546 mod_imm = mod_imm << 3;
8547 break;
8548
8549 default:
8550 break;
8551 }
8552
8553 func (stream, "%lu", mod_imm);
8554 }
8555 break;
bf0b396d
AV		 8556 case 'k':
8557 func (stream, "%lu", 64 - value);
8558 break;
1c8f2df8
AV		 8559 case 'l':
8560 {
8561 unsigned int even_reg = value << 1;
8562 func (stream, "%s", arm_regnames[even_reg]);
8563 }
8564 break;
8565 case 'u':
8566 switch (value)
8567 {
8568 case 0:
8569 func (stream, "1");
8570 break;
8571 case 1:
8572 func (stream, "2");
8573 break;
8574 case 2:
8575 func (stream, "4");
8576 break;
8577 case 3:
8578 func (stream, "8");
8579 break;
8580 default:
8581 break;
8582 }
8583 break;
897b9bbc
AV		 8584 case 'o':
8585 print_mve_rotate (info, value, width);
8586 break;
9743db03
AV		 8587 case 'r':
8588 func (stream, "%s", arm_regnames[value]);
8589 break;
04d54ace 8590 case 'd':
ed63aa17
AV		 8591 if (insn->mve_op == MVE_VQSHL_T2
8592 || insn->mve_op == MVE_VQSHLU_T3
8593 || insn->mve_op == MVE_VRSHR
8594 || insn->mve_op == MVE_VRSHRN
8595 || insn->mve_op == MVE_VSHL_T1
8596 || insn->mve_op == MVE_VSHLL_T1
8597 || insn->mve_op == MVE_VSHR
8598 || insn->mve_op == MVE_VSHRN
8599 || insn->mve_op == MVE_VSLI
8600 || insn->mve_op == MVE_VSRI)
8601 print_mve_shift_n (info, given, insn->mve_op);
8602 else if (insn->mve_op == MVE_VSHLL_T2)
8603 {
8604 switch (value)
8605 {
8606 case 0x00:
8607 func (stream, "8");
8608 break;
8609 case 0x01:
8610 func (stream, "16");
8611 break;
8612 case 0x10:
8613 print_mve_undefined (info, UNDEF_SIZE_0);
8614 break;
8615 default:
8616 assert (0);
8617 break;
8618 }
8619 }
8620 else
8621 {
8622 if (insn->mve_op == MVE_VSHLC && value == 0)
8623 value = 32;
8624 func (stream, "%ld", value);
8625 value_in_comment = value;
8626 }
04d54ace 8627 break;
c507f10b
AV		 8628 case 'F':
8629 func (stream, "s%ld", value);
8630 break;
143275ea
AV		 8631 case 'Q':
8632 if (value & 0x8)
8633 func (stream, "<illegal reg q%ld.5>", value);
8634 else
8635 func (stream, "q%ld", value);
8636 break;
c507f10b
AV		 8637 case 'x':
8638 func (stream, "0x%08lx", value);
8639 break;
143275ea
AV		 8640 default:
8641 abort ();
8642 }
8643 break;
8644 default:
8645 abort ();
8646 }
73cd51e5
AV		 8647 }
8648 }
8649 else
8650 func (stream, "%c", *c);
8651 }
8652
8653 if (value_in_comment > 32 || value_in_comment < -16)
8654 func (stream, "\t; 0x%lx", value_in_comment);
8655
8656 if (is_unpredictable)
8657 print_mve_unpredictable (info, unpredictable_cond);
8658
8659 if (is_undefined)
8660 print_mve_undefined (info, undefined_cond);
8661
143275ea
AV		 8662 if ((vpt_block_state.in_vpt_block == FALSE)
8663 && !ifthen_state
8664 && (is_vpt_instruction (given) == TRUE))
8665 mark_inside_vpt_block (given);
8666 else if (vpt_block_state.in_vpt_block == TRUE)
8667 update_vpt_block_state ();
8668
73cd51e5
AV		 8669 return TRUE;
8670 }
8671 }
8672 return FALSE;
8673}
8674
8675
90ec0d68
MGD		 8676/* Return the name of a v7A special register. */
8677
43e65147 8678static const char *
90ec0d68
MGD		 8679banked_regname (unsigned reg)
8680{
8681 switch (reg)
8682 {
8683 case 15: return "CPSR";
43e65147 8684 case 32: return "R8_usr";
90ec0d68
MGD		 8685 case 33: return "R9_usr";
8686 case 34: return "R10_usr";
8687 case 35: return "R11_usr";
8688 case 36: return "R12_usr";
8689 case 37: return "SP_usr";
8690 case 38: return "LR_usr";
43e65147 8691 case 40: return "R8_fiq";
90ec0d68
MGD		 8692 case 41: return "R9_fiq";
8693 case 42: return "R10_fiq";
8694 case 43: return "R11_fiq";
8695 case 44: return "R12_fiq";
8696 case 45: return "SP_fiq";
8697 case 46: return "LR_fiq";
8698 case 48: return "LR_irq";
8699 case 49: return "SP_irq";
8700 case 50: return "LR_svc";
8701 case 51: return "SP_svc";
8702 case 52: return "LR_abt";
8703 case 53: return "SP_abt";
8704 case 54: return "LR_und";
8705 case 55: return "SP_und";
8706 case 60: return "LR_mon";
8707 case 61: return "SP_mon";
8708 case 62: return "ELR_hyp";
8709 case 63: return "SP_hyp";
8710 case 79: return "SPSR";
8711 case 110: return "SPSR_fiq";
8712 case 112: return "SPSR_irq";
8713 case 114: return "SPSR_svc";
8714 case 116: return "SPSR_abt";
8715 case 118: return "SPSR_und";
8716 case 124: return "SPSR_mon";
8717 case 126: return "SPSR_hyp";
8718 default: return NULL;
8719 }
8720}
8721
e797f7e0
MGD		 8722/* Return the name of the DMB/DSB option. */
8723static const char *
8724data_barrier_option (unsigned option)
8725{
8726 switch (option & 0xf)
8727 {
8728 case 0xf: return "sy";
8729 case 0xe: return "st";
8730 case 0xd: return "ld";
8731 case 0xb: return "ish";
8732 case 0xa: return "ishst";
8733 case 0x9: return "ishld";
8734 case 0x7: return "un";
8735 case 0x6: return "unst";
8736 case 0x5: return "nshld";
8737 case 0x3: return "osh";
8738 case 0x2: return "oshst";
8739 case 0x1: return "oshld";
8740 default: return NULL;
8741 }
8742}
8743
4a5329c6
ZW		 8744/* Print one ARM instruction from PC on INFO->STREAM. */
8745
8746static void
8747print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 8748{
6b5d3a4d 8749 const struct opcode32 *insn;
6a51a8a8 8750 void *stream = info->stream;
6b5d3a4d 8751 fprintf_ftype func = info->fprintf_func;
b0e28b39 8752 struct arm_private_data *private_data = info->private_data;
252b5132 8753
16980d0b
JB		 8754 if (print_insn_coprocessor (pc, info, given, FALSE))
8755 return;
8756
8757 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 8758 return;
8759
252b5132
RH		 8760 for (insn = arm_opcodes; insn->assembler; insn++)
8761 {
0313a2b8
NC		 8762 if ((given & insn->mask) != insn->value)
8763 continue;
823d2571
TG		 8764
8765 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 8766 continue;
8767
8768 /* Special case: an instruction with all bits set in the condition field
8769 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
8770 or by the catchall at the end of the table. */
8771 if ((given & 0xF0000000) != 0xF0000000
8772 || (insn->mask & 0xF0000000) == 0xF0000000
8773 || (insn->mask == 0 && insn->value == 0))
252b5132 8774 {
ff4a8d2b
NC		 8775 unsigned long u_reg = 16;
8776 unsigned long U_reg = 16;
ab8e2090 8777 bfd_boolean is_unpredictable = FALSE;
05413229 8778 signed long value_in_comment = 0;
6b5d3a4d 8779 const char *c;
b34976b6 8780
252b5132
RH		 8781 for (c = insn->assembler; *c; c++)
8782 {
8783 if (*c == '%')
8784 {
c1e26897
NC		 8785 bfd_boolean allow_unpredictable = FALSE;
8786
252b5132
RH		 8787 switch (*++c)
8788 {
8789 case '%':
8790 func (stream, "%%");
8791 break;
8792
8793 case 'a':
05413229 8794 value_in_comment = print_arm_address (pc, info, given);
62b3e311 8795 break;
252b5132 8796
62b3e311
PB		 8797 case 'P':
8798 /* Set P address bit and use normal address
8799 printing routine. */
c1e26897 8800 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 8801 break;
8802
c1e26897
NC		 8803 case 'S':
8804 allow_unpredictable = TRUE;
1a0670f3 8805 /* Fall through. */
252b5132
RH		 8806 case 's':
8807 if ((given & 0x004f0000) == 0x004f0000)
8808 {
58efb6c0 8809 /* PC relative with immediate offset. */
f8b960bc 8810 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 8811
aefd8a40
NC		 8812 if (PRE_BIT_SET)
8813 {
26d97720
NS		 8814 /* Elide positive zero offset. */
8815 if (offset || NEGATIVE_BIT_SET)
8816 func (stream, "[pc, #%s%d]\t; ",
d908c8af 8817 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 8818 else
26d97720
NS		 8819 func (stream, "[pc]\t; ");
8820 if (NEGATIVE_BIT_SET)
8821 offset = -offset;
aefd8a40
NC		 8822 info->print_address_func (offset + pc + 8, info);
8823 }
8824 else
8825 {
26d97720
NS		 8826 /* Always show the offset. */
8827 func (stream, "[pc], #%s%d",
d908c8af 8828 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 8829 if (! allow_unpredictable)
8830 is_unpredictable = TRUE;
aefd8a40 8831 }
252b5132
RH		 8832 }
8833 else
8834 {
fe56b6ce
NC		 8835 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
8836
b34976b6 8837 func (stream, "[%s",
252b5132 8838 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 8839
c1e26897 8840 if (PRE_BIT_SET)
252b5132 8841 {
c1e26897 8842 if (IMMEDIATE_BIT_SET)
252b5132 8843 {
26d97720
NS		 8844 /* Elide offset for non-writeback
8845 positive zero. */
8846 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
8847 || offset)
8848 func (stream, ", #%s%d",
8849 NEGATIVE_BIT_SET ? "-" : "", offset);
8850
8851 if (NEGATIVE_BIT_SET)
8852 offset = -offset;
945ee430 8853
fe56b6ce 8854 value_in_comment = offset;
252b5132 8855 }
945ee430 8856 else
ff4a8d2b
NC		 8857 {
8858 /* Register Offset or Register Pre-Indexed. */
8859 func (stream, ", %s%s",
8860 NEGATIVE_BIT_SET ? "-" : "",
8861 arm_regnames[given & 0xf]);
8862
8863 /* Writing back to the register that is the source/
8864 destination of the load/store is unpredictable. */
8865 if (! allow_unpredictable
8866 && WRITEBACK_BIT_SET
8867 && ((given & 0xf) == ((given >> 12) & 0xf)))
8868 is_unpredictable = TRUE;
8869 }
252b5132 8870
b34976b6 8871 func (stream, "]%s",
c1e26897 8872 WRITEBACK_BIT_SET ? "!" : "");
252b5132 8873 }
945ee430 8874 else
252b5132 8875 {
c1e26897 8876 if (IMMEDIATE_BIT_SET)
252b5132 8877 {
945ee430 8878 /* Immediate Post-indexed. */
aefd8a40 8879 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 8880 func (stream, "], #%s%d",
8881 NEGATIVE_BIT_SET ? "-" : "", offset);
8882 if (NEGATIVE_BIT_SET)
8883 offset = -offset;
fe56b6ce 8884 value_in_comment = offset;
252b5132 8885 }
945ee430 8886 else
ff4a8d2b
NC		 8887 {
8888 /* Register Post-indexed. */
8889 func (stream, "], %s%s",
8890 NEGATIVE_BIT_SET ? "-" : "",
8891 arm_regnames[given & 0xf]);
8892
8893 /* Writing back to the register that is the source/
8894 destination of the load/store is unpredictable. */
8895 if (! allow_unpredictable
8896 && (given & 0xf) == ((given >> 12) & 0xf))
8897 is_unpredictable = TRUE;
8898 }
c1e26897 8899
07a28fab
NC		 8900 if (! allow_unpredictable)
8901 {
8902 /* Writeback is automatically implied by post- addressing.
8903 Setting the W bit is unnecessary and ARM specify it as
8904 being unpredictable. */
8905 if (WRITEBACK_BIT_SET
8906 /* Specifying the PC register as the post-indexed
8907 registers is also unpredictable. */
ab8e2090
NC		 8908 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
8909 is_unpredictable = TRUE;
07a28fab 8910 }
252b5132
RH		 8911 }
8912 }
8913 break;
b34976b6 8914
252b5132 8915 case 'b':
6b5d3a4d 8916 {
f8b960bc 8917 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
05413229 8918 info->print_address_func (disp * 4 + pc + 8, info);
6b5d3a4d 8919 }
252b5132
RH		 8920 break;
8921
8922 case 'c':
c22aaad1
PB		 8923 if (((given >> 28) & 0xf) != 0xe)
8924 func (stream, "%s",
8925 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 8926 break;
8927
8928 case 'm':
8929 {
8930 int started = 0;
8931 int reg;
8932
8933 func (stream, "{");
8934 for (reg = 0; reg < 16; reg++)
8935 if ((given & (1 << reg)) != 0)
8936 {
8937 if (started)
8938 func (stream, ", ");
8939 started = 1;
8940 func (stream, "%s", arm_regnames[reg]);
8941 }
8942 func (stream, "}");
ab8e2090
NC		 8943 if (! started)
8944 is_unpredictable = TRUE;
252b5132
RH		 8945 }
8946 break;
8947
37b37b2d 8948 case 'q':
78c66db8 8949 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 8950 break;
8951
252b5132
RH		 8952 case 'o':
8953 if ((given & 0x02000000) != 0)
8954 {
a415b1cd
JB		 8955 unsigned int rotate = (given & 0xf00) >> 7;
8956 unsigned int immed = (given & 0xff);
8957 unsigned int a, i;
8958
8959 a = (((immed << (32 - rotate))
8960 | (immed >> rotate)) & 0xffffffff);
8961 /* If there is another encoding with smaller rotate,
8962 the rotate should be specified directly. */
8963 for (i = 0; i < 32; i += 2)
8964 if ((a << i | a >> (32 - i)) <= 0xff)
8965 break;
8966
8967 if (i != rotate)
8968 func (stream, "#%d, %d", immed, rotate);
8969 else
8970 func (stream, "#%d", a);
8971 value_in_comment = a;
252b5132
RH		 8972 }
8973 else
78c66db8 8974 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 8975 break;
8976
8977 case 'p':
8978 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 8979 {
823d2571
TG		 8980 arm_feature_set arm_ext_v6 =
8981 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
8982
aefd8a40
NC		 8983 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
8984 mechanism for setting PSR flag bits. They are
8985 obsolete in V6 onwards. */
823d2571
TG		 8986 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
8987 arm_ext_v6))
aefd8a40 8988 func (stream, "p");
4ab90a7a
AV		 8989 else
8990 is_unpredictable = TRUE;
aefd8a40 8991 }
252b5132
RH		 8992 break;
8993
8994 case 't':
8995 if ((given & 0x01200000) == 0x00200000)
8996 func (stream, "t");
8997 break;
8998
252b5132 8999 case 'A':
05413229
NC		 9000 {
9001 int offset = given & 0xff;
f02232aa 9002
05413229 9003 value_in_comment = offset * 4;
c1e26897 9004 if (NEGATIVE_BIT_SET)
05413229 9005 value_in_comment = - value_in_comment;
f02232aa 9006
05413229 9007 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 9008
c1e26897 9009 if (PRE_BIT_SET)
05413229
NC		 9010 {
9011 if (offset)
fe56b6ce 9012 func (stream, ", #%d]%s",
d908c8af 9013 (int) value_in_comment,
c1e26897 9014 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 9015 else
9016 func (stream, "]");
9017 }
9018 else
9019 {
9020 func (stream, "]");
f02232aa 9021
c1e26897 9022 if (WRITEBACK_BIT_SET)
05413229
NC		 9023 {
9024 if (offset)
d908c8af 9025 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 9026 }
9027 else
fe56b6ce 9028 {
d908c8af 9029 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 9030 value_in_comment = offset;
9031 }
05413229
NC		 9032 }
9033 }
252b5132
RH		 9034 break;
9035
077b8428
NC		 9036 case 'B':
9037 /* Print ARM V5 BLX(1) address: pc+25 bits. */
9038 {
9039 bfd_vma address;
9040 bfd_vma offset = 0;
b34976b6 9041
c1e26897 9042 if (! NEGATIVE_BIT_SET)
077b8428
NC		 9043 /* Is signed, hi bits should be ones. */
9044 offset = (-1) ^ 0x00ffffff;
9045
9046 /* Offset is (SignExtend(offset field)<<2). */
9047 offset += given & 0x00ffffff;
9048 offset <<= 2;
9049 address = offset + pc + 8;
b34976b6 9050
8f06b2d8
PB		 9051 if (given & 0x01000000)
9052 /* H bit allows addressing to 2-byte boundaries. */
9053 address += 2;
b1ee46c5 9054
8f06b2d8 9055 info->print_address_func (address, info);
b1ee46c5 9056 }
b1ee46c5
AH		 9057 break;
9058
252b5132 9059 case 'C':
90ec0d68
MGD		 9060 if ((given & 0x02000200) == 0x200)
9061 {
9062 const char * name;
9063 unsigned sysm = (given & 0x004f0000) >> 16;
9064
9065 sysm |= (given & 0x300) >> 4;
9066 name = banked_regname (sysm);
9067
9068 if (name != NULL)
9069 func (stream, "%s", name);
9070 else
d908c8af 9071 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 9072 }
9073 else
9074 {
43e65147 9075 func (stream, "%cPSR_",
90ec0d68
MGD		 9076 (given & 0x00400000) ? 'S' : 'C');
9077 if (given & 0x80000)
9078 func (stream, "f");
9079 if (given & 0x40000)
9080 func (stream, "s");
9081 if (given & 0x20000)
9082 func (stream, "x");
9083 if (given & 0x10000)
9084 func (stream, "c");
9085 }
252b5132
RH		 9086 break;
9087
62b3e311 9088 case 'U':
43e65147 9089 if ((given & 0xf0) == 0x60)
62b3e311 9090 {
52e7f43d
RE		 9091 switch (given & 0xf)
9092 {
9093 case 0xf: func (stream, "sy"); break;
9094 default:
9095 func (stream, "#%d", (int) given & 0xf);
9096 break;
9097 }
43e65147
L		 9098 }
9099 else
52e7f43d 9100 {
e797f7e0
MGD		 9101 const char * opt = data_barrier_option (given & 0xf);
9102 if (opt != NULL)
9103 func (stream, "%s", opt);
9104 else
52e7f43d 9105 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 9106 }
9107 break;
9108
b34976b6 9109 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 9110 case '5': case '6': case '7': case '8': case '9':
9111 {
16980d0b
JB		 9112 int width;
9113 unsigned long value;
252b5132 9114
16980d0b 9115 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 9116
252b5132
RH		 9117 switch (*c)
9118 {
ab8e2090
NC		 9119 case 'R':
9120 if (value == 15)
9121 is_unpredictable = TRUE;
9122 /* Fall through. */
16980d0b 9123 case 'r':
9eb6c0f1
MGD		 9124 case 'T':
9125 /* We want register + 1 when decoding T. */
9126 if (*c == 'T')
9127 ++value;
9128
ff4a8d2b
NC		 9129 if (c[1] == 'u')
9130 {
9131 /* Eat the 'u' character. */
9132 ++ c;
9133
9134 if (u_reg == value)
9135 is_unpredictable = TRUE;
9136 u_reg = value;
9137 }
9138 if (c[1] == 'U')
9139 {
9140 /* Eat the 'U' character. */
9141 ++ c;
9142
9143 if (U_reg == value)
9144 is_unpredictable = TRUE;
9145 U_reg = value;
9146 }
16980d0b
JB		 9147 func (stream, "%s", arm_regnames[value]);
9148 break;
9149 case 'd':
9150 func (stream, "%ld", value);
05413229 9151 value_in_comment = value;
16980d0b
JB		 9152 break;
9153 case 'b':
9154 func (stream, "%ld", value * 8);
05413229 9155 value_in_comment = value * 8;
16980d0b
JB		 9156 break;
9157 case 'W':
9158 func (stream, "%ld", value + 1);
05413229 9159 value_in_comment = value + 1;
16980d0b
JB		 9160 break;
9161 case 'x':
9162 func (stream, "0x%08lx", value);
9163
9164 /* Some SWI instructions have special
9165 meanings. */
9166 if ((given & 0x0fffffff) == 0x0FF00000)
9167 func (stream, "\t; IMB");
9168 else if ((given & 0x0fffffff) == 0x0FF00001)
9169 func (stream, "\t; IMBRange");
9170 break;
9171 case 'X':
9172 func (stream, "%01lx", value & 0xf);
05413229 9173 value_in_comment = value;
252b5132
RH		 9174 break;
9175 case '`':
9176 c++;
16980d0b 9177 if (value == 0)
252b5132
RH		 9178 func (stream, "%c", *c);
9179 break;
9180 case '\'':
9181 c++;
16980d0b 9182 if (value == ((1ul << width) - 1))
252b5132
RH		 9183 func (stream, "%c", *c);
9184 break;
9185 case '?':
fe56b6ce 9186 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 9187 c += 1 << width;
252b5132
RH		 9188 break;
9189 default:
9190 abort ();
9191 }
dffaa15c
AM		 9192 }
9193 break;
0dd132b6 9194
dffaa15c
AM		 9195 case 'e':
9196 {
9197 int imm;
0dd132b6 9198
dffaa15c
AM		 9199 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
9200 func (stream, "%d", imm);
9201 value_in_comment = imm;
9202 }
9203 break;
fe56b6ce 9204
dffaa15c
AM		 9205 case 'E':
9206 /* LSB and WIDTH fields of BFI or BFC. The machine-
9207 language instruction encodes LSB and MSB. */
9208 {
9209 long msb = (given & 0x001f0000) >> 16;
9210 long lsb = (given & 0x00000f80) >> 7;
9211 long w = msb - lsb + 1;
0a003adc 9212
dffaa15c
AM		 9213 if (w > 0)
9214 func (stream, "#%lu, #%lu", lsb, w);
9215 else
9216 func (stream, "(invalid: %lu:%lu)", lsb, msb);
9217 }
9218 break;
90ec0d68 9219
dffaa15c
AM		 9220 case 'R':
9221 /* Get the PSR/banked register name. */
9222 {
9223 const char * name;
9224 unsigned sysm = (given & 0x004f0000) >> 16;
90ec0d68 9225
dffaa15c
AM		 9226 sysm |= (given & 0x300) >> 4;
9227 name = banked_regname (sysm);
90ec0d68 9228
dffaa15c
AM		 9229 if (name != NULL)
9230 func (stream, "%s", name);
9231 else
9232 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
9233 }
9234 break;
fe56b6ce 9235
dffaa15c
AM		 9236 case 'V':
9237 /* 16-bit unsigned immediate from a MOVT or MOVW
9238 instruction, encoded in bits 0:11 and 15:19. */
9239 {
9240 long hi = (given & 0x000f0000) >> 4;
9241 long lo = (given & 0x00000fff);
9242 long imm16 = hi | lo;
0a003adc 9243
dffaa15c
AM		 9244 func (stream, "#%lu", imm16);
9245 value_in_comment = imm16;
252b5132 9246 }
dffaa15c
AM		 9247 break;
9248
9249 default:
9250 abort ();
252b5132
RH		 9251 }
9252 }
9253 else
9254 func (stream, "%c", *c);
9255 }
05413229
NC		 9256
9257 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 9258 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 9259
9260 if (is_unpredictable)
9261 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 9262
4a5329c6 9263 return;
252b5132
RH		 9264 }
9265 }
0b347048
TC		 9266 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
9267 return;
252b5132
RH		 9268}
9269
4a5329c6 9270/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 9271
4a5329c6
ZW		 9272static void
9273print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 9274{
6b5d3a4d 9275 const struct opcode16 *insn;
6a51a8a8
AM		 9276 void *stream = info->stream;
9277 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 9278
9279 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 9280 if ((given & insn->mask) == insn->value)
9281 {
05413229 9282 signed long value_in_comment = 0;
6b5d3a4d 9283 const char *c = insn->assembler;
05413229 9284
c19d1205
ZW		 9285 for (; *c; c++)
9286 {
9287 int domaskpc = 0;
9288 int domasklr = 0;
9289
9290 if (*c != '%')
9291 {
9292 func (stream, "%c", *c);
9293 continue;
9294 }
252b5132 9295
c19d1205
ZW		 9296 switch (*++c)
9297 {
9298 case '%':
9299 func (stream, "%%");
9300 break;
b34976b6 9301
c22aaad1
PB		 9302 case 'c':
9303 if (ifthen_state)
9304 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9305 break;
9306
9307 case 'C':
9308 if (ifthen_state)
9309 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9310 else
9311 func (stream, "s");
9312 break;
9313
9314 case 'I':
9315 {
9316 unsigned int tmp;
9317
9318 ifthen_next_state = given & 0xff;
9319 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
9320 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
9321 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
9322 }
9323 break;
9324
9325 case 'x':
9326 if (ifthen_next_state)
9327 func (stream, "\t; unpredictable branch in IT block\n");
9328 break;
9329
9330 case 'X':
9331 if (ifthen_state)
9332 func (stream, "\t; unpredictable <IT:%s>",
9333 arm_conditional[IFTHEN_COND]);
9334 break;
9335
c19d1205
ZW		 9336 case 'S':
9337 {
9338 long reg;
9339
9340 reg = (given >> 3) & 0x7;
9341 if (given & (1 << 6))
9342 reg += 8;
4f3c3dbb 9343
c19d1205
ZW		 9344 func (stream, "%s", arm_regnames[reg]);
9345 }
9346 break;
baf0cc5e 9347
c19d1205 9348 case 'D':
4f3c3dbb 9349 {
c19d1205
ZW		 9350 long reg;
9351
9352 reg = given & 0x7;
9353 if (given & (1 << 7))
9354 reg += 8;
9355
9356 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 9357 }
c19d1205
ZW		 9358 break;
9359
9360 case 'N':
9361 if (given & (1 << 8))
9362 domasklr = 1;
9363 /* Fall through. */
9364 case 'O':
9365 if (*c == 'O' && (given & (1 << 8)))
9366 domaskpc = 1;
9367 /* Fall through. */
9368 case 'M':
9369 {
9370 int started = 0;
9371 int reg;
9372
9373 func (stream, "{");
9374
9375 /* It would be nice if we could spot
9376 ranges, and generate the rS-rE format: */
9377 for (reg = 0; (reg < 8); reg++)
9378 if ((given & (1 << reg)) != 0)
9379 {
9380 if (started)
9381 func (stream, ", ");
9382 started = 1;
9383 func (stream, "%s", arm_regnames[reg]);
9384 }
9385
9386 if (domasklr)
9387 {
9388 if (started)
9389 func (stream, ", ");
9390 started = 1;
d908c8af 9391 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 9392 }
9393
9394 if (domaskpc)
9395 {
9396 if (started)
9397 func (stream, ", ");
d908c8af 9398 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 9399 }
9400
9401 func (stream, "}");
9402 }
9403 break;
9404
4547cb56
NC		 9405 case 'W':
9406 /* Print writeback indicator for a LDMIA. We are doing a
9407 writeback if the base register is not in the register
9408 mask. */
9409 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
9410 func (stream, "!");
dffaa15c 9411 break;
4547cb56 9412
c19d1205
ZW		 9413 case 'b':
9414 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
9415 {
9416 bfd_vma address = (pc + 4
9417 + ((given & 0x00f8) >> 2)
9418 + ((given & 0x0200) >> 3));
9419 info->print_address_func (address, info);
9420 }
9421 break;
9422
9423 case 's':
9424 /* Right shift immediate -- bits 6..10; 1-31 print
9425 as themselves, 0 prints as 32. */
9426 {
9427 long imm = (given & 0x07c0) >> 6;
9428 if (imm == 0)
9429 imm = 32;
0fd3a477 9430 func (stream, "#%ld", imm);
c19d1205
ZW		 9431 }
9432 break;
9433
9434 case '0': case '1': case '2': case '3': case '4':
9435 case '5': case '6': case '7': case '8': case '9':
9436 {
9437 int bitstart = *c++ - '0';
9438 int bitend = 0;
9439
9440 while (*c >= '0' && *c <= '9')
9441 bitstart = (bitstart * 10) + *c++ - '0';
9442
9443 switch (*c)
9444 {
9445 case '-':
9446 {
f8b960bc 9447 bfd_vma reg;
c19d1205
ZW		 9448
9449 c++;
9450 while (*c >= '0' && *c <= '9')
9451 bitend = (bitend * 10) + *c++ - '0';
9452 if (!bitend)
9453 abort ();
9454 reg = given >> bitstart;
9455 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 9456
c19d1205
ZW		 9457 switch (*c)
9458 {
9459 case 'r':
9460 func (stream, "%s", arm_regnames[reg]);
9461 break;
9462
9463 case 'd':
d908c8af 9464 func (stream, "%ld", (long) reg);
05413229 9465 value_in_comment = reg;
c19d1205
ZW		 9466 break;
9467
9468 case 'H':
d908c8af 9469 func (stream, "%ld", (long) (reg << 1));
05413229 9470 value_in_comment = reg << 1;
c19d1205
ZW		 9471 break;
9472
9473 case 'W':
d908c8af 9474 func (stream, "%ld", (long) (reg << 2));
05413229 9475 value_in_comment = reg << 2;
c19d1205
ZW		 9476 break;
9477
9478 case 'a':
9479 /* PC-relative address -- the bottom two
9480 bits of the address are dropped
9481 before the calculation. */
9482 info->print_address_func
9483 (((pc + 4) & ~3) + (reg << 2), info);
05413229 9484 value_in_comment = 0;
c19d1205
ZW		 9485 break;
9486
9487 case 'x':
d908c8af 9488 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 9489 break;
9490
c19d1205
ZW		 9491 case 'B':
9492 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6b5d3a4d 9493 info->print_address_func (reg * 2 + pc + 4, info);
05413229 9494 value_in_comment = 0;
c19d1205
ZW		 9495 break;
9496
9497 case 'c':
c22aaad1 9498 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 9499 break;
9500
9501 default:
9502 abort ();
9503 }
9504 }
9505 break;
9506
9507 case '\'':
9508 c++;
9509 if ((given & (1 << bitstart)) != 0)
9510 func (stream, "%c", *c);
9511 break;
9512
9513 case '?':
9514 ++c;
9515 if ((given & (1 << bitstart)) != 0)
9516 func (stream, "%c", *c++);
9517 else
9518 func (stream, "%c", *++c);
9519 break;
9520
9521 default:
9522 abort ();
9523 }
9524 }
9525 break;
9526
9527 default:
9528 abort ();
9529 }
9530 }
05413229
NC		 9531
9532 if (value_in_comment > 32 || value_in_comment < -16)
9533 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 9534 return;
c19d1205
ZW		 9535 }
9536
9537 /* No match. */
0b347048
TC		 9538 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
9539 return;
c19d1205
ZW		 9540}
9541
62b3e311 9542/* Return the name of an V7M special register. */
fe56b6ce 9543
62b3e311
PB		 9544static const char *
9545psr_name (int regno)
9546{
9547 switch (regno)
9548 {
1a336194
TP		 9549 case 0x0: return "APSR";
9550 case 0x1: return "IAPSR";
9551 case 0x2: return "EAPSR";
9552 case 0x3: return "PSR";
9553 case 0x5: return "IPSR";
9554 case 0x6: return "EPSR";
9555 case 0x7: return "IEPSR";
9556 case 0x8: return "MSP";
9557 case 0x9: return "PSP";
9558 case 0xa: return "MSPLIM";
9559 case 0xb: return "PSPLIM";
9560 case 0x10: return "PRIMASK";
9561 case 0x11: return "BASEPRI";
9562 case 0x12: return "BASEPRI_MAX";
9563 case 0x13: return "FAULTMASK";
9564 case 0x14: return "CONTROL";
16a1fa25
TP		 9565 case 0x88: return "MSP_NS";
9566 case 0x89: return "PSP_NS";
1a336194
TP		 9567 case 0x8a: return "MSPLIM_NS";
9568 case 0x8b: return "PSPLIM_NS";
9569 case 0x90: return "PRIMASK_NS";
9570 case 0x91: return "BASEPRI_NS";
9571 case 0x93: return "FAULTMASK_NS";
9572 case 0x94: return "CONTROL_NS";
9573 case 0x98: return "SP_NS";
62b3e311
PB		 9574 default: return "<unknown>";
9575 }
9576}
9577
4a5329c6
ZW		 9578/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
9579
9580static void
9581print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 9582{
6b5d3a4d 9583 const struct opcode32 *insn;
c19d1205
ZW		 9584 void *stream = info->stream;
9585 fprintf_ftype func = info->fprintf_func;
73cd51e5 9586 bfd_boolean is_mve = is_mve_architecture (info);
c19d1205 9587
16980d0b
JB		 9588 if (print_insn_coprocessor (pc, info, given, TRUE))
9589 return;
9590
73cd51e5
AV		 9591 if ((is_mve == FALSE) && print_insn_neon (info, given, TRUE))
9592 return;
9593
9594 if (is_mve && print_insn_mve (info, given))
8f06b2d8
PB		 9595 return;
9596
c19d1205
ZW		 9597 for (insn = thumb32_opcodes; insn->assembler; insn++)
9598 if ((given & insn->mask) == insn->value)
9599 {
4b5a202f 9600 bfd_boolean is_clrm = FALSE;
ff4a8d2b 9601 bfd_boolean is_unpredictable = FALSE;
05413229 9602 signed long value_in_comment = 0;
6b5d3a4d 9603 const char *c = insn->assembler;
05413229 9604
c19d1205
ZW		 9605 for (; *c; c++)
9606 {
9607 if (*c != '%')
9608 {
9609 func (stream, "%c", *c);
9610 continue;
9611 }
9612
9613 switch (*++c)
9614 {
9615 case '%':
9616 func (stream, "%%");
9617 break;
9618
c22aaad1
PB		 9619 case 'c':
9620 if (ifthen_state)
9621 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9622 break;
9623
9624 case 'x':
9625 if (ifthen_next_state)
9626 func (stream, "\t; unpredictable branch in IT block\n");
9627 break;
9628
9629 case 'X':
9630 if (ifthen_state)
9631 func (stream, "\t; unpredictable <IT:%s>",
9632 arm_conditional[IFTHEN_COND]);
9633 break;
9634
c19d1205
ZW		 9635 case 'I':
9636 {
9637 unsigned int imm12 = 0;
fe56b6ce 9638
c19d1205
ZW		 9639 imm12 |= (given & 0x000000ffu);
9640 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 9641 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 9642 func (stream, "#%u", imm12);
9643 value_in_comment = imm12;
c19d1205
ZW		 9644 }
9645 break;
9646
9647 case 'M':
9648 {
9649 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 9650
c19d1205
ZW		 9651 bits |= (given & 0x000000ffu);
9652 bits |= (given & 0x00007000u) >> 4;
9653 bits |= (given & 0x04000000u) >> 15;
9654 imm8 = (bits & 0x0ff);
9655 mod = (bits & 0xf00) >> 8;
9656 switch (mod)
9657 {
9658 case 0: imm = imm8; break;
c1e26897
NC		 9659 case 1: imm = ((imm8 << 16) | imm8); break;
9660 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
9661 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 9662 default:
9663 mod = (bits & 0xf80) >> 7;
9664 imm8 = (bits & 0x07f) | 0x80;
9665 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
9666 }
fe56b6ce
NC		 9667 func (stream, "#%u", imm);
9668 value_in_comment = imm;
c19d1205
ZW		 9669 }
9670 break;
43e65147 9671
c19d1205
ZW		 9672 case 'J':
9673 {
9674 unsigned int imm = 0;
fe56b6ce 9675
c19d1205
ZW		 9676 imm |= (given & 0x000000ffu);
9677 imm |= (given & 0x00007000u) >> 4;
9678 imm |= (given & 0x04000000u) >> 15;
9679 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 9680 func (stream, "#%u", imm);
9681 value_in_comment = imm;
c19d1205
ZW		 9682 }
9683 break;
9684
9685 case 'K':
9686 {
9687 unsigned int imm = 0;
fe56b6ce 9688
c19d1205
ZW		 9689 imm |= (given & 0x000f0000u) >> 16;
9690 imm |= (given & 0x00000ff0u) >> 0;
9691 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 9692 func (stream, "#%u", imm);
9693 value_in_comment = imm;
c19d1205
ZW		 9694 }
9695 break;
9696
74db7efb
NC		 9697 case 'H':
9698 {
9699 unsigned int imm = 0;
9700
9701 imm |= (given & 0x000f0000u) >> 4;
9702 imm |= (given & 0x00000fffu) >> 0;
9703 func (stream, "#%u", imm);
9704 value_in_comment = imm;
9705 }
9706 break;
9707
90ec0d68
MGD		 9708 case 'V':
9709 {
9710 unsigned int imm = 0;
9711
9712 imm |= (given & 0x00000fffu);
9713 imm |= (given & 0x000f0000u) >> 4;
9714 func (stream, "#%u", imm);
9715 value_in_comment = imm;
9716 }
9717 break;
9718
c19d1205
ZW		 9719 case 'S':
9720 {
9721 unsigned int reg = (given & 0x0000000fu);
9722 unsigned int stp = (given & 0x00000030u) >> 4;
9723 unsigned int imm = 0;
9724 imm |= (given & 0x000000c0u) >> 6;
9725 imm |= (given & 0x00007000u) >> 10;
9726
9727 func (stream, "%s", arm_regnames[reg]);
9728 switch (stp)
9729 {
9730 case 0:
9731 if (imm > 0)
9732 func (stream, ", lsl #%u", imm);
9733 break;
9734
9735 case 1:
9736 if (imm == 0)
9737 imm = 32;
9738 func (stream, ", lsr #%u", imm);
9739 break;
9740
9741 case 2:
9742 if (imm == 0)
9743 imm = 32;
9744 func (stream, ", asr #%u", imm);
9745 break;
9746
9747 case 3:
9748 if (imm == 0)
9749 func (stream, ", rrx");
9750 else
9751 func (stream, ", ror #%u", imm);
9752 }
9753 }
9754 break;
9755
9756 case 'a':
9757 {
9758 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 9759 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 9760 unsigned int op = (given & 0x00000f00) >> 8;
9761 unsigned int i12 = (given & 0x00000fff);
9762 unsigned int i8 = (given & 0x000000ff);
9763 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 9764 bfd_vma offset = 0;
c19d1205
ZW		 9765
9766 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 9767 if (U) /* 12-bit positive immediate offset. */
9768 {
9769 offset = i12;
9770 if (Rn != 15)
9771 value_in_comment = offset;
9772 }
9773 else if (Rn == 15) /* 12-bit negative immediate offset. */
9774 offset = - (int) i12;
9775 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 9776 {
9777 unsigned int Rm = (i8 & 0x0f);
9778 unsigned int sh = (i8 & 0x30) >> 4;
05413229 9779
c19d1205
ZW		 9780 func (stream, ", %s", arm_regnames[Rm]);
9781 if (sh)
9782 func (stream, ", lsl #%u", sh);
9783 func (stream, "]");
9784 break;
9785 }
9786 else switch (op)
9787 {
05413229 9788 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 9789 offset = i8;
9790 break;
9791
05413229 9792 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 9793 offset = -i8;
9794 break;
9795
05413229 9796 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 9797 offset = i8;
9798 writeback = TRUE;
9799 break;
9800
05413229 9801 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 9802 offset = -i8;
9803 writeback = TRUE;
9804 break;
9805
05413229 9806 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 9807 offset = i8;
9808 postind = TRUE;
9809 break;
9810
05413229 9811 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 9812 offset = -i8;
9813 postind = TRUE;
9814 break;
9815
9816 default:
9817 func (stream, ", <undefined>]");
9818 goto skip;
9819 }
9820
9821 if (postind)
d908c8af 9822 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 9823 else
9824 {
9825 if (offset)
d908c8af 9826 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 9827 func (stream, writeback ? "]!" : "]");
9828 }
9829
9830 if (Rn == 15)
9831 {
9832 func (stream, "\t; ");
9833 info->print_address_func (((pc + 4) & ~3) + offset, info);
9834 }
9835 }
9836 skip:
9837 break;
9838
9839 case 'A':
9840 {
c1e26897
NC		 9841 unsigned int U = ! NEGATIVE_BIT_SET;
9842 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 9843 unsigned int Rn = (given & 0x000f0000) >> 16;
9844 unsigned int off = (given & 0x000000ff);
9845
9846 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 9847
9848 if (PRE_BIT_SET)
c19d1205
ZW		 9849 {
9850 if (off || !U)
05413229
NC		 9851 {
9852 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
fe50e98c 9853 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 9854 }
c19d1205
ZW		 9855 func (stream, "]");
9856 if (W)
9857 func (stream, "!");
9858 }
9859 else
9860 {
9861 func (stream, "], ");
9862 if (W)
05413229
NC		 9863 {
9864 func (stream, "#%c%u", U ? '+' : '-', off * 4);
fe50e98c 9865 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 9866 }
c19d1205 9867 else
fe56b6ce
NC		 9868 {
9869 func (stream, "{%u}", off);
9870 value_in_comment = off;
9871 }
c19d1205
ZW		 9872 }
9873 }
9874 break;
9875
9876 case 'w':
9877 {
9878 unsigned int Sbit = (given & 0x01000000) >> 24;
9879 unsigned int type = (given & 0x00600000) >> 21;
05413229 9880
c19d1205
ZW		 9881 switch (type)
9882 {
9883 case 0: func (stream, Sbit ? "sb" : "b"); break;
9884 case 1: func (stream, Sbit ? "sh" : "h"); break;
9885 case 2:
9886 if (Sbit)
9887 func (stream, "??");
9888 break;
9889 case 3:
9890 func (stream, "??");
9891 break;
9892 }
9893 }
9894 break;
9895
4b5a202f
AV		 9896 case 'n':
9897 is_clrm = TRUE;
9898 /* Fall through. */
c19d1205
ZW		 9899 case 'm':
9900 {
9901 int started = 0;
9902 int reg;
9903
9904 func (stream, "{");
9905 for (reg = 0; reg < 16; reg++)
9906 if ((given & (1 << reg)) != 0)
9907 {
9908 if (started)
9909 func (stream, ", ");
9910 started = 1;
4b5a202f
AV		 9911 if (is_clrm && reg == 13)
9912 func (stream, "(invalid: %s)", arm_regnames[reg]);
9913 else if (is_clrm && reg == 15)
9914 func (stream, "%s", "APSR");
9915 else
9916 func (stream, "%s", arm_regnames[reg]);
c19d1205
ZW		 9917 }
9918 func (stream, "}");
9919 }
9920 break;
9921
9922 case 'E':
9923 {
9924 unsigned int msb = (given & 0x0000001f);
9925 unsigned int lsb = 0;
fe56b6ce 9926
c19d1205
ZW		 9927 lsb |= (given & 0x000000c0u) >> 6;
9928 lsb |= (given & 0x00007000u) >> 10;
9929 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
9930 }
9931 break;
9932
9933 case 'F':
9934 {
9935 unsigned int width = (given & 0x0000001f) + 1;
9936 unsigned int lsb = 0;
fe56b6ce 9937
c19d1205
ZW		 9938 lsb |= (given & 0x000000c0u) >> 6;
9939 lsb |= (given & 0x00007000u) >> 10;
9940 func (stream, "#%u, #%u", lsb, width);
9941 }
9942 break;
9943
e12437dc
AV		 9944 case 'G':
9945 {
9946 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
9947 func (stream, "%x", boff);
9948 }
9949 break;
9950
e5d6e09e
AV		 9951 case 'W':
9952 {
9953 unsigned int immA = (given & 0x001f0000u) >> 16;
9954 unsigned int immB = (given & 0x000007feu) >> 1;
9955 unsigned int immC = (given & 0x00000800u) >> 11;
9956 bfd_vma offset = 0;
9957
9958 offset |= immA << 12;
9959 offset |= immB << 2;
9960 offset |= immC << 1;
9961 /* Sign extend. */
9962 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
9963
9964 info->print_address_func (pc + 4 + offset, info);
9965 }
9966 break;
9967
1caf72a5
AV		 9968 case 'Y':
9969 {
9970 unsigned int immA = (given & 0x007f0000u) >> 16;
9971 unsigned int immB = (given & 0x000007feu) >> 1;
9972 unsigned int immC = (given & 0x00000800u) >> 11;
9973 bfd_vma offset = 0;
9974
9975 offset |= immA << 12;
9976 offset |= immB << 2;
9977 offset |= immC << 1;
9978 /* Sign extend. */
9979 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
9980
9981 info->print_address_func (pc + 4 + offset, info);
9982 }
9983 break;
9984
1889da70
AV		 9985 case 'Z':
9986 {
9987 unsigned int immA = (given & 0x00010000u) >> 16;
9988 unsigned int immB = (given & 0x000007feu) >> 1;
9989 unsigned int immC = (given & 0x00000800u) >> 11;
9990 bfd_vma offset = 0;
9991
9992 offset |= immA << 12;
9993 offset |= immB << 2;
9994 offset |= immC << 1;
9995 /* Sign extend. */
9996 offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
9997
9998 info->print_address_func (pc + 4 + offset, info);
f6b2b12d
AV		 9999
10000 unsigned int T = (given & 0x00020000u) >> 17;
10001 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
10002 unsigned int boffset = (T == 1) ? 4 : 2;
10003 func (stream, ", ");
10004 func (stream, "%x", endoffset + boffset);
1889da70
AV		 10005 }
10006 break;
10007
60f993ce
AV		 10008 case 'Q':
10009 {
10010 unsigned int immh = (given & 0x000007feu) >> 1;
10011 unsigned int imml = (given & 0x00000800u) >> 11;
10012 bfd_vma imm32 = 0;
10013
10014 imm32 |= immh << 2;
10015 imm32 |= imml << 1;
10016
10017 info->print_address_func (pc + 4 + imm32, info);
10018 }
10019 break;
10020
10021 case 'P':
10022 {
10023 unsigned int immh = (given & 0x000007feu) >> 1;
10024 unsigned int imml = (given & 0x00000800u) >> 11;
10025 bfd_vma imm32 = 0;
10026
10027 imm32 |= immh << 2;
10028 imm32 |= imml << 1;
10029
10030 info->print_address_func (pc + 4 - imm32, info);
10031 }
10032 break;
10033
c19d1205
ZW		 10034 case 'b':
10035 {
10036 unsigned int S = (given & 0x04000000u) >> 26;
10037 unsigned int J1 = (given & 0x00002000u) >> 13;
10038 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 10039 bfd_vma offset = 0;
c19d1205
ZW		 10040
10041 offset |= !S << 20;
10042 offset |= J2 << 19;
10043 offset |= J1 << 18;
10044 offset |= (given & 0x003f0000) >> 4;
10045 offset |= (given & 0x000007ff) << 1;
10046 offset -= (1 << 20);
10047
10048 info->print_address_func (pc + 4 + offset, info);
10049 }
10050 break;
10051
10052 case 'B':
10053 {
10054 unsigned int S = (given & 0x04000000u) >> 26;
10055 unsigned int I1 = (given & 0x00002000u) >> 13;
10056 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 10057 bfd_vma offset = 0;
c19d1205
ZW		 10058
10059 offset |= !S << 24;
10060 offset |= !(I1 ^ S) << 23;
10061 offset |= !(I2 ^ S) << 22;
10062 offset |= (given & 0x03ff0000u) >> 4;
10063 offset |= (given & 0x000007ffu) << 1;
10064 offset -= (1 << 24);
36b0c57d 10065 offset += pc + 4;
c19d1205 10066
36b0c57d
PB		 10067 /* BLX target addresses are always word aligned. */
10068 if ((given & 0x00001000u) == 0)
10069 offset &= ~2u;
10070
10071 info->print_address_func (offset, info);
c19d1205
ZW		 10072 }
10073 break;
10074
10075 case 's':
10076 {
10077 unsigned int shift = 0;
fe56b6ce 10078
c19d1205
ZW		 10079 shift |= (given & 0x000000c0u) >> 6;
10080 shift |= (given & 0x00007000u) >> 10;
c1e26897 10081 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 10082 func (stream, ", asr #%u", shift);
10083 else if (shift)
10084 func (stream, ", lsl #%u", shift);
10085 /* else print nothing - lsl #0 */
10086 }
10087 break;
10088
10089 case 'R':
10090 {
10091 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 10092
c19d1205
ZW		 10093 if (rot)
10094 func (stream, ", ror #%u", rot * 8);
10095 }
10096 break;
10097
62b3e311 10098 case 'U':
43e65147 10099 if ((given & 0xf0) == 0x60)
62b3e311 10100 {
52e7f43d
RE		 10101 switch (given & 0xf)
10102 {
10103 case 0xf: func (stream, "sy"); break;
10104 default:
10105 func (stream, "#%d", (int) given & 0xf);
10106 break;
10107 }
62b3e311 10108 }
43e65147 10109 else
52e7f43d 10110 {
e797f7e0
MGD		 10111 const char * opt = data_barrier_option (given & 0xf);
10112 if (opt != NULL)
10113 func (stream, "%s", opt);
10114 else
10115 func (stream, "#%d", (int) given & 0xf);
52e7f43d 10116 }
62b3e311
PB		 10117 break;
10118
10119 case 'C':
10120 if ((given & 0xff) == 0)
10121 {
10122 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
10123 if (given & 0x800)
10124 func (stream, "f");
10125 if (given & 0x400)
10126 func (stream, "s");
10127 if (given & 0x200)
10128 func (stream, "x");
10129 if (given & 0x100)
10130 func (stream, "c");
10131 }
90ec0d68
MGD		 10132 else if ((given & 0x20) == 0x20)
10133 {
10134 char const* name;
10135 unsigned sysm = (given & 0xf00) >> 8;
10136
10137 sysm |= (given & 0x30);
10138 sysm |= (given & 0x00100000) >> 14;
10139 name = banked_regname (sysm);
43e65147 10140
90ec0d68
MGD		 10141 if (name != NULL)
10142 func (stream, "%s", name);
10143 else
d908c8af 10144 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 10145 }
62b3e311
PB		 10146 else
10147 {
d908c8af 10148 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 10149 }
10150 break;
10151
10152 case 'D':
90ec0d68
MGD		 10153 if (((given & 0xff) == 0)
10154 || ((given & 0x20) == 0x20))
10155 {
10156 char const* name;
10157 unsigned sm = (given & 0xf0000) >> 16;
10158
10159 sm |= (given & 0x30);
10160 sm |= (given & 0x00100000) >> 14;
10161 name = banked_regname (sm);
10162
10163 if (name != NULL)
10164 func (stream, "%s", name);
10165 else
d908c8af 10166 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 10167 }
62b3e311 10168 else
d908c8af 10169 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 10170 break;
10171
c19d1205
ZW		 10172 case '0': case '1': case '2': case '3': case '4':
10173 case '5': case '6': case '7': case '8': case '9':
10174 {
16980d0b
JB		 10175 int width;
10176 unsigned long val;
c19d1205 10177
16980d0b 10178 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 10179
c19d1205
ZW		 10180 switch (*c)
10181 {
d052b9b7
AV		 10182 case 's':
10183 if (val <= 3)
10184 func (stream, "%s", mve_vec_sizename[val]);
10185 else
10186 func (stream, "<undef size>");
10187 break;
10188
05413229
NC		 10189 case 'd':
10190 func (stream, "%lu", val);
10191 value_in_comment = val;
10192 break;
ff4a8d2b 10193
f0fba320
RL		 10194 case 'D':
10195 func (stream, "%lu", val + 1);
10196 value_in_comment = val + 1;
10197 break;
10198
05413229
NC		 10199 case 'W':
10200 func (stream, "%lu", val * 4);
10201 value_in_comment = val * 4;
10202 break;
ff4a8d2b 10203
f1c7f421
AV		 10204 case 'S':
10205 if (val == 13)
10206 is_unpredictable = TRUE;
10207 /* Fall through. */
ff4a8d2b
NC		 10208 case 'R':
10209 if (val == 15)
10210 is_unpredictable = TRUE;
10211 /* Fall through. */
10212 case 'r':
10213 func (stream, "%s", arm_regnames[val]);
10214 break;
c19d1205
ZW		 10215
10216 case 'c':
c22aaad1 10217 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 10218 break;
10219
10220 case '\'':
c19d1205 10221 c++;
16980d0b
JB		 10222 if (val == ((1ul << width) - 1))
10223 func (stream, "%c", *c);
c19d1205 10224 break;
43e65147 10225
c19d1205 10226 case '`':
c19d1205 10227 c++;
16980d0b
JB		 10228 if (val == 0)
10229 func (stream, "%c", *c);
c19d1205
ZW		 10230 break;
10231
10232 case '?':
fe56b6ce 10233 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 10234 c += 1 << width;
c19d1205 10235 break;
43e65147 10236
0bb027fd
RR		 10237 case 'x':
10238 func (stream, "0x%lx", val & 0xffffffffUL);
10239 break;
c19d1205
ZW		 10240
10241 default:
10242 abort ();
10243 }
10244 }
10245 break;
10246
32a94698
NC		 10247 case 'L':
10248 /* PR binutils/12534
10249 If we have a PC relative offset in an LDRD or STRD
10250 instructions then display the decoded address. */
10251 if (((given >> 16) & 0xf) == 0xf)
10252 {
10253 bfd_vma offset = (given & 0xff) * 4;
10254
10255 if ((given & (1 << 23)) == 0)
10256 offset = - offset;
10257 func (stream, "\t; ");
10258 info->print_address_func ((pc & ~3) + 4 + offset, info);
10259 }
10260 break;
10261
c19d1205
ZW		 10262 default:
10263 abort ();
10264 }
10265 }
05413229
NC		 10266
10267 if (value_in_comment > 32 || value_in_comment < -16)
10268 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 10269
10270 if (is_unpredictable)
10271 func (stream, UNPREDICTABLE_INSTRUCTION);
10272
4a5329c6 10273 return;
c19d1205 10274 }
252b5132 10275
58efb6c0 10276 /* No match. */
0b347048
TC		 10277 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
10278 return;
252b5132
RH		 10279}
10280
e821645d
DJ		 10281/* Print data bytes on INFO->STREAM. */
10282
10283static void
fe56b6ce
NC		 10284print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
10285 struct disassemble_info *info,
e821645d
DJ		 10286 long given)
10287{
10288 switch (info->bytes_per_chunk)
10289 {
10290 case 1:
10291 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
10292 break;
10293 case 2:
10294 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
10295 break;
10296 case 4:
10297 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
10298 break;
10299 default:
10300 abort ();
10301 }
10302}
10303
22a398e1 10304/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 10305 being displayed in symbol relative addresses.
10306
10307 Also disallow private symbol, with __tagsym$$ prefix,
10308 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 10309
10310bfd_boolean
10311arm_symbol_is_valid (asymbol * sym,
10312 struct disassemble_info * info ATTRIBUTE_UNUSED)
10313{
10314 const char * name;
43e65147 10315
22a398e1
NC		 10316 if (sym == NULL)
10317 return FALSE;
10318
10319 name = bfd_asymbol_name (sym);
10320
d8282f0e 10321 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 10322}
10323
65b48a81 10324/* Parse the string of disassembler options. */
baf0cc5e 10325
65b48a81 10326static void
f995bbe8 10327parse_arm_disassembler_options (const char *options)
dd92f639 10328{
f995bbe8 10329 const char *opt;
b34976b6 10330
65b48a81 10331 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
dd92f639 10332 {
65b48a81
PB		 10333 if (CONST_STRNEQ (opt, "reg-names-"))
10334 {
10335 unsigned int i;
10336 for (i = 0; i < NUM_ARM_OPTIONS; i++)
10337 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
10338 {
10339 regname_selected = i;
10340 break;
10341 }
b34976b6 10342
65b48a81 10343 if (i >= NUM_ARM_OPTIONS)
a6743a54
AM		 10344 /* xgettext: c-format */
10345 opcodes_error_handler (_("unrecognised register name set: %s"),
10346 opt);
65b48a81
PB		 10347 }
10348 else if (CONST_STRNEQ (opt, "force-thumb"))
10349 force_thumb = 1;
10350 else if (CONST_STRNEQ (opt, "no-force-thumb"))
10351 force_thumb = 0;
10352 else
a6743a54
AM		 10353 /* xgettext: c-format */
10354 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
dd92f639 10355 }
b34976b6 10356
dd92f639
NC		 10357 return;
10358}
10359
5bc5ae88
RL		 10360static bfd_boolean
10361mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
10362 enum map_type *map_symbol);
10363
c22aaad1
PB		 10364/* Search back through the insn stream to determine if this instruction is
10365 conditionally executed. */
fe56b6ce 10366
c22aaad1 10367static void
fe56b6ce
NC		 10368find_ifthen_state (bfd_vma pc,
10369 struct disassemble_info *info,
c22aaad1
PB		 10370 bfd_boolean little)
10371{
10372 unsigned char b[2];
10373 unsigned int insn;
10374 int status;
10375 /* COUNT is twice the number of instructions seen. It will be odd if we
10376 just crossed an instruction boundary. */
10377 int count;
10378 int it_count;
10379 unsigned int seen_it;
10380 bfd_vma addr;
10381
10382 ifthen_address = pc;
10383 ifthen_state = 0;
10384
10385 addr = pc;
10386 count = 1;
10387 it_count = 0;
10388 seen_it = 0;
10389 /* Scan backwards looking for IT instructions, keeping track of where
10390 instruction boundaries are. We don't know if something is actually an
10391 IT instruction until we find a definite instruction boundary. */
10392 for (;;)
10393 {
fe56b6ce 10394 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 10395 {
10396 /* A symbol must be on an instruction boundary, and will not
10397 be within an IT block. */
10398 if (seen_it && (count & 1))
10399 break;
10400
10401 return;
10402 }
10403 addr -= 2;
fe56b6ce 10404 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 10405 if (status)
10406 return;
10407
10408 if (little)
10409 insn = (b[0]) | (b[1] << 8);
10410 else
10411 insn = (b[1]) | (b[0] << 8);
10412 if (seen_it)
10413 {
10414 if ((insn & 0xf800) < 0xe800)
10415 {
10416 /* Addr + 2 is an instruction boundary. See if this matches
10417 the expected boundary based on the position of the last
10418 IT candidate. */
10419 if (count & 1)
10420 break;
10421 seen_it = 0;
10422 }
10423 }
10424 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
10425 {
5bc5ae88
RL		 10426 enum map_type type = MAP_ARM;
10427 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
10428
10429 if (!found || (found && type == MAP_THUMB))
10430 {
10431 /* This could be an IT instruction. */
10432 seen_it = insn;
10433 it_count = count >> 1;
10434 }
c22aaad1
PB		 10435 }
10436 if ((insn & 0xf800) >= 0xe800)
10437 count++;
10438 else
10439 count = (count + 2) | 1;
10440 /* IT blocks contain at most 4 instructions. */
10441 if (count >= 8 && !seen_it)
10442 return;
10443 }
10444 /* We found an IT instruction. */
10445 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
10446 if ((ifthen_state & 0xf) == 0)
10447 ifthen_state = 0;
10448}
10449
b0e28b39
DJ		 10450/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
10451 mapping symbol. */
10452
10453static int
10454is_mapping_symbol (struct disassemble_info *info, int n,
10455 enum map_type *map_type)
10456{
10457 const char *name;
10458
10459 name = bfd_asymbol_name (info->symtab[n]);
10460 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
10461 && (name[2] == 0 || name[2] == '.'))
10462 {
10463 *map_type = ((name[1] == 'a') ? MAP_ARM
10464 : (name[1] == 't') ? MAP_THUMB
10465 : MAP_DATA);
10466 return TRUE;
10467 }
10468
10469 return FALSE;
10470}
10471
10472/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
10473 Returns nonzero if *MAP_TYPE was set. */
10474
10475static int
10476get_map_sym_type (struct disassemble_info *info,
10477 int n,
10478 enum map_type *map_type)
10479{
10480 /* If the symbol is in a different section, ignore it. */
10481 if (info->section != NULL && info->section != info->symtab[n]->section)
10482 return FALSE;
10483
10484 return is_mapping_symbol (info, n, map_type);
10485}
10486
10487/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 10488 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 10489
10490static int
fe56b6ce
NC		 10491get_sym_code_type (struct disassemble_info *info,
10492 int n,
e821645d 10493 enum map_type *map_type)
2087ad84
PB		 10494{
10495 elf_symbol_type *es;
10496 unsigned int type;
b0e28b39
DJ		 10497
10498 /* If the symbol is in a different section, ignore it. */
10499 if (info->section != NULL && info->section != info->symtab[n]->section)
10500 return FALSE;
2087ad84 10501
e821645d 10502 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 10503 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
10504
10505 /* If the symbol has function type then use that. */
34e77a92 10506 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 10507 {
39d911fc
TP		 10508 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
10509 == ST_BRANCH_TO_THUMB)
35fc36a8
RS		 10510 *map_type = MAP_THUMB;
10511 else
10512 *map_type = MAP_ARM;
2087ad84
PB		 10513 return TRUE;
10514 }
10515
2087ad84
PB		 10516 return FALSE;
10517}
10518
5bc5ae88
RL		 10519/* Search the mapping symbol state for instruction at pc. This is only
10520 applicable for elf target.
10521
10522 There is an assumption Here, info->private_data contains the correct AND
10523 up-to-date information about current scan process. The information will be
10524 used to speed this search process.
10525
10526 Return TRUE if the mapping state can be determined, and map_symbol
10527 will be updated accordingly. Otherwise, return FALSE. */
10528
10529static bfd_boolean
10530mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
10531 enum map_type *map_symbol)
10532{
796d6298
TC		 10533 bfd_vma addr, section_vma = 0;
10534 int n, last_sym = -1;
5bc5ae88 10535 bfd_boolean found = FALSE;
796d6298
TC		 10536 bfd_boolean can_use_search_opt_p = FALSE;
10537
10538 /* Default to DATA. A text section is required by the ABI to contain an
10539 INSN mapping symbol at the start. A data section has no such
10540 requirement, hence if no mapping symbol is found the section must
10541 contain only data. This however isn't very useful if the user has
10542 fully stripped the binaries. If this is the case use the section
10543 attributes to determine the default. If we have no section default to
10544 INSN as well, as we may be disassembling some raw bytes on a baremetal
10545 HEX file or similar. */
10546 enum map_type type = MAP_DATA;
10547 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
10548 type = MAP_ARM;
5bc5ae88
RL		 10549 struct arm_private_data *private_data;
10550
796d6298 10551 if (info->private_data == NULL
5bc5ae88
RL		 10552 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
10553 return FALSE;
10554
10555 private_data = info->private_data;
5bc5ae88 10556
796d6298
TC		 10557 /* First, look for mapping symbols. */
10558 if (info->symtab_size != 0)
10559 {
10560 if (pc <= private_data->last_mapping_addr)
10561 private_data->last_mapping_sym = -1;
10562
10563 /* Start scanning at the start of the function, or wherever
10564 we finished last time. */
10565 n = info->symtab_pos + 1;
10566
10567 /* If the last stop offset is different from the current one it means we
10568 are disassembling a different glob of bytes. As such the optimization
10569 would not be safe and we should start over. */
10570 can_use_search_opt_p
10571 = private_data->last_mapping_sym >= 0
10572 && info->stop_offset == private_data->last_stop_offset;
10573
10574 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
10575 n = private_data->last_mapping_sym;
10576
10577 /* Look down while we haven't passed the location being disassembled.
10578 The reason for this is that there's no defined order between a symbol
10579 and an mapping symbol that may be at the same address. We may have to
10580 look at least one position ahead. */
10581 for (; n < info->symtab_size; n++)
10582 {
10583 addr = bfd_asymbol_value (info->symtab[n]);
10584 if (addr > pc)
10585 break;
10586 if (get_map_sym_type (info, n, &type))
10587 {
10588 last_sym = n;
10589 found = TRUE;
10590 }
10591 }
5bc5ae88 10592
796d6298
TC		 10593 if (!found)
10594 {
10595 n = info->symtab_pos;
10596 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
10597 n = private_data->last_mapping_sym;
10598
10599 /* No mapping symbol found at this address. Look backwards
10600 for a preceeding one, but don't go pass the section start
10601 otherwise a data section with no mapping symbol can pick up
10602 a text mapping symbol of a preceeding section. The documentation
10603 says section can be NULL, in which case we will seek up all the
10604 way to the top. */
10605 if (info->section)
10606 section_vma = info->section->vma;
10607
10608 for (; n >= 0; n--)
10609 {
10610 addr = bfd_asymbol_value (info->symtab[n]);
10611 if (addr < section_vma)
10612 break;
10613
10614 if (get_map_sym_type (info, n, &type))
10615 {
10616 last_sym = n;
10617 found = TRUE;
10618 break;
10619 }
10620 }
10621 }
10622 }
10623
10624 /* If no mapping symbol was found, try looking up without a mapping
10625 symbol. This is done by walking up from the current PC to the nearest
10626 symbol. We don't actually have to loop here since symtab_pos will
10627 contain the nearest symbol already. */
10628 if (!found)
5bc5ae88 10629 {
796d6298
TC		 10630 n = info->symtab_pos;
10631 if (n >= 0 && get_sym_code_type (info, n, &type))
5bc5ae88 10632 {
796d6298
TC		 10633 last_sym = n;
10634 found = TRUE;
5bc5ae88
RL		 10635 }
10636 }
10637
796d6298
TC		 10638 private_data->last_mapping_sym = last_sym;
10639 private_data->last_type = type;
10640 private_data->last_stop_offset = info->stop_offset;
5bc5ae88
RL		 10641
10642 *map_symbol = type;
10643 return found;
10644}
10645
0313a2b8
NC		 10646/* Given a bfd_mach_arm_XXX value, this function fills in the fields
10647 of the supplied arm_feature_set structure with bitmasks indicating
c0c468d5 10648 the supported base architectures and coprocessor extensions.
0313a2b8
NC		 10649
10650 FIXME: This could more efficiently implemented as a constant array,
10651 although it would also be less robust. */
10652
10653static void
10654select_arm_features (unsigned long mach,
10655 arm_feature_set * features)
10656{
c0c468d5
TP		 10657 arm_feature_set arch_fset;
10658 const arm_feature_set fpu_any = FPU_ANY;
10659
1af1dd51
MW		 10660#undef ARM_SET_FEATURES
10661#define ARM_SET_FEATURES(FSET) \
10662 { \
10663 const arm_feature_set fset = FSET; \
c0c468d5 10664 arch_fset = fset; \
1af1dd51 10665 }
823d2571 10666
c0c468d5
TP		 10667 /* When several architecture versions share the same bfd_mach_arm_XXX value
10668 the most featureful is chosen. */
0313a2b8
NC		 10669 switch (mach)
10670 {
c0c468d5
TP		 10671 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
10672 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
10673 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
10674 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
10675 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
10676 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
10677 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
10678 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
10679 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
10680 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
1af1dd51 10681 case bfd_mach_arm_ep9312:
c0c468d5
TP		 10682 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
10683 ARM_CEXT_MAVERICK | FPU_MAVERICK));
1af1dd51 10684 break;
c0c468d5
TP		 10685 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
10686 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
10687 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
10688 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
10689 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
10690 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
10691 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
10692 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
10693 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
10694 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
10695 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
10696 case bfd_mach_arm_8:
10697 {
0632eeea
SD		 10698 /* Add bits for extensions that Armv8.5-A recognizes. */
10699 arm_feature_set armv8_5_ext_fset
10700 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
10701 ARM_SET_FEATURES (ARM_ARCH_V8_5A);
10702 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset);
c0c468d5
TP		 10703 break;
10704 }
10705 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
10706 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
10707 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
73cd51e5
AV		 10708 case bfd_mach_arm_8_1M_MAIN:
10709 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
10710 force_thumb = 1;
10711 break;
c0c468d5
TP		 10712 /* If the machine type is unknown allow all architecture types and all
10713 extensions. */
10714 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
0313a2b8
NC		 10715 default:
10716 abort ();
10717 }
1af1dd51 10718#undef ARM_SET_FEATURES
c0c468d5
TP		 10719
10720 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
10721 and thus on bfd_mach_arm_XXX value. Therefore for a given
10722 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
10723 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
0313a2b8
NC		 10724}
10725
10726
58efb6c0
NC		 10727/* NOTE: There are no checks in these routines that
10728 the relevant number of data bytes exist. */
baf0cc5e 10729
58efb6c0 10730static int
4a5329c6 10731print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 10732{
c19d1205
ZW		 10733 unsigned char b[4];
10734 long given;
10735 int status;
e821645d 10736 int is_thumb = FALSE;
b0e28b39 10737 int is_data = FALSE;
bd2e2557 10738 int little_code;
e821645d 10739 unsigned int size = 4;
4a5329c6 10740 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 10741 bfd_boolean found = FALSE;
b0e28b39 10742 struct arm_private_data *private_data;
58efb6c0 10743
dd92f639
NC		 10744 if (info->disassembler_options)
10745 {
65b48a81 10746 parse_arm_disassembler_options (info->disassembler_options);
b34976b6 10747
58efb6c0 10748 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 10749 info->disassembler_options = NULL;
10750 }
b34976b6 10751
0313a2b8
NC		 10752 /* PR 10288: Control which instructions will be disassembled. */
10753 if (info->private_data == NULL)
10754 {
b0e28b39 10755 static struct arm_private_data private;
0313a2b8
NC		 10756
10757 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
10758 /* If the user did not use the -m command line switch then default to
10759 disassembling all types of ARM instruction.
43e65147 10760
0313a2b8
NC		 10761 The info->mach value has to be ignored as this will be based on
10762 the default archictecture for the target and/or hints in the notes
10763 section, but it will never be greater than the current largest arm
10764 machine value (iWMMXt2), which is only equivalent to the V5TE
10765 architecture. ARM architectures have advanced beyond the machine
10766 value encoding, and these newer architectures would be ignored if
10767 the machine value was used.
10768
10769 Ie the -m switch is used to restrict which instructions will be
10770 disassembled. If it is necessary to use the -m switch to tell
10771 objdump that an ARM binary is being disassembled, eg because the
10772 input is a raw binary file, but it is also desired to disassemble
10773 all ARM instructions then use "-marm". This will select the
10774 "unknown" arm architecture which is compatible with any ARM
10775 instruction. */
10776 info->mach = bfd_mach_arm_unknown;
10777
10778 /* Compute the architecture bitmask from the machine number.
10779 Note: This assumes that the machine number will not change
10780 during disassembly.... */
b0e28b39 10781 select_arm_features (info->mach, & private.features);
0313a2b8 10782
1fbaefec
PB		 10783 private.last_mapping_sym = -1;
10784 private.last_mapping_addr = 0;
796d6298 10785 private.last_stop_offset = 0;
b0e28b39
DJ		 10786
10787 info->private_data = & private;
0313a2b8 10788 }
b0e28b39
DJ		 10789
10790 private_data = info->private_data;
10791
bd2e2557
SS		 10792 /* Decide if our code is going to be little-endian, despite what the
10793 function argument might say. */
10794 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
10795
b0e28b39
DJ		 10796 /* For ELF, consult the symbol table to determine what kind of code
10797 or data we have. */
8977d4b2 10798 if (info->symtab_size != 0
e821645d
DJ		 10799 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
10800 {
10801 bfd_vma addr;
796d6298 10802 int n;
e821645d 10803 int last_sym = -1;
b0e28b39 10804 enum map_type type = MAP_ARM;
e821645d 10805
796d6298
TC		 10806 found = mapping_symbol_for_insn (pc, info, &type);
10807 last_sym = private_data->last_mapping_sym;
e821645d 10808
1fbaefec
PB		 10809 is_thumb = (private_data->last_type == MAP_THUMB);
10810 is_data = (private_data->last_type == MAP_DATA);
b34976b6 10811
e821645d
DJ		 10812 /* Look a little bit ahead to see if we should print out
10813 two or four bytes of data. If there's a symbol,
10814 mapping or otherwise, after two bytes then don't
10815 print more. */
10816 if (is_data)
10817 {
10818 size = 4 - (pc & 3);
10819 for (n = last_sym + 1; n < info->symtab_size; n++)
10820 {
10821 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 10822 if (addr > pc
10823 && (info->section == NULL
10824 || info->section == info->symtab[n]->section))
e821645d
DJ		 10825 {
10826 if (addr - pc < size)
10827 size = addr - pc;
10828 break;
10829 }
10830 }
10831 /* If the next symbol is after three bytes, we need to
10832 print only part of the data, so that we can use either
10833 .byte or .short. */
10834 if (size == 3)
10835 size = (pc & 1) ? 1 : 2;
10836 }
10837 }
10838
10839 if (info->symbols != NULL)
252b5132 10840 {
5876e06d
NC		 10841 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
10842 {
2f0ca46a 10843 coff_symbol_type * cs;
b34976b6 10844
5876e06d
NC		 10845 cs = coffsymbol (*info->symbols);
10846 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
10847 || cs->native->u.syment.n_sclass == C_THUMBSTAT
10848 || cs->native->u.syment.n_sclass == C_THUMBLABEL
10849 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
10850 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
10851 }
e821645d
DJ		 10852 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
10853 && !found)
5876e06d 10854 {
2087ad84
PB		 10855 /* If no mapping symbol has been found then fall back to the type
10856 of the function symbol. */
e821645d
DJ		 10857 elf_symbol_type * es;
10858 unsigned int type;
2087ad84 10859
e821645d
DJ		 10860 es = *(elf_symbol_type **)(info->symbols);
10861 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 10862
39d911fc
TP		 10863 is_thumb =
10864 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
10865 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
5876e06d 10866 }
e49d43ff
TG		 10867 else if (bfd_asymbol_flavour (*info->symbols)
10868 == bfd_target_mach_o_flavour)
10869 {
10870 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
10871
10872 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
10873 }
5876e06d 10874 }
b34976b6 10875
e821645d
DJ		 10876 if (force_thumb)
10877 is_thumb = TRUE;
10878
b8f9ee44
CL		 10879 if (is_data)
10880 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
10881 else
10882 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
10883
c19d1205 10884 info->bytes_per_line = 4;
252b5132 10885
1316c8b3
NC		 10886 /* PR 10263: Disassemble data if requested to do so by the user. */
10887 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 10888 {
10889 int i;
10890
1316c8b3 10891 /* Size was already set above. */
e821645d
DJ		 10892 info->bytes_per_chunk = size;
10893 printer = print_insn_data;
10894
fe56b6ce 10895 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 10896 given = 0;
10897 if (little)
10898 for (i = size - 1; i >= 0; i--)
10899 given = b[i] | (given << 8);
10900 else
10901 for (i = 0; i < (int) size; i++)
10902 given = b[i] | (given << 8);
10903 }
10904 else if (!is_thumb)
252b5132 10905 {
c19d1205
ZW		 10906 /* In ARM mode endianness is a straightforward issue: the instruction
10907 is four bytes long and is either ordered 0123 or 3210. */
10908 printer = print_insn_arm;
10909 info->bytes_per_chunk = 4;
4a5329c6 10910 size = 4;
c19d1205 10911
0313a2b8 10912 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 10913 if (little_code)
c19d1205
ZW		 10914 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
10915 else
10916 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
252b5132 10917 }
58efb6c0 10918 else
252b5132 10919 {
c19d1205
ZW		 10920 /* In Thumb mode we have the additional wrinkle of two
10921 instruction lengths. Fortunately, the bits that determine
10922 the length of the current instruction are always to be found
10923 in the first two bytes. */
4a5329c6 10924 printer = print_insn_thumb16;
c19d1205 10925 info->bytes_per_chunk = 2;
4a5329c6
ZW		 10926 size = 2;
10927
fe56b6ce 10928 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 10929 if (little_code)
9a2ff3f5
AM		 10930 given = (b[0]) | (b[1] << 8);
10931 else
10932 given = (b[1]) | (b[0] << 8);
10933
c19d1205 10934 if (!status)
252b5132 10935 {
c19d1205
ZW		 10936 /* These bit patterns signal a four-byte Thumb
10937 instruction. */
10938 if ((given & 0xF800) == 0xF800
10939 || (given & 0xF800) == 0xF000
10940 || (given & 0xF800) == 0xE800)
252b5132 10941 {
0313a2b8 10942 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 10943 if (little_code)
c19d1205 10944 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 10945 else
c19d1205
ZW		 10946 given = (b[1]) | (b[0] << 8) | (given << 16);
10947
10948 printer = print_insn_thumb32;
4a5329c6 10949 size = 4;
252b5132 10950 }
252b5132 10951 }
c22aaad1
PB		 10952
10953 if (ifthen_address != pc)
0313a2b8 10954 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 10955
10956 if (ifthen_state)
10957 {
10958 if ((ifthen_state & 0xf) == 0x8)
10959 ifthen_next_state = 0;
10960 else
10961 ifthen_next_state = (ifthen_state & 0xe0)
10962 | ((ifthen_state & 0xf) << 1);
10963 }
252b5132 10964 }
b34976b6 10965
c19d1205
ZW		 10966 if (status)
10967 {
10968 info->memory_error_func (status, pc, info);
10969 return -1;
10970 }
6a56ec7e
NC		 10971 if (info->flags & INSN_HAS_RELOC)
10972 /* If the instruction has a reloc associated with it, then
10973 the offset field in the instruction will actually be the
10974 addend for the reloc. (We are using REL type relocs).
10975 In such cases, we can ignore the pc when computing
10976 addresses, since the addend is not currently pc-relative. */
10977 pc = 0;
b34976b6 10978
4a5329c6 10979 printer (pc, info, given);
c22aaad1
PB		 10980
10981 if (is_thumb)
10982 {
10983 ifthen_state = ifthen_next_state;
10984 ifthen_address += size;
10985 }
4a5329c6 10986 return size;
252b5132
RH		 10987}
10988
10989int
4a5329c6 10990print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 10991{
bd2e2557
SS		 10992 /* Detect BE8-ness and record it in the disassembler info. */
10993 if (info->flavour == bfd_target_elf_flavour
10994 && info->section != NULL
10995 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
10996 info->endian_code = BFD_ENDIAN_LITTLE;
10997
b34976b6 10998 return print_insn (pc, info, FALSE);
58efb6c0 10999}
01c7f630 11000
58efb6c0 11001int
4a5329c6 11002print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 11003{
b34976b6 11004 return print_insn (pc, info, TRUE);
58efb6c0 11005}
252b5132 11006
471b9d15 11007const disasm_options_and_args_t *
65b48a81
PB		 11008disassembler_options_arm (void)
11009{
471b9d15 11010 static disasm_options_and_args_t *opts_and_args;
65b48a81 11011
471b9d15 11012 if (opts_and_args == NULL)
65b48a81 11013 {
471b9d15 11014 disasm_options_t *opts;
65b48a81 11015 unsigned int i;
471b9d15
MR		 11016
11017 opts_and_args = XNEW (disasm_options_and_args_t);
11018 opts_and_args->args = NULL;
11019
11020 opts = &opts_and_args->options;
65b48a81
PB		 11021 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
11022 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
471b9d15 11023 opts->arg = NULL;
65b48a81
PB		 11024 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11025 {
11026 opts->name[i] = regnames[i].name;
11027 if (regnames[i].description != NULL)
11028 opts->description[i] = _(regnames[i].description);
11029 else
11030 opts->description[i] = NULL;
11031 }
11032 /* The array we return must be NULL terminated. */
11033 opts->name[i] = NULL;
11034 opts->description[i] = NULL;
11035 }
11036
471b9d15 11037 return opts_and_args;
65b48a81
PB		 11038}
11039
58efb6c0 11040void
4a5329c6 11041print_arm_disassembler_options (FILE *stream)
58efb6c0 11042{
65b48a81 11043 unsigned int i, max_len = 0;
58efb6c0
NC		 11044 fprintf (stream, _("\n\
11045The following ARM specific disassembler options are supported for use with\n\
11046the -M switch:\n"));
b34976b6 11047
65b48a81
PB		 11048 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11049 {
11050 unsigned int len = strlen (regnames[i].name);
11051 if (max_len < len)
11052 max_len = len;
11053 }
58efb6c0 11054
65b48a81
PB		 11055 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
11056 fprintf (stream, " %s%*c %s\n",
11057 regnames[i].name,
11058 (int)(max_len - strlen (regnames[i].name)), ' ',
11059 _(regnames[i].description));
252b5132 11060}
GDB Binutils - Deliverables
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