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[PATCH 53/57][Arm][OBJDUMP] Add support for MVE instructions: vand, vbrsr, vcls,...
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
CommitLineData
252b5132 1/* Instruction printing code for the ARM
82704155 2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
143275ea 24#include <assert.h>
2fbad815 25
6394c606 26#include "disassemble.h"
2fbad815 27#include "opcode/arm.h"
252b5132 28#include "opintl.h"
31e0f3cd 29#include "safe-ctype.h"
65b48a81 30#include "libiberty.h"
0dbde4cf 31#include "floatformat.h"
252b5132 32
baf0cc5e 33/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 34#include "coff/internal.h"
35#include "libcoff.h"
2d5d5a8f 36#include "bfd.h"
252b5132
RH		 37#include "elf-bfd.h"
38#include "elf/internal.h"
39#include "elf/arm.h"
e49d43ff 40#include "mach-o.h"
252b5132 41
6b5d3a4d 42/* FIXME: Belongs in global header. */
01c7f630 43#ifndef strneq
58efb6c0
NC		 44#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
45#endif
46
1fbaefec
PB		 47/* Cached mapping symbol state. */
48enum map_type
49{
50 MAP_ARM,
51 MAP_THUMB,
52 MAP_DATA
53};
54
b0e28b39
DJ		 55struct arm_private_data
56{
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features;
59
1fbaefec
PB		 60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type;
62
63 /* Tracking symbol table information */
64 int last_mapping_sym;
796d6298
TC		 65
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset;
1fbaefec 68 bfd_vma last_mapping_addr;
b0e28b39
DJ		 69};
70
73cd51e5
AV		 71enum mve_instructions
72{
143275ea
AV		 73 MVE_VPST,
74 MVE_VPT_FP_T1,
75 MVE_VPT_FP_T2,
76 MVE_VPT_VEC_T1,
77 MVE_VPT_VEC_T2,
78 MVE_VPT_VEC_T3,
79 MVE_VPT_VEC_T4,
80 MVE_VPT_VEC_T5,
81 MVE_VPT_VEC_T6,
82 MVE_VCMP_FP_T1,
83 MVE_VCMP_FP_T2,
84 MVE_VCMP_VEC_T1,
85 MVE_VCMP_VEC_T2,
86 MVE_VCMP_VEC_T3,
87 MVE_VCMP_VEC_T4,
88 MVE_VCMP_VEC_T5,
89 MVE_VCMP_VEC_T6,
9743db03
AV		 90 MVE_VDUP,
91 MVE_VEOR,
92 MVE_VFMAS_FP_SCALAR,
93 MVE_VFMA_FP_SCALAR,
94 MVE_VFMA_FP,
95 MVE_VFMS_FP,
96 MVE_VHADD_T1,
97 MVE_VHADD_T2,
98 MVE_VHSUB_T1,
99 MVE_VHSUB_T2,
100 MVE_VRHADD,
04d54ace
AV		 101 MVE_VLD2,
102 MVE_VLD4,
103 MVE_VST2,
104 MVE_VST4,
aef6d006
AV		 105 MVE_VLDRB_T1,
106 MVE_VLDRH_T2,
107 MVE_VLDRB_T5,
108 MVE_VLDRH_T6,
109 MVE_VLDRW_T7,
110 MVE_VSTRB_T1,
111 MVE_VSTRH_T2,
112 MVE_VSTRB_T5,
113 MVE_VSTRH_T6,
114 MVE_VSTRW_T7,
ef1576a1
AV		 115 MVE_VLDRB_GATHER_T1,
116 MVE_VLDRH_GATHER_T2,
117 MVE_VLDRW_GATHER_T3,
118 MVE_VLDRD_GATHER_T4,
119 MVE_VLDRW_GATHER_T5,
120 MVE_VLDRD_GATHER_T6,
121 MVE_VSTRB_SCATTER_T1,
122 MVE_VSTRH_SCATTER_T2,
123 MVE_VSTRW_SCATTER_T3,
124 MVE_VSTRD_SCATTER_T4,
125 MVE_VSTRW_SCATTER_T5,
126 MVE_VSTRD_SCATTER_T6,
bf0b396d
AV		 127 MVE_VCVT_FP_FIX_VEC,
128 MVE_VCVT_BETWEEN_FP_INT,
129 MVE_VCVT_FP_HALF_FP,
130 MVE_VCVT_FROM_FP_TO_INT,
131 MVE_VRINT_FP,
c507f10b
AV		 132 MVE_VMOV_HFP_TO_GP,
133 MVE_VMOV_GP_TO_VEC_LANE,
134 MVE_VMOV_IMM_TO_VEC,
135 MVE_VMOV_VEC_TO_VEC,
136 MVE_VMOV2_VEC_LANE_TO_GP,
137 MVE_VMOV2_GP_TO_VEC_LANE,
138 MVE_VMOV_VEC_LANE_TO_GP,
139 MVE_VMVN_IMM,
140 MVE_VMVN_REG,
141 MVE_VORR_IMM,
142 MVE_VORR_REG,
143 MVE_VORN,
144 MVE_VBIC_IMM,
145 MVE_VBIC_REG,
146 MVE_VMOVX,
14925797
AV		 147 MVE_VMOVL,
148 MVE_VMOVN,
149 MVE_VMULL_INT,
150 MVE_VMULL_POLY,
151 MVE_VQDMULL_T1,
152 MVE_VQDMULL_T2,
153 MVE_VQMOVN,
154 MVE_VQMOVUN,
d3b63143
AV		 155 MVE_VADDV,
156 MVE_VMLADAV_T1,
157 MVE_VMLADAV_T2,
158 MVE_VMLALDAV,
159 MVE_VMLAS,
160 MVE_VADDLV,
161 MVE_VMLSDAV_T1,
162 MVE_VMLSDAV_T2,
163 MVE_VMLSLDAV,
164 MVE_VRMLALDAVH,
165 MVE_VRMLSLDAVH,
166 MVE_VQDMLADH,
167 MVE_VQRDMLADH,
168 MVE_VQDMLAH,
169 MVE_VQRDMLAH,
170 MVE_VQDMLASH,
171 MVE_VQRDMLASH,
172 MVE_VQDMLSDH,
173 MVE_VQRDMLSDH,
174 MVE_VQDMULH_T1,
175 MVE_VQRDMULH_T2,
176 MVE_VQDMULH_T3,
177 MVE_VQRDMULH_T4,
1c8f2df8
AV		 178 MVE_VDDUP,
179 MVE_VDWDUP,
180 MVE_VIWDUP,
181 MVE_VIDUP,
897b9bbc
AV		 182 MVE_VCADD_FP,
183 MVE_VCADD_VEC,
184 MVE_VHCADD,
185 MVE_VCMLA_FP,
186 MVE_VCMUL_FP,
ed63aa17
AV		 187 MVE_VQRSHL_T1,
188 MVE_VQRSHL_T2,
189 MVE_VQRSHRN,
190 MVE_VQRSHRUN,
191 MVE_VQSHL_T1,
192 MVE_VQSHL_T2,
193 MVE_VQSHLU_T3,
194 MVE_VQSHL_T4,
195 MVE_VQSHRN,
196 MVE_VQSHRUN,
197 MVE_VRSHL_T1,
198 MVE_VRSHL_T2,
199 MVE_VRSHR,
200 MVE_VRSHRN,
201 MVE_VSHL_T1,
202 MVE_VSHL_T2,
203 MVE_VSHL_T3,
204 MVE_VSHLC,
205 MVE_VSHLL_T1,
206 MVE_VSHLL_T2,
207 MVE_VSHR,
208 MVE_VSHRN,
209 MVE_VSLI,
210 MVE_VSRI,
66dcaa5d
AV		 211 MVE_VADC,
212 MVE_VABAV,
213 MVE_VABD_FP,
214 MVE_VABD_VEC,
215 MVE_VABS_FP,
216 MVE_VABS_VEC,
217 MVE_VADD_FP_T1,
218 MVE_VADD_FP_T2,
219 MVE_VADD_VEC_T1,
220 MVE_VADD_VEC_T2,
221 MVE_VSBC,
222 MVE_VSUB_FP_T1,
223 MVE_VSUB_FP_T2,
224 MVE_VSUB_VEC_T1,
225 MVE_VSUB_VEC_T2,
e523f101
AV		 226 MVE_VAND,
227 MVE_VBRSR,
228 MVE_VCLS,
229 MVE_VCLZ,
230 MVE_VCTP,
73cd51e5
AV		 231 MVE_NONE
232};
233
234enum mve_unpredictable
235{
236 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
237 */
143275ea
AV		 238 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and
239 fcB = 1 (vpt). */
240 UNPRED_R13, /* Unpredictable because r13 (sp) or
241 r15 (sp) used. */
9743db03 242 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
04d54ace
AV		 243 UNPRED_Q_GT_4, /* Unpredictable because
244 vec reg start > 4 (vld4/st4). */
245 UNPRED_Q_GT_6, /* Unpredictable because
246 vec reg start > 6 (vld2/st2). */
247 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
248 and WB bit = 1. */
ef1576a1
AV		 249 UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are
250 equal. */
251 UNPRED_OS, /* Unpredictable because offset scaled == 1. */
bf0b396d
AV		 252 UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the
253 same. */
c507f10b
AV		 254 UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and
255 size = 1. */
256 UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and
257 size = 2. */
73cd51e5
AV		 258 UNPRED_NONE /* No unpredictable behavior. */
259};
260
261enum mve_undefined
262{
ed63aa17 263 UNDEF_SIZE, /* undefined size. */
bf0b396d 264 UNDEF_SIZE_0, /* undefined because size == 0. */
c507f10b 265 UNDEF_SIZE_2, /* undefined because size == 2. */
aef6d006
AV		 266 UNDEF_SIZE_3, /* undefined because size == 3. */
267 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
ef1576a1
AV		 268 UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
269 UNDEF_SIZE_NOT_3, /* undefined because size != 3. */
270 UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and
271 size == 0. */
272 UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and
273 size == 1. */
274 UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
bf0b396d
AV		 275 UNDEF_VCVT_IMM6, /* imm6 < 32. */
276 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
c507f10b
AV		 277 UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and
278 op1 == (0 or 1). */
279 UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and
280 op2 == 0 and op1 == (0 or 1). */
281 UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode
282 in {0xx1, x0x1}. */
d3b63143 283 UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */
73cd51e5
AV		 284 UNDEF_NONE /* no undefined behavior. */
285};
286
6b5d3a4d
ZW		 287struct opcode32
288{
823d2571
TG		 289 arm_feature_set arch; /* Architecture defining this insn. */
290 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 291 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 292 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 293};
294
73cd51e5
AV		 295/* MVE opcodes. */
296
297struct mopcode32
298{
299 arm_feature_set arch; /* Architecture defining this insn. */
300 enum mve_instructions mve_op; /* Specific mve instruction for faster
301 decoding. */
302 unsigned long value; /* If arch is 0 then value is a sentinel. */
303 unsigned long mask; /* Recognise insn if (op & mask) == value. */
304 const char * assembler; /* How to disassemble this insn. */
305};
306
6b0dd094
AV		 307enum isa {
308 ANY,
309 T32,
310 ARM
311};
312
313
314/* Shared (between Arm and Thumb mode) opcode. */
315struct sopcode32
316{
317 enum isa isa; /* Execution mode instruction availability. */
318 arm_feature_set arch; /* Architecture defining this insn. */
319 unsigned long value; /* If arch is 0 then value is a sentinel. */
320 unsigned long mask; /* Recognise insn if (op & mask) == value. */
321 const char * assembler; /* How to disassemble this insn. */
322};
323
6b5d3a4d
ZW		 324struct opcode16
325{
823d2571 326 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 327 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 328 const char *assembler; /* How to disassemble this insn. */
329};
b7693d02 330
8f06b2d8 331/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 332
2fbad815 333 %% %
4a5329c6 334
c22aaad1 335 %c print condition code (always bits 28-31 in ARM mode)
37b37b2d 336 %q print shifter argument
e2efe87d
MGD		 337 %u print condition code (unconditional in ARM mode,
338 UNPREDICTABLE if not AL in Thumb)
4a5329c6 339 %A print address for ldc/stc/ldf/stf instruction
16980d0b 340 %B print vstm/vldm register list
efd6b359 341 %C print vscclrm register list
4a5329c6 342 %I print cirrus signed shift immediate: bits 0..3|4..6
32c36c3c
AV		 343 %J print register for VLDR instruction
344 %K print address for VLDR instruction
4a5329c6
ZW		 345 %F print the COUNT field of a LFM/SFM instruction.
346 %P print floating point precision in arithmetic insn
347 %Q print floating point precision in ldf/stf insn
348 %R print floating point rounding mode
349
33399f07 350 %<bitfield>c print as a condition code (for vsel)
4a5329c6 351 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 352 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
353 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 354 %<bitfield>d print the bitfield in decimal
16980d0b 355 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 356 %<bitfield>x print the bitfield in hex
357 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 358 %<bitfield>f print a floating point constant if >7 else a
359 floating point register
4a5329c6
ZW		 360 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
361 %<bitfield>g print as an iWMMXt 64-bit register
362 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 363 %<bitfield>D print as a NEON D register
364 %<bitfield>Q print as a NEON Q register
c28eeff2 365 %<bitfield>V print as a NEON D or Q register
6f1c2142 366 %<bitfield>E print a quarter-float immediate value
4a5329c6 367
16980d0b 368 %y<code> print a single precision VFP reg.
2fbad815 369 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 370 %z<code> print a double precision VFP reg
2fbad815 371 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 372
16980d0b
JB		 373 %<bitfield>'c print specified char iff bitfield is all ones
374 %<bitfield>`c print specified char iff bitfield is all zeroes
375 %<bitfield>?ab... select from array of values in big endian order
43e65147 376
2fbad815 377 %L print as an iWMMXt N/M width field.
4a5329c6 378 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 379 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 380 versions.
381 %i print 5-bit immediate in bits 8,3..0
382 (print "32" when 0)
fe56b6ce 383 %r print register offset address for wldt/wstr instruction. */
2fbad815 384
21d799b5 385enum opcode_sentinel_enum
05413229
NC		 386{
387 SENTINEL_IWMMXT_START = 1,
388 SENTINEL_IWMMXT_END,
389 SENTINEL_GENERIC_START
390} opcode_sentinels;
391
aefd8a40 392#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
0b347048
TC		 393#define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
394#define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
c1e26897 395#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 396
8f06b2d8 397/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 398
6b0dd094 399static const struct sopcode32 coprocessor_opcodes[] =
2fbad815 400{
2fbad815 401 /* XScale instructions. */
6b0dd094 402 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 403 0x0e200010, 0x0fff0ff0,
404 "mia%c\tacc0, %0-3r, %12-15r"},
6b0dd094 405 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 406 0x0e280010, 0x0fff0ff0,
407 "miaph%c\tacc0, %0-3r, %12-15r"},
6b0dd094 408 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 409 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
6b0dd094 410 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 411 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
6b0dd094 412 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 413 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 414
2fbad815 415 /* Intel Wireless MMX technology instructions. */
6b0dd094
AV		 416 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
417 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
823d2571 418 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
6b0dd094 419 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 420 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
6b0dd094 421 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 422 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
6b0dd094 423 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 424 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
6b0dd094 425 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 426 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
6b0dd094 427 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 428 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
6b0dd094 429 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 430 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
6b0dd094 431 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 432 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 433 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 434 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 435 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 436 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 437 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 438 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
6b0dd094 439 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 440 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
6b0dd094 441 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 442 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
6b0dd094 443 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 444 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
6b0dd094 445 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 446 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
6b0dd094 447 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 448 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 449 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 450 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 451 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 452 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 453 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 454 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 455 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 456 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 457 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 458 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
6b0dd094 459 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 460 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 461 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 462 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 463 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 464 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 465 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 466 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 467 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 468 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 469 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 470 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 471 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 472 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
6b0dd094 473 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 474 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
6b0dd094 475 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 476 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
6b0dd094 477 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 478 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 479 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 480 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 481 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 482 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 483 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 484 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 485 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 486 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
6b0dd094 487 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 488 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 489 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 490 0x0e800120, 0x0f800ff0,
491 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 492 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 493 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 494 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 495 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 496 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 497 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 498 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 499 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 500 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 501 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 502 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 503 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 504 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 505 0x0e8000a0, 0x0f800ff0,
506 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 507 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 508 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 509 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 510 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 511 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 512 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 513 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 514 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 515 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 516 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 517 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 518 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 519 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 520 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 521 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 522 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 523 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 524 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
6b0dd094 525 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 526 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 527 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 528 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 529 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 530 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 531 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 532 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 533 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 534 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 535 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 536 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 537 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 538 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 539 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 540 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 541 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 542 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 543 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 544 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
6b0dd094 545 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 546 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
6b0dd094 547 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 548 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
6b0dd094 549 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 550 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 551 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 552 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 553 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 554 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 555 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 556 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
6b0dd094 557 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 558 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
6b0dd094 559 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 560 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
6b0dd094 561 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 562 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 563 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 564 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 565 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 566 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 567 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 568 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 569 {ANY, ARM_FEATURE_CORE_LOW (0),
823d2571 570 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 571
fe56b6ce 572 /* Floating point coprocessor (FPA) instructions. */
6b0dd094 573 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 574 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 575 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 576 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 577 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 578 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 579 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 580 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 581 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 582 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 583 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 584 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 585 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 586 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 587 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 588 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 589 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 590 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 591 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 592 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 593 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 594 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 595 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 596 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 597 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 598 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 599 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 600 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 601 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 602 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 603 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 604 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 605 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 606 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 607 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 608 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
6b0dd094 609 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 610 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
6b0dd094 611 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 612 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 613 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 614 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
6b0dd094 615 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 616 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
6b0dd094 617 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 618 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
6b0dd094 619 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 620 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
6b0dd094 621 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 622 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 623 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 624 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 625 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 626 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 627 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 628 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 629 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 630 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
6b0dd094 631 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 632 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
6b0dd094 633 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 634 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
6b0dd094 635 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 636 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
6b0dd094 637 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 638 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
6b0dd094 639 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 640 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
6b0dd094 641 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 642 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
6b0dd094 643 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 644 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
6b0dd094 645 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 646 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
6b0dd094 647 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 648 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
6b0dd094 649 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 650 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
6b0dd094 651 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 652 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
6b0dd094 653 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 654 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
6b0dd094 655 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 656 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
6b0dd094 657 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 658 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 659
efd6b359
AV		 660 /* Armv8.1-M Mainline instructions. */
661 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
662 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
663 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
664 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
665
16a1fa25 666 /* ARMv8-M Mainline Security Extensions instructions. */
6b0dd094 667 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25 668 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
6b0dd094 669 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25
TP		 670 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
671
fe56b6ce 672 /* Register load/store. */
6b0dd094 673 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 674 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
6b0dd094 675 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 676 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
6b0dd094 677 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 678 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
6b0dd094 679 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 680 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
6b0dd094 681 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 682 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
6b0dd094 683 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 684 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
6b0dd094 685 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 686 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
6b0dd094 687 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 688 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
6b0dd094 689 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 690 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
6b0dd094 691 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 692 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
6b0dd094 693 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 694 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
6b0dd094 695 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 696 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
6b0dd094 697 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 698 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
6b0dd094 699 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 700 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
6b0dd094 701 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 702 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
6b0dd094 703 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 704 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
32c36c3c
AV		 705 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
706 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
707 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
708 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
823d2571 709
6b0dd094 710 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 711 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 712 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 713 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 714 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 715 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
6b0dd094 716 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 717 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 718
fe56b6ce 719 /* Data transfer between ARM and NEON registers. */
6b0dd094 720 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 721 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
6b0dd094 722 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 723 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
6b0dd094 724 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 725 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
6b0dd094 726 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 727 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
6b0dd094 728 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 729 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
6b0dd094 730 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 731 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
6b0dd094 732 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 733 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
6b0dd094 734 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 735 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 736 /* Half-precision conversion instructions. */
6b0dd094 737 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 738 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
6b0dd094 739 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 740 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
6b0dd094 741 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 742 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
6b0dd094 743 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 744 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 745
fe56b6ce 746 /* Floating point coprocessor (VFP) instructions. */
6b0dd094 747 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 748 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
6b0dd094 749 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 750 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
6b0dd094 751 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 752 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
6b0dd094 753 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 754 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
6b0dd094 755 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 756 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
6b0dd094 757 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 758 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
6b0dd094 759 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 760 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
6b0dd094 761 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 762 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
6b0dd094 763 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 764 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
6b0dd094 765 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 766 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
6b0dd094 767 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 768 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
6b0dd094 769 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 770 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
6b0dd094 771 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 772 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
6b0dd094 773 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 774 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
6b0dd094 775 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 776 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
6b0dd094 777 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 778 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
6b0dd094 779 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 780 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
6b0dd094 781 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 782 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
6b0dd094 783 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 784 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
6b0dd094 785 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 786 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
6b0dd094 787 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 788 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
6b0dd094 789 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 790 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
6b0dd094 791 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 792 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
6b0dd094 793 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 794 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
6b0dd094 795 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 796 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
6b0dd094 797 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 798 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
6b0dd094 799 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 800 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
6b0dd094 801 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 802 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
6b0dd094 803 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 804 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
6b0dd094 805 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 806 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
6b0dd094 807 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 808 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
6b0dd094 809 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 810 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
6b0dd094 811 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 812 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
6b0dd094 813 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 814 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
6b0dd094 815 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 816 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
6b0dd094 817 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 818 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
6b0dd094 819 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 820 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
6b0dd094 821 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 822 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
6b0dd094 823 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 824 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
6b0dd094 825 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 826 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 827 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 828 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
6b0dd094 829 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 830 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
6b0dd094 831 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 832 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
6b0dd094 833 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 834 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
6b0dd094 835 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 836 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
6b0dd094 837 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 838 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
6b0dd094 839 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6f1c2142 840 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
6b0dd094 841 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6f1c2142 842 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
6b0dd094 843 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 844 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
6b0dd094 845 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 846 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
6b0dd094 847 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 848 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
6b0dd094 849 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 850 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 851 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 852 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 853 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 854 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 855 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 856 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 857 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 858 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 859 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 860 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 861 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 862 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 863 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 864 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 865 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 866 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 867 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 868 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 869 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 870 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 871 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 872 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 873 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 874 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
6b0dd094 875 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 876 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
6b0dd094 877 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 878 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
6b0dd094 879 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 880 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
6b0dd094 881 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 882 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
6b0dd094 883 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 884 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 885
886 /* Cirrus coprocessor instructions. */
6b0dd094 887 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 888 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 889 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 890 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 891 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 892 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 893 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 894 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 895 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 896 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 897 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 898 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 899 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 900 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 901 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 902 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 903 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 904 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 905 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 906 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 907 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 908 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 909 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 910 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 911 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 912 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 913 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 914 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 915 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 916 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 917 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 918 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 919 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 920 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
6b0dd094 921 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 922 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
6b0dd094 923 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 924 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
6b0dd094 925 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 926 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
6b0dd094 927 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 928 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
6b0dd094 929 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 930 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
6b0dd094 931 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 932 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 933 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 934 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
6b0dd094 935 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 936 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 937 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 938 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
6b0dd094 939 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 940 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 941 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 942 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 943 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 944 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 945 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 946 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 947 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 948 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 949 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 950 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 951 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 952 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 953 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 954 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 955 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 956 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
6b0dd094 957 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 958 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
6b0dd094 959 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 960 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
6b0dd094 961 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 962 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
6b0dd094 963 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 964 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 965 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 966 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 967 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 968 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
6b0dd094 969 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 970 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
6b0dd094 971 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 972 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
6b0dd094 973 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 974 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
6b0dd094 975 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 976 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
6b0dd094 977 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 978 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
6b0dd094 979 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 980 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 981 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 982 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 983 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 984 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 985 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 986 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 987 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 988 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
6b0dd094 989 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 990 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
6b0dd094 991 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 992 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
6b0dd094 993 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 994 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
6b0dd094 995 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 996 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
6b0dd094 997 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 998 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
6b0dd094 999 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1000 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1001 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1002 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1003 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1004 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1005 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1006 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1007 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1008 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1009 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1010 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1011 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1012 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1013 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1014 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1015 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1016 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1017 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1018 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1019 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1020 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1021 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1022 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1023 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1024 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 1025 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1026 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 1027 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1028 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 1029 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1030 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 1031 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1032 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1033 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1034 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1035 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1036 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1037 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1038 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1039 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1040 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1041 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1042 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1043 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1044 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1045 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1046 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1047 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1048 0x0e000600, 0x0ff00f10,
1049 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1050 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1051 0x0e100600, 0x0ff00f10,
1052 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1053 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1054 0x0e200600, 0x0ff00f10,
1055 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1056 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1057 0x0e300600, 0x0ff00f10,
1058 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 1059
62f3b8c8 1060 /* VFP Fused multiply add instructions. */
6b0dd094 1061 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1062 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1063 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1064 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1065 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1066 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1067 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1068 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
6b0dd094 1069 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1070 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1071 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1072 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1073 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1074 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1075 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1076 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 1077
33399f07 1078 /* FP v5. */
6b0dd094 1079 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1080 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
6b0dd094 1081 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1082 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
6b0dd094 1083 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1084 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1085 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1086 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1087 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1088 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1089 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1090 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1091 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1092 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
6b0dd094 1093 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1094 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
6b0dd094 1095 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1096 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
6b0dd094 1097 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1098 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
6b0dd094 1099 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1100 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
6b0dd094 1101 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1102 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 1103
05413229 1104 /* Generic coprocessor instructions. */
6b0dd094
AV		 1105 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
1106 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
823d2571 1107 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
6b0dd094 1108 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
823d2571
TG		 1109 0x0c500000, 0x0ff00000,
1110 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
6b0dd094 1111 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1112 0x0e000000, 0x0f000010,
1113 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1114 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1115 0x0e10f010, 0x0f10f010,
1116 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1117 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1118 0x0e100010, 0x0f100010,
1119 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1120 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1121 0x0e000010, 0x0f100010,
1122 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1123 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571 1124 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 1125 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571 1126 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
2fbad815 1127
05413229 1128 /* V6 coprocessor instructions. */
6b0dd094 1129 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
823d2571
TG		 1130 0xfc500000, 0xfff00000,
1131 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
6b0dd094 1132 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
823d2571
TG		 1133 0xfc400000, 0xfff00000,
1134 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
8f06b2d8 1135
c28eeff2 1136 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
6b0dd094 1137 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1138 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1139 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1140 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1141 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1142 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1143 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1144 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1145 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1146 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1147 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1148 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1149 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1150 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
6b0dd094 1151 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1152 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
6b0dd094 1153 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1154 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
6b0dd094 1155 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1156 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
c28eeff2 1157
c604a79a 1158 /* Dot Product instructions in the space of coprocessor 13. */
6b0dd094 1159 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a 1160 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
6b0dd094 1161 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a
JW		 1162 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1163
dec41383 1164 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
6b0dd094 1165 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1166 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1167 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1168 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1169 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1170 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1171 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1172 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1173 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1174 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1175 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1176 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1177 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1178 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
6b0dd094 1179 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383
JW		 1180 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1181
05413229 1182 /* V5 coprocessor instructions. */
6b0dd094 1183 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571 1184 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 1185 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571 1186 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 1187 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1188 0xfe000000, 0xff000010,
1189 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1190 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1191 0xfe000010, 0xff100010,
1192 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1193 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1194 0xfe100010, 0xff100010,
1195 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1196
b0c11777
RL		 1197 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1198 cp_num: bit <11:8> == 0b1001.
1199 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
6b0dd094 1200 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1201 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
6b0dd094 1202 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1203 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
6b0dd094 1204 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1205 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
6b0dd094 1206 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1207 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
6b0dd094 1208 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1209 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 1210 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1211 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
6b0dd094 1212 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1213 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
6b0dd094 1214 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1215 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
6b0dd094 1216 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1217 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
6b0dd094 1218 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1219 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
6b0dd094 1220 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1221 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1222 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1223 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1224 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1225 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1226 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1227 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1228 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1229 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
6b0dd094 1230 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1231 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
6b0dd094 1232 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1233 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
6b0dd094 1234 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1235 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
6b0dd094 1236 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1237 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1238 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1239 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1240 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1241 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1242 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1243 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1244 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1245 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
6b0dd094 1246 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1247 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
6b0dd094 1248 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1249 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
6b0dd094 1250 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1251 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1252 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1253 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
6b0dd094 1254 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1255 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1256 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1257 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1258 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1259 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1260 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1261 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
6b0dd094 1262 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1263 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
6b0dd094 1264 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1265 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
6b0dd094 1266 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1267 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
6b0dd094 1268 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777
RL		 1269 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1270
49e8a725 1271 /* ARMv8.3 javascript conversion instruction. */
6b0dd094 1272 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
49e8a725
SN		 1273 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1274
6b0dd094 1275 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 1276};
1277
16980d0b
JB		 1278/* Neon opcode table: This does not encode the top byte -- that is
1279 checked by the print_insn_neon routine, as it depends on whether we are
1280 doing thumb32 or arm32 disassembly. */
1281
1282/* print_insn_neon recognizes the following format control codes:
1283
1284 %% %
1285
c22aaad1 1286 %c print condition code
e2efe87d
MGD		 1287 %u print condition code (unconditional in ARM mode,
1288 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 1289 %A print v{st,ld}[1234] operands
1290 %B print v{st,ld}[1234] any one operands
1291 %C print v{st,ld}[1234] single->all operands
1292 %D print scalar
1293 %E print vmov, vmvn, vorr, vbic encoded constant
1294 %F print vtbl,vtbx register list
1295
1296 %<bitfield>r print as an ARM register
1297 %<bitfield>d print the bitfield in decimal
1298 %<bitfield>e print the 2^N - bitfield in decimal
1299 %<bitfield>D print as a NEON D register
1300 %<bitfield>Q print as a NEON Q register
1301 %<bitfield>R print as a NEON D or Q register
1302 %<bitfield>Sn print byte scaled width limited by n
1303 %<bitfield>Tn print short scaled width limited by n
1304 %<bitfield>Un print long scaled width limited by n
43e65147 1305
16980d0b
JB		 1306 %<bitfield>'c print specified char iff bitfield is all ones
1307 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1308 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1309
1310static const struct opcode32 neon_opcodes[] =
1311{
fe56b6ce 1312 /* Extract. */
823d2571
TG		 1313 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1314 0xf2b00840, 0xffb00850,
1315 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1316 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1317 0xf2b00000, 0xffb00810,
1318 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 1319
9743db03
AV		 1320 /* Data transfer between ARM and NEON registers. */
1321 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1322 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1323 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1324 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1325 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1326 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1327 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1328 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1329 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1330 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1331 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1332 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1333
fe56b6ce 1334 /* Move data element to all lanes. */
823d2571
TG		 1335 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1336 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1337 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1338 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1339 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1340 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 1341
fe56b6ce 1342 /* Table lookup. */
823d2571
TG		 1343 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1344 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1345 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1346 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1347
8e79c3df 1348 /* Half-precision conversions. */
823d2571
TG		 1349 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1350 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1351 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1352 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1353
1354 /* NEON fused multiply add instructions. */
823d2571 1355 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1356 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1357 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1358 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1359 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1360 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1361 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1362 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1363
fe56b6ce 1364 /* Two registers, miscellaneous. */
823d2571
TG		 1365 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1366 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1367 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1368 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1369 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1370 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1371 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1372 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1373 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1374 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1375 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1376 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1377 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1378 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1379 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1380 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1381 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1382 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1383 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1384 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1385 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1386 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1387 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1388 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1389 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1390 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1391 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1392 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1393 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1394 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1395 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1396 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1397 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1398 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1399 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1400 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1401 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1402 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1403 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1404 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1405 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1406 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1407 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1408 0xf3b20300, 0xffb30fd0,
1409 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1410 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1411 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1412 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1413 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1414 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1415 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1416 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1417 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1418 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1419 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1420 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1421 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1422 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1423 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1424 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1425 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1426 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1427 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1428 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1429 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1430 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1431 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1432 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1433 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1434 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1435 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1436 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1437 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1438 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1439 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1440 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1441 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1442 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1443 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1444 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1445 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1446 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1447 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1448 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1449 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1450 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1451 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1452 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1453 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1454 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1455 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1456 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301 1457 0xf3bb0600, 0xffbf0e10,
823d2571 1458 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1459 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1460 0xf3b70600, 0xffbf0e10,
1461 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
16980d0b 1462
fe56b6ce 1463 /* Three registers of the same length. */
823d2571
TG		 1464 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1465 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1466 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1467 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1468 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1469 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1470 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1471 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1472 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1473 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1474 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1475 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1476 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1477 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1478 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1479 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1480 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1481 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1482 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1483 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1484 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1485 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1487 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1489 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1490 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1491 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1492 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1493 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1494 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1495 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1496 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1497 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1498 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1499 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1500 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1501 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1502 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1503 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1504 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1505 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1506 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1507 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1508 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1509 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1510 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1511 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1512 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1513 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1514 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1515 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1516 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1517 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1518 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1519 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1520 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1521 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1522 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1523 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1524 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1525 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1526 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1527 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1528 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1529 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1530 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1531 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1532 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1533 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1534 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1535 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1536 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1537 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1538 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1539 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1541 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1542 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1543 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1544 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1545 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1546 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1547 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1548 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1549 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1550 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1551 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1552 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1553 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1554 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1555 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1556 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1557 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1558 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1559 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1560 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1561 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1562 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1563 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1564 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1565 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1566 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1567 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1568 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1569 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1570 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1571 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1572 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1573 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1574 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1575 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1576 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1577 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1578 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1579 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1580 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1581 0xf2000b00, 0xff800f10,
1582 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1583 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1584 0xf2000b10, 0xff800f10,
1585 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1586 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1587 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1588 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1589 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1590 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1591 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1592 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1593 0xf3000b00, 0xff800f10,
1594 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1595 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1596 0xf2000000, 0xfe800f10,
1597 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1598 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1599 0xf2000010, 0xfe800f10,
1600 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1601 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1602 0xf2000100, 0xfe800f10,
1603 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1604 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1605 0xf2000200, 0xfe800f10,
1606 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1607 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1608 0xf2000210, 0xfe800f10,
1609 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1610 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1611 0xf2000300, 0xfe800f10,
1612 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1613 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1614 0xf2000310, 0xfe800f10,
1615 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1616 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1617 0xf2000400, 0xfe800f10,
1618 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1619 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1620 0xf2000410, 0xfe800f10,
1621 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1622 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1623 0xf2000500, 0xfe800f10,
1624 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1625 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1626 0xf2000510, 0xfe800f10,
1627 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1628 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1629 0xf2000600, 0xfe800f10,
1630 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1631 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1632 0xf2000610, 0xfe800f10,
1633 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1634 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1635 0xf2000700, 0xfe800f10,
1636 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1638 0xf2000710, 0xfe800f10,
1639 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1640 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1641 0xf2000910, 0xfe800f10,
1642 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1643 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1644 0xf2000a00, 0xfe800f10,
1645 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1646 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1647 0xf2000a10, 0xfe800f10,
1648 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1650 0xf3000b10, 0xff800f10,
1651 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1652 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1653 0xf3000c10, 0xff800f10,
1654 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1655
fe56b6ce 1656 /* One register and an immediate value. */
823d2571
TG		 1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1658 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1659 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1660 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1661 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1662 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1663 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1664 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1665 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1666 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1667 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1668 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1669 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1670 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1671 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1672 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1673 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1674 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1675 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1676 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1677 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1678 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1679 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1680 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1681 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1682 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1683
fe56b6ce 1684 /* Two registers and a shift amount. */
823d2571
TG		 1685 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1686 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1687 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1688 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1689 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1690 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1691 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1692 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1693 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1694 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1695 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1696 0xf2880950, 0xfeb80fd0,
1697 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1698 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1699 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1700 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1701 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1702 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1703 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1704 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1705 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1706 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1707 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1708 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1709 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1710 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1711 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1712 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1713 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1714 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1715 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1716 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1717 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1718 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1719 0xf2900950, 0xfeb00fd0,
1720 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1721 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1722 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1723 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1724 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1725 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1726 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1727 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1728 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1729 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1730 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1731 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1732 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1733 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1734 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1735 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1736 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1737 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1738 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1739 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1740 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1741 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1742 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1743 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1744 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1745 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1746 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1747 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1748 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1749 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1750 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1751 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1752 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1753 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1754 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1755 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1756 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1757 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1758 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1759 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1760 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1761 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1762 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1763 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1764 0xf2a00950, 0xfea00fd0,
1765 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1766 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1767 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1768 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1769 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1770 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1771 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1772 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1773 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1774 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1775 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1776 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1777 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1778 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1779 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1780 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1781 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1782 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1783 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1784 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1785 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1786 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1787 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1788 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1789 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1790 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1791 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1792 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1793 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1794 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1795 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1796 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1797 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1798 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1799 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1800 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1801 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1802 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1803 0xf2a00e10, 0xfea00e90,
1804 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
cc933301
JW		 1805 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1806 0xf2a00c10, 0xfea00e90,
1807 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 1808
fe56b6ce 1809 /* Three registers of different lengths. */
823d2571
TG		 1810 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1811 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1812 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1813 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1814 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1815 0xf2800400, 0xff800f50,
1816 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1817 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1818 0xf2800600, 0xff800f50,
1819 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1820 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1821 0xf2800900, 0xff800f50,
1822 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1823 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1824 0xf2800b00, 0xff800f50,
1825 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1826 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1827 0xf2800d00, 0xff800f50,
1828 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1829 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1830 0xf3800400, 0xff800f50,
1831 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1832 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1833 0xf3800600, 0xff800f50,
1834 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1835 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1836 0xf2800000, 0xfe800f50,
1837 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1838 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1839 0xf2800100, 0xfe800f50,
1840 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1841 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1842 0xf2800200, 0xfe800f50,
1843 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1844 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1845 0xf2800300, 0xfe800f50,
1846 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1847 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1848 0xf2800500, 0xfe800f50,
1849 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1850 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1851 0xf2800700, 0xfe800f50,
1852 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1853 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1854 0xf2800800, 0xfe800f50,
1855 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1856 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1857 0xf2800a00, 0xfe800f50,
1858 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1859 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1860 0xf2800c00, 0xfe800f50,
1861 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 1862
fe56b6ce 1863 /* Two registers and a scalar. */
823d2571
TG		 1864 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1865 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1866 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1867 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1868 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1869 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1870 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1871 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1872 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1873 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1874 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1875 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1876 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1877 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1878 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1879 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1880 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1881 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1882 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1883 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1884 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1885 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1886 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1887 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1888 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1889 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1890 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1891 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1892 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1893 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1894 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1895 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1896 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1897 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1898 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1899 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1900 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1901 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1902 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1903 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1904 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1905 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1906 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1907 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1908 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1909 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1910 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1911 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1912 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1913 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1914 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1915 0xf2800240, 0xfe800f50,
1916 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1917 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1918 0xf2800640, 0xfe800f50,
1919 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1920 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1921 0xf2800a40, 0xfe800f50,
1922 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 1923 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1924 0xf2800e40, 0xff800f50,
1925 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1926 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1927 0xf2800f40, 0xff800f50,
1928 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1929 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1930 0xf3800e40, 0xff800f50,
1931 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1932 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1933 0xf3800f40, 0xff800f50,
1934 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1935 },
16980d0b 1936
fe56b6ce 1937 /* Element and structure load/store. */
823d2571
TG		 1938 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1939 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1940 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1941 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1942 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1943 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1944 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1945 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1946 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1947 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1948 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1949 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1950 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1951 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1952 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1953 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1954 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1955 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1956 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1957 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1958 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1959 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1960 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1961 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1962 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1963 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1964 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1965 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1966 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1967 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1968 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1969 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1970 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1971 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1972 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1973 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1974 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1975 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1976
1977 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 1978};
1979
73cd51e5
AV		 1980/* mve opcode table. */
1981
1982/* print_insn_mve recognizes the following format control codes:
1983
1984 %% %
1985
ef1576a1
AV		 1986 %a print '+' or '-' or imm offset in vldr[bhwd] and
1987 vstr[bhwd]
9743db03 1988 %c print condition code
aef6d006
AV		 1989 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
1990 %u print 'U' (unsigned) or 'S' for various mve instructions
143275ea 1991 %i print MVE predicate(s) for vpt and vpst
bf0b396d 1992 %m print rounding mode for vcvt and vrint
143275ea 1993 %n print vector comparison code for predicated instruction
bf0b396d 1994 %s print size for various vcvt instructions
143275ea
AV		 1995 %v print vector predicate for instruction in predicated
1996 block
ef1576a1 1997 %o print offset scaled for vldr[hwd] and vstr[hwd]
04d54ace
AV		 1998 %w print writeback mode for MVE v{st,ld}[24]
1999 %B print v{st,ld}[24] any one operands
c507f10b
AV		 2000 %E print vmov, vmvn, vorr, vbic encoded constant
2001 %N print generic index for vmov
14925797 2002 %T print bottom ('b') or top ('t') of source register
d3b63143 2003 %X print exchange field in vmla* instructions
04d54ace 2004
9743db03 2005 %<bitfield>r print as an ARM register
04d54ace 2006 %<bitfield>d print the bitfield in decimal
d3b63143 2007 %<bitfield>A print accumulate or not
143275ea 2008 %<bitfield>Q print as a MVE Q register
c507f10b 2009 %<bitfield>F print as a MVE S register
143275ea
AV		 2010 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
2011 UNPREDICTABLE
2012 %<bitfield>s print size for vector predicate & non VMOV instructions
66dcaa5d 2013 %<bitfield>I print carry flag or not
ef1576a1 2014 %<bitfield>i print immediate for vstr/vldr reg +/- imm
1c8f2df8 2015 %<bitfield>h print high half of 64-bit destination reg
bf0b396d 2016 %<bitfield>k print immediate for vector conversion instruction
1c8f2df8 2017 %<bitfield>l print low half of 64-bit destination reg
897b9bbc 2018 %<bitfield>o print rotate value for vcmul
1c8f2df8 2019 %<bitfield>u print immediate value for vddup/vdwdup
c507f10b 2020 %<bitfield>x print the bitfield in hex.
1c8f2df8 2021 */
73cd51e5
AV		 2022
2023static const struct mopcode32 mve_opcodes[] =
2024{
143275ea
AV		 2025 /* MVE. */
2026
2027 {ARM_FEATURE_COPROC (FPU_MVE),
2028 MVE_VPST,
2029 0xfe310f4d, 0xffbf1fff,
2030 "vpst%i"
2031 },
2032
2033 /* Floating point VPT T1. */
2034 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2035 MVE_VPT_FP_T1,
2036 0xee310f00, 0xefb10f50,
2037 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2038 /* Floating point VPT T2. */
2039 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2040 MVE_VPT_FP_T2,
2041 0xee310f40, 0xefb10f50,
2042 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2043
2044 /* Vector VPT T1. */
2045 {ARM_FEATURE_COPROC (FPU_MVE),
2046 MVE_VPT_VEC_T1,
2047 0xfe010f00, 0xff811f51,
2048 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2049 /* Vector VPT T2. */
2050 {ARM_FEATURE_COPROC (FPU_MVE),
2051 MVE_VPT_VEC_T2,
2052 0xfe010f01, 0xff811f51,
2053 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2054 /* Vector VPT T3. */
2055 {ARM_FEATURE_COPROC (FPU_MVE),
2056 MVE_VPT_VEC_T3,
2057 0xfe011f00, 0xff811f50,
2058 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2059 /* Vector VPT T4. */
2060 {ARM_FEATURE_COPROC (FPU_MVE),
2061 MVE_VPT_VEC_T4,
2062 0xfe010f40, 0xff811f70,
2063 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2064 /* Vector VPT T5. */
2065 {ARM_FEATURE_COPROC (FPU_MVE),
2066 MVE_VPT_VEC_T5,
2067 0xfe010f60, 0xff811f70,
2068 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2069 /* Vector VPT T6. */
2070 {ARM_FEATURE_COPROC (FPU_MVE),
2071 MVE_VPT_VEC_T6,
2072 0xfe011f40, 0xff811f50,
2073 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2074
c507f10b
AV		 2075 /* Vector VBIC immediate. */
2076 {ARM_FEATURE_COPROC (FPU_MVE),
2077 MVE_VBIC_IMM,
2078 0xef800070, 0xefb81070,
2079 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2080
2081 /* Vector VBIC register. */
2082 {ARM_FEATURE_COPROC (FPU_MVE),
2083 MVE_VBIC_REG,
2084 0xef100150, 0xffb11f51,
2085 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2086
66dcaa5d
AV		 2087 /* Vector VABAV. */
2088 {ARM_FEATURE_COPROC (FPU_MVE),
2089 MVE_VABAV,
2090 0xee800f01, 0xefc10f51,
2091 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2092
2093 /* Vector VABD floating point. */
2094 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2095 MVE_VABD_FP,
2096 0xff200d40, 0xffa11f51,
2097 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2098
2099 /* Vector VABD. */
2100 {ARM_FEATURE_COPROC (FPU_MVE),
2101 MVE_VABD_VEC,
2102 0xef000740, 0xef811f51,
2103 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2104
2105 /* Vector VABS floating point. */
2106 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2107 MVE_VABS_FP,
2108 0xFFB10740, 0xFFB31FD1,
2109 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2110 /* Vector VABS. */
2111 {ARM_FEATURE_COPROC (FPU_MVE),
2112 MVE_VABS_VEC,
2113 0xffb10340, 0xffb31fd1,
2114 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2115
2116 /* Vector VADD floating point T1. */
2117 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2118 MVE_VADD_FP_T1,
2119 0xef000d40, 0xffa11f51,
2120 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2121 /* Vector VADD floating point T2. */
2122 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2123 MVE_VADD_FP_T2,
2124 0xee300f40, 0xefb11f70,
2125 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2126 /* Vector VADD T1. */
2127 {ARM_FEATURE_COPROC (FPU_MVE),
2128 MVE_VADD_VEC_T1,
2129 0xef000840, 0xff811f51,
2130 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2131 /* Vector VADD T2. */
2132 {ARM_FEATURE_COPROC (FPU_MVE),
2133 MVE_VADD_VEC_T2,
2134 0xee010f40, 0xff811f70,
2135 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2136
d3b63143
AV		 2137 /* Vector VADDLV. */
2138 {ARM_FEATURE_COPROC (FPU_MVE),
2139 MVE_VADDLV,
2140 0xee890f00, 0xef8f1fd1,
2141 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2142
2143 /* Vector VADDV. */
2144 {ARM_FEATURE_COPROC (FPU_MVE),
2145 MVE_VADDV,
2146 0xeef10f00, 0xeff31fd1,
2147 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2148
66dcaa5d
AV		 2149 /* Vector VADC. */
2150 {ARM_FEATURE_COPROC (FPU_MVE),
2151 MVE_VADC,
2152 0xee300f00, 0xffb10f51,
2153 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2154
e523f101
AV		 2155 /* Vector VAND. */
2156 {ARM_FEATURE_COPROC (FPU_MVE),
2157 MVE_VAND,
2158 0xef000150, 0xffb11f51,
2159 "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2160
2161 /* Vector VBRSR register. */
2162 {ARM_FEATURE_COPROC (FPU_MVE),
2163 MVE_VBRSR,
2164 0xfe011e60, 0xff811f70,
2165 "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2166
897b9bbc
AV		 2167 /* Vector VCADD floating point. */
2168 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2169 MVE_VCADD_FP,
2170 0xfc800840, 0xfea11f51,
2171 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2172
2173 /* Vector VCADD. */
2174 {ARM_FEATURE_COPROC (FPU_MVE),
2175 MVE_VCADD_VEC,
2176 0xfe000f00, 0xff810f51,
2177 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2178
e523f101
AV		 2179 /* Vector VCLS. */
2180 {ARM_FEATURE_COPROC (FPU_MVE),
2181 MVE_VCLS,
2182 0xffb00440, 0xffb31fd1,
2183 "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2184
2185 /* Vector VCLZ. */
2186 {ARM_FEATURE_COPROC (FPU_MVE),
2187 MVE_VCLZ,
2188 0xffb004c0, 0xffb31fd1,
2189 "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2190
897b9bbc
AV		 2191 /* Vector VCMLA. */
2192 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2193 MVE_VCMLA_FP,
2194 0xfc200840, 0xfe211f51,
2195 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2196
143275ea
AV		 2197 /* Vector VCMP floating point T1. */
2198 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2199 MVE_VCMP_FP_T1,
2200 0xee310f00, 0xeff1ef50,
2201 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2202
2203 /* Vector VCMP floating point T2. */
2204 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2205 MVE_VCMP_FP_T2,
2206 0xee310f40, 0xeff1ef50,
2207 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2208
2209 /* Vector VCMP T1. */
2210 {ARM_FEATURE_COPROC (FPU_MVE),
2211 MVE_VCMP_VEC_T1,
2212 0xfe010f00, 0xffc1ff51,
2213 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2214 /* Vector VCMP T2. */
2215 {ARM_FEATURE_COPROC (FPU_MVE),
2216 MVE_VCMP_VEC_T2,
2217 0xfe010f01, 0xffc1ff51,
2218 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2219 /* Vector VCMP T3. */
2220 {ARM_FEATURE_COPROC (FPU_MVE),
2221 MVE_VCMP_VEC_T3,
2222 0xfe011f00, 0xffc1ff50,
2223 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2224 /* Vector VCMP T4. */
2225 {ARM_FEATURE_COPROC (FPU_MVE),
2226 MVE_VCMP_VEC_T4,
2227 0xfe010f40, 0xffc1ff70,
2228 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2229 /* Vector VCMP T5. */
2230 {ARM_FEATURE_COPROC (FPU_MVE),
2231 MVE_VCMP_VEC_T5,
2232 0xfe010f60, 0xffc1ff70,
2233 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2234 /* Vector VCMP T6. */
2235 {ARM_FEATURE_COPROC (FPU_MVE),
2236 MVE_VCMP_VEC_T6,
2237 0xfe011f40, 0xffc1ff50,
2238 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2239
9743db03
AV		 2240 /* Vector VDUP. */
2241 {ARM_FEATURE_COPROC (FPU_MVE),
2242 MVE_VDUP,
2243 0xeea00b10, 0xffb10f5f,
2244 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2245
2246 /* Vector VEOR. */
2247 {ARM_FEATURE_COPROC (FPU_MVE),
2248 MVE_VEOR,
2249 0xff000150, 0xffd11f51,
2250 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2251
2252 /* Vector VFMA, vector * scalar. */
2253 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2254 MVE_VFMA_FP_SCALAR,
2255 0xee310e40, 0xefb11f70,
2256 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2257
2258 /* Vector VFMA floating point. */
2259 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2260 MVE_VFMA_FP,
2261 0xef000c50, 0xffa11f51,
2262 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2263
2264 /* Vector VFMS floating point. */
2265 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2266 MVE_VFMS_FP,
2267 0xef200c50, 0xffa11f51,
2268 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2269
2270 /* Vector VFMAS, vector * scalar. */
2271 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2272 MVE_VFMAS_FP_SCALAR,
2273 0xee311e40, 0xefb11f70,
2274 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2275
2276 /* Vector VHADD T1. */
2277 {ARM_FEATURE_COPROC (FPU_MVE),
2278 MVE_VHADD_T1,
2279 0xef000040, 0xef811f51,
2280 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2281
2282 /* Vector VHADD T2. */
2283 {ARM_FEATURE_COPROC (FPU_MVE),
2284 MVE_VHADD_T2,
2285 0xee000f40, 0xef811f70,
2286 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2287
2288 /* Vector VHSUB T1. */
2289 {ARM_FEATURE_COPROC (FPU_MVE),
2290 MVE_VHSUB_T1,
2291 0xef000240, 0xef811f51,
2292 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2293
2294 /* Vector VHSUB T2. */
2295 {ARM_FEATURE_COPROC (FPU_MVE),
2296 MVE_VHSUB_T2,
2297 0xee001f40, 0xef811f70,
2298 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2299
897b9bbc
AV		 2300 /* Vector VCMUL. */
2301 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2302 MVE_VCMUL_FP,
2303 0xee300e00, 0xefb10f50,
2304 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2305
e523f101
AV		 2306 /* Vector VCTP. */
2307 {ARM_FEATURE_COPROC (FPU_MVE),
2308 MVE_VCTP,
2309 0xf000e801, 0xffc0ffff,
2310 "vctp%v.%20-21s\t%16-19r"},
2311
9743db03
AV		 2312 /* Vector VDUP. */
2313 {ARM_FEATURE_COPROC (FPU_MVE),
2314 MVE_VDUP,
2315 0xeea00b10, 0xffb10f5f,
2316 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2317
2318 /* Vector VRHADD. */
2319 {ARM_FEATURE_COPROC (FPU_MVE),
2320 MVE_VRHADD,
2321 0xef000140, 0xef811f51,
2322 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2323
bf0b396d
AV		 2324 /* Vector VCVT. */
2325 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2326 MVE_VCVT_FP_FIX_VEC,
2327 0xef800c50, 0xef801cd1,
2328 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2329
2330 /* Vector VCVT. */
2331 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2332 MVE_VCVT_BETWEEN_FP_INT,
2333 0xffb30640, 0xffb31e51,
2334 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2335
2336 /* Vector VCVT between single and half-precision float, bottom half. */
2337 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2338 MVE_VCVT_FP_HALF_FP,
2339 0xee3f0e01, 0xefbf1fd1,
2340 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2341
2342 /* Vector VCVT between single and half-precision float, top half. */
2343 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2344 MVE_VCVT_FP_HALF_FP,
2345 0xee3f1e01, 0xefbf1fd1,
2346 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2347
2348 /* Vector VCVT. */
2349 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2350 MVE_VCVT_FROM_FP_TO_INT,
2351 0xffb30040, 0xffb31c51,
2352 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2353
1c8f2df8
AV		 2354 /* Vector VDDUP. */
2355 {ARM_FEATURE_COPROC (FPU_MVE),
2356 MVE_VDDUP,
2357 0xee011f6e, 0xff811f7e,
2358 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2359
2360 /* Vector VDWDUP. */
2361 {ARM_FEATURE_COPROC (FPU_MVE),
2362 MVE_VDWDUP,
2363 0xee011f60, 0xff811f70,
2364 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2365
897b9bbc
AV		 2366 /* Vector VHCADD. */
2367 {ARM_FEATURE_COPROC (FPU_MVE),
2368 MVE_VHCADD,
2369 0xee000f00, 0xff810f51,
2370 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2371
1c8f2df8
AV		 2372 /* Vector VIWDUP. */
2373 {ARM_FEATURE_COPROC (FPU_MVE),
2374 MVE_VIWDUP,
2375 0xee010f60, 0xff811f70,
2376 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2377
2378 /* Vector VIDUP. */
2379 {ARM_FEATURE_COPROC (FPU_MVE),
2380 MVE_VIDUP,
2381 0xee010f6e, 0xff811f7e,
2382 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2383
04d54ace
AV		 2384 /* Vector VLD2. */
2385 {ARM_FEATURE_COPROC (FPU_MVE),
2386 MVE_VLD2,
2387 0xfc901e00, 0xff901e5f,
2388 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2389
2390 /* Vector VLD4. */
2391 {ARM_FEATURE_COPROC (FPU_MVE),
2392 MVE_VLD4,
2393 0xfc901e01, 0xff901e1f,
2394 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2395
ef1576a1
AV		 2396 /* Vector VLDRB gather load. */
2397 {ARM_FEATURE_COPROC (FPU_MVE),
2398 MVE_VLDRB_GATHER_T1,
2399 0xec900e00, 0xefb01e50,
2400 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2401
2402 /* Vector VLDRH gather load. */
2403 {ARM_FEATURE_COPROC (FPU_MVE),
2404 MVE_VLDRH_GATHER_T2,
2405 0xec900e10, 0xefb01e50,
2406 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2407
2408 /* Vector VLDRW gather load. */
2409 {ARM_FEATURE_COPROC (FPU_MVE),
2410 MVE_VLDRW_GATHER_T3,
2411 0xfc900f40, 0xffb01fd0,
2412 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2413
2414 /* Vector VLDRD gather load. */
2415 {ARM_FEATURE_COPROC (FPU_MVE),
2416 MVE_VLDRD_GATHER_T4,
2417 0xec900fd0, 0xefb01fd0,
2418 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2419
2420 /* Vector VLDRW gather load. */
2421 {ARM_FEATURE_COPROC (FPU_MVE),
2422 MVE_VLDRW_GATHER_T5,
2423 0xfd101e00, 0xff111f00,
2424 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2425
2426 /* Vector VLDRD gather load, variant T6. */
2427 {ARM_FEATURE_COPROC (FPU_MVE),
2428 MVE_VLDRD_GATHER_T6,
2429 0xfd101f00, 0xff111f00,
2430 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2431
aef6d006
AV		 2432 /* Vector VLDRB. */
2433 {ARM_FEATURE_COPROC (FPU_MVE),
2434 MVE_VLDRB_T1,
2435 0xec100e00, 0xee581e00,
2436 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2437
2438 /* Vector VLDRH. */
2439 {ARM_FEATURE_COPROC (FPU_MVE),
2440 MVE_VLDRH_T2,
2441 0xec180e00, 0xee581e00,
2442 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2443
2444 /* Vector VLDRB unsigned, variant T5. */
2445 {ARM_FEATURE_COPROC (FPU_MVE),
2446 MVE_VLDRB_T5,
2447 0xec101e00, 0xfe101f80,
2448 "vldrb%v.u8\t%13-15,22Q, %d"},
2449
2450 /* Vector VLDRH unsigned, variant T6. */
2451 {ARM_FEATURE_COPROC (FPU_MVE),
2452 MVE_VLDRH_T6,
2453 0xec101e80, 0xfe101f80,
2454 "vldrh%v.u16\t%13-15,22Q, %d"},
2455
2456 /* Vector VLDRW unsigned, variant T7. */
2457 {ARM_FEATURE_COPROC (FPU_MVE),
2458 MVE_VLDRW_T7,
2459 0xec101f00, 0xfe101f80,
2460 "vldrw%v.u32\t%13-15,22Q, %d"},
2461
d3b63143
AV		 2462 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2463 opcode aliasing. */
2464 {ARM_FEATURE_COPROC (FPU_MVE),
2465 MVE_VMLALDAV,
2466 0xee801e00, 0xef801f51,
2467 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2468
2469 {ARM_FEATURE_COPROC (FPU_MVE),
2470 MVE_VMLALDAV,
2471 0xee800e00, 0xef801f51,
2472 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2473
2474 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2475 {ARM_FEATURE_COPROC (FPU_MVE),
2476 MVE_VMLADAV_T1,
2477 0xeef00e00, 0xeff01f51,
2478 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2479
2480 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2481 {ARM_FEATURE_COPROC (FPU_MVE),
2482 MVE_VMLADAV_T2,
2483 0xeef00f00, 0xeff11f51,
2484 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2485
2486 /* Vector VMLADAV T1 variant. */
2487 {ARM_FEATURE_COPROC (FPU_MVE),
2488 MVE_VMLADAV_T1,
2489 0xeef01e00, 0xeff01f51,
2490 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2491
2492 /* Vector VMLADAV T2 variant. */
2493 {ARM_FEATURE_COPROC (FPU_MVE),
2494 MVE_VMLADAV_T2,
2495 0xeef01f00, 0xeff11f51,
2496 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2497
2498 /* Vector VMLAS. */
2499 {ARM_FEATURE_COPROC (FPU_MVE),
2500 MVE_VMLAS,
2501 0xee011e40, 0xef811f70,
2502 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2503
2504 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2505 opcode aliasing. */
2506 {ARM_FEATURE_COPROC (FPU_MVE),
2507 MVE_VRMLSLDAVH,
2508 0xfe800e01, 0xff810f51,
2509 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2510
2511 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2512 opcdoe aliasing. */
2513 {ARM_FEATURE_COPROC (FPU_MVE),
2514 MVE_VMLSLDAV,
2515 0xee800e01, 0xff800f51,
2516 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2517
2518 /* Vector VMLSDAV T1 Variant. */
2519 {ARM_FEATURE_COPROC (FPU_MVE),
2520 MVE_VMLSDAV_T1,
2521 0xeef00e01, 0xfff00f51,
2522 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2523
2524 /* Vector VMLSDAV T2 Variant. */
2525 {ARM_FEATURE_COPROC (FPU_MVE),
2526 MVE_VMLSDAV_T2,
2527 0xfef00e01, 0xfff10f51,
2528 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2529
c507f10b
AV		 2530 /* Vector VMOV between gpr and half precision register, op == 0. */
2531 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2532 MVE_VMOV_HFP_TO_GP,
2533 0xee000910, 0xfff00f7f,
2534 "vmov.f16\t%7,16-19F, %12-15r"},
2535
2536 /* Vector VMOV between gpr and half precision register, op == 1. */
2537 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2538 MVE_VMOV_HFP_TO_GP,
2539 0xee100910, 0xfff00f7f,
2540 "vmov.f16\t%12-15r, %7,16-19F"},
2541
2542 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2543 MVE_VMOV_GP_TO_VEC_LANE,
2544 0xee000b10, 0xff900f1f,
2545 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2546
2547 /* Vector VORR immediate to vector.
2548 NOTE: MVE_VORR_IMM must appear in the table
2549 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2550 {ARM_FEATURE_COPROC (FPU_MVE),
2551 MVE_VORR_IMM,
2552 0xef800050, 0xefb810f0,
2553 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2554
ed63aa17
AV		 2555 /* Vector VQSHL T2 Variant.
2556 NOTE: MVE_VQSHL_T2 must appear in the table before
2557 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2558 {ARM_FEATURE_COPROC (FPU_MVE),
2559 MVE_VQSHL_T2,
2560 0xef800750, 0xef801fd1,
2561 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2562
2563 /* Vector VQSHLU T3 Variant
2564 NOTE: MVE_VQSHL_T2 must appear in the table before
2565 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2566
2567 {ARM_FEATURE_COPROC (FPU_MVE),
2568 MVE_VQSHLU_T3,
2569 0xff800650, 0xff801fd1,
2570 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2571
2572 /* Vector VRSHR
2573 NOTE: MVE_VRSHR must appear in the table before
2574 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2575 {ARM_FEATURE_COPROC (FPU_MVE),
2576 MVE_VRSHR,
2577 0xef800250, 0xef801fd1,
2578 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2579
2580 /* Vector VSHL.
2581 NOTE: MVE_VSHL must appear in the table before
2582 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2583 {ARM_FEATURE_COPROC (FPU_MVE),
2584 MVE_VSHL_T1,
2585 0xef800550, 0xff801fd1,
2586 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2587
2588 /* Vector VSHR
2589 NOTE: MVE_VSHR must appear in the table before
2590 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2591 {ARM_FEATURE_COPROC (FPU_MVE),
2592 MVE_VSHR,
2593 0xef800050, 0xef801fd1,
2594 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2595
2596 /* Vector VSLI
2597 NOTE: MVE_VSLI must appear in the table before
2598 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2599 {ARM_FEATURE_COPROC (FPU_MVE),
2600 MVE_VSLI,
2601 0xff800550, 0xff801fd1,
2602 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2603
2604 /* Vector VSRI
2605 NOTE: MVE_VSRI must appear in the table before
2606 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2607 {ARM_FEATURE_COPROC (FPU_MVE),
2608 MVE_VSRI,
2609 0xff800450, 0xff801fd1,
2610 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2611
c507f10b
AV		 2612 /* Vector VMOV immediate to vector,
2613 cmode == 11x1 -> VMVN which is UNDEFINED
2614 for such a cmode. */
2615 {ARM_FEATURE_COPROC (FPU_MVE),
2616 MVE_VMVN_IMM, 0xef800d50, 0xefb81dd0, UNDEFINED_INSTRUCTION},
2617
2618 /* Vector VMOV immediate to vector. */
2619 {ARM_FEATURE_COPROC (FPU_MVE),
2620 MVE_VMOV_IMM_TO_VEC,
2621 0xef800050, 0xefb810d0,
2622 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2623
2624 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2625 {ARM_FEATURE_COPROC (FPU_MVE),
2626 MVE_VMOV2_VEC_LANE_TO_GP,
2627 0xec000f00, 0xffb01ff0,
2628 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2629
2630 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2631 {ARM_FEATURE_COPROC (FPU_MVE),
2632 MVE_VMOV2_VEC_LANE_TO_GP,
2633 0xec000f10, 0xffb01ff0,
2634 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2635
2636 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2637 {ARM_FEATURE_COPROC (FPU_MVE),
2638 MVE_VMOV2_GP_TO_VEC_LANE,
2639 0xec100f00, 0xffb01ff0,
2640 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2641
2642 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2643 {ARM_FEATURE_COPROC (FPU_MVE),
2644 MVE_VMOV2_GP_TO_VEC_LANE,
2645 0xec100f10, 0xffb01ff0,
2646 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2647
2648 /* Vector VMOV Vector lane to gpr. */
2649 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2650 MVE_VMOV_VEC_LANE_TO_GP,
2651 0xee100b10, 0xff100f1f,
2652 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2653
ed63aa17
AV		 2654 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
2655 to instruction opcode aliasing. */
2656 {ARM_FEATURE_COPROC (FPU_MVE),
2657 MVE_VSHLL_T1,
2658 0xeea00f40, 0xefa00fd1,
2659 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2660
14925797
AV		 2661 /* Vector VMOVL long. */
2662 {ARM_FEATURE_COPROC (FPU_MVE),
2663 MVE_VMOVL,
2664 0xeea00f40, 0xefa70fd1,
2665 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2666
2667 /* Vector VMOV and narrow. */
2668 {ARM_FEATURE_COPROC (FPU_MVE),
2669 MVE_VMOVN,
2670 0xfe310e81, 0xffb30fd1,
2671 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2672
c507f10b
AV		 2673 /* Floating point move extract. */
2674 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2675 MVE_VMOVX,
2676 0xfeb00a40, 0xffbf0fd0,
2677 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2678
14925797
AV		 2679 /* Vector VMULL integer. */
2680 {ARM_FEATURE_COPROC (FPU_MVE),
2681 MVE_VMULL_INT,
2682 0xee010e00, 0xef810f51,
2683 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2684
2685 /* Vector VMULL polynomial. */
2686 {ARM_FEATURE_COPROC (FPU_MVE),
2687 MVE_VMULL_POLY,
2688 0xee310e00, 0xefb10f51,
2689 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2690
c507f10b
AV		 2691 /* Vector VMVN immediate to vector. */
2692 {ARM_FEATURE_COPROC (FPU_MVE),
2693 MVE_VMVN_IMM,
2694 0xef800070, 0xefb810f0,
2695 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2696
2697 /* Vector VMVN register. */
2698 {ARM_FEATURE_COPROC (FPU_MVE),
2699 MVE_VMVN_REG,
2700 0xffb005c0, 0xffbf1fd1,
2701 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2702
2703 /* Vector VORN, vector bitwise or not. */
2704 {ARM_FEATURE_COPROC (FPU_MVE),
2705 MVE_VORN,
2706 0xef300150, 0xffb11f51,
2707 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2708
2709 /* Vector VORR register. */
2710 {ARM_FEATURE_COPROC (FPU_MVE),
2711 MVE_VORR_REG,
2712 0xef200150, 0xffb11f51,
2713 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2714
14925797
AV		 2715 /* Vector VQDMULL T1 variant. */
2716 {ARM_FEATURE_COPROC (FPU_MVE),
2717 MVE_VQDMULL_T1,
2718 0xee300f01, 0xefb10f51,
2719 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2720
2721 /* Vector VQDMULL T2 variant. */
2722 {ARM_FEATURE_COPROC (FPU_MVE),
2723 MVE_VQDMULL_T2,
2724 0xee300f60, 0xefb10f70,
2725 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2726
2727 /* Vector VQMOVN. */
2728 {ARM_FEATURE_COPROC (FPU_MVE),
2729 MVE_VQMOVN,
2730 0xee330e01, 0xefb30fd1,
2731 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
2732
2733 /* Vector VQMOVUN. */
2734 {ARM_FEATURE_COPROC (FPU_MVE),
2735 MVE_VQMOVUN,
2736 0xee310e81, 0xffb30fd1,
2737 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2738
d3b63143
AV		 2739 /* Vector VQDMLADH. */
2740 {ARM_FEATURE_COPROC (FPU_MVE),
2741 MVE_VQDMLADH,
2742 0xee000e00, 0xff810f51,
2743 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2744
2745 /* Vector VQRDMLADH. */
2746 {ARM_FEATURE_COPROC (FPU_MVE),
2747 MVE_VQRDMLADH,
2748 0xee000e01, 0xff810f51,
2749 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2750
2751 /* Vector VQDMLAH. */
2752 {ARM_FEATURE_COPROC (FPU_MVE),
2753 MVE_VQDMLAH,
2754 0xee000e60, 0xef811f70,
2755 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2756
2757 /* Vector VQRDMLAH. */
2758 {ARM_FEATURE_COPROC (FPU_MVE),
2759 MVE_VQRDMLAH,
2760 0xee000e40, 0xef811f70,
2761 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2762
2763 /* Vector VQDMLASH. */
2764 {ARM_FEATURE_COPROC (FPU_MVE),
2765 MVE_VQDMLASH,
2766 0xee001e60, 0xef811f70,
2767 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2768
2769 /* Vector VQRDMLASH. */
2770 {ARM_FEATURE_COPROC (FPU_MVE),
2771 MVE_VQRDMLASH,
2772 0xee001e40, 0xef811f70,
2773 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2774
2775 /* Vector VQDMLSDH. */
2776 {ARM_FEATURE_COPROC (FPU_MVE),
2777 MVE_VQDMLSDH,
2778 0xfe000e00, 0xff810f51,
2779 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2780
2781 /* Vector VQRDMLSDH. */
2782 {ARM_FEATURE_COPROC (FPU_MVE),
2783 MVE_VQRDMLSDH,
2784 0xfe000e01, 0xff810f51,
2785 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2786
2787 /* Vector VQDMULH T1 variant. */
2788 {ARM_FEATURE_COPROC (FPU_MVE),
2789 MVE_VQDMULH_T1,
2790 0xef000b40, 0xff811f51,
2791 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2792
2793 /* Vector VQRDMULH T2 variant. */
2794 {ARM_FEATURE_COPROC (FPU_MVE),
2795 MVE_VQRDMULH_T2,
2796 0xff000b40, 0xff811f51,
2797 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2798
2799 /* Vector VQDMULH T3 variant. */
2800 {ARM_FEATURE_COPROC (FPU_MVE),
2801 MVE_VQDMULH_T3,
2802 0xee010e60, 0xff811f70,
2803 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2804
2805 /* Vector VQRDMULH T4 variant. */
2806 {ARM_FEATURE_COPROC (FPU_MVE),
2807 MVE_VQRDMULH_T4,
2808 0xfe010e60, 0xff811f70,
2809 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2810
ed63aa17
AV		 2811 /* Vector VQRSHL T1 variant. */
2812 {ARM_FEATURE_COPROC (FPU_MVE),
2813 MVE_VQRSHL_T1,
2814 0xef000550, 0xef811f51,
2815 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
2816
2817 /* Vector VQRSHL T2 variant. */
2818 {ARM_FEATURE_COPROC (FPU_MVE),
2819 MVE_VQRSHL_T2,
2820 0xee331ee0, 0xefb31ff0,
2821 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
2822
2823 /* Vector VQRSHRN. */
2824 {ARM_FEATURE_COPROC (FPU_MVE),
2825 MVE_VQRSHRN,
2826 0xee800f41, 0xefa00fd1,
2827 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2828
2829 /* Vector VQRSHRUN. */
2830 {ARM_FEATURE_COPROC (FPU_MVE),
2831 MVE_VQRSHRUN,
2832 0xfe800fc0, 0xffa00fd1,
2833 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2834
2835 /* Vector VQSHL T1 Variant. */
2836 {ARM_FEATURE_COPROC (FPU_MVE),
2837 MVE_VQSHL_T1,
2838 0xee311ee0, 0xefb31ff0,
2839 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
2840
2841 /* Vector VQSHL T4 Variant. */
2842 {ARM_FEATURE_COPROC (FPU_MVE),
2843 MVE_VQSHL_T4,
2844 0xef000450, 0xef811f51,
2845 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
2846
2847 /* Vector VQSHRN. */
2848 {ARM_FEATURE_COPROC (FPU_MVE),
2849 MVE_VQSHRN,
2850 0xee800f40, 0xefa00fd1,
2851 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2852
2853 /* Vector VQSHRUN. */
2854 {ARM_FEATURE_COPROC (FPU_MVE),
2855 MVE_VQSHRUN,
2856 0xee800fc0, 0xffa00fd1,
2857 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2858
bf0b396d
AV		 2859 /* Vector VRINT floating point. */
2860 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2861 MVE_VRINT_FP,
2862 0xffb20440, 0xffb31c51,
2863 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2864
d3b63143
AV		 2865 /* Vector VRMLALDAVH. */
2866 {ARM_FEATURE_COPROC (FPU_MVE),
2867 MVE_VRMLALDAVH,
2868 0xee800f00, 0xef811f51,
2869 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2870
2871 /* Vector VRMLALDAVH. */
2872 {ARM_FEATURE_COPROC (FPU_MVE),
2873 MVE_VRMLALDAVH,
2874 0xee801f00, 0xef811f51,
2875 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2876
ed63aa17
AV		 2877 /* Vector VRSHL T1 Variant. */
2878 {ARM_FEATURE_COPROC (FPU_MVE),
2879 MVE_VRSHL_T1,
2880 0xef000540, 0xef811f51,
2881 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
2882
2883 /* Vector VRSHL T2 Variant. */
2884 {ARM_FEATURE_COPROC (FPU_MVE),
2885 MVE_VRSHL_T2,
2886 0xee331e60, 0xefb31ff0,
2887 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
2888
2889 /* Vector VRSHRN. */
2890 {ARM_FEATURE_COPROC (FPU_MVE),
2891 MVE_VRSHRN,
2892 0xfe800fc1, 0xffa00fd1,
2893 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2894
66dcaa5d
AV		 2895 /* Vector VSBC. */
2896 {ARM_FEATURE_COPROC (FPU_MVE),
2897 MVE_VSBC,
2898 0xfe300f00, 0xffb10f51,
2899 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2900
ed63aa17
AV		 2901 /* Vector VSHL T2 Variant. */
2902 {ARM_FEATURE_COPROC (FPU_MVE),
2903 MVE_VSHL_T2,
2904 0xee311e60, 0xefb31ff0,
2905 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
2906
2907 /* Vector VSHL T3 Variant. */
2908 {ARM_FEATURE_COPROC (FPU_MVE),
2909 MVE_VSHL_T3,
2910 0xef000440, 0xef811f51,
2911 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
2912
2913 /* Vector VSHLC. */
2914 {ARM_FEATURE_COPROC (FPU_MVE),
2915 MVE_VSHLC,
2916 0xeea00fc0, 0xffa01ff0,
2917 "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
2918
2919 /* Vector VSHLL T2 Variant. */
2920 {ARM_FEATURE_COPROC (FPU_MVE),
2921 MVE_VSHLL_T2,
2922 0xee310e01, 0xefb30fd1,
2923 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
2924
2925 /* Vector VSHRN. */
2926 {ARM_FEATURE_COPROC (FPU_MVE),
2927 MVE_VSHRN,
2928 0xee800fc1, 0xffa00fd1,
2929 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2930
04d54ace
AV		 2931 /* Vector VST2 no writeback. */
2932 {ARM_FEATURE_COPROC (FPU_MVE),
2933 MVE_VST2,
2934 0xfc801e00, 0xffb01e5f,
2935 "vst2%5d.%7-8s\t%B, [%16-19r]"},
2936
2937 /* Vector VST2 writeback. */
2938 {ARM_FEATURE_COPROC (FPU_MVE),
2939 MVE_VST2,
2940 0xfca01e00, 0xffb01e5f,
2941 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
2942
2943 /* Vector VST4 no writeback. */
2944 {ARM_FEATURE_COPROC (FPU_MVE),
2945 MVE_VST4,
2946 0xfc801e01, 0xffb01e1f,
2947 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
2948
2949 /* Vector VST4 writeback. */
2950 {ARM_FEATURE_COPROC (FPU_MVE),
2951 MVE_VST4,
2952 0xfca01e01, 0xffb01e1f,
2953 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
2954
ef1576a1
AV		 2955 /* Vector VSTRB scatter store, T1 variant. */
2956 {ARM_FEATURE_COPROC (FPU_MVE),
2957 MVE_VSTRB_SCATTER_T1,
2958 0xec800e00, 0xffb01e50,
2959 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2960
2961 /* Vector VSTRH scatter store, T2 variant. */
2962 {ARM_FEATURE_COPROC (FPU_MVE),
2963 MVE_VSTRH_SCATTER_T2,
2964 0xec800e10, 0xffb01e50,
2965 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2966
2967 /* Vector VSTRW scatter store, T3 variant. */
2968 {ARM_FEATURE_COPROC (FPU_MVE),
2969 MVE_VSTRW_SCATTER_T3,
2970 0xec800e40, 0xffb01e50,
2971 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2972
2973 /* Vector VSTRD scatter store, T4 variant. */
2974 {ARM_FEATURE_COPROC (FPU_MVE),
2975 MVE_VSTRD_SCATTER_T4,
2976 0xec800fd0, 0xffb01fd0,
2977 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2978
2979 /* Vector VSTRW scatter store, T5 variant. */
2980 {ARM_FEATURE_COPROC (FPU_MVE),
2981 MVE_VSTRW_SCATTER_T5,
2982 0xfd001e00, 0xff111f00,
2983 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2984
2985 /* Vector VSTRD scatter store, T6 variant. */
2986 {ARM_FEATURE_COPROC (FPU_MVE),
2987 MVE_VSTRD_SCATTER_T6,
2988 0xfd001f00, 0xff111f00,
2989 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2990
aef6d006
AV		 2991 /* Vector VSTRB. */
2992 {ARM_FEATURE_COPROC (FPU_MVE),
2993 MVE_VSTRB_T1,
2994 0xec000e00, 0xfe581e00,
2995 "vstrb%v.%7-8s\t%13-15Q, %d"},
2996
2997 /* Vector VSTRH. */
2998 {ARM_FEATURE_COPROC (FPU_MVE),
2999 MVE_VSTRH_T2,
3000 0xec080e00, 0xfe581e00,
3001 "vstrh%v.%7-8s\t%13-15Q, %d"},
3002
3003 /* Vector VSTRB variant T5. */
3004 {ARM_FEATURE_COPROC (FPU_MVE),
3005 MVE_VSTRB_T5,
3006 0xec001e00, 0xfe101f80,
3007 "vstrb%v.8\t%13-15,22Q, %d"},
3008
3009 /* Vector VSTRH variant T6. */
3010 {ARM_FEATURE_COPROC (FPU_MVE),
3011 MVE_VSTRH_T6,
3012 0xec001e80, 0xfe101f80,
3013 "vstrh%v.16\t%13-15,22Q, %d"},
3014
3015 /* Vector VSTRW variant T7. */
3016 {ARM_FEATURE_COPROC (FPU_MVE),
3017 MVE_VSTRW_T7,
3018 0xec001f00, 0xfe101f80,
3019 "vstrw%v.32\t%13-15,22Q, %d"},
3020
66dcaa5d
AV		 3021 /* Vector VSUB floating point T1 variant. */
3022 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3023 MVE_VSUB_FP_T1,
3024 0xef200d40, 0xffa11f51,
3025 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3026
3027 /* Vector VSUB floating point T2 variant. */
3028 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3029 MVE_VSUB_FP_T2,
3030 0xee301f40, 0xefb11f70,
3031 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3032
3033 /* Vector VSUB T1 variant. */
3034 {ARM_FEATURE_COPROC (FPU_MVE),
3035 MVE_VSUB_VEC_T1,
3036 0xff000840, 0xff811f51,
3037 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3038
3039 /* Vector VSUB T2 variant. */
3040 {ARM_FEATURE_COPROC (FPU_MVE),
3041 MVE_VSUB_VEC_T2,
3042 0xee011f40, 0xff811f70,
3043 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3044
143275ea
AV		 3045 {ARM_FEATURE_CORE_LOW (0),
3046 MVE_NONE,
3047 0x00000000, 0x00000000, 0}
73cd51e5
AV		 3048};
3049
8f06b2d8
PB		 3050/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
3051 ordered: they must be searched linearly from the top to obtain a correct
3052 match. */
3053
3054/* print_insn_arm recognizes the following format control codes:
3055
3056 %% %
3057
3058 %a print address for ldr/str instruction
3059 %s print address for ldr/str halfword/signextend instruction
c1e26897 3060 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 3061 %b print branch destination
3062 %c print condition code (always bits 28-31)
3063 %m print register mask for ldm/stm instruction
3064 %o print operand2 (immediate or register + shift)
3065 %p print 'p' iff bits 12-15 are 15
3066 %t print 't' iff bit 21 set and bit 24 clear
3067 %B print arm BLX(1) destination
3068 %C print the PSR sub type.
62b3e311
PB		 3069 %U print barrier type.
3070 %P print address for pli instruction.
8f06b2d8
PB		 3071
3072 %<bitfield>r print as an ARM register
9eb6c0f1 3073 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 3074 %<bitfield>R as %r but r15 is UNPREDICTABLE
3075 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3076 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 3077 %<bitfield>d print the bitfield in decimal
43e65147 3078 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 3079 %<bitfield>x print the bitfield in hex
3080 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 3081
16980d0b
JB		 3082 %<bitfield>'c print specified char iff bitfield is all ones
3083 %<bitfield>`c print specified char iff bitfield is all zeroes
3084 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 3085
8f06b2d8
PB		 3086 %e print arm SMI operand (bits 0..7,8..19).
3087 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 3088 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
3089 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 3090
8f06b2d8
PB		 3091static const struct opcode32 arm_opcodes[] =
3092{
3093 /* ARM instructions. */
823d2571
TG		 3094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3095 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
3096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3097 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
3098
3099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
3100 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3102 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3104 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
3106 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3108 0x00800090, 0x0fa000f0,
3109 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3111 0x00a00090, 0x0fa000f0,
3112 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 3113
105bde57 3114 /* V8.2 RAS extension instructions. */
4d1464f2 3115 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 3116 0xe320f010, 0xffffffff, "esb"},
3117
53c4b28b 3118 /* V8 instructions. */
823d2571
TG		 3119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3120 0x0320f005, 0x0fffffff, "sevl"},
f7dd2fb2
TC		 3121 /* Defined in V8 but is in NOP space so available to all arch. */
3122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
823d2571 3123 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
4ed7ed8d 3124 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 3125 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3126 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 3127 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3129 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3131 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 3132 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3133 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3134 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3135 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3136 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3137 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3138 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3139 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3140 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3141 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3142 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3143 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3144 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3145 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3146 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3147 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3148 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3149 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3150 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 3151 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 3152 /* CRC32 instructions. */
823d2571
TG		 3153 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3154 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
3155 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3156 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
3157 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3158 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
3159 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3160 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
3161 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3162 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
3163 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3164 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 3165
ddfded2f
MW		 3166 /* Privileged Access Never extension instructions. */
3167 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
3168 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
3169
90ec0d68 3170 /* Virtualization Extension instructions. */
823d2571
TG		 3171 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
3172 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 3173
eea54501 3174 /* Integer Divide Extension instructions. */
823d2571
TG		 3175 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3176 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3177 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3178 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 3179
60e5ef9f 3180 /* MP Extension instructions. */
823d2571 3181 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 3182
c597cc3d
SD		 3183 /* Speculation Barriers. */
3184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
3185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
3186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
3187
62b3e311 3188 /* V7 instructions. */
823d2571
TG		 3189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
3190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
3191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a
AV		 3196 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3197 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
62b3e311 3198
c19d1205 3199 /* ARM V6T2 instructions. */
823d2571
TG		 3200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3201 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3203 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3205 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3207 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3208
3209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3210 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
3211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3212 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3213
ff8646ee 3214 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 3215 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 3216 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3217 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3219 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3221 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 3222
f4c65163 3223 /* ARM Security extension instructions. */
823d2571
TG		 3224 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
3225 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 3226
8f06b2d8 3227 /* ARM V6K instructions. */
823d2571
TG		 3228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3229 0xf57ff01f, 0xffffffff, "clrex"},
3230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3231 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3233 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3235 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3237 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3238 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3239 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3240 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3241 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 3242
7fadb25d
SD		 3243 /* ARMv8.5-A instructions. */
3244 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
3245
8f06b2d8 3246 /* ARM V6K NOP hints. */
823d2571
TG		 3247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3248 0x0320f001, 0x0fffffff, "yield%c"},
3249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3250 0x0320f002, 0x0fffffff, "wfe%c"},
3251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3252 0x0320f003, 0x0fffffff, "wfi%c"},
3253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3254 0x0320f004, 0x0fffffff, "sev%c"},
3255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3256 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 3257
fe56b6ce 3258 /* ARM V6 instructions. */
823d2571
TG		 3259 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3260 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
3261 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3262 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
3263 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3264 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
3265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3266 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
3267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3268 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
3269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3270 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3272 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
3273 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3274 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
3275 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3276 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
3277 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3278 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
3279 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3280 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3281 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3282 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3283 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3284 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3285 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3286 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3287 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3288 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3289 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3290 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3292 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3294 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3295 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3296 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3297 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3298 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3299 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3300 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3301 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3302 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3304 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3305 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3306 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3307 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3308 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3310 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3312 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3314 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3315 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3316 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3317 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3318 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3320 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3322 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3323 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3324 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3325 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3326 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3327 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3328 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3329 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3330 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3331 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3332 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3334 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3336 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3338 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3339 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3340 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3341 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3342 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3343 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3344 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3345 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3346 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3348 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3350 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3352 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3354 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3356 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3358 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3360 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3362 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3364 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3366 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3368 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3370 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3372 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3374 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3376 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3378 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3380 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3382 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3384 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3386 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3388 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3390 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3392 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3394 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3395 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3396 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3397 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3398 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3399 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3400 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3401 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3402 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3403 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3404 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3406 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3408 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3410 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3411 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3412 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3413 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3414 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3415 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3416 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3418 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3419 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3420 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3422 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3424 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3425 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3426 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3427 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3428 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3429 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3430 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3431 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3432 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3433 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3434 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3435 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3436 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3437 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3438 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3439 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3440 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3441 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3442 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3443 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3444 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3446 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
3447 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3448 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3450 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3451 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3452 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3453 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3454 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3455 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3456 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
3457 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3458 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
3459 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3460 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
3461 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3462 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
3463 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3464 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3465 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3466 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3467 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3468 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3469 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3470 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3471 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3472 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
3473 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3474 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3475 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3476 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3477 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3478 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
3479 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3480 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
3481 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3482 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
3483 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3484 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
3485 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3486 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
3487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3488 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
3489 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3490 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
3491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3492 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
3493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3494 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3495 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3496 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
3497 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3498 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
3499 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3500 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
3501 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3502 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 3503
8f06b2d8 3504 /* V5J instruction. */
823d2571
TG		 3505 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
3506 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 3507
8f06b2d8 3508 /* V5 Instructions. */
823d2571
TG		 3509 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3510 0xe1200070, 0xfff000f0,
3511 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
3512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3513 0xfa000000, 0xfe000000, "blx\t%B"},
3514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3515 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
3516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3517 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
3518
3519 /* V5E "El Segundo" Instructions. */
3520 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3521 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
3522 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3523 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
3524 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3525 0xf450f000, 0xfc70f000, "pld\t%a"},
3526 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3527 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3528 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3529 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3531 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3533 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
3534
3535 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3536 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3537 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3538 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
3539
3540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3541 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3543 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3545 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3547 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3548
3549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3550 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
3551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3552 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
3553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3554 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
3555 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3556 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
3557
3558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3559 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
3560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3561 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
3562
3563 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3564 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
3565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3566 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
3567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3568 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
3569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3570 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 3571
8f06b2d8 3572 /* ARM Instructions. */
823d2571
TG		 3573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3574 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
3575
3576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3577 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
3578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3579 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
3580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3581 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
3582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3583 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
3584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3585 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
3586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3587 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
3588
3589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3590 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
3591 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3592 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
3593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3594 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
3595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3596 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
3597
3598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3599 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
3600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3601 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
3602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3603 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
3604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3605 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
3606
3607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3608 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
3609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3610 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
3611 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3612 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
3613
3614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3615 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
3616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3617 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
3618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3619 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
3620
3621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3622 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
3623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3624 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
3625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3626 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
3627
3628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3629 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3631 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3633 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
3634
3635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3636 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
3637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3638 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
3639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3640 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
3641
3642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3643 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
3644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3645 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
3646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3647 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
3648
3649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3650 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3652 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3654 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
3655
3656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3657 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3658 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3659 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3661 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
3662
3663 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
3664 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
3665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
3666 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
3667 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
3668 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
3669
3670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3671 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
3672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3673 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
3674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3675 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
3676
3677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 3678 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 3679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 3680 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 3681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 3682 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
823d2571
TG		 3683
3684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3685 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
3686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3687 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
3688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3689 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
3690
3691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3692 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
3693 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3694 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
3695 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3696 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
3697
3698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3699 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
3700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3701 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
3702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3703 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
3704
3705 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3706 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
3707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3708 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
3709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3710 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
3711 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3712 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
3713 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3714 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
3715 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3716 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
3717 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3718 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
3719
3720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3721 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
3722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3723 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
3724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3725 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
3726
3727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3728 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
3729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3730 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
3731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3732 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
3733
3734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3735 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
3736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3737 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
3738
3739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3740 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
3741
3742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3743 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
3744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3745 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
3746
3747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3748 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3750 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3752 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3754 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3756 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3758 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3760 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3762 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3764 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3766 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3768 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3770 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3772 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3774 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3776 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3778 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3780 0x092d0000, 0x0fff0000, "push%c\t%m"},
3781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3782 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
3783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3784 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3785
3786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3787 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3789 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3791 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3793 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3795 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3797 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3799 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3801 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3803 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3805 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3807 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3809 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3811 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3813 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3815 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3817 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3819 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
3820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3821 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
3822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3823 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3824
3825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3826 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
3827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3828 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 3829
3830 /* The rest. */
4ab90a7a
AV		 3831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3832 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 3833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3834 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3835 {ARM_FEATURE_CORE_LOW (0),
3836 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 3837};
3838
3839/* print_insn_thumb16 recognizes the following format control codes:
3840
3841 %S print Thumb register (bits 3..5 as high number if bit 6 set)
3842 %D print Thumb register (bits 0..2 as high number if bit 7 set)
3843 %<bitfield>I print bitfield as a signed decimal
3844 (top bit of range being the sign bit)
3845 %N print Thumb register mask (with LR)
3846 %O print Thumb register mask (with PC)
3847 %M print Thumb register mask
3848 %b print CZB's 6-bit unsigned branch destination
3849 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 3850 %c print the condition code
3851 %C print the condition code, or "s" if not conditional
3852 %x print warning if conditional an not at end of IT block"
3853 %X print "\t; unpredictable <IT:code>" if conditional
3854 %I print IT instruction suffix and operands
4547cb56 3855 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 3856 %<bitfield>r print bitfield as an ARM register
3857 %<bitfield>d print bitfield as a decimal
3858 %<bitfield>H print (bitfield * 2) as a decimal
3859 %<bitfield>W print (bitfield * 4) as a decimal
3860 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
3861 %<bitfield>B print Thumb branch destination (signed displacement)
3862 %<bitfield>c print bitfield as a condition code
3863 %<bitnum>'c print specified char iff bit is one
3864 %<bitnum>?ab print a if bit is one else print b. */
3865
3866static const struct opcode16 thumb_opcodes[] =
3867{
3868 /* Thumb instructions. */
3869
16a1fa25
TP		 3870 /* ARMv8-M Security Extensions instructions. */
3871 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
e207bc53 3872 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
16a1fa25 3873
53c4b28b 3874 /* ARM V8 instructions. */
823d2571
TG		 3875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
3876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
ddfded2f 3877 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
53c4b28b 3878
8f06b2d8 3879 /* ARM V6K no-argument instructions. */
823d2571
TG		 3880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
3881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
3882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
3883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
3884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
3885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 3886
3887 /* ARM V6T2 instructions. */
ff8646ee
TP		 3888 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3889 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
3890 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3891 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 3892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 3893
3894 /* ARM V6. */
823d2571
TG		 3895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
3896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
3897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
3898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
3899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
3900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
3901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
3902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
3903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
3904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
3905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 3906
3907 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 3908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
3909 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 3910 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 3911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
3912 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 3913 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 3914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3915 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 3916 /* Format 4. */
823d2571
TG		 3917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
3918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
3919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
3920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
3921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
3922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
3923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
3924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
3925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
3926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
3927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
3928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
3929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
3930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
3931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
3932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 3933 /* format 13 */
823d2571
TG		 3934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
3935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 3936 /* format 5 */
823d2571
TG		 3937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
3938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
3939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
3940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 3941 /* format 14 */
823d2571
TG		 3942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
3943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 3944 /* format 2 */
823d2571
TG		 3945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3946 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
3947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3948 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
3949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3950 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
3951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3952 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 3953 /* format 8 */
823d2571
TG		 3954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3955 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
3956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3957 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
3958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3959 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 3960 /* format 7 */
823d2571
TG		 3961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3962 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
3963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3964 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 3965 /* format 1 */
823d2571
TG		 3966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
3967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3968 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
3969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
3970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 3971 /* format 3 */
823d2571
TG		 3972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
3973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
3974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
3975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 3976 /* format 6 */
823d2571
TG		 3977 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
3978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3979 0x4800, 0xF800,
3980 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 3981 /* format 9 */
823d2571
TG		 3982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3983 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
3984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3985 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
3986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3987 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
3988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3989 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 3990 /* format 10 */
823d2571
TG		 3991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3992 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
3993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3994 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 3995 /* format 11 */
823d2571
TG		 3996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3997 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
3998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3999 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 4000 /* format 12 */
823d2571
TG		 4001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4002 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
4003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4004 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 4005 /* format 15 */
823d2571
TG		 4006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 4008 /* format 17 */
823d2571 4009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 4010 /* format 16 */
823d2571
TG		 4011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
4012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
4013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 4014 /* format 18 */
823d2571 4015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 4016
4017 /* The E800 .. FFFF range is unconditionally redirected to the
4018 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4019 are processed via that table. Thus, we can never encounter a
4020 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 4021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
4022 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 4023};
4024
4025/* Thumb32 opcodes use the same table structure as the ARM opcodes.
4026 We adopt the convention that hw1 is the high 16 bits of .value and
4027 .mask, hw2 the low 16 bits.
4028
4029 print_insn_thumb32 recognizes the following format control codes:
4030
4031 %% %
4032
4033 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4034 %M print a modified 12-bit immediate (same location)
4035 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4036 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 4037 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 4038 %S print a possibly-shifted Rm
4039
32a94698 4040 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 4041 %a print the address of a plain load/store
4042 %w print the width and signedness of a core load/store
4043 %m print register mask for ldm/stm
4b5a202f 4044 %n print register mask for clrm
8f06b2d8
PB		 4045
4046 %E print the lsb and width fields of a bfc/bfi instruction
4047 %F print the lsb and width fields of a sbfx/ubfx instruction
e12437dc 4048 %G print a fallback offset for Branch Future instructions
e5d6e09e 4049 %W print an offset for BF instruction
1caf72a5 4050 %Y print an offset for BFL instruction
1889da70 4051 %Z print an offset for BFCSEL instruction
60f993ce
AV		 4052 %Q print an offset for Low Overhead Loop instructions
4053 %P print an offset for Low Overhead Loop end instructions
8f06b2d8
PB		 4054 %b print a conditional branch offset
4055 %B print an unconditional branch offset
4056 %s print the shift field of an SSAT instruction
4057 %R print the rotation field of an SXT instruction
62b3e311
PB		 4058 %U print barrier type.
4059 %P print address for pli instruction.
c22aaad1
PB		 4060 %c print the condition code
4061 %x print warning if conditional an not at end of IT block"
4062 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 4063
4064 %<bitfield>d print bitfield in decimal
f0fba320 4065 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 4066 %<bitfield>W print bitfield*4 in decimal
4067 %<bitfield>r print bitfield as an ARM register
dd5181d5 4068 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
f1c7f421 4069 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
8f06b2d8
PB		 4070 %<bitfield>c print bitfield as a condition code
4071
16980d0b
JB		 4072 %<bitfield>'c print specified char iff bitfield is all ones
4073 %<bitfield>`c print specified char iff bitfield is all zeroes
4074 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 4075
4076 With one exception at the bottom (done because BL and BLX(1) need
4077 to come dead last), this table was machine-sorted first in
4078 decreasing order of number of bits set in the mask, then in
4079 increasing numeric order of mask, then in increasing numeric order
4080 of opcode. This order is not the clearest for a human reader, but
4081 is guaranteed never to catch a special-case bit pattern with a more
4082 general mask, which is important, because this instruction encoding
4083 makes heavy use of special-case bit patterns. */
4084static const struct opcode32 thumb32_opcodes[] =
4085{
4b5a202f
AV		 4086 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4087 instructions. */
60f993ce 4088 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
d052b9b7 4089 0xf00fe001, 0xffffffff, "lctp%c"},
60f993ce
AV		 4090 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4091 0xf02fc001, 0xfffff001, "le\t%P"},
4092 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4093 0xf00fc001, 0xfffff001, "le\tlr, %P"},
d052b9b7
AV		 4094 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4095 0xf01fc001, 0xfffff001, "letp\tlr, %P"},
4096 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4097 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
4098 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4099 0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
4100 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4101 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
4102 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4103 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
60f993ce 4104
4389b29a
AV		 4105 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4106 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
f1c7f421
AV		 4107 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4108 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
65d1bc05
AV		 4109 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4110 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
f1c7f421
AV		 4111 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4112 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
f6b2b12d
AV		 4113 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4114 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4389b29a 4115
4b5a202f
AV		 4116 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4117 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4389b29a 4118
16a1fa25
TP		 4119 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
4120 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4ed7ed8d
TP		 4121 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4122 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4123 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4124 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
16a1fa25
TP		 4125 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4126 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4127 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4128 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4ed7ed8d 4129
105bde57 4130 /* ARM V8.2 RAS extension instructions. */
4d1464f2 4131 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 4132 0xf3af8010, 0xffffffff, "esb"},
4133
53c4b28b 4134 /* V8 instructions. */
823d2571
TG		 4135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4136 0xf3af8005, 0xffffffff, "sevl%c.w"},
4137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4138 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4140 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4142 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4144 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4146 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4148 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4150 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4152 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4154 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4156 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4158 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4160 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4162 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4164 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4166 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 4167
dd5181d5 4168 /* CRC32 instructions. */
823d2571 4169 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4170 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
823d2571 4171 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4172 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
823d2571 4173 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4174 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
823d2571 4175 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4176 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
823d2571 4177 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4178 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
823d2571 4179 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4180 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
dd5181d5 4181
c597cc3d
SD		 4182 /* Speculation Barriers. */
4183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
4184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
4185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
4186
62b3e311 4187 /* V7 instructions. */
823d2571
TG		 4188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
4190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4195 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4196 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4197 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4198 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 4199
90ec0d68 4200 /* Virtualization Extension instructions. */
823d2571 4201 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 4202 /* We skip ERET as that is SUBS pc, lr, #0. */
4203
60e5ef9f 4204 /* MP Extension instructions. */
823d2571 4205 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 4206
f4c65163 4207 /* Security extension instructions. */
823d2571 4208 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 4209
7fadb25d
SD		 4210 /* ARMv8.5-A instructions. */
4211 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
4212
8f06b2d8 4213 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 4214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
4215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
4216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4217 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
4219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4220 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
4221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4222
ff8646ee 4223 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4224 0xf3bf8f2f, 0xffffffff, "clrex%c"},
4225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4226 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
4227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4228 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
4229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4230 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4232 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4234 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4236 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4238 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
4239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4240 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4242 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
4243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4244 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
4245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4246 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
4247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4248 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
4249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4250 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 4251 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 4252 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 4253 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4254 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4256 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
4257 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4258 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
4259 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4260 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4261 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4262 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4263 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4264 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4266 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4268 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4270 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 4271 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4272 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4273 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4274 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4275 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4276 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4277 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4278 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4279 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4280 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4281 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4282 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4283 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4284 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4285 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4286 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4287 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4288 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4289 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4290 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4292 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4294 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4295 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4296 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4297 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4298 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4299 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4300 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4301 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4302 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4304 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4305 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4306 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4307 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4308 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4310 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4312 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4314 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4315 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4316 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4317 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4318 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4320 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4322 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4323 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4324 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4325 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4326 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4327 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4328 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4329 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4330 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4331 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4332 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4334 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4336 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4338 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4339 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4340 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4341 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4342 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4343 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4344 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4345 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4346 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4348 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4350 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4352 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4354 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4356 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4358 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4360 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4362 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4364 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4366 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4368 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4370 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4372 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4374 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4376 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4378 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 4379 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4380 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 4382 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 4383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4384 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4386 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4388 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4390 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4392 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4394 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4395 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4396 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4397 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4398 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4399 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4400 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4401 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4402 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4403 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4404 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4406 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4408 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4410 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4411 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4412 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4413 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4414 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4415 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4416 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4418 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4419 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4420 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4422 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4424 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4425 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4426 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4427 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4428 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4429 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4430 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4431 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4432 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4433 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4434 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4435 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4436 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4437 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4438 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4439 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4440 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4441 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4442 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4443 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4444 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4446 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 4447 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4448 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
4449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4450 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
4451 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4452 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
4453 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4454 0xf810f000, 0xff70f000, "pld%c\t%a"},
4455 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4456 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4457 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4458 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4459 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4460 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4461 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4462 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4463 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4464 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4465 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4466 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4467 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4468 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4469 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4470 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
4471 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4472 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
4473 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4474 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
4475 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4476 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
4477 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4478 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
4479 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4480 0xfb100000, 0xfff000c0,
4481 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4482 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4483 0xfbc00080, 0xfff000c0,
4484 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
4485 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4486 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
4487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4488 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
4489 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 4490 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 4491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4492 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
4493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4494 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 4495 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4496 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
4497 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4498 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 4499 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4500 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
4501 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4502 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
4503 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4504 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
4505 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4506 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
4507 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4508 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
4509 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4510 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
4511 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4512 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
4513 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4514 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
4515 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4516 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
4517 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4518 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
4519 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4520 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 4521 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4522 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
4523 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4524 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
4525 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4526 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
4527 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4528 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
4529 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4530 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
4531 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4532 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
4533 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4534 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
4535 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4536 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
4537 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4538 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
4539 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4540 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
4541 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4542 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
4543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4544 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
4545 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4546 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
4547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4548 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
4549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4550 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
4551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4552 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
4553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4554 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
4555 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4556 0xe9400000, 0xff500000,
4557 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4559 0xe9500000, 0xff500000,
4560 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4562 0xe8600000, 0xff700000,
4563 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4565 0xe8700000, 0xff700000,
4566 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4568 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
4569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4570 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 4571
4572 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 4573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4574 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
4575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4576 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
4577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4578 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
4579 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4580 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 4581
8f06b2d8 4582 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 4583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4584 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
4585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4586 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 4587
4588 /* Fallback. */
823d2571
TG		 4589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4590 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4591 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 4592};
ff4a8d2b 4593
8f06b2d8
PB		 4594static const char *const arm_conditional[] =
4595{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 4596 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 4597
4598static const char *const arm_fp_const[] =
4599{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
4600
4601static const char *const arm_shift[] =
4602{"lsl", "lsr", "asr", "ror"};
4603
4604typedef struct
4605{
4606 const char *name;
4607 const char *description;
4608 const char *reg_names[16];
4609}
4610arm_regname;
4611
4612static const arm_regname regnames[] =
4613{
65b48a81 4614 { "reg-names-raw", N_("Select raw register names"),
8f06b2d8 4615 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
65b48a81 4616 { "reg-names-gcc", N_("Select register names used by GCC"),
8f06b2d8 4617 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 4618 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
8f06b2d8 4619 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65b48a81
PB		 4620 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
4621 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
4622 { "reg-names-apcs", N_("Select register names used in the APCS"),
8f06b2d8 4623 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 4624 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
8f06b2d8 4625 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
65b48a81
PB		 4626 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
4627 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
8f06b2d8
PB		 4628};
4629
4630static const char *const iwmmxt_wwnames[] =
4631{"b", "h", "w", "d"};
4632
4633static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 4634{"b", "bus", "bc", "bss",
4635 "h", "hus", "hc", "hss",
4636 "w", "wus", "wc", "wss",
4637 "d", "dus", "dc", "dss"
8f06b2d8
PB		 4638};
4639
4640static const char *const iwmmxt_regnames[] =
4641{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
4642 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
4643};
4644
4645static const char *const iwmmxt_cregnames[] =
4646{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
4647 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
4648};
4649
143275ea
AV		 4650static const char *const vec_condnames[] =
4651{ "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
4652};
4653
4654static const char *const mve_predicatenames[] =
4655{ "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
4656 "eee", "ee", "eet", "e", "ett", "et", "ete"
4657};
4658
4659/* Names for 2-bit size field for mve vector isntructions. */
4660static const char *const mve_vec_sizename[] =
4661 { "8", "16", "32", "64"};
4662
4663/* Indicates whether we are processing a then predicate,
4664 else predicate or none at all. */
4665enum vpt_pred_state
4666{
4667 PRED_NONE,
4668 PRED_THEN,
4669 PRED_ELSE
4670};
4671
4672/* Information used to process a vpt block and subsequent instructions. */
4673struct vpt_block
4674{
4675 /* Are we in a vpt block. */
4676 bfd_boolean in_vpt_block;
4677
4678 /* Next predicate state if in vpt block. */
4679 enum vpt_pred_state next_pred_state;
4680
4681 /* Mask from vpt/vpst instruction. */
4682 long predicate_mask;
4683
4684 /* Instruction number in vpt block. */
4685 long current_insn_num;
4686
4687 /* Number of instructions in vpt block.. */
4688 long num_pred_insn;
4689};
4690
4691static struct vpt_block vpt_block_state =
4692{
4693 FALSE,
4694 PRED_NONE,
4695 0,
4696 0,
4697 0
4698};
4699
8f06b2d8
PB		 4700/* Default to GCC register name set. */
4701static unsigned int regname_selected = 1;
4702
65b48a81 4703#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
8f06b2d8
PB		 4704#define arm_regnames regnames[regname_selected].reg_names
4705
4706static bfd_boolean force_thumb = FALSE;
4707
c22aaad1
PB		 4708/* Current IT instruction state. This contains the same state as the IT
4709 bits in the CPSR. */
4710static unsigned int ifthen_state;
4711/* IT state for the next instruction. */
4712static unsigned int ifthen_next_state;
4713/* The address of the insn for which the IT state is valid. */
4714static bfd_vma ifthen_address;
4715#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 4716/* Indicates that the current Conditional state is unconditional or outside
4717 an IT block. */
4718#define COND_UNCOND 16
c22aaad1 4719
8f06b2d8
PB		 4720\f
4721/* Functions. */
143275ea
AV		 4722/* Extract the predicate mask for a VPT or VPST instruction.
4723 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
4724
4725static long
4726mve_extract_pred_mask (long given)
4727{
4728 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
4729}
4730
4731/* Return the number of instructions in a MVE predicate block. */
4732static long
4733num_instructions_vpt_block (long given)
4734{
4735 long mask = mve_extract_pred_mask (given);
4736 if (mask == 0)
4737 return 0;
4738
4739 if (mask == 8)
4740 return 1;
4741
4742 if ((mask & 7) == 4)
4743 return 2;
4744
4745 if ((mask & 3) == 2)
4746 return 3;
4747
4748 if ((mask & 1) == 1)
4749 return 4;
4750
4751 return 0;
4752}
4753
4754static void
4755mark_outside_vpt_block (void)
4756{
4757 vpt_block_state.in_vpt_block = FALSE;
4758 vpt_block_state.next_pred_state = PRED_NONE;
4759 vpt_block_state.predicate_mask = 0;
4760 vpt_block_state.current_insn_num = 0;
4761 vpt_block_state.num_pred_insn = 0;
4762}
4763
4764static void
4765mark_inside_vpt_block (long given)
4766{
4767 vpt_block_state.in_vpt_block = TRUE;
4768 vpt_block_state.next_pred_state = PRED_THEN;
4769 vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
4770 vpt_block_state.current_insn_num = 0;
4771 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
4772 assert (vpt_block_state.num_pred_insn >= 1);
4773}
4774
4775static enum vpt_pred_state
4776invert_next_predicate_state (enum vpt_pred_state astate)
4777{
4778 if (astate == PRED_THEN)
4779 return PRED_ELSE;
4780 else if (astate == PRED_ELSE)
4781 return PRED_THEN;
4782 else
4783 return PRED_NONE;
4784}
4785
4786static enum vpt_pred_state
4787update_next_predicate_state (void)
4788{
4789 long pred_mask = vpt_block_state.predicate_mask;
4790 long mask_for_insn = 0;
4791
4792 switch (vpt_block_state.current_insn_num)
4793 {
4794 case 1:
4795 mask_for_insn = 8;
4796 break;
4797
4798 case 2:
4799 mask_for_insn = 4;
4800 break;
4801
4802 case 3:
4803 mask_for_insn = 2;
4804 break;
4805
4806 case 4:
4807 return PRED_NONE;
4808 }
4809
4810 if (pred_mask & mask_for_insn)
4811 return invert_next_predicate_state (vpt_block_state.next_pred_state);
4812 else
4813 return vpt_block_state.next_pred_state;
4814}
4815
4816static void
4817update_vpt_block_state (void)
4818{
4819 vpt_block_state.current_insn_num++;
4820 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
4821 {
4822 /* No more instructions to process in vpt block. */
4823 mark_outside_vpt_block ();
4824 return;
4825 }
4826
4827 vpt_block_state.next_pred_state = update_next_predicate_state ();
4828}
8f06b2d8 4829
16980d0b
JB		 4830/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
4831 Returns pointer to following character of the format string and
4832 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 4833 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 4834
4835static const char *
fe56b6ce
NC		 4836arm_decode_bitfield (const char *ptr,
4837 unsigned long insn,
4838 unsigned long *valuep,
4839 int *widthp)
16980d0b
JB		 4840{
4841 unsigned long value = 0;
4842 int width = 0;
43e65147
L		 4843
4844 do
16980d0b
JB		 4845 {
4846 int start, end;
4847 int bits;
4848
4849 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
4850 start = start * 10 + *ptr - '0';
4851 if (*ptr == '-')
4852 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
4853 end = end * 10 + *ptr - '0';
4854 else
4855 end = start;
4856 bits = end - start;
4857 if (bits < 0)
4858 abort ();
4859 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
4860 width += bits + 1;
4861 }
4862 while (*ptr++ == ',');
4863 *valuep = value;
4864 if (widthp)
4865 *widthp = width;
4866 return ptr - 1;
4867}
4868
8f06b2d8 4869static void
37b37b2d 4870arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 4871 bfd_boolean print_shift)
8f06b2d8
PB		 4872{
4873 func (stream, "%s", arm_regnames[given & 0xf]);
4874
4875 if ((given & 0xff0) != 0)
4876 {
4877 if ((given & 0x10) == 0)
4878 {
4879 int amount = (given & 0xf80) >> 7;
4880 int shift = (given & 0x60) >> 5;
4881
4882 if (amount == 0)
4883 {
4884 if (shift == 3)
4885 {
4886 func (stream, ", rrx");
4887 return;
4888 }
4889
4890 amount = 32;
4891 }
4892
37b37b2d
RE		 4893 if (print_shift)
4894 func (stream, ", %s #%d", arm_shift[shift], amount);
4895 else
4896 func (stream, ", #%d", amount);
8f06b2d8 4897 }
74bdfecf 4898 else if ((given & 0x80) == 0x80)
aefd8a40 4899 func (stream, "\t; <illegal shifter operand>");
37b37b2d 4900 else if (print_shift)
8f06b2d8
PB		 4901 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
4902 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 4903 else
4904 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 4905 }
4906}
4907
73cd51e5
AV		 4908/* Return TRUE if the MATCHED_INSN can be inside an IT block. */
4909
4910static bfd_boolean
4911is_mve_okay_in_it (enum mve_instructions matched_insn)
4912{
c507f10b
AV		 4913 switch (matched_insn)
4914 {
4915 case MVE_VMOV_GP_TO_VEC_LANE:
4916 case MVE_VMOV2_VEC_LANE_TO_GP:
4917 case MVE_VMOV2_GP_TO_VEC_LANE:
4918 case MVE_VMOV_VEC_LANE_TO_GP:
4919 return TRUE;
4920 default:
4921 return FALSE;
4922 }
73cd51e5
AV		 4923}
4924
4925static bfd_boolean
4926is_mve_architecture (struct disassemble_info *info)
4927{
4928 struct arm_private_data *private_data = info->private_data;
4929 arm_feature_set allowed_arches = private_data->features;
4930
4931 arm_feature_set arm_ext_v8_1m_main
4932 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
4933
4934 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
4935 && !ARM_CPU_IS_ANY (allowed_arches))
4936 return TRUE;
4937 else
4938 return FALSE;
4939}
4940
143275ea
AV		 4941static bfd_boolean
4942is_vpt_instruction (long given)
4943{
4944
4945 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
4946 if ((given & 0x0040e000) == 0)
4947 return FALSE;
4948
4949 /* VPT floating point T1 variant. */
4950 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
4951 /* VPT floating point T2 variant. */
4952 || ((given & 0xefb10f50) == 0xee310f40)
4953 /* VPT vector T1 variant. */
4954 || ((given & 0xff811f51) == 0xfe010f00)
4955 /* VPT vector T2 variant. */
4956 || ((given & 0xff811f51) == 0xfe010f01
4957 && ((given & 0x300000) != 0x300000))
4958 /* VPT vector T3 variant. */
4959 || ((given & 0xff811f50) == 0xfe011f00)
4960 /* VPT vector T4 variant. */
4961 || ((given & 0xff811f70) == 0xfe010f40)
4962 /* VPT vector T5 variant. */
4963 || ((given & 0xff811f70) == 0xfe010f60)
4964 /* VPT vector T6 variant. */
4965 || ((given & 0xff811f50) == 0xfe011f40)
4966 /* VPST vector T variant. */
4967 || ((given & 0xffbf1fff) == 0xfe310f4d))
4968 return TRUE;
4969 else
4970 return FALSE;
4971}
4972
73cd51e5
AV		 4973/* Decode a bitfield from opcode GIVEN, with starting bitfield = START
4974 and ending bitfield = END. END must be greater than START. */
4975
4976static unsigned long
4977arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
4978{
4979 int bits = end - start;
4980
4981 if (bits < 0)
4982 abort ();
4983
4984 return ((given >> start) & ((2ul << bits) - 1));
4985}
4986
4987/* Decode a bitfield from opcode GIVEN, with multiple bitfields:
4988 START:END and START2:END2. END/END2 must be greater than
4989 START/START2. */
4990
4991static unsigned long
4992arm_decode_field_multiple (unsigned long given, unsigned int start,
4993 unsigned int end, unsigned int start2,
4994 unsigned int end2)
4995{
4996 int bits = end - start;
4997 int bits2 = end2 - start2;
4998 unsigned long value = 0;
4999 int width = 0;
5000
5001 if (bits2 < 0)
5002 abort ();
5003
5004 value = arm_decode_field (given, start, end);
5005 width += bits + 1;
5006
5007 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
5008 return value;
5009}
5010
5011/* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5012 This helps us decode instructions that change mnemonic depending on specific
5013 operand values/encodings. */
5014
5015static bfd_boolean
5016is_mve_encoding_conflict (unsigned long given,
5017 enum mve_instructions matched_insn)
5018{
143275ea
AV		 5019 switch (matched_insn)
5020 {
5021 case MVE_VPST:
5022 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5023 return TRUE;
5024 else
5025 return FALSE;
5026
5027 case MVE_VPT_FP_T1:
5028 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5029 return TRUE;
5030 if ((arm_decode_field (given, 12, 12) == 0)
5031 && (arm_decode_field (given, 0, 0) == 1))
5032 return TRUE;
5033 return FALSE;
5034
5035 case MVE_VPT_FP_T2:
5036 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5037 return TRUE;
5038 if (arm_decode_field (given, 0, 3) == 0xd)
5039 return TRUE;
5040 return FALSE;
5041
5042 case MVE_VPT_VEC_T1:
5043 case MVE_VPT_VEC_T2:
5044 case MVE_VPT_VEC_T3:
5045 case MVE_VPT_VEC_T4:
5046 case MVE_VPT_VEC_T5:
5047 case MVE_VPT_VEC_T6:
5048 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5049 return TRUE;
5050 if (arm_decode_field (given, 20, 21) == 3)
5051 return TRUE;
5052 return FALSE;
5053
5054 case MVE_VCMP_FP_T1:
5055 if ((arm_decode_field (given, 12, 12) == 0)
5056 && (arm_decode_field (given, 0, 0) == 1))
5057 return TRUE;
5058 else
5059 return FALSE;
5060
5061 case MVE_VCMP_FP_T2:
5062 if (arm_decode_field (given, 0, 3) == 0xd)
5063 return TRUE;
5064 else
5065 return FALSE;
5066
e523f101 5067 case MVE_VBRSR:
66dcaa5d
AV		 5068 case MVE_VADD_VEC_T2:
5069 case MVE_VSUB_VEC_T2:
5070 case MVE_VABAV:
ed63aa17
AV		 5071 case MVE_VQRSHL_T1:
5072 case MVE_VQSHL_T4:
5073 case MVE_VRSHL_T1:
5074 case MVE_VSHL_T3:
897b9bbc
AV		 5075 case MVE_VCADD_VEC:
5076 case MVE_VHCADD:
1c8f2df8
AV		 5077 case MVE_VDDUP:
5078 case MVE_VIDUP:
d3b63143
AV		 5079 case MVE_VQRDMLADH:
5080 case MVE_VQDMLAH:
5081 case MVE_VQRDMLAH:
5082 case MVE_VQDMLASH:
5083 case MVE_VQRDMLASH:
5084 case MVE_VQDMLSDH:
5085 case MVE_VQRDMLSDH:
5086 case MVE_VQDMULH_T3:
5087 case MVE_VQRDMULH_T4:
5088 case MVE_VQDMLADH:
5089 case MVE_VMLAS:
14925797 5090 case MVE_VMULL_INT:
9743db03
AV		 5091 case MVE_VHADD_T2:
5092 case MVE_VHSUB_T2:
143275ea
AV		 5093 case MVE_VCMP_VEC_T1:
5094 case MVE_VCMP_VEC_T2:
5095 case MVE_VCMP_VEC_T3:
5096 case MVE_VCMP_VEC_T4:
5097 case MVE_VCMP_VEC_T5:
5098 case MVE_VCMP_VEC_T6:
5099 if (arm_decode_field (given, 20, 21) == 3)
5100 return TRUE;
5101 else
5102 return FALSE;
5103
04d54ace
AV		 5104 case MVE_VLD2:
5105 case MVE_VLD4:
5106 case MVE_VST2:
5107 case MVE_VST4:
5108 if (arm_decode_field (given, 7, 8) == 3)
5109 return TRUE;
5110 else
5111 return FALSE;
5112
aef6d006
AV		 5113 case MVE_VSTRB_T1:
5114 case MVE_VSTRH_T2:
5115 if ((arm_decode_field (given, 24, 24) == 0)
5116 && (arm_decode_field (given, 21, 21) == 0))
5117 {
5118 return TRUE;
5119 }
5120 else if ((arm_decode_field (given, 7, 8) == 3))
5121 return TRUE;
5122 else
5123 return FALSE;
5124
5125 case MVE_VSTRB_T5:
5126 case MVE_VSTRH_T6:
5127 case MVE_VSTRW_T7:
5128 if ((arm_decode_field (given, 24, 24) == 0)
5129 && (arm_decode_field (given, 21, 21) == 0))
5130 {
5131 return TRUE;
5132 }
5133 else
5134 return FALSE;
5135
bf0b396d
AV		 5136 case MVE_VCVT_FP_FIX_VEC:
5137 return (arm_decode_field (given, 16, 21) & 0x38) == 0;
5138
c507f10b
AV		 5139 case MVE_VBIC_IMM:
5140 case MVE_VORR_IMM:
5141 {
5142 unsigned long cmode = arm_decode_field (given, 8, 11);
5143
5144 if ((cmode & 1) == 0)
5145 return TRUE;
5146 else if ((cmode & 0xc) == 0xc)
5147 return TRUE;
5148 else
5149 return FALSE;
5150 }
5151
5152 case MVE_VMVN_IMM:
5153 {
5154 unsigned long cmode = arm_decode_field (given, 8, 11);
5155
5156 if ((cmode & 9) == 1)
5157 return TRUE;
5158 else if ((cmode & 5) == 1)
5159 return TRUE;
5160 else if ((cmode & 0xe) == 0xe)
5161 return TRUE;
5162 else
5163 return FALSE;
5164 }
5165
5166 case MVE_VMOV_IMM_TO_VEC:
5167 if ((arm_decode_field (given, 5, 5) == 1)
5168 && (arm_decode_field (given, 8, 11) != 0xe))
5169 return TRUE;
5170 else
5171 return FALSE;
5172
14925797
AV		 5173 case MVE_VMOVL:
5174 {
5175 unsigned long size = arm_decode_field (given, 19, 20);
5176 if ((size == 0) || (size == 3))
5177 return TRUE;
5178 else
5179 return FALSE;
5180 }
5181
ed63aa17
AV		 5182 case MVE_VQRSHL_T2:
5183 case MVE_VQSHL_T1:
5184 case MVE_VRSHL_T2:
5185 case MVE_VSHL_T2:
5186 case MVE_VSHLL_T2:
d3b63143 5187 case MVE_VADDV:
14925797
AV		 5188 case MVE_VMOVN:
5189 case MVE_VQMOVUN:
5190 case MVE_VQMOVN:
5191 if (arm_decode_field (given, 18, 19) == 3)
5192 return TRUE;
5193 else
5194 return FALSE;
5195
d3b63143
AV		 5196 case MVE_VMLSLDAV:
5197 case MVE_VRMLSLDAVH:
5198 case MVE_VMLALDAV:
5199 case MVE_VADDLV:
5200 if (arm_decode_field (given, 20, 22) == 7)
5201 return TRUE;
5202 else
5203 return FALSE;
5204
5205 case MVE_VRMLALDAVH:
5206 if ((arm_decode_field (given, 20, 22) & 6) == 6)
5207 return TRUE;
5208 else
5209 return FALSE;
5210
1c8f2df8
AV		 5211 case MVE_VDWDUP:
5212 case MVE_VIWDUP:
5213 if ((arm_decode_field (given, 20, 21) == 3)
5214 || (arm_decode_field (given, 1, 3) == 7))
5215 return TRUE;
5216 else
5217 return FALSE;
5218
ed63aa17
AV		 5219
5220 case MVE_VSHLL_T1:
5221 if (arm_decode_field (given, 16, 18) == 0)
5222 {
5223 unsigned long sz = arm_decode_field (given, 19, 20);
5224
5225 if ((sz == 1) || (sz == 2))
5226 return TRUE;
5227 else
5228 return FALSE;
5229 }
5230 else
5231 return FALSE;
5232
5233 case MVE_VQSHL_T2:
5234 case MVE_VQSHLU_T3:
5235 case MVE_VRSHR:
5236 case MVE_VSHL_T1:
5237 case MVE_VSHR:
5238 case MVE_VSLI:
5239 case MVE_VSRI:
5240 if (arm_decode_field (given, 19, 21) == 0)
5241 return TRUE;
5242 else
5243 return FALSE;
5244
e523f101
AV		 5245 case MVE_VCTP:
5246 if (arm_decode_field (given, 16, 19) == 0xf)
5247 return TRUE;
5248 else
5249 return FALSE;
5250
143275ea 5251 default:
66dcaa5d
AV		 5252 case MVE_VADD_FP_T1:
5253 case MVE_VADD_FP_T2:
5254 case MVE_VADD_VEC_T1:
143275ea
AV		 5255 return FALSE;
5256
5257 }
73cd51e5
AV		 5258}
5259
aef6d006
AV		 5260static void
5261print_mve_vld_str_addr (struct disassemble_info *info,
5262 unsigned long given,
5263 enum mve_instructions matched_insn)
5264{
5265 void *stream = info->stream;
5266 fprintf_ftype func = info->fprintf_func;
5267
5268 unsigned long p, w, gpr, imm, add, mod_imm;
5269
5270 imm = arm_decode_field (given, 0, 6);
5271 mod_imm = imm;
5272
5273 switch (matched_insn)
5274 {
5275 case MVE_VLDRB_T1:
5276 case MVE_VSTRB_T1:
5277 gpr = arm_decode_field (given, 16, 18);
5278 break;
5279
5280 case MVE_VLDRH_T2:
5281 case MVE_VSTRH_T2:
5282 gpr = arm_decode_field (given, 16, 18);
5283 mod_imm = imm << 1;
5284 break;
5285
5286 case MVE_VLDRH_T6:
5287 case MVE_VSTRH_T6:
5288 gpr = arm_decode_field (given, 16, 19);
5289 mod_imm = imm << 1;
5290 break;
5291
5292 case MVE_VLDRW_T7:
5293 case MVE_VSTRW_T7:
5294 gpr = arm_decode_field (given, 16, 19);
5295 mod_imm = imm << 2;
5296 break;
5297
5298 case MVE_VLDRB_T5:
5299 case MVE_VSTRB_T5:
5300 gpr = arm_decode_field (given, 16, 19);
5301 break;
5302
5303 default:
5304 return;
5305 }
5306
5307 p = arm_decode_field (given, 24, 24);
5308 w = arm_decode_field (given, 21, 21);
5309
5310 add = arm_decode_field (given, 23, 23);
5311
5312 char * add_sub;
5313
5314 /* Don't print anything for '+' as it is implied. */
5315 if (add == 1)
5316 add_sub = "";
5317 else
5318 add_sub = "-";
5319
5320 if (p == 1)
5321 {
5322 /* Offset mode. */
5323 if (w == 0)
5324 func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm);
5325 /* Pre-indexed mode. */
5326 else
5327 func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm);
5328 }
5329 else if ((p == 0) && (w == 1))
5330 /* Post-index mode. */
5331 func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm);
5332}
5333
73cd51e5
AV		 5334/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5335 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5336 this encoding is undefined. */
5337
5338static bfd_boolean
5339is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
5340 enum mve_undefined *undefined_code)
5341{
5342 *undefined_code = UNDEF_NONE;
5343
9743db03
AV		 5344 switch (matched_insn)
5345 {
5346 case MVE_VDUP:
5347 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
5348 {
5349 *undefined_code = UNDEF_SIZE_3;
5350 return TRUE;
5351 }
5352 else
5353 return FALSE;
5354
66dcaa5d
AV		 5355 case MVE_VABD_VEC:
5356 case MVE_VADD_VEC_T1:
5357 case MVE_VSUB_VEC_T1:
d3b63143
AV		 5358 case MVE_VQDMULH_T1:
5359 case MVE_VQRDMULH_T2:
9743db03
AV		 5360 case MVE_VRHADD:
5361 case MVE_VHADD_T1:
5362 case MVE_VHSUB_T1:
5363 if (arm_decode_field (given, 20, 21) == 3)
5364 {
5365 *undefined_code = UNDEF_SIZE_3;
5366 return TRUE;
5367 }
5368 else
5369 return FALSE;
5370
aef6d006
AV		 5371 case MVE_VLDRB_T1:
5372 if (arm_decode_field (given, 7, 8) == 3)
5373 {
5374 *undefined_code = UNDEF_SIZE_3;
5375 return TRUE;
5376 }
5377 else
5378 return FALSE;
5379
5380 case MVE_VLDRH_T2:
5381 if (arm_decode_field (given, 7, 8) <= 1)
5382 {
5383 *undefined_code = UNDEF_SIZE_LE_1;
5384 return TRUE;
5385 }
5386 else
5387 return FALSE;
5388
5389 case MVE_VSTRB_T1:
5390 if ((arm_decode_field (given, 7, 8) == 0))
5391 {
5392 *undefined_code = UNDEF_SIZE_0;
5393 return TRUE;
5394 }
5395 else
5396 return FALSE;
5397
5398 case MVE_VSTRH_T2:
5399 if ((arm_decode_field (given, 7, 8) <= 1))
5400 {
5401 *undefined_code = UNDEF_SIZE_LE_1;
5402 return TRUE;
5403 }
5404 else
5405 return FALSE;
5406
ef1576a1
AV		 5407 case MVE_VLDRB_GATHER_T1:
5408 if (arm_decode_field (given, 7, 8) == 3)
5409 {
5410 *undefined_code = UNDEF_SIZE_3;
5411 return TRUE;
5412 }
5413 else if ((arm_decode_field (given, 28, 28) == 0)
5414 && (arm_decode_field (given, 7, 8) == 0))
5415 {
5416 *undefined_code = UNDEF_NOT_UNS_SIZE_0;
5417 return TRUE;
5418 }
5419 else
5420 return FALSE;
5421
5422 case MVE_VLDRH_GATHER_T2:
5423 if (arm_decode_field (given, 7, 8) == 3)
5424 {
5425 *undefined_code = UNDEF_SIZE_3;
5426 return TRUE;
5427 }
5428 else if ((arm_decode_field (given, 28, 28) == 0)
5429 && (arm_decode_field (given, 7, 8) == 1))
5430 {
5431 *undefined_code = UNDEF_NOT_UNS_SIZE_1;
5432 return TRUE;
5433 }
5434 else if (arm_decode_field (given, 7, 8) == 0)
5435 {
5436 *undefined_code = UNDEF_SIZE_0;
5437 return TRUE;
5438 }
5439 else
5440 return FALSE;
5441
5442 case MVE_VLDRW_GATHER_T3:
5443 if (arm_decode_field (given, 7, 8) != 2)
5444 {
5445 *undefined_code = UNDEF_SIZE_NOT_2;
5446 return TRUE;
5447 }
5448 else if (arm_decode_field (given, 28, 28) == 0)
5449 {
5450 *undefined_code = UNDEF_NOT_UNSIGNED;
5451 return TRUE;
5452 }
5453 else
5454 return FALSE;
5455
5456 case MVE_VLDRD_GATHER_T4:
5457 if (arm_decode_field (given, 7, 8) != 3)
5458 {
5459 *undefined_code = UNDEF_SIZE_NOT_3;
5460 return TRUE;
5461 }
5462 else if (arm_decode_field (given, 28, 28) == 0)
5463 {
5464 *undefined_code = UNDEF_NOT_UNSIGNED;
5465 return TRUE;
5466 }
5467 else
5468 return FALSE;
5469
5470 case MVE_VSTRB_SCATTER_T1:
5471 if (arm_decode_field (given, 7, 8) == 3)
5472 {
5473 *undefined_code = UNDEF_SIZE_3;
5474 return TRUE;
5475 }
5476 else
5477 return FALSE;
5478
5479 case MVE_VSTRH_SCATTER_T2:
5480 {
5481 unsigned long size = arm_decode_field (given, 7, 8);
5482 if (size == 3)
5483 {
5484 *undefined_code = UNDEF_SIZE_3;
5485 return TRUE;
5486 }
5487 else if (size == 0)
5488 {
5489 *undefined_code = UNDEF_SIZE_0;
5490 return TRUE;
5491 }
5492 else
5493 return FALSE;
5494 }
5495
5496 case MVE_VSTRW_SCATTER_T3:
5497 if (arm_decode_field (given, 7, 8) != 2)
5498 {
5499 *undefined_code = UNDEF_SIZE_NOT_2;
5500 return TRUE;
5501 }
5502 else
5503 return FALSE;
5504
5505 case MVE_VSTRD_SCATTER_T4:
5506 if (arm_decode_field (given, 7, 8) != 3)
5507 {
5508 *undefined_code = UNDEF_SIZE_NOT_3;
5509 return TRUE;
5510 }
5511 else
5512 return FALSE;
5513
bf0b396d
AV		 5514 case MVE_VCVT_FP_FIX_VEC:
5515 {
5516 unsigned long imm6 = arm_decode_field (given, 16, 21);
5517 if ((imm6 & 0x20) == 0)
5518 {
5519 *undefined_code = UNDEF_VCVT_IMM6;
5520 return TRUE;
5521 }
5522
5523 if ((arm_decode_field (given, 9, 9) == 0)
5524 && ((imm6 & 0x30) == 0x20))
5525 {
5526 *undefined_code = UNDEF_VCVT_FSI_IMM6;
5527 return TRUE;
5528 }
5529
5530 return FALSE;
5531 }
5532
66dcaa5d 5533 case MVE_VABS_FP:
bf0b396d
AV		 5534 case MVE_VCVT_BETWEEN_FP_INT:
5535 case MVE_VCVT_FROM_FP_TO_INT:
5536 {
5537 unsigned long size = arm_decode_field (given, 18, 19);
5538 if (size == 0)
5539 {
5540 *undefined_code = UNDEF_SIZE_0;
5541 return TRUE;
5542 }
5543 else if (size == 3)
5544 {
5545 *undefined_code = UNDEF_SIZE_3;
5546 return TRUE;
5547 }
5548 else
5549 return FALSE;
5550 }
5551
c507f10b
AV		 5552 case MVE_VMOV_VEC_LANE_TO_GP:
5553 {
5554 unsigned long op1 = arm_decode_field (given, 21, 22);
5555 unsigned long op2 = arm_decode_field (given, 5, 6);
5556 unsigned long u = arm_decode_field (given, 23, 23);
5557
5558 if ((op2 == 0) && (u == 1))
5559 {
5560 if ((op1 == 0) || (op1 == 1))
5561 {
5562 *undefined_code = UNDEF_BAD_U_OP1_OP2;
5563 return TRUE;
5564 }
5565 else
5566 return FALSE;
5567 }
5568 else if (op2 == 2)
5569 {
5570 if ((op1 == 0) || (op1 == 1))
5571 {
5572 *undefined_code = UNDEF_BAD_OP1_OP2;
5573 return TRUE;
5574 }
5575 else
5576 return FALSE;
5577 }
5578
5579 return FALSE;
5580 }
5581
5582 case MVE_VMOV_GP_TO_VEC_LANE:
5583 if (arm_decode_field (given, 5, 6) == 2)
5584 {
5585 unsigned long op1 = arm_decode_field (given, 21, 22);
5586 if ((op1 == 0) || (op1 == 1))
5587 {
5588 *undefined_code = UNDEF_BAD_OP1_OP2;
5589 return TRUE;
5590 }
5591 else
5592 return FALSE;
5593 }
5594 else
5595 return FALSE;
5596
5597 case MVE_VMOV_IMM_TO_VEC:
5598 if (arm_decode_field (given, 5, 5) == 0)
5599 {
5600 unsigned long cmode = arm_decode_field (given, 8, 11);
5601
5602 if (((cmode & 9) == 1) || ((cmode & 5) == 1))
5603 {
5604 *undefined_code = UNDEF_OP_0_BAD_CMODE;
5605 return TRUE;
5606 }
5607 else
5608 return FALSE;
5609 }
5610 else
5611 return FALSE;
5612
ed63aa17 5613 case MVE_VSHLL_T2:
14925797
AV		 5614 case MVE_VMOVN:
5615 if (arm_decode_field (given, 18, 19) == 2)
5616 {
5617 *undefined_code = UNDEF_SIZE_2;
5618 return TRUE;
5619 }
5620 else
5621 return FALSE;
5622
d3b63143
AV		 5623 case MVE_VRMLALDAVH:
5624 case MVE_VMLADAV_T1:
5625 case MVE_VMLADAV_T2:
5626 case MVE_VMLALDAV:
5627 if ((arm_decode_field (given, 28, 28) == 1)
5628 && (arm_decode_field (given, 12, 12) == 1))
5629 {
5630 *undefined_code = UNDEF_XCHG_UNS;
5631 return TRUE;
5632 }
5633 else
5634 return FALSE;
5635
ed63aa17
AV		 5636 case MVE_VQSHRN:
5637 case MVE_VQSHRUN:
5638 case MVE_VSHLL_T1:
5639 case MVE_VSHRN:
5640 {
5641 unsigned long sz = arm_decode_field (given, 19, 20);
5642 if (sz == 1)
5643 return FALSE;
5644 else if ((sz & 2) == 2)
5645 return FALSE;
5646 else
5647 {
5648 *undefined_code = UNDEF_SIZE;
5649 return TRUE;
5650 }
5651 }
5652 break;
5653
5654 case MVE_VQSHL_T2:
5655 case MVE_VQSHLU_T3:
5656 case MVE_VRSHR:
5657 case MVE_VSHL_T1:
5658 case MVE_VSHR:
5659 case MVE_VSLI:
5660 case MVE_VSRI:
5661 {
5662 unsigned long sz = arm_decode_field (given, 19, 21);
5663 if ((sz & 7) == 1)
5664 return FALSE;
5665 else if ((sz & 6) == 2)
5666 return FALSE;
5667 else if ((sz & 4) == 4)
5668 return FALSE;
5669 else
5670 {
5671 *undefined_code = UNDEF_SIZE;
5672 return TRUE;
5673 }
5674 }
5675
5676 case MVE_VQRSHRN:
5677 case MVE_VQRSHRUN:
5678 if (arm_decode_field (given, 19, 20) == 0)
5679 {
5680 *undefined_code = UNDEF_SIZE_0;
5681 return TRUE;
5682 }
5683 else
5684 return FALSE;
5685
66dcaa5d
AV		 5686 case MVE_VABS_VEC:
5687 if (arm_decode_field (given, 18, 19) == 3)
5688 {
5689 *undefined_code = UNDEF_SIZE_3;
5690 return TRUE;
5691 }
5692 else
5693 return FALSE;
5694
e523f101
AV		 5695 case MVE_VCLS:
5696 case MVE_VCLZ:
5697 if (arm_decode_field (given, 18, 19) == 3)
5698 {
5699 *undefined_code = UNDEF_SIZE_3;
5700 return TRUE;
5701 }
5702 else
5703 return FALSE;
5704
9743db03
AV		 5705 default:
5706 return FALSE;
5707 }
73cd51e5
AV		 5708}
5709
5710/* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
5711 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
5712 why this encoding is unpredictable. */
5713
5714static bfd_boolean
5715is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
5716 enum mve_unpredictable *unpredictable_code)
5717{
5718 *unpredictable_code = UNPRED_NONE;
5719
143275ea
AV		 5720 switch (matched_insn)
5721 {
5722 case MVE_VCMP_FP_T2:
5723 case MVE_VPT_FP_T2:
5724 if ((arm_decode_field (given, 12, 12) == 0)
5725 && (arm_decode_field (given, 5, 5) == 1))
5726 {
5727 *unpredictable_code = UNPRED_FCA_0_FCB_1;
5728 return TRUE;
5729 }
5730 else
5731 return FALSE;
73cd51e5 5732
143275ea
AV		 5733 case MVE_VPT_VEC_T4:
5734 case MVE_VPT_VEC_T5:
5735 case MVE_VPT_VEC_T6:
5736 case MVE_VCMP_VEC_T4:
5737 case MVE_VCMP_VEC_T5:
5738 case MVE_VCMP_VEC_T6:
5739 if (arm_decode_field (given, 0, 3) == 0xd)
5740 {
5741 *unpredictable_code = UNPRED_R13;
5742 return TRUE;
5743 }
5744 else
5745 return FALSE;
c1e26897 5746
9743db03
AV		 5747 case MVE_VDUP:
5748 {
5749 unsigned long gpr = arm_decode_field (given, 12, 15);
5750 if (gpr == 0xd)
5751 {
5752 *unpredictable_code = UNPRED_R13;
5753 return TRUE;
5754 }
5755 else if (gpr == 0xf)
5756 {
5757 *unpredictable_code = UNPRED_R15;
5758 return TRUE;
5759 }
5760
5761 return FALSE;
5762 }
5763
e523f101 5764 case MVE_VBRSR:
66dcaa5d
AV		 5765 case MVE_VADD_FP_T2:
5766 case MVE_VSUB_FP_T2:
5767 case MVE_VADD_VEC_T2:
5768 case MVE_VSUB_VEC_T2:
ed63aa17
AV		 5769 case MVE_VQRSHL_T2:
5770 case MVE_VQSHL_T1:
5771 case MVE_VRSHL_T2:
5772 case MVE_VSHL_T2:
5773 case MVE_VSHLC:
d3b63143
AV		 5774 case MVE_VQDMLAH:
5775 case MVE_VQRDMLAH:
5776 case MVE_VQDMLASH:
5777 case MVE_VQRDMLASH:
5778 case MVE_VQDMULH_T3:
5779 case MVE_VQRDMULH_T4:
5780 case MVE_VMLAS:
9743db03
AV		 5781 case MVE_VFMA_FP_SCALAR:
5782 case MVE_VFMAS_FP_SCALAR:
5783 case MVE_VHADD_T2:
5784 case MVE_VHSUB_T2:
5785 {
5786 unsigned long gpr = arm_decode_field (given, 0, 3);
5787 if (gpr == 0xd)
5788 {
5789 *unpredictable_code = UNPRED_R13;
5790 return TRUE;
5791 }
5792 else if (gpr == 0xf)
5793 {
5794 *unpredictable_code = UNPRED_R15;
5795 return TRUE;
5796 }
5797
5798 return FALSE;
5799 }
5800
04d54ace
AV		 5801 case MVE_VLD2:
5802 case MVE_VST2:
5803 {
5804 unsigned long rn = arm_decode_field (given, 16, 19);
5805
5806 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
5807 {
5808 *unpredictable_code = UNPRED_R13_AND_WB;
5809 return TRUE;
5810 }
5811
5812 if (rn == 0xf)
5813 {
5814 *unpredictable_code = UNPRED_R15;
5815 return TRUE;
5816 }
5817
5818 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
5819 {
5820 *unpredictable_code = UNPRED_Q_GT_6;
5821 return TRUE;
5822 }
5823 else
5824 return FALSE;
5825 }
5826
5827 case MVE_VLD4:
5828 case MVE_VST4:
5829 {
5830 unsigned long rn = arm_decode_field (given, 16, 19);
5831
5832 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
5833 {
5834 *unpredictable_code = UNPRED_R13_AND_WB;
5835 return TRUE;
5836 }
5837
5838 if (rn == 0xf)
5839 {
5840 *unpredictable_code = UNPRED_R15;
5841 return TRUE;
5842 }
5843
5844 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
5845 {
5846 *unpredictable_code = UNPRED_Q_GT_4;
5847 return TRUE;
5848 }
5849 else
5850 return FALSE;
5851 }
5852
aef6d006
AV		 5853 case MVE_VLDRB_T5:
5854 case MVE_VLDRH_T6:
5855 case MVE_VLDRW_T7:
5856 case MVE_VSTRB_T5:
5857 case MVE_VSTRH_T6:
5858 case MVE_VSTRW_T7:
5859 {
5860 unsigned long rn = arm_decode_field (given, 16, 19);
5861
5862 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
5863 {
5864 *unpredictable_code = UNPRED_R13_AND_WB;
5865 return TRUE;
5866 }
5867 else if (rn == 0xf)
5868 {
5869 *unpredictable_code = UNPRED_R15;
5870 return TRUE;
5871 }
5872 else
5873 return FALSE;
5874 }
5875
ef1576a1
AV		 5876 case MVE_VLDRB_GATHER_T1:
5877 if (arm_decode_field (given, 0, 0) == 1)
5878 {
5879 *unpredictable_code = UNPRED_OS;
5880 return TRUE;
5881 }
5882
5883 /* fall through. */
5884 /* To handle common code with T2-T4 variants. */
5885 case MVE_VLDRH_GATHER_T2:
5886 case MVE_VLDRW_GATHER_T3:
5887 case MVE_VLDRD_GATHER_T4:
5888 {
5889 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5890 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
5891
5892 if (qd == qm)
5893 {
5894 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
5895 return TRUE;
5896 }
5897
5898 if (arm_decode_field (given, 16, 19) == 0xf)
5899 {
5900 *unpredictable_code = UNPRED_R15;
5901 return TRUE;
5902 }
5903
5904 return FALSE;
5905 }
5906
5907 case MVE_VLDRW_GATHER_T5:
5908 case MVE_VLDRD_GATHER_T6:
5909 {
5910 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
5911 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
5912
5913 if (qd == qm)
5914 {
5915 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
5916 return TRUE;
5917 }
5918 else
5919 return FALSE;
5920 }
5921
5922 case MVE_VSTRB_SCATTER_T1:
5923 if (arm_decode_field (given, 16, 19) == 0xf)
5924 {
5925 *unpredictable_code = UNPRED_R15;
5926 return TRUE;
5927 }
5928 else if (arm_decode_field (given, 0, 0) == 1)
5929 {
5930 *unpredictable_code = UNPRED_OS;
5931 return TRUE;
5932 }
5933 else
5934 return FALSE;
5935
5936 case MVE_VSTRH_SCATTER_T2:
5937 case MVE_VSTRW_SCATTER_T3:
5938 case MVE_VSTRD_SCATTER_T4:
5939 if (arm_decode_field (given, 16, 19) == 0xf)
5940 {
5941 *unpredictable_code = UNPRED_R15;
5942 return TRUE;
5943 }
5944 else
5945 return FALSE;
5946
c507f10b
AV		 5947 case MVE_VMOV2_VEC_LANE_TO_GP:
5948 case MVE_VMOV2_GP_TO_VEC_LANE:
bf0b396d
AV		 5949 case MVE_VCVT_BETWEEN_FP_INT:
5950 case MVE_VCVT_FROM_FP_TO_INT:
5951 {
5952 unsigned long rt = arm_decode_field (given, 0, 3);
5953 unsigned long rt2 = arm_decode_field (given, 16, 19);
5954
5955 if ((rt == 0xd) || (rt2 == 0xd))
5956 {
5957 *unpredictable_code = UNPRED_R13;
5958 return TRUE;
5959 }
5960 else if ((rt == 0xf) || (rt2 == 0xf))
5961 {
5962 *unpredictable_code = UNPRED_R15;
5963 return TRUE;
5964 }
5965 else if (rt == rt2)
5966 {
5967 *unpredictable_code = UNPRED_GP_REGS_EQUAL;
5968 return TRUE;
5969 }
5970
5971 return FALSE;
5972 }
5973
66dcaa5d 5974 case MVE_VABAV:
c507f10b
AV		 5975 case MVE_VMOV_HFP_TO_GP:
5976 case MVE_VMOV_GP_TO_VEC_LANE:
5977 case MVE_VMOV_VEC_LANE_TO_GP:
5978 {
5979 unsigned long rda = arm_decode_field (given, 12, 15);
5980 if (rda == 0xd)
5981 {
5982 *unpredictable_code = UNPRED_R13;
5983 return TRUE;
5984 }
5985 else if (rda == 0xf)
5986 {
5987 *unpredictable_code = UNPRED_R15;
5988 return TRUE;
5989 }
5990
5991 return FALSE;
5992 }
5993
d3b63143
AV		 5994 case MVE_VQRDMLADH:
5995 case MVE_VQDMLSDH:
5996 case MVE_VQRDMLSDH:
5997 case MVE_VQDMLADH:
14925797
AV		 5998 case MVE_VMULL_INT:
5999 {
6000 unsigned long Qd;
6001 unsigned long Qm;
6002 unsigned long Qn;
6003
6004 if (arm_decode_field (given, 20, 21) == 2)
6005 {
6006 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6007 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6008 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6009
6010 if ((Qd == Qn) || (Qd == Qm))
6011 {
6012 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6013 return TRUE;
6014 }
6015 else
6016 return FALSE;
6017 }
6018 else
6019 return FALSE;
6020 }
6021
897b9bbc 6022 case MVE_VCMUL_FP:
14925797
AV		 6023 case MVE_VQDMULL_T1:
6024 {
6025 unsigned long Qd;
6026 unsigned long Qm;
6027 unsigned long Qn;
6028
6029 if (arm_decode_field (given, 28, 28) == 1)
6030 {
6031 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6032 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6033 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6034
6035 if ((Qd == Qn) || (Qd == Qm))
6036 {
6037 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6038 return TRUE;
6039 }
6040 else
6041 return FALSE;
6042 }
6043 else
6044 return FALSE;
6045 }
6046
6047 case MVE_VQDMULL_T2:
6048 {
6049 unsigned long gpr = arm_decode_field (given, 0, 3);
6050 if (gpr == 0xd)
6051 {
6052 *unpredictable_code = UNPRED_R13;
6053 return TRUE;
6054 }
6055 else if (gpr == 0xf)
6056 {
6057 *unpredictable_code = UNPRED_R15;
6058 return TRUE;
6059 }
6060
6061 if (arm_decode_field (given, 28, 28) == 1)
6062 {
6063 unsigned long Qd
6064 = arm_decode_field_multiple (given, 13, 15, 22, 22);
6065 unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6066
6067 if ((Qd == Qn))
6068 {
6069 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6070 return TRUE;
6071 }
6072 else
6073 return FALSE;
6074 }
6075
6076 return FALSE;
6077 }
6078
d3b63143
AV		 6079 case MVE_VMLSLDAV:
6080 case MVE_VRMLSLDAVH:
6081 case MVE_VMLALDAV:
6082 case MVE_VADDLV:
6083 if (arm_decode_field (given, 20, 22) == 6)
6084 {
6085 *unpredictable_code = UNPRED_R13;
6086 return TRUE;
6087 }
6088 else
6089 return FALSE;
6090
1c8f2df8
AV		 6091 case MVE_VDWDUP:
6092 case MVE_VIWDUP:
6093 if (arm_decode_field (given, 1, 3) == 6)
6094 {
6095 *unpredictable_code = UNPRED_R13;
6096 return TRUE;
6097 }
6098 else
6099 return FALSE;
6100
897b9bbc
AV		 6101 case MVE_VCADD_VEC:
6102 case MVE_VHCADD:
6103 {
6104 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6105 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6106 if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
6107 {
6108 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6109 return TRUE;
6110 }
6111 else
6112 return FALSE;
6113 }
6114
6115 case MVE_VCADD_FP:
6116 {
6117 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6118 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6119 if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
6120 {
6121 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6122 return TRUE;
6123 }
6124 else
6125 return FALSE;
6126 }
6127
6128 case MVE_VCMLA_FP:
6129 {
6130 unsigned long Qda;
6131 unsigned long Qm;
6132 unsigned long Qn;
6133
6134 if (arm_decode_field (given, 20, 20) == 1)
6135 {
6136 Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
6137 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6138 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6139
6140 if ((Qda == Qn) || (Qda == Qm))
6141 {
6142 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6143 return TRUE;
6144 }
6145 else
6146 return FALSE;
6147 }
6148 else
6149 return FALSE;
6150
6151 }
6152
e523f101
AV		 6153 case MVE_VCTP:
6154 if (arm_decode_field (given, 16, 19) == 0xd)
6155 {
6156 *unpredictable_code = UNPRED_R13;
6157 return TRUE;
6158 }
6159 else
6160 return FALSE;
6161
143275ea
AV		 6162 default:
6163 return FALSE;
6164 }
6165}
c1e26897 6166
c507f10b
AV		 6167static void
6168print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
6169{
6170 unsigned long op1 = arm_decode_field (given, 21, 22);
6171 unsigned long op2 = arm_decode_field (given, 5, 6);
6172 unsigned long h = arm_decode_field (given, 16, 16);
6173 unsigned long index, esize, targetBeat, idx;
6174 void *stream = info->stream;
6175 fprintf_ftype func = info->fprintf_func;
6176
6177 if ((op1 & 0x2) == 0x2)
6178 {
6179 index = op2;
6180 esize = 8;
6181 }
6182 else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
6183 {
6184 index = op2 >> 1;
6185 esize = 16;
6186 }
6187 else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
6188 {
6189 index = 0;
6190 esize = 32;
6191 }
6192 else
6193 {
6194 func (stream, "<undefined index>");
6195 return;
6196 }
6197
6198 targetBeat = (op1 & 0x1) | (h << 1);
6199 idx = index + targetBeat * (32/esize);
6200
6201 func (stream, "%lu", idx);
6202}
6203
6204/* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6205 in length and integer of floating-point type. */
6206static void
6207print_simd_imm8 (struct disassemble_info *info, unsigned long given,
6208 unsigned int ibit_loc, const struct mopcode32 *insn)
6209{
6210 int bits = 0;
6211 int cmode = (given >> 8) & 0xf;
6212 int op = (given >> 5) & 0x1;
6213 unsigned long value = 0, hival = 0;
6214 unsigned shift;
6215 int size = 0;
6216 int isfloat = 0;
6217 void *stream = info->stream;
6218 fprintf_ftype func = info->fprintf_func;
6219
6220 /* On Neon the 'i' bit is at bit 24, on mve it is
6221 at bit 28. */
6222 bits |= ((given >> ibit_loc) & 1) << 7;
6223 bits |= ((given >> 16) & 7) << 4;
6224 bits |= ((given >> 0) & 15) << 0;
6225
6226 if (cmode < 8)
6227 {
6228 shift = (cmode >> 1) & 3;
6229 value = (unsigned long) bits << (8 * shift);
6230 size = 32;
6231 }
6232 else if (cmode < 12)
6233 {
6234 shift = (cmode >> 1) & 1;
6235 value = (unsigned long) bits << (8 * shift);
6236 size = 16;
6237 }
6238 else if (cmode < 14)
6239 {
6240 shift = (cmode & 1) + 1;
6241 value = (unsigned long) bits << (8 * shift);
6242 value |= (1ul << (8 * shift)) - 1;
6243 size = 32;
6244 }
6245 else if (cmode == 14)
6246 {
6247 if (op)
6248 {
6249 /* Bit replication into bytes. */
6250 int ix;
6251 unsigned long mask;
6252
6253 value = 0;
6254 hival = 0;
6255 for (ix = 7; ix >= 0; ix--)
6256 {
6257 mask = ((bits >> ix) & 1) ? 0xff : 0;
6258 if (ix <= 3)
6259 value = (value << 8) | mask;
6260 else
6261 hival = (hival << 8) | mask;
6262 }
6263 size = 64;
6264 }
6265 else
6266 {
6267 /* Byte replication. */
6268 value = (unsigned long) bits;
6269 size = 8;
6270 }
6271 }
6272 else if (!op)
6273 {
6274 /* Floating point encoding. */
6275 int tmp;
6276
6277 value = (unsigned long) (bits & 0x7f) << 19;
6278 value |= (unsigned long) (bits & 0x80) << 24;
6279 tmp = bits & 0x40 ? 0x3c : 0x40;
6280 value |= (unsigned long) tmp << 24;
6281 size = 32;
6282 isfloat = 1;
6283 }
6284 else
6285 {
6286 func (stream, "<illegal constant %.8x:%x:%x>",
6287 bits, cmode, op);
6288 size = 32;
6289 return;
6290 }
6291
6292 // printU determines whether the immediate value should be printed as
6293 // unsigned.
6294 unsigned printU = 0;
6295 switch (insn->mve_op)
6296 {
6297 default:
6298 break;
6299 // We want this for instructions that don't have a 'signed' type
6300 case MVE_VBIC_IMM:
6301 case MVE_VORR_IMM:
6302 case MVE_VMVN_IMM:
6303 case MVE_VMOV_IMM_TO_VEC:
6304 printU = 1;
6305 break;
6306 }
6307 switch (size)
6308 {
6309 case 8:
6310 func (stream, "#%ld\t; 0x%.2lx", value, value);
6311 break;
6312
6313 case 16:
6314 func (stream,
6315 printU
6316 ? "#%lu\t; 0x%.4lx"
6317 : "#%ld\t; 0x%.4lx", value, value);
6318 break;
6319
6320 case 32:
6321 if (isfloat)
6322 {
6323 unsigned char valbytes[4];
6324 double fvalue;
6325
6326 /* Do this a byte at a time so we don't have to
6327 worry about the host's endianness. */
6328 valbytes[0] = value & 0xff;
6329 valbytes[1] = (value >> 8) & 0xff;
6330 valbytes[2] = (value >> 16) & 0xff;
6331 valbytes[3] = (value >> 24) & 0xff;
6332
6333 floatformat_to_double
6334 (& floatformat_ieee_single_little, valbytes,
6335 & fvalue);
6336
6337 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
6338 value);
6339 }
6340 else
6341 func (stream,
6342 printU
6343 ? "#%lu\t; 0x%.8lx"
6344 : "#%ld\t; 0x%.8lx",
6345 (long) (((value & 0x80000000L) != 0)
6346 && !printU
6347 ? value | ~0xffffffffL : value),
6348 value);
6349 break;
6350
6351 case 64:
6352 func (stream, "#0x%.8lx%.8lx", hival, value);
6353 break;
6354
6355 default:
6356 abort ();
6357 }
6358
6359}
6360
73cd51e5
AV		 6361static void
6362print_mve_undefined (struct disassemble_info *info,
6363 enum mve_undefined undefined_code)
6364{
6365 void *stream = info->stream;
6366 fprintf_ftype func = info->fprintf_func;
6367
6368 func (stream, "\t\tundefined instruction: ");
6369
6370 switch (undefined_code)
6371 {
ed63aa17
AV		 6372 case UNDEF_SIZE:
6373 func (stream, "illegal size");
6374 break;
6375
aef6d006
AV		 6376 case UNDEF_SIZE_0:
6377 func (stream, "size equals zero");
6378 break;
6379
c507f10b
AV		 6380 case UNDEF_SIZE_2:
6381 func (stream, "size equals two");
6382 break;
6383
9743db03
AV		 6384 case UNDEF_SIZE_3:
6385 func (stream, "size equals three");
6386 break;
6387
aef6d006
AV		 6388 case UNDEF_SIZE_LE_1:
6389 func (stream, "size <= 1");
6390 break;
6391
ef1576a1
AV		 6392 case UNDEF_SIZE_NOT_2:
6393 func (stream, "size not equal to 2");
6394 break;
6395
6396 case UNDEF_SIZE_NOT_3:
6397 func (stream, "size not equal to 3");
6398 break;
6399
6400 case UNDEF_NOT_UNS_SIZE_0:
6401 func (stream, "not unsigned and size = zero");
6402 break;
6403
6404 case UNDEF_NOT_UNS_SIZE_1:
6405 func (stream, "not unsigned and size = one");
6406 break;
6407
6408 case UNDEF_NOT_UNSIGNED:
6409 func (stream, "not unsigned");
6410 break;
6411
bf0b396d
AV		 6412 case UNDEF_VCVT_IMM6:
6413 func (stream, "invalid imm6");
6414 break;
6415
6416 case UNDEF_VCVT_FSI_IMM6:
6417 func (stream, "fsi = 0 and invalid imm6");
6418 break;
6419
c507f10b
AV		 6420 case UNDEF_BAD_OP1_OP2:
6421 func (stream, "bad size with op2 = 2 and op1 = 0 or 1");
6422 break;
6423
6424 case UNDEF_BAD_U_OP1_OP2:
6425 func (stream, "unsigned with op2 = 0 and op1 = 0 or 1");
6426 break;
6427
6428 case UNDEF_OP_0_BAD_CMODE:
6429 func (stream, "op field equal 0 and bad cmode");
6430 break;
6431
d3b63143
AV		 6432 case UNDEF_XCHG_UNS:
6433 func (stream, "exchange and unsigned together");
6434 break;
6435
73cd51e5
AV		 6436 case UNDEF_NONE:
6437 break;
6438 }
6439
6440}
6441
6442static void
6443print_mve_unpredictable (struct disassemble_info *info,
6444 enum mve_unpredictable unpredict_code)
6445{
6446 void *stream = info->stream;
6447 fprintf_ftype func = info->fprintf_func;
6448
6449 func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
6450
6451 switch (unpredict_code)
6452 {
6453 case UNPRED_IT_BLOCK:
6454 func (stream, "mve instruction in it block");
6455 break;
6456
143275ea
AV		 6457 case UNPRED_FCA_0_FCB_1:
6458 func (stream, "condition bits, fca = 0 and fcb = 1");
6459 break;
6460
6461 case UNPRED_R13:
6462 func (stream, "use of r13 (sp)");
6463 break;
6464
9743db03
AV		 6465 case UNPRED_R15:
6466 func (stream, "use of r15 (pc)");
6467 break;
6468
04d54ace
AV		 6469 case UNPRED_Q_GT_4:
6470 func (stream, "start register block > r4");
6471 break;
6472
6473 case UNPRED_Q_GT_6:
6474 func (stream, "start register block > r6");
6475 break;
6476
6477 case UNPRED_R13_AND_WB:
6478 func (stream, "use of r13 and write back");
6479 break;
6480
ef1576a1
AV		 6481 case UNPRED_Q_REGS_EQUAL:
6482 func (stream,
6483 "same vector register used for destination and other operand");
6484 break;
6485
6486 case UNPRED_OS:
6487 func (stream, "use of offset scaled");
6488 break;
6489
bf0b396d
AV		 6490 case UNPRED_GP_REGS_EQUAL:
6491 func (stream, "same general-purpose register used for both operands");
6492 break;
6493
c507f10b
AV		 6494 case UNPRED_Q_REGS_EQ_AND_SIZE_1:
6495 func (stream, "use of identical q registers and size = 1");
6496 break;
6497
6498 case UNPRED_Q_REGS_EQ_AND_SIZE_2:
6499 func (stream, "use of identical q registers and size = 1");
6500 break;
6501
73cd51e5
AV		 6502 case UNPRED_NONE:
6503 break;
6504 }
6505}
6506
04d54ace
AV		 6507/* Print register block operand for mve vld2/vld4/vst2/vld4. */
6508
6509static void
6510print_mve_register_blocks (struct disassemble_info *info,
6511 unsigned long given,
6512 enum mve_instructions matched_insn)
6513{
6514 void *stream = info->stream;
6515 fprintf_ftype func = info->fprintf_func;
6516
6517 unsigned long q_reg_start = arm_decode_field_multiple (given,
6518 13, 15,
6519 22, 22);
6520 switch (matched_insn)
6521 {
6522 case MVE_VLD2:
6523 case MVE_VST2:
6524 if (q_reg_start <= 6)
6525 func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
6526 else
6527 func (stream, "<illegal reg q%ld>", q_reg_start);
6528 break;
6529
6530 case MVE_VLD4:
6531 case MVE_VST4:
6532 if (q_reg_start <= 4)
6533 func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
6534 q_reg_start + 1, q_reg_start + 2,
6535 q_reg_start + 3);
6536 else
6537 func (stream, "<illegal reg q%ld>", q_reg_start);
6538 break;
6539
6540 default:
6541 break;
6542 }
6543}
6544
bf0b396d
AV		 6545static void
6546print_mve_rounding_mode (struct disassemble_info *info,
6547 unsigned long given,
6548 enum mve_instructions matched_insn)
6549{
6550 void *stream = info->stream;
6551 fprintf_ftype func = info->fprintf_func;
6552
6553 switch (matched_insn)
6554 {
6555 case MVE_VCVT_FROM_FP_TO_INT:
6556 {
6557 switch (arm_decode_field (given, 8, 9))
6558 {
6559 case 0:
6560 func (stream, "a");
6561 break;
6562
6563 case 1:
6564 func (stream, "n");
6565 break;
6566
6567 case 2:
6568 func (stream, "p");
6569 break;
6570
6571 case 3:
6572 func (stream, "m");
6573 break;
6574
6575 default:
6576 break;
6577 }
6578 }
6579 break;
6580
6581 case MVE_VRINT_FP:
6582 {
6583 switch (arm_decode_field (given, 7, 9))
6584 {
6585 case 0:
6586 func (stream, "n");
6587 break;
6588
6589 case 1:
6590 func (stream, "x");
6591 break;
6592
6593 case 2:
6594 func (stream, "a");
6595 break;
6596
6597 case 3:
6598 func (stream, "z");
6599 break;
6600
6601 case 5:
6602 func (stream, "m");
6603 break;
6604
6605 case 7:
6606 func (stream, "p");
6607
6608 case 4:
6609 case 6:
6610 default:
6611 break;
6612 }
6613 }
6614 break;
6615
6616 default:
6617 break;
6618 }
6619}
6620
6621static void
6622print_mve_vcvt_size (struct disassemble_info *info,
6623 unsigned long given,
6624 enum mve_instructions matched_insn)
6625{
6626 unsigned long mode = 0;
6627 void *stream = info->stream;
6628 fprintf_ftype func = info->fprintf_func;
6629
6630 switch (matched_insn)
6631 {
6632 case MVE_VCVT_FP_FIX_VEC:
6633 {
6634 mode = (((given & 0x200) >> 7)
6635 | ((given & 0x10000000) >> 27)
6636 | ((given & 0x100) >> 8));
6637
6638 switch (mode)
6639 {
6640 case 0:
6641 func (stream, "f16.s16");
6642 break;
6643
6644 case 1:
6645 func (stream, "s16.f16");
6646 break;
6647
6648 case 2:
6649 func (stream, "f16.u16");
6650 break;
6651
6652 case 3:
6653 func (stream, "u16.f16");
6654 break;
6655
6656 case 4:
6657 func (stream, "f32.s32");
6658 break;
6659
6660 case 5:
6661 func (stream, "s32.f32");
6662 break;
6663
6664 case 6:
6665 func (stream, "f32.u32");
6666 break;
6667
6668 case 7:
6669 func (stream, "u32.f32");
6670 break;
6671
6672 default:
6673 break;
6674 }
6675 break;
6676 }
6677 case MVE_VCVT_BETWEEN_FP_INT:
6678 {
6679 unsigned long size = arm_decode_field (given, 18, 19);
6680 unsigned long op = arm_decode_field (given, 7, 8);
6681
6682 if (size == 1)
6683 {
6684 switch (op)
6685 {
6686 case 0:
6687 func (stream, "f16.s16");
6688 break;
6689
6690 case 1:
6691 func (stream, "f16.u16");
6692 break;
6693
6694 case 2:
6695 func (stream, "s16.f16");
6696 break;
6697
6698 case 3:
6699 func (stream, "u16.f16");
6700 break;
6701
6702 default:
6703 break;
6704 }
6705 }
6706 else if (size == 2)
6707 {
6708 switch (op)
6709 {
6710 case 0:
6711 func (stream, "f32.s32");
6712 break;
6713
6714 case 1:
6715 func (stream, "f32.u32");
6716 break;
6717
6718 case 2:
6719 func (stream, "s32.f32");
6720 break;
6721
6722 case 3:
6723 func (stream, "u32.f32");
6724 break;
6725 }
6726 }
6727 }
6728 break;
6729
6730 case MVE_VCVT_FP_HALF_FP:
6731 {
6732 unsigned long op = arm_decode_field (given, 28, 28);
6733 if (op == 0)
6734 func (stream, "f16.f32");
6735 else if (op == 1)
6736 func (stream, "f32.f16");
6737 }
6738 break;
6739
6740 case MVE_VCVT_FROM_FP_TO_INT:
6741 {
6742 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
6743
6744 switch (size)
6745 {
6746 case 2:
6747 func (stream, "s16.f16");
6748 break;
6749
6750 case 3:
6751 func (stream, "u16.f16");
6752 break;
6753
6754 case 4:
6755 func (stream, "s32.f32");
6756 break;
6757
6758 case 5:
6759 func (stream, "u32.f32");
6760 break;
6761
6762 default:
6763 break;
6764 }
6765 }
6766 break;
6767
6768 default:
6769 break;
6770 }
6771}
6772
897b9bbc
AV		 6773static void
6774print_mve_rotate (struct disassemble_info *info, unsigned long rot,
6775 unsigned long rot_width)
6776{
6777 void *stream = info->stream;
6778 fprintf_ftype func = info->fprintf_func;
6779
6780 if (rot_width == 1)
6781 {
6782 switch (rot)
6783 {
6784 case 0:
6785 func (stream, "90");
6786 break;
6787 case 1:
6788 func (stream, "270");
6789 break;
6790 default:
6791 break;
6792 }
6793 }
6794 else if (rot_width == 2)
6795 {
6796 switch (rot)
6797 {
6798 case 0:
6799 func (stream, "0");
6800 break;
6801 case 1:
6802 func (stream, "90");
6803 break;
6804 case 2:
6805 func (stream, "180");
6806 break;
6807 case 3:
6808 func (stream, "270");
6809 break;
6810 default:
6811 break;
6812 }
6813 }
6814}
6815
143275ea
AV		 6816static void
6817print_instruction_predicate (struct disassemble_info *info)
6818{
6819 void *stream = info->stream;
6820 fprintf_ftype func = info->fprintf_func;
6821
6822 if (vpt_block_state.next_pred_state == PRED_THEN)
6823 func (stream, "t");
6824 else if (vpt_block_state.next_pred_state == PRED_ELSE)
6825 func (stream, "e");
6826}
6827
6828static void
6829print_mve_size (struct disassemble_info *info,
6830 unsigned long size,
6831 enum mve_instructions matched_insn)
6832{
6833 void *stream = info->stream;
6834 fprintf_ftype func = info->fprintf_func;
6835
6836 switch (matched_insn)
6837 {
66dcaa5d
AV		 6838 case MVE_VABAV:
6839 case MVE_VABD_VEC:
6840 case MVE_VABS_FP:
6841 case MVE_VABS_VEC:
6842 case MVE_VADD_VEC_T1:
6843 case MVE_VADD_VEC_T2:
d3b63143 6844 case MVE_VADDV:
e523f101 6845 case MVE_VBRSR:
897b9bbc 6846 case MVE_VCADD_VEC:
e523f101
AV		 6847 case MVE_VCLS:
6848 case MVE_VCLZ:
143275ea
AV		 6849 case MVE_VCMP_VEC_T1:
6850 case MVE_VCMP_VEC_T2:
6851 case MVE_VCMP_VEC_T3:
6852 case MVE_VCMP_VEC_T4:
6853 case MVE_VCMP_VEC_T5:
6854 case MVE_VCMP_VEC_T6:
e523f101 6855 case MVE_VCTP:
1c8f2df8
AV		 6856 case MVE_VDDUP:
6857 case MVE_VDWDUP:
9743db03
AV		 6858 case MVE_VHADD_T1:
6859 case MVE_VHADD_T2:
897b9bbc 6860 case MVE_VHCADD:
9743db03
AV		 6861 case MVE_VHSUB_T1:
6862 case MVE_VHSUB_T2:
1c8f2df8
AV		 6863 case MVE_VIDUP:
6864 case MVE_VIWDUP:
04d54ace
AV		 6865 case MVE_VLD2:
6866 case MVE_VLD4:
ef1576a1
AV		 6867 case MVE_VLDRB_GATHER_T1:
6868 case MVE_VLDRH_GATHER_T2:
6869 case MVE_VLDRW_GATHER_T3:
6870 case MVE_VLDRD_GATHER_T4:
aef6d006
AV		 6871 case MVE_VLDRB_T1:
6872 case MVE_VLDRH_T2:
d3b63143 6873 case MVE_VMLAS:
143275ea
AV		 6874 case MVE_VPT_VEC_T1:
6875 case MVE_VPT_VEC_T2:
6876 case MVE_VPT_VEC_T3:
6877 case MVE_VPT_VEC_T4:
6878 case MVE_VPT_VEC_T5:
6879 case MVE_VPT_VEC_T6:
d3b63143
AV		 6880 case MVE_VQDMLADH:
6881 case MVE_VQRDMLADH:
6882 case MVE_VQDMLAH:
6883 case MVE_VQRDMLAH:
6884 case MVE_VQDMLASH:
6885 case MVE_VQRDMLASH:
6886 case MVE_VQDMLSDH:
6887 case MVE_VQRDMLSDH:
6888 case MVE_VQDMULH_T1:
6889 case MVE_VQRDMULH_T2:
6890 case MVE_VQDMULH_T3:
6891 case MVE_VQRDMULH_T4:
ed63aa17
AV		 6892 case MVE_VQRSHL_T1:
6893 case MVE_VQRSHL_T2:
6894 case MVE_VQSHL_T1:
6895 case MVE_VQSHL_T4:
9743db03 6896 case MVE_VRHADD:
bf0b396d 6897 case MVE_VRINT_FP:
ed63aa17
AV		 6898 case MVE_VRSHL_T1:
6899 case MVE_VRSHL_T2:
6900 case MVE_VSHL_T2:
6901 case MVE_VSHL_T3:
6902 case MVE_VSHLL_T2:
04d54ace
AV		 6903 case MVE_VST2:
6904 case MVE_VST4:
ef1576a1
AV		 6905 case MVE_VSTRB_SCATTER_T1:
6906 case MVE_VSTRH_SCATTER_T2:
6907 case MVE_VSTRW_SCATTER_T3:
aef6d006
AV		 6908 case MVE_VSTRB_T1:
6909 case MVE_VSTRH_T2:
66dcaa5d
AV		 6910 case MVE_VSUB_VEC_T1:
6911 case MVE_VSUB_VEC_T2:
143275ea
AV		 6912 if (size <= 3)
6913 func (stream, "%s", mve_vec_sizename[size]);
6914 else
6915 func (stream, "<undef size>");
6916 break;
6917
66dcaa5d
AV		 6918 case MVE_VABD_FP:
6919 case MVE_VADD_FP_T1:
6920 case MVE_VADD_FP_T2:
6921 case MVE_VSUB_FP_T1:
6922 case MVE_VSUB_FP_T2:
143275ea
AV		 6923 case MVE_VCMP_FP_T1:
6924 case MVE_VCMP_FP_T2:
9743db03
AV		 6925 case MVE_VFMA_FP_SCALAR:
6926 case MVE_VFMA_FP:
6927 case MVE_VFMS_FP:
6928 case MVE_VFMAS_FP_SCALAR:
143275ea
AV		 6929 case MVE_VPT_FP_T1:
6930 case MVE_VPT_FP_T2:
6931 if (size == 0)
6932 func (stream, "32");
6933 else if (size == 1)
6934 func (stream, "16");
6935 break;
6936
897b9bbc
AV		 6937 case MVE_VCADD_FP:
6938 case MVE_VCMLA_FP:
6939 case MVE_VCMUL_FP:
d3b63143
AV		 6940 case MVE_VMLADAV_T1:
6941 case MVE_VMLALDAV:
6942 case MVE_VMLSDAV_T1:
6943 case MVE_VMLSLDAV:
14925797
AV		 6944 case MVE_VMOVN:
6945 case MVE_VQDMULL_T1:
6946 case MVE_VQDMULL_T2:
6947 case MVE_VQMOVN:
6948 case MVE_VQMOVUN:
6949 if (size == 0)
6950 func (stream, "16");
6951 else if (size == 1)
6952 func (stream, "32");
6953 break;
6954
6955 case MVE_VMOVL:
6956 if (size == 1)
6957 func (stream, "8");
6958 else if (size == 2)
6959 func (stream, "16");
6960 break;
6961
9743db03
AV		 6962 case MVE_VDUP:
6963 switch (size)
6964 {
6965 case 0:
6966 func (stream, "32");
6967 break;
6968 case 1:
6969 func (stream, "16");
6970 break;
6971 case 2:
6972 func (stream, "8");
6973 break;
6974 default:
6975 break;
6976 }
6977 break;
6978
c507f10b
AV		 6979 case MVE_VMOV_GP_TO_VEC_LANE:
6980 case MVE_VMOV_VEC_LANE_TO_GP:
6981 switch (size)
6982 {
6983 case 0: case 4:
6984 func (stream, "32");
6985 break;
6986
6987 case 1: case 3:
6988 case 5: case 7:
6989 func (stream, "16");
6990 break;
6991
6992 case 8: case 9: case 10: case 11:
6993 case 12: case 13: case 14: case 15:
6994 func (stream, "8");
6995 break;
6996
6997 default:
6998 break;
6999 }
7000 break;
7001
7002 case MVE_VMOV_IMM_TO_VEC:
7003 switch (size)
7004 {
7005 case 0: case 4: case 8:
7006 case 12: case 24: case 26:
7007 func (stream, "i32");
7008 break;
7009 case 16: case 20:
7010 func (stream, "i16");
7011 break;
7012 case 28:
7013 func (stream, "i8");
7014 break;
7015 case 29:
7016 func (stream, "i64");
7017 break;
7018 case 30:
7019 func (stream, "f32");
7020 break;
7021 default:
7022 break;
7023 }
7024 break;
7025
14925797
AV		 7026 case MVE_VMULL_POLY:
7027 if (size == 0)
7028 func (stream, "p8");
7029 else if (size == 1)
7030 func (stream, "p16");
7031 break;
7032
c507f10b
AV		 7033 case MVE_VMVN_IMM:
7034 switch (size)
7035 {
7036 case 0: case 2: case 4:
7037 case 6: case 12: case 13:
7038 func (stream, "32");
7039 break;
7040
7041 case 8: case 10:
7042 func (stream, "16");
7043 break;
7044
7045 default:
7046 break;
7047 }
7048 break;
7049
7050 case MVE_VBIC_IMM:
7051 case MVE_VORR_IMM:
7052 switch (size)
7053 {
7054 case 1: case 3:
7055 case 5: case 7:
7056 func (stream, "32");
7057 break;
7058
7059 case 9: case 11:
7060 func (stream, "16");
7061 break;
7062
7063 default:
7064 break;
7065 }
7066 break;
7067
ed63aa17
AV		 7068 case MVE_VQSHRN:
7069 case MVE_VQSHRUN:
7070 case MVE_VQRSHRN:
7071 case MVE_VQRSHRUN:
7072 case MVE_VRSHRN:
7073 case MVE_VSHRN:
7074 {
7075 switch (size)
7076 {
7077 case 1:
7078 func (stream, "16");
7079 break;
7080
7081 case 2: case 3:
7082 func (stream, "32");
7083 break;
7084
7085 default:
7086 break;
7087 }
7088 }
7089 break;
7090
7091 case MVE_VQSHL_T2:
7092 case MVE_VQSHLU_T3:
7093 case MVE_VRSHR:
7094 case MVE_VSHL_T1:
7095 case MVE_VSHLL_T1:
7096 case MVE_VSHR:
7097 case MVE_VSLI:
7098 case MVE_VSRI:
7099 {
7100 switch (size)
7101 {
7102 case 1:
7103 func (stream, "8");
7104 break;
7105
7106 case 2: case 3:
7107 func (stream, "16");
7108 break;
7109
7110 case 4: case 5: case 6: case 7:
7111 func (stream, "32");
7112 break;
7113
7114 default:
7115 break;
7116 }
7117 }
7118 break;
7119
143275ea
AV		 7120 default:
7121 break;
7122 }
7123}
7124
ed63aa17
AV		 7125static void
7126print_mve_shift_n (struct disassemble_info *info, long given,
7127 enum mve_instructions matched_insn)
7128{
7129 void *stream = info->stream;
7130 fprintf_ftype func = info->fprintf_func;
7131
7132 int startAt0
7133 = matched_insn == MVE_VQSHL_T2
7134 || matched_insn == MVE_VQSHLU_T3
7135 || matched_insn == MVE_VSHL_T1
7136 || matched_insn == MVE_VSHLL_T1
7137 || matched_insn == MVE_VSLI;
7138
7139 unsigned imm6 = (given & 0x3f0000) >> 16;
7140
7141 if (matched_insn == MVE_VSHLL_T1)
7142 imm6 &= 0x1f;
7143
7144 unsigned shiftAmount = 0;
7145 if ((imm6 & 0x20) != 0)
7146 shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
7147 else if ((imm6 & 0x10) != 0)
7148 shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
7149 else if ((imm6 & 0x08) != 0)
7150 shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
7151 else
7152 print_mve_undefined (info, UNDEF_SIZE_0);
7153
7154 func (stream, "%u", shiftAmount);
7155}
7156
143275ea
AV		 7157static void
7158print_vec_condition (struct disassemble_info *info, long given,
7159 enum mve_instructions matched_insn)
7160{
7161 void *stream = info->stream;
7162 fprintf_ftype func = info->fprintf_func;
7163 long vec_cond = 0;
7164
7165 switch (matched_insn)
7166 {
7167 case MVE_VPT_FP_T1:
7168 case MVE_VCMP_FP_T1:
7169 vec_cond = (((given & 0x1000) >> 10)
7170 | ((given & 1) << 1)
7171 | ((given & 0x0080) >> 7));
7172 func (stream, "%s",vec_condnames[vec_cond]);
7173 break;
7174
7175 case MVE_VPT_FP_T2:
7176 case MVE_VCMP_FP_T2:
7177 vec_cond = (((given & 0x1000) >> 10)
7178 | ((given & 0x0020) >> 4)
7179 | ((given & 0x0080) >> 7));
7180 func (stream, "%s",vec_condnames[vec_cond]);
7181 break;
7182
7183 case MVE_VPT_VEC_T1:
7184 case MVE_VCMP_VEC_T1:
7185 vec_cond = (given & 0x0080) >> 7;
7186 func (stream, "%s",vec_condnames[vec_cond]);
7187 break;
7188
7189 case MVE_VPT_VEC_T2:
7190 case MVE_VCMP_VEC_T2:
7191 vec_cond = 2 | ((given & 0x0080) >> 7);
7192 func (stream, "%s",vec_condnames[vec_cond]);
7193 break;
7194
7195 case MVE_VPT_VEC_T3:
7196 case MVE_VCMP_VEC_T3:
7197 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
7198 func (stream, "%s",vec_condnames[vec_cond]);
7199 break;
7200
7201 case MVE_VPT_VEC_T4:
7202 case MVE_VCMP_VEC_T4:
7203 vec_cond = (given & 0x0080) >> 7;
7204 func (stream, "%s",vec_condnames[vec_cond]);
7205 break;
7206
7207 case MVE_VPT_VEC_T5:
7208 case MVE_VCMP_VEC_T5:
7209 vec_cond = 2 | ((given & 0x0080) >> 7);
7210 func (stream, "%s",vec_condnames[vec_cond]);
7211 break;
7212
7213 case MVE_VPT_VEC_T6:
7214 case MVE_VCMP_VEC_T6:
7215 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
7216 func (stream, "%s",vec_condnames[vec_cond]);
7217 break;
7218
7219 case MVE_NONE:
7220 case MVE_VPST:
7221 default:
7222 break;
7223 }
7224}
7225
7226#define W_BIT 21
7227#define I_BIT 22
7228#define U_BIT 23
7229#define P_BIT 24
7230
7231#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
7232#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
7233#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
7234#define PRE_BIT_SET (given & (1 << P_BIT))
7235
7236
8f06b2d8
PB		 7237/* Print one coprocessor instruction on INFO->STREAM.
7238 Return TRUE if the instuction matched, FALSE if this is not a
7239 recognised coprocessor instruction. */
7240
7241static bfd_boolean
fe56b6ce
NC		 7242print_insn_coprocessor (bfd_vma pc,
7243 struct disassemble_info *info,
7244 long given,
8f06b2d8
PB		 7245 bfd_boolean thumb)
7246{
6b0dd094 7247 const struct sopcode32 *insn;
8f06b2d8
PB		 7248 void *stream = info->stream;
7249 fprintf_ftype func = info->fprintf_func;
7250 unsigned long mask;
2edcd244 7251 unsigned long value = 0;
c22aaad1 7252 int cond;
8afc7bea 7253 int cp_num;
823d2571
TG		 7254 struct arm_private_data *private_data = info->private_data;
7255 arm_feature_set allowed_arches = ARM_ARCH_NONE;
32c36c3c
AV		 7256 arm_feature_set arm_ext_v8_1m_main =
7257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
823d2571 7258
5b616bef 7259 allowed_arches = private_data->features;
8f06b2d8
PB		 7260
7261 for (insn = coprocessor_opcodes; insn->assembler; insn++)
7262 {
ff4a8d2b
NC		 7263 unsigned long u_reg = 16;
7264 bfd_boolean is_unpredictable = FALSE;
05413229 7265 signed long value_in_comment = 0;
0313a2b8
NC		 7266 const char *c;
7267
823d2571 7268 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 7269 switch (insn->value)
7270 {
7271 case SENTINEL_IWMMXT_START:
7272 if (info->mach != bfd_mach_arm_XScale
7273 && info->mach != bfd_mach_arm_iWMMXt
7274 && info->mach != bfd_mach_arm_iWMMXt2)
7275 do
7276 insn++;
823d2571
TG		 7277 while ((! ARM_FEATURE_ZERO (insn->arch))
7278 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 7279 continue;
7280
7281 case SENTINEL_IWMMXT_END:
7282 continue;
7283
7284 case SENTINEL_GENERIC_START:
5b616bef 7285 allowed_arches = private_data->features;
05413229
NC		 7286 continue;
7287
7288 default:
7289 abort ();
7290 }
8f06b2d8
PB		 7291
7292 mask = insn->mask;
7293 value = insn->value;
8afc7bea
RL		 7294 cp_num = (given >> 8) & 0xf;
7295
8f06b2d8
PB		 7296 if (thumb)
7297 {
7298 /* The high 4 bits are 0xe for Arm conditional instructions, and
7299 0xe for arm unconditional instructions. The rest of the
7300 encoding is the same. */
7301 mask |= 0xf0000000;
7302 value |= 0xe0000000;
c22aaad1
PB		 7303 if (ifthen_state)
7304 cond = IFTHEN_COND;
7305 else
e2efe87d 7306 cond = COND_UNCOND;
8f06b2d8
PB		 7307 }
7308 else
7309 {
7310 /* Only match unconditional instuctions against unconditional
7311 patterns. */
7312 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 7313 {
7314 mask |= 0xf0000000;
e2efe87d 7315 cond = COND_UNCOND;
c22aaad1
PB		 7316 }
7317 else
7318 {
7319 cond = (given >> 28) & 0xf;
7320 if (cond == 0xe)
e2efe87d 7321 cond = COND_UNCOND;
c22aaad1 7322 }
8f06b2d8 7323 }
823d2571 7324
6b0dd094
AV		 7325 if ((insn->isa == T32 && !thumb)
7326 || (insn->isa == ARM && thumb))
7327 continue;
7328
0313a2b8
NC		 7329 if ((given & mask) != value)
7330 continue;
8f06b2d8 7331
823d2571 7332 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 7333 continue;
7334
8afc7bea
RL		 7335 if (insn->value == 0xfe000010 /* mcr2 */
7336 || insn->value == 0xfe100010 /* mrc2 */
7337 || insn->value == 0xfc100000 /* ldc2 */
7338 || insn->value == 0xfc000000) /* stc2 */
7339 {
b0c11777 7340 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 7341 is_unpredictable = TRUE;
f08d8ce3
AV		 7342
7343 /* Armv8.1-M Mainline FP & MVE instructions. */
7344 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
7345 && !ARM_CPU_IS_ANY (allowed_arches)
7346 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
7347 continue;
7348
8afc7bea
RL		 7349 }
7350 else if (insn->value == 0x0e000000 /* cdp */
7351 || insn->value == 0xfe000000 /* cdp2 */
7352 || insn->value == 0x0e000010 /* mcr */
7353 || insn->value == 0x0e100010 /* mrc */
7354 || insn->value == 0x0c100000 /* ldc */
7355 || insn->value == 0x0c000000) /* stc */
7356 {
7357 /* Floating-point instructions. */
b0c11777 7358 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 7359 continue;
32c36c3c
AV		 7360
7361 /* Armv8.1-M Mainline FP & MVE instructions. */
7362 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
7363 && !ARM_CPU_IS_ANY (allowed_arches)
7364 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
7365 continue;
8afc7bea 7366 }
aef6d006
AV		 7367 else if ((insn->value == 0xec100f80 /* vldr (system register) */
7368 || insn->value == 0xec000f80) /* vstr (system register) */
7369 && arm_decode_field (given, 24, 24) == 0
7370 && arm_decode_field (given, 21, 21) == 0)
7371 /* If the P and W bits are both 0 then these encodings match the MVE
7372 VLDR and VSTR instructions, these are in a different table, so we
7373 don't let it match here. */
7374 continue;
7375
0313a2b8
NC		 7376 for (c = insn->assembler; *c; c++)
7377 {
7378 if (*c == '%')
8f06b2d8 7379 {
32c36c3c
AV		 7380 const char mod = *++c;
7381 switch (mod)
8f06b2d8 7382 {
0313a2b8
NC		 7383 case '%':
7384 func (stream, "%%");
7385 break;
7386
7387 case 'A':
32c36c3c 7388 case 'K':
05413229 7389 {
79862e45 7390 int rn = (given >> 16) & 0xf;
b0c11777 7391 bfd_vma offset = given & 0xff;
0313a2b8 7392
32c36c3c
AV		 7393 if (mod == 'K')
7394 offset = given & 0x7f;
7395
05413229 7396 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 7397
79862e45
DJ		 7398 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
7399 {
7400 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 7401 if (cp_num == 9)
7402 /* vldr.16/vstr.16 will shift the address
7403 left by 1 bit only. */
7404 offset = offset * 2;
7405 else
7406 offset = offset * 4;
7407
79862e45
DJ		 7408 if (NEGATIVE_BIT_SET)
7409 offset = - offset;
7410 if (rn != 15)
7411 value_in_comment = offset;
7412 }
7413
c1e26897 7414 if (PRE_BIT_SET)
05413229
NC		 7415 {
7416 if (offset)
fe56b6ce 7417 func (stream, ", #%d]%s",
d908c8af 7418 (int) offset,
c1e26897 7419 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 7420 else if (NEGATIVE_BIT_SET)
7421 func (stream, ", #-0]");
05413229
NC		 7422 else
7423 func (stream, "]");
7424 }
7425 else
7426 {
0313a2b8 7427 func (stream, "]");
8f06b2d8 7428
c1e26897 7429 if (WRITEBACK_BIT_SET)
05413229
NC		 7430 {
7431 if (offset)
d908c8af 7432 func (stream, ", #%d", (int) offset);
26d97720
NS		 7433 else if (NEGATIVE_BIT_SET)
7434 func (stream, ", #-0");
05413229
NC		 7435 }
7436 else
fe56b6ce 7437 {
26d97720
NS		 7438 func (stream, ", {%s%d}",
7439 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 7440 (int) offset);
fe56b6ce
NC		 7441 value_in_comment = offset;
7442 }
05413229 7443 }
79862e45
DJ		 7444 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
7445 {
7446 func (stream, "\t; ");
6844b2c2
MGD		 7447 /* For unaligned PCs, apply off-by-alignment
7448 correction. */
43e65147 7449 info->print_address_func (offset + pc
6844b2c2
MGD		 7450 + info->bytes_per_chunk * 2
7451 - (pc & 3),
dffaa15c 7452 info);
79862e45 7453 }
05413229 7454 }
0313a2b8 7455 break;
8f06b2d8 7456
0313a2b8
NC		 7457 case 'B':
7458 {
7459 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
7460 int offset = (given >> 1) & 0x3f;
7461
7462 if (offset == 1)
7463 func (stream, "{d%d}", regno);
7464 else if (regno + offset > 32)
7465 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
7466 else
7467 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
7468 }
7469 break;
8f06b2d8 7470
efd6b359
AV		 7471 case 'C':
7472 {
7473 bfd_boolean single = ((given >> 8) & 1) == 0;
7474 char reg_prefix = single ? 's' : 'd';
7475 int Dreg = (given >> 22) & 0x1;
7476 int Vdreg = (given >> 12) & 0xf;
7477 int reg = single ? ((Vdreg << 1) | Dreg)
7478 : ((Dreg << 4) | Vdreg);
7479 int num = (given >> (single ? 0 : 1)) & 0x7f;
7480 int maxreg = single ? 31 : 15;
7481 int topreg = reg + num - 1;
7482
7483 if (!num)
7484 func (stream, "{VPR}");
7485 else if (num == 1)
7486 func (stream, "{%c%d, VPR}", reg_prefix, reg);
7487 else if (topreg > maxreg)
7488 func (stream, "{%c%d-<overflow reg d%d, VPR}",
7489 reg_prefix, reg, single ? topreg >> 1 : topreg);
7490 else
7491 func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
7492 reg_prefix, topreg);
7493 }
7494 break;
7495
e2efe87d
MGD		 7496 case 'u':
7497 if (cond != COND_UNCOND)
7498 is_unpredictable = TRUE;
7499
7500 /* Fall through. */
0313a2b8 7501 case 'c':
b0c11777
RL		 7502 if (cond != COND_UNCOND && cp_num == 9)
7503 is_unpredictable = TRUE;
7504
0313a2b8
NC		 7505 func (stream, "%s", arm_conditional[cond]);
7506 break;
8f06b2d8 7507
0313a2b8
NC		 7508 case 'I':
7509 /* Print a Cirrus/DSP shift immediate. */
7510 /* Immediates are 7bit signed ints with bits 0..3 in
7511 bits 0..3 of opcode and bits 4..6 in bits 5..7
7512 of opcode. */
7513 {
7514 int imm;
8f06b2d8 7515
0313a2b8 7516 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 7517
0313a2b8
NC		 7518 /* Is ``imm'' a negative number? */
7519 if (imm & 0x40)
24b4cf66 7520 imm -= 0x80;
8f06b2d8 7521
0313a2b8
NC		 7522 func (stream, "%d", imm);
7523 }
7524
7525 break;
8f06b2d8 7526
32c36c3c
AV		 7527 case 'J':
7528 {
73cd51e5
AV		 7529 unsigned long regno
7530 = arm_decode_field_multiple (given, 13, 15, 22, 22);
32c36c3c
AV		 7531
7532 switch (regno)
7533 {
7534 case 0x1:
7535 func (stream, "FPSCR");
7536 break;
7537 case 0x2:
7538 func (stream, "FPSCR_nzcvqc");
7539 break;
7540 case 0xc:
7541 func (stream, "VPR");
7542 break;
7543 case 0xd:
7544 func (stream, "P0");
7545 break;
7546 case 0xe:
7547 func (stream, "FPCXTNS");
7548 break;
7549 case 0xf:
7550 func (stream, "FPCXTS");
7551 break;
7552 default:
73cd51e5 7553 func (stream, "<invalid reg %lu>", regno);
32c36c3c
AV		 7554 break;
7555 }
7556 }
7557 break;
7558
0313a2b8
NC		 7559 case 'F':
7560 switch (given & 0x00408000)
7561 {
7562 case 0:
7563 func (stream, "4");
7564 break;
7565 case 0x8000:
7566 func (stream, "1");
7567 break;
7568 case 0x00400000:
7569 func (stream, "2");
8f06b2d8 7570 break;
0313a2b8
NC		 7571 default:
7572 func (stream, "3");
7573 }
7574 break;
8f06b2d8 7575
0313a2b8
NC		 7576 case 'P':
7577 switch (given & 0x00080080)
7578 {
7579 case 0:
7580 func (stream, "s");
7581 break;
7582 case 0x80:
7583 func (stream, "d");
7584 break;
7585 case 0x00080000:
7586 func (stream, "e");
7587 break;
7588 default:
7589 func (stream, _("<illegal precision>"));
8f06b2d8 7590 break;
0313a2b8
NC		 7591 }
7592 break;
8f06b2d8 7593
0313a2b8
NC		 7594 case 'Q':
7595 switch (given & 0x00408000)
7596 {
7597 case 0:
7598 func (stream, "s");
8f06b2d8 7599 break;
0313a2b8
NC		 7600 case 0x8000:
7601 func (stream, "d");
8f06b2d8 7602 break;
0313a2b8
NC		 7603 case 0x00400000:
7604 func (stream, "e");
7605 break;
7606 default:
7607 func (stream, "p");
8f06b2d8 7608 break;
0313a2b8
NC		 7609 }
7610 break;
8f06b2d8 7611
0313a2b8
NC		 7612 case 'R':
7613 switch (given & 0x60)
7614 {
7615 case 0:
7616 break;
7617 case 0x20:
7618 func (stream, "p");
7619 break;
7620 case 0x40:
7621 func (stream, "m");
7622 break;
7623 default:
7624 func (stream, "z");
7625 break;
7626 }
7627 break;
16980d0b 7628
0313a2b8
NC		 7629 case '0': case '1': case '2': case '3': case '4':
7630 case '5': case '6': case '7': case '8': case '9':
7631 {
7632 int width;
8f06b2d8 7633
0313a2b8 7634 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 7635
0313a2b8
NC		 7636 switch (*c)
7637 {
ff4a8d2b
NC		 7638 case 'R':
7639 if (value == 15)
7640 is_unpredictable = TRUE;
7641 /* Fall through. */
0313a2b8 7642 case 'r':
ff4a8d2b
NC		 7643 if (c[1] == 'u')
7644 {
7645 /* Eat the 'u' character. */
7646 ++ c;
7647
7648 if (u_reg == value)
7649 is_unpredictable = TRUE;
7650 u_reg = value;
7651 }
0313a2b8
NC		 7652 func (stream, "%s", arm_regnames[value]);
7653 break;
c28eeff2
SN		 7654 case 'V':
7655 if (given & (1 << 6))
7656 goto Q;
7657 /* FALLTHROUGH */
0313a2b8
NC		 7658 case 'D':
7659 func (stream, "d%ld", value);
7660 break;
7661 case 'Q':
c28eeff2 7662 Q:
0313a2b8
NC		 7663 if (value & 1)
7664 func (stream, "<illegal reg q%ld.5>", value >> 1);
7665 else
7666 func (stream, "q%ld", value >> 1);
7667 break;
7668 case 'd':
7669 func (stream, "%ld", value);
05413229 7670 value_in_comment = value;
0313a2b8 7671 break;
6f1c2142
AM		 7672 case 'E':
7673 {
7674 /* Converts immediate 8 bit back to float value. */
7675 unsigned floatVal = (value & 0x80) << 24
7676 | (value & 0x3F) << 19
7677 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
7678
7679 /* Quarter float have a maximum value of 31.0.
7680 Get floating point value multiplied by 1e7.
7681 The maximum value stays in limit of a 32-bit int. */
7682 unsigned decVal =
7683 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
7684 (16 + (value & 0xF));
7685
7686 if (!(decVal % 1000000))
7687 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
7688 floatVal, value & 0x80 ? '-' : ' ',
7689 decVal / 10000000,
7690 decVal % 10000000 / 1000000);
7691 else if (!(decVal % 10000))
7692 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
7693 floatVal, value & 0x80 ? '-' : ' ',
7694 decVal / 10000000,
7695 decVal % 10000000 / 10000);
7696 else
7697 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
7698 floatVal, value & 0x80 ? '-' : ' ',
7699 decVal / 10000000, decVal % 10000000);
7700 break;
7701 }
0313a2b8
NC		 7702 case 'k':
7703 {
7704 int from = (given & (1 << 7)) ? 32 : 16;
7705 func (stream, "%ld", from - value);
7706 }
7707 break;
8f06b2d8 7708
0313a2b8
NC		 7709 case 'f':
7710 if (value > 7)
7711 func (stream, "#%s", arm_fp_const[value & 7]);
7712 else
7713 func (stream, "f%ld", value);
7714 break;
4146fd53 7715
0313a2b8
NC		 7716 case 'w':
7717 if (width == 2)
7718 func (stream, "%s", iwmmxt_wwnames[value]);
7719 else
7720 func (stream, "%s", iwmmxt_wwssnames[value]);
7721 break;
4146fd53 7722
0313a2b8
NC		 7723 case 'g':
7724 func (stream, "%s", iwmmxt_regnames[value]);
7725 break;
7726 case 'G':
7727 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 7728 break;
8f06b2d8 7729
0313a2b8 7730 case 'x':
d1aaab3c 7731 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 7732 break;
8f06b2d8 7733
33399f07
MGD		 7734 case 'c':
7735 switch (value)
7736 {
7737 case 0:
7738 func (stream, "eq");
7739 break;
7740
7741 case 1:
7742 func (stream, "vs");
7743 break;
7744
7745 case 2:
7746 func (stream, "ge");
7747 break;
7748
7749 case 3:
7750 func (stream, "gt");
7751 break;
7752
7753 default:
7754 func (stream, "??");
7755 break;
7756 }
7757 break;
7758
0313a2b8
NC		 7759 case '`':
7760 c++;
7761 if (value == 0)
7762 func (stream, "%c", *c);
7763 break;
7764 case '\'':
7765 c++;
7766 if (value == ((1ul << width) - 1))
7767 func (stream, "%c", *c);
7768 break;
7769 case '?':
fe56b6ce 7770 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 7771 c += 1 << width;
7772 break;
7773 default:
7774 abort ();
7775 }
dffaa15c
AM		 7776 }
7777 break;
0313a2b8 7778
dffaa15c
AM		 7779 case 'y':
7780 case 'z':
7781 {
7782 int single = *c++ == 'y';
7783 int regno;
8f06b2d8 7784
dffaa15c
AM		 7785 switch (*c)
7786 {
7787 case '4': /* Sm pair */
7788 case '0': /* Sm, Dm */
7789 regno = given & 0x0000000f;
7790 if (single)
7791 {
7792 regno <<= 1;
7793 regno += (given >> 5) & 1;
7794 }
7795 else
7796 regno += ((given >> 5) & 1) << 4;
7797 break;
8f06b2d8 7798
dffaa15c
AM		 7799 case '1': /* Sd, Dd */
7800 regno = (given >> 12) & 0x0000000f;
7801 if (single)
7802 {
7803 regno <<= 1;
7804 regno += (given >> 22) & 1;
7805 }
7806 else
7807 regno += ((given >> 22) & 1) << 4;
7808 break;
7df76b80 7809
dffaa15c
AM		 7810 case '2': /* Sn, Dn */
7811 regno = (given >> 16) & 0x0000000f;
7812 if (single)
7813 {
7814 regno <<= 1;
7815 regno += (given >> 7) & 1;
7816 }
7817 else
7818 regno += ((given >> 7) & 1) << 4;
7819 break;
a7f8487e 7820
dffaa15c
AM		 7821 case '3': /* List */
7822 func (stream, "{");
7823 regno = (given >> 12) & 0x0000000f;
7824 if (single)
7825 {
7826 regno <<= 1;
7827 regno += (given >> 22) & 1;
7828 }
7829 else
7830 regno += ((given >> 22) & 1) << 4;
7831 break;
a7f8487e 7832
dffaa15c
AM		 7833 default:
7834 abort ();
7835 }
0313a2b8 7836
dffaa15c 7837 func (stream, "%c%d", single ? 's' : 'd', regno);
a7f8487e 7838
dffaa15c
AM		 7839 if (*c == '3')
7840 {
7841 int count = given & 0xff;
b34976b6 7842
dffaa15c
AM		 7843 if (single == 0)
7844 count >>= 1;
0313a2b8 7845
dffaa15c
AM		 7846 if (--count)
7847 {
7848 func (stream, "-%c%d",
7849 single ? 's' : 'd',
7850 regno + count);
7851 }
0313a2b8 7852
dffaa15c 7853 func (stream, "}");
0313a2b8 7854 }
dffaa15c
AM		 7855 else if (*c == '4')
7856 func (stream, ", %c%d", single ? 's' : 'd',
7857 regno + 1);
7858 }
7859 break;
b34976b6 7860
dffaa15c
AM		 7861 case 'L':
7862 switch (given & 0x00400100)
0313a2b8 7863 {
dffaa15c
AM		 7864 case 0x00000000: func (stream, "b"); break;
7865 case 0x00400000: func (stream, "h"); break;
7866 case 0x00000100: func (stream, "w"); break;
7867 case 0x00400100: func (stream, "d"); break;
7868 default:
7869 break;
0313a2b8 7870 }
dffaa15c 7871 break;
2d447fca 7872
dffaa15c
AM		 7873 case 'Z':
7874 {
7875 /* given (20, 23) | given (0, 3) */
7876 value = ((given >> 16) & 0xf0) | (given & 0xf);
7877 func (stream, "%d", (int) value);
7878 }
7879 break;
0313a2b8 7880
dffaa15c
AM		 7881 case 'l':
7882 /* This is like the 'A' operator, except that if
7883 the width field "M" is zero, then the offset is
7884 *not* multiplied by four. */
7885 {
7886 int offset = given & 0xff;
7887 int multiplier = (given & 0x00000100) ? 4 : 1;
0313a2b8 7888
dffaa15c 7889 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
05413229 7890
dffaa15c
AM		 7891 if (multiplier > 1)
7892 {
7893 value_in_comment = offset * multiplier;
7894 if (NEGATIVE_BIT_SET)
7895 value_in_comment = - value_in_comment;
7896 }
0313a2b8 7897
dffaa15c
AM		 7898 if (offset)
7899 {
7900 if (PRE_BIT_SET)
7901 func (stream, ", #%s%d]%s",
7902 NEGATIVE_BIT_SET ? "-" : "",
7903 offset * multiplier,
7904 WRITEBACK_BIT_SET ? "!" : "");
7905 else
7906 func (stream, "], #%s%d",
7907 NEGATIVE_BIT_SET ? "-" : "",
7908 offset * multiplier);
7909 }
7910 else
7911 func (stream, "]");
7912 }
7913 break;
2d447fca 7914
dffaa15c
AM		 7915 case 'r':
7916 {
7917 int imm4 = (given >> 4) & 0xf;
7918 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
7919 int ubit = ! NEGATIVE_BIT_SET;
7920 const char *rm = arm_regnames [given & 0xf];
7921 const char *rn = arm_regnames [(given >> 16) & 0xf];
0313a2b8 7922
dffaa15c
AM		 7923 switch (puw_bits)
7924 {
7925 case 1:
7926 case 3:
7927 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
7928 if (imm4)
7929 func (stream, ", lsl #%d", imm4);
7930 break;
0313a2b8 7931
dffaa15c
AM		 7932 case 4:
7933 case 5:
7934 case 6:
7935 case 7:
7936 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
7937 if (imm4 > 0)
7938 func (stream, ", lsl #%d", imm4);
7939 func (stream, "]");
7940 if (puw_bits == 5 || puw_bits == 7)
7941 func (stream, "!");
7942 break;
2d447fca 7943
dffaa15c
AM		 7944 default:
7945 func (stream, "INVALID");
7946 }
7947 }
7948 break;
0313a2b8 7949
dffaa15c
AM		 7950 case 'i':
7951 {
7952 long imm5;
7953 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
7954 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
0313a2b8 7955 }
dffaa15c
AM		 7956 break;
7957
7958 default:
7959 abort ();
252b5132 7960 }
252b5132 7961 }
0313a2b8
NC		 7962 else
7963 func (stream, "%c", *c);
252b5132 7964 }
05413229
NC		 7965
7966 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 7967 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 7968
ff4a8d2b
NC		 7969 if (is_unpredictable)
7970 func (stream, UNPREDICTABLE_INSTRUCTION);
7971
0313a2b8 7972 return TRUE;
252b5132 7973 }
8f06b2d8 7974 return FALSE;
252b5132
RH		 7975}
7976
05413229
NC		 7977/* Decodes and prints ARM addressing modes. Returns the offset
7978 used in the address, if any, if it is worthwhile printing the
7979 offset as a hexadecimal value in a comment at the end of the
7980 line of disassembly. */
7981
7982static signed long
62b3e311
PB		 7983print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
7984{
7985 void *stream = info->stream;
7986 fprintf_ftype func = info->fprintf_func;
f8b960bc 7987 bfd_vma offset = 0;
62b3e311
PB		 7988
7989 if (((given & 0x000f0000) == 0x000f0000)
7990 && ((given & 0x02000000) == 0))
7991 {
05413229 7992 offset = given & 0xfff;
62b3e311
PB		 7993
7994 func (stream, "[pc");
7995
c1e26897 7996 if (PRE_BIT_SET)
62b3e311 7997 {
26d97720
NS		 7998 /* Pre-indexed. Elide offset of positive zero when
7999 non-writeback. */
8000 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 8001 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 8002
8003 if (NEGATIVE_BIT_SET)
8004 offset = -offset;
62b3e311
PB		 8005
8006 offset += pc + 8;
8007
8008 /* Cope with the possibility of write-back
8009 being used. Probably a very dangerous thing
8010 for the programmer to do, but who are we to
8011 argue ? */
26d97720 8012 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 8013 }
c1e26897 8014 else /* Post indexed. */
62b3e311 8015 {
d908c8af 8016 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 8017
c1e26897 8018 /* Ie ignore the offset. */
62b3e311
PB		 8019 offset = pc + 8;
8020 }
8021
8022 func (stream, "\t; ");
8023 info->print_address_func (offset, info);
05413229 8024 offset = 0;
62b3e311
PB		 8025 }
8026 else
8027 {
8028 func (stream, "[%s",
8029 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 8030
8031 if (PRE_BIT_SET)
62b3e311
PB		 8032 {
8033 if ((given & 0x02000000) == 0)
8034 {
26d97720 8035 /* Elide offset of positive zero when non-writeback. */
05413229 8036 offset = given & 0xfff;
26d97720 8037 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 8038 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 8039 }
8040 else
8041 {
26d97720 8042 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 8043 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 8044 }
8045
8046 func (stream, "]%s",
c1e26897 8047 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 8048 }
8049 else
8050 {
8051 if ((given & 0x02000000) == 0)
8052 {
26d97720 8053 /* Always show offset. */
05413229 8054 offset = given & 0xfff;
26d97720 8055 func (stream, "], #%s%d",
d908c8af 8056 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 8057 }
8058 else
8059 {
8060 func (stream, "], %s",
c1e26897 8061 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 8062 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 8063 }
8064 }
84919466
MR		 8065 if (NEGATIVE_BIT_SET)
8066 offset = -offset;
62b3e311 8067 }
05413229
NC		 8068
8069 return (signed long) offset;
62b3e311
PB		 8070}
8071
16980d0b
JB		 8072/* Print one neon instruction on INFO->STREAM.
8073 Return TRUE if the instuction matched, FALSE if this is not a
8074 recognised neon instruction. */
8075
8076static bfd_boolean
8077print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
8078{
8079 const struct opcode32 *insn;
8080 void *stream = info->stream;
8081 fprintf_ftype func = info->fprintf_func;
8082
8083 if (thumb)
8084 {
8085 if ((given & 0xef000000) == 0xef000000)
8086 {
0313a2b8 8087 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 8088 unsigned long bit28 = given & (1 << 28);
8089
8090 given &= 0x00ffffff;
8091 if (bit28)
8092 given |= 0xf3000000;
8093 else
8094 given |= 0xf2000000;
8095 }
8096 else if ((given & 0xff000000) == 0xf9000000)
8097 given ^= 0xf9000000 ^ 0xf4000000;
9743db03
AV		 8098 /* vdup is also a valid neon instruction. */
8099 else if ((given & 0xff910f5f) != 0xee800b10)
16980d0b
JB		 8100 return FALSE;
8101 }
43e65147 8102
16980d0b
JB		 8103 for (insn = neon_opcodes; insn->assembler; insn++)
8104 {
8105 if ((given & insn->mask) == insn->value)
8106 {
05413229 8107 signed long value_in_comment = 0;
e2efe87d 8108 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 8109 const char *c;
8110
8111 for (c = insn->assembler; *c; c++)
8112 {
8113 if (*c == '%')
8114 {
8115 switch (*++c)
8116 {
8117 case '%':
8118 func (stream, "%%");
8119 break;
8120
e2efe87d
MGD		 8121 case 'u':
8122 if (thumb && ifthen_state)
8123 is_unpredictable = TRUE;
8124
8125 /* Fall through. */
c22aaad1
PB		 8126 case 'c':
8127 if (thumb && ifthen_state)
8128 func (stream, "%s", arm_conditional[IFTHEN_COND]);
8129 break;
8130
16980d0b
JB		 8131 case 'A':
8132 {
43e65147 8133 static const unsigned char enc[16] =
16980d0b
JB		 8134 {
8135 0x4, 0x14, /* st4 0,1 */
8136 0x4, /* st1 2 */
8137 0x4, /* st2 3 */
8138 0x3, /* st3 4 */
8139 0x13, /* st3 5 */
8140 0x3, /* st1 6 */
8141 0x1, /* st1 7 */
8142 0x2, /* st2 8 */
8143 0x12, /* st2 9 */
8144 0x2, /* st1 10 */
8145 0, 0, 0, 0, 0
8146 };
8147 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8148 int rn = ((given >> 16) & 0xf);
8149 int rm = ((given >> 0) & 0xf);
8150 int align = ((given >> 4) & 0x3);
8151 int type = ((given >> 8) & 0xf);
8152 int n = enc[type] & 0xf;
8153 int stride = (enc[type] >> 4) + 1;
8154 int ix;
43e65147 8155
16980d0b
JB		 8156 func (stream, "{");
8157 if (stride > 1)
8158 for (ix = 0; ix != n; ix++)
8159 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
8160 else if (n == 1)
8161 func (stream, "d%d", rd);
8162 else
8163 func (stream, "d%d-d%d", rd, rd + n - 1);
8164 func (stream, "}, [%s", arm_regnames[rn]);
8165 if (align)
8e560766 8166 func (stream, " :%d", 32 << align);
16980d0b
JB		 8167 func (stream, "]");
8168 if (rm == 0xd)
8169 func (stream, "!");
8170 else if (rm != 0xf)
8171 func (stream, ", %s", arm_regnames[rm]);
8172 }
8173 break;
43e65147 8174
16980d0b
JB		 8175 case 'B':
8176 {
8177 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8178 int rn = ((given >> 16) & 0xf);
8179 int rm = ((given >> 0) & 0xf);
8180 int idx_align = ((given >> 4) & 0xf);
8181 int align = 0;
8182 int size = ((given >> 10) & 0x3);
8183 int idx = idx_align >> (size + 1);
8184 int length = ((given >> 8) & 3) + 1;
8185 int stride = 1;
8186 int i;
8187
8188 if (length > 1 && size > 0)
8189 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 8190
16980d0b
JB		 8191 switch (length)
8192 {
8193 case 1:
8194 {
8195 int amask = (1 << size) - 1;
8196 if ((idx_align & (1 << size)) != 0)
8197 return FALSE;
8198 if (size > 0)
8199 {
8200 if ((idx_align & amask) == amask)
8201 align = 8 << size;
8202 else if ((idx_align & amask) != 0)
8203 return FALSE;
8204 }
8205 }
8206 break;
43e65147 8207
16980d0b
JB		 8208 case 2:
8209 if (size == 2 && (idx_align & 2) != 0)
8210 return FALSE;
8211 align = (idx_align & 1) ? 16 << size : 0;
8212 break;
43e65147 8213
16980d0b
JB		 8214 case 3:
8215 if ((size == 2 && (idx_align & 3) != 0)
8216 || (idx_align & 1) != 0)
8217 return FALSE;
8218 break;
43e65147 8219
16980d0b
JB		 8220 case 4:
8221 if (size == 2)
8222 {
8223 if ((idx_align & 3) == 3)
8224 return FALSE;
8225 align = (idx_align & 3) * 64;
8226 }
8227 else
8228 align = (idx_align & 1) ? 32 << size : 0;
8229 break;
43e65147 8230
16980d0b
JB		 8231 default:
8232 abort ();
8233 }
43e65147 8234
16980d0b
JB		 8235 func (stream, "{");
8236 for (i = 0; i < length; i++)
8237 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
8238 rd + i * stride, idx);
8239 func (stream, "}, [%s", arm_regnames[rn]);
8240 if (align)
8e560766 8241 func (stream, " :%d", align);
16980d0b
JB		 8242 func (stream, "]");
8243 if (rm == 0xd)
8244 func (stream, "!");
8245 else if (rm != 0xf)
8246 func (stream, ", %s", arm_regnames[rm]);
8247 }
8248 break;
43e65147 8249
16980d0b
JB		 8250 case 'C':
8251 {
8252 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8253 int rn = ((given >> 16) & 0xf);
8254 int rm = ((given >> 0) & 0xf);
8255 int align = ((given >> 4) & 0x1);
8256 int size = ((given >> 6) & 0x3);
8257 int type = ((given >> 8) & 0x3);
8258 int n = type + 1;
8259 int stride = ((given >> 5) & 0x1);
8260 int ix;
43e65147 8261
16980d0b
JB		 8262 if (stride && (n == 1))
8263 n++;
8264 else
8265 stride++;
43e65147 8266
16980d0b
JB		 8267 func (stream, "{");
8268 if (stride > 1)
8269 for (ix = 0; ix != n; ix++)
8270 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
8271 else if (n == 1)
8272 func (stream, "d%d[]", rd);
8273 else
8274 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
8275 func (stream, "}, [%s", arm_regnames[rn]);
8276 if (align)
8277 {
91d6fa6a 8278 align = (8 * (type + 1)) << size;
16980d0b
JB		 8279 if (type == 3)
8280 align = (size > 1) ? align >> 1 : align;
8281 if (type == 2 || (type == 0 && !size))
8e560766 8282 func (stream, " :<bad align %d>", align);
16980d0b 8283 else
8e560766 8284 func (stream, " :%d", align);
16980d0b
JB		 8285 }
8286 func (stream, "]");
8287 if (rm == 0xd)
8288 func (stream, "!");
8289 else if (rm != 0xf)
8290 func (stream, ", %s", arm_regnames[rm]);
8291 }
8292 break;
43e65147 8293
16980d0b
JB		 8294 case 'D':
8295 {
8296 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
8297 int size = (given >> 20) & 3;
8298 int reg = raw_reg & ((4 << size) - 1);
8299 int ix = raw_reg >> size >> 2;
43e65147 8300
16980d0b
JB		 8301 func (stream, "d%d[%d]", reg, ix);
8302 }
8303 break;
43e65147 8304
16980d0b 8305 case 'E':
fe56b6ce 8306 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 8307 {
8308 int bits = 0;
8309 int cmode = (given >> 8) & 0xf;
8310 int op = (given >> 5) & 0x1;
8311 unsigned long value = 0, hival = 0;
8312 unsigned shift;
8313 int size = 0;
0dbde4cf 8314 int isfloat = 0;
43e65147 8315
16980d0b
JB		 8316 bits |= ((given >> 24) & 1) << 7;
8317 bits |= ((given >> 16) & 7) << 4;
8318 bits |= ((given >> 0) & 15) << 0;
43e65147 8319
16980d0b
JB		 8320 if (cmode < 8)
8321 {
8322 shift = (cmode >> 1) & 3;
fe56b6ce 8323 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 8324 size = 32;
8325 }
8326 else if (cmode < 12)
8327 {
8328 shift = (cmode >> 1) & 1;
fe56b6ce 8329 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 8330 size = 16;
8331 }
8332 else if (cmode < 14)
8333 {
8334 shift = (cmode & 1) + 1;
fe56b6ce 8335 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 8336 value |= (1ul << (8 * shift)) - 1;
8337 size = 32;
8338 }
8339 else if (cmode == 14)
8340 {
8341 if (op)
8342 {
fe56b6ce 8343 /* Bit replication into bytes. */
16980d0b
JB		 8344 int ix;
8345 unsigned long mask;
43e65147 8346
16980d0b
JB		 8347 value = 0;
8348 hival = 0;
8349 for (ix = 7; ix >= 0; ix--)
8350 {
8351 mask = ((bits >> ix) & 1) ? 0xff : 0;
8352 if (ix <= 3)
8353 value = (value << 8) | mask;
8354 else
8355 hival = (hival << 8) | mask;
8356 }
8357 size = 64;
8358 }
8359 else
8360 {
fe56b6ce
NC		 8361 /* Byte replication. */
8362 value = (unsigned long) bits;
16980d0b
JB		 8363 size = 8;
8364 }
8365 }
8366 else if (!op)
8367 {
fe56b6ce 8368 /* Floating point encoding. */
16980d0b 8369 int tmp;
43e65147 8370
fe56b6ce
NC		 8371 value = (unsigned long) (bits & 0x7f) << 19;
8372 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 8373 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 8374 value |= (unsigned long) tmp << 24;
16980d0b 8375 size = 32;
0dbde4cf 8376 isfloat = 1;
16980d0b
JB		 8377 }
8378 else
8379 {
8380 func (stream, "<illegal constant %.8x:%x:%x>",
8381 bits, cmode, op);
8382 size = 32;
8383 break;
8384 }
8385 switch (size)
8386 {
8387 case 8:
8388 func (stream, "#%ld\t; 0x%.2lx", value, value);
8389 break;
43e65147 8390
16980d0b
JB		 8391 case 16:
8392 func (stream, "#%ld\t; 0x%.4lx", value, value);
8393 break;
8394
8395 case 32:
0dbde4cf
JB		 8396 if (isfloat)
8397 {
8398 unsigned char valbytes[4];
8399 double fvalue;
43e65147 8400
0dbde4cf
JB		 8401 /* Do this a byte at a time so we don't have to
8402 worry about the host's endianness. */
8403 valbytes[0] = value & 0xff;
8404 valbytes[1] = (value >> 8) & 0xff;
8405 valbytes[2] = (value >> 16) & 0xff;
8406 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 8407
8408 floatformat_to_double
c1e26897
NC		 8409 (& floatformat_ieee_single_little, valbytes,
8410 & fvalue);
43e65147 8411
0dbde4cf
JB		 8412 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
8413 value);
8414 }
8415 else
4e9d3b81 8416 func (stream, "#%ld\t; 0x%.8lx",
43e65147 8417 (long) (((value & 0x80000000L) != 0)
9d82ec38 8418 ? value | ~0xffffffffL : value),
c1e26897 8419 value);
16980d0b
JB		 8420 break;
8421
8422 case 64:
8423 func (stream, "#0x%.8lx%.8lx", hival, value);
8424 break;
43e65147 8425
16980d0b
JB		 8426 default:
8427 abort ();
8428 }
8429 }
8430 break;
43e65147 8431
16980d0b
JB		 8432 case 'F':
8433 {
8434 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
8435 int num = (given >> 8) & 0x3;
43e65147 8436
16980d0b
JB		 8437 if (!num)
8438 func (stream, "{d%d}", regno);
8439 else if (num + regno >= 32)
8440 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
8441 else
8442 func (stream, "{d%d-d%d}", regno, regno + num);
8443 }
8444 break;
7e8e6784 8445
16980d0b
JB		 8446
8447 case '0': case '1': case '2': case '3': case '4':
8448 case '5': case '6': case '7': case '8': case '9':
8449 {
8450 int width;
8451 unsigned long value;
8452
8453 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 8454
16980d0b
JB		 8455 switch (*c)
8456 {
8457 case 'r':
8458 func (stream, "%s", arm_regnames[value]);
8459 break;
8460 case 'd':
8461 func (stream, "%ld", value);
05413229 8462 value_in_comment = value;
16980d0b
JB		 8463 break;
8464 case 'e':
8465 func (stream, "%ld", (1ul << width) - value);
8466 break;
43e65147 8467
16980d0b
JB		 8468 case 'S':
8469 case 'T':
8470 case 'U':
05413229 8471 /* Various width encodings. */
16980d0b
JB		 8472 {
8473 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
8474 int limit;
8475 unsigned low, high;
8476
8477 c++;
8478 if (*c >= '0' && *c <= '9')
8479 limit = *c - '0';
8480 else if (*c >= 'a' && *c <= 'f')
8481 limit = *c - 'a' + 10;
8482 else
8483 abort ();
8484 low = limit >> 2;
8485 high = limit & 3;
8486
8487 if (value < low || value > high)
8488 func (stream, "<illegal width %d>", base << value);
8489 else
8490 func (stream, "%d", base << value);
8491 }
8492 break;
8493 case 'R':
8494 if (given & (1 << 6))
8495 goto Q;
8496 /* FALLTHROUGH */
8497 case 'D':
8498 func (stream, "d%ld", value);
8499 break;
8500 case 'Q':
8501 Q:
8502 if (value & 1)
8503 func (stream, "<illegal reg q%ld.5>", value >> 1);
8504 else
8505 func (stream, "q%ld", value >> 1);
8506 break;
43e65147 8507
16980d0b
JB		 8508 case '`':
8509 c++;
8510 if (value == 0)
8511 func (stream, "%c", *c);
8512 break;
8513 case '\'':
8514 c++;
8515 if (value == ((1ul << width) - 1))
8516 func (stream, "%c", *c);
8517 break;
8518 case '?':
fe56b6ce 8519 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 8520 c += 1 << width;
8521 break;
8522 default:
8523 abort ();
8524 }
16980d0b 8525 }
dffaa15c
AM		 8526 break;
8527
8528 default:
8529 abort ();
16980d0b
JB		 8530 }
8531 }
8532 else
8533 func (stream, "%c", *c);
8534 }
05413229
NC		 8535
8536 if (value_in_comment > 32 || value_in_comment < -16)
8537 func (stream, "\t; 0x%lx", value_in_comment);
8538
e2efe87d
MGD		 8539 if (is_unpredictable)
8540 func (stream, UNPREDICTABLE_INSTRUCTION);
8541
16980d0b
JB		 8542 return TRUE;
8543 }
8544 }
8545 return FALSE;
8546}
8547
73cd51e5
AV		 8548/* Print one mve instruction on INFO->STREAM.
8549 Return TRUE if the instuction matched, FALSE if this is not a
8550 recognised mve instruction. */
8551
8552static bfd_boolean
8553print_insn_mve (struct disassemble_info *info, long given)
8554{
8555 const struct mopcode32 *insn;
8556 void *stream = info->stream;
8557 fprintf_ftype func = info->fprintf_func;
8558
8559 for (insn = mve_opcodes; insn->assembler; insn++)
8560 {
8561 if (((given & insn->mask) == insn->value)
8562 && !is_mve_encoding_conflict (given, insn->mve_op))
8563 {
8564 signed long value_in_comment = 0;
8565 bfd_boolean is_unpredictable = FALSE;
8566 bfd_boolean is_undefined = FALSE;
8567 const char *c;
8568 enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
8569 enum mve_undefined undefined_cond = UNDEF_NONE;
8570
8571 /* Most vector mve instruction are illegal in a it block.
8572 There are a few exceptions; check for them. */
8573 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
8574 {
8575 is_unpredictable = TRUE;
8576 unpredictable_cond = UNPRED_IT_BLOCK;
8577 }
8578 else if (is_mve_unpredictable (given, insn->mve_op,
8579 &unpredictable_cond))
8580 is_unpredictable = TRUE;
8581
8582 if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
8583 is_undefined = TRUE;
8584
8585 for (c = insn->assembler; *c; c++)
8586 {
8587 if (*c == '%')
8588 {
8589 switch (*++c)
8590 {
8591 case '%':
8592 func (stream, "%%");
8593 break;
8594
ef1576a1
AV		 8595 case 'a':
8596 /* Don't print anything for '+' as it is implied. */
8597 if (arm_decode_field (given, 23, 23) == 0)
8598 func (stream, "-");
8599 break;
8600
143275ea
AV		 8601 case 'c':
8602 if (ifthen_state)
8603 func (stream, "%s", arm_conditional[IFTHEN_COND]);
8604 break;
8605
aef6d006
AV		 8606 case 'd':
8607 print_mve_vld_str_addr (info, given, insn->mve_op);
8608 break;
8609
143275ea
AV		 8610 case 'i':
8611 {
8612 long mve_mask = mve_extract_pred_mask (given);
8613 func (stream, "%s", mve_predicatenames[mve_mask]);
8614 }
8615 break;
8616
8617 case 'n':
8618 print_vec_condition (info, given, insn->mve_op);
8619 break;
8620
ef1576a1
AV		 8621 case 'o':
8622 if (arm_decode_field (given, 0, 0) == 1)
8623 {
8624 unsigned long size
8625 = arm_decode_field (given, 4, 4)
8626 | (arm_decode_field (given, 6, 6) << 1);
8627
8628 func (stream, ", uxtw #%lu", size);
8629 }
8630 break;
8631
bf0b396d
AV		 8632 case 'm':
8633 print_mve_rounding_mode (info, given, insn->mve_op);
8634 break;
8635
8636 case 's':
8637 print_mve_vcvt_size (info, given, insn->mve_op);
8638 break;
8639
aef6d006
AV		 8640 case 'u':
8641 {
c507f10b
AV		 8642 unsigned long op1 = arm_decode_field (given, 21, 22);
8643
8644 if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
8645 {
8646 /* Check for signed. */
8647 if (arm_decode_field (given, 23, 23) == 0)
8648 {
8649 /* We don't print 's' for S32. */
8650 if ((arm_decode_field (given, 5, 6) == 0)
8651 && ((op1 == 0) || (op1 == 1)))
8652 ;
8653 else
8654 func (stream, "s");
8655 }
8656 else
8657 func (stream, "u");
8658 }
aef6d006 8659 else
c507f10b
AV		 8660 {
8661 if (arm_decode_field (given, 28, 28) == 0)
8662 func (stream, "s");
8663 else
8664 func (stream, "u");
8665 }
aef6d006 8666 }
ef1576a1 8667 break;
aef6d006 8668
143275ea
AV		 8669 case 'v':
8670 print_instruction_predicate (info);
8671 break;
8672
04d54ace
AV		 8673 case 'w':
8674 if (arm_decode_field (given, 21, 21) == 1)
8675 func (stream, "!");
8676 break;
8677
8678 case 'B':
8679 print_mve_register_blocks (info, given, insn->mve_op);
8680 break;
8681
c507f10b
AV		 8682 case 'E':
8683 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
8684
8685 print_simd_imm8 (info, given, 28, insn);
8686 break;
8687
8688 case 'N':
8689 print_mve_vmov_index (info, given);
8690 break;
8691
14925797
AV		 8692 case 'T':
8693 if (arm_decode_field (given, 12, 12) == 0)
8694 func (stream, "b");
8695 else
8696 func (stream, "t");
8697 break;
8698
d3b63143
AV		 8699 case 'X':
8700 if (arm_decode_field (given, 12, 12) == 1)
8701 func (stream, "x");
8702 break;
8703
143275ea
AV		 8704 case '0': case '1': case '2': case '3': case '4':
8705 case '5': case '6': case '7': case '8': case '9':
8706 {
8707 int width;
8708 unsigned long value;
8709
8710 c = arm_decode_bitfield (c, given, &value, &width);
8711
8712 switch (*c)
8713 {
8714 case 'Z':
8715 if (value == 13)
8716 is_unpredictable = TRUE;
8717 else if (value == 15)
8718 func (stream, "zr");
8719 else
8720 func (stream, "%s", arm_regnames[value]);
8721 break;
8722 case 's':
8723 print_mve_size (info,
8724 value,
8725 insn->mve_op);
8726 break;
66dcaa5d
AV		 8727 case 'I':
8728 if (value == 1)
8729 func (stream, "i");
8730 break;
d3b63143
AV		 8731 case 'A':
8732 if (value == 1)
8733 func (stream, "a");
8734 break;
1c8f2df8
AV		 8735 case 'h':
8736 {
8737 unsigned int odd_reg = (value << 1) | 1;
8738 func (stream, "%s", arm_regnames[odd_reg]);
8739 }
8740 break;
ef1576a1
AV		 8741 case 'i':
8742 {
8743 unsigned long imm
8744 = arm_decode_field (given, 0, 6);
8745 unsigned long mod_imm = imm;
8746
8747 switch (insn->mve_op)
8748 {
8749 case MVE_VLDRW_GATHER_T5:
8750 case MVE_VSTRW_SCATTER_T5:
8751 mod_imm = mod_imm << 2;
8752 break;
8753 case MVE_VSTRD_SCATTER_T6:
8754 case MVE_VLDRD_GATHER_T6:
8755 mod_imm = mod_imm << 3;
8756 break;
8757
8758 default:
8759 break;
8760 }
8761
8762 func (stream, "%lu", mod_imm);
8763 }
8764 break;
bf0b396d
AV		 8765 case 'k':
8766 func (stream, "%lu", 64 - value);
8767 break;
1c8f2df8
AV		 8768 case 'l':
8769 {
8770 unsigned int even_reg = value << 1;
8771 func (stream, "%s", arm_regnames[even_reg]);
8772 }
8773 break;
8774 case 'u':
8775 switch (value)
8776 {
8777 case 0:
8778 func (stream, "1");
8779 break;
8780 case 1:
8781 func (stream, "2");
8782 break;
8783 case 2:
8784 func (stream, "4");
8785 break;
8786 case 3:
8787 func (stream, "8");
8788 break;
8789 default:
8790 break;
8791 }
8792 break;
897b9bbc
AV		 8793 case 'o':
8794 print_mve_rotate (info, value, width);
8795 break;
9743db03
AV		 8796 case 'r':
8797 func (stream, "%s", arm_regnames[value]);
8798 break;
04d54ace 8799 case 'd':
ed63aa17
AV		 8800 if (insn->mve_op == MVE_VQSHL_T2
8801 || insn->mve_op == MVE_VQSHLU_T3
8802 || insn->mve_op == MVE_VRSHR
8803 || insn->mve_op == MVE_VRSHRN
8804 || insn->mve_op == MVE_VSHL_T1
8805 || insn->mve_op == MVE_VSHLL_T1
8806 || insn->mve_op == MVE_VSHR
8807 || insn->mve_op == MVE_VSHRN
8808 || insn->mve_op == MVE_VSLI
8809 || insn->mve_op == MVE_VSRI)
8810 print_mve_shift_n (info, given, insn->mve_op);
8811 else if (insn->mve_op == MVE_VSHLL_T2)
8812 {
8813 switch (value)
8814 {
8815 case 0x00:
8816 func (stream, "8");
8817 break;
8818 case 0x01:
8819 func (stream, "16");
8820 break;
8821 case 0x10:
8822 print_mve_undefined (info, UNDEF_SIZE_0);
8823 break;
8824 default:
8825 assert (0);
8826 break;
8827 }
8828 }
8829 else
8830 {
8831 if (insn->mve_op == MVE_VSHLC && value == 0)
8832 value = 32;
8833 func (stream, "%ld", value);
8834 value_in_comment = value;
8835 }
04d54ace 8836 break;
c507f10b
AV		 8837 case 'F':
8838 func (stream, "s%ld", value);
8839 break;
143275ea
AV		 8840 case 'Q':
8841 if (value & 0x8)
8842 func (stream, "<illegal reg q%ld.5>", value);
8843 else
8844 func (stream, "q%ld", value);
8845 break;
c507f10b
AV		 8846 case 'x':
8847 func (stream, "0x%08lx", value);
8848 break;
143275ea
AV		 8849 default:
8850 abort ();
8851 }
8852 break;
8853 default:
8854 abort ();
8855 }
73cd51e5
AV		 8856 }
8857 }
8858 else
8859 func (stream, "%c", *c);
8860 }
8861
8862 if (value_in_comment > 32 || value_in_comment < -16)
8863 func (stream, "\t; 0x%lx", value_in_comment);
8864
8865 if (is_unpredictable)
8866 print_mve_unpredictable (info, unpredictable_cond);
8867
8868 if (is_undefined)
8869 print_mve_undefined (info, undefined_cond);
8870
143275ea
AV		 8871 if ((vpt_block_state.in_vpt_block == FALSE)
8872 && !ifthen_state
8873 && (is_vpt_instruction (given) == TRUE))
8874 mark_inside_vpt_block (given);
8875 else if (vpt_block_state.in_vpt_block == TRUE)
8876 update_vpt_block_state ();
8877
73cd51e5
AV		 8878 return TRUE;
8879 }
8880 }
8881 return FALSE;
8882}
8883
8884
90ec0d68
MGD		 8885/* Return the name of a v7A special register. */
8886
43e65147 8887static const char *
90ec0d68
MGD		 8888banked_regname (unsigned reg)
8889{
8890 switch (reg)
8891 {
8892 case 15: return "CPSR";
43e65147 8893 case 32: return "R8_usr";
90ec0d68
MGD		 8894 case 33: return "R9_usr";
8895 case 34: return "R10_usr";
8896 case 35: return "R11_usr";
8897 case 36: return "R12_usr";
8898 case 37: return "SP_usr";
8899 case 38: return "LR_usr";
43e65147 8900 case 40: return "R8_fiq";
90ec0d68
MGD		 8901 case 41: return "R9_fiq";
8902 case 42: return "R10_fiq";
8903 case 43: return "R11_fiq";
8904 case 44: return "R12_fiq";
8905 case 45: return "SP_fiq";
8906 case 46: return "LR_fiq";
8907 case 48: return "LR_irq";
8908 case 49: return "SP_irq";
8909 case 50: return "LR_svc";
8910 case 51: return "SP_svc";
8911 case 52: return "LR_abt";
8912 case 53: return "SP_abt";
8913 case 54: return "LR_und";
8914 case 55: return "SP_und";
8915 case 60: return "LR_mon";
8916 case 61: return "SP_mon";
8917 case 62: return "ELR_hyp";
8918 case 63: return "SP_hyp";
8919 case 79: return "SPSR";
8920 case 110: return "SPSR_fiq";
8921 case 112: return "SPSR_irq";
8922 case 114: return "SPSR_svc";
8923 case 116: return "SPSR_abt";
8924 case 118: return "SPSR_und";
8925 case 124: return "SPSR_mon";
8926 case 126: return "SPSR_hyp";
8927 default: return NULL;
8928 }
8929}
8930
e797f7e0
MGD		 8931/* Return the name of the DMB/DSB option. */
8932static const char *
8933data_barrier_option (unsigned option)
8934{
8935 switch (option & 0xf)
8936 {
8937 case 0xf: return "sy";
8938 case 0xe: return "st";
8939 case 0xd: return "ld";
8940 case 0xb: return "ish";
8941 case 0xa: return "ishst";
8942 case 0x9: return "ishld";
8943 case 0x7: return "un";
8944 case 0x6: return "unst";
8945 case 0x5: return "nshld";
8946 case 0x3: return "osh";
8947 case 0x2: return "oshst";
8948 case 0x1: return "oshld";
8949 default: return NULL;
8950 }
8951}
8952
4a5329c6
ZW		 8953/* Print one ARM instruction from PC on INFO->STREAM. */
8954
8955static void
8956print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 8957{
6b5d3a4d 8958 const struct opcode32 *insn;
6a51a8a8 8959 void *stream = info->stream;
6b5d3a4d 8960 fprintf_ftype func = info->fprintf_func;
b0e28b39 8961 struct arm_private_data *private_data = info->private_data;
252b5132 8962
16980d0b
JB		 8963 if (print_insn_coprocessor (pc, info, given, FALSE))
8964 return;
8965
8966 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 8967 return;
8968
252b5132
RH		 8969 for (insn = arm_opcodes; insn->assembler; insn++)
8970 {
0313a2b8
NC		 8971 if ((given & insn->mask) != insn->value)
8972 continue;
823d2571
TG		 8973
8974 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 8975 continue;
8976
8977 /* Special case: an instruction with all bits set in the condition field
8978 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
8979 or by the catchall at the end of the table. */
8980 if ((given & 0xF0000000) != 0xF0000000
8981 || (insn->mask & 0xF0000000) == 0xF0000000
8982 || (insn->mask == 0 && insn->value == 0))
252b5132 8983 {
ff4a8d2b
NC		 8984 unsigned long u_reg = 16;
8985 unsigned long U_reg = 16;
ab8e2090 8986 bfd_boolean is_unpredictable = FALSE;
05413229 8987 signed long value_in_comment = 0;
6b5d3a4d 8988 const char *c;
b34976b6 8989
252b5132
RH		 8990 for (c = insn->assembler; *c; c++)
8991 {
8992 if (*c == '%')
8993 {
c1e26897
NC		 8994 bfd_boolean allow_unpredictable = FALSE;
8995
252b5132
RH		 8996 switch (*++c)
8997 {
8998 case '%':
8999 func (stream, "%%");
9000 break;
9001
9002 case 'a':
05413229 9003 value_in_comment = print_arm_address (pc, info, given);
62b3e311 9004 break;
252b5132 9005
62b3e311
PB		 9006 case 'P':
9007 /* Set P address bit and use normal address
9008 printing routine. */
c1e26897 9009 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 9010 break;
9011
c1e26897
NC		 9012 case 'S':
9013 allow_unpredictable = TRUE;
1a0670f3 9014 /* Fall through. */
252b5132
RH		 9015 case 's':
9016 if ((given & 0x004f0000) == 0x004f0000)
9017 {
58efb6c0 9018 /* PC relative with immediate offset. */
f8b960bc 9019 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 9020
aefd8a40
NC		 9021 if (PRE_BIT_SET)
9022 {
26d97720
NS		 9023 /* Elide positive zero offset. */
9024 if (offset || NEGATIVE_BIT_SET)
9025 func (stream, "[pc, #%s%d]\t; ",
d908c8af 9026 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 9027 else
26d97720
NS		 9028 func (stream, "[pc]\t; ");
9029 if (NEGATIVE_BIT_SET)
9030 offset = -offset;
aefd8a40
NC		 9031 info->print_address_func (offset + pc + 8, info);
9032 }
9033 else
9034 {
26d97720
NS		 9035 /* Always show the offset. */
9036 func (stream, "[pc], #%s%d",
d908c8af 9037 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 9038 if (! allow_unpredictable)
9039 is_unpredictable = TRUE;
aefd8a40 9040 }
252b5132
RH		 9041 }
9042 else
9043 {
fe56b6ce
NC		 9044 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
9045
b34976b6 9046 func (stream, "[%s",
252b5132 9047 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 9048
c1e26897 9049 if (PRE_BIT_SET)
252b5132 9050 {
c1e26897 9051 if (IMMEDIATE_BIT_SET)
252b5132 9052 {
26d97720
NS		 9053 /* Elide offset for non-writeback
9054 positive zero. */
9055 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
9056 || offset)
9057 func (stream, ", #%s%d",
9058 NEGATIVE_BIT_SET ? "-" : "", offset);
9059
9060 if (NEGATIVE_BIT_SET)
9061 offset = -offset;
945ee430 9062
fe56b6ce 9063 value_in_comment = offset;
252b5132 9064 }
945ee430 9065 else
ff4a8d2b
NC		 9066 {
9067 /* Register Offset or Register Pre-Indexed. */
9068 func (stream, ", %s%s",
9069 NEGATIVE_BIT_SET ? "-" : "",
9070 arm_regnames[given & 0xf]);
9071
9072 /* Writing back to the register that is the source/
9073 destination of the load/store is unpredictable. */
9074 if (! allow_unpredictable
9075 && WRITEBACK_BIT_SET
9076 && ((given & 0xf) == ((given >> 12) & 0xf)))
9077 is_unpredictable = TRUE;
9078 }
252b5132 9079
b34976b6 9080 func (stream, "]%s",
c1e26897 9081 WRITEBACK_BIT_SET ? "!" : "");
252b5132 9082 }
945ee430 9083 else
252b5132 9084 {
c1e26897 9085 if (IMMEDIATE_BIT_SET)
252b5132 9086 {
945ee430 9087 /* Immediate Post-indexed. */
aefd8a40 9088 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 9089 func (stream, "], #%s%d",
9090 NEGATIVE_BIT_SET ? "-" : "", offset);
9091 if (NEGATIVE_BIT_SET)
9092 offset = -offset;
fe56b6ce 9093 value_in_comment = offset;
252b5132 9094 }
945ee430 9095 else
ff4a8d2b
NC		 9096 {
9097 /* Register Post-indexed. */
9098 func (stream, "], %s%s",
9099 NEGATIVE_BIT_SET ? "-" : "",
9100 arm_regnames[given & 0xf]);
9101
9102 /* Writing back to the register that is the source/
9103 destination of the load/store is unpredictable. */
9104 if (! allow_unpredictable
9105 && (given & 0xf) == ((given >> 12) & 0xf))
9106 is_unpredictable = TRUE;
9107 }
c1e26897 9108
07a28fab
NC		 9109 if (! allow_unpredictable)
9110 {
9111 /* Writeback is automatically implied by post- addressing.
9112 Setting the W bit is unnecessary and ARM specify it as
9113 being unpredictable. */
9114 if (WRITEBACK_BIT_SET
9115 /* Specifying the PC register as the post-indexed
9116 registers is also unpredictable. */
ab8e2090
NC		 9117 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
9118 is_unpredictable = TRUE;
07a28fab 9119 }
252b5132
RH		 9120 }
9121 }
9122 break;
b34976b6 9123
252b5132 9124 case 'b':
6b5d3a4d 9125 {
f8b960bc 9126 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
05413229 9127 info->print_address_func (disp * 4 + pc + 8, info);
6b5d3a4d 9128 }
252b5132
RH		 9129 break;
9130
9131 case 'c':
c22aaad1
PB		 9132 if (((given >> 28) & 0xf) != 0xe)
9133 func (stream, "%s",
9134 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 9135 break;
9136
9137 case 'm':
9138 {
9139 int started = 0;
9140 int reg;
9141
9142 func (stream, "{");
9143 for (reg = 0; reg < 16; reg++)
9144 if ((given & (1 << reg)) != 0)
9145 {
9146 if (started)
9147 func (stream, ", ");
9148 started = 1;
9149 func (stream, "%s", arm_regnames[reg]);
9150 }
9151 func (stream, "}");
ab8e2090
NC		 9152 if (! started)
9153 is_unpredictable = TRUE;
252b5132
RH		 9154 }
9155 break;
9156
37b37b2d 9157 case 'q':
78c66db8 9158 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 9159 break;
9160
252b5132
RH		 9161 case 'o':
9162 if ((given & 0x02000000) != 0)
9163 {
a415b1cd
JB		 9164 unsigned int rotate = (given & 0xf00) >> 7;
9165 unsigned int immed = (given & 0xff);
9166 unsigned int a, i;
9167
9168 a = (((immed << (32 - rotate))
9169 | (immed >> rotate)) & 0xffffffff);
9170 /* If there is another encoding with smaller rotate,
9171 the rotate should be specified directly. */
9172 for (i = 0; i < 32; i += 2)
9173 if ((a << i | a >> (32 - i)) <= 0xff)
9174 break;
9175
9176 if (i != rotate)
9177 func (stream, "#%d, %d", immed, rotate);
9178 else
9179 func (stream, "#%d", a);
9180 value_in_comment = a;
252b5132
RH		 9181 }
9182 else
78c66db8 9183 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 9184 break;
9185
9186 case 'p':
9187 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 9188 {
823d2571
TG		 9189 arm_feature_set arm_ext_v6 =
9190 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
9191
aefd8a40
NC		 9192 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
9193 mechanism for setting PSR flag bits. They are
9194 obsolete in V6 onwards. */
823d2571
TG		 9195 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
9196 arm_ext_v6))
aefd8a40 9197 func (stream, "p");
4ab90a7a
AV		 9198 else
9199 is_unpredictable = TRUE;
aefd8a40 9200 }
252b5132
RH		 9201 break;
9202
9203 case 't':
9204 if ((given & 0x01200000) == 0x00200000)
9205 func (stream, "t");
9206 break;
9207
252b5132 9208 case 'A':
05413229
NC		 9209 {
9210 int offset = given & 0xff;
f02232aa 9211
05413229 9212 value_in_comment = offset * 4;
c1e26897 9213 if (NEGATIVE_BIT_SET)
05413229 9214 value_in_comment = - value_in_comment;
f02232aa 9215
05413229 9216 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 9217
c1e26897 9218 if (PRE_BIT_SET)
05413229
NC		 9219 {
9220 if (offset)
fe56b6ce 9221 func (stream, ", #%d]%s",
d908c8af 9222 (int) value_in_comment,
c1e26897 9223 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 9224 else
9225 func (stream, "]");
9226 }
9227 else
9228 {
9229 func (stream, "]");
f02232aa 9230
c1e26897 9231 if (WRITEBACK_BIT_SET)
05413229
NC		 9232 {
9233 if (offset)
d908c8af 9234 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 9235 }
9236 else
fe56b6ce 9237 {
d908c8af 9238 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 9239 value_in_comment = offset;
9240 }
05413229
NC		 9241 }
9242 }
252b5132
RH		 9243 break;
9244
077b8428
NC		 9245 case 'B':
9246 /* Print ARM V5 BLX(1) address: pc+25 bits. */
9247 {
9248 bfd_vma address;
9249 bfd_vma offset = 0;
b34976b6 9250
c1e26897 9251 if (! NEGATIVE_BIT_SET)
077b8428
NC		 9252 /* Is signed, hi bits should be ones. */
9253 offset = (-1) ^ 0x00ffffff;
9254
9255 /* Offset is (SignExtend(offset field)<<2). */
9256 offset += given & 0x00ffffff;
9257 offset <<= 2;
9258 address = offset + pc + 8;
b34976b6 9259
8f06b2d8
PB		 9260 if (given & 0x01000000)
9261 /* H bit allows addressing to 2-byte boundaries. */
9262 address += 2;
b1ee46c5 9263
8f06b2d8 9264 info->print_address_func (address, info);
b1ee46c5 9265 }
b1ee46c5
AH		 9266 break;
9267
252b5132 9268 case 'C':
90ec0d68
MGD		 9269 if ((given & 0x02000200) == 0x200)
9270 {
9271 const char * name;
9272 unsigned sysm = (given & 0x004f0000) >> 16;
9273
9274 sysm |= (given & 0x300) >> 4;
9275 name = banked_regname (sysm);
9276
9277 if (name != NULL)
9278 func (stream, "%s", name);
9279 else
d908c8af 9280 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 9281 }
9282 else
9283 {
43e65147 9284 func (stream, "%cPSR_",
90ec0d68
MGD		 9285 (given & 0x00400000) ? 'S' : 'C');
9286 if (given & 0x80000)
9287 func (stream, "f");
9288 if (given & 0x40000)
9289 func (stream, "s");
9290 if (given & 0x20000)
9291 func (stream, "x");
9292 if (given & 0x10000)
9293 func (stream, "c");
9294 }
252b5132
RH		 9295 break;
9296
62b3e311 9297 case 'U':
43e65147 9298 if ((given & 0xf0) == 0x60)
62b3e311 9299 {
52e7f43d
RE		 9300 switch (given & 0xf)
9301 {
9302 case 0xf: func (stream, "sy"); break;
9303 default:
9304 func (stream, "#%d", (int) given & 0xf);
9305 break;
9306 }
43e65147
L		 9307 }
9308 else
52e7f43d 9309 {
e797f7e0
MGD		 9310 const char * opt = data_barrier_option (given & 0xf);
9311 if (opt != NULL)
9312 func (stream, "%s", opt);
9313 else
52e7f43d 9314 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 9315 }
9316 break;
9317
b34976b6 9318 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 9319 case '5': case '6': case '7': case '8': case '9':
9320 {
16980d0b
JB		 9321 int width;
9322 unsigned long value;
252b5132 9323
16980d0b 9324 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 9325
252b5132
RH		 9326 switch (*c)
9327 {
ab8e2090
NC		 9328 case 'R':
9329 if (value == 15)
9330 is_unpredictable = TRUE;
9331 /* Fall through. */
16980d0b 9332 case 'r':
9eb6c0f1
MGD		 9333 case 'T':
9334 /* We want register + 1 when decoding T. */
9335 if (*c == 'T')
9336 ++value;
9337
ff4a8d2b
NC		 9338 if (c[1] == 'u')
9339 {
9340 /* Eat the 'u' character. */
9341 ++ c;
9342
9343 if (u_reg == value)
9344 is_unpredictable = TRUE;
9345 u_reg = value;
9346 }
9347 if (c[1] == 'U')
9348 {
9349 /* Eat the 'U' character. */
9350 ++ c;
9351
9352 if (U_reg == value)
9353 is_unpredictable = TRUE;
9354 U_reg = value;
9355 }
16980d0b
JB		 9356 func (stream, "%s", arm_regnames[value]);
9357 break;
9358 case 'd':
9359 func (stream, "%ld", value);
05413229 9360 value_in_comment = value;
16980d0b
JB		 9361 break;
9362 case 'b':
9363 func (stream, "%ld", value * 8);
05413229 9364 value_in_comment = value * 8;
16980d0b
JB		 9365 break;
9366 case 'W':
9367 func (stream, "%ld", value + 1);
05413229 9368 value_in_comment = value + 1;
16980d0b
JB		 9369 break;
9370 case 'x':
9371 func (stream, "0x%08lx", value);
9372
9373 /* Some SWI instructions have special
9374 meanings. */
9375 if ((given & 0x0fffffff) == 0x0FF00000)
9376 func (stream, "\t; IMB");
9377 else if ((given & 0x0fffffff) == 0x0FF00001)
9378 func (stream, "\t; IMBRange");
9379 break;
9380 case 'X':
9381 func (stream, "%01lx", value & 0xf);
05413229 9382 value_in_comment = value;
252b5132
RH		 9383 break;
9384 case '`':
9385 c++;
16980d0b 9386 if (value == 0)
252b5132
RH		 9387 func (stream, "%c", *c);
9388 break;
9389 case '\'':
9390 c++;
16980d0b 9391 if (value == ((1ul << width) - 1))
252b5132
RH		 9392 func (stream, "%c", *c);
9393 break;
9394 case '?':
fe56b6ce 9395 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 9396 c += 1 << width;
252b5132
RH		 9397 break;
9398 default:
9399 abort ();
9400 }
dffaa15c
AM		 9401 }
9402 break;
0dd132b6 9403
dffaa15c
AM		 9404 case 'e':
9405 {
9406 int imm;
0dd132b6 9407
dffaa15c
AM		 9408 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
9409 func (stream, "%d", imm);
9410 value_in_comment = imm;
9411 }
9412 break;
fe56b6ce 9413
dffaa15c
AM		 9414 case 'E':
9415 /* LSB and WIDTH fields of BFI or BFC. The machine-
9416 language instruction encodes LSB and MSB. */
9417 {
9418 long msb = (given & 0x001f0000) >> 16;
9419 long lsb = (given & 0x00000f80) >> 7;
9420 long w = msb - lsb + 1;
0a003adc 9421
dffaa15c
AM		 9422 if (w > 0)
9423 func (stream, "#%lu, #%lu", lsb, w);
9424 else
9425 func (stream, "(invalid: %lu:%lu)", lsb, msb);
9426 }
9427 break;
90ec0d68 9428
dffaa15c
AM		 9429 case 'R':
9430 /* Get the PSR/banked register name. */
9431 {
9432 const char * name;
9433 unsigned sysm = (given & 0x004f0000) >> 16;
90ec0d68 9434
dffaa15c
AM		 9435 sysm |= (given & 0x300) >> 4;
9436 name = banked_regname (sysm);
90ec0d68 9437
dffaa15c
AM		 9438 if (name != NULL)
9439 func (stream, "%s", name);
9440 else
9441 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
9442 }
9443 break;
fe56b6ce 9444
dffaa15c
AM		 9445 case 'V':
9446 /* 16-bit unsigned immediate from a MOVT or MOVW
9447 instruction, encoded in bits 0:11 and 15:19. */
9448 {
9449 long hi = (given & 0x000f0000) >> 4;
9450 long lo = (given & 0x00000fff);
9451 long imm16 = hi | lo;
0a003adc 9452
dffaa15c
AM		 9453 func (stream, "#%lu", imm16);
9454 value_in_comment = imm16;
252b5132 9455 }
dffaa15c
AM		 9456 break;
9457
9458 default:
9459 abort ();
252b5132
RH		 9460 }
9461 }
9462 else
9463 func (stream, "%c", *c);
9464 }
05413229
NC		 9465
9466 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 9467 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 9468
9469 if (is_unpredictable)
9470 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 9471
4a5329c6 9472 return;
252b5132
RH		 9473 }
9474 }
0b347048
TC		 9475 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
9476 return;
252b5132
RH		 9477}
9478
4a5329c6 9479/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 9480
4a5329c6
ZW		 9481static void
9482print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 9483{
6b5d3a4d 9484 const struct opcode16 *insn;
6a51a8a8
AM		 9485 void *stream = info->stream;
9486 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 9487
9488 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 9489 if ((given & insn->mask) == insn->value)
9490 {
05413229 9491 signed long value_in_comment = 0;
6b5d3a4d 9492 const char *c = insn->assembler;
05413229 9493
c19d1205
ZW		 9494 for (; *c; c++)
9495 {
9496 int domaskpc = 0;
9497 int domasklr = 0;
9498
9499 if (*c != '%')
9500 {
9501 func (stream, "%c", *c);
9502 continue;
9503 }
252b5132 9504
c19d1205
ZW		 9505 switch (*++c)
9506 {
9507 case '%':
9508 func (stream, "%%");
9509 break;
b34976b6 9510
c22aaad1
PB		 9511 case 'c':
9512 if (ifthen_state)
9513 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9514 break;
9515
9516 case 'C':
9517 if (ifthen_state)
9518 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9519 else
9520 func (stream, "s");
9521 break;
9522
9523 case 'I':
9524 {
9525 unsigned int tmp;
9526
9527 ifthen_next_state = given & 0xff;
9528 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
9529 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
9530 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
9531 }
9532 break;
9533
9534 case 'x':
9535 if (ifthen_next_state)
9536 func (stream, "\t; unpredictable branch in IT block\n");
9537 break;
9538
9539 case 'X':
9540 if (ifthen_state)
9541 func (stream, "\t; unpredictable <IT:%s>",
9542 arm_conditional[IFTHEN_COND]);
9543 break;
9544
c19d1205
ZW		 9545 case 'S':
9546 {
9547 long reg;
9548
9549 reg = (given >> 3) & 0x7;
9550 if (given & (1 << 6))
9551 reg += 8;
4f3c3dbb 9552
c19d1205
ZW		 9553 func (stream, "%s", arm_regnames[reg]);
9554 }
9555 break;
baf0cc5e 9556
c19d1205 9557 case 'D':
4f3c3dbb 9558 {
c19d1205
ZW		 9559 long reg;
9560
9561 reg = given & 0x7;
9562 if (given & (1 << 7))
9563 reg += 8;
9564
9565 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 9566 }
c19d1205
ZW		 9567 break;
9568
9569 case 'N':
9570 if (given & (1 << 8))
9571 domasklr = 1;
9572 /* Fall through. */
9573 case 'O':
9574 if (*c == 'O' && (given & (1 << 8)))
9575 domaskpc = 1;
9576 /* Fall through. */
9577 case 'M':
9578 {
9579 int started = 0;
9580 int reg;
9581
9582 func (stream, "{");
9583
9584 /* It would be nice if we could spot
9585 ranges, and generate the rS-rE format: */
9586 for (reg = 0; (reg < 8); reg++)
9587 if ((given & (1 << reg)) != 0)
9588 {
9589 if (started)
9590 func (stream, ", ");
9591 started = 1;
9592 func (stream, "%s", arm_regnames[reg]);
9593 }
9594
9595 if (domasklr)
9596 {
9597 if (started)
9598 func (stream, ", ");
9599 started = 1;
d908c8af 9600 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 9601 }
9602
9603 if (domaskpc)
9604 {
9605 if (started)
9606 func (stream, ", ");
d908c8af 9607 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 9608 }
9609
9610 func (stream, "}");
9611 }
9612 break;
9613
4547cb56
NC		 9614 case 'W':
9615 /* Print writeback indicator for a LDMIA. We are doing a
9616 writeback if the base register is not in the register
9617 mask. */
9618 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
9619 func (stream, "!");
dffaa15c 9620 break;
4547cb56 9621
c19d1205
ZW		 9622 case 'b':
9623 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
9624 {
9625 bfd_vma address = (pc + 4
9626 + ((given & 0x00f8) >> 2)
9627 + ((given & 0x0200) >> 3));
9628 info->print_address_func (address, info);
9629 }
9630 break;
9631
9632 case 's':
9633 /* Right shift immediate -- bits 6..10; 1-31 print
9634 as themselves, 0 prints as 32. */
9635 {
9636 long imm = (given & 0x07c0) >> 6;
9637 if (imm == 0)
9638 imm = 32;
0fd3a477 9639 func (stream, "#%ld", imm);
c19d1205
ZW		 9640 }
9641 break;
9642
9643 case '0': case '1': case '2': case '3': case '4':
9644 case '5': case '6': case '7': case '8': case '9':
9645 {
9646 int bitstart = *c++ - '0';
9647 int bitend = 0;
9648
9649 while (*c >= '0' && *c <= '9')
9650 bitstart = (bitstart * 10) + *c++ - '0';
9651
9652 switch (*c)
9653 {
9654 case '-':
9655 {
f8b960bc 9656 bfd_vma reg;
c19d1205
ZW		 9657
9658 c++;
9659 while (*c >= '0' && *c <= '9')
9660 bitend = (bitend * 10) + *c++ - '0';
9661 if (!bitend)
9662 abort ();
9663 reg = given >> bitstart;
9664 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 9665
c19d1205
ZW		 9666 switch (*c)
9667 {
9668 case 'r':
9669 func (stream, "%s", arm_regnames[reg]);
9670 break;
9671
9672 case 'd':
d908c8af 9673 func (stream, "%ld", (long) reg);
05413229 9674 value_in_comment = reg;
c19d1205
ZW		 9675 break;
9676
9677 case 'H':
d908c8af 9678 func (stream, "%ld", (long) (reg << 1));
05413229 9679 value_in_comment = reg << 1;
c19d1205
ZW		 9680 break;
9681
9682 case 'W':
d908c8af 9683 func (stream, "%ld", (long) (reg << 2));
05413229 9684 value_in_comment = reg << 2;
c19d1205
ZW		 9685 break;
9686
9687 case 'a':
9688 /* PC-relative address -- the bottom two
9689 bits of the address are dropped
9690 before the calculation. */
9691 info->print_address_func
9692 (((pc + 4) & ~3) + (reg << 2), info);
05413229 9693 value_in_comment = 0;
c19d1205
ZW		 9694 break;
9695
9696 case 'x':
d908c8af 9697 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 9698 break;
9699
c19d1205
ZW		 9700 case 'B':
9701 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6b5d3a4d 9702 info->print_address_func (reg * 2 + pc + 4, info);
05413229 9703 value_in_comment = 0;
c19d1205
ZW		 9704 break;
9705
9706 case 'c':
c22aaad1 9707 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 9708 break;
9709
9710 default:
9711 abort ();
9712 }
9713 }
9714 break;
9715
9716 case '\'':
9717 c++;
9718 if ((given & (1 << bitstart)) != 0)
9719 func (stream, "%c", *c);
9720 break;
9721
9722 case '?':
9723 ++c;
9724 if ((given & (1 << bitstart)) != 0)
9725 func (stream, "%c", *c++);
9726 else
9727 func (stream, "%c", *++c);
9728 break;
9729
9730 default:
9731 abort ();
9732 }
9733 }
9734 break;
9735
9736 default:
9737 abort ();
9738 }
9739 }
05413229
NC		 9740
9741 if (value_in_comment > 32 || value_in_comment < -16)
9742 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 9743 return;
c19d1205
ZW		 9744 }
9745
9746 /* No match. */
0b347048
TC		 9747 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
9748 return;
c19d1205
ZW		 9749}
9750
62b3e311 9751/* Return the name of an V7M special register. */
fe56b6ce 9752
62b3e311
PB		 9753static const char *
9754psr_name (int regno)
9755{
9756 switch (regno)
9757 {
1a336194
TP		 9758 case 0x0: return "APSR";
9759 case 0x1: return "IAPSR";
9760 case 0x2: return "EAPSR";
9761 case 0x3: return "PSR";
9762 case 0x5: return "IPSR";
9763 case 0x6: return "EPSR";
9764 case 0x7: return "IEPSR";
9765 case 0x8: return "MSP";
9766 case 0x9: return "PSP";
9767 case 0xa: return "MSPLIM";
9768 case 0xb: return "PSPLIM";
9769 case 0x10: return "PRIMASK";
9770 case 0x11: return "BASEPRI";
9771 case 0x12: return "BASEPRI_MAX";
9772 case 0x13: return "FAULTMASK";
9773 case 0x14: return "CONTROL";
16a1fa25
TP		 9774 case 0x88: return "MSP_NS";
9775 case 0x89: return "PSP_NS";
1a336194
TP		 9776 case 0x8a: return "MSPLIM_NS";
9777 case 0x8b: return "PSPLIM_NS";
9778 case 0x90: return "PRIMASK_NS";
9779 case 0x91: return "BASEPRI_NS";
9780 case 0x93: return "FAULTMASK_NS";
9781 case 0x94: return "CONTROL_NS";
9782 case 0x98: return "SP_NS";
62b3e311
PB		 9783 default: return "<unknown>";
9784 }
9785}
9786
4a5329c6
ZW		 9787/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
9788
9789static void
9790print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 9791{
6b5d3a4d 9792 const struct opcode32 *insn;
c19d1205
ZW		 9793 void *stream = info->stream;
9794 fprintf_ftype func = info->fprintf_func;
73cd51e5 9795 bfd_boolean is_mve = is_mve_architecture (info);
c19d1205 9796
16980d0b
JB		 9797 if (print_insn_coprocessor (pc, info, given, TRUE))
9798 return;
9799
73cd51e5
AV		 9800 if ((is_mve == FALSE) && print_insn_neon (info, given, TRUE))
9801 return;
9802
9803 if (is_mve && print_insn_mve (info, given))
8f06b2d8
PB		 9804 return;
9805
c19d1205
ZW		 9806 for (insn = thumb32_opcodes; insn->assembler; insn++)
9807 if ((given & insn->mask) == insn->value)
9808 {
4b5a202f 9809 bfd_boolean is_clrm = FALSE;
ff4a8d2b 9810 bfd_boolean is_unpredictable = FALSE;
05413229 9811 signed long value_in_comment = 0;
6b5d3a4d 9812 const char *c = insn->assembler;
05413229 9813
c19d1205
ZW		 9814 for (; *c; c++)
9815 {
9816 if (*c != '%')
9817 {
9818 func (stream, "%c", *c);
9819 continue;
9820 }
9821
9822 switch (*++c)
9823 {
9824 case '%':
9825 func (stream, "%%");
9826 break;
9827
c22aaad1
PB		 9828 case 'c':
9829 if (ifthen_state)
9830 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9831 break;
9832
9833 case 'x':
9834 if (ifthen_next_state)
9835 func (stream, "\t; unpredictable branch in IT block\n");
9836 break;
9837
9838 case 'X':
9839 if (ifthen_state)
9840 func (stream, "\t; unpredictable <IT:%s>",
9841 arm_conditional[IFTHEN_COND]);
9842 break;
9843
c19d1205
ZW		 9844 case 'I':
9845 {
9846 unsigned int imm12 = 0;
fe56b6ce 9847
c19d1205
ZW		 9848 imm12 |= (given & 0x000000ffu);
9849 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 9850 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 9851 func (stream, "#%u", imm12);
9852 value_in_comment = imm12;
c19d1205
ZW		 9853 }
9854 break;
9855
9856 case 'M':
9857 {
9858 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 9859
c19d1205
ZW		 9860 bits |= (given & 0x000000ffu);
9861 bits |= (given & 0x00007000u) >> 4;
9862 bits |= (given & 0x04000000u) >> 15;
9863 imm8 = (bits & 0x0ff);
9864 mod = (bits & 0xf00) >> 8;
9865 switch (mod)
9866 {
9867 case 0: imm = imm8; break;
c1e26897
NC		 9868 case 1: imm = ((imm8 << 16) | imm8); break;
9869 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
9870 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 9871 default:
9872 mod = (bits & 0xf80) >> 7;
9873 imm8 = (bits & 0x07f) | 0x80;
9874 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
9875 }
fe56b6ce
NC		 9876 func (stream, "#%u", imm);
9877 value_in_comment = imm;
c19d1205
ZW		 9878 }
9879 break;
43e65147 9880
c19d1205
ZW		 9881 case 'J':
9882 {
9883 unsigned int imm = 0;
fe56b6ce 9884
c19d1205
ZW		 9885 imm |= (given & 0x000000ffu);
9886 imm |= (given & 0x00007000u) >> 4;
9887 imm |= (given & 0x04000000u) >> 15;
9888 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 9889 func (stream, "#%u", imm);
9890 value_in_comment = imm;
c19d1205
ZW		 9891 }
9892 break;
9893
9894 case 'K':
9895 {
9896 unsigned int imm = 0;
fe56b6ce 9897
c19d1205
ZW		 9898 imm |= (given & 0x000f0000u) >> 16;
9899 imm |= (given & 0x00000ff0u) >> 0;
9900 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 9901 func (stream, "#%u", imm);
9902 value_in_comment = imm;
c19d1205
ZW		 9903 }
9904 break;
9905
74db7efb
NC		 9906 case 'H':
9907 {
9908 unsigned int imm = 0;
9909
9910 imm |= (given & 0x000f0000u) >> 4;
9911 imm |= (given & 0x00000fffu) >> 0;
9912 func (stream, "#%u", imm);
9913 value_in_comment = imm;
9914 }
9915 break;
9916
90ec0d68
MGD		 9917 case 'V':
9918 {
9919 unsigned int imm = 0;
9920
9921 imm |= (given & 0x00000fffu);
9922 imm |= (given & 0x000f0000u) >> 4;
9923 func (stream, "#%u", imm);
9924 value_in_comment = imm;
9925 }
9926 break;
9927
c19d1205
ZW		 9928 case 'S':
9929 {
9930 unsigned int reg = (given & 0x0000000fu);
9931 unsigned int stp = (given & 0x00000030u) >> 4;
9932 unsigned int imm = 0;
9933 imm |= (given & 0x000000c0u) >> 6;
9934 imm |= (given & 0x00007000u) >> 10;
9935
9936 func (stream, "%s", arm_regnames[reg]);
9937 switch (stp)
9938 {
9939 case 0:
9940 if (imm > 0)
9941 func (stream, ", lsl #%u", imm);
9942 break;
9943
9944 case 1:
9945 if (imm == 0)
9946 imm = 32;
9947 func (stream, ", lsr #%u", imm);
9948 break;
9949
9950 case 2:
9951 if (imm == 0)
9952 imm = 32;
9953 func (stream, ", asr #%u", imm);
9954 break;
9955
9956 case 3:
9957 if (imm == 0)
9958 func (stream, ", rrx");
9959 else
9960 func (stream, ", ror #%u", imm);
9961 }
9962 }
9963 break;
9964
9965 case 'a':
9966 {
9967 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 9968 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 9969 unsigned int op = (given & 0x00000f00) >> 8;
9970 unsigned int i12 = (given & 0x00000fff);
9971 unsigned int i8 = (given & 0x000000ff);
9972 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 9973 bfd_vma offset = 0;
c19d1205
ZW		 9974
9975 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 9976 if (U) /* 12-bit positive immediate offset. */
9977 {
9978 offset = i12;
9979 if (Rn != 15)
9980 value_in_comment = offset;
9981 }
9982 else if (Rn == 15) /* 12-bit negative immediate offset. */
9983 offset = - (int) i12;
9984 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 9985 {
9986 unsigned int Rm = (i8 & 0x0f);
9987 unsigned int sh = (i8 & 0x30) >> 4;
05413229 9988
c19d1205
ZW		 9989 func (stream, ", %s", arm_regnames[Rm]);
9990 if (sh)
9991 func (stream, ", lsl #%u", sh);
9992 func (stream, "]");
9993 break;
9994 }
9995 else switch (op)
9996 {
05413229 9997 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 9998 offset = i8;
9999 break;
10000
05413229 10001 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 10002 offset = -i8;
10003 break;
10004
05413229 10005 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 10006 offset = i8;
10007 writeback = TRUE;
10008 break;
10009
05413229 10010 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 10011 offset = -i8;
10012 writeback = TRUE;
10013 break;
10014
05413229 10015 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 10016 offset = i8;
10017 postind = TRUE;
10018 break;
10019
05413229 10020 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 10021 offset = -i8;
10022 postind = TRUE;
10023 break;
10024
10025 default:
10026 func (stream, ", <undefined>]");
10027 goto skip;
10028 }
10029
10030 if (postind)
d908c8af 10031 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 10032 else
10033 {
10034 if (offset)
d908c8af 10035 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 10036 func (stream, writeback ? "]!" : "]");
10037 }
10038
10039 if (Rn == 15)
10040 {
10041 func (stream, "\t; ");
10042 info->print_address_func (((pc + 4) & ~3) + offset, info);
10043 }
10044 }
10045 skip:
10046 break;
10047
10048 case 'A':
10049 {
c1e26897
NC		 10050 unsigned int U = ! NEGATIVE_BIT_SET;
10051 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 10052 unsigned int Rn = (given & 0x000f0000) >> 16;
10053 unsigned int off = (given & 0x000000ff);
10054
10055 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 10056
10057 if (PRE_BIT_SET)
c19d1205
ZW		 10058 {
10059 if (off || !U)
05413229
NC		 10060 {
10061 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
fe50e98c 10062 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 10063 }
c19d1205
ZW		 10064 func (stream, "]");
10065 if (W)
10066 func (stream, "!");
10067 }
10068 else
10069 {
10070 func (stream, "], ");
10071 if (W)
05413229
NC		 10072 {
10073 func (stream, "#%c%u", U ? '+' : '-', off * 4);
fe50e98c 10074 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 10075 }
c19d1205 10076 else
fe56b6ce
NC		 10077 {
10078 func (stream, "{%u}", off);
10079 value_in_comment = off;
10080 }
c19d1205
ZW		 10081 }
10082 }
10083 break;
10084
10085 case 'w':
10086 {
10087 unsigned int Sbit = (given & 0x01000000) >> 24;
10088 unsigned int type = (given & 0x00600000) >> 21;
05413229 10089
c19d1205
ZW		 10090 switch (type)
10091 {
10092 case 0: func (stream, Sbit ? "sb" : "b"); break;
10093 case 1: func (stream, Sbit ? "sh" : "h"); break;
10094 case 2:
10095 if (Sbit)
10096 func (stream, "??");
10097 break;
10098 case 3:
10099 func (stream, "??");
10100 break;
10101 }
10102 }
10103 break;
10104
4b5a202f
AV		 10105 case 'n':
10106 is_clrm = TRUE;
10107 /* Fall through. */
c19d1205
ZW		 10108 case 'm':
10109 {
10110 int started = 0;
10111 int reg;
10112
10113 func (stream, "{");
10114 for (reg = 0; reg < 16; reg++)
10115 if ((given & (1 << reg)) != 0)
10116 {
10117 if (started)
10118 func (stream, ", ");
10119 started = 1;
4b5a202f
AV		 10120 if (is_clrm && reg == 13)
10121 func (stream, "(invalid: %s)", arm_regnames[reg]);
10122 else if (is_clrm && reg == 15)
10123 func (stream, "%s", "APSR");
10124 else
10125 func (stream, "%s", arm_regnames[reg]);
c19d1205
ZW		 10126 }
10127 func (stream, "}");
10128 }
10129 break;
10130
10131 case 'E':
10132 {
10133 unsigned int msb = (given & 0x0000001f);
10134 unsigned int lsb = 0;
fe56b6ce 10135
c19d1205
ZW		 10136 lsb |= (given & 0x000000c0u) >> 6;
10137 lsb |= (given & 0x00007000u) >> 10;
10138 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
10139 }
10140 break;
10141
10142 case 'F':
10143 {
10144 unsigned int width = (given & 0x0000001f) + 1;
10145 unsigned int lsb = 0;
fe56b6ce 10146
c19d1205
ZW		 10147 lsb |= (given & 0x000000c0u) >> 6;
10148 lsb |= (given & 0x00007000u) >> 10;
10149 func (stream, "#%u, #%u", lsb, width);
10150 }
10151 break;
10152
e12437dc
AV		 10153 case 'G':
10154 {
10155 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
10156 func (stream, "%x", boff);
10157 }
10158 break;
10159
e5d6e09e
AV		 10160 case 'W':
10161 {
10162 unsigned int immA = (given & 0x001f0000u) >> 16;
10163 unsigned int immB = (given & 0x000007feu) >> 1;
10164 unsigned int immC = (given & 0x00000800u) >> 11;
10165 bfd_vma offset = 0;
10166
10167 offset |= immA << 12;
10168 offset |= immB << 2;
10169 offset |= immC << 1;
10170 /* Sign extend. */
10171 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
10172
10173 info->print_address_func (pc + 4 + offset, info);
10174 }
10175 break;
10176
1caf72a5
AV		 10177 case 'Y':
10178 {
10179 unsigned int immA = (given & 0x007f0000u) >> 16;
10180 unsigned int immB = (given & 0x000007feu) >> 1;
10181 unsigned int immC = (given & 0x00000800u) >> 11;
10182 bfd_vma offset = 0;
10183
10184 offset |= immA << 12;
10185 offset |= immB << 2;
10186 offset |= immC << 1;
10187 /* Sign extend. */
10188 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
10189
10190 info->print_address_func (pc + 4 + offset, info);
10191 }
10192 break;
10193
1889da70
AV		 10194 case 'Z':
10195 {
10196 unsigned int immA = (given & 0x00010000u) >> 16;
10197 unsigned int immB = (given & 0x000007feu) >> 1;
10198 unsigned int immC = (given & 0x00000800u) >> 11;
10199 bfd_vma offset = 0;
10200
10201 offset |= immA << 12;
10202 offset |= immB << 2;
10203 offset |= immC << 1;
10204 /* Sign extend. */
10205 offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
10206
10207 info->print_address_func (pc + 4 + offset, info);
f6b2b12d
AV		 10208
10209 unsigned int T = (given & 0x00020000u) >> 17;
10210 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
10211 unsigned int boffset = (T == 1) ? 4 : 2;
10212 func (stream, ", ");
10213 func (stream, "%x", endoffset + boffset);
1889da70
AV		 10214 }
10215 break;
10216
60f993ce
AV		 10217 case 'Q':
10218 {
10219 unsigned int immh = (given & 0x000007feu) >> 1;
10220 unsigned int imml = (given & 0x00000800u) >> 11;
10221 bfd_vma imm32 = 0;
10222
10223 imm32 |= immh << 2;
10224 imm32 |= imml << 1;
10225
10226 info->print_address_func (pc + 4 + imm32, info);
10227 }
10228 break;
10229
10230 case 'P':
10231 {
10232 unsigned int immh = (given & 0x000007feu) >> 1;
10233 unsigned int imml = (given & 0x00000800u) >> 11;
10234 bfd_vma imm32 = 0;
10235
10236 imm32 |= immh << 2;
10237 imm32 |= imml << 1;
10238
10239 info->print_address_func (pc + 4 - imm32, info);
10240 }
10241 break;
10242
c19d1205
ZW		 10243 case 'b':
10244 {
10245 unsigned int S = (given & 0x04000000u) >> 26;
10246 unsigned int J1 = (given & 0x00002000u) >> 13;
10247 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 10248 bfd_vma offset = 0;
c19d1205
ZW		 10249
10250 offset |= !S << 20;
10251 offset |= J2 << 19;
10252 offset |= J1 << 18;
10253 offset |= (given & 0x003f0000) >> 4;
10254 offset |= (given & 0x000007ff) << 1;
10255 offset -= (1 << 20);
10256
10257 info->print_address_func (pc + 4 + offset, info);
10258 }
10259 break;
10260
10261 case 'B':
10262 {
10263 unsigned int S = (given & 0x04000000u) >> 26;
10264 unsigned int I1 = (given & 0x00002000u) >> 13;
10265 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 10266 bfd_vma offset = 0;
c19d1205
ZW		 10267
10268 offset |= !S << 24;
10269 offset |= !(I1 ^ S) << 23;
10270 offset |= !(I2 ^ S) << 22;
10271 offset |= (given & 0x03ff0000u) >> 4;
10272 offset |= (given & 0x000007ffu) << 1;
10273 offset -= (1 << 24);
36b0c57d 10274 offset += pc + 4;
c19d1205 10275
36b0c57d
PB		 10276 /* BLX target addresses are always word aligned. */
10277 if ((given & 0x00001000u) == 0)
10278 offset &= ~2u;
10279
10280 info->print_address_func (offset, info);
c19d1205
ZW		 10281 }
10282 break;
10283
10284 case 's':
10285 {
10286 unsigned int shift = 0;
fe56b6ce 10287
c19d1205
ZW		 10288 shift |= (given & 0x000000c0u) >> 6;
10289 shift |= (given & 0x00007000u) >> 10;
c1e26897 10290 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 10291 func (stream, ", asr #%u", shift);
10292 else if (shift)
10293 func (stream, ", lsl #%u", shift);
10294 /* else print nothing - lsl #0 */
10295 }
10296 break;
10297
10298 case 'R':
10299 {
10300 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 10301
c19d1205
ZW		 10302 if (rot)
10303 func (stream, ", ror #%u", rot * 8);
10304 }
10305 break;
10306
62b3e311 10307 case 'U':
43e65147 10308 if ((given & 0xf0) == 0x60)
62b3e311 10309 {
52e7f43d
RE		 10310 switch (given & 0xf)
10311 {
10312 case 0xf: func (stream, "sy"); break;
10313 default:
10314 func (stream, "#%d", (int) given & 0xf);
10315 break;
10316 }
62b3e311 10317 }
43e65147 10318 else
52e7f43d 10319 {
e797f7e0
MGD		 10320 const char * opt = data_barrier_option (given & 0xf);
10321 if (opt != NULL)
10322 func (stream, "%s", opt);
10323 else
10324 func (stream, "#%d", (int) given & 0xf);
52e7f43d 10325 }
62b3e311
PB		 10326 break;
10327
10328 case 'C':
10329 if ((given & 0xff) == 0)
10330 {
10331 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
10332 if (given & 0x800)
10333 func (stream, "f");
10334 if (given & 0x400)
10335 func (stream, "s");
10336 if (given & 0x200)
10337 func (stream, "x");
10338 if (given & 0x100)
10339 func (stream, "c");
10340 }
90ec0d68
MGD		 10341 else if ((given & 0x20) == 0x20)
10342 {
10343 char const* name;
10344 unsigned sysm = (given & 0xf00) >> 8;
10345
10346 sysm |= (given & 0x30);
10347 sysm |= (given & 0x00100000) >> 14;
10348 name = banked_regname (sysm);
43e65147 10349
90ec0d68
MGD		 10350 if (name != NULL)
10351 func (stream, "%s", name);
10352 else
d908c8af 10353 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 10354 }
62b3e311
PB		 10355 else
10356 {
d908c8af 10357 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 10358 }
10359 break;
10360
10361 case 'D':
90ec0d68
MGD		 10362 if (((given & 0xff) == 0)
10363 || ((given & 0x20) == 0x20))
10364 {
10365 char const* name;
10366 unsigned sm = (given & 0xf0000) >> 16;
10367
10368 sm |= (given & 0x30);
10369 sm |= (given & 0x00100000) >> 14;
10370 name = banked_regname (sm);
10371
10372 if (name != NULL)
10373 func (stream, "%s", name);
10374 else
d908c8af 10375 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 10376 }
62b3e311 10377 else
d908c8af 10378 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 10379 break;
10380
c19d1205
ZW		 10381 case '0': case '1': case '2': case '3': case '4':
10382 case '5': case '6': case '7': case '8': case '9':
10383 {
16980d0b
JB		 10384 int width;
10385 unsigned long val;
c19d1205 10386
16980d0b 10387 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 10388
c19d1205
ZW		 10389 switch (*c)
10390 {
d052b9b7
AV		 10391 case 's':
10392 if (val <= 3)
10393 func (stream, "%s", mve_vec_sizename[val]);
10394 else
10395 func (stream, "<undef size>");
10396 break;
10397
05413229
NC		 10398 case 'd':
10399 func (stream, "%lu", val);
10400 value_in_comment = val;
10401 break;
ff4a8d2b 10402
f0fba320
RL		 10403 case 'D':
10404 func (stream, "%lu", val + 1);
10405 value_in_comment = val + 1;
10406 break;
10407
05413229
NC		 10408 case 'W':
10409 func (stream, "%lu", val * 4);
10410 value_in_comment = val * 4;
10411 break;
ff4a8d2b 10412
f1c7f421
AV		 10413 case 'S':
10414 if (val == 13)
10415 is_unpredictable = TRUE;
10416 /* Fall through. */
ff4a8d2b
NC		 10417 case 'R':
10418 if (val == 15)
10419 is_unpredictable = TRUE;
10420 /* Fall through. */
10421 case 'r':
10422 func (stream, "%s", arm_regnames[val]);
10423 break;
c19d1205
ZW		 10424
10425 case 'c':
c22aaad1 10426 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 10427 break;
10428
10429 case '\'':
c19d1205 10430 c++;
16980d0b
JB		 10431 if (val == ((1ul << width) - 1))
10432 func (stream, "%c", *c);
c19d1205 10433 break;
43e65147 10434
c19d1205 10435 case '`':
c19d1205 10436 c++;
16980d0b
JB		 10437 if (val == 0)
10438 func (stream, "%c", *c);
c19d1205
ZW		 10439 break;
10440
10441 case '?':
fe56b6ce 10442 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 10443 c += 1 << width;
c19d1205 10444 break;
43e65147 10445
0bb027fd
RR		 10446 case 'x':
10447 func (stream, "0x%lx", val & 0xffffffffUL);
10448 break;
c19d1205
ZW		 10449
10450 default:
10451 abort ();
10452 }
10453 }
10454 break;
10455
32a94698
NC		 10456 case 'L':
10457 /* PR binutils/12534
10458 If we have a PC relative offset in an LDRD or STRD
10459 instructions then display the decoded address. */
10460 if (((given >> 16) & 0xf) == 0xf)
10461 {
10462 bfd_vma offset = (given & 0xff) * 4;
10463
10464 if ((given & (1 << 23)) == 0)
10465 offset = - offset;
10466 func (stream, "\t; ");
10467 info->print_address_func ((pc & ~3) + 4 + offset, info);
10468 }
10469 break;
10470
c19d1205
ZW		 10471 default:
10472 abort ();
10473 }
10474 }
05413229
NC		 10475
10476 if (value_in_comment > 32 || value_in_comment < -16)
10477 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 10478
10479 if (is_unpredictable)
10480 func (stream, UNPREDICTABLE_INSTRUCTION);
10481
4a5329c6 10482 return;
c19d1205 10483 }
252b5132 10484
58efb6c0 10485 /* No match. */
0b347048
TC		 10486 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
10487 return;
252b5132
RH		 10488}
10489
e821645d
DJ		 10490/* Print data bytes on INFO->STREAM. */
10491
10492static void
fe56b6ce
NC		 10493print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
10494 struct disassemble_info *info,
e821645d
DJ		 10495 long given)
10496{
10497 switch (info->bytes_per_chunk)
10498 {
10499 case 1:
10500 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
10501 break;
10502 case 2:
10503 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
10504 break;
10505 case 4:
10506 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
10507 break;
10508 default:
10509 abort ();
10510 }
10511}
10512
22a398e1 10513/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 10514 being displayed in symbol relative addresses.
10515
10516 Also disallow private symbol, with __tagsym$$ prefix,
10517 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 10518
10519bfd_boolean
10520arm_symbol_is_valid (asymbol * sym,
10521 struct disassemble_info * info ATTRIBUTE_UNUSED)
10522{
10523 const char * name;
43e65147 10524
22a398e1
NC		 10525 if (sym == NULL)
10526 return FALSE;
10527
10528 name = bfd_asymbol_name (sym);
10529
d8282f0e 10530 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 10531}
10532
65b48a81 10533/* Parse the string of disassembler options. */
baf0cc5e 10534
65b48a81 10535static void
f995bbe8 10536parse_arm_disassembler_options (const char *options)
dd92f639 10537{
f995bbe8 10538 const char *opt;
b34976b6 10539
65b48a81 10540 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
dd92f639 10541 {
65b48a81
PB		 10542 if (CONST_STRNEQ (opt, "reg-names-"))
10543 {
10544 unsigned int i;
10545 for (i = 0; i < NUM_ARM_OPTIONS; i++)
10546 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
10547 {
10548 regname_selected = i;
10549 break;
10550 }
b34976b6 10551
65b48a81 10552 if (i >= NUM_ARM_OPTIONS)
a6743a54
AM		 10553 /* xgettext: c-format */
10554 opcodes_error_handler (_("unrecognised register name set: %s"),
10555 opt);
65b48a81
PB		 10556 }
10557 else if (CONST_STRNEQ (opt, "force-thumb"))
10558 force_thumb = 1;
10559 else if (CONST_STRNEQ (opt, "no-force-thumb"))
10560 force_thumb = 0;
10561 else
a6743a54
AM		 10562 /* xgettext: c-format */
10563 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
dd92f639 10564 }
b34976b6 10565
dd92f639
NC		 10566 return;
10567}
10568
5bc5ae88
RL		 10569static bfd_boolean
10570mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
10571 enum map_type *map_symbol);
10572
c22aaad1
PB		 10573/* Search back through the insn stream to determine if this instruction is
10574 conditionally executed. */
fe56b6ce 10575
c22aaad1 10576static void
fe56b6ce
NC		 10577find_ifthen_state (bfd_vma pc,
10578 struct disassemble_info *info,
c22aaad1
PB		 10579 bfd_boolean little)
10580{
10581 unsigned char b[2];
10582 unsigned int insn;
10583 int status;
10584 /* COUNT is twice the number of instructions seen. It will be odd if we
10585 just crossed an instruction boundary. */
10586 int count;
10587 int it_count;
10588 unsigned int seen_it;
10589 bfd_vma addr;
10590
10591 ifthen_address = pc;
10592 ifthen_state = 0;
10593
10594 addr = pc;
10595 count = 1;
10596 it_count = 0;
10597 seen_it = 0;
10598 /* Scan backwards looking for IT instructions, keeping track of where
10599 instruction boundaries are. We don't know if something is actually an
10600 IT instruction until we find a definite instruction boundary. */
10601 for (;;)
10602 {
fe56b6ce 10603 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 10604 {
10605 /* A symbol must be on an instruction boundary, and will not
10606 be within an IT block. */
10607 if (seen_it && (count & 1))
10608 break;
10609
10610 return;
10611 }
10612 addr -= 2;
fe56b6ce 10613 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 10614 if (status)
10615 return;
10616
10617 if (little)
10618 insn = (b[0]) | (b[1] << 8);
10619 else
10620 insn = (b[1]) | (b[0] << 8);
10621 if (seen_it)
10622 {
10623 if ((insn & 0xf800) < 0xe800)
10624 {
10625 /* Addr + 2 is an instruction boundary. See if this matches
10626 the expected boundary based on the position of the last
10627 IT candidate. */
10628 if (count & 1)
10629 break;
10630 seen_it = 0;
10631 }
10632 }
10633 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
10634 {
5bc5ae88
RL		 10635 enum map_type type = MAP_ARM;
10636 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
10637
10638 if (!found || (found && type == MAP_THUMB))
10639 {
10640 /* This could be an IT instruction. */
10641 seen_it = insn;
10642 it_count = count >> 1;
10643 }
c22aaad1
PB		 10644 }
10645 if ((insn & 0xf800) >= 0xe800)
10646 count++;
10647 else
10648 count = (count + 2) | 1;
10649 /* IT blocks contain at most 4 instructions. */
10650 if (count >= 8 && !seen_it)
10651 return;
10652 }
10653 /* We found an IT instruction. */
10654 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
10655 if ((ifthen_state & 0xf) == 0)
10656 ifthen_state = 0;
10657}
10658
b0e28b39
DJ		 10659/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
10660 mapping symbol. */
10661
10662static int
10663is_mapping_symbol (struct disassemble_info *info, int n,
10664 enum map_type *map_type)
10665{
10666 const char *name;
10667
10668 name = bfd_asymbol_name (info->symtab[n]);
10669 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
10670 && (name[2] == 0 || name[2] == '.'))
10671 {
10672 *map_type = ((name[1] == 'a') ? MAP_ARM
10673 : (name[1] == 't') ? MAP_THUMB
10674 : MAP_DATA);
10675 return TRUE;
10676 }
10677
10678 return FALSE;
10679}
10680
10681/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
10682 Returns nonzero if *MAP_TYPE was set. */
10683
10684static int
10685get_map_sym_type (struct disassemble_info *info,
10686 int n,
10687 enum map_type *map_type)
10688{
10689 /* If the symbol is in a different section, ignore it. */
10690 if (info->section != NULL && info->section != info->symtab[n]->section)
10691 return FALSE;
10692
10693 return is_mapping_symbol (info, n, map_type);
10694}
10695
10696/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 10697 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 10698
10699static int
fe56b6ce
NC		 10700get_sym_code_type (struct disassemble_info *info,
10701 int n,
e821645d 10702 enum map_type *map_type)
2087ad84
PB		 10703{
10704 elf_symbol_type *es;
10705 unsigned int type;
b0e28b39
DJ		 10706
10707 /* If the symbol is in a different section, ignore it. */
10708 if (info->section != NULL && info->section != info->symtab[n]->section)
10709 return FALSE;
2087ad84 10710
e821645d 10711 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 10712 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
10713
10714 /* If the symbol has function type then use that. */
34e77a92 10715 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 10716 {
39d911fc
TP		 10717 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
10718 == ST_BRANCH_TO_THUMB)
35fc36a8
RS		 10719 *map_type = MAP_THUMB;
10720 else
10721 *map_type = MAP_ARM;
2087ad84
PB		 10722 return TRUE;
10723 }
10724
2087ad84
PB		 10725 return FALSE;
10726}
10727
5bc5ae88
RL		 10728/* Search the mapping symbol state for instruction at pc. This is only
10729 applicable for elf target.
10730
10731 There is an assumption Here, info->private_data contains the correct AND
10732 up-to-date information about current scan process. The information will be
10733 used to speed this search process.
10734
10735 Return TRUE if the mapping state can be determined, and map_symbol
10736 will be updated accordingly. Otherwise, return FALSE. */
10737
10738static bfd_boolean
10739mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
10740 enum map_type *map_symbol)
10741{
796d6298
TC		 10742 bfd_vma addr, section_vma = 0;
10743 int n, last_sym = -1;
5bc5ae88 10744 bfd_boolean found = FALSE;
796d6298
TC		 10745 bfd_boolean can_use_search_opt_p = FALSE;
10746
10747 /* Default to DATA. A text section is required by the ABI to contain an
10748 INSN mapping symbol at the start. A data section has no such
10749 requirement, hence if no mapping symbol is found the section must
10750 contain only data. This however isn't very useful if the user has
10751 fully stripped the binaries. If this is the case use the section
10752 attributes to determine the default. If we have no section default to
10753 INSN as well, as we may be disassembling some raw bytes on a baremetal
10754 HEX file or similar. */
10755 enum map_type type = MAP_DATA;
10756 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
10757 type = MAP_ARM;
5bc5ae88
RL		 10758 struct arm_private_data *private_data;
10759
796d6298 10760 if (info->private_data == NULL
5bc5ae88
RL		 10761 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
10762 return FALSE;
10763
10764 private_data = info->private_data;
5bc5ae88 10765
796d6298
TC		 10766 /* First, look for mapping symbols. */
10767 if (info->symtab_size != 0)
10768 {
10769 if (pc <= private_data->last_mapping_addr)
10770 private_data->last_mapping_sym = -1;
10771
10772 /* Start scanning at the start of the function, or wherever
10773 we finished last time. */
10774 n = info->symtab_pos + 1;
10775
10776 /* If the last stop offset is different from the current one it means we
10777 are disassembling a different glob of bytes. As such the optimization
10778 would not be safe and we should start over. */
10779 can_use_search_opt_p
10780 = private_data->last_mapping_sym >= 0
10781 && info->stop_offset == private_data->last_stop_offset;
10782
10783 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
10784 n = private_data->last_mapping_sym;
10785
10786 /* Look down while we haven't passed the location being disassembled.
10787 The reason for this is that there's no defined order between a symbol
10788 and an mapping symbol that may be at the same address. We may have to
10789 look at least one position ahead. */
10790 for (; n < info->symtab_size; n++)
10791 {
10792 addr = bfd_asymbol_value (info->symtab[n]);
10793 if (addr > pc)
10794 break;
10795 if (get_map_sym_type (info, n, &type))
10796 {
10797 last_sym = n;
10798 found = TRUE;
10799 }
10800 }
5bc5ae88 10801
796d6298
TC		 10802 if (!found)
10803 {
10804 n = info->symtab_pos;
10805 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
10806 n = private_data->last_mapping_sym;
10807
10808 /* No mapping symbol found at this address. Look backwards
10809 for a preceeding one, but don't go pass the section start
10810 otherwise a data section with no mapping symbol can pick up
10811 a text mapping symbol of a preceeding section. The documentation
10812 says section can be NULL, in which case we will seek up all the
10813 way to the top. */
10814 if (info->section)
10815 section_vma = info->section->vma;
10816
10817 for (; n >= 0; n--)
10818 {
10819 addr = bfd_asymbol_value (info->symtab[n]);
10820 if (addr < section_vma)
10821 break;
10822
10823 if (get_map_sym_type (info, n, &type))
10824 {
10825 last_sym = n;
10826 found = TRUE;
10827 break;
10828 }
10829 }
10830 }
10831 }
10832
10833 /* If no mapping symbol was found, try looking up without a mapping
10834 symbol. This is done by walking up from the current PC to the nearest
10835 symbol. We don't actually have to loop here since symtab_pos will
10836 contain the nearest symbol already. */
10837 if (!found)
5bc5ae88 10838 {
796d6298
TC		 10839 n = info->symtab_pos;
10840 if (n >= 0 && get_sym_code_type (info, n, &type))
5bc5ae88 10841 {
796d6298
TC		 10842 last_sym = n;
10843 found = TRUE;
5bc5ae88
RL		 10844 }
10845 }
10846
796d6298
TC		 10847 private_data->last_mapping_sym = last_sym;
10848 private_data->last_type = type;
10849 private_data->last_stop_offset = info->stop_offset;
5bc5ae88
RL		 10850
10851 *map_symbol = type;
10852 return found;
10853}
10854
0313a2b8
NC		 10855/* Given a bfd_mach_arm_XXX value, this function fills in the fields
10856 of the supplied arm_feature_set structure with bitmasks indicating
c0c468d5 10857 the supported base architectures and coprocessor extensions.
0313a2b8
NC		 10858
10859 FIXME: This could more efficiently implemented as a constant array,
10860 although it would also be less robust. */
10861
10862static void
10863select_arm_features (unsigned long mach,
10864 arm_feature_set * features)
10865{
c0c468d5
TP		 10866 arm_feature_set arch_fset;
10867 const arm_feature_set fpu_any = FPU_ANY;
10868
1af1dd51
MW		 10869#undef ARM_SET_FEATURES
10870#define ARM_SET_FEATURES(FSET) \
10871 { \
10872 const arm_feature_set fset = FSET; \
c0c468d5 10873 arch_fset = fset; \
1af1dd51 10874 }
823d2571 10875
c0c468d5
TP		 10876 /* When several architecture versions share the same bfd_mach_arm_XXX value
10877 the most featureful is chosen. */
0313a2b8
NC		 10878 switch (mach)
10879 {
c0c468d5
TP		 10880 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
10881 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
10882 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
10883 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
10884 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
10885 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
10886 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
10887 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
10888 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
10889 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
1af1dd51 10890 case bfd_mach_arm_ep9312:
c0c468d5
TP		 10891 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
10892 ARM_CEXT_MAVERICK | FPU_MAVERICK));
1af1dd51 10893 break;
c0c468d5
TP		 10894 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
10895 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
10896 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
10897 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
10898 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
10899 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
10900 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
10901 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
10902 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
10903 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
10904 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
10905 case bfd_mach_arm_8:
10906 {
0632eeea
SD		 10907 /* Add bits for extensions that Armv8.5-A recognizes. */
10908 arm_feature_set armv8_5_ext_fset
10909 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
10910 ARM_SET_FEATURES (ARM_ARCH_V8_5A);
10911 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset);
c0c468d5
TP		 10912 break;
10913 }
10914 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
10915 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
10916 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
73cd51e5
AV		 10917 case bfd_mach_arm_8_1M_MAIN:
10918 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
10919 force_thumb = 1;
10920 break;
c0c468d5
TP		 10921 /* If the machine type is unknown allow all architecture types and all
10922 extensions. */
10923 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
0313a2b8
NC		 10924 default:
10925 abort ();
10926 }
1af1dd51 10927#undef ARM_SET_FEATURES
c0c468d5
TP		 10928
10929 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
10930 and thus on bfd_mach_arm_XXX value. Therefore for a given
10931 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
10932 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
0313a2b8
NC		 10933}
10934
10935
58efb6c0
NC		 10936/* NOTE: There are no checks in these routines that
10937 the relevant number of data bytes exist. */
baf0cc5e 10938
58efb6c0 10939static int
4a5329c6 10940print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 10941{
c19d1205
ZW		 10942 unsigned char b[4];
10943 long given;
10944 int status;
e821645d 10945 int is_thumb = FALSE;
b0e28b39 10946 int is_data = FALSE;
bd2e2557 10947 int little_code;
e821645d 10948 unsigned int size = 4;
4a5329c6 10949 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 10950 bfd_boolean found = FALSE;
b0e28b39 10951 struct arm_private_data *private_data;
58efb6c0 10952
dd92f639
NC		 10953 if (info->disassembler_options)
10954 {
65b48a81 10955 parse_arm_disassembler_options (info->disassembler_options);
b34976b6 10956
58efb6c0 10957 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 10958 info->disassembler_options = NULL;
10959 }
b34976b6 10960
0313a2b8
NC		 10961 /* PR 10288: Control which instructions will be disassembled. */
10962 if (info->private_data == NULL)
10963 {
b0e28b39 10964 static struct arm_private_data private;
0313a2b8
NC		 10965
10966 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
10967 /* If the user did not use the -m command line switch then default to
10968 disassembling all types of ARM instruction.
43e65147 10969
0313a2b8
NC		 10970 The info->mach value has to be ignored as this will be based on
10971 the default archictecture for the target and/or hints in the notes
10972 section, but it will never be greater than the current largest arm
10973 machine value (iWMMXt2), which is only equivalent to the V5TE
10974 architecture. ARM architectures have advanced beyond the machine
10975 value encoding, and these newer architectures would be ignored if
10976 the machine value was used.
10977
10978 Ie the -m switch is used to restrict which instructions will be
10979 disassembled. If it is necessary to use the -m switch to tell
10980 objdump that an ARM binary is being disassembled, eg because the
10981 input is a raw binary file, but it is also desired to disassemble
10982 all ARM instructions then use "-marm". This will select the
10983 "unknown" arm architecture which is compatible with any ARM
10984 instruction. */
10985 info->mach = bfd_mach_arm_unknown;
10986
10987 /* Compute the architecture bitmask from the machine number.
10988 Note: This assumes that the machine number will not change
10989 during disassembly.... */
b0e28b39 10990 select_arm_features (info->mach, & private.features);
0313a2b8 10991
1fbaefec
PB		 10992 private.last_mapping_sym = -1;
10993 private.last_mapping_addr = 0;
796d6298 10994 private.last_stop_offset = 0;
b0e28b39
DJ		 10995
10996 info->private_data = & private;
0313a2b8 10997 }
b0e28b39
DJ		 10998
10999 private_data = info->private_data;
11000
bd2e2557
SS		 11001 /* Decide if our code is going to be little-endian, despite what the
11002 function argument might say. */
11003 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
11004
b0e28b39
DJ		 11005 /* For ELF, consult the symbol table to determine what kind of code
11006 or data we have. */
8977d4b2 11007 if (info->symtab_size != 0
e821645d
DJ		 11008 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
11009 {
11010 bfd_vma addr;
796d6298 11011 int n;
e821645d 11012 int last_sym = -1;
b0e28b39 11013 enum map_type type = MAP_ARM;
e821645d 11014
796d6298
TC		 11015 found = mapping_symbol_for_insn (pc, info, &type);
11016 last_sym = private_data->last_mapping_sym;
e821645d 11017
1fbaefec
PB		 11018 is_thumb = (private_data->last_type == MAP_THUMB);
11019 is_data = (private_data->last_type == MAP_DATA);
b34976b6 11020
e821645d
DJ		 11021 /* Look a little bit ahead to see if we should print out
11022 two or four bytes of data. If there's a symbol,
11023 mapping or otherwise, after two bytes then don't
11024 print more. */
11025 if (is_data)
11026 {
11027 size = 4 - (pc & 3);
11028 for (n = last_sym + 1; n < info->symtab_size; n++)
11029 {
11030 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 11031 if (addr > pc
11032 && (info->section == NULL
11033 || info->section == info->symtab[n]->section))
e821645d
DJ		 11034 {
11035 if (addr - pc < size)
11036 size = addr - pc;
11037 break;
11038 }
11039 }
11040 /* If the next symbol is after three bytes, we need to
11041 print only part of the data, so that we can use either
11042 .byte or .short. */
11043 if (size == 3)
11044 size = (pc & 1) ? 1 : 2;
11045 }
11046 }
11047
11048 if (info->symbols != NULL)
252b5132 11049 {
5876e06d
NC		 11050 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
11051 {
2f0ca46a 11052 coff_symbol_type * cs;
b34976b6 11053
5876e06d
NC		 11054 cs = coffsymbol (*info->symbols);
11055 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
11056 || cs->native->u.syment.n_sclass == C_THUMBSTAT
11057 || cs->native->u.syment.n_sclass == C_THUMBLABEL
11058 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
11059 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
11060 }
e821645d
DJ		 11061 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
11062 && !found)
5876e06d 11063 {
2087ad84
PB		 11064 /* If no mapping symbol has been found then fall back to the type
11065 of the function symbol. */
e821645d
DJ		 11066 elf_symbol_type * es;
11067 unsigned int type;
2087ad84 11068
e821645d
DJ		 11069 es = *(elf_symbol_type **)(info->symbols);
11070 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 11071
39d911fc
TP		 11072 is_thumb =
11073 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
11074 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
5876e06d 11075 }
e49d43ff
TG		 11076 else if (bfd_asymbol_flavour (*info->symbols)
11077 == bfd_target_mach_o_flavour)
11078 {
11079 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
11080
11081 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
11082 }
5876e06d 11083 }
b34976b6 11084
e821645d
DJ		 11085 if (force_thumb)
11086 is_thumb = TRUE;
11087
b8f9ee44
CL		 11088 if (is_data)
11089 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
11090 else
11091 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
11092
c19d1205 11093 info->bytes_per_line = 4;
252b5132 11094
1316c8b3
NC		 11095 /* PR 10263: Disassemble data if requested to do so by the user. */
11096 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 11097 {
11098 int i;
11099
1316c8b3 11100 /* Size was already set above. */
e821645d
DJ		 11101 info->bytes_per_chunk = size;
11102 printer = print_insn_data;
11103
fe56b6ce 11104 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 11105 given = 0;
11106 if (little)
11107 for (i = size - 1; i >= 0; i--)
11108 given = b[i] | (given << 8);
11109 else
11110 for (i = 0; i < (int) size; i++)
11111 given = b[i] | (given << 8);
11112 }
11113 else if (!is_thumb)
252b5132 11114 {
c19d1205
ZW		 11115 /* In ARM mode endianness is a straightforward issue: the instruction
11116 is four bytes long and is either ordered 0123 or 3210. */
11117 printer = print_insn_arm;
11118 info->bytes_per_chunk = 4;
4a5329c6 11119 size = 4;
c19d1205 11120
0313a2b8 11121 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 11122 if (little_code)
c19d1205
ZW		 11123 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
11124 else
11125 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
252b5132 11126 }
58efb6c0 11127 else
252b5132 11128 {
c19d1205
ZW		 11129 /* In Thumb mode we have the additional wrinkle of two
11130 instruction lengths. Fortunately, the bits that determine
11131 the length of the current instruction are always to be found
11132 in the first two bytes. */
4a5329c6 11133 printer = print_insn_thumb16;
c19d1205 11134 info->bytes_per_chunk = 2;
4a5329c6
ZW		 11135 size = 2;
11136
fe56b6ce 11137 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 11138 if (little_code)
9a2ff3f5
AM		 11139 given = (b[0]) | (b[1] << 8);
11140 else
11141 given = (b[1]) | (b[0] << 8);
11142
c19d1205 11143 if (!status)
252b5132 11144 {
c19d1205
ZW		 11145 /* These bit patterns signal a four-byte Thumb
11146 instruction. */
11147 if ((given & 0xF800) == 0xF800
11148 || (given & 0xF800) == 0xF000
11149 || (given & 0xF800) == 0xE800)
252b5132 11150 {
0313a2b8 11151 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 11152 if (little_code)
c19d1205 11153 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 11154 else
c19d1205
ZW		 11155 given = (b[1]) | (b[0] << 8) | (given << 16);
11156
11157 printer = print_insn_thumb32;
4a5329c6 11158 size = 4;
252b5132 11159 }
252b5132 11160 }
c22aaad1
PB		 11161
11162 if (ifthen_address != pc)
0313a2b8 11163 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 11164
11165 if (ifthen_state)
11166 {
11167 if ((ifthen_state & 0xf) == 0x8)
11168 ifthen_next_state = 0;
11169 else
11170 ifthen_next_state = (ifthen_state & 0xe0)
11171 | ((ifthen_state & 0xf) << 1);
11172 }
252b5132 11173 }
b34976b6 11174
c19d1205
ZW		 11175 if (status)
11176 {
11177 info->memory_error_func (status, pc, info);
11178 return -1;
11179 }
6a56ec7e
NC		 11180 if (info->flags & INSN_HAS_RELOC)
11181 /* If the instruction has a reloc associated with it, then
11182 the offset field in the instruction will actually be the
11183 addend for the reloc. (We are using REL type relocs).
11184 In such cases, we can ignore the pc when computing
11185 addresses, since the addend is not currently pc-relative. */
11186 pc = 0;
b34976b6 11187
4a5329c6 11188 printer (pc, info, given);
c22aaad1
PB		 11189
11190 if (is_thumb)
11191 {
11192 ifthen_state = ifthen_next_state;
11193 ifthen_address += size;
11194 }
4a5329c6 11195 return size;
252b5132
RH		 11196}
11197
11198int
4a5329c6 11199print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 11200{
bd2e2557
SS		 11201 /* Detect BE8-ness and record it in the disassembler info. */
11202 if (info->flavour == bfd_target_elf_flavour
11203 && info->section != NULL
11204 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
11205 info->endian_code = BFD_ENDIAN_LITTLE;
11206
b34976b6 11207 return print_insn (pc, info, FALSE);
58efb6c0 11208}
01c7f630 11209
58efb6c0 11210int
4a5329c6 11211print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 11212{
b34976b6 11213 return print_insn (pc, info, TRUE);
58efb6c0 11214}
252b5132 11215
471b9d15 11216const disasm_options_and_args_t *
65b48a81
PB		 11217disassembler_options_arm (void)
11218{
471b9d15 11219 static disasm_options_and_args_t *opts_and_args;
65b48a81 11220
471b9d15 11221 if (opts_and_args == NULL)
65b48a81 11222 {
471b9d15 11223 disasm_options_t *opts;
65b48a81 11224 unsigned int i;
471b9d15
MR		 11225
11226 opts_and_args = XNEW (disasm_options_and_args_t);
11227 opts_and_args->args = NULL;
11228
11229 opts = &opts_and_args->options;
65b48a81
PB		 11230 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
11231 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
471b9d15 11232 opts->arg = NULL;
65b48a81
PB		 11233 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11234 {
11235 opts->name[i] = regnames[i].name;
11236 if (regnames[i].description != NULL)
11237 opts->description[i] = _(regnames[i].description);
11238 else
11239 opts->description[i] = NULL;
11240 }
11241 /* The array we return must be NULL terminated. */
11242 opts->name[i] = NULL;
11243 opts->description[i] = NULL;
11244 }
11245
471b9d15 11246 return opts_and_args;
65b48a81
PB		 11247}
11248
58efb6c0 11249void
4a5329c6 11250print_arm_disassembler_options (FILE *stream)
58efb6c0 11251{
65b48a81 11252 unsigned int i, max_len = 0;
58efb6c0
NC		 11253 fprintf (stream, _("\n\
11254The following ARM specific disassembler options are supported for use with\n\
11255the -M switch:\n"));
b34976b6 11256
65b48a81
PB		 11257 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11258 {
11259 unsigned int len = strlen (regnames[i].name);
11260 if (max_len < len)
11261 max_len = len;
11262 }
58efb6c0 11263
65b48a81
PB		 11264 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
11265 fprintf (stream, " %s%*c %s\n",
11266 regnames[i].name,
11267 (int)(max_len - strlen (regnames[i].name)), ' ',
11268 _(regnames[i].description));
252b5132 11269}
GDB Binutils - Deliverables
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