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[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
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252b5132 1/* Instruction printing code for the ARM
82704155 2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
143275ea 24#include <assert.h>
2fbad815 25
6394c606 26#include "disassemble.h"
2fbad815 27#include "opcode/arm.h"
252b5132 28#include "opintl.h"
31e0f3cd 29#include "safe-ctype.h"
65b48a81 30#include "libiberty.h"
0dbde4cf 31#include "floatformat.h"
252b5132 32
baf0cc5e 33/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 34#include "coff/internal.h"
35#include "libcoff.h"
2d5d5a8f 36#include "bfd.h"
252b5132
RH		 37#include "elf-bfd.h"
38#include "elf/internal.h"
39#include "elf/arm.h"
e49d43ff 40#include "mach-o.h"
252b5132 41
6b5d3a4d 42/* FIXME: Belongs in global header. */
01c7f630 43#ifndef strneq
58efb6c0
NC		 44#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
45#endif
46
1fbaefec
PB		 47/* Cached mapping symbol state. */
48enum map_type
49{
50 MAP_ARM,
51 MAP_THUMB,
52 MAP_DATA
53};
54
b0e28b39
DJ		 55struct arm_private_data
56{
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features;
59
1fbaefec
PB		 60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type;
62
63 /* Tracking symbol table information */
64 int last_mapping_sym;
796d6298
TC		 65
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset;
1fbaefec 68 bfd_vma last_mapping_addr;
b0e28b39
DJ		 69};
70
73cd51e5
AV		 71enum mve_instructions
72{
143275ea
AV		 73 MVE_VPST,
74 MVE_VPT_FP_T1,
75 MVE_VPT_FP_T2,
76 MVE_VPT_VEC_T1,
77 MVE_VPT_VEC_T2,
78 MVE_VPT_VEC_T3,
79 MVE_VPT_VEC_T4,
80 MVE_VPT_VEC_T5,
81 MVE_VPT_VEC_T6,
82 MVE_VCMP_FP_T1,
83 MVE_VCMP_FP_T2,
84 MVE_VCMP_VEC_T1,
85 MVE_VCMP_VEC_T2,
86 MVE_VCMP_VEC_T3,
87 MVE_VCMP_VEC_T4,
88 MVE_VCMP_VEC_T5,
89 MVE_VCMP_VEC_T6,
9743db03
AV		 90 MVE_VDUP,
91 MVE_VEOR,
92 MVE_VFMAS_FP_SCALAR,
93 MVE_VFMA_FP_SCALAR,
94 MVE_VFMA_FP,
95 MVE_VFMS_FP,
96 MVE_VHADD_T1,
97 MVE_VHADD_T2,
98 MVE_VHSUB_T1,
99 MVE_VHSUB_T2,
100 MVE_VRHADD,
04d54ace
AV		 101 MVE_VLD2,
102 MVE_VLD4,
103 MVE_VST2,
104 MVE_VST4,
aef6d006
AV		 105 MVE_VLDRB_T1,
106 MVE_VLDRH_T2,
107 MVE_VLDRB_T5,
108 MVE_VLDRH_T6,
109 MVE_VLDRW_T7,
110 MVE_VSTRB_T1,
111 MVE_VSTRH_T2,
112 MVE_VSTRB_T5,
113 MVE_VSTRH_T6,
114 MVE_VSTRW_T7,
ef1576a1
AV		 115 MVE_VLDRB_GATHER_T1,
116 MVE_VLDRH_GATHER_T2,
117 MVE_VLDRW_GATHER_T3,
118 MVE_VLDRD_GATHER_T4,
119 MVE_VLDRW_GATHER_T5,
120 MVE_VLDRD_GATHER_T6,
121 MVE_VSTRB_SCATTER_T1,
122 MVE_VSTRH_SCATTER_T2,
123 MVE_VSTRW_SCATTER_T3,
124 MVE_VSTRD_SCATTER_T4,
125 MVE_VSTRW_SCATTER_T5,
126 MVE_VSTRD_SCATTER_T6,
bf0b396d
AV		 127 MVE_VCVT_FP_FIX_VEC,
128 MVE_VCVT_BETWEEN_FP_INT,
129 MVE_VCVT_FP_HALF_FP,
130 MVE_VCVT_FROM_FP_TO_INT,
131 MVE_VRINT_FP,
c507f10b
AV		 132 MVE_VMOV_HFP_TO_GP,
133 MVE_VMOV_GP_TO_VEC_LANE,
134 MVE_VMOV_IMM_TO_VEC,
135 MVE_VMOV_VEC_TO_VEC,
136 MVE_VMOV2_VEC_LANE_TO_GP,
137 MVE_VMOV2_GP_TO_VEC_LANE,
138 MVE_VMOV_VEC_LANE_TO_GP,
139 MVE_VMVN_IMM,
140 MVE_VMVN_REG,
141 MVE_VORR_IMM,
142 MVE_VORR_REG,
143 MVE_VORN,
144 MVE_VBIC_IMM,
145 MVE_VBIC_REG,
146 MVE_VMOVX,
14925797
AV		 147 MVE_VMOVL,
148 MVE_VMOVN,
149 MVE_VMULL_INT,
150 MVE_VMULL_POLY,
151 MVE_VQDMULL_T1,
152 MVE_VQDMULL_T2,
153 MVE_VQMOVN,
154 MVE_VQMOVUN,
d3b63143
AV		 155 MVE_VADDV,
156 MVE_VMLADAV_T1,
157 MVE_VMLADAV_T2,
158 MVE_VMLALDAV,
159 MVE_VMLAS,
160 MVE_VADDLV,
161 MVE_VMLSDAV_T1,
162 MVE_VMLSDAV_T2,
163 MVE_VMLSLDAV,
164 MVE_VRMLALDAVH,
165 MVE_VRMLSLDAVH,
166 MVE_VQDMLADH,
167 MVE_VQRDMLADH,
168 MVE_VQDMLAH,
169 MVE_VQRDMLAH,
170 MVE_VQDMLASH,
171 MVE_VQRDMLASH,
172 MVE_VQDMLSDH,
173 MVE_VQRDMLSDH,
174 MVE_VQDMULH_T1,
175 MVE_VQRDMULH_T2,
176 MVE_VQDMULH_T3,
177 MVE_VQRDMULH_T4,
1c8f2df8
AV		 178 MVE_VDDUP,
179 MVE_VDWDUP,
180 MVE_VIWDUP,
181 MVE_VIDUP,
897b9bbc
AV		 182 MVE_VCADD_FP,
183 MVE_VCADD_VEC,
184 MVE_VHCADD,
185 MVE_VCMLA_FP,
186 MVE_VCMUL_FP,
ed63aa17
AV		 187 MVE_VQRSHL_T1,
188 MVE_VQRSHL_T2,
189 MVE_VQRSHRN,
190 MVE_VQRSHRUN,
191 MVE_VQSHL_T1,
192 MVE_VQSHL_T2,
193 MVE_VQSHLU_T3,
194 MVE_VQSHL_T4,
195 MVE_VQSHRN,
196 MVE_VQSHRUN,
197 MVE_VRSHL_T1,
198 MVE_VRSHL_T2,
199 MVE_VRSHR,
200 MVE_VRSHRN,
201 MVE_VSHL_T1,
202 MVE_VSHL_T2,
203 MVE_VSHL_T3,
204 MVE_VSHLC,
205 MVE_VSHLL_T1,
206 MVE_VSHLL_T2,
207 MVE_VSHR,
208 MVE_VSHRN,
209 MVE_VSLI,
210 MVE_VSRI,
66dcaa5d
AV		 211 MVE_VADC,
212 MVE_VABAV,
213 MVE_VABD_FP,
214 MVE_VABD_VEC,
215 MVE_VABS_FP,
216 MVE_VABS_VEC,
217 MVE_VADD_FP_T1,
218 MVE_VADD_FP_T2,
219 MVE_VADD_VEC_T1,
220 MVE_VADD_VEC_T2,
221 MVE_VSBC,
222 MVE_VSUB_FP_T1,
223 MVE_VSUB_FP_T2,
224 MVE_VSUB_VEC_T1,
225 MVE_VSUB_VEC_T2,
e523f101
AV		 226 MVE_VAND,
227 MVE_VBRSR,
228 MVE_VCLS,
229 MVE_VCLZ,
230 MVE_VCTP,
56858bea
AV		 231 MVE_VMAX,
232 MVE_VMAXA,
233 MVE_VMAXNM_FP,
234 MVE_VMAXNMA_FP,
235 MVE_VMAXNMV_FP,
236 MVE_VMAXNMAV_FP,
237 MVE_VMAXV,
238 MVE_VMAXAV,
239 MVE_VMIN,
240 MVE_VMINA,
241 MVE_VMINNM_FP,
242 MVE_VMINNMA_FP,
243 MVE_VMINNMV_FP,
244 MVE_VMINNMAV_FP,
245 MVE_VMINV,
246 MVE_VMINAV,
247 MVE_VMLA,
f49bb598
AV		 248 MVE_VMUL_FP_T1,
249 MVE_VMUL_FP_T2,
250 MVE_VMUL_VEC_T1,
251 MVE_VMUL_VEC_T2,
252 MVE_VMULH,
253 MVE_VRMULH,
254 MVE_VNEG_FP,
255 MVE_VNEG_VEC,
14b456f2
AV		 256 MVE_VPNOT,
257 MVE_VPSEL,
258 MVE_VQABS,
259 MVE_VQADD_T1,
260 MVE_VQADD_T2,
261 MVE_VQSUB_T1,
262 MVE_VQSUB_T2,
263 MVE_VQNEG,
264 MVE_VREV16,
265 MVE_VREV32,
266 MVE_VREV64,
23d00a41
SD		 267 MVE_LSLL,
268 MVE_LSLLI,
269 MVE_LSRL,
270 MVE_ASRL,
271 MVE_ASRLI,
272 MVE_SQRSHRL,
273 MVE_SQRSHR,
274 MVE_UQRSHL,
275 MVE_UQRSHLL,
276 MVE_UQSHL,
277 MVE_UQSHLL,
278 MVE_URSHRL,
279 MVE_URSHR,
280 MVE_SRSHRL,
281 MVE_SRSHR,
282 MVE_SQSHLL,
283 MVE_SQSHL,
e39c1607
SD		 284 MVE_CINC,
285 MVE_CINV,
286 MVE_CNEG,
287 MVE_CSINC,
288 MVE_CSINV,
289 MVE_CSET,
290 MVE_CSETM,
291 MVE_CSNEG,
292 MVE_CSEL,
73cd51e5
AV		 293 MVE_NONE
294};
295
296enum mve_unpredictable
297{
298 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
299 */
143275ea
AV		 300 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and
301 fcB = 1 (vpt). */
302 UNPRED_R13, /* Unpredictable because r13 (sp) or
303 r15 (sp) used. */
9743db03 304 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
04d54ace
AV		 305 UNPRED_Q_GT_4, /* Unpredictable because
306 vec reg start > 4 (vld4/st4). */
307 UNPRED_Q_GT_6, /* Unpredictable because
308 vec reg start > 6 (vld2/st2). */
309 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
310 and WB bit = 1. */
ef1576a1
AV		 311 UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are
312 equal. */
313 UNPRED_OS, /* Unpredictable because offset scaled == 1. */
bf0b396d
AV		 314 UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the
315 same. */
c507f10b
AV		 316 UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and
317 size = 1. */
318 UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and
319 size = 2. */
73cd51e5
AV		 320 UNPRED_NONE /* No unpredictable behavior. */
321};
322
323enum mve_undefined
324{
ed63aa17 325 UNDEF_SIZE, /* undefined size. */
bf0b396d 326 UNDEF_SIZE_0, /* undefined because size == 0. */
c507f10b 327 UNDEF_SIZE_2, /* undefined because size == 2. */
aef6d006
AV		 328 UNDEF_SIZE_3, /* undefined because size == 3. */
329 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
14b456f2 330 UNDEF_SIZE_NOT_0, /* undefined because size != 0. */
ef1576a1
AV		 331 UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
332 UNDEF_SIZE_NOT_3, /* undefined because size != 3. */
333 UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and
334 size == 0. */
335 UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and
336 size == 1. */
337 UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
bf0b396d
AV		 338 UNDEF_VCVT_IMM6, /* imm6 < 32. */
339 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
c507f10b
AV		 340 UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and
341 op1 == (0 or 1). */
342 UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and
343 op2 == 0 and op1 == (0 or 1). */
344 UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode
345 in {0xx1, x0x1}. */
d3b63143 346 UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */
73cd51e5
AV		 347 UNDEF_NONE /* no undefined behavior. */
348};
349
6b5d3a4d
ZW		 350struct opcode32
351{
823d2571
TG		 352 arm_feature_set arch; /* Architecture defining this insn. */
353 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 354 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 355 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 356};
357
73cd51e5
AV		 358/* MVE opcodes. */
359
360struct mopcode32
361{
362 arm_feature_set arch; /* Architecture defining this insn. */
363 enum mve_instructions mve_op; /* Specific mve instruction for faster
364 decoding. */
365 unsigned long value; /* If arch is 0 then value is a sentinel. */
366 unsigned long mask; /* Recognise insn if (op & mask) == value. */
367 const char * assembler; /* How to disassemble this insn. */
368};
369
6b0dd094
AV		 370enum isa {
371 ANY,
372 T32,
373 ARM
374};
375
376
377/* Shared (between Arm and Thumb mode) opcode. */
378struct sopcode32
379{
380 enum isa isa; /* Execution mode instruction availability. */
381 arm_feature_set arch; /* Architecture defining this insn. */
382 unsigned long value; /* If arch is 0 then value is a sentinel. */
383 unsigned long mask; /* Recognise insn if (op & mask) == value. */
384 const char * assembler; /* How to disassemble this insn. */
385};
386
6b5d3a4d
ZW		 387struct opcode16
388{
823d2571 389 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 390 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 391 const char *assembler; /* How to disassemble this insn. */
392};
b7693d02 393
8f06b2d8 394/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 395
2fbad815 396 %% %
4a5329c6 397
c22aaad1 398 %c print condition code (always bits 28-31 in ARM mode)
37b37b2d 399 %q print shifter argument
e2efe87d
MGD		 400 %u print condition code (unconditional in ARM mode,
401 UNPREDICTABLE if not AL in Thumb)
4a5329c6 402 %A print address for ldc/stc/ldf/stf instruction
16980d0b 403 %B print vstm/vldm register list
efd6b359 404 %C print vscclrm register list
4a5329c6 405 %I print cirrus signed shift immediate: bits 0..3|4..6
32c36c3c
AV		 406 %J print register for VLDR instruction
407 %K print address for VLDR instruction
4a5329c6
ZW		 408 %F print the COUNT field of a LFM/SFM instruction.
409 %P print floating point precision in arithmetic insn
410 %Q print floating point precision in ldf/stf insn
411 %R print floating point rounding mode
412
33399f07 413 %<bitfield>c print as a condition code (for vsel)
4a5329c6 414 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 415 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
416 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 417 %<bitfield>d print the bitfield in decimal
16980d0b 418 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 419 %<bitfield>x print the bitfield in hex
420 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 421 %<bitfield>f print a floating point constant if >7 else a
422 floating point register
4a5329c6
ZW		 423 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
424 %<bitfield>g print as an iWMMXt 64-bit register
425 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 426 %<bitfield>D print as a NEON D register
427 %<bitfield>Q print as a NEON Q register
c28eeff2 428 %<bitfield>V print as a NEON D or Q register
6f1c2142 429 %<bitfield>E print a quarter-float immediate value
4a5329c6 430
16980d0b 431 %y<code> print a single precision VFP reg.
2fbad815 432 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 433 %z<code> print a double precision VFP reg
2fbad815 434 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 435
16980d0b
JB		 436 %<bitfield>'c print specified char iff bitfield is all ones
437 %<bitfield>`c print specified char iff bitfield is all zeroes
438 %<bitfield>?ab... select from array of values in big endian order
43e65147 439
2fbad815 440 %L print as an iWMMXt N/M width field.
4a5329c6 441 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 442 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 443 versions.
444 %i print 5-bit immediate in bits 8,3..0
445 (print "32" when 0)
fe56b6ce 446 %r print register offset address for wldt/wstr instruction. */
2fbad815 447
21d799b5 448enum opcode_sentinel_enum
05413229
NC		 449{
450 SENTINEL_IWMMXT_START = 1,
451 SENTINEL_IWMMXT_END,
452 SENTINEL_GENERIC_START
453} opcode_sentinels;
454
aefd8a40 455#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
0b347048
TC		 456#define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
457#define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
c1e26897 458#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 459
8f06b2d8 460/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 461
6b0dd094 462static const struct sopcode32 coprocessor_opcodes[] =
2fbad815 463{
2fbad815 464 /* XScale instructions. */
6b0dd094 465 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 466 0x0e200010, 0x0fff0ff0,
467 "mia%c\tacc0, %0-3r, %12-15r"},
6b0dd094 468 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 469 0x0e280010, 0x0fff0ff0,
470 "miaph%c\tacc0, %0-3r, %12-15r"},
6b0dd094 471 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 472 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
6b0dd094 473 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 474 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
6b0dd094 475 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 476 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 477
2fbad815 478 /* Intel Wireless MMX technology instructions. */
6b0dd094
AV		 479 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
480 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
823d2571 481 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
6b0dd094 482 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 483 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
6b0dd094 484 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 485 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
6b0dd094 486 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 487 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
6b0dd094 488 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 489 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
6b0dd094 490 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 491 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
6b0dd094 492 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 493 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
6b0dd094 494 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 495 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 496 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 497 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 498 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 499 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 500 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 501 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
6b0dd094 502 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 503 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
6b0dd094 504 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 505 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
6b0dd094 506 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 507 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
6b0dd094 508 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 509 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
6b0dd094 510 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 511 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 512 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 513 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 514 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 515 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 516 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 517 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 518 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 519 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 520 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 521 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
6b0dd094 522 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 523 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 524 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 525 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 526 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 527 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 528 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 529 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 530 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 531 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 532 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 533 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 534 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 535 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
6b0dd094 536 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 537 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
6b0dd094 538 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 539 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
6b0dd094 540 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 541 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 542 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 543 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 544 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 545 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 546 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 547 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 548 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 549 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
6b0dd094 550 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 551 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 552 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 553 0x0e800120, 0x0f800ff0,
554 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 555 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 556 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 557 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 558 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 559 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 560 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 561 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 562 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 563 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 564 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 565 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 566 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 567 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 568 0x0e8000a0, 0x0f800ff0,
569 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 570 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 571 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 572 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 573 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 574 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 575 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 576 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 577 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 578 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 579 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 580 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 581 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 582 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 583 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 584 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 585 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 586 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 587 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
6b0dd094 588 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 589 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 590 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 591 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 592 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 593 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 594 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 595 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 596 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 597 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 598 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 599 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 600 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 601 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 602 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 603 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 604 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 605 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 606 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 607 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
6b0dd094 608 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 609 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
6b0dd094 610 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 611 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
6b0dd094 612 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 613 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 614 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 615 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 616 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 617 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 618 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 619 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
6b0dd094 620 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 621 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
6b0dd094 622 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 623 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
6b0dd094 624 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 625 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 626 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 627 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 628 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 629 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 630 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 631 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 632 {ANY, ARM_FEATURE_CORE_LOW (0),
823d2571 633 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 634
fe56b6ce 635 /* Floating point coprocessor (FPA) instructions. */
6b0dd094 636 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 637 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 638 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 639 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 640 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 641 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 642 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 643 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 644 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 645 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 646 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 647 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 648 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 649 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 650 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 651 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 652 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 653 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 654 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 655 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 656 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 657 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 658 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 659 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 660 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 661 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 662 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 663 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 664 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 665 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 666 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 667 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 668 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 669 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 670 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 671 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
6b0dd094 672 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 673 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
6b0dd094 674 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 675 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 676 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 677 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
6b0dd094 678 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 679 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
6b0dd094 680 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 681 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
6b0dd094 682 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 683 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
6b0dd094 684 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 685 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 686 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 687 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 688 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 689 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 690 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 691 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 692 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 693 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
6b0dd094 694 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 695 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
6b0dd094 696 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 697 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
6b0dd094 698 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 699 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
6b0dd094 700 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 701 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
6b0dd094 702 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 703 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
6b0dd094 704 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 705 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
6b0dd094 706 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 707 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
6b0dd094 708 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 709 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
6b0dd094 710 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 711 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
6b0dd094 712 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 713 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
6b0dd094 714 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 715 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
6b0dd094 716 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 717 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
6b0dd094 718 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 719 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
6b0dd094 720 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 721 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 722
efd6b359
AV		 723 /* Armv8.1-M Mainline instructions. */
724 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
725 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
726 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
727 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
728
16a1fa25 729 /* ARMv8-M Mainline Security Extensions instructions. */
6b0dd094 730 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25 731 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
6b0dd094 732 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25
TP		 733 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
734
fe56b6ce 735 /* Register load/store. */
6b0dd094 736 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 737 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
6b0dd094 738 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 739 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
6b0dd094 740 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 741 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
6b0dd094 742 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 743 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
6b0dd094 744 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 745 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
6b0dd094 746 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 747 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
6b0dd094 748 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 749 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
6b0dd094 750 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 751 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
6b0dd094 752 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 753 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
6b0dd094 754 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 755 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
6b0dd094 756 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 757 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
6b0dd094 758 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 759 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
6b0dd094 760 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 761 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
6b0dd094 762 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 763 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
6b0dd094 764 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 765 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
6b0dd094 766 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 767 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
32c36c3c
AV		 768 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
769 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
770 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
771 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
823d2571 772
6b0dd094 773 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 774 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 775 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 776 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 777 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 778 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
6b0dd094 779 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 780 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 781
fe56b6ce 782 /* Data transfer between ARM and NEON registers. */
6b0dd094 783 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 784 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
6b0dd094 785 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 786 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
6b0dd094 787 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 788 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
6b0dd094 789 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 790 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
6b0dd094 791 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 792 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
6b0dd094 793 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 794 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
6b0dd094 795 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 796 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
6b0dd094 797 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 798 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 799 /* Half-precision conversion instructions. */
6b0dd094 800 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 801 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
6b0dd094 802 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 803 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
6b0dd094 804 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 805 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
6b0dd094 806 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 807 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 808
fe56b6ce 809 /* Floating point coprocessor (VFP) instructions. */
6b0dd094 810 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 811 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
ba6cd17f 812 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_MVE),
823d2571 813 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
ba6cd17f
SD		 814 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
815 0x0ee20a10, 0x0fff0fff, "vmsr%c\tfpscr_nzcvqc, %12-15r"},
6b0dd094 816 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 817 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
6b0dd094 818 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 819 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
6b0dd094 820 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 821 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
6b0dd094 822 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 823 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
6b0dd094 824 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 825 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
6b0dd094 826 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 827 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
ba6cd17f
SD		 828 {ANY, ARM_FEATURE_COPROC (FPU_MVE),
829 0x0eec0a10, 0x0fff0fff, "vmsr%c\tvpr, %12-15r"},
830 {ANY, ARM_FEATURE_COPROC (FPU_MVE),
831 0x0eed0a10, 0x0fff0fff, "vmsr%c\tp0, %12-15r"},
832 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
833 0x0eee0a10, 0x0fff0fff, "vmsr%c\tfpcxt_ns, %12-15r"},
834 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
835 0x0eef0a10, 0x0fff0fff, "vmsr%c\tfpcxt_s, %12-15r"},
6b0dd094 836 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 837 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
6b0dd094 838 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 839 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
ba6cd17f 840 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_MVE),
823d2571 841 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
ba6cd17f
SD		 842 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
843 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr_nzcvqc"},
6b0dd094 844 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 845 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
6b0dd094 846 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 847 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
6b0dd094 848 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 849 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
6b0dd094 850 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 851 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
6b0dd094 852 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 853 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
6b0dd094 854 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 855 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
ba6cd17f
SD		 856 {ANY, ARM_FEATURE_COPROC (FPU_MVE),
857 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, vpr"},
858 {ANY, ARM_FEATURE_COPROC (FPU_MVE),
859 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, p0"},
860 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
861 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_ns"},
862 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
863 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_s"},
6b0dd094 864 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 865 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
6b0dd094 866 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 867 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
6b0dd094 868 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 869 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
6b0dd094 870 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 871 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
6b0dd094 872 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 873 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
6b0dd094 874 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 875 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
6b0dd094 876 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 877 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
6b0dd094 878 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 879 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
6b0dd094 880 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 881 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
6b0dd094 882 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 883 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
6b0dd094 884 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 885 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
6b0dd094 886 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 887 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
6b0dd094 888 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 889 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
6b0dd094 890 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 891 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
6b0dd094 892 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 893 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
6b0dd094 894 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 895 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
6b0dd094 896 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 897 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
6b0dd094 898 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 899 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
6b0dd094 900 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 901 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
6b0dd094 902 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 903 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
6b0dd094 904 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 905 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
6b0dd094 906 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 907 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
6b0dd094 908 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 909 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 910 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 911 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
6b0dd094 912 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 913 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
6b0dd094 914 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 915 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
6b0dd094 916 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 917 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
6b0dd094 918 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 919 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
6b0dd094 920 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 921 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
6b0dd094 922 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6f1c2142 923 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
6b0dd094 924 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6f1c2142 925 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
6b0dd094 926 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 927 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
6b0dd094 928 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 929 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
6b0dd094 930 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 931 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
6b0dd094 932 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 933 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 934 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 935 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 936 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 937 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 938 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 939 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 940 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 941 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 942 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 943 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 944 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 945 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 946 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 947 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 948 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 949 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 950 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 951 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 952 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 953 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 954 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 955 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 956 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 957 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
6b0dd094 958 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 959 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
6b0dd094 960 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 961 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
6b0dd094 962 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 963 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
6b0dd094 964 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 965 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
6b0dd094 966 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 967 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 968
969 /* Cirrus coprocessor instructions. */
6b0dd094 970 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 971 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 972 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 973 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 974 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 975 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 976 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 977 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 978 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 979 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 980 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 981 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 982 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 983 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 984 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 985 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 986 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 987 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 988 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 989 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 990 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 991 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 992 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 993 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 994 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 995 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 996 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 997 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 998 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 999 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 1000 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1001 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 1002 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1003 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
6b0dd094 1004 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1005 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
6b0dd094 1006 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1007 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
6b0dd094 1008 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1009 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
6b0dd094 1010 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1011 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
6b0dd094 1012 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1013 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
6b0dd094 1014 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1015 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 1016 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1017 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
6b0dd094 1018 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1019 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 1020 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1021 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
6b0dd094 1022 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1023 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1024 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1025 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1026 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1027 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1028 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1029 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1030 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1031 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1032 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1033 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1034 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1035 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1036 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1037 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1038 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1039 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
6b0dd094 1040 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1041 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
6b0dd094 1042 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1043 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
6b0dd094 1044 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1045 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
6b0dd094 1046 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1047 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1048 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1049 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1050 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1051 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
6b0dd094 1052 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1053 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
6b0dd094 1054 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1055 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
6b0dd094 1056 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1057 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
6b0dd094 1058 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1059 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
6b0dd094 1060 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1061 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
6b0dd094 1062 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1063 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 1064 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1065 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 1066 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1067 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 1068 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1069 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 1070 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1071 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
6b0dd094 1072 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1073 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
6b0dd094 1074 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1075 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
6b0dd094 1076 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1077 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
6b0dd094 1078 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1079 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
6b0dd094 1080 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1081 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
6b0dd094 1082 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1083 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1084 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1085 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1086 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1087 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1088 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1089 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1090 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1091 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1092 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1093 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1094 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1095 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1096 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1097 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1098 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1099 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1100 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1101 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1102 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1103 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1104 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1105 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1106 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1107 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 1108 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1109 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 1110 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1111 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 1112 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1113 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 1114 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1115 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1116 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1117 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1118 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1119 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1120 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1121 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1122 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1123 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1124 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1125 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1126 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1127 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1128 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1129 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1130 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1131 0x0e000600, 0x0ff00f10,
1132 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1133 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1134 0x0e100600, 0x0ff00f10,
1135 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1136 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1137 0x0e200600, 0x0ff00f10,
1138 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1139 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1140 0x0e300600, 0x0ff00f10,
1141 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 1142
62f3b8c8 1143 /* VFP Fused multiply add instructions. */
6b0dd094 1144 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1145 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1146 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1147 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1148 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1149 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1150 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1151 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
6b0dd094 1152 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1153 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1154 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1155 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1156 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1157 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1158 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1159 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 1160
33399f07 1161 /* FP v5. */
6b0dd094 1162 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1163 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
6b0dd094 1164 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1165 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
6b0dd094 1166 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1167 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1168 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1169 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1170 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1171 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1172 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1173 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1174 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1175 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
6b0dd094 1176 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1177 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
6b0dd094 1178 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1179 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
6b0dd094 1180 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1181 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
6b0dd094 1182 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1183 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
6b0dd094 1184 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1185 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 1186
05413229 1187 /* Generic coprocessor instructions. */
6b0dd094
AV		 1188 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
1189 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
823d2571 1190 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
6b0dd094 1191 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
823d2571
TG		 1192 0x0c500000, 0x0ff00000,
1193 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
6b0dd094 1194 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1195 0x0e000000, 0x0f000010,
1196 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1197 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1198 0x0e10f010, 0x0f10f010,
1199 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1200 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1201 0x0e100010, 0x0f100010,
1202 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1203 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1204 0x0e000010, 0x0f100010,
1205 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1206 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571 1207 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 1208 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571 1209 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
2fbad815 1210
05413229 1211 /* V6 coprocessor instructions. */
6b0dd094 1212 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
823d2571
TG		 1213 0xfc500000, 0xfff00000,
1214 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
6b0dd094 1215 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
823d2571
TG		 1216 0xfc400000, 0xfff00000,
1217 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
8f06b2d8 1218
c28eeff2 1219 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
6b0dd094 1220 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1221 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1222 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1223 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1224 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1225 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1226 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1227 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1228 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1229 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1230 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1231 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1232 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1233 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
6b0dd094 1234 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1235 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
6b0dd094 1236 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1237 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
6b0dd094 1238 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1239 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
c28eeff2 1240
c604a79a 1241 /* Dot Product instructions in the space of coprocessor 13. */
6b0dd094 1242 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a 1243 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
6b0dd094 1244 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a
JW		 1245 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1246
dec41383 1247 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
6b0dd094 1248 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1249 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1250 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1251 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1252 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1253 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1254 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1255 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1256 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1257 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1258 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1259 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1260 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1261 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
6b0dd094 1262 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383
JW		 1263 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1264
05413229 1265 /* V5 coprocessor instructions. */
6b0dd094 1266 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571 1267 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 1268 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571 1269 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 1270 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1271 0xfe000000, 0xff000010,
1272 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1273 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1274 0xfe000010, 0xff100010,
1275 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1276 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1277 0xfe100010, 0xff100010,
1278 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1279
b0c11777
RL		 1280 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1281 cp_num: bit <11:8> == 0b1001.
1282 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
6b0dd094 1283 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1284 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
6b0dd094 1285 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1286 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
6b0dd094 1287 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1288 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
6b0dd094 1289 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1290 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
6b0dd094 1291 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1292 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 1293 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1294 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
6b0dd094 1295 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1296 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
6b0dd094 1297 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1298 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
6b0dd094 1299 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1300 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
6b0dd094 1301 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1302 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
6b0dd094 1303 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1304 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1305 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1306 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1307 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1308 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1309 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1310 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1311 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1312 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
6b0dd094 1313 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1314 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
6b0dd094 1315 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1316 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
6b0dd094 1317 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1318 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
6b0dd094 1319 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1320 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1321 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1322 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1323 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1324 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1325 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1326 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1327 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1328 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
6b0dd094 1329 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1330 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
6b0dd094 1331 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1332 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
6b0dd094 1333 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1334 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1335 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1336 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
6b0dd094 1337 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1338 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1339 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1340 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1341 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1342 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1343 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1344 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
6b0dd094 1345 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1346 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
6b0dd094 1347 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1348 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
6b0dd094 1349 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1350 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
6b0dd094 1351 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777
RL		 1352 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1353
49e8a725 1354 /* ARMv8.3 javascript conversion instruction. */
6b0dd094 1355 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
49e8a725
SN		 1356 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1357
6b0dd094 1358 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 1359};
1360
16980d0b
JB		 1361/* Neon opcode table: This does not encode the top byte -- that is
1362 checked by the print_insn_neon routine, as it depends on whether we are
1363 doing thumb32 or arm32 disassembly. */
1364
1365/* print_insn_neon recognizes the following format control codes:
1366
1367 %% %
1368
c22aaad1 1369 %c print condition code
e2efe87d
MGD		 1370 %u print condition code (unconditional in ARM mode,
1371 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 1372 %A print v{st,ld}[1234] operands
1373 %B print v{st,ld}[1234] any one operands
1374 %C print v{st,ld}[1234] single->all operands
1375 %D print scalar
1376 %E print vmov, vmvn, vorr, vbic encoded constant
1377 %F print vtbl,vtbx register list
1378
1379 %<bitfield>r print as an ARM register
1380 %<bitfield>d print the bitfield in decimal
1381 %<bitfield>e print the 2^N - bitfield in decimal
1382 %<bitfield>D print as a NEON D register
1383 %<bitfield>Q print as a NEON Q register
1384 %<bitfield>R print as a NEON D or Q register
1385 %<bitfield>Sn print byte scaled width limited by n
1386 %<bitfield>Tn print short scaled width limited by n
1387 %<bitfield>Un print long scaled width limited by n
43e65147 1388
16980d0b
JB		 1389 %<bitfield>'c print specified char iff bitfield is all ones
1390 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1391 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1392
1393static const struct opcode32 neon_opcodes[] =
1394{
fe56b6ce 1395 /* Extract. */
823d2571
TG		 1396 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1397 0xf2b00840, 0xffb00850,
1398 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1399 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1400 0xf2b00000, 0xffb00810,
1401 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 1402
9743db03
AV		 1403 /* Data transfer between ARM and NEON registers. */
1404 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1405 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1406 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1407 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1408 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1409 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1410 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1411 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1412 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1413 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1414 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1415 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1416
fe56b6ce 1417 /* Move data element to all lanes. */
823d2571
TG		 1418 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1419 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1420 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1421 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1422 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1423 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 1424
fe56b6ce 1425 /* Table lookup. */
823d2571
TG		 1426 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1427 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1428 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1429 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1430
8e79c3df 1431 /* Half-precision conversions. */
823d2571
TG		 1432 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1433 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1434 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1435 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1436
1437 /* NEON fused multiply add instructions. */
823d2571 1438 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1439 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1440 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1441 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1442 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1443 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1444 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1445 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1446
fe56b6ce 1447 /* Two registers, miscellaneous. */
823d2571
TG		 1448 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1449 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1450 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1451 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1452 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1453 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1454 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1455 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1456 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1457 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1458 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1459 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1460 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1461 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1462 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1463 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1464 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1465 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1466 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1467 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1468 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1469 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1470 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1471 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1473 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1474 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1475 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1477 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1478 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1479 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1481 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1482 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1483 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1484 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1485 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1487 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1489 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1490 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1491 0xf3b20300, 0xffb30fd0,
1492 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1494 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1495 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1496 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1498 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1499 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1500 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1502 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1503 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1504 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1511 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1512 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1515 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1517 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1518 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1519 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1520 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1521 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1522 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1523 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1524 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1525 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1526 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1527 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1528 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1530 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1531 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1532 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1533 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1534 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1535 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1536 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1537 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1538 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1539 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301 1540 0xf3bb0600, 0xffbf0e10,
823d2571 1541 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1542 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1543 0xf3b70600, 0xffbf0e10,
1544 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
16980d0b 1545
fe56b6ce 1546 /* Three registers of the same length. */
823d2571
TG		 1547 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1548 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1549 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1550 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1551 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1552 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1553 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1554 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1555 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1556 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1557 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1558 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1559 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1560 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1561 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1562 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1563 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1564 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1565 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1566 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1567 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1568 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1569 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1570 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1571 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1572 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1573 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1574 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1576 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1577 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1578 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1579 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1580 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1581 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1582 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1583 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1584 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1585 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1586 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1587 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1588 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1589 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1590 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1591 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1592 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1594 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1595 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1596 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1597 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1598 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1599 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1600 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1601 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1602 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1603 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1604 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1605 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1606 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1607 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1608 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1609 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1610 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1611 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1612 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1613 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1614 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1615 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1616 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1618 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1619 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1620 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1621 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1622 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1623 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1624 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1625 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1626 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1627 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1628 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1630 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1631 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1632 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1633 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1634 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1635 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1636 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1638 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1639 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1640 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1642 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1643 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1644 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1646 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1647 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1648 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1650 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1651 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1652 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1653 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1654 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1655 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1656 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1658 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1659 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1660 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1661 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1662 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1663 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1664 0xf2000b00, 0xff800f10,
1665 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1666 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1667 0xf2000b10, 0xff800f10,
1668 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1669 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1670 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1671 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1672 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1673 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1674 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1675 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1676 0xf3000b00, 0xff800f10,
1677 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1678 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1679 0xf2000000, 0xfe800f10,
1680 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1681 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1682 0xf2000010, 0xfe800f10,
1683 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1685 0xf2000100, 0xfe800f10,
1686 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1687 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1688 0xf2000200, 0xfe800f10,
1689 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1691 0xf2000210, 0xfe800f10,
1692 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1693 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1694 0xf2000300, 0xfe800f10,
1695 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1696 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1697 0xf2000310, 0xfe800f10,
1698 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1699 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1700 0xf2000400, 0xfe800f10,
1701 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1702 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1703 0xf2000410, 0xfe800f10,
1704 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1705 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1706 0xf2000500, 0xfe800f10,
1707 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1708 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1709 0xf2000510, 0xfe800f10,
1710 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1711 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1712 0xf2000600, 0xfe800f10,
1713 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1714 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1715 0xf2000610, 0xfe800f10,
1716 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1717 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1718 0xf2000700, 0xfe800f10,
1719 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1720 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1721 0xf2000710, 0xfe800f10,
1722 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1723 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1724 0xf2000910, 0xfe800f10,
1725 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1726 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1727 0xf2000a00, 0xfe800f10,
1728 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1729 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1730 0xf2000a10, 0xfe800f10,
1731 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1732 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1733 0xf3000b10, 0xff800f10,
1734 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1735 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1736 0xf3000c10, 0xff800f10,
1737 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1738
fe56b6ce 1739 /* One register and an immediate value. */
823d2571
TG		 1740 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1741 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1742 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1743 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1744 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1745 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1746 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1747 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1748 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1749 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1750 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1751 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1753 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1754 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1755 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1756 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1757 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1758 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1759 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1760 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1761 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1762 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1763 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1764 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1765 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1766
fe56b6ce 1767 /* Two registers and a shift amount. */
823d2571
TG		 1768 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1769 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1770 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1771 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1772 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1773 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1774 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1775 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1776 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1777 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1778 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1779 0xf2880950, 0xfeb80fd0,
1780 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1781 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1782 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1783 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1784 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1785 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1786 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1787 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1788 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1789 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1790 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1791 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1792 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1793 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1794 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1795 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1796 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1797 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1798 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1799 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1800 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1801 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1802 0xf2900950, 0xfeb00fd0,
1803 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1804 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1805 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1806 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1807 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1808 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1809 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1810 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1811 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1812 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1813 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1814 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1815 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1816 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1817 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1818 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1819 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1820 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1821 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1822 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1823 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1824 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1825 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1826 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1827 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1828 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1829 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1830 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1831 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1832 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1833 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1834 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1835 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1836 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1837 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1838 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1839 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1840 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1841 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1842 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1843 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1844 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1845 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1846 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1847 0xf2a00950, 0xfea00fd0,
1848 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1849 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1850 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1851 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1852 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1853 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1854 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1855 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1856 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1857 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1858 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1859 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1860 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1861 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1862 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1863 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1864 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1865 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1866 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1867 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1868 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1869 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1870 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1871 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1872 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1873 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1874 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1875 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1876 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1877 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1878 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1879 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1880 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1881 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1882 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1883 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1884 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1885 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1886 0xf2a00e10, 0xfea00e90,
1887 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
cc933301
JW		 1888 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1889 0xf2a00c10, 0xfea00e90,
1890 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 1891
fe56b6ce 1892 /* Three registers of different lengths. */
823d2571
TG		 1893 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1894 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1895 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1896 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1897 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1898 0xf2800400, 0xff800f50,
1899 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1900 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1901 0xf2800600, 0xff800f50,
1902 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1903 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1904 0xf2800900, 0xff800f50,
1905 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1906 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1907 0xf2800b00, 0xff800f50,
1908 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1909 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1910 0xf2800d00, 0xff800f50,
1911 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1912 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1913 0xf3800400, 0xff800f50,
1914 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1915 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1916 0xf3800600, 0xff800f50,
1917 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1918 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1919 0xf2800000, 0xfe800f50,
1920 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1921 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1922 0xf2800100, 0xfe800f50,
1923 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1924 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1925 0xf2800200, 0xfe800f50,
1926 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1927 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1928 0xf2800300, 0xfe800f50,
1929 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1930 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1931 0xf2800500, 0xfe800f50,
1932 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1933 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1934 0xf2800700, 0xfe800f50,
1935 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1936 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1937 0xf2800800, 0xfe800f50,
1938 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1939 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1940 0xf2800a00, 0xfe800f50,
1941 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1942 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1943 0xf2800c00, 0xfe800f50,
1944 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 1945
fe56b6ce 1946 /* Two registers and a scalar. */
823d2571
TG		 1947 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1948 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1949 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1950 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1951 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1952 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1953 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1954 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1955 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1956 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1957 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1958 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1959 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1960 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1961 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1962 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1963 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1964 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1965 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1966 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1967 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1968 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1969 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1970 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1971 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1972 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1973 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1974 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1975 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1976 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1977 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1978 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1979 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1980 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1981 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1982 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1983 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1984 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1985 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1986 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1987 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1988 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1989 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1990 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1991 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1992 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1993 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1994 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1995 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1996 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1997 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1998 0xf2800240, 0xfe800f50,
1999 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2000 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2001 0xf2800640, 0xfe800f50,
2002 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2003 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2004 0xf2800a40, 0xfe800f50,
2005 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 2006 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2007 0xf2800e40, 0xff800f50,
2008 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2009 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2010 0xf2800f40, 0xff800f50,
2011 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2012 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2013 0xf3800e40, 0xff800f50,
2014 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2015 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2016 0xf3800f40, 0xff800f50,
2017 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
2018 },
16980d0b 2019
fe56b6ce 2020 /* Element and structure load/store. */
823d2571
TG		 2021 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2022 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
2023 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2024 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
2025 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2026 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
2027 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2028 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
2029 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2030 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
2031 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2032 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2033 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2034 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2035 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2036 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2037 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2038 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2039 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2040 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2041 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2042 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2043 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2044 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2045 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2046 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2047 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2048 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2049 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2050 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
2051 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2052 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
2053 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2054 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
2055 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2056 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
2057 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2058 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
2059
2060 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 2061};
2062
73cd51e5
AV		 2063/* mve opcode table. */
2064
2065/* print_insn_mve recognizes the following format control codes:
2066
2067 %% %
2068
ef1576a1
AV		 2069 %a print '+' or '-' or imm offset in vldr[bhwd] and
2070 vstr[bhwd]
9743db03 2071 %c print condition code
aef6d006
AV		 2072 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
2073 %u print 'U' (unsigned) or 'S' for various mve instructions
143275ea 2074 %i print MVE predicate(s) for vpt and vpst
23d00a41 2075 %j print a 5-bit immediate from hw2[14:12,7:6]
08132bdd 2076 %k print 48 if the 7th position bit is set else print 64.
bf0b396d 2077 %m print rounding mode for vcvt and vrint
143275ea 2078 %n print vector comparison code for predicated instruction
bf0b396d 2079 %s print size for various vcvt instructions
143275ea
AV		 2080 %v print vector predicate for instruction in predicated
2081 block
ef1576a1 2082 %o print offset scaled for vldr[hwd] and vstr[hwd]
04d54ace
AV		 2083 %w print writeback mode for MVE v{st,ld}[24]
2084 %B print v{st,ld}[24] any one operands
c507f10b
AV		 2085 %E print vmov, vmvn, vorr, vbic encoded constant
2086 %N print generic index for vmov
14925797 2087 %T print bottom ('b') or top ('t') of source register
d3b63143 2088 %X print exchange field in vmla* instructions
04d54ace 2089
9743db03 2090 %<bitfield>r print as an ARM register
04d54ace 2091 %<bitfield>d print the bitfield in decimal
d3b63143 2092 %<bitfield>A print accumulate or not
e39c1607
SD		 2093 %<bitfield>c print bitfield as a condition code
2094 %<bitfield>C print bitfield as an inverted condition code
143275ea 2095 %<bitfield>Q print as a MVE Q register
c507f10b 2096 %<bitfield>F print as a MVE S register
143275ea
AV		 2097 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
2098 UNPREDICTABLE
23d00a41
SD		 2099
2100 %<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE
143275ea 2101 %<bitfield>s print size for vector predicate & non VMOV instructions
66dcaa5d 2102 %<bitfield>I print carry flag or not
ef1576a1 2103 %<bitfield>i print immediate for vstr/vldr reg +/- imm
1c8f2df8 2104 %<bitfield>h print high half of 64-bit destination reg
bf0b396d 2105 %<bitfield>k print immediate for vector conversion instruction
1c8f2df8 2106 %<bitfield>l print low half of 64-bit destination reg
897b9bbc 2107 %<bitfield>o print rotate value for vcmul
1c8f2df8 2108 %<bitfield>u print immediate value for vddup/vdwdup
c507f10b 2109 %<bitfield>x print the bitfield in hex.
1c8f2df8 2110 */
73cd51e5
AV		 2111
2112static const struct mopcode32 mve_opcodes[] =
2113{
143275ea
AV		 2114 /* MVE. */
2115
2116 {ARM_FEATURE_COPROC (FPU_MVE),
2117 MVE_VPST,
2118 0xfe310f4d, 0xffbf1fff,
2119 "vpst%i"
2120 },
2121
2122 /* Floating point VPT T1. */
2123 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2124 MVE_VPT_FP_T1,
2125 0xee310f00, 0xefb10f50,
2126 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2127 /* Floating point VPT T2. */
2128 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2129 MVE_VPT_FP_T2,
2130 0xee310f40, 0xefb10f50,
2131 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2132
2133 /* Vector VPT T1. */
2134 {ARM_FEATURE_COPROC (FPU_MVE),
2135 MVE_VPT_VEC_T1,
2136 0xfe010f00, 0xff811f51,
2137 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2138 /* Vector VPT T2. */
2139 {ARM_FEATURE_COPROC (FPU_MVE),
2140 MVE_VPT_VEC_T2,
2141 0xfe010f01, 0xff811f51,
2142 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2143 /* Vector VPT T3. */
2144 {ARM_FEATURE_COPROC (FPU_MVE),
2145 MVE_VPT_VEC_T3,
2146 0xfe011f00, 0xff811f50,
2147 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2148 /* Vector VPT T4. */
2149 {ARM_FEATURE_COPROC (FPU_MVE),
2150 MVE_VPT_VEC_T4,
2151 0xfe010f40, 0xff811f70,
2152 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2153 /* Vector VPT T5. */
2154 {ARM_FEATURE_COPROC (FPU_MVE),
2155 MVE_VPT_VEC_T5,
2156 0xfe010f60, 0xff811f70,
2157 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2158 /* Vector VPT T6. */
2159 {ARM_FEATURE_COPROC (FPU_MVE),
2160 MVE_VPT_VEC_T6,
2161 0xfe011f40, 0xff811f50,
2162 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2163
c507f10b
AV		 2164 /* Vector VBIC immediate. */
2165 {ARM_FEATURE_COPROC (FPU_MVE),
2166 MVE_VBIC_IMM,
2167 0xef800070, 0xefb81070,
2168 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2169
2170 /* Vector VBIC register. */
2171 {ARM_FEATURE_COPROC (FPU_MVE),
2172 MVE_VBIC_REG,
2173 0xef100150, 0xffb11f51,
2174 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2175
66dcaa5d
AV		 2176 /* Vector VABAV. */
2177 {ARM_FEATURE_COPROC (FPU_MVE),
2178 MVE_VABAV,
2179 0xee800f01, 0xefc10f51,
2180 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2181
2182 /* Vector VABD floating point. */
2183 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2184 MVE_VABD_FP,
2185 0xff200d40, 0xffa11f51,
2186 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2187
2188 /* Vector VABD. */
2189 {ARM_FEATURE_COPROC (FPU_MVE),
2190 MVE_VABD_VEC,
2191 0xef000740, 0xef811f51,
2192 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2193
2194 /* Vector VABS floating point. */
2195 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2196 MVE_VABS_FP,
2197 0xFFB10740, 0xFFB31FD1,
2198 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2199 /* Vector VABS. */
2200 {ARM_FEATURE_COPROC (FPU_MVE),
2201 MVE_VABS_VEC,
2202 0xffb10340, 0xffb31fd1,
2203 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2204
2205 /* Vector VADD floating point T1. */
2206 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2207 MVE_VADD_FP_T1,
2208 0xef000d40, 0xffa11f51,
2209 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2210 /* Vector VADD floating point T2. */
2211 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2212 MVE_VADD_FP_T2,
2213 0xee300f40, 0xefb11f70,
2214 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2215 /* Vector VADD T1. */
2216 {ARM_FEATURE_COPROC (FPU_MVE),
2217 MVE_VADD_VEC_T1,
2218 0xef000840, 0xff811f51,
2219 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2220 /* Vector VADD T2. */
2221 {ARM_FEATURE_COPROC (FPU_MVE),
2222 MVE_VADD_VEC_T2,
2223 0xee010f40, 0xff811f70,
2224 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2225
d3b63143
AV		 2226 /* Vector VADDLV. */
2227 {ARM_FEATURE_COPROC (FPU_MVE),
2228 MVE_VADDLV,
2229 0xee890f00, 0xef8f1fd1,
2230 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2231
2232 /* Vector VADDV. */
2233 {ARM_FEATURE_COPROC (FPU_MVE),
2234 MVE_VADDV,
2235 0xeef10f00, 0xeff31fd1,
2236 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2237
66dcaa5d
AV		 2238 /* Vector VADC. */
2239 {ARM_FEATURE_COPROC (FPU_MVE),
2240 MVE_VADC,
2241 0xee300f00, 0xffb10f51,
2242 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2243
e523f101
AV		 2244 /* Vector VAND. */
2245 {ARM_FEATURE_COPROC (FPU_MVE),
2246 MVE_VAND,
2247 0xef000150, 0xffb11f51,
2248 "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2249
2250 /* Vector VBRSR register. */
2251 {ARM_FEATURE_COPROC (FPU_MVE),
2252 MVE_VBRSR,
2253 0xfe011e60, 0xff811f70,
2254 "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2255
897b9bbc
AV		 2256 /* Vector VCADD floating point. */
2257 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2258 MVE_VCADD_FP,
2259 0xfc800840, 0xfea11f51,
2260 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2261
2262 /* Vector VCADD. */
2263 {ARM_FEATURE_COPROC (FPU_MVE),
2264 MVE_VCADD_VEC,
2265 0xfe000f00, 0xff810f51,
2266 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2267
e523f101
AV		 2268 /* Vector VCLS. */
2269 {ARM_FEATURE_COPROC (FPU_MVE),
2270 MVE_VCLS,
2271 0xffb00440, 0xffb31fd1,
2272 "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2273
2274 /* Vector VCLZ. */
2275 {ARM_FEATURE_COPROC (FPU_MVE),
2276 MVE_VCLZ,
2277 0xffb004c0, 0xffb31fd1,
2278 "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2279
897b9bbc
AV		 2280 /* Vector VCMLA. */
2281 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2282 MVE_VCMLA_FP,
2283 0xfc200840, 0xfe211f51,
2284 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2285
143275ea
AV		 2286 /* Vector VCMP floating point T1. */
2287 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2288 MVE_VCMP_FP_T1,
2289 0xee310f00, 0xeff1ef50,
2290 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2291
2292 /* Vector VCMP floating point T2. */
2293 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2294 MVE_VCMP_FP_T2,
2295 0xee310f40, 0xeff1ef50,
2296 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2297
2298 /* Vector VCMP T1. */
2299 {ARM_FEATURE_COPROC (FPU_MVE),
2300 MVE_VCMP_VEC_T1,
2301 0xfe010f00, 0xffc1ff51,
2302 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2303 /* Vector VCMP T2. */
2304 {ARM_FEATURE_COPROC (FPU_MVE),
2305 MVE_VCMP_VEC_T2,
2306 0xfe010f01, 0xffc1ff51,
2307 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2308 /* Vector VCMP T3. */
2309 {ARM_FEATURE_COPROC (FPU_MVE),
2310 MVE_VCMP_VEC_T3,
2311 0xfe011f00, 0xffc1ff50,
2312 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2313 /* Vector VCMP T4. */
2314 {ARM_FEATURE_COPROC (FPU_MVE),
2315 MVE_VCMP_VEC_T4,
2316 0xfe010f40, 0xffc1ff70,
2317 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2318 /* Vector VCMP T5. */
2319 {ARM_FEATURE_COPROC (FPU_MVE),
2320 MVE_VCMP_VEC_T5,
2321 0xfe010f60, 0xffc1ff70,
2322 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2323 /* Vector VCMP T6. */
2324 {ARM_FEATURE_COPROC (FPU_MVE),
2325 MVE_VCMP_VEC_T6,
2326 0xfe011f40, 0xffc1ff50,
2327 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2328
9743db03
AV		 2329 /* Vector VDUP. */
2330 {ARM_FEATURE_COPROC (FPU_MVE),
2331 MVE_VDUP,
2332 0xeea00b10, 0xffb10f5f,
2333 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2334
2335 /* Vector VEOR. */
2336 {ARM_FEATURE_COPROC (FPU_MVE),
2337 MVE_VEOR,
2338 0xff000150, 0xffd11f51,
2339 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2340
2341 /* Vector VFMA, vector * scalar. */
2342 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2343 MVE_VFMA_FP_SCALAR,
2344 0xee310e40, 0xefb11f70,
2345 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2346
2347 /* Vector VFMA floating point. */
2348 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2349 MVE_VFMA_FP,
2350 0xef000c50, 0xffa11f51,
2351 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2352
2353 /* Vector VFMS floating point. */
2354 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2355 MVE_VFMS_FP,
2356 0xef200c50, 0xffa11f51,
2357 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2358
2359 /* Vector VFMAS, vector * scalar. */
2360 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2361 MVE_VFMAS_FP_SCALAR,
2362 0xee311e40, 0xefb11f70,
2363 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2364
2365 /* Vector VHADD T1. */
2366 {ARM_FEATURE_COPROC (FPU_MVE),
2367 MVE_VHADD_T1,
2368 0xef000040, 0xef811f51,
2369 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2370
2371 /* Vector VHADD T2. */
2372 {ARM_FEATURE_COPROC (FPU_MVE),
2373 MVE_VHADD_T2,
2374 0xee000f40, 0xef811f70,
2375 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2376
2377 /* Vector VHSUB T1. */
2378 {ARM_FEATURE_COPROC (FPU_MVE),
2379 MVE_VHSUB_T1,
2380 0xef000240, 0xef811f51,
2381 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2382
2383 /* Vector VHSUB T2. */
2384 {ARM_FEATURE_COPROC (FPU_MVE),
2385 MVE_VHSUB_T2,
2386 0xee001f40, 0xef811f70,
2387 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2388
897b9bbc
AV		 2389 /* Vector VCMUL. */
2390 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2391 MVE_VCMUL_FP,
2392 0xee300e00, 0xefb10f50,
2393 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2394
e523f101
AV		 2395 /* Vector VCTP. */
2396 {ARM_FEATURE_COPROC (FPU_MVE),
2397 MVE_VCTP,
2398 0xf000e801, 0xffc0ffff,
2399 "vctp%v.%20-21s\t%16-19r"},
2400
9743db03
AV		 2401 /* Vector VDUP. */
2402 {ARM_FEATURE_COPROC (FPU_MVE),
2403 MVE_VDUP,
2404 0xeea00b10, 0xffb10f5f,
2405 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2406
2407 /* Vector VRHADD. */
2408 {ARM_FEATURE_COPROC (FPU_MVE),
2409 MVE_VRHADD,
2410 0xef000140, 0xef811f51,
2411 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2412
bf0b396d
AV		 2413 /* Vector VCVT. */
2414 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2415 MVE_VCVT_FP_FIX_VEC,
2416 0xef800c50, 0xef801cd1,
2417 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2418
2419 /* Vector VCVT. */
2420 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2421 MVE_VCVT_BETWEEN_FP_INT,
2422 0xffb30640, 0xffb31e51,
2423 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2424
2425 /* Vector VCVT between single and half-precision float, bottom half. */
2426 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2427 MVE_VCVT_FP_HALF_FP,
2428 0xee3f0e01, 0xefbf1fd1,
2429 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2430
2431 /* Vector VCVT between single and half-precision float, top half. */
2432 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2433 MVE_VCVT_FP_HALF_FP,
2434 0xee3f1e01, 0xefbf1fd1,
2435 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2436
2437 /* Vector VCVT. */
2438 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2439 MVE_VCVT_FROM_FP_TO_INT,
2440 0xffb30040, 0xffb31c51,
2441 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2442
1c8f2df8
AV		 2443 /* Vector VDDUP. */
2444 {ARM_FEATURE_COPROC (FPU_MVE),
2445 MVE_VDDUP,
2446 0xee011f6e, 0xff811f7e,
2447 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2448
2449 /* Vector VDWDUP. */
2450 {ARM_FEATURE_COPROC (FPU_MVE),
2451 MVE_VDWDUP,
2452 0xee011f60, 0xff811f70,
2453 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2454
897b9bbc
AV		 2455 /* Vector VHCADD. */
2456 {ARM_FEATURE_COPROC (FPU_MVE),
2457 MVE_VHCADD,
2458 0xee000f00, 0xff810f51,
2459 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2460
1c8f2df8
AV		 2461 /* Vector VIWDUP. */
2462 {ARM_FEATURE_COPROC (FPU_MVE),
2463 MVE_VIWDUP,
2464 0xee010f60, 0xff811f70,
2465 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2466
2467 /* Vector VIDUP. */
2468 {ARM_FEATURE_COPROC (FPU_MVE),
2469 MVE_VIDUP,
2470 0xee010f6e, 0xff811f7e,
2471 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2472
04d54ace
AV		 2473 /* Vector VLD2. */
2474 {ARM_FEATURE_COPROC (FPU_MVE),
2475 MVE_VLD2,
2476 0xfc901e00, 0xff901e5f,
2477 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2478
2479 /* Vector VLD4. */
2480 {ARM_FEATURE_COPROC (FPU_MVE),
2481 MVE_VLD4,
2482 0xfc901e01, 0xff901e1f,
2483 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2484
ef1576a1
AV		 2485 /* Vector VLDRB gather load. */
2486 {ARM_FEATURE_COPROC (FPU_MVE),
2487 MVE_VLDRB_GATHER_T1,
2488 0xec900e00, 0xefb01e50,
2489 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2490
2491 /* Vector VLDRH gather load. */
2492 {ARM_FEATURE_COPROC (FPU_MVE),
2493 MVE_VLDRH_GATHER_T2,
2494 0xec900e10, 0xefb01e50,
2495 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2496
2497 /* Vector VLDRW gather load. */
2498 {ARM_FEATURE_COPROC (FPU_MVE),
2499 MVE_VLDRW_GATHER_T3,
2500 0xfc900f40, 0xffb01fd0,
2501 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2502
2503 /* Vector VLDRD gather load. */
2504 {ARM_FEATURE_COPROC (FPU_MVE),
2505 MVE_VLDRD_GATHER_T4,
2506 0xec900fd0, 0xefb01fd0,
2507 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2508
2509 /* Vector VLDRW gather load. */
2510 {ARM_FEATURE_COPROC (FPU_MVE),
2511 MVE_VLDRW_GATHER_T5,
2512 0xfd101e00, 0xff111f00,
2513 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2514
2515 /* Vector VLDRD gather load, variant T6. */
2516 {ARM_FEATURE_COPROC (FPU_MVE),
2517 MVE_VLDRD_GATHER_T6,
2518 0xfd101f00, 0xff111f00,
2519 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2520
aef6d006
AV		 2521 /* Vector VLDRB. */
2522 {ARM_FEATURE_COPROC (FPU_MVE),
2523 MVE_VLDRB_T1,
2524 0xec100e00, 0xee581e00,
2525 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2526
2527 /* Vector VLDRH. */
2528 {ARM_FEATURE_COPROC (FPU_MVE),
2529 MVE_VLDRH_T2,
2530 0xec180e00, 0xee581e00,
2531 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2532
2533 /* Vector VLDRB unsigned, variant T5. */
2534 {ARM_FEATURE_COPROC (FPU_MVE),
2535 MVE_VLDRB_T5,
2536 0xec101e00, 0xfe101f80,
2537 "vldrb%v.u8\t%13-15,22Q, %d"},
2538
2539 /* Vector VLDRH unsigned, variant T6. */
2540 {ARM_FEATURE_COPROC (FPU_MVE),
2541 MVE_VLDRH_T6,
2542 0xec101e80, 0xfe101f80,
2543 "vldrh%v.u16\t%13-15,22Q, %d"},
2544
2545 /* Vector VLDRW unsigned, variant T7. */
2546 {ARM_FEATURE_COPROC (FPU_MVE),
2547 MVE_VLDRW_T7,
2548 0xec101f00, 0xfe101f80,
2549 "vldrw%v.u32\t%13-15,22Q, %d"},
2550
56858bea
AV		 2551 /* Vector VMAX. */
2552 {ARM_FEATURE_COPROC (FPU_MVE),
2553 MVE_VMAX,
2554 0xef000640, 0xef811f51,
2555 "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2556
2557 /* Vector VMAXA. */
2558 {ARM_FEATURE_COPROC (FPU_MVE),
2559 MVE_VMAXA,
2560 0xee330e81, 0xffb31fd1,
2561 "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2562
2563 /* Vector VMAXNM floating point. */
2564 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2565 MVE_VMAXNM_FP,
2566 0xff000f50, 0xffa11f51,
2567 "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2568
2569 /* Vector VMAXNMA floating point. */
2570 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2571 MVE_VMAXNMA_FP,
2572 0xee3f0e81, 0xefbf1fd1,
2573 "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2574
2575 /* Vector VMAXNMV floating point. */
2576 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2577 MVE_VMAXNMV_FP,
2578 0xeeee0f00, 0xefff0fd1,
2579 "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2580
2581 /* Vector VMAXNMAV floating point. */
2582 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2583 MVE_VMAXNMAV_FP,
2584 0xeeec0f00, 0xefff0fd1,
2585 "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2586
2587 /* Vector VMAXV. */
2588 {ARM_FEATURE_COPROC (FPU_MVE),
2589 MVE_VMAXV,
2590 0xeee20f00, 0xeff30fd1,
2591 "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2592
2593 /* Vector VMAXAV. */
2594 {ARM_FEATURE_COPROC (FPU_MVE),
2595 MVE_VMAXAV,
2596 0xeee00f00, 0xfff30fd1,
2597 "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2598
2599 /* Vector VMIN. */
2600 {ARM_FEATURE_COPROC (FPU_MVE),
2601 MVE_VMIN,
2602 0xef000650, 0xef811f51,
2603 "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2604
2605 /* Vector VMINA. */
2606 {ARM_FEATURE_COPROC (FPU_MVE),
2607 MVE_VMINA,
2608 0xee331e81, 0xffb31fd1,
2609 "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2610
2611 /* Vector VMINNM floating point. */
2612 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2613 MVE_VMINNM_FP,
2614 0xff200f50, 0xffa11f51,
2615 "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2616
2617 /* Vector VMINNMA floating point. */
2618 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2619 MVE_VMINNMA_FP,
2620 0xee3f1e81, 0xefbf1fd1,
2621 "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2622
2623 /* Vector VMINNMV floating point. */
2624 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2625 MVE_VMINNMV_FP,
2626 0xeeee0f80, 0xefff0fd1,
2627 "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2628
2629 /* Vector VMINNMAV floating point. */
2630 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2631 MVE_VMINNMAV_FP,
2632 0xeeec0f80, 0xefff0fd1,
2633 "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2634
2635 /* Vector VMINV. */
2636 {ARM_FEATURE_COPROC (FPU_MVE),
2637 MVE_VMINV,
2638 0xeee20f80, 0xeff30fd1,
2639 "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2640
2641 /* Vector VMINAV. */
2642 {ARM_FEATURE_COPROC (FPU_MVE),
2643 MVE_VMINAV,
2644 0xeee00f80, 0xfff30fd1,
2645 "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2646
2647 /* Vector VMLA. */
2648 {ARM_FEATURE_COPROC (FPU_MVE),
2649 MVE_VMLA,
2650 0xee010e40, 0xef811f70,
2651 "vmla%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2652
d3b63143
AV		 2653 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2654 opcode aliasing. */
2655 {ARM_FEATURE_COPROC (FPU_MVE),
2656 MVE_VMLALDAV,
2657 0xee801e00, 0xef801f51,
2658 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2659
2660 {ARM_FEATURE_COPROC (FPU_MVE),
2661 MVE_VMLALDAV,
2662 0xee800e00, 0xef801f51,
2663 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2664
2665 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2666 {ARM_FEATURE_COPROC (FPU_MVE),
2667 MVE_VMLADAV_T1,
2668 0xeef00e00, 0xeff01f51,
2669 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2670
2671 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2672 {ARM_FEATURE_COPROC (FPU_MVE),
2673 MVE_VMLADAV_T2,
2674 0xeef00f00, 0xeff11f51,
2675 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2676
2677 /* Vector VMLADAV T1 variant. */
2678 {ARM_FEATURE_COPROC (FPU_MVE),
2679 MVE_VMLADAV_T1,
2680 0xeef01e00, 0xeff01f51,
2681 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2682
2683 /* Vector VMLADAV T2 variant. */
2684 {ARM_FEATURE_COPROC (FPU_MVE),
2685 MVE_VMLADAV_T2,
2686 0xeef01f00, 0xeff11f51,
2687 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2688
2689 /* Vector VMLAS. */
2690 {ARM_FEATURE_COPROC (FPU_MVE),
2691 MVE_VMLAS,
2692 0xee011e40, 0xef811f70,
2693 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2694
2695 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2696 opcode aliasing. */
2697 {ARM_FEATURE_COPROC (FPU_MVE),
2698 MVE_VRMLSLDAVH,
2699 0xfe800e01, 0xff810f51,
2700 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2701
2702 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2703 opcdoe aliasing. */
2704 {ARM_FEATURE_COPROC (FPU_MVE),
2705 MVE_VMLSLDAV,
2706 0xee800e01, 0xff800f51,
2707 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2708
2709 /* Vector VMLSDAV T1 Variant. */
2710 {ARM_FEATURE_COPROC (FPU_MVE),
2711 MVE_VMLSDAV_T1,
2712 0xeef00e01, 0xfff00f51,
2713 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2714
2715 /* Vector VMLSDAV T2 Variant. */
2716 {ARM_FEATURE_COPROC (FPU_MVE),
2717 MVE_VMLSDAV_T2,
2718 0xfef00e01, 0xfff10f51,
2719 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2720
c507f10b
AV		 2721 /* Vector VMOV between gpr and half precision register, op == 0. */
2722 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2723 MVE_VMOV_HFP_TO_GP,
2724 0xee000910, 0xfff00f7f,
2725 "vmov.f16\t%7,16-19F, %12-15r"},
2726
2727 /* Vector VMOV between gpr and half precision register, op == 1. */
2728 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2729 MVE_VMOV_HFP_TO_GP,
2730 0xee100910, 0xfff00f7f,
2731 "vmov.f16\t%12-15r, %7,16-19F"},
2732
2733 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2734 MVE_VMOV_GP_TO_VEC_LANE,
2735 0xee000b10, 0xff900f1f,
2736 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2737
2738 /* Vector VORR immediate to vector.
2739 NOTE: MVE_VORR_IMM must appear in the table
2740 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2741 {ARM_FEATURE_COPROC (FPU_MVE),
2742 MVE_VORR_IMM,
2743 0xef800050, 0xefb810f0,
2744 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2745
ed63aa17
AV		 2746 /* Vector VQSHL T2 Variant.
2747 NOTE: MVE_VQSHL_T2 must appear in the table before
2748 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2749 {ARM_FEATURE_COPROC (FPU_MVE),
2750 MVE_VQSHL_T2,
2751 0xef800750, 0xef801fd1,
2752 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2753
2754 /* Vector VQSHLU T3 Variant
2755 NOTE: MVE_VQSHL_T2 must appear in the table before
2756 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2757
2758 {ARM_FEATURE_COPROC (FPU_MVE),
2759 MVE_VQSHLU_T3,
2760 0xff800650, 0xff801fd1,
2761 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2762
2763 /* Vector VRSHR
2764 NOTE: MVE_VRSHR must appear in the table before
2765 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2766 {ARM_FEATURE_COPROC (FPU_MVE),
2767 MVE_VRSHR,
2768 0xef800250, 0xef801fd1,
2769 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2770
2771 /* Vector VSHL.
2772 NOTE: MVE_VSHL must appear in the table before
2773 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2774 {ARM_FEATURE_COPROC (FPU_MVE),
2775 MVE_VSHL_T1,
2776 0xef800550, 0xff801fd1,
2777 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2778
2779 /* Vector VSHR
2780 NOTE: MVE_VSHR must appear in the table before
2781 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2782 {ARM_FEATURE_COPROC (FPU_MVE),
2783 MVE_VSHR,
2784 0xef800050, 0xef801fd1,
2785 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2786
2787 /* Vector VSLI
2788 NOTE: MVE_VSLI must appear in the table before
2789 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2790 {ARM_FEATURE_COPROC (FPU_MVE),
2791 MVE_VSLI,
2792 0xff800550, 0xff801fd1,
2793 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2794
2795 /* Vector VSRI
2796 NOTE: MVE_VSRI must appear in the table before
2797 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2798 {ARM_FEATURE_COPROC (FPU_MVE),
2799 MVE_VSRI,
2800 0xff800450, 0xff801fd1,
2801 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2802
c507f10b
AV		 2803 /* Vector VMOV immediate to vector,
2804 cmode == 11x1 -> VMVN which is UNDEFINED
2805 for such a cmode. */
2806 {ARM_FEATURE_COPROC (FPU_MVE),
2807 MVE_VMVN_IMM, 0xef800d50, 0xefb81dd0, UNDEFINED_INSTRUCTION},
2808
2809 /* Vector VMOV immediate to vector. */
2810 {ARM_FEATURE_COPROC (FPU_MVE),
2811 MVE_VMOV_IMM_TO_VEC,
2812 0xef800050, 0xefb810d0,
2813 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2814
2815 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2816 {ARM_FEATURE_COPROC (FPU_MVE),
2817 MVE_VMOV2_VEC_LANE_TO_GP,
2818 0xec000f00, 0xffb01ff0,
2819 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2820
2821 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2822 {ARM_FEATURE_COPROC (FPU_MVE),
2823 MVE_VMOV2_VEC_LANE_TO_GP,
2824 0xec000f10, 0xffb01ff0,
2825 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2826
2827 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2828 {ARM_FEATURE_COPROC (FPU_MVE),
2829 MVE_VMOV2_GP_TO_VEC_LANE,
2830 0xec100f00, 0xffb01ff0,
2831 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2832
2833 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2834 {ARM_FEATURE_COPROC (FPU_MVE),
2835 MVE_VMOV2_GP_TO_VEC_LANE,
2836 0xec100f10, 0xffb01ff0,
2837 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2838
2839 /* Vector VMOV Vector lane to gpr. */
2840 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2841 MVE_VMOV_VEC_LANE_TO_GP,
2842 0xee100b10, 0xff100f1f,
2843 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2844
ed63aa17
AV		 2845 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
2846 to instruction opcode aliasing. */
2847 {ARM_FEATURE_COPROC (FPU_MVE),
2848 MVE_VSHLL_T1,
2849 0xeea00f40, 0xefa00fd1,
2850 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2851
14925797
AV		 2852 /* Vector VMOVL long. */
2853 {ARM_FEATURE_COPROC (FPU_MVE),
2854 MVE_VMOVL,
2855 0xeea00f40, 0xefa70fd1,
2856 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2857
2858 /* Vector VMOV and narrow. */
2859 {ARM_FEATURE_COPROC (FPU_MVE),
2860 MVE_VMOVN,
2861 0xfe310e81, 0xffb30fd1,
2862 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2863
c507f10b
AV		 2864 /* Floating point move extract. */
2865 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2866 MVE_VMOVX,
2867 0xfeb00a40, 0xffbf0fd0,
2868 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2869
f49bb598
AV		 2870 /* Vector VMUL floating-point T1 variant. */
2871 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2872 MVE_VMUL_FP_T1,
2873 0xff000d50, 0xffa11f51,
2874 "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2875
2876 /* Vector VMUL floating-point T2 variant. */
2877 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2878 MVE_VMUL_FP_T2,
2879 0xee310e60, 0xefb11f70,
2880 "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2881
2882 /* Vector VMUL T1 variant. */
2883 {ARM_FEATURE_COPROC (FPU_MVE),
2884 MVE_VMUL_VEC_T1,
2885 0xef000950, 0xff811f51,
2886 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2887
2888 /* Vector VMUL T2 variant. */
2889 {ARM_FEATURE_COPROC (FPU_MVE),
2890 MVE_VMUL_VEC_T2,
2891 0xee011e60, 0xff811f70,
2892 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2893
2894 /* Vector VMULH. */
2895 {ARM_FEATURE_COPROC (FPU_MVE),
2896 MVE_VMULH,
2897 0xee010e01, 0xef811f51,
2898 "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2899
2900 /* Vector VRMULH. */
2901 {ARM_FEATURE_COPROC (FPU_MVE),
2902 MVE_VRMULH,
2903 0xee011e01, 0xef811f51,
2904 "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2905
14925797
AV		 2906 /* Vector VMULL integer. */
2907 {ARM_FEATURE_COPROC (FPU_MVE),
2908 MVE_VMULL_INT,
2909 0xee010e00, 0xef810f51,
2910 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2911
2912 /* Vector VMULL polynomial. */
2913 {ARM_FEATURE_COPROC (FPU_MVE),
2914 MVE_VMULL_POLY,
2915 0xee310e00, 0xefb10f51,
2916 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2917
c507f10b
AV		 2918 /* Vector VMVN immediate to vector. */
2919 {ARM_FEATURE_COPROC (FPU_MVE),
2920 MVE_VMVN_IMM,
2921 0xef800070, 0xefb810f0,
2922 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2923
2924 /* Vector VMVN register. */
2925 {ARM_FEATURE_COPROC (FPU_MVE),
2926 MVE_VMVN_REG,
2927 0xffb005c0, 0xffbf1fd1,
2928 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2929
f49bb598
AV		 2930 /* Vector VNEG floating point. */
2931 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2932 MVE_VNEG_FP,
2933 0xffb107c0, 0xffb31fd1,
2934 "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2935
2936 /* Vector VNEG. */
2937 {ARM_FEATURE_COPROC (FPU_MVE),
2938 MVE_VNEG_VEC,
2939 0xffb103c0, 0xffb31fd1,
2940 "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2941
c507f10b
AV		 2942 /* Vector VORN, vector bitwise or not. */
2943 {ARM_FEATURE_COPROC (FPU_MVE),
2944 MVE_VORN,
2945 0xef300150, 0xffb11f51,
2946 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2947
2948 /* Vector VORR register. */
2949 {ARM_FEATURE_COPROC (FPU_MVE),
2950 MVE_VORR_REG,
2951 0xef200150, 0xffb11f51,
2952 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2953
14925797
AV		 2954 /* Vector VQDMULL T1 variant. */
2955 {ARM_FEATURE_COPROC (FPU_MVE),
2956 MVE_VQDMULL_T1,
2957 0xee300f01, 0xefb10f51,
2958 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2959
14b456f2
AV		 2960 /* Vector VPNOT. */
2961 {ARM_FEATURE_COPROC (FPU_MVE),
2962 MVE_VPNOT,
2963 0xfe310f4d, 0xffffffff,
2964 "vpnot%v"},
2965
2966 /* Vector VPSEL. */
2967 {ARM_FEATURE_COPROC (FPU_MVE),
2968 MVE_VPSEL,
2969 0xfe310f01, 0xffb11f51,
2970 "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2971
2972 /* Vector VQABS. */
2973 {ARM_FEATURE_COPROC (FPU_MVE),
2974 MVE_VQABS,
2975 0xffb00740, 0xffb31fd1,
2976 "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2977
2978 /* Vector VQADD T1 variant. */
2979 {ARM_FEATURE_COPROC (FPU_MVE),
2980 MVE_VQADD_T1,
2981 0xef000050, 0xef811f51,
2982 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2983
2984 /* Vector VQADD T2 variant. */
2985 {ARM_FEATURE_COPROC (FPU_MVE),
2986 MVE_VQADD_T2,
2987 0xee000f60, 0xef811f70,
2988 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2989
14925797
AV		 2990 /* Vector VQDMULL T2 variant. */
2991 {ARM_FEATURE_COPROC (FPU_MVE),
2992 MVE_VQDMULL_T2,
2993 0xee300f60, 0xefb10f70,
2994 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2995
2996 /* Vector VQMOVN. */
2997 {ARM_FEATURE_COPROC (FPU_MVE),
2998 MVE_VQMOVN,
2999 0xee330e01, 0xefb30fd1,
3000 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
3001
3002 /* Vector VQMOVUN. */
3003 {ARM_FEATURE_COPROC (FPU_MVE),
3004 MVE_VQMOVUN,
3005 0xee310e81, 0xffb30fd1,
3006 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3007
d3b63143
AV		 3008 /* Vector VQDMLADH. */
3009 {ARM_FEATURE_COPROC (FPU_MVE),
3010 MVE_VQDMLADH,
3011 0xee000e00, 0xff810f51,
3012 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3013
3014 /* Vector VQRDMLADH. */
3015 {ARM_FEATURE_COPROC (FPU_MVE),
3016 MVE_VQRDMLADH,
3017 0xee000e01, 0xff810f51,
3018 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3019
3020 /* Vector VQDMLAH. */
3021 {ARM_FEATURE_COPROC (FPU_MVE),
3022 MVE_VQDMLAH,
23d188c7 3023 0xee000e60, 0xff811f70,
d3b63143
AV		 3024 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3025
3026 /* Vector VQRDMLAH. */
3027 {ARM_FEATURE_COPROC (FPU_MVE),
3028 MVE_VQRDMLAH,
23d188c7 3029 0xee000e40, 0xff811f70,
d3b63143
AV		 3030 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3031
3032 /* Vector VQDMLASH. */
3033 {ARM_FEATURE_COPROC (FPU_MVE),
3034 MVE_VQDMLASH,
23d188c7 3035 0xee001e60, 0xff811f70,
d3b63143
AV		 3036 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3037
3038 /* Vector VQRDMLASH. */
3039 {ARM_FEATURE_COPROC (FPU_MVE),
3040 MVE_VQRDMLASH,
23d188c7 3041 0xee001e40, 0xff811f70,
d3b63143
AV		 3042 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3043
3044 /* Vector VQDMLSDH. */
3045 {ARM_FEATURE_COPROC (FPU_MVE),
3046 MVE_VQDMLSDH,
3047 0xfe000e00, 0xff810f51,
3048 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3049
3050 /* Vector VQRDMLSDH. */
3051 {ARM_FEATURE_COPROC (FPU_MVE),
3052 MVE_VQRDMLSDH,
3053 0xfe000e01, 0xff810f51,
3054 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3055
3056 /* Vector VQDMULH T1 variant. */
3057 {ARM_FEATURE_COPROC (FPU_MVE),
3058 MVE_VQDMULH_T1,
3059 0xef000b40, 0xff811f51,
3060 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3061
3062 /* Vector VQRDMULH T2 variant. */
3063 {ARM_FEATURE_COPROC (FPU_MVE),
3064 MVE_VQRDMULH_T2,
3065 0xff000b40, 0xff811f51,
3066 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3067
3068 /* Vector VQDMULH T3 variant. */
3069 {ARM_FEATURE_COPROC (FPU_MVE),
3070 MVE_VQDMULH_T3,
3071 0xee010e60, 0xff811f70,
3072 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3073
3074 /* Vector VQRDMULH T4 variant. */
3075 {ARM_FEATURE_COPROC (FPU_MVE),
3076 MVE_VQRDMULH_T4,
3077 0xfe010e60, 0xff811f70,
3078 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3079
14b456f2
AV		 3080 /* Vector VQNEG. */
3081 {ARM_FEATURE_COPROC (FPU_MVE),
3082 MVE_VQNEG,
3083 0xffb007c0, 0xffb31fd1,
3084 "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3085
ed63aa17
AV		 3086 /* Vector VQRSHL T1 variant. */
3087 {ARM_FEATURE_COPROC (FPU_MVE),
3088 MVE_VQRSHL_T1,
3089 0xef000550, 0xef811f51,
3090 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3091
3092 /* Vector VQRSHL T2 variant. */
3093 {ARM_FEATURE_COPROC (FPU_MVE),
3094 MVE_VQRSHL_T2,
3095 0xee331ee0, 0xefb31ff0,
3096 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3097
3098 /* Vector VQRSHRN. */
3099 {ARM_FEATURE_COPROC (FPU_MVE),
3100 MVE_VQRSHRN,
3101 0xee800f41, 0xefa00fd1,
3102 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3103
3104 /* Vector VQRSHRUN. */
3105 {ARM_FEATURE_COPROC (FPU_MVE),
3106 MVE_VQRSHRUN,
3107 0xfe800fc0, 0xffa00fd1,
3108 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3109
3110 /* Vector VQSHL T1 Variant. */
3111 {ARM_FEATURE_COPROC (FPU_MVE),
3112 MVE_VQSHL_T1,
3113 0xee311ee0, 0xefb31ff0,
3114 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3115
3116 /* Vector VQSHL T4 Variant. */
3117 {ARM_FEATURE_COPROC (FPU_MVE),
3118 MVE_VQSHL_T4,
3119 0xef000450, 0xef811f51,
3120 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3121
3122 /* Vector VQSHRN. */
3123 {ARM_FEATURE_COPROC (FPU_MVE),
3124 MVE_VQSHRN,
3125 0xee800f40, 0xefa00fd1,
3126 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3127
3128 /* Vector VQSHRUN. */
3129 {ARM_FEATURE_COPROC (FPU_MVE),
3130 MVE_VQSHRUN,
3131 0xee800fc0, 0xffa00fd1,
3132 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3133
14b456f2
AV		 3134 /* Vector VQSUB T1 Variant. */
3135 {ARM_FEATURE_COPROC (FPU_MVE),
3136 MVE_VQSUB_T1,
3137 0xef000250, 0xef811f51,
3138 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3139
3140 /* Vector VQSUB T2 Variant. */
3141 {ARM_FEATURE_COPROC (FPU_MVE),
3142 MVE_VQSUB_T2,
3143 0xee001f60, 0xef811f70,
3144 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3145
3146 /* Vector VREV16. */
3147 {ARM_FEATURE_COPROC (FPU_MVE),
3148 MVE_VREV16,
3149 0xffb00140, 0xffb31fd1,
3150 "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
3151
3152 /* Vector VREV32. */
3153 {ARM_FEATURE_COPROC (FPU_MVE),
3154 MVE_VREV32,
3155 0xffb000c0, 0xffb31fd1,
3156 "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3157
3158 /* Vector VREV64. */
3159 {ARM_FEATURE_COPROC (FPU_MVE),
3160 MVE_VREV64,
3161 0xffb00040, 0xffb31fd1,
3162 "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3163
bf0b396d
AV		 3164 /* Vector VRINT floating point. */
3165 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3166 MVE_VRINT_FP,
3167 0xffb20440, 0xffb31c51,
3168 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3169
d3b63143
AV		 3170 /* Vector VRMLALDAVH. */
3171 {ARM_FEATURE_COPROC (FPU_MVE),
3172 MVE_VRMLALDAVH,
3173 0xee800f00, 0xef811f51,
3174 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3175
3176 /* Vector VRMLALDAVH. */
3177 {ARM_FEATURE_COPROC (FPU_MVE),
3178 MVE_VRMLALDAVH,
3179 0xee801f00, 0xef811f51,
3180 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3181
ed63aa17
AV		 3182 /* Vector VRSHL T1 Variant. */
3183 {ARM_FEATURE_COPROC (FPU_MVE),
3184 MVE_VRSHL_T1,
3185 0xef000540, 0xef811f51,
3186 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3187
3188 /* Vector VRSHL T2 Variant. */
3189 {ARM_FEATURE_COPROC (FPU_MVE),
3190 MVE_VRSHL_T2,
3191 0xee331e60, 0xefb31ff0,
3192 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3193
3194 /* Vector VRSHRN. */
3195 {ARM_FEATURE_COPROC (FPU_MVE),
3196 MVE_VRSHRN,
3197 0xfe800fc1, 0xffa00fd1,
3198 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3199
66dcaa5d
AV		 3200 /* Vector VSBC. */
3201 {ARM_FEATURE_COPROC (FPU_MVE),
3202 MVE_VSBC,
3203 0xfe300f00, 0xffb10f51,
3204 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3205
ed63aa17
AV		 3206 /* Vector VSHL T2 Variant. */
3207 {ARM_FEATURE_COPROC (FPU_MVE),
3208 MVE_VSHL_T2,
3209 0xee311e60, 0xefb31ff0,
3210 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3211
3212 /* Vector VSHL T3 Variant. */
3213 {ARM_FEATURE_COPROC (FPU_MVE),
3214 MVE_VSHL_T3,
3215 0xef000440, 0xef811f51,
3216 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3217
3218 /* Vector VSHLC. */
3219 {ARM_FEATURE_COPROC (FPU_MVE),
3220 MVE_VSHLC,
3221 0xeea00fc0, 0xffa01ff0,
3222 "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
3223
3224 /* Vector VSHLL T2 Variant. */
3225 {ARM_FEATURE_COPROC (FPU_MVE),
3226 MVE_VSHLL_T2,
3227 0xee310e01, 0xefb30fd1,
3228 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
3229
3230 /* Vector VSHRN. */
3231 {ARM_FEATURE_COPROC (FPU_MVE),
3232 MVE_VSHRN,
3233 0xee800fc1, 0xffa00fd1,
3234 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3235
04d54ace
AV		 3236 /* Vector VST2 no writeback. */
3237 {ARM_FEATURE_COPROC (FPU_MVE),
3238 MVE_VST2,
3239 0xfc801e00, 0xffb01e5f,
3240 "vst2%5d.%7-8s\t%B, [%16-19r]"},
3241
3242 /* Vector VST2 writeback. */
3243 {ARM_FEATURE_COPROC (FPU_MVE),
3244 MVE_VST2,
3245 0xfca01e00, 0xffb01e5f,
3246 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3247
3248 /* Vector VST4 no writeback. */
3249 {ARM_FEATURE_COPROC (FPU_MVE),
3250 MVE_VST4,
3251 0xfc801e01, 0xffb01e1f,
3252 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3253
3254 /* Vector VST4 writeback. */
3255 {ARM_FEATURE_COPROC (FPU_MVE),
3256 MVE_VST4,
3257 0xfca01e01, 0xffb01e1f,
3258 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3259
ef1576a1
AV		 3260 /* Vector VSTRB scatter store, T1 variant. */
3261 {ARM_FEATURE_COPROC (FPU_MVE),
3262 MVE_VSTRB_SCATTER_T1,
3263 0xec800e00, 0xffb01e50,
3264 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3265
3266 /* Vector VSTRH scatter store, T2 variant. */
3267 {ARM_FEATURE_COPROC (FPU_MVE),
3268 MVE_VSTRH_SCATTER_T2,
3269 0xec800e10, 0xffb01e50,
3270 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3271
3272 /* Vector VSTRW scatter store, T3 variant. */
3273 {ARM_FEATURE_COPROC (FPU_MVE),
3274 MVE_VSTRW_SCATTER_T3,
3275 0xec800e40, 0xffb01e50,
3276 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3277
3278 /* Vector VSTRD scatter store, T4 variant. */
3279 {ARM_FEATURE_COPROC (FPU_MVE),
3280 MVE_VSTRD_SCATTER_T4,
3281 0xec800fd0, 0xffb01fd0,
3282 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3283
3284 /* Vector VSTRW scatter store, T5 variant. */
3285 {ARM_FEATURE_COPROC (FPU_MVE),
3286 MVE_VSTRW_SCATTER_T5,
3287 0xfd001e00, 0xff111f00,
3288 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3289
3290 /* Vector VSTRD scatter store, T6 variant. */
3291 {ARM_FEATURE_COPROC (FPU_MVE),
3292 MVE_VSTRD_SCATTER_T6,
3293 0xfd001f00, 0xff111f00,
3294 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3295
aef6d006
AV		 3296 /* Vector VSTRB. */
3297 {ARM_FEATURE_COPROC (FPU_MVE),
3298 MVE_VSTRB_T1,
3299 0xec000e00, 0xfe581e00,
3300 "vstrb%v.%7-8s\t%13-15Q, %d"},
3301
3302 /* Vector VSTRH. */
3303 {ARM_FEATURE_COPROC (FPU_MVE),
3304 MVE_VSTRH_T2,
3305 0xec080e00, 0xfe581e00,
3306 "vstrh%v.%7-8s\t%13-15Q, %d"},
3307
3308 /* Vector VSTRB variant T5. */
3309 {ARM_FEATURE_COPROC (FPU_MVE),
3310 MVE_VSTRB_T5,
3311 0xec001e00, 0xfe101f80,
3312 "vstrb%v.8\t%13-15,22Q, %d"},
3313
3314 /* Vector VSTRH variant T6. */
3315 {ARM_FEATURE_COPROC (FPU_MVE),
3316 MVE_VSTRH_T6,
3317 0xec001e80, 0xfe101f80,
3318 "vstrh%v.16\t%13-15,22Q, %d"},
3319
3320 /* Vector VSTRW variant T7. */
3321 {ARM_FEATURE_COPROC (FPU_MVE),
3322 MVE_VSTRW_T7,
3323 0xec001f00, 0xfe101f80,
3324 "vstrw%v.32\t%13-15,22Q, %d"},
3325
66dcaa5d
AV		 3326 /* Vector VSUB floating point T1 variant. */
3327 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3328 MVE_VSUB_FP_T1,
3329 0xef200d40, 0xffa11f51,
3330 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3331
3332 /* Vector VSUB floating point T2 variant. */
3333 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3334 MVE_VSUB_FP_T2,
3335 0xee301f40, 0xefb11f70,
3336 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3337
3338 /* Vector VSUB T1 variant. */
3339 {ARM_FEATURE_COPROC (FPU_MVE),
3340 MVE_VSUB_VEC_T1,
3341 0xff000840, 0xff811f51,
3342 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3343
3344 /* Vector VSUB T2 variant. */
3345 {ARM_FEATURE_COPROC (FPU_MVE),
3346 MVE_VSUB_VEC_T2,
3347 0xee011f40, 0xff811f70,
3348 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3349
23d00a41
SD		 3350 {ARM_FEATURE_COPROC (FPU_MVE),
3351 MVE_ASRLI,
3352 0xea50012f, 0xfff1813f,
3353 "asrl%c\t%17-19l, %9-11h, %j"},
3354
3355 {ARM_FEATURE_COPROC (FPU_MVE),
3356 MVE_ASRL,
3357 0xea50012d, 0xfff101ff,
3358 "asrl%c\t%17-19l, %9-11h, %12-15S"},
3359
3360 {ARM_FEATURE_COPROC (FPU_MVE),
3361 MVE_LSLLI,
3362 0xea50010f, 0xfff1813f,
3363 "lsll%c\t%17-19l, %9-11h, %j"},
3364
3365 {ARM_FEATURE_COPROC (FPU_MVE),
3366 MVE_LSLL,
3367 0xea50010d, 0xfff101ff,
3368 "lsll%c\t%17-19l, %9-11h, %12-15S"},
3369
3370 {ARM_FEATURE_COPROC (FPU_MVE),
3371 MVE_LSRL,
3372 0xea50011f, 0xfff1813f,
3373 "lsrl%c\t%17-19l, %9-11h, %j"},
3374
3375 {ARM_FEATURE_COPROC (FPU_MVE),
3376 MVE_SQRSHRL,
08132bdd
SP		 3377 0xea51012d, 0xfff1017f,
3378 "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"},
23d00a41
SD		 3379
3380 {ARM_FEATURE_COPROC (FPU_MVE),
3381 MVE_SQRSHR,
3382 0xea500f2d, 0xfff00fff,
3383 "sqrshr%c\t%16-19S, %12-15S"},
3384
3385 {ARM_FEATURE_COPROC (FPU_MVE),
3386 MVE_SQSHLL,
3387 0xea51013f, 0xfff1813f,
3388 "sqshll%c\t%17-19l, %9-11h, %j"},
3389
3390 {ARM_FEATURE_COPROC (FPU_MVE),
3391 MVE_SQSHL,
3392 0xea500f3f, 0xfff08f3f,
3393 "sqshl%c\t%16-19S, %j"},
3394
3395 {ARM_FEATURE_COPROC (FPU_MVE),
3396 MVE_SRSHRL,
3397 0xea51012f, 0xfff1813f,
3398 "srshrl%c\t%17-19l, %9-11h, %j"},
3399
3400 {ARM_FEATURE_COPROC (FPU_MVE),
3401 MVE_SRSHR,
3402 0xea500f2f, 0xfff08f3f,
3403 "srshr%c\t%16-19S, %j"},
3404
3405 {ARM_FEATURE_COPROC (FPU_MVE),
3406 MVE_UQRSHLL,
08132bdd
SP		 3407 0xea51010d, 0xfff1017f,
3408 "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"},
23d00a41
SD		 3409
3410 {ARM_FEATURE_COPROC (FPU_MVE),
3411 MVE_UQRSHL,
3412 0xea500f0d, 0xfff00fff,
3413 "uqrshl%c\t%16-19S, %12-15S"},
3414
3415 {ARM_FEATURE_COPROC (FPU_MVE),
3416 MVE_UQSHLL,
3417 0xea51010f, 0xfff1813f,
3418 "uqshll%c\t%17-19l, %9-11h, %j"},
3419
3420 {ARM_FEATURE_COPROC (FPU_MVE),
3421 MVE_UQSHL,
3422 0xea500f0f, 0xfff08f3f,
3423 "uqshl%c\t%16-19S, %j"},
3424
3425 {ARM_FEATURE_COPROC (FPU_MVE),
3426 MVE_URSHRL,
3427 0xea51011f, 0xfff1813f,
3428 "urshrl%c\t%17-19l, %9-11h, %j"},
3429
3430 {ARM_FEATURE_COPROC (FPU_MVE),
3431 MVE_URSHR,
3432 0xea500f1f, 0xfff08f3f,
3433 "urshr%c\t%16-19S, %j"},
3434
e39c1607
SD		 3435 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3436 MVE_CSINC,
3437 0xea509000, 0xfff0f000,
3438 "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3439
3440 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3441 MVE_CSINV,
3442 0xea50a000, 0xfff0f000,
3443 "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3444
3445 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3446 MVE_CSET,
3447 0xea5f900f, 0xfffff00f,
3448 "cset\t%8-11S, %4-7C"},
3449
3450 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3451 MVE_CSETM,
3452 0xea5fa00f, 0xfffff00f,
3453 "csetm\t%8-11S, %4-7C"},
3454
3455 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3456 MVE_CSEL,
3457 0xea508000, 0xfff0f000,
3458 "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3459
3460 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3461 MVE_CSNEG,
3462 0xea50b000, 0xfff0f000,
3463 "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3464
3465 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3466 MVE_CINC,
3467 0xea509000, 0xfff0f000,
3468 "cinc\t%8-11S, %16-19Z, %4-7C"},
3469
3470 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3471 MVE_CINV,
3472 0xea50a000, 0xfff0f000,
3473 "cinv\t%8-11S, %16-19Z, %4-7C"},
3474
3475 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3476 MVE_CNEG,
3477 0xea50b000, 0xfff0f000,
3478 "cneg\t%8-11S, %16-19Z, %4-7C"},
3479
143275ea
AV		 3480 {ARM_FEATURE_CORE_LOW (0),
3481 MVE_NONE,
3482 0x00000000, 0x00000000, 0}
73cd51e5
AV		 3483};
3484
8f06b2d8
PB		 3485/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
3486 ordered: they must be searched linearly from the top to obtain a correct
3487 match. */
3488
3489/* print_insn_arm recognizes the following format control codes:
3490
3491 %% %
3492
3493 %a print address for ldr/str instruction
3494 %s print address for ldr/str halfword/signextend instruction
c1e26897 3495 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 3496 %b print branch destination
3497 %c print condition code (always bits 28-31)
3498 %m print register mask for ldm/stm instruction
3499 %o print operand2 (immediate or register + shift)
3500 %p print 'p' iff bits 12-15 are 15
3501 %t print 't' iff bit 21 set and bit 24 clear
3502 %B print arm BLX(1) destination
3503 %C print the PSR sub type.
62b3e311
PB		 3504 %U print barrier type.
3505 %P print address for pli instruction.
8f06b2d8
PB		 3506
3507 %<bitfield>r print as an ARM register
9eb6c0f1 3508 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 3509 %<bitfield>R as %r but r15 is UNPREDICTABLE
3510 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3511 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 3512 %<bitfield>d print the bitfield in decimal
43e65147 3513 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 3514 %<bitfield>x print the bitfield in hex
3515 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 3516
16980d0b
JB		 3517 %<bitfield>'c print specified char iff bitfield is all ones
3518 %<bitfield>`c print specified char iff bitfield is all zeroes
3519 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 3520
8f06b2d8
PB		 3521 %e print arm SMI operand (bits 0..7,8..19).
3522 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 3523 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
3524 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 3525
8f06b2d8
PB		 3526static const struct opcode32 arm_opcodes[] =
3527{
3528 /* ARM instructions. */
823d2571
TG		 3529 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3530 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
3531 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3532 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
3533
3534 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
3535 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3537 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3539 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
3541 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3543 0x00800090, 0x0fa000f0,
3544 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3545 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3546 0x00a00090, 0x0fa000f0,
3547 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 3548
105bde57 3549 /* V8.2 RAS extension instructions. */
4d1464f2 3550 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 3551 0xe320f010, 0xffffffff, "esb"},
3552
53c4b28b 3553 /* V8 instructions. */
823d2571
TG		 3554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3555 0x0320f005, 0x0fffffff, "sevl"},
f7dd2fb2
TC		 3556 /* Defined in V8 but is in NOP space so available to all arch. */
3557 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
823d2571 3558 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
4ed7ed8d 3559 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 3560 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3561 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 3562 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3563 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3564 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3566 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 3567 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3568 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3569 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3570 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3571 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3572 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3573 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3574 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3575 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3576 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3577 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3578 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3579 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3580 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3581 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3582 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3583 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3584 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3585 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 3586 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 3587 /* CRC32 instructions. */
823d2571
TG		 3588 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3589 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
3590 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3591 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
3592 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3593 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
3594 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3595 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
3596 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3597 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
3598 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3599 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 3600
ddfded2f
MW		 3601 /* Privileged Access Never extension instructions. */
3602 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
3603 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
3604
90ec0d68 3605 /* Virtualization Extension instructions. */
823d2571
TG		 3606 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
3607 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 3608
eea54501 3609 /* Integer Divide Extension instructions. */
823d2571
TG		 3610 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3611 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3612 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3613 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 3614
60e5ef9f 3615 /* MP Extension instructions. */
823d2571 3616 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 3617
c597cc3d
SD		 3618 /* Speculation Barriers. */
3619 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
3620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
3621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
3622
62b3e311 3623 /* V7 instructions. */
823d2571
TG		 3624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
3625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
3626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3627 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3629 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a
AV		 3631 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3632 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
62b3e311 3633
c19d1205 3634 /* ARM V6T2 instructions. */
823d2571
TG		 3635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3636 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3638 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3640 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3641 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3642 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3643
3644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3645 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
3646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3647 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3648
ff8646ee 3649 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 3650 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 3651 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3652 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3654 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3656 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 3657
f4c65163 3658 /* ARM Security extension instructions. */
823d2571
TG		 3659 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
3660 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 3661
8f06b2d8 3662 /* ARM V6K instructions. */
823d2571
TG		 3663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3664 0xf57ff01f, 0xffffffff, "clrex"},
3665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3666 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3667 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3668 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3669 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3670 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3672 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3673 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3674 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3676 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 3677
7fadb25d
SD		 3678 /* ARMv8.5-A instructions. */
3679 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
3680
8f06b2d8 3681 /* ARM V6K NOP hints. */
823d2571
TG		 3682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3683 0x0320f001, 0x0fffffff, "yield%c"},
3684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3685 0x0320f002, 0x0fffffff, "wfe%c"},
3686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3687 0x0320f003, 0x0fffffff, "wfi%c"},
3688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3689 0x0320f004, 0x0fffffff, "sev%c"},
3690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3691 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 3692
fe56b6ce 3693 /* ARM V6 instructions. */
823d2571
TG		 3694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3695 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
3696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3697 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
3698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3699 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
3700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3701 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
3702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3703 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
3704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3705 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3707 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
3708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3709 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
3710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3711 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
3712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3713 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
3714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3715 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3717 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3719 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3721 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3723 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3725 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3727 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3729 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3731 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3733 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3735 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3737 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3739 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3741 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3743 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3745 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3747 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3749 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3751 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3753 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3755 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3757 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3759 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3761 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3763 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3765 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3767 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3769 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3771 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3773 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3775 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3777 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3779 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3781 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3783 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3785 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3787 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3789 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3791 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3793 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3795 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3797 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3799 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3801 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3803 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3805 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3807 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3809 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3811 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3813 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3815 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3817 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3819 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3821 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3823 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3825 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3827 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3829 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3831 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3833 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3835 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3837 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3839 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3841 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3843 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3845 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3847 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3849 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3851 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3853 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3855 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3857 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3859 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3861 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3863 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3865 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3867 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3869 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3871 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3873 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3875 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3877 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3879 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3881 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
3882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3883 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3885 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3887 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3889 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3891 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
3892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3893 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
3894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3895 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
3896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3897 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
3898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3899 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3901 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3903 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3905 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3907 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
3908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3909 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3911 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3913 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
3914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3915 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
3916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3917 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
3918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3919 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
3920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3921 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
3922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3923 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
3924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3925 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
3926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3927 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
3928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3929 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3931 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
3932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3933 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
3934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3935 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
3936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3937 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 3938
8f06b2d8 3939 /* V5J instruction. */
823d2571
TG		 3940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
3941 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 3942
8f06b2d8 3943 /* V5 Instructions. */
823d2571
TG		 3944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3945 0xe1200070, 0xfff000f0,
3946 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
3947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3948 0xfa000000, 0xfe000000, "blx\t%B"},
3949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3950 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
3951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3952 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
3953
3954 /* V5E "El Segundo" Instructions. */
3955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3956 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
3957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3958 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
3959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3960 0xf450f000, 0xfc70f000, "pld\t%a"},
3961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3962 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3964 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3966 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3968 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
3969
3970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3971 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3973 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
3974
3975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3976 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3978 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3980 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3982 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3983
3984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3985 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
3986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3987 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
3988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3989 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
3990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3991 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
3992
3993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3994 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
3995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3996 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
3997
3998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3999 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
4000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4001 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
4002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4003 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
4004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4005 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 4006
8f06b2d8 4007 /* ARM Instructions. */
823d2571
TG		 4008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4009 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
4010
4011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4012 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
4013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4014 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
4015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4016 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
4017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4018 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
4019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4020 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
4021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4022 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
4023
4024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4025 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
4026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4027 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
4028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4029 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
4030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4031 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
4032
4033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4034 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
4035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4036 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
4037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4038 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
4039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4040 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
4041
4042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4043 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
4044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4045 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
4046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4047 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
4048
4049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4050 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
4051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4052 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
4053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4054 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
4055
4056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4057 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
4058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4059 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
4060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4061 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
4062
4063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4064 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4066 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4068 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
4069
4070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4071 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
4072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4073 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
4074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4075 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
4076
4077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4078 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
4079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4080 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
4081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4082 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
4083
4084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4085 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4087 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4089 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
4090
4091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4092 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4094 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4096 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
4097
4098 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
4099 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
4100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4101 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
4102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4103 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
4104
4105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4106 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
4107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4108 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
4109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4110 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
4111
4112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4113 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 4114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4115 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 4116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4117 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
823d2571
TG		 4118
4119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4120 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
4121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4122 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
4123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4124 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
4125
4126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4127 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
4128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4129 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
4130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4131 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
4132
4133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4134 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
4135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4136 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
4137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4138 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
4139
4140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4141 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
4142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4143 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
4144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4145 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
4146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4147 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
4148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4149 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
4150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4151 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
4152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4153 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
4154
4155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4156 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
4157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4158 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
4159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4160 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
4161
4162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4163 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
4164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4165 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
4166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4167 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
4168
4169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4170 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
4171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4172 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
4173
4174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4175 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
4176
4177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4178 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
4179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4180 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
4181
4182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4183 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4185 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4187 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4189 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4191 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4193 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4195 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4196 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4197 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4199 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4201 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4203 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4205 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4207 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4209 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4210 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4211 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4212 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4213 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4215 0x092d0000, 0x0fff0000, "push%c\t%m"},
4216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4217 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
4218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4219 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4220
4221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4222 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4224 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4226 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4228 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4230 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4232 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4234 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4236 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4238 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4240 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4242 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4244 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4246 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4248 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4250 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4252 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4254 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
4255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4256 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
4257 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4258 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4259
4260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4261 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4263 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 4264
4265 /* The rest. */
4ab90a7a
AV		 4266 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
4267 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 4268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4269 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4270 {ARM_FEATURE_CORE_LOW (0),
4271 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 4272};
4273
4274/* print_insn_thumb16 recognizes the following format control codes:
4275
4276 %S print Thumb register (bits 3..5 as high number if bit 6 set)
4277 %D print Thumb register (bits 0..2 as high number if bit 7 set)
4278 %<bitfield>I print bitfield as a signed decimal
4279 (top bit of range being the sign bit)
4280 %N print Thumb register mask (with LR)
4281 %O print Thumb register mask (with PC)
4282 %M print Thumb register mask
4283 %b print CZB's 6-bit unsigned branch destination
4284 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 4285 %c print the condition code
4286 %C print the condition code, or "s" if not conditional
4287 %x print warning if conditional an not at end of IT block"
4288 %X print "\t; unpredictable <IT:code>" if conditional
4289 %I print IT instruction suffix and operands
4547cb56 4290 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 4291 %<bitfield>r print bitfield as an ARM register
4292 %<bitfield>d print bitfield as a decimal
4293 %<bitfield>H print (bitfield * 2) as a decimal
4294 %<bitfield>W print (bitfield * 4) as a decimal
4295 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
4296 %<bitfield>B print Thumb branch destination (signed displacement)
4297 %<bitfield>c print bitfield as a condition code
4298 %<bitnum>'c print specified char iff bit is one
4299 %<bitnum>?ab print a if bit is one else print b. */
4300
4301static const struct opcode16 thumb_opcodes[] =
4302{
4303 /* Thumb instructions. */
4304
16a1fa25
TP		 4305 /* ARMv8-M Security Extensions instructions. */
4306 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
e207bc53 4307 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
16a1fa25 4308
53c4b28b 4309 /* ARM V8 instructions. */
823d2571
TG		 4310 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
4311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
ddfded2f 4312 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
53c4b28b 4313
8f06b2d8 4314 /* ARM V6K no-argument instructions. */
823d2571
TG		 4315 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
4316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
4317 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
4318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
4319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
4320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 4321
4322 /* ARM V6T2 instructions. */
ff8646ee
TP		 4323 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4324 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4325 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4326 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 4327 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 4328
4329 /* ARM V6. */
823d2571
TG		 4330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
4331 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
4332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
4336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
4337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4339 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 4341
4342 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 4343 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4344 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 4345 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 4346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4347 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 4348 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 4349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4350 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 4351 /* Format 4. */
823d2571
TG		 4352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 4368 /* format 13 */
823d2571
TG		 4369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
4370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 4371 /* format 5 */
823d2571
TG		 4372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
4373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
4374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 4376 /* format 14 */
823d2571
TG		 4377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
4378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 4379 /* format 2 */
823d2571
TG		 4380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4381 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4383 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4385 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
4386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4387 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 4388 /* format 8 */
823d2571
TG		 4389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4390 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4392 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4394 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 4395 /* format 7 */
823d2571
TG		 4396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4397 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4399 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 4400 /* format 1 */
823d2571
TG		 4401 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4403 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
4404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 4406 /* format 3 */
823d2571
TG		 4407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
4408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
4409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
4410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 4411 /* format 6 */
823d2571
TG		 4412 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4413 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4414 0x4800, 0xF800,
4415 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 4416 /* format 9 */
823d2571
TG		 4417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4418 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
4419 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4420 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
4421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4422 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
4423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4424 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 4425 /* format 10 */
823d2571
TG		 4426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4427 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
4428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4429 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 4430 /* format 11 */
823d2571
TG		 4431 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4432 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
4433 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4434 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 4435 /* format 12 */
823d2571
TG		 4436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4437 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
4438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4439 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 4440 /* format 15 */
823d2571
TG		 4441 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 4443 /* format 17 */
823d2571 4444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 4445 /* format 16 */
823d2571
TG		 4446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
4447 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
4448 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 4449 /* format 18 */
823d2571 4450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 4451
4452 /* The E800 .. FFFF range is unconditionally redirected to the
4453 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4454 are processed via that table. Thus, we can never encounter a
4455 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 4456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
4457 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 4458};
4459
4460/* Thumb32 opcodes use the same table structure as the ARM opcodes.
4461 We adopt the convention that hw1 is the high 16 bits of .value and
4462 .mask, hw2 the low 16 bits.
4463
4464 print_insn_thumb32 recognizes the following format control codes:
4465
4466 %% %
4467
4468 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4469 %M print a modified 12-bit immediate (same location)
4470 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4471 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 4472 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 4473 %S print a possibly-shifted Rm
4474
32a94698 4475 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 4476 %a print the address of a plain load/store
4477 %w print the width and signedness of a core load/store
4478 %m print register mask for ldm/stm
4b5a202f 4479 %n print register mask for clrm
8f06b2d8
PB		 4480
4481 %E print the lsb and width fields of a bfc/bfi instruction
4482 %F print the lsb and width fields of a sbfx/ubfx instruction
e12437dc 4483 %G print a fallback offset for Branch Future instructions
e5d6e09e 4484 %W print an offset for BF instruction
1caf72a5 4485 %Y print an offset for BFL instruction
1889da70 4486 %Z print an offset for BFCSEL instruction
60f993ce
AV		 4487 %Q print an offset for Low Overhead Loop instructions
4488 %P print an offset for Low Overhead Loop end instructions
8f06b2d8
PB		 4489 %b print a conditional branch offset
4490 %B print an unconditional branch offset
4491 %s print the shift field of an SSAT instruction
4492 %R print the rotation field of an SXT instruction
62b3e311
PB		 4493 %U print barrier type.
4494 %P print address for pli instruction.
c22aaad1
PB		 4495 %c print the condition code
4496 %x print warning if conditional an not at end of IT block"
4497 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 4498
4499 %<bitfield>d print bitfield in decimal
f0fba320 4500 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 4501 %<bitfield>W print bitfield*4 in decimal
4502 %<bitfield>r print bitfield as an ARM register
dd5181d5 4503 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
f1c7f421 4504 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
8f06b2d8
PB		 4505 %<bitfield>c print bitfield as a condition code
4506
16980d0b
JB		 4507 %<bitfield>'c print specified char iff bitfield is all ones
4508 %<bitfield>`c print specified char iff bitfield is all zeroes
4509 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 4510
4511 With one exception at the bottom (done because BL and BLX(1) need
4512 to come dead last), this table was machine-sorted first in
4513 decreasing order of number of bits set in the mask, then in
4514 increasing numeric order of mask, then in increasing numeric order
4515 of opcode. This order is not the clearest for a human reader, but
4516 is guaranteed never to catch a special-case bit pattern with a more
4517 general mask, which is important, because this instruction encoding
4518 makes heavy use of special-case bit patterns. */
4519static const struct opcode32 thumb32_opcodes[] =
4520{
4b5a202f
AV		 4521 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4522 instructions. */
60f993ce 4523 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
d052b9b7 4524 0xf00fe001, 0xffffffff, "lctp%c"},
60f993ce
AV		 4525 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4526 0xf02fc001, 0xfffff001, "le\t%P"},
4527 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4528 0xf00fc001, 0xfffff001, "le\tlr, %P"},
d052b9b7
AV		 4529 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4530 0xf01fc001, 0xfffff001, "letp\tlr, %P"},
4531 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4532 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
4533 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4534 0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
4535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4536 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
4537 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4538 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
60f993ce 4539
4389b29a
AV		 4540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4541 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
f1c7f421
AV		 4542 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4543 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
65d1bc05
AV		 4544 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4545 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
f1c7f421
AV		 4546 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4547 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
f6b2b12d
AV		 4548 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4549 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4389b29a 4550
4b5a202f
AV		 4551 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4552 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4389b29a 4553
16a1fa25
TP		 4554 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
4555 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4ed7ed8d
TP		 4556 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4557 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4558 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4559 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
16a1fa25
TP		 4560 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4561 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4562 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4563 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4ed7ed8d 4564
105bde57 4565 /* ARM V8.2 RAS extension instructions. */
4d1464f2 4566 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 4567 0xf3af8010, 0xffffffff, "esb"},
4568
53c4b28b 4569 /* V8 instructions. */
823d2571
TG		 4570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4571 0xf3af8005, 0xffffffff, "sevl%c.w"},
4572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4573 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4575 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4577 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4579 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4581 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4583 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4585 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4587 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4589 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4591 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4593 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4595 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4597 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4599 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4601 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 4602
dd5181d5 4603 /* CRC32 instructions. */
823d2571 4604 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4605 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
823d2571 4606 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4607 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
823d2571 4608 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4609 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
823d2571 4610 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4611 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
823d2571 4612 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4613 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
823d2571 4614 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4615 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
dd5181d5 4616
c597cc3d
SD		 4617 /* Speculation Barriers. */
4618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
4619 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
4620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
4621
62b3e311 4622 /* V7 instructions. */
823d2571
TG		 4623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
4625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4627 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4629 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4630 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4631 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4632 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4633 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 4634
90ec0d68 4635 /* Virtualization Extension instructions. */
823d2571 4636 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 4637 /* We skip ERET as that is SUBS pc, lr, #0. */
4638
60e5ef9f 4639 /* MP Extension instructions. */
823d2571 4640 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 4641
f4c65163 4642 /* Security extension instructions. */
823d2571 4643 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 4644
7fadb25d
SD		 4645 /* ARMv8.5-A instructions. */
4646 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
4647
8f06b2d8 4648 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 4649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
4650 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
4651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4652 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
4654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4655 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
4656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4657
ff8646ee 4658 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4659 0xf3bf8f2f, 0xffffffff, "clrex%c"},
4660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4661 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
4662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4663 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
4664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4665 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4667 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4669 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4671 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4673 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
4674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4675 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4677 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
4678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4679 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
4680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4681 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
4682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4683 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
4684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4685 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 4686 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 4687 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 4688 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4689 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4691 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
4692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4693 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
4694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4695 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4697 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4699 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4701 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4703 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4705 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 4706 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4707 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4709 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4711 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4713 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4715 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4717 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4719 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4721 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4723 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4725 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4727 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4729 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4731 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4733 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4735 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4737 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4739 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4741 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4743 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4745 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4747 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4749 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4751 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4753 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4755 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4757 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4759 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4761 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4763 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4765 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4767 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4769 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4771 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4773 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4775 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4777 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4779 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4781 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4783 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4785 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4787 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4789 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4791 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4793 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4795 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4797 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4799 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4801 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4803 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4805 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4807 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4809 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4811 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4813 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 4814 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4815 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 4817 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 4818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4819 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4821 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4823 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4825 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4827 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4829 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4831 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4833 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4835 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4837 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4839 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4841 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4843 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4845 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4847 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4849 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4851 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4853 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4855 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4857 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4859 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4861 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4863 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4865 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4867 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4869 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4871 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4873 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4875 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4877 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4879 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4881 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 4882 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4883 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
4884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4885 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
4886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4887 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
4888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4889 0xf810f000, 0xff70f000, "pld%c\t%a"},
4890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4891 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4893 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4895 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4897 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4899 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4901 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4903 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4905 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
4906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4907 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
4908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4909 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
4910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4911 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
4912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4913 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
4914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4915 0xfb100000, 0xfff000c0,
4916 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4918 0xfbc00080, 0xfff000c0,
4919 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
4920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4921 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
4922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4923 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
4924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 4925 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 4926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4927 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
4928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4929 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 4930 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4931 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
4932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4933 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 4934 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4935 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
4936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4937 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
4938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4939 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
4940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4941 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
4942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4943 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
4944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4945 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
4946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4947 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
4948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4949 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
4950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4951 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
4952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4953 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
4954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4955 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 4956 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4957 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
4958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4959 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
4960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4961 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
4962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4963 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
4964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4965 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
4966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4967 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
4968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4969 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
4970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4971 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
4972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4973 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
4974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4975 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
4976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4977 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
4978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4979 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
4980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4981 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
4982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4983 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
4984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4985 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
4986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4987 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
4988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4989 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
4990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4991 0xe9400000, 0xff500000,
4992 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4994 0xe9500000, 0xff500000,
4995 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4997 0xe8600000, 0xff700000,
4998 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5000 0xe8700000, 0xff700000,
5001 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5003 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
5004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5005 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 5006
5007 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 5008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5009 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
5010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5011 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
5012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5013 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
5014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5015 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 5016
8f06b2d8 5017 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 5018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5019 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
5020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5021 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 5022
5023 /* Fallback. */
823d2571
TG		 5024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
5025 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
5026 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 5027};
ff4a8d2b 5028
8f06b2d8
PB		 5029static const char *const arm_conditional[] =
5030{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 5031 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 5032
5033static const char *const arm_fp_const[] =
5034{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
5035
5036static const char *const arm_shift[] =
5037{"lsl", "lsr", "asr", "ror"};
5038
5039typedef struct
5040{
5041 const char *name;
5042 const char *description;
5043 const char *reg_names[16];
5044}
5045arm_regname;
5046
5047static const arm_regname regnames[] =
5048{
65b48a81 5049 { "reg-names-raw", N_("Select raw register names"),
8f06b2d8 5050 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
65b48a81 5051 { "reg-names-gcc", N_("Select register names used by GCC"),
8f06b2d8 5052 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 5053 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
8f06b2d8 5054 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65b48a81
PB		 5055 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
5056 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
5057 { "reg-names-apcs", N_("Select register names used in the APCS"),
8f06b2d8 5058 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 5059 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
8f06b2d8 5060 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
65b48a81
PB		 5061 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
5062 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
8f06b2d8
PB		 5063};
5064
5065static const char *const iwmmxt_wwnames[] =
5066{"b", "h", "w", "d"};
5067
5068static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 5069{"b", "bus", "bc", "bss",
5070 "h", "hus", "hc", "hss",
5071 "w", "wus", "wc", "wss",
5072 "d", "dus", "dc", "dss"
8f06b2d8
PB		 5073};
5074
5075static const char *const iwmmxt_regnames[] =
5076{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
5077 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
5078};
5079
5080static const char *const iwmmxt_cregnames[] =
5081{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
5082 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
5083};
5084
143275ea
AV		 5085static const char *const vec_condnames[] =
5086{ "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
5087};
5088
5089static const char *const mve_predicatenames[] =
5090{ "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
5091 "eee", "ee", "eet", "e", "ett", "et", "ete"
5092};
5093
5094/* Names for 2-bit size field for mve vector isntructions. */
5095static const char *const mve_vec_sizename[] =
5096 { "8", "16", "32", "64"};
5097
5098/* Indicates whether we are processing a then predicate,
5099 else predicate or none at all. */
5100enum vpt_pred_state
5101{
5102 PRED_NONE,
5103 PRED_THEN,
5104 PRED_ELSE
5105};
5106
5107/* Information used to process a vpt block and subsequent instructions. */
5108struct vpt_block
5109{
5110 /* Are we in a vpt block. */
5111 bfd_boolean in_vpt_block;
5112
5113 /* Next predicate state if in vpt block. */
5114 enum vpt_pred_state next_pred_state;
5115
5116 /* Mask from vpt/vpst instruction. */
5117 long predicate_mask;
5118
5119 /* Instruction number in vpt block. */
5120 long current_insn_num;
5121
5122 /* Number of instructions in vpt block.. */
5123 long num_pred_insn;
5124};
5125
5126static struct vpt_block vpt_block_state =
5127{
5128 FALSE,
5129 PRED_NONE,
5130 0,
5131 0,
5132 0
5133};
5134
8f06b2d8
PB		 5135/* Default to GCC register name set. */
5136static unsigned int regname_selected = 1;
5137
65b48a81 5138#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
8f06b2d8
PB		 5139#define arm_regnames regnames[regname_selected].reg_names
5140
5141static bfd_boolean force_thumb = FALSE;
5142
c22aaad1
PB		 5143/* Current IT instruction state. This contains the same state as the IT
5144 bits in the CPSR. */
5145static unsigned int ifthen_state;
5146/* IT state for the next instruction. */
5147static unsigned int ifthen_next_state;
5148/* The address of the insn for which the IT state is valid. */
5149static bfd_vma ifthen_address;
5150#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 5151/* Indicates that the current Conditional state is unconditional or outside
5152 an IT block. */
5153#define COND_UNCOND 16
c22aaad1 5154
8f06b2d8
PB		 5155\f
5156/* Functions. */
143275ea
AV		 5157/* Extract the predicate mask for a VPT or VPST instruction.
5158 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
5159
5160static long
5161mve_extract_pred_mask (long given)
5162{
5163 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
5164}
5165
5166/* Return the number of instructions in a MVE predicate block. */
5167static long
5168num_instructions_vpt_block (long given)
5169{
5170 long mask = mve_extract_pred_mask (given);
5171 if (mask == 0)
5172 return 0;
5173
5174 if (mask == 8)
5175 return 1;
5176
5177 if ((mask & 7) == 4)
5178 return 2;
5179
5180 if ((mask & 3) == 2)
5181 return 3;
5182
5183 if ((mask & 1) == 1)
5184 return 4;
5185
5186 return 0;
5187}
5188
5189static void
5190mark_outside_vpt_block (void)
5191{
5192 vpt_block_state.in_vpt_block = FALSE;
5193 vpt_block_state.next_pred_state = PRED_NONE;
5194 vpt_block_state.predicate_mask = 0;
5195 vpt_block_state.current_insn_num = 0;
5196 vpt_block_state.num_pred_insn = 0;
5197}
5198
5199static void
5200mark_inside_vpt_block (long given)
5201{
5202 vpt_block_state.in_vpt_block = TRUE;
5203 vpt_block_state.next_pred_state = PRED_THEN;
5204 vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
5205 vpt_block_state.current_insn_num = 0;
5206 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
5207 assert (vpt_block_state.num_pred_insn >= 1);
5208}
5209
5210static enum vpt_pred_state
5211invert_next_predicate_state (enum vpt_pred_state astate)
5212{
5213 if (astate == PRED_THEN)
5214 return PRED_ELSE;
5215 else if (astate == PRED_ELSE)
5216 return PRED_THEN;
5217 else
5218 return PRED_NONE;
5219}
5220
5221static enum vpt_pred_state
5222update_next_predicate_state (void)
5223{
5224 long pred_mask = vpt_block_state.predicate_mask;
5225 long mask_for_insn = 0;
5226
5227 switch (vpt_block_state.current_insn_num)
5228 {
5229 case 1:
5230 mask_for_insn = 8;
5231 break;
5232
5233 case 2:
5234 mask_for_insn = 4;
5235 break;
5236
5237 case 3:
5238 mask_for_insn = 2;
5239 break;
5240
5241 case 4:
5242 return PRED_NONE;
5243 }
5244
5245 if (pred_mask & mask_for_insn)
5246 return invert_next_predicate_state (vpt_block_state.next_pred_state);
5247 else
5248 return vpt_block_state.next_pred_state;
5249}
5250
5251static void
5252update_vpt_block_state (void)
5253{
5254 vpt_block_state.current_insn_num++;
5255 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
5256 {
5257 /* No more instructions to process in vpt block. */
5258 mark_outside_vpt_block ();
5259 return;
5260 }
5261
5262 vpt_block_state.next_pred_state = update_next_predicate_state ();
5263}
8f06b2d8 5264
16980d0b
JB		 5265/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5266 Returns pointer to following character of the format string and
5267 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 5268 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 5269
5270static const char *
fe56b6ce
NC		 5271arm_decode_bitfield (const char *ptr,
5272 unsigned long insn,
5273 unsigned long *valuep,
5274 int *widthp)
16980d0b
JB		 5275{
5276 unsigned long value = 0;
5277 int width = 0;
43e65147
L		 5278
5279 do
16980d0b
JB		 5280 {
5281 int start, end;
5282 int bits;
5283
5284 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
5285 start = start * 10 + *ptr - '0';
5286 if (*ptr == '-')
5287 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
5288 end = end * 10 + *ptr - '0';
5289 else
5290 end = start;
5291 bits = end - start;
5292 if (bits < 0)
5293 abort ();
5294 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
5295 width += bits + 1;
5296 }
5297 while (*ptr++ == ',');
5298 *valuep = value;
5299 if (widthp)
5300 *widthp = width;
5301 return ptr - 1;
5302}
5303
8f06b2d8 5304static void
37b37b2d 5305arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 5306 bfd_boolean print_shift)
8f06b2d8
PB		 5307{
5308 func (stream, "%s", arm_regnames[given & 0xf]);
5309
5310 if ((given & 0xff0) != 0)
5311 {
5312 if ((given & 0x10) == 0)
5313 {
5314 int amount = (given & 0xf80) >> 7;
5315 int shift = (given & 0x60) >> 5;
5316
5317 if (amount == 0)
5318 {
5319 if (shift == 3)
5320 {
5321 func (stream, ", rrx");
5322 return;
5323 }
5324
5325 amount = 32;
5326 }
5327
37b37b2d
RE		 5328 if (print_shift)
5329 func (stream, ", %s #%d", arm_shift[shift], amount);
5330 else
5331 func (stream, ", #%d", amount);
8f06b2d8 5332 }
74bdfecf 5333 else if ((given & 0x80) == 0x80)
aefd8a40 5334 func (stream, "\t; <illegal shifter operand>");
37b37b2d 5335 else if (print_shift)
8f06b2d8
PB		 5336 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
5337 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 5338 else
5339 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 5340 }
5341}
5342
73cd51e5
AV		 5343/* Return TRUE if the MATCHED_INSN can be inside an IT block. */
5344
5345static bfd_boolean
5346is_mve_okay_in_it (enum mve_instructions matched_insn)
5347{
c507f10b
AV		 5348 switch (matched_insn)
5349 {
5350 case MVE_VMOV_GP_TO_VEC_LANE:
5351 case MVE_VMOV2_VEC_LANE_TO_GP:
5352 case MVE_VMOV2_GP_TO_VEC_LANE:
5353 case MVE_VMOV_VEC_LANE_TO_GP:
23d00a41
SD		 5354 case MVE_LSLL:
5355 case MVE_LSLLI:
5356 case MVE_LSRL:
5357 case MVE_ASRL:
5358 case MVE_ASRLI:
5359 case MVE_SQRSHRL:
5360 case MVE_SQRSHR:
5361 case MVE_UQRSHL:
5362 case MVE_UQRSHLL:
5363 case MVE_UQSHL:
5364 case MVE_UQSHLL:
5365 case MVE_URSHRL:
5366 case MVE_URSHR:
5367 case MVE_SRSHRL:
5368 case MVE_SRSHR:
5369 case MVE_SQSHLL:
5370 case MVE_SQSHL:
c507f10b
AV		 5371 return TRUE;
5372 default:
5373 return FALSE;
5374 }
73cd51e5
AV		 5375}
5376
5377static bfd_boolean
5378is_mve_architecture (struct disassemble_info *info)
5379{
5380 struct arm_private_data *private_data = info->private_data;
5381 arm_feature_set allowed_arches = private_data->features;
5382
5383 arm_feature_set arm_ext_v8_1m_main
5384 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
5385
5386 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
5387 && !ARM_CPU_IS_ANY (allowed_arches))
5388 return TRUE;
5389 else
5390 return FALSE;
5391}
5392
143275ea
AV		 5393static bfd_boolean
5394is_vpt_instruction (long given)
5395{
5396
5397 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
5398 if ((given & 0x0040e000) == 0)
5399 return FALSE;
5400
5401 /* VPT floating point T1 variant. */
5402 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
5403 /* VPT floating point T2 variant. */
5404 || ((given & 0xefb10f50) == 0xee310f40)
5405 /* VPT vector T1 variant. */
5406 || ((given & 0xff811f51) == 0xfe010f00)
5407 /* VPT vector T2 variant. */
5408 || ((given & 0xff811f51) == 0xfe010f01
5409 && ((given & 0x300000) != 0x300000))
5410 /* VPT vector T3 variant. */
5411 || ((given & 0xff811f50) == 0xfe011f00)
5412 /* VPT vector T4 variant. */
5413 || ((given & 0xff811f70) == 0xfe010f40)
5414 /* VPT vector T5 variant. */
5415 || ((given & 0xff811f70) == 0xfe010f60)
5416 /* VPT vector T6 variant. */
5417 || ((given & 0xff811f50) == 0xfe011f40)
5418 /* VPST vector T variant. */
5419 || ((given & 0xffbf1fff) == 0xfe310f4d))
5420 return TRUE;
5421 else
5422 return FALSE;
5423}
5424
73cd51e5
AV		 5425/* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5426 and ending bitfield = END. END must be greater than START. */
5427
5428static unsigned long
5429arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
5430{
5431 int bits = end - start;
5432
5433 if (bits < 0)
5434 abort ();
5435
5436 return ((given >> start) & ((2ul << bits) - 1));
5437}
5438
5439/* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5440 START:END and START2:END2. END/END2 must be greater than
5441 START/START2. */
5442
5443static unsigned long
5444arm_decode_field_multiple (unsigned long given, unsigned int start,
5445 unsigned int end, unsigned int start2,
5446 unsigned int end2)
5447{
5448 int bits = end - start;
5449 int bits2 = end2 - start2;
5450 unsigned long value = 0;
5451 int width = 0;
5452
5453 if (bits2 < 0)
5454 abort ();
5455
5456 value = arm_decode_field (given, start, end);
5457 width += bits + 1;
5458
5459 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
5460 return value;
5461}
5462
5463/* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5464 This helps us decode instructions that change mnemonic depending on specific
5465 operand values/encodings. */
5466
5467static bfd_boolean
5468is_mve_encoding_conflict (unsigned long given,
5469 enum mve_instructions matched_insn)
5470{
143275ea
AV		 5471 switch (matched_insn)
5472 {
5473 case MVE_VPST:
5474 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5475 return TRUE;
5476 else
5477 return FALSE;
5478
5479 case MVE_VPT_FP_T1:
5480 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5481 return TRUE;
5482 if ((arm_decode_field (given, 12, 12) == 0)
5483 && (arm_decode_field (given, 0, 0) == 1))
5484 return TRUE;
5485 return FALSE;
5486
5487 case MVE_VPT_FP_T2:
5488 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5489 return TRUE;
5490 if (arm_decode_field (given, 0, 3) == 0xd)
5491 return TRUE;
5492 return FALSE;
5493
5494 case MVE_VPT_VEC_T1:
5495 case MVE_VPT_VEC_T2:
5496 case MVE_VPT_VEC_T3:
5497 case MVE_VPT_VEC_T4:
5498 case MVE_VPT_VEC_T5:
5499 case MVE_VPT_VEC_T6:
5500 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5501 return TRUE;
5502 if (arm_decode_field (given, 20, 21) == 3)
5503 return TRUE;
5504 return FALSE;
5505
5506 case MVE_VCMP_FP_T1:
5507 if ((arm_decode_field (given, 12, 12) == 0)
5508 && (arm_decode_field (given, 0, 0) == 1))
5509 return TRUE;
5510 else
5511 return FALSE;
5512
5513 case MVE_VCMP_FP_T2:
5514 if (arm_decode_field (given, 0, 3) == 0xd)
5515 return TRUE;
5516 else
5517 return FALSE;
5518
14b456f2
AV		 5519 case MVE_VQADD_T2:
5520 case MVE_VQSUB_T2:
f49bb598
AV		 5521 case MVE_VMUL_VEC_T2:
5522 case MVE_VMULH:
5523 case MVE_VRMULH:
56858bea
AV		 5524 case MVE_VMLA:
5525 case MVE_VMAX:
5526 case MVE_VMIN:
e523f101 5527 case MVE_VBRSR:
66dcaa5d
AV		 5528 case MVE_VADD_VEC_T2:
5529 case MVE_VSUB_VEC_T2:
5530 case MVE_VABAV:
ed63aa17
AV		 5531 case MVE_VQRSHL_T1:
5532 case MVE_VQSHL_T4:
5533 case MVE_VRSHL_T1:
5534 case MVE_VSHL_T3:
897b9bbc
AV		 5535 case MVE_VCADD_VEC:
5536 case MVE_VHCADD:
1c8f2df8
AV		 5537 case MVE_VDDUP:
5538 case MVE_VIDUP:
d3b63143
AV		 5539 case MVE_VQRDMLADH:
5540 case MVE_VQDMLAH:
5541 case MVE_VQRDMLAH:
5542 case MVE_VQDMLASH:
5543 case MVE_VQRDMLASH:
5544 case MVE_VQDMLSDH:
5545 case MVE_VQRDMLSDH:
5546 case MVE_VQDMULH_T3:
5547 case MVE_VQRDMULH_T4:
5548 case MVE_VQDMLADH:
5549 case MVE_VMLAS:
14925797 5550 case MVE_VMULL_INT:
9743db03
AV		 5551 case MVE_VHADD_T2:
5552 case MVE_VHSUB_T2:
143275ea
AV		 5553 case MVE_VCMP_VEC_T1:
5554 case MVE_VCMP_VEC_T2:
5555 case MVE_VCMP_VEC_T3:
5556 case MVE_VCMP_VEC_T4:
5557 case MVE_VCMP_VEC_T5:
5558 case MVE_VCMP_VEC_T6:
5559 if (arm_decode_field (given, 20, 21) == 3)
5560 return TRUE;
5561 else
5562 return FALSE;
5563
04d54ace
AV		 5564 case MVE_VLD2:
5565 case MVE_VLD4:
5566 case MVE_VST2:
5567 case MVE_VST4:
5568 if (arm_decode_field (given, 7, 8) == 3)
5569 return TRUE;
5570 else
5571 return FALSE;
5572
aef6d006
AV		 5573 case MVE_VSTRB_T1:
5574 case MVE_VSTRH_T2:
5575 if ((arm_decode_field (given, 24, 24) == 0)
5576 && (arm_decode_field (given, 21, 21) == 0))
5577 {
5578 return TRUE;
5579 }
5580 else if ((arm_decode_field (given, 7, 8) == 3))
5581 return TRUE;
5582 else
5583 return FALSE;
5584
5585 case MVE_VSTRB_T5:
5586 case MVE_VSTRH_T6:
5587 case MVE_VSTRW_T7:
5588 if ((arm_decode_field (given, 24, 24) == 0)
5589 && (arm_decode_field (given, 21, 21) == 0))
5590 {
5591 return TRUE;
5592 }
5593 else
5594 return FALSE;
5595
bf0b396d
AV		 5596 case MVE_VCVT_FP_FIX_VEC:
5597 return (arm_decode_field (given, 16, 21) & 0x38) == 0;
5598
c507f10b
AV		 5599 case MVE_VBIC_IMM:
5600 case MVE_VORR_IMM:
5601 {
5602 unsigned long cmode = arm_decode_field (given, 8, 11);
5603
5604 if ((cmode & 1) == 0)
5605 return TRUE;
5606 else if ((cmode & 0xc) == 0xc)
5607 return TRUE;
5608 else
5609 return FALSE;
5610 }
5611
5612 case MVE_VMVN_IMM:
5613 {
5614 unsigned long cmode = arm_decode_field (given, 8, 11);
5615
5616 if ((cmode & 9) == 1)
5617 return TRUE;
5618 else if ((cmode & 5) == 1)
5619 return TRUE;
5620 else if ((cmode & 0xe) == 0xe)
5621 return TRUE;
5622 else
5623 return FALSE;
5624 }
5625
5626 case MVE_VMOV_IMM_TO_VEC:
5627 if ((arm_decode_field (given, 5, 5) == 1)
5628 && (arm_decode_field (given, 8, 11) != 0xe))
5629 return TRUE;
5630 else
5631 return FALSE;
5632
14925797
AV		 5633 case MVE_VMOVL:
5634 {
5635 unsigned long size = arm_decode_field (given, 19, 20);
5636 if ((size == 0) || (size == 3))
5637 return TRUE;
5638 else
5639 return FALSE;
5640 }
5641
56858bea
AV		 5642 case MVE_VMAXA:
5643 case MVE_VMINA:
5644 case MVE_VMAXV:
5645 case MVE_VMAXAV:
5646 case MVE_VMINV:
5647 case MVE_VMINAV:
ed63aa17
AV		 5648 case MVE_VQRSHL_T2:
5649 case MVE_VQSHL_T1:
5650 case MVE_VRSHL_T2:
5651 case MVE_VSHL_T2:
5652 case MVE_VSHLL_T2:
d3b63143 5653 case MVE_VADDV:
14925797
AV		 5654 case MVE_VMOVN:
5655 case MVE_VQMOVUN:
5656 case MVE_VQMOVN:
5657 if (arm_decode_field (given, 18, 19) == 3)
5658 return TRUE;
5659 else
5660 return FALSE;
5661
d3b63143
AV		 5662 case MVE_VMLSLDAV:
5663 case MVE_VRMLSLDAVH:
5664 case MVE_VMLALDAV:
5665 case MVE_VADDLV:
5666 if (arm_decode_field (given, 20, 22) == 7)
5667 return TRUE;
5668 else
5669 return FALSE;
5670
5671 case MVE_VRMLALDAVH:
5672 if ((arm_decode_field (given, 20, 22) & 6) == 6)
5673 return TRUE;
5674 else
5675 return FALSE;
5676
1c8f2df8
AV		 5677 case MVE_VDWDUP:
5678 case MVE_VIWDUP:
5679 if ((arm_decode_field (given, 20, 21) == 3)
5680 || (arm_decode_field (given, 1, 3) == 7))
5681 return TRUE;
5682 else
5683 return FALSE;
5684
ed63aa17
AV		 5685
5686 case MVE_VSHLL_T1:
5687 if (arm_decode_field (given, 16, 18) == 0)
5688 {
5689 unsigned long sz = arm_decode_field (given, 19, 20);
5690
5691 if ((sz == 1) || (sz == 2))
5692 return TRUE;
5693 else
5694 return FALSE;
5695 }
5696 else
5697 return FALSE;
5698
5699 case MVE_VQSHL_T2:
5700 case MVE_VQSHLU_T3:
5701 case MVE_VRSHR:
5702 case MVE_VSHL_T1:
5703 case MVE_VSHR:
5704 case MVE_VSLI:
5705 case MVE_VSRI:
5706 if (arm_decode_field (given, 19, 21) == 0)
5707 return TRUE;
5708 else
5709 return FALSE;
5710
e523f101
AV		 5711 case MVE_VCTP:
5712 if (arm_decode_field (given, 16, 19) == 0xf)
5713 return TRUE;
5714 else
5715 return FALSE;
5716
23d00a41
SD		 5717 case MVE_ASRLI:
5718 case MVE_ASRL:
5719 case MVE_LSLLI:
5720 case MVE_LSLL:
5721 case MVE_LSRL:
5722 case MVE_SQRSHRL:
5723 case MVE_SQSHLL:
5724 case MVE_SRSHRL:
5725 case MVE_UQRSHLL:
5726 case MVE_UQSHLL:
5727 case MVE_URSHRL:
5728 if (arm_decode_field (given, 9, 11) == 0x7)
5729 return TRUE;
5730 else
5731 return FALSE;
5732
e39c1607
SD		 5733 case MVE_CSINC:
5734 case MVE_CSINV:
5735 {
5736 unsigned long rm, rn;
5737 rm = arm_decode_field (given, 0, 3);
5738 rn = arm_decode_field (given, 16, 19);
5739 /* CSET/CSETM. */
5740 if (rm == 0xf && rn == 0xf)
5741 return TRUE;
5742 /* CINC/CINV. */
5743 else if (rn == rm && rn != 0xf)
5744 return TRUE;
5745 }
5746 /* Fall through. */
5747 case MVE_CSEL:
5748 case MVE_CSNEG:
5749 if (arm_decode_field (given, 0, 3) == 0xd)
5750 return TRUE;
5751 /* CNEG. */
5752 else if (matched_insn == MVE_CSNEG)
5753 if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19))
5754 return TRUE;
5755 return FALSE;
5756
143275ea 5757 default:
66dcaa5d
AV		 5758 case MVE_VADD_FP_T1:
5759 case MVE_VADD_FP_T2:
5760 case MVE_VADD_VEC_T1:
143275ea
AV		 5761 return FALSE;
5762
5763 }
73cd51e5
AV		 5764}
5765
aef6d006
AV		 5766static void
5767print_mve_vld_str_addr (struct disassemble_info *info,
5768 unsigned long given,
5769 enum mve_instructions matched_insn)
5770{
5771 void *stream = info->stream;
5772 fprintf_ftype func = info->fprintf_func;
5773
5774 unsigned long p, w, gpr, imm, add, mod_imm;
5775
5776 imm = arm_decode_field (given, 0, 6);
5777 mod_imm = imm;
5778
5779 switch (matched_insn)
5780 {
5781 case MVE_VLDRB_T1:
5782 case MVE_VSTRB_T1:
5783 gpr = arm_decode_field (given, 16, 18);
5784 break;
5785
5786 case MVE_VLDRH_T2:
5787 case MVE_VSTRH_T2:
5788 gpr = arm_decode_field (given, 16, 18);
5789 mod_imm = imm << 1;
5790 break;
5791
5792 case MVE_VLDRH_T6:
5793 case MVE_VSTRH_T6:
5794 gpr = arm_decode_field (given, 16, 19);
5795 mod_imm = imm << 1;
5796 break;
5797
5798 case MVE_VLDRW_T7:
5799 case MVE_VSTRW_T7:
5800 gpr = arm_decode_field (given, 16, 19);
5801 mod_imm = imm << 2;
5802 break;
5803
5804 case MVE_VLDRB_T5:
5805 case MVE_VSTRB_T5:
5806 gpr = arm_decode_field (given, 16, 19);
5807 break;
5808
5809 default:
5810 return;
5811 }
5812
5813 p = arm_decode_field (given, 24, 24);
5814 w = arm_decode_field (given, 21, 21);
5815
5816 add = arm_decode_field (given, 23, 23);
5817
5818 char * add_sub;
5819
5820 /* Don't print anything for '+' as it is implied. */
5821 if (add == 1)
5822 add_sub = "";
5823 else
5824 add_sub = "-";
5825
5826 if (p == 1)
5827 {
5828 /* Offset mode. */
5829 if (w == 0)
5830 func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm);
5831 /* Pre-indexed mode. */
5832 else
5833 func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm);
5834 }
5835 else if ((p == 0) && (w == 1))
5836 /* Post-index mode. */
5837 func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm);
5838}
5839
73cd51e5
AV		 5840/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5841 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5842 this encoding is undefined. */
5843
5844static bfd_boolean
5845is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
5846 enum mve_undefined *undefined_code)
5847{
5848 *undefined_code = UNDEF_NONE;
5849
9743db03
AV		 5850 switch (matched_insn)
5851 {
5852 case MVE_VDUP:
5853 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
5854 {
5855 *undefined_code = UNDEF_SIZE_3;
5856 return TRUE;
5857 }
5858 else
5859 return FALSE;
5860
14b456f2
AV		 5861 case MVE_VQADD_T1:
5862 case MVE_VQSUB_T1:
f49bb598 5863 case MVE_VMUL_VEC_T1:
66dcaa5d
AV		 5864 case MVE_VABD_VEC:
5865 case MVE_VADD_VEC_T1:
5866 case MVE_VSUB_VEC_T1:
d3b63143
AV		 5867 case MVE_VQDMULH_T1:
5868 case MVE_VQRDMULH_T2:
9743db03
AV		 5869 case MVE_VRHADD:
5870 case MVE_VHADD_T1:
5871 case MVE_VHSUB_T1:
5872 if (arm_decode_field (given, 20, 21) == 3)
5873 {
5874 *undefined_code = UNDEF_SIZE_3;
5875 return TRUE;
5876 }
5877 else
5878 return FALSE;
5879
aef6d006
AV		 5880 case MVE_VLDRB_T1:
5881 if (arm_decode_field (given, 7, 8) == 3)
5882 {
5883 *undefined_code = UNDEF_SIZE_3;
5884 return TRUE;
5885 }
5886 else
5887 return FALSE;
5888
5889 case MVE_VLDRH_T2:
5890 if (arm_decode_field (given, 7, 8) <= 1)
5891 {
5892 *undefined_code = UNDEF_SIZE_LE_1;
5893 return TRUE;
5894 }
5895 else
5896 return FALSE;
5897
5898 case MVE_VSTRB_T1:
5899 if ((arm_decode_field (given, 7, 8) == 0))
5900 {
5901 *undefined_code = UNDEF_SIZE_0;
5902 return TRUE;
5903 }
5904 else
5905 return FALSE;
5906
5907 case MVE_VSTRH_T2:
5908 if ((arm_decode_field (given, 7, 8) <= 1))
5909 {
5910 *undefined_code = UNDEF_SIZE_LE_1;
5911 return TRUE;
5912 }
5913 else
5914 return FALSE;
5915
ef1576a1
AV		 5916 case MVE_VLDRB_GATHER_T1:
5917 if (arm_decode_field (given, 7, 8) == 3)
5918 {
5919 *undefined_code = UNDEF_SIZE_3;
5920 return TRUE;
5921 }
5922 else if ((arm_decode_field (given, 28, 28) == 0)
5923 && (arm_decode_field (given, 7, 8) == 0))
5924 {
5925 *undefined_code = UNDEF_NOT_UNS_SIZE_0;
5926 return TRUE;
5927 }
5928 else
5929 return FALSE;
5930
5931 case MVE_VLDRH_GATHER_T2:
5932 if (arm_decode_field (given, 7, 8) == 3)
5933 {
5934 *undefined_code = UNDEF_SIZE_3;
5935 return TRUE;
5936 }
5937 else if ((arm_decode_field (given, 28, 28) == 0)
5938 && (arm_decode_field (given, 7, 8) == 1))
5939 {
5940 *undefined_code = UNDEF_NOT_UNS_SIZE_1;
5941 return TRUE;
5942 }
5943 else if (arm_decode_field (given, 7, 8) == 0)
5944 {
5945 *undefined_code = UNDEF_SIZE_0;
5946 return TRUE;
5947 }
5948 else
5949 return FALSE;
5950
5951 case MVE_VLDRW_GATHER_T3:
5952 if (arm_decode_field (given, 7, 8) != 2)
5953 {
5954 *undefined_code = UNDEF_SIZE_NOT_2;
5955 return TRUE;
5956 }
5957 else if (arm_decode_field (given, 28, 28) == 0)
5958 {
5959 *undefined_code = UNDEF_NOT_UNSIGNED;
5960 return TRUE;
5961 }
5962 else
5963 return FALSE;
5964
5965 case MVE_VLDRD_GATHER_T4:
5966 if (arm_decode_field (given, 7, 8) != 3)
5967 {
5968 *undefined_code = UNDEF_SIZE_NOT_3;
5969 return TRUE;
5970 }
5971 else if (arm_decode_field (given, 28, 28) == 0)
5972 {
5973 *undefined_code = UNDEF_NOT_UNSIGNED;
5974 return TRUE;
5975 }
5976 else
5977 return FALSE;
5978
5979 case MVE_VSTRB_SCATTER_T1:
5980 if (arm_decode_field (given, 7, 8) == 3)
5981 {
5982 *undefined_code = UNDEF_SIZE_3;
5983 return TRUE;
5984 }
5985 else
5986 return FALSE;
5987
5988 case MVE_VSTRH_SCATTER_T2:
5989 {
5990 unsigned long size = arm_decode_field (given, 7, 8);
5991 if (size == 3)
5992 {
5993 *undefined_code = UNDEF_SIZE_3;
5994 return TRUE;
5995 }
5996 else if (size == 0)
5997 {
5998 *undefined_code = UNDEF_SIZE_0;
5999 return TRUE;
6000 }
6001 else
6002 return FALSE;
6003 }
6004
6005 case MVE_VSTRW_SCATTER_T3:
6006 if (arm_decode_field (given, 7, 8) != 2)
6007 {
6008 *undefined_code = UNDEF_SIZE_NOT_2;
6009 return TRUE;
6010 }
6011 else
6012 return FALSE;
6013
6014 case MVE_VSTRD_SCATTER_T4:
6015 if (arm_decode_field (given, 7, 8) != 3)
6016 {
6017 *undefined_code = UNDEF_SIZE_NOT_3;
6018 return TRUE;
6019 }
6020 else
6021 return FALSE;
6022
bf0b396d
AV		 6023 case MVE_VCVT_FP_FIX_VEC:
6024 {
6025 unsigned long imm6 = arm_decode_field (given, 16, 21);
6026 if ((imm6 & 0x20) == 0)
6027 {
6028 *undefined_code = UNDEF_VCVT_IMM6;
6029 return TRUE;
6030 }
6031
6032 if ((arm_decode_field (given, 9, 9) == 0)
6033 && ((imm6 & 0x30) == 0x20))
6034 {
6035 *undefined_code = UNDEF_VCVT_FSI_IMM6;
6036 return TRUE;
6037 }
6038
6039 return FALSE;
6040 }
6041
f49bb598 6042 case MVE_VNEG_FP:
66dcaa5d 6043 case MVE_VABS_FP:
bf0b396d
AV		 6044 case MVE_VCVT_BETWEEN_FP_INT:
6045 case MVE_VCVT_FROM_FP_TO_INT:
6046 {
6047 unsigned long size = arm_decode_field (given, 18, 19);
6048 if (size == 0)
6049 {
6050 *undefined_code = UNDEF_SIZE_0;
6051 return TRUE;
6052 }
6053 else if (size == 3)
6054 {
6055 *undefined_code = UNDEF_SIZE_3;
6056 return TRUE;
6057 }
6058 else
6059 return FALSE;
6060 }
6061
c507f10b
AV		 6062 case MVE_VMOV_VEC_LANE_TO_GP:
6063 {
6064 unsigned long op1 = arm_decode_field (given, 21, 22);
6065 unsigned long op2 = arm_decode_field (given, 5, 6);
6066 unsigned long u = arm_decode_field (given, 23, 23);
6067
6068 if ((op2 == 0) && (u == 1))
6069 {
6070 if ((op1 == 0) || (op1 == 1))
6071 {
6072 *undefined_code = UNDEF_BAD_U_OP1_OP2;
6073 return TRUE;
6074 }
6075 else
6076 return FALSE;
6077 }
6078 else if (op2 == 2)
6079 {
6080 if ((op1 == 0) || (op1 == 1))
6081 {
6082 *undefined_code = UNDEF_BAD_OP1_OP2;
6083 return TRUE;
6084 }
6085 else
6086 return FALSE;
6087 }
6088
6089 return FALSE;
6090 }
6091
6092 case MVE_VMOV_GP_TO_VEC_LANE:
6093 if (arm_decode_field (given, 5, 6) == 2)
6094 {
6095 unsigned long op1 = arm_decode_field (given, 21, 22);
6096 if ((op1 == 0) || (op1 == 1))
6097 {
6098 *undefined_code = UNDEF_BAD_OP1_OP2;
6099 return TRUE;
6100 }
6101 else
6102 return FALSE;
6103 }
6104 else
6105 return FALSE;
6106
6107 case MVE_VMOV_IMM_TO_VEC:
6108 if (arm_decode_field (given, 5, 5) == 0)
6109 {
6110 unsigned long cmode = arm_decode_field (given, 8, 11);
6111
6112 if (((cmode & 9) == 1) || ((cmode & 5) == 1))
6113 {
6114 *undefined_code = UNDEF_OP_0_BAD_CMODE;
6115 return TRUE;
6116 }
6117 else
6118 return FALSE;
6119 }
6120 else
6121 return FALSE;
6122
ed63aa17 6123 case MVE_VSHLL_T2:
14925797
AV		 6124 case MVE_VMOVN:
6125 if (arm_decode_field (given, 18, 19) == 2)
6126 {
6127 *undefined_code = UNDEF_SIZE_2;
6128 return TRUE;
6129 }
6130 else
6131 return FALSE;
6132
d3b63143
AV		 6133 case MVE_VRMLALDAVH:
6134 case MVE_VMLADAV_T1:
6135 case MVE_VMLADAV_T2:
6136 case MVE_VMLALDAV:
6137 if ((arm_decode_field (given, 28, 28) == 1)
6138 && (arm_decode_field (given, 12, 12) == 1))
6139 {
6140 *undefined_code = UNDEF_XCHG_UNS;
6141 return TRUE;
6142 }
6143 else
6144 return FALSE;
6145
ed63aa17
AV		 6146 case MVE_VQSHRN:
6147 case MVE_VQSHRUN:
6148 case MVE_VSHLL_T1:
6149 case MVE_VSHRN:
6150 {
6151 unsigned long sz = arm_decode_field (given, 19, 20);
6152 if (sz == 1)
6153 return FALSE;
6154 else if ((sz & 2) == 2)
6155 return FALSE;
6156 else
6157 {
6158 *undefined_code = UNDEF_SIZE;
6159 return TRUE;
6160 }
6161 }
6162 break;
6163
6164 case MVE_VQSHL_T2:
6165 case MVE_VQSHLU_T3:
6166 case MVE_VRSHR:
6167 case MVE_VSHL_T1:
6168 case MVE_VSHR:
6169 case MVE_VSLI:
6170 case MVE_VSRI:
6171 {
6172 unsigned long sz = arm_decode_field (given, 19, 21);
6173 if ((sz & 7) == 1)
6174 return FALSE;
6175 else if ((sz & 6) == 2)
6176 return FALSE;
6177 else if ((sz & 4) == 4)
6178 return FALSE;
6179 else
6180 {
6181 *undefined_code = UNDEF_SIZE;
6182 return TRUE;
6183 }
6184 }
6185
6186 case MVE_VQRSHRN:
6187 case MVE_VQRSHRUN:
6188 if (arm_decode_field (given, 19, 20) == 0)
6189 {
6190 *undefined_code = UNDEF_SIZE_0;
6191 return TRUE;
6192 }
6193 else
6194 return FALSE;
6195
66dcaa5d
AV		 6196 case MVE_VABS_VEC:
6197 if (arm_decode_field (given, 18, 19) == 3)
6198 {
6199 *undefined_code = UNDEF_SIZE_3;
6200 return TRUE;
6201 }
6202 else
6203 return FALSE;
6204
14b456f2
AV		 6205 case MVE_VQNEG:
6206 case MVE_VQABS:
f49bb598 6207 case MVE_VNEG_VEC:
e523f101
AV		 6208 case MVE_VCLS:
6209 case MVE_VCLZ:
6210 if (arm_decode_field (given, 18, 19) == 3)
6211 {
6212 *undefined_code = UNDEF_SIZE_3;
6213 return TRUE;
6214 }
6215 else
6216 return FALSE;
6217
14b456f2
AV		 6218 case MVE_VREV16:
6219 if (arm_decode_field (given, 18, 19) == 0)
6220 return FALSE;
6221 else
6222 {
6223 *undefined_code = UNDEF_SIZE_NOT_0;
6224 return TRUE;
6225 }
6226
6227 case MVE_VREV32:
6228 {
6229 unsigned long size = arm_decode_field (given, 18, 19);
6230 if ((size & 2) == 2)
6231 {
6232 *undefined_code = UNDEF_SIZE_2;
6233 return TRUE;
6234 }
6235 else
6236 return FALSE;
6237 }
6238
6239 case MVE_VREV64:
6240 if (arm_decode_field (given, 18, 19) != 3)
6241 return FALSE;
6242 else
6243 {
6244 *undefined_code = UNDEF_SIZE_3;
6245 return TRUE;
6246 }
6247
9743db03
AV		 6248 default:
6249 return FALSE;
6250 }
73cd51e5
AV		 6251}
6252
6253/* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6254 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
6255 why this encoding is unpredictable. */
6256
6257static bfd_boolean
6258is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
6259 enum mve_unpredictable *unpredictable_code)
6260{
6261 *unpredictable_code = UNPRED_NONE;
6262
143275ea
AV		 6263 switch (matched_insn)
6264 {
6265 case MVE_VCMP_FP_T2:
6266 case MVE_VPT_FP_T2:
6267 if ((arm_decode_field (given, 12, 12) == 0)
6268 && (arm_decode_field (given, 5, 5) == 1))
6269 {
6270 *unpredictable_code = UNPRED_FCA_0_FCB_1;
6271 return TRUE;
6272 }
6273 else
6274 return FALSE;
73cd51e5 6275
143275ea
AV		 6276 case MVE_VPT_VEC_T4:
6277 case MVE_VPT_VEC_T5:
6278 case MVE_VPT_VEC_T6:
6279 case MVE_VCMP_VEC_T4:
6280 case MVE_VCMP_VEC_T5:
6281 case MVE_VCMP_VEC_T6:
6282 if (arm_decode_field (given, 0, 3) == 0xd)
6283 {
6284 *unpredictable_code = UNPRED_R13;
6285 return TRUE;
6286 }
6287 else
6288 return FALSE;
c1e26897 6289
9743db03
AV		 6290 case MVE_VDUP:
6291 {
6292 unsigned long gpr = arm_decode_field (given, 12, 15);
6293 if (gpr == 0xd)
6294 {
6295 *unpredictable_code = UNPRED_R13;
6296 return TRUE;
6297 }
6298 else if (gpr == 0xf)
6299 {
6300 *unpredictable_code = UNPRED_R15;
6301 return TRUE;
6302 }
6303
6304 return FALSE;
6305 }
6306
14b456f2
AV		 6307 case MVE_VQADD_T2:
6308 case MVE_VQSUB_T2:
f49bb598
AV		 6309 case MVE_VMUL_FP_T2:
6310 case MVE_VMUL_VEC_T2:
56858bea 6311 case MVE_VMLA:
e523f101 6312 case MVE_VBRSR:
66dcaa5d
AV		 6313 case MVE_VADD_FP_T2:
6314 case MVE_VSUB_FP_T2:
6315 case MVE_VADD_VEC_T2:
6316 case MVE_VSUB_VEC_T2:
ed63aa17
AV		 6317 case MVE_VQRSHL_T2:
6318 case MVE_VQSHL_T1:
6319 case MVE_VRSHL_T2:
6320 case MVE_VSHL_T2:
6321 case MVE_VSHLC:
d3b63143
AV		 6322 case MVE_VQDMLAH:
6323 case MVE_VQRDMLAH:
6324 case MVE_VQDMLASH:
6325 case MVE_VQRDMLASH:
6326 case MVE_VQDMULH_T3:
6327 case MVE_VQRDMULH_T4:
6328 case MVE_VMLAS:
9743db03
AV		 6329 case MVE_VFMA_FP_SCALAR:
6330 case MVE_VFMAS_FP_SCALAR:
6331 case MVE_VHADD_T2:
6332 case MVE_VHSUB_T2:
6333 {
6334 unsigned long gpr = arm_decode_field (given, 0, 3);
6335 if (gpr == 0xd)
6336 {
6337 *unpredictable_code = UNPRED_R13;
6338 return TRUE;
6339 }
6340 else if (gpr == 0xf)
6341 {
6342 *unpredictable_code = UNPRED_R15;
6343 return TRUE;
6344 }
6345
6346 return FALSE;
6347 }
6348
04d54ace
AV		 6349 case MVE_VLD2:
6350 case MVE_VST2:
6351 {
6352 unsigned long rn = arm_decode_field (given, 16, 19);
6353
6354 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6355 {
6356 *unpredictable_code = UNPRED_R13_AND_WB;
6357 return TRUE;
6358 }
6359
6360 if (rn == 0xf)
6361 {
6362 *unpredictable_code = UNPRED_R15;
6363 return TRUE;
6364 }
6365
6366 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
6367 {
6368 *unpredictable_code = UNPRED_Q_GT_6;
6369 return TRUE;
6370 }
6371 else
6372 return FALSE;
6373 }
6374
6375 case MVE_VLD4:
6376 case MVE_VST4:
6377 {
6378 unsigned long rn = arm_decode_field (given, 16, 19);
6379
6380 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6381 {
6382 *unpredictable_code = UNPRED_R13_AND_WB;
6383 return TRUE;
6384 }
6385
6386 if (rn == 0xf)
6387 {
6388 *unpredictable_code = UNPRED_R15;
6389 return TRUE;
6390 }
6391
6392 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
6393 {
6394 *unpredictable_code = UNPRED_Q_GT_4;
6395 return TRUE;
6396 }
6397 else
6398 return FALSE;
6399 }
6400
aef6d006
AV		 6401 case MVE_VLDRB_T5:
6402 case MVE_VLDRH_T6:
6403 case MVE_VLDRW_T7:
6404 case MVE_VSTRB_T5:
6405 case MVE_VSTRH_T6:
6406 case MVE_VSTRW_T7:
6407 {
6408 unsigned long rn = arm_decode_field (given, 16, 19);
6409
6410 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6411 {
6412 *unpredictable_code = UNPRED_R13_AND_WB;
6413 return TRUE;
6414 }
6415 else if (rn == 0xf)
6416 {
6417 *unpredictable_code = UNPRED_R15;
6418 return TRUE;
6419 }
6420 else
6421 return FALSE;
6422 }
6423
ef1576a1
AV		 6424 case MVE_VLDRB_GATHER_T1:
6425 if (arm_decode_field (given, 0, 0) == 1)
6426 {
6427 *unpredictable_code = UNPRED_OS;
6428 return TRUE;
6429 }
6430
6431 /* fall through. */
6432 /* To handle common code with T2-T4 variants. */
6433 case MVE_VLDRH_GATHER_T2:
6434 case MVE_VLDRW_GATHER_T3:
6435 case MVE_VLDRD_GATHER_T4:
6436 {
6437 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6438 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6439
6440 if (qd == qm)
6441 {
6442 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6443 return TRUE;
6444 }
6445
6446 if (arm_decode_field (given, 16, 19) == 0xf)
6447 {
6448 *unpredictable_code = UNPRED_R15;
6449 return TRUE;
6450 }
6451
6452 return FALSE;
6453 }
6454
6455 case MVE_VLDRW_GATHER_T5:
6456 case MVE_VLDRD_GATHER_T6:
6457 {
6458 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6459 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
6460
6461 if (qd == qm)
6462 {
6463 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6464 return TRUE;
6465 }
6466 else
6467 return FALSE;
6468 }
6469
6470 case MVE_VSTRB_SCATTER_T1:
6471 if (arm_decode_field (given, 16, 19) == 0xf)
6472 {
6473 *unpredictable_code = UNPRED_R15;
6474 return TRUE;
6475 }
6476 else if (arm_decode_field (given, 0, 0) == 1)
6477 {
6478 *unpredictable_code = UNPRED_OS;
6479 return TRUE;
6480 }
6481 else
6482 return FALSE;
6483
6484 case MVE_VSTRH_SCATTER_T2:
6485 case MVE_VSTRW_SCATTER_T3:
6486 case MVE_VSTRD_SCATTER_T4:
6487 if (arm_decode_field (given, 16, 19) == 0xf)
6488 {
6489 *unpredictable_code = UNPRED_R15;
6490 return TRUE;
6491 }
6492 else
6493 return FALSE;
6494
c507f10b
AV		 6495 case MVE_VMOV2_VEC_LANE_TO_GP:
6496 case MVE_VMOV2_GP_TO_VEC_LANE:
bf0b396d
AV		 6497 case MVE_VCVT_BETWEEN_FP_INT:
6498 case MVE_VCVT_FROM_FP_TO_INT:
6499 {
6500 unsigned long rt = arm_decode_field (given, 0, 3);
6501 unsigned long rt2 = arm_decode_field (given, 16, 19);
6502
6503 if ((rt == 0xd) || (rt2 == 0xd))
6504 {
6505 *unpredictable_code = UNPRED_R13;
6506 return TRUE;
6507 }
6508 else if ((rt == 0xf) || (rt2 == 0xf))
6509 {
6510 *unpredictable_code = UNPRED_R15;
6511 return TRUE;
6512 }
6513 else if (rt == rt2)
6514 {
6515 *unpredictable_code = UNPRED_GP_REGS_EQUAL;
6516 return TRUE;
6517 }
6518
6519 return FALSE;
6520 }
6521
56858bea
AV		 6522 case MVE_VMAXV:
6523 case MVE_VMAXAV:
6524 case MVE_VMAXNMV_FP:
6525 case MVE_VMAXNMAV_FP:
6526 case MVE_VMINNMV_FP:
6527 case MVE_VMINNMAV_FP:
6528 case MVE_VMINV:
6529 case MVE_VMINAV:
66dcaa5d 6530 case MVE_VABAV:
c507f10b
AV		 6531 case MVE_VMOV_HFP_TO_GP:
6532 case MVE_VMOV_GP_TO_VEC_LANE:
6533 case MVE_VMOV_VEC_LANE_TO_GP:
6534 {
6535 unsigned long rda = arm_decode_field (given, 12, 15);
6536 if (rda == 0xd)
6537 {
6538 *unpredictable_code = UNPRED_R13;
6539 return TRUE;
6540 }
6541 else if (rda == 0xf)
6542 {
6543 *unpredictable_code = UNPRED_R15;
6544 return TRUE;
6545 }
6546
6547 return FALSE;
6548 }
6549
14925797
AV		 6550 case MVE_VMULL_INT:
6551 {
6552 unsigned long Qd;
6553 unsigned long Qm;
6554 unsigned long Qn;
6555
6556 if (arm_decode_field (given, 20, 21) == 2)
6557 {
6558 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6559 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6560 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6561
6562 if ((Qd == Qn) || (Qd == Qm))
6563 {
6564 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6565 return TRUE;
6566 }
6567 else
6568 return FALSE;
6569 }
6570 else
6571 return FALSE;
6572 }
6573
897b9bbc 6574 case MVE_VCMUL_FP:
14925797
AV		 6575 case MVE_VQDMULL_T1:
6576 {
6577 unsigned long Qd;
6578 unsigned long Qm;
6579 unsigned long Qn;
6580
6581 if (arm_decode_field (given, 28, 28) == 1)
6582 {
6583 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6584 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6585 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6586
6587 if ((Qd == Qn) || (Qd == Qm))
6588 {
6589 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6590 return TRUE;
6591 }
6592 else
6593 return FALSE;
6594 }
6595 else
6596 return FALSE;
6597 }
6598
6599 case MVE_VQDMULL_T2:
6600 {
6601 unsigned long gpr = arm_decode_field (given, 0, 3);
6602 if (gpr == 0xd)
6603 {
6604 *unpredictable_code = UNPRED_R13;
6605 return TRUE;
6606 }
6607 else if (gpr == 0xf)
6608 {
6609 *unpredictable_code = UNPRED_R15;
6610 return TRUE;
6611 }
6612
6613 if (arm_decode_field (given, 28, 28) == 1)
6614 {
6615 unsigned long Qd
6616 = arm_decode_field_multiple (given, 13, 15, 22, 22);
6617 unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6618
a9d96ab9 6619 if (Qd == Qn)
14925797
AV		 6620 {
6621 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6622 return TRUE;
6623 }
6624 else
6625 return FALSE;
6626 }
6627
6628 return FALSE;
6629 }
6630
d3b63143
AV		 6631 case MVE_VMLSLDAV:
6632 case MVE_VRMLSLDAVH:
6633 case MVE_VMLALDAV:
6634 case MVE_VADDLV:
6635 if (arm_decode_field (given, 20, 22) == 6)
6636 {
6637 *unpredictable_code = UNPRED_R13;
6638 return TRUE;
6639 }
6640 else
6641 return FALSE;
6642
1c8f2df8
AV		 6643 case MVE_VDWDUP:
6644 case MVE_VIWDUP:
6645 if (arm_decode_field (given, 1, 3) == 6)
6646 {
6647 *unpredictable_code = UNPRED_R13;
6648 return TRUE;
6649 }
6650 else
6651 return FALSE;
6652
897b9bbc
AV		 6653 case MVE_VCADD_VEC:
6654 case MVE_VHCADD:
6655 {
6656 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6657 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6658 if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
6659 {
6660 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6661 return TRUE;
6662 }
6663 else
6664 return FALSE;
6665 }
6666
6667 case MVE_VCADD_FP:
6668 {
6669 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6670 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6671 if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
6672 {
6673 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6674 return TRUE;
6675 }
6676 else
6677 return FALSE;
6678 }
6679
6680 case MVE_VCMLA_FP:
6681 {
6682 unsigned long Qda;
6683 unsigned long Qm;
6684 unsigned long Qn;
6685
6686 if (arm_decode_field (given, 20, 20) == 1)
6687 {
6688 Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
6689 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6690 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6691
6692 if ((Qda == Qn) || (Qda == Qm))
6693 {
6694 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6695 return TRUE;
6696 }
6697 else
6698 return FALSE;
6699 }
6700 else
6701 return FALSE;
6702
6703 }
6704
e523f101
AV		 6705 case MVE_VCTP:
6706 if (arm_decode_field (given, 16, 19) == 0xd)
6707 {
6708 *unpredictable_code = UNPRED_R13;
6709 return TRUE;
6710 }
6711 else
6712 return FALSE;
6713
14b456f2
AV		 6714 case MVE_VREV64:
6715 {
6716 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6717 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6);
6718
6719 if (qd == qm)
6720 {
6721 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6722 return TRUE;
6723 }
6724 else
6725 return FALSE;
6726 }
6727
23d00a41
SD		 6728 case MVE_LSLL:
6729 case MVE_LSLLI:
6730 case MVE_LSRL:
6731 case MVE_ASRL:
6732 case MVE_ASRLI:
6733 case MVE_UQSHLL:
6734 case MVE_UQRSHLL:
6735 case MVE_URSHRL:
6736 case MVE_SRSHRL:
6737 case MVE_SQSHLL:
6738 case MVE_SQRSHRL:
6739 {
6740 unsigned long gpr = arm_decode_field (given, 9, 11);
6741 gpr = ((gpr << 1) | 1);
6742 if (gpr == 0xd)
6743 {
6744 *unpredictable_code = UNPRED_R13;
6745 return TRUE;
6746 }
6747 else if (gpr == 0xf)
6748 {
6749 *unpredictable_code = UNPRED_R15;
6750 return TRUE;
6751 }
6752
6753 return FALSE;
6754 }
6755
143275ea
AV		 6756 default:
6757 return FALSE;
6758 }
6759}
c1e26897 6760
c507f10b
AV		 6761static void
6762print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
6763{
6764 unsigned long op1 = arm_decode_field (given, 21, 22);
6765 unsigned long op2 = arm_decode_field (given, 5, 6);
6766 unsigned long h = arm_decode_field (given, 16, 16);
43dd7626 6767 unsigned long index_operand, esize, targetBeat, idx;
c507f10b
AV		 6768 void *stream = info->stream;
6769 fprintf_ftype func = info->fprintf_func;
6770
6771 if ((op1 & 0x2) == 0x2)
6772 {
43dd7626 6773 index_operand = op2;
c507f10b
AV		 6774 esize = 8;
6775 }
6776 else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
6777 {
43dd7626 6778 index_operand = op2 >> 1;
c507f10b
AV		 6779 esize = 16;
6780 }
6781 else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
6782 {
43dd7626 6783 index_operand = 0;
c507f10b
AV		 6784 esize = 32;
6785 }
6786 else
6787 {
6788 func (stream, "<undefined index>");
6789 return;
6790 }
6791
6792 targetBeat = (op1 & 0x1) | (h << 1);
43dd7626 6793 idx = index_operand + targetBeat * (32/esize);
c507f10b
AV		 6794
6795 func (stream, "%lu", idx);
6796}
6797
6798/* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6799 in length and integer of floating-point type. */
6800static void
6801print_simd_imm8 (struct disassemble_info *info, unsigned long given,
6802 unsigned int ibit_loc, const struct mopcode32 *insn)
6803{
6804 int bits = 0;
6805 int cmode = (given >> 8) & 0xf;
6806 int op = (given >> 5) & 0x1;
6807 unsigned long value = 0, hival = 0;
6808 unsigned shift;
6809 int size = 0;
6810 int isfloat = 0;
6811 void *stream = info->stream;
6812 fprintf_ftype func = info->fprintf_func;
6813
6814 /* On Neon the 'i' bit is at bit 24, on mve it is
6815 at bit 28. */
6816 bits |= ((given >> ibit_loc) & 1) << 7;
6817 bits |= ((given >> 16) & 7) << 4;
6818 bits |= ((given >> 0) & 15) << 0;
6819
6820 if (cmode < 8)
6821 {
6822 shift = (cmode >> 1) & 3;
6823 value = (unsigned long) bits << (8 * shift);
6824 size = 32;
6825 }
6826 else if (cmode < 12)
6827 {
6828 shift = (cmode >> 1) & 1;
6829 value = (unsigned long) bits << (8 * shift);
6830 size = 16;
6831 }
6832 else if (cmode < 14)
6833 {
6834 shift = (cmode & 1) + 1;
6835 value = (unsigned long) bits << (8 * shift);
6836 value |= (1ul << (8 * shift)) - 1;
6837 size = 32;
6838 }
6839 else if (cmode == 14)
6840 {
6841 if (op)
6842 {
6843 /* Bit replication into bytes. */
6844 int ix;
6845 unsigned long mask;
6846
6847 value = 0;
6848 hival = 0;
6849 for (ix = 7; ix >= 0; ix--)
6850 {
6851 mask = ((bits >> ix) & 1) ? 0xff : 0;
6852 if (ix <= 3)
6853 value = (value << 8) | mask;
6854 else
6855 hival = (hival << 8) | mask;
6856 }
6857 size = 64;
6858 }
6859 else
6860 {
6861 /* Byte replication. */
6862 value = (unsigned long) bits;
6863 size = 8;
6864 }
6865 }
6866 else if (!op)
6867 {
6868 /* Floating point encoding. */
6869 int tmp;
6870
6871 value = (unsigned long) (bits & 0x7f) << 19;
6872 value |= (unsigned long) (bits & 0x80) << 24;
6873 tmp = bits & 0x40 ? 0x3c : 0x40;
6874 value |= (unsigned long) tmp << 24;
6875 size = 32;
6876 isfloat = 1;
6877 }
6878 else
6879 {
6880 func (stream, "<illegal constant %.8x:%x:%x>",
6881 bits, cmode, op);
6882 size = 32;
6883 return;
6884 }
6885
6886 // printU determines whether the immediate value should be printed as
6887 // unsigned.
6888 unsigned printU = 0;
6889 switch (insn->mve_op)
6890 {
6891 default:
6892 break;
6893 // We want this for instructions that don't have a 'signed' type
6894 case MVE_VBIC_IMM:
6895 case MVE_VORR_IMM:
6896 case MVE_VMVN_IMM:
6897 case MVE_VMOV_IMM_TO_VEC:
6898 printU = 1;
6899 break;
6900 }
6901 switch (size)
6902 {
6903 case 8:
6904 func (stream, "#%ld\t; 0x%.2lx", value, value);
6905 break;
6906
6907 case 16:
6908 func (stream,
6909 printU
6910 ? "#%lu\t; 0x%.4lx"
6911 : "#%ld\t; 0x%.4lx", value, value);
6912 break;
6913
6914 case 32:
6915 if (isfloat)
6916 {
6917 unsigned char valbytes[4];
6918 double fvalue;
6919
6920 /* Do this a byte at a time so we don't have to
6921 worry about the host's endianness. */
6922 valbytes[0] = value & 0xff;
6923 valbytes[1] = (value >> 8) & 0xff;
6924 valbytes[2] = (value >> 16) & 0xff;
6925 valbytes[3] = (value >> 24) & 0xff;
6926
6927 floatformat_to_double
6928 (& floatformat_ieee_single_little, valbytes,
6929 & fvalue);
6930
6931 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
6932 value);
6933 }
6934 else
6935 func (stream,
6936 printU
6937 ? "#%lu\t; 0x%.8lx"
6938 : "#%ld\t; 0x%.8lx",
6939 (long) (((value & 0x80000000L) != 0)
6940 && !printU
6941 ? value | ~0xffffffffL : value),
6942 value);
6943 break;
6944
6945 case 64:
6946 func (stream, "#0x%.8lx%.8lx", hival, value);
6947 break;
6948
6949 default:
6950 abort ();
6951 }
6952
6953}
6954
73cd51e5
AV		 6955static void
6956print_mve_undefined (struct disassemble_info *info,
6957 enum mve_undefined undefined_code)
6958{
6959 void *stream = info->stream;
6960 fprintf_ftype func = info->fprintf_func;
6961
6962 func (stream, "\t\tundefined instruction: ");
6963
6964 switch (undefined_code)
6965 {
ed63aa17
AV		 6966 case UNDEF_SIZE:
6967 func (stream, "illegal size");
6968 break;
6969
aef6d006
AV		 6970 case UNDEF_SIZE_0:
6971 func (stream, "size equals zero");
6972 break;
6973
c507f10b
AV		 6974 case UNDEF_SIZE_2:
6975 func (stream, "size equals two");
6976 break;
6977
9743db03
AV		 6978 case UNDEF_SIZE_3:
6979 func (stream, "size equals three");
6980 break;
6981
aef6d006
AV		 6982 case UNDEF_SIZE_LE_1:
6983 func (stream, "size <= 1");
6984 break;
6985
14b456f2
AV		 6986 case UNDEF_SIZE_NOT_0:
6987 func (stream, "size not equal to 0");
6988 break;
6989
ef1576a1
AV		 6990 case UNDEF_SIZE_NOT_2:
6991 func (stream, "size not equal to 2");
6992 break;
6993
6994 case UNDEF_SIZE_NOT_3:
6995 func (stream, "size not equal to 3");
6996 break;
6997
6998 case UNDEF_NOT_UNS_SIZE_0:
6999 func (stream, "not unsigned and size = zero");
7000 break;
7001
7002 case UNDEF_NOT_UNS_SIZE_1:
7003 func (stream, "not unsigned and size = one");
7004 break;
7005
7006 case UNDEF_NOT_UNSIGNED:
7007 func (stream, "not unsigned");
7008 break;
7009
bf0b396d
AV		 7010 case UNDEF_VCVT_IMM6:
7011 func (stream, "invalid imm6");
7012 break;
7013
7014 case UNDEF_VCVT_FSI_IMM6:
7015 func (stream, "fsi = 0 and invalid imm6");
7016 break;
7017
c507f10b
AV		 7018 case UNDEF_BAD_OP1_OP2:
7019 func (stream, "bad size with op2 = 2 and op1 = 0 or 1");
7020 break;
7021
7022 case UNDEF_BAD_U_OP1_OP2:
7023 func (stream, "unsigned with op2 = 0 and op1 = 0 or 1");
7024 break;
7025
7026 case UNDEF_OP_0_BAD_CMODE:
7027 func (stream, "op field equal 0 and bad cmode");
7028 break;
7029
d3b63143
AV		 7030 case UNDEF_XCHG_UNS:
7031 func (stream, "exchange and unsigned together");
7032 break;
7033
73cd51e5
AV		 7034 case UNDEF_NONE:
7035 break;
7036 }
7037
7038}
7039
7040static void
7041print_mve_unpredictable (struct disassemble_info *info,
7042 enum mve_unpredictable unpredict_code)
7043{
7044 void *stream = info->stream;
7045 fprintf_ftype func = info->fprintf_func;
7046
7047 func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
7048
7049 switch (unpredict_code)
7050 {
7051 case UNPRED_IT_BLOCK:
7052 func (stream, "mve instruction in it block");
7053 break;
7054
143275ea
AV		 7055 case UNPRED_FCA_0_FCB_1:
7056 func (stream, "condition bits, fca = 0 and fcb = 1");
7057 break;
7058
7059 case UNPRED_R13:
7060 func (stream, "use of r13 (sp)");
7061 break;
7062
9743db03
AV		 7063 case UNPRED_R15:
7064 func (stream, "use of r15 (pc)");
7065 break;
7066
04d54ace
AV		 7067 case UNPRED_Q_GT_4:
7068 func (stream, "start register block > r4");
7069 break;
7070
7071 case UNPRED_Q_GT_6:
7072 func (stream, "start register block > r6");
7073 break;
7074
7075 case UNPRED_R13_AND_WB:
7076 func (stream, "use of r13 and write back");
7077 break;
7078
ef1576a1
AV		 7079 case UNPRED_Q_REGS_EQUAL:
7080 func (stream,
7081 "same vector register used for destination and other operand");
7082 break;
7083
7084 case UNPRED_OS:
7085 func (stream, "use of offset scaled");
7086 break;
7087
bf0b396d
AV		 7088 case UNPRED_GP_REGS_EQUAL:
7089 func (stream, "same general-purpose register used for both operands");
7090 break;
7091
c507f10b
AV		 7092 case UNPRED_Q_REGS_EQ_AND_SIZE_1:
7093 func (stream, "use of identical q registers and size = 1");
7094 break;
7095
7096 case UNPRED_Q_REGS_EQ_AND_SIZE_2:
7097 func (stream, "use of identical q registers and size = 1");
7098 break;
7099
73cd51e5
AV		 7100 case UNPRED_NONE:
7101 break;
7102 }
7103}
7104
04d54ace
AV		 7105/* Print register block operand for mve vld2/vld4/vst2/vld4. */
7106
7107static void
7108print_mve_register_blocks (struct disassemble_info *info,
7109 unsigned long given,
7110 enum mve_instructions matched_insn)
7111{
7112 void *stream = info->stream;
7113 fprintf_ftype func = info->fprintf_func;
7114
7115 unsigned long q_reg_start = arm_decode_field_multiple (given,
7116 13, 15,
7117 22, 22);
7118 switch (matched_insn)
7119 {
7120 case MVE_VLD2:
7121 case MVE_VST2:
7122 if (q_reg_start <= 6)
7123 func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
7124 else
7125 func (stream, "<illegal reg q%ld>", q_reg_start);
7126 break;
7127
7128 case MVE_VLD4:
7129 case MVE_VST4:
7130 if (q_reg_start <= 4)
7131 func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
7132 q_reg_start + 1, q_reg_start + 2,
7133 q_reg_start + 3);
7134 else
7135 func (stream, "<illegal reg q%ld>", q_reg_start);
7136 break;
7137
7138 default:
7139 break;
7140 }
7141}
7142
bf0b396d
AV		 7143static void
7144print_mve_rounding_mode (struct disassemble_info *info,
7145 unsigned long given,
7146 enum mve_instructions matched_insn)
7147{
7148 void *stream = info->stream;
7149 fprintf_ftype func = info->fprintf_func;
7150
7151 switch (matched_insn)
7152 {
7153 case MVE_VCVT_FROM_FP_TO_INT:
7154 {
7155 switch (arm_decode_field (given, 8, 9))
7156 {
7157 case 0:
7158 func (stream, "a");
7159 break;
7160
7161 case 1:
7162 func (stream, "n");
7163 break;
7164
7165 case 2:
7166 func (stream, "p");
7167 break;
7168
7169 case 3:
7170 func (stream, "m");
7171 break;
7172
7173 default:
7174 break;
7175 }
7176 }
7177 break;
7178
7179 case MVE_VRINT_FP:
7180 {
7181 switch (arm_decode_field (given, 7, 9))
7182 {
7183 case 0:
7184 func (stream, "n");
7185 break;
7186
7187 case 1:
7188 func (stream, "x");
7189 break;
7190
7191 case 2:
7192 func (stream, "a");
7193 break;
7194
7195 case 3:
7196 func (stream, "z");
7197 break;
7198
7199 case 5:
7200 func (stream, "m");
7201 break;
7202
7203 case 7:
7204 func (stream, "p");
7205
7206 case 4:
7207 case 6:
7208 default:
7209 break;
7210 }
7211 }
7212 break;
7213
7214 default:
7215 break;
7216 }
7217}
7218
7219static void
7220print_mve_vcvt_size (struct disassemble_info *info,
7221 unsigned long given,
7222 enum mve_instructions matched_insn)
7223{
7224 unsigned long mode = 0;
7225 void *stream = info->stream;
7226 fprintf_ftype func = info->fprintf_func;
7227
7228 switch (matched_insn)
7229 {
7230 case MVE_VCVT_FP_FIX_VEC:
7231 {
7232 mode = (((given & 0x200) >> 7)
7233 | ((given & 0x10000000) >> 27)
7234 | ((given & 0x100) >> 8));
7235
7236 switch (mode)
7237 {
7238 case 0:
7239 func (stream, "f16.s16");
7240 break;
7241
7242 case 1:
7243 func (stream, "s16.f16");
7244 break;
7245
7246 case 2:
7247 func (stream, "f16.u16");
7248 break;
7249
7250 case 3:
7251 func (stream, "u16.f16");
7252 break;
7253
7254 case 4:
7255 func (stream, "f32.s32");
7256 break;
7257
7258 case 5:
7259 func (stream, "s32.f32");
7260 break;
7261
7262 case 6:
7263 func (stream, "f32.u32");
7264 break;
7265
7266 case 7:
7267 func (stream, "u32.f32");
7268 break;
7269
7270 default:
7271 break;
7272 }
7273 break;
7274 }
7275 case MVE_VCVT_BETWEEN_FP_INT:
7276 {
7277 unsigned long size = arm_decode_field (given, 18, 19);
7278 unsigned long op = arm_decode_field (given, 7, 8);
7279
7280 if (size == 1)
7281 {
7282 switch (op)
7283 {
7284 case 0:
7285 func (stream, "f16.s16");
7286 break;
7287
7288 case 1:
7289 func (stream, "f16.u16");
7290 break;
7291
7292 case 2:
7293 func (stream, "s16.f16");
7294 break;
7295
7296 case 3:
7297 func (stream, "u16.f16");
7298 break;
7299
7300 default:
7301 break;
7302 }
7303 }
7304 else if (size == 2)
7305 {
7306 switch (op)
7307 {
7308 case 0:
7309 func (stream, "f32.s32");
7310 break;
7311
7312 case 1:
7313 func (stream, "f32.u32");
7314 break;
7315
7316 case 2:
7317 func (stream, "s32.f32");
7318 break;
7319
7320 case 3:
7321 func (stream, "u32.f32");
7322 break;
7323 }
7324 }
7325 }
7326 break;
7327
7328 case MVE_VCVT_FP_HALF_FP:
7329 {
7330 unsigned long op = arm_decode_field (given, 28, 28);
7331 if (op == 0)
7332 func (stream, "f16.f32");
7333 else if (op == 1)
7334 func (stream, "f32.f16");
7335 }
7336 break;
7337
7338 case MVE_VCVT_FROM_FP_TO_INT:
7339 {
7340 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
7341
7342 switch (size)
7343 {
7344 case 2:
7345 func (stream, "s16.f16");
7346 break;
7347
7348 case 3:
7349 func (stream, "u16.f16");
7350 break;
7351
7352 case 4:
7353 func (stream, "s32.f32");
7354 break;
7355
7356 case 5:
7357 func (stream, "u32.f32");
7358 break;
7359
7360 default:
7361 break;
7362 }
7363 }
7364 break;
7365
7366 default:
7367 break;
7368 }
7369}
7370
897b9bbc
AV		 7371static void
7372print_mve_rotate (struct disassemble_info *info, unsigned long rot,
7373 unsigned long rot_width)
7374{
7375 void *stream = info->stream;
7376 fprintf_ftype func = info->fprintf_func;
7377
7378 if (rot_width == 1)
7379 {
7380 switch (rot)
7381 {
7382 case 0:
7383 func (stream, "90");
7384 break;
7385 case 1:
7386 func (stream, "270");
7387 break;
7388 default:
7389 break;
7390 }
7391 }
7392 else if (rot_width == 2)
7393 {
7394 switch (rot)
7395 {
7396 case 0:
7397 func (stream, "0");
7398 break;
7399 case 1:
7400 func (stream, "90");
7401 break;
7402 case 2:
7403 func (stream, "180");
7404 break;
7405 case 3:
7406 func (stream, "270");
7407 break;
7408 default:
7409 break;
7410 }
7411 }
7412}
7413
143275ea
AV		 7414static void
7415print_instruction_predicate (struct disassemble_info *info)
7416{
7417 void *stream = info->stream;
7418 fprintf_ftype func = info->fprintf_func;
7419
7420 if (vpt_block_state.next_pred_state == PRED_THEN)
7421 func (stream, "t");
7422 else if (vpt_block_state.next_pred_state == PRED_ELSE)
7423 func (stream, "e");
7424}
7425
7426static void
7427print_mve_size (struct disassemble_info *info,
7428 unsigned long size,
7429 enum mve_instructions matched_insn)
7430{
7431 void *stream = info->stream;
7432 fprintf_ftype func = info->fprintf_func;
7433
7434 switch (matched_insn)
7435 {
66dcaa5d
AV		 7436 case MVE_VABAV:
7437 case MVE_VABD_VEC:
7438 case MVE_VABS_FP:
7439 case MVE_VABS_VEC:
7440 case MVE_VADD_VEC_T1:
7441 case MVE_VADD_VEC_T2:
d3b63143 7442 case MVE_VADDV:
e523f101 7443 case MVE_VBRSR:
897b9bbc 7444 case MVE_VCADD_VEC:
e523f101
AV		 7445 case MVE_VCLS:
7446 case MVE_VCLZ:
143275ea
AV		 7447 case MVE_VCMP_VEC_T1:
7448 case MVE_VCMP_VEC_T2:
7449 case MVE_VCMP_VEC_T3:
7450 case MVE_VCMP_VEC_T4:
7451 case MVE_VCMP_VEC_T5:
7452 case MVE_VCMP_VEC_T6:
e523f101 7453 case MVE_VCTP:
1c8f2df8
AV		 7454 case MVE_VDDUP:
7455 case MVE_VDWDUP:
9743db03
AV		 7456 case MVE_VHADD_T1:
7457 case MVE_VHADD_T2:
897b9bbc 7458 case MVE_VHCADD:
9743db03
AV		 7459 case MVE_VHSUB_T1:
7460 case MVE_VHSUB_T2:
1c8f2df8
AV		 7461 case MVE_VIDUP:
7462 case MVE_VIWDUP:
04d54ace
AV		 7463 case MVE_VLD2:
7464 case MVE_VLD4:
ef1576a1
AV		 7465 case MVE_VLDRB_GATHER_T1:
7466 case MVE_VLDRH_GATHER_T2:
7467 case MVE_VLDRW_GATHER_T3:
7468 case MVE_VLDRD_GATHER_T4:
aef6d006
AV		 7469 case MVE_VLDRB_T1:
7470 case MVE_VLDRH_T2:
56858bea
AV		 7471 case MVE_VMAX:
7472 case MVE_VMAXA:
7473 case MVE_VMAXV:
7474 case MVE_VMAXAV:
7475 case MVE_VMIN:
7476 case MVE_VMINA:
7477 case MVE_VMINV:
7478 case MVE_VMINAV:
7479 case MVE_VMLA:
d3b63143 7480 case MVE_VMLAS:
f49bb598
AV		 7481 case MVE_VMUL_VEC_T1:
7482 case MVE_VMUL_VEC_T2:
7483 case MVE_VMULH:
7484 case MVE_VRMULH:
7485 case MVE_VMULL_INT:
7486 case MVE_VNEG_FP:
7487 case MVE_VNEG_VEC:
143275ea
AV		 7488 case MVE_VPT_VEC_T1:
7489 case MVE_VPT_VEC_T2:
7490 case MVE_VPT_VEC_T3:
7491 case MVE_VPT_VEC_T4:
7492 case MVE_VPT_VEC_T5:
7493 case MVE_VPT_VEC_T6:
14b456f2
AV		 7494 case MVE_VQABS:
7495 case MVE_VQADD_T1:
7496 case MVE_VQADD_T2:
d3b63143
AV		 7497 case MVE_VQDMLADH:
7498 case MVE_VQRDMLADH:
7499 case MVE_VQDMLAH:
7500 case MVE_VQRDMLAH:
7501 case MVE_VQDMLASH:
7502 case MVE_VQRDMLASH:
7503 case MVE_VQDMLSDH:
7504 case MVE_VQRDMLSDH:
7505 case MVE_VQDMULH_T1:
7506 case MVE_VQRDMULH_T2:
7507 case MVE_VQDMULH_T3:
7508 case MVE_VQRDMULH_T4:
14b456f2 7509 case MVE_VQNEG:
ed63aa17
AV		 7510 case MVE_VQRSHL_T1:
7511 case MVE_VQRSHL_T2:
7512 case MVE_VQSHL_T1:
7513 case MVE_VQSHL_T4:
14b456f2
AV		 7514 case MVE_VQSUB_T1:
7515 case MVE_VQSUB_T2:
7516 case MVE_VREV32:
7517 case MVE_VREV64:
9743db03 7518 case MVE_VRHADD:
bf0b396d 7519 case MVE_VRINT_FP:
ed63aa17
AV		 7520 case MVE_VRSHL_T1:
7521 case MVE_VRSHL_T2:
7522 case MVE_VSHL_T2:
7523 case MVE_VSHL_T3:
7524 case MVE_VSHLL_T2:
04d54ace
AV		 7525 case MVE_VST2:
7526 case MVE_VST4:
ef1576a1
AV		 7527 case MVE_VSTRB_SCATTER_T1:
7528 case MVE_VSTRH_SCATTER_T2:
7529 case MVE_VSTRW_SCATTER_T3:
aef6d006
AV		 7530 case MVE_VSTRB_T1:
7531 case MVE_VSTRH_T2:
66dcaa5d
AV		 7532 case MVE_VSUB_VEC_T1:
7533 case MVE_VSUB_VEC_T2:
143275ea
AV		 7534 if (size <= 3)
7535 func (stream, "%s", mve_vec_sizename[size]);
7536 else
7537 func (stream, "<undef size>");
7538 break;
7539
66dcaa5d
AV		 7540 case MVE_VABD_FP:
7541 case MVE_VADD_FP_T1:
7542 case MVE_VADD_FP_T2:
7543 case MVE_VSUB_FP_T1:
7544 case MVE_VSUB_FP_T2:
143275ea
AV		 7545 case MVE_VCMP_FP_T1:
7546 case MVE_VCMP_FP_T2:
9743db03
AV		 7547 case MVE_VFMA_FP_SCALAR:
7548 case MVE_VFMA_FP:
7549 case MVE_VFMS_FP:
7550 case MVE_VFMAS_FP_SCALAR:
56858bea
AV		 7551 case MVE_VMAXNM_FP:
7552 case MVE_VMAXNMA_FP:
7553 case MVE_VMAXNMV_FP:
7554 case MVE_VMAXNMAV_FP:
7555 case MVE_VMINNM_FP:
7556 case MVE_VMINNMA_FP:
7557 case MVE_VMINNMV_FP:
7558 case MVE_VMINNMAV_FP:
f49bb598
AV		 7559 case MVE_VMUL_FP_T1:
7560 case MVE_VMUL_FP_T2:
143275ea
AV		 7561 case MVE_VPT_FP_T1:
7562 case MVE_VPT_FP_T2:
7563 if (size == 0)
7564 func (stream, "32");
7565 else if (size == 1)
7566 func (stream, "16");
7567 break;
7568
897b9bbc
AV		 7569 case MVE_VCADD_FP:
7570 case MVE_VCMLA_FP:
7571 case MVE_VCMUL_FP:
d3b63143
AV		 7572 case MVE_VMLADAV_T1:
7573 case MVE_VMLALDAV:
7574 case MVE_VMLSDAV_T1:
7575 case MVE_VMLSLDAV:
14925797
AV		 7576 case MVE_VMOVN:
7577 case MVE_VQDMULL_T1:
7578 case MVE_VQDMULL_T2:
7579 case MVE_VQMOVN:
7580 case MVE_VQMOVUN:
7581 if (size == 0)
7582 func (stream, "16");
7583 else if (size == 1)
7584 func (stream, "32");
7585 break;
7586
7587 case MVE_VMOVL:
7588 if (size == 1)
7589 func (stream, "8");
7590 else if (size == 2)
7591 func (stream, "16");
7592 break;
7593
9743db03
AV		 7594 case MVE_VDUP:
7595 switch (size)
7596 {
7597 case 0:
7598 func (stream, "32");
7599 break;
7600 case 1:
7601 func (stream, "16");
7602 break;
7603 case 2:
7604 func (stream, "8");
7605 break;
7606 default:
7607 break;
7608 }
7609 break;
7610
c507f10b
AV		 7611 case MVE_VMOV_GP_TO_VEC_LANE:
7612 case MVE_VMOV_VEC_LANE_TO_GP:
7613 switch (size)
7614 {
7615 case 0: case 4:
7616 func (stream, "32");
7617 break;
7618
7619 case 1: case 3:
7620 case 5: case 7:
7621 func (stream, "16");
7622 break;
7623
7624 case 8: case 9: case 10: case 11:
7625 case 12: case 13: case 14: case 15:
7626 func (stream, "8");
7627 break;
7628
7629 default:
7630 break;
7631 }
7632 break;
7633
7634 case MVE_VMOV_IMM_TO_VEC:
7635 switch (size)
7636 {
7637 case 0: case 4: case 8:
7638 case 12: case 24: case 26:
7639 func (stream, "i32");
7640 break;
7641 case 16: case 20:
7642 func (stream, "i16");
7643 break;
7644 case 28:
7645 func (stream, "i8");
7646 break;
7647 case 29:
7648 func (stream, "i64");
7649 break;
7650 case 30:
7651 func (stream, "f32");
7652 break;
7653 default:
7654 break;
7655 }
7656 break;
7657
14925797
AV		 7658 case MVE_VMULL_POLY:
7659 if (size == 0)
7660 func (stream, "p8");
7661 else if (size == 1)
7662 func (stream, "p16");
7663 break;
7664
c507f10b
AV		 7665 case MVE_VMVN_IMM:
7666 switch (size)
7667 {
7668 case 0: case 2: case 4:
7669 case 6: case 12: case 13:
7670 func (stream, "32");
7671 break;
7672
7673 case 8: case 10:
7674 func (stream, "16");
7675 break;
7676
7677 default:
7678 break;
7679 }
7680 break;
7681
7682 case MVE_VBIC_IMM:
7683 case MVE_VORR_IMM:
7684 switch (size)
7685 {
7686 case 1: case 3:
7687 case 5: case 7:
7688 func (stream, "32");
7689 break;
7690
7691 case 9: case 11:
7692 func (stream, "16");
7693 break;
7694
7695 default:
7696 break;
7697 }
7698 break;
7699
ed63aa17
AV		 7700 case MVE_VQSHRN:
7701 case MVE_VQSHRUN:
7702 case MVE_VQRSHRN:
7703 case MVE_VQRSHRUN:
7704 case MVE_VRSHRN:
7705 case MVE_VSHRN:
7706 {
7707 switch (size)
7708 {
7709 case 1:
7710 func (stream, "16");
7711 break;
7712
7713 case 2: case 3:
7714 func (stream, "32");
7715 break;
7716
7717 default:
7718 break;
7719 }
7720 }
7721 break;
7722
7723 case MVE_VQSHL_T2:
7724 case MVE_VQSHLU_T3:
7725 case MVE_VRSHR:
7726 case MVE_VSHL_T1:
7727 case MVE_VSHLL_T1:
7728 case MVE_VSHR:
7729 case MVE_VSLI:
7730 case MVE_VSRI:
7731 {
7732 switch (size)
7733 {
7734 case 1:
7735 func (stream, "8");
7736 break;
7737
7738 case 2: case 3:
7739 func (stream, "16");
7740 break;
7741
7742 case 4: case 5: case 6: case 7:
7743 func (stream, "32");
7744 break;
7745
7746 default:
7747 break;
7748 }
7749 }
7750 break;
7751
143275ea
AV		 7752 default:
7753 break;
7754 }
7755}
7756
ed63aa17
AV		 7757static void
7758print_mve_shift_n (struct disassemble_info *info, long given,
7759 enum mve_instructions matched_insn)
7760{
7761 void *stream = info->stream;
7762 fprintf_ftype func = info->fprintf_func;
7763
7764 int startAt0
7765 = matched_insn == MVE_VQSHL_T2
7766 || matched_insn == MVE_VQSHLU_T3
7767 || matched_insn == MVE_VSHL_T1
7768 || matched_insn == MVE_VSHLL_T1
7769 || matched_insn == MVE_VSLI;
7770
7771 unsigned imm6 = (given & 0x3f0000) >> 16;
7772
7773 if (matched_insn == MVE_VSHLL_T1)
7774 imm6 &= 0x1f;
7775
7776 unsigned shiftAmount = 0;
7777 if ((imm6 & 0x20) != 0)
7778 shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
7779 else if ((imm6 & 0x10) != 0)
7780 shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
7781 else if ((imm6 & 0x08) != 0)
7782 shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
7783 else
7784 print_mve_undefined (info, UNDEF_SIZE_0);
7785
7786 func (stream, "%u", shiftAmount);
7787}
7788
143275ea
AV		 7789static void
7790print_vec_condition (struct disassemble_info *info, long given,
7791 enum mve_instructions matched_insn)
7792{
7793 void *stream = info->stream;
7794 fprintf_ftype func = info->fprintf_func;
7795 long vec_cond = 0;
7796
7797 switch (matched_insn)
7798 {
7799 case MVE_VPT_FP_T1:
7800 case MVE_VCMP_FP_T1:
7801 vec_cond = (((given & 0x1000) >> 10)
7802 | ((given & 1) << 1)
7803 | ((given & 0x0080) >> 7));
7804 func (stream, "%s",vec_condnames[vec_cond]);
7805 break;
7806
7807 case MVE_VPT_FP_T2:
7808 case MVE_VCMP_FP_T2:
7809 vec_cond = (((given & 0x1000) >> 10)
7810 | ((given & 0x0020) >> 4)
7811 | ((given & 0x0080) >> 7));
7812 func (stream, "%s",vec_condnames[vec_cond]);
7813 break;
7814
7815 case MVE_VPT_VEC_T1:
7816 case MVE_VCMP_VEC_T1:
7817 vec_cond = (given & 0x0080) >> 7;
7818 func (stream, "%s",vec_condnames[vec_cond]);
7819 break;
7820
7821 case MVE_VPT_VEC_T2:
7822 case MVE_VCMP_VEC_T2:
7823 vec_cond = 2 | ((given & 0x0080) >> 7);
7824 func (stream, "%s",vec_condnames[vec_cond]);
7825 break;
7826
7827 case MVE_VPT_VEC_T3:
7828 case MVE_VCMP_VEC_T3:
7829 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
7830 func (stream, "%s",vec_condnames[vec_cond]);
7831 break;
7832
7833 case MVE_VPT_VEC_T4:
7834 case MVE_VCMP_VEC_T4:
7835 vec_cond = (given & 0x0080) >> 7;
7836 func (stream, "%s",vec_condnames[vec_cond]);
7837 break;
7838
7839 case MVE_VPT_VEC_T5:
7840 case MVE_VCMP_VEC_T5:
7841 vec_cond = 2 | ((given & 0x0080) >> 7);
7842 func (stream, "%s",vec_condnames[vec_cond]);
7843 break;
7844
7845 case MVE_VPT_VEC_T6:
7846 case MVE_VCMP_VEC_T6:
7847 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
7848 func (stream, "%s",vec_condnames[vec_cond]);
7849 break;
7850
7851 case MVE_NONE:
7852 case MVE_VPST:
7853 default:
7854 break;
7855 }
7856}
7857
7858#define W_BIT 21
7859#define I_BIT 22
7860#define U_BIT 23
7861#define P_BIT 24
7862
7863#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
7864#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
7865#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
7866#define PRE_BIT_SET (given & (1 << P_BIT))
7867
7868
8f06b2d8
PB		 7869/* Print one coprocessor instruction on INFO->STREAM.
7870 Return TRUE if the instuction matched, FALSE if this is not a
7871 recognised coprocessor instruction. */
7872
7873static bfd_boolean
fe56b6ce
NC		 7874print_insn_coprocessor (bfd_vma pc,
7875 struct disassemble_info *info,
7876 long given,
8f06b2d8
PB		 7877 bfd_boolean thumb)
7878{
6b0dd094 7879 const struct sopcode32 *insn;
8f06b2d8
PB		 7880 void *stream = info->stream;
7881 fprintf_ftype func = info->fprintf_func;
7882 unsigned long mask;
2edcd244 7883 unsigned long value = 0;
c22aaad1 7884 int cond;
8afc7bea 7885 int cp_num;
823d2571
TG		 7886 struct arm_private_data *private_data = info->private_data;
7887 arm_feature_set allowed_arches = ARM_ARCH_NONE;
32c36c3c
AV		 7888 arm_feature_set arm_ext_v8_1m_main =
7889 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
823d2571 7890
5b616bef 7891 allowed_arches = private_data->features;
8f06b2d8
PB		 7892
7893 for (insn = coprocessor_opcodes; insn->assembler; insn++)
7894 {
ff4a8d2b
NC		 7895 unsigned long u_reg = 16;
7896 bfd_boolean is_unpredictable = FALSE;
05413229 7897 signed long value_in_comment = 0;
0313a2b8
NC		 7898 const char *c;
7899
823d2571 7900 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 7901 switch (insn->value)
7902 {
7903 case SENTINEL_IWMMXT_START:
7904 if (info->mach != bfd_mach_arm_XScale
7905 && info->mach != bfd_mach_arm_iWMMXt
7906 && info->mach != bfd_mach_arm_iWMMXt2)
7907 do
7908 insn++;
823d2571
TG		 7909 while ((! ARM_FEATURE_ZERO (insn->arch))
7910 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 7911 continue;
7912
7913 case SENTINEL_IWMMXT_END:
7914 continue;
7915
7916 case SENTINEL_GENERIC_START:
5b616bef 7917 allowed_arches = private_data->features;
05413229
NC		 7918 continue;
7919
7920 default:
7921 abort ();
7922 }
8f06b2d8
PB		 7923
7924 mask = insn->mask;
7925 value = insn->value;
8afc7bea
RL		 7926 cp_num = (given >> 8) & 0xf;
7927
8f06b2d8
PB		 7928 if (thumb)
7929 {
7930 /* The high 4 bits are 0xe for Arm conditional instructions, and
7931 0xe for arm unconditional instructions. The rest of the
7932 encoding is the same. */
7933 mask |= 0xf0000000;
7934 value |= 0xe0000000;
c22aaad1
PB		 7935 if (ifthen_state)
7936 cond = IFTHEN_COND;
7937 else
e2efe87d 7938 cond = COND_UNCOND;
8f06b2d8
PB		 7939 }
7940 else
7941 {
7942 /* Only match unconditional instuctions against unconditional
7943 patterns. */
7944 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 7945 {
7946 mask |= 0xf0000000;
e2efe87d 7947 cond = COND_UNCOND;
c22aaad1
PB		 7948 }
7949 else
7950 {
7951 cond = (given >> 28) & 0xf;
7952 if (cond == 0xe)
e2efe87d 7953 cond = COND_UNCOND;
c22aaad1 7954 }
8f06b2d8 7955 }
823d2571 7956
6b0dd094
AV		 7957 if ((insn->isa == T32 && !thumb)
7958 || (insn->isa == ARM && thumb))
7959 continue;
7960
0313a2b8
NC		 7961 if ((given & mask) != value)
7962 continue;
8f06b2d8 7963
823d2571 7964 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 7965 continue;
7966
8afc7bea
RL		 7967 if (insn->value == 0xfe000010 /* mcr2 */
7968 || insn->value == 0xfe100010 /* mrc2 */
7969 || insn->value == 0xfc100000 /* ldc2 */
7970 || insn->value == 0xfc000000) /* stc2 */
7971 {
b0c11777 7972 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 7973 is_unpredictable = TRUE;
f08d8ce3
AV		 7974
7975 /* Armv8.1-M Mainline FP & MVE instructions. */
7976 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
7977 && !ARM_CPU_IS_ANY (allowed_arches)
7978 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
7979 continue;
7980
8afc7bea
RL		 7981 }
7982 else if (insn->value == 0x0e000000 /* cdp */
7983 || insn->value == 0xfe000000 /* cdp2 */
7984 || insn->value == 0x0e000010 /* mcr */
7985 || insn->value == 0x0e100010 /* mrc */
7986 || insn->value == 0x0c100000 /* ldc */
7987 || insn->value == 0x0c000000) /* stc */
7988 {
7989 /* Floating-point instructions. */
b0c11777 7990 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 7991 continue;
32c36c3c
AV		 7992
7993 /* Armv8.1-M Mainline FP & MVE instructions. */
7994 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
7995 && !ARM_CPU_IS_ANY (allowed_arches)
7996 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
7997 continue;
8afc7bea 7998 }
aef6d006
AV		 7999 else if ((insn->value == 0xec100f80 /* vldr (system register) */
8000 || insn->value == 0xec000f80) /* vstr (system register) */
8001 && arm_decode_field (given, 24, 24) == 0
8002 && arm_decode_field (given, 21, 21) == 0)
8003 /* If the P and W bits are both 0 then these encodings match the MVE
8004 VLDR and VSTR instructions, these are in a different table, so we
8005 don't let it match here. */
8006 continue;
8007
0313a2b8
NC		 8008 for (c = insn->assembler; *c; c++)
8009 {
8010 if (*c == '%')
8f06b2d8 8011 {
32c36c3c
AV		 8012 const char mod = *++c;
8013 switch (mod)
8f06b2d8 8014 {
0313a2b8
NC		 8015 case '%':
8016 func (stream, "%%");
8017 break;
8018
8019 case 'A':
32c36c3c 8020 case 'K':
05413229 8021 {
79862e45 8022 int rn = (given >> 16) & 0xf;
b0c11777 8023 bfd_vma offset = given & 0xff;
0313a2b8 8024
32c36c3c
AV		 8025 if (mod == 'K')
8026 offset = given & 0x7f;
8027
05413229 8028 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 8029
79862e45
DJ		 8030 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
8031 {
8032 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 8033 if (cp_num == 9)
8034 /* vldr.16/vstr.16 will shift the address
8035 left by 1 bit only. */
8036 offset = offset * 2;
8037 else
8038 offset = offset * 4;
8039
79862e45
DJ		 8040 if (NEGATIVE_BIT_SET)
8041 offset = - offset;
8042 if (rn != 15)
8043 value_in_comment = offset;
8044 }
8045
c1e26897 8046 if (PRE_BIT_SET)
05413229
NC		 8047 {
8048 if (offset)
fe56b6ce 8049 func (stream, ", #%d]%s",
d908c8af 8050 (int) offset,
c1e26897 8051 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 8052 else if (NEGATIVE_BIT_SET)
8053 func (stream, ", #-0]");
05413229
NC		 8054 else
8055 func (stream, "]");
8056 }
8057 else
8058 {
0313a2b8 8059 func (stream, "]");
8f06b2d8 8060
c1e26897 8061 if (WRITEBACK_BIT_SET)
05413229
NC		 8062 {
8063 if (offset)
d908c8af 8064 func (stream, ", #%d", (int) offset);
26d97720
NS		 8065 else if (NEGATIVE_BIT_SET)
8066 func (stream, ", #-0");
05413229
NC		 8067 }
8068 else
fe56b6ce 8069 {
26d97720
NS		 8070 func (stream, ", {%s%d}",
8071 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 8072 (int) offset);
fe56b6ce
NC		 8073 value_in_comment = offset;
8074 }
05413229 8075 }
79862e45
DJ		 8076 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
8077 {
8078 func (stream, "\t; ");
6844b2c2
MGD		 8079 /* For unaligned PCs, apply off-by-alignment
8080 correction. */
43e65147 8081 info->print_address_func (offset + pc
6844b2c2
MGD		 8082 + info->bytes_per_chunk * 2
8083 - (pc & 3),
dffaa15c 8084 info);
79862e45 8085 }
05413229 8086 }
0313a2b8 8087 break;
8f06b2d8 8088
0313a2b8
NC		 8089 case 'B':
8090 {
8091 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
8092 int offset = (given >> 1) & 0x3f;
8093
8094 if (offset == 1)
8095 func (stream, "{d%d}", regno);
8096 else if (regno + offset > 32)
8097 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
8098 else
8099 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
8100 }
8101 break;
8f06b2d8 8102
efd6b359
AV		 8103 case 'C':
8104 {
8105 bfd_boolean single = ((given >> 8) & 1) == 0;
8106 char reg_prefix = single ? 's' : 'd';
8107 int Dreg = (given >> 22) & 0x1;
8108 int Vdreg = (given >> 12) & 0xf;
8109 int reg = single ? ((Vdreg << 1) | Dreg)
8110 : ((Dreg << 4) | Vdreg);
8111 int num = (given >> (single ? 0 : 1)) & 0x7f;
8112 int maxreg = single ? 31 : 15;
8113 int topreg = reg + num - 1;
8114
8115 if (!num)
8116 func (stream, "{VPR}");
8117 else if (num == 1)
8118 func (stream, "{%c%d, VPR}", reg_prefix, reg);
8119 else if (topreg > maxreg)
8120 func (stream, "{%c%d-<overflow reg d%d, VPR}",
8121 reg_prefix, reg, single ? topreg >> 1 : topreg);
8122 else
8123 func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
8124 reg_prefix, topreg);
8125 }
8126 break;
8127
e2efe87d
MGD		 8128 case 'u':
8129 if (cond != COND_UNCOND)
8130 is_unpredictable = TRUE;
8131
8132 /* Fall through. */
0313a2b8 8133 case 'c':
b0c11777
RL		 8134 if (cond != COND_UNCOND && cp_num == 9)
8135 is_unpredictable = TRUE;
8136
0313a2b8
NC		 8137 func (stream, "%s", arm_conditional[cond]);
8138 break;
8f06b2d8 8139
0313a2b8
NC		 8140 case 'I':
8141 /* Print a Cirrus/DSP shift immediate. */
8142 /* Immediates are 7bit signed ints with bits 0..3 in
8143 bits 0..3 of opcode and bits 4..6 in bits 5..7
8144 of opcode. */
8145 {
8146 int imm;
8f06b2d8 8147
0313a2b8 8148 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 8149
0313a2b8
NC		 8150 /* Is ``imm'' a negative number? */
8151 if (imm & 0x40)
24b4cf66 8152 imm -= 0x80;
8f06b2d8 8153
0313a2b8
NC		 8154 func (stream, "%d", imm);
8155 }
8156
8157 break;
8f06b2d8 8158
32c36c3c
AV		 8159 case 'J':
8160 {
73cd51e5
AV		 8161 unsigned long regno
8162 = arm_decode_field_multiple (given, 13, 15, 22, 22);
32c36c3c
AV		 8163
8164 switch (regno)
8165 {
8166 case 0x1:
8167 func (stream, "FPSCR");
8168 break;
8169 case 0x2:
8170 func (stream, "FPSCR_nzcvqc");
8171 break;
8172 case 0xc:
8173 func (stream, "VPR");
8174 break;
8175 case 0xd:
8176 func (stream, "P0");
8177 break;
8178 case 0xe:
8179 func (stream, "FPCXTNS");
8180 break;
8181 case 0xf:
8182 func (stream, "FPCXTS");
8183 break;
8184 default:
73cd51e5 8185 func (stream, "<invalid reg %lu>", regno);
32c36c3c
AV		 8186 break;
8187 }
8188 }
8189 break;
8190
0313a2b8
NC		 8191 case 'F':
8192 switch (given & 0x00408000)
8193 {
8194 case 0:
8195 func (stream, "4");
8196 break;
8197 case 0x8000:
8198 func (stream, "1");
8199 break;
8200 case 0x00400000:
8201 func (stream, "2");
8f06b2d8 8202 break;
0313a2b8
NC		 8203 default:
8204 func (stream, "3");
8205 }
8206 break;
8f06b2d8 8207
0313a2b8
NC		 8208 case 'P':
8209 switch (given & 0x00080080)
8210 {
8211 case 0:
8212 func (stream, "s");
8213 break;
8214 case 0x80:
8215 func (stream, "d");
8216 break;
8217 case 0x00080000:
8218 func (stream, "e");
8219 break;
8220 default:
8221 func (stream, _("<illegal precision>"));
8f06b2d8 8222 break;
0313a2b8
NC		 8223 }
8224 break;
8f06b2d8 8225
0313a2b8
NC		 8226 case 'Q':
8227 switch (given & 0x00408000)
8228 {
8229 case 0:
8230 func (stream, "s");
8f06b2d8 8231 break;
0313a2b8
NC		 8232 case 0x8000:
8233 func (stream, "d");
8f06b2d8 8234 break;
0313a2b8
NC		 8235 case 0x00400000:
8236 func (stream, "e");
8237 break;
8238 default:
8239 func (stream, "p");
8f06b2d8 8240 break;
0313a2b8
NC		 8241 }
8242 break;
8f06b2d8 8243
0313a2b8
NC		 8244 case 'R':
8245 switch (given & 0x60)
8246 {
8247 case 0:
8248 break;
8249 case 0x20:
8250 func (stream, "p");
8251 break;
8252 case 0x40:
8253 func (stream, "m");
8254 break;
8255 default:
8256 func (stream, "z");
8257 break;
8258 }
8259 break;
16980d0b 8260
0313a2b8
NC		 8261 case '0': case '1': case '2': case '3': case '4':
8262 case '5': case '6': case '7': case '8': case '9':
8263 {
8264 int width;
8f06b2d8 8265
0313a2b8 8266 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 8267
0313a2b8
NC		 8268 switch (*c)
8269 {
ff4a8d2b
NC		 8270 case 'R':
8271 if (value == 15)
8272 is_unpredictable = TRUE;
8273 /* Fall through. */
0313a2b8 8274 case 'r':
ff4a8d2b
NC		 8275 if (c[1] == 'u')
8276 {
8277 /* Eat the 'u' character. */
8278 ++ c;
8279
8280 if (u_reg == value)
8281 is_unpredictable = TRUE;
8282 u_reg = value;
8283 }
0313a2b8
NC		 8284 func (stream, "%s", arm_regnames[value]);
8285 break;
c28eeff2
SN		 8286 case 'V':
8287 if (given & (1 << 6))
8288 goto Q;
8289 /* FALLTHROUGH */
0313a2b8
NC		 8290 case 'D':
8291 func (stream, "d%ld", value);
8292 break;
8293 case 'Q':
c28eeff2 8294 Q:
0313a2b8
NC		 8295 if (value & 1)
8296 func (stream, "<illegal reg q%ld.5>", value >> 1);
8297 else
8298 func (stream, "q%ld", value >> 1);
8299 break;
8300 case 'd':
8301 func (stream, "%ld", value);
05413229 8302 value_in_comment = value;
0313a2b8 8303 break;
6f1c2142
AM		 8304 case 'E':
8305 {
8306 /* Converts immediate 8 bit back to float value. */
8307 unsigned floatVal = (value & 0x80) << 24
8308 | (value & 0x3F) << 19
8309 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
8310
8311 /* Quarter float have a maximum value of 31.0.
8312 Get floating point value multiplied by 1e7.
8313 The maximum value stays in limit of a 32-bit int. */
8314 unsigned decVal =
8315 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
8316 (16 + (value & 0xF));
8317
8318 if (!(decVal % 1000000))
8319 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
8320 floatVal, value & 0x80 ? '-' : ' ',
8321 decVal / 10000000,
8322 decVal % 10000000 / 1000000);
8323 else if (!(decVal % 10000))
8324 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
8325 floatVal, value & 0x80 ? '-' : ' ',
8326 decVal / 10000000,
8327 decVal % 10000000 / 10000);
8328 else
8329 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
8330 floatVal, value & 0x80 ? '-' : ' ',
8331 decVal / 10000000, decVal % 10000000);
8332 break;
8333 }
0313a2b8
NC		 8334 case 'k':
8335 {
8336 int from = (given & (1 << 7)) ? 32 : 16;
8337 func (stream, "%ld", from - value);
8338 }
8339 break;
8f06b2d8 8340
0313a2b8
NC		 8341 case 'f':
8342 if (value > 7)
8343 func (stream, "#%s", arm_fp_const[value & 7]);
8344 else
8345 func (stream, "f%ld", value);
8346 break;
4146fd53 8347
0313a2b8
NC		 8348 case 'w':
8349 if (width == 2)
8350 func (stream, "%s", iwmmxt_wwnames[value]);
8351 else
8352 func (stream, "%s", iwmmxt_wwssnames[value]);
8353 break;
4146fd53 8354
0313a2b8
NC		 8355 case 'g':
8356 func (stream, "%s", iwmmxt_regnames[value]);
8357 break;
8358 case 'G':
8359 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 8360 break;
8f06b2d8 8361
0313a2b8 8362 case 'x':
d1aaab3c 8363 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 8364 break;
8f06b2d8 8365
33399f07
MGD		 8366 case 'c':
8367 switch (value)
8368 {
8369 case 0:
8370 func (stream, "eq");
8371 break;
8372
8373 case 1:
8374 func (stream, "vs");
8375 break;
8376
8377 case 2:
8378 func (stream, "ge");
8379 break;
8380
8381 case 3:
8382 func (stream, "gt");
8383 break;
8384
8385 default:
8386 func (stream, "??");
8387 break;
8388 }
8389 break;
8390
0313a2b8
NC		 8391 case '`':
8392 c++;
8393 if (value == 0)
8394 func (stream, "%c", *c);
8395 break;
8396 case '\'':
8397 c++;
8398 if (value == ((1ul << width) - 1))
8399 func (stream, "%c", *c);
8400 break;
8401 case '?':
fe56b6ce 8402 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 8403 c += 1 << width;
8404 break;
8405 default:
8406 abort ();
8407 }
dffaa15c
AM		 8408 }
8409 break;
0313a2b8 8410
dffaa15c
AM		 8411 case 'y':
8412 case 'z':
8413 {
8414 int single = *c++ == 'y';
8415 int regno;
8f06b2d8 8416
dffaa15c
AM		 8417 switch (*c)
8418 {
8419 case '4': /* Sm pair */
8420 case '0': /* Sm, Dm */
8421 regno = given & 0x0000000f;
8422 if (single)
8423 {
8424 regno <<= 1;
8425 regno += (given >> 5) & 1;
8426 }
8427 else
8428 regno += ((given >> 5) & 1) << 4;
8429 break;
8f06b2d8 8430
dffaa15c
AM		 8431 case '1': /* Sd, Dd */
8432 regno = (given >> 12) & 0x0000000f;
8433 if (single)
8434 {
8435 regno <<= 1;
8436 regno += (given >> 22) & 1;
8437 }
8438 else
8439 regno += ((given >> 22) & 1) << 4;
8440 break;
7df76b80 8441
dffaa15c
AM		 8442 case '2': /* Sn, Dn */
8443 regno = (given >> 16) & 0x0000000f;
8444 if (single)
8445 {
8446 regno <<= 1;
8447 regno += (given >> 7) & 1;
8448 }
8449 else
8450 regno += ((given >> 7) & 1) << 4;
8451 break;
a7f8487e 8452
dffaa15c
AM		 8453 case '3': /* List */
8454 func (stream, "{");
8455 regno = (given >> 12) & 0x0000000f;
8456 if (single)
8457 {
8458 regno <<= 1;
8459 regno += (given >> 22) & 1;
8460 }
8461 else
8462 regno += ((given >> 22) & 1) << 4;
8463 break;
a7f8487e 8464
dffaa15c
AM		 8465 default:
8466 abort ();
8467 }
0313a2b8 8468
dffaa15c 8469 func (stream, "%c%d", single ? 's' : 'd', regno);
a7f8487e 8470
dffaa15c
AM		 8471 if (*c == '3')
8472 {
8473 int count = given & 0xff;
b34976b6 8474
dffaa15c
AM		 8475 if (single == 0)
8476 count >>= 1;
0313a2b8 8477
dffaa15c
AM		 8478 if (--count)
8479 {
8480 func (stream, "-%c%d",
8481 single ? 's' : 'd',
8482 regno + count);
8483 }
0313a2b8 8484
dffaa15c 8485 func (stream, "}");
0313a2b8 8486 }
dffaa15c
AM		 8487 else if (*c == '4')
8488 func (stream, ", %c%d", single ? 's' : 'd',
8489 regno + 1);
8490 }
8491 break;
b34976b6 8492
dffaa15c
AM		 8493 case 'L':
8494 switch (given & 0x00400100)
0313a2b8 8495 {
dffaa15c
AM		 8496 case 0x00000000: func (stream, "b"); break;
8497 case 0x00400000: func (stream, "h"); break;
8498 case 0x00000100: func (stream, "w"); break;
8499 case 0x00400100: func (stream, "d"); break;
8500 default:
8501 break;
0313a2b8 8502 }
dffaa15c 8503 break;
2d447fca 8504
dffaa15c
AM		 8505 case 'Z':
8506 {
8507 /* given (20, 23) | given (0, 3) */
8508 value = ((given >> 16) & 0xf0) | (given & 0xf);
8509 func (stream, "%d", (int) value);
8510 }
8511 break;
0313a2b8 8512
dffaa15c
AM		 8513 case 'l':
8514 /* This is like the 'A' operator, except that if
8515 the width field "M" is zero, then the offset is
8516 *not* multiplied by four. */
8517 {
8518 int offset = given & 0xff;
8519 int multiplier = (given & 0x00000100) ? 4 : 1;
0313a2b8 8520
dffaa15c 8521 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
05413229 8522
dffaa15c
AM		 8523 if (multiplier > 1)
8524 {
8525 value_in_comment = offset * multiplier;
8526 if (NEGATIVE_BIT_SET)
8527 value_in_comment = - value_in_comment;
8528 }
0313a2b8 8529
dffaa15c
AM		 8530 if (offset)
8531 {
8532 if (PRE_BIT_SET)
8533 func (stream, ", #%s%d]%s",
8534 NEGATIVE_BIT_SET ? "-" : "",
8535 offset * multiplier,
8536 WRITEBACK_BIT_SET ? "!" : "");
8537 else
8538 func (stream, "], #%s%d",
8539 NEGATIVE_BIT_SET ? "-" : "",
8540 offset * multiplier);
8541 }
8542 else
8543 func (stream, "]");
8544 }
8545 break;
2d447fca 8546
dffaa15c
AM		 8547 case 'r':
8548 {
8549 int imm4 = (given >> 4) & 0xf;
8550 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
8551 int ubit = ! NEGATIVE_BIT_SET;
8552 const char *rm = arm_regnames [given & 0xf];
8553 const char *rn = arm_regnames [(given >> 16) & 0xf];
0313a2b8 8554
dffaa15c
AM		 8555 switch (puw_bits)
8556 {
8557 case 1:
8558 case 3:
8559 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
8560 if (imm4)
8561 func (stream, ", lsl #%d", imm4);
8562 break;
0313a2b8 8563
dffaa15c
AM		 8564 case 4:
8565 case 5:
8566 case 6:
8567 case 7:
8568 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
8569 if (imm4 > 0)
8570 func (stream, ", lsl #%d", imm4);
8571 func (stream, "]");
8572 if (puw_bits == 5 || puw_bits == 7)
8573 func (stream, "!");
8574 break;
2d447fca 8575
dffaa15c
AM		 8576 default:
8577 func (stream, "INVALID");
8578 }
8579 }
8580 break;
0313a2b8 8581
dffaa15c
AM		 8582 case 'i':
8583 {
8584 long imm5;
8585 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
8586 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
0313a2b8 8587 }
dffaa15c
AM		 8588 break;
8589
8590 default:
8591 abort ();
252b5132 8592 }
252b5132 8593 }
0313a2b8
NC		 8594 else
8595 func (stream, "%c", *c);
252b5132 8596 }
05413229
NC		 8597
8598 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 8599 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 8600
ff4a8d2b
NC		 8601 if (is_unpredictable)
8602 func (stream, UNPREDICTABLE_INSTRUCTION);
8603
0313a2b8 8604 return TRUE;
252b5132 8605 }
8f06b2d8 8606 return FALSE;
252b5132
RH		 8607}
8608
05413229
NC		 8609/* Decodes and prints ARM addressing modes. Returns the offset
8610 used in the address, if any, if it is worthwhile printing the
8611 offset as a hexadecimal value in a comment at the end of the
8612 line of disassembly. */
8613
8614static signed long
62b3e311
PB		 8615print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
8616{
8617 void *stream = info->stream;
8618 fprintf_ftype func = info->fprintf_func;
f8b960bc 8619 bfd_vma offset = 0;
62b3e311
PB		 8620
8621 if (((given & 0x000f0000) == 0x000f0000)
8622 && ((given & 0x02000000) == 0))
8623 {
05413229 8624 offset = given & 0xfff;
62b3e311
PB		 8625
8626 func (stream, "[pc");
8627
c1e26897 8628 if (PRE_BIT_SET)
62b3e311 8629 {
26d97720
NS		 8630 /* Pre-indexed. Elide offset of positive zero when
8631 non-writeback. */
8632 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 8633 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 8634
8635 if (NEGATIVE_BIT_SET)
8636 offset = -offset;
62b3e311
PB		 8637
8638 offset += pc + 8;
8639
8640 /* Cope with the possibility of write-back
8641 being used. Probably a very dangerous thing
8642 for the programmer to do, but who are we to
8643 argue ? */
26d97720 8644 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 8645 }
c1e26897 8646 else /* Post indexed. */
62b3e311 8647 {
d908c8af 8648 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 8649
c1e26897 8650 /* Ie ignore the offset. */
62b3e311
PB		 8651 offset = pc + 8;
8652 }
8653
8654 func (stream, "\t; ");
8655 info->print_address_func (offset, info);
05413229 8656 offset = 0;
62b3e311
PB		 8657 }
8658 else
8659 {
8660 func (stream, "[%s",
8661 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 8662
8663 if (PRE_BIT_SET)
62b3e311
PB		 8664 {
8665 if ((given & 0x02000000) == 0)
8666 {
26d97720 8667 /* Elide offset of positive zero when non-writeback. */
05413229 8668 offset = given & 0xfff;
26d97720 8669 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 8670 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 8671 }
8672 else
8673 {
26d97720 8674 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 8675 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 8676 }
8677
8678 func (stream, "]%s",
c1e26897 8679 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 8680 }
8681 else
8682 {
8683 if ((given & 0x02000000) == 0)
8684 {
26d97720 8685 /* Always show offset. */
05413229 8686 offset = given & 0xfff;
26d97720 8687 func (stream, "], #%s%d",
d908c8af 8688 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 8689 }
8690 else
8691 {
8692 func (stream, "], %s",
c1e26897 8693 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 8694 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 8695 }
8696 }
84919466
MR		 8697 if (NEGATIVE_BIT_SET)
8698 offset = -offset;
62b3e311 8699 }
05413229
NC		 8700
8701 return (signed long) offset;
62b3e311
PB		 8702}
8703
16980d0b
JB		 8704/* Print one neon instruction on INFO->STREAM.
8705 Return TRUE if the instuction matched, FALSE if this is not a
8706 recognised neon instruction. */
8707
8708static bfd_boolean
8709print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
8710{
8711 const struct opcode32 *insn;
8712 void *stream = info->stream;
8713 fprintf_ftype func = info->fprintf_func;
8714
8715 if (thumb)
8716 {
8717 if ((given & 0xef000000) == 0xef000000)
8718 {
0313a2b8 8719 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 8720 unsigned long bit28 = given & (1 << 28);
8721
8722 given &= 0x00ffffff;
8723 if (bit28)
8724 given |= 0xf3000000;
8725 else
8726 given |= 0xf2000000;
8727 }
8728 else if ((given & 0xff000000) == 0xf9000000)
8729 given ^= 0xf9000000 ^ 0xf4000000;
9743db03
AV		 8730 /* vdup is also a valid neon instruction. */
8731 else if ((given & 0xff910f5f) != 0xee800b10)
16980d0b
JB		 8732 return FALSE;
8733 }
43e65147 8734
16980d0b
JB		 8735 for (insn = neon_opcodes; insn->assembler; insn++)
8736 {
8737 if ((given & insn->mask) == insn->value)
8738 {
05413229 8739 signed long value_in_comment = 0;
e2efe87d 8740 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 8741 const char *c;
8742
8743 for (c = insn->assembler; *c; c++)
8744 {
8745 if (*c == '%')
8746 {
8747 switch (*++c)
8748 {
8749 case '%':
8750 func (stream, "%%");
8751 break;
8752
e2efe87d
MGD		 8753 case 'u':
8754 if (thumb && ifthen_state)
8755 is_unpredictable = TRUE;
8756
8757 /* Fall through. */
c22aaad1
PB		 8758 case 'c':
8759 if (thumb && ifthen_state)
8760 func (stream, "%s", arm_conditional[IFTHEN_COND]);
8761 break;
8762
16980d0b
JB		 8763 case 'A':
8764 {
43e65147 8765 static const unsigned char enc[16] =
16980d0b
JB		 8766 {
8767 0x4, 0x14, /* st4 0,1 */
8768 0x4, /* st1 2 */
8769 0x4, /* st2 3 */
8770 0x3, /* st3 4 */
8771 0x13, /* st3 5 */
8772 0x3, /* st1 6 */
8773 0x1, /* st1 7 */
8774 0x2, /* st2 8 */
8775 0x12, /* st2 9 */
8776 0x2, /* st1 10 */
8777 0, 0, 0, 0, 0
8778 };
8779 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8780 int rn = ((given >> 16) & 0xf);
8781 int rm = ((given >> 0) & 0xf);
8782 int align = ((given >> 4) & 0x3);
8783 int type = ((given >> 8) & 0xf);
8784 int n = enc[type] & 0xf;
8785 int stride = (enc[type] >> 4) + 1;
8786 int ix;
43e65147 8787
16980d0b
JB		 8788 func (stream, "{");
8789 if (stride > 1)
8790 for (ix = 0; ix != n; ix++)
8791 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
8792 else if (n == 1)
8793 func (stream, "d%d", rd);
8794 else
8795 func (stream, "d%d-d%d", rd, rd + n - 1);
8796 func (stream, "}, [%s", arm_regnames[rn]);
8797 if (align)
8e560766 8798 func (stream, " :%d", 32 << align);
16980d0b
JB		 8799 func (stream, "]");
8800 if (rm == 0xd)
8801 func (stream, "!");
8802 else if (rm != 0xf)
8803 func (stream, ", %s", arm_regnames[rm]);
8804 }
8805 break;
43e65147 8806
16980d0b
JB		 8807 case 'B':
8808 {
8809 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8810 int rn = ((given >> 16) & 0xf);
8811 int rm = ((given >> 0) & 0xf);
8812 int idx_align = ((given >> 4) & 0xf);
8813 int align = 0;
8814 int size = ((given >> 10) & 0x3);
8815 int idx = idx_align >> (size + 1);
8816 int length = ((given >> 8) & 3) + 1;
8817 int stride = 1;
8818 int i;
8819
8820 if (length > 1 && size > 0)
8821 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 8822
16980d0b
JB		 8823 switch (length)
8824 {
8825 case 1:
8826 {
8827 int amask = (1 << size) - 1;
8828 if ((idx_align & (1 << size)) != 0)
8829 return FALSE;
8830 if (size > 0)
8831 {
8832 if ((idx_align & amask) == amask)
8833 align = 8 << size;
8834 else if ((idx_align & amask) != 0)
8835 return FALSE;
8836 }
8837 }
8838 break;
43e65147 8839
16980d0b
JB		 8840 case 2:
8841 if (size == 2 && (idx_align & 2) != 0)
8842 return FALSE;
8843 align = (idx_align & 1) ? 16 << size : 0;
8844 break;
43e65147 8845
16980d0b
JB		 8846 case 3:
8847 if ((size == 2 && (idx_align & 3) != 0)
8848 || (idx_align & 1) != 0)
8849 return FALSE;
8850 break;
43e65147 8851
16980d0b
JB		 8852 case 4:
8853 if (size == 2)
8854 {
8855 if ((idx_align & 3) == 3)
8856 return FALSE;
8857 align = (idx_align & 3) * 64;
8858 }
8859 else
8860 align = (idx_align & 1) ? 32 << size : 0;
8861 break;
43e65147 8862
16980d0b
JB		 8863 default:
8864 abort ();
8865 }
43e65147 8866
16980d0b
JB		 8867 func (stream, "{");
8868 for (i = 0; i < length; i++)
8869 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
8870 rd + i * stride, idx);
8871 func (stream, "}, [%s", arm_regnames[rn]);
8872 if (align)
8e560766 8873 func (stream, " :%d", align);
16980d0b
JB		 8874 func (stream, "]");
8875 if (rm == 0xd)
8876 func (stream, "!");
8877 else if (rm != 0xf)
8878 func (stream, ", %s", arm_regnames[rm]);
8879 }
8880 break;
43e65147 8881
16980d0b
JB		 8882 case 'C':
8883 {
8884 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8885 int rn = ((given >> 16) & 0xf);
8886 int rm = ((given >> 0) & 0xf);
8887 int align = ((given >> 4) & 0x1);
8888 int size = ((given >> 6) & 0x3);
8889 int type = ((given >> 8) & 0x3);
8890 int n = type + 1;
8891 int stride = ((given >> 5) & 0x1);
8892 int ix;
43e65147 8893
16980d0b
JB		 8894 if (stride && (n == 1))
8895 n++;
8896 else
8897 stride++;
43e65147 8898
16980d0b
JB		 8899 func (stream, "{");
8900 if (stride > 1)
8901 for (ix = 0; ix != n; ix++)
8902 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
8903 else if (n == 1)
8904 func (stream, "d%d[]", rd);
8905 else
8906 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
8907 func (stream, "}, [%s", arm_regnames[rn]);
8908 if (align)
8909 {
91d6fa6a 8910 align = (8 * (type + 1)) << size;
16980d0b
JB		 8911 if (type == 3)
8912 align = (size > 1) ? align >> 1 : align;
8913 if (type == 2 || (type == 0 && !size))
8e560766 8914 func (stream, " :<bad align %d>", align);
16980d0b 8915 else
8e560766 8916 func (stream, " :%d", align);
16980d0b
JB		 8917 }
8918 func (stream, "]");
8919 if (rm == 0xd)
8920 func (stream, "!");
8921 else if (rm != 0xf)
8922 func (stream, ", %s", arm_regnames[rm]);
8923 }
8924 break;
43e65147 8925
16980d0b
JB		 8926 case 'D':
8927 {
8928 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
8929 int size = (given >> 20) & 3;
8930 int reg = raw_reg & ((4 << size) - 1);
8931 int ix = raw_reg >> size >> 2;
43e65147 8932
16980d0b
JB		 8933 func (stream, "d%d[%d]", reg, ix);
8934 }
8935 break;
43e65147 8936
16980d0b 8937 case 'E':
fe56b6ce 8938 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 8939 {
8940 int bits = 0;
8941 int cmode = (given >> 8) & 0xf;
8942 int op = (given >> 5) & 0x1;
8943 unsigned long value = 0, hival = 0;
8944 unsigned shift;
8945 int size = 0;
0dbde4cf 8946 int isfloat = 0;
43e65147 8947
16980d0b
JB		 8948 bits |= ((given >> 24) & 1) << 7;
8949 bits |= ((given >> 16) & 7) << 4;
8950 bits |= ((given >> 0) & 15) << 0;
43e65147 8951
16980d0b
JB		 8952 if (cmode < 8)
8953 {
8954 shift = (cmode >> 1) & 3;
fe56b6ce 8955 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 8956 size = 32;
8957 }
8958 else if (cmode < 12)
8959 {
8960 shift = (cmode >> 1) & 1;
fe56b6ce 8961 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 8962 size = 16;
8963 }
8964 else if (cmode < 14)
8965 {
8966 shift = (cmode & 1) + 1;
fe56b6ce 8967 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 8968 value |= (1ul << (8 * shift)) - 1;
8969 size = 32;
8970 }
8971 else if (cmode == 14)
8972 {
8973 if (op)
8974 {
fe56b6ce 8975 /* Bit replication into bytes. */
16980d0b
JB		 8976 int ix;
8977 unsigned long mask;
43e65147 8978
16980d0b
JB		 8979 value = 0;
8980 hival = 0;
8981 for (ix = 7; ix >= 0; ix--)
8982 {
8983 mask = ((bits >> ix) & 1) ? 0xff : 0;
8984 if (ix <= 3)
8985 value = (value << 8) | mask;
8986 else
8987 hival = (hival << 8) | mask;
8988 }
8989 size = 64;
8990 }
8991 else
8992 {
fe56b6ce
NC		 8993 /* Byte replication. */
8994 value = (unsigned long) bits;
16980d0b
JB		 8995 size = 8;
8996 }
8997 }
8998 else if (!op)
8999 {
fe56b6ce 9000 /* Floating point encoding. */
16980d0b 9001 int tmp;
43e65147 9002
fe56b6ce
NC		 9003 value = (unsigned long) (bits & 0x7f) << 19;
9004 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 9005 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 9006 value |= (unsigned long) tmp << 24;
16980d0b 9007 size = 32;
0dbde4cf 9008 isfloat = 1;
16980d0b
JB		 9009 }
9010 else
9011 {
9012 func (stream, "<illegal constant %.8x:%x:%x>",
9013 bits, cmode, op);
9014 size = 32;
9015 break;
9016 }
9017 switch (size)
9018 {
9019 case 8:
9020 func (stream, "#%ld\t; 0x%.2lx", value, value);
9021 break;
43e65147 9022
16980d0b
JB		 9023 case 16:
9024 func (stream, "#%ld\t; 0x%.4lx", value, value);
9025 break;
9026
9027 case 32:
0dbde4cf
JB		 9028 if (isfloat)
9029 {
9030 unsigned char valbytes[4];
9031 double fvalue;
43e65147 9032
0dbde4cf
JB		 9033 /* Do this a byte at a time so we don't have to
9034 worry about the host's endianness. */
9035 valbytes[0] = value & 0xff;
9036 valbytes[1] = (value >> 8) & 0xff;
9037 valbytes[2] = (value >> 16) & 0xff;
9038 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 9039
9040 floatformat_to_double
c1e26897
NC		 9041 (& floatformat_ieee_single_little, valbytes,
9042 & fvalue);
43e65147 9043
0dbde4cf
JB		 9044 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
9045 value);
9046 }
9047 else
4e9d3b81 9048 func (stream, "#%ld\t; 0x%.8lx",
43e65147 9049 (long) (((value & 0x80000000L) != 0)
9d82ec38 9050 ? value | ~0xffffffffL : value),
c1e26897 9051 value);
16980d0b
JB		 9052 break;
9053
9054 case 64:
9055 func (stream, "#0x%.8lx%.8lx", hival, value);
9056 break;
43e65147 9057
16980d0b
JB		 9058 default:
9059 abort ();
9060 }
9061 }
9062 break;
43e65147 9063
16980d0b
JB		 9064 case 'F':
9065 {
9066 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
9067 int num = (given >> 8) & 0x3;
43e65147 9068
16980d0b
JB		 9069 if (!num)
9070 func (stream, "{d%d}", regno);
9071 else if (num + regno >= 32)
9072 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
9073 else
9074 func (stream, "{d%d-d%d}", regno, regno + num);
9075 }
9076 break;
7e8e6784 9077
16980d0b
JB		 9078
9079 case '0': case '1': case '2': case '3': case '4':
9080 case '5': case '6': case '7': case '8': case '9':
9081 {
9082 int width;
9083 unsigned long value;
9084
9085 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 9086
16980d0b
JB		 9087 switch (*c)
9088 {
9089 case 'r':
9090 func (stream, "%s", arm_regnames[value]);
9091 break;
9092 case 'd':
9093 func (stream, "%ld", value);
05413229 9094 value_in_comment = value;
16980d0b
JB		 9095 break;
9096 case 'e':
9097 func (stream, "%ld", (1ul << width) - value);
9098 break;
43e65147 9099
16980d0b
JB		 9100 case 'S':
9101 case 'T':
9102 case 'U':
05413229 9103 /* Various width encodings. */
16980d0b
JB		 9104 {
9105 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
9106 int limit;
9107 unsigned low, high;
9108
9109 c++;
9110 if (*c >= '0' && *c <= '9')
9111 limit = *c - '0';
9112 else if (*c >= 'a' && *c <= 'f')
9113 limit = *c - 'a' + 10;
9114 else
9115 abort ();
9116 low = limit >> 2;
9117 high = limit & 3;
9118
9119 if (value < low || value > high)
9120 func (stream, "<illegal width %d>", base << value);
9121 else
9122 func (stream, "%d", base << value);
9123 }
9124 break;
9125 case 'R':
9126 if (given & (1 << 6))
9127 goto Q;
9128 /* FALLTHROUGH */
9129 case 'D':
9130 func (stream, "d%ld", value);
9131 break;
9132 case 'Q':
9133 Q:
9134 if (value & 1)
9135 func (stream, "<illegal reg q%ld.5>", value >> 1);
9136 else
9137 func (stream, "q%ld", value >> 1);
9138 break;
43e65147 9139
16980d0b
JB		 9140 case '`':
9141 c++;
9142 if (value == 0)
9143 func (stream, "%c", *c);
9144 break;
9145 case '\'':
9146 c++;
9147 if (value == ((1ul << width) - 1))
9148 func (stream, "%c", *c);
9149 break;
9150 case '?':
fe56b6ce 9151 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 9152 c += 1 << width;
9153 break;
9154 default:
9155 abort ();
9156 }
16980d0b 9157 }
dffaa15c
AM		 9158 break;
9159
9160 default:
9161 abort ();
16980d0b
JB		 9162 }
9163 }
9164 else
9165 func (stream, "%c", *c);
9166 }
05413229
NC		 9167
9168 if (value_in_comment > 32 || value_in_comment < -16)
9169 func (stream, "\t; 0x%lx", value_in_comment);
9170
e2efe87d
MGD		 9171 if (is_unpredictable)
9172 func (stream, UNPREDICTABLE_INSTRUCTION);
9173
16980d0b
JB		 9174 return TRUE;
9175 }
9176 }
9177 return FALSE;
9178}
9179
73cd51e5
AV		 9180/* Print one mve instruction on INFO->STREAM.
9181 Return TRUE if the instuction matched, FALSE if this is not a
9182 recognised mve instruction. */
9183
9184static bfd_boolean
9185print_insn_mve (struct disassemble_info *info, long given)
9186{
9187 const struct mopcode32 *insn;
9188 void *stream = info->stream;
9189 fprintf_ftype func = info->fprintf_func;
9190
9191 for (insn = mve_opcodes; insn->assembler; insn++)
9192 {
9193 if (((given & insn->mask) == insn->value)
9194 && !is_mve_encoding_conflict (given, insn->mve_op))
9195 {
9196 signed long value_in_comment = 0;
9197 bfd_boolean is_unpredictable = FALSE;
9198 bfd_boolean is_undefined = FALSE;
9199 const char *c;
9200 enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
9201 enum mve_undefined undefined_cond = UNDEF_NONE;
9202
9203 /* Most vector mve instruction are illegal in a it block.
9204 There are a few exceptions; check for them. */
9205 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
9206 {
9207 is_unpredictable = TRUE;
9208 unpredictable_cond = UNPRED_IT_BLOCK;
9209 }
9210 else if (is_mve_unpredictable (given, insn->mve_op,
9211 &unpredictable_cond))
9212 is_unpredictable = TRUE;
9213
9214 if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
9215 is_undefined = TRUE;
9216
9217 for (c = insn->assembler; *c; c++)
9218 {
9219 if (*c == '%')
9220 {
9221 switch (*++c)
9222 {
9223 case '%':
9224 func (stream, "%%");
9225 break;
9226
ef1576a1
AV		 9227 case 'a':
9228 /* Don't print anything for '+' as it is implied. */
9229 if (arm_decode_field (given, 23, 23) == 0)
9230 func (stream, "-");
9231 break;
9232
143275ea
AV		 9233 case 'c':
9234 if (ifthen_state)
9235 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9236 break;
9237
aef6d006
AV		 9238 case 'd':
9239 print_mve_vld_str_addr (info, given, insn->mve_op);
9240 break;
9241
143275ea
AV		 9242 case 'i':
9243 {
9244 long mve_mask = mve_extract_pred_mask (given);
9245 func (stream, "%s", mve_predicatenames[mve_mask]);
9246 }
9247 break;
9248
23d00a41
SD		 9249 case 'j':
9250 {
9251 unsigned int imm5 = 0;
9252 imm5 |= arm_decode_field (given, 6, 7);
9253 imm5 |= (arm_decode_field (given, 12, 14) << 2);
9254 func (stream, "#%u", (imm5 == 0) ? 32 : imm5);
9255 }
9256 break;
9257
08132bdd
SP		 9258 case 'k':
9259 func (stream, "#%u",
9260 (arm_decode_field (given, 7, 7) == 0) ? 64 : 48);
9261 break;
9262
143275ea
AV		 9263 case 'n':
9264 print_vec_condition (info, given, insn->mve_op);
9265 break;
9266
ef1576a1
AV		 9267 case 'o':
9268 if (arm_decode_field (given, 0, 0) == 1)
9269 {
9270 unsigned long size
9271 = arm_decode_field (given, 4, 4)
9272 | (arm_decode_field (given, 6, 6) << 1);
9273
9274 func (stream, ", uxtw #%lu", size);
9275 }
9276 break;
9277
bf0b396d
AV		 9278 case 'm':
9279 print_mve_rounding_mode (info, given, insn->mve_op);
9280 break;
9281
9282 case 's':
9283 print_mve_vcvt_size (info, given, insn->mve_op);
9284 break;
9285
aef6d006
AV		 9286 case 'u':
9287 {
c507f10b
AV		 9288 unsigned long op1 = arm_decode_field (given, 21, 22);
9289
9290 if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
9291 {
9292 /* Check for signed. */
9293 if (arm_decode_field (given, 23, 23) == 0)
9294 {
9295 /* We don't print 's' for S32. */
9296 if ((arm_decode_field (given, 5, 6) == 0)
9297 && ((op1 == 0) || (op1 == 1)))
9298 ;
9299 else
9300 func (stream, "s");
9301 }
9302 else
9303 func (stream, "u");
9304 }
aef6d006 9305 else
c507f10b
AV		 9306 {
9307 if (arm_decode_field (given, 28, 28) == 0)
9308 func (stream, "s");
9309 else
9310 func (stream, "u");
9311 }
aef6d006 9312 }
ef1576a1 9313 break;
aef6d006 9314
143275ea
AV		 9315 case 'v':
9316 print_instruction_predicate (info);
9317 break;
9318
04d54ace
AV		 9319 case 'w':
9320 if (arm_decode_field (given, 21, 21) == 1)
9321 func (stream, "!");
9322 break;
9323
9324 case 'B':
9325 print_mve_register_blocks (info, given, insn->mve_op);
9326 break;
9327
c507f10b
AV		 9328 case 'E':
9329 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
9330
9331 print_simd_imm8 (info, given, 28, insn);
9332 break;
9333
9334 case 'N':
9335 print_mve_vmov_index (info, given);
9336 break;
9337
14925797
AV		 9338 case 'T':
9339 if (arm_decode_field (given, 12, 12) == 0)
9340 func (stream, "b");
9341 else
9342 func (stream, "t");
9343 break;
9344
d3b63143
AV		 9345 case 'X':
9346 if (arm_decode_field (given, 12, 12) == 1)
9347 func (stream, "x");
9348 break;
9349
143275ea
AV		 9350 case '0': case '1': case '2': case '3': case '4':
9351 case '5': case '6': case '7': case '8': case '9':
9352 {
9353 int width;
9354 unsigned long value;
9355
9356 c = arm_decode_bitfield (c, given, &value, &width);
9357
9358 switch (*c)
9359 {
9360 case 'Z':
9361 if (value == 13)
9362 is_unpredictable = TRUE;
9363 else if (value == 15)
9364 func (stream, "zr");
9365 else
9366 func (stream, "%s", arm_regnames[value]);
9367 break;
23d00a41 9368
e39c1607
SD		 9369 case 'c':
9370 func (stream, "%s", arm_conditional[value]);
9371 break;
9372
9373 case 'C':
9374 value ^= 1;
9375 func (stream, "%s", arm_conditional[value]);
9376 break;
9377
23d00a41
SD		 9378 case 'S':
9379 if (value == 13 || value == 15)
9380 is_unpredictable = TRUE;
9381 else
9382 func (stream, "%s", arm_regnames[value]);
9383 break;
9384
143275ea
AV		 9385 case 's':
9386 print_mve_size (info,
9387 value,
9388 insn->mve_op);
9389 break;
66dcaa5d
AV		 9390 case 'I':
9391 if (value == 1)
9392 func (stream, "i");
9393 break;
d3b63143
AV		 9394 case 'A':
9395 if (value == 1)
9396 func (stream, "a");
9397 break;
1c8f2df8
AV		 9398 case 'h':
9399 {
9400 unsigned int odd_reg = (value << 1) | 1;
9401 func (stream, "%s", arm_regnames[odd_reg]);
9402 }
9403 break;
ef1576a1
AV		 9404 case 'i':
9405 {
9406 unsigned long imm
9407 = arm_decode_field (given, 0, 6);
9408 unsigned long mod_imm = imm;
9409
9410 switch (insn->mve_op)
9411 {
9412 case MVE_VLDRW_GATHER_T5:
9413 case MVE_VSTRW_SCATTER_T5:
9414 mod_imm = mod_imm << 2;
9415 break;
9416 case MVE_VSTRD_SCATTER_T6:
9417 case MVE_VLDRD_GATHER_T6:
9418 mod_imm = mod_imm << 3;
9419 break;
9420
9421 default:
9422 break;
9423 }
9424
9425 func (stream, "%lu", mod_imm);
9426 }
9427 break;
bf0b396d
AV		 9428 case 'k':
9429 func (stream, "%lu", 64 - value);
9430 break;
1c8f2df8
AV		 9431 case 'l':
9432 {
9433 unsigned int even_reg = value << 1;
9434 func (stream, "%s", arm_regnames[even_reg]);
9435 }
9436 break;
9437 case 'u':
9438 switch (value)
9439 {
9440 case 0:
9441 func (stream, "1");
9442 break;
9443 case 1:
9444 func (stream, "2");
9445 break;
9446 case 2:
9447 func (stream, "4");
9448 break;
9449 case 3:
9450 func (stream, "8");
9451 break;
9452 default:
9453 break;
9454 }
9455 break;
897b9bbc
AV		 9456 case 'o':
9457 print_mve_rotate (info, value, width);
9458 break;
9743db03
AV		 9459 case 'r':
9460 func (stream, "%s", arm_regnames[value]);
9461 break;
04d54ace 9462 case 'd':
ed63aa17
AV		 9463 if (insn->mve_op == MVE_VQSHL_T2
9464 || insn->mve_op == MVE_VQSHLU_T3
9465 || insn->mve_op == MVE_VRSHR
9466 || insn->mve_op == MVE_VRSHRN
9467 || insn->mve_op == MVE_VSHL_T1
9468 || insn->mve_op == MVE_VSHLL_T1
9469 || insn->mve_op == MVE_VSHR
9470 || insn->mve_op == MVE_VSHRN
9471 || insn->mve_op == MVE_VSLI
9472 || insn->mve_op == MVE_VSRI)
9473 print_mve_shift_n (info, given, insn->mve_op);
9474 else if (insn->mve_op == MVE_VSHLL_T2)
9475 {
9476 switch (value)
9477 {
9478 case 0x00:
9479 func (stream, "8");
9480 break;
9481 case 0x01:
9482 func (stream, "16");
9483 break;
9484 case 0x10:
9485 print_mve_undefined (info, UNDEF_SIZE_0);
9486 break;
9487 default:
9488 assert (0);
9489 break;
9490 }
9491 }
9492 else
9493 {
9494 if (insn->mve_op == MVE_VSHLC && value == 0)
9495 value = 32;
9496 func (stream, "%ld", value);
9497 value_in_comment = value;
9498 }
04d54ace 9499 break;
c507f10b
AV		 9500 case 'F':
9501 func (stream, "s%ld", value);
9502 break;
143275ea
AV		 9503 case 'Q':
9504 if (value & 0x8)
9505 func (stream, "<illegal reg q%ld.5>", value);
9506 else
9507 func (stream, "q%ld", value);
9508 break;
c507f10b
AV		 9509 case 'x':
9510 func (stream, "0x%08lx", value);
9511 break;
143275ea
AV		 9512 default:
9513 abort ();
9514 }
9515 break;
9516 default:
9517 abort ();
9518 }
73cd51e5
AV		 9519 }
9520 }
9521 else
9522 func (stream, "%c", *c);
9523 }
9524
9525 if (value_in_comment > 32 || value_in_comment < -16)
9526 func (stream, "\t; 0x%lx", value_in_comment);
9527
9528 if (is_unpredictable)
9529 print_mve_unpredictable (info, unpredictable_cond);
9530
9531 if (is_undefined)
9532 print_mve_undefined (info, undefined_cond);
9533
143275ea
AV		 9534 if ((vpt_block_state.in_vpt_block == FALSE)
9535 && !ifthen_state
9536 && (is_vpt_instruction (given) == TRUE))
9537 mark_inside_vpt_block (given);
9538 else if (vpt_block_state.in_vpt_block == TRUE)
9539 update_vpt_block_state ();
9540
73cd51e5
AV		 9541 return TRUE;
9542 }
9543 }
9544 return FALSE;
9545}
9546
9547
90ec0d68
MGD		 9548/* Return the name of a v7A special register. */
9549
43e65147 9550static const char *
90ec0d68
MGD		 9551banked_regname (unsigned reg)
9552{
9553 switch (reg)
9554 {
9555 case 15: return "CPSR";
43e65147 9556 case 32: return "R8_usr";
90ec0d68
MGD		 9557 case 33: return "R9_usr";
9558 case 34: return "R10_usr";
9559 case 35: return "R11_usr";
9560 case 36: return "R12_usr";
9561 case 37: return "SP_usr";
9562 case 38: return "LR_usr";
43e65147 9563 case 40: return "R8_fiq";
90ec0d68
MGD		 9564 case 41: return "R9_fiq";
9565 case 42: return "R10_fiq";
9566 case 43: return "R11_fiq";
9567 case 44: return "R12_fiq";
9568 case 45: return "SP_fiq";
9569 case 46: return "LR_fiq";
9570 case 48: return "LR_irq";
9571 case 49: return "SP_irq";
9572 case 50: return "LR_svc";
9573 case 51: return "SP_svc";
9574 case 52: return "LR_abt";
9575 case 53: return "SP_abt";
9576 case 54: return "LR_und";
9577 case 55: return "SP_und";
9578 case 60: return "LR_mon";
9579 case 61: return "SP_mon";
9580 case 62: return "ELR_hyp";
9581 case 63: return "SP_hyp";
9582 case 79: return "SPSR";
9583 case 110: return "SPSR_fiq";
9584 case 112: return "SPSR_irq";
9585 case 114: return "SPSR_svc";
9586 case 116: return "SPSR_abt";
9587 case 118: return "SPSR_und";
9588 case 124: return "SPSR_mon";
9589 case 126: return "SPSR_hyp";
9590 default: return NULL;
9591 }
9592}
9593
e797f7e0
MGD		 9594/* Return the name of the DMB/DSB option. */
9595static const char *
9596data_barrier_option (unsigned option)
9597{
9598 switch (option & 0xf)
9599 {
9600 case 0xf: return "sy";
9601 case 0xe: return "st";
9602 case 0xd: return "ld";
9603 case 0xb: return "ish";
9604 case 0xa: return "ishst";
9605 case 0x9: return "ishld";
9606 case 0x7: return "un";
9607 case 0x6: return "unst";
9608 case 0x5: return "nshld";
9609 case 0x3: return "osh";
9610 case 0x2: return "oshst";
9611 case 0x1: return "oshld";
9612 default: return NULL;
9613 }
9614}
9615
4a5329c6
ZW		 9616/* Print one ARM instruction from PC on INFO->STREAM. */
9617
9618static void
9619print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 9620{
6b5d3a4d 9621 const struct opcode32 *insn;
6a51a8a8 9622 void *stream = info->stream;
6b5d3a4d 9623 fprintf_ftype func = info->fprintf_func;
b0e28b39 9624 struct arm_private_data *private_data = info->private_data;
252b5132 9625
16980d0b
JB		 9626 if (print_insn_coprocessor (pc, info, given, FALSE))
9627 return;
9628
9629 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 9630 return;
9631
252b5132
RH		 9632 for (insn = arm_opcodes; insn->assembler; insn++)
9633 {
0313a2b8
NC		 9634 if ((given & insn->mask) != insn->value)
9635 continue;
823d2571
TG		 9636
9637 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 9638 continue;
9639
9640 /* Special case: an instruction with all bits set in the condition field
9641 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
9642 or by the catchall at the end of the table. */
9643 if ((given & 0xF0000000) != 0xF0000000
9644 || (insn->mask & 0xF0000000) == 0xF0000000
9645 || (insn->mask == 0 && insn->value == 0))
252b5132 9646 {
ff4a8d2b
NC		 9647 unsigned long u_reg = 16;
9648 unsigned long U_reg = 16;
ab8e2090 9649 bfd_boolean is_unpredictable = FALSE;
05413229 9650 signed long value_in_comment = 0;
6b5d3a4d 9651 const char *c;
b34976b6 9652
252b5132
RH		 9653 for (c = insn->assembler; *c; c++)
9654 {
9655 if (*c == '%')
9656 {
c1e26897
NC		 9657 bfd_boolean allow_unpredictable = FALSE;
9658
252b5132
RH		 9659 switch (*++c)
9660 {
9661 case '%':
9662 func (stream, "%%");
9663 break;
9664
9665 case 'a':
05413229 9666 value_in_comment = print_arm_address (pc, info, given);
62b3e311 9667 break;
252b5132 9668
62b3e311
PB		 9669 case 'P':
9670 /* Set P address bit and use normal address
9671 printing routine. */
c1e26897 9672 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 9673 break;
9674
c1e26897
NC		 9675 case 'S':
9676 allow_unpredictable = TRUE;
1a0670f3 9677 /* Fall through. */
252b5132
RH		 9678 case 's':
9679 if ((given & 0x004f0000) == 0x004f0000)
9680 {
58efb6c0 9681 /* PC relative with immediate offset. */
f8b960bc 9682 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 9683
aefd8a40
NC		 9684 if (PRE_BIT_SET)
9685 {
26d97720
NS		 9686 /* Elide positive zero offset. */
9687 if (offset || NEGATIVE_BIT_SET)
9688 func (stream, "[pc, #%s%d]\t; ",
d908c8af 9689 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 9690 else
26d97720
NS		 9691 func (stream, "[pc]\t; ");
9692 if (NEGATIVE_BIT_SET)
9693 offset = -offset;
aefd8a40
NC		 9694 info->print_address_func (offset + pc + 8, info);
9695 }
9696 else
9697 {
26d97720
NS		 9698 /* Always show the offset. */
9699 func (stream, "[pc], #%s%d",
d908c8af 9700 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 9701 if (! allow_unpredictable)
9702 is_unpredictable = TRUE;
aefd8a40 9703 }
252b5132
RH		 9704 }
9705 else
9706 {
fe56b6ce
NC		 9707 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
9708
b34976b6 9709 func (stream, "[%s",
252b5132 9710 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 9711
c1e26897 9712 if (PRE_BIT_SET)
252b5132 9713 {
c1e26897 9714 if (IMMEDIATE_BIT_SET)
252b5132 9715 {
26d97720
NS		 9716 /* Elide offset for non-writeback
9717 positive zero. */
9718 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
9719 || offset)
9720 func (stream, ", #%s%d",
9721 NEGATIVE_BIT_SET ? "-" : "", offset);
9722
9723 if (NEGATIVE_BIT_SET)
9724 offset = -offset;
945ee430 9725
fe56b6ce 9726 value_in_comment = offset;
252b5132 9727 }
945ee430 9728 else
ff4a8d2b
NC		 9729 {
9730 /* Register Offset or Register Pre-Indexed. */
9731 func (stream, ", %s%s",
9732 NEGATIVE_BIT_SET ? "-" : "",
9733 arm_regnames[given & 0xf]);
9734
9735 /* Writing back to the register that is the source/
9736 destination of the load/store is unpredictable. */
9737 if (! allow_unpredictable
9738 && WRITEBACK_BIT_SET
9739 && ((given & 0xf) == ((given >> 12) & 0xf)))
9740 is_unpredictable = TRUE;
9741 }
252b5132 9742
b34976b6 9743 func (stream, "]%s",
c1e26897 9744 WRITEBACK_BIT_SET ? "!" : "");
252b5132 9745 }
945ee430 9746 else
252b5132 9747 {
c1e26897 9748 if (IMMEDIATE_BIT_SET)
252b5132 9749 {
945ee430 9750 /* Immediate Post-indexed. */
aefd8a40 9751 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 9752 func (stream, "], #%s%d",
9753 NEGATIVE_BIT_SET ? "-" : "", offset);
9754 if (NEGATIVE_BIT_SET)
9755 offset = -offset;
fe56b6ce 9756 value_in_comment = offset;
252b5132 9757 }
945ee430 9758 else
ff4a8d2b
NC		 9759 {
9760 /* Register Post-indexed. */
9761 func (stream, "], %s%s",
9762 NEGATIVE_BIT_SET ? "-" : "",
9763 arm_regnames[given & 0xf]);
9764
9765 /* Writing back to the register that is the source/
9766 destination of the load/store is unpredictable. */
9767 if (! allow_unpredictable
9768 && (given & 0xf) == ((given >> 12) & 0xf))
9769 is_unpredictable = TRUE;
9770 }
c1e26897 9771
07a28fab
NC		 9772 if (! allow_unpredictable)
9773 {
9774 /* Writeback is automatically implied by post- addressing.
9775 Setting the W bit is unnecessary and ARM specify it as
9776 being unpredictable. */
9777 if (WRITEBACK_BIT_SET
9778 /* Specifying the PC register as the post-indexed
9779 registers is also unpredictable. */
ab8e2090
NC		 9780 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
9781 is_unpredictable = TRUE;
07a28fab 9782 }
252b5132
RH		 9783 }
9784 }
9785 break;
b34976b6 9786
252b5132 9787 case 'b':
6b5d3a4d 9788 {
f8b960bc 9789 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
05413229 9790 info->print_address_func (disp * 4 + pc + 8, info);
6b5d3a4d 9791 }
252b5132
RH		 9792 break;
9793
9794 case 'c':
c22aaad1
PB		 9795 if (((given >> 28) & 0xf) != 0xe)
9796 func (stream, "%s",
9797 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 9798 break;
9799
9800 case 'm':
9801 {
9802 int started = 0;
9803 int reg;
9804
9805 func (stream, "{");
9806 for (reg = 0; reg < 16; reg++)
9807 if ((given & (1 << reg)) != 0)
9808 {
9809 if (started)
9810 func (stream, ", ");
9811 started = 1;
9812 func (stream, "%s", arm_regnames[reg]);
9813 }
9814 func (stream, "}");
ab8e2090
NC		 9815 if (! started)
9816 is_unpredictable = TRUE;
252b5132
RH		 9817 }
9818 break;
9819
37b37b2d 9820 case 'q':
78c66db8 9821 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 9822 break;
9823
252b5132
RH		 9824 case 'o':
9825 if ((given & 0x02000000) != 0)
9826 {
a415b1cd
JB		 9827 unsigned int rotate = (given & 0xf00) >> 7;
9828 unsigned int immed = (given & 0xff);
9829 unsigned int a, i;
9830
9831 a = (((immed << (32 - rotate))
9832 | (immed >> rotate)) & 0xffffffff);
9833 /* If there is another encoding with smaller rotate,
9834 the rotate should be specified directly. */
9835 for (i = 0; i < 32; i += 2)
9836 if ((a << i | a >> (32 - i)) <= 0xff)
9837 break;
9838
9839 if (i != rotate)
9840 func (stream, "#%d, %d", immed, rotate);
9841 else
9842 func (stream, "#%d", a);
9843 value_in_comment = a;
252b5132
RH		 9844 }
9845 else
78c66db8 9846 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 9847 break;
9848
9849 case 'p':
9850 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 9851 {
823d2571
TG		 9852 arm_feature_set arm_ext_v6 =
9853 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
9854
aefd8a40
NC		 9855 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
9856 mechanism for setting PSR flag bits. They are
9857 obsolete in V6 onwards. */
823d2571
TG		 9858 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
9859 arm_ext_v6))
aefd8a40 9860 func (stream, "p");
4ab90a7a
AV		 9861 else
9862 is_unpredictable = TRUE;
aefd8a40 9863 }
252b5132
RH		 9864 break;
9865
9866 case 't':
9867 if ((given & 0x01200000) == 0x00200000)
9868 func (stream, "t");
9869 break;
9870
252b5132 9871 case 'A':
05413229
NC		 9872 {
9873 int offset = given & 0xff;
f02232aa 9874
05413229 9875 value_in_comment = offset * 4;
c1e26897 9876 if (NEGATIVE_BIT_SET)
05413229 9877 value_in_comment = - value_in_comment;
f02232aa 9878
05413229 9879 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 9880
c1e26897 9881 if (PRE_BIT_SET)
05413229
NC		 9882 {
9883 if (offset)
fe56b6ce 9884 func (stream, ", #%d]%s",
d908c8af 9885 (int) value_in_comment,
c1e26897 9886 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 9887 else
9888 func (stream, "]");
9889 }
9890 else
9891 {
9892 func (stream, "]");
f02232aa 9893
c1e26897 9894 if (WRITEBACK_BIT_SET)
05413229
NC		 9895 {
9896 if (offset)
d908c8af 9897 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 9898 }
9899 else
fe56b6ce 9900 {
d908c8af 9901 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 9902 value_in_comment = offset;
9903 }
05413229
NC		 9904 }
9905 }
252b5132
RH		 9906 break;
9907
077b8428
NC		 9908 case 'B':
9909 /* Print ARM V5 BLX(1) address: pc+25 bits. */
9910 {
9911 bfd_vma address;
9912 bfd_vma offset = 0;
b34976b6 9913
c1e26897 9914 if (! NEGATIVE_BIT_SET)
077b8428
NC		 9915 /* Is signed, hi bits should be ones. */
9916 offset = (-1) ^ 0x00ffffff;
9917
9918 /* Offset is (SignExtend(offset field)<<2). */
9919 offset += given & 0x00ffffff;
9920 offset <<= 2;
9921 address = offset + pc + 8;
b34976b6 9922
8f06b2d8
PB		 9923 if (given & 0x01000000)
9924 /* H bit allows addressing to 2-byte boundaries. */
9925 address += 2;
b1ee46c5 9926
8f06b2d8 9927 info->print_address_func (address, info);
b1ee46c5 9928 }
b1ee46c5
AH		 9929 break;
9930
252b5132 9931 case 'C':
90ec0d68
MGD		 9932 if ((given & 0x02000200) == 0x200)
9933 {
9934 const char * name;
9935 unsigned sysm = (given & 0x004f0000) >> 16;
9936
9937 sysm |= (given & 0x300) >> 4;
9938 name = banked_regname (sysm);
9939
9940 if (name != NULL)
9941 func (stream, "%s", name);
9942 else
d908c8af 9943 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 9944 }
9945 else
9946 {
43e65147 9947 func (stream, "%cPSR_",
90ec0d68
MGD		 9948 (given & 0x00400000) ? 'S' : 'C');
9949 if (given & 0x80000)
9950 func (stream, "f");
9951 if (given & 0x40000)
9952 func (stream, "s");
9953 if (given & 0x20000)
9954 func (stream, "x");
9955 if (given & 0x10000)
9956 func (stream, "c");
9957 }
252b5132
RH		 9958 break;
9959
62b3e311 9960 case 'U':
43e65147 9961 if ((given & 0xf0) == 0x60)
62b3e311 9962 {
52e7f43d
RE		 9963 switch (given & 0xf)
9964 {
9965 case 0xf: func (stream, "sy"); break;
9966 default:
9967 func (stream, "#%d", (int) given & 0xf);
9968 break;
9969 }
43e65147
L		 9970 }
9971 else
52e7f43d 9972 {
e797f7e0
MGD		 9973 const char * opt = data_barrier_option (given & 0xf);
9974 if (opt != NULL)
9975 func (stream, "%s", opt);
9976 else
52e7f43d 9977 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 9978 }
9979 break;
9980
b34976b6 9981 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 9982 case '5': case '6': case '7': case '8': case '9':
9983 {
16980d0b
JB		 9984 int width;
9985 unsigned long value;
252b5132 9986
16980d0b 9987 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 9988
252b5132
RH		 9989 switch (*c)
9990 {
ab8e2090
NC		 9991 case 'R':
9992 if (value == 15)
9993 is_unpredictable = TRUE;
9994 /* Fall through. */
16980d0b 9995 case 'r':
9eb6c0f1
MGD		 9996 case 'T':
9997 /* We want register + 1 when decoding T. */
9998 if (*c == 'T')
9999 ++value;
10000
ff4a8d2b
NC		 10001 if (c[1] == 'u')
10002 {
10003 /* Eat the 'u' character. */
10004 ++ c;
10005
10006 if (u_reg == value)
10007 is_unpredictable = TRUE;
10008 u_reg = value;
10009 }
10010 if (c[1] == 'U')
10011 {
10012 /* Eat the 'U' character. */
10013 ++ c;
10014
10015 if (U_reg == value)
10016 is_unpredictable = TRUE;
10017 U_reg = value;
10018 }
16980d0b
JB		 10019 func (stream, "%s", arm_regnames[value]);
10020 break;
10021 case 'd':
10022 func (stream, "%ld", value);
05413229 10023 value_in_comment = value;
16980d0b
JB		 10024 break;
10025 case 'b':
10026 func (stream, "%ld", value * 8);
05413229 10027 value_in_comment = value * 8;
16980d0b
JB		 10028 break;
10029 case 'W':
10030 func (stream, "%ld", value + 1);
05413229 10031 value_in_comment = value + 1;
16980d0b
JB		 10032 break;
10033 case 'x':
10034 func (stream, "0x%08lx", value);
10035
10036 /* Some SWI instructions have special
10037 meanings. */
10038 if ((given & 0x0fffffff) == 0x0FF00000)
10039 func (stream, "\t; IMB");
10040 else if ((given & 0x0fffffff) == 0x0FF00001)
10041 func (stream, "\t; IMBRange");
10042 break;
10043 case 'X':
10044 func (stream, "%01lx", value & 0xf);
05413229 10045 value_in_comment = value;
252b5132
RH		 10046 break;
10047 case '`':
10048 c++;
16980d0b 10049 if (value == 0)
252b5132
RH		 10050 func (stream, "%c", *c);
10051 break;
10052 case '\'':
10053 c++;
16980d0b 10054 if (value == ((1ul << width) - 1))
252b5132
RH		 10055 func (stream, "%c", *c);
10056 break;
10057 case '?':
fe56b6ce 10058 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 10059 c += 1 << width;
252b5132
RH		 10060 break;
10061 default:
10062 abort ();
10063 }
dffaa15c
AM		 10064 }
10065 break;
0dd132b6 10066
dffaa15c
AM		 10067 case 'e':
10068 {
10069 int imm;
0dd132b6 10070
dffaa15c
AM		 10071 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
10072 func (stream, "%d", imm);
10073 value_in_comment = imm;
10074 }
10075 break;
fe56b6ce 10076
dffaa15c
AM		 10077 case 'E':
10078 /* LSB and WIDTH fields of BFI or BFC. The machine-
10079 language instruction encodes LSB and MSB. */
10080 {
10081 long msb = (given & 0x001f0000) >> 16;
10082 long lsb = (given & 0x00000f80) >> 7;
10083 long w = msb - lsb + 1;
0a003adc 10084
dffaa15c
AM		 10085 if (w > 0)
10086 func (stream, "#%lu, #%lu", lsb, w);
10087 else
10088 func (stream, "(invalid: %lu:%lu)", lsb, msb);
10089 }
10090 break;
90ec0d68 10091
dffaa15c
AM		 10092 case 'R':
10093 /* Get the PSR/banked register name. */
10094 {
10095 const char * name;
10096 unsigned sysm = (given & 0x004f0000) >> 16;
90ec0d68 10097
dffaa15c
AM		 10098 sysm |= (given & 0x300) >> 4;
10099 name = banked_regname (sysm);
90ec0d68 10100
dffaa15c
AM		 10101 if (name != NULL)
10102 func (stream, "%s", name);
10103 else
10104 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
10105 }
10106 break;
fe56b6ce 10107
dffaa15c
AM		 10108 case 'V':
10109 /* 16-bit unsigned immediate from a MOVT or MOVW
10110 instruction, encoded in bits 0:11 and 15:19. */
10111 {
10112 long hi = (given & 0x000f0000) >> 4;
10113 long lo = (given & 0x00000fff);
10114 long imm16 = hi | lo;
0a003adc 10115
dffaa15c
AM		 10116 func (stream, "#%lu", imm16);
10117 value_in_comment = imm16;
252b5132 10118 }
dffaa15c
AM		 10119 break;
10120
10121 default:
10122 abort ();
252b5132
RH		 10123 }
10124 }
10125 else
10126 func (stream, "%c", *c);
10127 }
05413229
NC		 10128
10129 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 10130 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 10131
10132 if (is_unpredictable)
10133 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 10134
4a5329c6 10135 return;
252b5132
RH		 10136 }
10137 }
0b347048
TC		 10138 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
10139 return;
252b5132
RH		 10140}
10141
4a5329c6 10142/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 10143
4a5329c6
ZW		 10144static void
10145print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 10146{
6b5d3a4d 10147 const struct opcode16 *insn;
6a51a8a8
AM		 10148 void *stream = info->stream;
10149 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 10150
10151 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 10152 if ((given & insn->mask) == insn->value)
10153 {
05413229 10154 signed long value_in_comment = 0;
6b5d3a4d 10155 const char *c = insn->assembler;
05413229 10156
c19d1205
ZW		 10157 for (; *c; c++)
10158 {
10159 int domaskpc = 0;
10160 int domasklr = 0;
10161
10162 if (*c != '%')
10163 {
10164 func (stream, "%c", *c);
10165 continue;
10166 }
252b5132 10167
c19d1205
ZW		 10168 switch (*++c)
10169 {
10170 case '%':
10171 func (stream, "%%");
10172 break;
b34976b6 10173
c22aaad1
PB		 10174 case 'c':
10175 if (ifthen_state)
10176 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10177 break;
10178
10179 case 'C':
10180 if (ifthen_state)
10181 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10182 else
10183 func (stream, "s");
10184 break;
10185
10186 case 'I':
10187 {
10188 unsigned int tmp;
10189
10190 ifthen_next_state = given & 0xff;
10191 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
10192 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
10193 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
10194 }
10195 break;
10196
10197 case 'x':
10198 if (ifthen_next_state)
10199 func (stream, "\t; unpredictable branch in IT block\n");
10200 break;
10201
10202 case 'X':
10203 if (ifthen_state)
10204 func (stream, "\t; unpredictable <IT:%s>",
10205 arm_conditional[IFTHEN_COND]);
10206 break;
10207
c19d1205
ZW		 10208 case 'S':
10209 {
10210 long reg;
10211
10212 reg = (given >> 3) & 0x7;
10213 if (given & (1 << 6))
10214 reg += 8;
4f3c3dbb 10215
c19d1205
ZW		 10216 func (stream, "%s", arm_regnames[reg]);
10217 }
10218 break;
baf0cc5e 10219
c19d1205 10220 case 'D':
4f3c3dbb 10221 {
c19d1205
ZW		 10222 long reg;
10223
10224 reg = given & 0x7;
10225 if (given & (1 << 7))
10226 reg += 8;
10227
10228 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 10229 }
c19d1205
ZW		 10230 break;
10231
10232 case 'N':
10233 if (given & (1 << 8))
10234 domasklr = 1;
10235 /* Fall through. */
10236 case 'O':
10237 if (*c == 'O' && (given & (1 << 8)))
10238 domaskpc = 1;
10239 /* Fall through. */
10240 case 'M':
10241 {
10242 int started = 0;
10243 int reg;
10244
10245 func (stream, "{");
10246
10247 /* It would be nice if we could spot
10248 ranges, and generate the rS-rE format: */
10249 for (reg = 0; (reg < 8); reg++)
10250 if ((given & (1 << reg)) != 0)
10251 {
10252 if (started)
10253 func (stream, ", ");
10254 started = 1;
10255 func (stream, "%s", arm_regnames[reg]);
10256 }
10257
10258 if (domasklr)
10259 {
10260 if (started)
10261 func (stream, ", ");
10262 started = 1;
d908c8af 10263 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 10264 }
10265
10266 if (domaskpc)
10267 {
10268 if (started)
10269 func (stream, ", ");
d908c8af 10270 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 10271 }
10272
10273 func (stream, "}");
10274 }
10275 break;
10276
4547cb56
NC		 10277 case 'W':
10278 /* Print writeback indicator for a LDMIA. We are doing a
10279 writeback if the base register is not in the register
10280 mask. */
10281 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
10282 func (stream, "!");
dffaa15c 10283 break;
4547cb56 10284
c19d1205
ZW		 10285 case 'b':
10286 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
10287 {
10288 bfd_vma address = (pc + 4
10289 + ((given & 0x00f8) >> 2)
10290 + ((given & 0x0200) >> 3));
10291 info->print_address_func (address, info);
10292 }
10293 break;
10294
10295 case 's':
10296 /* Right shift immediate -- bits 6..10; 1-31 print
10297 as themselves, 0 prints as 32. */
10298 {
10299 long imm = (given & 0x07c0) >> 6;
10300 if (imm == 0)
10301 imm = 32;
0fd3a477 10302 func (stream, "#%ld", imm);
c19d1205
ZW		 10303 }
10304 break;
10305
10306 case '0': case '1': case '2': case '3': case '4':
10307 case '5': case '6': case '7': case '8': case '9':
10308 {
10309 int bitstart = *c++ - '0';
10310 int bitend = 0;
10311
10312 while (*c >= '0' && *c <= '9')
10313 bitstart = (bitstart * 10) + *c++ - '0';
10314
10315 switch (*c)
10316 {
10317 case '-':
10318 {
f8b960bc 10319 bfd_vma reg;
c19d1205
ZW		 10320
10321 c++;
10322 while (*c >= '0' && *c <= '9')
10323 bitend = (bitend * 10) + *c++ - '0';
10324 if (!bitend)
10325 abort ();
10326 reg = given >> bitstart;
10327 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 10328
c19d1205
ZW		 10329 switch (*c)
10330 {
10331 case 'r':
10332 func (stream, "%s", arm_regnames[reg]);
10333 break;
10334
10335 case 'd':
d908c8af 10336 func (stream, "%ld", (long) reg);
05413229 10337 value_in_comment = reg;
c19d1205
ZW		 10338 break;
10339
10340 case 'H':
d908c8af 10341 func (stream, "%ld", (long) (reg << 1));
05413229 10342 value_in_comment = reg << 1;
c19d1205
ZW		 10343 break;
10344
10345 case 'W':
d908c8af 10346 func (stream, "%ld", (long) (reg << 2));
05413229 10347 value_in_comment = reg << 2;
c19d1205
ZW		 10348 break;
10349
10350 case 'a':
10351 /* PC-relative address -- the bottom two
10352 bits of the address are dropped
10353 before the calculation. */
10354 info->print_address_func
10355 (((pc + 4) & ~3) + (reg << 2), info);
05413229 10356 value_in_comment = 0;
c19d1205
ZW		 10357 break;
10358
10359 case 'x':
d908c8af 10360 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 10361 break;
10362
c19d1205
ZW		 10363 case 'B':
10364 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6b5d3a4d 10365 info->print_address_func (reg * 2 + pc + 4, info);
05413229 10366 value_in_comment = 0;
c19d1205
ZW		 10367 break;
10368
10369 case 'c':
c22aaad1 10370 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 10371 break;
10372
10373 default:
10374 abort ();
10375 }
10376 }
10377 break;
10378
10379 case '\'':
10380 c++;
10381 if ((given & (1 << bitstart)) != 0)
10382 func (stream, "%c", *c);
10383 break;
10384
10385 case '?':
10386 ++c;
10387 if ((given & (1 << bitstart)) != 0)
10388 func (stream, "%c", *c++);
10389 else
10390 func (stream, "%c", *++c);
10391 break;
10392
10393 default:
10394 abort ();
10395 }
10396 }
10397 break;
10398
10399 default:
10400 abort ();
10401 }
10402 }
05413229
NC		 10403
10404 if (value_in_comment > 32 || value_in_comment < -16)
10405 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 10406 return;
c19d1205
ZW		 10407 }
10408
10409 /* No match. */
0b347048
TC		 10410 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
10411 return;
c19d1205
ZW		 10412}
10413
62b3e311 10414/* Return the name of an V7M special register. */
fe56b6ce 10415
62b3e311
PB		 10416static const char *
10417psr_name (int regno)
10418{
10419 switch (regno)
10420 {
1a336194
TP		 10421 case 0x0: return "APSR";
10422 case 0x1: return "IAPSR";
10423 case 0x2: return "EAPSR";
10424 case 0x3: return "PSR";
10425 case 0x5: return "IPSR";
10426 case 0x6: return "EPSR";
10427 case 0x7: return "IEPSR";
10428 case 0x8: return "MSP";
10429 case 0x9: return "PSP";
10430 case 0xa: return "MSPLIM";
10431 case 0xb: return "PSPLIM";
10432 case 0x10: return "PRIMASK";
10433 case 0x11: return "BASEPRI";
10434 case 0x12: return "BASEPRI_MAX";
10435 case 0x13: return "FAULTMASK";
10436 case 0x14: return "CONTROL";
16a1fa25
TP		 10437 case 0x88: return "MSP_NS";
10438 case 0x89: return "PSP_NS";
1a336194
TP		 10439 case 0x8a: return "MSPLIM_NS";
10440 case 0x8b: return "PSPLIM_NS";
10441 case 0x90: return "PRIMASK_NS";
10442 case 0x91: return "BASEPRI_NS";
10443 case 0x93: return "FAULTMASK_NS";
10444 case 0x94: return "CONTROL_NS";
10445 case 0x98: return "SP_NS";
62b3e311
PB		 10446 default: return "<unknown>";
10447 }
10448}
10449
4a5329c6
ZW		 10450/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
10451
10452static void
10453print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 10454{
6b5d3a4d 10455 const struct opcode32 *insn;
c19d1205
ZW		 10456 void *stream = info->stream;
10457 fprintf_ftype func = info->fprintf_func;
73cd51e5 10458 bfd_boolean is_mve = is_mve_architecture (info);
c19d1205 10459
16980d0b
JB		 10460 if (print_insn_coprocessor (pc, info, given, TRUE))
10461 return;
10462
73cd51e5
AV		 10463 if ((is_mve == FALSE) && print_insn_neon (info, given, TRUE))
10464 return;
10465
10466 if (is_mve && print_insn_mve (info, given))
8f06b2d8
PB		 10467 return;
10468
c19d1205
ZW		 10469 for (insn = thumb32_opcodes; insn->assembler; insn++)
10470 if ((given & insn->mask) == insn->value)
10471 {
4b5a202f 10472 bfd_boolean is_clrm = FALSE;
ff4a8d2b 10473 bfd_boolean is_unpredictable = FALSE;
05413229 10474 signed long value_in_comment = 0;
6b5d3a4d 10475 const char *c = insn->assembler;
05413229 10476
c19d1205
ZW		 10477 for (; *c; c++)
10478 {
10479 if (*c != '%')
10480 {
10481 func (stream, "%c", *c);
10482 continue;
10483 }
10484
10485 switch (*++c)
10486 {
10487 case '%':
10488 func (stream, "%%");
10489 break;
10490
c22aaad1
PB		 10491 case 'c':
10492 if (ifthen_state)
10493 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10494 break;
10495
10496 case 'x':
10497 if (ifthen_next_state)
10498 func (stream, "\t; unpredictable branch in IT block\n");
10499 break;
10500
10501 case 'X':
10502 if (ifthen_state)
10503 func (stream, "\t; unpredictable <IT:%s>",
10504 arm_conditional[IFTHEN_COND]);
10505 break;
10506
c19d1205
ZW		 10507 case 'I':
10508 {
10509 unsigned int imm12 = 0;
fe56b6ce 10510
c19d1205
ZW		 10511 imm12 |= (given & 0x000000ffu);
10512 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 10513 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 10514 func (stream, "#%u", imm12);
10515 value_in_comment = imm12;
c19d1205
ZW		 10516 }
10517 break;
10518
10519 case 'M':
10520 {
10521 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 10522
c19d1205
ZW		 10523 bits |= (given & 0x000000ffu);
10524 bits |= (given & 0x00007000u) >> 4;
10525 bits |= (given & 0x04000000u) >> 15;
10526 imm8 = (bits & 0x0ff);
10527 mod = (bits & 0xf00) >> 8;
10528 switch (mod)
10529 {
10530 case 0: imm = imm8; break;
c1e26897
NC		 10531 case 1: imm = ((imm8 << 16) | imm8); break;
10532 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
10533 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 10534 default:
10535 mod = (bits & 0xf80) >> 7;
10536 imm8 = (bits & 0x07f) | 0x80;
10537 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
10538 }
fe56b6ce
NC		 10539 func (stream, "#%u", imm);
10540 value_in_comment = imm;
c19d1205
ZW		 10541 }
10542 break;
43e65147 10543
c19d1205
ZW		 10544 case 'J':
10545 {
10546 unsigned int imm = 0;
fe56b6ce 10547
c19d1205
ZW		 10548 imm |= (given & 0x000000ffu);
10549 imm |= (given & 0x00007000u) >> 4;
10550 imm |= (given & 0x04000000u) >> 15;
10551 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 10552 func (stream, "#%u", imm);
10553 value_in_comment = imm;
c19d1205
ZW		 10554 }
10555 break;
10556
10557 case 'K':
10558 {
10559 unsigned int imm = 0;
fe56b6ce 10560
c19d1205
ZW		 10561 imm |= (given & 0x000f0000u) >> 16;
10562 imm |= (given & 0x00000ff0u) >> 0;
10563 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 10564 func (stream, "#%u", imm);
10565 value_in_comment = imm;
c19d1205
ZW		 10566 }
10567 break;
10568
74db7efb
NC		 10569 case 'H':
10570 {
10571 unsigned int imm = 0;
10572
10573 imm |= (given & 0x000f0000u) >> 4;
10574 imm |= (given & 0x00000fffu) >> 0;
10575 func (stream, "#%u", imm);
10576 value_in_comment = imm;
10577 }
10578 break;
10579
90ec0d68
MGD		 10580 case 'V':
10581 {
10582 unsigned int imm = 0;
10583
10584 imm |= (given & 0x00000fffu);
10585 imm |= (given & 0x000f0000u) >> 4;
10586 func (stream, "#%u", imm);
10587 value_in_comment = imm;
10588 }
10589 break;
10590
c19d1205
ZW		 10591 case 'S':
10592 {
10593 unsigned int reg = (given & 0x0000000fu);
10594 unsigned int stp = (given & 0x00000030u) >> 4;
10595 unsigned int imm = 0;
10596 imm |= (given & 0x000000c0u) >> 6;
10597 imm |= (given & 0x00007000u) >> 10;
10598
10599 func (stream, "%s", arm_regnames[reg]);
10600 switch (stp)
10601 {
10602 case 0:
10603 if (imm > 0)
10604 func (stream, ", lsl #%u", imm);
10605 break;
10606
10607 case 1:
10608 if (imm == 0)
10609 imm = 32;
10610 func (stream, ", lsr #%u", imm);
10611 break;
10612
10613 case 2:
10614 if (imm == 0)
10615 imm = 32;
10616 func (stream, ", asr #%u", imm);
10617 break;
10618
10619 case 3:
10620 if (imm == 0)
10621 func (stream, ", rrx");
10622 else
10623 func (stream, ", ror #%u", imm);
10624 }
10625 }
10626 break;
10627
10628 case 'a':
10629 {
10630 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 10631 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 10632 unsigned int op = (given & 0x00000f00) >> 8;
10633 unsigned int i12 = (given & 0x00000fff);
10634 unsigned int i8 = (given & 0x000000ff);
10635 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 10636 bfd_vma offset = 0;
c19d1205
ZW		 10637
10638 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 10639 if (U) /* 12-bit positive immediate offset. */
10640 {
10641 offset = i12;
10642 if (Rn != 15)
10643 value_in_comment = offset;
10644 }
10645 else if (Rn == 15) /* 12-bit negative immediate offset. */
10646 offset = - (int) i12;
10647 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 10648 {
10649 unsigned int Rm = (i8 & 0x0f);
10650 unsigned int sh = (i8 & 0x30) >> 4;
05413229 10651
c19d1205
ZW		 10652 func (stream, ", %s", arm_regnames[Rm]);
10653 if (sh)
10654 func (stream, ", lsl #%u", sh);
10655 func (stream, "]");
10656 break;
10657 }
10658 else switch (op)
10659 {
05413229 10660 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 10661 offset = i8;
10662 break;
10663
05413229 10664 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 10665 offset = -i8;
10666 break;
10667
05413229 10668 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 10669 offset = i8;
10670 writeback = TRUE;
10671 break;
10672
05413229 10673 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 10674 offset = -i8;
10675 writeback = TRUE;
10676 break;
10677
05413229 10678 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 10679 offset = i8;
10680 postind = TRUE;
10681 break;
10682
05413229 10683 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 10684 offset = -i8;
10685 postind = TRUE;
10686 break;
10687
10688 default:
10689 func (stream, ", <undefined>]");
10690 goto skip;
10691 }
10692
10693 if (postind)
d908c8af 10694 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 10695 else
10696 {
10697 if (offset)
d908c8af 10698 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 10699 func (stream, writeback ? "]!" : "]");
10700 }
10701
10702 if (Rn == 15)
10703 {
10704 func (stream, "\t; ");
10705 info->print_address_func (((pc + 4) & ~3) + offset, info);
10706 }
10707 }
10708 skip:
10709 break;
10710
10711 case 'A':
10712 {
c1e26897
NC		 10713 unsigned int U = ! NEGATIVE_BIT_SET;
10714 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 10715 unsigned int Rn = (given & 0x000f0000) >> 16;
10716 unsigned int off = (given & 0x000000ff);
10717
10718 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 10719
10720 if (PRE_BIT_SET)
c19d1205
ZW		 10721 {
10722 if (off || !U)
05413229
NC		 10723 {
10724 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
fe50e98c 10725 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 10726 }
c19d1205
ZW		 10727 func (stream, "]");
10728 if (W)
10729 func (stream, "!");
10730 }
10731 else
10732 {
10733 func (stream, "], ");
10734 if (W)
05413229
NC		 10735 {
10736 func (stream, "#%c%u", U ? '+' : '-', off * 4);
fe50e98c 10737 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 10738 }
c19d1205 10739 else
fe56b6ce
NC		 10740 {
10741 func (stream, "{%u}", off);
10742 value_in_comment = off;
10743 }
c19d1205
ZW		 10744 }
10745 }
10746 break;
10747
10748 case 'w':
10749 {
10750 unsigned int Sbit = (given & 0x01000000) >> 24;
10751 unsigned int type = (given & 0x00600000) >> 21;
05413229 10752
c19d1205
ZW		 10753 switch (type)
10754 {
10755 case 0: func (stream, Sbit ? "sb" : "b"); break;
10756 case 1: func (stream, Sbit ? "sh" : "h"); break;
10757 case 2:
10758 if (Sbit)
10759 func (stream, "??");
10760 break;
10761 case 3:
10762 func (stream, "??");
10763 break;
10764 }
10765 }
10766 break;
10767
4b5a202f
AV		 10768 case 'n':
10769 is_clrm = TRUE;
10770 /* Fall through. */
c19d1205
ZW		 10771 case 'm':
10772 {
10773 int started = 0;
10774 int reg;
10775
10776 func (stream, "{");
10777 for (reg = 0; reg < 16; reg++)
10778 if ((given & (1 << reg)) != 0)
10779 {
10780 if (started)
10781 func (stream, ", ");
10782 started = 1;
4b5a202f
AV		 10783 if (is_clrm && reg == 13)
10784 func (stream, "(invalid: %s)", arm_regnames[reg]);
10785 else if (is_clrm && reg == 15)
10786 func (stream, "%s", "APSR");
10787 else
10788 func (stream, "%s", arm_regnames[reg]);
c19d1205
ZW		 10789 }
10790 func (stream, "}");
10791 }
10792 break;
10793
10794 case 'E':
10795 {
10796 unsigned int msb = (given & 0x0000001f);
10797 unsigned int lsb = 0;
fe56b6ce 10798
c19d1205
ZW		 10799 lsb |= (given & 0x000000c0u) >> 6;
10800 lsb |= (given & 0x00007000u) >> 10;
10801 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
10802 }
10803 break;
10804
10805 case 'F':
10806 {
10807 unsigned int width = (given & 0x0000001f) + 1;
10808 unsigned int lsb = 0;
fe56b6ce 10809
c19d1205
ZW		 10810 lsb |= (given & 0x000000c0u) >> 6;
10811 lsb |= (given & 0x00007000u) >> 10;
10812 func (stream, "#%u, #%u", lsb, width);
10813 }
10814 break;
10815
e12437dc
AV		 10816 case 'G':
10817 {
10818 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
10819 func (stream, "%x", boff);
10820 }
10821 break;
10822
e5d6e09e
AV		 10823 case 'W':
10824 {
10825 unsigned int immA = (given & 0x001f0000u) >> 16;
10826 unsigned int immB = (given & 0x000007feu) >> 1;
10827 unsigned int immC = (given & 0x00000800u) >> 11;
10828 bfd_vma offset = 0;
10829
10830 offset |= immA << 12;
10831 offset |= immB << 2;
10832 offset |= immC << 1;
10833 /* Sign extend. */
10834 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
10835
10836 info->print_address_func (pc + 4 + offset, info);
10837 }
10838 break;
10839
1caf72a5
AV		 10840 case 'Y':
10841 {
10842 unsigned int immA = (given & 0x007f0000u) >> 16;
10843 unsigned int immB = (given & 0x000007feu) >> 1;
10844 unsigned int immC = (given & 0x00000800u) >> 11;
10845 bfd_vma offset = 0;
10846
10847 offset |= immA << 12;
10848 offset |= immB << 2;
10849 offset |= immC << 1;
10850 /* Sign extend. */
10851 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
10852
10853 info->print_address_func (pc + 4 + offset, info);
10854 }
10855 break;
10856
1889da70
AV		 10857 case 'Z':
10858 {
10859 unsigned int immA = (given & 0x00010000u) >> 16;
10860 unsigned int immB = (given & 0x000007feu) >> 1;
10861 unsigned int immC = (given & 0x00000800u) >> 11;
10862 bfd_vma offset = 0;
10863
10864 offset |= immA << 12;
10865 offset |= immB << 2;
10866 offset |= immC << 1;
10867 /* Sign extend. */
10868 offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
10869
10870 info->print_address_func (pc + 4 + offset, info);
f6b2b12d
AV		 10871
10872 unsigned int T = (given & 0x00020000u) >> 17;
10873 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
10874 unsigned int boffset = (T == 1) ? 4 : 2;
10875 func (stream, ", ");
10876 func (stream, "%x", endoffset + boffset);
1889da70
AV		 10877 }
10878 break;
10879
60f993ce
AV		 10880 case 'Q':
10881 {
10882 unsigned int immh = (given & 0x000007feu) >> 1;
10883 unsigned int imml = (given & 0x00000800u) >> 11;
10884 bfd_vma imm32 = 0;
10885
10886 imm32 |= immh << 2;
10887 imm32 |= imml << 1;
10888
10889 info->print_address_func (pc + 4 + imm32, info);
10890 }
10891 break;
10892
10893 case 'P':
10894 {
10895 unsigned int immh = (given & 0x000007feu) >> 1;
10896 unsigned int imml = (given & 0x00000800u) >> 11;
10897 bfd_vma imm32 = 0;
10898
10899 imm32 |= immh << 2;
10900 imm32 |= imml << 1;
10901
10902 info->print_address_func (pc + 4 - imm32, info);
10903 }
10904 break;
10905
c19d1205
ZW		 10906 case 'b':
10907 {
10908 unsigned int S = (given & 0x04000000u) >> 26;
10909 unsigned int J1 = (given & 0x00002000u) >> 13;
10910 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 10911 bfd_vma offset = 0;
c19d1205
ZW		 10912
10913 offset |= !S << 20;
10914 offset |= J2 << 19;
10915 offset |= J1 << 18;
10916 offset |= (given & 0x003f0000) >> 4;
10917 offset |= (given & 0x000007ff) << 1;
10918 offset -= (1 << 20);
10919
10920 info->print_address_func (pc + 4 + offset, info);
10921 }
10922 break;
10923
10924 case 'B':
10925 {
10926 unsigned int S = (given & 0x04000000u) >> 26;
10927 unsigned int I1 = (given & 0x00002000u) >> 13;
10928 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 10929 bfd_vma offset = 0;
c19d1205
ZW		 10930
10931 offset |= !S << 24;
10932 offset |= !(I1 ^ S) << 23;
10933 offset |= !(I2 ^ S) << 22;
10934 offset |= (given & 0x03ff0000u) >> 4;
10935 offset |= (given & 0x000007ffu) << 1;
10936 offset -= (1 << 24);
36b0c57d 10937 offset += pc + 4;
c19d1205 10938
36b0c57d
PB		 10939 /* BLX target addresses are always word aligned. */
10940 if ((given & 0x00001000u) == 0)
10941 offset &= ~2u;
10942
10943 info->print_address_func (offset, info);
c19d1205
ZW		 10944 }
10945 break;
10946
10947 case 's':
10948 {
10949 unsigned int shift = 0;
fe56b6ce 10950
c19d1205
ZW		 10951 shift |= (given & 0x000000c0u) >> 6;
10952 shift |= (given & 0x00007000u) >> 10;
c1e26897 10953 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 10954 func (stream, ", asr #%u", shift);
10955 else if (shift)
10956 func (stream, ", lsl #%u", shift);
10957 /* else print nothing - lsl #0 */
10958 }
10959 break;
10960
10961 case 'R':
10962 {
10963 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 10964
c19d1205
ZW		 10965 if (rot)
10966 func (stream, ", ror #%u", rot * 8);
10967 }
10968 break;
10969
62b3e311 10970 case 'U':
43e65147 10971 if ((given & 0xf0) == 0x60)
62b3e311 10972 {
52e7f43d
RE		 10973 switch (given & 0xf)
10974 {
10975 case 0xf: func (stream, "sy"); break;
10976 default:
10977 func (stream, "#%d", (int) given & 0xf);
10978 break;
10979 }
62b3e311 10980 }
43e65147 10981 else
52e7f43d 10982 {
e797f7e0
MGD		 10983 const char * opt = data_barrier_option (given & 0xf);
10984 if (opt != NULL)
10985 func (stream, "%s", opt);
10986 else
10987 func (stream, "#%d", (int) given & 0xf);
52e7f43d 10988 }
62b3e311
PB		 10989 break;
10990
10991 case 'C':
10992 if ((given & 0xff) == 0)
10993 {
10994 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
10995 if (given & 0x800)
10996 func (stream, "f");
10997 if (given & 0x400)
10998 func (stream, "s");
10999 if (given & 0x200)
11000 func (stream, "x");
11001 if (given & 0x100)
11002 func (stream, "c");
11003 }
90ec0d68
MGD		 11004 else if ((given & 0x20) == 0x20)
11005 {
11006 char const* name;
11007 unsigned sysm = (given & 0xf00) >> 8;
11008
11009 sysm |= (given & 0x30);
11010 sysm |= (given & 0x00100000) >> 14;
11011 name = banked_regname (sysm);
43e65147 11012
90ec0d68
MGD		 11013 if (name != NULL)
11014 func (stream, "%s", name);
11015 else
d908c8af 11016 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 11017 }
62b3e311
PB		 11018 else
11019 {
d908c8af 11020 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 11021 }
11022 break;
11023
11024 case 'D':
90ec0d68
MGD		 11025 if (((given & 0xff) == 0)
11026 || ((given & 0x20) == 0x20))
11027 {
11028 char const* name;
11029 unsigned sm = (given & 0xf0000) >> 16;
11030
11031 sm |= (given & 0x30);
11032 sm |= (given & 0x00100000) >> 14;
11033 name = banked_regname (sm);
11034
11035 if (name != NULL)
11036 func (stream, "%s", name);
11037 else
d908c8af 11038 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 11039 }
62b3e311 11040 else
d908c8af 11041 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 11042 break;
11043
c19d1205
ZW		 11044 case '0': case '1': case '2': case '3': case '4':
11045 case '5': case '6': case '7': case '8': case '9':
11046 {
16980d0b
JB		 11047 int width;
11048 unsigned long val;
c19d1205 11049
16980d0b 11050 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 11051
c19d1205
ZW		 11052 switch (*c)
11053 {
d052b9b7
AV		 11054 case 's':
11055 if (val <= 3)
11056 func (stream, "%s", mve_vec_sizename[val]);
11057 else
11058 func (stream, "<undef size>");
11059 break;
11060
05413229
NC		 11061 case 'd':
11062 func (stream, "%lu", val);
11063 value_in_comment = val;
11064 break;
ff4a8d2b 11065
f0fba320
RL		 11066 case 'D':
11067 func (stream, "%lu", val + 1);
11068 value_in_comment = val + 1;
11069 break;
11070
05413229
NC		 11071 case 'W':
11072 func (stream, "%lu", val * 4);
11073 value_in_comment = val * 4;
11074 break;
ff4a8d2b 11075
f1c7f421
AV		 11076 case 'S':
11077 if (val == 13)
11078 is_unpredictable = TRUE;
11079 /* Fall through. */
ff4a8d2b
NC		 11080 case 'R':
11081 if (val == 15)
11082 is_unpredictable = TRUE;
11083 /* Fall through. */
11084 case 'r':
11085 func (stream, "%s", arm_regnames[val]);
11086 break;
c19d1205
ZW		 11087
11088 case 'c':
c22aaad1 11089 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 11090 break;
11091
11092 case '\'':
c19d1205 11093 c++;
16980d0b
JB		 11094 if (val == ((1ul << width) - 1))
11095 func (stream, "%c", *c);
c19d1205 11096 break;
43e65147 11097
c19d1205 11098 case '`':
c19d1205 11099 c++;
16980d0b
JB		 11100 if (val == 0)
11101 func (stream, "%c", *c);
c19d1205
ZW		 11102 break;
11103
11104 case '?':
fe56b6ce 11105 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 11106 c += 1 << width;
c19d1205 11107 break;
43e65147 11108
0bb027fd
RR		 11109 case 'x':
11110 func (stream, "0x%lx", val & 0xffffffffUL);
11111 break;
c19d1205
ZW		 11112
11113 default:
11114 abort ();
11115 }
11116 }
11117 break;
11118
32a94698
NC		 11119 case 'L':
11120 /* PR binutils/12534
11121 If we have a PC relative offset in an LDRD or STRD
11122 instructions then display the decoded address. */
11123 if (((given >> 16) & 0xf) == 0xf)
11124 {
11125 bfd_vma offset = (given & 0xff) * 4;
11126
11127 if ((given & (1 << 23)) == 0)
11128 offset = - offset;
11129 func (stream, "\t; ");
11130 info->print_address_func ((pc & ~3) + 4 + offset, info);
11131 }
11132 break;
11133
c19d1205
ZW		 11134 default:
11135 abort ();
11136 }
11137 }
05413229
NC		 11138
11139 if (value_in_comment > 32 || value_in_comment < -16)
11140 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 11141
11142 if (is_unpredictable)
11143 func (stream, UNPREDICTABLE_INSTRUCTION);
11144
4a5329c6 11145 return;
c19d1205 11146 }
252b5132 11147
58efb6c0 11148 /* No match. */
0b347048
TC		 11149 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
11150 return;
252b5132
RH		 11151}
11152
e821645d
DJ		 11153/* Print data bytes on INFO->STREAM. */
11154
11155static void
fe56b6ce
NC		 11156print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
11157 struct disassemble_info *info,
e821645d
DJ		 11158 long given)
11159{
11160 switch (info->bytes_per_chunk)
11161 {
11162 case 1:
11163 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
11164 break;
11165 case 2:
11166 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
11167 break;
11168 case 4:
11169 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
11170 break;
11171 default:
11172 abort ();
11173 }
11174}
11175
22a398e1 11176/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 11177 being displayed in symbol relative addresses.
11178
11179 Also disallow private symbol, with __tagsym$$ prefix,
11180 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 11181
11182bfd_boolean
11183arm_symbol_is_valid (asymbol * sym,
11184 struct disassemble_info * info ATTRIBUTE_UNUSED)
11185{
11186 const char * name;
43e65147 11187
22a398e1
NC		 11188 if (sym == NULL)
11189 return FALSE;
11190
11191 name = bfd_asymbol_name (sym);
11192
d8282f0e 11193 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 11194}
11195
65b48a81 11196/* Parse the string of disassembler options. */
baf0cc5e 11197
65b48a81 11198static void
f995bbe8 11199parse_arm_disassembler_options (const char *options)
dd92f639 11200{
f995bbe8 11201 const char *opt;
b34976b6 11202
65b48a81 11203 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
dd92f639 11204 {
65b48a81
PB		 11205 if (CONST_STRNEQ (opt, "reg-names-"))
11206 {
11207 unsigned int i;
11208 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11209 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
11210 {
11211 regname_selected = i;
11212 break;
11213 }
b34976b6 11214
65b48a81 11215 if (i >= NUM_ARM_OPTIONS)
a6743a54
AM		 11216 /* xgettext: c-format */
11217 opcodes_error_handler (_("unrecognised register name set: %s"),
11218 opt);
65b48a81
PB		 11219 }
11220 else if (CONST_STRNEQ (opt, "force-thumb"))
11221 force_thumb = 1;
11222 else if (CONST_STRNEQ (opt, "no-force-thumb"))
11223 force_thumb = 0;
11224 else
a6743a54
AM		 11225 /* xgettext: c-format */
11226 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
dd92f639 11227 }
b34976b6 11228
dd92f639
NC		 11229 return;
11230}
11231
5bc5ae88
RL		 11232static bfd_boolean
11233mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11234 enum map_type *map_symbol);
11235
c22aaad1
PB		 11236/* Search back through the insn stream to determine if this instruction is
11237 conditionally executed. */
fe56b6ce 11238
c22aaad1 11239static void
fe56b6ce
NC		 11240find_ifthen_state (bfd_vma pc,
11241 struct disassemble_info *info,
c22aaad1
PB		 11242 bfd_boolean little)
11243{
11244 unsigned char b[2];
11245 unsigned int insn;
11246 int status;
11247 /* COUNT is twice the number of instructions seen. It will be odd if we
11248 just crossed an instruction boundary. */
11249 int count;
11250 int it_count;
11251 unsigned int seen_it;
11252 bfd_vma addr;
11253
11254 ifthen_address = pc;
11255 ifthen_state = 0;
11256
11257 addr = pc;
11258 count = 1;
11259 it_count = 0;
11260 seen_it = 0;
11261 /* Scan backwards looking for IT instructions, keeping track of where
11262 instruction boundaries are. We don't know if something is actually an
11263 IT instruction until we find a definite instruction boundary. */
11264 for (;;)
11265 {
fe56b6ce 11266 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 11267 {
11268 /* A symbol must be on an instruction boundary, and will not
11269 be within an IT block. */
11270 if (seen_it && (count & 1))
11271 break;
11272
11273 return;
11274 }
11275 addr -= 2;
fe56b6ce 11276 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 11277 if (status)
11278 return;
11279
11280 if (little)
11281 insn = (b[0]) | (b[1] << 8);
11282 else
11283 insn = (b[1]) | (b[0] << 8);
11284 if (seen_it)
11285 {
11286 if ((insn & 0xf800) < 0xe800)
11287 {
11288 /* Addr + 2 is an instruction boundary. See if this matches
11289 the expected boundary based on the position of the last
11290 IT candidate. */
11291 if (count & 1)
11292 break;
11293 seen_it = 0;
11294 }
11295 }
11296 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
11297 {
5bc5ae88
RL		 11298 enum map_type type = MAP_ARM;
11299 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
11300
11301 if (!found || (found && type == MAP_THUMB))
11302 {
11303 /* This could be an IT instruction. */
11304 seen_it = insn;
11305 it_count = count >> 1;
11306 }
c22aaad1
PB		 11307 }
11308 if ((insn & 0xf800) >= 0xe800)
11309 count++;
11310 else
11311 count = (count + 2) | 1;
11312 /* IT blocks contain at most 4 instructions. */
11313 if (count >= 8 && !seen_it)
11314 return;
11315 }
11316 /* We found an IT instruction. */
11317 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
11318 if ((ifthen_state & 0xf) == 0)
11319 ifthen_state = 0;
11320}
11321
b0e28b39
DJ		 11322/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
11323 mapping symbol. */
11324
11325static int
11326is_mapping_symbol (struct disassemble_info *info, int n,
11327 enum map_type *map_type)
11328{
11329 const char *name;
11330
11331 name = bfd_asymbol_name (info->symtab[n]);
11332 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
11333 && (name[2] == 0 || name[2] == '.'))
11334 {
11335 *map_type = ((name[1] == 'a') ? MAP_ARM
11336 : (name[1] == 't') ? MAP_THUMB
11337 : MAP_DATA);
11338 return TRUE;
11339 }
11340
11341 return FALSE;
11342}
11343
11344/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
11345 Returns nonzero if *MAP_TYPE was set. */
11346
11347static int
11348get_map_sym_type (struct disassemble_info *info,
11349 int n,
11350 enum map_type *map_type)
11351{
11352 /* If the symbol is in a different section, ignore it. */
11353 if (info->section != NULL && info->section != info->symtab[n]->section)
11354 return FALSE;
11355
11356 return is_mapping_symbol (info, n, map_type);
11357}
11358
11359/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 11360 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 11361
11362static int
fe56b6ce
NC		 11363get_sym_code_type (struct disassemble_info *info,
11364 int n,
e821645d 11365 enum map_type *map_type)
2087ad84
PB		 11366{
11367 elf_symbol_type *es;
11368 unsigned int type;
b0e28b39
DJ		 11369
11370 /* If the symbol is in a different section, ignore it. */
11371 if (info->section != NULL && info->section != info->symtab[n]->section)
11372 return FALSE;
2087ad84 11373
e821645d 11374 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 11375 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
11376
11377 /* If the symbol has function type then use that. */
34e77a92 11378 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 11379 {
39d911fc
TP		 11380 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
11381 == ST_BRANCH_TO_THUMB)
35fc36a8
RS		 11382 *map_type = MAP_THUMB;
11383 else
11384 *map_type = MAP_ARM;
2087ad84
PB		 11385 return TRUE;
11386 }
11387
2087ad84
PB		 11388 return FALSE;
11389}
11390
5bc5ae88
RL		 11391/* Search the mapping symbol state for instruction at pc. This is only
11392 applicable for elf target.
11393
11394 There is an assumption Here, info->private_data contains the correct AND
11395 up-to-date information about current scan process. The information will be
11396 used to speed this search process.
11397
11398 Return TRUE if the mapping state can be determined, and map_symbol
11399 will be updated accordingly. Otherwise, return FALSE. */
11400
11401static bfd_boolean
11402mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11403 enum map_type *map_symbol)
11404{
796d6298
TC		 11405 bfd_vma addr, section_vma = 0;
11406 int n, last_sym = -1;
5bc5ae88 11407 bfd_boolean found = FALSE;
796d6298
TC		 11408 bfd_boolean can_use_search_opt_p = FALSE;
11409
11410 /* Default to DATA. A text section is required by the ABI to contain an
11411 INSN mapping symbol at the start. A data section has no such
11412 requirement, hence if no mapping symbol is found the section must
11413 contain only data. This however isn't very useful if the user has
11414 fully stripped the binaries. If this is the case use the section
11415 attributes to determine the default. If we have no section default to
11416 INSN as well, as we may be disassembling some raw bytes on a baremetal
11417 HEX file or similar. */
11418 enum map_type type = MAP_DATA;
11419 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
11420 type = MAP_ARM;
5bc5ae88
RL		 11421 struct arm_private_data *private_data;
11422
796d6298 11423 if (info->private_data == NULL
5bc5ae88
RL		 11424 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
11425 return FALSE;
11426
11427 private_data = info->private_data;
5bc5ae88 11428
796d6298
TC		 11429 /* First, look for mapping symbols. */
11430 if (info->symtab_size != 0)
11431 {
11432 if (pc <= private_data->last_mapping_addr)
11433 private_data->last_mapping_sym = -1;
11434
11435 /* Start scanning at the start of the function, or wherever
11436 we finished last time. */
11437 n = info->symtab_pos + 1;
11438
11439 /* If the last stop offset is different from the current one it means we
11440 are disassembling a different glob of bytes. As such the optimization
11441 would not be safe and we should start over. */
11442 can_use_search_opt_p
11443 = private_data->last_mapping_sym >= 0
11444 && info->stop_offset == private_data->last_stop_offset;
11445
11446 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11447 n = private_data->last_mapping_sym;
11448
11449 /* Look down while we haven't passed the location being disassembled.
11450 The reason for this is that there's no defined order between a symbol
11451 and an mapping symbol that may be at the same address. We may have to
11452 look at least one position ahead. */
11453 for (; n < info->symtab_size; n++)
11454 {
11455 addr = bfd_asymbol_value (info->symtab[n]);
11456 if (addr > pc)
11457 break;
11458 if (get_map_sym_type (info, n, &type))
11459 {
11460 last_sym = n;
11461 found = TRUE;
11462 }
11463 }
5bc5ae88 11464
796d6298
TC		 11465 if (!found)
11466 {
11467 n = info->symtab_pos;
11468 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11469 n = private_data->last_mapping_sym;
11470
11471 /* No mapping symbol found at this address. Look backwards
11472 for a preceeding one, but don't go pass the section start
11473 otherwise a data section with no mapping symbol can pick up
11474 a text mapping symbol of a preceeding section. The documentation
11475 says section can be NULL, in which case we will seek up all the
11476 way to the top. */
11477 if (info->section)
11478 section_vma = info->section->vma;
11479
11480 for (; n >= 0; n--)
11481 {
11482 addr = bfd_asymbol_value (info->symtab[n]);
11483 if (addr < section_vma)
11484 break;
11485
11486 if (get_map_sym_type (info, n, &type))
11487 {
11488 last_sym = n;
11489 found = TRUE;
11490 break;
11491 }
11492 }
11493 }
11494 }
11495
11496 /* If no mapping symbol was found, try looking up without a mapping
11497 symbol. This is done by walking up from the current PC to the nearest
11498 symbol. We don't actually have to loop here since symtab_pos will
11499 contain the nearest symbol already. */
11500 if (!found)
5bc5ae88 11501 {
796d6298
TC		 11502 n = info->symtab_pos;
11503 if (n >= 0 && get_sym_code_type (info, n, &type))
5bc5ae88 11504 {
796d6298
TC		 11505 last_sym = n;
11506 found = TRUE;
5bc5ae88
RL		 11507 }
11508 }
11509
796d6298
TC		 11510 private_data->last_mapping_sym = last_sym;
11511 private_data->last_type = type;
11512 private_data->last_stop_offset = info->stop_offset;
5bc5ae88
RL		 11513
11514 *map_symbol = type;
11515 return found;
11516}
11517
0313a2b8
NC		 11518/* Given a bfd_mach_arm_XXX value, this function fills in the fields
11519 of the supplied arm_feature_set structure with bitmasks indicating
c0c468d5 11520 the supported base architectures and coprocessor extensions.
0313a2b8
NC		 11521
11522 FIXME: This could more efficiently implemented as a constant array,
11523 although it would also be less robust. */
11524
11525static void
11526select_arm_features (unsigned long mach,
11527 arm_feature_set * features)
11528{
c0c468d5
TP		 11529 arm_feature_set arch_fset;
11530 const arm_feature_set fpu_any = FPU_ANY;
11531
1af1dd51
MW		 11532#undef ARM_SET_FEATURES
11533#define ARM_SET_FEATURES(FSET) \
11534 { \
11535 const arm_feature_set fset = FSET; \
c0c468d5 11536 arch_fset = fset; \
1af1dd51 11537 }
823d2571 11538
c0c468d5
TP		 11539 /* When several architecture versions share the same bfd_mach_arm_XXX value
11540 the most featureful is chosen. */
0313a2b8
NC		 11541 switch (mach)
11542 {
c0c468d5
TP		 11543 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
11544 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
11545 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
11546 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
11547 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
11548 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
11549 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
11550 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
11551 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
11552 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
1af1dd51 11553 case bfd_mach_arm_ep9312:
c0c468d5
TP		 11554 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
11555 ARM_CEXT_MAVERICK | FPU_MAVERICK));
1af1dd51 11556 break;
c0c468d5
TP		 11557 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
11558 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
11559 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
11560 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
11561 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
11562 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
11563 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
11564 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
11565 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
11566 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
11567 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
11568 case bfd_mach_arm_8:
11569 {
0632eeea
SD		 11570 /* Add bits for extensions that Armv8.5-A recognizes. */
11571 arm_feature_set armv8_5_ext_fset
11572 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
11573 ARM_SET_FEATURES (ARM_ARCH_V8_5A);
11574 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset);
c0c468d5
TP		 11575 break;
11576 }
11577 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
11578 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
11579 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
73cd51e5
AV		 11580 case bfd_mach_arm_8_1M_MAIN:
11581 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
11582 force_thumb = 1;
11583 break;
c0c468d5
TP		 11584 /* If the machine type is unknown allow all architecture types and all
11585 extensions. */
11586 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
0313a2b8
NC		 11587 default:
11588 abort ();
11589 }
1af1dd51 11590#undef ARM_SET_FEATURES
c0c468d5
TP		 11591
11592 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
11593 and thus on bfd_mach_arm_XXX value. Therefore for a given
11594 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
11595 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
0313a2b8
NC		 11596}
11597
11598
58efb6c0
NC		 11599/* NOTE: There are no checks in these routines that
11600 the relevant number of data bytes exist. */
baf0cc5e 11601
58efb6c0 11602static int
4a5329c6 11603print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 11604{
c19d1205
ZW		 11605 unsigned char b[4];
11606 long given;
11607 int status;
e821645d 11608 int is_thumb = FALSE;
b0e28b39 11609 int is_data = FALSE;
bd2e2557 11610 int little_code;
e821645d 11611 unsigned int size = 4;
4a5329c6 11612 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 11613 bfd_boolean found = FALSE;
b0e28b39 11614 struct arm_private_data *private_data;
58efb6c0 11615
dd92f639
NC		 11616 if (info->disassembler_options)
11617 {
65b48a81 11618 parse_arm_disassembler_options (info->disassembler_options);
b34976b6 11619
58efb6c0 11620 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 11621 info->disassembler_options = NULL;
11622 }
b34976b6 11623
0313a2b8
NC		 11624 /* PR 10288: Control which instructions will be disassembled. */
11625 if (info->private_data == NULL)
11626 {
b0e28b39 11627 static struct arm_private_data private;
0313a2b8
NC		 11628
11629 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
11630 /* If the user did not use the -m command line switch then default to
11631 disassembling all types of ARM instruction.
43e65147 11632
0313a2b8
NC		 11633 The info->mach value has to be ignored as this will be based on
11634 the default archictecture for the target and/or hints in the notes
11635 section, but it will never be greater than the current largest arm
11636 machine value (iWMMXt2), which is only equivalent to the V5TE
11637 architecture. ARM architectures have advanced beyond the machine
11638 value encoding, and these newer architectures would be ignored if
11639 the machine value was used.
11640
11641 Ie the -m switch is used to restrict which instructions will be
11642 disassembled. If it is necessary to use the -m switch to tell
11643 objdump that an ARM binary is being disassembled, eg because the
11644 input is a raw binary file, but it is also desired to disassemble
11645 all ARM instructions then use "-marm". This will select the
11646 "unknown" arm architecture which is compatible with any ARM
11647 instruction. */
11648 info->mach = bfd_mach_arm_unknown;
11649
11650 /* Compute the architecture bitmask from the machine number.
11651 Note: This assumes that the machine number will not change
11652 during disassembly.... */
b0e28b39 11653 select_arm_features (info->mach, & private.features);
0313a2b8 11654
1fbaefec
PB		 11655 private.last_mapping_sym = -1;
11656 private.last_mapping_addr = 0;
796d6298 11657 private.last_stop_offset = 0;
b0e28b39
DJ		 11658
11659 info->private_data = & private;
0313a2b8 11660 }
b0e28b39
DJ		 11661
11662 private_data = info->private_data;
11663
bd2e2557
SS		 11664 /* Decide if our code is going to be little-endian, despite what the
11665 function argument might say. */
11666 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
11667
b0e28b39
DJ		 11668 /* For ELF, consult the symbol table to determine what kind of code
11669 or data we have. */
8977d4b2 11670 if (info->symtab_size != 0
e821645d
DJ		 11671 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
11672 {
11673 bfd_vma addr;
796d6298 11674 int n;
e821645d 11675 int last_sym = -1;
b0e28b39 11676 enum map_type type = MAP_ARM;
e821645d 11677
796d6298
TC		 11678 found = mapping_symbol_for_insn (pc, info, &type);
11679 last_sym = private_data->last_mapping_sym;
e821645d 11680
1fbaefec
PB		 11681 is_thumb = (private_data->last_type == MAP_THUMB);
11682 is_data = (private_data->last_type == MAP_DATA);
b34976b6 11683
e821645d
DJ		 11684 /* Look a little bit ahead to see if we should print out
11685 two or four bytes of data. If there's a symbol,
11686 mapping or otherwise, after two bytes then don't
11687 print more. */
11688 if (is_data)
11689 {
11690 size = 4 - (pc & 3);
11691 for (n = last_sym + 1; n < info->symtab_size; n++)
11692 {
11693 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 11694 if (addr > pc
11695 && (info->section == NULL
11696 || info->section == info->symtab[n]->section))
e821645d
DJ		 11697 {
11698 if (addr - pc < size)
11699 size = addr - pc;
11700 break;
11701 }
11702 }
11703 /* If the next symbol is after three bytes, we need to
11704 print only part of the data, so that we can use either
11705 .byte or .short. */
11706 if (size == 3)
11707 size = (pc & 1) ? 1 : 2;
11708 }
11709 }
11710
11711 if (info->symbols != NULL)
252b5132 11712 {
5876e06d
NC		 11713 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
11714 {
2f0ca46a 11715 coff_symbol_type * cs;
b34976b6 11716
5876e06d
NC		 11717 cs = coffsymbol (*info->symbols);
11718 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
11719 || cs->native->u.syment.n_sclass == C_THUMBSTAT
11720 || cs->native->u.syment.n_sclass == C_THUMBLABEL
11721 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
11722 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
11723 }
e821645d
DJ		 11724 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
11725 && !found)
5876e06d 11726 {
2087ad84
PB		 11727 /* If no mapping symbol has been found then fall back to the type
11728 of the function symbol. */
e821645d
DJ		 11729 elf_symbol_type * es;
11730 unsigned int type;
2087ad84 11731
e821645d
DJ		 11732 es = *(elf_symbol_type **)(info->symbols);
11733 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 11734
39d911fc
TP		 11735 is_thumb =
11736 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
11737 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
5876e06d 11738 }
e49d43ff
TG		 11739 else if (bfd_asymbol_flavour (*info->symbols)
11740 == bfd_target_mach_o_flavour)
11741 {
11742 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
11743
11744 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
11745 }
5876e06d 11746 }
b34976b6 11747
e821645d
DJ		 11748 if (force_thumb)
11749 is_thumb = TRUE;
11750
b8f9ee44
CL		 11751 if (is_data)
11752 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
11753 else
11754 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
11755
c19d1205 11756 info->bytes_per_line = 4;
252b5132 11757
1316c8b3
NC		 11758 /* PR 10263: Disassemble data if requested to do so by the user. */
11759 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 11760 {
11761 int i;
11762
1316c8b3 11763 /* Size was already set above. */
e821645d
DJ		 11764 info->bytes_per_chunk = size;
11765 printer = print_insn_data;
11766
fe56b6ce 11767 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 11768 given = 0;
11769 if (little)
11770 for (i = size - 1; i >= 0; i--)
11771 given = b[i] | (given << 8);
11772 else
11773 for (i = 0; i < (int) size; i++)
11774 given = b[i] | (given << 8);
11775 }
11776 else if (!is_thumb)
252b5132 11777 {
c19d1205
ZW		 11778 /* In ARM mode endianness is a straightforward issue: the instruction
11779 is four bytes long and is either ordered 0123 or 3210. */
11780 printer = print_insn_arm;
11781 info->bytes_per_chunk = 4;
4a5329c6 11782 size = 4;
c19d1205 11783
0313a2b8 11784 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 11785 if (little_code)
c19d1205
ZW		 11786 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
11787 else
11788 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
252b5132 11789 }
58efb6c0 11790 else
252b5132 11791 {
c19d1205
ZW		 11792 /* In Thumb mode we have the additional wrinkle of two
11793 instruction lengths. Fortunately, the bits that determine
11794 the length of the current instruction are always to be found
11795 in the first two bytes. */
4a5329c6 11796 printer = print_insn_thumb16;
c19d1205 11797 info->bytes_per_chunk = 2;
4a5329c6
ZW		 11798 size = 2;
11799
fe56b6ce 11800 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 11801 if (little_code)
9a2ff3f5
AM		 11802 given = (b[0]) | (b[1] << 8);
11803 else
11804 given = (b[1]) | (b[0] << 8);
11805
c19d1205 11806 if (!status)
252b5132 11807 {
c19d1205
ZW		 11808 /* These bit patterns signal a four-byte Thumb
11809 instruction. */
11810 if ((given & 0xF800) == 0xF800
11811 || (given & 0xF800) == 0xF000
11812 || (given & 0xF800) == 0xE800)
252b5132 11813 {
0313a2b8 11814 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 11815 if (little_code)
c19d1205 11816 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 11817 else
c19d1205
ZW		 11818 given = (b[1]) | (b[0] << 8) | (given << 16);
11819
11820 printer = print_insn_thumb32;
4a5329c6 11821 size = 4;
252b5132 11822 }
252b5132 11823 }
c22aaad1
PB		 11824
11825 if (ifthen_address != pc)
0313a2b8 11826 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 11827
11828 if (ifthen_state)
11829 {
11830 if ((ifthen_state & 0xf) == 0x8)
11831 ifthen_next_state = 0;
11832 else
11833 ifthen_next_state = (ifthen_state & 0xe0)
11834 | ((ifthen_state & 0xf) << 1);
11835 }
252b5132 11836 }
b34976b6 11837
c19d1205
ZW		 11838 if (status)
11839 {
11840 info->memory_error_func (status, pc, info);
11841 return -1;
11842 }
6a56ec7e
NC		 11843 if (info->flags & INSN_HAS_RELOC)
11844 /* If the instruction has a reloc associated with it, then
11845 the offset field in the instruction will actually be the
11846 addend for the reloc. (We are using REL type relocs).
11847 In such cases, we can ignore the pc when computing
11848 addresses, since the addend is not currently pc-relative. */
11849 pc = 0;
b34976b6 11850
4a5329c6 11851 printer (pc, info, given);
c22aaad1
PB		 11852
11853 if (is_thumb)
11854 {
11855 ifthen_state = ifthen_next_state;
11856 ifthen_address += size;
11857 }
4a5329c6 11858 return size;
252b5132
RH		 11859}
11860
11861int
4a5329c6 11862print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 11863{
bd2e2557
SS		 11864 /* Detect BE8-ness and record it in the disassembler info. */
11865 if (info->flavour == bfd_target_elf_flavour
11866 && info->section != NULL
11867 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
11868 info->endian_code = BFD_ENDIAN_LITTLE;
11869
b34976b6 11870 return print_insn (pc, info, FALSE);
58efb6c0 11871}
01c7f630 11872
58efb6c0 11873int
4a5329c6 11874print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 11875{
b34976b6 11876 return print_insn (pc, info, TRUE);
58efb6c0 11877}
252b5132 11878
471b9d15 11879const disasm_options_and_args_t *
65b48a81
PB		 11880disassembler_options_arm (void)
11881{
471b9d15 11882 static disasm_options_and_args_t *opts_and_args;
65b48a81 11883
471b9d15 11884 if (opts_and_args == NULL)
65b48a81 11885 {
471b9d15 11886 disasm_options_t *opts;
65b48a81 11887 unsigned int i;
471b9d15
MR		 11888
11889 opts_and_args = XNEW (disasm_options_and_args_t);
11890 opts_and_args->args = NULL;
11891
11892 opts = &opts_and_args->options;
65b48a81
PB		 11893 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
11894 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
471b9d15 11895 opts->arg = NULL;
65b48a81
PB		 11896 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11897 {
11898 opts->name[i] = regnames[i].name;
11899 if (regnames[i].description != NULL)
11900 opts->description[i] = _(regnames[i].description);
11901 else
11902 opts->description[i] = NULL;
11903 }
11904 /* The array we return must be NULL terminated. */
11905 opts->name[i] = NULL;
11906 opts->description[i] = NULL;
11907 }
11908
471b9d15 11909 return opts_and_args;
65b48a81
PB		 11910}
11911
58efb6c0 11912void
4a5329c6 11913print_arm_disassembler_options (FILE *stream)
58efb6c0 11914{
65b48a81 11915 unsigned int i, max_len = 0;
58efb6c0
NC		 11916 fprintf (stream, _("\n\
11917The following ARM specific disassembler options are supported for use with\n\
11918the -M switch:\n"));
b34976b6 11919
65b48a81
PB		 11920 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11921 {
11922 unsigned int len = strlen (regnames[i].name);
11923 if (max_len < len)
11924 max_len = len;
11925 }
58efb6c0 11926
65b48a81
PB		 11927 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
11928 fprintf (stream, " %s%*c %s\n",
11929 regnames[i].name,
11930 (int)(max_len - strlen (regnames[i].name)), ' ',
11931 _(regnames[i].description));
252b5132 11932}
GDB Binutils - Deliverables
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