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[PATCH 38/57][Arm][OBJDUMP] Disable the use of MVE reserved coproc numbers in coproce...
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
CommitLineData
252b5132 1/* Instruction printing code for the ARM
82704155 2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
2fbad815 24
6394c606 25#include "disassemble.h"
2fbad815 26#include "opcode/arm.h"
252b5132 27#include "opintl.h"
31e0f3cd 28#include "safe-ctype.h"
65b48a81 29#include "libiberty.h"
0dbde4cf 30#include "floatformat.h"
252b5132 31
baf0cc5e 32/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 33#include "coff/internal.h"
34#include "libcoff.h"
2d5d5a8f 35#include "bfd.h"
252b5132
RH		 36#include "elf-bfd.h"
37#include "elf/internal.h"
38#include "elf/arm.h"
e49d43ff 39#include "mach-o.h"
252b5132 40
6b5d3a4d 41/* FIXME: Belongs in global header. */
01c7f630 42#ifndef strneq
58efb6c0
NC		 43#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
44#endif
45
1fbaefec
PB		 46/* Cached mapping symbol state. */
47enum map_type
48{
49 MAP_ARM,
50 MAP_THUMB,
51 MAP_DATA
52};
53
b0e28b39
DJ		 54struct arm_private_data
55{
56 /* The features to use when disassembling optional instructions. */
57 arm_feature_set features;
58
1fbaefec
PB		 59 /* Track the last type (although this doesn't seem to be useful) */
60 enum map_type last_type;
61
62 /* Tracking symbol table information */
63 int last_mapping_sym;
796d6298
TC		 64
65 /* The end range of the current range being disassembled. */
66 bfd_vma last_stop_offset;
1fbaefec 67 bfd_vma last_mapping_addr;
b0e28b39
DJ		 68};
69
73cd51e5
AV		 70enum mve_instructions
71{
72 MVE_NONE
73};
74
75enum mve_unpredictable
76{
77 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
78 */
79 UNPRED_NONE /* No unpredictable behavior. */
80};
81
82enum mve_undefined
83{
84 UNDEF_NONE /* no undefined behavior. */
85};
86
6b5d3a4d
ZW		 87struct opcode32
88{
823d2571
TG		 89 arm_feature_set arch; /* Architecture defining this insn. */
90 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 91 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 92 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 93};
94
73cd51e5
AV		 95/* MVE opcodes. */
96
97struct mopcode32
98{
99 arm_feature_set arch; /* Architecture defining this insn. */
100 enum mve_instructions mve_op; /* Specific mve instruction for faster
101 decoding. */
102 unsigned long value; /* If arch is 0 then value is a sentinel. */
103 unsigned long mask; /* Recognise insn if (op & mask) == value. */
104 const char * assembler; /* How to disassemble this insn. */
105};
106
6b0dd094
AV		 107enum isa {
108 ANY,
109 T32,
110 ARM
111};
112
113
114/* Shared (between Arm and Thumb mode) opcode. */
115struct sopcode32
116{
117 enum isa isa; /* Execution mode instruction availability. */
118 arm_feature_set arch; /* Architecture defining this insn. */
119 unsigned long value; /* If arch is 0 then value is a sentinel. */
120 unsigned long mask; /* Recognise insn if (op & mask) == value. */
121 const char * assembler; /* How to disassemble this insn. */
122};
123
6b5d3a4d
ZW		 124struct opcode16
125{
823d2571 126 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 127 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 128 const char *assembler; /* How to disassemble this insn. */
129};
b7693d02 130
8f06b2d8 131/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 132
2fbad815 133 %% %
4a5329c6 134
c22aaad1 135 %c print condition code (always bits 28-31 in ARM mode)
37b37b2d 136 %q print shifter argument
e2efe87d
MGD		 137 %u print condition code (unconditional in ARM mode,
138 UNPREDICTABLE if not AL in Thumb)
4a5329c6 139 %A print address for ldc/stc/ldf/stf instruction
16980d0b 140 %B print vstm/vldm register list
efd6b359 141 %C print vscclrm register list
4a5329c6 142 %I print cirrus signed shift immediate: bits 0..3|4..6
32c36c3c
AV		 143 %J print register for VLDR instruction
144 %K print address for VLDR instruction
4a5329c6
ZW		 145 %F print the COUNT field of a LFM/SFM instruction.
146 %P print floating point precision in arithmetic insn
147 %Q print floating point precision in ldf/stf insn
148 %R print floating point rounding mode
149
33399f07 150 %<bitfield>c print as a condition code (for vsel)
4a5329c6 151 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 152 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
153 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 154 %<bitfield>d print the bitfield in decimal
16980d0b 155 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 156 %<bitfield>x print the bitfield in hex
157 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 158 %<bitfield>f print a floating point constant if >7 else a
159 floating point register
4a5329c6
ZW		 160 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
161 %<bitfield>g print as an iWMMXt 64-bit register
162 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 163 %<bitfield>D print as a NEON D register
164 %<bitfield>Q print as a NEON Q register
c28eeff2 165 %<bitfield>V print as a NEON D or Q register
6f1c2142 166 %<bitfield>E print a quarter-float immediate value
4a5329c6 167
16980d0b 168 %y<code> print a single precision VFP reg.
2fbad815 169 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 170 %z<code> print a double precision VFP reg
2fbad815 171 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 172
16980d0b
JB		 173 %<bitfield>'c print specified char iff bitfield is all ones
174 %<bitfield>`c print specified char iff bitfield is all zeroes
175 %<bitfield>?ab... select from array of values in big endian order
43e65147 176
2fbad815 177 %L print as an iWMMXt N/M width field.
4a5329c6 178 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 179 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 180 versions.
181 %i print 5-bit immediate in bits 8,3..0
182 (print "32" when 0)
fe56b6ce 183 %r print register offset address for wldt/wstr instruction. */
2fbad815 184
21d799b5 185enum opcode_sentinel_enum
05413229
NC		 186{
187 SENTINEL_IWMMXT_START = 1,
188 SENTINEL_IWMMXT_END,
189 SENTINEL_GENERIC_START
190} opcode_sentinels;
191
aefd8a40 192#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
0b347048
TC		 193#define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
194#define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
c1e26897 195#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 196
8f06b2d8 197/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 198
6b0dd094 199static const struct sopcode32 coprocessor_opcodes[] =
2fbad815 200{
2fbad815 201 /* XScale instructions. */
6b0dd094 202 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 203 0x0e200010, 0x0fff0ff0,
204 "mia%c\tacc0, %0-3r, %12-15r"},
6b0dd094 205 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 206 0x0e280010, 0x0fff0ff0,
207 "miaph%c\tacc0, %0-3r, %12-15r"},
6b0dd094 208 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 209 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
6b0dd094 210 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 211 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
6b0dd094 212 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 213 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 214
2fbad815 215 /* Intel Wireless MMX technology instructions. */
6b0dd094
AV		 216 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
217 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
823d2571 218 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
6b0dd094 219 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 220 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
6b0dd094 221 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 222 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
6b0dd094 223 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 224 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
6b0dd094 225 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 226 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
6b0dd094 227 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 228 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
6b0dd094 229 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 230 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
6b0dd094 231 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 232 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 233 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 234 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 235 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 236 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 237 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 238 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
6b0dd094 239 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 240 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
6b0dd094 241 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 242 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
6b0dd094 243 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 244 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
6b0dd094 245 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 246 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
6b0dd094 247 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 248 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 249 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 250 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 251 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 252 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 253 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 254 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 255 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 256 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 257 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 258 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
6b0dd094 259 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 260 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 261 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 262 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 263 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 264 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 265 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 266 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 267 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 268 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 269 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 270 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 271 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 272 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
6b0dd094 273 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 274 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
6b0dd094 275 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 276 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
6b0dd094 277 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 278 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 279 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 280 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 281 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 282 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 283 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 284 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 285 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 286 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
6b0dd094 287 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 288 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 289 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 290 0x0e800120, 0x0f800ff0,
291 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 292 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 293 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 294 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 295 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 296 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 297 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 298 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 299 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 300 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 301 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 302 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 303 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 304 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 305 0x0e8000a0, 0x0f800ff0,
306 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 307 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 308 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 309 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 310 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 311 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 312 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 313 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 314 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 315 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 316 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 317 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 318 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 319 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 320 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 321 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 322 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 323 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 324 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
6b0dd094 325 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 326 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 327 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 328 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 329 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 330 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 331 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 332 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 333 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 334 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 335 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 336 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 337 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 338 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 339 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 340 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 341 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 342 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 343 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 344 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
6b0dd094 345 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 346 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
6b0dd094 347 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 348 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
6b0dd094 349 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 350 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 351 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 352 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 353 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 354 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 355 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 356 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
6b0dd094 357 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 358 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
6b0dd094 359 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 360 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
6b0dd094 361 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 362 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 363 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 364 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 365 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 366 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 367 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 368 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 369 {ANY, ARM_FEATURE_CORE_LOW (0),
823d2571 370 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 371
fe56b6ce 372 /* Floating point coprocessor (FPA) instructions. */
6b0dd094 373 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 374 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 375 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 376 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 377 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 378 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 379 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 380 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 381 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 382 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 383 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 384 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 385 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 386 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 387 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 388 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 389 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 390 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 391 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 392 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 393 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 394 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 395 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 396 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 397 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 398 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 399 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 400 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 401 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 402 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 403 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 404 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 405 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 406 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 407 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 408 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
6b0dd094 409 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 410 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
6b0dd094 411 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 412 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 413 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 414 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
6b0dd094 415 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 416 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
6b0dd094 417 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 418 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
6b0dd094 419 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 420 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
6b0dd094 421 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 422 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 423 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 424 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 425 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 426 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 427 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 428 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 429 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 430 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
6b0dd094 431 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 432 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
6b0dd094 433 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 434 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
6b0dd094 435 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 436 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
6b0dd094 437 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 438 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
6b0dd094 439 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 440 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
6b0dd094 441 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 442 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
6b0dd094 443 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 444 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
6b0dd094 445 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 446 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
6b0dd094 447 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 448 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
6b0dd094 449 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 450 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
6b0dd094 451 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 452 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
6b0dd094 453 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 454 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
6b0dd094 455 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 456 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
6b0dd094 457 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 458 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 459
efd6b359
AV		 460 /* Armv8.1-M Mainline instructions. */
461 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
462 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
463 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
464 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
465
16a1fa25 466 /* ARMv8-M Mainline Security Extensions instructions. */
6b0dd094 467 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25 468 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
6b0dd094 469 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25
TP		 470 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
471
fe56b6ce 472 /* Register load/store. */
6b0dd094 473 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 474 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
6b0dd094 475 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 476 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
6b0dd094 477 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 478 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
6b0dd094 479 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 480 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
6b0dd094 481 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 482 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
6b0dd094 483 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 484 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
6b0dd094 485 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 486 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
6b0dd094 487 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 488 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
6b0dd094 489 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 490 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
6b0dd094 491 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 492 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
6b0dd094 493 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 494 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
6b0dd094 495 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 496 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
6b0dd094 497 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 498 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
6b0dd094 499 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 500 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
6b0dd094 501 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 502 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
6b0dd094 503 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 504 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
32c36c3c
AV		 505 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
506 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
507 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
508 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
823d2571 509
6b0dd094 510 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 511 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 512 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 513 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 514 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 515 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
6b0dd094 516 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 517 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 518
fe56b6ce 519 /* Data transfer between ARM and NEON registers. */
6b0dd094 520 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 521 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
6b0dd094 522 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 523 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
6b0dd094 524 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 525 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
6b0dd094 526 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 527 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
6b0dd094 528 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 529 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
6b0dd094 530 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 531 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
6b0dd094 532 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 533 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
6b0dd094 534 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 535 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
6b0dd094 536 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 537 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
6b0dd094 538 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 539 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
6b0dd094 540 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 541 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
6b0dd094 542 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 543 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
6b0dd094 544 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 545 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
6b0dd094 546 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 547 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 548 /* Half-precision conversion instructions. */
6b0dd094 549 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 550 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
6b0dd094 551 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 552 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
6b0dd094 553 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 554 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
6b0dd094 555 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 556 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 557
fe56b6ce 558 /* Floating point coprocessor (VFP) instructions. */
6b0dd094 559 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 560 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
6b0dd094 561 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 562 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
6b0dd094 563 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 564 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
6b0dd094 565 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 566 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
6b0dd094 567 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 568 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
6b0dd094 569 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 570 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
6b0dd094 571 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 572 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
6b0dd094 573 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 574 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
6b0dd094 575 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 576 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
6b0dd094 577 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 578 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
6b0dd094 579 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 580 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
6b0dd094 581 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 582 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
6b0dd094 583 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 584 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
6b0dd094 585 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 586 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
6b0dd094 587 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 588 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
6b0dd094 589 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 590 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
6b0dd094 591 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 592 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
6b0dd094 593 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 594 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
6b0dd094 595 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 596 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
6b0dd094 597 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 598 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
6b0dd094 599 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 600 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
6b0dd094 601 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 602 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
6b0dd094 603 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 604 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
6b0dd094 605 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 606 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
6b0dd094 607 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 608 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
6b0dd094 609 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 610 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
6b0dd094 611 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 612 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
6b0dd094 613 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 614 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
6b0dd094 615 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 616 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
6b0dd094 617 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 618 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
6b0dd094 619 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 620 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
6b0dd094 621 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 622 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
6b0dd094 623 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 624 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
6b0dd094 625 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 626 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
6b0dd094 627 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 628 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
6b0dd094 629 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 630 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
6b0dd094 631 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 632 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
6b0dd094 633 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 634 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
6b0dd094 635 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 636 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
6b0dd094 637 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 638 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 639 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 640 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
6b0dd094 641 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 642 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
6b0dd094 643 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 644 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
6b0dd094 645 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 646 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
6b0dd094 647 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 648 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
6b0dd094 649 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 650 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
6b0dd094 651 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6f1c2142 652 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
6b0dd094 653 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6f1c2142 654 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
6b0dd094 655 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 656 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
6b0dd094 657 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 658 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
6b0dd094 659 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 660 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
6b0dd094 661 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 662 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 663 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 664 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 665 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 666 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 667 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 668 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 669 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 670 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 671 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 672 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 673 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 674 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 675 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 676 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 677 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 678 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 679 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 680 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 681 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 682 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 683 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 684 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 685 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 686 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
6b0dd094 687 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 688 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
6b0dd094 689 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 690 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
6b0dd094 691 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 692 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
6b0dd094 693 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 694 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
6b0dd094 695 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 696 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 697
698 /* Cirrus coprocessor instructions. */
6b0dd094 699 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 700 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 701 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 702 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 703 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 704 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 705 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 706 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 707 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 708 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 709 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 710 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 711 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 712 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 713 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 714 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 715 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 716 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 717 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 718 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 719 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 720 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 721 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 722 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 723 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 724 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 725 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 726 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 727 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 728 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 729 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 730 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 731 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 732 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
6b0dd094 733 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 734 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
6b0dd094 735 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 736 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
6b0dd094 737 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 738 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
6b0dd094 739 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 740 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
6b0dd094 741 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 742 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
6b0dd094 743 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 744 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 745 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 746 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
6b0dd094 747 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 748 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 749 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 750 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
6b0dd094 751 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 752 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 753 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 754 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 755 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 756 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 757 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 758 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 759 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 760 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 761 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 762 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 763 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 764 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 765 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 766 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 767 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 768 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
6b0dd094 769 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 770 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
6b0dd094 771 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 772 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
6b0dd094 773 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 774 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
6b0dd094 775 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 776 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 777 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 778 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 779 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 780 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
6b0dd094 781 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 782 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
6b0dd094 783 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 784 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
6b0dd094 785 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 786 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
6b0dd094 787 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 788 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
6b0dd094 789 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 790 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
6b0dd094 791 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 792 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 793 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 794 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 795 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 796 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 797 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 798 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 799 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 800 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
6b0dd094 801 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 802 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
6b0dd094 803 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 804 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
6b0dd094 805 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 806 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
6b0dd094 807 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 808 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
6b0dd094 809 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 810 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
6b0dd094 811 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 812 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 813 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 814 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 815 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 816 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 817 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 818 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 819 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 820 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 821 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 822 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 823 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 824 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 825 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 826 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 827 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 828 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 829 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 830 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 831 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 832 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 833 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 834 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 835 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 836 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 837 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 838 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 839 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 840 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 841 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 842 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 843 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 844 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 845 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 846 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 847 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 848 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 849 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 850 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 851 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 852 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 853 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 854 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 855 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 856 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 857 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 858 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 859 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 860 0x0e000600, 0x0ff00f10,
861 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 862 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 863 0x0e100600, 0x0ff00f10,
864 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 865 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 866 0x0e200600, 0x0ff00f10,
867 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 868 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 869 0x0e300600, 0x0ff00f10,
870 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 871
62f3b8c8 872 /* VFP Fused multiply add instructions. */
6b0dd094 873 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 874 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
6b0dd094 875 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 876 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
6b0dd094 877 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 878 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
6b0dd094 879 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 880 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
6b0dd094 881 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 882 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
6b0dd094 883 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 884 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
6b0dd094 885 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 886 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
6b0dd094 887 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 888 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 889
33399f07 890 /* FP v5. */
6b0dd094 891 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 892 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
6b0dd094 893 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 894 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
6b0dd094 895 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 896 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 897 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 898 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 899 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 900 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 901 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 902 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 903 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 904 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
6b0dd094 905 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 906 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
6b0dd094 907 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 908 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
6b0dd094 909 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 910 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
6b0dd094 911 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 912 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
6b0dd094 913 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 914 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 915
05413229 916 /* Generic coprocessor instructions. */
6b0dd094
AV		 917 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
918 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
823d2571 919 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
6b0dd094 920 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
823d2571
TG		 921 0x0c500000, 0x0ff00000,
922 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
6b0dd094 923 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 924 0x0e000000, 0x0f000010,
925 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 926 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 927 0x0e10f010, 0x0f10f010,
928 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 929 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 930 0x0e100010, 0x0f100010,
931 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 932 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 933 0x0e000010, 0x0f100010,
934 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 935 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571 936 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 937 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571 938 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
2fbad815 939
05413229 940 /* V6 coprocessor instructions. */
6b0dd094 941 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
823d2571
TG		 942 0xfc500000, 0xfff00000,
943 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
6b0dd094 944 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
823d2571
TG		 945 0xfc400000, 0xfff00000,
946 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
8f06b2d8 947
c28eeff2 948 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
6b0dd094 949 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 950 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 951 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 952 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 953 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 954 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 955 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 956 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 957 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 958 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 959 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 960 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 961 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 962 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
6b0dd094 963 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 964 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
6b0dd094 965 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 966 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
6b0dd094 967 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 968 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
c28eeff2 969
c604a79a 970 /* Dot Product instructions in the space of coprocessor 13. */
6b0dd094 971 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a 972 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
6b0dd094 973 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a
JW		 974 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
975
dec41383 976 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
6b0dd094 977 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 978 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 979 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 980 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 981 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 982 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 983 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 984 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 985 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 986 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 987 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 988 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 989 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 990 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
6b0dd094 991 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383
JW		 992 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
993
05413229 994 /* V5 coprocessor instructions. */
6b0dd094 995 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571 996 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 997 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571 998 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 999 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1000 0xfe000000, 0xff000010,
1001 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1002 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1003 0xfe000010, 0xff100010,
1004 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1005 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1006 0xfe100010, 0xff100010,
1007 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1008
b0c11777
RL		 1009 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1010 cp_num: bit <11:8> == 0b1001.
1011 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
6b0dd094 1012 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1013 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
6b0dd094 1014 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1015 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
6b0dd094 1016 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1017 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
6b0dd094 1018 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1019 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
6b0dd094 1020 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1021 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 1022 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1023 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
6b0dd094 1024 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1025 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
6b0dd094 1026 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1027 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
6b0dd094 1028 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1029 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
6b0dd094 1030 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1031 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
6b0dd094 1032 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1033 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1034 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1035 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1036 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1037 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1038 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1039 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1040 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1041 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
6b0dd094 1042 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1043 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
6b0dd094 1044 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1045 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
6b0dd094 1046 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1047 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
6b0dd094 1048 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1049 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1050 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1051 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1052 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1053 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1054 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1055 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1056 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1057 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
6b0dd094 1058 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1059 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
6b0dd094 1060 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1061 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
6b0dd094 1062 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1063 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1064 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1065 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
6b0dd094 1066 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1067 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1068 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1069 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1070 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1071 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1072 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1073 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
6b0dd094 1074 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1075 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
6b0dd094 1076 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1077 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
6b0dd094 1078 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1079 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
6b0dd094 1080 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777
RL		 1081 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1082
49e8a725 1083 /* ARMv8.3 javascript conversion instruction. */
6b0dd094 1084 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
49e8a725
SN		 1085 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1086
6b0dd094 1087 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 1088};
1089
16980d0b
JB		 1090/* Neon opcode table: This does not encode the top byte -- that is
1091 checked by the print_insn_neon routine, as it depends on whether we are
1092 doing thumb32 or arm32 disassembly. */
1093
1094/* print_insn_neon recognizes the following format control codes:
1095
1096 %% %
1097
c22aaad1 1098 %c print condition code
e2efe87d
MGD		 1099 %u print condition code (unconditional in ARM mode,
1100 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 1101 %A print v{st,ld}[1234] operands
1102 %B print v{st,ld}[1234] any one operands
1103 %C print v{st,ld}[1234] single->all operands
1104 %D print scalar
1105 %E print vmov, vmvn, vorr, vbic encoded constant
1106 %F print vtbl,vtbx register list
1107
1108 %<bitfield>r print as an ARM register
1109 %<bitfield>d print the bitfield in decimal
1110 %<bitfield>e print the 2^N - bitfield in decimal
1111 %<bitfield>D print as a NEON D register
1112 %<bitfield>Q print as a NEON Q register
1113 %<bitfield>R print as a NEON D or Q register
1114 %<bitfield>Sn print byte scaled width limited by n
1115 %<bitfield>Tn print short scaled width limited by n
1116 %<bitfield>Un print long scaled width limited by n
43e65147 1117
16980d0b
JB		 1118 %<bitfield>'c print specified char iff bitfield is all ones
1119 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1120 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1121
1122static const struct opcode32 neon_opcodes[] =
1123{
fe56b6ce 1124 /* Extract. */
823d2571
TG		 1125 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1126 0xf2b00840, 0xffb00850,
1127 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1128 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1129 0xf2b00000, 0xffb00810,
1130 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 1131
fe56b6ce 1132 /* Move data element to all lanes. */
823d2571
TG		 1133 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1134 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1135 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1136 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1137 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1138 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 1139
fe56b6ce 1140 /* Table lookup. */
823d2571
TG		 1141 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1142 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1143 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1144 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1145
8e79c3df 1146 /* Half-precision conversions. */
823d2571
TG		 1147 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1148 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1149 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1150 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1151
1152 /* NEON fused multiply add instructions. */
823d2571 1153 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1154 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1155 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1156 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1157 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1158 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1159 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1160 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1161
fe56b6ce 1162 /* Two registers, miscellaneous. */
823d2571
TG		 1163 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1164 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1165 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1166 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1167 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1168 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1169 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1170 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1171 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1172 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1173 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1174 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1175 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1176 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1177 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1178 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1179 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1180 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1181 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1182 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1183 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1184 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1185 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1186 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1187 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1188 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1189 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1190 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1191 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1192 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1193 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1194 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1195 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1196 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1197 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1198 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1199 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1200 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1201 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1202 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1203 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1204 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1205 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1206 0xf3b20300, 0xffb30fd0,
1207 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1208 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1209 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1210 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1211 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1212 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1213 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1214 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1215 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1216 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1217 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1218 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1219 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1220 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1221 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1222 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1223 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1224 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1225 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1226 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1227 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1228 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1229 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1230 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1231 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1232 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1233 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1234 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1235 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1236 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1237 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1238 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1239 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1240 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1241 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1242 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1243 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1244 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1245 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1246 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1247 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1248 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1249 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1250 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1251 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1252 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1253 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1254 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301 1255 0xf3bb0600, 0xffbf0e10,
823d2571 1256 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1257 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1258 0xf3b70600, 0xffbf0e10,
1259 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
16980d0b 1260
fe56b6ce 1261 /* Three registers of the same length. */
823d2571
TG		 1262 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1263 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1264 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1265 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1266 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1267 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1268 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1269 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1270 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1271 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1272 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1273 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1274 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1275 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1276 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1277 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1278 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1279 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1280 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1281 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1282 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1283 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1284 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1285 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1286 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1287 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1288 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1289 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1290 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1291 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1292 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1293 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1294 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1295 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1296 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1297 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1298 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1299 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1300 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1301 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1302 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1303 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1304 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1305 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1306 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1307 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1308 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1309 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1310 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1311 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1312 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1313 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1314 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1315 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1316 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1317 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1318 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1319 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1320 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1321 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1322 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1323 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1324 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1325 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1326 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1327 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1328 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1329 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1330 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1331 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1332 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1333 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1334 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1335 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1336 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1337 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1338 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1339 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1340 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1341 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1342 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1343 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1344 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1345 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1346 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1347 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1348 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1349 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1350 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1351 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1352 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1353 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1354 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1355 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1356 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1357 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1358 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1359 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1360 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1361 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1362 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1363 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1364 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1365 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1366 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1367 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1368 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1369 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1370 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1371 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1372 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1373 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1374 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1375 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1376 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1377 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1378 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1379 0xf2000b00, 0xff800f10,
1380 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1381 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1382 0xf2000b10, 0xff800f10,
1383 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1384 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1385 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1386 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1387 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1388 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1389 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1390 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1391 0xf3000b00, 0xff800f10,
1392 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1393 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1394 0xf2000000, 0xfe800f10,
1395 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1396 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1397 0xf2000010, 0xfe800f10,
1398 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1399 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1400 0xf2000100, 0xfe800f10,
1401 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1402 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1403 0xf2000200, 0xfe800f10,
1404 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1405 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1406 0xf2000210, 0xfe800f10,
1407 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1408 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1409 0xf2000300, 0xfe800f10,
1410 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1411 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1412 0xf2000310, 0xfe800f10,
1413 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1414 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1415 0xf2000400, 0xfe800f10,
1416 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1417 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1418 0xf2000410, 0xfe800f10,
1419 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1420 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1421 0xf2000500, 0xfe800f10,
1422 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1423 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1424 0xf2000510, 0xfe800f10,
1425 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1426 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1427 0xf2000600, 0xfe800f10,
1428 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1429 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1430 0xf2000610, 0xfe800f10,
1431 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1432 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1433 0xf2000700, 0xfe800f10,
1434 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1435 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1436 0xf2000710, 0xfe800f10,
1437 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1438 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1439 0xf2000910, 0xfe800f10,
1440 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1441 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1442 0xf2000a00, 0xfe800f10,
1443 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1444 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1445 0xf2000a10, 0xfe800f10,
1446 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1447 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1448 0xf3000b10, 0xff800f10,
1449 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1450 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1451 0xf3000c10, 0xff800f10,
1452 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1453
fe56b6ce 1454 /* One register and an immediate value. */
823d2571
TG		 1455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1456 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1457 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1458 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1459 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1460 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1462 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1464 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1466 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1468 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1470 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1472 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1474 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1476 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1478 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1480 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1481
fe56b6ce 1482 /* Two registers and a shift amount. */
823d2571
TG		 1483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1484 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1486 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1487 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1488 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1489 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1490 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1492 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1494 0xf2880950, 0xfeb80fd0,
1495 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1496 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1497 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1498 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1499 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1500 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1501 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1502 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1503 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1504 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1505 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1506 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1507 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1508 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1509 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1510 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1511 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1512 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1513 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1514 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1515 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1516 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1517 0xf2900950, 0xfeb00fd0,
1518 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1519 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1520 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1521 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1522 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1523 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1524 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1525 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1526 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1527 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1528 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1530 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1531 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1532 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1533 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1534 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1535 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1536 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1537 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1538 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1539 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1540 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1541 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1542 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1543 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1544 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1545 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1546 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1547 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1548 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1549 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1550 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1551 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1552 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1553 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1554 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1555 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1556 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1557 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1558 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1559 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1560 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1561 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1562 0xf2a00950, 0xfea00fd0,
1563 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1564 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1565 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1566 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1567 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1568 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1569 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1570 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1571 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1572 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1573 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1574 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1575 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1576 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1577 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1578 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1579 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1580 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1581 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1582 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1583 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1584 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1585 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1586 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1587 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1588 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1589 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1590 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1591 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1592 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1593 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1594 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1595 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1596 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1597 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1598 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1599 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1600 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1601 0xf2a00e10, 0xfea00e90,
1602 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
cc933301
JW		 1603 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1604 0xf2a00c10, 0xfea00e90,
1605 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 1606
fe56b6ce 1607 /* Three registers of different lengths. */
823d2571
TG		 1608 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1609 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1610 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1611 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1612 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1613 0xf2800400, 0xff800f50,
1614 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1615 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1616 0xf2800600, 0xff800f50,
1617 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1618 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1619 0xf2800900, 0xff800f50,
1620 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1621 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1622 0xf2800b00, 0xff800f50,
1623 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1624 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1625 0xf2800d00, 0xff800f50,
1626 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1627 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1628 0xf3800400, 0xff800f50,
1629 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1630 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1631 0xf3800600, 0xff800f50,
1632 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1633 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1634 0xf2800000, 0xfe800f50,
1635 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1636 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1637 0xf2800100, 0xfe800f50,
1638 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1639 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1640 0xf2800200, 0xfe800f50,
1641 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1642 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1643 0xf2800300, 0xfe800f50,
1644 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1646 0xf2800500, 0xfe800f50,
1647 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1648 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1649 0xf2800700, 0xfe800f50,
1650 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1651 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1652 0xf2800800, 0xfe800f50,
1653 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1654 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1655 0xf2800a00, 0xfe800f50,
1656 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1658 0xf2800c00, 0xfe800f50,
1659 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 1660
fe56b6ce 1661 /* Two registers and a scalar. */
823d2571
TG		 1662 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1663 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1664 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1665 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1666 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1667 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1668 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1669 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1670 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1671 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1672 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1673 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1674 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1675 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1676 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1677 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1678 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1679 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1680 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1681 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1682 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1683 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1685 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1687 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1688 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1689 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1691 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1692 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1693 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1694 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1695 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1696 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1697 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1698 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1699 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1700 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1701 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1702 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1703 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1704 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1705 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1706 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1707 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1708 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1709 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1710 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1711 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1712 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1713 0xf2800240, 0xfe800f50,
1714 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1715 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1716 0xf2800640, 0xfe800f50,
1717 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1718 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1719 0xf2800a40, 0xfe800f50,
1720 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 1721 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1722 0xf2800e40, 0xff800f50,
1723 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1724 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1725 0xf2800f40, 0xff800f50,
1726 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1727 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1728 0xf3800e40, 0xff800f50,
1729 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1730 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1731 0xf3800f40, 0xff800f50,
1732 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1733 },
16980d0b 1734
fe56b6ce 1735 /* Element and structure load/store. */
823d2571
TG		 1736 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1737 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1738 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1739 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1740 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1741 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1742 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1743 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1744 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1745 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1746 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1747 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1748 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1749 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1750 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1751 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1753 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1754 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1755 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1756 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1757 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1758 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1759 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1760 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1761 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1762 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1763 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1764 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1765 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1766 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1767 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1768 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1769 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1770 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1771 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1772 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1773 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1774
1775 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 1776};
1777
73cd51e5
AV		 1778/* mve opcode table. */
1779
1780/* print_insn_mve recognizes the following format control codes:
1781
1782 %% %
1783
1784 */
1785
1786static const struct mopcode32 mve_opcodes[] =
1787{
1788};
1789
8f06b2d8
PB		 1790/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
1791 ordered: they must be searched linearly from the top to obtain a correct
1792 match. */
1793
1794/* print_insn_arm recognizes the following format control codes:
1795
1796 %% %
1797
1798 %a print address for ldr/str instruction
1799 %s print address for ldr/str halfword/signextend instruction
c1e26897 1800 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 1801 %b print branch destination
1802 %c print condition code (always bits 28-31)
1803 %m print register mask for ldm/stm instruction
1804 %o print operand2 (immediate or register + shift)
1805 %p print 'p' iff bits 12-15 are 15
1806 %t print 't' iff bit 21 set and bit 24 clear
1807 %B print arm BLX(1) destination
1808 %C print the PSR sub type.
62b3e311
PB		 1809 %U print barrier type.
1810 %P print address for pli instruction.
8f06b2d8
PB		 1811
1812 %<bitfield>r print as an ARM register
9eb6c0f1 1813 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 1814 %<bitfield>R as %r but r15 is UNPREDICTABLE
1815 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1816 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 1817 %<bitfield>d print the bitfield in decimal
43e65147 1818 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 1819 %<bitfield>x print the bitfield in hex
1820 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 1821
16980d0b
JB		 1822 %<bitfield>'c print specified char iff bitfield is all ones
1823 %<bitfield>`c print specified char iff bitfield is all zeroes
1824 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 1825
8f06b2d8
PB		 1826 %e print arm SMI operand (bits 0..7,8..19).
1827 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 1828 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
1829 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 1830
8f06b2d8
PB		 1831static const struct opcode32 arm_opcodes[] =
1832{
1833 /* ARM instructions. */
823d2571
TG		 1834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1835 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1837 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1838
1839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
1840 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1842 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1844 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
1846 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1848 0x00800090, 0x0fa000f0,
1849 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1851 0x00a00090, 0x0fa000f0,
1852 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 1853
105bde57 1854 /* V8.2 RAS extension instructions. */
4d1464f2 1855 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 1856 0xe320f010, 0xffffffff, "esb"},
1857
53c4b28b 1858 /* V8 instructions. */
823d2571
TG		 1859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1860 0x0320f005, 0x0fffffff, "sevl"},
f7dd2fb2
TC		 1861 /* Defined in V8 but is in NOP space so available to all arch. */
1862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
823d2571 1863 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
4ed7ed8d 1864 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 1865 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1866 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 1867 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1869 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1871 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 1872 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1873 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1874 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1875 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1876 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1877 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 1878 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1879 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1880 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1881 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1882 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1883 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1884 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1885 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1886 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1887 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 1888 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 1889 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 1890 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 1891 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 1892 /* CRC32 instructions. */
823d2571
TG		 1893 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1894 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
1895 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1896 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
1897 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1898 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
1899 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1900 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
1901 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1902 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
1903 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1904 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 1905
ddfded2f
MW		 1906 /* Privileged Access Never extension instructions. */
1907 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
1908 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
1909
90ec0d68 1910 /* Virtualization Extension instructions. */
823d2571
TG		 1911 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
1912 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 1913
eea54501 1914 /* Integer Divide Extension instructions. */
823d2571
TG		 1915 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1916 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1917 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1918 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 1919
60e5ef9f 1920 /* MP Extension instructions. */
823d2571 1921 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 1922
c597cc3d
SD		 1923 /* Speculation Barriers. */
1924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
1925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
1926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
1927
62b3e311 1928 /* V7 instructions. */
823d2571
TG		 1929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
1930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
1932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
1933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a
AV		 1936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
1937 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
62b3e311 1938
c19d1205 1939 /* ARM V6T2 instructions. */
823d2571
TG		 1940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1941 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1943 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1945 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1947 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
1948
1949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1950 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
1951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1952 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1953
ff8646ee 1954 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 1955 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 1956 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 1957 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1959 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1961 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 1962
f4c65163 1963 /* ARM Security extension instructions. */
823d2571
TG		 1964 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
1965 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 1966
8f06b2d8 1967 /* ARM V6K instructions. */
823d2571
TG		 1968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1969 0xf57ff01f, 0xffffffff, "clrex"},
1970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1971 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1973 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1975 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1977 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1979 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1981 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 1982
7fadb25d
SD		 1983 /* ARMv8.5-A instructions. */
1984 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
1985
8f06b2d8 1986 /* ARM V6K NOP hints. */
823d2571
TG		 1987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1988 0x0320f001, 0x0fffffff, "yield%c"},
1989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1990 0x0320f002, 0x0fffffff, "wfe%c"},
1991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1992 0x0320f003, 0x0fffffff, "wfi%c"},
1993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1994 0x0320f004, 0x0fffffff, "sev%c"},
1995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1996 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 1997
fe56b6ce 1998 /* ARM V6 instructions. */
823d2571
TG		 1999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2000 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
2001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2002 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
2003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2004 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
2005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2006 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
2007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2008 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
2009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2010 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
2011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2012 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
2013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2014 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
2015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2016 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
2017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2018 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
2019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2020 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
2021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2022 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
2023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2024 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
2025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2026 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
2027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2028 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
2029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2030 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
2031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2032 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
2033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2034 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
2035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2036 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
2037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2038 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
2039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2040 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
2041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2042 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
2043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2044 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
2045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2046 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
2047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2048 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
2049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2050 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
2051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2052 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
2053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2054 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
2055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2056 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
2057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2058 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
2059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2060 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
2061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2062 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
2063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2064 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
2065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2066 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
2067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2068 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
2069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2070 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
2071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2072 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
2073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2074 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
2075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2076 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
2077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2078 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
2079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2080 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
2081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2082 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
2083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2084 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
2085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2086 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
2087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2088 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
2089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2090 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
2091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2092 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
2093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2094 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
2095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2096 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
2097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2098 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
2099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2100 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
2101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2102 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
2103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2104 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
2105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2106 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
2107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2108 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
2109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2110 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
2111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2112 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
2113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2114 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
2115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2116 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
2117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2118 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
2119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2120 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
2121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2122 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
2123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2124 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
2125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2126 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
2127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2128 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
2129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2130 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
2131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2132 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
2133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2134 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
2135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2136 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
2137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2138 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
2139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2140 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
2141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2142 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
2143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2144 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
2145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2146 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
2147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2148 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
2149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2150 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2152 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2154 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2156 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
2157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2158 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2160 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2162 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2164 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
2165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2166 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2168 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2170 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2172 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
2173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2174 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2176 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2178 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2180 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
2181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2182 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2184 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2186 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
2187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2188 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
2189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2190 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2192 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2194 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2196 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
2197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2198 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
2199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2200 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
2201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2202 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
2203 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2204 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2206 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2208 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2210 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2212 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
2213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2214 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2216 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2217 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2218 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
2219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2220 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
2221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2222 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
2223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2224 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
2225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2226 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
2227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2228 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
2229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2230 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
2231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2232 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
2233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2234 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2236 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
2237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2238 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
2239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2240 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
2241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2242 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 2243
8f06b2d8 2244 /* V5J instruction. */
823d2571
TG		 2245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
2246 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 2247
8f06b2d8 2248 /* V5 Instructions. */
823d2571
TG		 2249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2250 0xe1200070, 0xfff000f0,
2251 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
2252 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2253 0xfa000000, 0xfe000000, "blx\t%B"},
2254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2255 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
2256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2257 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
2258
2259 /* V5E "El Segundo" Instructions. */
2260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2261 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
2262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2263 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
2264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2265 0xf450f000, 0xfc70f000, "pld\t%a"},
2266 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2267 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2269 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2271 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2273 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
2274
2275 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2276 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2277 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2278 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
2279
2280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2281 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2282 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2283 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2285 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2287 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2288
2289 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2290 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2292 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2294 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2295 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2296 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2297
2298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2299 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2301 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2302
2303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2304 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
2305 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2306 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2307 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2308 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
2309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2310 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 2311
8f06b2d8 2312 /* ARM Instructions. */
823d2571
TG		 2313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2314 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2315
2316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2317 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2319 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2321 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2323 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2325 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2327 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2328
2329 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2330 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2331 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2332 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2334 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2336 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2337
2338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2339 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2341 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2343 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2345 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2346
2347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2348 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2350 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2352 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2353
2354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2355 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2357 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2359 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2360
2361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2362 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2364 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2366 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2367
2368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2369 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2371 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2373 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2374
2375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2376 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2378 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2380 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2381
2382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2383 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2385 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2387 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2388
2389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2390 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2392 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2394 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2395
2396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2397 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2399 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2401 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2402
2403 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2404 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2406 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2408 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2409
2410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2411 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2413 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2415 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2416
2417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2418 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 2419 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2420 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 2421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 2422 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
823d2571
TG		 2423
2424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2425 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2427 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2429 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2430
2431 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2432 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2433 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2434 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2435 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2436 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2437
2438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2439 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2440 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2441 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2443 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2444
2445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2446 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2447 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2448 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2450 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2451 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2452 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2453 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2454 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2455 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2456 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2457 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2458 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2459
2460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2461 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2463 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2465 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2466
2467 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2468 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2469 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2470 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2471 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2472 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2473
2474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2475 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2476 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2477 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2478
2479 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2480 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2481
2482 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2483 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2485 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2486
2487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2488 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2489 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2490 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2492 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2494 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2495 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2496 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2497 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2498 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2499 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2500 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2501 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2502 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2503 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2504 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2505 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2506 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2507 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2508 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2509 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2510 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2511 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2512 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2513 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2514 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2515 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2516 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2517 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2518 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2519 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2520 0x092d0000, 0x0fff0000, "push%c\t%m"},
2521 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2522 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2523 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2524 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2525
2526 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2527 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2528 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2529 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2531 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2533 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2534 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2535 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2537 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2539 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2541 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2543 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2545 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2547 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2549 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2551 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2553 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2555 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2557 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2559 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2561 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2563 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2564
2565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2566 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2568 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 2569
2570 /* The rest. */
4ab90a7a
AV		 2571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2572 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 2573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2574 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2575 {ARM_FEATURE_CORE_LOW (0),
2576 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 2577};
2578
2579/* print_insn_thumb16 recognizes the following format control codes:
2580
2581 %S print Thumb register (bits 3..5 as high number if bit 6 set)
2582 %D print Thumb register (bits 0..2 as high number if bit 7 set)
2583 %<bitfield>I print bitfield as a signed decimal
2584 (top bit of range being the sign bit)
2585 %N print Thumb register mask (with LR)
2586 %O print Thumb register mask (with PC)
2587 %M print Thumb register mask
2588 %b print CZB's 6-bit unsigned branch destination
2589 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 2590 %c print the condition code
2591 %C print the condition code, or "s" if not conditional
2592 %x print warning if conditional an not at end of IT block"
2593 %X print "\t; unpredictable <IT:code>" if conditional
2594 %I print IT instruction suffix and operands
4547cb56 2595 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 2596 %<bitfield>r print bitfield as an ARM register
2597 %<bitfield>d print bitfield as a decimal
2598 %<bitfield>H print (bitfield * 2) as a decimal
2599 %<bitfield>W print (bitfield * 4) as a decimal
2600 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
2601 %<bitfield>B print Thumb branch destination (signed displacement)
2602 %<bitfield>c print bitfield as a condition code
2603 %<bitnum>'c print specified char iff bit is one
2604 %<bitnum>?ab print a if bit is one else print b. */
2605
2606static const struct opcode16 thumb_opcodes[] =
2607{
2608 /* Thumb instructions. */
2609
16a1fa25
TP		 2610 /* ARMv8-M Security Extensions instructions. */
2611 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
e207bc53 2612 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
16a1fa25 2613
53c4b28b 2614 /* ARM V8 instructions. */
823d2571
TG		 2615 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
2616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
ddfded2f 2617 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
53c4b28b 2618
8f06b2d8 2619 /* ARM V6K no-argument instructions. */
823d2571
TG		 2620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2622 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 2626
2627 /* ARM V6T2 instructions. */
ff8646ee
TP		 2628 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2629 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2630 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2631 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 2632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 2633
2634 /* ARM V6. */
823d2571
TG		 2635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2641 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 2646
2647 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 2648 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2649 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 2650 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 2651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2652 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 2653 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 2654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2655 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 2656 /* Format 4. */
823d2571
TG		 2657 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2658 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2667 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2669 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 2673 /* format 13 */
823d2571
TG		 2674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 2676 /* format 5 */
823d2571
TG		 2677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
2678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
2679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 2681 /* format 14 */
823d2571
TG		 2682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
2683 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 2684 /* format 2 */
823d2571
TG		 2685 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2686 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2687 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2688 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2690 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2692 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 2693 /* format 8 */
823d2571
TG		 2694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2695 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2697 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2699 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2700 /* format 7 */
823d2571
TG		 2701 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2702 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2703 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2704 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 2705 /* format 1 */
823d2571
TG		 2706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2708 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 2711 /* format 3 */
823d2571
TG		 2712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2713 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2715 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 2716 /* format 6 */
823d2571
TG		 2717 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2719 0x4800, 0xF800,
2720 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 2721 /* format 9 */
823d2571
TG		 2722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2723 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2725 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2727 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2729 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 2730 /* format 10 */
823d2571
TG		 2731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2732 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2734 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 2735 /* format 11 */
823d2571
TG		 2736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2737 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2739 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 2740 /* format 12 */
823d2571
TG		 2741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2742 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2744 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 2745 /* format 15 */
823d2571
TG		 2746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 2748 /* format 17 */
823d2571 2749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 2750 /* format 16 */
823d2571
TG		 2751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
2753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 2754 /* format 18 */
823d2571 2755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 2756
2757 /* The E800 .. FFFF range is unconditionally redirected to the
2758 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2759 are processed via that table. Thus, we can never encounter a
2760 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 2761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
2762 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 2763};
2764
2765/* Thumb32 opcodes use the same table structure as the ARM opcodes.
2766 We adopt the convention that hw1 is the high 16 bits of .value and
2767 .mask, hw2 the low 16 bits.
2768
2769 print_insn_thumb32 recognizes the following format control codes:
2770
2771 %% %
2772
2773 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2774 %M print a modified 12-bit immediate (same location)
2775 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2776 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 2777 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 2778 %S print a possibly-shifted Rm
2779
32a94698 2780 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 2781 %a print the address of a plain load/store
2782 %w print the width and signedness of a core load/store
2783 %m print register mask for ldm/stm
4b5a202f 2784 %n print register mask for clrm
8f06b2d8
PB		 2785
2786 %E print the lsb and width fields of a bfc/bfi instruction
2787 %F print the lsb and width fields of a sbfx/ubfx instruction
e12437dc 2788 %G print a fallback offset for Branch Future instructions
e5d6e09e 2789 %W print an offset for BF instruction
1caf72a5 2790 %Y print an offset for BFL instruction
1889da70 2791 %Z print an offset for BFCSEL instruction
60f993ce
AV		 2792 %Q print an offset for Low Overhead Loop instructions
2793 %P print an offset for Low Overhead Loop end instructions
8f06b2d8
PB		 2794 %b print a conditional branch offset
2795 %B print an unconditional branch offset
2796 %s print the shift field of an SSAT instruction
2797 %R print the rotation field of an SXT instruction
62b3e311
PB		 2798 %U print barrier type.
2799 %P print address for pli instruction.
c22aaad1
PB		 2800 %c print the condition code
2801 %x print warning if conditional an not at end of IT block"
2802 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 2803
2804 %<bitfield>d print bitfield in decimal
f0fba320 2805 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 2806 %<bitfield>W print bitfield*4 in decimal
2807 %<bitfield>r print bitfield as an ARM register
dd5181d5 2808 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
f1c7f421 2809 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
8f06b2d8
PB		 2810 %<bitfield>c print bitfield as a condition code
2811
16980d0b
JB		 2812 %<bitfield>'c print specified char iff bitfield is all ones
2813 %<bitfield>`c print specified char iff bitfield is all zeroes
2814 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 2815
2816 With one exception at the bottom (done because BL and BLX(1) need
2817 to come dead last), this table was machine-sorted first in
2818 decreasing order of number of bits set in the mask, then in
2819 increasing numeric order of mask, then in increasing numeric order
2820 of opcode. This order is not the clearest for a human reader, but
2821 is guaranteed never to catch a special-case bit pattern with a more
2822 general mask, which is important, because this instruction encoding
2823 makes heavy use of special-case bit patterns. */
2824static const struct opcode32 thumb32_opcodes[] =
2825{
4b5a202f
AV		 2826 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
2827 instructions. */
60f993ce
AV		 2828 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2829 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
2830 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2831 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
2832 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2833 0xf02fc001, 0xfffff001, "le\t%P"},
2834 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2835 0xf00fc001, 0xfffff001, "le\tlr, %P"},
2836
4389b29a
AV		 2837 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2838 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
f1c7f421
AV		 2839 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2840 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
65d1bc05
AV		 2841 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2842 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
f1c7f421
AV		 2843 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2844 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
f6b2b12d
AV		 2845 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2846 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4389b29a 2847
4b5a202f
AV		 2848 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
2849 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4389b29a 2850
16a1fa25
TP		 2851 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
2852 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4ed7ed8d
TP		 2853 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2854 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
2855 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2856 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
16a1fa25
TP		 2857 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2858 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
2859 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2860 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4ed7ed8d 2861
105bde57 2862 /* ARM V8.2 RAS extension instructions. */
4d1464f2 2863 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 2864 0xf3af8010, 0xffffffff, "esb"},
2865
53c4b28b 2866 /* V8 instructions. */
823d2571
TG		 2867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2868 0xf3af8005, 0xffffffff, "sevl%c.w"},
2869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2870 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2872 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2874 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
2875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2876 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
2877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2878 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
2879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2880 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
2881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2882 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
2883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2884 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
2885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2886 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2888 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2890 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
2891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2892 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2894 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2896 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2898 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 2899
dd5181d5 2900 /* CRC32 instructions. */
823d2571 2901 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2902 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
823d2571 2903 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2904 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
823d2571 2905 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2906 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
823d2571 2907 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2908 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
823d2571 2909 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2910 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
823d2571 2911 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 2912 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
dd5181d5 2913
c597cc3d
SD		 2914 /* Speculation Barriers. */
2915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
2916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
2917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
2918
62b3e311 2919 /* V7 instructions. */
823d2571
TG		 2920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
2921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
2922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
2923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
2924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
2925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
2926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
2927 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2928 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
2929 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2930 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 2931
90ec0d68 2932 /* Virtualization Extension instructions. */
823d2571 2933 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 2934 /* We skip ERET as that is SUBS pc, lr, #0. */
2935
60e5ef9f 2936 /* MP Extension instructions. */
823d2571 2937 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 2938
f4c65163 2939 /* Security extension instructions. */
823d2571 2940 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 2941
7fadb25d
SD		 2942 /* ARMv8.5-A instructions. */
2943 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
2944
8f06b2d8 2945 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 2946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
2947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
2948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
2951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2952 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
2953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
2954
ff8646ee 2955 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2956 0xf3bf8f2f, 0xffffffff, "clrex%c"},
2957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2958 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
2959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2960 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
2961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2962 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
2963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2964 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
2965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2966 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
2967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2968 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
2969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2970 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
2971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2972 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
2973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2974 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
2975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2976 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
2977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2978 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
2979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2980 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
2981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2982 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 2983 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 2984 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 2985 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 2986 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
2987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2988 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
2989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2990 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
2991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2992 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
2993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2994 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
2995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2996 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
2997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2998 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
2999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3000 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
3001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3002 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 3003 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3004 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
3005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3006 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
3007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3008 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
3009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3010 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
3011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3012 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
3013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3014 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
3015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3016 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
3017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3018 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
3019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3020 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
3021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3022 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
3023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3024 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
3025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3026 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
3027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3028 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
3029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3030 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
3031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3032 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
3033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3034 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
3035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3036 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
3037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3038 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
3039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3040 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
3041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3042 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
3043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3044 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
3045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3046 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
3047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3048 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
3049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3050 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
3051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3052 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
3053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3054 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
3055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3056 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
3057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3058 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
3059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3060 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
3061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3062 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
3063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3064 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
3065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3066 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
3067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3068 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
3069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3070 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
3071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3072 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
3073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3074 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
3075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3076 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
3077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3078 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
3079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3080 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
3081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3082 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
3083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3084 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
3085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3086 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
3087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3088 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
3089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3090 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
3091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3092 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
3093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3094 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
3095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3096 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
3097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3098 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
3099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3100 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
3101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3102 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
3103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3104 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3106 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3108 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3110 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 3111 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3112 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
3113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 3114 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 3115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3116 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
3117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3118 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
3119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3120 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3122 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
3123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3124 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
3125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3126 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3128 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3130 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3132 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3134 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3136 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3138 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3140 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
3141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3142 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
3143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3144 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
3145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3146 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
3147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3148 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
3149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3150 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
3151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3152 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
3153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3154 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
3155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3156 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
3157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3158 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
3159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3160 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
3161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3162 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
3163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3164 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3166 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3168 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3170 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3172 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3174 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3176 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3178 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 3179 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3180 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
3181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3182 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
3183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3184 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
3185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3186 0xf810f000, 0xff70f000, "pld%c\t%a"},
3187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3188 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3190 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3192 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3194 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3196 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3198 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3200 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3202 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
3203 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3204 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
3205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3206 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
3207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3208 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
3209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3210 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
3211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3212 0xfb100000, 0xfff000c0,
3213 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3215 0xfbc00080, 0xfff000c0,
3216 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
3217 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3218 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
3219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3220 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
3221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 3222 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 3223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3224 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
3225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3226 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 3227 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3228 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
3229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3230 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 3231 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3232 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
3233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3234 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
3235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3236 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
3237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3238 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
3239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3240 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
3241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3242 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
3243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3244 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
3245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3246 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
3247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3248 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
3249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3250 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
3251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3252 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 3253 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3254 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
3255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3256 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
3257 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3258 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
3259 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3260 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
3261 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3262 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
3263 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3264 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
3265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3266 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
3267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3268 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
3269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3270 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
3271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3272 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
3273 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3274 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
3275 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3276 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
3277 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3278 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
3279 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3280 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
3281 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3282 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
3283 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3284 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
3285 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3286 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
3287 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3288 0xe9400000, 0xff500000,
3289 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3291 0xe9500000, 0xff500000,
3292 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3294 0xe8600000, 0xff700000,
3295 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3297 0xe8700000, 0xff700000,
3298 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3299 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3300 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
3301 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3302 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 3303
3304 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 3305 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3306 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
3307 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3308 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
3309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3310 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
3311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3312 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 3313
8f06b2d8 3314 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 3315 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3316 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
3317 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3318 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 3319
3320 /* Fallback. */
823d2571
TG		 3321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3322 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3323 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 3324};
ff4a8d2b 3325
8f06b2d8
PB		 3326static const char *const arm_conditional[] =
3327{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 3328 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 3329
3330static const char *const arm_fp_const[] =
3331{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3332
3333static const char *const arm_shift[] =
3334{"lsl", "lsr", "asr", "ror"};
3335
3336typedef struct
3337{
3338 const char *name;
3339 const char *description;
3340 const char *reg_names[16];
3341}
3342arm_regname;
3343
3344static const arm_regname regnames[] =
3345{
65b48a81 3346 { "reg-names-raw", N_("Select raw register names"),
8f06b2d8 3347 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
65b48a81 3348 { "reg-names-gcc", N_("Select register names used by GCC"),
8f06b2d8 3349 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 3350 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
8f06b2d8 3351 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65b48a81
PB		 3352 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
3353 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
3354 { "reg-names-apcs", N_("Select register names used in the APCS"),
8f06b2d8 3355 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 3356 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
8f06b2d8 3357 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
65b48a81
PB		 3358 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
3359 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
8f06b2d8
PB		 3360};
3361
3362static const char *const iwmmxt_wwnames[] =
3363{"b", "h", "w", "d"};
3364
3365static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 3366{"b", "bus", "bc", "bss",
3367 "h", "hus", "hc", "hss",
3368 "w", "wus", "wc", "wss",
3369 "d", "dus", "dc", "dss"
8f06b2d8
PB		 3370};
3371
3372static const char *const iwmmxt_regnames[] =
3373{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3374 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3375};
3376
3377static const char *const iwmmxt_cregnames[] =
3378{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3379 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3380};
3381
3382/* Default to GCC register name set. */
3383static unsigned int regname_selected = 1;
3384
65b48a81 3385#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
8f06b2d8
PB		 3386#define arm_regnames regnames[regname_selected].reg_names
3387
3388static bfd_boolean force_thumb = FALSE;
3389
c22aaad1
PB		 3390/* Current IT instruction state. This contains the same state as the IT
3391 bits in the CPSR. */
3392static unsigned int ifthen_state;
3393/* IT state for the next instruction. */
3394static unsigned int ifthen_next_state;
3395/* The address of the insn for which the IT state is valid. */
3396static bfd_vma ifthen_address;
3397#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 3398/* Indicates that the current Conditional state is unconditional or outside
3399 an IT block. */
3400#define COND_UNCOND 16
c22aaad1 3401
8f06b2d8
PB		 3402\f
3403/* Functions. */
8f06b2d8 3404
16980d0b
JB		 3405/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3406 Returns pointer to following character of the format string and
3407 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 3408 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 3409
3410static const char *
fe56b6ce
NC		 3411arm_decode_bitfield (const char *ptr,
3412 unsigned long insn,
3413 unsigned long *valuep,
3414 int *widthp)
16980d0b
JB		 3415{
3416 unsigned long value = 0;
3417 int width = 0;
43e65147
L		 3418
3419 do
16980d0b
JB		 3420 {
3421 int start, end;
3422 int bits;
3423
3424 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3425 start = start * 10 + *ptr - '0';
3426 if (*ptr == '-')
3427 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3428 end = end * 10 + *ptr - '0';
3429 else
3430 end = start;
3431 bits = end - start;
3432 if (bits < 0)
3433 abort ();
3434 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3435 width += bits + 1;
3436 }
3437 while (*ptr++ == ',');
3438 *valuep = value;
3439 if (widthp)
3440 *widthp = width;
3441 return ptr - 1;
3442}
3443
8f06b2d8 3444static void
37b37b2d 3445arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 3446 bfd_boolean print_shift)
8f06b2d8
PB		 3447{
3448 func (stream, "%s", arm_regnames[given & 0xf]);
3449
3450 if ((given & 0xff0) != 0)
3451 {
3452 if ((given & 0x10) == 0)
3453 {
3454 int amount = (given & 0xf80) >> 7;
3455 int shift = (given & 0x60) >> 5;
3456
3457 if (amount == 0)
3458 {
3459 if (shift == 3)
3460 {
3461 func (stream, ", rrx");
3462 return;
3463 }
3464
3465 amount = 32;
3466 }
3467
37b37b2d
RE		 3468 if (print_shift)
3469 func (stream, ", %s #%d", arm_shift[shift], amount);
3470 else
3471 func (stream, ", #%d", amount);
8f06b2d8 3472 }
74bdfecf 3473 else if ((given & 0x80) == 0x80)
aefd8a40 3474 func (stream, "\t; <illegal shifter operand>");
37b37b2d 3475 else if (print_shift)
8f06b2d8
PB		 3476 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3477 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 3478 else
3479 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 3480 }
3481}
3482
73cd51e5
AV		 3483/* Return TRUE if the MATCHED_INSN can be inside an IT block. */
3484
3485static bfd_boolean
3486is_mve_okay_in_it (enum mve_instructions matched_insn)
3487{
3488 return FALSE;
3489}
3490
3491static bfd_boolean
3492is_mve_architecture (struct disassemble_info *info)
3493{
3494 struct arm_private_data *private_data = info->private_data;
3495 arm_feature_set allowed_arches = private_data->features;
3496
3497 arm_feature_set arm_ext_v8_1m_main
3498 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
3499
3500 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
3501 && !ARM_CPU_IS_ANY (allowed_arches))
3502 return TRUE;
3503 else
3504 return FALSE;
3505}
3506
3507/* Decode a bitfield from opcode GIVEN, with starting bitfield = START
3508 and ending bitfield = END. END must be greater than START. */
3509
3510static unsigned long
3511arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
3512{
3513 int bits = end - start;
3514
3515 if (bits < 0)
3516 abort ();
3517
3518 return ((given >> start) & ((2ul << bits) - 1));
3519}
3520
3521/* Decode a bitfield from opcode GIVEN, with multiple bitfields:
3522 START:END and START2:END2. END/END2 must be greater than
3523 START/START2. */
3524
3525static unsigned long
3526arm_decode_field_multiple (unsigned long given, unsigned int start,
3527 unsigned int end, unsigned int start2,
3528 unsigned int end2)
3529{
3530 int bits = end - start;
3531 int bits2 = end2 - start2;
3532 unsigned long value = 0;
3533 int width = 0;
3534
3535 if (bits2 < 0)
3536 abort ();
3537
3538 value = arm_decode_field (given, start, end);
3539 width += bits + 1;
3540
3541 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
3542 return value;
3543}
3544
3545/* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
3546 This helps us decode instructions that change mnemonic depending on specific
3547 operand values/encodings. */
3548
3549static bfd_boolean
3550is_mve_encoding_conflict (unsigned long given,
3551 enum mve_instructions matched_insn)
3552{
3553 return FALSE;
3554}
3555
3556/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
3557 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
3558 this encoding is undefined. */
3559
3560static bfd_boolean
3561is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
3562 enum mve_undefined *undefined_code)
3563{
3564 *undefined_code = UNDEF_NONE;
3565
3566 return FALSE;
3567}
3568
3569/* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
3570 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
3571 why this encoding is unpredictable. */
3572
3573static bfd_boolean
3574is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
3575 enum mve_unpredictable *unpredictable_code)
3576{
3577 *unpredictable_code = UNPRED_NONE;
3578
3579 return FALSE;
3580}
3581
c1e26897
NC		 3582#define W_BIT 21
3583#define I_BIT 22
3584#define U_BIT 23
3585#define P_BIT 24
3586
3587#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
3588#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
3589#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
3590#define PRE_BIT_SET (given & (1 << P_BIT))
3591
73cd51e5
AV		 3592static void
3593print_mve_undefined (struct disassemble_info *info,
3594 enum mve_undefined undefined_code)
3595{
3596 void *stream = info->stream;
3597 fprintf_ftype func = info->fprintf_func;
3598
3599 func (stream, "\t\tundefined instruction: ");
3600
3601 switch (undefined_code)
3602 {
3603 case UNDEF_NONE:
3604 break;
3605 }
3606
3607}
3608
3609static void
3610print_mve_unpredictable (struct disassemble_info *info,
3611 enum mve_unpredictable unpredict_code)
3612{
3613 void *stream = info->stream;
3614 fprintf_ftype func = info->fprintf_func;
3615
3616 func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
3617
3618 switch (unpredict_code)
3619 {
3620 case UNPRED_IT_BLOCK:
3621 func (stream, "mve instruction in it block");
3622 break;
3623
3624 case UNPRED_NONE:
3625 break;
3626 }
3627}
3628
8f06b2d8
PB		 3629/* Print one coprocessor instruction on INFO->STREAM.
3630 Return TRUE if the instuction matched, FALSE if this is not a
3631 recognised coprocessor instruction. */
3632
3633static bfd_boolean
fe56b6ce
NC		 3634print_insn_coprocessor (bfd_vma pc,
3635 struct disassemble_info *info,
3636 long given,
8f06b2d8
PB		 3637 bfd_boolean thumb)
3638{
6b0dd094 3639 const struct sopcode32 *insn;
8f06b2d8
PB		 3640 void *stream = info->stream;
3641 fprintf_ftype func = info->fprintf_func;
3642 unsigned long mask;
2edcd244 3643 unsigned long value = 0;
c22aaad1 3644 int cond;
8afc7bea 3645 int cp_num;
823d2571
TG		 3646 struct arm_private_data *private_data = info->private_data;
3647 arm_feature_set allowed_arches = ARM_ARCH_NONE;
32c36c3c
AV		 3648 arm_feature_set arm_ext_v8_1m_main =
3649 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
823d2571 3650
5b616bef 3651 allowed_arches = private_data->features;
8f06b2d8
PB		 3652
3653 for (insn = coprocessor_opcodes; insn->assembler; insn++)
3654 {
ff4a8d2b
NC		 3655 unsigned long u_reg = 16;
3656 bfd_boolean is_unpredictable = FALSE;
05413229 3657 signed long value_in_comment = 0;
0313a2b8
NC		 3658 const char *c;
3659
823d2571 3660 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 3661 switch (insn->value)
3662 {
3663 case SENTINEL_IWMMXT_START:
3664 if (info->mach != bfd_mach_arm_XScale
3665 && info->mach != bfd_mach_arm_iWMMXt
3666 && info->mach != bfd_mach_arm_iWMMXt2)
3667 do
3668 insn++;
823d2571
TG		 3669 while ((! ARM_FEATURE_ZERO (insn->arch))
3670 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 3671 continue;
3672
3673 case SENTINEL_IWMMXT_END:
3674 continue;
3675
3676 case SENTINEL_GENERIC_START:
5b616bef 3677 allowed_arches = private_data->features;
05413229
NC		 3678 continue;
3679
3680 default:
3681 abort ();
3682 }
8f06b2d8
PB		 3683
3684 mask = insn->mask;
3685 value = insn->value;
8afc7bea
RL		 3686 cp_num = (given >> 8) & 0xf;
3687
8f06b2d8
PB		 3688 if (thumb)
3689 {
3690 /* The high 4 bits are 0xe for Arm conditional instructions, and
3691 0xe for arm unconditional instructions. The rest of the
3692 encoding is the same. */
3693 mask |= 0xf0000000;
3694 value |= 0xe0000000;
c22aaad1
PB		 3695 if (ifthen_state)
3696 cond = IFTHEN_COND;
3697 else
e2efe87d 3698 cond = COND_UNCOND;
8f06b2d8
PB		 3699 }
3700 else
3701 {
3702 /* Only match unconditional instuctions against unconditional
3703 patterns. */
3704 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 3705 {
3706 mask |= 0xf0000000;
e2efe87d 3707 cond = COND_UNCOND;
c22aaad1
PB		 3708 }
3709 else
3710 {
3711 cond = (given >> 28) & 0xf;
3712 if (cond == 0xe)
e2efe87d 3713 cond = COND_UNCOND;
c22aaad1 3714 }
8f06b2d8 3715 }
823d2571 3716
6b0dd094
AV		 3717 if ((insn->isa == T32 && !thumb)
3718 || (insn->isa == ARM && thumb))
3719 continue;
3720
0313a2b8
NC		 3721 if ((given & mask) != value)
3722 continue;
8f06b2d8 3723
823d2571 3724 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 3725 continue;
3726
8afc7bea
RL		 3727 if (insn->value == 0xfe000010 /* mcr2 */
3728 || insn->value == 0xfe100010 /* mrc2 */
3729 || insn->value == 0xfc100000 /* ldc2 */
3730 || insn->value == 0xfc000000) /* stc2 */
3731 {
b0c11777 3732 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 3733 is_unpredictable = TRUE;
f08d8ce3
AV		 3734
3735 /* Armv8.1-M Mainline FP & MVE instructions. */
3736 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
3737 && !ARM_CPU_IS_ANY (allowed_arches)
3738 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
3739 continue;
3740
8afc7bea
RL		 3741 }
3742 else if (insn->value == 0x0e000000 /* cdp */
3743 || insn->value == 0xfe000000 /* cdp2 */
3744 || insn->value == 0x0e000010 /* mcr */
3745 || insn->value == 0x0e100010 /* mrc */
3746 || insn->value == 0x0c100000 /* ldc */
3747 || insn->value == 0x0c000000) /* stc */
3748 {
3749 /* Floating-point instructions. */
b0c11777 3750 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 3751 continue;
32c36c3c
AV		 3752
3753 /* Armv8.1-M Mainline FP & MVE instructions. */
3754 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
3755 && !ARM_CPU_IS_ANY (allowed_arches)
3756 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
3757 continue;
8afc7bea
RL		 3758 }
3759
0313a2b8
NC		 3760 for (c = insn->assembler; *c; c++)
3761 {
3762 if (*c == '%')
8f06b2d8 3763 {
32c36c3c
AV		 3764 const char mod = *++c;
3765 switch (mod)
8f06b2d8 3766 {
0313a2b8
NC		 3767 case '%':
3768 func (stream, "%%");
3769 break;
3770
3771 case 'A':
32c36c3c 3772 case 'K':
05413229 3773 {
79862e45 3774 int rn = (given >> 16) & 0xf;
b0c11777 3775 bfd_vma offset = given & 0xff;
0313a2b8 3776
32c36c3c
AV		 3777 if (mod == 'K')
3778 offset = given & 0x7f;
3779
05413229 3780 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 3781
79862e45
DJ		 3782 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
3783 {
3784 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 3785 if (cp_num == 9)
3786 /* vldr.16/vstr.16 will shift the address
3787 left by 1 bit only. */
3788 offset = offset * 2;
3789 else
3790 offset = offset * 4;
3791
79862e45
DJ		 3792 if (NEGATIVE_BIT_SET)
3793 offset = - offset;
3794 if (rn != 15)
3795 value_in_comment = offset;
3796 }
3797
c1e26897 3798 if (PRE_BIT_SET)
05413229
NC		 3799 {
3800 if (offset)
fe56b6ce 3801 func (stream, ", #%d]%s",
d908c8af 3802 (int) offset,
c1e26897 3803 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 3804 else if (NEGATIVE_BIT_SET)
3805 func (stream, ", #-0]");
05413229
NC		 3806 else
3807 func (stream, "]");
3808 }
3809 else
3810 {
0313a2b8 3811 func (stream, "]");
8f06b2d8 3812
c1e26897 3813 if (WRITEBACK_BIT_SET)
05413229
NC		 3814 {
3815 if (offset)
d908c8af 3816 func (stream, ", #%d", (int) offset);
26d97720
NS		 3817 else if (NEGATIVE_BIT_SET)
3818 func (stream, ", #-0");
05413229
NC		 3819 }
3820 else
fe56b6ce 3821 {
26d97720
NS		 3822 func (stream, ", {%s%d}",
3823 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 3824 (int) offset);
fe56b6ce
NC		 3825 value_in_comment = offset;
3826 }
05413229 3827 }
79862e45
DJ		 3828 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
3829 {
3830 func (stream, "\t; ");
6844b2c2
MGD		 3831 /* For unaligned PCs, apply off-by-alignment
3832 correction. */
43e65147 3833 info->print_address_func (offset + pc
6844b2c2
MGD		 3834 + info->bytes_per_chunk * 2
3835 - (pc & 3),
dffaa15c 3836 info);
79862e45 3837 }
05413229 3838 }
0313a2b8 3839 break;
8f06b2d8 3840
0313a2b8
NC		 3841 case 'B':
3842 {
3843 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
3844 int offset = (given >> 1) & 0x3f;
3845
3846 if (offset == 1)
3847 func (stream, "{d%d}", regno);
3848 else if (regno + offset > 32)
3849 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
3850 else
3851 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
3852 }
3853 break;
8f06b2d8 3854
efd6b359
AV		 3855 case 'C':
3856 {
3857 bfd_boolean single = ((given >> 8) & 1) == 0;
3858 char reg_prefix = single ? 's' : 'd';
3859 int Dreg = (given >> 22) & 0x1;
3860 int Vdreg = (given >> 12) & 0xf;
3861 int reg = single ? ((Vdreg << 1) | Dreg)
3862 : ((Dreg << 4) | Vdreg);
3863 int num = (given >> (single ? 0 : 1)) & 0x7f;
3864 int maxreg = single ? 31 : 15;
3865 int topreg = reg + num - 1;
3866
3867 if (!num)
3868 func (stream, "{VPR}");
3869 else if (num == 1)
3870 func (stream, "{%c%d, VPR}", reg_prefix, reg);
3871 else if (topreg > maxreg)
3872 func (stream, "{%c%d-<overflow reg d%d, VPR}",
3873 reg_prefix, reg, single ? topreg >> 1 : topreg);
3874 else
3875 func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
3876 reg_prefix, topreg);
3877 }
3878 break;
3879
e2efe87d
MGD		 3880 case 'u':
3881 if (cond != COND_UNCOND)
3882 is_unpredictable = TRUE;
3883
3884 /* Fall through. */
0313a2b8 3885 case 'c':
b0c11777
RL		 3886 if (cond != COND_UNCOND && cp_num == 9)
3887 is_unpredictable = TRUE;
3888
0313a2b8
NC		 3889 func (stream, "%s", arm_conditional[cond]);
3890 break;
8f06b2d8 3891
0313a2b8
NC		 3892 case 'I':
3893 /* Print a Cirrus/DSP shift immediate. */
3894 /* Immediates are 7bit signed ints with bits 0..3 in
3895 bits 0..3 of opcode and bits 4..6 in bits 5..7
3896 of opcode. */
3897 {
3898 int imm;
8f06b2d8 3899
0313a2b8 3900 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 3901
0313a2b8
NC		 3902 /* Is ``imm'' a negative number? */
3903 if (imm & 0x40)
24b4cf66 3904 imm -= 0x80;
8f06b2d8 3905
0313a2b8
NC		 3906 func (stream, "%d", imm);
3907 }
3908
3909 break;
8f06b2d8 3910
32c36c3c
AV		 3911 case 'J':
3912 {
73cd51e5
AV		 3913 unsigned long regno
3914 = arm_decode_field_multiple (given, 13, 15, 22, 22);
32c36c3c
AV		 3915
3916 switch (regno)
3917 {
3918 case 0x1:
3919 func (stream, "FPSCR");
3920 break;
3921 case 0x2:
3922 func (stream, "FPSCR_nzcvqc");
3923 break;
3924 case 0xc:
3925 func (stream, "VPR");
3926 break;
3927 case 0xd:
3928 func (stream, "P0");
3929 break;
3930 case 0xe:
3931 func (stream, "FPCXTNS");
3932 break;
3933 case 0xf:
3934 func (stream, "FPCXTS");
3935 break;
3936 default:
73cd51e5 3937 func (stream, "<invalid reg %lu>", regno);
32c36c3c
AV		 3938 break;
3939 }
3940 }
3941 break;
3942
0313a2b8
NC		 3943 case 'F':
3944 switch (given & 0x00408000)
3945 {
3946 case 0:
3947 func (stream, "4");
3948 break;
3949 case 0x8000:
3950 func (stream, "1");
3951 break;
3952 case 0x00400000:
3953 func (stream, "2");
8f06b2d8 3954 break;
0313a2b8
NC		 3955 default:
3956 func (stream, "3");
3957 }
3958 break;
8f06b2d8 3959
0313a2b8
NC		 3960 case 'P':
3961 switch (given & 0x00080080)
3962 {
3963 case 0:
3964 func (stream, "s");
3965 break;
3966 case 0x80:
3967 func (stream, "d");
3968 break;
3969 case 0x00080000:
3970 func (stream, "e");
3971 break;
3972 default:
3973 func (stream, _("<illegal precision>"));
8f06b2d8 3974 break;
0313a2b8
NC		 3975 }
3976 break;
8f06b2d8 3977
0313a2b8
NC		 3978 case 'Q':
3979 switch (given & 0x00408000)
3980 {
3981 case 0:
3982 func (stream, "s");
8f06b2d8 3983 break;
0313a2b8
NC		 3984 case 0x8000:
3985 func (stream, "d");
8f06b2d8 3986 break;
0313a2b8
NC		 3987 case 0x00400000:
3988 func (stream, "e");
3989 break;
3990 default:
3991 func (stream, "p");
8f06b2d8 3992 break;
0313a2b8
NC		 3993 }
3994 break;
8f06b2d8 3995
0313a2b8
NC		 3996 case 'R':
3997 switch (given & 0x60)
3998 {
3999 case 0:
4000 break;
4001 case 0x20:
4002 func (stream, "p");
4003 break;
4004 case 0x40:
4005 func (stream, "m");
4006 break;
4007 default:
4008 func (stream, "z");
4009 break;
4010 }
4011 break;
16980d0b 4012
0313a2b8
NC		 4013 case '0': case '1': case '2': case '3': case '4':
4014 case '5': case '6': case '7': case '8': case '9':
4015 {
4016 int width;
8f06b2d8 4017
0313a2b8 4018 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 4019
0313a2b8
NC		 4020 switch (*c)
4021 {
ff4a8d2b
NC		 4022 case 'R':
4023 if (value == 15)
4024 is_unpredictable = TRUE;
4025 /* Fall through. */
0313a2b8 4026 case 'r':
ff4a8d2b
NC		 4027 if (c[1] == 'u')
4028 {
4029 /* Eat the 'u' character. */
4030 ++ c;
4031
4032 if (u_reg == value)
4033 is_unpredictable = TRUE;
4034 u_reg = value;
4035 }
0313a2b8
NC		 4036 func (stream, "%s", arm_regnames[value]);
4037 break;
c28eeff2
SN		 4038 case 'V':
4039 if (given & (1 << 6))
4040 goto Q;
4041 /* FALLTHROUGH */
0313a2b8
NC		 4042 case 'D':
4043 func (stream, "d%ld", value);
4044 break;
4045 case 'Q':
c28eeff2 4046 Q:
0313a2b8
NC		 4047 if (value & 1)
4048 func (stream, "<illegal reg q%ld.5>", value >> 1);
4049 else
4050 func (stream, "q%ld", value >> 1);
4051 break;
4052 case 'd':
4053 func (stream, "%ld", value);
05413229 4054 value_in_comment = value;
0313a2b8 4055 break;
6f1c2142
AM		 4056 case 'E':
4057 {
4058 /* Converts immediate 8 bit back to float value. */
4059 unsigned floatVal = (value & 0x80) << 24
4060 | (value & 0x3F) << 19
4061 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
4062
4063 /* Quarter float have a maximum value of 31.0.
4064 Get floating point value multiplied by 1e7.
4065 The maximum value stays in limit of a 32-bit int. */
4066 unsigned decVal =
4067 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
4068 (16 + (value & 0xF));
4069
4070 if (!(decVal % 1000000))
4071 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
4072 floatVal, value & 0x80 ? '-' : ' ',
4073 decVal / 10000000,
4074 decVal % 10000000 / 1000000);
4075 else if (!(decVal % 10000))
4076 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
4077 floatVal, value & 0x80 ? '-' : ' ',
4078 decVal / 10000000,
4079 decVal % 10000000 / 10000);
4080 else
4081 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
4082 floatVal, value & 0x80 ? '-' : ' ',
4083 decVal / 10000000, decVal % 10000000);
4084 break;
4085 }
0313a2b8
NC		 4086 case 'k':
4087 {
4088 int from = (given & (1 << 7)) ? 32 : 16;
4089 func (stream, "%ld", from - value);
4090 }
4091 break;
8f06b2d8 4092
0313a2b8
NC		 4093 case 'f':
4094 if (value > 7)
4095 func (stream, "#%s", arm_fp_const[value & 7]);
4096 else
4097 func (stream, "f%ld", value);
4098 break;
4146fd53 4099
0313a2b8
NC		 4100 case 'w':
4101 if (width == 2)
4102 func (stream, "%s", iwmmxt_wwnames[value]);
4103 else
4104 func (stream, "%s", iwmmxt_wwssnames[value]);
4105 break;
4146fd53 4106
0313a2b8
NC		 4107 case 'g':
4108 func (stream, "%s", iwmmxt_regnames[value]);
4109 break;
4110 case 'G':
4111 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 4112 break;
8f06b2d8 4113
0313a2b8 4114 case 'x':
d1aaab3c 4115 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 4116 break;
8f06b2d8 4117
33399f07
MGD		 4118 case 'c':
4119 switch (value)
4120 {
4121 case 0:
4122 func (stream, "eq");
4123 break;
4124
4125 case 1:
4126 func (stream, "vs");
4127 break;
4128
4129 case 2:
4130 func (stream, "ge");
4131 break;
4132
4133 case 3:
4134 func (stream, "gt");
4135 break;
4136
4137 default:
4138 func (stream, "??");
4139 break;
4140 }
4141 break;
4142
0313a2b8
NC		 4143 case '`':
4144 c++;
4145 if (value == 0)
4146 func (stream, "%c", *c);
4147 break;
4148 case '\'':
4149 c++;
4150 if (value == ((1ul << width) - 1))
4151 func (stream, "%c", *c);
4152 break;
4153 case '?':
fe56b6ce 4154 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 4155 c += 1 << width;
4156 break;
4157 default:
4158 abort ();
4159 }
dffaa15c
AM		 4160 }
4161 break;
0313a2b8 4162
dffaa15c
AM		 4163 case 'y':
4164 case 'z':
4165 {
4166 int single = *c++ == 'y';
4167 int regno;
8f06b2d8 4168
dffaa15c
AM		 4169 switch (*c)
4170 {
4171 case '4': /* Sm pair */
4172 case '0': /* Sm, Dm */
4173 regno = given & 0x0000000f;
4174 if (single)
4175 {
4176 regno <<= 1;
4177 regno += (given >> 5) & 1;
4178 }
4179 else
4180 regno += ((given >> 5) & 1) << 4;
4181 break;
8f06b2d8 4182
dffaa15c
AM		 4183 case '1': /* Sd, Dd */
4184 regno = (given >> 12) & 0x0000000f;
4185 if (single)
4186 {
4187 regno <<= 1;
4188 regno += (given >> 22) & 1;
4189 }
4190 else
4191 regno += ((given >> 22) & 1) << 4;
4192 break;
7df76b80 4193
dffaa15c
AM		 4194 case '2': /* Sn, Dn */
4195 regno = (given >> 16) & 0x0000000f;
4196 if (single)
4197 {
4198 regno <<= 1;
4199 regno += (given >> 7) & 1;
4200 }
4201 else
4202 regno += ((given >> 7) & 1) << 4;
4203 break;
a7f8487e 4204
dffaa15c
AM		 4205 case '3': /* List */
4206 func (stream, "{");
4207 regno = (given >> 12) & 0x0000000f;
4208 if (single)
4209 {
4210 regno <<= 1;
4211 regno += (given >> 22) & 1;
4212 }
4213 else
4214 regno += ((given >> 22) & 1) << 4;
4215 break;
a7f8487e 4216
dffaa15c
AM		 4217 default:
4218 abort ();
4219 }
0313a2b8 4220
dffaa15c 4221 func (stream, "%c%d", single ? 's' : 'd', regno);
a7f8487e 4222
dffaa15c
AM		 4223 if (*c == '3')
4224 {
4225 int count = given & 0xff;
b34976b6 4226
dffaa15c
AM		 4227 if (single == 0)
4228 count >>= 1;
0313a2b8 4229
dffaa15c
AM		 4230 if (--count)
4231 {
4232 func (stream, "-%c%d",
4233 single ? 's' : 'd',
4234 regno + count);
4235 }
0313a2b8 4236
dffaa15c 4237 func (stream, "}");
0313a2b8 4238 }
dffaa15c
AM		 4239 else if (*c == '4')
4240 func (stream, ", %c%d", single ? 's' : 'd',
4241 regno + 1);
4242 }
4243 break;
b34976b6 4244
dffaa15c
AM		 4245 case 'L':
4246 switch (given & 0x00400100)
0313a2b8 4247 {
dffaa15c
AM		 4248 case 0x00000000: func (stream, "b"); break;
4249 case 0x00400000: func (stream, "h"); break;
4250 case 0x00000100: func (stream, "w"); break;
4251 case 0x00400100: func (stream, "d"); break;
4252 default:
4253 break;
0313a2b8 4254 }
dffaa15c 4255 break;
2d447fca 4256
dffaa15c
AM		 4257 case 'Z':
4258 {
4259 /* given (20, 23) | given (0, 3) */
4260 value = ((given >> 16) & 0xf0) | (given & 0xf);
4261 func (stream, "%d", (int) value);
4262 }
4263 break;
0313a2b8 4264
dffaa15c
AM		 4265 case 'l':
4266 /* This is like the 'A' operator, except that if
4267 the width field "M" is zero, then the offset is
4268 *not* multiplied by four. */
4269 {
4270 int offset = given & 0xff;
4271 int multiplier = (given & 0x00000100) ? 4 : 1;
0313a2b8 4272
dffaa15c 4273 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
05413229 4274
dffaa15c
AM		 4275 if (multiplier > 1)
4276 {
4277 value_in_comment = offset * multiplier;
4278 if (NEGATIVE_BIT_SET)
4279 value_in_comment = - value_in_comment;
4280 }
0313a2b8 4281
dffaa15c
AM		 4282 if (offset)
4283 {
4284 if (PRE_BIT_SET)
4285 func (stream, ", #%s%d]%s",
4286 NEGATIVE_BIT_SET ? "-" : "",
4287 offset * multiplier,
4288 WRITEBACK_BIT_SET ? "!" : "");
4289 else
4290 func (stream, "], #%s%d",
4291 NEGATIVE_BIT_SET ? "-" : "",
4292 offset * multiplier);
4293 }
4294 else
4295 func (stream, "]");
4296 }
4297 break;
2d447fca 4298
dffaa15c
AM		 4299 case 'r':
4300 {
4301 int imm4 = (given >> 4) & 0xf;
4302 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
4303 int ubit = ! NEGATIVE_BIT_SET;
4304 const char *rm = arm_regnames [given & 0xf];
4305 const char *rn = arm_regnames [(given >> 16) & 0xf];
0313a2b8 4306
dffaa15c
AM		 4307 switch (puw_bits)
4308 {
4309 case 1:
4310 case 3:
4311 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
4312 if (imm4)
4313 func (stream, ", lsl #%d", imm4);
4314 break;
0313a2b8 4315
dffaa15c
AM		 4316 case 4:
4317 case 5:
4318 case 6:
4319 case 7:
4320 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
4321 if (imm4 > 0)
4322 func (stream, ", lsl #%d", imm4);
4323 func (stream, "]");
4324 if (puw_bits == 5 || puw_bits == 7)
4325 func (stream, "!");
4326 break;
2d447fca 4327
dffaa15c
AM		 4328 default:
4329 func (stream, "INVALID");
4330 }
4331 }
4332 break;
0313a2b8 4333
dffaa15c
AM		 4334 case 'i':
4335 {
4336 long imm5;
4337 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
4338 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
0313a2b8 4339 }
dffaa15c
AM		 4340 break;
4341
4342 default:
4343 abort ();
252b5132 4344 }
252b5132 4345 }
0313a2b8
NC		 4346 else
4347 func (stream, "%c", *c);
252b5132 4348 }
05413229
NC		 4349
4350 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 4351 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 4352
ff4a8d2b
NC		 4353 if (is_unpredictable)
4354 func (stream, UNPREDICTABLE_INSTRUCTION);
4355
0313a2b8 4356 return TRUE;
252b5132 4357 }
8f06b2d8 4358 return FALSE;
252b5132
RH		 4359}
4360
05413229
NC		 4361/* Decodes and prints ARM addressing modes. Returns the offset
4362 used in the address, if any, if it is worthwhile printing the
4363 offset as a hexadecimal value in a comment at the end of the
4364 line of disassembly. */
4365
4366static signed long
62b3e311
PB		 4367print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
4368{
4369 void *stream = info->stream;
4370 fprintf_ftype func = info->fprintf_func;
f8b960bc 4371 bfd_vma offset = 0;
62b3e311
PB		 4372
4373 if (((given & 0x000f0000) == 0x000f0000)
4374 && ((given & 0x02000000) == 0))
4375 {
05413229 4376 offset = given & 0xfff;
62b3e311
PB		 4377
4378 func (stream, "[pc");
4379
c1e26897 4380 if (PRE_BIT_SET)
62b3e311 4381 {
26d97720
NS		 4382 /* Pre-indexed. Elide offset of positive zero when
4383 non-writeback. */
4384 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 4385 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 4386
4387 if (NEGATIVE_BIT_SET)
4388 offset = -offset;
62b3e311
PB		 4389
4390 offset += pc + 8;
4391
4392 /* Cope with the possibility of write-back
4393 being used. Probably a very dangerous thing
4394 for the programmer to do, but who are we to
4395 argue ? */
26d97720 4396 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 4397 }
c1e26897 4398 else /* Post indexed. */
62b3e311 4399 {
d908c8af 4400 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 4401
c1e26897 4402 /* Ie ignore the offset. */
62b3e311
PB		 4403 offset = pc + 8;
4404 }
4405
4406 func (stream, "\t; ");
4407 info->print_address_func (offset, info);
05413229 4408 offset = 0;
62b3e311
PB		 4409 }
4410 else
4411 {
4412 func (stream, "[%s",
4413 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 4414
4415 if (PRE_BIT_SET)
62b3e311
PB		 4416 {
4417 if ((given & 0x02000000) == 0)
4418 {
26d97720 4419 /* Elide offset of positive zero when non-writeback. */
05413229 4420 offset = given & 0xfff;
26d97720 4421 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 4422 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 4423 }
4424 else
4425 {
26d97720 4426 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 4427 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 4428 }
4429
4430 func (stream, "]%s",
c1e26897 4431 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 4432 }
4433 else
4434 {
4435 if ((given & 0x02000000) == 0)
4436 {
26d97720 4437 /* Always show offset. */
05413229 4438 offset = given & 0xfff;
26d97720 4439 func (stream, "], #%s%d",
d908c8af 4440 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 4441 }
4442 else
4443 {
4444 func (stream, "], %s",
c1e26897 4445 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 4446 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 4447 }
4448 }
84919466
MR		 4449 if (NEGATIVE_BIT_SET)
4450 offset = -offset;
62b3e311 4451 }
05413229
NC		 4452
4453 return (signed long) offset;
62b3e311
PB		 4454}
4455
16980d0b
JB		 4456/* Print one neon instruction on INFO->STREAM.
4457 Return TRUE if the instuction matched, FALSE if this is not a
4458 recognised neon instruction. */
4459
4460static bfd_boolean
4461print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
4462{
4463 const struct opcode32 *insn;
4464 void *stream = info->stream;
4465 fprintf_ftype func = info->fprintf_func;
4466
4467 if (thumb)
4468 {
4469 if ((given & 0xef000000) == 0xef000000)
4470 {
0313a2b8 4471 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 4472 unsigned long bit28 = given & (1 << 28);
4473
4474 given &= 0x00ffffff;
4475 if (bit28)
4476 given |= 0xf3000000;
4477 else
4478 given |= 0xf2000000;
4479 }
4480 else if ((given & 0xff000000) == 0xf9000000)
4481 given ^= 0xf9000000 ^ 0xf4000000;
4482 else
4483 return FALSE;
4484 }
43e65147 4485
16980d0b
JB		 4486 for (insn = neon_opcodes; insn->assembler; insn++)
4487 {
4488 if ((given & insn->mask) == insn->value)
4489 {
05413229 4490 signed long value_in_comment = 0;
e2efe87d 4491 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 4492 const char *c;
4493
4494 for (c = insn->assembler; *c; c++)
4495 {
4496 if (*c == '%')
4497 {
4498 switch (*++c)
4499 {
4500 case '%':
4501 func (stream, "%%");
4502 break;
4503
e2efe87d
MGD		 4504 case 'u':
4505 if (thumb && ifthen_state)
4506 is_unpredictable = TRUE;
4507
4508 /* Fall through. */
c22aaad1
PB		 4509 case 'c':
4510 if (thumb && ifthen_state)
4511 func (stream, "%s", arm_conditional[IFTHEN_COND]);
4512 break;
4513
16980d0b
JB		 4514 case 'A':
4515 {
43e65147 4516 static const unsigned char enc[16] =
16980d0b
JB		 4517 {
4518 0x4, 0x14, /* st4 0,1 */
4519 0x4, /* st1 2 */
4520 0x4, /* st2 3 */
4521 0x3, /* st3 4 */
4522 0x13, /* st3 5 */
4523 0x3, /* st1 6 */
4524 0x1, /* st1 7 */
4525 0x2, /* st2 8 */
4526 0x12, /* st2 9 */
4527 0x2, /* st1 10 */
4528 0, 0, 0, 0, 0
4529 };
4530 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4531 int rn = ((given >> 16) & 0xf);
4532 int rm = ((given >> 0) & 0xf);
4533 int align = ((given >> 4) & 0x3);
4534 int type = ((given >> 8) & 0xf);
4535 int n = enc[type] & 0xf;
4536 int stride = (enc[type] >> 4) + 1;
4537 int ix;
43e65147 4538
16980d0b
JB		 4539 func (stream, "{");
4540 if (stride > 1)
4541 for (ix = 0; ix != n; ix++)
4542 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
4543 else if (n == 1)
4544 func (stream, "d%d", rd);
4545 else
4546 func (stream, "d%d-d%d", rd, rd + n - 1);
4547 func (stream, "}, [%s", arm_regnames[rn]);
4548 if (align)
8e560766 4549 func (stream, " :%d", 32 << align);
16980d0b
JB		 4550 func (stream, "]");
4551 if (rm == 0xd)
4552 func (stream, "!");
4553 else if (rm != 0xf)
4554 func (stream, ", %s", arm_regnames[rm]);
4555 }
4556 break;
43e65147 4557
16980d0b
JB		 4558 case 'B':
4559 {
4560 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4561 int rn = ((given >> 16) & 0xf);
4562 int rm = ((given >> 0) & 0xf);
4563 int idx_align = ((given >> 4) & 0xf);
4564 int align = 0;
4565 int size = ((given >> 10) & 0x3);
4566 int idx = idx_align >> (size + 1);
4567 int length = ((given >> 8) & 3) + 1;
4568 int stride = 1;
4569 int i;
4570
4571 if (length > 1 && size > 0)
4572 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 4573
16980d0b
JB		 4574 switch (length)
4575 {
4576 case 1:
4577 {
4578 int amask = (1 << size) - 1;
4579 if ((idx_align & (1 << size)) != 0)
4580 return FALSE;
4581 if (size > 0)
4582 {
4583 if ((idx_align & amask) == amask)
4584 align = 8 << size;
4585 else if ((idx_align & amask) != 0)
4586 return FALSE;
4587 }
4588 }
4589 break;
43e65147 4590
16980d0b
JB		 4591 case 2:
4592 if (size == 2 && (idx_align & 2) != 0)
4593 return FALSE;
4594 align = (idx_align & 1) ? 16 << size : 0;
4595 break;
43e65147 4596
16980d0b
JB		 4597 case 3:
4598 if ((size == 2 && (idx_align & 3) != 0)
4599 || (idx_align & 1) != 0)
4600 return FALSE;
4601 break;
43e65147 4602
16980d0b
JB		 4603 case 4:
4604 if (size == 2)
4605 {
4606 if ((idx_align & 3) == 3)
4607 return FALSE;
4608 align = (idx_align & 3) * 64;
4609 }
4610 else
4611 align = (idx_align & 1) ? 32 << size : 0;
4612 break;
43e65147 4613
16980d0b
JB		 4614 default:
4615 abort ();
4616 }
43e65147 4617
16980d0b
JB		 4618 func (stream, "{");
4619 for (i = 0; i < length; i++)
4620 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
4621 rd + i * stride, idx);
4622 func (stream, "}, [%s", arm_regnames[rn]);
4623 if (align)
8e560766 4624 func (stream, " :%d", align);
16980d0b
JB		 4625 func (stream, "]");
4626 if (rm == 0xd)
4627 func (stream, "!");
4628 else if (rm != 0xf)
4629 func (stream, ", %s", arm_regnames[rm]);
4630 }
4631 break;
43e65147 4632
16980d0b
JB		 4633 case 'C':
4634 {
4635 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4636 int rn = ((given >> 16) & 0xf);
4637 int rm = ((given >> 0) & 0xf);
4638 int align = ((given >> 4) & 0x1);
4639 int size = ((given >> 6) & 0x3);
4640 int type = ((given >> 8) & 0x3);
4641 int n = type + 1;
4642 int stride = ((given >> 5) & 0x1);
4643 int ix;
43e65147 4644
16980d0b
JB		 4645 if (stride && (n == 1))
4646 n++;
4647 else
4648 stride++;
43e65147 4649
16980d0b
JB		 4650 func (stream, "{");
4651 if (stride > 1)
4652 for (ix = 0; ix != n; ix++)
4653 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
4654 else if (n == 1)
4655 func (stream, "d%d[]", rd);
4656 else
4657 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
4658 func (stream, "}, [%s", arm_regnames[rn]);
4659 if (align)
4660 {
91d6fa6a 4661 align = (8 * (type + 1)) << size;
16980d0b
JB		 4662 if (type == 3)
4663 align = (size > 1) ? align >> 1 : align;
4664 if (type == 2 || (type == 0 && !size))
8e560766 4665 func (stream, " :<bad align %d>", align);
16980d0b 4666 else
8e560766 4667 func (stream, " :%d", align);
16980d0b
JB		 4668 }
4669 func (stream, "]");
4670 if (rm == 0xd)
4671 func (stream, "!");
4672 else if (rm != 0xf)
4673 func (stream, ", %s", arm_regnames[rm]);
4674 }
4675 break;
43e65147 4676
16980d0b
JB		 4677 case 'D':
4678 {
4679 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
4680 int size = (given >> 20) & 3;
4681 int reg = raw_reg & ((4 << size) - 1);
4682 int ix = raw_reg >> size >> 2;
43e65147 4683
16980d0b
JB		 4684 func (stream, "d%d[%d]", reg, ix);
4685 }
4686 break;
43e65147 4687
16980d0b 4688 case 'E':
fe56b6ce 4689 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 4690 {
4691 int bits = 0;
4692 int cmode = (given >> 8) & 0xf;
4693 int op = (given >> 5) & 0x1;
4694 unsigned long value = 0, hival = 0;
4695 unsigned shift;
4696 int size = 0;
0dbde4cf 4697 int isfloat = 0;
43e65147 4698
16980d0b
JB		 4699 bits |= ((given >> 24) & 1) << 7;
4700 bits |= ((given >> 16) & 7) << 4;
4701 bits |= ((given >> 0) & 15) << 0;
43e65147 4702
16980d0b
JB		 4703 if (cmode < 8)
4704 {
4705 shift = (cmode >> 1) & 3;
fe56b6ce 4706 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4707 size = 32;
4708 }
4709 else if (cmode < 12)
4710 {
4711 shift = (cmode >> 1) & 1;
fe56b6ce 4712 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4713 size = 16;
4714 }
4715 else if (cmode < 14)
4716 {
4717 shift = (cmode & 1) + 1;
fe56b6ce 4718 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 4719 value |= (1ul << (8 * shift)) - 1;
4720 size = 32;
4721 }
4722 else if (cmode == 14)
4723 {
4724 if (op)
4725 {
fe56b6ce 4726 /* Bit replication into bytes. */
16980d0b
JB		 4727 int ix;
4728 unsigned long mask;
43e65147 4729
16980d0b
JB		 4730 value = 0;
4731 hival = 0;
4732 for (ix = 7; ix >= 0; ix--)
4733 {
4734 mask = ((bits >> ix) & 1) ? 0xff : 0;
4735 if (ix <= 3)
4736 value = (value << 8) | mask;
4737 else
4738 hival = (hival << 8) | mask;
4739 }
4740 size = 64;
4741 }
4742 else
4743 {
fe56b6ce
NC		 4744 /* Byte replication. */
4745 value = (unsigned long) bits;
16980d0b
JB		 4746 size = 8;
4747 }
4748 }
4749 else if (!op)
4750 {
fe56b6ce 4751 /* Floating point encoding. */
16980d0b 4752 int tmp;
43e65147 4753
fe56b6ce
NC		 4754 value = (unsigned long) (bits & 0x7f) << 19;
4755 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 4756 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 4757 value |= (unsigned long) tmp << 24;
16980d0b 4758 size = 32;
0dbde4cf 4759 isfloat = 1;
16980d0b
JB		 4760 }
4761 else
4762 {
4763 func (stream, "<illegal constant %.8x:%x:%x>",
4764 bits, cmode, op);
4765 size = 32;
4766 break;
4767 }
4768 switch (size)
4769 {
4770 case 8:
4771 func (stream, "#%ld\t; 0x%.2lx", value, value);
4772 break;
43e65147 4773
16980d0b
JB		 4774 case 16:
4775 func (stream, "#%ld\t; 0x%.4lx", value, value);
4776 break;
4777
4778 case 32:
0dbde4cf
JB		 4779 if (isfloat)
4780 {
4781 unsigned char valbytes[4];
4782 double fvalue;
43e65147 4783
0dbde4cf
JB		 4784 /* Do this a byte at a time so we don't have to
4785 worry about the host's endianness. */
4786 valbytes[0] = value & 0xff;
4787 valbytes[1] = (value >> 8) & 0xff;
4788 valbytes[2] = (value >> 16) & 0xff;
4789 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 4790
4791 floatformat_to_double
c1e26897
NC		 4792 (& floatformat_ieee_single_little, valbytes,
4793 & fvalue);
43e65147 4794
0dbde4cf
JB		 4795 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
4796 value);
4797 }
4798 else
4e9d3b81 4799 func (stream, "#%ld\t; 0x%.8lx",
43e65147 4800 (long) (((value & 0x80000000L) != 0)
9d82ec38 4801 ? value | ~0xffffffffL : value),
c1e26897 4802 value);
16980d0b
JB		 4803 break;
4804
4805 case 64:
4806 func (stream, "#0x%.8lx%.8lx", hival, value);
4807 break;
43e65147 4808
16980d0b
JB		 4809 default:
4810 abort ();
4811 }
4812 }
4813 break;
43e65147 4814
16980d0b
JB		 4815 case 'F':
4816 {
4817 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
4818 int num = (given >> 8) & 0x3;
43e65147 4819
16980d0b
JB		 4820 if (!num)
4821 func (stream, "{d%d}", regno);
4822 else if (num + regno >= 32)
4823 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
4824 else
4825 func (stream, "{d%d-d%d}", regno, regno + num);
4826 }
4827 break;
7e8e6784 4828
16980d0b
JB		 4829
4830 case '0': case '1': case '2': case '3': case '4':
4831 case '5': case '6': case '7': case '8': case '9':
4832 {
4833 int width;
4834 unsigned long value;
4835
4836 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 4837
16980d0b
JB		 4838 switch (*c)
4839 {
4840 case 'r':
4841 func (stream, "%s", arm_regnames[value]);
4842 break;
4843 case 'd':
4844 func (stream, "%ld", value);
05413229 4845 value_in_comment = value;
16980d0b
JB		 4846 break;
4847 case 'e':
4848 func (stream, "%ld", (1ul << width) - value);
4849 break;
43e65147 4850
16980d0b
JB		 4851 case 'S':
4852 case 'T':
4853 case 'U':
05413229 4854 /* Various width encodings. */
16980d0b
JB		 4855 {
4856 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
4857 int limit;
4858 unsigned low, high;
4859
4860 c++;
4861 if (*c >= '0' && *c <= '9')
4862 limit = *c - '0';
4863 else if (*c >= 'a' && *c <= 'f')
4864 limit = *c - 'a' + 10;
4865 else
4866 abort ();
4867 low = limit >> 2;
4868 high = limit & 3;
4869
4870 if (value < low || value > high)
4871 func (stream, "<illegal width %d>", base << value);
4872 else
4873 func (stream, "%d", base << value);
4874 }
4875 break;
4876 case 'R':
4877 if (given & (1 << 6))
4878 goto Q;
4879 /* FALLTHROUGH */
4880 case 'D':
4881 func (stream, "d%ld", value);
4882 break;
4883 case 'Q':
4884 Q:
4885 if (value & 1)
4886 func (stream, "<illegal reg q%ld.5>", value >> 1);
4887 else
4888 func (stream, "q%ld", value >> 1);
4889 break;
43e65147 4890
16980d0b
JB		 4891 case '`':
4892 c++;
4893 if (value == 0)
4894 func (stream, "%c", *c);
4895 break;
4896 case '\'':
4897 c++;
4898 if (value == ((1ul << width) - 1))
4899 func (stream, "%c", *c);
4900 break;
4901 case '?':
fe56b6ce 4902 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 4903 c += 1 << width;
4904 break;
4905 default:
4906 abort ();
4907 }
16980d0b 4908 }
dffaa15c
AM		 4909 break;
4910
4911 default:
4912 abort ();
16980d0b
JB		 4913 }
4914 }
4915 else
4916 func (stream, "%c", *c);
4917 }
05413229
NC		 4918
4919 if (value_in_comment > 32 || value_in_comment < -16)
4920 func (stream, "\t; 0x%lx", value_in_comment);
4921
e2efe87d
MGD		 4922 if (is_unpredictable)
4923 func (stream, UNPREDICTABLE_INSTRUCTION);
4924
16980d0b
JB		 4925 return TRUE;
4926 }
4927 }
4928 return FALSE;
4929}
4930
73cd51e5
AV		 4931/* Print one mve instruction on INFO->STREAM.
4932 Return TRUE if the instuction matched, FALSE if this is not a
4933 recognised mve instruction. */
4934
4935static bfd_boolean
4936print_insn_mve (struct disassemble_info *info, long given)
4937{
4938 const struct mopcode32 *insn;
4939 void *stream = info->stream;
4940 fprintf_ftype func = info->fprintf_func;
4941
4942 for (insn = mve_opcodes; insn->assembler; insn++)
4943 {
4944 if (((given & insn->mask) == insn->value)
4945 && !is_mve_encoding_conflict (given, insn->mve_op))
4946 {
4947 signed long value_in_comment = 0;
4948 bfd_boolean is_unpredictable = FALSE;
4949 bfd_boolean is_undefined = FALSE;
4950 const char *c;
4951 enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
4952 enum mve_undefined undefined_cond = UNDEF_NONE;
4953
4954 /* Most vector mve instruction are illegal in a it block.
4955 There are a few exceptions; check for them. */
4956 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
4957 {
4958 is_unpredictable = TRUE;
4959 unpredictable_cond = UNPRED_IT_BLOCK;
4960 }
4961 else if (is_mve_unpredictable (given, insn->mve_op,
4962 &unpredictable_cond))
4963 is_unpredictable = TRUE;
4964
4965 if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
4966 is_undefined = TRUE;
4967
4968 for (c = insn->assembler; *c; c++)
4969 {
4970 if (*c == '%')
4971 {
4972 switch (*++c)
4973 {
4974 case '%':
4975 func (stream, "%%");
4976 break;
4977
4978 }
4979 }
4980 else
4981 func (stream, "%c", *c);
4982 }
4983
4984 if (value_in_comment > 32 || value_in_comment < -16)
4985 func (stream, "\t; 0x%lx", value_in_comment);
4986
4987 if (is_unpredictable)
4988 print_mve_unpredictable (info, unpredictable_cond);
4989
4990 if (is_undefined)
4991 print_mve_undefined (info, undefined_cond);
4992
4993 return TRUE;
4994 }
4995 }
4996 return FALSE;
4997}
4998
4999
90ec0d68
MGD		 5000/* Return the name of a v7A special register. */
5001
43e65147 5002static const char *
90ec0d68
MGD		 5003banked_regname (unsigned reg)
5004{
5005 switch (reg)
5006 {
5007 case 15: return "CPSR";
43e65147 5008 case 32: return "R8_usr";
90ec0d68
MGD		 5009 case 33: return "R9_usr";
5010 case 34: return "R10_usr";
5011 case 35: return "R11_usr";
5012 case 36: return "R12_usr";
5013 case 37: return "SP_usr";
5014 case 38: return "LR_usr";
43e65147 5015 case 40: return "R8_fiq";
90ec0d68
MGD		 5016 case 41: return "R9_fiq";
5017 case 42: return "R10_fiq";
5018 case 43: return "R11_fiq";
5019 case 44: return "R12_fiq";
5020 case 45: return "SP_fiq";
5021 case 46: return "LR_fiq";
5022 case 48: return "LR_irq";
5023 case 49: return "SP_irq";
5024 case 50: return "LR_svc";
5025 case 51: return "SP_svc";
5026 case 52: return "LR_abt";
5027 case 53: return "SP_abt";
5028 case 54: return "LR_und";
5029 case 55: return "SP_und";
5030 case 60: return "LR_mon";
5031 case 61: return "SP_mon";
5032 case 62: return "ELR_hyp";
5033 case 63: return "SP_hyp";
5034 case 79: return "SPSR";
5035 case 110: return "SPSR_fiq";
5036 case 112: return "SPSR_irq";
5037 case 114: return "SPSR_svc";
5038 case 116: return "SPSR_abt";
5039 case 118: return "SPSR_und";
5040 case 124: return "SPSR_mon";
5041 case 126: return "SPSR_hyp";
5042 default: return NULL;
5043 }
5044}
5045
e797f7e0
MGD		 5046/* Return the name of the DMB/DSB option. */
5047static const char *
5048data_barrier_option (unsigned option)
5049{
5050 switch (option & 0xf)
5051 {
5052 case 0xf: return "sy";
5053 case 0xe: return "st";
5054 case 0xd: return "ld";
5055 case 0xb: return "ish";
5056 case 0xa: return "ishst";
5057 case 0x9: return "ishld";
5058 case 0x7: return "un";
5059 case 0x6: return "unst";
5060 case 0x5: return "nshld";
5061 case 0x3: return "osh";
5062 case 0x2: return "oshst";
5063 case 0x1: return "oshld";
5064 default: return NULL;
5065 }
5066}
5067
4a5329c6
ZW		 5068/* Print one ARM instruction from PC on INFO->STREAM. */
5069
5070static void
5071print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 5072{
6b5d3a4d 5073 const struct opcode32 *insn;
6a51a8a8 5074 void *stream = info->stream;
6b5d3a4d 5075 fprintf_ftype func = info->fprintf_func;
b0e28b39 5076 struct arm_private_data *private_data = info->private_data;
252b5132 5077
16980d0b
JB		 5078 if (print_insn_coprocessor (pc, info, given, FALSE))
5079 return;
5080
5081 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 5082 return;
5083
252b5132
RH		 5084 for (insn = arm_opcodes; insn->assembler; insn++)
5085 {
0313a2b8
NC		 5086 if ((given & insn->mask) != insn->value)
5087 continue;
823d2571
TG		 5088
5089 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 5090 continue;
5091
5092 /* Special case: an instruction with all bits set in the condition field
5093 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
5094 or by the catchall at the end of the table. */
5095 if ((given & 0xF0000000) != 0xF0000000
5096 || (insn->mask & 0xF0000000) == 0xF0000000
5097 || (insn->mask == 0 && insn->value == 0))
252b5132 5098 {
ff4a8d2b
NC		 5099 unsigned long u_reg = 16;
5100 unsigned long U_reg = 16;
ab8e2090 5101 bfd_boolean is_unpredictable = FALSE;
05413229 5102 signed long value_in_comment = 0;
6b5d3a4d 5103 const char *c;
b34976b6 5104
252b5132
RH		 5105 for (c = insn->assembler; *c; c++)
5106 {
5107 if (*c == '%')
5108 {
c1e26897
NC		 5109 bfd_boolean allow_unpredictable = FALSE;
5110
252b5132
RH		 5111 switch (*++c)
5112 {
5113 case '%':
5114 func (stream, "%%");
5115 break;
5116
5117 case 'a':
05413229 5118 value_in_comment = print_arm_address (pc, info, given);
62b3e311 5119 break;
252b5132 5120
62b3e311
PB		 5121 case 'P':
5122 /* Set P address bit and use normal address
5123 printing routine. */
c1e26897 5124 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 5125 break;
5126
c1e26897
NC		 5127 case 'S':
5128 allow_unpredictable = TRUE;
1a0670f3 5129 /* Fall through. */
252b5132
RH		 5130 case 's':
5131 if ((given & 0x004f0000) == 0x004f0000)
5132 {
58efb6c0 5133 /* PC relative with immediate offset. */
f8b960bc 5134 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 5135
aefd8a40
NC		 5136 if (PRE_BIT_SET)
5137 {
26d97720
NS		 5138 /* Elide positive zero offset. */
5139 if (offset || NEGATIVE_BIT_SET)
5140 func (stream, "[pc, #%s%d]\t; ",
d908c8af 5141 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 5142 else
26d97720
NS		 5143 func (stream, "[pc]\t; ");
5144 if (NEGATIVE_BIT_SET)
5145 offset = -offset;
aefd8a40
NC		 5146 info->print_address_func (offset + pc + 8, info);
5147 }
5148 else
5149 {
26d97720
NS		 5150 /* Always show the offset. */
5151 func (stream, "[pc], #%s%d",
d908c8af 5152 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 5153 if (! allow_unpredictable)
5154 is_unpredictable = TRUE;
aefd8a40 5155 }
252b5132
RH		 5156 }
5157 else
5158 {
fe56b6ce
NC		 5159 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
5160
b34976b6 5161 func (stream, "[%s",
252b5132 5162 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 5163
c1e26897 5164 if (PRE_BIT_SET)
252b5132 5165 {
c1e26897 5166 if (IMMEDIATE_BIT_SET)
252b5132 5167 {
26d97720
NS		 5168 /* Elide offset for non-writeback
5169 positive zero. */
5170 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
5171 || offset)
5172 func (stream, ", #%s%d",
5173 NEGATIVE_BIT_SET ? "-" : "", offset);
5174
5175 if (NEGATIVE_BIT_SET)
5176 offset = -offset;
945ee430 5177
fe56b6ce 5178 value_in_comment = offset;
252b5132 5179 }
945ee430 5180 else
ff4a8d2b
NC		 5181 {
5182 /* Register Offset or Register Pre-Indexed. */
5183 func (stream, ", %s%s",
5184 NEGATIVE_BIT_SET ? "-" : "",
5185 arm_regnames[given & 0xf]);
5186
5187 /* Writing back to the register that is the source/
5188 destination of the load/store is unpredictable. */
5189 if (! allow_unpredictable
5190 && WRITEBACK_BIT_SET
5191 && ((given & 0xf) == ((given >> 12) & 0xf)))
5192 is_unpredictable = TRUE;
5193 }
252b5132 5194
b34976b6 5195 func (stream, "]%s",
c1e26897 5196 WRITEBACK_BIT_SET ? "!" : "");
252b5132 5197 }
945ee430 5198 else
252b5132 5199 {
c1e26897 5200 if (IMMEDIATE_BIT_SET)
252b5132 5201 {
945ee430 5202 /* Immediate Post-indexed. */
aefd8a40 5203 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 5204 func (stream, "], #%s%d",
5205 NEGATIVE_BIT_SET ? "-" : "", offset);
5206 if (NEGATIVE_BIT_SET)
5207 offset = -offset;
fe56b6ce 5208 value_in_comment = offset;
252b5132 5209 }
945ee430 5210 else
ff4a8d2b
NC		 5211 {
5212 /* Register Post-indexed. */
5213 func (stream, "], %s%s",
5214 NEGATIVE_BIT_SET ? "-" : "",
5215 arm_regnames[given & 0xf]);
5216
5217 /* Writing back to the register that is the source/
5218 destination of the load/store is unpredictable. */
5219 if (! allow_unpredictable
5220 && (given & 0xf) == ((given >> 12) & 0xf))
5221 is_unpredictable = TRUE;
5222 }
c1e26897 5223
07a28fab
NC		 5224 if (! allow_unpredictable)
5225 {
5226 /* Writeback is automatically implied by post- addressing.
5227 Setting the W bit is unnecessary and ARM specify it as
5228 being unpredictable. */
5229 if (WRITEBACK_BIT_SET
5230 /* Specifying the PC register as the post-indexed
5231 registers is also unpredictable. */
ab8e2090
NC		 5232 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
5233 is_unpredictable = TRUE;
07a28fab 5234 }
252b5132
RH		 5235 }
5236 }
5237 break;
b34976b6 5238
252b5132 5239 case 'b':
6b5d3a4d 5240 {
f8b960bc 5241 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
05413229 5242 info->print_address_func (disp * 4 + pc + 8, info);
6b5d3a4d 5243 }
252b5132
RH		 5244 break;
5245
5246 case 'c':
c22aaad1
PB		 5247 if (((given >> 28) & 0xf) != 0xe)
5248 func (stream, "%s",
5249 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 5250 break;
5251
5252 case 'm':
5253 {
5254 int started = 0;
5255 int reg;
5256
5257 func (stream, "{");
5258 for (reg = 0; reg < 16; reg++)
5259 if ((given & (1 << reg)) != 0)
5260 {
5261 if (started)
5262 func (stream, ", ");
5263 started = 1;
5264 func (stream, "%s", arm_regnames[reg]);
5265 }
5266 func (stream, "}");
ab8e2090
NC		 5267 if (! started)
5268 is_unpredictable = TRUE;
252b5132
RH		 5269 }
5270 break;
5271
37b37b2d 5272 case 'q':
78c66db8 5273 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 5274 break;
5275
252b5132
RH		 5276 case 'o':
5277 if ((given & 0x02000000) != 0)
5278 {
a415b1cd
JB		 5279 unsigned int rotate = (given & 0xf00) >> 7;
5280 unsigned int immed = (given & 0xff);
5281 unsigned int a, i;
5282
5283 a = (((immed << (32 - rotate))
5284 | (immed >> rotate)) & 0xffffffff);
5285 /* If there is another encoding with smaller rotate,
5286 the rotate should be specified directly. */
5287 for (i = 0; i < 32; i += 2)
5288 if ((a << i | a >> (32 - i)) <= 0xff)
5289 break;
5290
5291 if (i != rotate)
5292 func (stream, "#%d, %d", immed, rotate);
5293 else
5294 func (stream, "#%d", a);
5295 value_in_comment = a;
252b5132
RH		 5296 }
5297 else
78c66db8 5298 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 5299 break;
5300
5301 case 'p':
5302 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 5303 {
823d2571
TG		 5304 arm_feature_set arm_ext_v6 =
5305 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
5306
aefd8a40
NC		 5307 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
5308 mechanism for setting PSR flag bits. They are
5309 obsolete in V6 onwards. */
823d2571
TG		 5310 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
5311 arm_ext_v6))
aefd8a40 5312 func (stream, "p");
4ab90a7a
AV		 5313 else
5314 is_unpredictable = TRUE;
aefd8a40 5315 }
252b5132
RH		 5316 break;
5317
5318 case 't':
5319 if ((given & 0x01200000) == 0x00200000)
5320 func (stream, "t");
5321 break;
5322
252b5132 5323 case 'A':
05413229
NC		 5324 {
5325 int offset = given & 0xff;
f02232aa 5326
05413229 5327 value_in_comment = offset * 4;
c1e26897 5328 if (NEGATIVE_BIT_SET)
05413229 5329 value_in_comment = - value_in_comment;
f02232aa 5330
05413229 5331 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 5332
c1e26897 5333 if (PRE_BIT_SET)
05413229
NC		 5334 {
5335 if (offset)
fe56b6ce 5336 func (stream, ", #%d]%s",
d908c8af 5337 (int) value_in_comment,
c1e26897 5338 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 5339 else
5340 func (stream, "]");
5341 }
5342 else
5343 {
5344 func (stream, "]");
f02232aa 5345
c1e26897 5346 if (WRITEBACK_BIT_SET)
05413229
NC		 5347 {
5348 if (offset)
d908c8af 5349 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 5350 }
5351 else
fe56b6ce 5352 {
d908c8af 5353 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 5354 value_in_comment = offset;
5355 }
05413229
NC		 5356 }
5357 }
252b5132
RH		 5358 break;
5359
077b8428
NC		 5360 case 'B':
5361 /* Print ARM V5 BLX(1) address: pc+25 bits. */
5362 {
5363 bfd_vma address;
5364 bfd_vma offset = 0;
b34976b6 5365
c1e26897 5366 if (! NEGATIVE_BIT_SET)
077b8428
NC		 5367 /* Is signed, hi bits should be ones. */
5368 offset = (-1) ^ 0x00ffffff;
5369
5370 /* Offset is (SignExtend(offset field)<<2). */
5371 offset += given & 0x00ffffff;
5372 offset <<= 2;
5373 address = offset + pc + 8;
b34976b6 5374
8f06b2d8
PB		 5375 if (given & 0x01000000)
5376 /* H bit allows addressing to 2-byte boundaries. */
5377 address += 2;
b1ee46c5 5378
8f06b2d8 5379 info->print_address_func (address, info);
b1ee46c5 5380 }
b1ee46c5
AH		 5381 break;
5382
252b5132 5383 case 'C':
90ec0d68
MGD		 5384 if ((given & 0x02000200) == 0x200)
5385 {
5386 const char * name;
5387 unsigned sysm = (given & 0x004f0000) >> 16;
5388
5389 sysm |= (given & 0x300) >> 4;
5390 name = banked_regname (sysm);
5391
5392 if (name != NULL)
5393 func (stream, "%s", name);
5394 else
d908c8af 5395 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 5396 }
5397 else
5398 {
43e65147 5399 func (stream, "%cPSR_",
90ec0d68
MGD		 5400 (given & 0x00400000) ? 'S' : 'C');
5401 if (given & 0x80000)
5402 func (stream, "f");
5403 if (given & 0x40000)
5404 func (stream, "s");
5405 if (given & 0x20000)
5406 func (stream, "x");
5407 if (given & 0x10000)
5408 func (stream, "c");
5409 }
252b5132
RH		 5410 break;
5411
62b3e311 5412 case 'U':
43e65147 5413 if ((given & 0xf0) == 0x60)
62b3e311 5414 {
52e7f43d
RE		 5415 switch (given & 0xf)
5416 {
5417 case 0xf: func (stream, "sy"); break;
5418 default:
5419 func (stream, "#%d", (int) given & 0xf);
5420 break;
5421 }
43e65147
L		 5422 }
5423 else
52e7f43d 5424 {
e797f7e0
MGD		 5425 const char * opt = data_barrier_option (given & 0xf);
5426 if (opt != NULL)
5427 func (stream, "%s", opt);
5428 else
52e7f43d 5429 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 5430 }
5431 break;
5432
b34976b6 5433 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 5434 case '5': case '6': case '7': case '8': case '9':
5435 {
16980d0b
JB		 5436 int width;
5437 unsigned long value;
252b5132 5438
16980d0b 5439 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 5440
252b5132
RH		 5441 switch (*c)
5442 {
ab8e2090
NC		 5443 case 'R':
5444 if (value == 15)
5445 is_unpredictable = TRUE;
5446 /* Fall through. */
16980d0b 5447 case 'r':
9eb6c0f1
MGD		 5448 case 'T':
5449 /* We want register + 1 when decoding T. */
5450 if (*c == 'T')
5451 ++value;
5452
ff4a8d2b
NC		 5453 if (c[1] == 'u')
5454 {
5455 /* Eat the 'u' character. */
5456 ++ c;
5457
5458 if (u_reg == value)
5459 is_unpredictable = TRUE;
5460 u_reg = value;
5461 }
5462 if (c[1] == 'U')
5463 {
5464 /* Eat the 'U' character. */
5465 ++ c;
5466
5467 if (U_reg == value)
5468 is_unpredictable = TRUE;
5469 U_reg = value;
5470 }
16980d0b
JB		 5471 func (stream, "%s", arm_regnames[value]);
5472 break;
5473 case 'd':
5474 func (stream, "%ld", value);
05413229 5475 value_in_comment = value;
16980d0b
JB		 5476 break;
5477 case 'b':
5478 func (stream, "%ld", value * 8);
05413229 5479 value_in_comment = value * 8;
16980d0b
JB		 5480 break;
5481 case 'W':
5482 func (stream, "%ld", value + 1);
05413229 5483 value_in_comment = value + 1;
16980d0b
JB		 5484 break;
5485 case 'x':
5486 func (stream, "0x%08lx", value);
5487
5488 /* Some SWI instructions have special
5489 meanings. */
5490 if ((given & 0x0fffffff) == 0x0FF00000)
5491 func (stream, "\t; IMB");
5492 else if ((given & 0x0fffffff) == 0x0FF00001)
5493 func (stream, "\t; IMBRange");
5494 break;
5495 case 'X':
5496 func (stream, "%01lx", value & 0xf);
05413229 5497 value_in_comment = value;
252b5132
RH		 5498 break;
5499 case '`':
5500 c++;
16980d0b 5501 if (value == 0)
252b5132
RH		 5502 func (stream, "%c", *c);
5503 break;
5504 case '\'':
5505 c++;
16980d0b 5506 if (value == ((1ul << width) - 1))
252b5132
RH		 5507 func (stream, "%c", *c);
5508 break;
5509 case '?':
fe56b6ce 5510 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 5511 c += 1 << width;
252b5132
RH		 5512 break;
5513 default:
5514 abort ();
5515 }
dffaa15c
AM		 5516 }
5517 break;
0dd132b6 5518
dffaa15c
AM		 5519 case 'e':
5520 {
5521 int imm;
0dd132b6 5522
dffaa15c
AM		 5523 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
5524 func (stream, "%d", imm);
5525 value_in_comment = imm;
5526 }
5527 break;
fe56b6ce 5528
dffaa15c
AM		 5529 case 'E':
5530 /* LSB and WIDTH fields of BFI or BFC. The machine-
5531 language instruction encodes LSB and MSB. */
5532 {
5533 long msb = (given & 0x001f0000) >> 16;
5534 long lsb = (given & 0x00000f80) >> 7;
5535 long w = msb - lsb + 1;
0a003adc 5536
dffaa15c
AM		 5537 if (w > 0)
5538 func (stream, "#%lu, #%lu", lsb, w);
5539 else
5540 func (stream, "(invalid: %lu:%lu)", lsb, msb);
5541 }
5542 break;
90ec0d68 5543
dffaa15c
AM		 5544 case 'R':
5545 /* Get the PSR/banked register name. */
5546 {
5547 const char * name;
5548 unsigned sysm = (given & 0x004f0000) >> 16;
90ec0d68 5549
dffaa15c
AM		 5550 sysm |= (given & 0x300) >> 4;
5551 name = banked_regname (sysm);
90ec0d68 5552
dffaa15c
AM		 5553 if (name != NULL)
5554 func (stream, "%s", name);
5555 else
5556 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
5557 }
5558 break;
fe56b6ce 5559
dffaa15c
AM		 5560 case 'V':
5561 /* 16-bit unsigned immediate from a MOVT or MOVW
5562 instruction, encoded in bits 0:11 and 15:19. */
5563 {
5564 long hi = (given & 0x000f0000) >> 4;
5565 long lo = (given & 0x00000fff);
5566 long imm16 = hi | lo;
0a003adc 5567
dffaa15c
AM		 5568 func (stream, "#%lu", imm16);
5569 value_in_comment = imm16;
252b5132 5570 }
dffaa15c
AM		 5571 break;
5572
5573 default:
5574 abort ();
252b5132
RH		 5575 }
5576 }
5577 else
5578 func (stream, "%c", *c);
5579 }
05413229
NC		 5580
5581 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 5582 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 5583
5584 if (is_unpredictable)
5585 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 5586
4a5329c6 5587 return;
252b5132
RH		 5588 }
5589 }
0b347048
TC		 5590 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
5591 return;
252b5132
RH		 5592}
5593
4a5329c6 5594/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 5595
4a5329c6
ZW		 5596static void
5597print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 5598{
6b5d3a4d 5599 const struct opcode16 *insn;
6a51a8a8
AM		 5600 void *stream = info->stream;
5601 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 5602
5603 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 5604 if ((given & insn->mask) == insn->value)
5605 {
05413229 5606 signed long value_in_comment = 0;
6b5d3a4d 5607 const char *c = insn->assembler;
05413229 5608
c19d1205
ZW		 5609 for (; *c; c++)
5610 {
5611 int domaskpc = 0;
5612 int domasklr = 0;
5613
5614 if (*c != '%')
5615 {
5616 func (stream, "%c", *c);
5617 continue;
5618 }
252b5132 5619
c19d1205
ZW		 5620 switch (*++c)
5621 {
5622 case '%':
5623 func (stream, "%%");
5624 break;
b34976b6 5625
c22aaad1
PB		 5626 case 'c':
5627 if (ifthen_state)
5628 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5629 break;
5630
5631 case 'C':
5632 if (ifthen_state)
5633 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5634 else
5635 func (stream, "s");
5636 break;
5637
5638 case 'I':
5639 {
5640 unsigned int tmp;
5641
5642 ifthen_next_state = given & 0xff;
5643 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
5644 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
5645 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
5646 }
5647 break;
5648
5649 case 'x':
5650 if (ifthen_next_state)
5651 func (stream, "\t; unpredictable branch in IT block\n");
5652 break;
5653
5654 case 'X':
5655 if (ifthen_state)
5656 func (stream, "\t; unpredictable <IT:%s>",
5657 arm_conditional[IFTHEN_COND]);
5658 break;
5659
c19d1205
ZW		 5660 case 'S':
5661 {
5662 long reg;
5663
5664 reg = (given >> 3) & 0x7;
5665 if (given & (1 << 6))
5666 reg += 8;
4f3c3dbb 5667
c19d1205
ZW		 5668 func (stream, "%s", arm_regnames[reg]);
5669 }
5670 break;
baf0cc5e 5671
c19d1205 5672 case 'D':
4f3c3dbb 5673 {
c19d1205
ZW		 5674 long reg;
5675
5676 reg = given & 0x7;
5677 if (given & (1 << 7))
5678 reg += 8;
5679
5680 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 5681 }
c19d1205
ZW		 5682 break;
5683
5684 case 'N':
5685 if (given & (1 << 8))
5686 domasklr = 1;
5687 /* Fall through. */
5688 case 'O':
5689 if (*c == 'O' && (given & (1 << 8)))
5690 domaskpc = 1;
5691 /* Fall through. */
5692 case 'M':
5693 {
5694 int started = 0;
5695 int reg;
5696
5697 func (stream, "{");
5698
5699 /* It would be nice if we could spot
5700 ranges, and generate the rS-rE format: */
5701 for (reg = 0; (reg < 8); reg++)
5702 if ((given & (1 << reg)) != 0)
5703 {
5704 if (started)
5705 func (stream, ", ");
5706 started = 1;
5707 func (stream, "%s", arm_regnames[reg]);
5708 }
5709
5710 if (domasklr)
5711 {
5712 if (started)
5713 func (stream, ", ");
5714 started = 1;
d908c8af 5715 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 5716 }
5717
5718 if (domaskpc)
5719 {
5720 if (started)
5721 func (stream, ", ");
d908c8af 5722 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 5723 }
5724
5725 func (stream, "}");
5726 }
5727 break;
5728
4547cb56
NC		 5729 case 'W':
5730 /* Print writeback indicator for a LDMIA. We are doing a
5731 writeback if the base register is not in the register
5732 mask. */
5733 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
5734 func (stream, "!");
dffaa15c 5735 break;
4547cb56 5736
c19d1205
ZW		 5737 case 'b':
5738 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
5739 {
5740 bfd_vma address = (pc + 4
5741 + ((given & 0x00f8) >> 2)
5742 + ((given & 0x0200) >> 3));
5743 info->print_address_func (address, info);
5744 }
5745 break;
5746
5747 case 's':
5748 /* Right shift immediate -- bits 6..10; 1-31 print
5749 as themselves, 0 prints as 32. */
5750 {
5751 long imm = (given & 0x07c0) >> 6;
5752 if (imm == 0)
5753 imm = 32;
0fd3a477 5754 func (stream, "#%ld", imm);
c19d1205
ZW		 5755 }
5756 break;
5757
5758 case '0': case '1': case '2': case '3': case '4':
5759 case '5': case '6': case '7': case '8': case '9':
5760 {
5761 int bitstart = *c++ - '0';
5762 int bitend = 0;
5763
5764 while (*c >= '0' && *c <= '9')
5765 bitstart = (bitstart * 10) + *c++ - '0';
5766
5767 switch (*c)
5768 {
5769 case '-':
5770 {
f8b960bc 5771 bfd_vma reg;
c19d1205
ZW		 5772
5773 c++;
5774 while (*c >= '0' && *c <= '9')
5775 bitend = (bitend * 10) + *c++ - '0';
5776 if (!bitend)
5777 abort ();
5778 reg = given >> bitstart;
5779 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 5780
c19d1205
ZW		 5781 switch (*c)
5782 {
5783 case 'r':
5784 func (stream, "%s", arm_regnames[reg]);
5785 break;
5786
5787 case 'd':
d908c8af 5788 func (stream, "%ld", (long) reg);
05413229 5789 value_in_comment = reg;
c19d1205
ZW		 5790 break;
5791
5792 case 'H':
d908c8af 5793 func (stream, "%ld", (long) (reg << 1));
05413229 5794 value_in_comment = reg << 1;
c19d1205
ZW		 5795 break;
5796
5797 case 'W':
d908c8af 5798 func (stream, "%ld", (long) (reg << 2));
05413229 5799 value_in_comment = reg << 2;
c19d1205
ZW		 5800 break;
5801
5802 case 'a':
5803 /* PC-relative address -- the bottom two
5804 bits of the address are dropped
5805 before the calculation. */
5806 info->print_address_func
5807 (((pc + 4) & ~3) + (reg << 2), info);
05413229 5808 value_in_comment = 0;
c19d1205
ZW		 5809 break;
5810
5811 case 'x':
d908c8af 5812 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 5813 break;
5814
c19d1205
ZW		 5815 case 'B':
5816 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6b5d3a4d 5817 info->print_address_func (reg * 2 + pc + 4, info);
05413229 5818 value_in_comment = 0;
c19d1205
ZW		 5819 break;
5820
5821 case 'c':
c22aaad1 5822 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 5823 break;
5824
5825 default:
5826 abort ();
5827 }
5828 }
5829 break;
5830
5831 case '\'':
5832 c++;
5833 if ((given & (1 << bitstart)) != 0)
5834 func (stream, "%c", *c);
5835 break;
5836
5837 case '?':
5838 ++c;
5839 if ((given & (1 << bitstart)) != 0)
5840 func (stream, "%c", *c++);
5841 else
5842 func (stream, "%c", *++c);
5843 break;
5844
5845 default:
5846 abort ();
5847 }
5848 }
5849 break;
5850
5851 default:
5852 abort ();
5853 }
5854 }
05413229
NC		 5855
5856 if (value_in_comment > 32 || value_in_comment < -16)
5857 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 5858 return;
c19d1205
ZW		 5859 }
5860
5861 /* No match. */
0b347048
TC		 5862 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
5863 return;
c19d1205
ZW		 5864}
5865
62b3e311 5866/* Return the name of an V7M special register. */
fe56b6ce 5867
62b3e311
PB		 5868static const char *
5869psr_name (int regno)
5870{
5871 switch (regno)
5872 {
1a336194
TP		 5873 case 0x0: return "APSR";
5874 case 0x1: return "IAPSR";
5875 case 0x2: return "EAPSR";
5876 case 0x3: return "PSR";
5877 case 0x5: return "IPSR";
5878 case 0x6: return "EPSR";
5879 case 0x7: return "IEPSR";
5880 case 0x8: return "MSP";
5881 case 0x9: return "PSP";
5882 case 0xa: return "MSPLIM";
5883 case 0xb: return "PSPLIM";
5884 case 0x10: return "PRIMASK";
5885 case 0x11: return "BASEPRI";
5886 case 0x12: return "BASEPRI_MAX";
5887 case 0x13: return "FAULTMASK";
5888 case 0x14: return "CONTROL";
16a1fa25
TP		 5889 case 0x88: return "MSP_NS";
5890 case 0x89: return "PSP_NS";
1a336194
TP		 5891 case 0x8a: return "MSPLIM_NS";
5892 case 0x8b: return "PSPLIM_NS";
5893 case 0x90: return "PRIMASK_NS";
5894 case 0x91: return "BASEPRI_NS";
5895 case 0x93: return "FAULTMASK_NS";
5896 case 0x94: return "CONTROL_NS";
5897 case 0x98: return "SP_NS";
62b3e311
PB		 5898 default: return "<unknown>";
5899 }
5900}
5901
4a5329c6
ZW		 5902/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
5903
5904static void
5905print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 5906{
6b5d3a4d 5907 const struct opcode32 *insn;
c19d1205
ZW		 5908 void *stream = info->stream;
5909 fprintf_ftype func = info->fprintf_func;
73cd51e5 5910 bfd_boolean is_mve = is_mve_architecture (info);
c19d1205 5911
16980d0b
JB		 5912 if (print_insn_coprocessor (pc, info, given, TRUE))
5913 return;
5914
73cd51e5
AV		 5915 if ((is_mve == FALSE) && print_insn_neon (info, given, TRUE))
5916 return;
5917
5918 if (is_mve && print_insn_mve (info, given))
8f06b2d8
PB		 5919 return;
5920
c19d1205
ZW		 5921 for (insn = thumb32_opcodes; insn->assembler; insn++)
5922 if ((given & insn->mask) == insn->value)
5923 {
4b5a202f 5924 bfd_boolean is_clrm = FALSE;
ff4a8d2b 5925 bfd_boolean is_unpredictable = FALSE;
05413229 5926 signed long value_in_comment = 0;
6b5d3a4d 5927 const char *c = insn->assembler;
05413229 5928
c19d1205
ZW		 5929 for (; *c; c++)
5930 {
5931 if (*c != '%')
5932 {
5933 func (stream, "%c", *c);
5934 continue;
5935 }
5936
5937 switch (*++c)
5938 {
5939 case '%':
5940 func (stream, "%%");
5941 break;
5942
c22aaad1
PB		 5943 case 'c':
5944 if (ifthen_state)
5945 func (stream, "%s", arm_conditional[IFTHEN_COND]);
5946 break;
5947
5948 case 'x':
5949 if (ifthen_next_state)
5950 func (stream, "\t; unpredictable branch in IT block\n");
5951 break;
5952
5953 case 'X':
5954 if (ifthen_state)
5955 func (stream, "\t; unpredictable <IT:%s>",
5956 arm_conditional[IFTHEN_COND]);
5957 break;
5958
c19d1205
ZW		 5959 case 'I':
5960 {
5961 unsigned int imm12 = 0;
fe56b6ce 5962
c19d1205
ZW		 5963 imm12 |= (given & 0x000000ffu);
5964 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 5965 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 5966 func (stream, "#%u", imm12);
5967 value_in_comment = imm12;
c19d1205
ZW		 5968 }
5969 break;
5970
5971 case 'M':
5972 {
5973 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 5974
c19d1205
ZW		 5975 bits |= (given & 0x000000ffu);
5976 bits |= (given & 0x00007000u) >> 4;
5977 bits |= (given & 0x04000000u) >> 15;
5978 imm8 = (bits & 0x0ff);
5979 mod = (bits & 0xf00) >> 8;
5980 switch (mod)
5981 {
5982 case 0: imm = imm8; break;
c1e26897
NC		 5983 case 1: imm = ((imm8 << 16) | imm8); break;
5984 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
5985 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 5986 default:
5987 mod = (bits & 0xf80) >> 7;
5988 imm8 = (bits & 0x07f) | 0x80;
5989 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
5990 }
fe56b6ce
NC		 5991 func (stream, "#%u", imm);
5992 value_in_comment = imm;
c19d1205
ZW		 5993 }
5994 break;
43e65147 5995
c19d1205
ZW		 5996 case 'J':
5997 {
5998 unsigned int imm = 0;
fe56b6ce 5999
c19d1205
ZW		 6000 imm |= (given & 0x000000ffu);
6001 imm |= (given & 0x00007000u) >> 4;
6002 imm |= (given & 0x04000000u) >> 15;
6003 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 6004 func (stream, "#%u", imm);
6005 value_in_comment = imm;
c19d1205
ZW		 6006 }
6007 break;
6008
6009 case 'K':
6010 {
6011 unsigned int imm = 0;
fe56b6ce 6012
c19d1205
ZW		 6013 imm |= (given & 0x000f0000u) >> 16;
6014 imm |= (given & 0x00000ff0u) >> 0;
6015 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 6016 func (stream, "#%u", imm);
6017 value_in_comment = imm;
c19d1205
ZW		 6018 }
6019 break;
6020
74db7efb
NC		 6021 case 'H':
6022 {
6023 unsigned int imm = 0;
6024
6025 imm |= (given & 0x000f0000u) >> 4;
6026 imm |= (given & 0x00000fffu) >> 0;
6027 func (stream, "#%u", imm);
6028 value_in_comment = imm;
6029 }
6030 break;
6031
90ec0d68
MGD		 6032 case 'V':
6033 {
6034 unsigned int imm = 0;
6035
6036 imm |= (given & 0x00000fffu);
6037 imm |= (given & 0x000f0000u) >> 4;
6038 func (stream, "#%u", imm);
6039 value_in_comment = imm;
6040 }
6041 break;
6042
c19d1205
ZW		 6043 case 'S':
6044 {
6045 unsigned int reg = (given & 0x0000000fu);
6046 unsigned int stp = (given & 0x00000030u) >> 4;
6047 unsigned int imm = 0;
6048 imm |= (given & 0x000000c0u) >> 6;
6049 imm |= (given & 0x00007000u) >> 10;
6050
6051 func (stream, "%s", arm_regnames[reg]);
6052 switch (stp)
6053 {
6054 case 0:
6055 if (imm > 0)
6056 func (stream, ", lsl #%u", imm);
6057 break;
6058
6059 case 1:
6060 if (imm == 0)
6061 imm = 32;
6062 func (stream, ", lsr #%u", imm);
6063 break;
6064
6065 case 2:
6066 if (imm == 0)
6067 imm = 32;
6068 func (stream, ", asr #%u", imm);
6069 break;
6070
6071 case 3:
6072 if (imm == 0)
6073 func (stream, ", rrx");
6074 else
6075 func (stream, ", ror #%u", imm);
6076 }
6077 }
6078 break;
6079
6080 case 'a':
6081 {
6082 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 6083 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 6084 unsigned int op = (given & 0x00000f00) >> 8;
6085 unsigned int i12 = (given & 0x00000fff);
6086 unsigned int i8 = (given & 0x000000ff);
6087 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 6088 bfd_vma offset = 0;
c19d1205
ZW		 6089
6090 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 6091 if (U) /* 12-bit positive immediate offset. */
6092 {
6093 offset = i12;
6094 if (Rn != 15)
6095 value_in_comment = offset;
6096 }
6097 else if (Rn == 15) /* 12-bit negative immediate offset. */
6098 offset = - (int) i12;
6099 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 6100 {
6101 unsigned int Rm = (i8 & 0x0f);
6102 unsigned int sh = (i8 & 0x30) >> 4;
05413229 6103
c19d1205
ZW		 6104 func (stream, ", %s", arm_regnames[Rm]);
6105 if (sh)
6106 func (stream, ", lsl #%u", sh);
6107 func (stream, "]");
6108 break;
6109 }
6110 else switch (op)
6111 {
05413229 6112 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 6113 offset = i8;
6114 break;
6115
05413229 6116 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 6117 offset = -i8;
6118 break;
6119
05413229 6120 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 6121 offset = i8;
6122 writeback = TRUE;
6123 break;
6124
05413229 6125 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 6126 offset = -i8;
6127 writeback = TRUE;
6128 break;
6129
05413229 6130 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 6131 offset = i8;
6132 postind = TRUE;
6133 break;
6134
05413229 6135 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 6136 offset = -i8;
6137 postind = TRUE;
6138 break;
6139
6140 default:
6141 func (stream, ", <undefined>]");
6142 goto skip;
6143 }
6144
6145 if (postind)
d908c8af 6146 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 6147 else
6148 {
6149 if (offset)
d908c8af 6150 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 6151 func (stream, writeback ? "]!" : "]");
6152 }
6153
6154 if (Rn == 15)
6155 {
6156 func (stream, "\t; ");
6157 info->print_address_func (((pc + 4) & ~3) + offset, info);
6158 }
6159 }
6160 skip:
6161 break;
6162
6163 case 'A':
6164 {
c1e26897
NC		 6165 unsigned int U = ! NEGATIVE_BIT_SET;
6166 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 6167 unsigned int Rn = (given & 0x000f0000) >> 16;
6168 unsigned int off = (given & 0x000000ff);
6169
6170 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 6171
6172 if (PRE_BIT_SET)
c19d1205
ZW		 6173 {
6174 if (off || !U)
05413229
NC		 6175 {
6176 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
fe50e98c 6177 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 6178 }
c19d1205
ZW		 6179 func (stream, "]");
6180 if (W)
6181 func (stream, "!");
6182 }
6183 else
6184 {
6185 func (stream, "], ");
6186 if (W)
05413229
NC		 6187 {
6188 func (stream, "#%c%u", U ? '+' : '-', off * 4);
fe50e98c 6189 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 6190 }
c19d1205 6191 else
fe56b6ce
NC		 6192 {
6193 func (stream, "{%u}", off);
6194 value_in_comment = off;
6195 }
c19d1205
ZW		 6196 }
6197 }
6198 break;
6199
6200 case 'w':
6201 {
6202 unsigned int Sbit = (given & 0x01000000) >> 24;
6203 unsigned int type = (given & 0x00600000) >> 21;
05413229 6204
c19d1205
ZW		 6205 switch (type)
6206 {
6207 case 0: func (stream, Sbit ? "sb" : "b"); break;
6208 case 1: func (stream, Sbit ? "sh" : "h"); break;
6209 case 2:
6210 if (Sbit)
6211 func (stream, "??");
6212 break;
6213 case 3:
6214 func (stream, "??");
6215 break;
6216 }
6217 }
6218 break;
6219
4b5a202f
AV		 6220 case 'n':
6221 is_clrm = TRUE;
6222 /* Fall through. */
c19d1205
ZW		 6223 case 'm':
6224 {
6225 int started = 0;
6226 int reg;
6227
6228 func (stream, "{");
6229 for (reg = 0; reg < 16; reg++)
6230 if ((given & (1 << reg)) != 0)
6231 {
6232 if (started)
6233 func (stream, ", ");
6234 started = 1;
4b5a202f
AV		 6235 if (is_clrm && reg == 13)
6236 func (stream, "(invalid: %s)", arm_regnames[reg]);
6237 else if (is_clrm && reg == 15)
6238 func (stream, "%s", "APSR");
6239 else
6240 func (stream, "%s", arm_regnames[reg]);
c19d1205
ZW		 6241 }
6242 func (stream, "}");
6243 }
6244 break;
6245
6246 case 'E':
6247 {
6248 unsigned int msb = (given & 0x0000001f);
6249 unsigned int lsb = 0;
fe56b6ce 6250
c19d1205
ZW		 6251 lsb |= (given & 0x000000c0u) >> 6;
6252 lsb |= (given & 0x00007000u) >> 10;
6253 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
6254 }
6255 break;
6256
6257 case 'F':
6258 {
6259 unsigned int width = (given & 0x0000001f) + 1;
6260 unsigned int lsb = 0;
fe56b6ce 6261
c19d1205
ZW		 6262 lsb |= (given & 0x000000c0u) >> 6;
6263 lsb |= (given & 0x00007000u) >> 10;
6264 func (stream, "#%u, #%u", lsb, width);
6265 }
6266 break;
6267
e12437dc
AV		 6268 case 'G':
6269 {
6270 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
6271 func (stream, "%x", boff);
6272 }
6273 break;
6274
e5d6e09e
AV		 6275 case 'W':
6276 {
6277 unsigned int immA = (given & 0x001f0000u) >> 16;
6278 unsigned int immB = (given & 0x000007feu) >> 1;
6279 unsigned int immC = (given & 0x00000800u) >> 11;
6280 bfd_vma offset = 0;
6281
6282 offset |= immA << 12;
6283 offset |= immB << 2;
6284 offset |= immC << 1;
6285 /* Sign extend. */
6286 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
6287
6288 info->print_address_func (pc + 4 + offset, info);
6289 }
6290 break;
6291
1caf72a5
AV		 6292 case 'Y':
6293 {
6294 unsigned int immA = (given & 0x007f0000u) >> 16;
6295 unsigned int immB = (given & 0x000007feu) >> 1;
6296 unsigned int immC = (given & 0x00000800u) >> 11;
6297 bfd_vma offset = 0;
6298
6299 offset |= immA << 12;
6300 offset |= immB << 2;
6301 offset |= immC << 1;
6302 /* Sign extend. */
6303 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
6304
6305 info->print_address_func (pc + 4 + offset, info);
6306 }
6307 break;
6308
1889da70
AV		 6309 case 'Z':
6310 {
6311 unsigned int immA = (given & 0x00010000u) >> 16;
6312 unsigned int immB = (given & 0x000007feu) >> 1;
6313 unsigned int immC = (given & 0x00000800u) >> 11;
6314 bfd_vma offset = 0;
6315
6316 offset |= immA << 12;
6317 offset |= immB << 2;
6318 offset |= immC << 1;
6319 /* Sign extend. */
6320 offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
6321
6322 info->print_address_func (pc + 4 + offset, info);
f6b2b12d
AV		 6323
6324 unsigned int T = (given & 0x00020000u) >> 17;
6325 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
6326 unsigned int boffset = (T == 1) ? 4 : 2;
6327 func (stream, ", ");
6328 func (stream, "%x", endoffset + boffset);
1889da70
AV		 6329 }
6330 break;
6331
60f993ce
AV		 6332 case 'Q':
6333 {
6334 unsigned int immh = (given & 0x000007feu) >> 1;
6335 unsigned int imml = (given & 0x00000800u) >> 11;
6336 bfd_vma imm32 = 0;
6337
6338 imm32 |= immh << 2;
6339 imm32 |= imml << 1;
6340
6341 info->print_address_func (pc + 4 + imm32, info);
6342 }
6343 break;
6344
6345 case 'P':
6346 {
6347 unsigned int immh = (given & 0x000007feu) >> 1;
6348 unsigned int imml = (given & 0x00000800u) >> 11;
6349 bfd_vma imm32 = 0;
6350
6351 imm32 |= immh << 2;
6352 imm32 |= imml << 1;
6353
6354 info->print_address_func (pc + 4 - imm32, info);
6355 }
6356 break;
6357
c19d1205
ZW		 6358 case 'b':
6359 {
6360 unsigned int S = (given & 0x04000000u) >> 26;
6361 unsigned int J1 = (given & 0x00002000u) >> 13;
6362 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 6363 bfd_vma offset = 0;
c19d1205
ZW		 6364
6365 offset |= !S << 20;
6366 offset |= J2 << 19;
6367 offset |= J1 << 18;
6368 offset |= (given & 0x003f0000) >> 4;
6369 offset |= (given & 0x000007ff) << 1;
6370 offset -= (1 << 20);
6371
6372 info->print_address_func (pc + 4 + offset, info);
6373 }
6374 break;
6375
6376 case 'B':
6377 {
6378 unsigned int S = (given & 0x04000000u) >> 26;
6379 unsigned int I1 = (given & 0x00002000u) >> 13;
6380 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 6381 bfd_vma offset = 0;
c19d1205
ZW		 6382
6383 offset |= !S << 24;
6384 offset |= !(I1 ^ S) << 23;
6385 offset |= !(I2 ^ S) << 22;
6386 offset |= (given & 0x03ff0000u) >> 4;
6387 offset |= (given & 0x000007ffu) << 1;
6388 offset -= (1 << 24);
36b0c57d 6389 offset += pc + 4;
c19d1205 6390
36b0c57d
PB		 6391 /* BLX target addresses are always word aligned. */
6392 if ((given & 0x00001000u) == 0)
6393 offset &= ~2u;
6394
6395 info->print_address_func (offset, info);
c19d1205
ZW		 6396 }
6397 break;
6398
6399 case 's':
6400 {
6401 unsigned int shift = 0;
fe56b6ce 6402
c19d1205
ZW		 6403 shift |= (given & 0x000000c0u) >> 6;
6404 shift |= (given & 0x00007000u) >> 10;
c1e26897 6405 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 6406 func (stream, ", asr #%u", shift);
6407 else if (shift)
6408 func (stream, ", lsl #%u", shift);
6409 /* else print nothing - lsl #0 */
6410 }
6411 break;
6412
6413 case 'R':
6414 {
6415 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 6416
c19d1205
ZW		 6417 if (rot)
6418 func (stream, ", ror #%u", rot * 8);
6419 }
6420 break;
6421
62b3e311 6422 case 'U':
43e65147 6423 if ((given & 0xf0) == 0x60)
62b3e311 6424 {
52e7f43d
RE		 6425 switch (given & 0xf)
6426 {
6427 case 0xf: func (stream, "sy"); break;
6428 default:
6429 func (stream, "#%d", (int) given & 0xf);
6430 break;
6431 }
62b3e311 6432 }
43e65147 6433 else
52e7f43d 6434 {
e797f7e0
MGD		 6435 const char * opt = data_barrier_option (given & 0xf);
6436 if (opt != NULL)
6437 func (stream, "%s", opt);
6438 else
6439 func (stream, "#%d", (int) given & 0xf);
52e7f43d 6440 }
62b3e311
PB		 6441 break;
6442
6443 case 'C':
6444 if ((given & 0xff) == 0)
6445 {
6446 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
6447 if (given & 0x800)
6448 func (stream, "f");
6449 if (given & 0x400)
6450 func (stream, "s");
6451 if (given & 0x200)
6452 func (stream, "x");
6453 if (given & 0x100)
6454 func (stream, "c");
6455 }
90ec0d68
MGD		 6456 else if ((given & 0x20) == 0x20)
6457 {
6458 char const* name;
6459 unsigned sysm = (given & 0xf00) >> 8;
6460
6461 sysm |= (given & 0x30);
6462 sysm |= (given & 0x00100000) >> 14;
6463 name = banked_regname (sysm);
43e65147 6464
90ec0d68
MGD		 6465 if (name != NULL)
6466 func (stream, "%s", name);
6467 else
d908c8af 6468 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 6469 }
62b3e311
PB		 6470 else
6471 {
d908c8af 6472 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 6473 }
6474 break;
6475
6476 case 'D':
90ec0d68
MGD		 6477 if (((given & 0xff) == 0)
6478 || ((given & 0x20) == 0x20))
6479 {
6480 char const* name;
6481 unsigned sm = (given & 0xf0000) >> 16;
6482
6483 sm |= (given & 0x30);
6484 sm |= (given & 0x00100000) >> 14;
6485 name = banked_regname (sm);
6486
6487 if (name != NULL)
6488 func (stream, "%s", name);
6489 else
d908c8af 6490 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 6491 }
62b3e311 6492 else
d908c8af 6493 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 6494 break;
6495
c19d1205
ZW		 6496 case '0': case '1': case '2': case '3': case '4':
6497 case '5': case '6': case '7': case '8': case '9':
6498 {
16980d0b
JB		 6499 int width;
6500 unsigned long val;
c19d1205 6501
16980d0b 6502 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 6503
c19d1205
ZW		 6504 switch (*c)
6505 {
05413229
NC		 6506 case 'd':
6507 func (stream, "%lu", val);
6508 value_in_comment = val;
6509 break;
ff4a8d2b 6510
f0fba320
RL		 6511 case 'D':
6512 func (stream, "%lu", val + 1);
6513 value_in_comment = val + 1;
6514 break;
6515
05413229
NC		 6516 case 'W':
6517 func (stream, "%lu", val * 4);
6518 value_in_comment = val * 4;
6519 break;
ff4a8d2b 6520
f1c7f421
AV		 6521 case 'S':
6522 if (val == 13)
6523 is_unpredictable = TRUE;
6524 /* Fall through. */
ff4a8d2b
NC		 6525 case 'R':
6526 if (val == 15)
6527 is_unpredictable = TRUE;
6528 /* Fall through. */
6529 case 'r':
6530 func (stream, "%s", arm_regnames[val]);
6531 break;
c19d1205
ZW		 6532
6533 case 'c':
c22aaad1 6534 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 6535 break;
6536
6537 case '\'':
c19d1205 6538 c++;
16980d0b
JB		 6539 if (val == ((1ul << width) - 1))
6540 func (stream, "%c", *c);
c19d1205 6541 break;
43e65147 6542
c19d1205 6543 case '`':
c19d1205 6544 c++;
16980d0b
JB		 6545 if (val == 0)
6546 func (stream, "%c", *c);
c19d1205
ZW		 6547 break;
6548
6549 case '?':
fe56b6ce 6550 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 6551 c += 1 << width;
c19d1205 6552 break;
43e65147 6553
0bb027fd
RR		 6554 case 'x':
6555 func (stream, "0x%lx", val & 0xffffffffUL);
6556 break;
c19d1205
ZW		 6557
6558 default:
6559 abort ();
6560 }
6561 }
6562 break;
6563
32a94698
NC		 6564 case 'L':
6565 /* PR binutils/12534
6566 If we have a PC relative offset in an LDRD or STRD
6567 instructions then display the decoded address. */
6568 if (((given >> 16) & 0xf) == 0xf)
6569 {
6570 bfd_vma offset = (given & 0xff) * 4;
6571
6572 if ((given & (1 << 23)) == 0)
6573 offset = - offset;
6574 func (stream, "\t; ");
6575 info->print_address_func ((pc & ~3) + 4 + offset, info);
6576 }
6577 break;
6578
c19d1205
ZW		 6579 default:
6580 abort ();
6581 }
6582 }
05413229
NC		 6583
6584 if (value_in_comment > 32 || value_in_comment < -16)
6585 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 6586
6587 if (is_unpredictable)
6588 func (stream, UNPREDICTABLE_INSTRUCTION);
6589
4a5329c6 6590 return;
c19d1205 6591 }
252b5132 6592
58efb6c0 6593 /* No match. */
0b347048
TC		 6594 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
6595 return;
252b5132
RH		 6596}
6597
e821645d
DJ		 6598/* Print data bytes on INFO->STREAM. */
6599
6600static void
fe56b6ce
NC		 6601print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
6602 struct disassemble_info *info,
e821645d
DJ		 6603 long given)
6604{
6605 switch (info->bytes_per_chunk)
6606 {
6607 case 1:
6608 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
6609 break;
6610 case 2:
6611 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
6612 break;
6613 case 4:
6614 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
6615 break;
6616 default:
6617 abort ();
6618 }
6619}
6620
22a398e1 6621/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 6622 being displayed in symbol relative addresses.
6623
6624 Also disallow private symbol, with __tagsym$$ prefix,
6625 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 6626
6627bfd_boolean
6628arm_symbol_is_valid (asymbol * sym,
6629 struct disassemble_info * info ATTRIBUTE_UNUSED)
6630{
6631 const char * name;
43e65147 6632
22a398e1
NC		 6633 if (sym == NULL)
6634 return FALSE;
6635
6636 name = bfd_asymbol_name (sym);
6637
d8282f0e 6638 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 6639}
6640
65b48a81 6641/* Parse the string of disassembler options. */
baf0cc5e 6642
65b48a81 6643static void
f995bbe8 6644parse_arm_disassembler_options (const char *options)
dd92f639 6645{
f995bbe8 6646 const char *opt;
b34976b6 6647
65b48a81 6648 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
dd92f639 6649 {
65b48a81
PB		 6650 if (CONST_STRNEQ (opt, "reg-names-"))
6651 {
6652 unsigned int i;
6653 for (i = 0; i < NUM_ARM_OPTIONS; i++)
6654 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
6655 {
6656 regname_selected = i;
6657 break;
6658 }
b34976b6 6659
65b48a81 6660 if (i >= NUM_ARM_OPTIONS)
a6743a54
AM		 6661 /* xgettext: c-format */
6662 opcodes_error_handler (_("unrecognised register name set: %s"),
6663 opt);
65b48a81
PB		 6664 }
6665 else if (CONST_STRNEQ (opt, "force-thumb"))
6666 force_thumb = 1;
6667 else if (CONST_STRNEQ (opt, "no-force-thumb"))
6668 force_thumb = 0;
6669 else
a6743a54
AM		 6670 /* xgettext: c-format */
6671 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
dd92f639 6672 }
b34976b6 6673
dd92f639
NC		 6674 return;
6675}
6676
5bc5ae88
RL		 6677static bfd_boolean
6678mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6679 enum map_type *map_symbol);
6680
c22aaad1
PB		 6681/* Search back through the insn stream to determine if this instruction is
6682 conditionally executed. */
fe56b6ce 6683
c22aaad1 6684static void
fe56b6ce
NC		 6685find_ifthen_state (bfd_vma pc,
6686 struct disassemble_info *info,
c22aaad1
PB		 6687 bfd_boolean little)
6688{
6689 unsigned char b[2];
6690 unsigned int insn;
6691 int status;
6692 /* COUNT is twice the number of instructions seen. It will be odd if we
6693 just crossed an instruction boundary. */
6694 int count;
6695 int it_count;
6696 unsigned int seen_it;
6697 bfd_vma addr;
6698
6699 ifthen_address = pc;
6700 ifthen_state = 0;
6701
6702 addr = pc;
6703 count = 1;
6704 it_count = 0;
6705 seen_it = 0;
6706 /* Scan backwards looking for IT instructions, keeping track of where
6707 instruction boundaries are. We don't know if something is actually an
6708 IT instruction until we find a definite instruction boundary. */
6709 for (;;)
6710 {
fe56b6ce 6711 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 6712 {
6713 /* A symbol must be on an instruction boundary, and will not
6714 be within an IT block. */
6715 if (seen_it && (count & 1))
6716 break;
6717
6718 return;
6719 }
6720 addr -= 2;
fe56b6ce 6721 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 6722 if (status)
6723 return;
6724
6725 if (little)
6726 insn = (b[0]) | (b[1] << 8);
6727 else
6728 insn = (b[1]) | (b[0] << 8);
6729 if (seen_it)
6730 {
6731 if ((insn & 0xf800) < 0xe800)
6732 {
6733 /* Addr + 2 is an instruction boundary. See if this matches
6734 the expected boundary based on the position of the last
6735 IT candidate. */
6736 if (count & 1)
6737 break;
6738 seen_it = 0;
6739 }
6740 }
6741 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
6742 {
5bc5ae88
RL		 6743 enum map_type type = MAP_ARM;
6744 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
6745
6746 if (!found || (found && type == MAP_THUMB))
6747 {
6748 /* This could be an IT instruction. */
6749 seen_it = insn;
6750 it_count = count >> 1;
6751 }
c22aaad1
PB		 6752 }
6753 if ((insn & 0xf800) >= 0xe800)
6754 count++;
6755 else
6756 count = (count + 2) | 1;
6757 /* IT blocks contain at most 4 instructions. */
6758 if (count >= 8 && !seen_it)
6759 return;
6760 }
6761 /* We found an IT instruction. */
6762 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
6763 if ((ifthen_state & 0xf) == 0)
6764 ifthen_state = 0;
6765}
6766
b0e28b39
DJ		 6767/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
6768 mapping symbol. */
6769
6770static int
6771is_mapping_symbol (struct disassemble_info *info, int n,
6772 enum map_type *map_type)
6773{
6774 const char *name;
6775
6776 name = bfd_asymbol_name (info->symtab[n]);
6777 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
6778 && (name[2] == 0 || name[2] == '.'))
6779 {
6780 *map_type = ((name[1] == 'a') ? MAP_ARM
6781 : (name[1] == 't') ? MAP_THUMB
6782 : MAP_DATA);
6783 return TRUE;
6784 }
6785
6786 return FALSE;
6787}
6788
6789/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
6790 Returns nonzero if *MAP_TYPE was set. */
6791
6792static int
6793get_map_sym_type (struct disassemble_info *info,
6794 int n,
6795 enum map_type *map_type)
6796{
6797 /* If the symbol is in a different section, ignore it. */
6798 if (info->section != NULL && info->section != info->symtab[n]->section)
6799 return FALSE;
6800
6801 return is_mapping_symbol (info, n, map_type);
6802}
6803
6804/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 6805 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 6806
6807static int
fe56b6ce
NC		 6808get_sym_code_type (struct disassemble_info *info,
6809 int n,
e821645d 6810 enum map_type *map_type)
2087ad84
PB		 6811{
6812 elf_symbol_type *es;
6813 unsigned int type;
b0e28b39
DJ		 6814
6815 /* If the symbol is in a different section, ignore it. */
6816 if (info->section != NULL && info->section != info->symtab[n]->section)
6817 return FALSE;
2087ad84 6818
e821645d 6819 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 6820 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6821
6822 /* If the symbol has function type then use that. */
34e77a92 6823 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 6824 {
39d911fc
TP		 6825 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6826 == ST_BRANCH_TO_THUMB)
35fc36a8
RS		 6827 *map_type = MAP_THUMB;
6828 else
6829 *map_type = MAP_ARM;
2087ad84
PB		 6830 return TRUE;
6831 }
6832
2087ad84
PB		 6833 return FALSE;
6834}
6835
5bc5ae88
RL		 6836/* Search the mapping symbol state for instruction at pc. This is only
6837 applicable for elf target.
6838
6839 There is an assumption Here, info->private_data contains the correct AND
6840 up-to-date information about current scan process. The information will be
6841 used to speed this search process.
6842
6843 Return TRUE if the mapping state can be determined, and map_symbol
6844 will be updated accordingly. Otherwise, return FALSE. */
6845
6846static bfd_boolean
6847mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6848 enum map_type *map_symbol)
6849{
796d6298
TC		 6850 bfd_vma addr, section_vma = 0;
6851 int n, last_sym = -1;
5bc5ae88 6852 bfd_boolean found = FALSE;
796d6298
TC		 6853 bfd_boolean can_use_search_opt_p = FALSE;
6854
6855 /* Default to DATA. A text section is required by the ABI to contain an
6856 INSN mapping symbol at the start. A data section has no such
6857 requirement, hence if no mapping symbol is found the section must
6858 contain only data. This however isn't very useful if the user has
6859 fully stripped the binaries. If this is the case use the section
6860 attributes to determine the default. If we have no section default to
6861 INSN as well, as we may be disassembling some raw bytes on a baremetal
6862 HEX file or similar. */
6863 enum map_type type = MAP_DATA;
6864 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
6865 type = MAP_ARM;
5bc5ae88
RL		 6866 struct arm_private_data *private_data;
6867
796d6298 6868 if (info->private_data == NULL
5bc5ae88
RL		 6869 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
6870 return FALSE;
6871
6872 private_data = info->private_data;
5bc5ae88 6873
796d6298
TC		 6874 /* First, look for mapping symbols. */
6875 if (info->symtab_size != 0)
6876 {
6877 if (pc <= private_data->last_mapping_addr)
6878 private_data->last_mapping_sym = -1;
6879
6880 /* Start scanning at the start of the function, or wherever
6881 we finished last time. */
6882 n = info->symtab_pos + 1;
6883
6884 /* If the last stop offset is different from the current one it means we
6885 are disassembling a different glob of bytes. As such the optimization
6886 would not be safe and we should start over. */
6887 can_use_search_opt_p
6888 = private_data->last_mapping_sym >= 0
6889 && info->stop_offset == private_data->last_stop_offset;
6890
6891 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
6892 n = private_data->last_mapping_sym;
6893
6894 /* Look down while we haven't passed the location being disassembled.
6895 The reason for this is that there's no defined order between a symbol
6896 and an mapping symbol that may be at the same address. We may have to
6897 look at least one position ahead. */
6898 for (; n < info->symtab_size; n++)
6899 {
6900 addr = bfd_asymbol_value (info->symtab[n]);
6901 if (addr > pc)
6902 break;
6903 if (get_map_sym_type (info, n, &type))
6904 {
6905 last_sym = n;
6906 found = TRUE;
6907 }
6908 }
5bc5ae88 6909
796d6298
TC		 6910 if (!found)
6911 {
6912 n = info->symtab_pos;
6913 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
6914 n = private_data->last_mapping_sym;
6915
6916 /* No mapping symbol found at this address. Look backwards
6917 for a preceeding one, but don't go pass the section start
6918 otherwise a data section with no mapping symbol can pick up
6919 a text mapping symbol of a preceeding section. The documentation
6920 says section can be NULL, in which case we will seek up all the
6921 way to the top. */
6922 if (info->section)
6923 section_vma = info->section->vma;
6924
6925 for (; n >= 0; n--)
6926 {
6927 addr = bfd_asymbol_value (info->symtab[n]);
6928 if (addr < section_vma)
6929 break;
6930
6931 if (get_map_sym_type (info, n, &type))
6932 {
6933 last_sym = n;
6934 found = TRUE;
6935 break;
6936 }
6937 }
6938 }
6939 }
6940
6941 /* If no mapping symbol was found, try looking up without a mapping
6942 symbol. This is done by walking up from the current PC to the nearest
6943 symbol. We don't actually have to loop here since symtab_pos will
6944 contain the nearest symbol already. */
6945 if (!found)
5bc5ae88 6946 {
796d6298
TC		 6947 n = info->symtab_pos;
6948 if (n >= 0 && get_sym_code_type (info, n, &type))
5bc5ae88 6949 {
796d6298
TC		 6950 last_sym = n;
6951 found = TRUE;
5bc5ae88
RL		 6952 }
6953 }
6954
796d6298
TC		 6955 private_data->last_mapping_sym = last_sym;
6956 private_data->last_type = type;
6957 private_data->last_stop_offset = info->stop_offset;
5bc5ae88
RL		 6958
6959 *map_symbol = type;
6960 return found;
6961}
6962
0313a2b8
NC		 6963/* Given a bfd_mach_arm_XXX value, this function fills in the fields
6964 of the supplied arm_feature_set structure with bitmasks indicating
c0c468d5 6965 the supported base architectures and coprocessor extensions.
0313a2b8
NC		 6966
6967 FIXME: This could more efficiently implemented as a constant array,
6968 although it would also be less robust. */
6969
6970static void
6971select_arm_features (unsigned long mach,
6972 arm_feature_set * features)
6973{
c0c468d5
TP		 6974 arm_feature_set arch_fset;
6975 const arm_feature_set fpu_any = FPU_ANY;
6976
1af1dd51
MW		 6977#undef ARM_SET_FEATURES
6978#define ARM_SET_FEATURES(FSET) \
6979 { \
6980 const arm_feature_set fset = FSET; \
c0c468d5 6981 arch_fset = fset; \
1af1dd51 6982 }
823d2571 6983
c0c468d5
TP		 6984 /* When several architecture versions share the same bfd_mach_arm_XXX value
6985 the most featureful is chosen. */
0313a2b8
NC		 6986 switch (mach)
6987 {
c0c468d5
TP		 6988 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
6989 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
6990 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
6991 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
6992 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
6993 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
6994 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
6995 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
6996 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
6997 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
1af1dd51 6998 case bfd_mach_arm_ep9312:
c0c468d5
TP		 6999 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
7000 ARM_CEXT_MAVERICK | FPU_MAVERICK));
1af1dd51 7001 break;
c0c468d5
TP		 7002 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
7003 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
7004 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
7005 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
7006 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
7007 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
7008 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
7009 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
7010 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
7011 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
7012 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
7013 case bfd_mach_arm_8:
7014 {
0632eeea
SD		 7015 /* Add bits for extensions that Armv8.5-A recognizes. */
7016 arm_feature_set armv8_5_ext_fset
7017 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
7018 ARM_SET_FEATURES (ARM_ARCH_V8_5A);
7019 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset);
c0c468d5
TP		 7020 break;
7021 }
7022 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
7023 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
7024 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
73cd51e5
AV		 7025 case bfd_mach_arm_8_1M_MAIN:
7026 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
7027 force_thumb = 1;
7028 break;
c0c468d5
TP		 7029 /* If the machine type is unknown allow all architecture types and all
7030 extensions. */
7031 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
0313a2b8
NC		 7032 default:
7033 abort ();
7034 }
1af1dd51 7035#undef ARM_SET_FEATURES
c0c468d5
TP		 7036
7037 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
7038 and thus on bfd_mach_arm_XXX value. Therefore for a given
7039 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
7040 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
0313a2b8
NC		 7041}
7042
7043
58efb6c0
NC		 7044/* NOTE: There are no checks in these routines that
7045 the relevant number of data bytes exist. */
baf0cc5e 7046
58efb6c0 7047static int
4a5329c6 7048print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 7049{
c19d1205
ZW		 7050 unsigned char b[4];
7051 long given;
7052 int status;
e821645d 7053 int is_thumb = FALSE;
b0e28b39 7054 int is_data = FALSE;
bd2e2557 7055 int little_code;
e821645d 7056 unsigned int size = 4;
4a5329c6 7057 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 7058 bfd_boolean found = FALSE;
b0e28b39 7059 struct arm_private_data *private_data;
58efb6c0 7060
dd92f639
NC		 7061 if (info->disassembler_options)
7062 {
65b48a81 7063 parse_arm_disassembler_options (info->disassembler_options);
b34976b6 7064
58efb6c0 7065 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 7066 info->disassembler_options = NULL;
7067 }
b34976b6 7068
0313a2b8
NC		 7069 /* PR 10288: Control which instructions will be disassembled. */
7070 if (info->private_data == NULL)
7071 {
b0e28b39 7072 static struct arm_private_data private;
0313a2b8
NC		 7073
7074 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
7075 /* If the user did not use the -m command line switch then default to
7076 disassembling all types of ARM instruction.
43e65147 7077
0313a2b8
NC		 7078 The info->mach value has to be ignored as this will be based on
7079 the default archictecture for the target and/or hints in the notes
7080 section, but it will never be greater than the current largest arm
7081 machine value (iWMMXt2), which is only equivalent to the V5TE
7082 architecture. ARM architectures have advanced beyond the machine
7083 value encoding, and these newer architectures would be ignored if
7084 the machine value was used.
7085
7086 Ie the -m switch is used to restrict which instructions will be
7087 disassembled. If it is necessary to use the -m switch to tell
7088 objdump that an ARM binary is being disassembled, eg because the
7089 input is a raw binary file, but it is also desired to disassemble
7090 all ARM instructions then use "-marm". This will select the
7091 "unknown" arm architecture which is compatible with any ARM
7092 instruction. */
7093 info->mach = bfd_mach_arm_unknown;
7094
7095 /* Compute the architecture bitmask from the machine number.
7096 Note: This assumes that the machine number will not change
7097 during disassembly.... */
b0e28b39 7098 select_arm_features (info->mach, & private.features);
0313a2b8 7099
1fbaefec
PB		 7100 private.last_mapping_sym = -1;
7101 private.last_mapping_addr = 0;
796d6298 7102 private.last_stop_offset = 0;
b0e28b39
DJ		 7103
7104 info->private_data = & private;
0313a2b8 7105 }
b0e28b39
DJ		 7106
7107 private_data = info->private_data;
7108
bd2e2557
SS		 7109 /* Decide if our code is going to be little-endian, despite what the
7110 function argument might say. */
7111 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
7112
b0e28b39
DJ		 7113 /* For ELF, consult the symbol table to determine what kind of code
7114 or data we have. */
8977d4b2 7115 if (info->symtab_size != 0
e821645d
DJ		 7116 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
7117 {
7118 bfd_vma addr;
796d6298 7119 int n;
e821645d 7120 int last_sym = -1;
b0e28b39 7121 enum map_type type = MAP_ARM;
e821645d 7122
796d6298
TC		 7123 found = mapping_symbol_for_insn (pc, info, &type);
7124 last_sym = private_data->last_mapping_sym;
e821645d 7125
1fbaefec
PB		 7126 is_thumb = (private_data->last_type == MAP_THUMB);
7127 is_data = (private_data->last_type == MAP_DATA);
b34976b6 7128
e821645d
DJ		 7129 /* Look a little bit ahead to see if we should print out
7130 two or four bytes of data. If there's a symbol,
7131 mapping or otherwise, after two bytes then don't
7132 print more. */
7133 if (is_data)
7134 {
7135 size = 4 - (pc & 3);
7136 for (n = last_sym + 1; n < info->symtab_size; n++)
7137 {
7138 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 7139 if (addr > pc
7140 && (info->section == NULL
7141 || info->section == info->symtab[n]->section))
e821645d
DJ		 7142 {
7143 if (addr - pc < size)
7144 size = addr - pc;
7145 break;
7146 }
7147 }
7148 /* If the next symbol is after three bytes, we need to
7149 print only part of the data, so that we can use either
7150 .byte or .short. */
7151 if (size == 3)
7152 size = (pc & 1) ? 1 : 2;
7153 }
7154 }
7155
7156 if (info->symbols != NULL)
252b5132 7157 {
5876e06d
NC		 7158 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
7159 {
2f0ca46a 7160 coff_symbol_type * cs;
b34976b6 7161
5876e06d
NC		 7162 cs = coffsymbol (*info->symbols);
7163 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
7164 || cs->native->u.syment.n_sclass == C_THUMBSTAT
7165 || cs->native->u.syment.n_sclass == C_THUMBLABEL
7166 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
7167 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
7168 }
e821645d
DJ		 7169 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
7170 && !found)
5876e06d 7171 {
2087ad84
PB		 7172 /* If no mapping symbol has been found then fall back to the type
7173 of the function symbol. */
e821645d
DJ		 7174 elf_symbol_type * es;
7175 unsigned int type;
2087ad84 7176
e821645d
DJ		 7177 es = *(elf_symbol_type **)(info->symbols);
7178 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 7179
39d911fc
TP		 7180 is_thumb =
7181 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
7182 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
5876e06d 7183 }
e49d43ff
TG		 7184 else if (bfd_asymbol_flavour (*info->symbols)
7185 == bfd_target_mach_o_flavour)
7186 {
7187 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
7188
7189 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
7190 }
5876e06d 7191 }
b34976b6 7192
e821645d
DJ		 7193 if (force_thumb)
7194 is_thumb = TRUE;
7195
b8f9ee44
CL		 7196 if (is_data)
7197 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
7198 else
7199 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
7200
c19d1205 7201 info->bytes_per_line = 4;
252b5132 7202
1316c8b3
NC		 7203 /* PR 10263: Disassemble data if requested to do so by the user. */
7204 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 7205 {
7206 int i;
7207
1316c8b3 7208 /* Size was already set above. */
e821645d
DJ		 7209 info->bytes_per_chunk = size;
7210 printer = print_insn_data;
7211
fe56b6ce 7212 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 7213 given = 0;
7214 if (little)
7215 for (i = size - 1; i >= 0; i--)
7216 given = b[i] | (given << 8);
7217 else
7218 for (i = 0; i < (int) size; i++)
7219 given = b[i] | (given << 8);
7220 }
7221 else if (!is_thumb)
252b5132 7222 {
c19d1205
ZW		 7223 /* In ARM mode endianness is a straightforward issue: the instruction
7224 is four bytes long and is either ordered 0123 or 3210. */
7225 printer = print_insn_arm;
7226 info->bytes_per_chunk = 4;
4a5329c6 7227 size = 4;
c19d1205 7228
0313a2b8 7229 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 7230 if (little_code)
c19d1205
ZW		 7231 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
7232 else
7233 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
252b5132 7234 }
58efb6c0 7235 else
252b5132 7236 {
c19d1205
ZW		 7237 /* In Thumb mode we have the additional wrinkle of two
7238 instruction lengths. Fortunately, the bits that determine
7239 the length of the current instruction are always to be found
7240 in the first two bytes. */
4a5329c6 7241 printer = print_insn_thumb16;
c19d1205 7242 info->bytes_per_chunk = 2;
4a5329c6
ZW		 7243 size = 2;
7244
fe56b6ce 7245 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 7246 if (little_code)
9a2ff3f5
AM		 7247 given = (b[0]) | (b[1] << 8);
7248 else
7249 given = (b[1]) | (b[0] << 8);
7250
c19d1205 7251 if (!status)
252b5132 7252 {
c19d1205
ZW		 7253 /* These bit patterns signal a four-byte Thumb
7254 instruction. */
7255 if ((given & 0xF800) == 0xF800
7256 || (given & 0xF800) == 0xF000
7257 || (given & 0xF800) == 0xE800)
252b5132 7258 {
0313a2b8 7259 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 7260 if (little_code)
c19d1205 7261 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 7262 else
c19d1205
ZW		 7263 given = (b[1]) | (b[0] << 8) | (given << 16);
7264
7265 printer = print_insn_thumb32;
4a5329c6 7266 size = 4;
252b5132 7267 }
252b5132 7268 }
c22aaad1
PB		 7269
7270 if (ifthen_address != pc)
0313a2b8 7271 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 7272
7273 if (ifthen_state)
7274 {
7275 if ((ifthen_state & 0xf) == 0x8)
7276 ifthen_next_state = 0;
7277 else
7278 ifthen_next_state = (ifthen_state & 0xe0)
7279 | ((ifthen_state & 0xf) << 1);
7280 }
252b5132 7281 }
b34976b6 7282
c19d1205
ZW		 7283 if (status)
7284 {
7285 info->memory_error_func (status, pc, info);
7286 return -1;
7287 }
6a56ec7e
NC		 7288 if (info->flags & INSN_HAS_RELOC)
7289 /* If the instruction has a reloc associated with it, then
7290 the offset field in the instruction will actually be the
7291 addend for the reloc. (We are using REL type relocs).
7292 In such cases, we can ignore the pc when computing
7293 addresses, since the addend is not currently pc-relative. */
7294 pc = 0;
b34976b6 7295
4a5329c6 7296 printer (pc, info, given);
c22aaad1
PB		 7297
7298 if (is_thumb)
7299 {
7300 ifthen_state = ifthen_next_state;
7301 ifthen_address += size;
7302 }
4a5329c6 7303 return size;
252b5132
RH		 7304}
7305
7306int
4a5329c6 7307print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 7308{
bd2e2557
SS		 7309 /* Detect BE8-ness and record it in the disassembler info. */
7310 if (info->flavour == bfd_target_elf_flavour
7311 && info->section != NULL
7312 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
7313 info->endian_code = BFD_ENDIAN_LITTLE;
7314
b34976b6 7315 return print_insn (pc, info, FALSE);
58efb6c0 7316}
01c7f630 7317
58efb6c0 7318int
4a5329c6 7319print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 7320{
b34976b6 7321 return print_insn (pc, info, TRUE);
58efb6c0 7322}
252b5132 7323
471b9d15 7324const disasm_options_and_args_t *
65b48a81
PB		 7325disassembler_options_arm (void)
7326{
471b9d15 7327 static disasm_options_and_args_t *opts_and_args;
65b48a81 7328
471b9d15 7329 if (opts_and_args == NULL)
65b48a81 7330 {
471b9d15 7331 disasm_options_t *opts;
65b48a81 7332 unsigned int i;
471b9d15
MR		 7333
7334 opts_and_args = XNEW (disasm_options_and_args_t);
7335 opts_and_args->args = NULL;
7336
7337 opts = &opts_and_args->options;
65b48a81
PB		 7338 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
7339 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
471b9d15 7340 opts->arg = NULL;
65b48a81
PB		 7341 for (i = 0; i < NUM_ARM_OPTIONS; i++)
7342 {
7343 opts->name[i] = regnames[i].name;
7344 if (regnames[i].description != NULL)
7345 opts->description[i] = _(regnames[i].description);
7346 else
7347 opts->description[i] = NULL;
7348 }
7349 /* The array we return must be NULL terminated. */
7350 opts->name[i] = NULL;
7351 opts->description[i] = NULL;
7352 }
7353
471b9d15 7354 return opts_and_args;
65b48a81
PB		 7355}
7356
58efb6c0 7357void
4a5329c6 7358print_arm_disassembler_options (FILE *stream)
58efb6c0 7359{
65b48a81 7360 unsigned int i, max_len = 0;
58efb6c0
NC		 7361 fprintf (stream, _("\n\
7362The following ARM specific disassembler options are supported for use with\n\
7363the -M switch:\n"));
b34976b6 7364
65b48a81
PB		 7365 for (i = 0; i < NUM_ARM_OPTIONS; i++)
7366 {
7367 unsigned int len = strlen (regnames[i].name);
7368 if (max_len < len)
7369 max_len = len;
7370 }
58efb6c0 7371
65b48a81
PB		 7372 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
7373 fprintf (stream, " %s%*c %s\n",
7374 regnames[i].name,
7375 (int)(max_len - strlen (regnames[i].name)), ' ',
7376 _(regnames[i].description));
252b5132 7377}
GDB Binutils - Deliverables
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