[deliverable/binutils-gdb.git] / opcodes / avr-dis.c

/* Disassemble AVR instructions.
   Copyright (C) 1999, 2000 Free Software Foundation, Inc.

   Contributed by Denis Chertykov <denisc@overta.ru>

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

#include <assert.h>
#include "sysdep.h"
#include "dis-asm.h"
#include "opintl.h"


struct avr_opcodes_s
{
  char *name;
  char *constraints;
  char *opcode;
  int insn_size;		/* in words */
  int isa;
  unsigned int bin_opcode;
  unsigned int bin_mask;
};

#define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
{#NAME, CONSTR, OPCODE, SIZE, ISA, BIN, 0},

struct avr_opcodes_s avr_opcodes[] =
{
  #include "opcode/avr.h"
  {NULL, NULL, NULL, 0, 0, 0, 0}
};


static void avr_operand (unsigned int insn, unsigned int insn2,
			 unsigned int pc, int constraint, char *buf,
			 char *comment, int regs);

static void
avr_operand (insn, insn2, pc, constraint, buf, comment, regs)
     unsigned int insn;
     unsigned int insn2;
     unsigned int pc;
     int constraint;
     char *buf;
     char *comment;
     int regs;
{
  switch (constraint)
    {
      /* Any register operand.  */
    case 'r':
      if (regs)
	insn = (insn & 0xf) | ((insn & 0x0200) >> 5); /* source register */
      else
	insn = (insn & 0x01f0) >> 4; /* destination register */
      
      sprintf (buf, "r%d", insn);
      break;

    case 'd':
      if (regs)
	sprintf (buf, "r%d", 16 + (insn & 0xf));
      else
	sprintf (buf, "r%d", 16 + ((insn & 0xf0) >> 4));
      break;
      
    case 'w':
      sprintf (buf, "r%d", 24 + ((insn & 0x30) >> 3));
      break;
      
    case 'a':
      if (regs)
	sprintf (buf, "r%d", 16 + (insn & 7));
      else
	sprintf (buf, "r%d", 16 + ((insn >> 4) & 7));
      break;

    case 'v':
      if (regs)
	sprintf (buf, "r%d", (insn & 0xf) * 2);
      else
	sprintf (buf, "r%d", ((insn & 0xf0) >> 3));
      break;

    case 'e':
      if (insn & 0x2)
	*buf++ = '-';
      switch ((insn >> 2) & 0x3)
	{
	case 0: *buf++ = 'Z'; break;
	case 2: *buf++ = 'Y'; break;
	case 3: *buf++ = 'X'; break;
	default: buf += sprintf (buf, _(" unknown register ")); break;
	}
      if (insn & 0x1)
	*buf++ = '+';
      *buf = '\0';
      break;

    case 'z':
      *buf++ = 'Z';
      if (insn & 0x1)
	*buf++ = '+';
      *buf = '\0';
      break;

    case 'b':
      {
	unsigned int x = insn;
	
	x = (insn & 7);
	x |= (insn >> 7) & (3 << 3);
	x |= (insn >> 8) & (1 << 5);
	
	if (insn & 0x8)
	  *buf++ = 'Y';
	else
	  *buf++ = 'Z';
	sprintf (buf, "+%d", x);
	sprintf (comment, "0x%02x", x);
      }
      break;
      
    case 'h':
      sprintf (buf, "0x%x",
	       ((((insn & 1) | ((insn & 0x1f0) >> 3)) << 16) | insn2) * 2);
      break;
      
    case 'L':
      {
	int rel_addr = (((insn & 0xfff) ^ 0x800) - 0x800) * 2;
	sprintf (buf, ".%+-8d", rel_addr);
	sprintf (comment, "0x%x", pc + 2 + rel_addr);
      }
      break;

    case 'l':
      {
	int rel_addr = ((((insn >> 3) & 0x7f) ^ 0x40) - 0x40) * 2;
	sprintf (buf, ".%+-8d", rel_addr);
	sprintf (comment, "0x%x", pc + 2 + rel_addr);
      }
      break;

    case 'i':
      sprintf (buf, "0x%04X", insn2);
      break;
      
    case 'M':
      sprintf (buf, "0x%02X", ((insn & 0xf00) >> 4) | (insn & 0xf));
      sprintf (comment, "%d", ((insn & 0xf00) >> 4) | (insn & 0xf));
      break;

    case 'n':
      sprintf (buf, _("Internal disassembler error"));
      break;
      
    case 'K':
      sprintf (buf, "%d", (insn & 0xf) | ((insn >> 2) & 0x30));
      break;
      
    case 's':
      sprintf (buf, "%d", insn & 7);
      break;
      
    case 'S':
      sprintf (buf, "%d", (insn >> 4) & 7);
      break;
      
    case 'P':
      {
	unsigned int x;
	x = (insn & 0xf);
	x |= (insn >> 5) & 0x30;
	sprintf (buf, "0x%02x", x);
	sprintf (comment, "%d", x);
      }
      break;

    case 'p':
      {
	unsigned int x;
	
	x = (insn >> 3) & 0x1f;
	sprintf (buf, "0x%02x", x);
	sprintf (comment, "%d", x);
      }
      break;
      
    case '?':
      *buf = '\0';
      break;
      
    default:
      sprintf (buf, _("unknown constraint `%c'"), constraint);
    }
}

static unsigned short avrdis_opcode PARAMS ((bfd_vma, disassemble_info *));

static unsigned short
avrdis_opcode (addr, info)
     bfd_vma addr;
     disassemble_info *info;
{
  bfd_byte buffer[2];
  int status;
  status = info->read_memory_func(addr, buffer, 2, info);
  if (status != 0)
    {
      info->memory_error_func(status, addr, info);
      return -1;
    }
  return bfd_getl16 (buffer);
}


int
print_insn_avr(addr, info)
     bfd_vma addr;
     disassemble_info *info;
{
  unsigned int insn, insn2;
  struct avr_opcodes_s *opcode;
  void *stream = info->stream;
  fprintf_ftype prin = info->fprintf_func;
  static int initialized;
  int cmd_len = 2;

  if (!initialized)
    {
      initialized = 1;
      
      for (opcode = avr_opcodes; opcode->name; opcode++)
	{
	  char * s;
	  unsigned int bin = 0;
	  unsigned int mask = 0;
	
	  for (s = opcode->opcode; *s; ++s)
	    {
	      bin <<= 1;
	      mask <<= 1;
	      bin |= (*s == '1');
	      mask |= (*s == '1' || *s == '0');
	    }
	  assert (s - opcode->opcode == 16);
	  assert (opcode->bin_opcode == bin);
	  opcode->bin_mask = mask;
	}
    }

  insn = avrdis_opcode (addr, info);
  
  for (opcode = avr_opcodes; opcode->name; opcode++)
    {
      if ((insn & opcode->bin_mask) == opcode->bin_opcode)
	break;
    }
  
  if (opcode->name)
    {
      char op1[20], op2[20], comment1[40], comment2[40];
      char *op = opcode->constraints;

      op1[0] = 0;
      op2[0] = 0;
      comment1[0] = 0;
      comment2[0] = 0;
      insn2 = 0;

      if (opcode->insn_size > 1)
	{
	  insn2 = avrdis_opcode (addr + 2, info);
	  cmd_len = 4;
	}

      if (*op && *op != '?')
	{
	  int regs = REGISTER_P (*op);

	  avr_operand (insn, insn2, addr, *op, op1, comment1, 0);

	  if (*(++op) == ',')
	    avr_operand (insn, insn2, addr, *(++op), op2,
			 *comment1 ? comment2 : comment1, regs);
	}

      (*prin) (stream, "    %-8s", opcode->name);

      if (*op1)
	(*prin) (stream, "%s", op1);

      if (*op2)
	(*prin) (stream, ", %s", op2);

      if (*comment1)
	(*prin) (stream, "\t; %s", comment1);

      if (*comment2)
	(*prin) (stream, " %s", comment2);
    }
  else
   (*prin) (stream, ".word 0x%04x\t; ????", insn);
  
  return cmd_len;
}
Commit	Line	Data
adde6300 AM	1	/* Disassemble AVR instructions.
	2	Copyright (C) 1999, 2000 Free Software Foundation, Inc.
	3
	4	Contributed by Denis Chertykov <denisc@overta.ru>
	5
	6	This program is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
	8	the Free Software Foundation; either version 2 of the License, or
	9	(at your option) any later version.
	10
	11	This program is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public License
	17	along with this program; if not, write to the Free Software
	18	Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
	19
bab84c47	20	#include <assert.h>
0d8dfecf	21	#include "sysdep.h"
adde6300 AM	22	#include "dis-asm.h"
	23	#include "opintl.h"
	24
3c504221	25
bab84c47	26	struct avr_opcodes_s
adde6300	27	{
bab84c47 DC	28	char *name;
	29	char *constraints;
	30	char *opcode;
	31	int insn_size; /* in words */
	32	int isa;
	33	unsigned int bin_opcode;
	34	unsigned int bin_mask;
	35	};
adde6300	36
bab84c47 DC	37	#define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
bab84c47 DC	38	{#NAME, CONSTR, OPCODE, SIZE, ISA, BIN, 0},
adde6300	39
bab84c47	40	struct avr_opcodes_s avr_opcodes[] =
adde6300	41	{
bab84c47 DC	42	#include "opcode/avr.h"
	43	{NULL, NULL, NULL, 0, 0, 0, 0}
	44	};
adde6300 AM	45
adde6300 AM	46
bab84c47 DC	47	static void avr_operand (unsigned int insn, unsigned int insn2,
	48	unsigned int pc, int constraint, char *buf,
	49	char *comment, int regs);
adde6300 AM	50
adde6300 AM	51	static void
bab84c47 DC	52	avr_operand (insn, insn2, pc, constraint, buf, comment, regs)
	53	unsigned int insn;
	54	unsigned int insn2;
	55	unsigned int pc;
	56	int constraint;
	57	char *buf;
	58	char *comment;
	59	int regs;
adde6300	60	{
bab84c47 DC	61	switch (constraint)
	62	{
	63	/* Any register operand. */
	64	case 'r':
	65	if (regs)
	66	insn = (insn & 0xf) \| ((insn & 0x0200) >> 5); /* source register */
	67	else
	68	insn = (insn & 0x01f0) >> 4; /* destination register */
	69
	70	sprintf (buf, "r%d", insn);
	71	break;
	72
	73	case 'd':
	74	if (regs)
	75	sprintf (buf, "r%d", 16 + (insn & 0xf));
	76	else
	77	sprintf (buf, "r%d", 16 + ((insn & 0xf0) >> 4));
	78	break;
	79
	80	case 'w':
	81	sprintf (buf, "r%d", 24 + ((insn & 0x30) >> 3));
	82	break;
	83
	84	case 'a':
	85	if (regs)
	86	sprintf (buf, "r%d", 16 + (insn & 7));
	87	else
	88	sprintf (buf, "r%d", 16 + ((insn >> 4) & 7));
	89	break;
adde6300	90
bab84c47 DC	91	case 'v':
	92	if (regs)
	93	sprintf (buf, "r%d", (insn & 0xf) * 2);
	94	else
	95	sprintf (buf, "r%d", ((insn & 0xf0) >> 3));
	96	break;
	97
	98	case 'e':
	99	if (insn & 0x2)
	100	*buf++ = '-';
	101	switch ((insn >> 2) & 0x3)
	102	{
	103	case 0: *buf++ = 'Z'; break;
	104	case 2: *buf++ = 'Y'; break;
	105	case 3: *buf++ = 'X'; break;
00d2865b	106	default: buf += sprintf (buf, _(" unknown register ")); break;
bab84c47 DC	107	}
	108	if (insn & 0x1)
	109	*buf++ = '+';
	110	*buf = '\0';
	111	break;
	112
	113	case 'z':
	114	*buf++ = 'Z';
	115	if (insn & 0x1)
	116	*buf++ = '+';
	117	*buf = '\0';
	118	break;
	119
	120	case 'b':
	121	{
	122	unsigned int x = insn;
	123
	124	x = (insn & 7);
	125	x \|= (insn >> 7) & (3 << 3);
	126	x \|= (insn >> 8) & (1 << 5);
	127
	128	if (insn & 0x8)
	129	*buf++ = 'Y';
	130	else
	131	*buf++ = 'Z';
	132	sprintf (buf, "+%d", x);
	133	sprintf (comment, "0x%02x", x);
	134	}
	135	break;
	136
	137	case 'h':
8776c5fe DC	138	sprintf (buf, "0x%x",
8776c5fe DC	139	((((insn & 1) \| ((insn & 0x1f0) >> 3)) << 16) \| insn2) * 2);
bab84c47 DC	140	break;
	141
	142	case 'L':
	143	{
	144	int rel_addr = (((insn & 0xfff) ^ 0x800) - 0x800) * 2;
	145	sprintf (buf, ".%+-8d", rel_addr);
	146	sprintf (comment, "0x%x", pc + 2 + rel_addr);
	147	}
	148	break;
	149
	150	case 'l':
	151	{
	152	int rel_addr = ((((insn >> 3) & 0x7f) ^ 0x40) - 0x40) * 2;
	153	sprintf (buf, ".%+-8d", rel_addr);
	154	sprintf (comment, "0x%x", pc + 2 + rel_addr);
	155	}
	156	break;
	157
	158	case 'i':
	159	sprintf (buf, "0x%04X", insn2);
	160	break;
	161
	162	case 'M':
	163	sprintf (buf, "0x%02X", ((insn & 0xf00) >> 4) \| (insn & 0xf));
	164	sprintf (comment, "%d", ((insn & 0xf00) >> 4) \| (insn & 0xf));
	165	break;
	166
	167	case 'n':
00d2865b	168	sprintf (buf, _("Internal disassembler error"));
bab84c47 DC	169	break;
	170
	171	case 'K':
	172	sprintf (buf, "%d", (insn & 0xf) \| ((insn >> 2) & 0x30));
	173	break;
	174
	175	case 's':
	176	sprintf (buf, "%d", insn & 7);
	177	break;
	178
	179	case 'S':
	180	sprintf (buf, "%d", (insn >> 4) & 7);
	181	break;
	182
	183	case 'P':
	184	{
	185	unsigned int x;
	186	x = (insn & 0xf);
	187	x \|= (insn >> 5) & 0x30;
	188	sprintf (buf, "0x%02x", x);
	189	sprintf (comment, "%d", x);
	190	}
	191	break;
	192
	193	case 'p':
	194	{
	195	unsigned int x;
	196
	197	x = (insn >> 3) & 0x1f;
	198	sprintf (buf, "0x%02x", x);
	199	sprintf (comment, "%d", x);
	200	}
	201	break;
	202
	203	case '?':
	204	*buf = '\0';
	205	break;
	206
	207	default:
00d2865b	208	sprintf (buf, _("unknown constraint `%c'"), constraint);
bab84c47	209	}
adde6300 AM	210	}
adde6300 AM	211
bab84c47	212	static unsigned short avrdis_opcode PARAMS ((bfd_vma, disassemble_info *));
adde6300	213
bab84c47	214	static unsigned short
adde6300 AM	215	avrdis_opcode (addr, info)
	216	bfd_vma addr;
	217	disassemble_info *info;
	218	{
	219	bfd_byte buffer[2];
	220	int status;
	221	status = info->read_memory_func(addr, buffer, 2, info);
	222	if (status != 0)
	223	{
	224	info->memory_error_func(status, addr, info);
	225	return -1;
	226	}
	227	return bfd_getl16 (buffer);
	228	}
	229
	230
	231	int
	232	print_insn_avr(addr, info)
	233	bfd_vma addr;
	234	disassemble_info *info;
	235	{
bab84c47 DC	236	unsigned int insn, insn2;
bab84c47 DC	237	struct avr_opcodes_s *opcode;
adde6300 AM	238	void *stream = info->stream;
adde6300 AM	239	fprintf_ftype prin = info->fprintf_func;
bab84c47	240	static int initialized;
adde6300 AM	241	int cmd_len = 2;
adde6300 AM	242
bab84c47 DC	243	if (!initialized)
	244	{
	245	initialized = 1;
	246
	247	for (opcode = avr_opcodes; opcode->name; opcode++)
	248	{
	249	char * s;
	250	unsigned int bin = 0;
	251	unsigned int mask = 0;
	252
	253	for (s = opcode->opcode; *s; ++s)
	254	{
	255	bin <<= 1;
	256	mask <<= 1;
	257	bin \|= (*s == '1');
	258	mask \|= (s == '1' \|\| s == '0');
	259	}
	260	assert (s - opcode->opcode == 16);
	261	assert (opcode->bin_opcode == bin);
	262	opcode->bin_mask = mask;
	263	}
	264	}
adde6300	265
bab84c47 DC	266	insn = avrdis_opcode (addr, info);
	267
	268	for (opcode = avr_opcodes; opcode->name; opcode++)
adde6300	269	{
bab84c47 DC	270	if ((insn & opcode->bin_mask) == opcode->bin_opcode)
bab84c47 DC	271	break;
adde6300	272	}
bab84c47 DC	273
bab84c47 DC	274	if (opcode->name)
adde6300	275	{
bab84c47 DC	276	char op1[20], op2[20], comment1[40], comment2[40];
	277	char *op = opcode->constraints;
	278
	279	op1[0] = 0;
	280	op2[0] = 0;
	281	comment1[0] = 0;
	282	comment2[0] = 0;
00d2865b	283	insn2 = 0;
bab84c47 DC	284
	285	if (opcode->insn_size > 1)
	286	{
	287	insn2 = avrdis_opcode (addr + 2, info);
	288	cmd_len = 4;
	289	}
	290
	291	if (op && op != '?')
	292	{
	293	int regs = REGISTER_P (*op);
	294
	295	avr_operand (insn, insn2, addr, *op, op1, comment1, 0);
	296
	297	if (*(++op) == ',')
	298	avr_operand (insn, insn2, addr, *(++op), op2,
	299	*comment1 ? comment2 : comment1, regs);
	300	}
	301
	302	(*prin) (stream, " %-8s", opcode->name);
	303
	304	if (*op1)
	305	(*prin) (stream, "%s", op1);
	306
	307	if (*op2)
	308	(*prin) (stream, ", %s", op2);
	309
	310	if (*comment1)
	311	(*prin) (stream, "\t; %s", comment1);
	312
	313	if (*comment2)
	314	(*prin) (stream, " %s", comment2);
adde6300	315	}
bab84c47 DC	316	else
	317	(*prin) (stream, ".word 0x%04x\t; ????", insn);
	318
adde6300 AM	319	return cmd_len;
adde6300 AM	320	}