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Include 32-linux.c and x32-avx-linux.c
[deliverable/binutils-gdb.git] / opcodes / bfin-dis.c
CommitLineData
4b7f6baa 1/* Disassemble ADI Blackfin Instructions.
69b8ea4a
MF		 2 Copyright 2005, 2006, 2007, 2008, 2009, 2010, 2011
3 Free Software Foundation, Inc.
4b7f6baa 4
9b201bb5
NC		 5 This file is part of libopcodes.
6
7 This library is free software; you can redistribute it and/or modify
4b7f6baa 8 it under the terms of the GNU General Public License as published by
9b201bb5
NC		 9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
4b7f6baa 11
9b201bb5
NC		 12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
4b7f6baa
CM		 16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
22#include <stdio.h>
23#include <stdlib.h>
24#include <string.h>
25
26#include "opcode/bfin.h"
27
4b7f6baa
CM		 28#ifndef PRINTF
29#define PRINTF printf
30#endif
31
32#ifndef EXIT
33#define EXIT exit
34#endif
35
36typedef long TIword;
37
b7d48530
NC		 38#define HOST_LONG_WORD_SIZE (sizeof (long) * 8)
39#define XFIELD(w,p,s) (((w) & ((1 << (s)) - 1) << (p)) >> (p))
40#define SIGNEXTEND(v, n) ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
41#define MASKBITS(val, bits) (val & ((1 << bits) - 1))
4b7f6baa
CM		 42
43#include "dis-asm.h"
b7d48530 44
b21c9cb4
BS		 45typedef unsigned int bu32;
46
528c6277
MF		 47static char comment = 0;
48static char parallel = 0;
49
4b7f6baa
CM		 50typedef enum
51{
52 c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
086134ec
BS		 53 c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_imm5d, c_uimm5, c_imm6,
54 c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10,
55 c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4,
56 c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e,
4b7f6baa
CM		 57} const_forms_t;
58
528c6277 59static const struct
4b7f6baa 60{
528c6277
MF		 61 const char *name;
62 const int nbits;
63 const char reloc;
64 const char issigned;
65 const char pcrel;
66 const char scale;
67 const char offset;
68 const char negative;
69 const char positive;
70 const char decimal;
71 const char leading;
72 const char exact;
4b7f6baa
CM		 73} constant_formats[] =
74{
086134ec
BS		 75 { "0", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
76 { "1", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
77 { "4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
78 { "2", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
79 { "uimm2", 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
80 { "uimm3", 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
81 { "imm3", 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
82 { "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
83 { "imm4", 4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
84 { "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0},
85 { "uimm4s4d", 4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0},
86 { "uimm4", 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
87 { "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0},
88 { "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0},
89 { "imm5", 5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
90 { "imm5d", 5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0},
91 { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
92 { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
93 { "imm7", 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
94 { "imm7d", 7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
95 { "imm8", 8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
96 { "uimm8", 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
97 { "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
98 { "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
99 { "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0},
100 { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
101 { "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
102 { "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
103 { "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0},
104 { "luimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
105 { "imm16", 16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
106 { "imm16d", 16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
107 { "huimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
108 { "rimm16", 16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
109 { "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0},
110 { "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
111 { "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0},
112 { "uimm16", 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
113 { "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
114 { "uimm32", 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
115 { "imm32", 32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
116 { "huimm32", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
117 { "huimm32e", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1},
4b7f6baa
CM		 118};
119
528c6277
MF		 120static const char *
121fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info *outf)
4b7f6baa
CM		 122{
123 static char buf[60];
124
125 if (constant_formats[cf].reloc)
126 {
127 bfd_vma ea = (((constant_formats[cf].pcrel ? SIGNEXTEND (x, constant_formats[cf].nbits)
128 : x) + constant_formats[cf].offset) << constant_formats[cf].scale);
129 if (constant_formats[cf].pcrel)
130 ea += pc;
131
602427c4
MF		 132 /* truncate to 32-bits for proper symbol lookup/matching */
133 ea = (bu32)ea;
7a360e83 134
602427c4
MF		 135 if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact)
136 {
086134ec
BS		 137 outf->print_address_func (ea, outf);
138 return "";
602427c4
MF		 139 }
140 else
141 {
0af1713e 142 sprintf (buf, "%lx", (unsigned long) x);
086134ec 143 return buf;
602427c4 144 }
4b7f6baa
CM		 145 }
146
147 /* Negative constants have an implied sign bit. */
148 if (constant_formats[cf].negative)
149 {
150 int nb = constant_formats[cf].nbits + 1;
b7d48530 151
4b7f6baa
CM		 152 x = x | (1 << constant_formats[cf].nbits);
153 x = SIGNEXTEND (x, nb);
154 }
155 else
156 x = constant_formats[cf].issigned ? SIGNEXTEND (x, constant_formats[cf].nbits) : x;
157
158 if (constant_formats[cf].offset)
159 x += constant_formats[cf].offset;
160
161 if (constant_formats[cf].scale)
162 x <<= constant_formats[cf].scale;
163
086134ec 164 if (constant_formats[cf].decimal)
5de10af0 165 sprintf (buf, "%*li", constant_formats[cf].leading, x);
4b7f6baa 166 else
086134ec
BS		 167 {
168 if (constant_formats[cf].issigned && x < 0)
169 sprintf (buf, "-0x%x", abs (x));
170 else
0af1713e 171 sprintf (buf, "0x%lx", (unsigned long) x);
086134ec 172 }
4b7f6baa
CM		 173
174 return buf;
175}
176
b21c9cb4
BS		 177static bu32
178fmtconst_val (const_forms_t cf, unsigned int x, unsigned int pc)
179{
180 if (0 && constant_formats[cf].reloc)
181 {
182 bu32 ea = (((constant_formats[cf].pcrel
086134ec
BS		 183 ? SIGNEXTEND (x, constant_formats[cf].nbits)
184 : x) + constant_formats[cf].offset)
185 << constant_formats[cf].scale);
b21c9cb4 186 if (constant_formats[cf].pcrel)
086134ec 187 ea += pc;
b21c9cb4
BS		 188
189 return ea;
190 }
191
192 /* Negative constants have an implied sign bit. */
193 if (constant_formats[cf].negative)
194 {
195 int nb = constant_formats[cf].nbits + 1;
196 x = x | (1 << constant_formats[cf].nbits);
197 x = SIGNEXTEND (x, nb);
198 }
199 else if (constant_formats[cf].issigned)
200 x = SIGNEXTEND (x, constant_formats[cf].nbits);
201
202 x += constant_formats[cf].offset;
203 x <<= constant_formats[cf].scale;
204
205 return x;
206}
207
4b7f6baa
CM		 208enum machine_registers
209{
210 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
211 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
212 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
213 REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3,
214 REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w,
215 REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1,
216 REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1,
217 REG_L2, REG_L3,
218 REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S,
219 REG_AQ, REG_V, REG_VS,
220 REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0,
43a6aa65 221 REG_LC1, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1,
4b7f6baa
CM		 222 REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN,
223 REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6,
224 REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
225 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
226 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
227 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
228 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
229 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
22215ae0 230 REG_AC0_COPY, REG_V_COPY, REG_RND_MOD,
4b7f6baa
CM		 231 REG_LASTREG,
232};
233
234enum reg_class
235{
236 rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext,
237 rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs,
238 rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2,
239 rc_sysregs3, rc_allregs,
240 LIM_REG_CLASSES
241};
242
69b8ea4a 243static const char * const reg_names[] =
4b7f6baa
CM		 244{
245 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
246 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
247 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
248 "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
086134ec 249 "P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W",
4b7f6baa
CM		 250 "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
251 "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
252 "L2", "L3",
253 "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
254 "AQ", "V", "VS",
255 "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0",
43a6aa65 256 "LC1", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
4b7f6baa
CM		 257 "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN",
258 "RETE", "EMUDAT",
259 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",
260 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L",
261 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H",
262 "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L",
263 "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L",
264 "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H",
265 "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H",
22215ae0 266 "AC0_COPY", "V_COPY", "RND_MOD",
4b7f6baa
CM		 267 "LASTREG",
268 0
269};
270
271#define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......")
272
273/* RL(0..7). */
69b8ea4a 274static const enum machine_registers decode_dregs_lo[] =
4b7f6baa
CM		 275{
276 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
277};
278
b7d48530 279#define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
4b7f6baa
CM		 280
281/* RH(0..7). */
69b8ea4a 282static const enum machine_registers decode_dregs_hi[] =
4b7f6baa
CM		 283{
284 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
285};
286
b7d48530 287#define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
4b7f6baa
CM		 288
289/* R(0..7). */
69b8ea4a 290static const enum machine_registers decode_dregs[] =
4b7f6baa
CM		 291{
292 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
293};
294
b7d48530 295#define dregs(x) REGNAME (decode_dregs[(x) & 7])
4b7f6baa
CM		 296
297/* R BYTE(0..7). */
69b8ea4a 298static const enum machine_registers decode_dregs_byte[] =
4b7f6baa
CM		 299{
300 REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
301};
302
b7d48530 303#define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
4b7f6baa
CM		 304
305/* P(0..5) SP FP. */
69b8ea4a 306static const enum machine_registers decode_pregs[] =
4b7f6baa
CM		 307{
308 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
309};
310
b7d48530
NC		 311#define pregs(x) REGNAME (decode_pregs[(x) & 7])
312#define spfp(x) REGNAME (decode_spfp[(x) & 1])
602427c4 313#define dregs_hilo(x, i) REGNAME (decode_dregs_hilo[((i) << 3) | (x)])
b7d48530
NC		 314#define accum_ext(x) REGNAME (decode_accum_ext[(x) & 1])
315#define accum_word(x) REGNAME (decode_accum_word[(x) & 1])
316#define accum(x) REGNAME (decode_accum[(x) & 1])
4b7f6baa
CM		 317
318/* I(0..3). */
69b8ea4a 319static const enum machine_registers decode_iregs[] =
4b7f6baa
CM		 320{
321 REG_I0, REG_I1, REG_I2, REG_I3,
322};
323
b7d48530 324#define iregs(x) REGNAME (decode_iregs[(x) & 3])
4b7f6baa
CM		 325
326/* M(0..3). */
69b8ea4a 327static const enum machine_registers decode_mregs[] =
4b7f6baa
CM		 328{
329 REG_M0, REG_M1, REG_M2, REG_M3,
330};
331
b7d48530
NC		 332#define mregs(x) REGNAME (decode_mregs[(x) & 3])
333#define bregs(x) REGNAME (decode_bregs[(x) & 3])
334#define lregs(x) REGNAME (decode_lregs[(x) & 3])
4b7f6baa
CM		 335
336/* dregs pregs. */
69b8ea4a 337static const enum machine_registers decode_dpregs[] =
4b7f6baa
CM		 338{
339 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
340 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
341};
342
b7d48530 343#define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
4b7f6baa
CM		 344
345/* [dregs pregs]. */
69b8ea4a 346static const enum machine_registers decode_gregs[] =
4b7f6baa
CM		 347{
348 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
349 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
350};
351
602427c4 352#define gregs(x, i) REGNAME (decode_gregs[((i) << 3) | (x)])
4b7f6baa
CM		 353
354/* [dregs pregs (iregs mregs) (bregs lregs)]. */
69b8ea4a 355static const enum machine_registers decode_regs[] =
4b7f6baa
CM		 356{
357 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
358 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
359 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
360 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
361};
362
602427c4 363#define regs(x, i) REGNAME (decode_regs[((i) << 3) | (x)])
4b7f6baa
CM		 364
365/* [dregs pregs (iregs mregs) (bregs lregs) Low Half]. */
69b8ea4a 366static const enum machine_registers decode_regs_lo[] =
4b7f6baa
CM		 367{
368 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
369 REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
370 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
371 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
372};
373
602427c4
MF		 374#define regs_lo(x, i) REGNAME (decode_regs_lo[((i) << 3) | (x)])
375
4b7f6baa 376/* [dregs pregs (iregs mregs) (bregs lregs) High Half]. */
69b8ea4a 377static const enum machine_registers decode_regs_hi[] =
4b7f6baa
CM		 378{
379 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
380 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
1985c81c 381 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
4b7f6baa
CM		 382 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
383};
384
602427c4 385#define regs_hi(x, i) REGNAME (decode_regs_hi[((i) << 3) | (x)])
4b7f6baa 386
69b8ea4a 387static const enum machine_registers decode_statbits[] =
4b7f6baa 388{
22215ae0
MF		 389 REG_AZ, REG_AN, REG_AC0_COPY, REG_V_COPY,
390 REG_LASTREG, REG_LASTREG, REG_AQ, REG_LASTREG,
391 REG_RND_MOD, REG_LASTREG, REG_LASTREG, REG_LASTREG,
392 REG_AC0, REG_AC1, REG_LASTREG, REG_LASTREG,
393 REG_AV0, REG_AV0S, REG_AV1, REG_AV1S,
394 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
395 REG_V, REG_VS, REG_LASTREG, REG_LASTREG,
396 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
4b7f6baa
CM		 397};
398
ad15c38e 399#define statbits(x) REGNAME (decode_statbits[(x) & 31])
4b7f6baa
CM		 400
401/* LC0 LC1. */
69b8ea4a 402static const enum machine_registers decode_counters[] =
4b7f6baa
CM		 403{
404 REG_LC0, REG_LC1,
405};
406
b7d48530
NC		 407#define counters(x) REGNAME (decode_counters[(x) & 1])
408#define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7])
4b7f6baa
CM		 409
410/* [dregs pregs (iregs mregs) (bregs lregs)
411 dregs2_sysregs1 open sysregs2 sysregs3]. */
69b8ea4a 412static const enum machine_registers decode_allregs[] =
4b7f6baa
CM		 413{
414 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
415 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
416 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
417 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
43a6aa65 418 REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_LASTREG, REG_LASTREG, REG_ASTAT, REG_RETS,
4b7f6baa
CM		 419 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
420 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
c958a8a8
JZ		 421 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,
422 REG_LASTREG,
4b7f6baa
CM		 423};
424
50e2162a
MF		 425#define IS_DREG(g,r) ((g) == 0 && (r) < 8)
426#define IS_PREG(g,r) ((g) == 1 && (r) < 8)
c958a8a8 427#define IS_AREG(g,r) ((g) == 4 && (r) >= 0 && (r) < 4)
50e2162a
MF		 428#define IS_GENREG(g,r) ((((g) == 0 || (g) == 1) && (r) < 8) || IS_AREG (g, r))
429#define IS_DAGREG(g,r) (((g) == 2 || (g) == 3) && (r) < 8)
c958a8a8
JZ		 430#define IS_SYSREG(g,r) \
431 (((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7)
50e2162a
MF		 432#define IS_RESERVEDREG(g,r) \
433 (((r) > 7) || ((g) == 4 && ((r) == 4 || (r) == 5)) || (g) == 5)
434
435#define allreg(r,g) (!IS_RESERVEDREG (g, r))
436#define mostreg(r,g) (!(IS_DREG (g, r) || IS_PREG (g, r) || IS_RESERVEDREG (g, r)))
c958a8a8 437
602427c4 438#define allregs(x, i) REGNAME (decode_allregs[((i) << 3) | (x)])
b7d48530 439#define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf)
086134ec 440#define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf)
b7d48530
NC		 441#define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf)
442#define pcrel8(x) fmtconst (c_pcrel8, x, pc, outf)
443#define pcrel8s4(x) fmtconst (c_pcrel8s4, x, pc, outf)
444#define pcrel10(x) fmtconst (c_pcrel10, x, pc, outf)
445#define pcrel12(x) fmtconst (c_pcrel12, x, pc, outf)
446#define negimm5s4(x) fmtconst (c_negimm5s4, x, 0, outf)
447#define rimm16(x) fmtconst (c_rimm16, x, 0, outf)
448#define huimm16(x) fmtconst (c_huimm16, x, 0, outf)
449#define imm16(x) fmtconst (c_imm16, x, 0, outf)
086134ec 450#define imm16d(x) fmtconst (c_imm16d, x, 0, outf)
b7d48530
NC		 451#define uimm2(x) fmtconst (c_uimm2, x, 0, outf)
452#define uimm3(x) fmtconst (c_uimm3, x, 0, outf)
453#define luimm16(x) fmtconst (c_luimm16, x, 0, outf)
454#define uimm4(x) fmtconst (c_uimm4, x, 0, outf)
455#define uimm5(x) fmtconst (c_uimm5, x, 0, outf)
456#define imm16s2(x) fmtconst (c_imm16s2, x, 0, outf)
457#define uimm8(x) fmtconst (c_uimm8, x, 0, outf)
458#define imm16s4(x) fmtconst (c_imm16s4, x, 0, outf)
459#define uimm4s2(x) fmtconst (c_uimm4s2, x, 0, outf)
460#define uimm4s4(x) fmtconst (c_uimm4s4, x, 0, outf)
086134ec 461#define uimm4s4d(x) fmtconst (c_uimm4s4d, x, 0, outf)
b7d48530
NC		 462#define lppcrel10(x) fmtconst (c_lppcrel10, x, pc, outf)
463#define imm3(x) fmtconst (c_imm3, x, 0, outf)
464#define imm4(x) fmtconst (c_imm4, x, 0, outf)
465#define uimm8s4(x) fmtconst (c_uimm8s4, x, 0, outf)
466#define imm5(x) fmtconst (c_imm5, x, 0, outf)
086134ec 467#define imm5d(x) fmtconst (c_imm5d, x, 0, outf)
b7d48530
NC		 468#define imm6(x) fmtconst (c_imm6, x, 0, outf)
469#define imm7(x) fmtconst (c_imm7, x, 0, outf)
086134ec 470#define imm7d(x) fmtconst (c_imm7d, x, 0, outf)
b7d48530
NC		 471#define imm8(x) fmtconst (c_imm8, x, 0, outf)
472#define pcrel24(x) fmtconst (c_pcrel24, x, pc, outf)
473#define uimm16(x) fmtconst (c_uimm16, x, 0, outf)
b21c9cb4 474#define uimm32(x) fmtconst (c_uimm32, x, 0, outf)
086134ec 475#define imm32(x) fmtconst (c_imm32, x, 0, outf)
b21c9cb4 476#define huimm32(x) fmtconst (c_huimm32, x, 0, outf)
086134ec
BS		 477#define huimm32e(x) fmtconst (c_huimm32e, x, 0, outf)
478#define imm7_val(x) fmtconst_val (c_imm7, x, 0)
b21c9cb4
BS		 479#define imm16_val(x) fmtconst_val (c_uimm16, x, 0)
480#define luimm16_val(x) fmtconst_val (c_luimm16, x, 0)
4b7f6baa
CM		 481
482/* (arch.pm)arch_disassembler_functions. */
4b7f6baa 483#ifndef OUTS
500cccad 484#define OUTS(p, txt) (p)->fprintf_func ((p)->stream, "%s", txt)
4b7f6baa
CM		 485#endif
486
4b7f6baa
CM		 487static void
488amod0 (int s0, int x0, disassemble_info *outf)
489{
b7d48530 490 if (s0 == 1 && x0 == 0)
086134ec 491 OUTS (outf, " (S)");
4b7f6baa 492 else if (s0 == 0 && x0 == 1)
086134ec 493 OUTS (outf, " (CO)");
4b7f6baa 494 else if (s0 == 1 && x0 == 1)
086134ec 495 OUTS (outf, " (SCO)");
4b7f6baa
CM		 496}
497
498static void
499amod1 (int s0, int x0, disassemble_info *outf)
500{
501 if (s0 == 0 && x0 == 0)
086134ec 502 OUTS (outf, " (NS)");
4b7f6baa 503 else if (s0 == 1 && x0 == 0)
086134ec 504 OUTS (outf, " (S)");
4b7f6baa
CM		 505}
506
507static void
508amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf)
509{
b7d48530 510 if (s0 == 1 && x0 == 0 && aop0 == 0)
086134ec 511 OUTS (outf, " (S)");
4b7f6baa 512 else if (s0 == 0 && x0 == 1 && aop0 == 0)
086134ec 513 OUTS (outf, " (CO)");
4b7f6baa 514 else if (s0 == 1 && x0 == 1 && aop0 == 0)
086134ec 515 OUTS (outf, " (SCO)");
4b7f6baa 516 else if (s0 == 0 && x0 == 0 && aop0 == 2)
086134ec 517 OUTS (outf, " (ASR)");
4b7f6baa 518 else if (s0 == 1 && x0 == 0 && aop0 == 2)
086134ec 519 OUTS (outf, " (S, ASR)");
4b7f6baa 520 else if (s0 == 0 && x0 == 1 && aop0 == 2)
086134ec 521 OUTS (outf, " (CO, ASR)");
4b7f6baa 522 else if (s0 == 1 && x0 == 1 && aop0 == 2)
086134ec 523 OUTS (outf, " (SCO, ASR)");
4b7f6baa 524 else if (s0 == 0 && x0 == 0 && aop0 == 3)
086134ec 525 OUTS (outf, " (ASL)");
4b7f6baa 526 else if (s0 == 1 && x0 == 0 && aop0 == 3)
086134ec 527 OUTS (outf, " (S, ASL)");
4b7f6baa 528 else if (s0 == 0 && x0 == 1 && aop0 == 3)
086134ec 529 OUTS (outf, " (CO, ASL)");
4b7f6baa 530 else if (s0 == 1 && x0 == 1 && aop0 == 3)
086134ec 531 OUTS (outf, " (SCO, ASL)");
4b7f6baa
CM		 532}
533
534static void
535searchmod (int r0, disassemble_info *outf)
536{
b7d48530
NC		 537 if (r0 == 0)
538 OUTS (outf, "GT");
539 else if (r0 == 1)
540 OUTS (outf, "GE");
541 else if (r0 == 2)
542 OUTS (outf, "LT");
543 else if (r0 == 3)
544 OUTS (outf, "LE");
4b7f6baa
CM		 545}
546
547static void
548aligndir (int r0, disassemble_info *outf)
549{
b7d48530 550 if (r0 == 1)
086134ec 551 OUTS (outf, " (R)");
4b7f6baa
CM		 552}
553
554static int
602427c4 555decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info *outf)
4b7f6baa 556{
528c6277 557 const char *s0, *s1;
4b7f6baa
CM		 558
559 if (h0)
560 s0 = dregs_hi (src0);
561 else
562 s0 = dregs_lo (src0);
563
564 if (h1)
565 s1 = dregs_hi (src1);
566 else
567 s1 = dregs_lo (src1);
568
569 OUTS (outf, s0);
570 OUTS (outf, " * ");
571 OUTS (outf, s1);
572 return 0;
573}
574
575static int
602427c4 576decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info *outf)
4b7f6baa 577{
528c6277
MF		 578 const char *a;
579 const char *sop = "<unknown op>";
4b7f6baa
CM		 580
581 if (which)
086134ec 582 a = "A1";
4b7f6baa 583 else
086134ec 584 a = "A0";
4b7f6baa
CM		 585
586 if (op == 3)
587 {
588 OUTS (outf, a);
589 return 0;
590 }
591
592 switch (op)
593 {
086134ec
BS		 594 case 0: sop = " = "; break;
595 case 1: sop = " += "; break;
596 case 2: sop = " -= "; break;
b7d48530 597 default: break;
4b7f6baa
CM		 598 }
599
600 OUTS (outf, a);
4b7f6baa 601 OUTS (outf, sop);
4b7f6baa
CM		 602 decode_multfunc (h0, h1, src0, src1, outf);
603
604 return 0;
605}
606
607static void
608decode_optmode (int mod, int MM, disassemble_info *outf)
609{
610 if (mod == 0 && MM == 0)
611 return;
612
613 OUTS (outf, " (");
614
615 if (MM && !mod)
616 {
617 OUTS (outf, "M)");
618 return;
619 }
620
621 if (MM)
622 OUTS (outf, "M, ");
b7d48530 623
4b7f6baa
CM		 624 if (mod == M_S2RND)
625 OUTS (outf, "S2RND");
626 else if (mod == M_T)
627 OUTS (outf, "T");
628 else if (mod == M_W32)
629 OUTS (outf, "W32");
630 else if (mod == M_FU)
631 OUTS (outf, "FU");
632 else if (mod == M_TFU)
633 OUTS (outf, "TFU");
634 else if (mod == M_IS)
635 OUTS (outf, "IS");
636 else if (mod == M_ISS2)
637 OUTS (outf, "ISS2");
638 else if (mod == M_IH)
639 OUTS (outf, "IH");
640 else if (mod == M_IU)
641 OUTS (outf, "IU");
642 else
643 abort ();
644
645 OUTS (outf, ")");
646}
b7d48530 647
e5bc4265 648static struct saved_state
b21c9cb4
BS		 649{
650 bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4];
e5bc4265 651 bu32 ax[2], aw[2];
b21c9cb4 652 bu32 lt[2], lc[2], lb[2];
e5bc4265 653 bu32 rets;
602427c4 654} saved_state;
b21c9cb4
BS		 655
656#define DREG(x) (saved_state.dpregs[x])
602427c4 657#define GREG(x, i) DPREG ((x) | ((i) << 3))
b21c9cb4
BS		 658#define DPREG(x) (saved_state.dpregs[x])
659#define DREG(x) (saved_state.dpregs[x])
602427c4 660#define PREG(x) (saved_state.dpregs[(x) + 8])
b21c9cb4
BS		 661#define SPREG PREG (6)
662#define FPREG PREG (7)
663#define IREG(x) (saved_state.iregs[x])
664#define MREG(x) (saved_state.mregs[x])
665#define BREG(x) (saved_state.bregs[x])
666#define LREG(x) (saved_state.lregs[x])
e5bc4265
MF		 667#define AXREG(x) (saved_state.ax[x])
668#define AWREG(x) (saved_state.aw[x])
669#define LCREG(x) (saved_state.lc[x])
670#define LTREG(x) (saved_state.lt[x])
671#define LBREG(x) (saved_state.lb[x])
b21c9cb4 672#define RETSREG (saved_state.rets)
b21c9cb4
BS		 673
674static bu32 *
675get_allreg (int grp, int reg)
676{
677 int fullreg = (grp << 3) | reg;
678 /* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
679 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
680 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
681 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
682 REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS,
683 , , , , , , , ,
684 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
685 REG_CYCLES2,
686 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE,
687 REG_LASTREG */
688 switch (fullreg >> 2)
689 {
e5bc4265
MF		 690 case 0: case 1: return &DREG (reg);
691 case 2: case 3: return &PREG (reg);
692 case 4: return &IREG (reg & 3);
693 case 5: return &MREG (reg & 3);
694 case 6: return &BREG (reg & 3);
695 case 7: return &LREG (reg & 3);
b21c9cb4
BS		 696 default:
697 switch (fullreg)
086134ec 698 {
e5bc4265
MF		 699 case 32: return &AXREG (0);
700 case 33: return &AWREG (0);
701 case 34: return &AXREG (1);
702 case 35: return &AWREG (1);
703 case 39: return &RETSREG;
704 case 48: return &LCREG (0);
705 case 49: return &LTREG (0);
706 case 50: return &LBREG (0);
707 case 51: return &LCREG (1);
708 case 52: return &LTREG (1);
709 case 53: return &LBREG (1);
086134ec 710 }
b21c9cb4 711 }
e5bc4265 712 abort ();
b21c9cb4
BS		 713}
714
4b7f6baa
CM		 715static int
716decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
717{
b7d48530
NC		 718 /* ProgCtrl
719 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
720 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
721 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 722 int poprnd = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
723 int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
724
725 if (prgfunc == 0 && poprnd == 0)
b7d48530 726 OUTS (outf, "NOP");
219b747a
MF		 727 else if (parallel)
728 return 0;
4b7f6baa 729 else if (prgfunc == 1 && poprnd == 0)
b7d48530 730 OUTS (outf, "RTS");
4b7f6baa 731 else if (prgfunc == 1 && poprnd == 1)
b7d48530 732 OUTS (outf, "RTI");
4b7f6baa 733 else if (prgfunc == 1 && poprnd == 2)
b7d48530 734 OUTS (outf, "RTX");
4b7f6baa 735 else if (prgfunc == 1 && poprnd == 3)
b7d48530 736 OUTS (outf, "RTN");
4b7f6baa 737 else if (prgfunc == 1 && poprnd == 4)
b7d48530 738 OUTS (outf, "RTE");
4b7f6baa 739 else if (prgfunc == 2 && poprnd == 0)
b7d48530 740 OUTS (outf, "IDLE");
4b7f6baa 741 else if (prgfunc == 2 && poprnd == 3)
b7d48530 742 OUTS (outf, "CSYNC");
4b7f6baa 743 else if (prgfunc == 2 && poprnd == 4)
b7d48530 744 OUTS (outf, "SSYNC");
4b7f6baa 745 else if (prgfunc == 2 && poprnd == 5)
b7d48530 746 OUTS (outf, "EMUEXCPT");
50e2162a 747 else if (prgfunc == 3 && IS_DREG (0, poprnd))
4b7f6baa 748 {
086134ec 749 OUTS (outf, "CLI ");
4b7f6baa 750 OUTS (outf, dregs (poprnd));
4b7f6baa 751 }
50e2162a 752 else if (prgfunc == 4 && IS_DREG (0, poprnd))
4b7f6baa 753 {
086134ec 754 OUTS (outf, "STI ");
4b7f6baa 755 OUTS (outf, dregs (poprnd));
4b7f6baa 756 }
50e2162a 757 else if (prgfunc == 5 && IS_PREG (1, poprnd))
4b7f6baa 758 {
086134ec 759 OUTS (outf, "JUMP (");
4b7f6baa
CM		 760 OUTS (outf, pregs (poprnd));
761 OUTS (outf, ")");
4b7f6baa 762 }
50e2162a 763 else if (prgfunc == 6 && IS_PREG (1, poprnd))
4b7f6baa 764 {
086134ec 765 OUTS (outf, "CALL (");
4b7f6baa
CM		 766 OUTS (outf, pregs (poprnd));
767 OUTS (outf, ")");
4b7f6baa 768 }
50e2162a 769 else if (prgfunc == 7 && IS_PREG (1, poprnd))
4b7f6baa 770 {
086134ec 771 OUTS (outf, "CALL (PC + ");
4b7f6baa
CM		 772 OUTS (outf, pregs (poprnd));
773 OUTS (outf, ")");
4b7f6baa 774 }
50e2162a 775 else if (prgfunc == 8 && IS_PREG (1, poprnd))
4b7f6baa 776 {
086134ec 777 OUTS (outf, "JUMP (PC + ");
4b7f6baa
CM		 778 OUTS (outf, pregs (poprnd));
779 OUTS (outf, ")");
4b7f6baa
CM		 780 }
781 else if (prgfunc == 9)
782 {
086134ec 783 OUTS (outf, "RAISE ");
4b7f6baa 784 OUTS (outf, uimm4 (poprnd));
4b7f6baa
CM		 785 }
786 else if (prgfunc == 10)
787 {
086134ec 788 OUTS (outf, "EXCPT ");
4b7f6baa 789 OUTS (outf, uimm4 (poprnd));
4b7f6baa 790 }
219b747a 791 else if (prgfunc == 11 && IS_PREG (1, poprnd) && poprnd <= 5)
4b7f6baa 792 {
086134ec 793 OUTS (outf, "TESTSET (");
4b7f6baa
CM		 794 OUTS (outf, pregs (poprnd));
795 OUTS (outf, ")");
4b7f6baa
CM		 796 }
797 else
b7d48530
NC		 798 return 0;
799 return 2;
4b7f6baa
CM		 800}
801
802static int
803decode_CaCTRL_0 (TIword iw0, disassemble_info *outf)
804{
b7d48530
NC		 805 /* CaCTRL
806 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
807 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
808 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 809 int a = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask);
810 int op = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask);
811 int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask);
812
219b747a
MF		 813 if (parallel)
814 return 0;
815
4b7f6baa
CM		 816 if (a == 0 && op == 0)
817 {
4b7f6baa
CM		 818 OUTS (outf, "PREFETCH[");
819 OUTS (outf, pregs (reg));
820 OUTS (outf, "]");
4b7f6baa
CM		 821 }
822 else if (a == 0 && op == 1)
823 {
4b7f6baa
CM		 824 OUTS (outf, "FLUSHINV[");
825 OUTS (outf, pregs (reg));
826 OUTS (outf, "]");
4b7f6baa
CM		 827 }
828 else if (a == 0 && op == 2)
829 {
4b7f6baa
CM		 830 OUTS (outf, "FLUSH[");
831 OUTS (outf, pregs (reg));
832 OUTS (outf, "]");
4b7f6baa
CM		 833 }
834 else if (a == 0 && op == 3)
835 {
4b7f6baa
CM		 836 OUTS (outf, "IFLUSH[");
837 OUTS (outf, pregs (reg));
838 OUTS (outf, "]");
4b7f6baa
CM		 839 }
840 else if (a == 1 && op == 0)
841 {
4b7f6baa
CM		 842 OUTS (outf, "PREFETCH[");
843 OUTS (outf, pregs (reg));
844 OUTS (outf, "++]");
4b7f6baa
CM		 845 }
846 else if (a == 1 && op == 1)
847 {
4b7f6baa
CM		 848 OUTS (outf, "FLUSHINV[");
849 OUTS (outf, pregs (reg));
850 OUTS (outf, "++]");
4b7f6baa
CM		 851 }
852 else if (a == 1 && op == 2)
853 {
4b7f6baa
CM		 854 OUTS (outf, "FLUSH[");
855 OUTS (outf, pregs (reg));
856 OUTS (outf, "++]");
4b7f6baa
CM		 857 }
858 else if (a == 1 && op == 3)
859 {
4b7f6baa
CM		 860 OUTS (outf, "IFLUSH[");
861 OUTS (outf, pregs (reg));
862 OUTS (outf, "++]");
4b7f6baa
CM		 863 }
864 else
b7d48530
NC		 865 return 0;
866 return 2;
4b7f6baa
CM		 867}
868
869static int
870decode_PushPopReg_0 (TIword iw0, disassemble_info *outf)
871{
b7d48530
NC		 872 /* PushPopReg
873 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
874 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
875 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 876 int W = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask);
877 int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask);
878 int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask);
879
219b747a
MF		 880 if (parallel)
881 return 0;
882
50e2162a 883 if (W == 0 && mostreg (reg, grp))
4b7f6baa 884 {
4b7f6baa
CM		 885 OUTS (outf, allregs (reg, grp));
886 OUTS (outf, " = [SP++]");
4b7f6baa 887 }
219b747a 888 else if (W == 1 && allreg (reg, grp) && !(grp == 1 && reg == 6))
4b7f6baa 889 {
4b7f6baa
CM		 890 OUTS (outf, "[--SP] = ");
891 OUTS (outf, allregs (reg, grp));
4b7f6baa
CM		 892 }
893 else
b7d48530
NC		 894 return 0;
895 return 2;
4b7f6baa
CM		 896}
897
898static int
899decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf)
900{
b7d48530
NC		 901 /* PushPopMultiple
902 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
903 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
904 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 905 int p = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask);
906 int d = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask);
907 int W = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
908 int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
909 int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
4b7f6baa 910
219b747a
MF		 911 if (parallel)
912 return 0;
913
775f1cf0
MF		 914 if (pr > 5)
915 return 0;
916
4b7f6baa
CM		 917 if (W == 1 && d == 1 && p == 1)
918 {
4b7f6baa 919 OUTS (outf, "[--SP] = (R7:");
086134ec 920 OUTS (outf, imm5d (dr));
4b7f6baa 921 OUTS (outf, ", P5:");
086134ec 922 OUTS (outf, imm5d (pr));
4b7f6baa 923 OUTS (outf, ")");
4b7f6baa 924 }
219b747a 925 else if (W == 1 && d == 1 && p == 0 && pr == 0)
4b7f6baa 926 {
4b7f6baa 927 OUTS (outf, "[--SP] = (R7:");
086134ec 928 OUTS (outf, imm5d (dr));
4b7f6baa 929 OUTS (outf, ")");
4b7f6baa 930 }
219b747a 931 else if (W == 1 && d == 0 && p == 1 && dr == 0)
4b7f6baa 932 {
4b7f6baa 933 OUTS (outf, "[--SP] = (P5:");
086134ec 934 OUTS (outf, imm5d (pr));
4b7f6baa 935 OUTS (outf, ")");
4b7f6baa
CM		 936 }
937 else if (W == 0 && d == 1 && p == 1)
938 {
4b7f6baa 939 OUTS (outf, "(R7:");
086134ec 940 OUTS (outf, imm5d (dr));
4b7f6baa 941 OUTS (outf, ", P5:");
086134ec 942 OUTS (outf, imm5d (pr));
4b7f6baa 943 OUTS (outf, ") = [SP++]");
4b7f6baa 944 }
219b747a 945 else if (W == 0 && d == 1 && p == 0 && pr == 0)
4b7f6baa 946 {
4b7f6baa 947 OUTS (outf, "(R7:");
086134ec 948 OUTS (outf, imm5d (dr));
4b7f6baa 949 OUTS (outf, ") = [SP++]");
4b7f6baa 950 }
219b747a 951 else if (W == 0 && d == 0 && p == 1 && dr == 0)
4b7f6baa 952 {
4b7f6baa 953 OUTS (outf, "(P5:");
086134ec 954 OUTS (outf, imm5d (pr));
4b7f6baa 955 OUTS (outf, ") = [SP++]");
4b7f6baa
CM		 956 }
957 else
b7d48530
NC		 958 return 0;
959 return 2;
4b7f6baa
CM		 960}
961
962static int
963decode_ccMV_0 (TIword iw0, disassemble_info *outf)
964{
b7d48530
NC		 965 /* ccMV
966 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
967 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
968 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 969 int s = ((iw0 >> CCmv_s_bits) & CCmv_s_mask);
970 int d = ((iw0 >> CCmv_d_bits) & CCmv_d_mask);
971 int T = ((iw0 >> CCmv_T_bits) & CCmv_T_mask);
972 int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask);
973 int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask);
974
219b747a
MF		 975 if (parallel)
976 return 0;
977
4b7f6baa
CM		 978 if (T == 1)
979 {
4b7f6baa
CM		 980 OUTS (outf, "IF CC ");
981 OUTS (outf, gregs (dst, d));
982 OUTS (outf, " = ");
983 OUTS (outf, gregs (src, s));
4b7f6baa
CM		 984 }
985 else if (T == 0)
986 {
086134ec 987 OUTS (outf, "IF !CC ");
4b7f6baa
CM		 988 OUTS (outf, gregs (dst, d));
989 OUTS (outf, " = ");
990 OUTS (outf, gregs (src, s));
4b7f6baa
CM		 991 }
992 else
b7d48530
NC		 993 return 0;
994 return 2;
4b7f6baa
CM		 995}
996
997static int
998decode_CCflag_0 (TIword iw0, disassemble_info *outf)
999{
b7d48530
NC		 1000 /* CCflag
1001 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1002 | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
1003 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1004 int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask);
1005 int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask);
1006 int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask);
1007 int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask);
1008 int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask);
1009
219b747a
MF		 1010 if (parallel)
1011 return 0;
1012
4b7f6baa
CM		 1013 if (opc == 0 && I == 0 && G == 0)
1014 {
086134ec 1015 OUTS (outf, "CC = ");
4b7f6baa 1016 OUTS (outf, dregs (x));
086134ec 1017 OUTS (outf, " == ");
4b7f6baa 1018 OUTS (outf, dregs (y));
4b7f6baa
CM		 1019 }
1020 else if (opc == 1 && I == 0 && G == 0)
1021 {
086134ec 1022 OUTS (outf, "CC = ");
4b7f6baa 1023 OUTS (outf, dregs (x));
086134ec 1024 OUTS (outf, " < ");
4b7f6baa 1025 OUTS (outf, dregs (y));
4b7f6baa
CM		 1026 }
1027 else if (opc == 2 && I == 0 && G == 0)
1028 {
086134ec 1029 OUTS (outf, "CC = ");
4b7f6baa 1030 OUTS (outf, dregs (x));
086134ec 1031 OUTS (outf, " <= ");
4b7f6baa 1032 OUTS (outf, dregs (y));
4b7f6baa
CM		 1033 }
1034 else if (opc == 3 && I == 0 && G == 0)
1035 {
086134ec 1036 OUTS (outf, "CC = ");
4b7f6baa 1037 OUTS (outf, dregs (x));
086134ec 1038 OUTS (outf, " < ");
4b7f6baa 1039 OUTS (outf, dregs (y));
086134ec 1040 OUTS (outf, " (IU)");
4b7f6baa
CM		 1041 }
1042 else if (opc == 4 && I == 0 && G == 0)
1043 {
086134ec 1044 OUTS (outf, "CC = ");
4b7f6baa 1045 OUTS (outf, dregs (x));
086134ec 1046 OUTS (outf, " <= ");
4b7f6baa 1047 OUTS (outf, dregs (y));
086134ec 1048 OUTS (outf, " (IU)");
4b7f6baa
CM		 1049 }
1050 else if (opc == 0 && I == 1 && G == 0)
1051 {
086134ec 1052 OUTS (outf, "CC = ");
4b7f6baa 1053 OUTS (outf, dregs (x));
086134ec 1054 OUTS (outf, " == ");
4b7f6baa 1055 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1056 }
1057 else if (opc == 1 && I == 1 && G == 0)
1058 {
086134ec 1059 OUTS (outf, "CC = ");
4b7f6baa 1060 OUTS (outf, dregs (x));
086134ec 1061 OUTS (outf, " < ");
4b7f6baa 1062 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1063 }
1064 else if (opc == 2 && I == 1 && G == 0)
1065 {
086134ec 1066 OUTS (outf, "CC = ");
4b7f6baa 1067 OUTS (outf, dregs (x));
086134ec 1068 OUTS (outf, " <= ");
4b7f6baa 1069 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1070 }
1071 else if (opc == 3 && I == 1 && G == 0)
1072 {
086134ec 1073 OUTS (outf, "CC = ");
4b7f6baa 1074 OUTS (outf, dregs (x));
086134ec 1075 OUTS (outf, " < ");
4b7f6baa 1076 OUTS (outf, uimm3 (y));
086134ec 1077 OUTS (outf, " (IU)");
4b7f6baa
CM		 1078 }
1079 else if (opc == 4 && I == 1 && G == 0)
1080 {
086134ec 1081 OUTS (outf, "CC = ");
4b7f6baa 1082 OUTS (outf, dregs (x));
086134ec 1083 OUTS (outf, " <= ");
4b7f6baa 1084 OUTS (outf, uimm3 (y));
086134ec 1085 OUTS (outf, " (IU)");
4b7f6baa
CM		 1086 }
1087 else if (opc == 0 && I == 0 && G == 1)
1088 {
086134ec 1089 OUTS (outf, "CC = ");
4b7f6baa 1090 OUTS (outf, pregs (x));
086134ec 1091 OUTS (outf, " == ");
4b7f6baa 1092 OUTS (outf, pregs (y));
4b7f6baa
CM		 1093 }
1094 else if (opc == 1 && I == 0 && G == 1)
1095 {
086134ec 1096 OUTS (outf, "CC = ");
4b7f6baa 1097 OUTS (outf, pregs (x));
086134ec 1098 OUTS (outf, " < ");
4b7f6baa 1099 OUTS (outf, pregs (y));
4b7f6baa
CM		 1100 }
1101 else if (opc == 2 && I == 0 && G == 1)
1102 {
086134ec 1103 OUTS (outf, "CC = ");
4b7f6baa 1104 OUTS (outf, pregs (x));
086134ec 1105 OUTS (outf, " <= ");
4b7f6baa 1106 OUTS (outf, pregs (y));
4b7f6baa
CM		 1107 }
1108 else if (opc == 3 && I == 0 && G == 1)
1109 {
086134ec 1110 OUTS (outf, "CC = ");
4b7f6baa 1111 OUTS (outf, pregs (x));
086134ec 1112 OUTS (outf, " < ");
4b7f6baa 1113 OUTS (outf, pregs (y));
086134ec 1114 OUTS (outf, " (IU)");
4b7f6baa
CM		 1115 }
1116 else if (opc == 4 && I == 0 && G == 1)
1117 {
086134ec 1118 OUTS (outf, "CC = ");
4b7f6baa 1119 OUTS (outf, pregs (x));
086134ec 1120 OUTS (outf, " <= ");
4b7f6baa 1121 OUTS (outf, pregs (y));
086134ec 1122 OUTS (outf, " (IU)");
4b7f6baa
CM		 1123 }
1124 else if (opc == 0 && I == 1 && G == 1)
1125 {
086134ec 1126 OUTS (outf, "CC = ");
4b7f6baa 1127 OUTS (outf, pregs (x));
086134ec 1128 OUTS (outf, " == ");
4b7f6baa 1129 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1130 }
1131 else if (opc == 1 && I == 1 && G == 1)
1132 {
086134ec 1133 OUTS (outf, "CC = ");
4b7f6baa 1134 OUTS (outf, pregs (x));
086134ec 1135 OUTS (outf, " < ");
4b7f6baa 1136 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1137 }
1138 else if (opc == 2 && I == 1 && G == 1)
1139 {
086134ec 1140 OUTS (outf, "CC = ");
4b7f6baa 1141 OUTS (outf, pregs (x));
086134ec 1142 OUTS (outf, " <= ");
4b7f6baa 1143 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1144 }
1145 else if (opc == 3 && I == 1 && G == 1)
1146 {
086134ec 1147 OUTS (outf, "CC = ");
4b7f6baa 1148 OUTS (outf, pregs (x));
086134ec 1149 OUTS (outf, " < ");
4b7f6baa 1150 OUTS (outf, uimm3 (y));
086134ec 1151 OUTS (outf, " (IU)");
4b7f6baa
CM		 1152 }
1153 else if (opc == 4 && I == 1 && G == 1)
1154 {
086134ec 1155 OUTS (outf, "CC = ");
4b7f6baa 1156 OUTS (outf, pregs (x));
086134ec 1157 OUTS (outf, " <= ");
4b7f6baa 1158 OUTS (outf, uimm3 (y));
086134ec 1159 OUTS (outf, " (IU)");
4b7f6baa 1160 }
219b747a 1161 else if (opc == 5 && I == 0 && G == 0 && x == 0 && y == 0)
086134ec 1162 OUTS (outf, "CC = A0 == A1");
b7d48530 1163
219b747a 1164 else if (opc == 6 && I == 0 && G == 0 && x == 0 && y == 0)
086134ec 1165 OUTS (outf, "CC = A0 < A1");
b7d48530 1166
219b747a 1167 else if (opc == 7 && I == 0 && G == 0 && x == 0 && y == 0)
086134ec 1168 OUTS (outf, "CC = A0 <= A1");
b7d48530 1169
4b7f6baa 1170 else
b7d48530
NC		 1171 return 0;
1172 return 2;
4b7f6baa
CM		 1173}
1174
1175static int
1176decode_CC2dreg_0 (TIword iw0, disassemble_info *outf)
1177{
b7d48530
NC		 1178 /* CC2dreg
1179 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1180 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
1181 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1182 int op = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask);
1183 int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask);
1184
219b747a
MF		 1185 if (parallel)
1186 return 0;
1187
4b7f6baa
CM		 1188 if (op == 0)
1189 {
4b7f6baa 1190 OUTS (outf, dregs (reg));
086134ec 1191 OUTS (outf, " = CC");
4b7f6baa
CM		 1192 }
1193 else if (op == 1)
1194 {
086134ec 1195 OUTS (outf, "CC = ");
4b7f6baa 1196 OUTS (outf, dregs (reg));
4b7f6baa 1197 }
50e2162a 1198 else if (op == 3 && reg == 0)
086134ec 1199 OUTS (outf, "CC = !CC");
4b7f6baa 1200 else
b7d48530
NC		 1201 return 0;
1202
1203 return 2;
4b7f6baa
CM		 1204}
1205
1206static int
1207decode_CC2stat_0 (TIword iw0, disassemble_info *outf)
1208{
b7d48530
NC		 1209 /* CC2stat
1210 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1211 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
1212 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1213 int D = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask);
1214 int op = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask);
1215 int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask);
1216
b2459327 1217 const char *bitname = statbits (cbit);
219b747a
MF		 1218
1219 if (parallel)
1220 return 0;
1221
b2459327
MF		 1222 if (decode_statbits[cbit] == REG_LASTREG)
1223 {
1224 /* All ASTAT bits except CC may be operated on in hardware, but may
1225 not have a dedicated insn, so still decode "valid" insns. */
1226 static char bitnames[64];
1227 if (cbit != 5)
1228 sprintf (bitnames, "ASTAT[%i /* unused bit */]", cbit);
1229 else
219b747a
MF		 1230 return 0;
1231
b2459327
MF		 1232 bitname = bitnames;
1233 }
1234
4b7f6baa
CM		 1235 if (op == 0 && D == 0)
1236 {
4b7f6baa 1237 OUTS (outf, "CC = ");
b2459327 1238 OUTS (outf, bitname);
4b7f6baa
CM		 1239 }
1240 else if (op == 1 && D == 0)
1241 {
086134ec 1242 OUTS (outf, "CC |= ");
b2459327 1243 OUTS (outf, bitname);
4b7f6baa
CM		 1244 }
1245 else if (op == 2 && D == 0)
1246 {
086134ec 1247 OUTS (outf, "CC &= ");
b2459327 1248 OUTS (outf, bitname);
4b7f6baa
CM		 1249 }
1250 else if (op == 3 && D == 0)
1251 {
086134ec 1252 OUTS (outf, "CC ^= ");
b2459327 1253 OUTS (outf, bitname);
4b7f6baa
CM		 1254 }
1255 else if (op == 0 && D == 1)
1256 {
b2459327 1257 OUTS (outf, bitname);
086134ec 1258 OUTS (outf, " = CC");
4b7f6baa
CM		 1259 }
1260 else if (op == 1 && D == 1)
1261 {
b2459327 1262 OUTS (outf, bitname);
086134ec 1263 OUTS (outf, " |= CC");
4b7f6baa
CM		 1264 }
1265 else if (op == 2 && D == 1)
1266 {
b2459327 1267 OUTS (outf, bitname);
086134ec 1268 OUTS (outf, " &= CC");
4b7f6baa
CM		 1269 }
1270 else if (op == 3 && D == 1)
1271 {
b2459327 1272 OUTS (outf, bitname);
086134ec 1273 OUTS (outf, " ^= CC");
4b7f6baa
CM		 1274 }
1275 else
b7d48530
NC		 1276 return 0;
1277
1278 return 2;
4b7f6baa
CM		 1279}
1280
1281static int
1282decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1283{
b7d48530
NC		 1284 /* BRCC
1285 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1286 | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
1287 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1288 int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask);
1289 int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask);
1290 int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask);
1291
219b747a
MF		 1292 if (parallel)
1293 return 0;
1294
4b7f6baa
CM		 1295 if (T == 1 && B == 1)
1296 {
086134ec 1297 OUTS (outf, "IF CC JUMP 0x");
4b7f6baa 1298 OUTS (outf, pcrel10 (offset));
086134ec 1299 OUTS (outf, " (BP)");
4b7f6baa
CM		 1300 }
1301 else if (T == 0 && B == 1)
1302 {
086134ec 1303 OUTS (outf, "IF !CC JUMP 0x");
4b7f6baa 1304 OUTS (outf, pcrel10 (offset));
086134ec 1305 OUTS (outf, " (BP)");
4b7f6baa
CM		 1306 }
1307 else if (T == 1)
1308 {
086134ec 1309 OUTS (outf, "IF CC JUMP 0x");
4b7f6baa 1310 OUTS (outf, pcrel10 (offset));
4b7f6baa
CM		 1311 }
1312 else if (T == 0)
1313 {
086134ec 1314 OUTS (outf, "IF !CC JUMP 0x");
4b7f6baa 1315 OUTS (outf, pcrel10 (offset));
4b7f6baa
CM		 1316 }
1317 else
b7d48530
NC		 1318 return 0;
1319
1320 return 2;
4b7f6baa
CM		 1321}
1322
1323static int
1324decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1325{
b7d48530
NC		 1326 /* UJUMP
1327 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1328 | 0 | 0 | 1 | 0 |.offset........................................|
1329 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1330 int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask);
1331
219b747a
MF		 1332 if (parallel)
1333 return 0;
1334
086134ec 1335 OUTS (outf, "JUMP.S 0x");
4b7f6baa 1336 OUTS (outf, pcrel12 (offset));
b7d48530 1337 return 2;
4b7f6baa
CM		 1338}
1339
1340static int
1341decode_REGMV_0 (TIword iw0, disassemble_info *outf)
1342{
b7d48530
NC		 1343 /* REGMV
1344 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1345 | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
1346 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1347 int gs = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask);
1348 int gd = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask);
1349 int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
1350 int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
1351
602427c4 1352 /* Reserved slots cannot be a src/dst. */
35fc57f3
MF		 1353 if (IS_RESERVEDREG (gs, src) || IS_RESERVEDREG (gd, dst))
1354 goto invalid_move;
1355
1356 /* Standard register moves */
1357 if ((gs < 2) || /* Dregs/Pregs as source */
1358 (gd < 2) || /* Dregs/Pregs as dest */
1359 (gs == 4 && src < 4) || /* Accumulators as source */
1360 (gd == 4 && dst < 4 && (gs < 4)) || /* Accumulators as dest */
1361 (gs == 7 && src == 7 && !(gd == 4 && dst < 4)) || /* EMUDAT as src */
1362 (gd == 7 && dst == 7)) /* EMUDAT as dest */
1363 goto valid_move;
1364
1365 /* dareg = dareg (IMBL) */
1366 if (gs < 4 && gd < 4)
1367 goto valid_move;
1368
1369 /* USP can be src to sysregs, but not dagregs. */
1370 if ((gs == 7 && src == 0) && (gd >= 4))
1371 goto valid_move;
1372
1373 /* USP can move between genregs (only check Accumulators). */
1374 if (((gs == 7 && src == 0) && (gd == 4 && dst < 4)) ||
1375 ((gd == 7 && dst == 0) && (gs == 4 && src < 4)))
1376 goto valid_move;
1377
1378 /* Still here ? Invalid reg pair. */
1379 invalid_move:
1380 return 0;
c958a8a8 1381
35fc57f3 1382 valid_move:
4b7f6baa 1383 OUTS (outf, allregs (dst, gd));
086134ec 1384 OUTS (outf, " = ");
4b7f6baa 1385 OUTS (outf, allregs (src, gs));
b7d48530 1386 return 2;
4b7f6baa
CM		 1387}
1388
1389static int
1390decode_ALU2op_0 (TIword iw0, disassemble_info *outf)
1391{
b7d48530
NC		 1392 /* ALU2op
1393 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1394 | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
1395 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1396 int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask);
1397 int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask);
1398 int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask);
1399
1400 if (opc == 0)
1401 {
4b7f6baa 1402 OUTS (outf, dregs (dst));
086134ec 1403 OUTS (outf, " >>>= ");
4b7f6baa 1404 OUTS (outf, dregs (src));
4b7f6baa
CM		 1405 }
1406 else if (opc == 1)
1407 {
4b7f6baa 1408 OUTS (outf, dregs (dst));
086134ec 1409 OUTS (outf, " >>= ");
4b7f6baa 1410 OUTS (outf, dregs (src));
4b7f6baa
CM		 1411 }
1412 else if (opc == 2)
1413 {
4b7f6baa 1414 OUTS (outf, dregs (dst));
086134ec 1415 OUTS (outf, " <<= ");
4b7f6baa 1416 OUTS (outf, dregs (src));
4b7f6baa
CM		 1417 }
1418 else if (opc == 3)
1419 {
4b7f6baa 1420 OUTS (outf, dregs (dst));
086134ec 1421 OUTS (outf, " *= ");
4b7f6baa 1422 OUTS (outf, dregs (src));
4b7f6baa
CM		 1423 }
1424 else if (opc == 4)
1425 {
4b7f6baa 1426 OUTS (outf, dregs (dst));
086134ec 1427 OUTS (outf, " = (");
4b7f6baa 1428 OUTS (outf, dregs (dst));
086134ec 1429 OUTS (outf, " + ");
4b7f6baa 1430 OUTS (outf, dregs (src));
086134ec 1431 OUTS (outf, ") << 0x1");
4b7f6baa
CM		 1432 }
1433 else if (opc == 5)
1434 {
4b7f6baa 1435 OUTS (outf, dregs (dst));
086134ec 1436 OUTS (outf, " = (");
4b7f6baa 1437 OUTS (outf, dregs (dst));
086134ec 1438 OUTS (outf, " + ");
4b7f6baa 1439 OUTS (outf, dregs (src));
086134ec 1440 OUTS (outf, ") << 0x2");
4b7f6baa
CM		 1441 }
1442 else if (opc == 8)
1443 {
086134ec 1444 OUTS (outf, "DIVQ (");
4b7f6baa 1445 OUTS (outf, dregs (dst));
086134ec 1446 OUTS (outf, ", ");
4b7f6baa
CM		 1447 OUTS (outf, dregs (src));
1448 OUTS (outf, ")");
4b7f6baa
CM		 1449 }
1450 else if (opc == 9)
1451 {
086134ec 1452 OUTS (outf, "DIVS (");
4b7f6baa 1453 OUTS (outf, dregs (dst));
086134ec 1454 OUTS (outf, ", ");
4b7f6baa
CM		 1455 OUTS (outf, dregs (src));
1456 OUTS (outf, ")");
4b7f6baa
CM		 1457 }
1458 else if (opc == 10)
1459 {
4b7f6baa 1460 OUTS (outf, dregs (dst));
086134ec 1461 OUTS (outf, " = ");
4b7f6baa 1462 OUTS (outf, dregs_lo (src));
086134ec 1463 OUTS (outf, " (X)");
4b7f6baa
CM		 1464 }
1465 else if (opc == 11)
1466 {
4b7f6baa 1467 OUTS (outf, dregs (dst));
086134ec 1468 OUTS (outf, " = ");
4b7f6baa 1469 OUTS (outf, dregs_lo (src));
086134ec 1470 OUTS (outf, " (Z)");
4b7f6baa
CM		 1471 }
1472 else if (opc == 12)
1473 {
4b7f6baa 1474 OUTS (outf, dregs (dst));
086134ec 1475 OUTS (outf, " = ");
4b7f6baa 1476 OUTS (outf, dregs_byte (src));
086134ec 1477 OUTS (outf, " (X)");
4b7f6baa
CM		 1478 }
1479 else if (opc == 13)
1480 {
4b7f6baa 1481 OUTS (outf, dregs (dst));
086134ec 1482 OUTS (outf, " = ");
4b7f6baa 1483 OUTS (outf, dregs_byte (src));
086134ec 1484 OUTS (outf, " (Z)");
4b7f6baa
CM		 1485 }
1486 else if (opc == 14)
1487 {
4b7f6baa 1488 OUTS (outf, dregs (dst));
086134ec 1489 OUTS (outf, " = -");
4b7f6baa 1490 OUTS (outf, dregs (src));
4b7f6baa
CM		 1491 }
1492 else if (opc == 15)
1493 {
4b7f6baa 1494 OUTS (outf, dregs (dst));
086134ec 1495 OUTS (outf, " =~ ");
4b7f6baa 1496 OUTS (outf, dregs (src));
4b7f6baa
CM		 1497 }
1498 else
b7d48530
NC		 1499 return 0;
1500
1501 return 2;
4b7f6baa
CM		 1502}
1503
1504static int
1505decode_PTR2op_0 (TIword iw0, disassemble_info *outf)
1506{
b7d48530
NC		 1507 /* PTR2op
1508 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1509 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
1510 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1511 int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask);
1512 int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask);
1513 int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask);
1514
1515 if (opc == 0)
1516 {
4b7f6baa 1517 OUTS (outf, pregs (dst));
086134ec 1518 OUTS (outf, " -= ");
4b7f6baa 1519 OUTS (outf, pregs (src));
4b7f6baa
CM		 1520 }
1521 else if (opc == 1)
1522 {
4b7f6baa 1523 OUTS (outf, pregs (dst));
086134ec 1524 OUTS (outf, " = ");
4b7f6baa 1525 OUTS (outf, pregs (src));
086134ec 1526 OUTS (outf, " << 0x2");
4b7f6baa
CM		 1527 }
1528 else if (opc == 3)
1529 {
4b7f6baa 1530 OUTS (outf, pregs (dst));
086134ec 1531 OUTS (outf, " = ");
4b7f6baa 1532 OUTS (outf, pregs (src));
086134ec 1533 OUTS (outf, " >> 0x2");
4b7f6baa
CM		 1534 }
1535 else if (opc == 4)
1536 {
4b7f6baa 1537 OUTS (outf, pregs (dst));
086134ec 1538 OUTS (outf, " = ");
4b7f6baa 1539 OUTS (outf, pregs (src));
086134ec 1540 OUTS (outf, " >> 0x1");
4b7f6baa
CM		 1541 }
1542 else if (opc == 5)
1543 {
4b7f6baa 1544 OUTS (outf, pregs (dst));
086134ec 1545 OUTS (outf, " += ");
4b7f6baa 1546 OUTS (outf, pregs (src));
086134ec 1547 OUTS (outf, " (BREV)");
4b7f6baa
CM		 1548 }
1549 else if (opc == 6)
1550 {
4b7f6baa 1551 OUTS (outf, pregs (dst));
086134ec 1552 OUTS (outf, " = (");
4b7f6baa 1553 OUTS (outf, pregs (dst));
086134ec 1554 OUTS (outf, " + ");
4b7f6baa 1555 OUTS (outf, pregs (src));
086134ec 1556 OUTS (outf, ") << 0x1");
4b7f6baa
CM		 1557 }
1558 else if (opc == 7)
1559 {
4b7f6baa 1560 OUTS (outf, pregs (dst));
086134ec 1561 OUTS (outf, " = (");
4b7f6baa 1562 OUTS (outf, pregs (dst));
086134ec 1563 OUTS (outf, " + ");
4b7f6baa 1564 OUTS (outf, pregs (src));
086134ec 1565 OUTS (outf, ") << 0x2");
4b7f6baa
CM		 1566 }
1567 else
b7d48530
NC		 1568 return 0;
1569
1570 return 2;
4b7f6baa
CM		 1571}
1572
1573static int
1574decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
1575{
b7d48530
NC		 1576 /* LOGI2op
1577 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1578 | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
1579 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1580 int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask);
1581 int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask);
1582 int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask);
1583
219b747a
MF		 1584 if (parallel)
1585 return 0;
1586
4b7f6baa
CM		 1587 if (opc == 0)
1588 {
086134ec 1589 OUTS (outf, "CC = !BITTST (");
4b7f6baa 1590 OUTS (outf, dregs (dst));
086134ec 1591 OUTS (outf, ", ");
4b7f6baa 1592 OUTS (outf, uimm5 (src));
086134ec
BS		 1593 OUTS (outf, ");\t\t/* bit");
1594 OUTS (outf, imm7d (src));
1595 OUTS (outf, " */");
1596 comment = 1;
4b7f6baa
CM		 1597 }
1598 else if (opc == 1)
1599 {
4b7f6baa
CM		 1600 OUTS (outf, "CC = BITTST (");
1601 OUTS (outf, dregs (dst));
086134ec 1602 OUTS (outf, ", ");
4b7f6baa 1603 OUTS (outf, uimm5 (src));
086134ec
BS		 1604 OUTS (outf, ");\t\t/* bit");
1605 OUTS (outf, imm7d (src));
1606 OUTS (outf, " */");
1607 comment = 1;
4b7f6baa
CM		 1608 }
1609 else if (opc == 2)
1610 {
4b7f6baa
CM		 1611 OUTS (outf, "BITSET (");
1612 OUTS (outf, dregs (dst));
086134ec 1613 OUTS (outf, ", ");
4b7f6baa 1614 OUTS (outf, uimm5 (src));
086134ec
BS		 1615 OUTS (outf, ");\t\t/* bit");
1616 OUTS (outf, imm7d (src));
1617 OUTS (outf, " */");
1618 comment = 1;
4b7f6baa
CM		 1619 }
1620 else if (opc == 3)
1621 {
4b7f6baa
CM		 1622 OUTS (outf, "BITTGL (");
1623 OUTS (outf, dregs (dst));
086134ec 1624 OUTS (outf, ", ");
4b7f6baa 1625 OUTS (outf, uimm5 (src));
086134ec
BS		 1626 OUTS (outf, ");\t\t/* bit");
1627 OUTS (outf, imm7d (src));
1628 OUTS (outf, " */");
1629 comment = 1;
4b7f6baa
CM		 1630 }
1631 else if (opc == 4)
1632 {
4b7f6baa
CM		 1633 OUTS (outf, "BITCLR (");
1634 OUTS (outf, dregs (dst));
086134ec 1635 OUTS (outf, ", ");
4b7f6baa 1636 OUTS (outf, uimm5 (src));
086134ec
BS		 1637 OUTS (outf, ");\t\t/* bit");
1638 OUTS (outf, imm7d (src));
1639 OUTS (outf, " */");
1640 comment = 1;
4b7f6baa
CM		 1641 }
1642 else if (opc == 5)
1643 {
4b7f6baa 1644 OUTS (outf, dregs (dst));
086134ec 1645 OUTS (outf, " >>>= ");
4b7f6baa 1646 OUTS (outf, uimm5 (src));
4b7f6baa
CM		 1647 }
1648 else if (opc == 6)
1649 {
4b7f6baa 1650 OUTS (outf, dregs (dst));
086134ec 1651 OUTS (outf, " >>= ");
4b7f6baa 1652 OUTS (outf, uimm5 (src));
4b7f6baa
CM		 1653 }
1654 else if (opc == 7)
1655 {
4b7f6baa 1656 OUTS (outf, dregs (dst));
086134ec 1657 OUTS (outf, " <<= ");
4b7f6baa 1658 OUTS (outf, uimm5 (src));
4b7f6baa
CM		 1659 }
1660 else
b7d48530
NC		 1661 return 0;
1662
1663 return 2;
4b7f6baa
CM		 1664}
1665
1666static int
1667decode_COMP3op_0 (TIword iw0, disassemble_info *outf)
1668{
b7d48530
NC		 1669 /* COMP3op
1670 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1671 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1672 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1673 int opc = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask);
1674 int dst = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask);
1675 int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask);
1676 int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask);
1677
1678 if (opc == 5 && src1 == src0)
1679 {
4b7f6baa 1680 OUTS (outf, pregs (dst));
086134ec 1681 OUTS (outf, " = ");
4b7f6baa 1682 OUTS (outf, pregs (src0));
086134ec 1683 OUTS (outf, " << 0x1");
4b7f6baa
CM		 1684 }
1685 else if (opc == 1)
1686 {
4b7f6baa 1687 OUTS (outf, dregs (dst));
086134ec 1688 OUTS (outf, " = ");
4b7f6baa 1689 OUTS (outf, dregs (src0));
086134ec 1690 OUTS (outf, " - ");
4b7f6baa 1691 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1692 }
1693 else if (opc == 2)
1694 {
4b7f6baa 1695 OUTS (outf, dregs (dst));
086134ec 1696 OUTS (outf, " = ");
4b7f6baa 1697 OUTS (outf, dregs (src0));
086134ec 1698 OUTS (outf, " & ");
4b7f6baa 1699 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1700 }
1701 else if (opc == 3)
1702 {
4b7f6baa 1703 OUTS (outf, dregs (dst));
086134ec 1704 OUTS (outf, " = ");
4b7f6baa 1705 OUTS (outf, dregs (src0));
086134ec 1706 OUTS (outf, " | ");
4b7f6baa 1707 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1708 }
1709 else if (opc == 4)
1710 {
4b7f6baa 1711 OUTS (outf, dregs (dst));
086134ec 1712 OUTS (outf, " = ");
4b7f6baa 1713 OUTS (outf, dregs (src0));
086134ec 1714 OUTS (outf, " ^ ");
4b7f6baa 1715 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1716 }
1717 else if (opc == 5)
1718 {
4b7f6baa 1719 OUTS (outf, pregs (dst));
086134ec 1720 OUTS (outf, " = ");
4b7f6baa 1721 OUTS (outf, pregs (src0));
086134ec 1722 OUTS (outf, " + ");
4b7f6baa 1723 OUTS (outf, pregs (src1));
4b7f6baa
CM		 1724 }
1725 else if (opc == 6)
1726 {
4b7f6baa 1727 OUTS (outf, pregs (dst));
086134ec 1728 OUTS (outf, " = ");
4b7f6baa 1729 OUTS (outf, pregs (src0));
086134ec 1730 OUTS (outf, " + (");
4b7f6baa 1731 OUTS (outf, pregs (src1));
086134ec 1732 OUTS (outf, " << 0x1)");
4b7f6baa
CM		 1733 }
1734 else if (opc == 7)
1735 {
4b7f6baa 1736 OUTS (outf, pregs (dst));
086134ec 1737 OUTS (outf, " = ");
4b7f6baa 1738 OUTS (outf, pregs (src0));
086134ec 1739 OUTS (outf, " + (");
4b7f6baa 1740 OUTS (outf, pregs (src1));
086134ec 1741 OUTS (outf, " << 0x2)");
4b7f6baa
CM		 1742 }
1743 else if (opc == 0)
1744 {
4b7f6baa 1745 OUTS (outf, dregs (dst));
086134ec 1746 OUTS (outf, " = ");
4b7f6baa 1747 OUTS (outf, dregs (src0));
086134ec 1748 OUTS (outf, " + ");
4b7f6baa 1749 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1750 }
1751 else
b7d48530
NC		 1752 return 0;
1753
1754 return 2;
4b7f6baa
CM		 1755}
1756
1757static int
1758decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf)
1759{
b7d48530
NC		 1760 /* COMPI2opD
1761 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1762 | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......|
1763 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1764 int op = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask);
1765 int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask);
1766 int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask);
1767
086134ec
BS		 1768 bu32 *pval = get_allreg (0, dst);
1769
219b747a
MF		 1770 if (parallel)
1771 return 0;
1772
086134ec
BS		 1773 /* Since we don't have 32-bit immediate loads, we allow the disassembler
1774 to combine them, so it prints out the right values.
1775 Here we keep track of the registers. */
1776 if (op == 0)
1777 {
1778 *pval = imm7_val (src);
1779 if (src & 0x40)
1780 *pval |= 0xFFFFFF80;
1781 else
1782 *pval &= 0x7F;
1783 }
1784
4b7f6baa
CM		 1785 if (op == 0)
1786 {
4b7f6baa 1787 OUTS (outf, dregs (dst));
086134ec 1788 OUTS (outf, " = ");
4b7f6baa 1789 OUTS (outf, imm7 (src));
086134ec
BS		 1790 OUTS (outf, " (X);\t\t/*\t\t");
1791 OUTS (outf, dregs (dst));
1792 OUTS (outf, "=");
1793 OUTS (outf, uimm32 (*pval));
1794 OUTS (outf, "(");
1795 OUTS (outf, imm32 (*pval));
1796 OUTS (outf, ") */");
1797 comment = 1;
4b7f6baa
CM		 1798 }
1799 else if (op == 1)
1800 {
4b7f6baa 1801 OUTS (outf, dregs (dst));
086134ec 1802 OUTS (outf, " += ");
4b7f6baa 1803 OUTS (outf, imm7 (src));
086134ec
BS		 1804 OUTS (outf, ";\t\t/* (");
1805 OUTS (outf, imm7d (src));
1806 OUTS (outf, ") */");
1807 comment = 1;
4b7f6baa
CM		 1808 }
1809 else
b7d48530
NC		 1810 return 0;
1811
1812 return 2;
4b7f6baa
CM		 1813}
1814
1815static int
1816decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf)
1817{
b7d48530
NC		 1818 /* COMPI2opP
1819 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1820 | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
1821 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1822 int op = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask);
1823 int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask);
1824 int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask);
1825
086134ec
BS		 1826 bu32 *pval = get_allreg (1, dst);
1827
219b747a
MF		 1828 if (parallel)
1829 return 0;
1830
086134ec
BS		 1831 if (op == 0)
1832 {
1833 *pval = imm7_val (src);
1834 if (src & 0x40)
1835 *pval |= 0xFFFFFF80;
1836 else
1837 *pval &= 0x7F;
1838 }
1839
4b7f6baa
CM		 1840 if (op == 0)
1841 {
4b7f6baa 1842 OUTS (outf, pregs (dst));
086134ec 1843 OUTS (outf, " = ");
4b7f6baa 1844 OUTS (outf, imm7 (src));
086134ec
BS		 1845 OUTS (outf, " (X);\t\t/*\t\t");
1846 OUTS (outf, pregs (dst));
1847 OUTS (outf, "=");
1848 OUTS (outf, uimm32 (*pval));
1849 OUTS (outf, "(");
1850 OUTS (outf, imm32 (*pval));
1851 OUTS (outf, ") */");
1852 comment = 1;
4b7f6baa
CM		 1853 }
1854 else if (op == 1)
1855 {
4b7f6baa 1856 OUTS (outf, pregs (dst));
086134ec 1857 OUTS (outf, " += ");
4b7f6baa 1858 OUTS (outf, imm7 (src));
086134ec
BS		 1859 OUTS (outf, ";\t\t/* (");
1860 OUTS (outf, imm7d (src));
1861 OUTS (outf, ") */");
1862 comment = 1;
4b7f6baa
CM		 1863 }
1864 else
b7d48530
NC		 1865 return 0;
1866
1867 return 2;
4b7f6baa
CM		 1868}
1869
1870static int
1871decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf)
1872{
b7d48530
NC		 1873 /* LDSTpmod
1874 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1875 | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
1876 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1877 int W = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask);
1878 int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask);
1879 int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask);
1880 int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask);
1881 int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask);
1882
1883 if (aop == 1 && W == 0 && idx == ptr)
1884 {
4b7f6baa 1885 OUTS (outf, dregs_lo (reg));
086134ec 1886 OUTS (outf, " = W[");
4b7f6baa
CM		 1887 OUTS (outf, pregs (ptr));
1888 OUTS (outf, "]");
4b7f6baa
CM		 1889 }
1890 else if (aop == 2 && W == 0 && idx == ptr)
1891 {
4b7f6baa 1892 OUTS (outf, dregs_hi (reg));
086134ec 1893 OUTS (outf, " = W[");
4b7f6baa
CM		 1894 OUTS (outf, pregs (ptr));
1895 OUTS (outf, "]");
4b7f6baa
CM		 1896 }
1897 else if (aop == 1 && W == 1 && idx == ptr)
1898 {
4b7f6baa
CM		 1899 OUTS (outf, "W[");
1900 OUTS (outf, pregs (ptr));
086134ec 1901 OUTS (outf, "] = ");
4b7f6baa 1902 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 1903 }
1904 else if (aop == 2 && W == 1 && idx == ptr)
1905 {
4b7f6baa
CM		 1906 OUTS (outf, "W[");
1907 OUTS (outf, pregs (ptr));
086134ec 1908 OUTS (outf, "] = ");
4b7f6baa 1909 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 1910 }
1911 else if (aop == 0 && W == 0)
1912 {
4b7f6baa 1913 OUTS (outf, dregs (reg));
086134ec 1914 OUTS (outf, " = [");
4b7f6baa 1915 OUTS (outf, pregs (ptr));
086134ec 1916 OUTS (outf, " ++ ");
4b7f6baa
CM		 1917 OUTS (outf, pregs (idx));
1918 OUTS (outf, "]");
4b7f6baa
CM		 1919 }
1920 else if (aop == 1 && W == 0)
1921 {
4b7f6baa 1922 OUTS (outf, dregs_lo (reg));
086134ec 1923 OUTS (outf, " = W[");
4b7f6baa 1924 OUTS (outf, pregs (ptr));
086134ec 1925 OUTS (outf, " ++ ");
4b7f6baa
CM		 1926 OUTS (outf, pregs (idx));
1927 OUTS (outf, "]");
4b7f6baa
CM		 1928 }
1929 else if (aop == 2 && W == 0)
1930 {
4b7f6baa 1931 OUTS (outf, dregs_hi (reg));
086134ec 1932 OUTS (outf, " = W[");
4b7f6baa 1933 OUTS (outf, pregs (ptr));
086134ec 1934 OUTS (outf, " ++ ");
4b7f6baa
CM		 1935 OUTS (outf, pregs (idx));
1936 OUTS (outf, "]");
4b7f6baa
CM		 1937 }
1938 else if (aop == 3 && W == 0)
1939 {
4b7f6baa 1940 OUTS (outf, dregs (reg));
086134ec 1941 OUTS (outf, " = W[");
4b7f6baa 1942 OUTS (outf, pregs (ptr));
086134ec 1943 OUTS (outf, " ++ ");
4b7f6baa
CM		 1944 OUTS (outf, pregs (idx));
1945 OUTS (outf, "] (Z)");
4b7f6baa
CM		 1946 }
1947 else if (aop == 3 && W == 1)
1948 {
4b7f6baa 1949 OUTS (outf, dregs (reg));
086134ec 1950 OUTS (outf, " = W[");
4b7f6baa 1951 OUTS (outf, pregs (ptr));
086134ec 1952 OUTS (outf, " ++ ");
4b7f6baa 1953 OUTS (outf, pregs (idx));
086134ec 1954 OUTS (outf, "] (X)");
4b7f6baa
CM		 1955 }
1956 else if (aop == 0 && W == 1)
1957 {
4b7f6baa
CM		 1958 OUTS (outf, "[");
1959 OUTS (outf, pregs (ptr));
086134ec 1960 OUTS (outf, " ++ ");
4b7f6baa 1961 OUTS (outf, pregs (idx));
086134ec 1962 OUTS (outf, "] = ");
4b7f6baa 1963 OUTS (outf, dregs (reg));
4b7f6baa
CM		 1964 }
1965 else if (aop == 1 && W == 1)
1966 {
4b7f6baa
CM		 1967 OUTS (outf, "W[");
1968 OUTS (outf, pregs (ptr));
086134ec 1969 OUTS (outf, " ++ ");
4b7f6baa 1970 OUTS (outf, pregs (idx));
086134ec 1971 OUTS (outf, "] = ");
4b7f6baa 1972 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 1973 }
1974 else if (aop == 2 && W == 1)
1975 {
4b7f6baa
CM		 1976 OUTS (outf, "W[");
1977 OUTS (outf, pregs (ptr));
086134ec 1978 OUTS (outf, " ++ ");
4b7f6baa 1979 OUTS (outf, pregs (idx));
086134ec 1980 OUTS (outf, "] = ");
4b7f6baa 1981 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 1982 }
1983 else
b7d48530
NC		 1984 return 0;
1985
1986 return 2;
4b7f6baa
CM		 1987}
1988
1989static int
1990decode_dagMODim_0 (TIword iw0, disassemble_info *outf)
1991{
b7d48530
NC		 1992 /* dagMODim
1993 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1994 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
1995 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1996 int i = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
1997 int m = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask);
1998 int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask);
1999 int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
2000
2001 if (op == 0 && br == 1)
2002 {
4b7f6baa 2003 OUTS (outf, iregs (i));
086134ec 2004 OUTS (outf, " += ");
4b7f6baa 2005 OUTS (outf, mregs (m));
086134ec 2006 OUTS (outf, " (BREV)");
4b7f6baa
CM		 2007 }
2008 else if (op == 0)
2009 {
4b7f6baa 2010 OUTS (outf, iregs (i));
086134ec 2011 OUTS (outf, " += ");
4b7f6baa 2012 OUTS (outf, mregs (m));
4b7f6baa 2013 }
219b747a 2014 else if (op == 1 && br == 0)
4b7f6baa 2015 {
4b7f6baa 2016 OUTS (outf, iregs (i));
086134ec 2017 OUTS (outf, " -= ");
4b7f6baa 2018 OUTS (outf, mregs (m));
4b7f6baa
CM		 2019 }
2020 else
b7d48530
NC		 2021 return 0;
2022
2023 return 2;
4b7f6baa
CM		 2024}
2025
2026static int
2027decode_dagMODik_0 (TIword iw0, disassemble_info *outf)
2028{
b7d48530
NC		 2029 /* dagMODik
2030 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2031 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
2032 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2033 int i = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
2034 int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask);
2035
2036 if (op == 0)
2037 {
4b7f6baa 2038 OUTS (outf, iregs (i));
086134ec 2039 OUTS (outf, " += 0x2");
4b7f6baa
CM		 2040 }
2041 else if (op == 1)
2042 {
4b7f6baa 2043 OUTS (outf, iregs (i));
086134ec 2044 OUTS (outf, " -= 0x2");
4b7f6baa
CM		 2045 }
2046 else if (op == 2)
2047 {
4b7f6baa 2048 OUTS (outf, iregs (i));
086134ec 2049 OUTS (outf, " += 0x4");
4b7f6baa
CM		 2050 }
2051 else if (op == 3)
2052 {
4b7f6baa 2053 OUTS (outf, iregs (i));
086134ec 2054 OUTS (outf, " -= 0x4");
4b7f6baa
CM		 2055 }
2056 else
b7d48530
NC		 2057 return 0;
2058
602427c4
MF		 2059 if (! parallel)
2060 {
2061 OUTS (outf, ";\t\t/* ( ");
2062 if (op == 0 || op == 1)
2063 OUTS (outf, "2");
2064 else if (op == 2 || op == 3)
086134ec 2065 OUTS (outf, "4");
602427c4
MF		 2066 OUTS (outf, ") */");
2067 comment = 1;
2068 }
086134ec 2069
b7d48530 2070 return 2;
4b7f6baa
CM		 2071}
2072
2073static int
2074decode_dspLDST_0 (TIword iw0, disassemble_info *outf)
2075{
b7d48530
NC		 2076 /* dspLDST
2077 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2078 | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
2079 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2080 int i = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
2081 int m = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask);
2082 int W = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask);
2083 int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask);
2084 int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask);
2085
2086 if (aop == 0 && W == 0 && m == 0)
2087 {
4b7f6baa 2088 OUTS (outf, dregs (reg));
086134ec 2089 OUTS (outf, " = [");
4b7f6baa
CM		 2090 OUTS (outf, iregs (i));
2091 OUTS (outf, "++]");
4b7f6baa
CM		 2092 }
2093 else if (aop == 0 && W == 0 && m == 1)
2094 {
4b7f6baa 2095 OUTS (outf, dregs_lo (reg));
086134ec 2096 OUTS (outf, " = W[");
4b7f6baa
CM		 2097 OUTS (outf, iregs (i));
2098 OUTS (outf, "++]");
4b7f6baa
CM		 2099 }
2100 else if (aop == 0 && W == 0 && m == 2)
2101 {
4b7f6baa 2102 OUTS (outf, dregs_hi (reg));
086134ec 2103 OUTS (outf, " = W[");
4b7f6baa
CM		 2104 OUTS (outf, iregs (i));
2105 OUTS (outf, "++]");
4b7f6baa
CM		 2106 }
2107 else if (aop == 1 && W == 0 && m == 0)
2108 {
4b7f6baa 2109 OUTS (outf, dregs (reg));
086134ec 2110 OUTS (outf, " = [");
4b7f6baa
CM		 2111 OUTS (outf, iregs (i));
2112 OUTS (outf, "--]");
4b7f6baa
CM		 2113 }
2114 else if (aop == 1 && W == 0 && m == 1)
2115 {
4b7f6baa 2116 OUTS (outf, dregs_lo (reg));
086134ec 2117 OUTS (outf, " = W[");
4b7f6baa
CM		 2118 OUTS (outf, iregs (i));
2119 OUTS (outf, "--]");
4b7f6baa
CM		 2120 }
2121 else if (aop == 1 && W == 0 && m == 2)
2122 {
4b7f6baa 2123 OUTS (outf, dregs_hi (reg));
086134ec 2124 OUTS (outf, " = W[");
4b7f6baa
CM		 2125 OUTS (outf, iregs (i));
2126 OUTS (outf, "--]");
4b7f6baa
CM		 2127 }
2128 else if (aop == 2 && W == 0 && m == 0)
2129 {
4b7f6baa 2130 OUTS (outf, dregs (reg));
086134ec 2131 OUTS (outf, " = [");
4b7f6baa
CM		 2132 OUTS (outf, iregs (i));
2133 OUTS (outf, "]");
4b7f6baa
CM		 2134 }
2135 else if (aop == 2 && W == 0 && m == 1)
2136 {
4b7f6baa 2137 OUTS (outf, dregs_lo (reg));
086134ec 2138 OUTS (outf, " = W[");
4b7f6baa
CM		 2139 OUTS (outf, iregs (i));
2140 OUTS (outf, "]");
4b7f6baa
CM		 2141 }
2142 else if (aop == 2 && W == 0 && m == 2)
2143 {
4b7f6baa 2144 OUTS (outf, dregs_hi (reg));
086134ec 2145 OUTS (outf, " = W[");
4b7f6baa
CM		 2146 OUTS (outf, iregs (i));
2147 OUTS (outf, "]");
4b7f6baa
CM		 2148 }
2149 else if (aop == 0 && W == 1 && m == 0)
2150 {
4b7f6baa
CM		 2151 OUTS (outf, "[");
2152 OUTS (outf, iregs (i));
086134ec 2153 OUTS (outf, "++] = ");
4b7f6baa 2154 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2155 }
2156 else if (aop == 0 && W == 1 && m == 1)
2157 {
4b7f6baa
CM		 2158 OUTS (outf, "W[");
2159 OUTS (outf, iregs (i));
086134ec 2160 OUTS (outf, "++] = ");
4b7f6baa 2161 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 2162 }
2163 else if (aop == 0 && W == 1 && m == 2)
2164 {
4b7f6baa
CM		 2165 OUTS (outf, "W[");
2166 OUTS (outf, iregs (i));
086134ec 2167 OUTS (outf, "++] = ");
4b7f6baa 2168 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 2169 }
2170 else if (aop == 1 && W == 1 && m == 0)
2171 {
4b7f6baa
CM		 2172 OUTS (outf, "[");
2173 OUTS (outf, iregs (i));
086134ec 2174 OUTS (outf, "--] = ");
4b7f6baa 2175 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2176 }
2177 else if (aop == 1 && W == 1 && m == 1)
2178 {
4b7f6baa
CM		 2179 OUTS (outf, "W[");
2180 OUTS (outf, iregs (i));
086134ec 2181 OUTS (outf, "--] = ");
4b7f6baa 2182 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 2183 }
2184 else if (aop == 1 && W == 1 && m == 2)
2185 {
4b7f6baa
CM		 2186 OUTS (outf, "W[");
2187 OUTS (outf, iregs (i));
086134ec 2188 OUTS (outf, "--] = ");
4b7f6baa 2189 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 2190 }
2191 else if (aop == 2 && W == 1 && m == 0)
2192 {
4b7f6baa
CM		 2193 OUTS (outf, "[");
2194 OUTS (outf, iregs (i));
086134ec 2195 OUTS (outf, "] = ");
4b7f6baa 2196 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2197 }
2198 else if (aop == 2 && W == 1 && m == 1)
2199 {
4b7f6baa
CM		 2200 OUTS (outf, "W[");
2201 OUTS (outf, iregs (i));
086134ec 2202 OUTS (outf, "] = ");
4b7f6baa 2203 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 2204 }
2205 else if (aop == 2 && W == 1 && m == 2)
2206 {
4b7f6baa
CM		 2207 OUTS (outf, "W[");
2208 OUTS (outf, iregs (i));
086134ec 2209 OUTS (outf, "] = ");
4b7f6baa 2210 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 2211 }
2212 else if (aop == 3 && W == 0)
2213 {
4b7f6baa 2214 OUTS (outf, dregs (reg));
086134ec 2215 OUTS (outf, " = [");
4b7f6baa 2216 OUTS (outf, iregs (i));
086134ec 2217 OUTS (outf, " ++ ");
4b7f6baa
CM		 2218 OUTS (outf, mregs (m));
2219 OUTS (outf, "]");
4b7f6baa
CM		 2220 }
2221 else if (aop == 3 && W == 1)
2222 {
4b7f6baa
CM		 2223 OUTS (outf, "[");
2224 OUTS (outf, iregs (i));
086134ec 2225 OUTS (outf, " ++ ");
4b7f6baa 2226 OUTS (outf, mregs (m));
086134ec 2227 OUTS (outf, "] = ");
4b7f6baa 2228 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2229 }
2230 else
b7d48530
NC		 2231 return 0;
2232
2233 return 2;
4b7f6baa
CM		 2234}
2235
2236static int
2237decode_LDST_0 (TIword iw0, disassemble_info *outf)
2238{
b7d48530
NC		 2239 /* LDST
2240 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2241 | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
2242 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2243 int Z = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
2244 int W = ((iw0 >> LDST_W_bits) & LDST_W_mask);
2245 int sz = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
2246 int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
2247 int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
2248 int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask);
2249
2250 if (aop == 0 && sz == 0 && Z == 0 && W == 0)
2251 {
4b7f6baa 2252 OUTS (outf, dregs (reg));
086134ec 2253 OUTS (outf, " = [");
4b7f6baa
CM		 2254 OUTS (outf, pregs (ptr));
2255 OUTS (outf, "++]");
4b7f6baa 2256 }
219b747a 2257 else if (aop == 0 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
4b7f6baa 2258 {
4b7f6baa 2259 OUTS (outf, pregs (reg));
086134ec 2260 OUTS (outf, " = [");
4b7f6baa
CM		 2261 OUTS (outf, pregs (ptr));
2262 OUTS (outf, "++]");
4b7f6baa
CM		 2263 }
2264 else if (aop == 0 && sz == 1 && Z == 0 && W == 0)
2265 {
4b7f6baa 2266 OUTS (outf, dregs (reg));
086134ec 2267 OUTS (outf, " = W[");
4b7f6baa
CM		 2268 OUTS (outf, pregs (ptr));
2269 OUTS (outf, "++] (Z)");
4b7f6baa
CM		 2270 }
2271 else if (aop == 0 && sz == 1 && Z == 1 && W == 0)
2272 {
4b7f6baa 2273 OUTS (outf, dregs (reg));
086134ec 2274 OUTS (outf, " = W[");
4b7f6baa 2275 OUTS (outf, pregs (ptr));
086134ec 2276 OUTS (outf, "++] (X)");
4b7f6baa
CM		 2277 }
2278 else if (aop == 0 && sz == 2 && Z == 0 && W == 0)
2279 {
4b7f6baa 2280 OUTS (outf, dregs (reg));
086134ec 2281 OUTS (outf, " = B[");
4b7f6baa
CM		 2282 OUTS (outf, pregs (ptr));
2283 OUTS (outf, "++] (Z)");
4b7f6baa
CM		 2284 }
2285 else if (aop == 0 && sz == 2 && Z == 1 && W == 0)
2286 {
4b7f6baa 2287 OUTS (outf, dregs (reg));
086134ec 2288 OUTS (outf, " = B[");
4b7f6baa 2289 OUTS (outf, pregs (ptr));
086134ec 2290 OUTS (outf, "++] (X)");
4b7f6baa
CM		 2291 }
2292 else if (aop == 1 && sz == 0 && Z == 0 && W == 0)
2293 {
4b7f6baa 2294 OUTS (outf, dregs (reg));
086134ec 2295 OUTS (outf, " = [");
4b7f6baa
CM		 2296 OUTS (outf, pregs (ptr));
2297 OUTS (outf, "--]");
4b7f6baa 2298 }
219b747a 2299 else if (aop == 1 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
4b7f6baa 2300 {
4b7f6baa 2301 OUTS (outf, pregs (reg));
086134ec 2302 OUTS (outf, " = [");
4b7f6baa
CM		 2303 OUTS (outf, pregs (ptr));
2304 OUTS (outf, "--]");
4b7f6baa
CM		 2305 }
2306 else if (aop == 1 && sz == 1 && Z == 0 && W == 0)
2307 {
4b7f6baa 2308 OUTS (outf, dregs (reg));
086134ec 2309 OUTS (outf, " = W[");
4b7f6baa
CM		 2310 OUTS (outf, pregs (ptr));
2311 OUTS (outf, "--] (Z)");
4b7f6baa
CM		 2312 }
2313 else if (aop == 1 && sz == 1 && Z == 1 && W == 0)
2314 {
4b7f6baa 2315 OUTS (outf, dregs (reg));
086134ec 2316 OUTS (outf, " = W[");
4b7f6baa 2317 OUTS (outf, pregs (ptr));
086134ec 2318 OUTS (outf, "--] (X)");
4b7f6baa
CM		 2319 }
2320 else if (aop == 1 && sz == 2 && Z == 0 && W == 0)
2321 {
4b7f6baa 2322 OUTS (outf, dregs (reg));
086134ec 2323 OUTS (outf, " = B[");
4b7f6baa
CM		 2324 OUTS (outf, pregs (ptr));
2325 OUTS (outf, "--] (Z)");
4b7f6baa
CM		 2326 }
2327 else if (aop == 1 && sz == 2 && Z == 1 && W == 0)
2328 {
4b7f6baa 2329 OUTS (outf, dregs (reg));
086134ec 2330 OUTS (outf, " = B[");
4b7f6baa 2331 OUTS (outf, pregs (ptr));
086134ec 2332 OUTS (outf, "--] (X)");
4b7f6baa
CM		 2333 }
2334 else if (aop == 2 && sz == 0 && Z == 0 && W == 0)
2335 {
4b7f6baa 2336 OUTS (outf, dregs (reg));
086134ec 2337 OUTS (outf, " = [");
4b7f6baa
CM		 2338 OUTS (outf, pregs (ptr));
2339 OUTS (outf, "]");
4b7f6baa
CM		 2340 }
2341 else if (aop == 2 && sz == 0 && Z == 1 && W == 0)
2342 {
4b7f6baa 2343 OUTS (outf, pregs (reg));
086134ec 2344 OUTS (outf, " = [");
4b7f6baa
CM		 2345 OUTS (outf, pregs (ptr));
2346 OUTS (outf, "]");
4b7f6baa
CM		 2347 }
2348 else if (aop == 2 && sz == 1 && Z == 0 && W == 0)
2349 {
4b7f6baa 2350 OUTS (outf, dregs (reg));
086134ec 2351 OUTS (outf, " = W[");
4b7f6baa
CM		 2352 OUTS (outf, pregs (ptr));
2353 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2354 }
2355 else if (aop == 2 && sz == 1 && Z == 1 && W == 0)
2356 {
4b7f6baa 2357 OUTS (outf, dregs (reg));
086134ec 2358 OUTS (outf, " = W[");
4b7f6baa 2359 OUTS (outf, pregs (ptr));
086134ec 2360 OUTS (outf, "] (X)");
4b7f6baa
CM		 2361 }
2362 else if (aop == 2 && sz == 2 && Z == 0 && W == 0)
2363 {
4b7f6baa 2364 OUTS (outf, dregs (reg));
086134ec 2365 OUTS (outf, " = B[");
4b7f6baa
CM		 2366 OUTS (outf, pregs (ptr));
2367 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2368 }
2369 else if (aop == 2 && sz == 2 && Z == 1 && W == 0)
2370 {
4b7f6baa 2371 OUTS (outf, dregs (reg));
086134ec 2372 OUTS (outf, " = B[");
4b7f6baa 2373 OUTS (outf, pregs (ptr));
086134ec 2374 OUTS (outf, "] (X)");
4b7f6baa
CM		 2375 }
2376 else if (aop == 0 && sz == 0 && Z == 0 && W == 1)
2377 {
4b7f6baa
CM		 2378 OUTS (outf, "[");
2379 OUTS (outf, pregs (ptr));
086134ec 2380 OUTS (outf, "++] = ");
4b7f6baa 2381 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2382 }
2383 else if (aop == 0 && sz == 0 && Z == 1 && W == 1)
2384 {
4b7f6baa
CM		 2385 OUTS (outf, "[");
2386 OUTS (outf, pregs (ptr));
086134ec 2387 OUTS (outf, "++] = ");
4b7f6baa 2388 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2389 }
2390 else if (aop == 0 && sz == 1 && Z == 0 && W == 1)
2391 {
4b7f6baa
CM		 2392 OUTS (outf, "W[");
2393 OUTS (outf, pregs (ptr));
086134ec 2394 OUTS (outf, "++] = ");
4b7f6baa 2395 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2396 }
2397 else if (aop == 0 && sz == 2 && Z == 0 && W == 1)
2398 {
4b7f6baa
CM		 2399 OUTS (outf, "B[");
2400 OUTS (outf, pregs (ptr));
086134ec 2401 OUTS (outf, "++] = ");
4b7f6baa 2402 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2403 }
2404 else if (aop == 1 && sz == 0 && Z == 0 && W == 1)
2405 {
4b7f6baa
CM		 2406 OUTS (outf, "[");
2407 OUTS (outf, pregs (ptr));
086134ec 2408 OUTS (outf, "--] = ");
4b7f6baa 2409 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2410 }
2411 else if (aop == 1 && sz == 0 && Z == 1 && W == 1)
2412 {
4b7f6baa
CM		 2413 OUTS (outf, "[");
2414 OUTS (outf, pregs (ptr));
086134ec 2415 OUTS (outf, "--] = ");
4b7f6baa 2416 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2417 }
2418 else if (aop == 1 && sz == 1 && Z == 0 && W == 1)
2419 {
4b7f6baa
CM		 2420 OUTS (outf, "W[");
2421 OUTS (outf, pregs (ptr));
086134ec 2422 OUTS (outf, "--] = ");
4b7f6baa 2423 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2424 }
2425 else if (aop == 1 && sz == 2 && Z == 0 && W == 1)
2426 {
4b7f6baa
CM		 2427 OUTS (outf, "B[");
2428 OUTS (outf, pregs (ptr));
086134ec 2429 OUTS (outf, "--] = ");
4b7f6baa 2430 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2431 }
2432 else if (aop == 2 && sz == 0 && Z == 0 && W == 1)
2433 {
4b7f6baa
CM		 2434 OUTS (outf, "[");
2435 OUTS (outf, pregs (ptr));
086134ec 2436 OUTS (outf, "] = ");
4b7f6baa 2437 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2438 }
2439 else if (aop == 2 && sz == 0 && Z == 1 && W == 1)
2440 {
4b7f6baa
CM		 2441 OUTS (outf, "[");
2442 OUTS (outf, pregs (ptr));
086134ec 2443 OUTS (outf, "] = ");
4b7f6baa 2444 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2445 }
2446 else if (aop == 2 && sz == 1 && Z == 0 && W == 1)
2447 {
4b7f6baa
CM		 2448 OUTS (outf, "W[");
2449 OUTS (outf, pregs (ptr));
086134ec 2450 OUTS (outf, "] = ");
4b7f6baa 2451 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2452 }
2453 else if (aop == 2 && sz == 2 && Z == 0 && W == 1)
2454 {
4b7f6baa
CM		 2455 OUTS (outf, "B[");
2456 OUTS (outf, pregs (ptr));
086134ec 2457 OUTS (outf, "] = ");
4b7f6baa 2458 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2459 }
2460 else
b7d48530
NC		 2461 return 0;
2462
2463 return 2;
4b7f6baa
CM		 2464}
2465
2466static int
2467decode_LDSTiiFP_0 (TIword iw0, disassemble_info *outf)
2468{
b7d48530
NC		 2469 /* LDSTiiFP
2470 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2471 | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
2472 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2473 int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask);
2474 int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask);
2475 int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask);
2476
2477 if (W == 0)
2478 {
4b7f6baa 2479 OUTS (outf, dpregs (reg));
086134ec 2480 OUTS (outf, " = [FP ");
4b7f6baa
CM		 2481 OUTS (outf, negimm5s4 (offset));
2482 OUTS (outf, "]");
4b7f6baa
CM		 2483 }
2484 else if (W == 1)
2485 {
086134ec 2486 OUTS (outf, "[FP ");
4b7f6baa 2487 OUTS (outf, negimm5s4 (offset));
086134ec 2488 OUTS (outf, "] = ");
4b7f6baa 2489 OUTS (outf, dpregs (reg));
4b7f6baa
CM		 2490 }
2491 else
b7d48530
NC		 2492 return 0;
2493
2494 return 2;
4b7f6baa
CM		 2495}
2496
2497static int
2498decode_LDSTii_0 (TIword iw0, disassemble_info *outf)
2499{
b7d48530
NC		 2500 /* LDSTii
2501 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2502 | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
2503 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2504 int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask);
2505 int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
2506 int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask);
2507 int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask);
2508 int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask);
2509
2510 if (W == 0 && op == 0)
2511 {
4b7f6baa 2512 OUTS (outf, dregs (reg));
086134ec 2513 OUTS (outf, " = [");
4b7f6baa 2514 OUTS (outf, pregs (ptr));
086134ec 2515 OUTS (outf, " + ");
4b7f6baa
CM		 2516 OUTS (outf, uimm4s4 (offset));
2517 OUTS (outf, "]");
4b7f6baa
CM		 2518 }
2519 else if (W == 0 && op == 1)
2520 {
4b7f6baa 2521 OUTS (outf, dregs (reg));
086134ec 2522 OUTS (outf, " = W[");
4b7f6baa 2523 OUTS (outf, pregs (ptr));
086134ec 2524 OUTS (outf, " + ");
4b7f6baa
CM		 2525 OUTS (outf, uimm4s2 (offset));
2526 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2527 }
2528 else if (W == 0 && op == 2)
2529 {
4b7f6baa 2530 OUTS (outf, dregs (reg));
086134ec 2531 OUTS (outf, " = W[");
4b7f6baa 2532 OUTS (outf, pregs (ptr));
086134ec 2533 OUTS (outf, " + ");
4b7f6baa 2534 OUTS (outf, uimm4s2 (offset));
086134ec 2535 OUTS (outf, "] (X)");
4b7f6baa
CM		 2536 }
2537 else if (W == 0 && op == 3)
2538 {
4b7f6baa 2539 OUTS (outf, pregs (reg));
086134ec 2540 OUTS (outf, " = [");
4b7f6baa 2541 OUTS (outf, pregs (ptr));
086134ec 2542 OUTS (outf, " + ");
4b7f6baa
CM		 2543 OUTS (outf, uimm4s4 (offset));
2544 OUTS (outf, "]");
4b7f6baa
CM		 2545 }
2546 else if (W == 1 && op == 0)
2547 {
4b7f6baa
CM		 2548 OUTS (outf, "[");
2549 OUTS (outf, pregs (ptr));
086134ec 2550 OUTS (outf, " + ");
4b7f6baa 2551 OUTS (outf, uimm4s4 (offset));
086134ec 2552 OUTS (outf, "] = ");
4b7f6baa 2553 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2554 }
2555 else if (W == 1 && op == 1)
2556 {
086134ec 2557 OUTS (outf, "W[");
4b7f6baa 2558 OUTS (outf, pregs (ptr));
086134ec 2559 OUTS (outf, " + ");
4b7f6baa 2560 OUTS (outf, uimm4s2 (offset));
086134ec 2561 OUTS (outf, "] = ");
4b7f6baa 2562 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2563 }
2564 else if (W == 1 && op == 3)
2565 {
4b7f6baa
CM		 2566 OUTS (outf, "[");
2567 OUTS (outf, pregs (ptr));
086134ec 2568 OUTS (outf, " + ");
4b7f6baa 2569 OUTS (outf, uimm4s4 (offset));
086134ec 2570 OUTS (outf, "] = ");
4b7f6baa 2571 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2572 }
2573 else
b7d48530
NC		 2574 return 0;
2575
2576 return 2;
4b7f6baa
CM		 2577}
2578
2579static int
2580decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2581{
b7d48530
NC		 2582 /* LoopSetup
2583 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2584 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
2585 |.reg...........| - | - |.eoffset...............................|
2586 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2587 int c = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask);
2588 int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
2589 int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask);
2590 int soffset = ((iw0 >> (LoopSetup_soffset_bits - 16)) & LoopSetup_soffset_mask);
2591 int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask);
2592
219b747a
MF		 2593 if (parallel)
2594 return 0;
2595
298c1ec2
MF		 2596 if (reg > 7)
2597 return 0;
2598
4b7f6baa
CM		 2599 if (rop == 0)
2600 {
4b7f6baa 2601 OUTS (outf, "LSETUP");
086134ec 2602 OUTS (outf, "(0x");
4b7f6baa 2603 OUTS (outf, pcrel4 (soffset));
086134ec 2604 OUTS (outf, ", 0x");
4b7f6baa 2605 OUTS (outf, lppcrel10 (eoffset));
086134ec 2606 OUTS (outf, ") ");
4b7f6baa 2607 OUTS (outf, counters (c));
4b7f6baa
CM		 2608 }
2609 else if (rop == 1)
2610 {
4b7f6baa 2611 OUTS (outf, "LSETUP");
086134ec 2612 OUTS (outf, "(0x");
4b7f6baa 2613 OUTS (outf, pcrel4 (soffset));
086134ec 2614 OUTS (outf, ", 0x");
4b7f6baa 2615 OUTS (outf, lppcrel10 (eoffset));
086134ec 2616 OUTS (outf, ") ");
4b7f6baa 2617 OUTS (outf, counters (c));
086134ec 2618 OUTS (outf, " = ");
4b7f6baa 2619 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2620 }
2621 else if (rop == 3)
2622 {
4b7f6baa 2623 OUTS (outf, "LSETUP");
086134ec 2624 OUTS (outf, "(0x");
4b7f6baa 2625 OUTS (outf, pcrel4 (soffset));
086134ec 2626 OUTS (outf, ", 0x");
4b7f6baa 2627 OUTS (outf, lppcrel10 (eoffset));
086134ec 2628 OUTS (outf, ") ");
4b7f6baa 2629 OUTS (outf, counters (c));
086134ec 2630 OUTS (outf, " = ");
4b7f6baa 2631 OUTS (outf, pregs (reg));
086134ec 2632 OUTS (outf, " >> 0x1");
4b7f6baa
CM		 2633 }
2634 else
b7d48530
NC		 2635 return 0;
2636
2637 return 4;
4b7f6baa
CM		 2638}
2639
2640static int
2641decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2642{
b7d48530
NC		 2643 /* LDIMMhalf
2644 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2645 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
2646 |.hword.........................................................|
2647 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2648 int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask);
2649 int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask);
2650 int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask);
2651 int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask);
2652 int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask);
2653 int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask);
2654
b21c9cb4
BS		 2655 bu32 *pval = get_allreg (grp, reg);
2656
219b747a
MF		 2657 if (parallel)
2658 return 0;
2659
b21c9cb4
BS		 2660 /* Since we don't have 32-bit immediate loads, we allow the disassembler
2661 to combine them, so it prints out the right values.
2662 Here we keep track of the registers. */
2663 if (H == 0 && S == 1 && Z == 0)
2664 {
2665 /* regs = imm16 (x) */
2666 *pval = imm16_val (hword);
086134ec
BS		 2667 if (hword & 0x8000)
2668 *pval |= 0xFFFF0000;
2669 else
2670 *pval &= 0xFFFF;
b21c9cb4
BS		 2671 }
2672 else if (H == 0 && S == 0 && Z == 1)
2673 {
2674 /* regs = luimm16 (Z) */
2675 *pval = luimm16_val (hword);
086134ec 2676 *pval &= 0xFFFF;
b21c9cb4
BS		 2677 }
2678 else if (H == 0 && S == 0 && Z == 0)
2679 {
2680 /* regs_lo = luimm16 */
2681 *pval &= 0xFFFF0000;
2682 *pval |= luimm16_val (hword);
2683 }
2684 else if (H == 1 && S == 0 && Z == 0)
2685 {
2686 /* regs_hi = huimm16 */
2687 *pval &= 0xFFFF;
2688 *pval |= luimm16_val (hword) << 16;
2689 }
2690
2691 /* Here we do the disassembly */
4b7f6baa
CM		 2692 if (grp == 0 && H == 0 && S == 0 && Z == 0)
2693 {
4b7f6baa 2694 OUTS (outf, dregs_lo (reg));
086134ec
BS		 2695 OUTS (outf, " = ");
2696 OUTS (outf, uimm16 (hword));
4b7f6baa
CM		 2697 }
2698 else if (grp == 0 && H == 1 && S == 0 && Z == 0)
2699 {
4b7f6baa 2700 OUTS (outf, dregs_hi (reg));
086134ec
BS		 2701 OUTS (outf, " = ");
2702 OUTS (outf, uimm16 (hword));
4b7f6baa
CM		 2703 }
2704 else if (grp == 0 && H == 0 && S == 1 && Z == 0)
2705 {
4b7f6baa 2706 OUTS (outf, dregs (reg));
086134ec 2707 OUTS (outf, " = ");
4b7f6baa
CM		 2708 OUTS (outf, imm16 (hword));
2709 OUTS (outf, " (X)");
4b7f6baa
CM		 2710 }
2711 else if (H == 0 && S == 1 && Z == 0)
602427c4 2712 {
4b7f6baa 2713 OUTS (outf, regs (reg, grp));
086134ec 2714 OUTS (outf, " = ");
4b7f6baa
CM		 2715 OUTS (outf, imm16 (hword));
2716 OUTS (outf, " (X)");
4b7f6baa
CM		 2717 }
2718 else if (H == 0 && S == 0 && Z == 1)
2719 {
4b7f6baa 2720 OUTS (outf, regs (reg, grp));
086134ec
BS		 2721 OUTS (outf, " = ");
2722 OUTS (outf, uimm16 (hword));
2723 OUTS (outf, " (Z)");
4b7f6baa
CM		 2724 }
2725 else if (H == 0 && S == 0 && Z == 0)
2726 {
4b7f6baa 2727 OUTS (outf, regs_lo (reg, grp));
086134ec 2728 OUTS (outf, " = ");
b21c9cb4 2729 OUTS (outf, uimm16 (hword));
4b7f6baa
CM		 2730 }
2731 else if (H == 1 && S == 0 && Z == 0)
2732 {
4b7f6baa 2733 OUTS (outf, regs_hi (reg, grp));
086134ec 2734 OUTS (outf, " = ");
b21c9cb4 2735 OUTS (outf, uimm16 (hword));
4b7f6baa
CM		 2736 }
2737 else
b7d48530
NC		 2738 return 0;
2739
b21c9cb4 2740 /* And we print out the 32-bit value if it is a pointer. */
086134ec 2741 if (S == 0 && Z == 0)
b21c9cb4 2742 {
086134ec
BS		 2743 OUTS (outf, ";\t\t/* (");
2744 OUTS (outf, imm16d (hword));
2745 OUTS (outf, ")\t");
2746
b21c9cb4 2747 /* If it is an MMR, don't print the symbol. */
086134ec
BS		 2748 if (*pval < 0xFFC00000 && grp == 1)
2749 {
2750 OUTS (outf, regs (reg, grp));
2751 OUTS (outf, "=0x");
2752 OUTS (outf, huimm32e (*pval));
2753 }
b21c9cb4 2754 else
086134ec
BS		 2755 {
2756 OUTS (outf, regs (reg, grp));
2757 OUTS (outf, "=0x");
2758 OUTS (outf, huimm32e (*pval));
2759 OUTS (outf, "(");
2760 OUTS (outf, imm32 (*pval));
2761 OUTS (outf, ")");
2762 }
b21c9cb4
BS		 2763
2764 OUTS (outf, " */");
086134ec
BS		 2765 comment = 1;
2766 }
2767 if (S == 1 || Z == 1)
2768 {
602427c4
MF		 2769 OUTS (outf, ";\t\t/*\t\t");
2770 OUTS (outf, regs (reg, grp));
2771 OUTS (outf, "=0x");
2772 OUTS (outf, huimm32e (*pval));
2773 OUTS (outf, "(");
2774 OUTS (outf, imm32 (*pval));
2775 OUTS (outf, ") */");
2776 comment = 1;
b21c9cb4 2777 }
b7d48530 2778 return 4;
4b7f6baa
CM		 2779}
2780
2781static int
2782decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2783{
b7d48530
NC		 2784 /* CALLa
2785 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2786 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
2787 |.lsw...........................................................|
2788 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2789 int S = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask);
2790 int lsw = ((iw1 >> 0) & 0xffff);
2791 int msw = ((iw0 >> 0) & 0xff);
2792
219b747a
MF		 2793 if (parallel)
2794 return 0;
2795
4b7f6baa 2796 if (S == 1)
086134ec 2797 OUTS (outf, "CALL 0x");
4b7f6baa 2798 else if (S == 0)
086134ec 2799 OUTS (outf, "JUMP.L 0x");
4b7f6baa 2800 else
b7d48530
NC		 2801 return 0;
2802
2803 OUTS (outf, pcrel24 (((msw) << 16) | (lsw)));
2804 return 4;
4b7f6baa
CM		 2805}
2806
2807static int
2808decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2809{
b7d48530
NC		 2810 /* LDSTidxI
2811 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2812 | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
2813 |.offset........................................................|
2814 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2815 int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask);
2816 int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask);
2817 int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask);
2818 int reg = ((iw0 >> (LDSTidxI_reg_bits - 16)) & LDSTidxI_reg_mask);
2819 int ptr = ((iw0 >> (LDSTidxI_ptr_bits - 16)) & LDSTidxI_ptr_mask);
2820 int offset = ((iw1 >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
2821
2822 if (W == 0 && sz == 0 && Z == 0)
2823 {
4b7f6baa 2824 OUTS (outf, dregs (reg));
086134ec 2825 OUTS (outf, " = [");
4b7f6baa 2826 OUTS (outf, pregs (ptr));
086134ec 2827 OUTS (outf, " + ");
4b7f6baa
CM		 2828 OUTS (outf, imm16s4 (offset));
2829 OUTS (outf, "]");
4b7f6baa
CM		 2830 }
2831 else if (W == 0 && sz == 0 && Z == 1)
2832 {
4b7f6baa 2833 OUTS (outf, pregs (reg));
086134ec 2834 OUTS (outf, " = [");
4b7f6baa 2835 OUTS (outf, pregs (ptr));
086134ec 2836 OUTS (outf, " + ");
4b7f6baa
CM		 2837 OUTS (outf, imm16s4 (offset));
2838 OUTS (outf, "]");
4b7f6baa
CM		 2839 }
2840 else if (W == 0 && sz == 1 && Z == 0)
2841 {
4b7f6baa 2842 OUTS (outf, dregs (reg));
086134ec 2843 OUTS (outf, " = W[");
4b7f6baa 2844 OUTS (outf, pregs (ptr));
086134ec 2845 OUTS (outf, " + ");
4b7f6baa
CM		 2846 OUTS (outf, imm16s2 (offset));
2847 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2848 }
2849 else if (W == 0 && sz == 1 && Z == 1)
2850 {
4b7f6baa 2851 OUTS (outf, dregs (reg));
086134ec 2852 OUTS (outf, " = W[");
4b7f6baa 2853 OUTS (outf, pregs (ptr));
086134ec 2854 OUTS (outf, " + ");
4b7f6baa 2855 OUTS (outf, imm16s2 (offset));
086134ec 2856 OUTS (outf, "] (X)");
4b7f6baa
CM		 2857 }
2858 else if (W == 0 && sz == 2 && Z == 0)
2859 {
4b7f6baa 2860 OUTS (outf, dregs (reg));
086134ec 2861 OUTS (outf, " = B[");
4b7f6baa 2862 OUTS (outf, pregs (ptr));
086134ec 2863 OUTS (outf, " + ");
4b7f6baa
CM		 2864 OUTS (outf, imm16 (offset));
2865 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2866 }
2867 else if (W == 0 && sz == 2 && Z == 1)
2868 {
4b7f6baa 2869 OUTS (outf, dregs (reg));
086134ec 2870 OUTS (outf, " = B[");
4b7f6baa 2871 OUTS (outf, pregs (ptr));
086134ec 2872 OUTS (outf, " + ");
4b7f6baa 2873 OUTS (outf, imm16 (offset));
086134ec 2874 OUTS (outf, "] (X)");
4b7f6baa
CM		 2875 }
2876 else if (W == 1 && sz == 0 && Z == 0)
2877 {
4b7f6baa
CM		 2878 OUTS (outf, "[");
2879 OUTS (outf, pregs (ptr));
086134ec 2880 OUTS (outf, " + ");
4b7f6baa 2881 OUTS (outf, imm16s4 (offset));
086134ec 2882 OUTS (outf, "] = ");
4b7f6baa 2883 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2884 }
2885 else if (W == 1 && sz == 0 && Z == 1)
2886 {
4b7f6baa
CM		 2887 OUTS (outf, "[");
2888 OUTS (outf, pregs (ptr));
086134ec 2889 OUTS (outf, " + ");
4b7f6baa 2890 OUTS (outf, imm16s4 (offset));
086134ec 2891 OUTS (outf, "] = ");
4b7f6baa 2892 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2893 }
2894 else if (W == 1 && sz == 1 && Z == 0)
2895 {
4b7f6baa
CM		 2896 OUTS (outf, "W[");
2897 OUTS (outf, pregs (ptr));
086134ec 2898 OUTS (outf, " + ");
4b7f6baa 2899 OUTS (outf, imm16s2 (offset));
086134ec 2900 OUTS (outf, "] = ");
4b7f6baa 2901 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2902 }
2903 else if (W == 1 && sz == 2 && Z == 0)
2904 {
4b7f6baa
CM		 2905 OUTS (outf, "B[");
2906 OUTS (outf, pregs (ptr));
086134ec 2907 OUTS (outf, " + ");
4b7f6baa 2908 OUTS (outf, imm16 (offset));
086134ec 2909 OUTS (outf, "] = ");
4b7f6baa 2910 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2911 }
2912 else
b7d48530
NC		 2913 return 0;
2914
2915 return 4;
4b7f6baa
CM		 2916}
2917
2918static int
2919decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2920{
b7d48530
NC		 2921 /* linkage
2922 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2923 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
2924 |.framesize.....................................................|
2925 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2926 int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask);
2927 int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask);
2928
219b747a
MF		 2929 if (parallel)
2930 return 0;
2931
4b7f6baa
CM		 2932 if (R == 0)
2933 {
4b7f6baa
CM		 2934 OUTS (outf, "LINK ");
2935 OUTS (outf, uimm16s4 (framesize));
086134ec
BS		 2936 OUTS (outf, ";\t\t/* (");
2937 OUTS (outf, uimm16s4d (framesize));
2938 OUTS (outf, ") */");
2939 comment = 1;
4b7f6baa
CM		 2940 }
2941 else if (R == 1)
b7d48530 2942 OUTS (outf, "UNLINK");
4b7f6baa 2943 else
b7d48530
NC		 2944 return 0;
2945
2946 return 4;
4b7f6baa
CM		 2947}
2948
2949static int
2950decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2951{
b7d48530
NC		 2952 /* dsp32mac
2953 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2954 | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
2955 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2956 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2957 int op1 = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask);
2958 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2959 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2960 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
4b7f6baa 2961 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
b7d48530 2962 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
4b7f6baa
CM		 2963 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
2964 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
b7d48530
NC		 2965 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2966 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
2967 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
2968 int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask);
2969 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
2970 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
4b7f6baa
CM		 2971
2972 if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3)
2973 return 0;
2974
2975 if (op1 == 3 && MM)
2976 return 0;
2977
2978 if ((w1 || w0) && mmod == M_W32)
2979 return 0;
2980
ee171c8f 2981 if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0)
4b7f6baa
CM		 2982 return 0;
2983
2984 if (w1 == 1 || op1 != 3)
2985 {
2986 if (w1)
2987 OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
2988
2989 if (op1 == 3)
2990 OUTS (outf, " = A1");
2991 else
2992 {
2993 if (w1)
2994 OUTS (outf, " = (");
2995 decode_macfunc (1, op1, h01, h11, src0, src1, outf);
2996 if (w1)
2997 OUTS (outf, ")");
2998 }
2999
3000 if (w0 == 1 || op0 != 3)
3001 {
3002 if (MM)
3003 OUTS (outf, " (M)");
4b7f6baa
CM		 3004 OUTS (outf, ", ");
3005 }
3006 }
3007
3008 if (w0 == 1 || op0 != 3)
3009 {
67171547
MF		 3010 /* Clear MM option since it only matters for MAC1, and if we made
3011 it this far, we've already shown it or we want to ignore it. */
3012 MM = 0;
3013
4b7f6baa
CM		 3014 if (w0)
3015 OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
3016
3017 if (op0 == 3)
3018 OUTS (outf, " = A0");
3019 else
3020 {
3021 if (w0)
3022 OUTS (outf, " = (");
3023 decode_macfunc (0, op0, h00, h10, src0, src1, outf);
3024 if (w0)
3025 OUTS (outf, ")");
3026 }
3027 }
3028
3029 decode_optmode (mmod, MM, outf);
3030
3031 return 4;
3032}
3033
3034static int
3035decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3036{
b7d48530
NC		 3037 /* dsp32mult
3038 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3039 | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
3040 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
3041 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3042 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
3043 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
3044 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
4b7f6baa 3045 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
b7d48530 3046 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
4b7f6baa
CM		 3047 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
3048 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
b7d48530
NC		 3049 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
3050 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
3051 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
3052 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
3053 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
4b7f6baa
CM		 3054
3055 if (w1 == 0 && w0 == 0)
3056 return 0;
b7d48530 3057
4b7f6baa
CM		 3058 if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0)
3059 return 0;
b7d48530 3060
4b7f6baa
CM		 3061 if (w1)
3062 {
4db66394 3063 OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
4b7f6baa
CM		 3064 OUTS (outf, " = ");
3065 decode_multfunc (h01, h11, src0, src1, outf);
3066
3067 if (w0)
3068 {
3069 if (MM)
3070 OUTS (outf, " (M)");
3071 MM = 0;
3072 OUTS (outf, ", ");
3073 }
3074 }
3075
3076 if (w0)
3077 {
4db66394 3078 OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
4b7f6baa
CM		 3079 OUTS (outf, " = ");
3080 decode_multfunc (h00, h10, src0, src1, outf);
3081 }
3082
3083 decode_optmode (mmod, MM, outf);
3084 return 4;
3085}
3086
3087static int
3088decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3089{
b7d48530
NC		 3090 /* dsp32alu
3091 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3092 | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
3093 |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
3094 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 3095 int s = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask);
3096 int x = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask);
3097 int aop = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask);
3098 int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask);
3099 int src1 = ((iw1 >> DSP32Alu_src1_bits) & DSP32Alu_src1_mask);
3100 int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask);
3101 int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask);
3102 int HL = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask);
3103 int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask);
3104
3105 if (aop == 0 && aopcde == 9 && HL == 0 && s == 0)
3106 {
086134ec 3107 OUTS (outf, "A0.L = ");
4b7f6baa 3108 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3109 }
3110 else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0)
3111 {
086134ec 3112 OUTS (outf, "A1.H = ");
4b7f6baa 3113 OUTS (outf, dregs_hi (src0));
4b7f6baa
CM		 3114 }
3115 else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0)
3116 {
086134ec 3117 OUTS (outf, "A1.L = ");
4b7f6baa 3118 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3119 }
3120 else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0)
3121 {
086134ec 3122 OUTS (outf, "A0.H = ");
4b7f6baa 3123 OUTS (outf, dregs_hi (src0));
4b7f6baa
CM		 3124 }
3125 else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5)
3126 {
4b7f6baa 3127 OUTS (outf, dregs_hi (dst0));
086134ec 3128 OUTS (outf, " = ");
4b7f6baa 3129 OUTS (outf, dregs (src0));
086134ec 3130 OUTS (outf, " - ");
4b7f6baa 3131 OUTS (outf, dregs (src1));
086134ec 3132 OUTS (outf, " (RND20)");
4b7f6baa
CM		 3133 }
3134 else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5)
3135 {
4b7f6baa 3136 OUTS (outf, dregs_hi (dst0));
086134ec 3137 OUTS (outf, " = ");
4b7f6baa 3138 OUTS (outf, dregs (src0));
086134ec 3139 OUTS (outf, " + ");
4b7f6baa 3140 OUTS (outf, dregs (src1));
086134ec 3141 OUTS (outf, " (RND20)");
4b7f6baa
CM		 3142 }
3143 else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5)
3144 {
4b7f6baa 3145 OUTS (outf, dregs_lo (dst0));
086134ec 3146 OUTS (outf, " = ");
4b7f6baa 3147 OUTS (outf, dregs (src0));
086134ec 3148 OUTS (outf, " - ");
4b7f6baa 3149 OUTS (outf, dregs (src1));
086134ec 3150 OUTS (outf, " (RND12)");
4b7f6baa
CM		 3151 }
3152 else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5)
3153 {
4b7f6baa 3154 OUTS (outf, dregs_lo (dst0));
086134ec 3155 OUTS (outf, " = ");
4b7f6baa 3156 OUTS (outf, dregs (src0));
086134ec 3157 OUTS (outf, " + ");
4b7f6baa 3158 OUTS (outf, dregs (src1));
086134ec 3159 OUTS (outf, " (RND12)");
4b7f6baa
CM		 3160 }
3161 else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5)
3162 {
4b7f6baa 3163 OUTS (outf, dregs_lo (dst0));
086134ec 3164 OUTS (outf, " = ");
4b7f6baa 3165 OUTS (outf, dregs (src0));
086134ec 3166 OUTS (outf, " - ");
4b7f6baa 3167 OUTS (outf, dregs (src1));
086134ec 3168 OUTS (outf, " (RND20)");
4b7f6baa
CM		 3169 }
3170 else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5)
3171 {
4b7f6baa 3172 OUTS (outf, dregs_hi (dst0));
086134ec 3173 OUTS (outf, " = ");
4b7f6baa 3174 OUTS (outf, dregs (src0));
086134ec 3175 OUTS (outf, " + ");
4b7f6baa 3176 OUTS (outf, dregs (src1));
086134ec 3177 OUTS (outf, " (RND12)");
4b7f6baa
CM		 3178 }
3179 else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5)
3180 {
4b7f6baa 3181 OUTS (outf, dregs_lo (dst0));
086134ec 3182 OUTS (outf, " = ");
4b7f6baa 3183 OUTS (outf, dregs (src0));
086134ec 3184 OUTS (outf, " + ");
4b7f6baa 3185 OUTS (outf, dregs (src1));
086134ec 3186 OUTS (outf, " (RND20)");
4b7f6baa
CM		 3187 }
3188 else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5)
3189 {
4b7f6baa 3190 OUTS (outf, dregs_hi (dst0));
086134ec 3191 OUTS (outf, " = ");
4b7f6baa 3192 OUTS (outf, dregs (src0));
086134ec 3193 OUTS (outf, " - ");
4b7f6baa 3194 OUTS (outf, dregs (src1));
086134ec 3195 OUTS (outf, " (RND12)");
4b7f6baa
CM		 3196 }
3197 else if (HL == 1 && aop == 0 && aopcde == 2)
3198 {
4b7f6baa 3199 OUTS (outf, dregs_hi (dst0));
086134ec 3200 OUTS (outf, " = ");
4b7f6baa 3201 OUTS (outf, dregs_lo (src0));
086134ec 3202 OUTS (outf, " + ");
4b7f6baa 3203 OUTS (outf, dregs_lo (src1));
4b7f6baa 3204 amod1 (s, x, outf);
4b7f6baa
CM		 3205 }
3206 else if (HL == 1 && aop == 1 && aopcde == 2)
3207 {
4b7f6baa 3208 OUTS (outf, dregs_hi (dst0));
086134ec 3209 OUTS (outf, " = ");
4b7f6baa 3210 OUTS (outf, dregs_lo (src0));
086134ec 3211 OUTS (outf, " + ");
4b7f6baa 3212 OUTS (outf, dregs_hi (src1));
4b7f6baa 3213 amod1 (s, x, outf);
4b7f6baa
CM		 3214 }
3215 else if (HL == 1 && aop == 2 && aopcde == 2)
3216 {
4b7f6baa 3217 OUTS (outf, dregs_hi (dst0));
086134ec 3218 OUTS (outf, " = ");
4b7f6baa 3219 OUTS (outf, dregs_hi (src0));
086134ec 3220 OUTS (outf, " + ");
4b7f6baa 3221 OUTS (outf, dregs_lo (src1));
4b7f6baa 3222 amod1 (s, x, outf);
4b7f6baa
CM		 3223 }
3224 else if (HL == 1 && aop == 3 && aopcde == 2)
3225 {
4b7f6baa 3226 OUTS (outf, dregs_hi (dst0));
086134ec 3227 OUTS (outf, " = ");
4b7f6baa 3228 OUTS (outf, dregs_hi (src0));
086134ec 3229 OUTS (outf, " + ");
4b7f6baa 3230 OUTS (outf, dregs_hi (src1));
4b7f6baa 3231 amod1 (s, x, outf);
4b7f6baa
CM		 3232 }
3233 else if (HL == 0 && aop == 0 && aopcde == 3)
3234 {
4b7f6baa 3235 OUTS (outf, dregs_lo (dst0));
086134ec 3236 OUTS (outf, " = ");
4b7f6baa 3237 OUTS (outf, dregs_lo (src0));
086134ec 3238 OUTS (outf, " - ");
4b7f6baa 3239 OUTS (outf, dregs_lo (src1));
4b7f6baa 3240 amod1 (s, x, outf);
4b7f6baa
CM		 3241 }
3242 else if (HL == 0 && aop == 1 && aopcde == 3)
3243 {
4b7f6baa 3244 OUTS (outf, dregs_lo (dst0));
086134ec 3245 OUTS (outf, " = ");
4b7f6baa 3246 OUTS (outf, dregs_lo (src0));
086134ec 3247 OUTS (outf, " - ");
4b7f6baa 3248 OUTS (outf, dregs_hi (src1));
4b7f6baa 3249 amod1 (s, x, outf);
4b7f6baa
CM		 3250 }
3251 else if (HL == 0 && aop == 3 && aopcde == 2)
3252 {
4b7f6baa 3253 OUTS (outf, dregs_lo (dst0));
086134ec 3254 OUTS (outf, " = ");
4b7f6baa 3255 OUTS (outf, dregs_hi (src0));
086134ec 3256 OUTS (outf, " + ");
4b7f6baa 3257 OUTS (outf, dregs_hi (src1));
4b7f6baa 3258 amod1 (s, x, outf);
4b7f6baa
CM		 3259 }
3260 else if (HL == 1 && aop == 0 && aopcde == 3)
3261 {
4b7f6baa 3262 OUTS (outf, dregs_hi (dst0));
086134ec 3263 OUTS (outf, " = ");
4b7f6baa 3264 OUTS (outf, dregs_lo (src0));
086134ec 3265 OUTS (outf, " - ");
4b7f6baa 3266 OUTS (outf, dregs_lo (src1));
4b7f6baa 3267 amod1 (s, x, outf);
4b7f6baa
CM		 3268 }
3269 else if (HL == 1 && aop == 1 && aopcde == 3)
3270 {
4b7f6baa 3271 OUTS (outf, dregs_hi (dst0));
086134ec 3272 OUTS (outf, " = ");
4b7f6baa 3273 OUTS (outf, dregs_lo (src0));
086134ec 3274 OUTS (outf, " - ");
4b7f6baa 3275 OUTS (outf, dregs_hi (src1));
4b7f6baa 3276 amod1 (s, x, outf);
4b7f6baa
CM		 3277 }
3278 else if (HL == 1 && aop == 2 && aopcde == 3)
3279 {
4b7f6baa 3280 OUTS (outf, dregs_hi (dst0));
086134ec 3281 OUTS (outf, " = ");
4b7f6baa 3282 OUTS (outf, dregs_hi (src0));
086134ec 3283 OUTS (outf, " - ");
4b7f6baa 3284 OUTS (outf, dregs_lo (src1));
4b7f6baa 3285 amod1 (s, x, outf);
4b7f6baa
CM		 3286 }
3287 else if (HL == 1 && aop == 3 && aopcde == 3)
3288 {
4b7f6baa 3289 OUTS (outf, dregs_hi (dst0));
086134ec 3290 OUTS (outf, " = ");
4b7f6baa 3291 OUTS (outf, dregs_hi (src0));
086134ec 3292 OUTS (outf, " - ");
4b7f6baa 3293 OUTS (outf, dregs_hi (src1));
4b7f6baa 3294 amod1 (s, x, outf);
4b7f6baa
CM		 3295 }
3296 else if (HL == 0 && aop == 2 && aopcde == 2)
3297 {
4b7f6baa 3298 OUTS (outf, dregs_lo (dst0));
086134ec 3299 OUTS (outf, " = ");
4b7f6baa 3300 OUTS (outf, dregs_hi (src0));
086134ec 3301 OUTS (outf, " + ");
4b7f6baa 3302 OUTS (outf, dregs_lo (src1));
4b7f6baa 3303 amod1 (s, x, outf);
4b7f6baa
CM		 3304 }
3305 else if (HL == 0 && aop == 1 && aopcde == 2)
3306 {
4b7f6baa 3307 OUTS (outf, dregs_lo (dst0));
086134ec 3308 OUTS (outf, " = ");
4b7f6baa 3309 OUTS (outf, dregs_lo (src0));
086134ec 3310 OUTS (outf, " + ");
4b7f6baa 3311 OUTS (outf, dregs_hi (src1));
4b7f6baa 3312 amod1 (s, x, outf);
4b7f6baa
CM		 3313 }
3314 else if (HL == 0 && aop == 2 && aopcde == 3)
3315 {
4b7f6baa 3316 OUTS (outf, dregs_lo (dst0));
086134ec 3317 OUTS (outf, " = ");
4b7f6baa 3318 OUTS (outf, dregs_hi (src0));
086134ec 3319 OUTS (outf, " - ");
4b7f6baa 3320 OUTS (outf, dregs_lo (src1));
4b7f6baa 3321 amod1 (s, x, outf);
4b7f6baa
CM		 3322 }
3323 else if (HL == 0 && aop == 3 && aopcde == 3)
3324 {
4b7f6baa 3325 OUTS (outf, dregs_lo (dst0));
086134ec 3326 OUTS (outf, " = ");
4b7f6baa 3327 OUTS (outf, dregs_hi (src0));
086134ec 3328 OUTS (outf, " - ");
4b7f6baa 3329 OUTS (outf, dregs_hi (src1));
4b7f6baa 3330 amod1 (s, x, outf);
4b7f6baa
CM		 3331 }
3332 else if (HL == 0 && aop == 0 && aopcde == 2)
3333 {
4b7f6baa 3334 OUTS (outf, dregs_lo (dst0));
086134ec 3335 OUTS (outf, " = ");
4b7f6baa 3336 OUTS (outf, dregs_lo (src0));
086134ec 3337 OUTS (outf, " + ");
4b7f6baa 3338 OUTS (outf, dregs_lo (src1));
4b7f6baa 3339 amod1 (s, x, outf);
4b7f6baa
CM		 3340 }
3341 else if (aop == 0 && aopcde == 9 && s == 1)
3342 {
086134ec 3343 OUTS (outf, "A0 = ");
4b7f6baa 3344 OUTS (outf, dregs (src0));
4b7f6baa
CM		 3345 }
3346 else if (aop == 3 && aopcde == 11 && s == 0)
086134ec 3347 OUTS (outf, "A0 -= A1");
b7d48530 3348
4b7f6baa 3349 else if (aop == 3 && aopcde == 11 && s == 1)
086134ec 3350 OUTS (outf, "A0 -= A1 (W32)");
b7d48530 3351
4b7f6baa
CM		 3352 else if (aop == 1 && aopcde == 22 && HL == 1)
3353 {
4b7f6baa 3354 OUTS (outf, dregs (dst0));
086134ec 3355 OUTS (outf, " = BYTEOP2P (");
4b7f6baa
CM		 3356 OUTS (outf, dregs (src0 + 1));
3357 OUTS (outf, ":");
086134ec
BS		 3358 OUTS (outf, imm5d (src0));
3359 OUTS (outf, ", ");
4b7f6baa
CM		 3360 OUTS (outf, dregs (src1 + 1));
3361 OUTS (outf, ":");
086134ec
BS		 3362 OUTS (outf, imm5d (src1));
3363 OUTS (outf, ") (TH");
4b7f6baa
CM		 3364 if (s == 1)
3365 OUTS (outf, ", R)");
3366 else
3367 OUTS (outf, ")");
4b7f6baa
CM		 3368 }
3369 else if (aop == 1 && aopcde == 22 && HL == 0)
3370 {
4b7f6baa 3371 OUTS (outf, dregs (dst0));
086134ec 3372 OUTS (outf, " = BYTEOP2P (");
4b7f6baa
CM		 3373 OUTS (outf, dregs (src0 + 1));
3374 OUTS (outf, ":");
086134ec
BS		 3375 OUTS (outf, imm5d (src0));
3376 OUTS (outf, ", ");
4b7f6baa
CM		 3377 OUTS (outf, dregs (src1 + 1));
3378 OUTS (outf, ":");
086134ec
BS		 3379 OUTS (outf, imm5d (src1));
3380 OUTS (outf, ") (TL");
4b7f6baa
CM		 3381 if (s == 1)
3382 OUTS (outf, ", R)");
3383 else
3384 OUTS (outf, ")");
4b7f6baa
CM		 3385 }
3386 else if (aop == 0 && aopcde == 22 && HL == 1)
3387 {
4b7f6baa 3388 OUTS (outf, dregs (dst0));
086134ec 3389 OUTS (outf, " = BYTEOP2P (");
4b7f6baa
CM		 3390 OUTS (outf, dregs (src0 + 1));
3391 OUTS (outf, ":");
086134ec
BS		 3392 OUTS (outf, imm5d (src0));
3393 OUTS (outf, ", ");
4b7f6baa
CM		 3394 OUTS (outf, dregs (src1 + 1));
3395 OUTS (outf, ":");
086134ec
BS		 3396 OUTS (outf, imm5d (src1));
3397 OUTS (outf, ") (RNDH");
4b7f6baa
CM		 3398 if (s == 1)
3399 OUTS (outf, ", R)");
3400 else
3401 OUTS (outf, ")");
4b7f6baa
CM		 3402 }
3403 else if (aop == 0 && aopcde == 22 && HL == 0)
3404 {
4b7f6baa 3405 OUTS (outf, dregs (dst0));
086134ec 3406 OUTS (outf, " = BYTEOP2P (");
4b7f6baa
CM		 3407 OUTS (outf, dregs (src0 + 1));
3408 OUTS (outf, ":");
086134ec
BS		 3409 OUTS (outf, imm5d (src0));
3410 OUTS (outf, ", ");
4b7f6baa
CM		 3411 OUTS (outf, dregs (src1 + 1));
3412 OUTS (outf, ":");
086134ec
BS		 3413 OUTS (outf, imm5d (src1));
3414 OUTS (outf, ") (RNDL");
4b7f6baa
CM		 3415 if (s == 1)
3416 OUTS (outf, ", R)");
3417 else
3418 OUTS (outf, ")");
4b7f6baa
CM		 3419 }
3420 else if (aop == 0 && s == 0 && aopcde == 8)
086134ec 3421 OUTS (outf, "A0 = 0");
b7d48530 3422
4b7f6baa 3423 else if (aop == 0 && s == 1 && aopcde == 8)
086134ec 3424 OUTS (outf, "A0 = A0 (S)");
b7d48530 3425
4b7f6baa 3426 else if (aop == 1 && s == 0 && aopcde == 8)
086134ec 3427 OUTS (outf, "A1 = 0");
b7d48530 3428
4b7f6baa 3429 else if (aop == 1 && s == 1 && aopcde == 8)
086134ec 3430 OUTS (outf, "A1 = A1 (S)");
b7d48530 3431
4b7f6baa 3432 else if (aop == 2 && s == 0 && aopcde == 8)
086134ec 3433 OUTS (outf, "A1 = A0 = 0");
b7d48530 3434
4b7f6baa 3435 else if (aop == 2 && s == 1 && aopcde == 8)
086134ec 3436 OUTS (outf, "A1 = A1 (S), A0 = A0 (S)");
b7d48530 3437
4b7f6baa 3438 else if (aop == 3 && s == 0 && aopcde == 8)
086134ec 3439 OUTS (outf, "A0 = A1");
b7d48530 3440
4b7f6baa 3441 else if (aop == 3 && s == 1 && aopcde == 8)
086134ec 3442 OUTS (outf, "A1 = A0");
b7d48530 3443
4b7f6baa
CM		 3444 else if (aop == 1 && aopcde == 9 && s == 0)
3445 {
086134ec 3446 OUTS (outf, "A0.X = ");
4b7f6baa 3447 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3448 }
3449 else if (aop == 1 && HL == 0 && aopcde == 11)
3450 {
4b7f6baa 3451 OUTS (outf, dregs_lo (dst0));
086134ec 3452 OUTS (outf, " = (A0 += A1)");
4b7f6baa
CM		 3453 }
3454 else if (aop == 3 && HL == 0 && aopcde == 16)
13c02f06 3455 OUTS (outf, "A1 = ABS A1, A0 = ABS A0");
b7d48530 3456
4b7f6baa
CM		 3457 else if (aop == 0 && aopcde == 23 && HL == 1)
3458 {
4b7f6baa 3459 OUTS (outf, dregs (dst0));
086134ec 3460 OUTS (outf, " = BYTEOP3P (");
4b7f6baa
CM		 3461 OUTS (outf, dregs (src0 + 1));
3462 OUTS (outf, ":");
086134ec
BS		 3463 OUTS (outf, imm5d (src0));
3464 OUTS (outf, ", ");
4b7f6baa
CM		 3465 OUTS (outf, dregs (src1 + 1));
3466 OUTS (outf, ":");
086134ec
BS		 3467 OUTS (outf, imm5d (src1));
3468 OUTS (outf, ") (HI");
4b7f6baa
CM		 3469 if (s == 1)
3470 OUTS (outf, ", R)");
3471 else
3472 OUTS (outf, ")");
4b7f6baa
CM		 3473 }
3474 else if (aop == 3 && aopcde == 9 && s == 0)
3475 {
086134ec 3476 OUTS (outf, "A1.X = ");
4b7f6baa 3477 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3478 }
3479 else if (aop == 1 && HL == 1 && aopcde == 16)
086134ec 3480 OUTS (outf, "A1 = ABS A1");
b7d48530 3481
4b7f6baa 3482 else if (aop == 0 && HL == 1 && aopcde == 16)
086134ec 3483 OUTS (outf, "A1 = ABS A0");
b7d48530 3484
4b7f6baa
CM		 3485 else if (aop == 2 && aopcde == 9 && s == 1)
3486 {
086134ec 3487 OUTS (outf, "A1 = ");
4b7f6baa 3488 OUTS (outf, dregs (src0));
4b7f6baa
CM		 3489 }
3490 else if (HL == 0 && aop == 3 && aopcde == 12)
3491 {
4b7f6baa 3492 OUTS (outf, dregs_lo (dst0));
086134ec 3493 OUTS (outf, " = ");
4b7f6baa 3494 OUTS (outf, dregs (src0));
086134ec 3495 OUTS (outf, " (RND)");
4b7f6baa
CM		 3496 }
3497 else if (aop == 1 && HL == 0 && aopcde == 16)
086134ec 3498 OUTS (outf, "A0 = ABS A1");
b7d48530 3499
4b7f6baa 3500 else if (aop == 0 && HL == 0 && aopcde == 16)
086134ec 3501 OUTS (outf, "A0 = ABS A0");
b7d48530 3502
4b7f6baa
CM		 3503 else if (aop == 3 && HL == 0 && aopcde == 15)
3504 {
4b7f6baa 3505 OUTS (outf, dregs (dst0));
086134ec 3506 OUTS (outf, " = -");
4b7f6baa 3507 OUTS (outf, dregs (src0));
086134ec 3508 OUTS (outf, " (V)");
4b7f6baa
CM		 3509 }
3510 else if (aop == 3 && s == 1 && HL == 0 && aopcde == 7)
3511 {
4b7f6baa 3512 OUTS (outf, dregs (dst0));
086134ec 3513 OUTS (outf, " = -");
4b7f6baa 3514 OUTS (outf, dregs (src0));
086134ec 3515 OUTS (outf, " (S)");
4b7f6baa
CM		 3516 }
3517 else if (aop == 3 && s == 0 && HL == 0 && aopcde == 7)
3518 {
4b7f6baa 3519 OUTS (outf, dregs (dst0));
086134ec 3520 OUTS (outf, " = -");
4b7f6baa 3521 OUTS (outf, dregs (src0));
086134ec 3522 OUTS (outf, " (NS)");
4b7f6baa
CM		 3523 }
3524 else if (aop == 1 && HL == 1 && aopcde == 11)
3525 {
4b7f6baa 3526 OUTS (outf, dregs_hi (dst0));
086134ec 3527 OUTS (outf, " = (A0 += A1)");
4b7f6baa
CM		 3528 }
3529 else if (aop == 2 && aopcde == 11 && s == 0)
086134ec 3530 OUTS (outf, "A0 += A1");
b7d48530 3531
4b7f6baa 3532 else if (aop == 2 && aopcde == 11 && s == 1)
086134ec 3533 OUTS (outf, "A0 += A1 (W32)");
b7d48530 3534
4b7f6baa 3535 else if (aop == 3 && HL == 0 && aopcde == 14)
086134ec 3536 OUTS (outf, "A1 = -A1, A0 = -A0");
b7d48530 3537
4b7f6baa
CM		 3538 else if (HL == 1 && aop == 3 && aopcde == 12)
3539 {
4b7f6baa 3540 OUTS (outf, dregs_hi (dst0));
086134ec 3541 OUTS (outf, " = ");
4b7f6baa 3542 OUTS (outf, dregs (src0));
086134ec 3543 OUTS (outf, " (RND)");
4b7f6baa
CM		 3544 }
3545 else if (aop == 0 && aopcde == 23 && HL == 0)
3546 {
4b7f6baa 3547 OUTS (outf, dregs (dst0));
086134ec 3548 OUTS (outf, " = BYTEOP3P (");
4b7f6baa
CM		 3549 OUTS (outf, dregs (src0 + 1));
3550 OUTS (outf, ":");
086134ec
BS		 3551 OUTS (outf, imm5d (src0));
3552 OUTS (outf, ", ");
4b7f6baa
CM		 3553 OUTS (outf, dregs (src1 + 1));
3554 OUTS (outf, ":");
086134ec
BS		 3555 OUTS (outf, imm5d (src1));
3556 OUTS (outf, ") (LO");
4b7f6baa
CM		 3557 if (s == 1)
3558 OUTS (outf, ", R)");
3559 else
3560 OUTS (outf, ")");
4b7f6baa
CM		 3561 }
3562 else if (aop == 0 && HL == 0 && aopcde == 14)
086134ec 3563 OUTS (outf, "A0 = -A0");
b7d48530 3564
4b7f6baa 3565 else if (aop == 1 && HL == 0 && aopcde == 14)
086134ec 3566 OUTS (outf, "A0 = -A1");
b7d48530 3567
4b7f6baa 3568 else if (aop == 0 && HL == 1 && aopcde == 14)
086134ec 3569 OUTS (outf, "A1 = -A0");
b7d48530 3570
4b7f6baa 3571 else if (aop == 1 && HL == 1 && aopcde == 14)
086134ec 3572 OUTS (outf, "A1 = -A1");
b7d48530 3573
4b7f6baa
CM		 3574 else if (aop == 0 && aopcde == 12)
3575 {
4b7f6baa 3576 OUTS (outf, dregs_hi (dst0));
086134ec 3577 OUTS (outf, " = ");
4b7f6baa 3578 OUTS (outf, dregs_lo (dst0));
086134ec 3579 OUTS (outf, " = SIGN (");
4b7f6baa 3580 OUTS (outf, dregs_hi (src0));
086134ec 3581 OUTS (outf, ") * ");
4b7f6baa 3582 OUTS (outf, dregs_hi (src1));
086134ec 3583 OUTS (outf, " + SIGN (");
4b7f6baa 3584 OUTS (outf, dregs_lo (src0));
086134ec 3585 OUTS (outf, ") * ");
4b7f6baa 3586 OUTS (outf, dregs_lo (src1));
4b7f6baa
CM		 3587 }
3588 else if (aop == 2 && aopcde == 0)
3589 {
4b7f6baa 3590 OUTS (outf, dregs (dst0));
086134ec 3591 OUTS (outf, " = ");
4b7f6baa 3592 OUTS (outf, dregs (src0));
086134ec 3593 OUTS (outf, " -|+ ");
4b7f6baa 3594 OUTS (outf, dregs (src1));
4b7f6baa 3595 amod0 (s, x, outf);
4b7f6baa
CM		 3596 }
3597 else if (aop == 1 && aopcde == 12)
3598 {
4b7f6baa 3599 OUTS (outf, dregs (dst1));
086134ec 3600 OUTS (outf, " = A1.L + A1.H, ");
4b7f6baa 3601 OUTS (outf, dregs (dst0));
086134ec 3602 OUTS (outf, " = A0.L + A0.H");
4b7f6baa
CM		 3603 }
3604 else if (aop == 2 && aopcde == 4)
3605 {
4b7f6baa 3606 OUTS (outf, dregs (dst1));
086134ec 3607 OUTS (outf, " = ");
4b7f6baa 3608 OUTS (outf, dregs (src0));
086134ec 3609 OUTS (outf, " + ");
4b7f6baa 3610 OUTS (outf, dregs (src1));
086134ec 3611 OUTS (outf, ", ");
4b7f6baa 3612 OUTS (outf, dregs (dst0));
086134ec 3613 OUTS (outf, " = ");
4b7f6baa 3614 OUTS (outf, dregs (src0));
086134ec 3615 OUTS (outf, " - ");
4b7f6baa 3616 OUTS (outf, dregs (src1));
4b7f6baa 3617 amod1 (s, x, outf);
4b7f6baa
CM		 3618 }
3619 else if (HL == 0 && aopcde == 1)
3620 {
4b7f6baa 3621 OUTS (outf, dregs (dst1));
086134ec 3622 OUTS (outf, " = ");
4b7f6baa 3623 OUTS (outf, dregs (src0));
086134ec 3624 OUTS (outf, " +|+ ");
4b7f6baa 3625 OUTS (outf, dregs (src1));
086134ec 3626 OUTS (outf, ", ");
4b7f6baa 3627 OUTS (outf, dregs (dst0));
086134ec 3628 OUTS (outf, " = ");
4b7f6baa 3629 OUTS (outf, dregs (src0));
086134ec 3630 OUTS (outf, " -|- ");
4b7f6baa
CM		 3631 OUTS (outf, dregs (src1));
3632 amod0amod2 (s, x, aop, outf);
4b7f6baa
CM		 3633 }
3634 else if (aop == 0 && aopcde == 11)
3635 {
4b7f6baa 3636 OUTS (outf, dregs (dst0));
086134ec 3637 OUTS (outf, " = (A0 += A1)");
4b7f6baa
CM		 3638 }
3639 else if (aop == 0 && aopcde == 10)
3640 {
4b7f6baa 3641 OUTS (outf, dregs_lo (dst0));
086134ec 3642 OUTS (outf, " = A0.X");
4b7f6baa
CM		 3643 }
3644 else if (aop == 1 && aopcde == 10)
3645 {
4b7f6baa 3646 OUTS (outf, dregs_lo (dst0));
086134ec 3647 OUTS (outf, " = A1.X");
4b7f6baa
CM		 3648 }
3649 else if (aop == 1 && aopcde == 0)
3650 {
4b7f6baa 3651 OUTS (outf, dregs (dst0));
086134ec 3652 OUTS (outf, " = ");
4b7f6baa 3653 OUTS (outf, dregs (src0));
086134ec 3654 OUTS (outf, " +|- ");
4b7f6baa 3655 OUTS (outf, dregs (src1));
4b7f6baa 3656 amod0 (s, x, outf);
4b7f6baa
CM		 3657 }
3658 else if (aop == 3 && aopcde == 0)
3659 {
4b7f6baa 3660 OUTS (outf, dregs (dst0));
086134ec 3661 OUTS (outf, " = ");
4b7f6baa 3662 OUTS (outf, dregs (src0));
086134ec 3663 OUTS (outf, " -|- ");
4b7f6baa 3664 OUTS (outf, dregs (src1));
4b7f6baa 3665 amod0 (s, x, outf);
4b7f6baa
CM		 3666 }
3667 else if (aop == 1 && aopcde == 4)
3668 {
4b7f6baa 3669 OUTS (outf, dregs (dst0));
086134ec 3670 OUTS (outf, " = ");
4b7f6baa 3671 OUTS (outf, dregs (src0));
086134ec 3672 OUTS (outf, " - ");
4b7f6baa 3673 OUTS (outf, dregs (src1));
4b7f6baa 3674 amod1 (s, x, outf);
4b7f6baa
CM		 3675 }
3676 else if (aop == 0 && aopcde == 17)
3677 {
4b7f6baa 3678 OUTS (outf, dregs (dst1));
086134ec 3679 OUTS (outf, " = A1 + A0, ");
4b7f6baa 3680 OUTS (outf, dregs (dst0));
086134ec 3681 OUTS (outf, " = A1 - A0");
4b7f6baa 3682 amod1 (s, x, outf);
4b7f6baa
CM		 3683 }
3684 else if (aop == 1 && aopcde == 17)
3685 {
4b7f6baa 3686 OUTS (outf, dregs (dst1));
086134ec 3687 OUTS (outf, " = A0 + A1, ");
4b7f6baa 3688 OUTS (outf, dregs (dst0));
086134ec 3689 OUTS (outf, " = A0 - A1");
4b7f6baa 3690 amod1 (s, x, outf);
4b7f6baa
CM		 3691 }
3692 else if (aop == 0 && aopcde == 18)
3693 {
086134ec 3694 OUTS (outf, "SAA (");
4b7f6baa
CM		 3695 OUTS (outf, dregs (src0 + 1));
3696 OUTS (outf, ":");
086134ec
BS		 3697 OUTS (outf, imm5d (src0));
3698 OUTS (outf, ", ");
4b7f6baa
CM		 3699 OUTS (outf, dregs (src1 + 1));
3700 OUTS (outf, ":");
086134ec
BS		 3701 OUTS (outf, imm5d (src1));
3702 OUTS (outf, ")");
4b7f6baa 3703 aligndir (s, outf);
4b7f6baa
CM		 3704 }
3705 else if (aop == 3 && aopcde == 18)
b7d48530
NC		 3706 OUTS (outf, "DISALGNEXCPT");
3707
4b7f6baa
CM		 3708 else if (aop == 0 && aopcde == 20)
3709 {
4b7f6baa 3710 OUTS (outf, dregs (dst0));
086134ec 3711 OUTS (outf, " = BYTEOP1P (");
4b7f6baa
CM		 3712 OUTS (outf, dregs (src0 + 1));
3713 OUTS (outf, ":");
086134ec
BS		 3714 OUTS (outf, imm5d (src0));
3715 OUTS (outf, ", ");
4b7f6baa
CM		 3716 OUTS (outf, dregs (src1 + 1));
3717 OUTS (outf, ":");
086134ec 3718 OUTS (outf, imm5d (src1));
4b7f6baa
CM		 3719 OUTS (outf, ")");
3720 aligndir (s, outf);
4b7f6baa
CM		 3721 }
3722 else if (aop == 1 && aopcde == 20)
3723 {
4b7f6baa 3724 OUTS (outf, dregs (dst0));
086134ec 3725 OUTS (outf, " = BYTEOP1P (");
4b7f6baa
CM		 3726 OUTS (outf, dregs (src0 + 1));
3727 OUTS (outf, ":");
086134ec
BS		 3728 OUTS (outf, imm5d (src0));
3729 OUTS (outf, ", ");
4b7f6baa
CM		 3730 OUTS (outf, dregs (src1 + 1));
3731 OUTS (outf, ":");
086134ec
BS		 3732 OUTS (outf, imm5d (src1));
3733 OUTS (outf, ") (T");
4b7f6baa
CM		 3734 if (s == 1)
3735 OUTS (outf, ", R)");
3736 else
3737 OUTS (outf, ")");
4b7f6baa
CM		 3738 }
3739 else if (aop == 0 && aopcde == 21)
3740 {
4b7f6baa
CM		 3741 OUTS (outf, "(");
3742 OUTS (outf, dregs (dst1));
086134ec 3743 OUTS (outf, ", ");
4b7f6baa 3744 OUTS (outf, dregs (dst0));
086134ec 3745 OUTS (outf, ") = BYTEOP16P (");
4b7f6baa
CM		 3746 OUTS (outf, dregs (src0 + 1));
3747 OUTS (outf, ":");
086134ec
BS		 3748 OUTS (outf, imm5d (src0));
3749 OUTS (outf, ", ");
4b7f6baa
CM		 3750 OUTS (outf, dregs (src1 + 1));
3751 OUTS (outf, ":");
086134ec
BS		 3752 OUTS (outf, imm5d (src1));
3753 OUTS (outf, ")");
4b7f6baa 3754 aligndir (s, outf);
4b7f6baa
CM		 3755 }
3756 else if (aop == 1 && aopcde == 21)
3757 {
4b7f6baa
CM		 3758 OUTS (outf, "(");
3759 OUTS (outf, dregs (dst1));
086134ec 3760 OUTS (outf, ", ");
4b7f6baa 3761 OUTS (outf, dregs (dst0));
086134ec 3762 OUTS (outf, ") = BYTEOP16M (");
4b7f6baa
CM		 3763 OUTS (outf, dregs (src0 + 1));
3764 OUTS (outf, ":");
086134ec
BS		 3765 OUTS (outf, imm5d (src0));
3766 OUTS (outf, ", ");
4b7f6baa
CM		 3767 OUTS (outf, dregs (src1 + 1));
3768 OUTS (outf, ":");
086134ec
BS		 3769 OUTS (outf, imm5d (src1));
3770 OUTS (outf, ")");
4b7f6baa 3771 aligndir (s, outf);
4b7f6baa
CM		 3772 }
3773 else if (aop == 2 && aopcde == 7)
3774 {
4b7f6baa 3775 OUTS (outf, dregs (dst0));
086134ec 3776 OUTS (outf, " = ABS ");
4b7f6baa 3777 OUTS (outf, dregs (src0));
4b7f6baa
CM		 3778 }
3779 else if (aop == 1 && aopcde == 7)
3780 {
4b7f6baa 3781 OUTS (outf, dregs (dst0));
086134ec 3782 OUTS (outf, " = MIN (");
4b7f6baa 3783 OUTS (outf, dregs (src0));
086134ec 3784 OUTS (outf, ", ");
4b7f6baa
CM		 3785 OUTS (outf, dregs (src1));
3786 OUTS (outf, ")");
4b7f6baa
CM		 3787 }
3788 else if (aop == 0 && aopcde == 7)
3789 {
4b7f6baa 3790 OUTS (outf, dregs (dst0));
086134ec 3791 OUTS (outf, " = MAX (");
4b7f6baa 3792 OUTS (outf, dregs (src0));
086134ec 3793 OUTS (outf, ", ");
4b7f6baa
CM		 3794 OUTS (outf, dregs (src1));
3795 OUTS (outf, ")");
4b7f6baa
CM		 3796 }
3797 else if (aop == 2 && aopcde == 6)
3798 {
4b7f6baa 3799 OUTS (outf, dregs (dst0));
086134ec 3800 OUTS (outf, " = ABS ");
4b7f6baa 3801 OUTS (outf, dregs (src0));
086134ec 3802 OUTS (outf, " (V)");
4b7f6baa
CM		 3803 }
3804 else if (aop == 1 && aopcde == 6)
3805 {
4b7f6baa 3806 OUTS (outf, dregs (dst0));
086134ec 3807 OUTS (outf, " = MIN (");
4b7f6baa 3808 OUTS (outf, dregs (src0));
086134ec 3809 OUTS (outf, ", ");
4b7f6baa 3810 OUTS (outf, dregs (src1));
086134ec 3811 OUTS (outf, ") (V)");
4b7f6baa
CM		 3812 }
3813 else if (aop == 0 && aopcde == 6)
3814 {
4b7f6baa 3815 OUTS (outf, dregs (dst0));
086134ec 3816 OUTS (outf, " = MAX (");
4b7f6baa 3817 OUTS (outf, dregs (src0));
086134ec 3818 OUTS (outf, ", ");
4b7f6baa 3819 OUTS (outf, dregs (src1));
086134ec 3820 OUTS (outf, ") (V)");
4b7f6baa
CM		 3821 }
3822 else if (HL == 1 && aopcde == 1)
3823 {
4b7f6baa 3824 OUTS (outf, dregs (dst1));
086134ec 3825 OUTS (outf, " = ");
4b7f6baa 3826 OUTS (outf, dregs (src0));
086134ec 3827 OUTS (outf, " +|- ");
4b7f6baa 3828 OUTS (outf, dregs (src1));
086134ec 3829 OUTS (outf, ", ");
4b7f6baa 3830 OUTS (outf, dregs (dst0));
086134ec 3831 OUTS (outf, " = ");
4b7f6baa 3832 OUTS (outf, dregs (src0));
086134ec 3833 OUTS (outf, " -|+ ");
4b7f6baa
CM		 3834 OUTS (outf, dregs (src1));
3835 amod0amod2 (s, x, aop, outf);
4b7f6baa
CM		 3836 }
3837 else if (aop == 0 && aopcde == 4)
3838 {
4b7f6baa 3839 OUTS (outf, dregs (dst0));
086134ec 3840 OUTS (outf, " = ");
4b7f6baa 3841 OUTS (outf, dregs (src0));
086134ec 3842 OUTS (outf, " + ");
4b7f6baa 3843 OUTS (outf, dregs (src1));
4b7f6baa 3844 amod1 (s, x, outf);
4b7f6baa
CM		 3845 }
3846 else if (aop == 0 && aopcde == 0)
3847 {
4b7f6baa 3848 OUTS (outf, dregs (dst0));
086134ec 3849 OUTS (outf, " = ");
4b7f6baa 3850 OUTS (outf, dregs (src0));
086134ec 3851 OUTS (outf, " +|+ ");
4b7f6baa 3852 OUTS (outf, dregs (src1));
4b7f6baa 3853 amod0 (s, x, outf);
4b7f6baa
CM		 3854 }
3855 else if (aop == 0 && aopcde == 24)
3856 {
4b7f6baa 3857 OUTS (outf, dregs (dst0));
086134ec 3858 OUTS (outf, " = BYTEPACK (");
4b7f6baa 3859 OUTS (outf, dregs (src0));
086134ec 3860 OUTS (outf, ", ");
4b7f6baa
CM		 3861 OUTS (outf, dregs (src1));
3862 OUTS (outf, ")");
4b7f6baa
CM		 3863 }
3864 else if (aop == 1 && aopcde == 24)
3865 {
4b7f6baa
CM		 3866 OUTS (outf, "(");
3867 OUTS (outf, dregs (dst1));
086134ec 3868 OUTS (outf, ", ");
4b7f6baa
CM		 3869 OUTS (outf, dregs (dst0));
3870 OUTS (outf, ") = BYTEUNPACK ");
3871 OUTS (outf, dregs (src0 + 1));
3872 OUTS (outf, ":");
086134ec 3873 OUTS (outf, imm5d (src0));
4b7f6baa 3874 aligndir (s, outf);
4b7f6baa
CM		 3875 }
3876 else if (aopcde == 13)
3877 {
4b7f6baa
CM		 3878 OUTS (outf, "(");
3879 OUTS (outf, dregs (dst1));
086134ec 3880 OUTS (outf, ", ");
4b7f6baa
CM		 3881 OUTS (outf, dregs (dst0));
3882 OUTS (outf, ") = SEARCH ");
3883 OUTS (outf, dregs (src0));
086134ec 3884 OUTS (outf, " (");
4b7f6baa
CM		 3885 searchmod (aop, outf);
3886 OUTS (outf, ")");
4b7f6baa
CM		 3887 }
3888 else
b7d48530
NC		 3889 return 0;
3890
3891 return 4;
4b7f6baa
CM		 3892}
3893
3894static int
3895decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3896{
b7d48530
NC		 3897 /* dsp32shift
3898 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3899 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
3900 |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
3901 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 3902 int HLs = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask);
3903 int sop = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask);
3904 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask);
3905 int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask);
3906 int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask);
3907 int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask);
3908 const char *acc01 = (HLs & 1) == 0 ? "A0" : "A1";
3909
4b7f6baa
CM		 3910 if (HLs == 0 && sop == 0 && sopcde == 0)
3911 {
4b7f6baa 3912 OUTS (outf, dregs_lo (dst0));
086134ec 3913 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3914 OUTS (outf, dregs_lo (src1));
3915 OUTS (outf, " BY ");
3916 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3917 }
3918 else if (HLs == 1 && sop == 0 && sopcde == 0)
3919 {
4b7f6baa 3920 OUTS (outf, dregs_lo (dst0));
086134ec 3921 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3922 OUTS (outf, dregs_hi (src1));
3923 OUTS (outf, " BY ");
3924 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3925 }
3926 else if (HLs == 2 && sop == 0 && sopcde == 0)
3927 {
4b7f6baa 3928 OUTS (outf, dregs_hi (dst0));
086134ec 3929 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3930 OUTS (outf, dregs_lo (src1));
3931 OUTS (outf, " BY ");
3932 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3933 }
3934 else if (HLs == 3 && sop == 0 && sopcde == 0)
3935 {
4b7f6baa 3936 OUTS (outf, dregs_hi (dst0));
086134ec 3937 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3938 OUTS (outf, dregs_hi (src1));
3939 OUTS (outf, " BY ");
3940 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3941 }
3942 else if (HLs == 0 && sop == 1 && sopcde == 0)
3943 {
4b7f6baa 3944 OUTS (outf, dregs_lo (dst0));
086134ec 3945 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3946 OUTS (outf, dregs_lo (src1));
3947 OUTS (outf, " BY ");
3948 OUTS (outf, dregs_lo (src0));
086134ec 3949 OUTS (outf, " (S)");
4b7f6baa
CM		 3950 }
3951 else if (HLs == 1 && sop == 1 && sopcde == 0)
3952 {
4b7f6baa 3953 OUTS (outf, dregs_lo (dst0));
086134ec 3954 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3955 OUTS (outf, dregs_hi (src1));
3956 OUTS (outf, " BY ");
3957 OUTS (outf, dregs_lo (src0));
086134ec 3958 OUTS (outf, " (S)");
4b7f6baa
CM		 3959 }
3960 else if (HLs == 2 && sop == 1 && sopcde == 0)
3961 {
4b7f6baa 3962 OUTS (outf, dregs_hi (dst0));
086134ec 3963 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3964 OUTS (outf, dregs_lo (src1));
3965 OUTS (outf, " BY ");
3966 OUTS (outf, dregs_lo (src0));
086134ec 3967 OUTS (outf, " (S)");
4b7f6baa
CM		 3968 }
3969 else if (HLs == 3 && sop == 1 && sopcde == 0)
3970 {
4b7f6baa 3971 OUTS (outf, dregs_hi (dst0));
086134ec 3972 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3973 OUTS (outf, dregs_hi (src1));
3974 OUTS (outf, " BY ");
3975 OUTS (outf, dregs_lo (src0));
086134ec 3976 OUTS (outf, " (S)");
4b7f6baa
CM		 3977 }
3978 else if (sop == 2 && sopcde == 0)
3979 {
4b7f6baa 3980 OUTS (outf, (HLs & 2) == 0 ? dregs_lo (dst0) : dregs_hi (dst0));
086134ec 3981 OUTS (outf, " = LSHIFT ");
4b7f6baa
CM		 3982 OUTS (outf, (HLs & 1) == 0 ? dregs_lo (src1) : dregs_hi (src1));
3983 OUTS (outf, " BY ");
3984 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3985 }
3986 else if (sop == 0 && sopcde == 3)
3987 {
4b7f6baa 3988 OUTS (outf, acc01);
086134ec 3989 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3990 OUTS (outf, acc01);
3991 OUTS (outf, " BY ");
3992 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3993 }
3994 else if (sop == 1 && sopcde == 3)
3995 {
4b7f6baa 3996 OUTS (outf, acc01);
086134ec 3997 OUTS (outf, " = LSHIFT ");
4b7f6baa
CM		 3998 OUTS (outf, acc01);
3999 OUTS (outf, " BY ");
4000 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4001 }
4002 else if (sop == 2 && sopcde == 3)
4003 {
4b7f6baa 4004 OUTS (outf, acc01);
086134ec 4005 OUTS (outf, " = ROT ");
4b7f6baa
CM		 4006 OUTS (outf, acc01);
4007 OUTS (outf, " BY ");
4008 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4009 }
4010 else if (sop == 3 && sopcde == 3)
4011 {
4b7f6baa 4012 OUTS (outf, dregs (dst0));
086134ec 4013 OUTS (outf, " = ROT ");
4b7f6baa
CM		 4014 OUTS (outf, dregs (src1));
4015 OUTS (outf, " BY ");
4016 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4017 }
4018 else if (sop == 1 && sopcde == 1)
4019 {
4b7f6baa 4020 OUTS (outf, dregs (dst0));
086134ec 4021 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4022 OUTS (outf, dregs (src1));
4023 OUTS (outf, " BY ");
4024 OUTS (outf, dregs_lo (src0));
086134ec 4025 OUTS (outf, " (V, S)");
4b7f6baa
CM		 4026 }
4027 else if (sop == 0 && sopcde == 1)
4028 {
4b7f6baa 4029 OUTS (outf, dregs (dst0));
086134ec 4030 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4031 OUTS (outf, dregs (src1));
4032 OUTS (outf, " BY ");
4033 OUTS (outf, dregs_lo (src0));
086134ec 4034 OUTS (outf, " (V)");
4b7f6baa
CM		 4035 }
4036 else if (sop == 0 && sopcde == 2)
4037 {
4b7f6baa 4038 OUTS (outf, dregs (dst0));
086134ec 4039 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4040 OUTS (outf, dregs (src1));
4041 OUTS (outf, " BY ");
4042 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4043 }
4044 else if (sop == 1 && sopcde == 2)
4045 {
4b7f6baa 4046 OUTS (outf, dregs (dst0));
086134ec 4047 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4048 OUTS (outf, dregs (src1));
4049 OUTS (outf, " BY ");
4050 OUTS (outf, dregs_lo (src0));
086134ec 4051 OUTS (outf, " (S)");
4b7f6baa
CM		 4052 }
4053 else if (sop == 2 && sopcde == 2)
4054 {
4b7f6baa 4055 OUTS (outf, dregs (dst0));
59a82d23 4056 OUTS (outf, " = LSHIFT ");
4b7f6baa
CM		 4057 OUTS (outf, dregs (src1));
4058 OUTS (outf, " BY ");
4059 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4060 }
4061 else if (sop == 3 && sopcde == 2)
4062 {
4b7f6baa 4063 OUTS (outf, dregs (dst0));
086134ec 4064 OUTS (outf, " = ROT ");
4b7f6baa
CM		 4065 OUTS (outf, dregs (src1));
4066 OUTS (outf, " BY ");
4067 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4068 }
4069 else if (sop == 2 && sopcde == 1)
4070 {
4b7f6baa 4071 OUTS (outf, dregs (dst0));
59a82d23 4072 OUTS (outf, " = LSHIFT ");
4b7f6baa
CM		 4073 OUTS (outf, dregs (src1));
4074 OUTS (outf, " BY ");
4075 OUTS (outf, dregs_lo (src0));
086134ec 4076 OUTS (outf, " (V)");
4b7f6baa
CM		 4077 }
4078 else if (sop == 0 && sopcde == 4)
4079 {
4b7f6baa 4080 OUTS (outf, dregs (dst0));
086134ec 4081 OUTS (outf, " = PACK (");
4b7f6baa 4082 OUTS (outf, dregs_lo (src1));
086134ec 4083 OUTS (outf, ", ");
4b7f6baa
CM		 4084 OUTS (outf, dregs_lo (src0));
4085 OUTS (outf, ")");
4b7f6baa
CM		 4086 }
4087 else if (sop == 1 && sopcde == 4)
4088 {
4b7f6baa 4089 OUTS (outf, dregs (dst0));
086134ec 4090 OUTS (outf, " = PACK (");
4b7f6baa 4091 OUTS (outf, dregs_lo (src1));
086134ec 4092 OUTS (outf, ", ");
4b7f6baa
CM		 4093 OUTS (outf, dregs_hi (src0));
4094 OUTS (outf, ")");
4b7f6baa
CM		 4095 }
4096 else if (sop == 2 && sopcde == 4)
4097 {
4b7f6baa 4098 OUTS (outf, dregs (dst0));
086134ec 4099 OUTS (outf, " = PACK (");
4b7f6baa 4100 OUTS (outf, dregs_hi (src1));
086134ec 4101 OUTS (outf, ", ");
4b7f6baa
CM		 4102 OUTS (outf, dregs_lo (src0));
4103 OUTS (outf, ")");
4b7f6baa
CM		 4104 }
4105 else if (sop == 3 && sopcde == 4)
4106 {
4b7f6baa 4107 OUTS (outf, dregs (dst0));
086134ec 4108 OUTS (outf, " = PACK (");
4b7f6baa 4109 OUTS (outf, dregs_hi (src1));
086134ec 4110 OUTS (outf, ", ");
4b7f6baa
CM		 4111 OUTS (outf, dregs_hi (src0));
4112 OUTS (outf, ")");
4b7f6baa
CM		 4113 }
4114 else if (sop == 0 && sopcde == 5)
4115 {
4b7f6baa 4116 OUTS (outf, dregs_lo (dst0));
086134ec 4117 OUTS (outf, " = SIGNBITS ");
4b7f6baa 4118 OUTS (outf, dregs (src1));
4b7f6baa
CM		 4119 }
4120 else if (sop == 1 && sopcde == 5)
4121 {
4b7f6baa 4122 OUTS (outf, dregs_lo (dst0));
086134ec 4123 OUTS (outf, " = SIGNBITS ");
4b7f6baa 4124 OUTS (outf, dregs_lo (src1));
4b7f6baa
CM		 4125 }
4126 else if (sop == 2 && sopcde == 5)
4127 {
4b7f6baa 4128 OUTS (outf, dregs_lo (dst0));
086134ec 4129 OUTS (outf, " = SIGNBITS ");
4b7f6baa 4130 OUTS (outf, dregs_hi (src1));
4b7f6baa
CM		 4131 }
4132 else if (sop == 0 && sopcde == 6)
4133 {
4b7f6baa 4134 OUTS (outf, dregs_lo (dst0));
086134ec 4135 OUTS (outf, " = SIGNBITS A0");
4b7f6baa
CM		 4136 }
4137 else if (sop == 1 && sopcde == 6)
4138 {
4b7f6baa 4139 OUTS (outf, dregs_lo (dst0));
086134ec 4140 OUTS (outf, " = SIGNBITS A1");
4b7f6baa
CM		 4141 }
4142 else if (sop == 3 && sopcde == 6)
4143 {
4b7f6baa 4144 OUTS (outf, dregs_lo (dst0));
086134ec 4145 OUTS (outf, " = ONES ");
4b7f6baa 4146 OUTS (outf, dregs (src1));
4b7f6baa
CM		 4147 }
4148 else if (sop == 0 && sopcde == 7)
4149 {
4b7f6baa 4150 OUTS (outf, dregs_lo (dst0));
086134ec 4151 OUTS (outf, " = EXPADJ (");
4b7f6baa 4152 OUTS (outf, dregs (src1));
086134ec 4153 OUTS (outf, ", ");
4b7f6baa
CM		 4154 OUTS (outf, dregs_lo (src0));
4155 OUTS (outf, ")");
4b7f6baa
CM		 4156 }
4157 else if (sop == 1 && sopcde == 7)
4158 {
4b7f6baa 4159 OUTS (outf, dregs_lo (dst0));
086134ec 4160 OUTS (outf, " = EXPADJ (");
4b7f6baa 4161 OUTS (outf, dregs (src1));
086134ec 4162 OUTS (outf, ", ");
4b7f6baa
CM		 4163 OUTS (outf, dregs_lo (src0));
4164 OUTS (outf, ") (V)");
4b7f6baa
CM		 4165 }
4166 else if (sop == 2 && sopcde == 7)
4167 {
4b7f6baa 4168 OUTS (outf, dregs_lo (dst0));
086134ec 4169 OUTS (outf, " = EXPADJ (");
4b7f6baa 4170 OUTS (outf, dregs_lo (src1));
086134ec 4171 OUTS (outf, ", ");
4b7f6baa
CM		 4172 OUTS (outf, dregs_lo (src0));
4173 OUTS (outf, ")");
4b7f6baa
CM		 4174 }
4175 else if (sop == 3 && sopcde == 7)
4176 {
4b7f6baa 4177 OUTS (outf, dregs_lo (dst0));
086134ec 4178 OUTS (outf, " = EXPADJ (");
4b7f6baa 4179 OUTS (outf, dregs_hi (src1));
086134ec 4180 OUTS (outf, ", ");
4b7f6baa
CM		 4181 OUTS (outf, dregs_lo (src0));
4182 OUTS (outf, ")");
4b7f6baa
CM		 4183 }
4184 else if (sop == 0 && sopcde == 8)
4185 {
4b7f6baa
CM		 4186 OUTS (outf, "BITMUX (");
4187 OUTS (outf, dregs (src0));
086134ec 4188 OUTS (outf, ", ");
4b7f6baa 4189 OUTS (outf, dregs (src1));
086134ec 4190 OUTS (outf, ", A0) (ASR)");
4b7f6baa
CM		 4191 }
4192 else if (sop == 1 && sopcde == 8)
4193 {
4b7f6baa
CM		 4194 OUTS (outf, "BITMUX (");
4195 OUTS (outf, dregs (src0));
086134ec 4196 OUTS (outf, ", ");
4b7f6baa 4197 OUTS (outf, dregs (src1));
086134ec 4198 OUTS (outf, ", A0) (ASL)");
4b7f6baa
CM		 4199 }
4200 else if (sop == 0 && sopcde == 9)
4201 {
4b7f6baa 4202 OUTS (outf, dregs_lo (dst0));
086134ec 4203 OUTS (outf, " = VIT_MAX (");
4b7f6baa
CM		 4204 OUTS (outf, dregs (src1));
4205 OUTS (outf, ") (ASL)");
4b7f6baa
CM		 4206 }
4207 else if (sop == 1 && sopcde == 9)
4208 {
4b7f6baa 4209 OUTS (outf, dregs_lo (dst0));
086134ec 4210 OUTS (outf, " = VIT_MAX (");
4b7f6baa
CM		 4211 OUTS (outf, dregs (src1));
4212 OUTS (outf, ") (ASR)");
4b7f6baa
CM		 4213 }
4214 else if (sop == 2 && sopcde == 9)
4215 {
4b7f6baa 4216 OUTS (outf, dregs (dst0));
086134ec 4217 OUTS (outf, " = VIT_MAX (");
4b7f6baa 4218 OUTS (outf, dregs (src1));
086134ec 4219 OUTS (outf, ", ");
4b7f6baa 4220 OUTS (outf, dregs (src0));
086134ec 4221 OUTS (outf, ") (ASL)");
4b7f6baa
CM		 4222 }
4223 else if (sop == 3 && sopcde == 9)
4224 {
4b7f6baa 4225 OUTS (outf, dregs (dst0));
086134ec 4226 OUTS (outf, " = VIT_MAX (");
4b7f6baa 4227 OUTS (outf, dregs (src1));
086134ec 4228 OUTS (outf, ", ");
4b7f6baa 4229 OUTS (outf, dregs (src0));
086134ec 4230 OUTS (outf, ") (ASR)");
4b7f6baa
CM		 4231 }
4232 else if (sop == 0 && sopcde == 10)
4233 {
4b7f6baa 4234 OUTS (outf, dregs (dst0));
086134ec 4235 OUTS (outf, " = EXTRACT (");
4b7f6baa 4236 OUTS (outf, dregs (src1));
086134ec 4237 OUTS (outf, ", ");
4b7f6baa
CM		 4238 OUTS (outf, dregs_lo (src0));
4239 OUTS (outf, ") (Z)");
4b7f6baa
CM		 4240 }
4241 else if (sop == 1 && sopcde == 10)
4242 {
4b7f6baa 4243 OUTS (outf, dregs (dst0));
086134ec 4244 OUTS (outf, " = EXTRACT (");
4b7f6baa 4245 OUTS (outf, dregs (src1));
086134ec 4246 OUTS (outf, ", ");
4b7f6baa 4247 OUTS (outf, dregs_lo (src0));
086134ec 4248 OUTS (outf, ") (X)");
4b7f6baa
CM		 4249 }
4250 else if (sop == 2 && sopcde == 10)
4251 {
4b7f6baa 4252 OUTS (outf, dregs (dst0));
086134ec 4253 OUTS (outf, " = DEPOSIT (");
4b7f6baa 4254 OUTS (outf, dregs (src1));
086134ec 4255 OUTS (outf, ", ");
4b7f6baa
CM		 4256 OUTS (outf, dregs (src0));
4257 OUTS (outf, ")");
4b7f6baa
CM		 4258 }
4259 else if (sop == 3 && sopcde == 10)
4260 {
4b7f6baa 4261 OUTS (outf, dregs (dst0));
086134ec 4262 OUTS (outf, " = DEPOSIT (");
4b7f6baa 4263 OUTS (outf, dregs (src1));
086134ec 4264 OUTS (outf, ", ");
4b7f6baa 4265 OUTS (outf, dregs (src0));
086134ec 4266 OUTS (outf, ") (X)");
4b7f6baa
CM		 4267 }
4268 else if (sop == 0 && sopcde == 11)
4269 {
4b7f6baa 4270 OUTS (outf, dregs_lo (dst0));
086134ec 4271 OUTS (outf, " = CC = BXORSHIFT (A0, ");
4b7f6baa
CM		 4272 OUTS (outf, dregs (src0));
4273 OUTS (outf, ")");
4b7f6baa
CM		 4274 }
4275 else if (sop == 1 && sopcde == 11)
4276 {
4b7f6baa 4277 OUTS (outf, dregs_lo (dst0));
086134ec 4278 OUTS (outf, " = CC = BXOR (A0, ");
4b7f6baa
CM		 4279 OUTS (outf, dregs (src0));
4280 OUTS (outf, ")");
4b7f6baa
CM		 4281 }
4282 else if (sop == 0 && sopcde == 12)
086134ec 4283 OUTS (outf, "A0 = BXORSHIFT (A0, A1, CC)");
b7d48530 4284
4b7f6baa
CM		 4285 else if (sop == 1 && sopcde == 12)
4286 {
4b7f6baa 4287 OUTS (outf, dregs_lo (dst0));
086134ec 4288 OUTS (outf, " = CC = BXOR (A0, A1, CC)");
4b7f6baa
CM		 4289 }
4290 else if (sop == 0 && sopcde == 13)
4291 {
4b7f6baa 4292 OUTS (outf, dregs (dst0));
086134ec 4293 OUTS (outf, " = ALIGN8 (");
4b7f6baa 4294 OUTS (outf, dregs (src1));
086134ec 4295 OUTS (outf, ", ");
4b7f6baa
CM		 4296 OUTS (outf, dregs (src0));
4297 OUTS (outf, ")");
4b7f6baa
CM		 4298 }
4299 else if (sop == 1 && sopcde == 13)
4300 {
4b7f6baa 4301 OUTS (outf, dregs (dst0));
086134ec 4302 OUTS (outf, " = ALIGN16 (");
4b7f6baa 4303 OUTS (outf, dregs (src1));
086134ec 4304 OUTS (outf, ", ");
4b7f6baa
CM		 4305 OUTS (outf, dregs (src0));
4306 OUTS (outf, ")");
4b7f6baa
CM		 4307 }
4308 else if (sop == 2 && sopcde == 13)
4309 {
4b7f6baa 4310 OUTS (outf, dregs (dst0));
086134ec 4311 OUTS (outf, " = ALIGN24 (");
4b7f6baa 4312 OUTS (outf, dregs (src1));
086134ec 4313 OUTS (outf, ", ");
4b7f6baa
CM		 4314 OUTS (outf, dregs (src0));
4315 OUTS (outf, ")");
4b7f6baa
CM		 4316 }
4317 else
b7d48530
NC		 4318 return 0;
4319
4320 return 4;
4b7f6baa
CM		 4321}
4322
4323static int
4324decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4325{
b7d48530
NC		 4326 /* dsp32shiftimm
4327 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4328 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
4329 |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
4330 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4331 int src1 = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask);
4332 int sop = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
4333 int bit8 = ((iw1 >> 8) & 0x1);
4334 int immag = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4b7f6baa 4335 int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
b7d48530
NC		 4336 int dst0 = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);
4337 int sopcde = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
4338 int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
4b7f6baa 4339
331f1cbe 4340 if (sop == 0 && sopcde == 0)
4b7f6baa 4341 {
331f1cbe
BS		 4342 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4343 OUTS (outf, " = ");
4344 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4345 OUTS (outf, " >>> ");
4b7f6baa 4346 OUTS (outf, uimm4 (newimmag));
4b7f6baa 4347 }
331f1cbe 4348 else if (sop == 1 && sopcde == 0 && bit8 == 0)
4b7f6baa 4349 {
331f1cbe
BS		 4350 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4351 OUTS (outf, " = ");
4352 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4353 OUTS (outf, " << ");
4b7f6baa 4354 OUTS (outf, uimm4 (immag));
331f1cbe 4355 OUTS (outf, " (S)");
4b7f6baa 4356 }
331f1cbe 4357 else if (sop == 1 && sopcde == 0 && bit8 == 1)
4b7f6baa 4358 {
331f1cbe
BS		 4359 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4360 OUTS (outf, " = ");
4361 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4362 OUTS (outf, " >>> ");
4b7f6baa 4363 OUTS (outf, uimm4 (newimmag));
331f1cbe 4364 OUTS (outf, " (S)");
4b7f6baa 4365 }
331f1cbe 4366 else if (sop == 2 && sopcde == 0 && bit8 == 0)
4b7f6baa 4367 {
331f1cbe
BS		 4368 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4369 OUTS (outf, " = ");
4370 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4371 OUTS (outf, " << ");
4b7f6baa 4372 OUTS (outf, uimm4 (immag));
4b7f6baa 4373 }
331f1cbe 4374 else if (sop == 2 && sopcde == 0 && bit8 == 1)
4b7f6baa 4375 {
331f1cbe
BS		 4376 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4377 OUTS (outf, " = ");
4378 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4379 OUTS (outf, " >> ");
4b7f6baa 4380 OUTS (outf, uimm4 (newimmag));
4b7f6baa 4381 }
4b7f6baa
CM		 4382 else if (sop == 2 && sopcde == 3 && HLs == 1)
4383 {
086134ec 4384 OUTS (outf, "A1 = ROT A1 BY ");
4b7f6baa 4385 OUTS (outf, imm6 (immag));
4b7f6baa
CM		 4386 }
4387 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0)
4388 {
086134ec 4389 OUTS (outf, "A0 = A0 << ");
4b7f6baa 4390 OUTS (outf, uimm5 (immag));
4b7f6baa
CM		 4391 }
4392 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1)
4393 {
086134ec 4394 OUTS (outf, "A0 = A0 >>> ");
4b7f6baa 4395 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4396 }
4397 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0)
4398 {
086134ec 4399 OUTS (outf, "A1 = A1 << ");
4b7f6baa 4400 OUTS (outf, uimm5 (immag));
4b7f6baa
CM		 4401 }
4402 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1)
4403 {
086134ec 4404 OUTS (outf, "A1 = A1 >>> ");
4b7f6baa 4405 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4406 }
4407 else if (sop == 1 && sopcde == 3 && HLs == 0)
4408 {
086134ec 4409 OUTS (outf, "A0 = A0 >> ");
4b7f6baa 4410 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4411 }
4412 else if (sop == 1 && sopcde == 3 && HLs == 1)
4413 {
086134ec 4414 OUTS (outf, "A1 = A1 >> ");
4b7f6baa 4415 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4416 }
4417 else if (sop == 2 && sopcde == 3 && HLs == 0)
4418 {
086134ec 4419 OUTS (outf, "A0 = ROT A0 BY ");
4b7f6baa 4420 OUTS (outf, imm6 (immag));
4b7f6baa
CM		 4421 }
4422 else if (sop == 1 && sopcde == 1 && bit8 == 0)
4423 {
4b7f6baa 4424 OUTS (outf, dregs (dst0));
086134ec 4425 OUTS (outf, " = ");
4b7f6baa 4426 OUTS (outf, dregs (src1));
086134ec 4427 OUTS (outf, " << ");
4b7f6baa
CM		 4428 OUTS (outf, uimm5 (immag));
4429 OUTS (outf, " (V, S)");
4b7f6baa
CM		 4430 }
4431 else if (sop == 1 && sopcde == 1 && bit8 == 1)
4432 {
4b7f6baa 4433 OUTS (outf, dregs (dst0));
086134ec 4434 OUTS (outf, " = ");
4b7f6baa 4435 OUTS (outf, dregs (src1));
086134ec 4436 OUTS (outf, " >>> ");
4b7f6baa 4437 OUTS (outf, imm5 (-immag));
0b7691fd 4438 OUTS (outf, " (V, S)");
4b7f6baa
CM		 4439 }
4440 else if (sop == 2 && sopcde == 1 && bit8 == 1)
4441 {
4b7f6baa 4442 OUTS (outf, dregs (dst0));
086134ec 4443 OUTS (outf, " = ");
4b7f6baa
CM		 4444 OUTS (outf, dregs (src1));
4445 OUTS (outf, " >> ");
4446 OUTS (outf, uimm5 (newimmag));
4447 OUTS (outf, " (V)");
4b7f6baa
CM		 4448 }
4449 else if (sop == 2 && sopcde == 1 && bit8 == 0)
4450 {
4b7f6baa 4451 OUTS (outf, dregs (dst0));
086134ec 4452 OUTS (outf, " = ");
4b7f6baa 4453 OUTS (outf, dregs (src1));
086134ec 4454 OUTS (outf, " << ");
4b7f6baa
CM		 4455 OUTS (outf, imm5 (immag));
4456 OUTS (outf, " (V)");
4b7f6baa
CM		 4457 }
4458 else if (sop == 0 && sopcde == 1)
4459 {
4b7f6baa 4460 OUTS (outf, dregs (dst0));
086134ec 4461 OUTS (outf, " = ");
4b7f6baa 4462 OUTS (outf, dregs (src1));
086134ec 4463 OUTS (outf, " >>> ");
4b7f6baa
CM		 4464 OUTS (outf, uimm5 (newimmag));
4465 OUTS (outf, " (V)");
4b7f6baa
CM		 4466 }
4467 else if (sop == 1 && sopcde == 2)
4468 {
4b7f6baa 4469 OUTS (outf, dregs (dst0));
086134ec 4470 OUTS (outf, " = ");
4b7f6baa 4471 OUTS (outf, dregs (src1));
086134ec 4472 OUTS (outf, " << ");
4b7f6baa 4473 OUTS (outf, uimm5 (immag));
086134ec 4474 OUTS (outf, " (S)");
4b7f6baa
CM		 4475 }
4476 else if (sop == 2 && sopcde == 2 && bit8 == 1)
4477 {
4b7f6baa 4478 OUTS (outf, dregs (dst0));
086134ec 4479 OUTS (outf, " = ");
4b7f6baa 4480 OUTS (outf, dregs (src1));
086134ec 4481 OUTS (outf, " >> ");
4b7f6baa 4482 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4483 }
4484 else if (sop == 2 && sopcde == 2 && bit8 == 0)
4485 {
4b7f6baa 4486 OUTS (outf, dregs (dst0));
086134ec 4487 OUTS (outf, " = ");
4b7f6baa 4488 OUTS (outf, dregs (src1));
086134ec 4489 OUTS (outf, " << ");
4b7f6baa 4490 OUTS (outf, uimm5 (immag));
4b7f6baa
CM		 4491 }
4492 else if (sop == 3 && sopcde == 2)
4493 {
4b7f6baa 4494 OUTS (outf, dregs (dst0));
086134ec 4495 OUTS (outf, " = ROT ");
4b7f6baa
CM		 4496 OUTS (outf, dregs (src1));
4497 OUTS (outf, " BY ");
4498 OUTS (outf, imm6 (immag));
4b7f6baa
CM		 4499 }
4500 else if (sop == 0 && sopcde == 2)
4501 {
4b7f6baa 4502 OUTS (outf, dregs (dst0));
086134ec 4503 OUTS (outf, " = ");
4b7f6baa 4504 OUTS (outf, dregs (src1));
086134ec 4505 OUTS (outf, " >>> ");
4b7f6baa 4506 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4507 }
4508 else
b7d48530
NC		 4509 return 0;
4510
4511 return 4;
4b7f6baa
CM		 4512}
4513
4514static int
4515decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf)
4516{
b7d48530
NC		 4517 /* pseudoDEBUG
4518 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4519 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
4520 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 4521 int fn = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
4522 int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask);
4523 int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
4524
219b747a
MF		 4525 if (parallel)
4526 return 0;
4527
4b7f6baa 4528 if (reg == 0 && fn == 3)
b7d48530
NC		 4529 OUTS (outf, "DBG A0");
4530
4b7f6baa 4531 else if (reg == 1 && fn == 3)
b7d48530
NC		 4532 OUTS (outf, "DBG A1");
4533
4b7f6baa 4534 else if (reg == 3 && fn == 3)
b7d48530
NC		 4535 OUTS (outf, "ABORT");
4536
4b7f6baa 4537 else if (reg == 4 && fn == 3)
b7d48530
NC		 4538 OUTS (outf, "HLT");
4539
4b7f6baa 4540 else if (reg == 5 && fn == 3)
b7d48530
NC		 4541 OUTS (outf, "DBGHALT");
4542
4b7f6baa
CM		 4543 else if (reg == 6 && fn == 3)
4544 {
086134ec 4545 OUTS (outf, "DBGCMPLX (");
4b7f6baa
CM		 4546 OUTS (outf, dregs (grp));
4547 OUTS (outf, ")");
4b7f6baa
CM		 4548 }
4549 else if (reg == 7 && fn == 3)
b7d48530
NC		 4550 OUTS (outf, "DBG");
4551
4b7f6baa
CM		 4552 else if (grp == 0 && fn == 2)
4553 {
73a63ccf 4554 OUTS (outf, "OUTC ");
4b7f6baa 4555 OUTS (outf, dregs (reg));
4b7f6baa
CM		 4556 }
4557 else if (fn == 0)
4558 {
a01eda85 4559 OUTS (outf, "DBG ");
4b7f6baa 4560 OUTS (outf, allregs (reg, grp));
4b7f6baa
CM		 4561 }
4562 else if (fn == 1)
4563 {
9805c0a5 4564 OUTS (outf, "PRNT ");
4b7f6baa 4565 OUTS (outf, allregs (reg, grp));
4b7f6baa
CM		 4566 }
4567 else
b7d48530
NC		 4568 return 0;
4569
4570 return 2;
4b7f6baa
CM		 4571}
4572
73a63ccf
MF		 4573static int
4574decode_pseudoOChar_0 (TIword iw0, disassemble_info *outf)
4575{
4576 /* psedoOChar
4577 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4578 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
4579 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4580 int ch = ((iw0 >> PseudoChr_ch_bits) & PseudoChr_ch_mask);
4581
219b747a
MF		 4582 if (parallel)
4583 return 0;
4584
73a63ccf
MF		 4585 OUTS (outf, "OUTC ");
4586 OUTS (outf, uimm8 (ch));
4587
4588 return 2;
4589}
4590
4b7f6baa
CM		 4591static int
4592decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4593{
b7d48530
NC		 4594 /* pseudodbg_assert
4595 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
66a6900a 4596 | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
b7d48530
NC		 4597 |.expected......................................................|
4598 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa 4599 int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
b7d48530 4600 int dbgop = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
66a6900a 4601 int grp = ((iw0 >> (PseudoDbg_Assert_grp_bits - 16)) & PseudoDbg_Assert_grp_mask);
b7d48530 4602 int regtest = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
4b7f6baa 4603
219b747a
MF		 4604 if (parallel)
4605 return 0;
4606
4b7f6baa
CM		 4607 if (dbgop == 0)
4608 {
086134ec 4609 OUTS (outf, "DBGA (");
66a6900a 4610 OUTS (outf, regs_lo (regtest, grp));
086134ec 4611 OUTS (outf, ", ");
4b7f6baa
CM		 4612 OUTS (outf, uimm16 (expected));
4613 OUTS (outf, ")");
4b7f6baa
CM		 4614 }
4615 else if (dbgop == 1)
4616 {
086134ec 4617 OUTS (outf, "DBGA (");
66a6900a 4618 OUTS (outf, regs_hi (regtest, grp));
086134ec 4619 OUTS (outf, ", ");
4b7f6baa
CM		 4620 OUTS (outf, uimm16 (expected));
4621 OUTS (outf, ")");
4b7f6baa
CM		 4622 }
4623 else if (dbgop == 2)
4624 {
086134ec 4625 OUTS (outf, "DBGAL (");
66a6900a 4626 OUTS (outf, allregs (regtest, grp));
086134ec 4627 OUTS (outf, ", ");
4b7f6baa
CM		 4628 OUTS (outf, uimm16 (expected));
4629 OUTS (outf, ")");
4b7f6baa
CM		 4630 }
4631 else if (dbgop == 3)
4632 {
086134ec 4633 OUTS (outf, "DBGAH (");
66a6900a 4634 OUTS (outf, allregs (regtest, grp));
086134ec 4635 OUTS (outf, ", ");
4b7f6baa
CM		 4636 OUTS (outf, uimm16 (expected));
4637 OUTS (outf, ")");
4b7f6baa
CM		 4638 }
4639 else
b7d48530
NC		 4640 return 0;
4641 return 4;
4b7f6baa
CM		 4642}
4643
ad15c38e 4644static int
4b7f6baa
CM		 4645_print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4646{
4b7f6baa
CM		 4647 bfd_byte buf[4];
4648 TIword iw0;
4649 TIword iw1;
4650 int status;
b7d48530
NC		 4651 int rv = 0;
4652
4b7f6baa 4653 status = (*outf->read_memory_func) (pc & ~0x1, buf, 2, outf);
c7e2358a
AM		 4654 /* FIXME */
4655 (void) status;
4b7f6baa 4656 status = (*outf->read_memory_func) ((pc + 2) & ~0x1, buf + 2, 2, outf);
c7e2358a
AM		 4657 /* FIXME */
4658 (void) status;
4b7f6baa
CM		 4659
4660 iw0 = bfd_getl16 (buf);
4661 iw1 = bfd_getl16 (buf + 2);
4662
4663 if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800)
4664 {
219b747a
MF		 4665 if (parallel)
4666 {
602427c4
MF		 4667 OUTS (outf, "ILLEGAL");
4668 return 0;
219b747a 4669 }
086134ec 4670 OUTS (outf, "MNOP");
4b7f6baa
CM		 4671 return 4;
4672 }
4673 else if ((iw0 & 0xff00) == 0x0000)
b7d48530 4674 rv = decode_ProgCtrl_0 (iw0, outf);
4b7f6baa 4675 else if ((iw0 & 0xffc0) == 0x0240)
b7d48530 4676 rv = decode_CaCTRL_0 (iw0, outf);
4b7f6baa 4677 else if ((iw0 & 0xff80) == 0x0100)
b7d48530 4678 rv = decode_PushPopReg_0 (iw0, outf);
4b7f6baa 4679 else if ((iw0 & 0xfe00) == 0x0400)
b7d48530 4680 rv = decode_PushPopMultiple_0 (iw0, outf);
4b7f6baa 4681 else if ((iw0 & 0xfe00) == 0x0600)
b7d48530 4682 rv = decode_ccMV_0 (iw0, outf);
4b7f6baa 4683 else if ((iw0 & 0xf800) == 0x0800)
b7d48530 4684 rv = decode_CCflag_0 (iw0, outf);
4b7f6baa 4685 else if ((iw0 & 0xffe0) == 0x0200)
b7d48530 4686 rv = decode_CC2dreg_0 (iw0, outf);
4b7f6baa 4687 else if ((iw0 & 0xff00) == 0x0300)
b7d48530 4688 rv = decode_CC2stat_0 (iw0, outf);
4b7f6baa 4689 else if ((iw0 & 0xf000) == 0x1000)
b7d48530 4690 rv = decode_BRCC_0 (iw0, pc, outf);
4b7f6baa 4691 else if ((iw0 & 0xf000) == 0x2000)
b7d48530 4692 rv = decode_UJUMP_0 (iw0, pc, outf);
4b7f6baa 4693 else if ((iw0 & 0xf000) == 0x3000)
b7d48530 4694 rv = decode_REGMV_0 (iw0, outf);
4b7f6baa 4695 else if ((iw0 & 0xfc00) == 0x4000)
b7d48530 4696 rv = decode_ALU2op_0 (iw0, outf);
4b7f6baa 4697 else if ((iw0 & 0xfe00) == 0x4400)
b7d48530 4698 rv = decode_PTR2op_0 (iw0, outf);
4b7f6baa 4699 else if ((iw0 & 0xf800) == 0x4800)
b7d48530 4700 rv = decode_LOGI2op_0 (iw0, outf);
4b7f6baa 4701 else if ((iw0 & 0xf000) == 0x5000)
b7d48530 4702 rv = decode_COMP3op_0 (iw0, outf);
4b7f6baa 4703 else if ((iw0 & 0xf800) == 0x6000)
b7d48530 4704 rv = decode_COMPI2opD_0 (iw0, outf);
4b7f6baa 4705 else if ((iw0 & 0xf800) == 0x6800)
b7d48530 4706 rv = decode_COMPI2opP_0 (iw0, outf);
4b7f6baa 4707 else if ((iw0 & 0xf000) == 0x8000)
b7d48530 4708 rv = decode_LDSTpmod_0 (iw0, outf);
4b7f6baa 4709 else if ((iw0 & 0xff60) == 0x9e60)
b7d48530 4710 rv = decode_dagMODim_0 (iw0, outf);
4b7f6baa 4711 else if ((iw0 & 0xfff0) == 0x9f60)
b7d48530 4712 rv = decode_dagMODik_0 (iw0, outf);
4b7f6baa 4713 else if ((iw0 & 0xfc00) == 0x9c00)
b7d48530 4714 rv = decode_dspLDST_0 (iw0, outf);
4b7f6baa 4715 else if ((iw0 & 0xf000) == 0x9000)
b7d48530 4716 rv = decode_LDST_0 (iw0, outf);
4b7f6baa 4717 else if ((iw0 & 0xfc00) == 0xb800)
b7d48530 4718 rv = decode_LDSTiiFP_0 (iw0, outf);
4b7f6baa 4719 else if ((iw0 & 0xe000) == 0xA000)
b7d48530 4720 rv = decode_LDSTii_0 (iw0, outf);
4b7f6baa 4721 else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000)
b7d48530 4722 rv = decode_LoopSetup_0 (iw0, iw1, pc, outf);
4b7f6baa 4723 else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000)
b7d48530 4724 rv = decode_LDIMMhalf_0 (iw0, iw1, outf);
4b7f6baa 4725 else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000)
b7d48530 4726 rv = decode_CALLa_0 (iw0, iw1, pc, outf);
4b7f6baa 4727 else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000)
b7d48530 4728 rv = decode_LDSTidxI_0 (iw0, iw1, outf);
4b7f6baa 4729 else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000)
b7d48530 4730 rv = decode_linkage_0 (iw0, iw1, outf);
4b7f6baa 4731 else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000)
b7d48530 4732 rv = decode_dsp32mac_0 (iw0, iw1, outf);
4b7f6baa 4733 else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000)
b7d48530 4734 rv = decode_dsp32mult_0 (iw0, iw1, outf);
4b7f6baa 4735 else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000)
b7d48530 4736 rv = decode_dsp32alu_0 (iw0, iw1, outf);
4b7f6baa 4737 else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000)
b7d48530 4738 rv = decode_dsp32shift_0 (iw0, iw1, outf);
4b7f6baa 4739 else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000)
b7d48530 4740 rv = decode_dsp32shiftimm_0 (iw0, iw1, outf);
4b7f6baa 4741 else if ((iw0 & 0xff00) == 0xf800)
b7d48530 4742 rv = decode_pseudoDEBUG_0 (iw0, outf);
4b7f6baa 4743 else if ((iw0 & 0xFF00) == 0xF900)
73a63ccf 4744 rv = decode_pseudoOChar_0 (iw0, outf);
66a6900a 4745 else if ((iw0 & 0xFF00) == 0xf000 && (iw1 & 0x0000) == 0x0000)
b7d48530 4746 rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
4b7f6baa 4747
219b747a
MF		 4748 if (rv == 0)
4749 OUTS (outf, "ILLEGAL");
4750
b7d48530 4751 return rv;
4b7f6baa
CM		 4752}
4753
4b7f6baa
CM		 4754int
4755print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4756{
471e4e36
JZ		 4757 bfd_byte buf[2];
4758 unsigned short iw0;
4759 int status;
4b7f6baa 4760 int count = 0;
471e4e36
JZ		 4761
4762 status = (*outf->read_memory_func) (pc & ~0x01, buf, 2, outf);
c7e2358a
AM		 4763 /* FIXME */
4764 (void) status;
471e4e36 4765 iw0 = bfd_getl16 (buf);
4b7f6baa
CM		 4766
4767 count += _print_insn_bfin (pc, outf);
471e4e36 4768
4b7f6baa 4769 /* Proper display of multiple issue instructions. */
471e4e36 4770
219b747a 4771 if (count == 4 && (iw0 & 0xc000) == 0xc000 && (iw0 & BIT_MULTI_INS)
b7d48530 4772 && ((iw0 & 0xe800) != 0xe800 /* Not Linkage. */ ))
4b7f6baa 4773 {
219b747a
MF		 4774 int legal = 1;
4775 int len;
4776
086134ec 4777 parallel = 1;
f5caf9f4 4778 OUTS (outf, " || ");
219b747a 4779 len = _print_insn_bfin (pc + 4, outf);
f5caf9f4 4780 OUTS (outf, " || ");
219b747a 4781 if (len != 2)
602427c4 4782 legal = 0;
219b747a
MF		 4783 len = _print_insn_bfin (pc + 6, outf);
4784 if (len != 2)
4785 legal = 0;
4786
4787 if (legal)
4788 count = 8;
4789 else
4790 {
f5caf9f4 4791 OUTS (outf, ";\t\t/* ILLEGAL PARALLEL INSTRUCTION */");
219b747a
MF		 4792 comment = 1;
4793 count = 0;
4794 }
086134ec 4795 parallel = 0;
4b7f6baa 4796 }
219b747a 4797
086134ec 4798 if (!comment)
f5caf9f4 4799 OUTS (outf, ";");
086134ec 4800
219b747a
MF		 4801 if (count == 0)
4802 return 2;
4803
086134ec
BS		 4804 comment = 0;
4805
4b7f6baa
CM		 4806 return count;
4807}
GDB Binutils - Deliverables
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