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opcodes: blackfin: avoid duplicate memory reads
[deliverable/binutils-gdb.git] / opcodes / bfin-dis.c
CommitLineData
4b7f6baa 1/* Disassemble ADI Blackfin Instructions.
4b95cf5c 2 Copyright (C) 2005-2014 Free Software Foundation, Inc.
4b7f6baa 3
9b201bb5
NC		 4 This file is part of libopcodes.
5
6 This library is free software; you can redistribute it and/or modify
4b7f6baa 7 it under the terms of the GNU General Public License as published by
9b201bb5
NC		 8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
4b7f6baa 10
9b201bb5
NC		 11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
4b7f6baa
CM		 15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
5eb3690e 21#include "sysdep.h"
4b7f6baa 22#include <stdio.h>
4b7f6baa
CM		 23
24#include "opcode/bfin.h"
25
4b7f6baa
CM		 26#ifndef PRINTF
27#define PRINTF printf
28#endif
29
30#ifndef EXIT
31#define EXIT exit
32#endif
33
34typedef long TIword;
35
b7d48530
NC		 36#define HOST_LONG_WORD_SIZE (sizeof (long) * 8)
37#define XFIELD(w,p,s) (((w) & ((1 << (s)) - 1) << (p)) >> (p))
38#define SIGNEXTEND(v, n) ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
39#define MASKBITS(val, bits) (val & ((1 << bits) - 1))
4b7f6baa
CM		 40
41#include "dis-asm.h"
b7d48530 42
b21c9cb4
BS		 43typedef unsigned int bu32;
44
703ec4e8
MF		 45struct private
46{
a4e600b2 47 TIword iw0;
703ec4e8
MF		 48 int comment, parallel;
49};
528c6277 50
4b7f6baa
CM		 51typedef enum
52{
53 c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
086134ec
BS		 54 c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_imm5d, c_uimm5, c_imm6,
55 c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10,
56 c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4,
57 c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e,
4b7f6baa
CM		 58} const_forms_t;
59
528c6277 60static const struct
4b7f6baa 61{
528c6277
MF		 62 const char *name;
63 const int nbits;
64 const char reloc;
65 const char issigned;
66 const char pcrel;
67 const char scale;
68 const char offset;
69 const char negative;
70 const char positive;
71 const char decimal;
72 const char leading;
73 const char exact;
4b7f6baa
CM		 74} constant_formats[] =
75{
086134ec
BS		 76 { "0", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
77 { "1", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
78 { "4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
79 { "2", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
80 { "uimm2", 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
81 { "uimm3", 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
82 { "imm3", 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
83 { "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
84 { "imm4", 4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
85 { "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0},
86 { "uimm4s4d", 4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0},
87 { "uimm4", 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
88 { "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0},
89 { "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0},
90 { "imm5", 5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
91 { "imm5d", 5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0},
92 { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
93 { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
94 { "imm7", 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
95 { "imm7d", 7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
96 { "imm8", 8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
97 { "uimm8", 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
98 { "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
99 { "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
100 { "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0},
101 { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
102 { "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
103 { "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
104 { "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0},
105 { "luimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
106 { "imm16", 16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
107 { "imm16d", 16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
108 { "huimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
109 { "rimm16", 16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
110 { "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0},
111 { "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
112 { "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0},
113 { "uimm16", 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
114 { "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
115 { "uimm32", 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
116 { "imm32", 32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
117 { "huimm32", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
118 { "huimm32e", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1},
4b7f6baa
CM		 119};
120
528c6277
MF		 121static const char *
122fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info *outf)
4b7f6baa
CM		 123{
124 static char buf[60];
125
126 if (constant_formats[cf].reloc)
127 {
128 bfd_vma ea = (((constant_formats[cf].pcrel ? SIGNEXTEND (x, constant_formats[cf].nbits)
129 : x) + constant_formats[cf].offset) << constant_formats[cf].scale);
130 if (constant_formats[cf].pcrel)
131 ea += pc;
132
602427c4
MF		 133 /* truncate to 32-bits for proper symbol lookup/matching */
134 ea = (bu32)ea;
7a360e83 135
602427c4
MF		 136 if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact)
137 {
086134ec
BS		 138 outf->print_address_func (ea, outf);
139 return "";
602427c4
MF		 140 }
141 else
142 {
0af1713e 143 sprintf (buf, "%lx", (unsigned long) x);
086134ec 144 return buf;
602427c4 145 }
4b7f6baa
CM		 146 }
147
148 /* Negative constants have an implied sign bit. */
149 if (constant_formats[cf].negative)
150 {
151 int nb = constant_formats[cf].nbits + 1;
b7d48530 152
4b7f6baa
CM		 153 x = x | (1 << constant_formats[cf].nbits);
154 x = SIGNEXTEND (x, nb);
155 }
156 else
157 x = constant_formats[cf].issigned ? SIGNEXTEND (x, constant_formats[cf].nbits) : x;
158
159 if (constant_formats[cf].offset)
160 x += constant_formats[cf].offset;
161
162 if (constant_formats[cf].scale)
163 x <<= constant_formats[cf].scale;
164
086134ec 165 if (constant_formats[cf].decimal)
5de10af0 166 sprintf (buf, "%*li", constant_formats[cf].leading, x);
4b7f6baa 167 else
086134ec
BS		 168 {
169 if (constant_formats[cf].issigned && x < 0)
170 sprintf (buf, "-0x%x", abs (x));
171 else
0af1713e 172 sprintf (buf, "0x%lx", (unsigned long) x);
086134ec 173 }
4b7f6baa
CM		 174
175 return buf;
176}
177
b21c9cb4
BS		 178static bu32
179fmtconst_val (const_forms_t cf, unsigned int x, unsigned int pc)
180{
181 if (0 && constant_formats[cf].reloc)
182 {
183 bu32 ea = (((constant_formats[cf].pcrel
086134ec
BS		 184 ? SIGNEXTEND (x, constant_formats[cf].nbits)
185 : x) + constant_formats[cf].offset)
186 << constant_formats[cf].scale);
b21c9cb4 187 if (constant_formats[cf].pcrel)
086134ec 188 ea += pc;
b21c9cb4
BS		 189
190 return ea;
191 }
192
193 /* Negative constants have an implied sign bit. */
194 if (constant_formats[cf].negative)
195 {
196 int nb = constant_formats[cf].nbits + 1;
197 x = x | (1 << constant_formats[cf].nbits);
198 x = SIGNEXTEND (x, nb);
199 }
200 else if (constant_formats[cf].issigned)
201 x = SIGNEXTEND (x, constant_formats[cf].nbits);
202
203 x += constant_formats[cf].offset;
204 x <<= constant_formats[cf].scale;
205
206 return x;
207}
208
4b7f6baa
CM		 209enum machine_registers
210{
211 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
212 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
213 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
214 REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3,
215 REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w,
216 REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1,
217 REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1,
218 REG_L2, REG_L3,
219 REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S,
220 REG_AQ, REG_V, REG_VS,
221 REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0,
43a6aa65 222 REG_LC1, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1,
4b7f6baa
CM		 223 REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN,
224 REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6,
225 REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
226 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
227 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
228 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
229 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
230 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
22215ae0 231 REG_AC0_COPY, REG_V_COPY, REG_RND_MOD,
4b7f6baa
CM		 232 REG_LASTREG,
233};
234
235enum reg_class
236{
237 rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext,
238 rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs,
239 rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2,
240 rc_sysregs3, rc_allregs,
241 LIM_REG_CLASSES
242};
243
69b8ea4a 244static const char * const reg_names[] =
4b7f6baa
CM		 245{
246 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
247 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
248 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
249 "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
086134ec 250 "P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W",
4b7f6baa
CM		 251 "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
252 "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
253 "L2", "L3",
254 "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
255 "AQ", "V", "VS",
256 "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0",
43a6aa65 257 "LC1", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
4b7f6baa
CM		 258 "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN",
259 "RETE", "EMUDAT",
260 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",
261 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L",
262 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H",
263 "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L",
264 "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L",
265 "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H",
266 "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H",
22215ae0 267 "AC0_COPY", "V_COPY", "RND_MOD",
4b7f6baa
CM		 268 "LASTREG",
269 0
270};
271
272#define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......")
273
274/* RL(0..7). */
69b8ea4a 275static const enum machine_registers decode_dregs_lo[] =
4b7f6baa
CM		 276{
277 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
278};
279
b7d48530 280#define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
4b7f6baa
CM		 281
282/* RH(0..7). */
69b8ea4a 283static const enum machine_registers decode_dregs_hi[] =
4b7f6baa
CM		 284{
285 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
286};
287
b7d48530 288#define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
4b7f6baa
CM		 289
290/* R(0..7). */
69b8ea4a 291static const enum machine_registers decode_dregs[] =
4b7f6baa
CM		 292{
293 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
294};
295
b7d48530 296#define dregs(x) REGNAME (decode_dregs[(x) & 7])
4b7f6baa
CM		 297
298/* R BYTE(0..7). */
69b8ea4a 299static const enum machine_registers decode_dregs_byte[] =
4b7f6baa
CM		 300{
301 REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
302};
303
b7d48530 304#define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
4b7f6baa
CM		 305
306/* P(0..5) SP FP. */
69b8ea4a 307static const enum machine_registers decode_pregs[] =
4b7f6baa
CM		 308{
309 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
310};
311
b7d48530
NC		 312#define pregs(x) REGNAME (decode_pregs[(x) & 7])
313#define spfp(x) REGNAME (decode_spfp[(x) & 1])
602427c4 314#define dregs_hilo(x, i) REGNAME (decode_dregs_hilo[((i) << 3) | (x)])
b7d48530
NC		 315#define accum_ext(x) REGNAME (decode_accum_ext[(x) & 1])
316#define accum_word(x) REGNAME (decode_accum_word[(x) & 1])
317#define accum(x) REGNAME (decode_accum[(x) & 1])
4b7f6baa
CM		 318
319/* I(0..3). */
69b8ea4a 320static const enum machine_registers decode_iregs[] =
4b7f6baa
CM		 321{
322 REG_I0, REG_I1, REG_I2, REG_I3,
323};
324
b7d48530 325#define iregs(x) REGNAME (decode_iregs[(x) & 3])
4b7f6baa
CM		 326
327/* M(0..3). */
69b8ea4a 328static const enum machine_registers decode_mregs[] =
4b7f6baa
CM		 329{
330 REG_M0, REG_M1, REG_M2, REG_M3,
331};
332
b7d48530
NC		 333#define mregs(x) REGNAME (decode_mregs[(x) & 3])
334#define bregs(x) REGNAME (decode_bregs[(x) & 3])
335#define lregs(x) REGNAME (decode_lregs[(x) & 3])
4b7f6baa
CM		 336
337/* dregs pregs. */
69b8ea4a 338static const enum machine_registers decode_dpregs[] =
4b7f6baa
CM		 339{
340 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
341 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
342};
343
b7d48530 344#define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
4b7f6baa
CM		 345
346/* [dregs pregs]. */
69b8ea4a 347static const enum machine_registers decode_gregs[] =
4b7f6baa
CM		 348{
349 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
350 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
351};
352
602427c4 353#define gregs(x, i) REGNAME (decode_gregs[((i) << 3) | (x)])
4b7f6baa
CM		 354
355/* [dregs pregs (iregs mregs) (bregs lregs)]. */
69b8ea4a 356static const enum machine_registers decode_regs[] =
4b7f6baa
CM		 357{
358 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
359 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
360 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
361 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
362};
363
602427c4 364#define regs(x, i) REGNAME (decode_regs[((i) << 3) | (x)])
4b7f6baa
CM		 365
366/* [dregs pregs (iregs mregs) (bregs lregs) Low Half]. */
69b8ea4a 367static const enum machine_registers decode_regs_lo[] =
4b7f6baa
CM		 368{
369 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
370 REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
371 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
372 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
373};
374
602427c4
MF		 375#define regs_lo(x, i) REGNAME (decode_regs_lo[((i) << 3) | (x)])
376
4b7f6baa 377/* [dregs pregs (iregs mregs) (bregs lregs) High Half]. */
69b8ea4a 378static const enum machine_registers decode_regs_hi[] =
4b7f6baa
CM		 379{
380 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
381 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
1985c81c 382 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
4b7f6baa
CM		 383 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
384};
385
602427c4 386#define regs_hi(x, i) REGNAME (decode_regs_hi[((i) << 3) | (x)])
4b7f6baa 387
69b8ea4a 388static const enum machine_registers decode_statbits[] =
4b7f6baa 389{
22215ae0
MF		 390 REG_AZ, REG_AN, REG_AC0_COPY, REG_V_COPY,
391 REG_LASTREG, REG_LASTREG, REG_AQ, REG_LASTREG,
392 REG_RND_MOD, REG_LASTREG, REG_LASTREG, REG_LASTREG,
393 REG_AC0, REG_AC1, REG_LASTREG, REG_LASTREG,
394 REG_AV0, REG_AV0S, REG_AV1, REG_AV1S,
395 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
396 REG_V, REG_VS, REG_LASTREG, REG_LASTREG,
397 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
4b7f6baa
CM		 398};
399
ad15c38e 400#define statbits(x) REGNAME (decode_statbits[(x) & 31])
4b7f6baa
CM		 401
402/* LC0 LC1. */
69b8ea4a 403static const enum machine_registers decode_counters[] =
4b7f6baa
CM		 404{
405 REG_LC0, REG_LC1,
406};
407
b7d48530
NC		 408#define counters(x) REGNAME (decode_counters[(x) & 1])
409#define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7])
4b7f6baa
CM		 410
411/* [dregs pregs (iregs mregs) (bregs lregs)
412 dregs2_sysregs1 open sysregs2 sysregs3]. */
69b8ea4a 413static const enum machine_registers decode_allregs[] =
4b7f6baa
CM		 414{
415 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
416 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
417 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
418 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
43a6aa65 419 REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_LASTREG, REG_LASTREG, REG_ASTAT, REG_RETS,
4b7f6baa
CM		 420 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
421 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
c958a8a8
JZ		 422 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,
423 REG_LASTREG,
4b7f6baa
CM		 424};
425
50e2162a
MF		 426#define IS_DREG(g,r) ((g) == 0 && (r) < 8)
427#define IS_PREG(g,r) ((g) == 1 && (r) < 8)
c958a8a8 428#define IS_AREG(g,r) ((g) == 4 && (r) >= 0 && (r) < 4)
50e2162a
MF		 429#define IS_GENREG(g,r) ((((g) == 0 || (g) == 1) && (r) < 8) || IS_AREG (g, r))
430#define IS_DAGREG(g,r) (((g) == 2 || (g) == 3) && (r) < 8)
c958a8a8
JZ		 431#define IS_SYSREG(g,r) \
432 (((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7)
50e2162a
MF		 433#define IS_RESERVEDREG(g,r) \
434 (((r) > 7) || ((g) == 4 && ((r) == 4 || (r) == 5)) || (g) == 5)
435
436#define allreg(r,g) (!IS_RESERVEDREG (g, r))
437#define mostreg(r,g) (!(IS_DREG (g, r) || IS_PREG (g, r) || IS_RESERVEDREG (g, r)))
c958a8a8 438
602427c4 439#define allregs(x, i) REGNAME (decode_allregs[((i) << 3) | (x)])
b7d48530 440#define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf)
086134ec 441#define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf)
b7d48530
NC		 442#define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf)
443#define pcrel8(x) fmtconst (c_pcrel8, x, pc, outf)
444#define pcrel8s4(x) fmtconst (c_pcrel8s4, x, pc, outf)
445#define pcrel10(x) fmtconst (c_pcrel10, x, pc, outf)
446#define pcrel12(x) fmtconst (c_pcrel12, x, pc, outf)
447#define negimm5s4(x) fmtconst (c_negimm5s4, x, 0, outf)
448#define rimm16(x) fmtconst (c_rimm16, x, 0, outf)
449#define huimm16(x) fmtconst (c_huimm16, x, 0, outf)
450#define imm16(x) fmtconst (c_imm16, x, 0, outf)
086134ec 451#define imm16d(x) fmtconst (c_imm16d, x, 0, outf)
b7d48530
NC		 452#define uimm2(x) fmtconst (c_uimm2, x, 0, outf)
453#define uimm3(x) fmtconst (c_uimm3, x, 0, outf)
454#define luimm16(x) fmtconst (c_luimm16, x, 0, outf)
455#define uimm4(x) fmtconst (c_uimm4, x, 0, outf)
456#define uimm5(x) fmtconst (c_uimm5, x, 0, outf)
457#define imm16s2(x) fmtconst (c_imm16s2, x, 0, outf)
458#define uimm8(x) fmtconst (c_uimm8, x, 0, outf)
459#define imm16s4(x) fmtconst (c_imm16s4, x, 0, outf)
460#define uimm4s2(x) fmtconst (c_uimm4s2, x, 0, outf)
461#define uimm4s4(x) fmtconst (c_uimm4s4, x, 0, outf)
086134ec 462#define uimm4s4d(x) fmtconst (c_uimm4s4d, x, 0, outf)
b7d48530
NC		 463#define lppcrel10(x) fmtconst (c_lppcrel10, x, pc, outf)
464#define imm3(x) fmtconst (c_imm3, x, 0, outf)
465#define imm4(x) fmtconst (c_imm4, x, 0, outf)
466#define uimm8s4(x) fmtconst (c_uimm8s4, x, 0, outf)
467#define imm5(x) fmtconst (c_imm5, x, 0, outf)
086134ec 468#define imm5d(x) fmtconst (c_imm5d, x, 0, outf)
b7d48530
NC		 469#define imm6(x) fmtconst (c_imm6, x, 0, outf)
470#define imm7(x) fmtconst (c_imm7, x, 0, outf)
086134ec 471#define imm7d(x) fmtconst (c_imm7d, x, 0, outf)
b7d48530
NC		 472#define imm8(x) fmtconst (c_imm8, x, 0, outf)
473#define pcrel24(x) fmtconst (c_pcrel24, x, pc, outf)
474#define uimm16(x) fmtconst (c_uimm16, x, 0, outf)
b21c9cb4 475#define uimm32(x) fmtconst (c_uimm32, x, 0, outf)
086134ec 476#define imm32(x) fmtconst (c_imm32, x, 0, outf)
b21c9cb4 477#define huimm32(x) fmtconst (c_huimm32, x, 0, outf)
086134ec
BS		 478#define huimm32e(x) fmtconst (c_huimm32e, x, 0, outf)
479#define imm7_val(x) fmtconst_val (c_imm7, x, 0)
b21c9cb4
BS		 480#define imm16_val(x) fmtconst_val (c_uimm16, x, 0)
481#define luimm16_val(x) fmtconst_val (c_luimm16, x, 0)
4b7f6baa
CM		 482
483/* (arch.pm)arch_disassembler_functions. */
4b7f6baa 484#ifndef OUTS
500cccad 485#define OUTS(p, txt) (p)->fprintf_func ((p)->stream, "%s", txt)
4b7f6baa
CM		 486#endif
487
4b7f6baa
CM		 488static void
489amod0 (int s0, int x0, disassemble_info *outf)
490{
b7d48530 491 if (s0 == 1 && x0 == 0)
086134ec 492 OUTS (outf, " (S)");
4b7f6baa 493 else if (s0 == 0 && x0 == 1)
086134ec 494 OUTS (outf, " (CO)");
4b7f6baa 495 else if (s0 == 1 && x0 == 1)
086134ec 496 OUTS (outf, " (SCO)");
4b7f6baa
CM		 497}
498
499static void
500amod1 (int s0, int x0, disassemble_info *outf)
501{
502 if (s0 == 0 && x0 == 0)
086134ec 503 OUTS (outf, " (NS)");
4b7f6baa 504 else if (s0 == 1 && x0 == 0)
086134ec 505 OUTS (outf, " (S)");
4b7f6baa
CM		 506}
507
508static void
509amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf)
510{
b7d48530 511 if (s0 == 1 && x0 == 0 && aop0 == 0)
086134ec 512 OUTS (outf, " (S)");
4b7f6baa 513 else if (s0 == 0 && x0 == 1 && aop0 == 0)
086134ec 514 OUTS (outf, " (CO)");
4b7f6baa 515 else if (s0 == 1 && x0 == 1 && aop0 == 0)
086134ec 516 OUTS (outf, " (SCO)");
4b7f6baa 517 else if (s0 == 0 && x0 == 0 && aop0 == 2)
086134ec 518 OUTS (outf, " (ASR)");
4b7f6baa 519 else if (s0 == 1 && x0 == 0 && aop0 == 2)
086134ec 520 OUTS (outf, " (S, ASR)");
4b7f6baa 521 else if (s0 == 0 && x0 == 1 && aop0 == 2)
086134ec 522 OUTS (outf, " (CO, ASR)");
4b7f6baa 523 else if (s0 == 1 && x0 == 1 && aop0 == 2)
086134ec 524 OUTS (outf, " (SCO, ASR)");
4b7f6baa 525 else if (s0 == 0 && x0 == 0 && aop0 == 3)
086134ec 526 OUTS (outf, " (ASL)");
4b7f6baa 527 else if (s0 == 1 && x0 == 0 && aop0 == 3)
086134ec 528 OUTS (outf, " (S, ASL)");
4b7f6baa 529 else if (s0 == 0 && x0 == 1 && aop0 == 3)
086134ec 530 OUTS (outf, " (CO, ASL)");
4b7f6baa 531 else if (s0 == 1 && x0 == 1 && aop0 == 3)
086134ec 532 OUTS (outf, " (SCO, ASL)");
4b7f6baa
CM		 533}
534
535static void
536searchmod (int r0, disassemble_info *outf)
537{
b7d48530
NC		 538 if (r0 == 0)
539 OUTS (outf, "GT");
540 else if (r0 == 1)
541 OUTS (outf, "GE");
542 else if (r0 == 2)
543 OUTS (outf, "LT");
544 else if (r0 == 3)
545 OUTS (outf, "LE");
4b7f6baa
CM		 546}
547
548static void
549aligndir (int r0, disassemble_info *outf)
550{
b7d48530 551 if (r0 == 1)
086134ec 552 OUTS (outf, " (R)");
4b7f6baa
CM		 553}
554
555static int
602427c4 556decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info *outf)
4b7f6baa 557{
528c6277 558 const char *s0, *s1;
4b7f6baa
CM		 559
560 if (h0)
561 s0 = dregs_hi (src0);
562 else
563 s0 = dregs_lo (src0);
564
565 if (h1)
566 s1 = dregs_hi (src1);
567 else
568 s1 = dregs_lo (src1);
569
570 OUTS (outf, s0);
571 OUTS (outf, " * ");
572 OUTS (outf, s1);
573 return 0;
574}
575
576static int
602427c4 577decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info *outf)
4b7f6baa 578{
528c6277
MF		 579 const char *a;
580 const char *sop = "<unknown op>";
4b7f6baa
CM		 581
582 if (which)
086134ec 583 a = "A1";
4b7f6baa 584 else
086134ec 585 a = "A0";
4b7f6baa
CM		 586
587 if (op == 3)
588 {
589 OUTS (outf, a);
590 return 0;
591 }
592
593 switch (op)
594 {
086134ec
BS		 595 case 0: sop = " = "; break;
596 case 1: sop = " += "; break;
597 case 2: sop = " -= "; break;
b7d48530 598 default: break;
4b7f6baa
CM		 599 }
600
601 OUTS (outf, a);
4b7f6baa 602 OUTS (outf, sop);
4b7f6baa
CM		 603 decode_multfunc (h0, h1, src0, src1, outf);
604
605 return 0;
606}
607
608static void
609decode_optmode (int mod, int MM, disassemble_info *outf)
610{
611 if (mod == 0 && MM == 0)
612 return;
613
614 OUTS (outf, " (");
615
616 if (MM && !mod)
617 {
618 OUTS (outf, "M)");
619 return;
620 }
621
622 if (MM)
623 OUTS (outf, "M, ");
b7d48530 624
4b7f6baa
CM		 625 if (mod == M_S2RND)
626 OUTS (outf, "S2RND");
627 else if (mod == M_T)
628 OUTS (outf, "T");
629 else if (mod == M_W32)
630 OUTS (outf, "W32");
631 else if (mod == M_FU)
632 OUTS (outf, "FU");
633 else if (mod == M_TFU)
634 OUTS (outf, "TFU");
635 else if (mod == M_IS)
636 OUTS (outf, "IS");
637 else if (mod == M_ISS2)
638 OUTS (outf, "ISS2");
639 else if (mod == M_IH)
640 OUTS (outf, "IH");
641 else if (mod == M_IU)
642 OUTS (outf, "IU");
643 else
644 abort ();
645
646 OUTS (outf, ")");
647}
b7d48530 648
e5bc4265 649static struct saved_state
b21c9cb4
BS		 650{
651 bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4];
e5bc4265 652 bu32 ax[2], aw[2];
b21c9cb4 653 bu32 lt[2], lc[2], lb[2];
e5bc4265 654 bu32 rets;
602427c4 655} saved_state;
b21c9cb4
BS		 656
657#define DREG(x) (saved_state.dpregs[x])
602427c4 658#define GREG(x, i) DPREG ((x) | ((i) << 3))
b21c9cb4
BS		 659#define DPREG(x) (saved_state.dpregs[x])
660#define DREG(x) (saved_state.dpregs[x])
602427c4 661#define PREG(x) (saved_state.dpregs[(x) + 8])
b21c9cb4
BS		 662#define SPREG PREG (6)
663#define FPREG PREG (7)
664#define IREG(x) (saved_state.iregs[x])
665#define MREG(x) (saved_state.mregs[x])
666#define BREG(x) (saved_state.bregs[x])
667#define LREG(x) (saved_state.lregs[x])
e5bc4265
MF		 668#define AXREG(x) (saved_state.ax[x])
669#define AWREG(x) (saved_state.aw[x])
670#define LCREG(x) (saved_state.lc[x])
671#define LTREG(x) (saved_state.lt[x])
672#define LBREG(x) (saved_state.lb[x])
b21c9cb4 673#define RETSREG (saved_state.rets)
b21c9cb4
BS		 674
675static bu32 *
676get_allreg (int grp, int reg)
677{
678 int fullreg = (grp << 3) | reg;
679 /* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
680 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
681 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
682 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
683 REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS,
684 , , , , , , , ,
685 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
686 REG_CYCLES2,
687 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE,
688 REG_LASTREG */
689 switch (fullreg >> 2)
690 {
e5bc4265
MF		 691 case 0: case 1: return &DREG (reg);
692 case 2: case 3: return &PREG (reg);
693 case 4: return &IREG (reg & 3);
694 case 5: return &MREG (reg & 3);
695 case 6: return &BREG (reg & 3);
696 case 7: return &LREG (reg & 3);
b21c9cb4
BS		 697 default:
698 switch (fullreg)
086134ec 699 {
e5bc4265
MF		 700 case 32: return &AXREG (0);
701 case 33: return &AWREG (0);
702 case 34: return &AXREG (1);
703 case 35: return &AWREG (1);
704 case 39: return &RETSREG;
705 case 48: return &LCREG (0);
706 case 49: return &LTREG (0);
707 case 50: return &LBREG (0);
708 case 51: return &LCREG (1);
709 case 52: return &LTREG (1);
710 case 53: return &LBREG (1);
086134ec 711 }
b21c9cb4 712 }
e5bc4265 713 abort ();
b21c9cb4
BS		 714}
715
4b7f6baa
CM		 716static int
717decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
718{
703ec4e8 719 struct private *priv = outf->private_data;
b7d48530
NC		 720 /* ProgCtrl
721 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
722 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
723 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 724 int poprnd = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
725 int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
726
727 if (prgfunc == 0 && poprnd == 0)
b7d48530 728 OUTS (outf, "NOP");
703ec4e8 729 else if (priv->parallel)
219b747a 730 return 0;
4b7f6baa 731 else if (prgfunc == 1 && poprnd == 0)
b7d48530 732 OUTS (outf, "RTS");
4b7f6baa 733 else if (prgfunc == 1 && poprnd == 1)
b7d48530 734 OUTS (outf, "RTI");
4b7f6baa 735 else if (prgfunc == 1 && poprnd == 2)
b7d48530 736 OUTS (outf, "RTX");
4b7f6baa 737 else if (prgfunc == 1 && poprnd == 3)
b7d48530 738 OUTS (outf, "RTN");
4b7f6baa 739 else if (prgfunc == 1 && poprnd == 4)
b7d48530 740 OUTS (outf, "RTE");
4b7f6baa 741 else if (prgfunc == 2 && poprnd == 0)
b7d48530 742 OUTS (outf, "IDLE");
4b7f6baa 743 else if (prgfunc == 2 && poprnd == 3)
b7d48530 744 OUTS (outf, "CSYNC");
4b7f6baa 745 else if (prgfunc == 2 && poprnd == 4)
b7d48530 746 OUTS (outf, "SSYNC");
4b7f6baa 747 else if (prgfunc == 2 && poprnd == 5)
b7d48530 748 OUTS (outf, "EMUEXCPT");
50e2162a 749 else if (prgfunc == 3 && IS_DREG (0, poprnd))
4b7f6baa 750 {
086134ec 751 OUTS (outf, "CLI ");
4b7f6baa 752 OUTS (outf, dregs (poprnd));
4b7f6baa 753 }
50e2162a 754 else if (prgfunc == 4 && IS_DREG (0, poprnd))
4b7f6baa 755 {
086134ec 756 OUTS (outf, "STI ");
4b7f6baa 757 OUTS (outf, dregs (poprnd));
4b7f6baa 758 }
50e2162a 759 else if (prgfunc == 5 && IS_PREG (1, poprnd))
4b7f6baa 760 {
086134ec 761 OUTS (outf, "JUMP (");
4b7f6baa
CM		 762 OUTS (outf, pregs (poprnd));
763 OUTS (outf, ")");
4b7f6baa 764 }
50e2162a 765 else if (prgfunc == 6 && IS_PREG (1, poprnd))
4b7f6baa 766 {
086134ec 767 OUTS (outf, "CALL (");
4b7f6baa
CM		 768 OUTS (outf, pregs (poprnd));
769 OUTS (outf, ")");
4b7f6baa 770 }
50e2162a 771 else if (prgfunc == 7 && IS_PREG (1, poprnd))
4b7f6baa 772 {
086134ec 773 OUTS (outf, "CALL (PC + ");
4b7f6baa
CM		 774 OUTS (outf, pregs (poprnd));
775 OUTS (outf, ")");
4b7f6baa 776 }
50e2162a 777 else if (prgfunc == 8 && IS_PREG (1, poprnd))
4b7f6baa 778 {
086134ec 779 OUTS (outf, "JUMP (PC + ");
4b7f6baa
CM		 780 OUTS (outf, pregs (poprnd));
781 OUTS (outf, ")");
4b7f6baa
CM		 782 }
783 else if (prgfunc == 9)
784 {
086134ec 785 OUTS (outf, "RAISE ");
4b7f6baa 786 OUTS (outf, uimm4 (poprnd));
4b7f6baa
CM		 787 }
788 else if (prgfunc == 10)
789 {
086134ec 790 OUTS (outf, "EXCPT ");
4b7f6baa 791 OUTS (outf, uimm4 (poprnd));
4b7f6baa 792 }
219b747a 793 else if (prgfunc == 11 && IS_PREG (1, poprnd) && poprnd <= 5)
4b7f6baa 794 {
086134ec 795 OUTS (outf, "TESTSET (");
4b7f6baa
CM		 796 OUTS (outf, pregs (poprnd));
797 OUTS (outf, ")");
4b7f6baa
CM		 798 }
799 else
b7d48530
NC		 800 return 0;
801 return 2;
4b7f6baa
CM		 802}
803
804static int
805decode_CaCTRL_0 (TIword iw0, disassemble_info *outf)
806{
703ec4e8 807 struct private *priv = outf->private_data;
b7d48530
NC		 808 /* CaCTRL
809 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
810 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
811 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 812 int a = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask);
813 int op = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask);
814 int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask);
815
703ec4e8 816 if (priv->parallel)
219b747a
MF		 817 return 0;
818
4b7f6baa
CM		 819 if (a == 0 && op == 0)
820 {
4b7f6baa
CM		 821 OUTS (outf, "PREFETCH[");
822 OUTS (outf, pregs (reg));
823 OUTS (outf, "]");
4b7f6baa
CM		 824 }
825 else if (a == 0 && op == 1)
826 {
4b7f6baa
CM		 827 OUTS (outf, "FLUSHINV[");
828 OUTS (outf, pregs (reg));
829 OUTS (outf, "]");
4b7f6baa
CM		 830 }
831 else if (a == 0 && op == 2)
832 {
4b7f6baa
CM		 833 OUTS (outf, "FLUSH[");
834 OUTS (outf, pregs (reg));
835 OUTS (outf, "]");
4b7f6baa
CM		 836 }
837 else if (a == 0 && op == 3)
838 {
4b7f6baa
CM		 839 OUTS (outf, "IFLUSH[");
840 OUTS (outf, pregs (reg));
841 OUTS (outf, "]");
4b7f6baa
CM		 842 }
843 else if (a == 1 && op == 0)
844 {
4b7f6baa
CM		 845 OUTS (outf, "PREFETCH[");
846 OUTS (outf, pregs (reg));
847 OUTS (outf, "++]");
4b7f6baa
CM		 848 }
849 else if (a == 1 && op == 1)
850 {
4b7f6baa
CM		 851 OUTS (outf, "FLUSHINV[");
852 OUTS (outf, pregs (reg));
853 OUTS (outf, "++]");
4b7f6baa
CM		 854 }
855 else if (a == 1 && op == 2)
856 {
4b7f6baa
CM		 857 OUTS (outf, "FLUSH[");
858 OUTS (outf, pregs (reg));
859 OUTS (outf, "++]");
4b7f6baa
CM		 860 }
861 else if (a == 1 && op == 3)
862 {
4b7f6baa
CM		 863 OUTS (outf, "IFLUSH[");
864 OUTS (outf, pregs (reg));
865 OUTS (outf, "++]");
4b7f6baa
CM		 866 }
867 else
b7d48530
NC		 868 return 0;
869 return 2;
4b7f6baa
CM		 870}
871
872static int
873decode_PushPopReg_0 (TIword iw0, disassemble_info *outf)
874{
703ec4e8 875 struct private *priv = outf->private_data;
b7d48530
NC		 876 /* PushPopReg
877 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
878 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
879 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 880 int W = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask);
881 int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask);
882 int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask);
883
703ec4e8 884 if (priv->parallel)
219b747a
MF		 885 return 0;
886
50e2162a 887 if (W == 0 && mostreg (reg, grp))
4b7f6baa 888 {
4b7f6baa
CM		 889 OUTS (outf, allregs (reg, grp));
890 OUTS (outf, " = [SP++]");
4b7f6baa 891 }
219b747a 892 else if (W == 1 && allreg (reg, grp) && !(grp == 1 && reg == 6))
4b7f6baa 893 {
4b7f6baa
CM		 894 OUTS (outf, "[--SP] = ");
895 OUTS (outf, allregs (reg, grp));
4b7f6baa
CM		 896 }
897 else
b7d48530
NC		 898 return 0;
899 return 2;
4b7f6baa
CM		 900}
901
902static int
903decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf)
904{
703ec4e8 905 struct private *priv = outf->private_data;
b7d48530
NC		 906 /* PushPopMultiple
907 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
908 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
909 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 910 int p = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask);
911 int d = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask);
912 int W = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
913 int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
914 int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
4b7f6baa 915
703ec4e8 916 if (priv->parallel)
219b747a
MF		 917 return 0;
918
775f1cf0
MF		 919 if (pr > 5)
920 return 0;
921
4b7f6baa
CM		 922 if (W == 1 && d == 1 && p == 1)
923 {
4b7f6baa 924 OUTS (outf, "[--SP] = (R7:");
086134ec 925 OUTS (outf, imm5d (dr));
4b7f6baa 926 OUTS (outf, ", P5:");
086134ec 927 OUTS (outf, imm5d (pr));
4b7f6baa 928 OUTS (outf, ")");
4b7f6baa 929 }
219b747a 930 else if (W == 1 && d == 1 && p == 0 && pr == 0)
4b7f6baa 931 {
4b7f6baa 932 OUTS (outf, "[--SP] = (R7:");
086134ec 933 OUTS (outf, imm5d (dr));
4b7f6baa 934 OUTS (outf, ")");
4b7f6baa 935 }
219b747a 936 else if (W == 1 && d == 0 && p == 1 && dr == 0)
4b7f6baa 937 {
4b7f6baa 938 OUTS (outf, "[--SP] = (P5:");
086134ec 939 OUTS (outf, imm5d (pr));
4b7f6baa 940 OUTS (outf, ")");
4b7f6baa
CM		 941 }
942 else if (W == 0 && d == 1 && p == 1)
943 {
4b7f6baa 944 OUTS (outf, "(R7:");
086134ec 945 OUTS (outf, imm5d (dr));
4b7f6baa 946 OUTS (outf, ", P5:");
086134ec 947 OUTS (outf, imm5d (pr));
4b7f6baa 948 OUTS (outf, ") = [SP++]");
4b7f6baa 949 }
219b747a 950 else if (W == 0 && d == 1 && p == 0 && pr == 0)
4b7f6baa 951 {
4b7f6baa 952 OUTS (outf, "(R7:");
086134ec 953 OUTS (outf, imm5d (dr));
4b7f6baa 954 OUTS (outf, ") = [SP++]");
4b7f6baa 955 }
219b747a 956 else if (W == 0 && d == 0 && p == 1 && dr == 0)
4b7f6baa 957 {
4b7f6baa 958 OUTS (outf, "(P5:");
086134ec 959 OUTS (outf, imm5d (pr));
4b7f6baa 960 OUTS (outf, ") = [SP++]");
4b7f6baa
CM		 961 }
962 else
b7d48530
NC		 963 return 0;
964 return 2;
4b7f6baa
CM		 965}
966
967static int
968decode_ccMV_0 (TIword iw0, disassemble_info *outf)
969{
703ec4e8 970 struct private *priv = outf->private_data;
b7d48530
NC		 971 /* ccMV
972 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
973 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
974 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 975 int s = ((iw0 >> CCmv_s_bits) & CCmv_s_mask);
976 int d = ((iw0 >> CCmv_d_bits) & CCmv_d_mask);
977 int T = ((iw0 >> CCmv_T_bits) & CCmv_T_mask);
978 int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask);
979 int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask);
980
703ec4e8 981 if (priv->parallel)
219b747a
MF		 982 return 0;
983
4b7f6baa
CM		 984 if (T == 1)
985 {
4b7f6baa
CM		 986 OUTS (outf, "IF CC ");
987 OUTS (outf, gregs (dst, d));
988 OUTS (outf, " = ");
989 OUTS (outf, gregs (src, s));
4b7f6baa
CM		 990 }
991 else if (T == 0)
992 {
086134ec 993 OUTS (outf, "IF !CC ");
4b7f6baa
CM		 994 OUTS (outf, gregs (dst, d));
995 OUTS (outf, " = ");
996 OUTS (outf, gregs (src, s));
4b7f6baa
CM		 997 }
998 else
b7d48530
NC		 999 return 0;
1000 return 2;
4b7f6baa
CM		 1001}
1002
1003static int
1004decode_CCflag_0 (TIword iw0, disassemble_info *outf)
1005{
703ec4e8 1006 struct private *priv = outf->private_data;
b7d48530
NC		 1007 /* CCflag
1008 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1009 | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
1010 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1011 int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask);
1012 int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask);
1013 int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask);
1014 int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask);
1015 int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask);
1016
703ec4e8 1017 if (priv->parallel)
219b747a
MF		 1018 return 0;
1019
4b7f6baa
CM		 1020 if (opc == 0 && I == 0 && G == 0)
1021 {
086134ec 1022 OUTS (outf, "CC = ");
4b7f6baa 1023 OUTS (outf, dregs (x));
086134ec 1024 OUTS (outf, " == ");
4b7f6baa 1025 OUTS (outf, dregs (y));
4b7f6baa
CM		 1026 }
1027 else if (opc == 1 && I == 0 && G == 0)
1028 {
086134ec 1029 OUTS (outf, "CC = ");
4b7f6baa 1030 OUTS (outf, dregs (x));
086134ec 1031 OUTS (outf, " < ");
4b7f6baa 1032 OUTS (outf, dregs (y));
4b7f6baa
CM		 1033 }
1034 else if (opc == 2 && I == 0 && G == 0)
1035 {
086134ec 1036 OUTS (outf, "CC = ");
4b7f6baa 1037 OUTS (outf, dregs (x));
086134ec 1038 OUTS (outf, " <= ");
4b7f6baa 1039 OUTS (outf, dregs (y));
4b7f6baa
CM		 1040 }
1041 else if (opc == 3 && I == 0 && G == 0)
1042 {
086134ec 1043 OUTS (outf, "CC = ");
4b7f6baa 1044 OUTS (outf, dregs (x));
086134ec 1045 OUTS (outf, " < ");
4b7f6baa 1046 OUTS (outf, dregs (y));
086134ec 1047 OUTS (outf, " (IU)");
4b7f6baa
CM		 1048 }
1049 else if (opc == 4 && I == 0 && G == 0)
1050 {
086134ec 1051 OUTS (outf, "CC = ");
4b7f6baa 1052 OUTS (outf, dregs (x));
086134ec 1053 OUTS (outf, " <= ");
4b7f6baa 1054 OUTS (outf, dregs (y));
086134ec 1055 OUTS (outf, " (IU)");
4b7f6baa
CM		 1056 }
1057 else if (opc == 0 && I == 1 && G == 0)
1058 {
086134ec 1059 OUTS (outf, "CC = ");
4b7f6baa 1060 OUTS (outf, dregs (x));
086134ec 1061 OUTS (outf, " == ");
4b7f6baa 1062 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1063 }
1064 else if (opc == 1 && I == 1 && G == 0)
1065 {
086134ec 1066 OUTS (outf, "CC = ");
4b7f6baa 1067 OUTS (outf, dregs (x));
086134ec 1068 OUTS (outf, " < ");
4b7f6baa 1069 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1070 }
1071 else if (opc == 2 && I == 1 && G == 0)
1072 {
086134ec 1073 OUTS (outf, "CC = ");
4b7f6baa 1074 OUTS (outf, dregs (x));
086134ec 1075 OUTS (outf, " <= ");
4b7f6baa 1076 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1077 }
1078 else if (opc == 3 && I == 1 && G == 0)
1079 {
086134ec 1080 OUTS (outf, "CC = ");
4b7f6baa 1081 OUTS (outf, dregs (x));
086134ec 1082 OUTS (outf, " < ");
4b7f6baa 1083 OUTS (outf, uimm3 (y));
086134ec 1084 OUTS (outf, " (IU)");
4b7f6baa
CM		 1085 }
1086 else if (opc == 4 && I == 1 && G == 0)
1087 {
086134ec 1088 OUTS (outf, "CC = ");
4b7f6baa 1089 OUTS (outf, dregs (x));
086134ec 1090 OUTS (outf, " <= ");
4b7f6baa 1091 OUTS (outf, uimm3 (y));
086134ec 1092 OUTS (outf, " (IU)");
4b7f6baa
CM		 1093 }
1094 else if (opc == 0 && I == 0 && G == 1)
1095 {
086134ec 1096 OUTS (outf, "CC = ");
4b7f6baa 1097 OUTS (outf, pregs (x));
086134ec 1098 OUTS (outf, " == ");
4b7f6baa 1099 OUTS (outf, pregs (y));
4b7f6baa
CM		 1100 }
1101 else if (opc == 1 && I == 0 && G == 1)
1102 {
086134ec 1103 OUTS (outf, "CC = ");
4b7f6baa 1104 OUTS (outf, pregs (x));
086134ec 1105 OUTS (outf, " < ");
4b7f6baa 1106 OUTS (outf, pregs (y));
4b7f6baa
CM		 1107 }
1108 else if (opc == 2 && I == 0 && G == 1)
1109 {
086134ec 1110 OUTS (outf, "CC = ");
4b7f6baa 1111 OUTS (outf, pregs (x));
086134ec 1112 OUTS (outf, " <= ");
4b7f6baa 1113 OUTS (outf, pregs (y));
4b7f6baa
CM		 1114 }
1115 else if (opc == 3 && I == 0 && G == 1)
1116 {
086134ec 1117 OUTS (outf, "CC = ");
4b7f6baa 1118 OUTS (outf, pregs (x));
086134ec 1119 OUTS (outf, " < ");
4b7f6baa 1120 OUTS (outf, pregs (y));
086134ec 1121 OUTS (outf, " (IU)");
4b7f6baa
CM		 1122 }
1123 else if (opc == 4 && I == 0 && G == 1)
1124 {
086134ec 1125 OUTS (outf, "CC = ");
4b7f6baa 1126 OUTS (outf, pregs (x));
086134ec 1127 OUTS (outf, " <= ");
4b7f6baa 1128 OUTS (outf, pregs (y));
086134ec 1129 OUTS (outf, " (IU)");
4b7f6baa
CM		 1130 }
1131 else if (opc == 0 && I == 1 && G == 1)
1132 {
086134ec 1133 OUTS (outf, "CC = ");
4b7f6baa 1134 OUTS (outf, pregs (x));
086134ec 1135 OUTS (outf, " == ");
4b7f6baa 1136 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1137 }
1138 else if (opc == 1 && I == 1 && G == 1)
1139 {
086134ec 1140 OUTS (outf, "CC = ");
4b7f6baa 1141 OUTS (outf, pregs (x));
086134ec 1142 OUTS (outf, " < ");
4b7f6baa 1143 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1144 }
1145 else if (opc == 2 && I == 1 && G == 1)
1146 {
086134ec 1147 OUTS (outf, "CC = ");
4b7f6baa 1148 OUTS (outf, pregs (x));
086134ec 1149 OUTS (outf, " <= ");
4b7f6baa 1150 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1151 }
1152 else if (opc == 3 && I == 1 && G == 1)
1153 {
086134ec 1154 OUTS (outf, "CC = ");
4b7f6baa 1155 OUTS (outf, pregs (x));
086134ec 1156 OUTS (outf, " < ");
4b7f6baa 1157 OUTS (outf, uimm3 (y));
086134ec 1158 OUTS (outf, " (IU)");
4b7f6baa
CM		 1159 }
1160 else if (opc == 4 && I == 1 && G == 1)
1161 {
086134ec 1162 OUTS (outf, "CC = ");
4b7f6baa 1163 OUTS (outf, pregs (x));
086134ec 1164 OUTS (outf, " <= ");
4b7f6baa 1165 OUTS (outf, uimm3 (y));
086134ec 1166 OUTS (outf, " (IU)");
4b7f6baa 1167 }
219b747a 1168 else if (opc == 5 && I == 0 && G == 0 && x == 0 && y == 0)
086134ec 1169 OUTS (outf, "CC = A0 == A1");
b7d48530 1170
219b747a 1171 else if (opc == 6 && I == 0 && G == 0 && x == 0 && y == 0)
086134ec 1172 OUTS (outf, "CC = A0 < A1");
b7d48530 1173
219b747a 1174 else if (opc == 7 && I == 0 && G == 0 && x == 0 && y == 0)
086134ec 1175 OUTS (outf, "CC = A0 <= A1");
b7d48530 1176
4b7f6baa 1177 else
b7d48530
NC		 1178 return 0;
1179 return 2;
4b7f6baa
CM		 1180}
1181
1182static int
1183decode_CC2dreg_0 (TIword iw0, disassemble_info *outf)
1184{
703ec4e8 1185 struct private *priv = outf->private_data;
b7d48530
NC		 1186 /* CC2dreg
1187 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1188 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
1189 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1190 int op = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask);
1191 int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask);
1192
703ec4e8 1193 if (priv->parallel)
219b747a
MF		 1194 return 0;
1195
4b7f6baa
CM		 1196 if (op == 0)
1197 {
4b7f6baa 1198 OUTS (outf, dregs (reg));
086134ec 1199 OUTS (outf, " = CC");
4b7f6baa
CM		 1200 }
1201 else if (op == 1)
1202 {
086134ec 1203 OUTS (outf, "CC = ");
4b7f6baa 1204 OUTS (outf, dregs (reg));
4b7f6baa 1205 }
50e2162a 1206 else if (op == 3 && reg == 0)
086134ec 1207 OUTS (outf, "CC = !CC");
4b7f6baa 1208 else
b7d48530
NC		 1209 return 0;
1210
1211 return 2;
4b7f6baa
CM		 1212}
1213
1214static int
1215decode_CC2stat_0 (TIword iw0, disassemble_info *outf)
1216{
703ec4e8 1217 struct private *priv = outf->private_data;
b7d48530
NC		 1218 /* CC2stat
1219 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1220 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
1221 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1222 int D = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask);
1223 int op = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask);
1224 int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask);
1225
b2459327 1226 const char *bitname = statbits (cbit);
219b747a 1227
703ec4e8 1228 if (priv->parallel)
219b747a
MF		 1229 return 0;
1230
b2459327
MF		 1231 if (decode_statbits[cbit] == REG_LASTREG)
1232 {
1233 /* All ASTAT bits except CC may be operated on in hardware, but may
1234 not have a dedicated insn, so still decode "valid" insns. */
1235 static char bitnames[64];
1236 if (cbit != 5)
1237 sprintf (bitnames, "ASTAT[%i /* unused bit */]", cbit);
1238 else
219b747a
MF		 1239 return 0;
1240
b2459327
MF		 1241 bitname = bitnames;
1242 }
1243
4b7f6baa
CM		 1244 if (op == 0 && D == 0)
1245 {
4b7f6baa 1246 OUTS (outf, "CC = ");
b2459327 1247 OUTS (outf, bitname);
4b7f6baa
CM		 1248 }
1249 else if (op == 1 && D == 0)
1250 {
086134ec 1251 OUTS (outf, "CC |= ");
b2459327 1252 OUTS (outf, bitname);
4b7f6baa
CM		 1253 }
1254 else if (op == 2 && D == 0)
1255 {
086134ec 1256 OUTS (outf, "CC &= ");
b2459327 1257 OUTS (outf, bitname);
4b7f6baa
CM		 1258 }
1259 else if (op == 3 && D == 0)
1260 {
086134ec 1261 OUTS (outf, "CC ^= ");
b2459327 1262 OUTS (outf, bitname);
4b7f6baa
CM		 1263 }
1264 else if (op == 0 && D == 1)
1265 {
b2459327 1266 OUTS (outf, bitname);
086134ec 1267 OUTS (outf, " = CC");
4b7f6baa
CM		 1268 }
1269 else if (op == 1 && D == 1)
1270 {
b2459327 1271 OUTS (outf, bitname);
086134ec 1272 OUTS (outf, " |= CC");
4b7f6baa
CM		 1273 }
1274 else if (op == 2 && D == 1)
1275 {
b2459327 1276 OUTS (outf, bitname);
086134ec 1277 OUTS (outf, " &= CC");
4b7f6baa
CM		 1278 }
1279 else if (op == 3 && D == 1)
1280 {
b2459327 1281 OUTS (outf, bitname);
086134ec 1282 OUTS (outf, " ^= CC");
4b7f6baa
CM		 1283 }
1284 else
b7d48530
NC		 1285 return 0;
1286
1287 return 2;
4b7f6baa
CM		 1288}
1289
1290static int
1291decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1292{
703ec4e8 1293 struct private *priv = outf->private_data;
b7d48530
NC		 1294 /* BRCC
1295 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1296 | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
1297 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1298 int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask);
1299 int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask);
1300 int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask);
1301
703ec4e8 1302 if (priv->parallel)
219b747a
MF		 1303 return 0;
1304
4b7f6baa
CM		 1305 if (T == 1 && B == 1)
1306 {
086134ec 1307 OUTS (outf, "IF CC JUMP 0x");
4b7f6baa 1308 OUTS (outf, pcrel10 (offset));
086134ec 1309 OUTS (outf, " (BP)");
4b7f6baa
CM		 1310 }
1311 else if (T == 0 && B == 1)
1312 {
086134ec 1313 OUTS (outf, "IF !CC JUMP 0x");
4b7f6baa 1314 OUTS (outf, pcrel10 (offset));
086134ec 1315 OUTS (outf, " (BP)");
4b7f6baa
CM		 1316 }
1317 else if (T == 1)
1318 {
086134ec 1319 OUTS (outf, "IF CC JUMP 0x");
4b7f6baa 1320 OUTS (outf, pcrel10 (offset));
4b7f6baa
CM		 1321 }
1322 else if (T == 0)
1323 {
086134ec 1324 OUTS (outf, "IF !CC JUMP 0x");
4b7f6baa 1325 OUTS (outf, pcrel10 (offset));
4b7f6baa
CM		 1326 }
1327 else
b7d48530
NC		 1328 return 0;
1329
1330 return 2;
4b7f6baa
CM		 1331}
1332
1333static int
1334decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1335{
703ec4e8 1336 struct private *priv = outf->private_data;
b7d48530
NC		 1337 /* UJUMP
1338 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1339 | 0 | 0 | 1 | 0 |.offset........................................|
1340 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1341 int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask);
1342
703ec4e8 1343 if (priv->parallel)
219b747a
MF		 1344 return 0;
1345
086134ec 1346 OUTS (outf, "JUMP.S 0x");
4b7f6baa 1347 OUTS (outf, pcrel12 (offset));
b7d48530 1348 return 2;
4b7f6baa
CM		 1349}
1350
1351static int
1352decode_REGMV_0 (TIword iw0, disassemble_info *outf)
1353{
b7d48530
NC		 1354 /* REGMV
1355 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1356 | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
1357 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1358 int gs = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask);
1359 int gd = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask);
1360 int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
1361 int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
1362
602427c4 1363 /* Reserved slots cannot be a src/dst. */
35fc57f3
MF		 1364 if (IS_RESERVEDREG (gs, src) || IS_RESERVEDREG (gd, dst))
1365 goto invalid_move;
1366
1367 /* Standard register moves */
1368 if ((gs < 2) || /* Dregs/Pregs as source */
1369 (gd < 2) || /* Dregs/Pregs as dest */
1370 (gs == 4 && src < 4) || /* Accumulators as source */
1371 (gd == 4 && dst < 4 && (gs < 4)) || /* Accumulators as dest */
1372 (gs == 7 && src == 7 && !(gd == 4 && dst < 4)) || /* EMUDAT as src */
1373 (gd == 7 && dst == 7)) /* EMUDAT as dest */
1374 goto valid_move;
1375
1376 /* dareg = dareg (IMBL) */
1377 if (gs < 4 && gd < 4)
1378 goto valid_move;
1379
1380 /* USP can be src to sysregs, but not dagregs. */
1381 if ((gs == 7 && src == 0) && (gd >= 4))
1382 goto valid_move;
1383
1384 /* USP can move between genregs (only check Accumulators). */
1385 if (((gs == 7 && src == 0) && (gd == 4 && dst < 4)) ||
1386 ((gd == 7 && dst == 0) && (gs == 4 && src < 4)))
1387 goto valid_move;
1388
1389 /* Still here ? Invalid reg pair. */
1390 invalid_move:
1391 return 0;
c958a8a8 1392
35fc57f3 1393 valid_move:
4b7f6baa 1394 OUTS (outf, allregs (dst, gd));
086134ec 1395 OUTS (outf, " = ");
4b7f6baa 1396 OUTS (outf, allregs (src, gs));
b7d48530 1397 return 2;
4b7f6baa
CM		 1398}
1399
1400static int
1401decode_ALU2op_0 (TIword iw0, disassemble_info *outf)
1402{
b7d48530
NC		 1403 /* ALU2op
1404 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1405 | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
1406 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1407 int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask);
1408 int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask);
1409 int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask);
1410
1411 if (opc == 0)
1412 {
4b7f6baa 1413 OUTS (outf, dregs (dst));
086134ec 1414 OUTS (outf, " >>>= ");
4b7f6baa 1415 OUTS (outf, dregs (src));
4b7f6baa
CM		 1416 }
1417 else if (opc == 1)
1418 {
4b7f6baa 1419 OUTS (outf, dregs (dst));
086134ec 1420 OUTS (outf, " >>= ");
4b7f6baa 1421 OUTS (outf, dregs (src));
4b7f6baa
CM		 1422 }
1423 else if (opc == 2)
1424 {
4b7f6baa 1425 OUTS (outf, dregs (dst));
086134ec 1426 OUTS (outf, " <<= ");
4b7f6baa 1427 OUTS (outf, dregs (src));
4b7f6baa
CM		 1428 }
1429 else if (opc == 3)
1430 {
4b7f6baa 1431 OUTS (outf, dregs (dst));
086134ec 1432 OUTS (outf, " *= ");
4b7f6baa 1433 OUTS (outf, dregs (src));
4b7f6baa
CM		 1434 }
1435 else if (opc == 4)
1436 {
4b7f6baa 1437 OUTS (outf, dregs (dst));
086134ec 1438 OUTS (outf, " = (");
4b7f6baa 1439 OUTS (outf, dregs (dst));
086134ec 1440 OUTS (outf, " + ");
4b7f6baa 1441 OUTS (outf, dregs (src));
086134ec 1442 OUTS (outf, ") << 0x1");
4b7f6baa
CM		 1443 }
1444 else if (opc == 5)
1445 {
4b7f6baa 1446 OUTS (outf, dregs (dst));
086134ec 1447 OUTS (outf, " = (");
4b7f6baa 1448 OUTS (outf, dregs (dst));
086134ec 1449 OUTS (outf, " + ");
4b7f6baa 1450 OUTS (outf, dregs (src));
086134ec 1451 OUTS (outf, ") << 0x2");
4b7f6baa
CM		 1452 }
1453 else if (opc == 8)
1454 {
086134ec 1455 OUTS (outf, "DIVQ (");
4b7f6baa 1456 OUTS (outf, dregs (dst));
086134ec 1457 OUTS (outf, ", ");
4b7f6baa
CM		 1458 OUTS (outf, dregs (src));
1459 OUTS (outf, ")");
4b7f6baa
CM		 1460 }
1461 else if (opc == 9)
1462 {
086134ec 1463 OUTS (outf, "DIVS (");
4b7f6baa 1464 OUTS (outf, dregs (dst));
086134ec 1465 OUTS (outf, ", ");
4b7f6baa
CM		 1466 OUTS (outf, dregs (src));
1467 OUTS (outf, ")");
4b7f6baa
CM		 1468 }
1469 else if (opc == 10)
1470 {
4b7f6baa 1471 OUTS (outf, dregs (dst));
086134ec 1472 OUTS (outf, " = ");
4b7f6baa 1473 OUTS (outf, dregs_lo (src));
086134ec 1474 OUTS (outf, " (X)");
4b7f6baa
CM		 1475 }
1476 else if (opc == 11)
1477 {
4b7f6baa 1478 OUTS (outf, dregs (dst));
086134ec 1479 OUTS (outf, " = ");
4b7f6baa 1480 OUTS (outf, dregs_lo (src));
086134ec 1481 OUTS (outf, " (Z)");
4b7f6baa
CM		 1482 }
1483 else if (opc == 12)
1484 {
4b7f6baa 1485 OUTS (outf, dregs (dst));
086134ec 1486 OUTS (outf, " = ");
4b7f6baa 1487 OUTS (outf, dregs_byte (src));
086134ec 1488 OUTS (outf, " (X)");
4b7f6baa
CM		 1489 }
1490 else if (opc == 13)
1491 {
4b7f6baa 1492 OUTS (outf, dregs (dst));
086134ec 1493 OUTS (outf, " = ");
4b7f6baa 1494 OUTS (outf, dregs_byte (src));
086134ec 1495 OUTS (outf, " (Z)");
4b7f6baa
CM		 1496 }
1497 else if (opc == 14)
1498 {
4b7f6baa 1499 OUTS (outf, dregs (dst));
086134ec 1500 OUTS (outf, " = -");
4b7f6baa 1501 OUTS (outf, dregs (src));
4b7f6baa
CM		 1502 }
1503 else if (opc == 15)
1504 {
4b7f6baa 1505 OUTS (outf, dregs (dst));
086134ec 1506 OUTS (outf, " =~ ");
4b7f6baa 1507 OUTS (outf, dregs (src));
4b7f6baa
CM		 1508 }
1509 else
b7d48530
NC		 1510 return 0;
1511
1512 return 2;
4b7f6baa
CM		 1513}
1514
1515static int
1516decode_PTR2op_0 (TIword iw0, disassemble_info *outf)
1517{
b7d48530
NC		 1518 /* PTR2op
1519 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1520 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
1521 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1522 int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask);
1523 int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask);
1524 int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask);
1525
1526 if (opc == 0)
1527 {
4b7f6baa 1528 OUTS (outf, pregs (dst));
086134ec 1529 OUTS (outf, " -= ");
4b7f6baa 1530 OUTS (outf, pregs (src));
4b7f6baa
CM		 1531 }
1532 else if (opc == 1)
1533 {
4b7f6baa 1534 OUTS (outf, pregs (dst));
086134ec 1535 OUTS (outf, " = ");
4b7f6baa 1536 OUTS (outf, pregs (src));
086134ec 1537 OUTS (outf, " << 0x2");
4b7f6baa
CM		 1538 }
1539 else if (opc == 3)
1540 {
4b7f6baa 1541 OUTS (outf, pregs (dst));
086134ec 1542 OUTS (outf, " = ");
4b7f6baa 1543 OUTS (outf, pregs (src));
086134ec 1544 OUTS (outf, " >> 0x2");
4b7f6baa
CM		 1545 }
1546 else if (opc == 4)
1547 {
4b7f6baa 1548 OUTS (outf, pregs (dst));
086134ec 1549 OUTS (outf, " = ");
4b7f6baa 1550 OUTS (outf, pregs (src));
086134ec 1551 OUTS (outf, " >> 0x1");
4b7f6baa
CM		 1552 }
1553 else if (opc == 5)
1554 {
4b7f6baa 1555 OUTS (outf, pregs (dst));
086134ec 1556 OUTS (outf, " += ");
4b7f6baa 1557 OUTS (outf, pregs (src));
086134ec 1558 OUTS (outf, " (BREV)");
4b7f6baa
CM		 1559 }
1560 else if (opc == 6)
1561 {
4b7f6baa 1562 OUTS (outf, pregs (dst));
086134ec 1563 OUTS (outf, " = (");
4b7f6baa 1564 OUTS (outf, pregs (dst));
086134ec 1565 OUTS (outf, " + ");
4b7f6baa 1566 OUTS (outf, pregs (src));
086134ec 1567 OUTS (outf, ") << 0x1");
4b7f6baa
CM		 1568 }
1569 else if (opc == 7)
1570 {
4b7f6baa 1571 OUTS (outf, pregs (dst));
086134ec 1572 OUTS (outf, " = (");
4b7f6baa 1573 OUTS (outf, pregs (dst));
086134ec 1574 OUTS (outf, " + ");
4b7f6baa 1575 OUTS (outf, pregs (src));
086134ec 1576 OUTS (outf, ") << 0x2");
4b7f6baa
CM		 1577 }
1578 else
b7d48530
NC		 1579 return 0;
1580
1581 return 2;
4b7f6baa
CM		 1582}
1583
1584static int
1585decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
1586{
703ec4e8 1587 struct private *priv = outf->private_data;
b7d48530
NC		 1588 /* LOGI2op
1589 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1590 | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
1591 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1592 int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask);
1593 int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask);
1594 int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask);
1595
703ec4e8 1596 if (priv->parallel)
219b747a
MF		 1597 return 0;
1598
4b7f6baa
CM		 1599 if (opc == 0)
1600 {
086134ec 1601 OUTS (outf, "CC = !BITTST (");
4b7f6baa 1602 OUTS (outf, dregs (dst));
086134ec 1603 OUTS (outf, ", ");
4b7f6baa 1604 OUTS (outf, uimm5 (src));
086134ec
BS		 1605 OUTS (outf, ");\t\t/* bit");
1606 OUTS (outf, imm7d (src));
1607 OUTS (outf, " */");
703ec4e8 1608 priv->comment = 1;
4b7f6baa
CM		 1609 }
1610 else if (opc == 1)
1611 {
4b7f6baa
CM		 1612 OUTS (outf, "CC = BITTST (");
1613 OUTS (outf, dregs (dst));
086134ec 1614 OUTS (outf, ", ");
4b7f6baa 1615 OUTS (outf, uimm5 (src));
086134ec
BS		 1616 OUTS (outf, ");\t\t/* bit");
1617 OUTS (outf, imm7d (src));
1618 OUTS (outf, " */");
703ec4e8 1619 priv->comment = 1;
4b7f6baa
CM		 1620 }
1621 else if (opc == 2)
1622 {
4b7f6baa
CM		 1623 OUTS (outf, "BITSET (");
1624 OUTS (outf, dregs (dst));
086134ec 1625 OUTS (outf, ", ");
4b7f6baa 1626 OUTS (outf, uimm5 (src));
086134ec
BS		 1627 OUTS (outf, ");\t\t/* bit");
1628 OUTS (outf, imm7d (src));
1629 OUTS (outf, " */");
703ec4e8 1630 priv->comment = 1;
4b7f6baa
CM		 1631 }
1632 else if (opc == 3)
1633 {
4b7f6baa
CM		 1634 OUTS (outf, "BITTGL (");
1635 OUTS (outf, dregs (dst));
086134ec 1636 OUTS (outf, ", ");
4b7f6baa 1637 OUTS (outf, uimm5 (src));
086134ec
BS		 1638 OUTS (outf, ");\t\t/* bit");
1639 OUTS (outf, imm7d (src));
1640 OUTS (outf, " */");
703ec4e8 1641 priv->comment = 1;
4b7f6baa
CM		 1642 }
1643 else if (opc == 4)
1644 {
4b7f6baa
CM		 1645 OUTS (outf, "BITCLR (");
1646 OUTS (outf, dregs (dst));
086134ec 1647 OUTS (outf, ", ");
4b7f6baa 1648 OUTS (outf, uimm5 (src));
086134ec
BS		 1649 OUTS (outf, ");\t\t/* bit");
1650 OUTS (outf, imm7d (src));
1651 OUTS (outf, " */");
703ec4e8 1652 priv->comment = 1;
4b7f6baa
CM		 1653 }
1654 else if (opc == 5)
1655 {
4b7f6baa 1656 OUTS (outf, dregs (dst));
086134ec 1657 OUTS (outf, " >>>= ");
4b7f6baa 1658 OUTS (outf, uimm5 (src));
4b7f6baa
CM		 1659 }
1660 else if (opc == 6)
1661 {
4b7f6baa 1662 OUTS (outf, dregs (dst));
086134ec 1663 OUTS (outf, " >>= ");
4b7f6baa 1664 OUTS (outf, uimm5 (src));
4b7f6baa
CM		 1665 }
1666 else if (opc == 7)
1667 {
4b7f6baa 1668 OUTS (outf, dregs (dst));
086134ec 1669 OUTS (outf, " <<= ");
4b7f6baa 1670 OUTS (outf, uimm5 (src));
4b7f6baa
CM		 1671 }
1672 else
b7d48530
NC		 1673 return 0;
1674
1675 return 2;
4b7f6baa
CM		 1676}
1677
1678static int
1679decode_COMP3op_0 (TIword iw0, disassemble_info *outf)
1680{
b7d48530
NC		 1681 /* COMP3op
1682 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1683 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1684 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1685 int opc = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask);
1686 int dst = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask);
1687 int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask);
1688 int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask);
1689
1690 if (opc == 5 && src1 == src0)
1691 {
4b7f6baa 1692 OUTS (outf, pregs (dst));
086134ec 1693 OUTS (outf, " = ");
4b7f6baa 1694 OUTS (outf, pregs (src0));
086134ec 1695 OUTS (outf, " << 0x1");
4b7f6baa
CM		 1696 }
1697 else if (opc == 1)
1698 {
4b7f6baa 1699 OUTS (outf, dregs (dst));
086134ec 1700 OUTS (outf, " = ");
4b7f6baa 1701 OUTS (outf, dregs (src0));
086134ec 1702 OUTS (outf, " - ");
4b7f6baa 1703 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1704 }
1705 else if (opc == 2)
1706 {
4b7f6baa 1707 OUTS (outf, dregs (dst));
086134ec 1708 OUTS (outf, " = ");
4b7f6baa 1709 OUTS (outf, dregs (src0));
086134ec 1710 OUTS (outf, " & ");
4b7f6baa 1711 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1712 }
1713 else if (opc == 3)
1714 {
4b7f6baa 1715 OUTS (outf, dregs (dst));
086134ec 1716 OUTS (outf, " = ");
4b7f6baa 1717 OUTS (outf, dregs (src0));
086134ec 1718 OUTS (outf, " | ");
4b7f6baa 1719 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1720 }
1721 else if (opc == 4)
1722 {
4b7f6baa 1723 OUTS (outf, dregs (dst));
086134ec 1724 OUTS (outf, " = ");
4b7f6baa 1725 OUTS (outf, dregs (src0));
086134ec 1726 OUTS (outf, " ^ ");
4b7f6baa 1727 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1728 }
1729 else if (opc == 5)
1730 {
4b7f6baa 1731 OUTS (outf, pregs (dst));
086134ec 1732 OUTS (outf, " = ");
4b7f6baa 1733 OUTS (outf, pregs (src0));
086134ec 1734 OUTS (outf, " + ");
4b7f6baa 1735 OUTS (outf, pregs (src1));
4b7f6baa
CM		 1736 }
1737 else if (opc == 6)
1738 {
4b7f6baa 1739 OUTS (outf, pregs (dst));
086134ec 1740 OUTS (outf, " = ");
4b7f6baa 1741 OUTS (outf, pregs (src0));
086134ec 1742 OUTS (outf, " + (");
4b7f6baa 1743 OUTS (outf, pregs (src1));
086134ec 1744 OUTS (outf, " << 0x1)");
4b7f6baa
CM		 1745 }
1746 else if (opc == 7)
1747 {
4b7f6baa 1748 OUTS (outf, pregs (dst));
086134ec 1749 OUTS (outf, " = ");
4b7f6baa 1750 OUTS (outf, pregs (src0));
086134ec 1751 OUTS (outf, " + (");
4b7f6baa 1752 OUTS (outf, pregs (src1));
086134ec 1753 OUTS (outf, " << 0x2)");
4b7f6baa
CM		 1754 }
1755 else if (opc == 0)
1756 {
4b7f6baa 1757 OUTS (outf, dregs (dst));
086134ec 1758 OUTS (outf, " = ");
4b7f6baa 1759 OUTS (outf, dregs (src0));
086134ec 1760 OUTS (outf, " + ");
4b7f6baa 1761 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1762 }
1763 else
b7d48530
NC		 1764 return 0;
1765
1766 return 2;
4b7f6baa
CM		 1767}
1768
1769static int
1770decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf)
1771{
703ec4e8 1772 struct private *priv = outf->private_data;
b7d48530
NC		 1773 /* COMPI2opD
1774 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1775 | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......|
1776 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1777 int op = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask);
1778 int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask);
1779 int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask);
1780
086134ec
BS		 1781 bu32 *pval = get_allreg (0, dst);
1782
703ec4e8 1783 if (priv->parallel)
219b747a
MF		 1784 return 0;
1785
086134ec
BS		 1786 /* Since we don't have 32-bit immediate loads, we allow the disassembler
1787 to combine them, so it prints out the right values.
1788 Here we keep track of the registers. */
1789 if (op == 0)
1790 {
1791 *pval = imm7_val (src);
1792 if (src & 0x40)
1793 *pval |= 0xFFFFFF80;
1794 else
1795 *pval &= 0x7F;
1796 }
1797
4b7f6baa
CM		 1798 if (op == 0)
1799 {
4b7f6baa 1800 OUTS (outf, dregs (dst));
086134ec 1801 OUTS (outf, " = ");
4b7f6baa 1802 OUTS (outf, imm7 (src));
086134ec
BS		 1803 OUTS (outf, " (X);\t\t/*\t\t");
1804 OUTS (outf, dregs (dst));
1805 OUTS (outf, "=");
1806 OUTS (outf, uimm32 (*pval));
1807 OUTS (outf, "(");
1808 OUTS (outf, imm32 (*pval));
1809 OUTS (outf, ") */");
703ec4e8 1810 priv->comment = 1;
4b7f6baa
CM		 1811 }
1812 else if (op == 1)
1813 {
4b7f6baa 1814 OUTS (outf, dregs (dst));
086134ec 1815 OUTS (outf, " += ");
4b7f6baa 1816 OUTS (outf, imm7 (src));
086134ec
BS		 1817 OUTS (outf, ";\t\t/* (");
1818 OUTS (outf, imm7d (src));
1819 OUTS (outf, ") */");
703ec4e8 1820 priv->comment = 1;
4b7f6baa
CM		 1821 }
1822 else
b7d48530
NC		 1823 return 0;
1824
1825 return 2;
4b7f6baa
CM		 1826}
1827
1828static int
1829decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf)
1830{
703ec4e8 1831 struct private *priv = outf->private_data;
b7d48530
NC		 1832 /* COMPI2opP
1833 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1834 | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
1835 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1836 int op = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask);
1837 int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask);
1838 int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask);
1839
086134ec
BS		 1840 bu32 *pval = get_allreg (1, dst);
1841
703ec4e8 1842 if (priv->parallel)
219b747a
MF		 1843 return 0;
1844
086134ec
BS		 1845 if (op == 0)
1846 {
1847 *pval = imm7_val (src);
1848 if (src & 0x40)
1849 *pval |= 0xFFFFFF80;
1850 else
1851 *pval &= 0x7F;
1852 }
1853
4b7f6baa
CM		 1854 if (op == 0)
1855 {
4b7f6baa 1856 OUTS (outf, pregs (dst));
086134ec 1857 OUTS (outf, " = ");
4b7f6baa 1858 OUTS (outf, imm7 (src));
086134ec
BS		 1859 OUTS (outf, " (X);\t\t/*\t\t");
1860 OUTS (outf, pregs (dst));
1861 OUTS (outf, "=");
1862 OUTS (outf, uimm32 (*pval));
1863 OUTS (outf, "(");
1864 OUTS (outf, imm32 (*pval));
1865 OUTS (outf, ") */");
703ec4e8 1866 priv->comment = 1;
4b7f6baa
CM		 1867 }
1868 else if (op == 1)
1869 {
4b7f6baa 1870 OUTS (outf, pregs (dst));
086134ec 1871 OUTS (outf, " += ");
4b7f6baa 1872 OUTS (outf, imm7 (src));
086134ec
BS		 1873 OUTS (outf, ";\t\t/* (");
1874 OUTS (outf, imm7d (src));
1875 OUTS (outf, ") */");
703ec4e8 1876 priv->comment = 1;
4b7f6baa
CM		 1877 }
1878 else
b7d48530
NC		 1879 return 0;
1880
1881 return 2;
4b7f6baa
CM		 1882}
1883
1884static int
1885decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf)
1886{
b7d48530
NC		 1887 /* LDSTpmod
1888 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1889 | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
1890 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1891 int W = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask);
1892 int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask);
1893 int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask);
1894 int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask);
1895 int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask);
1896
1897 if (aop == 1 && W == 0 && idx == ptr)
1898 {
4b7f6baa 1899 OUTS (outf, dregs_lo (reg));
086134ec 1900 OUTS (outf, " = W[");
4b7f6baa
CM		 1901 OUTS (outf, pregs (ptr));
1902 OUTS (outf, "]");
4b7f6baa
CM		 1903 }
1904 else if (aop == 2 && W == 0 && idx == ptr)
1905 {
4b7f6baa 1906 OUTS (outf, dregs_hi (reg));
086134ec 1907 OUTS (outf, " = W[");
4b7f6baa
CM		 1908 OUTS (outf, pregs (ptr));
1909 OUTS (outf, "]");
4b7f6baa
CM		 1910 }
1911 else if (aop == 1 && W == 1 && idx == ptr)
1912 {
4b7f6baa
CM		 1913 OUTS (outf, "W[");
1914 OUTS (outf, pregs (ptr));
086134ec 1915 OUTS (outf, "] = ");
4b7f6baa 1916 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 1917 }
1918 else if (aop == 2 && W == 1 && idx == ptr)
1919 {
4b7f6baa
CM		 1920 OUTS (outf, "W[");
1921 OUTS (outf, pregs (ptr));
086134ec 1922 OUTS (outf, "] = ");
4b7f6baa 1923 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 1924 }
1925 else if (aop == 0 && W == 0)
1926 {
4b7f6baa 1927 OUTS (outf, dregs (reg));
086134ec 1928 OUTS (outf, " = [");
4b7f6baa 1929 OUTS (outf, pregs (ptr));
086134ec 1930 OUTS (outf, " ++ ");
4b7f6baa
CM		 1931 OUTS (outf, pregs (idx));
1932 OUTS (outf, "]");
4b7f6baa
CM		 1933 }
1934 else if (aop == 1 && W == 0)
1935 {
4b7f6baa 1936 OUTS (outf, dregs_lo (reg));
086134ec 1937 OUTS (outf, " = W[");
4b7f6baa 1938 OUTS (outf, pregs (ptr));
086134ec 1939 OUTS (outf, " ++ ");
4b7f6baa
CM		 1940 OUTS (outf, pregs (idx));
1941 OUTS (outf, "]");
4b7f6baa
CM		 1942 }
1943 else if (aop == 2 && W == 0)
1944 {
4b7f6baa 1945 OUTS (outf, dregs_hi (reg));
086134ec 1946 OUTS (outf, " = W[");
4b7f6baa 1947 OUTS (outf, pregs (ptr));
086134ec 1948 OUTS (outf, " ++ ");
4b7f6baa
CM		 1949 OUTS (outf, pregs (idx));
1950 OUTS (outf, "]");
4b7f6baa
CM		 1951 }
1952 else if (aop == 3 && W == 0)
1953 {
4b7f6baa 1954 OUTS (outf, dregs (reg));
086134ec 1955 OUTS (outf, " = W[");
4b7f6baa 1956 OUTS (outf, pregs (ptr));
086134ec 1957 OUTS (outf, " ++ ");
4b7f6baa
CM		 1958 OUTS (outf, pregs (idx));
1959 OUTS (outf, "] (Z)");
4b7f6baa
CM		 1960 }
1961 else if (aop == 3 && W == 1)
1962 {
4b7f6baa 1963 OUTS (outf, dregs (reg));
086134ec 1964 OUTS (outf, " = W[");
4b7f6baa 1965 OUTS (outf, pregs (ptr));
086134ec 1966 OUTS (outf, " ++ ");
4b7f6baa 1967 OUTS (outf, pregs (idx));
086134ec 1968 OUTS (outf, "] (X)");
4b7f6baa
CM		 1969 }
1970 else if (aop == 0 && W == 1)
1971 {
4b7f6baa
CM		 1972 OUTS (outf, "[");
1973 OUTS (outf, pregs (ptr));
086134ec 1974 OUTS (outf, " ++ ");
4b7f6baa 1975 OUTS (outf, pregs (idx));
086134ec 1976 OUTS (outf, "] = ");
4b7f6baa 1977 OUTS (outf, dregs (reg));
4b7f6baa
CM		 1978 }
1979 else if (aop == 1 && W == 1)
1980 {
4b7f6baa
CM		 1981 OUTS (outf, "W[");
1982 OUTS (outf, pregs (ptr));
086134ec 1983 OUTS (outf, " ++ ");
4b7f6baa 1984 OUTS (outf, pregs (idx));
086134ec 1985 OUTS (outf, "] = ");
4b7f6baa 1986 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 1987 }
1988 else if (aop == 2 && W == 1)
1989 {
4b7f6baa
CM		 1990 OUTS (outf, "W[");
1991 OUTS (outf, pregs (ptr));
086134ec 1992 OUTS (outf, " ++ ");
4b7f6baa 1993 OUTS (outf, pregs (idx));
086134ec 1994 OUTS (outf, "] = ");
4b7f6baa 1995 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 1996 }
1997 else
b7d48530
NC		 1998 return 0;
1999
2000 return 2;
4b7f6baa
CM		 2001}
2002
2003static int
2004decode_dagMODim_0 (TIword iw0, disassemble_info *outf)
2005{
b7d48530
NC		 2006 /* dagMODim
2007 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2008 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
2009 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2010 int i = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
2011 int m = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask);
2012 int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask);
2013 int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
2014
2015 if (op == 0 && br == 1)
2016 {
4b7f6baa 2017 OUTS (outf, iregs (i));
086134ec 2018 OUTS (outf, " += ");
4b7f6baa 2019 OUTS (outf, mregs (m));
086134ec 2020 OUTS (outf, " (BREV)");
4b7f6baa
CM		 2021 }
2022 else if (op == 0)
2023 {
4b7f6baa 2024 OUTS (outf, iregs (i));
086134ec 2025 OUTS (outf, " += ");
4b7f6baa 2026 OUTS (outf, mregs (m));
4b7f6baa 2027 }
219b747a 2028 else if (op == 1 && br == 0)
4b7f6baa 2029 {
4b7f6baa 2030 OUTS (outf, iregs (i));
086134ec 2031 OUTS (outf, " -= ");
4b7f6baa 2032 OUTS (outf, mregs (m));
4b7f6baa
CM		 2033 }
2034 else
b7d48530
NC		 2035 return 0;
2036
2037 return 2;
4b7f6baa
CM		 2038}
2039
2040static int
2041decode_dagMODik_0 (TIword iw0, disassemble_info *outf)
2042{
703ec4e8 2043 struct private *priv = outf->private_data;
b7d48530
NC		 2044 /* dagMODik
2045 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2046 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
2047 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2048 int i = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
2049 int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask);
2050
2051 if (op == 0)
2052 {
4b7f6baa 2053 OUTS (outf, iregs (i));
086134ec 2054 OUTS (outf, " += 0x2");
4b7f6baa
CM		 2055 }
2056 else if (op == 1)
2057 {
4b7f6baa 2058 OUTS (outf, iregs (i));
086134ec 2059 OUTS (outf, " -= 0x2");
4b7f6baa
CM		 2060 }
2061 else if (op == 2)
2062 {
4b7f6baa 2063 OUTS (outf, iregs (i));
086134ec 2064 OUTS (outf, " += 0x4");
4b7f6baa
CM		 2065 }
2066 else if (op == 3)
2067 {
4b7f6baa 2068 OUTS (outf, iregs (i));
086134ec 2069 OUTS (outf, " -= 0x4");
4b7f6baa
CM		 2070 }
2071 else
b7d48530
NC		 2072 return 0;
2073
703ec4e8 2074 if (!priv->parallel)
602427c4
MF		 2075 {
2076 OUTS (outf, ";\t\t/* ( ");
2077 if (op == 0 || op == 1)
2078 OUTS (outf, "2");
2079 else if (op == 2 || op == 3)
086134ec 2080 OUTS (outf, "4");
602427c4 2081 OUTS (outf, ") */");
703ec4e8 2082 priv->comment = 1;
602427c4 2083 }
086134ec 2084
b7d48530 2085 return 2;
4b7f6baa
CM		 2086}
2087
2088static int
2089decode_dspLDST_0 (TIword iw0, disassemble_info *outf)
2090{
b7d48530
NC		 2091 /* dspLDST
2092 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2093 | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
2094 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2095 int i = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
2096 int m = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask);
2097 int W = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask);
2098 int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask);
2099 int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask);
2100
2101 if (aop == 0 && W == 0 && m == 0)
2102 {
4b7f6baa 2103 OUTS (outf, dregs (reg));
086134ec 2104 OUTS (outf, " = [");
4b7f6baa
CM		 2105 OUTS (outf, iregs (i));
2106 OUTS (outf, "++]");
4b7f6baa
CM		 2107 }
2108 else if (aop == 0 && W == 0 && m == 1)
2109 {
4b7f6baa 2110 OUTS (outf, dregs_lo (reg));
086134ec 2111 OUTS (outf, " = W[");
4b7f6baa
CM		 2112 OUTS (outf, iregs (i));
2113 OUTS (outf, "++]");
4b7f6baa
CM		 2114 }
2115 else if (aop == 0 && W == 0 && m == 2)
2116 {
4b7f6baa 2117 OUTS (outf, dregs_hi (reg));
086134ec 2118 OUTS (outf, " = W[");
4b7f6baa
CM		 2119 OUTS (outf, iregs (i));
2120 OUTS (outf, "++]");
4b7f6baa
CM		 2121 }
2122 else if (aop == 1 && W == 0 && m == 0)
2123 {
4b7f6baa 2124 OUTS (outf, dregs (reg));
086134ec 2125 OUTS (outf, " = [");
4b7f6baa
CM		 2126 OUTS (outf, iregs (i));
2127 OUTS (outf, "--]");
4b7f6baa
CM		 2128 }
2129 else if (aop == 1 && W == 0 && m == 1)
2130 {
4b7f6baa 2131 OUTS (outf, dregs_lo (reg));
086134ec 2132 OUTS (outf, " = W[");
4b7f6baa
CM		 2133 OUTS (outf, iregs (i));
2134 OUTS (outf, "--]");
4b7f6baa
CM		 2135 }
2136 else if (aop == 1 && W == 0 && m == 2)
2137 {
4b7f6baa 2138 OUTS (outf, dregs_hi (reg));
086134ec 2139 OUTS (outf, " = W[");
4b7f6baa
CM		 2140 OUTS (outf, iregs (i));
2141 OUTS (outf, "--]");
4b7f6baa
CM		 2142 }
2143 else if (aop == 2 && W == 0 && m == 0)
2144 {
4b7f6baa 2145 OUTS (outf, dregs (reg));
086134ec 2146 OUTS (outf, " = [");
4b7f6baa
CM		 2147 OUTS (outf, iregs (i));
2148 OUTS (outf, "]");
4b7f6baa
CM		 2149 }
2150 else if (aop == 2 && W == 0 && m == 1)
2151 {
4b7f6baa 2152 OUTS (outf, dregs_lo (reg));
086134ec 2153 OUTS (outf, " = W[");
4b7f6baa
CM		 2154 OUTS (outf, iregs (i));
2155 OUTS (outf, "]");
4b7f6baa
CM		 2156 }
2157 else if (aop == 2 && W == 0 && m == 2)
2158 {
4b7f6baa 2159 OUTS (outf, dregs_hi (reg));
086134ec 2160 OUTS (outf, " = W[");
4b7f6baa
CM		 2161 OUTS (outf, iregs (i));
2162 OUTS (outf, "]");
4b7f6baa
CM		 2163 }
2164 else if (aop == 0 && W == 1 && m == 0)
2165 {
4b7f6baa
CM		 2166 OUTS (outf, "[");
2167 OUTS (outf, iregs (i));
086134ec 2168 OUTS (outf, "++] = ");
4b7f6baa 2169 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2170 }
2171 else if (aop == 0 && W == 1 && m == 1)
2172 {
4b7f6baa
CM		 2173 OUTS (outf, "W[");
2174 OUTS (outf, iregs (i));
086134ec 2175 OUTS (outf, "++] = ");
4b7f6baa 2176 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 2177 }
2178 else if (aop == 0 && W == 1 && m == 2)
2179 {
4b7f6baa
CM		 2180 OUTS (outf, "W[");
2181 OUTS (outf, iregs (i));
086134ec 2182 OUTS (outf, "++] = ");
4b7f6baa 2183 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 2184 }
2185 else if (aop == 1 && W == 1 && m == 0)
2186 {
4b7f6baa
CM		 2187 OUTS (outf, "[");
2188 OUTS (outf, iregs (i));
086134ec 2189 OUTS (outf, "--] = ");
4b7f6baa 2190 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2191 }
2192 else if (aop == 1 && W == 1 && m == 1)
2193 {
4b7f6baa
CM		 2194 OUTS (outf, "W[");
2195 OUTS (outf, iregs (i));
086134ec 2196 OUTS (outf, "--] = ");
4b7f6baa 2197 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 2198 }
2199 else if (aop == 1 && W == 1 && m == 2)
2200 {
4b7f6baa
CM		 2201 OUTS (outf, "W[");
2202 OUTS (outf, iregs (i));
086134ec 2203 OUTS (outf, "--] = ");
4b7f6baa 2204 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 2205 }
2206 else if (aop == 2 && W == 1 && m == 0)
2207 {
4b7f6baa
CM		 2208 OUTS (outf, "[");
2209 OUTS (outf, iregs (i));
086134ec 2210 OUTS (outf, "] = ");
4b7f6baa 2211 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2212 }
2213 else if (aop == 2 && W == 1 && m == 1)
2214 {
4b7f6baa
CM		 2215 OUTS (outf, "W[");
2216 OUTS (outf, iregs (i));
086134ec 2217 OUTS (outf, "] = ");
4b7f6baa 2218 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 2219 }
2220 else if (aop == 2 && W == 1 && m == 2)
2221 {
4b7f6baa
CM		 2222 OUTS (outf, "W[");
2223 OUTS (outf, iregs (i));
086134ec 2224 OUTS (outf, "] = ");
4b7f6baa 2225 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 2226 }
2227 else if (aop == 3 && W == 0)
2228 {
4b7f6baa 2229 OUTS (outf, dregs (reg));
086134ec 2230 OUTS (outf, " = [");
4b7f6baa 2231 OUTS (outf, iregs (i));
086134ec 2232 OUTS (outf, " ++ ");
4b7f6baa
CM		 2233 OUTS (outf, mregs (m));
2234 OUTS (outf, "]");
4b7f6baa
CM		 2235 }
2236 else if (aop == 3 && W == 1)
2237 {
4b7f6baa
CM		 2238 OUTS (outf, "[");
2239 OUTS (outf, iregs (i));
086134ec 2240 OUTS (outf, " ++ ");
4b7f6baa 2241 OUTS (outf, mregs (m));
086134ec 2242 OUTS (outf, "] = ");
4b7f6baa 2243 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2244 }
2245 else
b7d48530
NC		 2246 return 0;
2247
2248 return 2;
4b7f6baa
CM		 2249}
2250
2251static int
2252decode_LDST_0 (TIword iw0, disassemble_info *outf)
2253{
b7d48530
NC		 2254 /* LDST
2255 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2256 | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
2257 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2258 int Z = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
2259 int W = ((iw0 >> LDST_W_bits) & LDST_W_mask);
2260 int sz = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
2261 int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
2262 int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
2263 int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask);
2264
2265 if (aop == 0 && sz == 0 && Z == 0 && W == 0)
2266 {
4b7f6baa 2267 OUTS (outf, dregs (reg));
086134ec 2268 OUTS (outf, " = [");
4b7f6baa
CM		 2269 OUTS (outf, pregs (ptr));
2270 OUTS (outf, "++]");
4b7f6baa 2271 }
219b747a 2272 else if (aop == 0 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
4b7f6baa 2273 {
4b7f6baa 2274 OUTS (outf, pregs (reg));
086134ec 2275 OUTS (outf, " = [");
4b7f6baa
CM		 2276 OUTS (outf, pregs (ptr));
2277 OUTS (outf, "++]");
4b7f6baa
CM		 2278 }
2279 else if (aop == 0 && sz == 1 && Z == 0 && W == 0)
2280 {
4b7f6baa 2281 OUTS (outf, dregs (reg));
086134ec 2282 OUTS (outf, " = W[");
4b7f6baa
CM		 2283 OUTS (outf, pregs (ptr));
2284 OUTS (outf, "++] (Z)");
4b7f6baa
CM		 2285 }
2286 else if (aop == 0 && sz == 1 && Z == 1 && W == 0)
2287 {
4b7f6baa 2288 OUTS (outf, dregs (reg));
086134ec 2289 OUTS (outf, " = W[");
4b7f6baa 2290 OUTS (outf, pregs (ptr));
086134ec 2291 OUTS (outf, "++] (X)");
4b7f6baa
CM		 2292 }
2293 else if (aop == 0 && sz == 2 && Z == 0 && W == 0)
2294 {
4b7f6baa 2295 OUTS (outf, dregs (reg));
086134ec 2296 OUTS (outf, " = B[");
4b7f6baa
CM		 2297 OUTS (outf, pregs (ptr));
2298 OUTS (outf, "++] (Z)");
4b7f6baa
CM		 2299 }
2300 else if (aop == 0 && sz == 2 && Z == 1 && W == 0)
2301 {
4b7f6baa 2302 OUTS (outf, dregs (reg));
086134ec 2303 OUTS (outf, " = B[");
4b7f6baa 2304 OUTS (outf, pregs (ptr));
086134ec 2305 OUTS (outf, "++] (X)");
4b7f6baa
CM		 2306 }
2307 else if (aop == 1 && sz == 0 && Z == 0 && W == 0)
2308 {
4b7f6baa 2309 OUTS (outf, dregs (reg));
086134ec 2310 OUTS (outf, " = [");
4b7f6baa
CM		 2311 OUTS (outf, pregs (ptr));
2312 OUTS (outf, "--]");
4b7f6baa 2313 }
219b747a 2314 else if (aop == 1 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
4b7f6baa 2315 {
4b7f6baa 2316 OUTS (outf, pregs (reg));
086134ec 2317 OUTS (outf, " = [");
4b7f6baa
CM		 2318 OUTS (outf, pregs (ptr));
2319 OUTS (outf, "--]");
4b7f6baa
CM		 2320 }
2321 else if (aop == 1 && sz == 1 && Z == 0 && W == 0)
2322 {
4b7f6baa 2323 OUTS (outf, dregs (reg));
086134ec 2324 OUTS (outf, " = W[");
4b7f6baa
CM		 2325 OUTS (outf, pregs (ptr));
2326 OUTS (outf, "--] (Z)");
4b7f6baa
CM		 2327 }
2328 else if (aop == 1 && sz == 1 && Z == 1 && W == 0)
2329 {
4b7f6baa 2330 OUTS (outf, dregs (reg));
086134ec 2331 OUTS (outf, " = W[");
4b7f6baa 2332 OUTS (outf, pregs (ptr));
086134ec 2333 OUTS (outf, "--] (X)");
4b7f6baa
CM		 2334 }
2335 else if (aop == 1 && sz == 2 && Z == 0 && W == 0)
2336 {
4b7f6baa 2337 OUTS (outf, dregs (reg));
086134ec 2338 OUTS (outf, " = B[");
4b7f6baa
CM		 2339 OUTS (outf, pregs (ptr));
2340 OUTS (outf, "--] (Z)");
4b7f6baa
CM		 2341 }
2342 else if (aop == 1 && sz == 2 && Z == 1 && W == 0)
2343 {
4b7f6baa 2344 OUTS (outf, dregs (reg));
086134ec 2345 OUTS (outf, " = B[");
4b7f6baa 2346 OUTS (outf, pregs (ptr));
086134ec 2347 OUTS (outf, "--] (X)");
4b7f6baa
CM		 2348 }
2349 else if (aop == 2 && sz == 0 && Z == 0 && W == 0)
2350 {
4b7f6baa 2351 OUTS (outf, dregs (reg));
086134ec 2352 OUTS (outf, " = [");
4b7f6baa
CM		 2353 OUTS (outf, pregs (ptr));
2354 OUTS (outf, "]");
4b7f6baa
CM		 2355 }
2356 else if (aop == 2 && sz == 0 && Z == 1 && W == 0)
2357 {
4b7f6baa 2358 OUTS (outf, pregs (reg));
086134ec 2359 OUTS (outf, " = [");
4b7f6baa
CM		 2360 OUTS (outf, pregs (ptr));
2361 OUTS (outf, "]");
4b7f6baa
CM		 2362 }
2363 else if (aop == 2 && sz == 1 && Z == 0 && W == 0)
2364 {
4b7f6baa 2365 OUTS (outf, dregs (reg));
086134ec 2366 OUTS (outf, " = W[");
4b7f6baa
CM		 2367 OUTS (outf, pregs (ptr));
2368 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2369 }
2370 else if (aop == 2 && sz == 1 && Z == 1 && W == 0)
2371 {
4b7f6baa 2372 OUTS (outf, dregs (reg));
086134ec 2373 OUTS (outf, " = W[");
4b7f6baa 2374 OUTS (outf, pregs (ptr));
086134ec 2375 OUTS (outf, "] (X)");
4b7f6baa
CM		 2376 }
2377 else if (aop == 2 && sz == 2 && Z == 0 && W == 0)
2378 {
4b7f6baa 2379 OUTS (outf, dregs (reg));
086134ec 2380 OUTS (outf, " = B[");
4b7f6baa
CM		 2381 OUTS (outf, pregs (ptr));
2382 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2383 }
2384 else if (aop == 2 && sz == 2 && Z == 1 && W == 0)
2385 {
4b7f6baa 2386 OUTS (outf, dregs (reg));
086134ec 2387 OUTS (outf, " = B[");
4b7f6baa 2388 OUTS (outf, pregs (ptr));
086134ec 2389 OUTS (outf, "] (X)");
4b7f6baa
CM		 2390 }
2391 else if (aop == 0 && sz == 0 && Z == 0 && W == 1)
2392 {
4b7f6baa
CM		 2393 OUTS (outf, "[");
2394 OUTS (outf, pregs (ptr));
086134ec 2395 OUTS (outf, "++] = ");
4b7f6baa 2396 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2397 }
2398 else if (aop == 0 && sz == 0 && Z == 1 && W == 1)
2399 {
4b7f6baa
CM		 2400 OUTS (outf, "[");
2401 OUTS (outf, pregs (ptr));
086134ec 2402 OUTS (outf, "++] = ");
4b7f6baa 2403 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2404 }
2405 else if (aop == 0 && sz == 1 && Z == 0 && W == 1)
2406 {
4b7f6baa
CM		 2407 OUTS (outf, "W[");
2408 OUTS (outf, pregs (ptr));
086134ec 2409 OUTS (outf, "++] = ");
4b7f6baa 2410 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2411 }
2412 else if (aop == 0 && sz == 2 && Z == 0 && W == 1)
2413 {
4b7f6baa
CM		 2414 OUTS (outf, "B[");
2415 OUTS (outf, pregs (ptr));
086134ec 2416 OUTS (outf, "++] = ");
4b7f6baa 2417 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2418 }
2419 else if (aop == 1 && sz == 0 && Z == 0 && W == 1)
2420 {
4b7f6baa
CM		 2421 OUTS (outf, "[");
2422 OUTS (outf, pregs (ptr));
086134ec 2423 OUTS (outf, "--] = ");
4b7f6baa 2424 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2425 }
2426 else if (aop == 1 && sz == 0 && Z == 1 && W == 1)
2427 {
4b7f6baa
CM		 2428 OUTS (outf, "[");
2429 OUTS (outf, pregs (ptr));
086134ec 2430 OUTS (outf, "--] = ");
4b7f6baa 2431 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2432 }
2433 else if (aop == 1 && sz == 1 && Z == 0 && W == 1)
2434 {
4b7f6baa
CM		 2435 OUTS (outf, "W[");
2436 OUTS (outf, pregs (ptr));
086134ec 2437 OUTS (outf, "--] = ");
4b7f6baa 2438 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2439 }
2440 else if (aop == 1 && sz == 2 && Z == 0 && W == 1)
2441 {
4b7f6baa
CM		 2442 OUTS (outf, "B[");
2443 OUTS (outf, pregs (ptr));
086134ec 2444 OUTS (outf, "--] = ");
4b7f6baa 2445 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2446 }
2447 else if (aop == 2 && sz == 0 && Z == 0 && W == 1)
2448 {
4b7f6baa
CM		 2449 OUTS (outf, "[");
2450 OUTS (outf, pregs (ptr));
086134ec 2451 OUTS (outf, "] = ");
4b7f6baa 2452 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2453 }
2454 else if (aop == 2 && sz == 0 && Z == 1 && W == 1)
2455 {
4b7f6baa
CM		 2456 OUTS (outf, "[");
2457 OUTS (outf, pregs (ptr));
086134ec 2458 OUTS (outf, "] = ");
4b7f6baa 2459 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2460 }
2461 else if (aop == 2 && sz == 1 && Z == 0 && W == 1)
2462 {
4b7f6baa
CM		 2463 OUTS (outf, "W[");
2464 OUTS (outf, pregs (ptr));
086134ec 2465 OUTS (outf, "] = ");
4b7f6baa 2466 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2467 }
2468 else if (aop == 2 && sz == 2 && Z == 0 && W == 1)
2469 {
4b7f6baa
CM		 2470 OUTS (outf, "B[");
2471 OUTS (outf, pregs (ptr));
086134ec 2472 OUTS (outf, "] = ");
4b7f6baa 2473 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2474 }
2475 else
b7d48530
NC		 2476 return 0;
2477
2478 return 2;
4b7f6baa
CM		 2479}
2480
2481static int
2482decode_LDSTiiFP_0 (TIword iw0, disassemble_info *outf)
2483{
b7d48530
NC		 2484 /* LDSTiiFP
2485 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2486 | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
2487 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2488 int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask);
2489 int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask);
2490 int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask);
2491
2492 if (W == 0)
2493 {
4b7f6baa 2494 OUTS (outf, dpregs (reg));
086134ec 2495 OUTS (outf, " = [FP ");
4b7f6baa
CM		 2496 OUTS (outf, negimm5s4 (offset));
2497 OUTS (outf, "]");
4b7f6baa
CM		 2498 }
2499 else if (W == 1)
2500 {
086134ec 2501 OUTS (outf, "[FP ");
4b7f6baa 2502 OUTS (outf, negimm5s4 (offset));
086134ec 2503 OUTS (outf, "] = ");
4b7f6baa 2504 OUTS (outf, dpregs (reg));
4b7f6baa
CM		 2505 }
2506 else
b7d48530
NC		 2507 return 0;
2508
2509 return 2;
4b7f6baa
CM		 2510}
2511
2512static int
2513decode_LDSTii_0 (TIword iw0, disassemble_info *outf)
2514{
b7d48530
NC		 2515 /* LDSTii
2516 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2517 | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
2518 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2519 int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask);
2520 int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
2521 int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask);
2522 int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask);
2523 int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask);
2524
2525 if (W == 0 && op == 0)
2526 {
4b7f6baa 2527 OUTS (outf, dregs (reg));
086134ec 2528 OUTS (outf, " = [");
4b7f6baa 2529 OUTS (outf, pregs (ptr));
086134ec 2530 OUTS (outf, " + ");
4b7f6baa
CM		 2531 OUTS (outf, uimm4s4 (offset));
2532 OUTS (outf, "]");
4b7f6baa
CM		 2533 }
2534 else if (W == 0 && op == 1)
2535 {
4b7f6baa 2536 OUTS (outf, dregs (reg));
086134ec 2537 OUTS (outf, " = W[");
4b7f6baa 2538 OUTS (outf, pregs (ptr));
086134ec 2539 OUTS (outf, " + ");
4b7f6baa
CM		 2540 OUTS (outf, uimm4s2 (offset));
2541 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2542 }
2543 else if (W == 0 && op == 2)
2544 {
4b7f6baa 2545 OUTS (outf, dregs (reg));
086134ec 2546 OUTS (outf, " = W[");
4b7f6baa 2547 OUTS (outf, pregs (ptr));
086134ec 2548 OUTS (outf, " + ");
4b7f6baa 2549 OUTS (outf, uimm4s2 (offset));
086134ec 2550 OUTS (outf, "] (X)");
4b7f6baa
CM		 2551 }
2552 else if (W == 0 && op == 3)
2553 {
4b7f6baa 2554 OUTS (outf, pregs (reg));
086134ec 2555 OUTS (outf, " = [");
4b7f6baa 2556 OUTS (outf, pregs (ptr));
086134ec 2557 OUTS (outf, " + ");
4b7f6baa
CM		 2558 OUTS (outf, uimm4s4 (offset));
2559 OUTS (outf, "]");
4b7f6baa
CM		 2560 }
2561 else if (W == 1 && op == 0)
2562 {
4b7f6baa
CM		 2563 OUTS (outf, "[");
2564 OUTS (outf, pregs (ptr));
086134ec 2565 OUTS (outf, " + ");
4b7f6baa 2566 OUTS (outf, uimm4s4 (offset));
086134ec 2567 OUTS (outf, "] = ");
4b7f6baa 2568 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2569 }
2570 else if (W == 1 && op == 1)
2571 {
086134ec 2572 OUTS (outf, "W[");
4b7f6baa 2573 OUTS (outf, pregs (ptr));
086134ec 2574 OUTS (outf, " + ");
4b7f6baa 2575 OUTS (outf, uimm4s2 (offset));
086134ec 2576 OUTS (outf, "] = ");
4b7f6baa 2577 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2578 }
2579 else if (W == 1 && op == 3)
2580 {
4b7f6baa
CM		 2581 OUTS (outf, "[");
2582 OUTS (outf, pregs (ptr));
086134ec 2583 OUTS (outf, " + ");
4b7f6baa 2584 OUTS (outf, uimm4s4 (offset));
086134ec 2585 OUTS (outf, "] = ");
4b7f6baa 2586 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2587 }
2588 else
b7d48530
NC		 2589 return 0;
2590
2591 return 2;
4b7f6baa
CM		 2592}
2593
2594static int
2595decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2596{
703ec4e8 2597 struct private *priv = outf->private_data;
b7d48530
NC		 2598 /* LoopSetup
2599 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2600 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
2601 |.reg...........| - | - |.eoffset...............................|
2602 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2603 int c = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask);
2604 int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
2605 int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask);
2606 int soffset = ((iw0 >> (LoopSetup_soffset_bits - 16)) & LoopSetup_soffset_mask);
2607 int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask);
2608
703ec4e8 2609 if (priv->parallel)
219b747a
MF		 2610 return 0;
2611
298c1ec2
MF		 2612 if (reg > 7)
2613 return 0;
2614
4b7f6baa
CM		 2615 if (rop == 0)
2616 {
4b7f6baa 2617 OUTS (outf, "LSETUP");
086134ec 2618 OUTS (outf, "(0x");
4b7f6baa 2619 OUTS (outf, pcrel4 (soffset));
086134ec 2620 OUTS (outf, ", 0x");
4b7f6baa 2621 OUTS (outf, lppcrel10 (eoffset));
086134ec 2622 OUTS (outf, ") ");
4b7f6baa 2623 OUTS (outf, counters (c));
4b7f6baa
CM		 2624 }
2625 else if (rop == 1)
2626 {
4b7f6baa 2627 OUTS (outf, "LSETUP");
086134ec 2628 OUTS (outf, "(0x");
4b7f6baa 2629 OUTS (outf, pcrel4 (soffset));
086134ec 2630 OUTS (outf, ", 0x");
4b7f6baa 2631 OUTS (outf, lppcrel10 (eoffset));
086134ec 2632 OUTS (outf, ") ");
4b7f6baa 2633 OUTS (outf, counters (c));
086134ec 2634 OUTS (outf, " = ");
4b7f6baa 2635 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2636 }
2637 else if (rop == 3)
2638 {
4b7f6baa 2639 OUTS (outf, "LSETUP");
086134ec 2640 OUTS (outf, "(0x");
4b7f6baa 2641 OUTS (outf, pcrel4 (soffset));
086134ec 2642 OUTS (outf, ", 0x");
4b7f6baa 2643 OUTS (outf, lppcrel10 (eoffset));
086134ec 2644 OUTS (outf, ") ");
4b7f6baa 2645 OUTS (outf, counters (c));
086134ec 2646 OUTS (outf, " = ");
4b7f6baa 2647 OUTS (outf, pregs (reg));
086134ec 2648 OUTS (outf, " >> 0x1");
4b7f6baa
CM		 2649 }
2650 else
b7d48530
NC		 2651 return 0;
2652
2653 return 4;
4b7f6baa
CM		 2654}
2655
2656static int
2657decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2658{
703ec4e8 2659 struct private *priv = outf->private_data;
b7d48530
NC		 2660 /* LDIMMhalf
2661 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2662 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
2663 |.hword.........................................................|
2664 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2665 int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask);
2666 int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask);
2667 int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask);
2668 int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask);
2669 int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask);
2670 int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask);
2671
b21c9cb4
BS		 2672 bu32 *pval = get_allreg (grp, reg);
2673
703ec4e8 2674 if (priv->parallel)
219b747a
MF		 2675 return 0;
2676
b21c9cb4
BS		 2677 /* Since we don't have 32-bit immediate loads, we allow the disassembler
2678 to combine them, so it prints out the right values.
2679 Here we keep track of the registers. */
2680 if (H == 0 && S == 1 && Z == 0)
2681 {
2682 /* regs = imm16 (x) */
2683 *pval = imm16_val (hword);
086134ec
BS		 2684 if (hword & 0x8000)
2685 *pval |= 0xFFFF0000;
2686 else
2687 *pval &= 0xFFFF;
b21c9cb4
BS		 2688 }
2689 else if (H == 0 && S == 0 && Z == 1)
2690 {
2691 /* regs = luimm16 (Z) */
2692 *pval = luimm16_val (hword);
086134ec 2693 *pval &= 0xFFFF;
b21c9cb4
BS		 2694 }
2695 else if (H == 0 && S == 0 && Z == 0)
2696 {
2697 /* regs_lo = luimm16 */
2698 *pval &= 0xFFFF0000;
2699 *pval |= luimm16_val (hword);
2700 }
2701 else if (H == 1 && S == 0 && Z == 0)
2702 {
2703 /* regs_hi = huimm16 */
2704 *pval &= 0xFFFF;
2705 *pval |= luimm16_val (hword) << 16;
2706 }
2707
2708 /* Here we do the disassembly */
4b7f6baa
CM		 2709 if (grp == 0 && H == 0 && S == 0 && Z == 0)
2710 {
4b7f6baa 2711 OUTS (outf, dregs_lo (reg));
086134ec
BS		 2712 OUTS (outf, " = ");
2713 OUTS (outf, uimm16 (hword));
4b7f6baa
CM		 2714 }
2715 else if (grp == 0 && H == 1 && S == 0 && Z == 0)
2716 {
4b7f6baa 2717 OUTS (outf, dregs_hi (reg));
086134ec
BS		 2718 OUTS (outf, " = ");
2719 OUTS (outf, uimm16 (hword));
4b7f6baa
CM		 2720 }
2721 else if (grp == 0 && H == 0 && S == 1 && Z == 0)
2722 {
4b7f6baa 2723 OUTS (outf, dregs (reg));
086134ec 2724 OUTS (outf, " = ");
4b7f6baa
CM		 2725 OUTS (outf, imm16 (hword));
2726 OUTS (outf, " (X)");
4b7f6baa
CM		 2727 }
2728 else if (H == 0 && S == 1 && Z == 0)
602427c4 2729 {
4b7f6baa 2730 OUTS (outf, regs (reg, grp));
086134ec 2731 OUTS (outf, " = ");
4b7f6baa
CM		 2732 OUTS (outf, imm16 (hword));
2733 OUTS (outf, " (X)");
4b7f6baa
CM		 2734 }
2735 else if (H == 0 && S == 0 && Z == 1)
2736 {
4b7f6baa 2737 OUTS (outf, regs (reg, grp));
086134ec
BS		 2738 OUTS (outf, " = ");
2739 OUTS (outf, uimm16 (hword));
2740 OUTS (outf, " (Z)");
4b7f6baa
CM		 2741 }
2742 else if (H == 0 && S == 0 && Z == 0)
2743 {
4b7f6baa 2744 OUTS (outf, regs_lo (reg, grp));
086134ec 2745 OUTS (outf, " = ");
b21c9cb4 2746 OUTS (outf, uimm16 (hword));
4b7f6baa
CM		 2747 }
2748 else if (H == 1 && S == 0 && Z == 0)
2749 {
4b7f6baa 2750 OUTS (outf, regs_hi (reg, grp));
086134ec 2751 OUTS (outf, " = ");
b21c9cb4 2752 OUTS (outf, uimm16 (hword));
4b7f6baa
CM		 2753 }
2754 else
b7d48530
NC		 2755 return 0;
2756
b21c9cb4 2757 /* And we print out the 32-bit value if it is a pointer. */
086134ec 2758 if (S == 0 && Z == 0)
b21c9cb4 2759 {
086134ec
BS		 2760 OUTS (outf, ";\t\t/* (");
2761 OUTS (outf, imm16d (hword));
2762 OUTS (outf, ")\t");
2763
b21c9cb4 2764 /* If it is an MMR, don't print the symbol. */
086134ec
BS		 2765 if (*pval < 0xFFC00000 && grp == 1)
2766 {
2767 OUTS (outf, regs (reg, grp));
2768 OUTS (outf, "=0x");
2769 OUTS (outf, huimm32e (*pval));
2770 }
b21c9cb4 2771 else
086134ec
BS		 2772 {
2773 OUTS (outf, regs (reg, grp));
2774 OUTS (outf, "=0x");
2775 OUTS (outf, huimm32e (*pval));
2776 OUTS (outf, "(");
2777 OUTS (outf, imm32 (*pval));
2778 OUTS (outf, ")");
2779 }
b21c9cb4
BS		 2780
2781 OUTS (outf, " */");
703ec4e8 2782 priv->comment = 1;
086134ec
BS		 2783 }
2784 if (S == 1 || Z == 1)
2785 {
602427c4
MF		 2786 OUTS (outf, ";\t\t/*\t\t");
2787 OUTS (outf, regs (reg, grp));
2788 OUTS (outf, "=0x");
2789 OUTS (outf, huimm32e (*pval));
2790 OUTS (outf, "(");
2791 OUTS (outf, imm32 (*pval));
2792 OUTS (outf, ") */");
703ec4e8 2793 priv->comment = 1;
b21c9cb4 2794 }
b7d48530 2795 return 4;
4b7f6baa
CM		 2796}
2797
2798static int
2799decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2800{
703ec4e8 2801 struct private *priv = outf->private_data;
b7d48530
NC		 2802 /* CALLa
2803 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2804 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
2805 |.lsw...........................................................|
2806 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2807 int S = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask);
2808 int lsw = ((iw1 >> 0) & 0xffff);
2809 int msw = ((iw0 >> 0) & 0xff);
2810
703ec4e8 2811 if (priv->parallel)
219b747a
MF		 2812 return 0;
2813
4b7f6baa 2814 if (S == 1)
086134ec 2815 OUTS (outf, "CALL 0x");
4b7f6baa 2816 else if (S == 0)
086134ec 2817 OUTS (outf, "JUMP.L 0x");
4b7f6baa 2818 else
b7d48530
NC		 2819 return 0;
2820
2821 OUTS (outf, pcrel24 (((msw) << 16) | (lsw)));
2822 return 4;
4b7f6baa
CM		 2823}
2824
2825static int
2826decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2827{
b7d48530
NC		 2828 /* LDSTidxI
2829 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2830 | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
2831 |.offset........................................................|
2832 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2833 int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask);
2834 int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask);
2835 int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask);
2836 int reg = ((iw0 >> (LDSTidxI_reg_bits - 16)) & LDSTidxI_reg_mask);
2837 int ptr = ((iw0 >> (LDSTidxI_ptr_bits - 16)) & LDSTidxI_ptr_mask);
2838 int offset = ((iw1 >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
2839
2840 if (W == 0 && sz == 0 && Z == 0)
2841 {
4b7f6baa 2842 OUTS (outf, dregs (reg));
086134ec 2843 OUTS (outf, " = [");
4b7f6baa 2844 OUTS (outf, pregs (ptr));
086134ec 2845 OUTS (outf, " + ");
4b7f6baa
CM		 2846 OUTS (outf, imm16s4 (offset));
2847 OUTS (outf, "]");
4b7f6baa
CM		 2848 }
2849 else if (W == 0 && sz == 0 && Z == 1)
2850 {
4b7f6baa 2851 OUTS (outf, pregs (reg));
086134ec 2852 OUTS (outf, " = [");
4b7f6baa 2853 OUTS (outf, pregs (ptr));
086134ec 2854 OUTS (outf, " + ");
4b7f6baa
CM		 2855 OUTS (outf, imm16s4 (offset));
2856 OUTS (outf, "]");
4b7f6baa
CM		 2857 }
2858 else if (W == 0 && sz == 1 && Z == 0)
2859 {
4b7f6baa 2860 OUTS (outf, dregs (reg));
086134ec 2861 OUTS (outf, " = W[");
4b7f6baa 2862 OUTS (outf, pregs (ptr));
086134ec 2863 OUTS (outf, " + ");
4b7f6baa
CM		 2864 OUTS (outf, imm16s2 (offset));
2865 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2866 }
2867 else if (W == 0 && sz == 1 && Z == 1)
2868 {
4b7f6baa 2869 OUTS (outf, dregs (reg));
086134ec 2870 OUTS (outf, " = W[");
4b7f6baa 2871 OUTS (outf, pregs (ptr));
086134ec 2872 OUTS (outf, " + ");
4b7f6baa 2873 OUTS (outf, imm16s2 (offset));
086134ec 2874 OUTS (outf, "] (X)");
4b7f6baa
CM		 2875 }
2876 else if (W == 0 && sz == 2 && Z == 0)
2877 {
4b7f6baa 2878 OUTS (outf, dregs (reg));
086134ec 2879 OUTS (outf, " = B[");
4b7f6baa 2880 OUTS (outf, pregs (ptr));
086134ec 2881 OUTS (outf, " + ");
4b7f6baa
CM		 2882 OUTS (outf, imm16 (offset));
2883 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2884 }
2885 else if (W == 0 && sz == 2 && Z == 1)
2886 {
4b7f6baa 2887 OUTS (outf, dregs (reg));
086134ec 2888 OUTS (outf, " = B[");
4b7f6baa 2889 OUTS (outf, pregs (ptr));
086134ec 2890 OUTS (outf, " + ");
4b7f6baa 2891 OUTS (outf, imm16 (offset));
086134ec 2892 OUTS (outf, "] (X)");
4b7f6baa
CM		 2893 }
2894 else if (W == 1 && sz == 0 && Z == 0)
2895 {
4b7f6baa
CM		 2896 OUTS (outf, "[");
2897 OUTS (outf, pregs (ptr));
086134ec 2898 OUTS (outf, " + ");
4b7f6baa 2899 OUTS (outf, imm16s4 (offset));
086134ec 2900 OUTS (outf, "] = ");
4b7f6baa 2901 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2902 }
2903 else if (W == 1 && sz == 0 && Z == 1)
2904 {
4b7f6baa
CM		 2905 OUTS (outf, "[");
2906 OUTS (outf, pregs (ptr));
086134ec 2907 OUTS (outf, " + ");
4b7f6baa 2908 OUTS (outf, imm16s4 (offset));
086134ec 2909 OUTS (outf, "] = ");
4b7f6baa 2910 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2911 }
2912 else if (W == 1 && sz == 1 && Z == 0)
2913 {
4b7f6baa
CM		 2914 OUTS (outf, "W[");
2915 OUTS (outf, pregs (ptr));
086134ec 2916 OUTS (outf, " + ");
4b7f6baa 2917 OUTS (outf, imm16s2 (offset));
086134ec 2918 OUTS (outf, "] = ");
4b7f6baa 2919 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2920 }
2921 else if (W == 1 && sz == 2 && Z == 0)
2922 {
4b7f6baa
CM		 2923 OUTS (outf, "B[");
2924 OUTS (outf, pregs (ptr));
086134ec 2925 OUTS (outf, " + ");
4b7f6baa 2926 OUTS (outf, imm16 (offset));
086134ec 2927 OUTS (outf, "] = ");
4b7f6baa 2928 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2929 }
2930 else
b7d48530
NC		 2931 return 0;
2932
2933 return 4;
4b7f6baa
CM		 2934}
2935
2936static int
2937decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2938{
703ec4e8 2939 struct private *priv = outf->private_data;
b7d48530
NC		 2940 /* linkage
2941 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2942 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
2943 |.framesize.....................................................|
2944 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2945 int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask);
2946 int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask);
2947
703ec4e8 2948 if (priv->parallel)
219b747a
MF		 2949 return 0;
2950
4b7f6baa
CM		 2951 if (R == 0)
2952 {
4b7f6baa
CM		 2953 OUTS (outf, "LINK ");
2954 OUTS (outf, uimm16s4 (framesize));
086134ec
BS		 2955 OUTS (outf, ";\t\t/* (");
2956 OUTS (outf, uimm16s4d (framesize));
2957 OUTS (outf, ") */");
703ec4e8 2958 priv->comment = 1;
4b7f6baa
CM		 2959 }
2960 else if (R == 1)
b7d48530 2961 OUTS (outf, "UNLINK");
4b7f6baa 2962 else
b7d48530
NC		 2963 return 0;
2964
2965 return 4;
4b7f6baa
CM		 2966}
2967
2968static int
2969decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2970{
b7d48530
NC		 2971 /* dsp32mac
2972 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2973 | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
2974 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2975 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2976 int op1 = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask);
2977 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2978 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2979 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
4b7f6baa 2980 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
b7d48530 2981 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
4b7f6baa
CM		 2982 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
2983 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
b7d48530
NC		 2984 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2985 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
2986 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
2987 int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask);
2988 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
2989 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
4b7f6baa
CM		 2990
2991 if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3)
2992 return 0;
2993
2994 if (op1 == 3 && MM)
2995 return 0;
2996
2997 if ((w1 || w0) && mmod == M_W32)
2998 return 0;
2999
ee171c8f 3000 if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0)
4b7f6baa
CM		 3001 return 0;
3002
3003 if (w1 == 1 || op1 != 3)
3004 {
3005 if (w1)
3006 OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
3007
3008 if (op1 == 3)
3009 OUTS (outf, " = A1");
3010 else
3011 {
3012 if (w1)
3013 OUTS (outf, " = (");
3014 decode_macfunc (1, op1, h01, h11, src0, src1, outf);
3015 if (w1)
3016 OUTS (outf, ")");
3017 }
3018
3019 if (w0 == 1 || op0 != 3)
3020 {
3021 if (MM)
3022 OUTS (outf, " (M)");
4b7f6baa
CM		 3023 OUTS (outf, ", ");
3024 }
3025 }
3026
3027 if (w0 == 1 || op0 != 3)
3028 {
67171547
MF		 3029 /* Clear MM option since it only matters for MAC1, and if we made
3030 it this far, we've already shown it or we want to ignore it. */
3031 MM = 0;
3032
4b7f6baa
CM		 3033 if (w0)
3034 OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
3035
3036 if (op0 == 3)
3037 OUTS (outf, " = A0");
3038 else
3039 {
3040 if (w0)
3041 OUTS (outf, " = (");
3042 decode_macfunc (0, op0, h00, h10, src0, src1, outf);
3043 if (w0)
3044 OUTS (outf, ")");
3045 }
3046 }
3047
3048 decode_optmode (mmod, MM, outf);
3049
3050 return 4;
3051}
3052
3053static int
3054decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3055{
b7d48530
NC		 3056 /* dsp32mult
3057 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3058 | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
3059 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
3060 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3061 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
3062 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
3063 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
4b7f6baa 3064 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
b7d48530 3065 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
4b7f6baa
CM		 3066 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
3067 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
b7d48530
NC		 3068 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
3069 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
3070 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
3071 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
3072 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
4b7f6baa
CM		 3073
3074 if (w1 == 0 && w0 == 0)
3075 return 0;
b7d48530 3076
4b7f6baa
CM		 3077 if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0)
3078 return 0;
b7d48530 3079
4b7f6baa
CM		 3080 if (w1)
3081 {
4db66394 3082 OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
4b7f6baa
CM		 3083 OUTS (outf, " = ");
3084 decode_multfunc (h01, h11, src0, src1, outf);
3085
3086 if (w0)
3087 {
3088 if (MM)
3089 OUTS (outf, " (M)");
3090 MM = 0;
3091 OUTS (outf, ", ");
3092 }
3093 }
3094
3095 if (w0)
3096 {
4db66394 3097 OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
4b7f6baa
CM		 3098 OUTS (outf, " = ");
3099 decode_multfunc (h00, h10, src0, src1, outf);
3100 }
3101
3102 decode_optmode (mmod, MM, outf);
3103 return 4;
3104}
3105
3106static int
3107decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3108{
b7d48530
NC		 3109 /* dsp32alu
3110 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3111 | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
3112 |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
3113 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 3114 int s = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask);
3115 int x = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask);
3116 int aop = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask);
3117 int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask);
3118 int src1 = ((iw1 >> DSP32Alu_src1_bits) & DSP32Alu_src1_mask);
3119 int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask);
3120 int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask);
3121 int HL = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask);
3122 int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask);
3123
3124 if (aop == 0 && aopcde == 9 && HL == 0 && s == 0)
3125 {
086134ec 3126 OUTS (outf, "A0.L = ");
4b7f6baa 3127 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3128 }
3129 else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0)
3130 {
086134ec 3131 OUTS (outf, "A1.H = ");
4b7f6baa 3132 OUTS (outf, dregs_hi (src0));
4b7f6baa
CM		 3133 }
3134 else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0)
3135 {
086134ec 3136 OUTS (outf, "A1.L = ");
4b7f6baa 3137 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3138 }
3139 else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0)
3140 {
086134ec 3141 OUTS (outf, "A0.H = ");
4b7f6baa 3142 OUTS (outf, dregs_hi (src0));
4b7f6baa
CM		 3143 }
3144 else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5)
3145 {
4b7f6baa 3146 OUTS (outf, dregs_hi (dst0));
086134ec 3147 OUTS (outf, " = ");
4b7f6baa 3148 OUTS (outf, dregs (src0));
086134ec 3149 OUTS (outf, " - ");
4b7f6baa 3150 OUTS (outf, dregs (src1));
086134ec 3151 OUTS (outf, " (RND20)");
4b7f6baa
CM		 3152 }
3153 else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5)
3154 {
4b7f6baa 3155 OUTS (outf, dregs_hi (dst0));
086134ec 3156 OUTS (outf, " = ");
4b7f6baa 3157 OUTS (outf, dregs (src0));
086134ec 3158 OUTS (outf, " + ");
4b7f6baa 3159 OUTS (outf, dregs (src1));
086134ec 3160 OUTS (outf, " (RND20)");
4b7f6baa
CM		 3161 }
3162 else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5)
3163 {
4b7f6baa 3164 OUTS (outf, dregs_lo (dst0));
086134ec 3165 OUTS (outf, " = ");
4b7f6baa 3166 OUTS (outf, dregs (src0));
086134ec 3167 OUTS (outf, " - ");
4b7f6baa 3168 OUTS (outf, dregs (src1));
086134ec 3169 OUTS (outf, " (RND12)");
4b7f6baa
CM		 3170 }
3171 else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5)
3172 {
4b7f6baa 3173 OUTS (outf, dregs_lo (dst0));
086134ec 3174 OUTS (outf, " = ");
4b7f6baa 3175 OUTS (outf, dregs (src0));
086134ec 3176 OUTS (outf, " + ");
4b7f6baa 3177 OUTS (outf, dregs (src1));
086134ec 3178 OUTS (outf, " (RND12)");
4b7f6baa
CM		 3179 }
3180 else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5)
3181 {
4b7f6baa 3182 OUTS (outf, dregs_lo (dst0));
086134ec 3183 OUTS (outf, " = ");
4b7f6baa 3184 OUTS (outf, dregs (src0));
086134ec 3185 OUTS (outf, " - ");
4b7f6baa 3186 OUTS (outf, dregs (src1));
086134ec 3187 OUTS (outf, " (RND20)");
4b7f6baa
CM		 3188 }
3189 else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5)
3190 {
4b7f6baa 3191 OUTS (outf, dregs_hi (dst0));
086134ec 3192 OUTS (outf, " = ");
4b7f6baa 3193 OUTS (outf, dregs (src0));
086134ec 3194 OUTS (outf, " + ");
4b7f6baa 3195 OUTS (outf, dregs (src1));
086134ec 3196 OUTS (outf, " (RND12)");
4b7f6baa
CM		 3197 }
3198 else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5)
3199 {
4b7f6baa 3200 OUTS (outf, dregs_lo (dst0));
086134ec 3201 OUTS (outf, " = ");
4b7f6baa 3202 OUTS (outf, dregs (src0));
086134ec 3203 OUTS (outf, " + ");
4b7f6baa 3204 OUTS (outf, dregs (src1));
086134ec 3205 OUTS (outf, " (RND20)");
4b7f6baa
CM		 3206 }
3207 else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5)
3208 {
4b7f6baa 3209 OUTS (outf, dregs_hi (dst0));
086134ec 3210 OUTS (outf, " = ");
4b7f6baa 3211 OUTS (outf, dregs (src0));
086134ec 3212 OUTS (outf, " - ");
4b7f6baa 3213 OUTS (outf, dregs (src1));
086134ec 3214 OUTS (outf, " (RND12)");
4b7f6baa
CM		 3215 }
3216 else if (HL == 1 && aop == 0 && aopcde == 2)
3217 {
4b7f6baa 3218 OUTS (outf, dregs_hi (dst0));
086134ec 3219 OUTS (outf, " = ");
4b7f6baa 3220 OUTS (outf, dregs_lo (src0));
086134ec 3221 OUTS (outf, " + ");
4b7f6baa 3222 OUTS (outf, dregs_lo (src1));
4b7f6baa 3223 amod1 (s, x, outf);
4b7f6baa
CM		 3224 }
3225 else if (HL == 1 && aop == 1 && aopcde == 2)
3226 {
4b7f6baa 3227 OUTS (outf, dregs_hi (dst0));
086134ec 3228 OUTS (outf, " = ");
4b7f6baa 3229 OUTS (outf, dregs_lo (src0));
086134ec 3230 OUTS (outf, " + ");
4b7f6baa 3231 OUTS (outf, dregs_hi (src1));
4b7f6baa 3232 amod1 (s, x, outf);
4b7f6baa
CM		 3233 }
3234 else if (HL == 1 && aop == 2 && aopcde == 2)
3235 {
4b7f6baa 3236 OUTS (outf, dregs_hi (dst0));
086134ec 3237 OUTS (outf, " = ");
4b7f6baa 3238 OUTS (outf, dregs_hi (src0));
086134ec 3239 OUTS (outf, " + ");
4b7f6baa 3240 OUTS (outf, dregs_lo (src1));
4b7f6baa 3241 amod1 (s, x, outf);
4b7f6baa
CM		 3242 }
3243 else if (HL == 1 && aop == 3 && aopcde == 2)
3244 {
4b7f6baa 3245 OUTS (outf, dregs_hi (dst0));
086134ec 3246 OUTS (outf, " = ");
4b7f6baa 3247 OUTS (outf, dregs_hi (src0));
086134ec 3248 OUTS (outf, " + ");
4b7f6baa 3249 OUTS (outf, dregs_hi (src1));
4b7f6baa 3250 amod1 (s, x, outf);
4b7f6baa
CM		 3251 }
3252 else if (HL == 0 && aop == 0 && aopcde == 3)
3253 {
4b7f6baa 3254 OUTS (outf, dregs_lo (dst0));
086134ec 3255 OUTS (outf, " = ");
4b7f6baa 3256 OUTS (outf, dregs_lo (src0));
086134ec 3257 OUTS (outf, " - ");
4b7f6baa 3258 OUTS (outf, dregs_lo (src1));
4b7f6baa 3259 amod1 (s, x, outf);
4b7f6baa
CM		 3260 }
3261 else if (HL == 0 && aop == 1 && aopcde == 3)
3262 {
4b7f6baa 3263 OUTS (outf, dregs_lo (dst0));
086134ec 3264 OUTS (outf, " = ");
4b7f6baa 3265 OUTS (outf, dregs_lo (src0));
086134ec 3266 OUTS (outf, " - ");
4b7f6baa 3267 OUTS (outf, dregs_hi (src1));
4b7f6baa 3268 amod1 (s, x, outf);
4b7f6baa
CM		 3269 }
3270 else if (HL == 0 && aop == 3 && aopcde == 2)
3271 {
4b7f6baa 3272 OUTS (outf, dregs_lo (dst0));
086134ec 3273 OUTS (outf, " = ");
4b7f6baa 3274 OUTS (outf, dregs_hi (src0));
086134ec 3275 OUTS (outf, " + ");
4b7f6baa 3276 OUTS (outf, dregs_hi (src1));
4b7f6baa 3277 amod1 (s, x, outf);
4b7f6baa
CM		 3278 }
3279 else if (HL == 1 && aop == 0 && aopcde == 3)
3280 {
4b7f6baa 3281 OUTS (outf, dregs_hi (dst0));
086134ec 3282 OUTS (outf, " = ");
4b7f6baa 3283 OUTS (outf, dregs_lo (src0));
086134ec 3284 OUTS (outf, " - ");
4b7f6baa 3285 OUTS (outf, dregs_lo (src1));
4b7f6baa 3286 amod1 (s, x, outf);
4b7f6baa
CM		 3287 }
3288 else if (HL == 1 && aop == 1 && aopcde == 3)
3289 {
4b7f6baa 3290 OUTS (outf, dregs_hi (dst0));
086134ec 3291 OUTS (outf, " = ");
4b7f6baa 3292 OUTS (outf, dregs_lo (src0));
086134ec 3293 OUTS (outf, " - ");
4b7f6baa 3294 OUTS (outf, dregs_hi (src1));
4b7f6baa 3295 amod1 (s, x, outf);
4b7f6baa
CM		 3296 }
3297 else if (HL == 1 && aop == 2 && aopcde == 3)
3298 {
4b7f6baa 3299 OUTS (outf, dregs_hi (dst0));
086134ec 3300 OUTS (outf, " = ");
4b7f6baa 3301 OUTS (outf, dregs_hi (src0));
086134ec 3302 OUTS (outf, " - ");
4b7f6baa 3303 OUTS (outf, dregs_lo (src1));
4b7f6baa 3304 amod1 (s, x, outf);
4b7f6baa
CM		 3305 }
3306 else if (HL == 1 && aop == 3 && aopcde == 3)
3307 {
4b7f6baa 3308 OUTS (outf, dregs_hi (dst0));
086134ec 3309 OUTS (outf, " = ");
4b7f6baa 3310 OUTS (outf, dregs_hi (src0));
086134ec 3311 OUTS (outf, " - ");
4b7f6baa 3312 OUTS (outf, dregs_hi (src1));
4b7f6baa 3313 amod1 (s, x, outf);
4b7f6baa
CM		 3314 }
3315 else if (HL == 0 && aop == 2 && aopcde == 2)
3316 {
4b7f6baa 3317 OUTS (outf, dregs_lo (dst0));
086134ec 3318 OUTS (outf, " = ");
4b7f6baa 3319 OUTS (outf, dregs_hi (src0));
086134ec 3320 OUTS (outf, " + ");
4b7f6baa 3321 OUTS (outf, dregs_lo (src1));
4b7f6baa 3322 amod1 (s, x, outf);
4b7f6baa
CM		 3323 }
3324 else if (HL == 0 && aop == 1 && aopcde == 2)
3325 {
4b7f6baa 3326 OUTS (outf, dregs_lo (dst0));
086134ec 3327 OUTS (outf, " = ");
4b7f6baa 3328 OUTS (outf, dregs_lo (src0));
086134ec 3329 OUTS (outf, " + ");
4b7f6baa 3330 OUTS (outf, dregs_hi (src1));
4b7f6baa 3331 amod1 (s, x, outf);
4b7f6baa
CM		 3332 }
3333 else if (HL == 0 && aop == 2 && aopcde == 3)
3334 {
4b7f6baa 3335 OUTS (outf, dregs_lo (dst0));
086134ec 3336 OUTS (outf, " = ");
4b7f6baa 3337 OUTS (outf, dregs_hi (src0));
086134ec 3338 OUTS (outf, " - ");
4b7f6baa 3339 OUTS (outf, dregs_lo (src1));
4b7f6baa 3340 amod1 (s, x, outf);
4b7f6baa
CM		 3341 }
3342 else if (HL == 0 && aop == 3 && aopcde == 3)
3343 {
4b7f6baa 3344 OUTS (outf, dregs_lo (dst0));
086134ec 3345 OUTS (outf, " = ");
4b7f6baa 3346 OUTS (outf, dregs_hi (src0));
086134ec 3347 OUTS (outf, " - ");
4b7f6baa 3348 OUTS (outf, dregs_hi (src1));
4b7f6baa 3349 amod1 (s, x, outf);
4b7f6baa
CM		 3350 }
3351 else if (HL == 0 && aop == 0 && aopcde == 2)
3352 {
4b7f6baa 3353 OUTS (outf, dregs_lo (dst0));
086134ec 3354 OUTS (outf, " = ");
4b7f6baa 3355 OUTS (outf, dregs_lo (src0));
086134ec 3356 OUTS (outf, " + ");
4b7f6baa 3357 OUTS (outf, dregs_lo (src1));
4b7f6baa 3358 amod1 (s, x, outf);
4b7f6baa
CM		 3359 }
3360 else if (aop == 0 && aopcde == 9 && s == 1)
3361 {
086134ec 3362 OUTS (outf, "A0 = ");
4b7f6baa 3363 OUTS (outf, dregs (src0));
4b7f6baa
CM		 3364 }
3365 else if (aop == 3 && aopcde == 11 && s == 0)
086134ec 3366 OUTS (outf, "A0 -= A1");
b7d48530 3367
4b7f6baa 3368 else if (aop == 3 && aopcde == 11 && s == 1)
086134ec 3369 OUTS (outf, "A0 -= A1 (W32)");
b7d48530 3370
4b7f6baa
CM		 3371 else if (aop == 1 && aopcde == 22 && HL == 1)
3372 {
4b7f6baa 3373 OUTS (outf, dregs (dst0));
086134ec 3374 OUTS (outf, " = BYTEOP2P (");
4b7f6baa
CM		 3375 OUTS (outf, dregs (src0 + 1));
3376 OUTS (outf, ":");
086134ec
BS		 3377 OUTS (outf, imm5d (src0));
3378 OUTS (outf, ", ");
4b7f6baa
CM		 3379 OUTS (outf, dregs (src1 + 1));
3380 OUTS (outf, ":");
086134ec
BS		 3381 OUTS (outf, imm5d (src1));
3382 OUTS (outf, ") (TH");
4b7f6baa
CM		 3383 if (s == 1)
3384 OUTS (outf, ", R)");
3385 else
3386 OUTS (outf, ")");
4b7f6baa
CM		 3387 }
3388 else if (aop == 1 && aopcde == 22 && HL == 0)
3389 {
4b7f6baa 3390 OUTS (outf, dregs (dst0));
086134ec 3391 OUTS (outf, " = BYTEOP2P (");
4b7f6baa
CM		 3392 OUTS (outf, dregs (src0 + 1));
3393 OUTS (outf, ":");
086134ec
BS		 3394 OUTS (outf, imm5d (src0));
3395 OUTS (outf, ", ");
4b7f6baa
CM		 3396 OUTS (outf, dregs (src1 + 1));
3397 OUTS (outf, ":");
086134ec
BS		 3398 OUTS (outf, imm5d (src1));
3399 OUTS (outf, ") (TL");
4b7f6baa
CM		 3400 if (s == 1)
3401 OUTS (outf, ", R)");
3402 else
3403 OUTS (outf, ")");
4b7f6baa
CM		 3404 }
3405 else if (aop == 0 && aopcde == 22 && HL == 1)
3406 {
4b7f6baa 3407 OUTS (outf, dregs (dst0));
086134ec 3408 OUTS (outf, " = BYTEOP2P (");
4b7f6baa
CM		 3409 OUTS (outf, dregs (src0 + 1));
3410 OUTS (outf, ":");
086134ec
BS		 3411 OUTS (outf, imm5d (src0));
3412 OUTS (outf, ", ");
4b7f6baa
CM		 3413 OUTS (outf, dregs (src1 + 1));
3414 OUTS (outf, ":");
086134ec
BS		 3415 OUTS (outf, imm5d (src1));
3416 OUTS (outf, ") (RNDH");
4b7f6baa
CM		 3417 if (s == 1)
3418 OUTS (outf, ", R)");
3419 else
3420 OUTS (outf, ")");
4b7f6baa
CM		 3421 }
3422 else if (aop == 0 && aopcde == 22 && HL == 0)
3423 {
4b7f6baa 3424 OUTS (outf, dregs (dst0));
086134ec 3425 OUTS (outf, " = BYTEOP2P (");
4b7f6baa
CM		 3426 OUTS (outf, dregs (src0 + 1));
3427 OUTS (outf, ":");
086134ec
BS		 3428 OUTS (outf, imm5d (src0));
3429 OUTS (outf, ", ");
4b7f6baa
CM		 3430 OUTS (outf, dregs (src1 + 1));
3431 OUTS (outf, ":");
086134ec
BS		 3432 OUTS (outf, imm5d (src1));
3433 OUTS (outf, ") (RNDL");
4b7f6baa
CM		 3434 if (s == 1)
3435 OUTS (outf, ", R)");
3436 else
3437 OUTS (outf, ")");
4b7f6baa
CM		 3438 }
3439 else if (aop == 0 && s == 0 && aopcde == 8)
086134ec 3440 OUTS (outf, "A0 = 0");
b7d48530 3441
4b7f6baa 3442 else if (aop == 0 && s == 1 && aopcde == 8)
086134ec 3443 OUTS (outf, "A0 = A0 (S)");
b7d48530 3444
4b7f6baa 3445 else if (aop == 1 && s == 0 && aopcde == 8)
086134ec 3446 OUTS (outf, "A1 = 0");
b7d48530 3447
4b7f6baa 3448 else if (aop == 1 && s == 1 && aopcde == 8)
086134ec 3449 OUTS (outf, "A1 = A1 (S)");
b7d48530 3450
4b7f6baa 3451 else if (aop == 2 && s == 0 && aopcde == 8)
086134ec 3452 OUTS (outf, "A1 = A0 = 0");
b7d48530 3453
4b7f6baa 3454 else if (aop == 2 && s == 1 && aopcde == 8)
086134ec 3455 OUTS (outf, "A1 = A1 (S), A0 = A0 (S)");
b7d48530 3456
4b7f6baa 3457 else if (aop == 3 && s == 0 && aopcde == 8)
086134ec 3458 OUTS (outf, "A0 = A1");
b7d48530 3459
4b7f6baa 3460 else if (aop == 3 && s == 1 && aopcde == 8)
086134ec 3461 OUTS (outf, "A1 = A0");
b7d48530 3462
4b7f6baa
CM		 3463 else if (aop == 1 && aopcde == 9 && s == 0)
3464 {
086134ec 3465 OUTS (outf, "A0.X = ");
4b7f6baa 3466 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3467 }
3468 else if (aop == 1 && HL == 0 && aopcde == 11)
3469 {
4b7f6baa 3470 OUTS (outf, dregs_lo (dst0));
086134ec 3471 OUTS (outf, " = (A0 += A1)");
4b7f6baa
CM		 3472 }
3473 else if (aop == 3 && HL == 0 && aopcde == 16)
13c02f06 3474 OUTS (outf, "A1 = ABS A1, A0 = ABS A0");
b7d48530 3475
4b7f6baa
CM		 3476 else if (aop == 0 && aopcde == 23 && HL == 1)
3477 {
4b7f6baa 3478 OUTS (outf, dregs (dst0));
086134ec 3479 OUTS (outf, " = BYTEOP3P (");
4b7f6baa
CM		 3480 OUTS (outf, dregs (src0 + 1));
3481 OUTS (outf, ":");
086134ec
BS		 3482 OUTS (outf, imm5d (src0));
3483 OUTS (outf, ", ");
4b7f6baa
CM		 3484 OUTS (outf, dregs (src1 + 1));
3485 OUTS (outf, ":");
086134ec
BS		 3486 OUTS (outf, imm5d (src1));
3487 OUTS (outf, ") (HI");
4b7f6baa
CM		 3488 if (s == 1)
3489 OUTS (outf, ", R)");
3490 else
3491 OUTS (outf, ")");
4b7f6baa
CM		 3492 }
3493 else if (aop == 3 && aopcde == 9 && s == 0)
3494 {
086134ec 3495 OUTS (outf, "A1.X = ");
4b7f6baa 3496 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3497 }
3498 else if (aop == 1 && HL == 1 && aopcde == 16)
086134ec 3499 OUTS (outf, "A1 = ABS A1");
b7d48530 3500
4b7f6baa 3501 else if (aop == 0 && HL == 1 && aopcde == 16)
086134ec 3502 OUTS (outf, "A1 = ABS A0");
b7d48530 3503
4b7f6baa
CM		 3504 else if (aop == 2 && aopcde == 9 && s == 1)
3505 {
086134ec 3506 OUTS (outf, "A1 = ");
4b7f6baa 3507 OUTS (outf, dregs (src0));
4b7f6baa
CM		 3508 }
3509 else if (HL == 0 && aop == 3 && aopcde == 12)
3510 {
4b7f6baa 3511 OUTS (outf, dregs_lo (dst0));
086134ec 3512 OUTS (outf, " = ");
4b7f6baa 3513 OUTS (outf, dregs (src0));
086134ec 3514 OUTS (outf, " (RND)");
4b7f6baa
CM		 3515 }
3516 else if (aop == 1 && HL == 0 && aopcde == 16)
086134ec 3517 OUTS (outf, "A0 = ABS A1");
b7d48530 3518
4b7f6baa 3519 else if (aop == 0 && HL == 0 && aopcde == 16)
086134ec 3520 OUTS (outf, "A0 = ABS A0");
b7d48530 3521
4b7f6baa
CM		 3522 else if (aop == 3 && HL == 0 && aopcde == 15)
3523 {
4b7f6baa 3524 OUTS (outf, dregs (dst0));
086134ec 3525 OUTS (outf, " = -");
4b7f6baa 3526 OUTS (outf, dregs (src0));
086134ec 3527 OUTS (outf, " (V)");
4b7f6baa
CM		 3528 }
3529 else if (aop == 3 && s == 1 && HL == 0 && aopcde == 7)
3530 {
4b7f6baa 3531 OUTS (outf, dregs (dst0));
086134ec 3532 OUTS (outf, " = -");
4b7f6baa 3533 OUTS (outf, dregs (src0));
086134ec 3534 OUTS (outf, " (S)");
4b7f6baa
CM		 3535 }
3536 else if (aop == 3 && s == 0 && HL == 0 && aopcde == 7)
3537 {
4b7f6baa 3538 OUTS (outf, dregs (dst0));
086134ec 3539 OUTS (outf, " = -");
4b7f6baa 3540 OUTS (outf, dregs (src0));
086134ec 3541 OUTS (outf, " (NS)");
4b7f6baa
CM		 3542 }
3543 else if (aop == 1 && HL == 1 && aopcde == 11)
3544 {
4b7f6baa 3545 OUTS (outf, dregs_hi (dst0));
086134ec 3546 OUTS (outf, " = (A0 += A1)");
4b7f6baa
CM		 3547 }
3548 else if (aop == 2 && aopcde == 11 && s == 0)
086134ec 3549 OUTS (outf, "A0 += A1");
b7d48530 3550
4b7f6baa 3551 else if (aop == 2 && aopcde == 11 && s == 1)
086134ec 3552 OUTS (outf, "A0 += A1 (W32)");
b7d48530 3553
4b7f6baa 3554 else if (aop == 3 && HL == 0 && aopcde == 14)
086134ec 3555 OUTS (outf, "A1 = -A1, A0 = -A0");
b7d48530 3556
4b7f6baa
CM		 3557 else if (HL == 1 && aop == 3 && aopcde == 12)
3558 {
4b7f6baa 3559 OUTS (outf, dregs_hi (dst0));
086134ec 3560 OUTS (outf, " = ");
4b7f6baa 3561 OUTS (outf, dregs (src0));
086134ec 3562 OUTS (outf, " (RND)");
4b7f6baa
CM		 3563 }
3564 else if (aop == 0 && aopcde == 23 && HL == 0)
3565 {
4b7f6baa 3566 OUTS (outf, dregs (dst0));
086134ec 3567 OUTS (outf, " = BYTEOP3P (");
4b7f6baa
CM		 3568 OUTS (outf, dregs (src0 + 1));
3569 OUTS (outf, ":");
086134ec
BS		 3570 OUTS (outf, imm5d (src0));
3571 OUTS (outf, ", ");
4b7f6baa
CM		 3572 OUTS (outf, dregs (src1 + 1));
3573 OUTS (outf, ":");
086134ec
BS		 3574 OUTS (outf, imm5d (src1));
3575 OUTS (outf, ") (LO");
4b7f6baa
CM		 3576 if (s == 1)
3577 OUTS (outf, ", R)");
3578 else
3579 OUTS (outf, ")");
4b7f6baa
CM		 3580 }
3581 else if (aop == 0 && HL == 0 && aopcde == 14)
086134ec 3582 OUTS (outf, "A0 = -A0");
b7d48530 3583
4b7f6baa 3584 else if (aop == 1 && HL == 0 && aopcde == 14)
086134ec 3585 OUTS (outf, "A0 = -A1");
b7d48530 3586
4b7f6baa 3587 else if (aop == 0 && HL == 1 && aopcde == 14)
086134ec 3588 OUTS (outf, "A1 = -A0");
b7d48530 3589
4b7f6baa 3590 else if (aop == 1 && HL == 1 && aopcde == 14)
086134ec 3591 OUTS (outf, "A1 = -A1");
b7d48530 3592
4b7f6baa
CM		 3593 else if (aop == 0 && aopcde == 12)
3594 {
4b7f6baa 3595 OUTS (outf, dregs_hi (dst0));
086134ec 3596 OUTS (outf, " = ");
4b7f6baa 3597 OUTS (outf, dregs_lo (dst0));
086134ec 3598 OUTS (outf, " = SIGN (");
4b7f6baa 3599 OUTS (outf, dregs_hi (src0));
086134ec 3600 OUTS (outf, ") * ");
4b7f6baa 3601 OUTS (outf, dregs_hi (src1));
086134ec 3602 OUTS (outf, " + SIGN (");
4b7f6baa 3603 OUTS (outf, dregs_lo (src0));
086134ec 3604 OUTS (outf, ") * ");
4b7f6baa 3605 OUTS (outf, dregs_lo (src1));
4b7f6baa
CM		 3606 }
3607 else if (aop == 2 && aopcde == 0)
3608 {
4b7f6baa 3609 OUTS (outf, dregs (dst0));
086134ec 3610 OUTS (outf, " = ");
4b7f6baa 3611 OUTS (outf, dregs (src0));
086134ec 3612 OUTS (outf, " -|+ ");
4b7f6baa 3613 OUTS (outf, dregs (src1));
4b7f6baa 3614 amod0 (s, x, outf);
4b7f6baa
CM		 3615 }
3616 else if (aop == 1 && aopcde == 12)
3617 {
4b7f6baa 3618 OUTS (outf, dregs (dst1));
086134ec 3619 OUTS (outf, " = A1.L + A1.H, ");
4b7f6baa 3620 OUTS (outf, dregs (dst0));
086134ec 3621 OUTS (outf, " = A0.L + A0.H");
4b7f6baa
CM		 3622 }
3623 else if (aop == 2 && aopcde == 4)
3624 {
4b7f6baa 3625 OUTS (outf, dregs (dst1));
086134ec 3626 OUTS (outf, " = ");
4b7f6baa 3627 OUTS (outf, dregs (src0));
086134ec 3628 OUTS (outf, " + ");
4b7f6baa 3629 OUTS (outf, dregs (src1));
086134ec 3630 OUTS (outf, ", ");
4b7f6baa 3631 OUTS (outf, dregs (dst0));
086134ec 3632 OUTS (outf, " = ");
4b7f6baa 3633 OUTS (outf, dregs (src0));
086134ec 3634 OUTS (outf, " - ");
4b7f6baa 3635 OUTS (outf, dregs (src1));
4b7f6baa 3636 amod1 (s, x, outf);
4b7f6baa
CM		 3637 }
3638 else if (HL == 0 && aopcde == 1)
3639 {
4b7f6baa 3640 OUTS (outf, dregs (dst1));
086134ec 3641 OUTS (outf, " = ");
4b7f6baa 3642 OUTS (outf, dregs (src0));
086134ec 3643 OUTS (outf, " +|+ ");
4b7f6baa 3644 OUTS (outf, dregs (src1));
086134ec 3645 OUTS (outf, ", ");
4b7f6baa 3646 OUTS (outf, dregs (dst0));
086134ec 3647 OUTS (outf, " = ");
4b7f6baa 3648 OUTS (outf, dregs (src0));
086134ec 3649 OUTS (outf, " -|- ");
4b7f6baa
CM		 3650 OUTS (outf, dregs (src1));
3651 amod0amod2 (s, x, aop, outf);
4b7f6baa
CM		 3652 }
3653 else if (aop == 0 && aopcde == 11)
3654 {
4b7f6baa 3655 OUTS (outf, dregs (dst0));
086134ec 3656 OUTS (outf, " = (A0 += A1)");
4b7f6baa
CM		 3657 }
3658 else if (aop == 0 && aopcde == 10)
3659 {
4b7f6baa 3660 OUTS (outf, dregs_lo (dst0));
086134ec 3661 OUTS (outf, " = A0.X");
4b7f6baa
CM		 3662 }
3663 else if (aop == 1 && aopcde == 10)
3664 {
4b7f6baa 3665 OUTS (outf, dregs_lo (dst0));
086134ec 3666 OUTS (outf, " = A1.X");
4b7f6baa
CM		 3667 }
3668 else if (aop == 1 && aopcde == 0)
3669 {
4b7f6baa 3670 OUTS (outf, dregs (dst0));
086134ec 3671 OUTS (outf, " = ");
4b7f6baa 3672 OUTS (outf, dregs (src0));
086134ec 3673 OUTS (outf, " +|- ");
4b7f6baa 3674 OUTS (outf, dregs (src1));
4b7f6baa 3675 amod0 (s, x, outf);
4b7f6baa
CM		 3676 }
3677 else if (aop == 3 && aopcde == 0)
3678 {
4b7f6baa 3679 OUTS (outf, dregs (dst0));
086134ec 3680 OUTS (outf, " = ");
4b7f6baa 3681 OUTS (outf, dregs (src0));
086134ec 3682 OUTS (outf, " -|- ");
4b7f6baa 3683 OUTS (outf, dregs (src1));
4b7f6baa 3684 amod0 (s, x, outf);
4b7f6baa
CM		 3685 }
3686 else if (aop == 1 && aopcde == 4)
3687 {
4b7f6baa 3688 OUTS (outf, dregs (dst0));
086134ec 3689 OUTS (outf, " = ");
4b7f6baa 3690 OUTS (outf, dregs (src0));
086134ec 3691 OUTS (outf, " - ");
4b7f6baa 3692 OUTS (outf, dregs (src1));
4b7f6baa 3693 amod1 (s, x, outf);
4b7f6baa
CM		 3694 }
3695 else if (aop == 0 && aopcde == 17)
3696 {
4b7f6baa 3697 OUTS (outf, dregs (dst1));
086134ec 3698 OUTS (outf, " = A1 + A0, ");
4b7f6baa 3699 OUTS (outf, dregs (dst0));
086134ec 3700 OUTS (outf, " = A1 - A0");
4b7f6baa 3701 amod1 (s, x, outf);
4b7f6baa
CM		 3702 }
3703 else if (aop == 1 && aopcde == 17)
3704 {
4b7f6baa 3705 OUTS (outf, dregs (dst1));
086134ec 3706 OUTS (outf, " = A0 + A1, ");
4b7f6baa 3707 OUTS (outf, dregs (dst0));
086134ec 3708 OUTS (outf, " = A0 - A1");
4b7f6baa 3709 amod1 (s, x, outf);
4b7f6baa
CM		 3710 }
3711 else if (aop == 0 && aopcde == 18)
3712 {
086134ec 3713 OUTS (outf, "SAA (");
4b7f6baa
CM		 3714 OUTS (outf, dregs (src0 + 1));
3715 OUTS (outf, ":");
086134ec
BS		 3716 OUTS (outf, imm5d (src0));
3717 OUTS (outf, ", ");
4b7f6baa
CM		 3718 OUTS (outf, dregs (src1 + 1));
3719 OUTS (outf, ":");
086134ec
BS		 3720 OUTS (outf, imm5d (src1));
3721 OUTS (outf, ")");
4b7f6baa 3722 aligndir (s, outf);
4b7f6baa
CM		 3723 }
3724 else if (aop == 3 && aopcde == 18)
b7d48530
NC		 3725 OUTS (outf, "DISALGNEXCPT");
3726
4b7f6baa
CM		 3727 else if (aop == 0 && aopcde == 20)
3728 {
4b7f6baa 3729 OUTS (outf, dregs (dst0));
086134ec 3730 OUTS (outf, " = BYTEOP1P (");
4b7f6baa
CM		 3731 OUTS (outf, dregs (src0 + 1));
3732 OUTS (outf, ":");
086134ec
BS		 3733 OUTS (outf, imm5d (src0));
3734 OUTS (outf, ", ");
4b7f6baa
CM		 3735 OUTS (outf, dregs (src1 + 1));
3736 OUTS (outf, ":");
086134ec 3737 OUTS (outf, imm5d (src1));
4b7f6baa
CM		 3738 OUTS (outf, ")");
3739 aligndir (s, outf);
4b7f6baa
CM		 3740 }
3741 else if (aop == 1 && aopcde == 20)
3742 {
4b7f6baa 3743 OUTS (outf, dregs (dst0));
086134ec 3744 OUTS (outf, " = BYTEOP1P (");
4b7f6baa
CM		 3745 OUTS (outf, dregs (src0 + 1));
3746 OUTS (outf, ":");
086134ec
BS		 3747 OUTS (outf, imm5d (src0));
3748 OUTS (outf, ", ");
4b7f6baa
CM		 3749 OUTS (outf, dregs (src1 + 1));
3750 OUTS (outf, ":");
086134ec
BS		 3751 OUTS (outf, imm5d (src1));
3752 OUTS (outf, ") (T");
4b7f6baa
CM		 3753 if (s == 1)
3754 OUTS (outf, ", R)");
3755 else
3756 OUTS (outf, ")");
4b7f6baa
CM		 3757 }
3758 else if (aop == 0 && aopcde == 21)
3759 {
4b7f6baa
CM		 3760 OUTS (outf, "(");
3761 OUTS (outf, dregs (dst1));
086134ec 3762 OUTS (outf, ", ");
4b7f6baa 3763 OUTS (outf, dregs (dst0));
086134ec 3764 OUTS (outf, ") = BYTEOP16P (");
4b7f6baa
CM		 3765 OUTS (outf, dregs (src0 + 1));
3766 OUTS (outf, ":");
086134ec
BS		 3767 OUTS (outf, imm5d (src0));
3768 OUTS (outf, ", ");
4b7f6baa
CM		 3769 OUTS (outf, dregs (src1 + 1));
3770 OUTS (outf, ":");
086134ec
BS		 3771 OUTS (outf, imm5d (src1));
3772 OUTS (outf, ")");
4b7f6baa 3773 aligndir (s, outf);
4b7f6baa
CM		 3774 }
3775 else if (aop == 1 && aopcde == 21)
3776 {
4b7f6baa
CM		 3777 OUTS (outf, "(");
3778 OUTS (outf, dregs (dst1));
086134ec 3779 OUTS (outf, ", ");
4b7f6baa 3780 OUTS (outf, dregs (dst0));
086134ec 3781 OUTS (outf, ") = BYTEOP16M (");
4b7f6baa
CM		 3782 OUTS (outf, dregs (src0 + 1));
3783 OUTS (outf, ":");
086134ec
BS		 3784 OUTS (outf, imm5d (src0));
3785 OUTS (outf, ", ");
4b7f6baa
CM		 3786 OUTS (outf, dregs (src1 + 1));
3787 OUTS (outf, ":");
086134ec
BS		 3788 OUTS (outf, imm5d (src1));
3789 OUTS (outf, ")");
4b7f6baa 3790 aligndir (s, outf);
4b7f6baa
CM		 3791 }
3792 else if (aop == 2 && aopcde == 7)
3793 {
4b7f6baa 3794 OUTS (outf, dregs (dst0));
086134ec 3795 OUTS (outf, " = ABS ");
4b7f6baa 3796 OUTS (outf, dregs (src0));
4b7f6baa
CM		 3797 }
3798 else if (aop == 1 && aopcde == 7)
3799 {
4b7f6baa 3800 OUTS (outf, dregs (dst0));
086134ec 3801 OUTS (outf, " = MIN (");
4b7f6baa 3802 OUTS (outf, dregs (src0));
086134ec 3803 OUTS (outf, ", ");
4b7f6baa
CM		 3804 OUTS (outf, dregs (src1));
3805 OUTS (outf, ")");
4b7f6baa
CM		 3806 }
3807 else if (aop == 0 && aopcde == 7)
3808 {
4b7f6baa 3809 OUTS (outf, dregs (dst0));
086134ec 3810 OUTS (outf, " = MAX (");
4b7f6baa 3811 OUTS (outf, dregs (src0));
086134ec 3812 OUTS (outf, ", ");
4b7f6baa
CM		 3813 OUTS (outf, dregs (src1));
3814 OUTS (outf, ")");
4b7f6baa
CM		 3815 }
3816 else if (aop == 2 && aopcde == 6)
3817 {
4b7f6baa 3818 OUTS (outf, dregs (dst0));
086134ec 3819 OUTS (outf, " = ABS ");
4b7f6baa 3820 OUTS (outf, dregs (src0));
086134ec 3821 OUTS (outf, " (V)");
4b7f6baa
CM		 3822 }
3823 else if (aop == 1 && aopcde == 6)
3824 {
4b7f6baa 3825 OUTS (outf, dregs (dst0));
086134ec 3826 OUTS (outf, " = MIN (");
4b7f6baa 3827 OUTS (outf, dregs (src0));
086134ec 3828 OUTS (outf, ", ");
4b7f6baa 3829 OUTS (outf, dregs (src1));
086134ec 3830 OUTS (outf, ") (V)");
4b7f6baa
CM		 3831 }
3832 else if (aop == 0 && aopcde == 6)
3833 {
4b7f6baa 3834 OUTS (outf, dregs (dst0));
086134ec 3835 OUTS (outf, " = MAX (");
4b7f6baa 3836 OUTS (outf, dregs (src0));
086134ec 3837 OUTS (outf, ", ");
4b7f6baa 3838 OUTS (outf, dregs (src1));
086134ec 3839 OUTS (outf, ") (V)");
4b7f6baa
CM		 3840 }
3841 else if (HL == 1 && aopcde == 1)
3842 {
4b7f6baa 3843 OUTS (outf, dregs (dst1));
086134ec 3844 OUTS (outf, " = ");
4b7f6baa 3845 OUTS (outf, dregs (src0));
086134ec 3846 OUTS (outf, " +|- ");
4b7f6baa 3847 OUTS (outf, dregs (src1));
086134ec 3848 OUTS (outf, ", ");
4b7f6baa 3849 OUTS (outf, dregs (dst0));
086134ec 3850 OUTS (outf, " = ");
4b7f6baa 3851 OUTS (outf, dregs (src0));
086134ec 3852 OUTS (outf, " -|+ ");
4b7f6baa
CM		 3853 OUTS (outf, dregs (src1));
3854 amod0amod2 (s, x, aop, outf);
4b7f6baa
CM		 3855 }
3856 else if (aop == 0 && aopcde == 4)
3857 {
4b7f6baa 3858 OUTS (outf, dregs (dst0));
086134ec 3859 OUTS (outf, " = ");
4b7f6baa 3860 OUTS (outf, dregs (src0));
086134ec 3861 OUTS (outf, " + ");
4b7f6baa 3862 OUTS (outf, dregs (src1));
4b7f6baa 3863 amod1 (s, x, outf);
4b7f6baa
CM		 3864 }
3865 else if (aop == 0 && aopcde == 0)
3866 {
4b7f6baa 3867 OUTS (outf, dregs (dst0));
086134ec 3868 OUTS (outf, " = ");
4b7f6baa 3869 OUTS (outf, dregs (src0));
086134ec 3870 OUTS (outf, " +|+ ");
4b7f6baa 3871 OUTS (outf, dregs (src1));
4b7f6baa 3872 amod0 (s, x, outf);
4b7f6baa
CM		 3873 }
3874 else if (aop == 0 && aopcde == 24)
3875 {
4b7f6baa 3876 OUTS (outf, dregs (dst0));
086134ec 3877 OUTS (outf, " = BYTEPACK (");
4b7f6baa 3878 OUTS (outf, dregs (src0));
086134ec 3879 OUTS (outf, ", ");
4b7f6baa
CM		 3880 OUTS (outf, dregs (src1));
3881 OUTS (outf, ")");
4b7f6baa
CM		 3882 }
3883 else if (aop == 1 && aopcde == 24)
3884 {
4b7f6baa
CM		 3885 OUTS (outf, "(");
3886 OUTS (outf, dregs (dst1));
086134ec 3887 OUTS (outf, ", ");
4b7f6baa
CM		 3888 OUTS (outf, dregs (dst0));
3889 OUTS (outf, ") = BYTEUNPACK ");
3890 OUTS (outf, dregs (src0 + 1));
3891 OUTS (outf, ":");
086134ec 3892 OUTS (outf, imm5d (src0));
4b7f6baa 3893 aligndir (s, outf);
4b7f6baa
CM		 3894 }
3895 else if (aopcde == 13)
3896 {
4b7f6baa
CM		 3897 OUTS (outf, "(");
3898 OUTS (outf, dregs (dst1));
086134ec 3899 OUTS (outf, ", ");
4b7f6baa
CM		 3900 OUTS (outf, dregs (dst0));
3901 OUTS (outf, ") = SEARCH ");
3902 OUTS (outf, dregs (src0));
086134ec 3903 OUTS (outf, " (");
4b7f6baa
CM		 3904 searchmod (aop, outf);
3905 OUTS (outf, ")");
4b7f6baa
CM		 3906 }
3907 else
b7d48530
NC		 3908 return 0;
3909
3910 return 4;
4b7f6baa
CM		 3911}
3912
3913static int
3914decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3915{
b7d48530
NC		 3916 /* dsp32shift
3917 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3918 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
3919 |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
3920 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 3921 int HLs = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask);
3922 int sop = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask);
3923 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask);
3924 int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask);
3925 int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask);
3926 int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask);
3927 const char *acc01 = (HLs & 1) == 0 ? "A0" : "A1";
3928
4b7f6baa
CM		 3929 if (HLs == 0 && sop == 0 && sopcde == 0)
3930 {
4b7f6baa 3931 OUTS (outf, dregs_lo (dst0));
086134ec 3932 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3933 OUTS (outf, dregs_lo (src1));
3934 OUTS (outf, " BY ");
3935 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3936 }
3937 else if (HLs == 1 && sop == 0 && sopcde == 0)
3938 {
4b7f6baa 3939 OUTS (outf, dregs_lo (dst0));
086134ec 3940 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3941 OUTS (outf, dregs_hi (src1));
3942 OUTS (outf, " BY ");
3943 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3944 }
3945 else if (HLs == 2 && sop == 0 && sopcde == 0)
3946 {
4b7f6baa 3947 OUTS (outf, dregs_hi (dst0));
086134ec 3948 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3949 OUTS (outf, dregs_lo (src1));
3950 OUTS (outf, " BY ");
3951 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3952 }
3953 else if (HLs == 3 && sop == 0 && sopcde == 0)
3954 {
4b7f6baa 3955 OUTS (outf, dregs_hi (dst0));
086134ec 3956 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3957 OUTS (outf, dregs_hi (src1));
3958 OUTS (outf, " BY ");
3959 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3960 }
3961 else if (HLs == 0 && sop == 1 && sopcde == 0)
3962 {
4b7f6baa 3963 OUTS (outf, dregs_lo (dst0));
086134ec 3964 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3965 OUTS (outf, dregs_lo (src1));
3966 OUTS (outf, " BY ");
3967 OUTS (outf, dregs_lo (src0));
086134ec 3968 OUTS (outf, " (S)");
4b7f6baa
CM		 3969 }
3970 else if (HLs == 1 && sop == 1 && sopcde == 0)
3971 {
4b7f6baa 3972 OUTS (outf, dregs_lo (dst0));
086134ec 3973 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3974 OUTS (outf, dregs_hi (src1));
3975 OUTS (outf, " BY ");
3976 OUTS (outf, dregs_lo (src0));
086134ec 3977 OUTS (outf, " (S)");
4b7f6baa
CM		 3978 }
3979 else if (HLs == 2 && sop == 1 && sopcde == 0)
3980 {
4b7f6baa 3981 OUTS (outf, dregs_hi (dst0));
086134ec 3982 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3983 OUTS (outf, dregs_lo (src1));
3984 OUTS (outf, " BY ");
3985 OUTS (outf, dregs_lo (src0));
086134ec 3986 OUTS (outf, " (S)");
4b7f6baa
CM		 3987 }
3988 else if (HLs == 3 && sop == 1 && sopcde == 0)
3989 {
4b7f6baa 3990 OUTS (outf, dregs_hi (dst0));
086134ec 3991 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3992 OUTS (outf, dregs_hi (src1));
3993 OUTS (outf, " BY ");
3994 OUTS (outf, dregs_lo (src0));
086134ec 3995 OUTS (outf, " (S)");
4b7f6baa
CM		 3996 }
3997 else if (sop == 2 && sopcde == 0)
3998 {
4b7f6baa 3999 OUTS (outf, (HLs & 2) == 0 ? dregs_lo (dst0) : dregs_hi (dst0));
086134ec 4000 OUTS (outf, " = LSHIFT ");
4b7f6baa
CM		 4001 OUTS (outf, (HLs & 1) == 0 ? dregs_lo (src1) : dregs_hi (src1));
4002 OUTS (outf, " BY ");
4003 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4004 }
4005 else if (sop == 0 && sopcde == 3)
4006 {
4b7f6baa 4007 OUTS (outf, acc01);
086134ec 4008 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4009 OUTS (outf, acc01);
4010 OUTS (outf, " BY ");
4011 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4012 }
4013 else if (sop == 1 && sopcde == 3)
4014 {
4b7f6baa 4015 OUTS (outf, acc01);
086134ec 4016 OUTS (outf, " = LSHIFT ");
4b7f6baa
CM		 4017 OUTS (outf, acc01);
4018 OUTS (outf, " BY ");
4019 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4020 }
4021 else if (sop == 2 && sopcde == 3)
4022 {
4b7f6baa 4023 OUTS (outf, acc01);
086134ec 4024 OUTS (outf, " = ROT ");
4b7f6baa
CM		 4025 OUTS (outf, acc01);
4026 OUTS (outf, " BY ");
4027 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4028 }
4029 else if (sop == 3 && sopcde == 3)
4030 {
4b7f6baa 4031 OUTS (outf, dregs (dst0));
086134ec 4032 OUTS (outf, " = ROT ");
4b7f6baa
CM		 4033 OUTS (outf, dregs (src1));
4034 OUTS (outf, " BY ");
4035 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4036 }
4037 else if (sop == 1 && sopcde == 1)
4038 {
4b7f6baa 4039 OUTS (outf, dregs (dst0));
086134ec 4040 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4041 OUTS (outf, dregs (src1));
4042 OUTS (outf, " BY ");
4043 OUTS (outf, dregs_lo (src0));
086134ec 4044 OUTS (outf, " (V, S)");
4b7f6baa
CM		 4045 }
4046 else if (sop == 0 && sopcde == 1)
4047 {
4b7f6baa 4048 OUTS (outf, dregs (dst0));
086134ec 4049 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4050 OUTS (outf, dregs (src1));
4051 OUTS (outf, " BY ");
4052 OUTS (outf, dregs_lo (src0));
086134ec 4053 OUTS (outf, " (V)");
4b7f6baa
CM		 4054 }
4055 else if (sop == 0 && sopcde == 2)
4056 {
4b7f6baa 4057 OUTS (outf, dregs (dst0));
086134ec 4058 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4059 OUTS (outf, dregs (src1));
4060 OUTS (outf, " BY ");
4061 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4062 }
4063 else if (sop == 1 && sopcde == 2)
4064 {
4b7f6baa 4065 OUTS (outf, dregs (dst0));
086134ec 4066 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4067 OUTS (outf, dregs (src1));
4068 OUTS (outf, " BY ");
4069 OUTS (outf, dregs_lo (src0));
086134ec 4070 OUTS (outf, " (S)");
4b7f6baa
CM		 4071 }
4072 else if (sop == 2 && sopcde == 2)
4073 {
4b7f6baa 4074 OUTS (outf, dregs (dst0));
59a82d23 4075 OUTS (outf, " = LSHIFT ");
4b7f6baa
CM		 4076 OUTS (outf, dregs (src1));
4077 OUTS (outf, " BY ");
4078 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4079 }
4080 else if (sop == 3 && sopcde == 2)
4081 {
4b7f6baa 4082 OUTS (outf, dregs (dst0));
086134ec 4083 OUTS (outf, " = ROT ");
4b7f6baa
CM		 4084 OUTS (outf, dregs (src1));
4085 OUTS (outf, " BY ");
4086 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4087 }
4088 else if (sop == 2 && sopcde == 1)
4089 {
4b7f6baa 4090 OUTS (outf, dregs (dst0));
59a82d23 4091 OUTS (outf, " = LSHIFT ");
4b7f6baa
CM		 4092 OUTS (outf, dregs (src1));
4093 OUTS (outf, " BY ");
4094 OUTS (outf, dregs_lo (src0));
086134ec 4095 OUTS (outf, " (V)");
4b7f6baa
CM		 4096 }
4097 else if (sop == 0 && sopcde == 4)
4098 {
4b7f6baa 4099 OUTS (outf, dregs (dst0));
086134ec 4100 OUTS (outf, " = PACK (");
4b7f6baa 4101 OUTS (outf, dregs_lo (src1));
086134ec 4102 OUTS (outf, ", ");
4b7f6baa
CM		 4103 OUTS (outf, dregs_lo (src0));
4104 OUTS (outf, ")");
4b7f6baa
CM		 4105 }
4106 else if (sop == 1 && sopcde == 4)
4107 {
4b7f6baa 4108 OUTS (outf, dregs (dst0));
086134ec 4109 OUTS (outf, " = PACK (");
4b7f6baa 4110 OUTS (outf, dregs_lo (src1));
086134ec 4111 OUTS (outf, ", ");
4b7f6baa
CM		 4112 OUTS (outf, dregs_hi (src0));
4113 OUTS (outf, ")");
4b7f6baa
CM		 4114 }
4115 else if (sop == 2 && sopcde == 4)
4116 {
4b7f6baa 4117 OUTS (outf, dregs (dst0));
086134ec 4118 OUTS (outf, " = PACK (");
4b7f6baa 4119 OUTS (outf, dregs_hi (src1));
086134ec 4120 OUTS (outf, ", ");
4b7f6baa
CM		 4121 OUTS (outf, dregs_lo (src0));
4122 OUTS (outf, ")");
4b7f6baa
CM		 4123 }
4124 else if (sop == 3 && sopcde == 4)
4125 {
4b7f6baa 4126 OUTS (outf, dregs (dst0));
086134ec 4127 OUTS (outf, " = PACK (");
4b7f6baa 4128 OUTS (outf, dregs_hi (src1));
086134ec 4129 OUTS (outf, ", ");
4b7f6baa
CM		 4130 OUTS (outf, dregs_hi (src0));
4131 OUTS (outf, ")");
4b7f6baa
CM		 4132 }
4133 else if (sop == 0 && sopcde == 5)
4134 {
4b7f6baa 4135 OUTS (outf, dregs_lo (dst0));
086134ec 4136 OUTS (outf, " = SIGNBITS ");
4b7f6baa 4137 OUTS (outf, dregs (src1));
4b7f6baa
CM		 4138 }
4139 else if (sop == 1 && sopcde == 5)
4140 {
4b7f6baa 4141 OUTS (outf, dregs_lo (dst0));
086134ec 4142 OUTS (outf, " = SIGNBITS ");
4b7f6baa 4143 OUTS (outf, dregs_lo (src1));
4b7f6baa
CM		 4144 }
4145 else if (sop == 2 && sopcde == 5)
4146 {
4b7f6baa 4147 OUTS (outf, dregs_lo (dst0));
086134ec 4148 OUTS (outf, " = SIGNBITS ");
4b7f6baa 4149 OUTS (outf, dregs_hi (src1));
4b7f6baa
CM		 4150 }
4151 else if (sop == 0 && sopcde == 6)
4152 {
4b7f6baa 4153 OUTS (outf, dregs_lo (dst0));
086134ec 4154 OUTS (outf, " = SIGNBITS A0");
4b7f6baa
CM		 4155 }
4156 else if (sop == 1 && sopcde == 6)
4157 {
4b7f6baa 4158 OUTS (outf, dregs_lo (dst0));
086134ec 4159 OUTS (outf, " = SIGNBITS A1");
4b7f6baa
CM		 4160 }
4161 else if (sop == 3 && sopcde == 6)
4162 {
4b7f6baa 4163 OUTS (outf, dregs_lo (dst0));
086134ec 4164 OUTS (outf, " = ONES ");
4b7f6baa 4165 OUTS (outf, dregs (src1));
4b7f6baa
CM		 4166 }
4167 else if (sop == 0 && sopcde == 7)
4168 {
4b7f6baa 4169 OUTS (outf, dregs_lo (dst0));
086134ec 4170 OUTS (outf, " = EXPADJ (");
4b7f6baa 4171 OUTS (outf, dregs (src1));
086134ec 4172 OUTS (outf, ", ");
4b7f6baa
CM		 4173 OUTS (outf, dregs_lo (src0));
4174 OUTS (outf, ")");
4b7f6baa
CM		 4175 }
4176 else if (sop == 1 && sopcde == 7)
4177 {
4b7f6baa 4178 OUTS (outf, dregs_lo (dst0));
086134ec 4179 OUTS (outf, " = EXPADJ (");
4b7f6baa 4180 OUTS (outf, dregs (src1));
086134ec 4181 OUTS (outf, ", ");
4b7f6baa
CM		 4182 OUTS (outf, dregs_lo (src0));
4183 OUTS (outf, ") (V)");
4b7f6baa
CM		 4184 }
4185 else if (sop == 2 && sopcde == 7)
4186 {
4b7f6baa 4187 OUTS (outf, dregs_lo (dst0));
086134ec 4188 OUTS (outf, " = EXPADJ (");
4b7f6baa 4189 OUTS (outf, dregs_lo (src1));
086134ec 4190 OUTS (outf, ", ");
4b7f6baa
CM		 4191 OUTS (outf, dregs_lo (src0));
4192 OUTS (outf, ")");
4b7f6baa
CM		 4193 }
4194 else if (sop == 3 && sopcde == 7)
4195 {
4b7f6baa 4196 OUTS (outf, dregs_lo (dst0));
086134ec 4197 OUTS (outf, " = EXPADJ (");
4b7f6baa 4198 OUTS (outf, dregs_hi (src1));
086134ec 4199 OUTS (outf, ", ");
4b7f6baa
CM		 4200 OUTS (outf, dregs_lo (src0));
4201 OUTS (outf, ")");
4b7f6baa
CM		 4202 }
4203 else if (sop == 0 && sopcde == 8)
4204 {
4b7f6baa
CM		 4205 OUTS (outf, "BITMUX (");
4206 OUTS (outf, dregs (src0));
086134ec 4207 OUTS (outf, ", ");
4b7f6baa 4208 OUTS (outf, dregs (src1));
086134ec 4209 OUTS (outf, ", A0) (ASR)");
4b7f6baa
CM		 4210 }
4211 else if (sop == 1 && sopcde == 8)
4212 {
4b7f6baa
CM		 4213 OUTS (outf, "BITMUX (");
4214 OUTS (outf, dregs (src0));
086134ec 4215 OUTS (outf, ", ");
4b7f6baa 4216 OUTS (outf, dregs (src1));
086134ec 4217 OUTS (outf, ", A0) (ASL)");
4b7f6baa
CM		 4218 }
4219 else if (sop == 0 && sopcde == 9)
4220 {
4b7f6baa 4221 OUTS (outf, dregs_lo (dst0));
086134ec 4222 OUTS (outf, " = VIT_MAX (");
4b7f6baa
CM		 4223 OUTS (outf, dregs (src1));
4224 OUTS (outf, ") (ASL)");
4b7f6baa
CM		 4225 }
4226 else if (sop == 1 && sopcde == 9)
4227 {
4b7f6baa 4228 OUTS (outf, dregs_lo (dst0));
086134ec 4229 OUTS (outf, " = VIT_MAX (");
4b7f6baa
CM		 4230 OUTS (outf, dregs (src1));
4231 OUTS (outf, ") (ASR)");
4b7f6baa
CM		 4232 }
4233 else if (sop == 2 && sopcde == 9)
4234 {
4b7f6baa 4235 OUTS (outf, dregs (dst0));
086134ec 4236 OUTS (outf, " = VIT_MAX (");
4b7f6baa 4237 OUTS (outf, dregs (src1));
086134ec 4238 OUTS (outf, ", ");
4b7f6baa 4239 OUTS (outf, dregs (src0));
086134ec 4240 OUTS (outf, ") (ASL)");
4b7f6baa
CM		 4241 }
4242 else if (sop == 3 && sopcde == 9)
4243 {
4b7f6baa 4244 OUTS (outf, dregs (dst0));
086134ec 4245 OUTS (outf, " = VIT_MAX (");
4b7f6baa 4246 OUTS (outf, dregs (src1));
086134ec 4247 OUTS (outf, ", ");
4b7f6baa 4248 OUTS (outf, dregs (src0));
086134ec 4249 OUTS (outf, ") (ASR)");
4b7f6baa
CM		 4250 }
4251 else if (sop == 0 && sopcde == 10)
4252 {
4b7f6baa 4253 OUTS (outf, dregs (dst0));
086134ec 4254 OUTS (outf, " = EXTRACT (");
4b7f6baa 4255 OUTS (outf, dregs (src1));
086134ec 4256 OUTS (outf, ", ");
4b7f6baa
CM		 4257 OUTS (outf, dregs_lo (src0));
4258 OUTS (outf, ") (Z)");
4b7f6baa
CM		 4259 }
4260 else if (sop == 1 && sopcde == 10)
4261 {
4b7f6baa 4262 OUTS (outf, dregs (dst0));
086134ec 4263 OUTS (outf, " = EXTRACT (");
4b7f6baa 4264 OUTS (outf, dregs (src1));
086134ec 4265 OUTS (outf, ", ");
4b7f6baa 4266 OUTS (outf, dregs_lo (src0));
086134ec 4267 OUTS (outf, ") (X)");
4b7f6baa
CM		 4268 }
4269 else if (sop == 2 && sopcde == 10)
4270 {
4b7f6baa 4271 OUTS (outf, dregs (dst0));
086134ec 4272 OUTS (outf, " = DEPOSIT (");
4b7f6baa 4273 OUTS (outf, dregs (src1));
086134ec 4274 OUTS (outf, ", ");
4b7f6baa
CM		 4275 OUTS (outf, dregs (src0));
4276 OUTS (outf, ")");
4b7f6baa
CM		 4277 }
4278 else if (sop == 3 && sopcde == 10)
4279 {
4b7f6baa 4280 OUTS (outf, dregs (dst0));
086134ec 4281 OUTS (outf, " = DEPOSIT (");
4b7f6baa 4282 OUTS (outf, dregs (src1));
086134ec 4283 OUTS (outf, ", ");
4b7f6baa 4284 OUTS (outf, dregs (src0));
086134ec 4285 OUTS (outf, ") (X)");
4b7f6baa
CM		 4286 }
4287 else if (sop == 0 && sopcde == 11)
4288 {
4b7f6baa 4289 OUTS (outf, dregs_lo (dst0));
086134ec 4290 OUTS (outf, " = CC = BXORSHIFT (A0, ");
4b7f6baa
CM		 4291 OUTS (outf, dregs (src0));
4292 OUTS (outf, ")");
4b7f6baa
CM		 4293 }
4294 else if (sop == 1 && sopcde == 11)
4295 {
4b7f6baa 4296 OUTS (outf, dregs_lo (dst0));
086134ec 4297 OUTS (outf, " = CC = BXOR (A0, ");
4b7f6baa
CM		 4298 OUTS (outf, dregs (src0));
4299 OUTS (outf, ")");
4b7f6baa
CM		 4300 }
4301 else if (sop == 0 && sopcde == 12)
086134ec 4302 OUTS (outf, "A0 = BXORSHIFT (A0, A1, CC)");
b7d48530 4303
4b7f6baa
CM		 4304 else if (sop == 1 && sopcde == 12)
4305 {
4b7f6baa 4306 OUTS (outf, dregs_lo (dst0));
086134ec 4307 OUTS (outf, " = CC = BXOR (A0, A1, CC)");
4b7f6baa
CM		 4308 }
4309 else if (sop == 0 && sopcde == 13)
4310 {
4b7f6baa 4311 OUTS (outf, dregs (dst0));
086134ec 4312 OUTS (outf, " = ALIGN8 (");
4b7f6baa 4313 OUTS (outf, dregs (src1));
086134ec 4314 OUTS (outf, ", ");
4b7f6baa
CM		 4315 OUTS (outf, dregs (src0));
4316 OUTS (outf, ")");
4b7f6baa
CM		 4317 }
4318 else if (sop == 1 && sopcde == 13)
4319 {
4b7f6baa 4320 OUTS (outf, dregs (dst0));
086134ec 4321 OUTS (outf, " = ALIGN16 (");
4b7f6baa 4322 OUTS (outf, dregs (src1));
086134ec 4323 OUTS (outf, ", ");
4b7f6baa
CM		 4324 OUTS (outf, dregs (src0));
4325 OUTS (outf, ")");
4b7f6baa
CM		 4326 }
4327 else if (sop == 2 && sopcde == 13)
4328 {
4b7f6baa 4329 OUTS (outf, dregs (dst0));
086134ec 4330 OUTS (outf, " = ALIGN24 (");
4b7f6baa 4331 OUTS (outf, dregs (src1));
086134ec 4332 OUTS (outf, ", ");
4b7f6baa
CM		 4333 OUTS (outf, dregs (src0));
4334 OUTS (outf, ")");
4b7f6baa
CM		 4335 }
4336 else
b7d48530
NC		 4337 return 0;
4338
4339 return 4;
4b7f6baa
CM		 4340}
4341
4342static int
4343decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4344{
b7d48530
NC		 4345 /* dsp32shiftimm
4346 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4347 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
4348 |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
4349 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4350 int src1 = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask);
4351 int sop = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
4352 int bit8 = ((iw1 >> 8) & 0x1);
4353 int immag = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4b7f6baa 4354 int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
b7d48530
NC		 4355 int dst0 = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);
4356 int sopcde = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
4357 int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
4b7f6baa 4358
331f1cbe 4359 if (sop == 0 && sopcde == 0)
4b7f6baa 4360 {
331f1cbe
BS		 4361 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4362 OUTS (outf, " = ");
4363 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4364 OUTS (outf, " >>> ");
4b7f6baa 4365 OUTS (outf, uimm4 (newimmag));
4b7f6baa 4366 }
331f1cbe 4367 else if (sop == 1 && sopcde == 0 && bit8 == 0)
4b7f6baa 4368 {
331f1cbe
BS		 4369 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4370 OUTS (outf, " = ");
4371 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4372 OUTS (outf, " << ");
4b7f6baa 4373 OUTS (outf, uimm4 (immag));
331f1cbe 4374 OUTS (outf, " (S)");
4b7f6baa 4375 }
331f1cbe 4376 else if (sop == 1 && sopcde == 0 && bit8 == 1)
4b7f6baa 4377 {
331f1cbe
BS		 4378 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4379 OUTS (outf, " = ");
4380 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4381 OUTS (outf, " >>> ");
4b7f6baa 4382 OUTS (outf, uimm4 (newimmag));
331f1cbe 4383 OUTS (outf, " (S)");
4b7f6baa 4384 }
331f1cbe 4385 else if (sop == 2 && sopcde == 0 && bit8 == 0)
4b7f6baa 4386 {
331f1cbe
BS		 4387 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4388 OUTS (outf, " = ");
4389 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4390 OUTS (outf, " << ");
4b7f6baa 4391 OUTS (outf, uimm4 (immag));
4b7f6baa 4392 }
331f1cbe 4393 else if (sop == 2 && sopcde == 0 && bit8 == 1)
4b7f6baa 4394 {
331f1cbe
BS		 4395 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4396 OUTS (outf, " = ");
4397 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4398 OUTS (outf, " >> ");
4b7f6baa 4399 OUTS (outf, uimm4 (newimmag));
4b7f6baa 4400 }
4b7f6baa
CM		 4401 else if (sop == 2 && sopcde == 3 && HLs == 1)
4402 {
086134ec 4403 OUTS (outf, "A1 = ROT A1 BY ");
4b7f6baa 4404 OUTS (outf, imm6 (immag));
4b7f6baa
CM		 4405 }
4406 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0)
4407 {
086134ec 4408 OUTS (outf, "A0 = A0 << ");
4b7f6baa 4409 OUTS (outf, uimm5 (immag));
4b7f6baa
CM		 4410 }
4411 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1)
4412 {
086134ec 4413 OUTS (outf, "A0 = A0 >>> ");
4b7f6baa 4414 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4415 }
4416 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0)
4417 {
086134ec 4418 OUTS (outf, "A1 = A1 << ");
4b7f6baa 4419 OUTS (outf, uimm5 (immag));
4b7f6baa
CM		 4420 }
4421 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1)
4422 {
086134ec 4423 OUTS (outf, "A1 = A1 >>> ");
4b7f6baa 4424 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4425 }
4426 else if (sop == 1 && sopcde == 3 && HLs == 0)
4427 {
086134ec 4428 OUTS (outf, "A0 = A0 >> ");
4b7f6baa 4429 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4430 }
4431 else if (sop == 1 && sopcde == 3 && HLs == 1)
4432 {
086134ec 4433 OUTS (outf, "A1 = A1 >> ");
4b7f6baa 4434 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4435 }
4436 else if (sop == 2 && sopcde == 3 && HLs == 0)
4437 {
086134ec 4438 OUTS (outf, "A0 = ROT A0 BY ");
4b7f6baa 4439 OUTS (outf, imm6 (immag));
4b7f6baa
CM		 4440 }
4441 else if (sop == 1 && sopcde == 1 && bit8 == 0)
4442 {
4b7f6baa 4443 OUTS (outf, dregs (dst0));
086134ec 4444 OUTS (outf, " = ");
4b7f6baa 4445 OUTS (outf, dregs (src1));
086134ec 4446 OUTS (outf, " << ");
4b7f6baa
CM		 4447 OUTS (outf, uimm5 (immag));
4448 OUTS (outf, " (V, S)");
4b7f6baa
CM		 4449 }
4450 else if (sop == 1 && sopcde == 1 && bit8 == 1)
4451 {
4b7f6baa 4452 OUTS (outf, dregs (dst0));
086134ec 4453 OUTS (outf, " = ");
4b7f6baa 4454 OUTS (outf, dregs (src1));
086134ec 4455 OUTS (outf, " >>> ");
4b7f6baa 4456 OUTS (outf, imm5 (-immag));
0b7691fd 4457 OUTS (outf, " (V, S)");
4b7f6baa
CM		 4458 }
4459 else if (sop == 2 && sopcde == 1 && bit8 == 1)
4460 {
4b7f6baa 4461 OUTS (outf, dregs (dst0));
086134ec 4462 OUTS (outf, " = ");
4b7f6baa
CM		 4463 OUTS (outf, dregs (src1));
4464 OUTS (outf, " >> ");
4465 OUTS (outf, uimm5 (newimmag));
4466 OUTS (outf, " (V)");
4b7f6baa
CM		 4467 }
4468 else if (sop == 2 && sopcde == 1 && bit8 == 0)
4469 {
4b7f6baa 4470 OUTS (outf, dregs (dst0));
086134ec 4471 OUTS (outf, " = ");
4b7f6baa 4472 OUTS (outf, dregs (src1));
086134ec 4473 OUTS (outf, " << ");
4b7f6baa
CM		 4474 OUTS (outf, imm5 (immag));
4475 OUTS (outf, " (V)");
4b7f6baa
CM		 4476 }
4477 else if (sop == 0 && sopcde == 1)
4478 {
4b7f6baa 4479 OUTS (outf, dregs (dst0));
086134ec 4480 OUTS (outf, " = ");
4b7f6baa 4481 OUTS (outf, dregs (src1));
086134ec 4482 OUTS (outf, " >>> ");
4b7f6baa
CM		 4483 OUTS (outf, uimm5 (newimmag));
4484 OUTS (outf, " (V)");
4b7f6baa
CM		 4485 }
4486 else if (sop == 1 && sopcde == 2)
4487 {
4b7f6baa 4488 OUTS (outf, dregs (dst0));
086134ec 4489 OUTS (outf, " = ");
4b7f6baa 4490 OUTS (outf, dregs (src1));
086134ec 4491 OUTS (outf, " << ");
4b7f6baa 4492 OUTS (outf, uimm5 (immag));
086134ec 4493 OUTS (outf, " (S)");
4b7f6baa
CM		 4494 }
4495 else if (sop == 2 && sopcde == 2 && bit8 == 1)
4496 {
4b7f6baa 4497 OUTS (outf, dregs (dst0));
086134ec 4498 OUTS (outf, " = ");
4b7f6baa 4499 OUTS (outf, dregs (src1));
086134ec 4500 OUTS (outf, " >> ");
4b7f6baa 4501 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4502 }
4503 else if (sop == 2 && sopcde == 2 && bit8 == 0)
4504 {
4b7f6baa 4505 OUTS (outf, dregs (dst0));
086134ec 4506 OUTS (outf, " = ");
4b7f6baa 4507 OUTS (outf, dregs (src1));
086134ec 4508 OUTS (outf, " << ");
4b7f6baa 4509 OUTS (outf, uimm5 (immag));
4b7f6baa
CM		 4510 }
4511 else if (sop == 3 && sopcde == 2)
4512 {
4b7f6baa 4513 OUTS (outf, dregs (dst0));
086134ec 4514 OUTS (outf, " = ROT ");
4b7f6baa
CM		 4515 OUTS (outf, dregs (src1));
4516 OUTS (outf, " BY ");
4517 OUTS (outf, imm6 (immag));
4b7f6baa
CM		 4518 }
4519 else if (sop == 0 && sopcde == 2)
4520 {
4b7f6baa 4521 OUTS (outf, dregs (dst0));
086134ec 4522 OUTS (outf, " = ");
4b7f6baa 4523 OUTS (outf, dregs (src1));
086134ec 4524 OUTS (outf, " >>> ");
4b7f6baa 4525 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4526 }
4527 else
b7d48530
NC		 4528 return 0;
4529
4530 return 4;
4b7f6baa
CM		 4531}
4532
4533static int
4534decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf)
4535{
703ec4e8 4536 struct private *priv = outf->private_data;
b7d48530
NC		 4537 /* pseudoDEBUG
4538 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4539 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
4540 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 4541 int fn = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
4542 int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask);
4543 int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
4544
703ec4e8 4545 if (priv->parallel)
219b747a
MF		 4546 return 0;
4547
4b7f6baa 4548 if (reg == 0 && fn == 3)
b7d48530
NC		 4549 OUTS (outf, "DBG A0");
4550
4b7f6baa 4551 else if (reg == 1 && fn == 3)
b7d48530
NC		 4552 OUTS (outf, "DBG A1");
4553
4b7f6baa 4554 else if (reg == 3 && fn == 3)
b7d48530
NC		 4555 OUTS (outf, "ABORT");
4556
4b7f6baa 4557 else if (reg == 4 && fn == 3)
b7d48530
NC		 4558 OUTS (outf, "HLT");
4559
4b7f6baa 4560 else if (reg == 5 && fn == 3)
b7d48530
NC		 4561 OUTS (outf, "DBGHALT");
4562
4b7f6baa
CM		 4563 else if (reg == 6 && fn == 3)
4564 {
086134ec 4565 OUTS (outf, "DBGCMPLX (");
4b7f6baa
CM		 4566 OUTS (outf, dregs (grp));
4567 OUTS (outf, ")");
4b7f6baa
CM		 4568 }
4569 else if (reg == 7 && fn == 3)
b7d48530
NC		 4570 OUTS (outf, "DBG");
4571
4b7f6baa
CM		 4572 else if (grp == 0 && fn == 2)
4573 {
73a63ccf 4574 OUTS (outf, "OUTC ");
4b7f6baa 4575 OUTS (outf, dregs (reg));
4b7f6baa
CM		 4576 }
4577 else if (fn == 0)
4578 {
a01eda85 4579 OUTS (outf, "DBG ");
4b7f6baa 4580 OUTS (outf, allregs (reg, grp));
4b7f6baa
CM		 4581 }
4582 else if (fn == 1)
4583 {
9805c0a5 4584 OUTS (outf, "PRNT ");
4b7f6baa 4585 OUTS (outf, allregs (reg, grp));
4b7f6baa
CM		 4586 }
4587 else
b7d48530
NC		 4588 return 0;
4589
4590 return 2;
4b7f6baa
CM		 4591}
4592
73a63ccf
MF		 4593static int
4594decode_pseudoOChar_0 (TIword iw0, disassemble_info *outf)
4595{
703ec4e8 4596 struct private *priv = outf->private_data;
73a63ccf
MF		 4597 /* psedoOChar
4598 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4599 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
4600 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4601 int ch = ((iw0 >> PseudoChr_ch_bits) & PseudoChr_ch_mask);
4602
703ec4e8 4603 if (priv->parallel)
219b747a
MF		 4604 return 0;
4605
73a63ccf
MF		 4606 OUTS (outf, "OUTC ");
4607 OUTS (outf, uimm8 (ch));
4608
4609 return 2;
4610}
4611
4b7f6baa
CM		 4612static int
4613decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4614{
703ec4e8 4615 struct private *priv = outf->private_data;
b7d48530
NC		 4616 /* pseudodbg_assert
4617 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
66a6900a 4618 | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
b7d48530
NC		 4619 |.expected......................................................|
4620 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa 4621 int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
b7d48530 4622 int dbgop = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
66a6900a 4623 int grp = ((iw0 >> (PseudoDbg_Assert_grp_bits - 16)) & PseudoDbg_Assert_grp_mask);
b7d48530 4624 int regtest = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
4b7f6baa 4625
703ec4e8 4626 if (priv->parallel)
219b747a
MF		 4627 return 0;
4628
4b7f6baa
CM		 4629 if (dbgop == 0)
4630 {
086134ec 4631 OUTS (outf, "DBGA (");
66a6900a 4632 OUTS (outf, regs_lo (regtest, grp));
086134ec 4633 OUTS (outf, ", ");
4b7f6baa
CM		 4634 OUTS (outf, uimm16 (expected));
4635 OUTS (outf, ")");
4b7f6baa
CM		 4636 }
4637 else if (dbgop == 1)
4638 {
086134ec 4639 OUTS (outf, "DBGA (");
66a6900a 4640 OUTS (outf, regs_hi (regtest, grp));
086134ec 4641 OUTS (outf, ", ");
4b7f6baa
CM		 4642 OUTS (outf, uimm16 (expected));
4643 OUTS (outf, ")");
4b7f6baa
CM		 4644 }
4645 else if (dbgop == 2)
4646 {
086134ec 4647 OUTS (outf, "DBGAL (");
66a6900a 4648 OUTS (outf, allregs (regtest, grp));
086134ec 4649 OUTS (outf, ", ");
4b7f6baa
CM		 4650 OUTS (outf, uimm16 (expected));
4651 OUTS (outf, ")");
4b7f6baa
CM		 4652 }
4653 else if (dbgop == 3)
4654 {
086134ec 4655 OUTS (outf, "DBGAH (");
66a6900a 4656 OUTS (outf, allregs (regtest, grp));
086134ec 4657 OUTS (outf, ", ");
4b7f6baa
CM		 4658 OUTS (outf, uimm16 (expected));
4659 OUTS (outf, ")");
4b7f6baa
CM		 4660 }
4661 else
b7d48530
NC		 4662 return 0;
4663 return 4;
4b7f6baa
CM		 4664}
4665
ba329817
MF		 4666static int
4667ifetch (bfd_vma pc, disassemble_info *outf, TIword *iw)
4668{
4669 bfd_byte buf[2];
4670 int status;
4671
ed2c4879 4672 status = (*outf->read_memory_func) (pc, buf, 2, outf);
ba329817
MF		 4673 if (status != 0)
4674 {
4675 (*outf->memory_error_func) (status, pc, outf);
4676 return -1;
4677 }
4678
4679 *iw = bfd_getl16 (buf);
4680 return 0;
4681}
4682
ad15c38e 4683static int
4b7f6baa
CM		 4684_print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4685{
703ec4e8 4686 struct private *priv = outf->private_data;
4b7f6baa
CM		 4687 TIword iw0;
4688 TIword iw1;
b7d48530
NC		 4689 int rv = 0;
4690
ed2c4879
MF		 4691 /* The PC must be 16-bit aligned. */
4692 if (pc & 1)
4693 {
4694 OUTS (outf, "ILLEGAL (UNALIGNED)");
4695 /* For people dumping data, just re-align the return value. */
4696 return 1;
4697 }
4698
ba329817
MF		 4699 if (ifetch (pc, outf, &iw0))
4700 return -1;
a4e600b2 4701 priv->iw0 = iw0;
4b7f6baa 4702
ba329817
MF		 4703 if ((iw0 & 0xc000) == 0xc000)
4704 {
4705 /* 32-bit insn. */
4706 if (ifetch (pc + 2, outf, &iw1))
4707 return -1;
4708 }
4709 else
4710 /* 16-bit insn. */
4711 iw1 = 0;
4b7f6baa
CM		 4712
4713 if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800)
4714 {
703ec4e8 4715 if (priv->parallel)
219b747a 4716 {
602427c4
MF		 4717 OUTS (outf, "ILLEGAL");
4718 return 0;
219b747a 4719 }
086134ec 4720 OUTS (outf, "MNOP");
4b7f6baa
CM		 4721 return 4;
4722 }
4723 else if ((iw0 & 0xff00) == 0x0000)
b7d48530 4724 rv = decode_ProgCtrl_0 (iw0, outf);
4b7f6baa 4725 else if ((iw0 & 0xffc0) == 0x0240)
b7d48530 4726 rv = decode_CaCTRL_0 (iw0, outf);
4b7f6baa 4727 else if ((iw0 & 0xff80) == 0x0100)
b7d48530 4728 rv = decode_PushPopReg_0 (iw0, outf);
4b7f6baa 4729 else if ((iw0 & 0xfe00) == 0x0400)
b7d48530 4730 rv = decode_PushPopMultiple_0 (iw0, outf);
4b7f6baa 4731 else if ((iw0 & 0xfe00) == 0x0600)
b7d48530 4732 rv = decode_ccMV_0 (iw0, outf);
4b7f6baa 4733 else if ((iw0 & 0xf800) == 0x0800)
b7d48530 4734 rv = decode_CCflag_0 (iw0, outf);
4b7f6baa 4735 else if ((iw0 & 0xffe0) == 0x0200)
b7d48530 4736 rv = decode_CC2dreg_0 (iw0, outf);
4b7f6baa 4737 else if ((iw0 & 0xff00) == 0x0300)
b7d48530 4738 rv = decode_CC2stat_0 (iw0, outf);
4b7f6baa 4739 else if ((iw0 & 0xf000) == 0x1000)
b7d48530 4740 rv = decode_BRCC_0 (iw0, pc, outf);
4b7f6baa 4741 else if ((iw0 & 0xf000) == 0x2000)
b7d48530 4742 rv = decode_UJUMP_0 (iw0, pc, outf);
4b7f6baa 4743 else if ((iw0 & 0xf000) == 0x3000)
b7d48530 4744 rv = decode_REGMV_0 (iw0, outf);
4b7f6baa 4745 else if ((iw0 & 0xfc00) == 0x4000)
b7d48530 4746 rv = decode_ALU2op_0 (iw0, outf);
4b7f6baa 4747 else if ((iw0 & 0xfe00) == 0x4400)
b7d48530 4748 rv = decode_PTR2op_0 (iw0, outf);
4b7f6baa 4749 else if ((iw0 & 0xf800) == 0x4800)
b7d48530 4750 rv = decode_LOGI2op_0 (iw0, outf);
4b7f6baa 4751 else if ((iw0 & 0xf000) == 0x5000)
b7d48530 4752 rv = decode_COMP3op_0 (iw0, outf);
4b7f6baa 4753 else if ((iw0 & 0xf800) == 0x6000)
b7d48530 4754 rv = decode_COMPI2opD_0 (iw0, outf);
4b7f6baa 4755 else if ((iw0 & 0xf800) == 0x6800)
b7d48530 4756 rv = decode_COMPI2opP_0 (iw0, outf);
4b7f6baa 4757 else if ((iw0 & 0xf000) == 0x8000)
b7d48530 4758 rv = decode_LDSTpmod_0 (iw0, outf);
4b7f6baa 4759 else if ((iw0 & 0xff60) == 0x9e60)
b7d48530 4760 rv = decode_dagMODim_0 (iw0, outf);
4b7f6baa 4761 else if ((iw0 & 0xfff0) == 0x9f60)
b7d48530 4762 rv = decode_dagMODik_0 (iw0, outf);
4b7f6baa 4763 else if ((iw0 & 0xfc00) == 0x9c00)
b7d48530 4764 rv = decode_dspLDST_0 (iw0, outf);
4b7f6baa 4765 else if ((iw0 & 0xf000) == 0x9000)
b7d48530 4766 rv = decode_LDST_0 (iw0, outf);
4b7f6baa 4767 else if ((iw0 & 0xfc00) == 0xb800)
b7d48530 4768 rv = decode_LDSTiiFP_0 (iw0, outf);
4b7f6baa 4769 else if ((iw0 & 0xe000) == 0xA000)
b7d48530 4770 rv = decode_LDSTii_0 (iw0, outf);
4b7f6baa 4771 else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000)
b7d48530 4772 rv = decode_LoopSetup_0 (iw0, iw1, pc, outf);
4b7f6baa 4773 else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000)
b7d48530 4774 rv = decode_LDIMMhalf_0 (iw0, iw1, outf);
4b7f6baa 4775 else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000)
b7d48530 4776 rv = decode_CALLa_0 (iw0, iw1, pc, outf);
4b7f6baa 4777 else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000)
b7d48530 4778 rv = decode_LDSTidxI_0 (iw0, iw1, outf);
4b7f6baa 4779 else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000)
b7d48530 4780 rv = decode_linkage_0 (iw0, iw1, outf);
4b7f6baa 4781 else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000)
b7d48530 4782 rv = decode_dsp32mac_0 (iw0, iw1, outf);
4b7f6baa 4783 else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000)
b7d48530 4784 rv = decode_dsp32mult_0 (iw0, iw1, outf);
4b7f6baa 4785 else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000)
b7d48530 4786 rv = decode_dsp32alu_0 (iw0, iw1, outf);
4b7f6baa 4787 else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000)
b7d48530 4788 rv = decode_dsp32shift_0 (iw0, iw1, outf);
4b7f6baa 4789 else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000)
b7d48530 4790 rv = decode_dsp32shiftimm_0 (iw0, iw1, outf);
4b7f6baa 4791 else if ((iw0 & 0xff00) == 0xf800)
b7d48530 4792 rv = decode_pseudoDEBUG_0 (iw0, outf);
4b7f6baa 4793 else if ((iw0 & 0xFF00) == 0xF900)
73a63ccf 4794 rv = decode_pseudoOChar_0 (iw0, outf);
66a6900a 4795 else if ((iw0 & 0xFF00) == 0xf000 && (iw1 & 0x0000) == 0x0000)
b7d48530 4796 rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
4b7f6baa 4797
219b747a
MF		 4798 if (rv == 0)
4799 OUTS (outf, "ILLEGAL");
4800
b7d48530 4801 return rv;
4b7f6baa
CM		 4802}
4803
4b7f6baa
CM		 4804int
4805print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4806{
703ec4e8 4807 struct private priv;
ba329817 4808 int count;
471e4e36 4809
703ec4e8
MF		 4810 priv.parallel = 0;
4811 priv.comment = 0;
4812 outf->private_data = &priv;
4813
ba329817
MF		 4814 count = _print_insn_bfin (pc, outf);
4815 if (count == -1)
4816 return -1;
471e4e36 4817
4b7f6baa 4818 /* Proper display of multiple issue instructions. */
471e4e36 4819
a4e600b2
MF		 4820 if (count == 4 && (priv.iw0 & 0xc000) == 0xc000 && (priv.iw0 & BIT_MULTI_INS)
4821 && ((priv.iw0 & 0xe800) != 0xe800 /* Not Linkage. */ ))
4b7f6baa 4822 {
219b747a
MF		 4823 int legal = 1;
4824 int len;
4825
703ec4e8 4826 priv.parallel = 1;
f5caf9f4 4827 OUTS (outf, " || ");
219b747a 4828 len = _print_insn_bfin (pc + 4, outf);
ba329817
MF		 4829 if (len == -1)
4830 return -1;
f5caf9f4 4831 OUTS (outf, " || ");
219b747a 4832 if (len != 2)
602427c4 4833 legal = 0;
219b747a 4834 len = _print_insn_bfin (pc + 6, outf);
ba329817
MF		 4835 if (len == -1)
4836 return -1;
219b747a
MF		 4837 if (len != 2)
4838 legal = 0;
4839
4840 if (legal)
4841 count = 8;
4842 else
4843 {
f5caf9f4 4844 OUTS (outf, ";\t\t/* ILLEGAL PARALLEL INSTRUCTION */");
703ec4e8 4845 priv.comment = 1;
219b747a
MF		 4846 count = 0;
4847 }
4b7f6baa 4848 }
219b747a 4849
703ec4e8 4850 if (!priv.comment)
f5caf9f4 4851 OUTS (outf, ";");
086134ec 4852
219b747a
MF		 4853 if (count == 0)
4854 return 2;
4855
4b7f6baa
CM		 4856 return count;
4857}
GDB Binutils - Deliverables
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