[deliverable/binutils-gdb.git] / opcodes / crx-dis.c

/* Disassembler code for CRX.
   Copyright 2004, 2005 Free Software Foundation, Inc.
   Contributed by Tomer Levi, NSC, Israel.
   Written by Tomer Levi.

   This file is part of the GNU binutils and GDB, the GNU debugger.

   This program is free software; you can redistribute it and/or modify it under
   the terms of the GNU General Public License as published by the Free
   Software Foundation; either version 2, or (at your option)
   any later version.

   This program is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */

#include "dis-asm.h"
#include "sysdep.h"
#include "opcode/crx.h"

/* String to print when opcode was not matched.  */
#define ILLEGAL	"illegal"
  /* Escape to 16-bit immediate.  */
#define ESCAPE_16_BIT  0xE

/* Extract 'n_bits' from 'a' starting from offset 'offs'.  */
#define EXTRACT(a, offs, n_bits)	    \
  (n_bits == 32 ? (((a) >> (offs)) & ~0L)   \
  : (((a) >> (offs)) & ((1 << (n_bits)) -1)))

/* Set Bit Mask - a mask to set all bits starting from offset 'offs'.  */
#define SBM(offs)  ((((1 << (32 - offs)) -1) << (offs)))

typedef unsigned long dwordU;
typedef unsigned short wordU;

typedef struct
{
  dwordU val;
  int nbits;
} parameter;

/* Structure to hold valid 'cinv' instruction options.  */

typedef struct
  {
    /* Cinv printed string.  */
    char *str;
    /* Value corresponding to the string.  */
    unsigned int value;
  }
cinv_entry;

/* CRX 'cinv' options.  */
const cinv_entry crx_cinvs[] =
{
  {"[i]", 2}, {"[i,u]", 3}, {"[d]", 4}, {"[d,u]", 5}, 
  {"[d,i]", 6}, {"[d,i,u]", 7}, {"[b]", 8}, 
  {"[b,i]", 10}, {"[b,i,u]", 11}, {"[b,d]", 12}, 
  {"[b,d,u]", 13}, {"[b,d,i]", 14}, {"[b,d,i,u]", 15}
};

/* Enum to distinguish different registers argument types.  */
typedef enum REG_ARG_TYPE
  {
    /* General purpose register (r<N>).  */
    REG_ARG = 0,
    /* User register (u<N>).  */
    USER_REG_ARG,
    /* CO-Processor register (c<N>).  */
    COP_ARG,
    /* CO-Processor special register (cs<N>).  */
    COPS_ARG 
  }
REG_ARG_TYPE;

/* Number of valid 'cinv' instruction options.  */
int NUMCINVS = ((sizeof crx_cinvs)/(sizeof crx_cinvs[0]));
/* Current opcode table entry we're disassembling.  */
const inst *instruction;
/* Current instruction we're disassembling.  */
ins currInsn;
/* The current instruction is read into 3 consecutive words.  */
wordU words[3];
/* Contains all words in appropriate order.  */
ULONGLONG allWords;
/* Holds the current processed argument number.  */
int processing_argument_number;
/* Nonzero means a CST4 instruction.  */
int cst4flag;
/* Nonzero means the instruction's original size is
   incremented (escape sequence is used).  */
int size_changed;

static int get_number_of_operands (void);
static argtype getargtype     (operand_type);
static int getbits	      (operand_type);
static char *getregname	      (reg);
static char *getcopregname    (copreg, reg_type);
static char * getprocregname  (int);
static char *gettrapstring    (unsigned);
static char *getcinvstring    (unsigned);
static void getregliststring  (int, char *, enum REG_ARG_TYPE);
static wordU get_word_at_PC   (bfd_vma, struct disassemble_info *);
static void get_words_at_PC   (bfd_vma, struct disassemble_info *);
static unsigned long build_mask (void);
static int powerof2	      (int);
static int match_opcode	      (void);
static void make_instruction  (void);
static void print_arguments   (ins *, bfd_vma, struct disassemble_info *);
static void print_arg	      (argument *, bfd_vma, struct disassemble_info *);

/* Retrieve the number of operands for the current assembled instruction.  */

static int
get_number_of_operands (void)
{
  int i;

  for (i = 0; instruction->operands[i].op_type && i < MAX_OPERANDS; i++)
    ;

  return i;
}

/* Return the bit size for a given operand.  */

static int
getbits (operand_type op)
{
  if (op < MAX_OPRD)
    return crx_optab[op].bit_size;
  else
    return 0;
}

/* Return the argument type of a given operand.  */

static argtype
getargtype (operand_type op)
{
  if (op < MAX_OPRD)
    return crx_optab[op].arg_type;
  else
    return nullargs;
}

/* Given the trap index in dispatch table, return its name.
   This routine is used when disassembling the 'excp' instruction.  */

static char *
gettrapstring (unsigned int index)
{
  const trap_entry *trap;

  for (trap = crx_traps; trap < crx_traps + NUMTRAPS; trap++)
    if (trap->entry == index)
      return trap->name;

  return ILLEGAL;
}

/* Given a 'cinv' instruction constant operand, return its corresponding string.
   This routine is used when disassembling the 'cinv' instruction.  */

static char *
getcinvstring (unsigned int num)
{
  const cinv_entry *cinv;

  for (cinv = crx_cinvs; cinv < (crx_cinvs + NUMCINVS); cinv++)
    if (cinv->value == num)
      return cinv->str;

  return ILLEGAL;
}

/* Given a register enum value, retrieve its name.  */

char *
getregname (reg r)
{
  const reg_entry *reg = &crx_regtab[r];

  if (reg->type != CRX_R_REGTYPE)
    return ILLEGAL;
  else
    return reg->name;
}

/* Given a coprocessor register enum value, retrieve its name.  */

char *
getcopregname (copreg r, reg_type type)
{
  const reg_entry *reg;

  if (type == CRX_C_REGTYPE)
    reg = &crx_copregtab[r];
  else if (type == CRX_CS_REGTYPE)
    reg = &crx_copregtab[r+(cs0-c0)];
  else
    return ILLEGAL;

  return reg->name;
}


/* Getting a processor register name.  */

static char *
getprocregname (int index)
{
  const reg_entry *r;

  for (r = crx_regtab; r < crx_regtab + NUMREGS; r++)
    if (r->image == index)
      return r->name;

  return "ILLEGAL REGISTER";
}

/* Get the power of two for a given integer.  */

static int
powerof2 (int x)
{
  int product, i;

  for (i = 0, product = 1; i < x; i++)
    product *= 2;

  return product;
}

/* Transform a register bit mask to a register list.  */

void
getregliststring (int mask, char *string, enum REG_ARG_TYPE core_cop)
{
  char temp_string[5];
  int i;

  string[0] = '{';
  string[1] = '\0';


  /* A zero mask means HI/LO registers.  */
  if (mask == 0)
    {
      if (core_cop == USER_REG_ARG)
	strcat (string, "ulo,uhi");
      else
	strcat (string, "lo,hi");
    }
  else
    {
      for (i = 0; i < 16; i++)
	{
	  if (mask & 0x1)
	    {
	      switch (core_cop)
	      {
	      case REG_ARG:
		sprintf (temp_string, "r%d", i);
		break;
	      case USER_REG_ARG:
		sprintf (temp_string, "u%d", i);
		break;
	      case COP_ARG:
		sprintf (temp_string, "c%d", i);
		break;
	      case COPS_ARG:
		sprintf (temp_string, "cs%d", i);
		break;
	      default:
		break;
	      }
	      strcat (string, temp_string);
	      if (mask & 0xfffe)
		strcat (string, ",");
	    }
	  mask >>= 1;
	}
    }

  strcat (string, "}");
}

/* START and END are relating 'allWords' struct, which is 48 bits size.

			  START|--------|END
	    +---------+---------+---------+---------+
	    |	      |	   V    |     A	  |   L	    |
	    +---------+---------+---------+---------+
	    	      0		16	  32	    48
    words		  [0]	    [1]	      [2]	*/

static parameter
makelongparameter (ULONGLONG val, int start, int end)
{
  parameter p;

  p.val = (dwordU) EXTRACT(val, 48 - end, end - start);
  p.nbits = end - start;
  return p;
}

/* Build a mask of the instruction's 'constant' opcode,
   based on the instruction's printing flags.  */

static unsigned long
build_mask (void)
{
  unsigned int print_flags;
  unsigned long mask;

  print_flags = instruction->flags & FMT_CRX;
  switch (print_flags)
    {
      case FMT_1:
	mask = 0xF0F00000;
	break;
      case FMT_2:
	mask = 0xFFF0FF00;
	break;
      case FMT_3:
	mask = 0xFFF00F00;
	break;
      case FMT_4:
	mask = 0xFFF0F000;
	break;
      case FMT_5:
	mask = 0xFFF0FFF0;
	break;
      default:
	mask = SBM(instruction->match_bits);
	break;
    }

  return mask;
}

/* Search for a matching opcode. Return 1 for success, 0 for failure.  */

static int
match_opcode (void)
{
  unsigned long mask;

  /* The instruction 'constant' opcode doewsn't exceed 32 bits.  */
  unsigned long doubleWord = words[1] + (words[0] << 16);

  /* Start searching from end of instruction table.  */
  instruction = &crx_instruction[NUMOPCODES - 2];

  /* Loop over instruction table until a full match is found.  */
  while (instruction >= crx_instruction)
    {
      mask = build_mask ();
      if ((doubleWord & mask) == BIN(instruction->match, instruction->match_bits))
	return 1;
      else
	instruction--;
    }
  return 0;
}

/* Set the proper parameter value for different type of arguments.  */

static void
make_argument (argument * a, int start_bits)
{
  int inst_bit_size, total_size;
  parameter p;

  if ((instruction->size == 3) && a->size >= 16)
    inst_bit_size = 48;
  else
    inst_bit_size = 32;

  switch (a->type)
    {
    case arg_copr:
    case arg_copsr:
      p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size),
			     inst_bit_size - start_bits);
      a->cr = p.val;
      break;

    case arg_r:
      p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size),
			     inst_bit_size - start_bits);
      a->r = p.val;
      break;

    case arg_ic:
      p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size),
			     inst_bit_size - start_bits);

      if ((p.nbits == 4) && cst4flag)
        {
	  if (IS_INSN_TYPE (CMPBR_INS) && (p.val == ESCAPE_16_BIT))
	    {
	      /* A special case, where the value is actually stored
		 in the last 4 bits.  */
	      p = makelongparameter (allWords, 44, 48);
	      /* The size of the instruction should be incremented.  */
	      size_changed = 1;
	    }

          if (p.val == 6)
            p.val = -1;
          else if (p.val == 13)
            p.val = 48;
          else if (p.val == 5)
            p.val = -4;
          else if (p.val == 10)
            p.val = 32;
          else if (p.val == 11)
            p.val = 20;
          else if (p.val == 9)
            p.val = 16;
        }

      a->constant = p.val;
      break;

    case arg_idxr:
      a->scale = 0;
      total_size = a->size + 10;  /* sizeof(rbase + ridx + scl2) = 10.  */
      p = makelongparameter (allWords, inst_bit_size - total_size,
			     inst_bit_size - (total_size - 4));
      a->r = p.val;
      p = makelongparameter (allWords, inst_bit_size - (total_size - 4),
			     inst_bit_size - (total_size - 8));
      a->i_r = p.val;
      p = makelongparameter (allWords, inst_bit_size - (total_size - 8),
			     inst_bit_size - (total_size - 10));
      a->scale = p.val;
      p = makelongparameter (allWords, inst_bit_size - (total_size - 10),
			     inst_bit_size);
      a->constant = p.val;
      break;

    case arg_rbase:
      p = makelongparameter (allWords, inst_bit_size - (start_bits + 4),
			     inst_bit_size - start_bits);
      a->r = p.val;
      break;

    case arg_cr:
      if (a->size <= 8)
        {
          p = makelongparameter (allWords, inst_bit_size - (start_bits + 4),
				 inst_bit_size - start_bits);
          a->r = p.val;
          /* Case for opc4 r dispu rbase.  */
          p = makelongparameter (allWords, inst_bit_size - (start_bits + 8),
				 inst_bit_size - (start_bits + 4));
        }
      else
        {
	  /* The 'rbase' start_bits is always relative to a 32-bit data type.  */
          p = makelongparameter (allWords, 32 - (start_bits + 4),
				 32 - start_bits);
          a->r = p.val;
          p = makelongparameter (allWords, 32 - start_bits,
				 inst_bit_size);
        }
      if ((p.nbits == 4) && cst4flag)
        {
          if (instruction->flags & DISPUW4)
	    p.val *= 2;
          else if (instruction->flags & DISPUD4)
	    p.val *= 4;
        }
      a->constant = p.val;
      break;

    case arg_c:
      p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size),
			     inst_bit_size - start_bits);
      a->constant = p.val;
      break;
    default:
      break;
    }
}

/*  Print a single argument.  */

static void
print_arg (argument *a, bfd_vma memaddr, struct disassemble_info *info)
{
  LONGLONG longdisp, mask;
  int sign_flag = 0;
  int relative = 0;
  bfd_vma number;
  int op_index = 0;
  char string[200];
  PTR stream = info->stream;
  fprintf_ftype func = info->fprintf_func;

  switch (a->type)
    {
    case arg_copr:
      func (stream, "%s", getcopregname (a->cr, CRX_C_REGTYPE));
      break;

    case arg_copsr:
      func (stream, "%s", getcopregname (a->cr, CRX_CS_REGTYPE));
      break;

    case arg_r:
      if (IS_INSN_MNEMONIC ("mtpr") || IS_INSN_MNEMONIC ("mfpr"))
	func (stream, "%s", getprocregname (a->r));
      else
	func (stream, "%s", getregname (a->r));
      break;

    case arg_ic:
      if (IS_INSN_MNEMONIC ("excp"))
	func (stream, "%s", gettrapstring (a->constant));

      else if (IS_INSN_MNEMONIC ("cinv"))
	func (stream, "%s", getcinvstring (a->constant));

      else if (INST_HAS_REG_LIST)
        {
	  REG_ARG_TYPE reg_arg_type = IS_INSN_TYPE (COP_REG_INS) ? 
				 COP_ARG : IS_INSN_TYPE (COPS_REG_INS) ? 
				 COPS_ARG : (instruction->flags & USER_REG) ?
				 USER_REG_ARG : REG_ARG;

          if ((reg_arg_type == COP_ARG) || (reg_arg_type == COPS_ARG))
	    {
		/*  Check for proper argument number.  */
		if (processing_argument_number == 2)
		  {
		    getregliststring (a->constant, string, reg_arg_type);
		    func (stream, "%s", string);
		  }
		else
		  func (stream, "$0x%lx", a->constant);
	    }
	  else
            {
              getregliststring (a->constant, string, reg_arg_type);
              func (stream, "%s", string);
            }
        }
      else
	func (stream, "$0x%lx", a->constant);
      break;

    case arg_idxr:
      func (stream, "0x%lx(%s,%s,%d)", a->constant, getregname (a->r),
	    getregname (a->i_r), powerof2 (a->scale));
      break;

    case arg_rbase:
      func (stream, "(%s)", getregname (a->r));
      break;

    case arg_cr:
      func (stream, "0x%lx(%s)", a->constant, getregname (a->r));

      if (IS_INSN_TYPE (LD_STOR_INS_INC))
	func (stream, "+");
      break;

    case arg_c:
      /* Removed the *2 part as because implicit zeros are no more required.
	 Have to fix this as this needs a bit of extension in terms of branchins.
	 Have to add support for cmp and branch instructions.  */
      if (IS_INSN_TYPE (BRANCH_INS) || IS_INSN_MNEMONIC ("bal")
	  || IS_INSN_TYPE (CMPBR_INS) || IS_INSN_TYPE (DCR_BRANCH_INS)
	  || IS_INSN_TYPE (COP_BRANCH_INS))
        {
	  relative = 1;
          longdisp = a->constant;
          longdisp <<= 1;

          switch (a->size)
            {
            case 8:
	    case 16:
	    case 24:
	    case 32:
	      mask = ((LONGLONG)1 << a->size) - 1;
              if (longdisp & ((LONGLONG)1 << a->size))
                {
                  sign_flag = 1;
                  longdisp = ~(longdisp) + 1;
                }
              a->constant = (unsigned long int) (longdisp & mask);
              break;
            default:
	      func (stream,
		    "Wrong offset used in branch/bal instruction");
              break;
            }

        }
      /* For branch Neq instruction it is 2*offset + 2.  */
      else if (IS_INSN_TYPE (BRANCH_NEQ_INS))
	a->constant = 2 * a->constant + 2;
      else if (IS_INSN_TYPE (LD_STOR_INS_INC)
	  || IS_INSN_TYPE (LD_STOR_INS)
	  || IS_INSN_TYPE (STOR_IMM_INS)
	  || IS_INSN_TYPE (CSTBIT_INS))
        {
          op_index = instruction->flags & REVERSE_MATCH ? 0 : 1;
          if (instruction->operands[op_index].op_type == abs16)
	    a->constant |= 0xFFFF0000;
        }
      func (stream, "%s", "0x");
      number = (relative ? memaddr : 0)
	       + (sign_flag ? -a->constant : a->constant);
      (*info->print_address_func) (number, info);
      break;
    default:
      break;
    }
}

/* Print all the arguments of CURRINSN instruction.  */

static void
print_arguments (ins *currInsn, bfd_vma memaddr, struct disassemble_info *info)
{
  int i;

  for (i = 0; i < currInsn->nargs; i++)
    {
      processing_argument_number = i;

      print_arg (&currInsn->arg[i], memaddr, info);

      if (i != currInsn->nargs - 1)
	info->fprintf_func (info->stream, ", ");
    }
}

/* Build the instruction's arguments.  */

static void
make_instruction (void)
{
  int i;
  unsigned int shift;

  for (i = 0; i < currInsn.nargs; i++)
    {
      argument a;

      memset (&a, 0, sizeof (a));
      a.type = getargtype (instruction->operands[i].op_type);
      if (instruction->operands[i].op_type == cst4
	  || instruction->operands[i].op_type == rbase_dispu4)
	cst4flag = 1;
      a.size = getbits (instruction->operands[i].op_type);
      shift = instruction->operands[i].shift;

      make_argument (&a, shift);
      currInsn.arg[i] = a;
    }

  /* Calculate instruction size (in bytes).  */
  currInsn.size = instruction->size + (size_changed ? 1 : 0);
  /* Now in bits.  */
  currInsn.size *= 2;
}

/* Retrieve a single word from a given memory address.  */

static wordU
get_word_at_PC (bfd_vma memaddr, struct disassemble_info *info)
{
  bfd_byte buffer[4];
  int status;
  wordU insn = 0;

  status = info->read_memory_func (memaddr, buffer, 2, info);

  if (status == 0)
    insn = (wordU) bfd_getl16 (buffer);

  return insn;
}

/* Retrieve multiple words (3) from a given memory address.  */

static void
get_words_at_PC (bfd_vma memaddr, struct disassemble_info *info)
{
  int i;
  bfd_vma mem;

  for (i = 0, mem = memaddr; i < 3; i++, mem += 2)
    words[i] = get_word_at_PC (mem, info);

  allWords =
    ((ULONGLONG) words[0] << 32) + ((unsigned long) words[1] << 16) + words[2];
}

/* Prints the instruction by calling print_arguments after proper matching.  */

int
print_insn_crx (memaddr, info)
     bfd_vma memaddr;
     struct disassemble_info *info;
{
  int is_decoded;     /* Nonzero means instruction has a match.  */

  /* Initialize global variables.  */
  cst4flag = 0;
  size_changed = 0;

  /* Retrieve the encoding from current memory location.  */
  get_words_at_PC (memaddr, info);
  /* Find a matching opcode in table.  */
  is_decoded = match_opcode ();
  /* If found, print the instruction's mnemonic and arguments.  */
  if (is_decoded > 0 && (words[0] << 16 || words[1]) != 0)
    {
      info->fprintf_func (info->stream, "%s", instruction->mnemonic);
      if ((currInsn.nargs = get_number_of_operands ()) != 0)
	info->fprintf_func (info->stream, "\t");
      make_instruction ();
      print_arguments (&currInsn, memaddr, info);
      return currInsn.size;
    }

  /* No match found.  */
  info->fprintf_func (info->stream,"%s ",ILLEGAL);
  return 2;
}
Commit	Line	Data
1fe1f39c	1	/* Disassembler code for CRX.
aef6203b	2	Copyright 2004, 2005 Free Software Foundation, Inc.
1fe1f39c NC	3	Contributed by Tomer Levi, NSC, Israel.
	4	Written by Tomer Levi.
	5
	6	This file is part of the GNU binutils and GDB, the GNU debugger.
	7
	8	This program is free software; you can redistribute it and/or modify it under
	9	the terms of the GNU General Public License as published by the Free
	10	Software Foundation; either version 2, or (at your option)
	11	any later version.
	12
	13	This program is distributed in the hope that it will be useful, but WITHOUT
	14	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	15	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	16	more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this program; if not, write to the Free Software
f4321104	20	Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
1fe1f39c NC	21
	22	#include "dis-asm.h"
	23	#include "sysdep.h"
	24	#include "opcode/crx.h"
	25
	26	/* String to print when opcode was not matched. */
	27	#define ILLEGAL "illegal"
	28	/* Escape to 16-bit immediate. */
	29	#define ESCAPE_16_BIT 0xE
	30
	31	/* Extract 'n_bits' from 'a' starting from offset 'offs'. */
	32	#define EXTRACT(a, offs, n_bits) \
	33	(n_bits == 32 ? (((a) >> (offs)) & ~0L) \
	34	: (((a) >> (offs)) & ((1 << (n_bits)) -1)))
	35
	36	/* Set Bit Mask - a mask to set all bits starting from offset 'offs'. */
	37	#define SBM(offs) ((((1 << (32 - offs)) -1) << (offs)))
	38
	39	typedef unsigned long dwordU;
	40	typedef unsigned short wordU;
	41
	42	typedef struct
	43	{
	44	dwordU val;
	45	int nbits;
	46	} parameter;
	47
	48	/* Structure to hold valid 'cinv' instruction options. */
	49
	50	typedef struct
	51	{
	52	/* Cinv printed string. */
	53	char *str;
	54	/* Value corresponding to the string. */
	55	unsigned int value;
	56	}
	57	cinv_entry;
	58
	59	/* CRX 'cinv' options. */
	60	const cinv_entry crx_cinvs[] =
	61	{
48c9f030 NC	62	{"[i]", 2}, {"[i,u]", 3}, {"[d]", 4}, {"[d,u]", 5},
	63	{"[d,i]", 6}, {"[d,i,u]", 7}, {"[b]", 8},
	64	{"[b,i]", 10}, {"[b,i,u]", 11}, {"[b,d]", 12},
	65	{"[b,d,u]", 13}, {"[b,d,i]", 14}, {"[b,d,i,u]", 15}
1fe1f39c NC	66	};
1fe1f39c NC	67
a58a3762 TL	68	/* Enum to distinguish different registers argument types. */
a58a3762 TL	69	typedef enum REG_ARG_TYPE
48c9f030	70	{
a58a3762 TL	71	/* General purpose register (r<N>). */
	72	REG_ARG = 0,
	73	/* User register (u<N>). */
	74	USER_REG_ARG,
	75	/* CO-Processor register (c<N>). */
48c9f030	76	COP_ARG,
a58a3762	77	/* CO-Processor special register (cs<N>). */
48c9f030 NC	78	COPS_ARG
48c9f030 NC	79	}
a58a3762	80	REG_ARG_TYPE;
48c9f030	81
1fe1f39c NC	82	/* Number of valid 'cinv' instruction options. */
	83	int NUMCINVS = ((sizeof crx_cinvs)/(sizeof crx_cinvs[0]));
	84	/* Current opcode table entry we're disassembling. */
	85	const inst *instruction;
	86	/* Current instruction we're disassembling. */
	87	ins currInsn;
	88	/* The current instruction is read into 3 consecutive words. */
	89	wordU words[3];
	90	/* Contains all words in appropriate order. */
	91	ULONGLONG allWords;
	92	/* Holds the current processed argument number. */
	93	int processing_argument_number;
	94	/* Nonzero means a CST4 instruction. */
	95	int cst4flag;
	96	/* Nonzero means the instruction's original size is
	97	incremented (escape sequence is used). */
	98	int size_changed;
	99
	100	static int get_number_of_operands (void);
	101	static argtype getargtype (operand_type);
	102	static int getbits (operand_type);
	103	static char *getregname (reg);
	104	static char *getcopregname (copreg, reg_type);
	105	static char * getprocregname (int);
	106	static char *gettrapstring (unsigned);
	107	static char *getcinvstring (unsigned);
a58a3762	108	static void getregliststring (int, char *, enum REG_ARG_TYPE);
1fe1f39c NC	109	static wordU get_word_at_PC (bfd_vma, struct disassemble_info *);
	110	static void get_words_at_PC (bfd_vma, struct disassemble_info *);
	111	static unsigned long build_mask (void);
	112	static int powerof2 (int);
	113	static int match_opcode (void);
	114	static void make_instruction (void);
12855a36 TL	115	static void print_arguments (ins , bfd_vma, struct disassemble_info );
12855a36 TL	116	static void print_arg (argument , bfd_vma, struct disassemble_info );
1fe1f39c NC	117
	118	/* Retrieve the number of operands for the current assembled instruction. */
	119
	120	static int
	121	get_number_of_operands (void)
	122	{
	123	int i;
	124
	125	for (i = 0; instruction->operands[i].op_type && i < MAX_OPERANDS; i++)
	126	;
	127
	128	return i;
	129	}
	130
	131	/* Return the bit size for a given operand. */
	132
	133	static int
	134	getbits (operand_type op)
	135	{
	136	if (op < MAX_OPRD)
	137	return crx_optab[op].bit_size;
	138	else
	139	return 0;
	140	}
	141
	142	/* Return the argument type of a given operand. */
	143
	144	static argtype
	145	getargtype (operand_type op)
	146	{
	147	if (op < MAX_OPRD)
	148	return crx_optab[op].arg_type;
	149	else
	150	return nullargs;
	151	}
	152
	153	/* Given the trap index in dispatch table, return its name.
	154	This routine is used when disassembling the 'excp' instruction. */
	155
	156	static char *
	157	gettrapstring (unsigned int index)
	158	{
	159	const trap_entry *trap;
	160
	161	for (trap = crx_traps; trap < crx_traps + NUMTRAPS; trap++)
	162	if (trap->entry == index)
	163	return trap->name;
	164
	165	return ILLEGAL;
	166	}
	167
	168	/* Given a 'cinv' instruction constant operand, return its corresponding string.
	169	This routine is used when disassembling the 'cinv' instruction. */
	170
	171	static char *
	172	getcinvstring (unsigned int num)
	173	{
	174	const cinv_entry *cinv;
	175
	176	for (cinv = crx_cinvs; cinv < (crx_cinvs + NUMCINVS); cinv++)
	177	if (cinv->value == num)
	178	return cinv->str;
	179
	180	return ILLEGAL;
181	}
182
183	/* Given a register enum value, retrieve its name. */
184
185	char *
186	getregname (reg r)
187	{
188	const reg_entry *reg = &crx_regtab[r];
189
190	if (reg->type != CRX_R_REGTYPE)
191	return ILLEGAL;
192	else
193	return reg->name;
194	}
195
196	/* Given a coprocessor register enum value, retrieve its name. */
197
198	char *
199	getcopregname (copreg r, reg_type type)
200	{
201	const reg_entry *reg;
202
203	if (type == CRX_C_REGTYPE)
204	reg = &crx_copregtab[r];
205	else if (type == CRX_CS_REGTYPE)
206	reg = &crx_copregtab[r+(cs0-c0)];
207	else
208	return ILLEGAL;
209
210	return reg->name;
211	}
212
213
214	/* Getting a processor register name. */
215
216	static char *
217	getprocregname (int index)
218	{
219	const reg_entry *r;
220
221	for (r = crx_regtab; r < crx_regtab + NUMREGS; r++)
222	if (r->image == index)
223	return r->name;
224
225	return "ILLEGAL REGISTER";
226	}
227
228	/* Get the power of two for a given integer. */
229
230	static int
231	powerof2 (int x)
232	{
233	int product, i;
234
235	for (i = 0, product = 1; i < x; i++)
236	product *= 2;
237
238	return product;
239	}
240
241	/* Transform a register bit mask to a register list. */
242
243	void
a58a3762	244	getregliststring (int mask, char *string, enum REG_ARG_TYPE core_cop)
1fe1f39c NC	245	{
	246	char temp_string[5];
	247	int i;
	248
	249	string[0] = '{';
	250	string[1] = '\0';
	251
a58a3762 TL	252
	253	/* A zero mask means HI/LO registers. */
	254	if (mask == 0)
	255	{
	256	if (core_cop == USER_REG_ARG)
	257	strcat (string, "ulo,uhi");
	258	else
	259	strcat (string, "lo,hi");
	260	}
	261	else
1fe1f39c	262	{
a58a3762	263	for (i = 0; i < 16; i++)
48c9f030	264	{
a58a3762	265	if (mask & 0x1)
48c9f030	266	{
a58a3762 TL	267	switch (core_cop)
	268	{
	269	case REG_ARG:
	270	sprintf (temp_string, "r%d", i);
	271	break;
	272	case USER_REG_ARG:
	273	sprintf (temp_string, "u%d", i);
	274	break;
	275	case COP_ARG:
	276	sprintf (temp_string, "c%d", i);
	277	break;
	278	case COPS_ARG:
	279	sprintf (temp_string, "cs%d", i);
	280	break;
	281	default:
	282	break;
	283	}
	284	strcat (string, temp_string);
	285	if (mask & 0xfffe)
	286	strcat (string, ",");
48c9f030	287	}
a58a3762 TL	288	mask >>= 1;
a58a3762 TL	289	}
1fe1f39c NC	290	}
	291
	292	strcat (string, "}");
	293	}
	294
	295	/* START and END are relating 'allWords' struct, which is 48 bits size.
	296
	297	START\|--------\|END
	298	+---------+---------+---------+---------+
	299	\| \| V \| A \| L \|
	300	+---------+---------+---------+---------+
	301	0 16 32 48
	302	words [0] [1] [2] */
	303
	304	static parameter
	305	makelongparameter (ULONGLONG val, int start, int end)
	306	{
	307	parameter p;
	308
	309	p.val = (dwordU) EXTRACT(val, 48 - end, end - start);
	310	p.nbits = end - start;
	311	return p;
	312	}
	313
	314	/* Build a mask of the instruction's 'constant' opcode,
	315	based on the instruction's printing flags. */
	316
	317	static unsigned long
	318	build_mask (void)
	319	{
	320	unsigned int print_flags;
	321	unsigned long mask;
	322
	323	print_flags = instruction->flags & FMT_CRX;
	324	switch (print_flags)
	325	{
	326	case FMT_1:
	327	mask = 0xF0F00000;
	328	break;
	329	case FMT_2:
	330	mask = 0xFFF0FF00;
	331	break;
	332	case FMT_3:
	333	mask = 0xFFF00F00;
	334	break;
	335	case FMT_4:
	336	mask = 0xFFF0F000;
	337	break;
	338	case FMT_5:
	339	mask = 0xFFF0FFF0;
	340	break;
	341	default:
	342	mask = SBM(instruction->match_bits);
	343	break;
	344	}
	345
	346	return mask;
	347	}
	348
	349	/* Search for a matching opcode. Return 1 for success, 0 for failure. */
	350
	351	static int
	352	match_opcode (void)
	353	{
354	unsigned long mask;
355
356	/* The instruction 'constant' opcode doewsn't exceed 32 bits. */
357	unsigned long doubleWord = words[1] + (words[0] << 16);
358
359	/* Start searching from end of instruction table. */
360	instruction = &crx_instruction[NUMOPCODES - 2];
361
362	/* Loop over instruction table until a full match is found. */
363	while (instruction >= crx_instruction)
364	{
365	mask = build_mask ();
366	if ((doubleWord & mask) == BIN(instruction->match, instruction->match_bits))
367	return 1;
368	else
369	instruction--;
370	}
371	return 0;
372	}
373
374	/* Set the proper parameter value for different type of arguments. */
375
376	static void
377	make_argument (argument * a, int start_bits)
378	{
379	int inst_bit_size, total_size;
380	parameter p;
381
382	if ((instruction->size == 3) && a->size >= 16)
383	inst_bit_size = 48;
384	else
385	inst_bit_size = 32;
386
387	switch (a->type)
388	{
389	case arg_copr:
390	case arg_copsr:
391	p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size),
392	inst_bit_size - start_bits);
393	a->cr = p.val;
394	break;
395
396	case arg_r:
397	p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size),
398	inst_bit_size - start_bits);
399	a->r = p.val;
400	break;
401
402	case arg_ic:
403	p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size),
404	inst_bit_size - start_bits);
405
406	if ((p.nbits == 4) && cst4flag)
407	{
408	if (IS_INSN_TYPE (CMPBR_INS) && (p.val == ESCAPE_16_BIT))
409	{
410	/* A special case, where the value is actually stored
411	in the last 4 bits. */
412	p = makelongparameter (allWords, 44, 48);
413	/* The size of the instruction should be incremented. */
414	size_changed = 1;
415	}
416
417	if (p.val == 6)
418	p.val = -1;
419	else if (p.val == 13)
420	p.val = 48;
421	else if (p.val == 5)
422	p.val = -4;
423	else if (p.val == 10)
424	p.val = 32;
425	else if (p.val == 11)
426	p.val = 20;
427	else if (p.val == 9)
428	p.val = 16;
429	}
430
431	a->constant = p.val;
432	break;
433
42048ee7	434	case arg_idxr:
1fe1f39c NC	435	a->scale = 0;
	436	total_size = a->size + 10; /* sizeof(rbase + ridx + scl2) = 10. */
	437	p = makelongparameter (allWords, inst_bit_size - total_size,
	438	inst_bit_size - (total_size - 4));
	439	a->r = p.val;
	440	p = makelongparameter (allWords, inst_bit_size - (total_size - 4),
	441	inst_bit_size - (total_size - 8));
	442	a->i_r = p.val;
	443	p = makelongparameter (allWords, inst_bit_size - (total_size - 8),
	444	inst_bit_size - (total_size - 10));
	445	a->scale = p.val;
	446	p = makelongparameter (allWords, inst_bit_size - (total_size - 10),
	447	inst_bit_size);
	448	a->constant = p.val;
	449	break;
	450
	451	case arg_rbase:
	452	p = makelongparameter (allWords, inst_bit_size - (start_bits + 4),
	453	inst_bit_size - start_bits);
	454	a->r = p.val;
	455	break;
	456
	457	case arg_cr:
	458	if (a->size <= 8)
	459	{
	460	p = makelongparameter (allWords, inst_bit_size - (start_bits + 4),
	461	inst_bit_size - start_bits);
	462	a->r = p.val;
	463	/* Case for opc4 r dispu rbase. */
	464	p = makelongparameter (allWords, inst_bit_size - (start_bits + 8),
	465	inst_bit_size - (start_bits + 4));
	466	}
	467	else
	468	{
	469	/* The 'rbase' start_bits is always relative to a 32-bit data type. */
	470	p = makelongparameter (allWords, 32 - (start_bits + 4),
	471	32 - start_bits);
	472	a->r = p.val;
	473	p = makelongparameter (allWords, 32 - start_bits,
	474	inst_bit_size);
	475	}
	476	if ((p.nbits == 4) && cst4flag)
	477	{
	478	if (instruction->flags & DISPUW4)
	479	p.val *= 2;
	480	else if (instruction->flags & DISPUD4)
	481	p.val *= 4;
	482	}
	483	a->constant = p.val;
	484	break;
	485
	486	case arg_c:
	487	p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size),
	488	inst_bit_size - start_bits);
	489	a->constant = p.val;
	490	break;
	491	default:
	492	break;
	493	}
	494	}
	495
	496	/* Print a single argument. */
	497
	498	static void
12855a36	499	print_arg (argument a, bfd_vma memaddr, struct disassemble_info info)
1fe1f39c NC	500	{
1fe1f39c NC	501	LONGLONG longdisp, mask;
12855a36 TL	502	int sign_flag = 0;
	503	int relative = 0;
	504	bfd_vma number;
1fe1f39c NC	505	int op_index = 0;
	506	char string[200];
	507	PTR stream = info->stream;
	508	fprintf_ftype func = info->fprintf_func;
	509
	510	switch (a->type)
	511	{
	512	case arg_copr:
	513	func (stream, "%s", getcopregname (a->cr, CRX_C_REGTYPE));
	514	break;
	515
	516	case arg_copsr:
	517	func (stream, "%s", getcopregname (a->cr, CRX_CS_REGTYPE));
	518	break;
	519
	520	case arg_r:
	521	if (IS_INSN_MNEMONIC ("mtpr") \|\| IS_INSN_MNEMONIC ("mfpr"))
	522	func (stream, "%s", getprocregname (a->r));
	523	else
	524	func (stream, "%s", getregname (a->r));
	525	break;
	526
	527	case arg_ic:
	528	if (IS_INSN_MNEMONIC ("excp"))
	529	func (stream, "%s", gettrapstring (a->constant));
	530
	531	else if (IS_INSN_MNEMONIC ("cinv"))
	532	func (stream, "%s", getcinvstring (a->constant));
	533
	534	else if (INST_HAS_REG_LIST)
	535	{
a58a3762	536	REG_ARG_TYPE reg_arg_type = IS_INSN_TYPE (COP_REG_INS) ?
48c9f030	537	COP_ARG : IS_INSN_TYPE (COPS_REG_INS) ?
a58a3762 TL	538	COPS_ARG : (instruction->flags & USER_REG) ?
a58a3762 TL	539	USER_REG_ARG : REG_ARG;
48c9f030	540
a58a3762	541	if ((reg_arg_type == COP_ARG) \|\| (reg_arg_type == COPS_ARG))
48c9f030	542	{
a58a3762 TL	543	/* Check for proper argument number. */
	544	if (processing_argument_number == 2)
	545	{
	546	getregliststring (a->constant, string, reg_arg_type);
	547	func (stream, "%s", string);
	548	}
	549	else
0fd3a477	550	func (stream, "$0x%lx", a->constant);
48c9f030 NC	551	}
48c9f030 NC	552	else
1fe1f39c	553	{
a58a3762	554	getregliststring (a->constant, string, reg_arg_type);
1fe1f39c NC	555	func (stream, "%s", string);
1fe1f39c NC	556	}
1fe1f39c NC	557	}
1fe1f39c NC	558	else
0fd3a477	559	func (stream, "$0x%lx", a->constant);
1fe1f39c NC	560	break;
1fe1f39c NC	561
42048ee7	562	case arg_idxr:
0fd3a477	563	func (stream, "0x%lx(%s,%s,%d)", a->constant, getregname (a->r),
1fe1f39c NC	564	getregname (a->i_r), powerof2 (a->scale));
	565	break;
	566
	567	case arg_rbase:
	568	func (stream, "(%s)", getregname (a->r));
	569	break;
	570
	571	case arg_cr:
0fd3a477	572	func (stream, "0x%lx(%s)", a->constant, getregname (a->r));
1fe1f39c NC	573
	574	if (IS_INSN_TYPE (LD_STOR_INS_INC))
	575	func (stream, "+");
	576	break;
	577
	578	case arg_c:
	579	/* Removed the *2 part as because implicit zeros are no more required.
	580	Have to fix this as this needs a bit of extension in terms of branchins.
	581	Have to add support for cmp and branch instructions. */
	582	if (IS_INSN_TYPE (BRANCH_INS) \|\| IS_INSN_MNEMONIC ("bal")
	583	\|\| IS_INSN_TYPE (CMPBR_INS) \|\| IS_INSN_TYPE (DCR_BRANCH_INS)
	584	\|\| IS_INSN_TYPE (COP_BRANCH_INS))
	585	{
12855a36	586	relative = 1;
1fe1f39c NC	587	longdisp = a->constant;
1fe1f39c NC	588	longdisp <<= 1;
1fe1f39c NC	589
	590	switch (a->size)
	591	{
	592	case 8:
	593	case 16:
	594	case 24:
	595	case 32:
	596	mask = ((LONGLONG)1 << a->size) - 1;
	597	if (longdisp & ((LONGLONG)1 << a->size))
	598	{
12855a36	599	sign_flag = 1;
1fe1f39c NC	600	longdisp = ~(longdisp) + 1;
	601	}
	602	a->constant = (unsigned long int) (longdisp & mask);
	603	break;
	604	default:
	605	func (stream,
	606	"Wrong offset used in branch/bal instruction");
	607	break;
	608	}
	609
1fe1f39c NC	610	}
1fe1f39c NC	611	/* For branch Neq instruction it is 2offset + 2. /
12855a36	612	else if (IS_INSN_TYPE (BRANCH_NEQ_INS))
1fe1f39c	613	a->constant = 2 * a->constant + 2;
12855a36	614	else if (IS_INSN_TYPE (LD_STOR_INS_INC)
1fe1f39c NC	615	\|\| IS_INSN_TYPE (LD_STOR_INS)
	616	\|\| IS_INSN_TYPE (STOR_IMM_INS)
	617	\|\| IS_INSN_TYPE (CSTBIT_INS))
	618	{
	619	op_index = instruction->flags & REVERSE_MATCH ? 0 : 1;
	620	if (instruction->operands[op_index].op_type == abs16)
	621	a->constant \|= 0xFFFF0000;
	622	}
12855a36 TL	623	func (stream, "%s", "0x");
	624	number = (relative ? memaddr : 0)
	625	+ (sign_flag ? -a->constant : a->constant);
	626	(*info->print_address_func) (number, info);
1fe1f39c NC	627	break;
	628	default:
	629	break;
	630	}
	631	}
	632
	633	/* Print all the arguments of CURRINSN instruction. */
	634
	635	static void
12855a36	636	print_arguments (ins currInsn, bfd_vma memaddr, struct disassemble_info info)
1fe1f39c NC	637	{
	638	int i;
	639
	640	for (i = 0; i < currInsn->nargs; i++)
	641	{
	642	processing_argument_number = i;
	643
12855a36	644	print_arg (&currInsn->arg[i], memaddr, info);
1fe1f39c NC	645
	646	if (i != currInsn->nargs - 1)
	647	info->fprintf_func (info->stream, ", ");
	648	}
	649	}
	650
	651	/* Build the instruction's arguments. */
	652
	653	static void
	654	make_instruction (void)
	655	{
	656	int i;
89a649f7	657	unsigned int shift;
1fe1f39c NC	658
	659	for (i = 0; i < currInsn.nargs; i++)
	660	{
47d8304e	661	argument a;
ec36c4a4	662
47d8304e	663	memset (&a, 0, sizeof (a));
1fe1f39c NC	664	a.type = getargtype (instruction->operands[i].op_type);
1fe1f39c NC	665	if (instruction->operands[i].op_type == cst4
89a649f7	666	\|\| instruction->operands[i].op_type == rbase_dispu4)
1fe1f39c NC	667	cst4flag = 1;
	668	a.size = getbits (instruction->operands[i].op_type);
	669	shift = instruction->operands[i].shift;
	670
	671	make_argument (&a, shift);
	672	currInsn.arg[i] = a;
	673	}
	674
	675	/* Calculate instruction size (in bytes). */
	676	currInsn.size = instruction->size + (size_changed ? 1 : 0);
89a649f7	677	/* Now in bits. */
1fe1f39c	678	currInsn.size *= 2;
1fe1f39c NC	679	}
	680
	681	/* Retrieve a single word from a given memory address. */
	682
	683	static wordU
	684	get_word_at_PC (bfd_vma memaddr, struct disassemble_info *info)
	685	{
	686	bfd_byte buffer[4];
	687	int status;
	688	wordU insn = 0;
	689
	690	status = info->read_memory_func (memaddr, buffer, 2, info);
	691
	692	if (status == 0)
	693	insn = (wordU) bfd_getl16 (buffer);
	694
	695	return insn;
	696	}
	697
	698	/* Retrieve multiple words (3) from a given memory address. */
	699
	700	static void
	701	get_words_at_PC (bfd_vma memaddr, struct disassemble_info *info)
	702	{
	703	int i;
	704	bfd_vma mem;
	705
	706	for (i = 0, mem = memaddr; i < 3; i++, mem += 2)
	707	words[i] = get_word_at_PC (mem, info);
	708
	709	allWords =
	710	((ULONGLONG) words[0] << 32) + ((unsigned long) words[1] << 16) + words[2];
	711	}
	712
	713	/* Prints the instruction by calling print_arguments after proper matching. */
	714
	715	int
	716	print_insn_crx (memaddr, info)
	717	bfd_vma memaddr;
	718	struct disassemble_info *info;
	719	{
	720	int is_decoded; /* Nonzero means instruction has a match. */
	721
	722	/* Initialize global variables. */
	723	cst4flag = 0;
	724	size_changed = 0;
	725
	726	/* Retrieve the encoding from current memory location. */
	727	get_words_at_PC (memaddr, info);
	728	/* Find a matching opcode in table. */
	729	is_decoded = match_opcode ();
	730	/* If found, print the instruction's mnemonic and arguments. */
	731	if (is_decoded > 0 && (words[0] << 16 \|\| words[1]) != 0)
	732	{
	733	info->fprintf_func (info->stream, "%s", instruction->mnemonic);
	734	if ((currInsn.nargs = get_number_of_operands ()) != 0)
	735	info->fprintf_func (info->stream, "\t");
	736	make_instruction ();
12855a36	737	print_arguments (&currInsn, memaddr, info);
1fe1f39c NC	738	return currInsn.size;
	739	}
	740
	741	/* No match found. */
	742	info->fprintf_func (info->stream,"%s ",ILLEGAL);
	743	return 2;
	744	}