[deliverable/binutils-gdb.git] / opcodes / d30v-dis.c

/* Disassemble D30V instructions.
   Copyright (C) 1997-2019 Free Software Foundation, Inc.

   This file is part of the GNU opcodes library.

   This library is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
   MA 02110-1301, USA.  */

#include "sysdep.h"
#include <stdio.h>
#include "opcode/d30v.h"
#include "disassemble.h"
#include "opintl.h"
#include "libiberty.h"

#define PC_MASK 0xFFFFFFFF

/* Return 0 if lookup fails,
   1 if found and only one form,
   2 if found and there are short and long forms.  */

static int
lookup_opcode (struct d30v_insn *insn, long num, int is_long)
{
  int i = 0, op_index;
  struct d30v_format *f;
  struct d30v_opcode *op = (struct d30v_opcode *) d30v_opcode_table;
  int op1 = (num >> 25) & 0x7;
  int op2 = (num >> 20) & 0x1f;
  int mod = (num >> 18) & 0x3;

  /* Find the opcode.  */
  do
    {
      if ((op->op1 == op1) && (op->op2 == op2))
	break;
      op++;
    }
  while (op->name);

  if (!op || !op->name)
    return 0;

  while (op->op1 == op1 && op->op2 == op2)
    {
      /* Scan through all the formats for the opcode.  */
      op_index = op->format[i++];
      do
	{
	  f = (struct d30v_format *) &d30v_format_table[op_index];
	  while (f->form == op_index)
	    {
	      if ((!is_long || f->form >= LONG) && (f->modifier == mod))
		{
		  insn->form = f;
		  break;
		}
	      f++;
	    }
	  if (insn->form)
	    break;
	}
      while ((op_index = op->format[i++]) != 0);
      if (insn->form)
	break;
      op++;
      i = 0;
    }
  if (insn->form == NULL)
    return 0;

  insn->op = op;
  insn->ecc = (num >> 28) & 0x7;
  if (op->format[1])
    return 2;
  else
    return 1;
}

static int
extract_value (long long num, struct d30v_operand *oper, int is_long)
{
  int val;
  int shift = 12 - oper->position;
  int mask = (0xFFFFFFFF >> (32 - oper->bits));

  if (is_long)
    {
      if (oper->bits == 32)
	/* Piece together 32-bit constant.  */
	val = ((num & 0x3FFFF)
	       | ((num & 0xFF00000) >> 2)
	       | ((num & 0x3F00000000LL) >> 6));
      else
	val = (num >> (32 + shift)) & mask;
    }
  else
    val = (num >> shift) & mask;

  if (oper->flags & OPERAND_SHIFT)
    val <<= 3;

  return val;
}

static void
print_insn (struct disassemble_info *info,
	    bfd_vma memaddr,
	    long long num,
	    struct d30v_insn *insn,
	    int is_long,
	    int show_ext)
{
  int val, opnum, need_comma = 0;
  struct d30v_operand *oper;
  int i, match, need_paren = 0, found_control = 0;
  unsigned int opind = 0;

  (*info->fprintf_func) (info->stream, "%s", insn->op->name);

  /* Check for CMP or CMPU.  */
  if (d30v_operand_table[insn->form->operands[0]].flags & OPERAND_NAME)
    {
      opind++;
      val =
	extract_value (num,
		       (struct d30v_operand *) &d30v_operand_table[insn->form->operands[0]],
		       is_long);
      (*info->fprintf_func) (info->stream, "%s", d30v_cc_names[val]);
    }

  /* Add in ".s" or ".l".  */
  if (show_ext == 2)
    {
      if (is_long)
	(*info->fprintf_func) (info->stream, ".l");
      else
	(*info->fprintf_func) (info->stream, ".s");
    }

  if (insn->ecc)
    (*info->fprintf_func) (info->stream, "/%s", d30v_ecc_names[insn->ecc]);

  (*info->fprintf_func) (info->stream, "\t");

  while (opind < ARRAY_SIZE (insn->form->operands)
	 && (opnum = insn->form->operands[opind++]) != 0)
    {
      int bits;

      oper = (struct d30v_operand *) &d30v_operand_table[opnum];
      bits = oper->bits;
      if (oper->flags & OPERAND_SHIFT)
	bits += 3;

      if (need_comma
	  && oper->flags != OPERAND_PLUS
	  && oper->flags != OPERAND_MINUS)
	{
	  need_comma = 0;
	  (*info->fprintf_func) (info->stream, ", ");
	}

      if (oper->flags == OPERAND_ATMINUS)
	{
	  (*info->fprintf_func) (info->stream, "@-");
	  continue;
	}
      if (oper->flags == OPERAND_MINUS)
	{
	  (*info->fprintf_func) (info->stream, "-");
	  continue;
	}
      if (oper->flags == OPERAND_PLUS)
	{
	  (*info->fprintf_func) (info->stream, "+");
	  continue;
	}
      if (oper->flags == OPERAND_ATSIGN)
	{
	  (*info->fprintf_func) (info->stream, "@");
	  continue;
	}
      if (oper->flags == OPERAND_ATPAR)
	{
	  (*info->fprintf_func) (info->stream, "@(");
	  need_paren = 1;
	  continue;
	}

      if (oper->flags == OPERAND_SPECIAL)
	continue;

      val = extract_value (num, oper, is_long);

      if (oper->flags & OPERAND_REG)
	{
	  match = 0;
	  if (oper->flags & OPERAND_CONTROL)
	    {
	      struct d30v_operand *oper3 =
		(struct d30v_operand *) &d30v_operand_table[insn->form->operands[2]];
	      int id = extract_value (num, oper3, is_long);

	      found_control = 1;
	      switch (id)
		{
		case 0:
		  val |= OPERAND_CONTROL;
		  break;
		case 1:
		case 2:
		  val = OPERAND_CONTROL + MAX_CONTROL_REG + id;
		  break;
		case 3:
		  val |= OPERAND_FLAG;
		  break;
		default:
		  /* xgettext: c-format */
		  opcodes_error_handler (_("illegal id (%d)"), id);
		  abort ();
		}
	    }
	  else if (oper->flags & OPERAND_ACC)
	    val |= OPERAND_ACC;
	  else if (oper->flags & OPERAND_FLAG)
	    val |= OPERAND_FLAG;
	  for (i = 0; i < reg_name_cnt (); i++)
	    {
	      if (val == pre_defined_registers[i].value)
		{
		  if (pre_defined_registers[i].pname)
		    (*info->fprintf_func)
		      (info->stream, "%s", pre_defined_registers[i].pname);
		  else
		    (*info->fprintf_func)
		      (info->stream, "%s", pre_defined_registers[i].name);
		  match = 1;
		  break;
		}
	    }
	  if (match == 0)
	    {
	      /* This would only get executed if a register was not in
		 the register table.  */
	      (*info->fprintf_func)
		(info->stream, _("<unknown register %d>"), val & 0x3F);
	    }
	}
      /* repeati has a relocation, but its first argument is a plain
	 immediate.  OTOH instructions like djsri have a pc-relative
	 delay target, but an absolute jump target.  Therefore, a test
	 of insn->op->reloc_flag is not specific enough; we must test
	 if the actual operand we are handling now is pc-relative.  */
      else if (oper->flags & OPERAND_PCREL)
	{
	  int neg = 0;

	  /* IMM6S3 is unsigned.  */
	  if (oper->flags & OPERAND_SIGNED || bits == 32)
	    {
	      long max;
	      max = (1 << (bits - 1));
	      if (val & max)
		{
		  if (bits == 32)
		    val = -val;
		  else
		    val = -val & ((1 << bits) - 1);
		  neg = 1;
		}
	    }
	  if (neg)
	    {
	      (*info->fprintf_func) (info->stream, "-%x\t(", val);
	      (*info->print_address_func) ((memaddr - val) & PC_MASK, info);
	      (*info->fprintf_func) (info->stream, ")");
	    }
	  else
	    {
	      (*info->fprintf_func) (info->stream, "%x\t(", val);
	      (*info->print_address_func) ((memaddr + val) & PC_MASK, info);
	      (*info->fprintf_func) (info->stream, ")");
	    }
	}
      else if (insn->op->reloc_flag == RELOC_ABS)
	{
	  (*info->print_address_func) (val, info);
	}
      else
	{
	  if (oper->flags & OPERAND_SIGNED)
	    {
	      int max = (1 << (bits - 1));

	      if (val & max)
		{
		  val = -val;
		  if (bits < 32)
		    val &= ((1 << bits) - 1);
		  (*info->fprintf_func) (info->stream, "-");
		}
	    }
	  (*info->fprintf_func) (info->stream, "0x%x", val);
	}
      /* If there is another operand, then write a comma and space.  */
      if (opind < ARRAY_SIZE (insn->form->operands)
	  && insn->form->operands[opind]
	  && !(found_control && opind == 2))
	need_comma = 1;
    }
  if (need_paren)
    (*info->fprintf_func) (info->stream, ")");
}

int
print_insn_d30v (bfd_vma memaddr, struct disassemble_info *info)
{
  int status, result;
  bfd_byte buffer[12];
  unsigned long in1, in2;
  struct d30v_insn insn;
  long long num;

  insn.form = NULL;

  info->bytes_per_line = 8;
  info->bytes_per_chunk = 4;
  info->display_endian = BFD_ENDIAN_BIG;

  status = (*info->read_memory_func) (memaddr, buffer, 4, info);
  if (status != 0)
    {
      (*info->memory_error_func) (status, memaddr, info);
      return -1;
    }
  in1 = bfd_getb32 (buffer);

  status = (*info->read_memory_func) (memaddr + 4, buffer, 4, info);
  if (status != 0)
    {
      info->bytes_per_line = 8;
      if (!(result = lookup_opcode (&insn, in1, 0)))
	(*info->fprintf_func) (info->stream, ".long\t0x%lx", in1);
      else
	print_insn (info, memaddr, (long long) in1, &insn, 0, result);
      return 4;
    }
  in2 = bfd_getb32 (buffer);

  if (in1 & in2 & FM01)
    {
      /* LONG instruction.  */
      if (!(result = lookup_opcode (&insn, in1, 1)))
	{
	  (*info->fprintf_func) (info->stream, ".long\t0x%lx,0x%lx", in1, in2);
	  return 8;
	}
      num = (long long) in1 << 32 | in2;
      print_insn (info, memaddr, num, &insn, 1, result);
    }
  else
    {
      num = in1;
      if (!(result = lookup_opcode (&insn, in1, 0)))
	(*info->fprintf_func) (info->stream, ".long\t0x%lx", in1);
      else
	print_insn (info, memaddr, num, &insn, 0, result);

      switch (((in1 >> 31) << 1) | (in2 >> 31))
	{
	case 0:
	  (*info->fprintf_func) (info->stream, "\t||\t");
	  break;
	case 1:
	  (*info->fprintf_func) (info->stream, "\t->\t");
	  break;
	case 2:
	  (*info->fprintf_func) (info->stream, "\t<-\t");
	default:
	  break;
	}

      insn.form = NULL;
      num = in2;
      if (!(result = lookup_opcode (&insn, in2, 0)))
	(*info->fprintf_func) (info->stream, ".long\t0x%lx", in2);
      else
	print_insn (info, memaddr, num, &insn, 0, result);
    }
  return 8;
}
Commit	Line	Data
252b5132	1	/* Disassemble D30V instructions.
82704155	2	Copyright (C) 1997-2019 Free Software Foundation, Inc.
252b5132	3
9b201bb5 NC	4	This file is part of the GNU opcodes library.
	5
	6	This library is free software; you can redistribute it and/or modify
47b0e7ad	7	it under the terms of the GNU General Public License as published by
9b201bb5 NC	8	the Free Software Foundation; either version 3, or (at your option)
9b201bb5 NC	9	any later version.
252b5132	10
9b201bb5 NC	11	It is distributed in the hope that it will be useful, but WITHOUT
	12	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	13	or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	14	License for more details.
252b5132	15
47b0e7ad NC	16	You should have received a copy of the GNU General Public License
	17	along with this program; if not, write to the Free Software
	18	Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
	19	MA 02110-1301, USA. */
252b5132	20
0d8dfecf	21	#include "sysdep.h"
df7b86aa	22	#include <stdio.h>
2dcee538	23	#include "opcode/d30v.h"
88c1242d	24	#include "disassemble.h"
252b5132	25	#include "opintl.h"
9adb2591	26	#include "libiberty.h"
252b5132 RH	27
	28	#define PC_MASK 0xFFFFFFFF
	29
2dcee538 KH	30	/* Return 0 if lookup fails,
	31	1 if found and only one form,
	32	2 if found and there are short and long forms. */
252b5132	33
252b5132	34	static int
47b0e7ad	35	lookup_opcode (struct d30v_insn *insn, long num, int is_long)
252b5132	36	{
91d6fa6a	37	int i = 0, op_index;
252b5132	38	struct d30v_format *f;
2dcee538	39	struct d30v_opcode op = (struct d30v_opcode ) d30v_opcode_table;
252b5132 RH	40	int op1 = (num >> 25) & 0x7;
	41	int op2 = (num >> 20) & 0x1f;
	42	int mod = (num >> 18) & 0x3;
	43
2dcee538 KH	44	/* Find the opcode. */
	45	do
	46	{
	47	if ((op->op1 == op1) && (op->op2 == op2))
	48	break;
	49	op++;
	50	}
	51	while (op->name);
252b5132 RH	52
	53	if (!op \|\| !op->name)
	54	return 0;
	55
	56	while (op->op1 == op1 && op->op2 == op2)
	57	{
2dcee538	58	/* Scan through all the formats for the opcode. */
91d6fa6a	59	op_index = op->format[i++];
2dcee538	60	do
252b5132	61	{
91d6fa6a NC	62	f = (struct d30v_format *) &d30v_format_table[op_index];
91d6fa6a NC	63	while (f->form == op_index)
252b5132 RH	64	{
	65	if ((!is_long \|\| f->form >= LONG) && (f->modifier == mod))
	66	{
	67	insn->form = f;
	68	break;
	69	}
	70	f++;
	71	}
	72	if (insn->form)
	73	break;
2dcee538	74	}
91d6fa6a	75	while ((op_index = op->format[i++]) != 0);
252b5132 RH	76	if (insn->form)
	77	break;
	78	op++;
2dcee538	79	i = 0;
252b5132 RH	80	}
	81	if (insn->form == NULL)
	82	return 0;
	83
	84	insn->op = op;
	85	insn->ecc = (num >> 28) & 0x7;
	86	if (op->format[1])
	87	return 2;
	88	else
	89	return 1;
	90	}
	91
47b0e7ad NC	92	static int
	93	extract_value (long long num, struct d30v_operand *oper, int is_long)
	94	{
	95	int val;
	96	int shift = 12 - oper->position;
	97	int mask = (0xFFFFFFFF >> (32 - oper->bits));
	98
	99	if (is_long)
	100	{
	101	if (oper->bits == 32)
	102	/* Piece together 32-bit constant. */
	103	val = ((num & 0x3FFFF)
	104	\| ((num & 0xFF00000) >> 2)
	105	\| ((num & 0x3F00000000LL) >> 6));
	106	else
	107	val = (num >> (32 + shift)) & mask;
	108	}
	109	else
	110	val = (num >> shift) & mask;
	111
	112	if (oper->flags & OPERAND_SHIFT)
	113	val <<= 3;
	114
	115	return val;
	116	}
	117
2dcee538	118	static void
47b0e7ad NC	119	print_insn (struct disassemble_info *info,
	120	bfd_vma memaddr,
	121	long long num,
	122	struct d30v_insn *insn,
	123	int is_long,
	124	int show_ext)
252b5132	125	{
2dcee538	126	int val, opnum, need_comma = 0;
252b5132	127	struct d30v_operand *oper;
159653d8 AM	128	int i, match, need_paren = 0, found_control = 0;
159653d8 AM	129	unsigned int opind = 0;
252b5132	130
2dcee538	131	(*info->fprintf_func) (info->stream, "%s", insn->op->name);
252b5132	132
2dcee538	133	/* Check for CMP or CMPU. */
252b5132 RH	134	if (d30v_operand_table[insn->form->operands[0]].flags & OPERAND_NAME)
	135	{
	136	opind++;
2dcee538 KH	137	val =
	138	extract_value (num,
	139	(struct d30v_operand *) &d30v_operand_table[insn->form->operands[0]],
	140	is_long);
	141	(*info->fprintf_func) (info->stream, "%s", d30v_cc_names[val]);
252b5132 RH	142	}
252b5132 RH	143
2dcee538	144	/* Add in ".s" or ".l". */
252b5132 RH	145	if (show_ext == 2)
	146	{
	147	if (is_long)
	148	(*info->fprintf_func) (info->stream, ".l");
	149	else
	150	(*info->fprintf_func) (info->stream, ".s");
	151	}
	152
	153	if (insn->ecc)
2dcee538	154	(*info->fprintf_func) (info->stream, "/%s", d30v_ecc_names[insn->ecc]);
252b5132 RH	155
	156	(*info->fprintf_func) (info->stream, "\t");
	157
159653d8 AM	158	while (opind < ARRAY_SIZE (insn->form->operands)
159653d8 AM	159	&& (opnum = insn->form->operands[opind++]) != 0)
252b5132 RH	160	{
252b5132 RH	161	int bits;
47b0e7ad	162
2dcee538	163	oper = (struct d30v_operand *) &d30v_operand_table[opnum];
252b5132 RH	164	bits = oper->bits;
	165	if (oper->flags & OPERAND_SHIFT)
	166	bits += 3;
	167
2dcee538 KH	168	if (need_comma
	169	&& oper->flags != OPERAND_PLUS
	170	&& oper->flags != OPERAND_MINUS)
252b5132	171	{
2dcee538	172	need_comma = 0;
252b5132 RH	173	(*info->fprintf_func) (info->stream, ", ");
	174	}
	175
	176	if (oper->flags == OPERAND_ATMINUS)
	177	{
	178	(*info->fprintf_func) (info->stream, "@-");
	179	continue;
	180	}
	181	if (oper->flags == OPERAND_MINUS)
	182	{
2dcee538	183	(*info->fprintf_func) (info->stream, "-");
252b5132 RH	184	continue;
	185	}
	186	if (oper->flags == OPERAND_PLUS)
	187	{
2dcee538	188	(*info->fprintf_func) (info->stream, "+");
252b5132 RH	189	continue;
	190	}
	191	if (oper->flags == OPERAND_ATSIGN)
	192	{
2dcee538	193	(*info->fprintf_func) (info->stream, "@");
252b5132 RH	194	continue;
	195	}
	196	if (oper->flags == OPERAND_ATPAR)
	197	{
2dcee538	198	(*info->fprintf_func) (info->stream, "@(");
252b5132 RH	199	need_paren = 1;
	200	continue;
	201	}
	202
	203	if (oper->flags == OPERAND_SPECIAL)
	204	continue;
	205
2dcee538 KH	206	val = extract_value (num, oper, is_long);
2dcee538 KH	207
252b5132 RH	208	if (oper->flags & OPERAND_REG)
	209	{
	210	match = 0;
	211	if (oper->flags & OPERAND_CONTROL)
	212	{
2dcee538 KH	213	struct d30v_operand *oper3 =
	214	(struct d30v_operand *) &d30v_operand_table[insn->form->operands[2]];
	215	int id = extract_value (num, oper3, is_long);
47b0e7ad	216
252b5132	217	found_control = 1;
2dcee538	218	switch (id)
252b5132 RH	219	{
	220	case 0:
	221	val \|= OPERAND_CONTROL;
	222	break;
	223	case 1:
	224	case 2:
	225	val = OPERAND_CONTROL + MAX_CONTROL_REG + id;
	226	break;
	227	case 3:
	228	val \|= OPERAND_FLAG;
	229	break;
	230	default:
a6743a54 AM	231	/* xgettext: c-format */
	232	opcodes_error_handler (_("illegal id (%d)"), id);
	233	abort ();
252b5132 RH	234	}
	235	}
	236	else if (oper->flags & OPERAND_ACC)
	237	val \|= OPERAND_ACC;
	238	else if (oper->flags & OPERAND_FLAG)
	239	val \|= OPERAND_FLAG;
2dcee538	240	for (i = 0; i < reg_name_cnt (); i++)
252b5132 RH	241	{
	242	if (val == pre_defined_registers[i].value)
	243	{
	244	if (pre_defined_registers[i].pname)
	245	(*info->fprintf_func)
2dcee538	246	(info->stream, "%s", pre_defined_registers[i].pname);
252b5132 RH	247	else
252b5132 RH	248	(*info->fprintf_func)
2dcee538 KH	249	(info->stream, "%s", pre_defined_registers[i].name);
2dcee538 KH	250	match = 1;
252b5132 RH	251	break;
	252	}
	253	}
2dcee538	254	if (match == 0)
252b5132	255	{
2dcee538 KH	256	/* This would only get executed if a register was not in
2dcee538 KH	257	the register table. */
252b5132	258	(*info->fprintf_func)
2dcee538	259	(info->stream, _("<unknown register %d>"), val & 0x3F);
252b5132 RH	260	}
252b5132 RH	261	}
866afedc NC	262	/* repeati has a relocation, but its first argument is a plain
866afedc NC	263	immediate. OTOH instructions like djsri have a pc-relative
d9a35582	264	delay target, but an absolute jump target. Therefore, a test
866afedc NC	265	of insn->op->reloc_flag is not specific enough; we must test
	266	if the actual operand we are handling now is pc-relative. */
	267	else if (oper->flags & OPERAND_PCREL)
252b5132	268	{
866afedc	269	int neg = 0;
2dcee538	270
866afedc NC	271	/* IMM6S3 is unsigned. */
866afedc NC	272	if (oper->flags & OPERAND_SIGNED \|\| bits == 32)
252b5132	273	{
866afedc NC	274	long max;
	275	max = (1 << (bits - 1));
	276	if (val & max)
	277	{
	278	if (bits == 32)
	279	val = -val;
	280	else
2dcee538	281	val = -val & ((1 << bits) - 1);
866afedc NC	282	neg = 1;
	283	}
	284	}
	285	if (neg)
	286	{
2dcee538	287	(*info->fprintf_func) (info->stream, "-%x\t(", val);
866afedc NC	288	(*info->print_address_func) ((memaddr - val) & PC_MASK, info);
866afedc NC	289	(*info->fprintf_func) (info->stream, ")");
252b5132	290	}
866afedc	291	else
252b5132	292	{
2dcee538	293	(*info->fprintf_func) (info->stream, "%x\t(", val);
866afedc NC	294	(*info->print_address_func) ((memaddr + val) & PC_MASK, info);
866afedc NC	295	(*info->fprintf_func) (info->stream, ")");
252b5132	296	}
252b5132 RH	297	}
	298	else if (insn->op->reloc_flag == RELOC_ABS)
	299	{
	300	(*info->print_address_func) (val, info);
	301	}
	302	else
	303	{
	304	if (oper->flags & OPERAND_SIGNED)
	305	{
	306	int max = (1 << (bits - 1));
47b0e7ad	307
252b5132 RH	308	if (val & max)
	309	{
	310	val = -val;
	311	if (bits < 32)
	312	val &= ((1 << bits) - 1);
	313	(*info->fprintf_func) (info->stream, "-");
	314	}
	315	}
2dcee538	316	(*info->fprintf_func) (info->stream, "0x%x", val);
252b5132	317	}
2dcee538	318	/* If there is another operand, then write a comma and space. */
159653d8	319	if (opind < ARRAY_SIZE (insn->form->operands)
9adb2591 NC	320	&& insn->form->operands[opind]
9adb2591 NC	321	&& !(found_control && opind == 2))
252b5132 RH	322	need_comma = 1;
	323	}
	324	if (need_paren)
	325	(*info->fprintf_func) (info->stream, ")");
	326	}
	327
47b0e7ad NC	328	int
47b0e7ad NC	329	print_insn_d30v (bfd_vma memaddr, struct disassemble_info *info)
252b5132	330	{
47b0e7ad NC	331	int status, result;
	332	bfd_byte buffer[12];
	333	unsigned long in1, in2;
	334	struct d30v_insn insn;
	335	long long num;
252b5132	336
47b0e7ad NC	337	insn.form = NULL;
	338
	339	info->bytes_per_line = 8;
	340	info->bytes_per_chunk = 4;
	341	info->display_endian = BFD_ENDIAN_BIG;
	342
	343	status = (*info->read_memory_func) (memaddr, buffer, 4, info);
	344	if (status != 0)
252b5132	345	{
47b0e7ad NC	346	(*info->memory_error_func) (status, memaddr, info);
	347	return -1;
	348	}
	349	in1 = bfd_getb32 (buffer);
	350
	351	status = (*info->read_memory_func) (memaddr + 4, buffer, 4, info);
	352	if (status != 0)
	353	{
	354	info->bytes_per_line = 8;
	355	if (!(result = lookup_opcode (&insn, in1, 0)))
0fd3a477	356	(*info->fprintf_func) (info->stream, ".long\t0x%lx", in1);
47b0e7ad NC	357	else
	358	print_insn (info, memaddr, (long long) in1, &insn, 0, result);
	359	return 4;
	360	}
	361	in2 = bfd_getb32 (buffer);
	362
	363	if (in1 & in2 & FM01)
	364	{
	365	/* LONG instruction. */
	366	if (!(result = lookup_opcode (&insn, in1, 1)))
252b5132	367	{
0fd3a477	368	(*info->fprintf_func) (info->stream, ".long\t0x%lx,0x%lx", in1, in2);
47b0e7ad	369	return 8;
252b5132	370	}
47b0e7ad NC	371	num = (long long) in1 << 32 \| in2;
47b0e7ad NC	372	print_insn (info, memaddr, num, &insn, 1, result);
252b5132 RH	373	}
252b5132 RH	374	else
47b0e7ad NC	375	{
	376	num = in1;
	377	if (!(result = lookup_opcode (&insn, in1, 0)))
0fd3a477	378	(*info->fprintf_func) (info->stream, ".long\t0x%lx", in1);
47b0e7ad NC	379	else
47b0e7ad NC	380	print_insn (info, memaddr, num, &insn, 0, result);
252b5132	381
47b0e7ad NC	382	switch (((in1 >> 31) << 1) \| (in2 >> 31))
	383	{
	384	case 0:
	385	(*info->fprintf_func) (info->stream, "\t\|\|\t");
	386	break;
	387	case 1:
	388	(*info->fprintf_func) (info->stream, "\t->\t");
	389	break;
	390	case 2:
	391	(*info->fprintf_func) (info->stream, "\t<-\t");
	392	default:
	393	break;
	394	}
252b5132	395
47b0e7ad NC	396	insn.form = NULL;
	397	num = in2;
	398	if (!(result = lookup_opcode (&insn, in2, 0)))
0fd3a477	399	(*info->fprintf_func) (info->stream, ".long\t0x%lx", in2);
47b0e7ad NC	400	else
	401	print_insn (info, memaddr, num, &insn, 0, result);
	402	}
	403	return 8;
252b5132	404	}