Commit | Line | Data |
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b2e3f844 | 1 | /* d30v-opc.c -- D30V opcode list |
42b5fd36 | 2 | Copyright 1997, 1998 Free Software Foundation, Inc. |
b2e3f844 MH |
3 | Written by Martin Hunt, Cygnus Support |
4 | ||
5 | This file is part of GDB, GAS, and the GNU binutils. | |
6 | ||
7 | GDB, GAS, and the GNU binutils are free software; you can redistribute | |
8 | them and/or modify them under the terms of the GNU General Public | |
9 | License as published by the Free Software Foundation; either version | |
10 | 2, or (at your option) any later version. | |
11 | ||
12 | GDB, GAS, and the GNU binutils are distributed in the hope that they | |
13 | will be useful, but WITHOUT ANY WARRANTY; without even the implied | |
14 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See | |
15 | the GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this file; see the file COPYING. If not, write to the Free | |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | #include <stdio.h> | |
22 | #include "ansidecl.h" | |
23 | #include "opcode/d30v.h" | |
24 | ||
25 | ||
26 | /* This table is sorted. */ | |
27 | /* If you add anything, it MUST be in alphabetical order */ | |
28 | /* The first field is the name the assembler uses when looking */ | |
29 | /* up orcodes. The second field is the name the disassembler will use. */ | |
30 | /* This allows the assembler to assemble references to r63 (for example) */ | |
31 | /* or "sp". The disassembler will always use the preferred form (sp) */ | |
32 | const struct pd_reg pre_defined_registers[] = | |
33 | { | |
34 | { "a0", NULL, OPERAND_ACC+0 }, | |
35 | { "a1", NULL, OPERAND_ACC+1 }, | |
d51bcb70 KR |
36 | { "bpc", NULL, OPERAND_CONTROL+3 }, |
37 | { "bpsw", NULL, OPERAND_CONTROL+1 }, | |
b2e3f844 | 38 | { "c", "c", OPERAND_FLAG+7 }, |
d51bcb70 KR |
39 | { "cr0", "psw", OPERAND_CONTROL }, |
40 | { "cr1", "bpsw", OPERAND_CONTROL+1 }, | |
41 | { "cr10", "mod_s", OPERAND_CONTROL+10 }, | |
42 | { "cr11", "mod_e", OPERAND_CONTROL+11 }, | |
b2e3f844 MH |
43 | { "cr12", NULL, OPERAND_CONTROL+12 }, |
44 | { "cr13", NULL, OPERAND_CONTROL+13 }, | |
d51bcb70 | 45 | { "cr14", "iba", OPERAND_CONTROL+14 }, |
42b5fd36 NC |
46 | { "cr15", "eit_vb", OPERAND_CONTROL+15 }, |
47 | { "cr16", "int_s", OPERAND_CONTROL+16 }, | |
48 | { "cr17", "int_m", OPERAND_CONTROL+17 }, | |
d51bcb70 KR |
49 | { "cr18", NULL, OPERAND_CONTROL+18 }, |
50 | { "cr19", NULL, OPERAND_CONTROL+19 }, | |
51 | { "cr2", "pc", OPERAND_CONTROL+2 }, | |
52 | { "cr20", NULL, OPERAND_CONTROL+20 }, | |
53 | { "cr21", NULL, OPERAND_CONTROL+21 }, | |
54 | { "cr22", NULL, OPERAND_CONTROL+22 }, | |
55 | { "cr23", NULL, OPERAND_CONTROL+23 }, | |
56 | { "cr24", NULL, OPERAND_CONTROL+24 }, | |
57 | { "cr25", NULL, OPERAND_CONTROL+25 }, | |
58 | { "cr26", NULL, OPERAND_CONTROL+26 }, | |
59 | { "cr27", NULL, OPERAND_CONTROL+27 }, | |
60 | { "cr28", NULL, OPERAND_CONTROL+28 }, | |
61 | { "cr29", NULL, OPERAND_CONTROL+29 }, | |
62 | { "cr3", "bpc", OPERAND_CONTROL+3 }, | |
63 | { "cr30", NULL, OPERAND_CONTROL+30 }, | |
64 | { "cr31", NULL, OPERAND_CONTROL+31 }, | |
65 | { "cr32", NULL, OPERAND_CONTROL+32 }, | |
66 | { "cr33", NULL, OPERAND_CONTROL+33 }, | |
67 | { "cr34", NULL, OPERAND_CONTROL+34 }, | |
68 | { "cr35", NULL, OPERAND_CONTROL+35 }, | |
69 | { "cr36", NULL, OPERAND_CONTROL+36 }, | |
70 | { "cr37", NULL, OPERAND_CONTROL+37 }, | |
71 | { "cr38", NULL, OPERAND_CONTROL+38 }, | |
72 | { "cr39", NULL, OPERAND_CONTROL+39 }, | |
73 | { "cr4", "dpsw", OPERAND_CONTROL+4 }, | |
74 | { "cr40", NULL, OPERAND_CONTROL+40 }, | |
75 | { "cr41", NULL, OPERAND_CONTROL+41 }, | |
76 | { "cr42", NULL, OPERAND_CONTROL+42 }, | |
77 | { "cr43", NULL, OPERAND_CONTROL+43 }, | |
78 | { "cr44", NULL, OPERAND_CONTROL+44 }, | |
79 | { "cr45", NULL, OPERAND_CONTROL+45 }, | |
80 | { "cr46", NULL, OPERAND_CONTROL+46 }, | |
81 | { "cr47", NULL, OPERAND_CONTROL+47 }, | |
82 | { "cr48", NULL, OPERAND_CONTROL+48 }, | |
83 | { "cr49", NULL, OPERAND_CONTROL+49 }, | |
84 | { "cr5","dpc", OPERAND_CONTROL+5 }, | |
85 | { "cr50", NULL, OPERAND_CONTROL+50 }, | |
86 | { "cr51", NULL, OPERAND_CONTROL+51 }, | |
87 | { "cr52", NULL, OPERAND_CONTROL+52 }, | |
88 | { "cr53", NULL, OPERAND_CONTROL+53 }, | |
89 | { "cr54", NULL, OPERAND_CONTROL+54 }, | |
90 | { "cr55", NULL, OPERAND_CONTROL+55 }, | |
91 | { "cr56", NULL, OPERAND_CONTROL+56 }, | |
92 | { "cr57", NULL, OPERAND_CONTROL+57 }, | |
93 | { "cr58", NULL, OPERAND_CONTROL+58 }, | |
94 | { "cr59", NULL, OPERAND_CONTROL+59 }, | |
95 | { "cr6", NULL, OPERAND_CONTROL+6 }, | |
96 | { "cr60", NULL, OPERAND_CONTROL+60 }, | |
97 | { "cr61", NULL, OPERAND_CONTROL+61 }, | |
98 | { "cr62", NULL, OPERAND_CONTROL+62 }, | |
99 | { "cr63", NULL, OPERAND_CONTROL+63 }, | |
100 | { "cr7", "rpt_c", OPERAND_CONTROL+7 }, | |
101 | { "cr8", "rpt_s", OPERAND_CONTROL+8 }, | |
102 | { "cr9", "rpt_e", OPERAND_CONTROL+9 }, | |
103 | { "dpc", NULL, OPERAND_CONTROL+5 }, | |
104 | { "dpsw", NULL, OPERAND_CONTROL+4 }, | |
42b5fd36 | 105 | { "eit_vb", NULL, OPERAND_CONTROL+15 }, |
b2e3f844 MH |
106 | { "f0", NULL, OPERAND_FLAG+0 }, |
107 | { "f1", NULL, OPERAND_FLAG+1 }, | |
108 | { "f2", NULL, OPERAND_FLAG+2 }, | |
109 | { "f3", NULL, OPERAND_FLAG+3 }, | |
110 | { "f4", "s", OPERAND_FLAG+4 }, | |
111 | { "f5", "v", OPERAND_FLAG+5 }, | |
112 | { "f6", "va", OPERAND_FLAG+6 }, | |
113 | { "f7", "c", OPERAND_FLAG+7 }, | |
d51bcb70 | 114 | { "iba", NULL, OPERAND_CONTROL+14 }, |
42b5fd36 NC |
115 | { "int_m", NULL, OPERAND_CONTROL+17 }, |
116 | { "int_s", NULL, OPERAND_CONTROL+16 }, | |
b2e3f844 | 117 | { "link", "r62", 62 }, |
d51bcb70 KR |
118 | { "mod_e", NULL, OPERAND_CONTROL+11 }, |
119 | { "mod_s", NULL, OPERAND_CONTROL+10 }, | |
120 | { "pc", NULL, OPERAND_CONTROL+2 }, | |
121 | { "psw", NULL, OPERAND_CONTROL }, | |
b2e3f844 MH |
122 | { "pswh", NULL, OPERAND_CONTROL+MAX_CONTROL_REG+2 }, |
123 | { "pswl", NULL, OPERAND_CONTROL+MAX_CONTROL_REG+1 }, | |
42b5fd36 | 124 | { "r0", NULL, 0 }, |
b2e3f844 MH |
125 | { "r1", NULL, 1 }, |
126 | { "r10", NULL, 10 }, | |
127 | { "r11", NULL, 11 }, | |
128 | { "r12", NULL, 12 }, | |
129 | { "r13", NULL, 13 }, | |
130 | { "r14", NULL, 14 }, | |
131 | { "r15", NULL, 15 }, | |
132 | { "r16", NULL, 16 }, | |
133 | { "r17", NULL, 17 }, | |
134 | { "r18", NULL, 18 }, | |
135 | { "r19", NULL, 19 }, | |
136 | { "r2", NULL, 2 }, | |
137 | { "r20", NULL, 20 }, | |
138 | { "r21", NULL, 21 }, | |
139 | { "r22", NULL, 22 }, | |
140 | { "r23", NULL, 23 }, | |
141 | { "r24", NULL, 24 }, | |
142 | { "r25", NULL, 25 }, | |
143 | { "r26", NULL, 26 }, | |
144 | { "r27", NULL, 27 }, | |
145 | { "r28", NULL, 28 }, | |
146 | { "r29", NULL, 29 }, | |
147 | { "r3", NULL, 3 }, | |
148 | { "r30", NULL, 30 }, | |
149 | { "r31", NULL, 31 }, | |
150 | { "r32", NULL, 32 }, | |
151 | { "r33", NULL, 33 }, | |
152 | { "r34", NULL, 34 }, | |
153 | { "r35", NULL, 35 }, | |
154 | { "r36", NULL, 36 }, | |
155 | { "r37", NULL, 37 }, | |
156 | { "r38", NULL, 38 }, | |
157 | { "r39", NULL, 39 }, | |
158 | { "r4", NULL, 4 }, | |
159 | { "r40", NULL, 40 }, | |
160 | { "r41", NULL, 41 }, | |
161 | { "r42", NULL, 42 }, | |
162 | { "r43", NULL, 43 }, | |
163 | { "r44", NULL, 44 }, | |
164 | { "r45", NULL, 45 }, | |
165 | { "r46", NULL, 46 }, | |
166 | { "r47", NULL, 47 }, | |
167 | { "r48", NULL, 48 }, | |
168 | { "r49", NULL, 49 }, | |
169 | { "r5", NULL, 5 }, | |
170 | { "r50", NULL, 50 }, | |
171 | { "r51", NULL, 51 }, | |
172 | { "r52", NULL, 52 }, | |
173 | { "r53", NULL, 53 }, | |
174 | { "r54", NULL, 54 }, | |
175 | { "r55", NULL, 55 }, | |
176 | { "r56", NULL, 56 }, | |
177 | { "r57", NULL, 57 }, | |
178 | { "r58", NULL, 58 }, | |
179 | { "r59", NULL, 59 }, | |
180 | { "r6", NULL, 6 }, | |
181 | { "r60", NULL, 60 }, | |
182 | { "r61", NULL, 61 }, | |
183 | { "r62", "link", 62 }, | |
184 | { "r63", "sp", 63 }, | |
185 | { "r7", NULL, 7 }, | |
186 | { "r8", NULL, 8 }, | |
187 | { "r9", NULL, 9 }, | |
d51bcb70 KR |
188 | { "rpt_c", NULL, OPERAND_CONTROL+7 }, |
189 | { "rpt_e", NULL, OPERAND_CONTROL+9 }, | |
190 | { "rpt_s", NULL, OPERAND_CONTROL+8 }, | |
b2e3f844 MH |
191 | { "s", NULL, OPERAND_FLAG+4 }, |
192 | { "sp", NULL, 63 }, | |
193 | { "v", NULL, OPERAND_FLAG+5 }, | |
194 | { "va", NULL, OPERAND_FLAG+6 }, | |
195 | }; | |
196 | ||
197 | int | |
198 | reg_name_cnt() | |
199 | { | |
200 | return (sizeof(pre_defined_registers) / sizeof(struct pd_reg)); | |
201 | } | |
202 | ||
203 | /* OPCODE TABLE */ | |
204 | /* The format of this table is defined in opcode/d30v.h */ | |
205 | const struct d30v_opcode d30v_opcode_table[] = { | |
206 | { "abs", IALU1, 0x8, { SHORT_U }, EITHER, 0, 0, 0 }, | |
207 | { "add", IALU1, 0x0, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 }, | |
208 | { "add2h", IALU1, 0x1, { SHORT_A, LONG}, EITHER, 0, 0, 0 }, | |
209 | { "addc", IALU1, 0x4, { SHORT_A, LONG }, EITHER, FLAG_C, FLAG_CVVA, 0 }, | |
42b5fd36 NC |
210 | { "addhlll", IALU1, 0x10, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, |
211 | { "addhllh", IALU1, 0x11, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, | |
212 | { "addhlhl", IALU1, 0x12, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, | |
213 | { "addhlhh", IALU1, 0x13, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, | |
214 | { "addhhll", IALU1, 0x14, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, | |
215 | { "addhhlh", IALU1, 0x15, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, | |
216 | { "addhhhl", IALU1, 0x16, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, | |
217 | { "addhhhh", IALU1, 0x17, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, | |
b2e3f844 MH |
218 | { "adds", IALU1, 0x6, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 }, |
219 | { "adds2h", IALU1, 0x7, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, | |
220 | { "and", LOGIC, 0x18, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, | |
d51bcb70 | 221 | { "andfg", LOGIC, 0x8, { SHORT_F }, EITHER, 0, 0, 0 }, |
b2e3f844 MH |
222 | { "avg", IALU1, 0xa, { SHORT_A, LONG}, EITHER, 0, 0, 0 }, |
223 | { "avg2h", IALU1, 0xb, { SHORT_A, LONG}, EITHER, 0, 0, 0 }, | |
b835e47b NC |
224 | { "bclr", LOGIC, 0x3, { SHORT_A }, EITHER_BUT_PREFER_MU, 0, 0, 0 }, |
225 | { "bnot", LOGIC, 0x1, { SHORT_A }, EITHER_BUT_PREFER_MU, 0, 0, 0 }, | |
b2e3f844 MH |
226 | { "bra", BRA, 0, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JMP, 0, RELOC_PCREL }, |
227 | { "bratnz", BRA, 0x4, { SHORT_B3b, LONG_2b }, MU, FLAG_JMP, 0, RELOC_PCREL }, | |
228 | { "bratzr", BRA, 0x4, { SHORT_B3, LONG_2 }, MU, FLAG_JMP, 0, RELOC_PCREL }, | |
b835e47b | 229 | { "bset", LOGIC, 0x2, { SHORT_A }, EITHER_BUT_PREFER_MU, 0, 0, 0 }, |
b2e3f844 MH |
230 | { "bsr", BRA, 0x2, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JSR, 0, RELOC_PCREL }, |
231 | { "bsrtnz", BRA, 0x6, { SHORT_B3b, LONG_2b }, MU, FLAG_JSR, 0, RELOC_PCREL }, | |
232 | { "bsrtzr", BRA, 0x6, { SHORT_B3, LONG_2 }, MU, FLAG_JSR, 0, RELOC_PCREL }, | |
b835e47b | 233 | { "btst", LOGIC, 0, { SHORT_AF }, EITHER_BUT_PREFER_MU, 0, 0, 0 }, |
d51bcb70 | 234 | { "cmp", LOGIC, 0xC, { SHORT_CMP, LONG_CMP }, EITHER, 0, 0, 0 }, |
42b5fd36 NC |
235 | { "cmpu", LOGIC, 0xD, { SHORT_CMPU, LONG_CMP }, EITHER, 0, 0, 0 }, |
236 | { "dbra", BRA, 0x10, { SHORT_B3, LONG_2 }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_PCREL }, | |
237 | { "dbrai", BRA, 0x14, { SHORT_D2, LONG_D }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_PCREL }, | |
238 | { "dbsr", BRA, 0x12, { SHORT_B3, LONG_2 }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_PCREL }, | |
239 | { "dbsri", BRA, 0x16, { SHORT_D2, LONG_D }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_PCREL }, | |
b835e47b | 240 | { "dbt", BRA, 0xb, { SHORT_NONE }, MU, 0, FLAG_LKR, 0 }, |
42b5fd36 NC |
241 | { "djmp", BRA, 0x11, { SHORT_B3, LONG_2 }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_ABS }, |
242 | { "djmpi", BRA, 0x15, { SHORT_D2, LONG_D }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_ABS }, | |
243 | { "djsr", BRA, 0x13, { SHORT_B3, LONG_2 }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_ABS }, | |
244 | { "djsri", BRA, 0x17, { SHORT_D2, LONG_D }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_ABS }, | |
b2e3f844 MH |
245 | { "jmp", BRA, 0x1, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JMP, 0, RELOC_ABS }, |
246 | { "jmptnz", BRA, 0x5, { SHORT_B3b, LONG_2b }, MU, FLAG_JMP, 0, RELOC_ABS }, | |
247 | { "jmptzr", BRA, 0x5, { SHORT_B3, LONG_2 }, MU, FLAG_JMP, 0, RELOC_ABS }, | |
248 | { "joinll", IALU1, 0xC, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, | |
249 | { "joinlh", IALU1, 0xD, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, | |
250 | { "joinhl", IALU1, 0xE, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, | |
251 | { "joinhh", IALU1, 0xF, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, | |
252 | { "jsr", BRA, 0x3, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JSR, 0, RELOC_ABS }, | |
253 | { "jsrtnz", BRA, 0x7, { SHORT_B3b, LONG_2b }, MU, FLAG_JSR, 0, RELOC_ABS }, | |
254 | { "jsrtzr", BRA, 0x7, { SHORT_B3, LONG_2 }, MU, FLAG_JSR, 0, RELOC_ABS }, | |
d51bcb70 | 255 | { "ld2h", IMEM, 0x3, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM, 0, 0 }, |
42b5fd36 NC |
256 | { "ld2w", IMEM, 0x6, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM | FLAG_2WORD, 0, 0 }, |
257 | { "ld4bh", IMEM, 0x5, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM | FLAG_2WORD, 0, 0 }, | |
d51bcb70 | 258 | { "ld4bhu", IMEM, 0xd, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM, 0, 0 }, |
b2e3f844 MH |
259 | { "ldb", IMEM, 0, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, |
260 | { "ldbu", IMEM, 0x9, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, | |
261 | { "ldh", IMEM, 0x2, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, | |
262 | { "ldhh", IMEM, 0x1, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, | |
263 | { "ldhu", IMEM, 0xa, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, | |
264 | { "ldw", IMEM, 0x4, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, | |
b835e47b NC |
265 | { "mac0", IALU2, 0x14, { SHORT_A }, IU, FLAG_MUL32, 0, 0 }, |
266 | { "mac1", IALU2, 0x14, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 }, | |
267 | { "macs0", IALU2, 0x15, { SHORT_A }, IU, FLAG_MUL32, 0, 0 }, | |
268 | { "macs1", IALU2, 0x15, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 }, | |
b2e3f844 MH |
269 | { "moddec", IMEM, 0x7, { SHORT_MODDEC }, MU, 0, 0, 0 }, |
270 | { "modinc", IMEM, 0x7, { SHORT_MODINC }, MU, 0, 0, 0 }, | |
b835e47b NC |
271 | { "msub0", IALU2, 0x16, { SHORT_A }, IU, FLAG_MUL32, 0, 0 }, |
272 | { "msub1", IALU2, 0x16, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 }, | |
273 | { "msubs0", IALU2, 0x17, { SHORT_A }, IU, FLAG_MUL32, 0, 0 }, | |
274 | { "msubs1", IALU2, 0x17, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 }, | |
42b5fd36 NC |
275 | { "mul", IALU2, 0x10, { SHORT_A }, IU, FLAG_MUL32, 0, 0 }, |
276 | { "mul2h", IALU2, 0, { SHORT_A }, IU, FLAG_MUL16, 0, 0 }, | |
277 | { "mulhxll", IALU2, 0x4, { SHORT_A }, IU, FLAG_MUL16, 0, 0 }, | |
278 | { "mulhxlh", IALU2, 0x5, { SHORT_A }, IU, FLAG_MUL16, 0, 0 }, | |
279 | { "mulhxhl", IALU2, 0x6, { SHORT_A }, IU, FLAG_MUL16, 0, 0 }, | |
280 | { "mulhxhh", IALU2, 0x7, { SHORT_A }, IU, FLAG_MUL16, 0, 0 }, | |
281 | { "mulx", IALU2, 0x18, { SHORT_AA }, IU, FLAG_MUL32, 0, 0 }, | |
b835e47b | 282 | { "mulx2h", IALU2, 0x1, { SHORT_A2 }, IU, FLAG_MUL16, 0, 0 }, |
42b5fd36 | 283 | { "mulxs", IALU2, 0x19, { SHORT_AA }, IU, FLAG_MUL32, 0, 0 }, |
b2e3f844 MH |
284 | { "mvfacc", IALU2, 0x1f, { SHORT_RA }, IU, 0, 0, 0 }, |
285 | { "mvfsys", BRA, 0x1e, { SHORT_C1 }, MU, FLAG_ALL, FLAG_ALL, 0 }, | |
286 | { "mvtacc", IALU2, 0xf, { SHORT_AA }, IU, 0, 0, 0 }, | |
b835e47b | 287 | { "mvtsys", BRA, 0xe, { SHORT_C2 }, MU, FLAG_ALL, FLAG_ALL | FLAG_LKR, 0 }, |
b2e3f844 MH |
288 | { "nop", BRA, 0xF, { SHORT_NONE }, EITHER, 0, 0, 0 }, |
289 | { "not", LOGIC, 0x19, { SHORT_U }, EITHER, 0, 0, 0 }, | |
d51bcb70 | 290 | { "notfg", LOGIC, 0x9, { SHORT_UF }, EITHER, 0, 0, 0 }, |
b2e3f844 | 291 | { "or", LOGIC, 0x1a, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, |
d51bcb70 | 292 | { "orfg", LOGIC, 0xa, { SHORT_F }, EITHER, 0, 0, 0 }, |
b835e47b | 293 | { "reit", BRA, 0x8, { SHORT_NONE }, MU, FLAG_SM, FLAG_SM | FLAG_LKR, 0 }, |
42b5fd36 NC |
294 | { "repeat", BRA, 0x18, { SHORT_D1, LONG_2 }, MU, FLAG_RP, FLAG_RP, RELOC_PCREL }, |
295 | { "repeati", BRA, 0x1a, { SHORT_D2B, LONG_Db }, MU, FLAG_RP, FLAG_RP, RELOC_PCREL }, | |
b2e3f844 | 296 | { "rot", LOGIC, 0x14, { SHORT_A }, EITHER, 0, 0, 0 }, |
42b5fd36 | 297 | { "rot2h", LOGIC, 0x15, { SHORT_A }, EITHER, 0, 0, 0 }, |
b835e47b | 298 | { "rtd", BRA, 0xa, { SHORT_NONE }, MU, 0, FLAG_LKR, 0 }, |
d51bcb70 KR |
299 | { "sat", IALU2, 0x8, { SHORT_A5 }, IU, 0, 0, 0 }, |
300 | { "sat2h", IALU2, 0x9, { SHORT_A5 }, IU, 0, 0, 0 }, | |
3db24c6b NC |
301 | { "sathl", IALU2, 0x1c, { SHORT_A5 }, IU, FLAG_ADDSUBppp, 0, 0 }, |
302 | { "sathh", IALU2, 0x1d, { SHORT_A5 }, IU, FLAG_ADDSUBppp, 0, 0 }, | |
d51bcb70 KR |
303 | { "satz", IALU2, 0xa, { SHORT_A5 }, IU, 0, 0, 0 }, |
304 | { "satz2h", IALU2, 0xb, { SHORT_A5 }, IU, 0, 0, 0 }, | |
b2e3f844 | 305 | { "sra", LOGIC, 0x10, { SHORT_A }, EITHER, 0, 0, 0 }, |
42b5fd36 | 306 | { "sra2h", LOGIC, 0x11, { SHORT_A }, EITHER, 0, 0, 0 }, |
d51bcb70 KR |
307 | { "srahh", LOGIC, 0x5, { SHORT_A }, EITHER, 0, 0, 0 }, |
308 | { "srahl", LOGIC, 0x4, { SHORT_A }, EITHER, 0, 0, 0 }, | |
3db24c6b | 309 | { "src", LOGIC, 0x16, { SHORT_A }, EITHER, FLAG_ADDSUBppp, 0, 0 }, |
b2e3f844 | 310 | { "srl", LOGIC, 0x12, { SHORT_A }, EITHER, 0, 0, 0 }, |
42b5fd36 | 311 | { "srl2h", LOGIC, 0x13, { SHORT_A }, EITHER, 0, 0, 0 }, |
d51bcb70 KR |
312 | { "srlhh", LOGIC, 0x7, { SHORT_A }, EITHER, 0, 0, 0 }, |
313 | { "srlhl", LOGIC, 0x6, { SHORT_A }, EITHER, 0, 0, 0 }, | |
314 | { "st2h", IMEM, 0x13, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM, 0 }, | |
42b5fd36 NC |
315 | { "st2w", IMEM, 0x16, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM | FLAG_2WORD, 0 }, |
316 | { "st4hb", IMEM, 0x15, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM | FLAG_2WORD, 0 }, | |
b2e3f844 MH |
317 | { "stb", IMEM, 0x10, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 }, |
318 | { "sth", IMEM, 0x12, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 }, | |
319 | { "sthh", IMEM, 0x11, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 }, | |
320 | { "stw", IMEM, 0x14, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 }, | |
321 | { "sub", IALU1, 0x2, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 }, | |
322 | { "sub2h", IALU1, 0x3, { SHORT_A, LONG}, EITHER, 0, 0, 0 }, | |
323 | { "subb", IALU1, 0x5, { SHORT_A, LONG}, EITHER, FLAG_C, FLAG_CVVA, 0 }, | |
42b5fd36 NC |
324 | { "subhlll", IALU1, 0x18, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, |
325 | { "subhllh", IALU1, 0x19, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, | |
326 | { "subhlhl", IALU1, 0x1a, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, | |
327 | { "subhlhh", IALU1, 0x1b, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, | |
328 | { "subhhll", IALU1, 0x1c, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, | |
329 | { "subhhlh", IALU1, 0x1d, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, | |
330 | { "subhhhl", IALU1, 0x1e, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, | |
331 | { "subhhhh", IALU1, 0x1f, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 }, | |
b835e47b | 332 | { "trap", BRA, 0x9, { SHORT_B1, SHORT_T}, MU, 0, FLAG_SM | FLAG_LKR, 0 }, |
b2e3f844 | 333 | { "xor", LOGIC, 0x1b, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, |
d51bcb70 | 334 | { "xorfg", LOGIC, 0xb, { SHORT_F }, EITHER, 0, 0, 0 }, |
b2e3f844 MH |
335 | { NULL, 0, 0, { 0 }, 0, 0, 0, 0 }, |
336 | }; | |
337 | ||
338 | ||
339 | /* now define the operand types */ | |
340 | /* format is length, bits, position, flags */ | |
341 | const struct d30v_operand d30v_operand_table[] = | |
342 | { | |
343 | #define UNUSED (0) | |
344 | { 0, 0, 0, 0 }, | |
345 | #define Ra (UNUSED + 1) | |
346 | { 6, 6, 0, OPERAND_REG|OPERAND_DEST }, | |
d51bcb70 KR |
347 | #define Ra2 (Ra + 1) |
348 | { 6, 6, 0, OPERAND_REG|OPERAND_DEST|OPERAND_2REG }, | |
b835e47b NC |
349 | #define Ra3 (Ra2 + 1) |
350 | { 6, 6, 0, OPERAND_REG }, | |
351 | #define Rb (Ra3 + 1) | |
b2e3f844 MH |
352 | { 6, 6, 6, OPERAND_REG }, |
353 | #define Rc (Rb + 1) | |
354 | { 6, 6, 12, OPERAND_REG }, | |
355 | #define Aa (Rc + 1) | |
356 | { 6, 1, 0, OPERAND_ACC|OPERAND_REG|OPERAND_DEST }, | |
357 | #define Ab (Aa + 1) | |
358 | { 6, 1, 6, OPERAND_ACC|OPERAND_REG }, | |
359 | #define IMM5 (Ab + 1) | |
d51bcb70 KR |
360 | { 6, 5, 12, OPERAND_NUM }, |
361 | #define IMM5U (IMM5 + 1) | |
b2e3f844 | 362 | { 6, 5, 12, OPERAND_NUM|OPERAND_SIGNED }, |
d51bcb70 | 363 | #define IMM5S3 (IMM5U + 1) |
b2e3f844 MH |
364 | { 6, 5, 12, OPERAND_NUM|OPERAND_SIGNED }, |
365 | #define IMM6 (IMM5S3 + 1) | |
366 | { 6, 6, 12, OPERAND_NUM|OPERAND_SIGNED }, | |
d51bcb70 KR |
367 | #define IMM6U (IMM6 + 1) |
368 | { 6, 6, 0, OPERAND_NUM }, | |
369 | #define IMM6U2 (IMM6U + 1) | |
370 | { 6, 6, 12, OPERAND_NUM }, | |
371 | #define IMM6S3 (IMM6U2 + 1) | |
372 | { 6, 6, 0, OPERAND_NUM|OPERAND_SHIFT }, | |
373 | #define IMM12S3 (IMM6S3 + 1) | |
374 | { 12, 12, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT }, | |
375 | #define IMM12S3U (IMM12S3 + 1) | |
376 | { 12, 12, 12, OPERAND_NUM|OPERAND_SHIFT }, | |
377 | #define IMM18S3 (IMM12S3U + 1) | |
b2e3f844 MH |
378 | { 18, 18, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT }, |
379 | #define IMM32 (IMM18S3 + 1) | |
380 | { 32, 32, 0, OPERAND_NUM }, | |
381 | #define Fa (IMM32 + 1) | |
382 | { 6, 3, 0, OPERAND_REG | OPERAND_FLAG | OPERAND_DEST }, | |
383 | #define Fb (Fa + 1) | |
384 | { 6, 3, 6, OPERAND_REG | OPERAND_FLAG }, | |
385 | #define Fc (Fb + 1) | |
386 | { 6, 3, 12, OPERAND_REG | OPERAND_FLAG }, | |
387 | #define ATSIGN (Fc + 1) | |
388 | { 0, 0, 0, OPERAND_ATSIGN}, | |
389 | #define ATPAR (ATSIGN + 1) /* "@(" */ | |
390 | { 0, 0, 0, OPERAND_ATPAR}, | |
391 | #define PLUS (ATPAR + 1) /* postincrement */ | |
392 | { 0, 0, 0, OPERAND_PLUS}, | |
393 | #define MINUS (PLUS + 1) /* postdecrement */ | |
394 | { 0, 0, 0, OPERAND_MINUS}, | |
395 | #define ATMINUS (MINUS + 1) /* predecrement */ | |
396 | { 0, 0, 0, OPERAND_ATMINUS}, | |
397 | #define Ca (ATMINUS + 1) /* control register */ | |
d51bcb70 | 398 | { 6, 6, 0, OPERAND_REG|OPERAND_CONTROL|OPERAND_DEST}, |
b2e3f844 | 399 | #define Cb (Ca + 1) /* control register */ |
d51bcb70 | 400 | { 6, 6, 6, OPERAND_REG|OPERAND_CONTROL}, |
b2e3f844 MH |
401 | #define CC (Cb + 1) /* condition code (CMPcc and CMPUcc) */ |
402 | { 3, 3, -3, OPERAND_NAME}, | |
403 | #define Fa2 (CC + 1) /* flag register (CMPcc and CMPUcc) */ | |
404 | { 3, 3, 0, OPERAND_REG|OPERAND_FLAG|OPERAND_DEST}, | |
405 | #define Fake (Fa2 + 1) /* place holder for "id" field in mvfsys and mvtsys */ | |
406 | { 6, 2, 12, OPERAND_SPECIAL}, | |
407 | }; | |
408 | ||
409 | /* now we need to define the instruction formats */ | |
410 | const struct d30v_format d30v_format_table[] = | |
411 | { | |
412 | { 0, 0, { 0 } }, | |
413 | { SHORT_M, 0, { Ra, ATPAR, Rb, Rc } }, /* Ra,@(Rb,Rc) */ | |
414 | { SHORT_M, 1, { Ra, ATPAR, Rb, PLUS, Rc } }, /* Ra,@(Rb+,Rc) */ | |
415 | { SHORT_M, 2, { Ra, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */ | |
416 | { SHORT_M, 3, { Ra, ATPAR, Rb, MINUS, Rc } }, /* Ra,@(Rb-,Rc) */ | |
d51bcb70 KR |
417 | { SHORT_M2, 0, { Ra2, ATPAR, Rb, Rc } }, /* Ra,@(Rb,Rc) */ |
418 | { SHORT_M2, 1, { Ra2, ATPAR, Rb, PLUS, Rc } }, /* Ra,@(Rb+,Rc) */ | |
419 | { SHORT_M2, 2, { Ra2, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */ | |
420 | { SHORT_M2, 3, { Ra2, ATPAR, Rb, MINUS, Rc } }, /* Ra,@(Rb-,Rc) */ | |
b2e3f844 MH |
421 | { SHORT_A, 0, { Ra, Rb, Rc } }, /* Ra,Rb,Rc */ |
422 | { SHORT_A, 2, { Ra, Rb, IMM6 } }, /* Ra,Rb,imm6 */ | |
423 | { SHORT_B1, 0, { Rc } }, /* Rc */ | |
424 | { SHORT_B2, 2, { IMM18S3 } }, /* imm18 */ | |
b835e47b NC |
425 | { SHORT_B3, 0, { Ra3, Rc } }, /* Ra,Rc */ |
426 | { SHORT_B3, 2, { Ra3, IMM12S3 } }, /* Ra,imm12 */ | |
427 | { SHORT_B3b, 1, { Ra3, Rc } }, /* Ra,Rc */ | |
428 | { SHORT_B3b, 3, { Ra3, IMM12S3 } }, /* Ra,imm12 */ | |
b2e3f844 MH |
429 | { SHORT_D1, 0, { Ra, Rc } }, /* Ra,Rc */ |
430 | { SHORT_D1, 2, { Ra, IMM12S3 } }, /* Ra,imm12s3 */ | |
d51bcb70 KR |
431 | { SHORT_D2, 0, { IMM6S3, Rc } }, /* imm6s3,Rc */ |
432 | { SHORT_D2, 2, { IMM6S3, IMM12S3 } }, /* imm6s3,imm12s3 */ | |
433 | { SHORT_D2B, 0, { IMM6U, Rc } }, /* imm6u,Rc */ | |
434 | { SHORT_D2B, 2, { IMM6U, IMM12S3U } }, /* imm6u,imm12s3u */ | |
b2e3f844 | 435 | { SHORT_U, 0, { Ra, Rb } }, /* Ra,Rb */ |
d51bcb70 | 436 | { SHORT_U, 2, { Ra, IMM12S3 } }, /* Ra,imm12 (repeat) */ |
b2e3f844 MH |
437 | { SHORT_F, 0, { Fa, Fb, Fc } }, /* Fa,Fb,Fc (orfg, xorfg) */ |
438 | { SHORT_F, 2, { Fa, Fb, IMM6 } }, /* Fa,Fb,imm6 */ | |
439 | { SHORT_AF, 0, { Fa, Rb, Rc } }, /* Fa,Rb,Rc */ | |
440 | { SHORT_AF, 2, { Fa, Rb, IMM6 } }, /* Fa,Rb,imm6 */ | |
d51bcb70 KR |
441 | { SHORT_T, 2, { IMM5 } }, /* imm5s3 (trap) */ |
442 | { SHORT_A5, 0, { Ra, Rb, Rc } }, /* Ra,Rb,Rc */ | |
b2e3f844 MH |
443 | { SHORT_A5, 2, { Ra, Rb, IMM5 } }, /* Ra,Rb,imm5 (sat*) */ |
444 | { SHORT_CMP, 0, { CC, Fa2, Rb, Rc} }, /* CC Fa2,Rb,Rc */ | |
445 | { SHORT_CMP, 2, { CC, Fa2, Rb, IMM6} }, /* CC Fa2,Rb,imm6 */ | |
42b5fd36 NC |
446 | { SHORT_CMPU, 0, { CC, Fa2, Rb, Rc} }, /* CC Fa2,Rb,Rc */ |
447 | { SHORT_CMPU, 2, { CC, Fa2, Rb, IMM6U2} }, /* CC Fa2,Rb,imm6 */ | |
b2e3f844 MH |
448 | { SHORT_A1, 1, { Ra, Rb, Rc } }, /* Ra,Rb,Rc for MAC where a=1 */ |
449 | { SHORT_A1, 3, { Ra, Rb, IMM6 } }, /* Ra,Rb,imm6 for MAC where a=1 */ | |
450 | { SHORT_AA, 0, { Aa, Rb, Rc } }, /* Aa,Rb,Rc */ | |
451 | { SHORT_AA, 2, { Aa, Rb, IMM6 } }, /* Aa,Rb,imm6 */ | |
452 | { SHORT_RA, 0, { Ra, Ab, Rc } }, /* Ra,Ab,Rc */ | |
d51bcb70 | 453 | { SHORT_RA, 2, { Ra, Ab, IMM6U2 } }, /* Ra,Ab,imm6u */ |
b2e3f844 MH |
454 | { SHORT_MODINC, 1, { Rb, IMM5 } }, /* Rb,imm5 (modinc) */ |
455 | { SHORT_MODDEC, 3, { Rb, IMM5 } }, /* Rb,imm5 (moddec) */ | |
d51bcb70 KR |
456 | { SHORT_C1, 0, { Ra, Cb, Fake } }, /* Ra,Cb (mvfsys) */ |
457 | { SHORT_C2, 0, { Ca, Rb, Fake } }, /* Ca,Rb (mvtsys) */ | |
b2e3f844 | 458 | { SHORT_UF, 0, { Fa, Fb } }, /* Fa,Fb (notfg) */ |
d51bcb70 KR |
459 | { SHORT_A2, 0, { Ra2, Rb, Rc } }, /* Ra2,Rb,Rc */ |
460 | { SHORT_A2, 2, { Ra2, Rb, IMM6 } }, /* Ra2,Rb,imm6 */ | |
461 | { SHORT_A5S, 0, { Ra, Rb, Rc } }, /* Ra,Rb,Rc */ | |
462 | { SHORT_A5S, 2, { Ra, Rb, IMM5U } }, /* Ra,Rb,imm5u (shifts) */ | |
b2e3f844 MH |
463 | { SHORT_NONE, 0, { 0 } }, /* no operands (nop, reit) */ |
464 | { LONG, 2, { Ra, Rb, IMM32 } }, /* Ra,Rb,imm32 */ | |
465 | { LONG_U, 2, { IMM32 } }, /* imm32 */ | |
466 | { LONG_AF, 2, { Fa, Rb, IMM32 } }, /* Fa,Rb,imm32 */ | |
467 | { LONG_CMP, 2, { CC, Fa2, Rb, IMM32} }, /* CC Fa2,Rb,imm32 */ | |
468 | { LONG_M, 2, { Ra, ATPAR, Rb, IMM32 } }, /* Ra,@(Rb,imm32) */ | |
d51bcb70 | 469 | { LONG_M2, 2, { Ra2, ATPAR, Rb, IMM32 } }, /* Ra,@(Rb,imm32) */ |
b835e47b NC |
470 | { LONG_2, 2, { Ra3, IMM32 } }, /* Ra,imm32 */ |
471 | { LONG_2b, 3, { Ra3, IMM32 } }, /* Ra,imm32 */ | |
d51bcb70 KR |
472 | { LONG_D, 2, { IMM6S3, IMM32 } }, /* imm6s3,imm32 */ |
473 | { LONG_Db, 2, { IMM6U, IMM32 } }, /* imm6,imm32 */ | |
b2e3f844 MH |
474 | { 0, 0, { 0 } }, |
475 | }; | |
476 | ||
477 | const char *d30v_ecc_names[] = | |
478 | { | |
479 | "al", | |
480 | "tx", | |
481 | "fx", | |
482 | "xt", | |
483 | "xf", | |
484 | "tt", | |
485 | "tf", | |
486 | "res" | |
487 | }; | |
488 | ||
489 | const char *d30v_cc_names[] = | |
490 | { | |
491 | "eq", | |
492 | "ne", | |
493 | "gt", | |
494 | "ge", | |
495 | "lt", | |
496 | "le", | |
497 | "ps", | |
498 | "ng", | |
499 | NULL | |
500 | }; |