projects / deliverable / binutils-gdb.git / blame
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|---|---|---|
| b2e3f844 MH |
1 | /* d30v-opc.c -- D30V opcode list |
| 2 | Copyright 1997 Free Software Foundation, Inc. | |
| 3 | Written by Martin Hunt, Cygnus Support | |
| 4 | ||
| 5 | This file is part of GDB, GAS, and the GNU binutils. | |
| 6 | ||
| 7 | GDB, GAS, and the GNU binutils are free software; you can redistribute | |
| 8 | them and/or modify them under the terms of the GNU General Public | |
| 9 | License as published by the Free Software Foundation; either version | |
| 10 | 2, or (at your option) any later version. | |
| 11 | ||
| 12 | GDB, GAS, and the GNU binutils are distributed in the hope that they | |
| 13 | will be useful, but WITHOUT ANY WARRANTY; without even the implied | |
| 14 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See | |
| 15 | the GNU General Public License for more details. | |
| 16 | ||
| 17 | You should have received a copy of the GNU General Public License | |
| 18 | along with this file; see the file COPYING. If not, write to the Free | |
| 19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
| 20 | ||
| 21 | #include <stdio.h> | |
| 22 | #include "ansidecl.h" | |
| 23 | #include "opcode/d30v.h" | |
| 24 | ||
| 25 | ||
| 26 | /* This table is sorted. */ | |
| 27 | /* If you add anything, it MUST be in alphabetical order */ | |
| 28 | /* The first field is the name the assembler uses when looking */ | |
| 29 | /* up orcodes. The second field is the name the disassembler will use. */ | |
| 30 | /* This allows the assembler to assemble references to r63 (for example) */ | |
| 31 | /* or "sp". The disassembler will always use the preferred form (sp) */ | |
| 32 | const struct pd_reg pre_defined_registers[] = | |
| 33 | { | |
| 34 | { "a0", NULL, OPERAND_ACC+0 }, | |
| 35 | { "a1", NULL, OPERAND_ACC+1 }, | |
| 36 | { "bpc", NULL, OPERAND_CONTROL+2 }, | |
| 37 | { "bpsw", NULL, OPERAND_CONTROL+3 }, | |
| 38 | { "c", "c", OPERAND_FLAG+7 }, | |
| 39 | { "cr0", "pc", OPERAND_CONTROL }, | |
| 40 | { "cr1", "psw", OPERAND_CONTROL+1 }, | |
| 41 | { "cr10", "mod_e", OPERAND_CONTROL+10 }, | |
| 42 | { "cr11", "iba", OPERAND_CONTROL+11 }, | |
| 43 | { "cr12", NULL, OPERAND_CONTROL+12 }, | |
| 44 | { "cr13", NULL, OPERAND_CONTROL+13 }, | |
| 45 | { "cr14", NULL, OPERAND_CONTROL+14 }, | |
| 46 | { "cr15", NULL, OPERAND_CONTROL+15 }, | |
| 47 | { "cr2", "bpc", OPERAND_CONTROL+2 }, | |
| 48 | { "cr3", "bpsw", OPERAND_CONTROL+3 }, | |
| 49 | { "cr4", NULL, OPERAND_CONTROL+4 }, | |
| 50 | { "cr5", NULL, OPERAND_CONTROL+5 }, | |
| 51 | { "cr6", "rpt_c", OPERAND_CONTROL+6 }, | |
| 52 | { "cr7", "rpt_s", OPERAND_CONTROL+7 }, | |
| 53 | { "cr8", "rpt_e", OPERAND_CONTROL+8 }, | |
| 54 | { "cr9", "mod_s", OPERAND_CONTROL+9 }, | |
| 55 | { "f0", NULL, OPERAND_FLAG+0 }, | |
| 56 | { "f1", NULL, OPERAND_FLAG+1 }, | |
| 57 | { "f2", NULL, OPERAND_FLAG+2 }, | |
| 58 | { "f3", NULL, OPERAND_FLAG+3 }, | |
| 59 | { "f4", "s", OPERAND_FLAG+4 }, | |
| 60 | { "f5", "v", OPERAND_FLAG+5 }, | |
| 61 | { "f6", "va", OPERAND_FLAG+6 }, | |
| 62 | { "f7", "c", OPERAND_FLAG+7 }, | |
| 63 | { "iba", NULL, OPERAND_CONTROL+11 }, | |
| 64 | { "link", "r62", 62 }, | |
| 65 | { "mod_e", NULL, OPERAND_CONTROL+10 }, | |
| 66 | { "mod_s", NULL, OPERAND_CONTROL+9 }, | |
| 67 | { "pc", NULL, OPERAND_CONTROL+0 }, | |
| 68 | { "psw", NULL, OPERAND_CONTROL+1 }, | |
| 69 | { "pswh", NULL, OPERAND_CONTROL+MAX_CONTROL_REG+2 }, | |
| 70 | { "pswl", NULL, OPERAND_CONTROL+MAX_CONTROL_REG+1 }, | |
| 71 | { "r0", "0", 0 }, | |
| 72 | { "r1", NULL, 1 }, | |
| 73 | { "r10", NULL, 10 }, | |
| 74 | { "r11", NULL, 11 }, | |
| 75 | { "r12", NULL, 12 }, | |
| 76 | { "r13", NULL, 13 }, | |
| 77 | { "r14", NULL, 14 }, | |
| 78 | { "r15", NULL, 15 }, | |
| 79 | { "r16", NULL, 16 }, | |
| 80 | { "r17", NULL, 17 }, | |
| 81 | { "r18", NULL, 18 }, | |
| 82 | { "r19", NULL, 19 }, | |
| 83 | { "r2", NULL, 2 }, | |
| 84 | { "r20", NULL, 20 }, | |
| 85 | { "r21", NULL, 21 }, | |
| 86 | { "r22", NULL, 22 }, | |
| 87 | { "r23", NULL, 23 }, | |
| 88 | { "r24", NULL, 24 }, | |
| 89 | { "r25", NULL, 25 }, | |
| 90 | { "r26", NULL, 26 }, | |
| 91 | { "r27", NULL, 27 }, | |
| 92 | { "r28", NULL, 28 }, | |
| 93 | { "r29", NULL, 29 }, | |
| 94 | { "r3", NULL, 3 }, | |
| 95 | { "r30", NULL, 30 }, | |
| 96 | { "r31", NULL, 31 }, | |
| 97 | { "r32", NULL, 32 }, | |
| 98 | { "r33", NULL, 33 }, | |
| 99 | { "r34", NULL, 34 }, | |
| 100 | { "r35", NULL, 35 }, | |
| 101 | { "r36", NULL, 36 }, | |
| 102 | { "r37", NULL, 37 }, | |
| 103 | { "r38", NULL, 38 }, | |
| 104 | { "r39", NULL, 39 }, | |
| 105 | { "r4", NULL, 4 }, | |
| 106 | { "r40", NULL, 40 }, | |
| 107 | { "r41", NULL, 41 }, | |
| 108 | { "r42", NULL, 42 }, | |
| 109 | { "r43", NULL, 43 }, | |
| 110 | { "r44", NULL, 44 }, | |
| 111 | { "r45", NULL, 45 }, | |
| 112 | { "r46", NULL, 46 }, | |
| 113 | { "r47", NULL, 47 }, | |
| 114 | { "r48", NULL, 48 }, | |
| 115 | { "r49", NULL, 49 }, | |
| 116 | { "r5", NULL, 5 }, | |
| 117 | { "r50", NULL, 50 }, | |
| 118 | { "r51", NULL, 51 }, | |
| 119 | { "r52", NULL, 52 }, | |
| 120 | { "r53", NULL, 53 }, | |
| 121 | { "r54", NULL, 54 }, | |
| 122 | { "r55", NULL, 55 }, | |
| 123 | { "r56", NULL, 56 }, | |
| 124 | { "r57", NULL, 57 }, | |
| 125 | { "r58", NULL, 58 }, | |
| 126 | { "r59", NULL, 59 }, | |
| 127 | { "r6", NULL, 6 }, | |
| 128 | { "r60", NULL, 60 }, | |
| 129 | { "r61", NULL, 61 }, | |
| 130 | { "r62", "link", 62 }, | |
| 131 | { "r63", "sp", 63 }, | |
| 132 | { "r7", NULL, 7 }, | |
| 133 | { "r8", NULL, 8 }, | |
| 134 | { "r9", NULL, 9 }, | |
| 135 | { "rpt_c", NULL, OPERAND_CONTROL+6 }, | |
| 136 | { "rpt_e", NULL, OPERAND_CONTROL+8 }, | |
| 137 | { "rpt_s", NULL, OPERAND_CONTROL+7 }, | |
| 138 | { "s", NULL, OPERAND_FLAG+4 }, | |
| 139 | { "sp", NULL, 63 }, | |
| 140 | { "v", NULL, OPERAND_FLAG+5 }, | |
| 141 | { "va", NULL, OPERAND_FLAG+6 }, | |
| 142 | }; | |
| 143 | ||
| 144 | int | |
| 145 | reg_name_cnt() | |
| 146 | { | |
| 147 | return (sizeof(pre_defined_registers) / sizeof(struct pd_reg)); | |
| 148 | } | |
| 149 | ||
| 150 | /* OPCODE TABLE */ | |
| 151 | /* The format of this table is defined in opcode/d30v.h */ | |
| 152 | const struct d30v_opcode d30v_opcode_table[] = { | |
| 153 | { "abs", IALU1, 0x8, { SHORT_U }, EITHER, 0, 0, 0 }, | |
| 154 | { "add", IALU1, 0x0, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 }, | |
| 155 | { "add2h", IALU1, 0x1, { SHORT_A, LONG}, EITHER, 0, 0, 0 }, | |
| 156 | { "addc", IALU1, 0x4, { SHORT_A, LONG }, EITHER, FLAG_C, FLAG_CVVA, 0 }, | |
| 157 | { "addhlll", IALU1, 0x10, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 }, | |
| 158 | { "addhllh", IALU1, 0x11, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 }, | |
| 159 | { "addhlhl", IALU1, 0x12, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 }, | |
| 160 | { "addhlhh", IALU1, 0x13, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 }, | |
| 161 | { "addhhll", IALU1, 0x14, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 }, | |
| 162 | { "addhhlh", IALU1, 0x15, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 }, | |
| 163 | { "addhhhl", IALU1, 0x16, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 }, | |
| 164 | { "addhhhh", IALU1, 0x17, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 }, | |
| 165 | { "adds", IALU1, 0x6, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 }, | |
| 166 | { "adds2h", IALU1, 0x7, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, | |
| 167 | { "and", LOGIC, 0x18, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, | |
| 168 | { "andfg", LOGIC, 0x8, { SHORT_F }, EITHER, FLAG_X, FLAG_X, 0 }, | |
| 169 | { "avg", IALU1, 0xa, { SHORT_A, LONG}, EITHER, 0, 0, 0 }, | |
| 170 | { "avg2h", IALU1, 0xb, { SHORT_A, LONG}, EITHER, 0, 0, 0 }, | |
| 171 | { "bclr", LOGIC, 0x3, { SHORT_A }, EITHER, 0, 0, 0 }, | |
| 172 | { "bnot", LOGIC, 0x1, { SHORT_A }, EITHER, 0, 0, 0 }, | |
| 173 | { "bra", BRA, 0, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JMP, 0, RELOC_PCREL }, | |
| 174 | { "bratnz", BRA, 0x4, { SHORT_B3b, LONG_2b }, MU, FLAG_JMP, 0, RELOC_PCREL }, | |
| 175 | { "bratzr", BRA, 0x4, { SHORT_B3, LONG_2 }, MU, FLAG_JMP, 0, RELOC_PCREL }, | |
| 176 | { "bset", LOGIC, 0x2, { SHORT_A }, EITHER, 0, 0, 0 }, | |
| 177 | { "bsr", BRA, 0x2, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JSR, 0, RELOC_PCREL }, | |
| 178 | { "bsrtnz", BRA, 0x6, { SHORT_B3b, LONG_2b }, MU, FLAG_JSR, 0, RELOC_PCREL }, | |
| 179 | { "bsrtzr", BRA, 0x6, { SHORT_B3, LONG_2 }, MU, FLAG_JSR, 0, RELOC_PCREL }, | |
| 180 | { "btst", LOGIC, 0, { SHORT_AF }, EITHER, 0, FLAG_X, 0 }, | |
| 181 | { "cmp", LOGIC, 0xC, { SHORT_CMP, LONG_CMP }, EITHER, 0, FLAG_X, 0 }, | |
| 182 | { "cmpu", LOGIC, 0xD, { SHORT_CMP, LONG_CMP }, EITHER, 0, FLAG_X, 0 }, | |
| 183 | { "dbra", BRA, 0x10, { SHORT_B3, LONG_2 }, MU, FLAG_JMP, FLAG_RP, RELOC_PCREL }, | |
| 184 | { "dbrai", BRA, 0x14, { SHORT_D2, LONG_D }, MU, FLAG_JMP, FLAG_RP, RELOC_PCREL }, | |
| 185 | { "dbsr", BRA, 0x12, { SHORT_B3, LONG_2 }, MU, FLAG_JSR, FLAG_RP, RELOC_PCREL }, | |
| 186 | { "dbsri", BRA, 0x16, { SHORT_D2, LONG_D }, MU, FLAG_JSR, FLAG_RP, RELOC_PCREL }, | |
| 187 | { "djmp", BRA, 0x11, { SHORT_B3, LONG_2 }, MU, FLAG_JMP, FLAG_RP, RELOC_ABS }, | |
| 188 | { "djmpi", BRA, 0x15, { SHORT_D2, LONG_D }, MU, FLAG_JMP, FLAG_RP, RELOC_ABS }, | |
| 189 | { "djsr", BRA, 0x13, { SHORT_B3, LONG_2 }, MU, FLAG_JSR, FLAG_RP, RELOC_ABS }, | |
| 190 | { "djsri", BRA, 0x17, { SHORT_D2, LONG_D }, MU, FLAG_JSR, FLAG_RP, RELOC_ABS }, | |
| 191 | { "jmp", BRA, 0x1, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JMP, 0, RELOC_ABS }, | |
| 192 | { "jmptnz", BRA, 0x5, { SHORT_B3b, LONG_2b }, MU, FLAG_JMP, 0, RELOC_ABS }, | |
| 193 | { "jmptzr", BRA, 0x5, { SHORT_B3, LONG_2 }, MU, FLAG_JMP, 0, RELOC_ABS }, | |
| 194 | { "joinll", IALU1, 0xC, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, | |
| 195 | { "joinlh", IALU1, 0xD, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, | |
| 196 | { "joinhl", IALU1, 0xE, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, | |
| 197 | { "joinhh", IALU1, 0xF, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, | |
| 198 | { "jsr", BRA, 0x3, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JSR, 0, RELOC_ABS }, | |
| 199 | { "jsrtnz", BRA, 0x7, { SHORT_B3b, LONG_2b }, MU, FLAG_JSR, 0, RELOC_ABS }, | |
| 200 | { "jsrtzr", BRA, 0x7, { SHORT_B3, LONG_2 }, MU, FLAG_JSR, 0, RELOC_ABS }, | |
| 201 | { "ld2h", IMEM, 0x3, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, | |
| 202 | { "ld2w", IMEM, 0x6, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, | |
| 203 | { "ld4bh", IMEM, 0x5, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, | |
| 204 | { "ld4bhu", IMEM, 0xd, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, | |
| 205 | { "ldb", IMEM, 0, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, | |
| 206 | { "ldbu", IMEM, 0x9, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, | |
| 207 | { "ldh", IMEM, 0x2, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, | |
| 208 | { "ldhh", IMEM, 0x1, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, | |
| 209 | { "ldhu", IMEM, 0xa, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, | |
| 210 | { "ldw", IMEM, 0x4, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, | |
| 211 | { "mac0", IALU2, 0x14, { SHORT_A }, IU, 0, 0, 0 }, | |
| 212 | { "mac1", IALU2, 0x14, { SHORT_A1 }, IU, 0, 0, 0 }, | |
| 213 | { "macs0", IALU2, 0x15, { SHORT_A }, IU, 0, 0, 0 }, | |
| 214 | { "macs1", IALU2, 0x15, { SHORT_A1 }, IU, 0, 0, 0 }, | |
| 215 | { "moddec", IMEM, 0x7, { SHORT_MODDEC }, MU, 0, 0, 0 }, | |
| 216 | { "modinc", IMEM, 0x7, { SHORT_MODINC }, MU, 0, 0, 0 }, | |
| 217 | { "msub0", IALU2, 0x16, { SHORT_A }, IU, 0, 0, 0 }, | |
| 218 | { "msub1", IALU2, 0x16, { SHORT_A1 }, IU, 0, 0, 0 }, | |
| 219 | { "msubs0", IALU2, 0x17, { SHORT_A }, IU, 0, 0, 0 }, | |
| 220 | { "msubs1", IALU2, 0x17, { SHORT_A1 }, IU, 0, 0, 0 }, | |
| 221 | { "mul", IALU2, 0x10, { SHORT_A }, IU, 0, 0, 0 }, | |
| 222 | { "mul2h", IALU2, 0, { SHORT_A }, IU, 0, 0, 0 }, | |
| 223 | { "mulhxll", IALU2, 0x4, { SHORT_A }, IU, 0, 0, 0 }, | |
| 224 | { "mulhxlh", IALU2, 0x5, { SHORT_A }, IU, 0, 0, 0 }, | |
| 225 | { "mulhxhl", IALU2, 0x6, { SHORT_A }, IU, 0, 0, 0 }, | |
| 226 | { "mulhxhh", IALU2, 0x7, { SHORT_A }, IU, 0, 0, 0 }, | |
| 227 | { "mulx", IALU2, 0x18, { SHORT_AA }, IU, 0, 0, 0 }, | |
| 228 | { "mulx2h", IALU2, 0x1, { SHORT_A }, IU, 0, 0, 0 }, | |
| 229 | { "mulxs", IALU2, 0x19, { SHORT_AA }, IU, 0, 0, 0 }, | |
| 230 | { "mvfacc", IALU2, 0x1f, { SHORT_RA }, IU, 0, 0, 0 }, | |
| 231 | { "mvfsys", BRA, 0x1e, { SHORT_C1 }, MU, FLAG_ALL, FLAG_ALL, 0 }, | |
| 232 | { "mvtacc", IALU2, 0xf, { SHORT_AA }, IU, 0, 0, 0 }, | |
| 233 | { "mvtsys", BRA, 0xe, { SHORT_C2 }, MU, FLAG_ALL, FLAG_ALL, 0 }, | |
| 234 | { "nop", BRA, 0xF, { SHORT_NONE }, EITHER, 0, 0, 0 }, | |
| 235 | { "not", LOGIC, 0x19, { SHORT_U }, EITHER, 0, 0, 0 }, | |
| 236 | { "notfg", LOGIC, 0x9, { SHORT_UF }, EITHER, FLAG_X, FLAG_X, 0 }, | |
| 237 | { "or", LOGIC, 0x1a, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, | |
| 238 | { "orfg", LOGIC, 0xa, { SHORT_F }, EITHER, FLAG_X, FLAG_X, 0 }, | |
| 239 | { "reit", BRA, 0x8, { SHORT_NONE }, MU, FLAG_SM, FLAG_SM, 0 }, | |
| 240 | { "repeat", BRA, 0x18, { SHORT_D1, LONG_2 }, MU, FLAG_RP, FLAG_RP, 0 }, | |
| 241 | { "repeati", BRA, 0x1a, { SHORT_D2, LONG_D }, MU, FLAG_RP, FLAG_RP, 0 }, | |
| 242 | { "rot", LOGIC, 0x14, { SHORT_A }, EITHER, 0, 0, 0 }, | |
| 243 | { "rot2h", LOGIC, 0x15, { SHORT_A }, EITHER, 0, 0, 0 }, | |
| 244 | { "sat", IALU2, 0x8, { SHORT_A }, IU, 0, 0, 0 }, | |
| 245 | { "sat2h", IALU2, 0x9, { SHORT_A }, IU, 0, 0, 0 }, | |
| 246 | { "sathl", IALU2, 0x1c, { SHORT_A }, IU, 0, 0, 0 }, | |
| 247 | { "sathh", IALU2, 0x1d, { SHORT_A }, IU, 0, 0, 0 }, | |
| 248 | { "satz", IALU2, 0xa, { SHORT_A }, IU, 0, 0, 0 }, | |
| 249 | { "satz2h", IALU2, 0xb, { SHORT_A }, IU, 0, 0, 0 }, | |
| 250 | { "sra", LOGIC, 0x10, { SHORT_A }, EITHER, 0, 0, 0 }, | |
| 251 | { "sra2h", LOGIC, 0x11, { SHORT_A }, EITHER, 0, 0, 0 }, | |
| 252 | { "src", LOGIC, 0x16, { SHORT_A }, EITHER, 0, 0, 0 }, | |
| 253 | { "srl", LOGIC, 0x12, { SHORT_A }, EITHER, 0, 0, 0 }, | |
| 254 | { "srl2h", LOGIC, 0x12, { SHORT_A }, EITHER, 0, 0, 0 }, | |
| 255 | { "st2h", IMEM, 0x13, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 }, | |
| 256 | { "st2w", IMEM, 0x16, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 }, | |
| 257 | { "st4hb", IMEM, 0x15, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 }, | |
| 258 | { "stb", IMEM, 0x10, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 }, | |
| 259 | { "sth", IMEM, 0x12, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 }, | |
| 260 | { "sthh", IMEM, 0x11, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 }, | |
| 261 | { "stw", IMEM, 0x14, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 }, | |
| 262 | { "sub", IALU1, 0x2, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 }, | |
| 263 | { "sub2h", IALU1, 0x3, { SHORT_A, LONG}, EITHER, 0, 0, 0 }, | |
| 264 | { "subb", IALU1, 0x5, { SHORT_A, LONG}, EITHER, FLAG_C, FLAG_CVVA, 0 }, | |
| 265 | { "subhlll", IALU1, 0x18, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 }, | |
| 266 | { "subhllh", IALU1, 0x19, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 }, | |
| 267 | { "subhlhl", IALU1, 0x1a, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 }, | |
| 268 | { "subhlhh", IALU1, 0x1b, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 }, | |
| 269 | { "subhhll", IALU1, 0x1c, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 }, | |
| 270 | { "subhhlh", IALU1, 0x1d, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 }, | |
| 271 | { "subhhhl", IALU1, 0x1e, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 }, | |
| 272 | { "subhhhh", IALU1, 0x1f, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 }, | |
| 273 | { "trap", BRA, 0x9, { SHORT_B1, SHORT_T}, MU, 0, FLAG_SM, 0 }, | |
| 274 | { "xor", LOGIC, 0x1b, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, | |
| 275 | { "xorfg", LOGIC, 0xb, { SHORT_F }, EITHER, FLAG_X, FLAG_X, 0 }, | |
| 276 | { NULL, 0, 0, { 0 }, 0, 0, 0, 0 }, | |
| 277 | }; | |
| 278 | ||
| 279 | ||
| 280 | /* now define the operand types */ | |
| 281 | /* format is length, bits, position, flags */ | |
| 282 | const struct d30v_operand d30v_operand_table[] = | |
| 283 | { | |
| 284 | #define UNUSED (0) | |
| 285 | { 0, 0, 0, 0 }, | |
| 286 | #define Ra (UNUSED + 1) | |
| 287 | { 6, 6, 0, OPERAND_REG|OPERAND_DEST }, | |
| 288 | #define Rb (Ra + 1) | |
| 289 | { 6, 6, 6, OPERAND_REG }, | |
| 290 | #define Rc (Rb + 1) | |
| 291 | { 6, 6, 12, OPERAND_REG }, | |
| 292 | #define Aa (Rc + 1) | |
| 293 | { 6, 1, 0, OPERAND_ACC|OPERAND_REG|OPERAND_DEST }, | |
| 294 | #define Ab (Aa + 1) | |
| 295 | { 6, 1, 6, OPERAND_ACC|OPERAND_REG }, | |
| 296 | #define IMM5 (Ab + 1) | |
| 297 | { 6, 5, 12, OPERAND_NUM|OPERAND_SIGNED }, | |
| 298 | #define IMM5S3 (IMM5 + 1) | |
| 299 | { 6, 5, 12, OPERAND_NUM|OPERAND_SIGNED }, | |
| 300 | #define IMM6 (IMM5S3 + 1) | |
| 301 | { 6, 6, 12, OPERAND_NUM|OPERAND_SIGNED }, | |
| 302 | #define IMM12 (IMM6 + 1) | |
| 303 | { 12, 12, 6, OPERAND_NUM|OPERAND_SIGNED }, | |
| 304 | #define IMM12S3 (IMM12 + 1) | |
| 305 | { 12, 12, 6, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT }, | |
| 306 | #define IMM18S3 (IMM12S3 + 1) | |
| 307 | { 18, 18, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT }, | |
| 308 | #define IMM32 (IMM18S3 + 1) | |
| 309 | { 32, 32, 0, OPERAND_NUM }, | |
| 310 | #define Fa (IMM32 + 1) | |
| 311 | { 6, 3, 0, OPERAND_REG | OPERAND_FLAG | OPERAND_DEST }, | |
| 312 | #define Fb (Fa + 1) | |
| 313 | { 6, 3, 6, OPERAND_REG | OPERAND_FLAG }, | |
| 314 | #define Fc (Fb + 1) | |
| 315 | { 6, 3, 12, OPERAND_REG | OPERAND_FLAG }, | |
| 316 | #define ATSIGN (Fc + 1) | |
| 317 | { 0, 0, 0, OPERAND_ATSIGN}, | |
| 318 | #define ATPAR (ATSIGN + 1) /* "@(" */ | |
| 319 | { 0, 0, 0, OPERAND_ATPAR}, | |
| 320 | #define PLUS (ATPAR + 1) /* postincrement */ | |
| 321 | { 0, 0, 0, OPERAND_PLUS}, | |
| 322 | #define MINUS (PLUS + 1) /* postdecrement */ | |
| 323 | { 0, 0, 0, OPERAND_MINUS}, | |
| 324 | #define ATMINUS (MINUS + 1) /* predecrement */ | |
| 325 | { 0, 0, 0, OPERAND_ATMINUS}, | |
| 326 | #define Ca (ATMINUS + 1) /* control register */ | |
| 327 | { 6, 4, 0, OPERAND_REG|OPERAND_CONTROL|OPERAND_DEST}, | |
| 328 | #define Cb (Ca + 1) /* control register */ | |
| 329 | { 6, 4, 6, OPERAND_REG|OPERAND_CONTROL}, | |
| 330 | #define CC (Cb + 1) /* condition code (CMPcc and CMPUcc) */ | |
| 331 | { 3, 3, -3, OPERAND_NAME}, | |
| 332 | #define Fa2 (CC + 1) /* flag register (CMPcc and CMPUcc) */ | |
| 333 | { 3, 3, 0, OPERAND_REG|OPERAND_FLAG|OPERAND_DEST}, | |
| 334 | #define Fake (Fa2 + 1) /* place holder for "id" field in mvfsys and mvtsys */ | |
| 335 | { 6, 2, 12, OPERAND_SPECIAL}, | |
| 336 | }; | |
| 337 | ||
| 338 | /* now we need to define the instruction formats */ | |
| 339 | const struct d30v_format d30v_format_table[] = | |
| 340 | { | |
| 341 | { 0, 0, { 0 } }, | |
| 342 | { SHORT_M, 0, { Ra, ATPAR, Rb, Rc } }, /* Ra,@(Rb,Rc) */ | |
| 343 | { SHORT_M, 1, { Ra, ATPAR, Rb, PLUS, Rc } }, /* Ra,@(Rb+,Rc) */ | |
| 344 | { SHORT_M, 2, { Ra, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */ | |
| 345 | { SHORT_M, 3, { Ra, ATPAR, Rb, MINUS, Rc } }, /* Ra,@(Rb-,Rc) */ | |
| 346 | { SHORT_A, 0, { Ra, Rb, Rc } }, /* Ra,Rb,Rc */ | |
| 347 | { SHORT_A, 2, { Ra, Rb, IMM6 } }, /* Ra,Rb,imm6 */ | |
| 348 | { SHORT_B1, 0, { Rc } }, /* Rc */ | |
| 349 | { SHORT_B2, 2, { IMM18S3 } }, /* imm18 */ | |
| 350 | { SHORT_B3, 0, { Ra, Rc } }, /* Ra,Rc */ | |
| 351 | { SHORT_B3, 2, { Ra, IMM12 } }, /* Ra,imm12 */ | |
| 352 | { SHORT_B3b, 1, { Ra, Rc } }, /* Ra,Rc */ | |
| 353 | { SHORT_B3b, 3, { Ra, IMM12 } }, /* Ra,imm12 */ | |
| 354 | { SHORT_D1, 0, { Ra, Rc } }, /* Ra,Rc */ | |
| 355 | { SHORT_D1, 2, { Ra, IMM12S3 } }, /* Ra,imm12s3 */ | |
| 356 | { SHORT_D2, 0, { IMM6, Rc } }, /* imm6,Rc */ | |
| 357 | { SHORT_D2, 2, { IMM6, IMM12S3 } }, /* imm6,imm12s3 */ | |
| 358 | { SHORT_U, 0, { Ra, Rb } }, /* Ra,Rb */ | |
| 359 | { SHORT_U, 2, { Ra, IMM12 } }, /* Ra,imm12 (repeat) */ | |
| 360 | { SHORT_F, 0, { Fa, Fb, Fc } }, /* Fa,Fb,Fc (orfg, xorfg) */ | |
| 361 | { SHORT_F, 2, { Fa, Fb, IMM6 } }, /* Fa,Fb,imm6 */ | |
| 362 | { SHORT_AF, 0, { Fa, Rb, Rc } }, /* Fa,Rb,Rc */ | |
| 363 | { SHORT_AF, 2, { Fa, Rb, IMM6 } }, /* Fa,Rb,imm6 */ | |
| 364 | { SHORT_T, 2, { IMM5S3 } }, /* imm5s3 (trap) */ | |
| 365 | { SHORT_A5, 2, { Ra, Rb, IMM5 } }, /* Ra,Rb,imm5 (sat*) */ | |
| 366 | { SHORT_CMP, 0, { CC, Fa2, Rb, Rc} }, /* CC Fa2,Rb,Rc */ | |
| 367 | { SHORT_CMP, 2, { CC, Fa2, Rb, IMM6} }, /* CC Fa2,Rb,imm6 */ | |
| 368 | { SHORT_A1, 1, { Ra, Rb, Rc } }, /* Ra,Rb,Rc for MAC where a=1 */ | |
| 369 | { SHORT_A1, 3, { Ra, Rb, IMM6 } }, /* Ra,Rb,imm6 for MAC where a=1 */ | |
| 370 | { SHORT_AA, 0, { Aa, Rb, Rc } }, /* Aa,Rb,Rc */ | |
| 371 | { SHORT_AA, 2, { Aa, Rb, IMM6 } }, /* Aa,Rb,imm6 */ | |
| 372 | { SHORT_RA, 0, { Ra, Ab, Rc } }, /* Ra,Ab,Rc */ | |
| 373 | { SHORT_RA, 2, { Ra, Ab, IMM5 } }, /* Ra,Ab,imm5 */ | |
| 374 | { SHORT_MODINC, 1, { Rb, IMM5 } }, /* Rb,imm5 (modinc) */ | |
| 375 | { SHORT_MODDEC, 3, { Rb, IMM5 } }, /* Rb,imm5 (moddec) */ | |
| 376 | { SHORT_C1, 2, { Ra, Cb, Fake } }, /* Ra,Cb (mvfsys) */ | |
| 377 | { SHORT_C2, 2, { Ca, Rb, Fake } }, /* Ca,Rb (mvtsys) */ | |
| 378 | { SHORT_UF, 0, { Fa, Fb } }, /* Fa,Fb (notfg) */ | |
| 379 | { SHORT_NONE, 0, { 0 } }, /* no operands (nop, reit) */ | |
| 380 | { LONG, 2, { Ra, Rb, IMM32 } }, /* Ra,Rb,imm32 */ | |
| 381 | { LONG_U, 2, { IMM32 } }, /* imm32 */ | |
| 382 | { LONG_AF, 2, { Fa, Rb, IMM32 } }, /* Fa,Rb,imm32 */ | |
| 383 | { LONG_CMP, 2, { CC, Fa2, Rb, IMM32} }, /* CC Fa2,Rb,imm32 */ | |
| 384 | { LONG_M, 2, { Ra, ATPAR, Rb, IMM32 } }, /* Ra,@(Rb,imm32) */ | |
| 385 | { LONG_2, 2, { Ra, IMM32 } }, /* Ra,imm32 */ | |
| 386 | { LONG_2b, 3, { Ra, IMM32 } }, /* Ra,imm32 */ | |
| 387 | { LONG_D, 2, { IMM6, IMM32 } }, /* imm6,imm32 */ | |
| 388 | { 0, 0, { 0 } }, | |
| 389 | }; | |
| 390 | ||
| 391 | const char *d30v_ecc_names[] = | |
| 392 | { | |
| 393 | "al", | |
| 394 | "tx", | |
| 395 | "fx", | |
| 396 | "xt", | |
| 397 | "xf", | |
| 398 | "tt", | |
| 399 | "tf", | |
| 400 | "res" | |
| 401 | }; | |
| 402 | ||
| 403 | const char *d30v_cc_names[] = | |
| 404 | { | |
| 405 | "eq", | |
| 406 | "ne", | |
| 407 | "gt", | |
| 408 | "ge", | |
| 409 | "lt", | |
| 410 | "le", | |
| 411 | "ps", | |
| 412 | "ng", | |
| 413 | NULL | |
| 414 | }; |