Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* Select disassembly routine for specified architecture. |
219d1afa | 2 | Copyright (C) 1994-2018 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 NC |
4 | This file is part of the GNU opcodes library. |
5 | ||
6 | This library is free software; you can redistribute it and/or modify | |
7499d566 | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 | 8 | the Free Software Foundation; either version 3 of the License, or |
7499d566 | 9 | (at your option) any later version. |
252b5132 | 10 | |
7499d566 NC |
11 | This program is distributed in the hope that it will be useful, |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
252b5132 | 15 | |
7499d566 NC |
16 | You should have received a copy of the GNU General Public License |
17 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
252b5132 | 20 | |
0d8dfecf | 21 | #include "sysdep.h" |
88c1242d | 22 | #include "disassemble.h" |
65b48a81 | 23 | #include "safe-ctype.h" |
003ca0fd | 24 | #include <assert.h> |
252b5132 RH |
25 | |
26 | #ifdef ARCH_all | |
a06ea964 | 27 | #define ARCH_aarch64 |
252b5132 RH |
28 | #define ARCH_alpha |
29 | #define ARCH_arc | |
30 | #define ARCH_arm | |
adde6300 | 31 | #define ARCH_avr |
4b7f6baa | 32 | #define ARCH_bfin |
3d3d428f | 33 | #define ARCH_cr16 |
6c95a37f | 34 | #define ARCH_cris |
1fe1f39c | 35 | #define ARCH_crx |
b8891f8d | 36 | #define ARCH_csky |
252b5132 RH |
37 | #define ARCH_d10v |
38 | #define ARCH_d30v | |
d172d4ba | 39 | #define ARCH_dlx |
56b13185 | 40 | #define ARCH_epiphany |
e729279b NC |
41 | #define ARCH_fr30 |
42 | #define ARCH_frv | |
3f8107ab | 43 | #define ARCH_ft32 |
252b5132 | 44 | #define ARCH_h8300 |
252b5132 RH |
45 | #define ARCH_hppa |
46 | #define ARCH_i386 | |
800eeca4 | 47 | #define ARCH_ia64 |
e729279b NC |
48 | #define ARCH_ip2k |
49 | #define ARCH_iq2000 | |
84e94c90 | 50 | #define ARCH_lm32 |
e729279b | 51 | #define ARCH_m32c |
252b5132 | 52 | #define ARCH_m32r |
60bcf0fa NC |
53 | #define ARCH_m68hc11 |
54 | #define ARCH_m68hc12 | |
e729279b | 55 | #define ARCH_m68k |
252b5132 | 56 | #define ARCH_mcore |
bd2f2e55 | 57 | #define ARCH_mep |
a3c62988 | 58 | #define ARCH_metag |
7ba29e2a | 59 | #define ARCH_microblaze |
252b5132 | 60 | #define ARCH_mips |
3c3bdf30 | 61 | #define ARCH_mmix |
252b5132 RH |
62 | #define ARCH_mn10200 |
63 | #define ARCH_mn10300 | |
59b1530d | 64 | #define ARCH_moxie |
d031aafb | 65 | #define ARCH_mt |
2469cfa2 | 66 | #define ARCH_msp430 |
35c08157 | 67 | #define ARCH_nds32 |
fe944acf | 68 | #define ARCH_nfp |
36591ba1 | 69 | #define ARCH_nios2 |
252b5132 | 70 | #define ARCH_ns32k |
73589c9d | 71 | #define ARCH_or1k |
e135f41b | 72 | #define ARCH_pdp11 |
1e608f98 | 73 | #define ARCH_pj |
252b5132 | 74 | #define ARCH_powerpc |
11146849 | 75 | #define ARCH_pru |
0bccfb29 | 76 | #define ARCH_riscv |
252b5132 | 77 | #define ARCH_rs6000 |
99c513f6 | 78 | #define ARCH_rl78 |
c7927a3c | 79 | #define ARCH_rx |
9da4dfd6 | 80 | #define ARCH_s12z |
a85d7ed0 | 81 | #define ARCH_s390 |
1c0d3aa6 | 82 | #define ARCH_score |
252b5132 RH |
83 | #define ARCH_sh |
84 | #define ARCH_sparc | |
e9f53129 | 85 | #define ARCH_spu |
252b5132 | 86 | #define ARCH_tic30 |
026df7c5 | 87 | #define ARCH_tic4x |
5c84d377 | 88 | #define ARCH_tic54x |
40b36596 | 89 | #define ARCH_tic6x |
252b5132 | 90 | #define ARCH_tic80 |
aa137e4d NC |
91 | #define ARCH_tilegx |
92 | #define ARCH_tilepro | |
252b5132 RH |
93 | #define ARCH_v850 |
94 | #define ARCH_vax | |
1945cfa5 | 95 | #define ARCH_visium |
62ecb94c | 96 | #define ARCH_wasm32 |
93fbbb04 | 97 | #define ARCH_xstormy16 |
d70c5fc7 | 98 | #define ARCH_xc16x |
f6c1a2d5 | 99 | #define ARCH_xgate |
e0001a05 | 100 | #define ARCH_xtensa |
3c9b82ba | 101 | #define ARCH_z80 |
252b5132 RH |
102 | #define ARCH_z8k |
103 | #endif | |
104 | ||
49f58d10 JB |
105 | #ifdef ARCH_m32c |
106 | #include "m32c-desc.h" | |
107 | #endif | |
252b5132 RH |
108 | |
109 | disassembler_ftype | |
b28b8b5e L |
110 | disassembler (enum bfd_architecture a, |
111 | bfd_boolean big ATTRIBUTE_UNUSED, | |
112 | unsigned long mach ATTRIBUTE_UNUSED, | |
e347efc3 | 113 | bfd *abfd ATTRIBUTE_UNUSED) |
252b5132 | 114 | { |
252b5132 RH |
115 | disassembler_ftype disassemble; |
116 | ||
117 | switch (a) | |
118 | { | |
119 | /* If you add a case to this table, also add it to the | |
120 | ARCH_all definition right above this function. */ | |
a06ea964 NC |
121 | #ifdef ARCH_aarch64 |
122 | case bfd_arch_aarch64: | |
123 | disassemble = print_insn_aarch64; | |
124 | break; | |
125 | #endif | |
252b5132 RH |
126 | #ifdef ARCH_alpha |
127 | case bfd_arch_alpha: | |
128 | disassemble = print_insn_alpha; | |
129 | break; | |
130 | #endif | |
131 | #ifdef ARCH_arc | |
132 | case bfd_arch_arc: | |
6ca4eb77 AM |
133 | disassemble = arc_get_disassembler (abfd); |
134 | break; | |
252b5132 RH |
135 | #endif |
136 | #ifdef ARCH_arm | |
137 | case bfd_arch_arm: | |
003ca0fd | 138 | if (big) |
252b5132 RH |
139 | disassemble = print_insn_big_arm; |
140 | else | |
141 | disassemble = print_insn_little_arm; | |
142 | break; | |
143 | #endif | |
adde6300 AM |
144 | #ifdef ARCH_avr |
145 | case bfd_arch_avr: | |
146 | disassemble = print_insn_avr; | |
147 | break; | |
148 | #endif | |
4b7f6baa CM |
149 | #ifdef ARCH_bfin |
150 | case bfd_arch_bfin: | |
151 | disassemble = print_insn_bfin; | |
152 | break; | |
153 | #endif | |
3d3d428f NC |
154 | #ifdef ARCH_cr16 |
155 | case bfd_arch_cr16: | |
156 | disassemble = print_insn_cr16; | |
157 | break; | |
158 | #endif | |
6c95a37f HPN |
159 | #ifdef ARCH_cris |
160 | case bfd_arch_cris: | |
78966507 | 161 | disassemble = cris_get_disassembler (abfd); |
6c95a37f | 162 | break; |
1fe1f39c NC |
163 | #endif |
164 | #ifdef ARCH_crx | |
165 | case bfd_arch_crx: | |
166 | disassemble = print_insn_crx; | |
167 | break; | |
6c95a37f | 168 | #endif |
b8891f8d AJ |
169 | #ifdef ARCH_csky |
170 | case bfd_arch_csky: | |
171 | disassemble = csky_get_disassembler (abfd); | |
172 | break; | |
173 | #endif | |
174 | ||
252b5132 RH |
175 | #ifdef ARCH_d10v |
176 | case bfd_arch_d10v: | |
177 | disassemble = print_insn_d10v; | |
178 | break; | |
179 | #endif | |
180 | #ifdef ARCH_d30v | |
181 | case bfd_arch_d30v: | |
182 | disassemble = print_insn_d30v; | |
183 | break; | |
184 | #endif | |
d172d4ba NC |
185 | #ifdef ARCH_dlx |
186 | case bfd_arch_dlx: | |
187 | /* As far as I know we only handle big-endian DLX objects. */ | |
188 | disassemble = print_insn_dlx; | |
189 | break; | |
190 | #endif | |
252b5132 RH |
191 | #ifdef ARCH_h8300 |
192 | case bfd_arch_h8300: | |
003ca0fd | 193 | if (mach == bfd_mach_h8300h || mach == bfd_mach_h8300hn) |
252b5132 | 194 | disassemble = print_insn_h8300h; |
003ca0fd YQ |
195 | else if (mach == bfd_mach_h8300s |
196 | || mach == bfd_mach_h8300sn | |
197 | || mach == bfd_mach_h8300sx | |
198 | || mach == bfd_mach_h8300sxn) | |
252b5132 | 199 | disassemble = print_insn_h8300s; |
b7ed8fad | 200 | else |
252b5132 RH |
201 | disassemble = print_insn_h8300; |
202 | break; | |
203 | #endif | |
252b5132 RH |
204 | #ifdef ARCH_hppa |
205 | case bfd_arch_hppa: | |
206 | disassemble = print_insn_hppa; | |
207 | break; | |
208 | #endif | |
209 | #ifdef ARCH_i386 | |
210 | case bfd_arch_i386: | |
7b6d09fb | 211 | case bfd_arch_iamcu: |
8a9036a4 | 212 | case bfd_arch_l1om: |
7a9068fe | 213 | case bfd_arch_k1om: |
e396998b | 214 | disassemble = print_insn_i386; |
252b5132 RH |
215 | break; |
216 | #endif | |
800eeca4 JW |
217 | #ifdef ARCH_ia64 |
218 | case bfd_arch_ia64: | |
219 | disassemble = print_insn_ia64; | |
220 | break; | |
221 | #endif | |
a40cbfa3 NC |
222 | #ifdef ARCH_ip2k |
223 | case bfd_arch_ip2k: | |
224 | disassemble = print_insn_ip2k; | |
225 | break; | |
226 | #endif | |
cfb8c092 NC |
227 | #ifdef ARCH_epiphany |
228 | case bfd_arch_epiphany: | |
229 | disassemble = print_insn_epiphany; | |
230 | break; | |
231 | #endif | |
252b5132 RH |
232 | #ifdef ARCH_fr30 |
233 | case bfd_arch_fr30: | |
234 | disassemble = print_insn_fr30; | |
235 | break; | |
236 | #endif | |
84e94c90 NC |
237 | #ifdef ARCH_lm32 |
238 | case bfd_arch_lm32: | |
239 | disassemble = print_insn_lm32; | |
240 | break; | |
241 | #endif | |
252b5132 RH |
242 | #ifdef ARCH_m32r |
243 | case bfd_arch_m32r: | |
244 | disassemble = print_insn_m32r; | |
245 | break; | |
246 | #endif | |
6927f982 NC |
247 | #if defined(ARCH_m68hc11) || defined(ARCH_m68hc12) \ |
248 | || defined(ARCH_9s12x) || defined(ARCH_m9s12xg) | |
60bcf0fa NC |
249 | case bfd_arch_m68hc11: |
250 | disassemble = print_insn_m68hc11; | |
251 | break; | |
252 | case bfd_arch_m68hc12: | |
253 | disassemble = print_insn_m68hc12; | |
254 | break; | |
6927f982 NC |
255 | case bfd_arch_m9s12x: |
256 | disassemble = print_insn_m9s12x; | |
257 | break; | |
258 | case bfd_arch_m9s12xg: | |
259 | disassemble = print_insn_m9s12xg; | |
260 | break; | |
60bcf0fa | 261 | #endif |
7b4ae824 JD |
262 | #if defined(ARCH_s12z) |
263 | case bfd_arch_s12z: | |
264 | disassemble = print_insn_s12z; | |
265 | break; | |
266 | #endif | |
252b5132 RH |
267 | #ifdef ARCH_m68k |
268 | case bfd_arch_m68k: | |
269 | disassemble = print_insn_m68k; | |
270 | break; | |
271 | #endif | |
d031aafb NS |
272 | #ifdef ARCH_mt |
273 | case bfd_arch_mt: | |
274 | disassemble = print_insn_mt; | |
ac188222 DB |
275 | break; |
276 | #endif | |
7ba29e2a NC |
277 | #ifdef ARCH_microblaze |
278 | case bfd_arch_microblaze: | |
279 | disassemble = print_insn_microblaze; | |
280 | break; | |
281 | #endif | |
2469cfa2 NC |
282 | #ifdef ARCH_msp430 |
283 | case bfd_arch_msp430: | |
284 | disassemble = print_insn_msp430; | |
285 | break; | |
286 | #endif | |
35c08157 KLC |
287 | #ifdef ARCH_nds32 |
288 | case bfd_arch_nds32: | |
289 | disassemble = print_insn_nds32; | |
290 | break; | |
291 | #endif | |
fe944acf FT |
292 | #ifdef ARCH_nfp |
293 | case bfd_arch_nfp: | |
294 | disassemble = print_insn_nfp; | |
295 | break; | |
296 | #endif | |
252b5132 RH |
297 | #ifdef ARCH_ns32k |
298 | case bfd_arch_ns32k: | |
299 | disassemble = print_insn_ns32k; | |
300 | break; | |
301 | #endif | |
302 | #ifdef ARCH_mcore | |
303 | case bfd_arch_mcore: | |
304 | disassemble = print_insn_mcore; | |
305 | break; | |
306 | #endif | |
bd2f2e55 DB |
307 | #ifdef ARCH_mep |
308 | case bfd_arch_mep: | |
309 | disassemble = print_insn_mep; | |
310 | break; | |
311 | #endif | |
a3c62988 NC |
312 | #ifdef ARCH_metag |
313 | case bfd_arch_metag: | |
314 | disassemble = print_insn_metag; | |
315 | break; | |
316 | #endif | |
252b5132 RH |
317 | #ifdef ARCH_mips |
318 | case bfd_arch_mips: | |
003ca0fd | 319 | if (big) |
252b5132 RH |
320 | disassemble = print_insn_big_mips; |
321 | else | |
322 | disassemble = print_insn_little_mips; | |
323 | break; | |
324 | #endif | |
3c3bdf30 NC |
325 | #ifdef ARCH_mmix |
326 | case bfd_arch_mmix: | |
327 | disassemble = print_insn_mmix; | |
328 | break; | |
329 | #endif | |
252b5132 RH |
330 | #ifdef ARCH_mn10200 |
331 | case bfd_arch_mn10200: | |
332 | disassemble = print_insn_mn10200; | |
333 | break; | |
334 | #endif | |
335 | #ifdef ARCH_mn10300 | |
336 | case bfd_arch_mn10300: | |
337 | disassemble = print_insn_mn10300; | |
338 | break; | |
339 | #endif | |
36591ba1 SL |
340 | #ifdef ARCH_nios2 |
341 | case bfd_arch_nios2: | |
003ca0fd | 342 | if (big) |
36591ba1 SL |
343 | disassemble = print_insn_big_nios2; |
344 | else | |
345 | disassemble = print_insn_little_nios2; | |
346 | break; | |
347 | #endif | |
73589c9d CS |
348 | #ifdef ARCH_or1k |
349 | case bfd_arch_or1k: | |
350 | disassemble = print_insn_or1k; | |
3b16e843 NC |
351 | break; |
352 | #endif | |
e135f41b NC |
353 | #ifdef ARCH_pdp11 |
354 | case bfd_arch_pdp11: | |
355 | disassemble = print_insn_pdp11; | |
356 | break; | |
357 | #endif | |
1e608f98 ILT |
358 | #ifdef ARCH_pj |
359 | case bfd_arch_pj: | |
360 | disassemble = print_insn_pj; | |
361 | break; | |
362 | #endif | |
252b5132 RH |
363 | #ifdef ARCH_powerpc |
364 | case bfd_arch_powerpc: | |
52fe4420 AM |
365 | #endif |
366 | #ifdef ARCH_rs6000 | |
367 | case bfd_arch_rs6000: | |
368 | #endif | |
369 | #if defined ARCH_powerpc || defined ARCH_rs6000 | |
003ca0fd | 370 | if (big) |
252b5132 RH |
371 | disassemble = print_insn_big_powerpc; |
372 | else | |
373 | disassemble = print_insn_little_powerpc; | |
374 | break; | |
375 | #endif | |
11146849 DD |
376 | #ifdef ARCH_pru |
377 | case bfd_arch_pru: | |
378 | disassemble = print_insn_pru; | |
379 | break; | |
380 | #endif | |
e23eba97 NC |
381 | #ifdef ARCH_riscv |
382 | case bfd_arch_riscv: | |
383 | disassemble = print_insn_riscv; | |
ae4c0df4 | 384 | break; |
e23eba97 | 385 | #endif |
99c513f6 DD |
386 | #ifdef ARCH_rl78 |
387 | case bfd_arch_rl78: | |
0952813b | 388 | disassemble = rl78_get_disassembler (abfd); |
99c513f6 DD |
389 | break; |
390 | #endif | |
c7927a3c NC |
391 | #ifdef ARCH_rx |
392 | case bfd_arch_rx: | |
393 | disassemble = print_insn_rx; | |
394 | break; | |
395 | #endif | |
a85d7ed0 NC |
396 | #ifdef ARCH_s390 |
397 | case bfd_arch_s390: | |
398 | disassemble = print_insn_s390; | |
399 | break; | |
400 | #endif | |
1c0d3aa6 NC |
401 | #ifdef ARCH_score |
402 | case bfd_arch_score: | |
003ca0fd | 403 | if (big) |
6ca4eb77 | 404 | disassemble = print_insn_big_score; |
1c0d3aa6 | 405 | else |
6ca4eb77 | 406 | disassemble = print_insn_little_score; |
1c0d3aa6 NC |
407 | break; |
408 | #endif | |
252b5132 RH |
409 | #ifdef ARCH_sh |
410 | case bfd_arch_sh: | |
1c509ca8 | 411 | disassemble = print_insn_sh; |
252b5132 RH |
412 | break; |
413 | #endif | |
414 | #ifdef ARCH_sparc | |
415 | case bfd_arch_sparc: | |
416 | disassemble = print_insn_sparc; | |
417 | break; | |
418 | #endif | |
e9f53129 AM |
419 | #ifdef ARCH_spu |
420 | case bfd_arch_spu: | |
421 | disassemble = print_insn_spu; | |
422 | break; | |
423 | #endif | |
252b5132 RH |
424 | #ifdef ARCH_tic30 |
425 | case bfd_arch_tic30: | |
426 | disassemble = print_insn_tic30; | |
427 | break; | |
428 | #endif | |
026df7c5 NC |
429 | #ifdef ARCH_tic4x |
430 | case bfd_arch_tic4x: | |
431 | disassemble = print_insn_tic4x; | |
432 | break; | |
433 | #endif | |
5c84d377 TW |
434 | #ifdef ARCH_tic54x |
435 | case bfd_arch_tic54x: | |
436 | disassemble = print_insn_tic54x; | |
437 | break; | |
438 | #endif | |
40b36596 JM |
439 | #ifdef ARCH_tic6x |
440 | case bfd_arch_tic6x: | |
441 | disassemble = print_insn_tic6x; | |
442 | break; | |
443 | #endif | |
252b5132 RH |
444 | #ifdef ARCH_tic80 |
445 | case bfd_arch_tic80: | |
446 | disassemble = print_insn_tic80; | |
447 | break; | |
448 | #endif | |
3f8107ab AM |
449 | #ifdef ARCH_ft32 |
450 | case bfd_arch_ft32: | |
451 | disassemble = print_insn_ft32; | |
452 | break; | |
453 | #endif | |
252b5132 RH |
454 | #ifdef ARCH_v850 |
455 | case bfd_arch_v850: | |
de863c74 | 456 | case bfd_arch_v850_rh850: |
252b5132 RH |
457 | disassemble = print_insn_v850; |
458 | break; | |
459 | #endif | |
62ecb94c PC |
460 | #ifdef ARCH_wasm32 |
461 | case bfd_arch_wasm32: | |
462 | disassemble = print_insn_wasm32; | |
463 | break; | |
464 | #endif | |
f6c1a2d5 NC |
465 | #ifdef ARCH_xgate |
466 | case bfd_arch_xgate: | |
467 | disassemble = print_insn_xgate; | |
468 | break; | |
469 | #endif | |
93fbbb04 GK |
470 | #ifdef ARCH_xstormy16 |
471 | case bfd_arch_xstormy16: | |
472 | disassemble = print_insn_xstormy16; | |
473 | break; | |
474 | #endif | |
d70c5fc7 NC |
475 | #ifdef ARCH_xc16x |
476 | case bfd_arch_xc16x: | |
477 | disassemble = print_insn_xc16x; | |
478 | break; | |
479 | #endif | |
e0001a05 NC |
480 | #ifdef ARCH_xtensa |
481 | case bfd_arch_xtensa: | |
482 | disassemble = print_insn_xtensa; | |
483 | break; | |
484 | #endif | |
3c9b82ba NC |
485 | #ifdef ARCH_z80 |
486 | case bfd_arch_z80: | |
487 | disassemble = print_insn_z80; | |
488 | break; | |
489 | #endif | |
252b5132 RH |
490 | #ifdef ARCH_z8k |
491 | case bfd_arch_z8k: | |
003ca0fd | 492 | if (mach == bfd_mach_z8001) |
252b5132 | 493 | disassemble = print_insn_z8001; |
b7ed8fad | 494 | else |
252b5132 RH |
495 | disassemble = print_insn_z8002; |
496 | break; | |
497 | #endif | |
498 | #ifdef ARCH_vax | |
499 | case bfd_arch_vax: | |
500 | disassemble = print_insn_vax; | |
501 | break; | |
fd3c93d5 | 502 | #endif |
1945cfa5 EB |
503 | #ifdef ARCH_visium |
504 | case bfd_arch_visium: | |
505 | disassemble = print_insn_visium; | |
506 | break; | |
507 | #endif | |
fd3c93d5 DB |
508 | #ifdef ARCH_frv |
509 | case bfd_arch_frv: | |
510 | disassemble = print_insn_frv; | |
511 | break; | |
47b1a55a | 512 | #endif |
59b1530d AG |
513 | #ifdef ARCH_moxie |
514 | case bfd_arch_moxie: | |
515 | disassemble = print_insn_moxie; | |
516 | break; | |
517 | #endif | |
47b1a55a SC |
518 | #ifdef ARCH_iq2000 |
519 | case bfd_arch_iq2000: | |
520 | disassemble = print_insn_iq2000; | |
521 | break; | |
49f58d10 JB |
522 | #endif |
523 | #ifdef ARCH_m32c | |
524 | case bfd_arch_m32c: | |
525 | disassemble = print_insn_m32c; | |
526 | break; | |
aa137e4d NC |
527 | #endif |
528 | #ifdef ARCH_tilegx | |
529 | case bfd_arch_tilegx: | |
530 | disassemble = print_insn_tilegx; | |
531 | break; | |
532 | #endif | |
533 | #ifdef ARCH_tilepro | |
534 | case bfd_arch_tilepro: | |
535 | disassemble = print_insn_tilepro; | |
536 | break; | |
252b5132 RH |
537 | #endif |
538 | default: | |
539 | return 0; | |
540 | } | |
541 | return disassemble; | |
542 | } | |
94470b23 NC |
543 | |
544 | void | |
e6c7cdec | 545 | disassembler_usage (FILE *stream ATTRIBUTE_UNUSED) |
94470b23 | 546 | { |
a06ea964 NC |
547 | #ifdef ARCH_aarch64 |
548 | print_aarch64_disassembler_options (stream); | |
549 | #endif | |
37fd5ef3 CZ |
550 | #ifdef ARCH_arc |
551 | print_arc_disassembler_options (stream); | |
552 | #endif | |
58efb6c0 NC |
553 | #ifdef ARCH_arm |
554 | print_arm_disassembler_options (stream); | |
555 | #endif | |
640c0ccd CD |
556 | #ifdef ARCH_mips |
557 | print_mips_disassembler_options (stream); | |
558 | #endif | |
fe944acf FT |
559 | #ifdef ARCH_nfp |
560 | print_nfp_disassembler_options (stream); | |
561 | #endif | |
07dd56a9 NC |
562 | #ifdef ARCH_powerpc |
563 | print_ppc_disassembler_options (stream); | |
564 | #endif | |
e23eba97 NC |
565 | #ifdef ARCH_riscv |
566 | print_riscv_disassembler_options (stream); | |
567 | #endif | |
f59a29b9 L |
568 | #ifdef ARCH_i386 |
569 | print_i386_disassembler_options (stream); | |
570 | #endif | |
112b7c50 AK |
571 | #ifdef ARCH_s390 |
572 | print_s390_disassembler_options (stream); | |
573 | #endif | |
62ecb94c PC |
574 | #ifdef ARCH_wasm32 |
575 | print_wasm32_disassembler_options (stream); | |
576 | #endif | |
b7ed8fad | 577 | |
94470b23 NC |
578 | return; |
579 | } | |
22a398e1 NC |
580 | |
581 | void | |
582 | disassemble_init_for_target (struct disassemble_info * info) | |
583 | { | |
584 | if (info == NULL) | |
585 | return; | |
586 | ||
587 | switch (info->arch) | |
588 | { | |
a06ea964 NC |
589 | #ifdef ARCH_aarch64 |
590 | case bfd_arch_aarch64: | |
591 | info->symbol_is_valid = aarch64_symbol_is_valid; | |
592 | info->disassembler_needs_relocs = TRUE; | |
593 | break; | |
594 | #endif | |
22a398e1 NC |
595 | #ifdef ARCH_arm |
596 | case bfd_arch_arm: | |
597 | info->symbol_is_valid = arm_symbol_is_valid; | |
d99b6465 | 598 | info->disassembler_needs_relocs = TRUE; |
22a398e1 | 599 | break; |
0bcb06d2 | 600 | #endif |
b8891f8d AJ |
601 | #ifdef ARCH_csky |
602 | case bfd_arch_csky: | |
603 | info->symbol_is_valid = csky_symbol_is_valid; | |
604 | info->disassembler_needs_relocs = TRUE; | |
605 | break; | |
606 | #endif | |
607 | ||
0bcb06d2 AS |
608 | #ifdef ARCH_ia64 |
609 | case bfd_arch_ia64: | |
610 | info->skip_zeroes = 16; | |
611 | break; | |
612 | #endif | |
613 | #ifdef ARCH_tic4x | |
614 | case bfd_arch_tic4x: | |
615 | info->skip_zeroes = 32; | |
fb53f5a8 | 616 | break; |
49f58d10 | 617 | #endif |
bd2f2e55 DB |
618 | #ifdef ARCH_mep |
619 | case bfd_arch_mep: | |
620 | info->skip_zeroes = 256; | |
621 | info->skip_zeroes_at_end = 0; | |
622 | break; | |
623 | #endif | |
a3c62988 NC |
624 | #ifdef ARCH_metag |
625 | case bfd_arch_metag: | |
626 | info->disassembler_needs_relocs = TRUE; | |
627 | break; | |
628 | #endif | |
49f58d10 JB |
629 | #ifdef ARCH_m32c |
630 | case bfd_arch_m32c: | |
6ca4eb77 AM |
631 | /* This processor in fact is little endian. The value set here |
632 | reflects the way opcodes are written in the cgen description. */ | |
49f58d10 | 633 | info->endian = BFD_ENDIAN_BIG; |
fb53f5a8 DB |
634 | if (! info->insn_sets) |
635 | { | |
636 | info->insn_sets = cgen_bitset_create (ISA_MAX); | |
637 | if (info->mach == bfd_mach_m16c) | |
638 | cgen_bitset_set (info->insn_sets, ISA_M16C); | |
639 | else | |
640 | cgen_bitset_set (info->insn_sets, ISA_M32C); | |
641 | } | |
49f58d10 | 642 | break; |
b240011a | 643 | #endif |
024d185c DD |
644 | #ifdef ARCH_pru |
645 | case bfd_arch_pru: | |
646 | info->disassembler_needs_relocs = TRUE; | |
647 | break; | |
648 | #endif | |
fbc22555 DD |
649 | #ifdef ARCH_powerpc |
650 | case bfd_arch_powerpc: | |
651 | #endif | |
b240011a AM |
652 | #ifdef ARCH_rs6000 |
653 | case bfd_arch_rs6000: | |
654 | #endif | |
655 | #if defined (ARCH_powerpc) || defined (ARCH_rs6000) | |
656 | disassemble_init_powerpc (info); | |
657 | break; | |
65b48a81 | 658 | #endif |
62ecb94c PC |
659 | #ifdef ARCH_wasm32 |
660 | case bfd_arch_wasm32: | |
661 | disassemble_init_wasm32 (info); | |
662 | break; | |
663 | #endif | |
65b48a81 PB |
664 | #ifdef ARCH_s390 |
665 | case bfd_arch_s390: | |
666 | disassemble_init_s390 (info); | |
667 | break; | |
22a398e1 NC |
668 | #endif |
669 | default: | |
670 | break; | |
671 | } | |
672 | } | |
65b48a81 PB |
673 | |
674 | /* Remove whitespace and consecutive commas from OPTIONS. */ | |
675 | ||
676 | char * | |
677 | remove_whitespace_and_extra_commas (char *options) | |
678 | { | |
679 | char *str; | |
680 | size_t i, len; | |
681 | ||
682 | if (options == NULL) | |
683 | return NULL; | |
684 | ||
685 | /* Strip off all trailing whitespace and commas. */ | |
686 | for (len = strlen (options); len > 0; len--) | |
687 | { | |
688 | if (!ISSPACE (options[len - 1]) && options[len - 1] != ',') | |
689 | break; | |
690 | options[len - 1] = '\0'; | |
691 | } | |
692 | ||
693 | /* Convert all remaining whitespace to commas. */ | |
694 | for (i = 0; options[i] != '\0'; i++) | |
695 | if (ISSPACE (options[i])) | |
696 | options[i] = ','; | |
697 | ||
698 | /* Remove consecutive commas. */ | |
699 | for (str = options; *str != '\0'; str++) | |
700 | if (*str == ',' && (*(str + 1) == ',' || str == options)) | |
701 | { | |
702 | char *next = str + 1; | |
703 | while (*next == ',') | |
704 | next++; | |
705 | len = strlen (next); | |
706 | if (str != options) | |
707 | str++; | |
708 | memmove (str, next, len); | |
709 | next[len - (size_t)(next - str)] = '\0'; | |
710 | } | |
711 | return (strlen (options) != 0) ? options : NULL; | |
712 | } | |
713 | ||
714 | /* Like STRCMP, but treat ',' the same as '\0' so that we match | |
715 | strings like "foobar" against "foobar,xxyyzz,...". */ | |
716 | ||
717 | int | |
718 | disassembler_options_cmp (const char *s1, const char *s2) | |
719 | { | |
720 | unsigned char c1, c2; | |
721 | ||
722 | do | |
723 | { | |
724 | c1 = (unsigned char) *s1++; | |
725 | if (c1 == ',') | |
726 | c1 = '\0'; | |
727 | c2 = (unsigned char) *s2++; | |
728 | if (c2 == ',') | |
729 | c2 = '\0'; | |
730 | if (c1 == '\0') | |
731 | return c1 - c2; | |
732 | } | |
733 | while (c1 == c2); | |
734 | ||
735 | return c1 - c2; | |
736 | } |