Commit | Line | Data |
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252b5132 | 1 | /* Select disassembly routine for specified architecture. |
aef6203b | 2 | Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, |
9b201bb5 | 3 | 2004, 2005, 2006, 2007 Free Software Foundation, Inc. |
252b5132 | 4 | |
9b201bb5 NC |
5 | This file is part of the GNU opcodes library. |
6 | ||
7 | This library is free software; you can redistribute it and/or modify | |
7499d566 | 8 | it under the terms of the GNU General Public License as published by |
9b201bb5 | 9 | the Free Software Foundation; either version 3 of the License, or |
7499d566 | 10 | (at your option) any later version. |
252b5132 | 11 | |
7499d566 NC |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
252b5132 | 16 | |
7499d566 NC |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
19 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
20 | MA 02110-1301, USA. */ | |
252b5132 | 21 | |
0d8dfecf | 22 | #include "sysdep.h" |
252b5132 RH |
23 | #include "dis-asm.h" |
24 | ||
25 | #ifdef ARCH_all | |
252b5132 RH |
26 | #define ARCH_alpha |
27 | #define ARCH_arc | |
28 | #define ARCH_arm | |
adde6300 | 29 | #define ARCH_avr |
4b7f6baa | 30 | #define ARCH_bfin |
3d3d428f | 31 | #define ARCH_cr16 |
6c95a37f | 32 | #define ARCH_cris |
1fe1f39c | 33 | #define ARCH_crx |
252b5132 RH |
34 | #define ARCH_d10v |
35 | #define ARCH_d30v | |
d172d4ba | 36 | #define ARCH_dlx |
e729279b NC |
37 | #define ARCH_fr30 |
38 | #define ARCH_frv | |
252b5132 RH |
39 | #define ARCH_h8300 |
40 | #define ARCH_h8500 | |
41 | #define ARCH_hppa | |
5b93d8bb | 42 | #define ARCH_i370 |
252b5132 | 43 | #define ARCH_i386 |
9d751335 | 44 | #define ARCH_i860 |
252b5132 | 45 | #define ARCH_i960 |
800eeca4 | 46 | #define ARCH_ia64 |
e729279b NC |
47 | #define ARCH_ip2k |
48 | #define ARCH_iq2000 | |
84e94c90 | 49 | #define ARCH_lm32 |
e729279b | 50 | #define ARCH_m32c |
252b5132 | 51 | #define ARCH_m32r |
60bcf0fa NC |
52 | #define ARCH_m68hc11 |
53 | #define ARCH_m68hc12 | |
e729279b | 54 | #define ARCH_m68k |
252b5132 | 55 | #define ARCH_m88k |
7499d566 | 56 | #define ARCH_maxq |
252b5132 | 57 | #define ARCH_mcore |
bd2f2e55 | 58 | #define ARCH_mep |
252b5132 | 59 | #define ARCH_mips |
3c3bdf30 | 60 | #define ARCH_mmix |
252b5132 RH |
61 | #define ARCH_mn10200 |
62 | #define ARCH_mn10300 | |
59b1530d | 63 | #define ARCH_moxie |
d031aafb | 64 | #define ARCH_mt |
2469cfa2 | 65 | #define ARCH_msp430 |
252b5132 | 66 | #define ARCH_ns32k |
87e6d782 | 67 | #define ARCH_openrisc |
3b16e843 | 68 | #define ARCH_or32 |
e135f41b | 69 | #define ARCH_pdp11 |
1e608f98 | 70 | #define ARCH_pj |
252b5132 RH |
71 | #define ARCH_powerpc |
72 | #define ARCH_rs6000 | |
a85d7ed0 | 73 | #define ARCH_s390 |
1c0d3aa6 | 74 | #define ARCH_score |
252b5132 RH |
75 | #define ARCH_sh |
76 | #define ARCH_sparc | |
e9f53129 | 77 | #define ARCH_spu |
252b5132 | 78 | #define ARCH_tic30 |
026df7c5 | 79 | #define ARCH_tic4x |
5c84d377 | 80 | #define ARCH_tic54x |
252b5132 RH |
81 | #define ARCH_tic80 |
82 | #define ARCH_v850 | |
83 | #define ARCH_vax | |
84 | #define ARCH_w65 | |
93fbbb04 | 85 | #define ARCH_xstormy16 |
d70c5fc7 | 86 | #define ARCH_xc16x |
e0001a05 | 87 | #define ARCH_xtensa |
3c9b82ba | 88 | #define ARCH_z80 |
252b5132 | 89 | #define ARCH_z8k |
d28847ce | 90 | #define INCLUDE_SHMEDIA |
252b5132 RH |
91 | #endif |
92 | ||
49f58d10 JB |
93 | #ifdef ARCH_m32c |
94 | #include "m32c-desc.h" | |
95 | #endif | |
252b5132 RH |
96 | |
97 | disassembler_ftype | |
98 | disassembler (abfd) | |
99 | bfd *abfd; | |
100 | { | |
101 | enum bfd_architecture a = bfd_get_arch (abfd); | |
102 | disassembler_ftype disassemble; | |
103 | ||
104 | switch (a) | |
105 | { | |
106 | /* If you add a case to this table, also add it to the | |
107 | ARCH_all definition right above this function. */ | |
252b5132 RH |
108 | #ifdef ARCH_alpha |
109 | case bfd_arch_alpha: | |
110 | disassemble = print_insn_alpha; | |
111 | break; | |
112 | #endif | |
113 | #ifdef ARCH_arc | |
114 | case bfd_arch_arc: | |
115 | { | |
0d2bcfaf | 116 | disassemble = arc_get_disassembler (abfd); |
252b5132 RH |
117 | break; |
118 | } | |
119 | #endif | |
120 | #ifdef ARCH_arm | |
121 | case bfd_arch_arm: | |
122 | if (bfd_big_endian (abfd)) | |
123 | disassemble = print_insn_big_arm; | |
124 | else | |
125 | disassemble = print_insn_little_arm; | |
126 | break; | |
127 | #endif | |
adde6300 AM |
128 | #ifdef ARCH_avr |
129 | case bfd_arch_avr: | |
130 | disassemble = print_insn_avr; | |
131 | break; | |
132 | #endif | |
4b7f6baa CM |
133 | #ifdef ARCH_bfin |
134 | case bfd_arch_bfin: | |
135 | disassemble = print_insn_bfin; | |
136 | break; | |
137 | #endif | |
3d3d428f NC |
138 | #ifdef ARCH_cr16 |
139 | case bfd_arch_cr16: | |
140 | disassemble = print_insn_cr16; | |
141 | break; | |
142 | #endif | |
6c95a37f HPN |
143 | #ifdef ARCH_cris |
144 | case bfd_arch_cris: | |
78966507 | 145 | disassemble = cris_get_disassembler (abfd); |
6c95a37f | 146 | break; |
1fe1f39c NC |
147 | #endif |
148 | #ifdef ARCH_crx | |
149 | case bfd_arch_crx: | |
150 | disassemble = print_insn_crx; | |
151 | break; | |
6c95a37f | 152 | #endif |
252b5132 RH |
153 | #ifdef ARCH_d10v |
154 | case bfd_arch_d10v: | |
155 | disassemble = print_insn_d10v; | |
156 | break; | |
157 | #endif | |
158 | #ifdef ARCH_d30v | |
159 | case bfd_arch_d30v: | |
160 | disassemble = print_insn_d30v; | |
161 | break; | |
162 | #endif | |
d172d4ba NC |
163 | #ifdef ARCH_dlx |
164 | case bfd_arch_dlx: | |
165 | /* As far as I know we only handle big-endian DLX objects. */ | |
166 | disassemble = print_insn_dlx; | |
167 | break; | |
168 | #endif | |
252b5132 RH |
169 | #ifdef ARCH_h8300 |
170 | case bfd_arch_h8300: | |
049f8936 NC |
171 | if (bfd_get_mach (abfd) == bfd_mach_h8300h |
172 | || bfd_get_mach (abfd) == bfd_mach_h8300hn) | |
252b5132 | 173 | disassemble = print_insn_h8300h; |
049f8936 | 174 | else if (bfd_get_mach (abfd) == bfd_mach_h8300s |
d43ff6d2 | 175 | || bfd_get_mach (abfd) == bfd_mach_h8300sn |
a53b85e2 AO |
176 | || bfd_get_mach (abfd) == bfd_mach_h8300sx |
177 | || bfd_get_mach (abfd) == bfd_mach_h8300sxn) | |
252b5132 | 178 | disassemble = print_insn_h8300s; |
b7ed8fad | 179 | else |
252b5132 RH |
180 | disassemble = print_insn_h8300; |
181 | break; | |
182 | #endif | |
183 | #ifdef ARCH_h8500 | |
184 | case bfd_arch_h8500: | |
185 | disassemble = print_insn_h8500; | |
186 | break; | |
187 | #endif | |
188 | #ifdef ARCH_hppa | |
189 | case bfd_arch_hppa: | |
190 | disassemble = print_insn_hppa; | |
191 | break; | |
192 | #endif | |
5b93d8bb AM |
193 | #ifdef ARCH_i370 |
194 | case bfd_arch_i370: | |
195 | disassemble = print_insn_i370; | |
196 | break; | |
197 | #endif | |
252b5132 RH |
198 | #ifdef ARCH_i386 |
199 | case bfd_arch_i386: | |
e396998b | 200 | disassemble = print_insn_i386; |
252b5132 RH |
201 | break; |
202 | #endif | |
9d751335 JE |
203 | #ifdef ARCH_i860 |
204 | case bfd_arch_i860: | |
205 | disassemble = print_insn_i860; | |
206 | break; | |
207 | #endif | |
252b5132 RH |
208 | #ifdef ARCH_i960 |
209 | case bfd_arch_i960: | |
210 | disassemble = print_insn_i960; | |
211 | break; | |
212 | #endif | |
800eeca4 JW |
213 | #ifdef ARCH_ia64 |
214 | case bfd_arch_ia64: | |
215 | disassemble = print_insn_ia64; | |
216 | break; | |
217 | #endif | |
a40cbfa3 NC |
218 | #ifdef ARCH_ip2k |
219 | case bfd_arch_ip2k: | |
220 | disassemble = print_insn_ip2k; | |
221 | break; | |
222 | #endif | |
252b5132 RH |
223 | #ifdef ARCH_fr30 |
224 | case bfd_arch_fr30: | |
225 | disassemble = print_insn_fr30; | |
226 | break; | |
227 | #endif | |
84e94c90 NC |
228 | #ifdef ARCH_lm32 |
229 | case bfd_arch_lm32: | |
230 | disassemble = print_insn_lm32; | |
231 | break; | |
232 | #endif | |
252b5132 RH |
233 | #ifdef ARCH_m32r |
234 | case bfd_arch_m32r: | |
235 | disassemble = print_insn_m32r; | |
236 | break; | |
237 | #endif | |
60bcf0fa NC |
238 | #if defined(ARCH_m68hc11) || defined(ARCH_m68hc12) |
239 | case bfd_arch_m68hc11: | |
240 | disassemble = print_insn_m68hc11; | |
241 | break; | |
242 | case bfd_arch_m68hc12: | |
243 | disassemble = print_insn_m68hc12; | |
244 | break; | |
245 | #endif | |
252b5132 RH |
246 | #ifdef ARCH_m68k |
247 | case bfd_arch_m68k: | |
248 | disassemble = print_insn_m68k; | |
249 | break; | |
250 | #endif | |
251 | #ifdef ARCH_m88k | |
252 | case bfd_arch_m88k: | |
253 | disassemble = print_insn_m88k; | |
254 | break; | |
255 | #endif | |
7499d566 NC |
256 | #ifdef ARCH_maxq |
257 | case bfd_arch_maxq: | |
258 | disassemble = print_insn_maxq_little; | |
259 | break; | |
260 | #endif | |
d031aafb NS |
261 | #ifdef ARCH_mt |
262 | case bfd_arch_mt: | |
263 | disassemble = print_insn_mt; | |
ac188222 DB |
264 | break; |
265 | #endif | |
2469cfa2 NC |
266 | #ifdef ARCH_msp430 |
267 | case bfd_arch_msp430: | |
268 | disassemble = print_insn_msp430; | |
269 | break; | |
270 | #endif | |
252b5132 RH |
271 | #ifdef ARCH_ns32k |
272 | case bfd_arch_ns32k: | |
273 | disassemble = print_insn_ns32k; | |
274 | break; | |
275 | #endif | |
276 | #ifdef ARCH_mcore | |
277 | case bfd_arch_mcore: | |
278 | disassemble = print_insn_mcore; | |
279 | break; | |
280 | #endif | |
bd2f2e55 DB |
281 | #ifdef ARCH_mep |
282 | case bfd_arch_mep: | |
283 | disassemble = print_insn_mep; | |
284 | break; | |
285 | #endif | |
252b5132 RH |
286 | #ifdef ARCH_mips |
287 | case bfd_arch_mips: | |
288 | if (bfd_big_endian (abfd)) | |
289 | disassemble = print_insn_big_mips; | |
290 | else | |
291 | disassemble = print_insn_little_mips; | |
292 | break; | |
293 | #endif | |
3c3bdf30 NC |
294 | #ifdef ARCH_mmix |
295 | case bfd_arch_mmix: | |
296 | disassemble = print_insn_mmix; | |
297 | break; | |
298 | #endif | |
252b5132 RH |
299 | #ifdef ARCH_mn10200 |
300 | case bfd_arch_mn10200: | |
301 | disassemble = print_insn_mn10200; | |
302 | break; | |
303 | #endif | |
304 | #ifdef ARCH_mn10300 | |
305 | case bfd_arch_mn10300: | |
306 | disassemble = print_insn_mn10300; | |
307 | break; | |
308 | #endif | |
87e6d782 NC |
309 | #ifdef ARCH_openrisc |
310 | case bfd_arch_openrisc: | |
311 | disassemble = print_insn_openrisc; | |
312 | break; | |
313 | #endif | |
3b16e843 NC |
314 | #ifdef ARCH_or32 |
315 | case bfd_arch_or32: | |
316 | if (bfd_big_endian (abfd)) | |
317 | disassemble = print_insn_big_or32; | |
318 | else | |
319 | disassemble = print_insn_little_or32; | |
320 | break; | |
321 | #endif | |
e135f41b NC |
322 | #ifdef ARCH_pdp11 |
323 | case bfd_arch_pdp11: | |
324 | disassemble = print_insn_pdp11; | |
325 | break; | |
326 | #endif | |
1e608f98 ILT |
327 | #ifdef ARCH_pj |
328 | case bfd_arch_pj: | |
329 | disassemble = print_insn_pj; | |
330 | break; | |
331 | #endif | |
252b5132 RH |
332 | #ifdef ARCH_powerpc |
333 | case bfd_arch_powerpc: | |
334 | if (bfd_big_endian (abfd)) | |
335 | disassemble = print_insn_big_powerpc; | |
336 | else | |
337 | disassemble = print_insn_little_powerpc; | |
338 | break; | |
339 | #endif | |
340 | #ifdef ARCH_rs6000 | |
341 | case bfd_arch_rs6000: | |
39c20e8f | 342 | if (bfd_get_mach (abfd) == bfd_mach_ppc_620) |
7f6d05e8 CP |
343 | disassemble = print_insn_big_powerpc; |
344 | else | |
345 | disassemble = print_insn_rs6000; | |
252b5132 RH |
346 | break; |
347 | #endif | |
a85d7ed0 NC |
348 | #ifdef ARCH_s390 |
349 | case bfd_arch_s390: | |
350 | disassemble = print_insn_s390; | |
351 | break; | |
352 | #endif | |
1c0d3aa6 NC |
353 | #ifdef ARCH_score |
354 | case bfd_arch_score: | |
355 | if (bfd_big_endian (abfd)) | |
356 | disassemble = print_insn_big_score; | |
357 | else | |
358 | disassemble = print_insn_little_score; | |
359 | break; | |
360 | #endif | |
252b5132 RH |
361 | #ifdef ARCH_sh |
362 | case bfd_arch_sh: | |
1c509ca8 | 363 | disassemble = print_insn_sh; |
252b5132 RH |
364 | break; |
365 | #endif | |
366 | #ifdef ARCH_sparc | |
367 | case bfd_arch_sparc: | |
368 | disassemble = print_insn_sparc; | |
369 | break; | |
370 | #endif | |
e9f53129 AM |
371 | #ifdef ARCH_spu |
372 | case bfd_arch_spu: | |
373 | disassemble = print_insn_spu; | |
374 | break; | |
375 | #endif | |
252b5132 RH |
376 | #ifdef ARCH_tic30 |
377 | case bfd_arch_tic30: | |
378 | disassemble = print_insn_tic30; | |
379 | break; | |
380 | #endif | |
026df7c5 NC |
381 | #ifdef ARCH_tic4x |
382 | case bfd_arch_tic4x: | |
383 | disassemble = print_insn_tic4x; | |
384 | break; | |
385 | #endif | |
5c84d377 TW |
386 | #ifdef ARCH_tic54x |
387 | case bfd_arch_tic54x: | |
388 | disassemble = print_insn_tic54x; | |
389 | break; | |
390 | #endif | |
252b5132 RH |
391 | #ifdef ARCH_tic80 |
392 | case bfd_arch_tic80: | |
393 | disassemble = print_insn_tic80; | |
394 | break; | |
395 | #endif | |
396 | #ifdef ARCH_v850 | |
397 | case bfd_arch_v850: | |
398 | disassemble = print_insn_v850; | |
399 | break; | |
400 | #endif | |
401 | #ifdef ARCH_w65 | |
402 | case bfd_arch_w65: | |
403 | disassemble = print_insn_w65; | |
404 | break; | |
405 | #endif | |
93fbbb04 GK |
406 | #ifdef ARCH_xstormy16 |
407 | case bfd_arch_xstormy16: | |
408 | disassemble = print_insn_xstormy16; | |
409 | break; | |
410 | #endif | |
d70c5fc7 NC |
411 | #ifdef ARCH_xc16x |
412 | case bfd_arch_xc16x: | |
413 | disassemble = print_insn_xc16x; | |
414 | break; | |
415 | #endif | |
e0001a05 NC |
416 | #ifdef ARCH_xtensa |
417 | case bfd_arch_xtensa: | |
418 | disassemble = print_insn_xtensa; | |
419 | break; | |
420 | #endif | |
3c9b82ba NC |
421 | #ifdef ARCH_z80 |
422 | case bfd_arch_z80: | |
423 | disassemble = print_insn_z80; | |
424 | break; | |
425 | #endif | |
252b5132 RH |
426 | #ifdef ARCH_z8k |
427 | case bfd_arch_z8k: | |
428 | if (bfd_get_mach(abfd) == bfd_mach_z8001) | |
429 | disassemble = print_insn_z8001; | |
b7ed8fad | 430 | else |
252b5132 RH |
431 | disassemble = print_insn_z8002; |
432 | break; | |
433 | #endif | |
434 | #ifdef ARCH_vax | |
435 | case bfd_arch_vax: | |
436 | disassemble = print_insn_vax; | |
437 | break; | |
fd3c93d5 DB |
438 | #endif |
439 | #ifdef ARCH_frv | |
440 | case bfd_arch_frv: | |
441 | disassemble = print_insn_frv; | |
442 | break; | |
47b1a55a | 443 | #endif |
59b1530d AG |
444 | #ifdef ARCH_moxie |
445 | case bfd_arch_moxie: | |
446 | disassemble = print_insn_moxie; | |
447 | break; | |
448 | #endif | |
47b1a55a SC |
449 | #ifdef ARCH_iq2000 |
450 | case bfd_arch_iq2000: | |
451 | disassemble = print_insn_iq2000; | |
452 | break; | |
49f58d10 JB |
453 | #endif |
454 | #ifdef ARCH_m32c | |
455 | case bfd_arch_m32c: | |
456 | disassemble = print_insn_m32c; | |
457 | break; | |
252b5132 RH |
458 | #endif |
459 | default: | |
460 | return 0; | |
461 | } | |
462 | return disassemble; | |
463 | } | |
94470b23 NC |
464 | |
465 | void | |
9aaaa291 | 466 | disassembler_usage (stream) |
7f32bebc | 467 | FILE * stream ATTRIBUTE_UNUSED; |
94470b23 | 468 | { |
58efb6c0 NC |
469 | #ifdef ARCH_arm |
470 | print_arm_disassembler_options (stream); | |
471 | #endif | |
640c0ccd CD |
472 | #ifdef ARCH_mips |
473 | print_mips_disassembler_options (stream); | |
474 | #endif | |
07dd56a9 NC |
475 | #ifdef ARCH_powerpc |
476 | print_ppc_disassembler_options (stream); | |
477 | #endif | |
f59a29b9 L |
478 | #ifdef ARCH_i386 |
479 | print_i386_disassembler_options (stream); | |
480 | #endif | |
112b7c50 AK |
481 | #ifdef ARCH_s390 |
482 | print_s390_disassembler_options (stream); | |
483 | #endif | |
b7ed8fad | 484 | |
94470b23 NC |
485 | return; |
486 | } | |
22a398e1 NC |
487 | |
488 | void | |
489 | disassemble_init_for_target (struct disassemble_info * info) | |
490 | { | |
491 | if (info == NULL) | |
492 | return; | |
493 | ||
494 | switch (info->arch) | |
495 | { | |
496 | #ifdef ARCH_arm | |
497 | case bfd_arch_arm: | |
498 | info->symbol_is_valid = arm_symbol_is_valid; | |
d99b6465 | 499 | info->disassembler_needs_relocs = TRUE; |
22a398e1 | 500 | break; |
0bcb06d2 AS |
501 | #endif |
502 | #ifdef ARCH_ia64 | |
503 | case bfd_arch_ia64: | |
504 | info->skip_zeroes = 16; | |
505 | break; | |
506 | #endif | |
507 | #ifdef ARCH_tic4x | |
508 | case bfd_arch_tic4x: | |
509 | info->skip_zeroes = 32; | |
fb53f5a8 | 510 | break; |
49f58d10 | 511 | #endif |
bd2f2e55 DB |
512 | #ifdef ARCH_mep |
513 | case bfd_arch_mep: | |
514 | info->skip_zeroes = 256; | |
515 | info->skip_zeroes_at_end = 0; | |
516 | break; | |
517 | #endif | |
49f58d10 JB |
518 | #ifdef ARCH_m32c |
519 | case bfd_arch_m32c: | |
520 | info->endian = BFD_ENDIAN_BIG; | |
fb53f5a8 DB |
521 | if (! info->insn_sets) |
522 | { | |
523 | info->insn_sets = cgen_bitset_create (ISA_MAX); | |
524 | if (info->mach == bfd_mach_m16c) | |
525 | cgen_bitset_set (info->insn_sets, ISA_M16C); | |
526 | else | |
527 | cgen_bitset_set (info->insn_sets, ISA_M32C); | |
528 | } | |
49f58d10 | 529 | break; |
22a398e1 NC |
530 | #endif |
531 | default: | |
532 | break; | |
533 | } | |
534 | } |