Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* Select disassembly routine for specified architecture. |
aef6203b AM |
2 | Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, |
3 | 2004, 2005 Free Software Foundation, Inc. | |
252b5132 | 4 | |
7499d566 NC |
5 | This program is free software; you can redistribute it and/or modify |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
252b5132 | 9 | |
7499d566 NC |
10 | This program is distributed in the hope that it will be useful, |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
252b5132 | 14 | |
7499d566 NC |
15 | You should have received a copy of the GNU General Public License |
16 | along with this program; if not, write to the Free Software | |
f4321104 | 17 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ |
252b5132 | 18 | |
0d8dfecf | 19 | #include "sysdep.h" |
252b5132 RH |
20 | #include "dis-asm.h" |
21 | ||
22 | #ifdef ARCH_all | |
252b5132 RH |
23 | #define ARCH_alpha |
24 | #define ARCH_arc | |
25 | #define ARCH_arm | |
adde6300 | 26 | #define ARCH_avr |
4b7f6baa | 27 | #define ARCH_bfin |
6c95a37f | 28 | #define ARCH_cris |
1fe1f39c | 29 | #define ARCH_crx |
252b5132 RH |
30 | #define ARCH_d10v |
31 | #define ARCH_d30v | |
d172d4ba | 32 | #define ARCH_dlx |
e729279b NC |
33 | #define ARCH_fr30 |
34 | #define ARCH_frv | |
252b5132 RH |
35 | #define ARCH_h8300 |
36 | #define ARCH_h8500 | |
37 | #define ARCH_hppa | |
5b93d8bb | 38 | #define ARCH_i370 |
252b5132 | 39 | #define ARCH_i386 |
9d751335 | 40 | #define ARCH_i860 |
252b5132 | 41 | #define ARCH_i960 |
800eeca4 | 42 | #define ARCH_ia64 |
e729279b NC |
43 | #define ARCH_ip2k |
44 | #define ARCH_iq2000 | |
45 | #define ARCH_m32c | |
252b5132 | 46 | #define ARCH_m32r |
60bcf0fa NC |
47 | #define ARCH_m68hc11 |
48 | #define ARCH_m68hc12 | |
e729279b | 49 | #define ARCH_m68k |
252b5132 | 50 | #define ARCH_m88k |
7499d566 | 51 | #define ARCH_maxq |
252b5132 RH |
52 | #define ARCH_mcore |
53 | #define ARCH_mips | |
3c3bdf30 | 54 | #define ARCH_mmix |
252b5132 RH |
55 | #define ARCH_mn10200 |
56 | #define ARCH_mn10300 | |
ac188222 | 57 | #define ARCH_ms1 |
2469cfa2 | 58 | #define ARCH_msp430 |
252b5132 | 59 | #define ARCH_ns32k |
87e6d782 | 60 | #define ARCH_openrisc |
3b16e843 | 61 | #define ARCH_or32 |
e135f41b | 62 | #define ARCH_pdp11 |
1e608f98 | 63 | #define ARCH_pj |
252b5132 RH |
64 | #define ARCH_powerpc |
65 | #define ARCH_rs6000 | |
a85d7ed0 | 66 | #define ARCH_s390 |
252b5132 RH |
67 | #define ARCH_sh |
68 | #define ARCH_sparc | |
69 | #define ARCH_tic30 | |
026df7c5 | 70 | #define ARCH_tic4x |
5c84d377 | 71 | #define ARCH_tic54x |
252b5132 RH |
72 | #define ARCH_tic80 |
73 | #define ARCH_v850 | |
74 | #define ARCH_vax | |
75 | #define ARCH_w65 | |
93fbbb04 | 76 | #define ARCH_xstormy16 |
e0001a05 | 77 | #define ARCH_xtensa |
3c9b82ba | 78 | #define ARCH_z80 |
252b5132 | 79 | #define ARCH_z8k |
d28847ce | 80 | #define INCLUDE_SHMEDIA |
252b5132 RH |
81 | #endif |
82 | ||
49f58d10 JB |
83 | #ifdef ARCH_m32c |
84 | #include "m32c-desc.h" | |
85 | #endif | |
252b5132 RH |
86 | |
87 | disassembler_ftype | |
88 | disassembler (abfd) | |
89 | bfd *abfd; | |
90 | { | |
91 | enum bfd_architecture a = bfd_get_arch (abfd); | |
92 | disassembler_ftype disassemble; | |
93 | ||
94 | switch (a) | |
95 | { | |
96 | /* If you add a case to this table, also add it to the | |
97 | ARCH_all definition right above this function. */ | |
252b5132 RH |
98 | #ifdef ARCH_alpha |
99 | case bfd_arch_alpha: | |
100 | disassemble = print_insn_alpha; | |
101 | break; | |
102 | #endif | |
103 | #ifdef ARCH_arc | |
104 | case bfd_arch_arc: | |
105 | { | |
0d2bcfaf | 106 | disassemble = arc_get_disassembler (abfd); |
252b5132 RH |
107 | break; |
108 | } | |
109 | #endif | |
110 | #ifdef ARCH_arm | |
111 | case bfd_arch_arm: | |
112 | if (bfd_big_endian (abfd)) | |
113 | disassemble = print_insn_big_arm; | |
114 | else | |
115 | disassemble = print_insn_little_arm; | |
116 | break; | |
117 | #endif | |
adde6300 AM |
118 | #ifdef ARCH_avr |
119 | case bfd_arch_avr: | |
120 | disassemble = print_insn_avr; | |
121 | break; | |
122 | #endif | |
4b7f6baa CM |
123 | #ifdef ARCH_bfin |
124 | case bfd_arch_bfin: | |
125 | disassemble = print_insn_bfin; | |
126 | break; | |
127 | #endif | |
6c95a37f HPN |
128 | #ifdef ARCH_cris |
129 | case bfd_arch_cris: | |
78966507 | 130 | disassemble = cris_get_disassembler (abfd); |
6c95a37f | 131 | break; |
1fe1f39c NC |
132 | #endif |
133 | #ifdef ARCH_crx | |
134 | case bfd_arch_crx: | |
135 | disassemble = print_insn_crx; | |
136 | break; | |
6c95a37f | 137 | #endif |
252b5132 RH |
138 | #ifdef ARCH_d10v |
139 | case bfd_arch_d10v: | |
140 | disassemble = print_insn_d10v; | |
141 | break; | |
142 | #endif | |
143 | #ifdef ARCH_d30v | |
144 | case bfd_arch_d30v: | |
145 | disassemble = print_insn_d30v; | |
146 | break; | |
147 | #endif | |
d172d4ba NC |
148 | #ifdef ARCH_dlx |
149 | case bfd_arch_dlx: | |
150 | /* As far as I know we only handle big-endian DLX objects. */ | |
151 | disassemble = print_insn_dlx; | |
152 | break; | |
153 | #endif | |
252b5132 RH |
154 | #ifdef ARCH_h8300 |
155 | case bfd_arch_h8300: | |
049f8936 NC |
156 | if (bfd_get_mach (abfd) == bfd_mach_h8300h |
157 | || bfd_get_mach (abfd) == bfd_mach_h8300hn) | |
252b5132 | 158 | disassemble = print_insn_h8300h; |
049f8936 | 159 | else if (bfd_get_mach (abfd) == bfd_mach_h8300s |
d43ff6d2 | 160 | || bfd_get_mach (abfd) == bfd_mach_h8300sn |
a53b85e2 AO |
161 | || bfd_get_mach (abfd) == bfd_mach_h8300sx |
162 | || bfd_get_mach (abfd) == bfd_mach_h8300sxn) | |
252b5132 | 163 | disassemble = print_insn_h8300s; |
b7ed8fad | 164 | else |
252b5132 RH |
165 | disassemble = print_insn_h8300; |
166 | break; | |
167 | #endif | |
168 | #ifdef ARCH_h8500 | |
169 | case bfd_arch_h8500: | |
170 | disassemble = print_insn_h8500; | |
171 | break; | |
172 | #endif | |
173 | #ifdef ARCH_hppa | |
174 | case bfd_arch_hppa: | |
175 | disassemble = print_insn_hppa; | |
176 | break; | |
177 | #endif | |
5b93d8bb AM |
178 | #ifdef ARCH_i370 |
179 | case bfd_arch_i370: | |
180 | disassemble = print_insn_i370; | |
181 | break; | |
182 | #endif | |
252b5132 RH |
183 | #ifdef ARCH_i386 |
184 | case bfd_arch_i386: | |
e396998b | 185 | disassemble = print_insn_i386; |
252b5132 RH |
186 | break; |
187 | #endif | |
9d751335 JE |
188 | #ifdef ARCH_i860 |
189 | case bfd_arch_i860: | |
190 | disassemble = print_insn_i860; | |
191 | break; | |
192 | #endif | |
252b5132 RH |
193 | #ifdef ARCH_i960 |
194 | case bfd_arch_i960: | |
195 | disassemble = print_insn_i960; | |
196 | break; | |
197 | #endif | |
800eeca4 JW |
198 | #ifdef ARCH_ia64 |
199 | case bfd_arch_ia64: | |
200 | disassemble = print_insn_ia64; | |
201 | break; | |
202 | #endif | |
a40cbfa3 NC |
203 | #ifdef ARCH_ip2k |
204 | case bfd_arch_ip2k: | |
205 | disassemble = print_insn_ip2k; | |
206 | break; | |
207 | #endif | |
252b5132 RH |
208 | #ifdef ARCH_fr30 |
209 | case bfd_arch_fr30: | |
210 | disassemble = print_insn_fr30; | |
211 | break; | |
212 | #endif | |
213 | #ifdef ARCH_m32r | |
214 | case bfd_arch_m32r: | |
215 | disassemble = print_insn_m32r; | |
216 | break; | |
217 | #endif | |
60bcf0fa NC |
218 | #if defined(ARCH_m68hc11) || defined(ARCH_m68hc12) |
219 | case bfd_arch_m68hc11: | |
220 | disassemble = print_insn_m68hc11; | |
221 | break; | |
222 | case bfd_arch_m68hc12: | |
223 | disassemble = print_insn_m68hc12; | |
224 | break; | |
225 | #endif | |
252b5132 RH |
226 | #ifdef ARCH_m68k |
227 | case bfd_arch_m68k: | |
228 | disassemble = print_insn_m68k; | |
229 | break; | |
230 | #endif | |
231 | #ifdef ARCH_m88k | |
232 | case bfd_arch_m88k: | |
233 | disassemble = print_insn_m88k; | |
234 | break; | |
235 | #endif | |
7499d566 NC |
236 | #ifdef ARCH_maxq |
237 | case bfd_arch_maxq: | |
238 | disassemble = print_insn_maxq_little; | |
239 | break; | |
240 | #endif | |
ac188222 DB |
241 | #ifdef ARCH_ms1 |
242 | case bfd_arch_ms1: | |
243 | disassemble = print_insn_ms1; | |
244 | break; | |
245 | #endif | |
2469cfa2 NC |
246 | #ifdef ARCH_msp430 |
247 | case bfd_arch_msp430: | |
248 | disassemble = print_insn_msp430; | |
249 | break; | |
250 | #endif | |
252b5132 RH |
251 | #ifdef ARCH_ns32k |
252 | case bfd_arch_ns32k: | |
253 | disassemble = print_insn_ns32k; | |
254 | break; | |
255 | #endif | |
256 | #ifdef ARCH_mcore | |
257 | case bfd_arch_mcore: | |
258 | disassemble = print_insn_mcore; | |
259 | break; | |
260 | #endif | |
261 | #ifdef ARCH_mips | |
262 | case bfd_arch_mips: | |
263 | if (bfd_big_endian (abfd)) | |
264 | disassemble = print_insn_big_mips; | |
265 | else | |
266 | disassemble = print_insn_little_mips; | |
267 | break; | |
268 | #endif | |
3c3bdf30 NC |
269 | #ifdef ARCH_mmix |
270 | case bfd_arch_mmix: | |
271 | disassemble = print_insn_mmix; | |
272 | break; | |
273 | #endif | |
252b5132 RH |
274 | #ifdef ARCH_mn10200 |
275 | case bfd_arch_mn10200: | |
276 | disassemble = print_insn_mn10200; | |
277 | break; | |
278 | #endif | |
279 | #ifdef ARCH_mn10300 | |
280 | case bfd_arch_mn10300: | |
281 | disassemble = print_insn_mn10300; | |
282 | break; | |
283 | #endif | |
87e6d782 NC |
284 | #ifdef ARCH_openrisc |
285 | case bfd_arch_openrisc: | |
286 | disassemble = print_insn_openrisc; | |
287 | break; | |
288 | #endif | |
3b16e843 NC |
289 | #ifdef ARCH_or32 |
290 | case bfd_arch_or32: | |
291 | if (bfd_big_endian (abfd)) | |
292 | disassemble = print_insn_big_or32; | |
293 | else | |
294 | disassemble = print_insn_little_or32; | |
295 | break; | |
296 | #endif | |
e135f41b NC |
297 | #ifdef ARCH_pdp11 |
298 | case bfd_arch_pdp11: | |
299 | disassemble = print_insn_pdp11; | |
300 | break; | |
301 | #endif | |
1e608f98 ILT |
302 | #ifdef ARCH_pj |
303 | case bfd_arch_pj: | |
304 | disassemble = print_insn_pj; | |
305 | break; | |
306 | #endif | |
252b5132 RH |
307 | #ifdef ARCH_powerpc |
308 | case bfd_arch_powerpc: | |
309 | if (bfd_big_endian (abfd)) | |
310 | disassemble = print_insn_big_powerpc; | |
311 | else | |
312 | disassemble = print_insn_little_powerpc; | |
313 | break; | |
314 | #endif | |
315 | #ifdef ARCH_rs6000 | |
316 | case bfd_arch_rs6000: | |
39c20e8f | 317 | if (bfd_get_mach (abfd) == bfd_mach_ppc_620) |
7f6d05e8 CP |
318 | disassemble = print_insn_big_powerpc; |
319 | else | |
320 | disassemble = print_insn_rs6000; | |
252b5132 RH |
321 | break; |
322 | #endif | |
a85d7ed0 NC |
323 | #ifdef ARCH_s390 |
324 | case bfd_arch_s390: | |
325 | disassemble = print_insn_s390; | |
326 | break; | |
327 | #endif | |
252b5132 RH |
328 | #ifdef ARCH_sh |
329 | case bfd_arch_sh: | |
1c509ca8 | 330 | disassemble = print_insn_sh; |
252b5132 RH |
331 | break; |
332 | #endif | |
333 | #ifdef ARCH_sparc | |
334 | case bfd_arch_sparc: | |
335 | disassemble = print_insn_sparc; | |
336 | break; | |
337 | #endif | |
338 | #ifdef ARCH_tic30 | |
339 | case bfd_arch_tic30: | |
340 | disassemble = print_insn_tic30; | |
341 | break; | |
342 | #endif | |
026df7c5 NC |
343 | #ifdef ARCH_tic4x |
344 | case bfd_arch_tic4x: | |
345 | disassemble = print_insn_tic4x; | |
346 | break; | |
347 | #endif | |
5c84d377 TW |
348 | #ifdef ARCH_tic54x |
349 | case bfd_arch_tic54x: | |
350 | disassemble = print_insn_tic54x; | |
351 | break; | |
352 | #endif | |
252b5132 RH |
353 | #ifdef ARCH_tic80 |
354 | case bfd_arch_tic80: | |
355 | disassemble = print_insn_tic80; | |
356 | break; | |
357 | #endif | |
358 | #ifdef ARCH_v850 | |
359 | case bfd_arch_v850: | |
360 | disassemble = print_insn_v850; | |
361 | break; | |
362 | #endif | |
363 | #ifdef ARCH_w65 | |
364 | case bfd_arch_w65: | |
365 | disassemble = print_insn_w65; | |
366 | break; | |
367 | #endif | |
93fbbb04 GK |
368 | #ifdef ARCH_xstormy16 |
369 | case bfd_arch_xstormy16: | |
370 | disassemble = print_insn_xstormy16; | |
371 | break; | |
372 | #endif | |
e0001a05 NC |
373 | #ifdef ARCH_xtensa |
374 | case bfd_arch_xtensa: | |
375 | disassemble = print_insn_xtensa; | |
376 | break; | |
377 | #endif | |
3c9b82ba NC |
378 | #ifdef ARCH_z80 |
379 | case bfd_arch_z80: | |
380 | disassemble = print_insn_z80; | |
381 | break; | |
382 | #endif | |
252b5132 RH |
383 | #ifdef ARCH_z8k |
384 | case bfd_arch_z8k: | |
385 | if (bfd_get_mach(abfd) == bfd_mach_z8001) | |
386 | disassemble = print_insn_z8001; | |
b7ed8fad | 387 | else |
252b5132 RH |
388 | disassemble = print_insn_z8002; |
389 | break; | |
390 | #endif | |
391 | #ifdef ARCH_vax | |
392 | case bfd_arch_vax: | |
393 | disassemble = print_insn_vax; | |
394 | break; | |
fd3c93d5 DB |
395 | #endif |
396 | #ifdef ARCH_frv | |
397 | case bfd_arch_frv: | |
398 | disassemble = print_insn_frv; | |
399 | break; | |
47b1a55a SC |
400 | #endif |
401 | #ifdef ARCH_iq2000 | |
402 | case bfd_arch_iq2000: | |
403 | disassemble = print_insn_iq2000; | |
404 | break; | |
49f58d10 JB |
405 | #endif |
406 | #ifdef ARCH_m32c | |
407 | case bfd_arch_m32c: | |
408 | disassemble = print_insn_m32c; | |
409 | break; | |
252b5132 RH |
410 | #endif |
411 | default: | |
412 | return 0; | |
413 | } | |
414 | return disassemble; | |
415 | } | |
94470b23 NC |
416 | |
417 | void | |
9aaaa291 | 418 | disassembler_usage (stream) |
7f32bebc | 419 | FILE * stream ATTRIBUTE_UNUSED; |
94470b23 | 420 | { |
58efb6c0 NC |
421 | #ifdef ARCH_arm |
422 | print_arm_disassembler_options (stream); | |
423 | #endif | |
640c0ccd CD |
424 | #ifdef ARCH_mips |
425 | print_mips_disassembler_options (stream); | |
426 | #endif | |
07dd56a9 NC |
427 | #ifdef ARCH_powerpc |
428 | print_ppc_disassembler_options (stream); | |
429 | #endif | |
b7ed8fad | 430 | |
94470b23 NC |
431 | return; |
432 | } | |
22a398e1 NC |
433 | |
434 | void | |
435 | disassemble_init_for_target (struct disassemble_info * info) | |
436 | { | |
437 | if (info == NULL) | |
438 | return; | |
439 | ||
440 | switch (info->arch) | |
441 | { | |
442 | #ifdef ARCH_arm | |
443 | case bfd_arch_arm: | |
444 | info->symbol_is_valid = arm_symbol_is_valid; | |
445 | break; | |
0bcb06d2 AS |
446 | #endif |
447 | #ifdef ARCH_ia64 | |
448 | case bfd_arch_ia64: | |
449 | info->skip_zeroes = 16; | |
450 | break; | |
451 | #endif | |
452 | #ifdef ARCH_tic4x | |
453 | case bfd_arch_tic4x: | |
454 | info->skip_zeroes = 32; | |
49f58d10 JB |
455 | #endif |
456 | #ifdef ARCH_m32c | |
457 | case bfd_arch_m32c: | |
458 | info->endian = BFD_ENDIAN_BIG; | |
459 | if (info->mach == bfd_mach_m16c) | |
760c0f6a | 460 | info->insn_sets = 1 << ISA_M16C; |
49f58d10 | 461 | else |
760c0f6a | 462 | info->insn_sets = 1 << ISA_M32C; |
49f58d10 | 463 | break; |
22a398e1 NC |
464 | #endif |
465 | default: | |
466 | break; | |
467 | } | |
468 | } |