Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* Select disassembly routine for specified architecture. |
6f2750fe | 2 | Copyright (C) 1994-2016 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 NC |
4 | This file is part of the GNU opcodes library. |
5 | ||
6 | This library is free software; you can redistribute it and/or modify | |
7499d566 | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 | 8 | the Free Software Foundation; either version 3 of the License, or |
7499d566 | 9 | (at your option) any later version. |
252b5132 | 10 | |
7499d566 NC |
11 | This program is distributed in the hope that it will be useful, |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
252b5132 | 15 | |
7499d566 NC |
16 | You should have received a copy of the GNU General Public License |
17 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
252b5132 | 20 | |
0d8dfecf | 21 | #include "sysdep.h" |
252b5132 RH |
22 | #include "dis-asm.h" |
23 | ||
24 | #ifdef ARCH_all | |
a06ea964 | 25 | #define ARCH_aarch64 |
252b5132 RH |
26 | #define ARCH_alpha |
27 | #define ARCH_arc | |
28 | #define ARCH_arm | |
adde6300 | 29 | #define ARCH_avr |
4b7f6baa | 30 | #define ARCH_bfin |
3d3d428f | 31 | #define ARCH_cr16 |
6c95a37f | 32 | #define ARCH_cris |
1fe1f39c | 33 | #define ARCH_crx |
252b5132 RH |
34 | #define ARCH_d10v |
35 | #define ARCH_d30v | |
d172d4ba | 36 | #define ARCH_dlx |
56b13185 | 37 | #define ARCH_epiphany |
e729279b NC |
38 | #define ARCH_fr30 |
39 | #define ARCH_frv | |
3f8107ab | 40 | #define ARCH_ft32 |
252b5132 RH |
41 | #define ARCH_h8300 |
42 | #define ARCH_h8500 | |
43 | #define ARCH_hppa | |
5b93d8bb | 44 | #define ARCH_i370 |
252b5132 | 45 | #define ARCH_i386 |
9d751335 | 46 | #define ARCH_i860 |
252b5132 | 47 | #define ARCH_i960 |
800eeca4 | 48 | #define ARCH_ia64 |
e729279b NC |
49 | #define ARCH_ip2k |
50 | #define ARCH_iq2000 | |
84e94c90 | 51 | #define ARCH_lm32 |
e729279b | 52 | #define ARCH_m32c |
252b5132 | 53 | #define ARCH_m32r |
60bcf0fa NC |
54 | #define ARCH_m68hc11 |
55 | #define ARCH_m68hc12 | |
e729279b | 56 | #define ARCH_m68k |
252b5132 RH |
57 | #define ARCH_m88k |
58 | #define ARCH_mcore | |
bd2f2e55 | 59 | #define ARCH_mep |
a3c62988 | 60 | #define ARCH_metag |
7ba29e2a | 61 | #define ARCH_microblaze |
252b5132 | 62 | #define ARCH_mips |
3c3bdf30 | 63 | #define ARCH_mmix |
252b5132 RH |
64 | #define ARCH_mn10200 |
65 | #define ARCH_mn10300 | |
59b1530d | 66 | #define ARCH_moxie |
d031aafb | 67 | #define ARCH_mt |
2469cfa2 | 68 | #define ARCH_msp430 |
35c08157 | 69 | #define ARCH_nds32 |
36591ba1 | 70 | #define ARCH_nios2 |
252b5132 | 71 | #define ARCH_ns32k |
73589c9d | 72 | #define ARCH_or1k |
e135f41b | 73 | #define ARCH_pdp11 |
1e608f98 | 74 | #define ARCH_pj |
252b5132 | 75 | #define ARCH_powerpc |
11146849 | 76 | #define ARCH_pru |
252b5132 | 77 | #define ARCH_rs6000 |
99c513f6 | 78 | #define ARCH_rl78 |
c7927a3c | 79 | #define ARCH_rx |
a85d7ed0 | 80 | #define ARCH_s390 |
1c0d3aa6 | 81 | #define ARCH_score |
252b5132 RH |
82 | #define ARCH_sh |
83 | #define ARCH_sparc | |
e9f53129 | 84 | #define ARCH_spu |
252b5132 | 85 | #define ARCH_tic30 |
026df7c5 | 86 | #define ARCH_tic4x |
5c84d377 | 87 | #define ARCH_tic54x |
40b36596 | 88 | #define ARCH_tic6x |
252b5132 | 89 | #define ARCH_tic80 |
aa137e4d NC |
90 | #define ARCH_tilegx |
91 | #define ARCH_tilepro | |
252b5132 RH |
92 | #define ARCH_v850 |
93 | #define ARCH_vax | |
1945cfa5 | 94 | #define ARCH_visium |
252b5132 | 95 | #define ARCH_w65 |
93fbbb04 | 96 | #define ARCH_xstormy16 |
d70c5fc7 | 97 | #define ARCH_xc16x |
f6c1a2d5 | 98 | #define ARCH_xgate |
e0001a05 | 99 | #define ARCH_xtensa |
3c9b82ba | 100 | #define ARCH_z80 |
252b5132 | 101 | #define ARCH_z8k |
d28847ce | 102 | #define INCLUDE_SHMEDIA |
252b5132 RH |
103 | #endif |
104 | ||
49f58d10 JB |
105 | #ifdef ARCH_m32c |
106 | #include "m32c-desc.h" | |
107 | #endif | |
252b5132 RH |
108 | |
109 | disassembler_ftype | |
e6c7cdec | 110 | disassembler (bfd *abfd) |
252b5132 RH |
111 | { |
112 | enum bfd_architecture a = bfd_get_arch (abfd); | |
113 | disassembler_ftype disassemble; | |
114 | ||
115 | switch (a) | |
116 | { | |
117 | /* If you add a case to this table, also add it to the | |
118 | ARCH_all definition right above this function. */ | |
a06ea964 NC |
119 | #ifdef ARCH_aarch64 |
120 | case bfd_arch_aarch64: | |
121 | disassemble = print_insn_aarch64; | |
122 | break; | |
123 | #endif | |
252b5132 RH |
124 | #ifdef ARCH_alpha |
125 | case bfd_arch_alpha: | |
126 | disassemble = print_insn_alpha; | |
127 | break; | |
128 | #endif | |
129 | #ifdef ARCH_arc | |
130 | case bfd_arch_arc: | |
6ca4eb77 AM |
131 | disassemble = arc_get_disassembler (abfd); |
132 | break; | |
252b5132 RH |
133 | #endif |
134 | #ifdef ARCH_arm | |
135 | case bfd_arch_arm: | |
136 | if (bfd_big_endian (abfd)) | |
137 | disassemble = print_insn_big_arm; | |
138 | else | |
139 | disassemble = print_insn_little_arm; | |
140 | break; | |
141 | #endif | |
adde6300 AM |
142 | #ifdef ARCH_avr |
143 | case bfd_arch_avr: | |
144 | disassemble = print_insn_avr; | |
145 | break; | |
146 | #endif | |
4b7f6baa CM |
147 | #ifdef ARCH_bfin |
148 | case bfd_arch_bfin: | |
149 | disassemble = print_insn_bfin; | |
150 | break; | |
151 | #endif | |
3d3d428f NC |
152 | #ifdef ARCH_cr16 |
153 | case bfd_arch_cr16: | |
154 | disassemble = print_insn_cr16; | |
155 | break; | |
156 | #endif | |
6c95a37f HPN |
157 | #ifdef ARCH_cris |
158 | case bfd_arch_cris: | |
78966507 | 159 | disassemble = cris_get_disassembler (abfd); |
6c95a37f | 160 | break; |
1fe1f39c NC |
161 | #endif |
162 | #ifdef ARCH_crx | |
163 | case bfd_arch_crx: | |
164 | disassemble = print_insn_crx; | |
165 | break; | |
6c95a37f | 166 | #endif |
252b5132 RH |
167 | #ifdef ARCH_d10v |
168 | case bfd_arch_d10v: | |
169 | disassemble = print_insn_d10v; | |
170 | break; | |
171 | #endif | |
172 | #ifdef ARCH_d30v | |
173 | case bfd_arch_d30v: | |
174 | disassemble = print_insn_d30v; | |
175 | break; | |
176 | #endif | |
d172d4ba NC |
177 | #ifdef ARCH_dlx |
178 | case bfd_arch_dlx: | |
179 | /* As far as I know we only handle big-endian DLX objects. */ | |
180 | disassemble = print_insn_dlx; | |
181 | break; | |
182 | #endif | |
252b5132 RH |
183 | #ifdef ARCH_h8300 |
184 | case bfd_arch_h8300: | |
049f8936 NC |
185 | if (bfd_get_mach (abfd) == bfd_mach_h8300h |
186 | || bfd_get_mach (abfd) == bfd_mach_h8300hn) | |
252b5132 | 187 | disassemble = print_insn_h8300h; |
049f8936 | 188 | else if (bfd_get_mach (abfd) == bfd_mach_h8300s |
d43ff6d2 | 189 | || bfd_get_mach (abfd) == bfd_mach_h8300sn |
a53b85e2 AO |
190 | || bfd_get_mach (abfd) == bfd_mach_h8300sx |
191 | || bfd_get_mach (abfd) == bfd_mach_h8300sxn) | |
252b5132 | 192 | disassemble = print_insn_h8300s; |
b7ed8fad | 193 | else |
252b5132 RH |
194 | disassemble = print_insn_h8300; |
195 | break; | |
196 | #endif | |
197 | #ifdef ARCH_h8500 | |
198 | case bfd_arch_h8500: | |
199 | disassemble = print_insn_h8500; | |
200 | break; | |
201 | #endif | |
202 | #ifdef ARCH_hppa | |
203 | case bfd_arch_hppa: | |
204 | disassemble = print_insn_hppa; | |
205 | break; | |
206 | #endif | |
5b93d8bb AM |
207 | #ifdef ARCH_i370 |
208 | case bfd_arch_i370: | |
209 | disassemble = print_insn_i370; | |
210 | break; | |
211 | #endif | |
252b5132 RH |
212 | #ifdef ARCH_i386 |
213 | case bfd_arch_i386: | |
7b6d09fb | 214 | case bfd_arch_iamcu: |
8a9036a4 | 215 | case bfd_arch_l1om: |
7a9068fe | 216 | case bfd_arch_k1om: |
e396998b | 217 | disassemble = print_insn_i386; |
252b5132 RH |
218 | break; |
219 | #endif | |
9d751335 JE |
220 | #ifdef ARCH_i860 |
221 | case bfd_arch_i860: | |
222 | disassemble = print_insn_i860; | |
223 | break; | |
224 | #endif | |
252b5132 RH |
225 | #ifdef ARCH_i960 |
226 | case bfd_arch_i960: | |
227 | disassemble = print_insn_i960; | |
228 | break; | |
229 | #endif | |
800eeca4 JW |
230 | #ifdef ARCH_ia64 |
231 | case bfd_arch_ia64: | |
232 | disassemble = print_insn_ia64; | |
233 | break; | |
234 | #endif | |
a40cbfa3 NC |
235 | #ifdef ARCH_ip2k |
236 | case bfd_arch_ip2k: | |
237 | disassemble = print_insn_ip2k; | |
238 | break; | |
239 | #endif | |
cfb8c092 NC |
240 | #ifdef ARCH_epiphany |
241 | case bfd_arch_epiphany: | |
242 | disassemble = print_insn_epiphany; | |
243 | break; | |
244 | #endif | |
252b5132 RH |
245 | #ifdef ARCH_fr30 |
246 | case bfd_arch_fr30: | |
247 | disassemble = print_insn_fr30; | |
248 | break; | |
249 | #endif | |
84e94c90 NC |
250 | #ifdef ARCH_lm32 |
251 | case bfd_arch_lm32: | |
252 | disassemble = print_insn_lm32; | |
253 | break; | |
254 | #endif | |
252b5132 RH |
255 | #ifdef ARCH_m32r |
256 | case bfd_arch_m32r: | |
257 | disassemble = print_insn_m32r; | |
258 | break; | |
259 | #endif | |
6927f982 NC |
260 | #if defined(ARCH_m68hc11) || defined(ARCH_m68hc12) \ |
261 | || defined(ARCH_9s12x) || defined(ARCH_m9s12xg) | |
60bcf0fa NC |
262 | case bfd_arch_m68hc11: |
263 | disassemble = print_insn_m68hc11; | |
264 | break; | |
265 | case bfd_arch_m68hc12: | |
266 | disassemble = print_insn_m68hc12; | |
267 | break; | |
6927f982 NC |
268 | case bfd_arch_m9s12x: |
269 | disassemble = print_insn_m9s12x; | |
270 | break; | |
271 | case bfd_arch_m9s12xg: | |
272 | disassemble = print_insn_m9s12xg; | |
273 | break; | |
60bcf0fa | 274 | #endif |
252b5132 RH |
275 | #ifdef ARCH_m68k |
276 | case bfd_arch_m68k: | |
277 | disassemble = print_insn_m68k; | |
278 | break; | |
279 | #endif | |
280 | #ifdef ARCH_m88k | |
281 | case bfd_arch_m88k: | |
282 | disassemble = print_insn_m88k; | |
283 | break; | |
284 | #endif | |
d031aafb NS |
285 | #ifdef ARCH_mt |
286 | case bfd_arch_mt: | |
287 | disassemble = print_insn_mt; | |
ac188222 DB |
288 | break; |
289 | #endif | |
7ba29e2a NC |
290 | #ifdef ARCH_microblaze |
291 | case bfd_arch_microblaze: | |
292 | disassemble = print_insn_microblaze; | |
293 | break; | |
294 | #endif | |
2469cfa2 NC |
295 | #ifdef ARCH_msp430 |
296 | case bfd_arch_msp430: | |
297 | disassemble = print_insn_msp430; | |
298 | break; | |
299 | #endif | |
35c08157 KLC |
300 | #ifdef ARCH_nds32 |
301 | case bfd_arch_nds32: | |
302 | disassemble = print_insn_nds32; | |
303 | break; | |
304 | #endif | |
252b5132 RH |
305 | #ifdef ARCH_ns32k |
306 | case bfd_arch_ns32k: | |
307 | disassemble = print_insn_ns32k; | |
308 | break; | |
309 | #endif | |
310 | #ifdef ARCH_mcore | |
311 | case bfd_arch_mcore: | |
312 | disassemble = print_insn_mcore; | |
313 | break; | |
314 | #endif | |
bd2f2e55 DB |
315 | #ifdef ARCH_mep |
316 | case bfd_arch_mep: | |
317 | disassemble = print_insn_mep; | |
318 | break; | |
319 | #endif | |
a3c62988 NC |
320 | #ifdef ARCH_metag |
321 | case bfd_arch_metag: | |
322 | disassemble = print_insn_metag; | |
323 | break; | |
324 | #endif | |
252b5132 RH |
325 | #ifdef ARCH_mips |
326 | case bfd_arch_mips: | |
327 | if (bfd_big_endian (abfd)) | |
328 | disassemble = print_insn_big_mips; | |
329 | else | |
330 | disassemble = print_insn_little_mips; | |
331 | break; | |
332 | #endif | |
3c3bdf30 NC |
333 | #ifdef ARCH_mmix |
334 | case bfd_arch_mmix: | |
335 | disassemble = print_insn_mmix; | |
336 | break; | |
337 | #endif | |
252b5132 RH |
338 | #ifdef ARCH_mn10200 |
339 | case bfd_arch_mn10200: | |
340 | disassemble = print_insn_mn10200; | |
341 | break; | |
342 | #endif | |
343 | #ifdef ARCH_mn10300 | |
344 | case bfd_arch_mn10300: | |
345 | disassemble = print_insn_mn10300; | |
346 | break; | |
347 | #endif | |
36591ba1 SL |
348 | #ifdef ARCH_nios2 |
349 | case bfd_arch_nios2: | |
350 | if (bfd_big_endian (abfd)) | |
351 | disassemble = print_insn_big_nios2; | |
352 | else | |
353 | disassemble = print_insn_little_nios2; | |
354 | break; | |
355 | #endif | |
73589c9d CS |
356 | #ifdef ARCH_or1k |
357 | case bfd_arch_or1k: | |
358 | disassemble = print_insn_or1k; | |
3b16e843 NC |
359 | break; |
360 | #endif | |
e135f41b NC |
361 | #ifdef ARCH_pdp11 |
362 | case bfd_arch_pdp11: | |
363 | disassemble = print_insn_pdp11; | |
364 | break; | |
365 | #endif | |
1e608f98 ILT |
366 | #ifdef ARCH_pj |
367 | case bfd_arch_pj: | |
368 | disassemble = print_insn_pj; | |
369 | break; | |
370 | #endif | |
252b5132 RH |
371 | #ifdef ARCH_powerpc |
372 | case bfd_arch_powerpc: | |
373 | if (bfd_big_endian (abfd)) | |
374 | disassemble = print_insn_big_powerpc; | |
375 | else | |
376 | disassemble = print_insn_little_powerpc; | |
377 | break; | |
378 | #endif | |
11146849 DD |
379 | #ifdef ARCH_pru |
380 | case bfd_arch_pru: | |
381 | disassemble = print_insn_pru; | |
382 | break; | |
383 | #endif | |
e23eba97 NC |
384 | #ifdef ARCH_riscv |
385 | case bfd_arch_riscv: | |
386 | disassemble = print_insn_riscv; | |
ae4c0df4 | 387 | break; |
e23eba97 | 388 | #endif |
252b5132 RH |
389 | #ifdef ARCH_rs6000 |
390 | case bfd_arch_rs6000: | |
39c20e8f | 391 | if (bfd_get_mach (abfd) == bfd_mach_ppc_620) |
7f6d05e8 CP |
392 | disassemble = print_insn_big_powerpc; |
393 | else | |
394 | disassemble = print_insn_rs6000; | |
252b5132 RH |
395 | break; |
396 | #endif | |
99c513f6 DD |
397 | #ifdef ARCH_rl78 |
398 | case bfd_arch_rl78: | |
0952813b | 399 | disassemble = rl78_get_disassembler (abfd); |
99c513f6 DD |
400 | break; |
401 | #endif | |
c7927a3c NC |
402 | #ifdef ARCH_rx |
403 | case bfd_arch_rx: | |
404 | disassemble = print_insn_rx; | |
405 | break; | |
406 | #endif | |
a85d7ed0 NC |
407 | #ifdef ARCH_s390 |
408 | case bfd_arch_s390: | |
409 | disassemble = print_insn_s390; | |
410 | break; | |
411 | #endif | |
1c0d3aa6 NC |
412 | #ifdef ARCH_score |
413 | case bfd_arch_score: | |
414 | if (bfd_big_endian (abfd)) | |
6ca4eb77 | 415 | disassemble = print_insn_big_score; |
1c0d3aa6 | 416 | else |
6ca4eb77 | 417 | disassemble = print_insn_little_score; |
1c0d3aa6 NC |
418 | break; |
419 | #endif | |
252b5132 RH |
420 | #ifdef ARCH_sh |
421 | case bfd_arch_sh: | |
1c509ca8 | 422 | disassemble = print_insn_sh; |
252b5132 RH |
423 | break; |
424 | #endif | |
425 | #ifdef ARCH_sparc | |
426 | case bfd_arch_sparc: | |
427 | disassemble = print_insn_sparc; | |
428 | break; | |
429 | #endif | |
e9f53129 AM |
430 | #ifdef ARCH_spu |
431 | case bfd_arch_spu: | |
432 | disassemble = print_insn_spu; | |
433 | break; | |
434 | #endif | |
252b5132 RH |
435 | #ifdef ARCH_tic30 |
436 | case bfd_arch_tic30: | |
437 | disassemble = print_insn_tic30; | |
438 | break; | |
439 | #endif | |
026df7c5 NC |
440 | #ifdef ARCH_tic4x |
441 | case bfd_arch_tic4x: | |
442 | disassemble = print_insn_tic4x; | |
443 | break; | |
444 | #endif | |
5c84d377 TW |
445 | #ifdef ARCH_tic54x |
446 | case bfd_arch_tic54x: | |
447 | disassemble = print_insn_tic54x; | |
448 | break; | |
449 | #endif | |
40b36596 JM |
450 | #ifdef ARCH_tic6x |
451 | case bfd_arch_tic6x: | |
452 | disassemble = print_insn_tic6x; | |
453 | break; | |
454 | #endif | |
252b5132 RH |
455 | #ifdef ARCH_tic80 |
456 | case bfd_arch_tic80: | |
457 | disassemble = print_insn_tic80; | |
458 | break; | |
459 | #endif | |
3f8107ab AM |
460 | #ifdef ARCH_ft32 |
461 | case bfd_arch_ft32: | |
462 | disassemble = print_insn_ft32; | |
463 | break; | |
464 | #endif | |
252b5132 RH |
465 | #ifdef ARCH_v850 |
466 | case bfd_arch_v850: | |
de863c74 | 467 | case bfd_arch_v850_rh850: |
252b5132 RH |
468 | disassemble = print_insn_v850; |
469 | break; | |
470 | #endif | |
471 | #ifdef ARCH_w65 | |
472 | case bfd_arch_w65: | |
473 | disassemble = print_insn_w65; | |
474 | break; | |
475 | #endif | |
f6c1a2d5 NC |
476 | #ifdef ARCH_xgate |
477 | case bfd_arch_xgate: | |
478 | disassemble = print_insn_xgate; | |
479 | break; | |
480 | #endif | |
93fbbb04 GK |
481 | #ifdef ARCH_xstormy16 |
482 | case bfd_arch_xstormy16: | |
483 | disassemble = print_insn_xstormy16; | |
484 | break; | |
485 | #endif | |
d70c5fc7 NC |
486 | #ifdef ARCH_xc16x |
487 | case bfd_arch_xc16x: | |
488 | disassemble = print_insn_xc16x; | |
489 | break; | |
490 | #endif | |
e0001a05 NC |
491 | #ifdef ARCH_xtensa |
492 | case bfd_arch_xtensa: | |
493 | disassemble = print_insn_xtensa; | |
494 | break; | |
495 | #endif | |
3c9b82ba NC |
496 | #ifdef ARCH_z80 |
497 | case bfd_arch_z80: | |
498 | disassemble = print_insn_z80; | |
499 | break; | |
500 | #endif | |
252b5132 RH |
501 | #ifdef ARCH_z8k |
502 | case bfd_arch_z8k: | |
503 | if (bfd_get_mach(abfd) == bfd_mach_z8001) | |
504 | disassemble = print_insn_z8001; | |
b7ed8fad | 505 | else |
252b5132 RH |
506 | disassemble = print_insn_z8002; |
507 | break; | |
508 | #endif | |
509 | #ifdef ARCH_vax | |
510 | case bfd_arch_vax: | |
511 | disassemble = print_insn_vax; | |
512 | break; | |
fd3c93d5 | 513 | #endif |
1945cfa5 EB |
514 | #ifdef ARCH_visium |
515 | case bfd_arch_visium: | |
516 | disassemble = print_insn_visium; | |
517 | break; | |
518 | #endif | |
fd3c93d5 DB |
519 | #ifdef ARCH_frv |
520 | case bfd_arch_frv: | |
521 | disassemble = print_insn_frv; | |
522 | break; | |
47b1a55a | 523 | #endif |
59b1530d AG |
524 | #ifdef ARCH_moxie |
525 | case bfd_arch_moxie: | |
526 | disassemble = print_insn_moxie; | |
527 | break; | |
528 | #endif | |
47b1a55a SC |
529 | #ifdef ARCH_iq2000 |
530 | case bfd_arch_iq2000: | |
531 | disassemble = print_insn_iq2000; | |
532 | break; | |
49f58d10 JB |
533 | #endif |
534 | #ifdef ARCH_m32c | |
535 | case bfd_arch_m32c: | |
536 | disassemble = print_insn_m32c; | |
537 | break; | |
aa137e4d NC |
538 | #endif |
539 | #ifdef ARCH_tilegx | |
540 | case bfd_arch_tilegx: | |
541 | disassemble = print_insn_tilegx; | |
542 | break; | |
543 | #endif | |
544 | #ifdef ARCH_tilepro | |
545 | case bfd_arch_tilepro: | |
546 | disassemble = print_insn_tilepro; | |
547 | break; | |
252b5132 RH |
548 | #endif |
549 | default: | |
550 | return 0; | |
551 | } | |
552 | return disassemble; | |
553 | } | |
94470b23 NC |
554 | |
555 | void | |
e6c7cdec | 556 | disassembler_usage (FILE *stream ATTRIBUTE_UNUSED) |
94470b23 | 557 | { |
a06ea964 NC |
558 | #ifdef ARCH_aarch64 |
559 | print_aarch64_disassembler_options (stream); | |
560 | #endif | |
37fd5ef3 CZ |
561 | #ifdef ARCH_arc |
562 | print_arc_disassembler_options (stream); | |
563 | #endif | |
58efb6c0 NC |
564 | #ifdef ARCH_arm |
565 | print_arm_disassembler_options (stream); | |
566 | #endif | |
640c0ccd CD |
567 | #ifdef ARCH_mips |
568 | print_mips_disassembler_options (stream); | |
569 | #endif | |
07dd56a9 NC |
570 | #ifdef ARCH_powerpc |
571 | print_ppc_disassembler_options (stream); | |
572 | #endif | |
e23eba97 NC |
573 | #ifdef ARCH_riscv |
574 | print_riscv_disassembler_options (stream); | |
575 | #endif | |
f59a29b9 L |
576 | #ifdef ARCH_i386 |
577 | print_i386_disassembler_options (stream); | |
578 | #endif | |
112b7c50 AK |
579 | #ifdef ARCH_s390 |
580 | print_s390_disassembler_options (stream); | |
581 | #endif | |
b7ed8fad | 582 | |
94470b23 NC |
583 | return; |
584 | } | |
22a398e1 NC |
585 | |
586 | void | |
587 | disassemble_init_for_target (struct disassemble_info * info) | |
588 | { | |
589 | if (info == NULL) | |
590 | return; | |
591 | ||
592 | switch (info->arch) | |
593 | { | |
a06ea964 NC |
594 | #ifdef ARCH_aarch64 |
595 | case bfd_arch_aarch64: | |
596 | info->symbol_is_valid = aarch64_symbol_is_valid; | |
597 | info->disassembler_needs_relocs = TRUE; | |
598 | break; | |
599 | #endif | |
22a398e1 NC |
600 | #ifdef ARCH_arm |
601 | case bfd_arch_arm: | |
602 | info->symbol_is_valid = arm_symbol_is_valid; | |
d99b6465 | 603 | info->disassembler_needs_relocs = TRUE; |
22a398e1 | 604 | break; |
0bcb06d2 AS |
605 | #endif |
606 | #ifdef ARCH_ia64 | |
607 | case bfd_arch_ia64: | |
608 | info->skip_zeroes = 16; | |
609 | break; | |
610 | #endif | |
611 | #ifdef ARCH_tic4x | |
612 | case bfd_arch_tic4x: | |
613 | info->skip_zeroes = 32; | |
fb53f5a8 | 614 | break; |
49f58d10 | 615 | #endif |
bd2f2e55 DB |
616 | #ifdef ARCH_mep |
617 | case bfd_arch_mep: | |
618 | info->skip_zeroes = 256; | |
619 | info->skip_zeroes_at_end = 0; | |
620 | break; | |
621 | #endif | |
a3c62988 NC |
622 | #ifdef ARCH_metag |
623 | case bfd_arch_metag: | |
624 | info->disassembler_needs_relocs = TRUE; | |
625 | break; | |
626 | #endif | |
49f58d10 JB |
627 | #ifdef ARCH_m32c |
628 | case bfd_arch_m32c: | |
6ca4eb77 AM |
629 | /* This processor in fact is little endian. The value set here |
630 | reflects the way opcodes are written in the cgen description. */ | |
49f58d10 | 631 | info->endian = BFD_ENDIAN_BIG; |
fb53f5a8 DB |
632 | if (! info->insn_sets) |
633 | { | |
634 | info->insn_sets = cgen_bitset_create (ISA_MAX); | |
635 | if (info->mach == bfd_mach_m16c) | |
636 | cgen_bitset_set (info->insn_sets, ISA_M16C); | |
637 | else | |
638 | cgen_bitset_set (info->insn_sets, ISA_M32C); | |
639 | } | |
49f58d10 | 640 | break; |
b240011a AM |
641 | #endif |
642 | #ifdef ARCH_powerpc | |
643 | case bfd_arch_powerpc: | |
644 | #endif | |
645 | #ifdef ARCH_rs6000 | |
646 | case bfd_arch_rs6000: | |
647 | #endif | |
648 | #if defined (ARCH_powerpc) || defined (ARCH_rs6000) | |
649 | disassemble_init_powerpc (info); | |
650 | break; | |
22a398e1 NC |
651 | #endif |
652 | default: | |
653 | break; | |
654 | } | |
655 | } |