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2076-02-02 H.J. Lu <hongjiu.lu@intel.com>
[deliverable/binutils-gdb.git] / opcodes / disassemble.c
CommitLineData
252b5132 1/* Select disassembly routine for specified architecture.
aef6203b 2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
1c0d3aa6 3 2004, 2005, 2006 Free Software Foundation, Inc.
252b5132 4
7499d566
NC		 5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
252b5132 9
7499d566
NC		 10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
252b5132 14
7499d566
NC		 15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
f4321104 17 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
252b5132 18
0d8dfecf 19#include "sysdep.h"
252b5132
RH		 20#include "dis-asm.h"
21
22#ifdef ARCH_all
252b5132
RH		 23#define ARCH_alpha
24#define ARCH_arc
25#define ARCH_arm
adde6300 26#define ARCH_avr
4b7f6baa 27#define ARCH_bfin
6c95a37f 28#define ARCH_cris
1fe1f39c 29#define ARCH_crx
252b5132
RH		 30#define ARCH_d10v
31#define ARCH_d30v
d172d4ba 32#define ARCH_dlx
e729279b
NC		 33#define ARCH_fr30
34#define ARCH_frv
252b5132
RH		 35#define ARCH_h8300
36#define ARCH_h8500
37#define ARCH_hppa
5b93d8bb 38#define ARCH_i370
252b5132 39#define ARCH_i386
9d751335 40#define ARCH_i860
252b5132 41#define ARCH_i960
800eeca4 42#define ARCH_ia64
e729279b
NC		 43#define ARCH_ip2k
44#define ARCH_iq2000
45#define ARCH_m32c
252b5132 46#define ARCH_m32r
60bcf0fa
NC		 47#define ARCH_m68hc11
48#define ARCH_m68hc12
e729279b 49#define ARCH_m68k
252b5132 50#define ARCH_m88k
7499d566 51#define ARCH_maxq
252b5132
RH		 52#define ARCH_mcore
53#define ARCH_mips
3c3bdf30 54#define ARCH_mmix
252b5132
RH		 55#define ARCH_mn10200
56#define ARCH_mn10300
d031aafb 57#define ARCH_mt
2469cfa2 58#define ARCH_msp430
252b5132 59#define ARCH_ns32k
87e6d782 60#define ARCH_openrisc
3b16e843 61#define ARCH_or32
e135f41b 62#define ARCH_pdp11
1e608f98 63#define ARCH_pj
252b5132
RH		 64#define ARCH_powerpc
65#define ARCH_rs6000
a85d7ed0 66#define ARCH_s390
1c0d3aa6 67#define ARCH_score
252b5132
RH		 68#define ARCH_sh
69#define ARCH_sparc
e9f53129 70#define ARCH_spu
252b5132 71#define ARCH_tic30
026df7c5 72#define ARCH_tic4x
5c84d377 73#define ARCH_tic54x
252b5132
RH		 74#define ARCH_tic80
75#define ARCH_v850
76#define ARCH_vax
77#define ARCH_w65
93fbbb04 78#define ARCH_xstormy16
d70c5fc7 79#define ARCH_xc16x
e0001a05 80#define ARCH_xtensa
3c9b82ba 81#define ARCH_z80
252b5132 82#define ARCH_z8k
d28847ce 83#define INCLUDE_SHMEDIA
252b5132
RH		 84#endif
85
49f58d10
JB		 86#ifdef ARCH_m32c
87#include "m32c-desc.h"
88#endif
252b5132
RH		 89
90disassembler_ftype
91disassembler (abfd)
92 bfd *abfd;
93{
94 enum bfd_architecture a = bfd_get_arch (abfd);
95 disassembler_ftype disassemble;
96
97 switch (a)
98 {
99 /* If you add a case to this table, also add it to the
100 ARCH_all definition right above this function. */
252b5132
RH		 101#ifdef ARCH_alpha
102 case bfd_arch_alpha:
103 disassemble = print_insn_alpha;
104 break;
105#endif
106#ifdef ARCH_arc
107 case bfd_arch_arc:
108 {
0d2bcfaf 109 disassemble = arc_get_disassembler (abfd);
252b5132
RH		 110 break;
111 }
112#endif
113#ifdef ARCH_arm
114 case bfd_arch_arm:
115 if (bfd_big_endian (abfd))
116 disassemble = print_insn_big_arm;
117 else
118 disassemble = print_insn_little_arm;
119 break;
120#endif
adde6300
AM		 121#ifdef ARCH_avr
122 case bfd_arch_avr:
123 disassemble = print_insn_avr;
124 break;
125#endif
4b7f6baa
CM		 126#ifdef ARCH_bfin
127 case bfd_arch_bfin:
128 disassemble = print_insn_bfin;
129 break;
130#endif
6c95a37f
HPN		 131#ifdef ARCH_cris
132 case bfd_arch_cris:
78966507 133 disassemble = cris_get_disassembler (abfd);
6c95a37f 134 break;
1fe1f39c
NC		 135#endif
136#ifdef ARCH_crx
137 case bfd_arch_crx:
138 disassemble = print_insn_crx;
139 break;
6c95a37f 140#endif
252b5132
RH		 141#ifdef ARCH_d10v
142 case bfd_arch_d10v:
143 disassemble = print_insn_d10v;
144 break;
145#endif
146#ifdef ARCH_d30v
147 case bfd_arch_d30v:
148 disassemble = print_insn_d30v;
149 break;
150#endif
d172d4ba
NC		 151#ifdef ARCH_dlx
152 case bfd_arch_dlx:
153 /* As far as I know we only handle big-endian DLX objects. */
154 disassemble = print_insn_dlx;
155 break;
156#endif
252b5132
RH		 157#ifdef ARCH_h8300
158 case bfd_arch_h8300:
049f8936
NC		 159 if (bfd_get_mach (abfd) == bfd_mach_h8300h
160 || bfd_get_mach (abfd) == bfd_mach_h8300hn)
252b5132 161 disassemble = print_insn_h8300h;
049f8936 162 else if (bfd_get_mach (abfd) == bfd_mach_h8300s
d43ff6d2 163 || bfd_get_mach (abfd) == bfd_mach_h8300sn
a53b85e2
AO		 164 || bfd_get_mach (abfd) == bfd_mach_h8300sx
165 || bfd_get_mach (abfd) == bfd_mach_h8300sxn)
252b5132 166 disassemble = print_insn_h8300s;
b7ed8fad 167 else
252b5132
RH		 168 disassemble = print_insn_h8300;
169 break;
170#endif
171#ifdef ARCH_h8500
172 case bfd_arch_h8500:
173 disassemble = print_insn_h8500;
174 break;
175#endif
176#ifdef ARCH_hppa
177 case bfd_arch_hppa:
178 disassemble = print_insn_hppa;
179 break;
180#endif
5b93d8bb
AM		 181#ifdef ARCH_i370
182 case bfd_arch_i370:
183 disassemble = print_insn_i370;
184 break;
185#endif
252b5132
RH		 186#ifdef ARCH_i386
187 case bfd_arch_i386:
e396998b 188 disassemble = print_insn_i386;
252b5132
RH		 189 break;
190#endif
9d751335
JE		 191#ifdef ARCH_i860
192 case bfd_arch_i860:
193 disassemble = print_insn_i860;
194 break;
195#endif
252b5132
RH		 196#ifdef ARCH_i960
197 case bfd_arch_i960:
198 disassemble = print_insn_i960;
199 break;
200#endif
800eeca4
JW		 201#ifdef ARCH_ia64
202 case bfd_arch_ia64:
203 disassemble = print_insn_ia64;
204 break;
205#endif
a40cbfa3
NC		 206#ifdef ARCH_ip2k
207 case bfd_arch_ip2k:
208 disassemble = print_insn_ip2k;
209 break;
210#endif
252b5132
RH		 211#ifdef ARCH_fr30
212 case bfd_arch_fr30:
213 disassemble = print_insn_fr30;
214 break;
215#endif
216#ifdef ARCH_m32r
217 case bfd_arch_m32r:
218 disassemble = print_insn_m32r;
219 break;
220#endif
60bcf0fa
NC		 221#if defined(ARCH_m68hc11) || defined(ARCH_m68hc12)
222 case bfd_arch_m68hc11:
223 disassemble = print_insn_m68hc11;
224 break;
225 case bfd_arch_m68hc12:
226 disassemble = print_insn_m68hc12;
227 break;
228#endif
252b5132
RH		 229#ifdef ARCH_m68k
230 case bfd_arch_m68k:
231 disassemble = print_insn_m68k;
232 break;
233#endif
234#ifdef ARCH_m88k
235 case bfd_arch_m88k:
236 disassemble = print_insn_m88k;
237 break;
238#endif
7499d566
NC		 239#ifdef ARCH_maxq
240 case bfd_arch_maxq:
241 disassemble = print_insn_maxq_little;
242 break;
243#endif
d031aafb
NS		 244#ifdef ARCH_mt
245 case bfd_arch_mt:
246 disassemble = print_insn_mt;
ac188222
DB		 247 break;
248#endif
2469cfa2
NC		 249#ifdef ARCH_msp430
250 case bfd_arch_msp430:
251 disassemble = print_insn_msp430;
252 break;
253#endif
252b5132
RH		 254#ifdef ARCH_ns32k
255 case bfd_arch_ns32k:
256 disassemble = print_insn_ns32k;
257 break;
258#endif
259#ifdef ARCH_mcore
260 case bfd_arch_mcore:
261 disassemble = print_insn_mcore;
262 break;
263#endif
264#ifdef ARCH_mips
265 case bfd_arch_mips:
266 if (bfd_big_endian (abfd))
267 disassemble = print_insn_big_mips;
268 else
269 disassemble = print_insn_little_mips;
270 break;
271#endif
3c3bdf30
NC		 272#ifdef ARCH_mmix
273 case bfd_arch_mmix:
274 disassemble = print_insn_mmix;
275 break;
276#endif
252b5132
RH		 277#ifdef ARCH_mn10200
278 case bfd_arch_mn10200:
279 disassemble = print_insn_mn10200;
280 break;
281#endif
282#ifdef ARCH_mn10300
283 case bfd_arch_mn10300:
284 disassemble = print_insn_mn10300;
285 break;
286#endif
87e6d782
NC		 287#ifdef ARCH_openrisc
288 case bfd_arch_openrisc:
289 disassemble = print_insn_openrisc;
290 break;
291#endif
3b16e843
NC		 292#ifdef ARCH_or32
293 case bfd_arch_or32:
294 if (bfd_big_endian (abfd))
295 disassemble = print_insn_big_or32;
296 else
297 disassemble = print_insn_little_or32;
298 break;
299#endif
e135f41b
NC		 300#ifdef ARCH_pdp11
301 case bfd_arch_pdp11:
302 disassemble = print_insn_pdp11;
303 break;
304#endif
1e608f98
ILT		 305#ifdef ARCH_pj
306 case bfd_arch_pj:
307 disassemble = print_insn_pj;
308 break;
309#endif
252b5132
RH		 310#ifdef ARCH_powerpc
311 case bfd_arch_powerpc:
312 if (bfd_big_endian (abfd))
313 disassemble = print_insn_big_powerpc;
314 else
315 disassemble = print_insn_little_powerpc;
316 break;
317#endif
318#ifdef ARCH_rs6000
319 case bfd_arch_rs6000:
39c20e8f 320 if (bfd_get_mach (abfd) == bfd_mach_ppc_620)
7f6d05e8
CP		 321 disassemble = print_insn_big_powerpc;
322 else
323 disassemble = print_insn_rs6000;
252b5132
RH		 324 break;
325#endif
a85d7ed0
NC		 326#ifdef ARCH_s390
327 case bfd_arch_s390:
328 disassemble = print_insn_s390;
329 break;
330#endif
1c0d3aa6
NC		 331#ifdef ARCH_score
332 case bfd_arch_score:
333 if (bfd_big_endian (abfd))
334 disassemble = print_insn_big_score;
335 else
336 disassemble = print_insn_little_score;
337 break;
338#endif
252b5132
RH		 339#ifdef ARCH_sh
340 case bfd_arch_sh:
1c509ca8 341 disassemble = print_insn_sh;
252b5132
RH		 342 break;
343#endif
344#ifdef ARCH_sparc
345 case bfd_arch_sparc:
346 disassemble = print_insn_sparc;
347 break;
348#endif
e9f53129
AM		 349#ifdef ARCH_spu
350 case bfd_arch_spu:
351 disassemble = print_insn_spu;
352 break;
353#endif
252b5132
RH		 354#ifdef ARCH_tic30
355 case bfd_arch_tic30:
356 disassemble = print_insn_tic30;
357 break;
358#endif
026df7c5
NC		 359#ifdef ARCH_tic4x
360 case bfd_arch_tic4x:
361 disassemble = print_insn_tic4x;
362 break;
363#endif
5c84d377
TW		 364#ifdef ARCH_tic54x
365 case bfd_arch_tic54x:
366 disassemble = print_insn_tic54x;
367 break;
368#endif
252b5132
RH		 369#ifdef ARCH_tic80
370 case bfd_arch_tic80:
371 disassemble = print_insn_tic80;
372 break;
373#endif
374#ifdef ARCH_v850
375 case bfd_arch_v850:
376 disassemble = print_insn_v850;
377 break;
378#endif
379#ifdef ARCH_w65
380 case bfd_arch_w65:
381 disassemble = print_insn_w65;
382 break;
383#endif
93fbbb04
GK		 384#ifdef ARCH_xstormy16
385 case bfd_arch_xstormy16:
386 disassemble = print_insn_xstormy16;
387 break;
388#endif
d70c5fc7
NC		 389#ifdef ARCH_xc16x
390 case bfd_arch_xc16x:
391 disassemble = print_insn_xc16x;
392 break;
393#endif
e0001a05
NC		 394#ifdef ARCH_xtensa
395 case bfd_arch_xtensa:
396 disassemble = print_insn_xtensa;
397 break;
398#endif
3c9b82ba
NC		 399#ifdef ARCH_z80
400 case bfd_arch_z80:
401 disassemble = print_insn_z80;
402 break;
403#endif
252b5132
RH		 404#ifdef ARCH_z8k
405 case bfd_arch_z8k:
406 if (bfd_get_mach(abfd) == bfd_mach_z8001)
407 disassemble = print_insn_z8001;
b7ed8fad 408 else
252b5132
RH		 409 disassemble = print_insn_z8002;
410 break;
411#endif
412#ifdef ARCH_vax
413 case bfd_arch_vax:
414 disassemble = print_insn_vax;
415 break;
fd3c93d5
DB		 416#endif
417#ifdef ARCH_frv
418 case bfd_arch_frv:
419 disassemble = print_insn_frv;
420 break;
47b1a55a
SC		 421#endif
422#ifdef ARCH_iq2000
423 case bfd_arch_iq2000:
424 disassemble = print_insn_iq2000;
425 break;
49f58d10
JB		 426#endif
427#ifdef ARCH_m32c
428 case bfd_arch_m32c:
429 disassemble = print_insn_m32c;
430 break;
252b5132
RH		 431#endif
432 default:
433 return 0;
434 }
435 return disassemble;
436}
94470b23
NC		 437
438void
9aaaa291 439disassembler_usage (stream)
7f32bebc 440 FILE * stream ATTRIBUTE_UNUSED;
94470b23 441{
58efb6c0
NC		 442#ifdef ARCH_arm
443 print_arm_disassembler_options (stream);
444#endif
640c0ccd
CD		 445#ifdef ARCH_mips
446 print_mips_disassembler_options (stream);
447#endif
07dd56a9
NC		 448#ifdef ARCH_powerpc
449 print_ppc_disassembler_options (stream);
450#endif
b7ed8fad 451
94470b23
NC		 452 return;
453}
22a398e1
NC		 454
455void
456disassemble_init_for_target (struct disassemble_info * info)
457{
458 if (info == NULL)
459 return;
460
461 switch (info->arch)
462 {
463#ifdef ARCH_arm
464 case bfd_arch_arm:
465 info->symbol_is_valid = arm_symbol_is_valid;
d99b6465 466 info->disassembler_needs_relocs = TRUE;
22a398e1 467 break;
0bcb06d2
AS		 468#endif
469#ifdef ARCH_ia64
470 case bfd_arch_ia64:
471 info->skip_zeroes = 16;
472 break;
473#endif
474#ifdef ARCH_tic4x
475 case bfd_arch_tic4x:
476 info->skip_zeroes = 32;
fb53f5a8 477 break;
49f58d10
JB		 478#endif
479#ifdef ARCH_m32c
480 case bfd_arch_m32c:
481 info->endian = BFD_ENDIAN_BIG;
fb53f5a8
DB		 482 if (! info->insn_sets)
483 {
484 info->insn_sets = cgen_bitset_create (ISA_MAX);
485 if (info->mach == bfd_mach_m16c)
486 cgen_bitset_set (info->insn_sets, ISA_M16C);
487 else
488 cgen_bitset_set (info->insn_sets, ISA_M32C);
489 }
49f58d10 490 break;
22a398e1
NC		 491#endif
492 default:
493 break;
494 }
495}
GDB Binutils - Deliverables
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