Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* Select disassembly routine for specified architecture. |
aef6203b | 2 | Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, |
b240011a AM |
3 | 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012 |
4 | Free Software Foundation, Inc. | |
252b5132 | 5 | |
9b201bb5 NC |
6 | This file is part of the GNU opcodes library. |
7 | ||
8 | This library is free software; you can redistribute it and/or modify | |
7499d566 | 9 | it under the terms of the GNU General Public License as published by |
9b201bb5 | 10 | the Free Software Foundation; either version 3 of the License, or |
7499d566 | 11 | (at your option) any later version. |
252b5132 | 12 | |
7499d566 NC |
13 | This program is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
252b5132 | 17 | |
7499d566 NC |
18 | You should have received a copy of the GNU General Public License |
19 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
20 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
21 | MA 02110-1301, USA. */ | |
252b5132 | 22 | |
0d8dfecf | 23 | #include "sysdep.h" |
252b5132 RH |
24 | #include "dis-asm.h" |
25 | ||
26 | #ifdef ARCH_all | |
252b5132 RH |
27 | #define ARCH_alpha |
28 | #define ARCH_arc | |
29 | #define ARCH_arm | |
adde6300 | 30 | #define ARCH_avr |
4b7f6baa | 31 | #define ARCH_bfin |
3d3d428f | 32 | #define ARCH_cr16 |
6c95a37f | 33 | #define ARCH_cris |
1fe1f39c | 34 | #define ARCH_crx |
252b5132 RH |
35 | #define ARCH_d10v |
36 | #define ARCH_d30v | |
d172d4ba | 37 | #define ARCH_dlx |
56b13185 | 38 | #define ARCH_epiphany |
e729279b NC |
39 | #define ARCH_fr30 |
40 | #define ARCH_frv | |
252b5132 RH |
41 | #define ARCH_h8300 |
42 | #define ARCH_h8500 | |
43 | #define ARCH_hppa | |
5b93d8bb | 44 | #define ARCH_i370 |
252b5132 | 45 | #define ARCH_i386 |
9d751335 | 46 | #define ARCH_i860 |
252b5132 | 47 | #define ARCH_i960 |
800eeca4 | 48 | #define ARCH_ia64 |
e729279b NC |
49 | #define ARCH_ip2k |
50 | #define ARCH_iq2000 | |
84e94c90 | 51 | #define ARCH_lm32 |
e729279b | 52 | #define ARCH_m32c |
252b5132 | 53 | #define ARCH_m32r |
60bcf0fa NC |
54 | #define ARCH_m68hc11 |
55 | #define ARCH_m68hc12 | |
e729279b | 56 | #define ARCH_m68k |
252b5132 RH |
57 | #define ARCH_m88k |
58 | #define ARCH_mcore | |
bd2f2e55 | 59 | #define ARCH_mep |
7ba29e2a | 60 | #define ARCH_microblaze |
252b5132 | 61 | #define ARCH_mips |
3c3bdf30 | 62 | #define ARCH_mmix |
252b5132 RH |
63 | #define ARCH_mn10200 |
64 | #define ARCH_mn10300 | |
59b1530d | 65 | #define ARCH_moxie |
d031aafb | 66 | #define ARCH_mt |
2469cfa2 | 67 | #define ARCH_msp430 |
252b5132 | 68 | #define ARCH_ns32k |
87e6d782 | 69 | #define ARCH_openrisc |
3b16e843 | 70 | #define ARCH_or32 |
e135f41b | 71 | #define ARCH_pdp11 |
1e608f98 | 72 | #define ARCH_pj |
252b5132 RH |
73 | #define ARCH_powerpc |
74 | #define ARCH_rs6000 | |
99c513f6 | 75 | #define ARCH_rl78 |
c7927a3c | 76 | #define ARCH_rx |
a85d7ed0 | 77 | #define ARCH_s390 |
1c0d3aa6 | 78 | #define ARCH_score |
252b5132 RH |
79 | #define ARCH_sh |
80 | #define ARCH_sparc | |
e9f53129 | 81 | #define ARCH_spu |
252b5132 | 82 | #define ARCH_tic30 |
026df7c5 | 83 | #define ARCH_tic4x |
5c84d377 | 84 | #define ARCH_tic54x |
40b36596 | 85 | #define ARCH_tic6x |
252b5132 | 86 | #define ARCH_tic80 |
aa137e4d NC |
87 | #define ARCH_tilegx |
88 | #define ARCH_tilepro | |
252b5132 RH |
89 | #define ARCH_v850 |
90 | #define ARCH_vax | |
91 | #define ARCH_w65 | |
93fbbb04 | 92 | #define ARCH_xstormy16 |
d70c5fc7 | 93 | #define ARCH_xc16x |
f6c1a2d5 | 94 | #define ARCH_xgate |
e0001a05 | 95 | #define ARCH_xtensa |
3c9b82ba | 96 | #define ARCH_z80 |
252b5132 | 97 | #define ARCH_z8k |
d28847ce | 98 | #define INCLUDE_SHMEDIA |
252b5132 RH |
99 | #endif |
100 | ||
49f58d10 JB |
101 | #ifdef ARCH_m32c |
102 | #include "m32c-desc.h" | |
103 | #endif | |
252b5132 RH |
104 | |
105 | disassembler_ftype | |
106 | disassembler (abfd) | |
107 | bfd *abfd; | |
108 | { | |
109 | enum bfd_architecture a = bfd_get_arch (abfd); | |
110 | disassembler_ftype disassemble; | |
111 | ||
112 | switch (a) | |
113 | { | |
114 | /* If you add a case to this table, also add it to the | |
115 | ARCH_all definition right above this function. */ | |
252b5132 RH |
116 | #ifdef ARCH_alpha |
117 | case bfd_arch_alpha: | |
118 | disassemble = print_insn_alpha; | |
119 | break; | |
120 | #endif | |
121 | #ifdef ARCH_arc | |
122 | case bfd_arch_arc: | |
6ca4eb77 AM |
123 | disassemble = arc_get_disassembler (abfd); |
124 | break; | |
252b5132 RH |
125 | #endif |
126 | #ifdef ARCH_arm | |
127 | case bfd_arch_arm: | |
128 | if (bfd_big_endian (abfd)) | |
129 | disassemble = print_insn_big_arm; | |
130 | else | |
131 | disassemble = print_insn_little_arm; | |
132 | break; | |
133 | #endif | |
adde6300 AM |
134 | #ifdef ARCH_avr |
135 | case bfd_arch_avr: | |
136 | disassemble = print_insn_avr; | |
137 | break; | |
138 | #endif | |
4b7f6baa CM |
139 | #ifdef ARCH_bfin |
140 | case bfd_arch_bfin: | |
141 | disassemble = print_insn_bfin; | |
142 | break; | |
143 | #endif | |
3d3d428f NC |
144 | #ifdef ARCH_cr16 |
145 | case bfd_arch_cr16: | |
146 | disassemble = print_insn_cr16; | |
147 | break; | |
148 | #endif | |
6c95a37f HPN |
149 | #ifdef ARCH_cris |
150 | case bfd_arch_cris: | |
78966507 | 151 | disassemble = cris_get_disassembler (abfd); |
6c95a37f | 152 | break; |
1fe1f39c NC |
153 | #endif |
154 | #ifdef ARCH_crx | |
155 | case bfd_arch_crx: | |
156 | disassemble = print_insn_crx; | |
157 | break; | |
6c95a37f | 158 | #endif |
252b5132 RH |
159 | #ifdef ARCH_d10v |
160 | case bfd_arch_d10v: | |
161 | disassemble = print_insn_d10v; | |
162 | break; | |
163 | #endif | |
164 | #ifdef ARCH_d30v | |
165 | case bfd_arch_d30v: | |
166 | disassemble = print_insn_d30v; | |
167 | break; | |
168 | #endif | |
d172d4ba NC |
169 | #ifdef ARCH_dlx |
170 | case bfd_arch_dlx: | |
171 | /* As far as I know we only handle big-endian DLX objects. */ | |
172 | disassemble = print_insn_dlx; | |
173 | break; | |
174 | #endif | |
252b5132 RH |
175 | #ifdef ARCH_h8300 |
176 | case bfd_arch_h8300: | |
049f8936 NC |
177 | if (bfd_get_mach (abfd) == bfd_mach_h8300h |
178 | || bfd_get_mach (abfd) == bfd_mach_h8300hn) | |
252b5132 | 179 | disassemble = print_insn_h8300h; |
049f8936 | 180 | else if (bfd_get_mach (abfd) == bfd_mach_h8300s |
d43ff6d2 | 181 | || bfd_get_mach (abfd) == bfd_mach_h8300sn |
a53b85e2 AO |
182 | || bfd_get_mach (abfd) == bfd_mach_h8300sx |
183 | || bfd_get_mach (abfd) == bfd_mach_h8300sxn) | |
252b5132 | 184 | disassemble = print_insn_h8300s; |
b7ed8fad | 185 | else |
252b5132 RH |
186 | disassemble = print_insn_h8300; |
187 | break; | |
188 | #endif | |
189 | #ifdef ARCH_h8500 | |
190 | case bfd_arch_h8500: | |
191 | disassemble = print_insn_h8500; | |
192 | break; | |
193 | #endif | |
194 | #ifdef ARCH_hppa | |
195 | case bfd_arch_hppa: | |
196 | disassemble = print_insn_hppa; | |
197 | break; | |
198 | #endif | |
5b93d8bb AM |
199 | #ifdef ARCH_i370 |
200 | case bfd_arch_i370: | |
201 | disassemble = print_insn_i370; | |
202 | break; | |
203 | #endif | |
252b5132 RH |
204 | #ifdef ARCH_i386 |
205 | case bfd_arch_i386: | |
8a9036a4 | 206 | case bfd_arch_l1om: |
7a9068fe | 207 | case bfd_arch_k1om: |
e396998b | 208 | disassemble = print_insn_i386; |
252b5132 RH |
209 | break; |
210 | #endif | |
9d751335 JE |
211 | #ifdef ARCH_i860 |
212 | case bfd_arch_i860: | |
213 | disassemble = print_insn_i860; | |
214 | break; | |
215 | #endif | |
252b5132 RH |
216 | #ifdef ARCH_i960 |
217 | case bfd_arch_i960: | |
218 | disassemble = print_insn_i960; | |
219 | break; | |
220 | #endif | |
800eeca4 JW |
221 | #ifdef ARCH_ia64 |
222 | case bfd_arch_ia64: | |
223 | disassemble = print_insn_ia64; | |
224 | break; | |
225 | #endif | |
a40cbfa3 NC |
226 | #ifdef ARCH_ip2k |
227 | case bfd_arch_ip2k: | |
228 | disassemble = print_insn_ip2k; | |
229 | break; | |
230 | #endif | |
cfb8c092 NC |
231 | #ifdef ARCH_epiphany |
232 | case bfd_arch_epiphany: | |
233 | disassemble = print_insn_epiphany; | |
234 | break; | |
235 | #endif | |
252b5132 RH |
236 | #ifdef ARCH_fr30 |
237 | case bfd_arch_fr30: | |
238 | disassemble = print_insn_fr30; | |
239 | break; | |
240 | #endif | |
84e94c90 NC |
241 | #ifdef ARCH_lm32 |
242 | case bfd_arch_lm32: | |
243 | disassemble = print_insn_lm32; | |
244 | break; | |
245 | #endif | |
252b5132 RH |
246 | #ifdef ARCH_m32r |
247 | case bfd_arch_m32r: | |
248 | disassemble = print_insn_m32r; | |
249 | break; | |
250 | #endif | |
6927f982 NC |
251 | #if defined(ARCH_m68hc11) || defined(ARCH_m68hc12) \ |
252 | || defined(ARCH_9s12x) || defined(ARCH_m9s12xg) | |
60bcf0fa NC |
253 | case bfd_arch_m68hc11: |
254 | disassemble = print_insn_m68hc11; | |
255 | break; | |
256 | case bfd_arch_m68hc12: | |
257 | disassemble = print_insn_m68hc12; | |
258 | break; | |
6927f982 NC |
259 | case bfd_arch_m9s12x: |
260 | disassemble = print_insn_m9s12x; | |
261 | break; | |
262 | case bfd_arch_m9s12xg: | |
263 | disassemble = print_insn_m9s12xg; | |
264 | break; | |
60bcf0fa | 265 | #endif |
252b5132 RH |
266 | #ifdef ARCH_m68k |
267 | case bfd_arch_m68k: | |
268 | disassemble = print_insn_m68k; | |
269 | break; | |
270 | #endif | |
271 | #ifdef ARCH_m88k | |
272 | case bfd_arch_m88k: | |
273 | disassemble = print_insn_m88k; | |
274 | break; | |
275 | #endif | |
d031aafb NS |
276 | #ifdef ARCH_mt |
277 | case bfd_arch_mt: | |
278 | disassemble = print_insn_mt; | |
ac188222 DB |
279 | break; |
280 | #endif | |
7ba29e2a NC |
281 | #ifdef ARCH_microblaze |
282 | case bfd_arch_microblaze: | |
283 | disassemble = print_insn_microblaze; | |
284 | break; | |
285 | #endif | |
2469cfa2 NC |
286 | #ifdef ARCH_msp430 |
287 | case bfd_arch_msp430: | |
288 | disassemble = print_insn_msp430; | |
289 | break; | |
290 | #endif | |
252b5132 RH |
291 | #ifdef ARCH_ns32k |
292 | case bfd_arch_ns32k: | |
293 | disassemble = print_insn_ns32k; | |
294 | break; | |
295 | #endif | |
296 | #ifdef ARCH_mcore | |
297 | case bfd_arch_mcore: | |
298 | disassemble = print_insn_mcore; | |
299 | break; | |
300 | #endif | |
bd2f2e55 DB |
301 | #ifdef ARCH_mep |
302 | case bfd_arch_mep: | |
303 | disassemble = print_insn_mep; | |
304 | break; | |
305 | #endif | |
252b5132 RH |
306 | #ifdef ARCH_mips |
307 | case bfd_arch_mips: | |
308 | if (bfd_big_endian (abfd)) | |
309 | disassemble = print_insn_big_mips; | |
310 | else | |
311 | disassemble = print_insn_little_mips; | |
312 | break; | |
313 | #endif | |
3c3bdf30 NC |
314 | #ifdef ARCH_mmix |
315 | case bfd_arch_mmix: | |
316 | disassemble = print_insn_mmix; | |
317 | break; | |
318 | #endif | |
252b5132 RH |
319 | #ifdef ARCH_mn10200 |
320 | case bfd_arch_mn10200: | |
321 | disassemble = print_insn_mn10200; | |
322 | break; | |
323 | #endif | |
324 | #ifdef ARCH_mn10300 | |
325 | case bfd_arch_mn10300: | |
326 | disassemble = print_insn_mn10300; | |
327 | break; | |
328 | #endif | |
87e6d782 NC |
329 | #ifdef ARCH_openrisc |
330 | case bfd_arch_openrisc: | |
331 | disassemble = print_insn_openrisc; | |
332 | break; | |
333 | #endif | |
3b16e843 NC |
334 | #ifdef ARCH_or32 |
335 | case bfd_arch_or32: | |
336 | if (bfd_big_endian (abfd)) | |
6ca4eb77 | 337 | disassemble = print_insn_big_or32; |
3b16e843 | 338 | else |
6ca4eb77 | 339 | disassemble = print_insn_little_or32; |
3b16e843 NC |
340 | break; |
341 | #endif | |
e135f41b NC |
342 | #ifdef ARCH_pdp11 |
343 | case bfd_arch_pdp11: | |
344 | disassemble = print_insn_pdp11; | |
345 | break; | |
346 | #endif | |
1e608f98 ILT |
347 | #ifdef ARCH_pj |
348 | case bfd_arch_pj: | |
349 | disassemble = print_insn_pj; | |
350 | break; | |
351 | #endif | |
252b5132 RH |
352 | #ifdef ARCH_powerpc |
353 | case bfd_arch_powerpc: | |
354 | if (bfd_big_endian (abfd)) | |
355 | disassemble = print_insn_big_powerpc; | |
356 | else | |
357 | disassemble = print_insn_little_powerpc; | |
358 | break; | |
359 | #endif | |
360 | #ifdef ARCH_rs6000 | |
361 | case bfd_arch_rs6000: | |
39c20e8f | 362 | if (bfd_get_mach (abfd) == bfd_mach_ppc_620) |
7f6d05e8 CP |
363 | disassemble = print_insn_big_powerpc; |
364 | else | |
365 | disassemble = print_insn_rs6000; | |
252b5132 RH |
366 | break; |
367 | #endif | |
99c513f6 DD |
368 | #ifdef ARCH_rl78 |
369 | case bfd_arch_rl78: | |
370 | disassemble = print_insn_rl78; | |
371 | break; | |
372 | #endif | |
c7927a3c NC |
373 | #ifdef ARCH_rx |
374 | case bfd_arch_rx: | |
375 | disassemble = print_insn_rx; | |
376 | break; | |
377 | #endif | |
a85d7ed0 NC |
378 | #ifdef ARCH_s390 |
379 | case bfd_arch_s390: | |
380 | disassemble = print_insn_s390; | |
381 | break; | |
382 | #endif | |
1c0d3aa6 NC |
383 | #ifdef ARCH_score |
384 | case bfd_arch_score: | |
385 | if (bfd_big_endian (abfd)) | |
6ca4eb77 | 386 | disassemble = print_insn_big_score; |
1c0d3aa6 | 387 | else |
6ca4eb77 | 388 | disassemble = print_insn_little_score; |
1c0d3aa6 NC |
389 | break; |
390 | #endif | |
252b5132 RH |
391 | #ifdef ARCH_sh |
392 | case bfd_arch_sh: | |
1c509ca8 | 393 | disassemble = print_insn_sh; |
252b5132 RH |
394 | break; |
395 | #endif | |
396 | #ifdef ARCH_sparc | |
397 | case bfd_arch_sparc: | |
398 | disassemble = print_insn_sparc; | |
399 | break; | |
400 | #endif | |
e9f53129 AM |
401 | #ifdef ARCH_spu |
402 | case bfd_arch_spu: | |
403 | disassemble = print_insn_spu; | |
404 | break; | |
405 | #endif | |
252b5132 RH |
406 | #ifdef ARCH_tic30 |
407 | case bfd_arch_tic30: | |
408 | disassemble = print_insn_tic30; | |
409 | break; | |
410 | #endif | |
026df7c5 NC |
411 | #ifdef ARCH_tic4x |
412 | case bfd_arch_tic4x: | |
413 | disassemble = print_insn_tic4x; | |
414 | break; | |
415 | #endif | |
5c84d377 TW |
416 | #ifdef ARCH_tic54x |
417 | case bfd_arch_tic54x: | |
418 | disassemble = print_insn_tic54x; | |
419 | break; | |
420 | #endif | |
40b36596 JM |
421 | #ifdef ARCH_tic6x |
422 | case bfd_arch_tic6x: | |
423 | disassemble = print_insn_tic6x; | |
424 | break; | |
425 | #endif | |
252b5132 RH |
426 | #ifdef ARCH_tic80 |
427 | case bfd_arch_tic80: | |
428 | disassemble = print_insn_tic80; | |
429 | break; | |
430 | #endif | |
431 | #ifdef ARCH_v850 | |
432 | case bfd_arch_v850: | |
433 | disassemble = print_insn_v850; | |
434 | break; | |
435 | #endif | |
436 | #ifdef ARCH_w65 | |
437 | case bfd_arch_w65: | |
438 | disassemble = print_insn_w65; | |
439 | break; | |
440 | #endif | |
f6c1a2d5 NC |
441 | #ifdef ARCH_xgate |
442 | case bfd_arch_xgate: | |
443 | disassemble = print_insn_xgate; | |
444 | break; | |
445 | #endif | |
93fbbb04 GK |
446 | #ifdef ARCH_xstormy16 |
447 | case bfd_arch_xstormy16: | |
448 | disassemble = print_insn_xstormy16; | |
449 | break; | |
450 | #endif | |
d70c5fc7 NC |
451 | #ifdef ARCH_xc16x |
452 | case bfd_arch_xc16x: | |
453 | disassemble = print_insn_xc16x; | |
454 | break; | |
455 | #endif | |
e0001a05 NC |
456 | #ifdef ARCH_xtensa |
457 | case bfd_arch_xtensa: | |
458 | disassemble = print_insn_xtensa; | |
459 | break; | |
460 | #endif | |
3c9b82ba NC |
461 | #ifdef ARCH_z80 |
462 | case bfd_arch_z80: | |
463 | disassemble = print_insn_z80; | |
464 | break; | |
465 | #endif | |
252b5132 RH |
466 | #ifdef ARCH_z8k |
467 | case bfd_arch_z8k: | |
468 | if (bfd_get_mach(abfd) == bfd_mach_z8001) | |
469 | disassemble = print_insn_z8001; | |
b7ed8fad | 470 | else |
252b5132 RH |
471 | disassemble = print_insn_z8002; |
472 | break; | |
473 | #endif | |
474 | #ifdef ARCH_vax | |
475 | case bfd_arch_vax: | |
476 | disassemble = print_insn_vax; | |
477 | break; | |
fd3c93d5 DB |
478 | #endif |
479 | #ifdef ARCH_frv | |
480 | case bfd_arch_frv: | |
481 | disassemble = print_insn_frv; | |
482 | break; | |
47b1a55a | 483 | #endif |
59b1530d AG |
484 | #ifdef ARCH_moxie |
485 | case bfd_arch_moxie: | |
486 | disassemble = print_insn_moxie; | |
487 | break; | |
488 | #endif | |
47b1a55a SC |
489 | #ifdef ARCH_iq2000 |
490 | case bfd_arch_iq2000: | |
491 | disassemble = print_insn_iq2000; | |
492 | break; | |
49f58d10 JB |
493 | #endif |
494 | #ifdef ARCH_m32c | |
495 | case bfd_arch_m32c: | |
496 | disassemble = print_insn_m32c; | |
497 | break; | |
aa137e4d NC |
498 | #endif |
499 | #ifdef ARCH_tilegx | |
500 | case bfd_arch_tilegx: | |
501 | disassemble = print_insn_tilegx; | |
502 | break; | |
503 | #endif | |
504 | #ifdef ARCH_tilepro | |
505 | case bfd_arch_tilepro: | |
506 | disassemble = print_insn_tilepro; | |
507 | break; | |
252b5132 RH |
508 | #endif |
509 | default: | |
510 | return 0; | |
511 | } | |
512 | return disassemble; | |
513 | } | |
94470b23 NC |
514 | |
515 | void | |
9aaaa291 | 516 | disassembler_usage (stream) |
7f32bebc | 517 | FILE * stream ATTRIBUTE_UNUSED; |
94470b23 | 518 | { |
58efb6c0 NC |
519 | #ifdef ARCH_arm |
520 | print_arm_disassembler_options (stream); | |
521 | #endif | |
640c0ccd CD |
522 | #ifdef ARCH_mips |
523 | print_mips_disassembler_options (stream); | |
524 | #endif | |
07dd56a9 NC |
525 | #ifdef ARCH_powerpc |
526 | print_ppc_disassembler_options (stream); | |
527 | #endif | |
f59a29b9 L |
528 | #ifdef ARCH_i386 |
529 | print_i386_disassembler_options (stream); | |
530 | #endif | |
112b7c50 AK |
531 | #ifdef ARCH_s390 |
532 | print_s390_disassembler_options (stream); | |
533 | #endif | |
b7ed8fad | 534 | |
94470b23 NC |
535 | return; |
536 | } | |
22a398e1 NC |
537 | |
538 | void | |
539 | disassemble_init_for_target (struct disassemble_info * info) | |
540 | { | |
541 | if (info == NULL) | |
542 | return; | |
543 | ||
544 | switch (info->arch) | |
545 | { | |
546 | #ifdef ARCH_arm | |
547 | case bfd_arch_arm: | |
548 | info->symbol_is_valid = arm_symbol_is_valid; | |
d99b6465 | 549 | info->disassembler_needs_relocs = TRUE; |
22a398e1 | 550 | break; |
0bcb06d2 AS |
551 | #endif |
552 | #ifdef ARCH_ia64 | |
553 | case bfd_arch_ia64: | |
554 | info->skip_zeroes = 16; | |
555 | break; | |
556 | #endif | |
557 | #ifdef ARCH_tic4x | |
558 | case bfd_arch_tic4x: | |
559 | info->skip_zeroes = 32; | |
fb53f5a8 | 560 | break; |
49f58d10 | 561 | #endif |
bd2f2e55 DB |
562 | #ifdef ARCH_mep |
563 | case bfd_arch_mep: | |
564 | info->skip_zeroes = 256; | |
565 | info->skip_zeroes_at_end = 0; | |
566 | break; | |
567 | #endif | |
49f58d10 JB |
568 | #ifdef ARCH_m32c |
569 | case bfd_arch_m32c: | |
6ca4eb77 AM |
570 | /* This processor in fact is little endian. The value set here |
571 | reflects the way opcodes are written in the cgen description. */ | |
49f58d10 | 572 | info->endian = BFD_ENDIAN_BIG; |
fb53f5a8 DB |
573 | if (! info->insn_sets) |
574 | { | |
575 | info->insn_sets = cgen_bitset_create (ISA_MAX); | |
576 | if (info->mach == bfd_mach_m16c) | |
577 | cgen_bitset_set (info->insn_sets, ISA_M16C); | |
578 | else | |
579 | cgen_bitset_set (info->insn_sets, ISA_M32C); | |
580 | } | |
49f58d10 | 581 | break; |
b240011a AM |
582 | #endif |
583 | #ifdef ARCH_powerpc | |
584 | case bfd_arch_powerpc: | |
585 | #endif | |
586 | #ifdef ARCH_rs6000 | |
587 | case bfd_arch_rs6000: | |
588 | #endif | |
589 | #if defined (ARCH_powerpc) || defined (ARCH_rs6000) | |
590 | disassemble_init_powerpc (info); | |
591 | break; | |
22a398e1 NC |
592 | #endif |
593 | default: | |
594 | break; | |
595 | } | |
596 | } |