Commit | Line | Data |
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d172d4ba | 1 | /* Instruction printing code for the DLX Microprocessor |
47b0e7ad | 2 | Copyright 2002, 2005 Free Software Foundation, Inc. |
d172d4ba NC |
3 | Contributed by Kuang Hwa Lin. Written by Kuang Hwa Lin, 03/2002. |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the Free Software | |
47b0e7ad NC |
17 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
18 | MA 02110-1301, USA. */ | |
d172d4ba NC |
19 | |
20 | #include "sysdep.h" | |
21 | #include "dis-asm.h" | |
22 | #include "opcode/dlx.h" | |
23 | ||
24 | #define R_ERROR 0x1 | |
25 | #define R_TYPE 0x2 | |
26 | #define ILD_TYPE 0x3 | |
27 | #define IST_TYPE 0x4 | |
28 | #define IAL_TYPE 0x5 | |
29 | #define IBR_TYPE 0x6 | |
30 | #define IJ_TYPE 0x7 | |
31 | #define IJR_TYPE 0x8 | |
32 | #define NIL 0x9 | |
33 | ||
34 | #define OPC(x) ((x >> 26) & 0x3F) | |
35 | #define FUNC(x) (x & 0x7FF) | |
36 | ||
37 | unsigned char opc, rs1, rs2, rd; | |
38 | unsigned long imm26, imm16, func, current_insn_addr; | |
39 | ||
d172d4ba NC |
40 | /* Print one instruction from MEMADDR on INFO->STREAM. |
41 | Return the size of the instruction (always 4 on dlx). */ | |
42 | ||
43 | static unsigned char | |
47b0e7ad | 44 | dlx_get_opcode (unsigned long opcode) |
d172d4ba NC |
45 | { |
46 | return (unsigned char) ((opcode >> 26) & 0x3F); | |
47 | } | |
48 | ||
49 | static unsigned char | |
47b0e7ad | 50 | dlx_get_rs1 (unsigned long opcode) |
d172d4ba NC |
51 | { |
52 | return (unsigned char) ((opcode >> 21) & 0x1F); | |
53 | } | |
54 | ||
55 | static unsigned char | |
47b0e7ad | 56 | dlx_get_rs2 (unsigned long opcode) |
d172d4ba NC |
57 | { |
58 | return (unsigned char) ((opcode >> 16) & 0x1F); | |
59 | } | |
60 | ||
61 | static unsigned char | |
47b0e7ad | 62 | dlx_get_rdR (unsigned long opcode) |
d172d4ba NC |
63 | { |
64 | return (unsigned char) ((opcode >> 11) & 0x1F); | |
65 | } | |
66 | ||
67 | static unsigned long | |
47b0e7ad | 68 | dlx_get_func (unsigned long opcode) |
d172d4ba NC |
69 | { |
70 | return (unsigned char) (opcode & 0x7FF); | |
71 | } | |
72 | ||
73 | static unsigned long | |
47b0e7ad | 74 | dlx_get_imm16 (unsigned long opcode) |
d172d4ba NC |
75 | { |
76 | return (unsigned long) (opcode & 0xFFFF); | |
77 | } | |
78 | ||
79 | static unsigned long | |
47b0e7ad | 80 | dlx_get_imm26 (unsigned long opcode) |
d172d4ba NC |
81 | { |
82 | return (unsigned long) (opcode & 0x03FFFFFF); | |
83 | } | |
84 | ||
85 | /* Fill the opcode to the max length. */ | |
47b0e7ad | 86 | |
d172d4ba | 87 | static void |
47b0e7ad | 88 | operand_deliminator (struct disassemble_info *info, char *ptr) |
d172d4ba NC |
89 | { |
90 | int difft = 8 - (int) strlen (ptr); | |
91 | ||
92 | while (difft > 0) | |
93 | { | |
94 | (*info->fprintf_func) (info->stream, "%c", ' '); | |
95 | difft -= 1; | |
96 | } | |
97 | } | |
98 | ||
99 | /* Process the R-type opcode. */ | |
47b0e7ad | 100 | |
d172d4ba | 101 | static unsigned char |
47b0e7ad | 102 | dlx_r_type (struct disassemble_info *info) |
d172d4ba NC |
103 | { |
104 | unsigned char r_opc[] = { OPC(ALUOP) }; /* Fix ME */ | |
105 | int r_opc_num = (sizeof r_opc) / (sizeof (char)); | |
106 | struct _r_opcode | |
107 | { | |
108 | unsigned long func; | |
109 | char *name; | |
110 | } | |
111 | dlx_r_opcode[] = | |
47b0e7ad | 112 | { |
d172d4ba NC |
113 | { NOPF, "nop" }, /* NOP */ |
114 | { ADDF, "add" }, /* Add */ | |
115 | { ADDUF, "addu" }, /* Add Unsigned */ | |
116 | { SUBF, "sub" }, /* SUB */ | |
117 | { SUBUF, "subu" }, /* Sub Unsigned */ | |
118 | { MULTF, "mult" }, /* MULTIPLY */ | |
119 | { MULTUF, "multu" }, /* MULTIPLY Unsigned */ | |
120 | { DIVF, "div" }, /* DIVIDE */ | |
121 | { DIVUF, "divu" }, /* DIVIDE Unsigned */ | |
122 | { ANDF, "and" }, /* AND */ | |
123 | { ORF, "or" }, /* OR */ | |
124 | { XORF, "xor" }, /* Exclusive OR */ | |
125 | { SLLF, "sll" }, /* SHIFT LEFT LOGICAL */ | |
126 | { SRAF, "sra" }, /* SHIFT RIGHT ARITHMETIC */ | |
127 | { SRLF, "srl" }, /* SHIFT RIGHT LOGICAL */ | |
128 | { SEQF, "seq" }, /* Set if equal */ | |
129 | { SNEF, "sne" }, /* Set if not equal */ | |
130 | { SLTF, "slt" }, /* Set if less */ | |
131 | { SGTF, "sgt" }, /* Set if greater */ | |
132 | { SLEF, "sle" }, /* Set if less or equal */ | |
133 | { SGEF, "sge" }, /* Set if greater or equal */ | |
134 | { SEQUF, "sequ" }, /* Set if equal */ | |
135 | { SNEUF, "sneu" }, /* Set if not equal */ | |
136 | { SLTUF, "sltu" }, /* Set if less */ | |
137 | { SGTUF, "sgtu" }, /* Set if greater */ | |
138 | { SLEUF, "sleu" }, /* Set if less or equal */ | |
139 | { SGEUF, "sgeu" }, /* Set if greater or equal */ | |
140 | { MVTSF, "mvts" }, /* Move to special register */ | |
141 | { MVFSF, "mvfs" }, /* Move from special register */ | |
142 | { BSWAPF, "bswap" }, /* Byte swap ?? */ | |
143 | { LUTF, "lut" } /* ????????? ?? */ | |
144 | }; | |
145 | int dlx_r_opcode_num = (sizeof dlx_r_opcode) / (sizeof dlx_r_opcode[0]); | |
146 | int idx; | |
147 | ||
148 | for (idx = 0; idx < r_opc_num; idx++) | |
149 | { | |
150 | if (r_opc[idx] != opc) | |
151 | continue; | |
152 | else | |
153 | break; | |
47b0e7ad | 154 | } |
d172d4ba NC |
155 | |
156 | if (idx == r_opc_num) | |
157 | return NIL; | |
158 | ||
159 | for (idx = 0 ; idx < dlx_r_opcode_num; idx++) | |
160 | if (dlx_r_opcode[idx].func == func) | |
161 | { | |
162 | (*info->fprintf_func) (info->stream, "%s", dlx_r_opcode[idx].name); | |
163 | ||
164 | if (func != NOPF) | |
165 | { | |
166 | /* This is not a nop. */ | |
167 | operand_deliminator (info, dlx_r_opcode[idx].name); | |
168 | (*info->fprintf_func) (info->stream, "r%d,", (int)rd); | |
169 | (*info->fprintf_func) (info->stream, "r%d", (int)rs1); | |
170 | if (func != MVTSF && func != MVFSF) | |
171 | (*info->fprintf_func) (info->stream, ",r%d", (int)rs2); | |
172 | } | |
173 | return (unsigned char) R_TYPE; | |
174 | } | |
175 | ||
176 | return (unsigned char) R_ERROR; | |
177 | } | |
178 | ||
179 | /* Process the memory read opcode. */ | |
180 | ||
181 | static unsigned char | |
47b0e7ad | 182 | dlx_load_type (struct disassemble_info* info) |
d172d4ba NC |
183 | { |
184 | struct _load_opcode | |
185 | { | |
186 | unsigned long opcode; | |
187 | char *name; | |
188 | } | |
189 | dlx_load_opcode[] = | |
47b0e7ad NC |
190 | { |
191 | { OPC(LHIOP), "lhi" }, /* Load HI to register. */ | |
192 | { OPC(LBOP), "lb" }, /* load byte sign extended. */ | |
193 | { OPC(LBUOP), "lbu" }, /* load byte unsigned. */ | |
194 | { OPC(LSBUOP),"ldstbu"}, /* load store byte unsigned. */ | |
195 | { OPC(LHOP), "lh" }, /* load halfword sign extended. */ | |
196 | { OPC(LHUOP), "lhu" }, /* load halfword unsigned. */ | |
197 | { OPC(LSHUOP),"ldsthu"}, /* load store halfword unsigned. */ | |
198 | { OPC(LWOP), "lw" }, /* load word. */ | |
199 | { OPC(LSWOP), "ldstw" } /* load store word. */ | |
200 | }; | |
d172d4ba NC |
201 | int dlx_load_opcode_num = |
202 | (sizeof dlx_load_opcode) / (sizeof dlx_load_opcode[0]); | |
203 | int idx; | |
204 | ||
205 | for (idx = 0 ; idx < dlx_load_opcode_num; idx++) | |
206 | if (dlx_load_opcode[idx].opcode == opc) | |
207 | { | |
208 | if (opc == OPC (LHIOP)) | |
209 | { | |
210 | (*info->fprintf_func) (info->stream, "%s", dlx_load_opcode[idx].name); | |
211 | operand_deliminator (info, dlx_load_opcode[idx].name); | |
212 | (*info->fprintf_func) (info->stream, "r%d,", (int)rs2); | |
213 | (*info->fprintf_func) (info->stream, "0x%04x", (int)imm16); | |
214 | } | |
215 | else | |
216 | { | |
217 | (*info->fprintf_func) (info->stream, "%s", dlx_load_opcode[idx].name); | |
218 | operand_deliminator (info, dlx_load_opcode[idx].name); | |
219 | (*info->fprintf_func) (info->stream, "r%d,", (int)rs2); | |
220 | (*info->fprintf_func) (info->stream, "0x%04x[r%d]", (int)imm16, (int)rs1); | |
221 | } | |
222 | ||
223 | return (unsigned char) ILD_TYPE; | |
224 | } | |
225 | ||
226 | return (unsigned char) NIL; | |
227 | } | |
228 | ||
229 | /* Process the memory store opcode. */ | |
230 | ||
231 | static unsigned char | |
47b0e7ad | 232 | dlx_store_type (struct disassemble_info* info) |
d172d4ba NC |
233 | { |
234 | struct _store_opcode | |
235 | { | |
236 | unsigned long opcode; | |
237 | char *name; | |
238 | } | |
239 | dlx_store_opcode[] = | |
47b0e7ad NC |
240 | { |
241 | { OPC(SBOP), "sb" }, /* Store byte. */ | |
242 | { OPC(SHOP), "sh" }, /* Store halfword. */ | |
243 | { OPC(SWOP), "sw" }, /* Store word. */ | |
244 | }; | |
d172d4ba NC |
245 | int dlx_store_opcode_num = |
246 | (sizeof dlx_store_opcode) / (sizeof dlx_store_opcode[0]); | |
247 | int idx; | |
248 | ||
249 | for (idx = 0 ; idx < dlx_store_opcode_num; idx++) | |
250 | if (dlx_store_opcode[idx].opcode == opc) | |
251 | { | |
252 | (*info->fprintf_func) (info->stream, "%s", dlx_store_opcode[idx].name); | |
253 | operand_deliminator (info, dlx_store_opcode[idx].name); | |
254 | (*info->fprintf_func) (info->stream, "0x%04x[r%d],", (int)imm16, (int)rs1); | |
255 | (*info->fprintf_func) (info->stream, "r%d", (int)rs2); | |
256 | return (unsigned char) IST_TYPE; | |
257 | } | |
258 | ||
259 | return (unsigned char) NIL; | |
260 | } | |
261 | ||
262 | /* Process the Arithmetic and Logical I-TYPE opcode. */ | |
263 | ||
264 | static unsigned char | |
47b0e7ad | 265 | dlx_aluI_type (struct disassemble_info* info) |
d172d4ba NC |
266 | { |
267 | struct _aluI_opcode | |
268 | { | |
269 | unsigned long opcode; | |
270 | char *name; | |
271 | } | |
272 | dlx_aluI_opcode[] = | |
47b0e7ad NC |
273 | { |
274 | { OPC(ADDIOP), "addi" }, /* Store byte. */ | |
275 | { OPC(ADDUIOP), "addui" }, /* Store halfword. */ | |
276 | { OPC(SUBIOP), "subi" }, /* Store word. */ | |
277 | { OPC(SUBUIOP), "subui" }, /* Store word. */ | |
278 | { OPC(ANDIOP), "andi" }, /* Store word. */ | |
279 | { OPC(ORIOP), "ori" }, /* Store word. */ | |
280 | { OPC(XORIOP), "xori" }, /* Store word. */ | |
281 | { OPC(SLLIOP), "slli" }, /* Store word. */ | |
282 | { OPC(SRAIOP), "srai" }, /* Store word. */ | |
283 | { OPC(SRLIOP), "srli" }, /* Store word. */ | |
284 | { OPC(SEQIOP), "seqi" }, /* Store word. */ | |
285 | { OPC(SNEIOP), "snei" }, /* Store word. */ | |
286 | { OPC(SLTIOP), "slti" }, /* Store word. */ | |
287 | { OPC(SGTIOP), "sgti" }, /* Store word. */ | |
288 | { OPC(SLEIOP), "slei" }, /* Store word. */ | |
289 | { OPC(SGEIOP), "sgei" }, /* Store word. */ | |
290 | { OPC(SEQUIOP), "sequi" }, /* Store word. */ | |
291 | { OPC(SNEUIOP), "sneui" }, /* Store word. */ | |
292 | { OPC(SLTUIOP), "sltui" }, /* Store word. */ | |
293 | { OPC(SGTUIOP), "sgtui" }, /* Store word. */ | |
294 | { OPC(SLEUIOP), "sleui" }, /* Store word. */ | |
295 | { OPC(SGEUIOP), "sgeui" }, /* Store word. */ | |
d172d4ba | 296 | #if 0 |
47b0e7ad NC |
297 | { OPC(MVTSOP), "mvts" }, /* Store word. */ |
298 | { OPC(MVFSOP), "mvfs" }, /* Store word. */ | |
d172d4ba | 299 | #endif |
47b0e7ad | 300 | }; |
d172d4ba NC |
301 | int dlx_aluI_opcode_num = |
302 | (sizeof dlx_aluI_opcode) / (sizeof dlx_aluI_opcode[0]); | |
303 | int idx; | |
304 | ||
305 | for (idx = 0 ; idx < dlx_aluI_opcode_num; idx++) | |
306 | if (dlx_aluI_opcode[idx].opcode == opc) | |
307 | { | |
308 | (*info->fprintf_func) (info->stream, "%s", dlx_aluI_opcode[idx].name); | |
309 | operand_deliminator (info, dlx_aluI_opcode[idx].name); | |
310 | (*info->fprintf_func) (info->stream, "r%d,", (int)rs2); | |
311 | (*info->fprintf_func) (info->stream, "r%d,", (int)rs1); | |
312 | (*info->fprintf_func) (info->stream, "0x%04x", (int)imm16); | |
313 | ||
314 | return (unsigned char) IAL_TYPE; | |
315 | } | |
316 | ||
317 | return (unsigned char) NIL; | |
318 | } | |
319 | ||
320 | /* Process the branch instruction. */ | |
321 | ||
322 | static unsigned char | |
47b0e7ad | 323 | dlx_br_type (struct disassemble_info* info) |
d172d4ba NC |
324 | { |
325 | struct _br_opcode | |
326 | { | |
327 | unsigned long opcode; | |
328 | char *name; | |
329 | } | |
330 | dlx_br_opcode[] = | |
47b0e7ad NC |
331 | { |
332 | { OPC(BEQOP), "beqz" }, /* Store byte. */ | |
333 | { OPC(BNEOP), "bnez" } /* Store halfword. */ | |
334 | }; | |
d172d4ba NC |
335 | int dlx_br_opcode_num = |
336 | (sizeof dlx_br_opcode) / (sizeof dlx_br_opcode[0]); | |
337 | int idx; | |
338 | ||
339 | for (idx = 0 ; idx < dlx_br_opcode_num; idx++) | |
340 | if (dlx_br_opcode[idx].opcode == opc) | |
341 | { | |
342 | if (imm16 & 0x00008000) | |
343 | imm16 |= 0xFFFF0000; | |
344 | ||
345 | imm16 += (current_insn_addr + 4); | |
346 | (*info->fprintf_func) (info->stream, "%s", dlx_br_opcode[idx].name); | |
347 | operand_deliminator (info, dlx_br_opcode[idx].name); | |
47b0e7ad NC |
348 | (*info->fprintf_func) (info->stream, "r%d,", (int) rs1); |
349 | (*info->fprintf_func) (info->stream, "0x%08x", (int) imm16); | |
d172d4ba NC |
350 | |
351 | return (unsigned char) IBR_TYPE; | |
352 | } | |
353 | ||
354 | return (unsigned char) NIL; | |
355 | } | |
356 | ||
357 | /* Process the jump instruction. */ | |
358 | ||
359 | static unsigned char | |
47b0e7ad | 360 | dlx_jmp_type (struct disassemble_info* info) |
d172d4ba NC |
361 | { |
362 | struct _jmp_opcode | |
363 | { | |
364 | unsigned long opcode; | |
365 | char *name; | |
366 | } | |
367 | dlx_jmp_opcode[] = | |
47b0e7ad NC |
368 | { |
369 | { OPC(JOP), "j" }, /* Store byte. */ | |
370 | { OPC(JALOP), "jal" }, /* Store halfword. */ | |
371 | { OPC(BREAKOP), "break" }, /* Store halfword. */ | |
372 | { OPC(TRAPOP), "trap" }, /* Store halfword. */ | |
373 | { OPC(RFEOP), "rfe" } /* Store halfword. */ | |
374 | }; | |
d172d4ba NC |
375 | int dlx_jmp_opcode_num = |
376 | (sizeof dlx_jmp_opcode) / (sizeof dlx_jmp_opcode[0]); | |
377 | int idx; | |
378 | ||
379 | for (idx = 0 ; idx < dlx_jmp_opcode_num; idx++) | |
380 | if (dlx_jmp_opcode[idx].opcode == opc) | |
381 | { | |
382 | if (imm26 & 0x02000000) | |
383 | imm26 |= 0xFC000000; | |
384 | ||
385 | imm26 += (current_insn_addr + 4); | |
386 | ||
387 | (*info->fprintf_func) (info->stream, "%s", dlx_jmp_opcode[idx].name); | |
388 | operand_deliminator (info, dlx_jmp_opcode[idx].name); | |
389 | (*info->fprintf_func) (info->stream, "0x%08x", (int)imm26); | |
390 | ||
391 | return (unsigned char) IJ_TYPE; | |
392 | } | |
393 | ||
394 | return (unsigned char) NIL; | |
395 | } | |
396 | ||
397 | /* Process the jump register instruction. */ | |
398 | ||
399 | static unsigned char | |
47b0e7ad | 400 | dlx_jr_type (struct disassemble_info* info) |
d172d4ba NC |
401 | { |
402 | struct _jr_opcode | |
403 | { | |
404 | unsigned long opcode; | |
405 | char *name; | |
406 | } | |
47b0e7ad NC |
407 | dlx_jr_opcode[] = |
408 | { | |
d172d4ba NC |
409 | { OPC(JROP), "jr" }, /* Store byte. */ |
410 | { OPC(JALROP), "jalr" } /* Store halfword. */ | |
411 | }; | |
412 | int dlx_jr_opcode_num = | |
413 | (sizeof dlx_jr_opcode) / (sizeof dlx_jr_opcode[0]); | |
414 | int idx; | |
415 | ||
416 | for (idx = 0 ; idx < dlx_jr_opcode_num; idx++) | |
417 | if (dlx_jr_opcode[idx].opcode == opc) | |
418 | { | |
419 | (*info->fprintf_func) (info->stream, "%s", dlx_jr_opcode[idx].name); | |
420 | operand_deliminator (info, dlx_jr_opcode[idx].name); | |
421 | (*info->fprintf_func) (info->stream, "r%d", (int)rs1); | |
422 | return (unsigned char) IJR_TYPE; | |
423 | } | |
424 | ||
425 | return (unsigned char) NIL; | |
426 | } | |
427 | ||
47b0e7ad | 428 | typedef unsigned char (* dlx_insn) (struct disassemble_info *); |
d172d4ba NC |
429 | |
430 | /* This is the main DLX insn handling routine. */ | |
431 | ||
432 | int | |
47b0e7ad | 433 | print_insn_dlx (bfd_vma memaddr, struct disassemble_info* info) |
d172d4ba NC |
434 | { |
435 | bfd_byte buffer[4]; | |
436 | int insn_idx; | |
437 | unsigned long insn_word; | |
438 | unsigned char rtn_code; | |
439 | unsigned long dlx_insn_type[] = | |
47b0e7ad NC |
440 | { |
441 | (unsigned long) dlx_r_type, | |
442 | (unsigned long) dlx_load_type, | |
443 | (unsigned long) dlx_store_type, | |
444 | (unsigned long) dlx_aluI_type, | |
445 | (unsigned long) dlx_br_type, | |
446 | (unsigned long) dlx_jmp_type, | |
447 | (unsigned long) dlx_jr_type, | |
448 | (unsigned long) NULL | |
d172d4ba NC |
449 | }; |
450 | int dlx_insn_type_num = ((sizeof dlx_insn_type) / (sizeof (unsigned long))) - 1; | |
451 | int status = | |
452 | (*info->read_memory_func) (memaddr, (bfd_byte *) &buffer[0], 4, info); | |
453 | ||
454 | if (status != 0) | |
455 | { | |
456 | (*info->memory_error_func) (status, memaddr, info); | |
457 | return -1; | |
458 | } | |
459 | ||
460 | /* Now decode the insn */ | |
461 | insn_word = bfd_getb32 (buffer); | |
462 | opc = dlx_get_opcode (insn_word); | |
463 | rs1 = dlx_get_rs1 (insn_word); | |
464 | rs2 = dlx_get_rs2 (insn_word); | |
465 | rd = dlx_get_rdR (insn_word); | |
466 | func = dlx_get_func (insn_word); | |
467 | imm16= dlx_get_imm16 (insn_word); | |
468 | imm26= dlx_get_imm26 (insn_word); | |
469 | ||
470 | #if 0 | |
471 | printf ("print_insn_big_dlx: opc = 0x%02x\n" | |
472 | " rs1 = 0x%02x\n" | |
473 | " rs2 = 0x%02x\n" | |
474 | " rd = 0x%02x\n" | |
475 | " func = 0x%08x\n" | |
476 | " imm16 = 0x%08x\n" | |
477 | " imm26 = 0x%08x\n", | |
478 | opc, rs1, rs2, rd, func, imm16, imm26); | |
479 | #endif | |
480 | ||
481 | /* Scan through all the insn type and print the insn out. */ | |
482 | rtn_code = 0; | |
483 | current_insn_addr = (unsigned long) memaddr; | |
484 | ||
485 | for (insn_idx = 0; dlx_insn_type[insn_idx] != 0x0; insn_idx++) | |
486 | switch (((dlx_insn) (dlx_insn_type[insn_idx])) (info)) | |
487 | { | |
488 | /* Found the correct opcode */ | |
489 | case R_TYPE: | |
490 | case ILD_TYPE: | |
491 | case IST_TYPE: | |
492 | case IAL_TYPE: | |
493 | case IBR_TYPE: | |
494 | case IJ_TYPE: | |
495 | case IJR_TYPE: | |
496 | return 4; | |
497 | ||
498 | /* Wrong insn type check next one. */ | |
499 | default: | |
500 | case NIL: | |
501 | continue; | |
502 | ||
503 | /* All rest of the return code are not recongnized, treat it as error */ | |
504 | /* we should never get here, I hope! */ | |
505 | case R_ERROR: | |
506 | return -1; | |
507 | } | |
508 | ||
509 | if (insn_idx == dlx_insn_type_num) | |
510 | /* Well, does not recoganize this opcode. */ | |
511 | (*info->fprintf_func) (info->stream, "<%s>", "Unrecognized Opcode"); | |
512 | ||
513 | return 4; | |
514 | } |