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Arm64: correct 64-bit element fmmla encoding
[deliverable/binutils-gdb.git] / opcodes / epiphany-desc.c
CommitLineData
4162bb66 1/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
cfb8c092
NC		 2/* CPU data for epiphany.
3
4THIS FILE IS MACHINE GENERATED WITH CGEN.
5
b3adc24a 6Copyright (C) 1996-2020 Free Software Foundation, Inc.
cfb8c092
NC		 7
8This file is part of the GNU Binutils and/or GDB, the GNU debugger.
9
10 This file is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 It is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
19
20 You should have received a copy of the GNU General Public License along
21 with this program; if not, write to the Free Software Foundation, Inc.,
22 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
23
24*/
25
26#include "sysdep.h"
27#include <stdio.h>
28#include <stdarg.h>
29#include "ansidecl.h"
30#include "bfd.h"
31#include "symcat.h"
32#include "epiphany-desc.h"
33#include "epiphany-opc.h"
34#include "opintl.h"
35#include "libiberty.h"
36#include "xregex.h"
37
38/* Attributes. */
39
40static const CGEN_ATTR_ENTRY bool_attr[] =
41{
42 { "#f", 0 },
43 { "#t", 1 },
44 { 0, 0 }
45};
46
47static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
48{
49 { "base", MACH_BASE },
50 { "epiphany32", MACH_EPIPHANY32 },
51 { "max", MACH_MAX },
52 { 0, 0 }
53};
54
55static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
56{
57 { "epiphany", ISA_EPIPHANY },
58 { "max", ISA_MAX },
59 { 0, 0 }
60};
61
62const CGEN_ATTR_TABLE epiphany_cgen_ifield_attr_table[] =
63{
64 { "MACH", & MACH_attr[0], & MACH_attr[0] },
65 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
66 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
67 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
68 { "RESERVED", &bool_attr[0], &bool_attr[0] },
69 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
70 { "SIGNED", &bool_attr[0], &bool_attr[0] },
71 { "RELOC", &bool_attr[0], &bool_attr[0] },
72 { 0, 0, 0 }
73};
74
75const CGEN_ATTR_TABLE epiphany_cgen_hardware_attr_table[] =
76{
77 { "MACH", & MACH_attr[0], & MACH_attr[0] },
78 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
79 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
80 { "PC", &bool_attr[0], &bool_attr[0] },
81 { "PROFILE", &bool_attr[0], &bool_attr[0] },
82 { 0, 0, 0 }
83};
84
85const CGEN_ATTR_TABLE epiphany_cgen_operand_attr_table[] =
86{
87 { "MACH", & MACH_attr[0], & MACH_attr[0] },
88 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
89 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
90 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
91 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
92 { "SIGNED", &bool_attr[0], &bool_attr[0] },
93 { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
94 { "RELAX", &bool_attr[0], &bool_attr[0] },
95 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
96 { "RELOC", &bool_attr[0], &bool_attr[0] },
97 { 0, 0, 0 }
98};
99
100const CGEN_ATTR_TABLE epiphany_cgen_insn_attr_table[] =
101{
102 { "MACH", & MACH_attr[0], & MACH_attr[0] },
103 { "ALIAS", &bool_attr[0], &bool_attr[0] },
104 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
105 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
106 { "COND-CTI", &bool_attr[0], &bool_attr[0] },
107 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
108 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
109 { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
110 { "RELAXED", &bool_attr[0], &bool_attr[0] },
111 { "NO-DIS", &bool_attr[0], &bool_attr[0] },
112 { "PBB", &bool_attr[0], &bool_attr[0] },
113 { "SHORT-INSN", &bool_attr[0], &bool_attr[0] },
114 { "IMM3", &bool_attr[0], &bool_attr[0] },
115 { "IMM8", &bool_attr[0], &bool_attr[0] },
116 { 0, 0, 0 }
117};
118
119/* Instruction set variants. */
120
121static const CGEN_ISA epiphany_cgen_isa_table[] = {
122 { "epiphany", 32, 32, 16, 32 },
123 { 0, 0, 0, 0, 0 }
124};
125
126/* Machine variants. */
127
128static const CGEN_MACH epiphany_cgen_mach_table[] = {
129 { "epiphany32", "epiphany32", MACH_EPIPHANY32, 0 },
130 { 0, 0, 0, 0 }
131};
132
133static CGEN_KEYWORD_ENTRY epiphany_cgen_opval_gr_names_entries[] =
134{
cfb8c092 135 { "fp", 11, {0, {{{0, 0}}}}, 0, 0 },
cfb8c092
NC		 136 { "sp", 13, {0, {{{0, 0}}}}, 0, 0 },
137 { "lr", 14, {0, {{{0, 0}}}}, 0, 0 },
138 { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
139 { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
140 { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
141 { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
142 { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
143 { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
144 { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
145 { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
146 { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
147 { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
148 { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
149 { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
150 { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
151 { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
152 { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
153 { "r15", 15, {0, {{{0, 0}}}}, 0, 0 },
154 { "r16", 16, {0, {{{0, 0}}}}, 0, 0 },
155 { "r17", 17, {0, {{{0, 0}}}}, 0, 0 },
156 { "r18", 18, {0, {{{0, 0}}}}, 0, 0 },
157 { "r19", 19, {0, {{{0, 0}}}}, 0, 0 },
158 { "r20", 20, {0, {{{0, 0}}}}, 0, 0 },
159 { "r21", 21, {0, {{{0, 0}}}}, 0, 0 },
160 { "r22", 22, {0, {{{0, 0}}}}, 0, 0 },
161 { "r23", 23, {0, {{{0, 0}}}}, 0, 0 },
162 { "r24", 24, {0, {{{0, 0}}}}, 0, 0 },
163 { "r25", 25, {0, {{{0, 0}}}}, 0, 0 },
164 { "r26", 26, {0, {{{0, 0}}}}, 0, 0 },
165 { "r27", 27, {0, {{{0, 0}}}}, 0, 0 },
166 { "r28", 28, {0, {{{0, 0}}}}, 0, 0 },
167 { "r29", 29, {0, {{{0, 0}}}}, 0, 0 },
168 { "r30", 30, {0, {{{0, 0}}}}, 0, 0 },
169 { "r31", 31, {0, {{{0, 0}}}}, 0, 0 },
170 { "r32", 32, {0, {{{0, 0}}}}, 0, 0 },
171 { "r33", 33, {0, {{{0, 0}}}}, 0, 0 },
172 { "r34", 34, {0, {{{0, 0}}}}, 0, 0 },
173 { "r35", 35, {0, {{{0, 0}}}}, 0, 0 },
174 { "r36", 36, {0, {{{0, 0}}}}, 0, 0 },
175 { "r37", 37, {0, {{{0, 0}}}}, 0, 0 },
176 { "r38", 38, {0, {{{0, 0}}}}, 0, 0 },
177 { "r39", 39, {0, {{{0, 0}}}}, 0, 0 },
178 { "r40", 40, {0, {{{0, 0}}}}, 0, 0 },
179 { "r41", 41, {0, {{{0, 0}}}}, 0, 0 },
180 { "r42", 42, {0, {{{0, 0}}}}, 0, 0 },
181 { "r43", 43, {0, {{{0, 0}}}}, 0, 0 },
182 { "r44", 44, {0, {{{0, 0}}}}, 0, 0 },
183 { "r45", 45, {0, {{{0, 0}}}}, 0, 0 },
184 { "r46", 46, {0, {{{0, 0}}}}, 0, 0 },
185 { "r47", 47, {0, {{{0, 0}}}}, 0, 0 },
186 { "r48", 48, {0, {{{0, 0}}}}, 0, 0 },
187 { "r49", 49, {0, {{{0, 0}}}}, 0, 0 },
188 { "r50", 50, {0, {{{0, 0}}}}, 0, 0 },
189 { "r51", 51, {0, {{{0, 0}}}}, 0, 0 },
190 { "r52", 52, {0, {{{0, 0}}}}, 0, 0 },
191 { "r53", 53, {0, {{{0, 0}}}}, 0, 0 },
192 { "r54", 54, {0, {{{0, 0}}}}, 0, 0 },
193 { "r55", 55, {0, {{{0, 0}}}}, 0, 0 },
194 { "r56", 56, {0, {{{0, 0}}}}, 0, 0 },
195 { "r57", 57, {0, {{{0, 0}}}}, 0, 0 },
196 { "r58", 58, {0, {{{0, 0}}}}, 0, 0 },
197 { "r59", 59, {0, {{{0, 0}}}}, 0, 0 },
198 { "r60", 60, {0, {{{0, 0}}}}, 0, 0 },
199 { "r61", 61, {0, {{{0, 0}}}}, 0, 0 },
200 { "r62", 62, {0, {{{0, 0}}}}, 0, 0 },
201 { "r63", 63, {0, {{{0, 0}}}}, 0, 0 },
202 { "a1", 0, {0, {{{0, 0}}}}, 0, 0 },
203 { "a2", 1, {0, {{{0, 0}}}}, 0, 0 },
204 { "a3", 2, {0, {{{0, 0}}}}, 0, 0 },
205 { "a4", 3, {0, {{{0, 0}}}}, 0, 0 },
206 { "v1", 4, {0, {{{0, 0}}}}, 0, 0 },
207 { "v2", 5, {0, {{{0, 0}}}}, 0, 0 },
208 { "v3", 6, {0, {{{0, 0}}}}, 0, 0 },
209 { "v4", 7, {0, {{{0, 0}}}}, 0, 0 },
210 { "v5", 8, {0, {{{0, 0}}}}, 0, 0 },
211 { "v6", 9, {0, {{{0, 0}}}}, 0, 0 },
212 { "v7", 10, {0, {{{0, 0}}}}, 0, 0 },
02a79b89
JR		 213 { "v8", 11, {0, {{{0, 0}}}}, 0, 0 },
214 { "sb", 9, {0, {{{0, 0}}}}, 0, 0 },
215 { "sl", 10, {0, {{{0, 0}}}}, 0, 0 },
216 { "ip", 12, {0, {{{0, 0}}}}, 0, 0 }
cfb8c092
NC		 217};
218
219CGEN_KEYWORD epiphany_cgen_opval_gr_names =
220{
221 & epiphany_cgen_opval_gr_names_entries[0],
222 82,
223 0, 0, 0, 0, ""
224};
225
226static CGEN_KEYWORD_ENTRY epiphany_cgen_opval_cr_names_entries[] =
227{
228 { "config", 0, {0, {{{0, 0}}}}, 0, 0 },
229 { "status", 1, {0, {{{0, 0}}}}, 0, 0 },
230 { "pc", 2, {0, {{{0, 0}}}}, 0, 0 },
231 { "debug", 3, {0, {{{0, 0}}}}, 0, 0 },
232 { "iab", 4, {0, {{{0, 0}}}}, 0, 0 },
233 { "lc", 5, {0, {{{0, 0}}}}, 0, 0 },
234 { "ls", 6, {0, {{{0, 0}}}}, 0, 0 },
235 { "le", 7, {0, {{{0, 0}}}}, 0, 0 },
236 { "iret", 8, {0, {{{0, 0}}}}, 0, 0 },
237 { "imask", 9, {0, {{{0, 0}}}}, 0, 0 },
238 { "ilat", 10, {0, {{{0, 0}}}}, 0, 0 },
239 { "ilatst", 11, {0, {{{0, 0}}}}, 0, 0 },
240 { "ilatcl", 12, {0, {{{0, 0}}}}, 0, 0 },
241 { "ipend", 13, {0, {{{0, 0}}}}, 0, 0 },
242 { "ctimer0", 14, {0, {{{0, 0}}}}, 0, 0 },
243 { "ctimer1", 15, {0, {{{0, 0}}}}, 0, 0 },
244 { "hstatus", 16, {0, {{{0, 0}}}}, 0, 0 }
245};
246
247CGEN_KEYWORD epiphany_cgen_opval_cr_names =
248{
249 & epiphany_cgen_opval_cr_names_entries[0],
250 17,
251 0, 0, 0, 0, ""
252};
253
254static CGEN_KEYWORD_ENTRY epiphany_cgen_opval_crdma_names_entries[] =
255{
256 { "dma0config", 0, {0, {{{0, 0}}}}, 0, 0 },
257 { "dma0stride", 1, {0, {{{0, 0}}}}, 0, 0 },
258 { "dma0count", 2, {0, {{{0, 0}}}}, 0, 0 },
259 { "dma0srcaddr", 3, {0, {{{0, 0}}}}, 0, 0 },
260 { "dma0dstaddr", 4, {0, {{{0, 0}}}}, 0, 0 },
261 { "dma0auto0", 5, {0, {{{0, 0}}}}, 0, 0 },
262 { "dma0auto1", 6, {0, {{{0, 0}}}}, 0, 0 },
263 { "dma0status", 7, {0, {{{0, 0}}}}, 0, 0 },
264 { "dma1config", 8, {0, {{{0, 0}}}}, 0, 0 },
265 { "dma1stride", 9, {0, {{{0, 0}}}}, 0, 0 },
266 { "dma1count", 10, {0, {{{0, 0}}}}, 0, 0 },
267 { "dma1srcaddr", 11, {0, {{{0, 0}}}}, 0, 0 },
268 { "dma1dstaddr", 12, {0, {{{0, 0}}}}, 0, 0 },
269 { "dma1auto0", 13, {0, {{{0, 0}}}}, 0, 0 },
270 { "dma1auto1", 14, {0, {{{0, 0}}}}, 0, 0 },
271 { "dma1status", 15, {0, {{{0, 0}}}}, 0, 0 }
272};
273
274CGEN_KEYWORD epiphany_cgen_opval_crdma_names =
275{
276 & epiphany_cgen_opval_crdma_names_entries[0],
277 16,
278 0, 0, 0, 0, ""
279};
280
281static CGEN_KEYWORD_ENTRY epiphany_cgen_opval_crmem_names_entries[] =
282{
283 { "memconfig", 0, {0, {{{0, 0}}}}, 0, 0 },
284 { "memstatus", 1, {0, {{{0, 0}}}}, 0, 0 },
285 { "memprotect", 2, {0, {{{0, 0}}}}, 0, 0 },
286 { "memreserve", 3, {0, {{{0, 0}}}}, 0, 0 }
287};
288
289CGEN_KEYWORD epiphany_cgen_opval_crmem_names =
290{
291 & epiphany_cgen_opval_crmem_names_entries[0],
292 4,
293 0, 0, 0, 0, ""
294};
295
296static CGEN_KEYWORD_ENTRY epiphany_cgen_opval_crmesh_names_entries[] =
297{
298 { "meshconfig", 0, {0, {{{0, 0}}}}, 0, 0 },
299 { "coreid", 1, {0, {{{0, 0}}}}, 0, 0 },
300 { "meshmulticast", 2, {0, {{{0, 0}}}}, 0, 0 },
301 { "swreset", 3, {0, {{{0, 0}}}}, 0, 0 }
302};
303
304CGEN_KEYWORD epiphany_cgen_opval_crmesh_names =
305{
306 & epiphany_cgen_opval_crmesh_names_entries[0],
307 4,
308 0, 0, 0, 0, ""
309};
310
311
312/* The hardware table. */
313
314#define A(a) (1 << CGEN_HW_##a)
315
316const CGEN_HW_ENTRY epiphany_cgen_hw_table[] =
317{
318 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
319 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
320 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
321 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
322 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
323 { "h-registers", HW_H_REGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
324 { "h-fpregisters", HW_H_FPREGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
325 { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
326 { "h-nbit", HW_H_NBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
327 { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
328 { "h-vbit", HW_H_VBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
329 { "h-vsbit", HW_H_VSBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
330 { "h-bzbit", HW_H_BZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
331 { "h-bnbit", HW_H_BNBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
332 { "h-bvbit", HW_H_BVBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
333 { "h-bubit", HW_H_BUBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
334 { "h-bibit", HW_H_BIBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
335 { "h-bcbit", HW_H_BCBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
336 { "h-bvsbit", HW_H_BVSBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
337 { "h-bisbit", HW_H_BISBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
338 { "h-busbit", HW_H_BUSBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
339 { "h-expcause0bit", HW_H_EXPCAUSE0BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
340 { "h-expcause1bit", HW_H_EXPCAUSE1BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
341 { "h-expcause2bit", HW_H_EXPCAUSE2BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
342 { "h-extFstallbit", HW_H_EXTFSTALLBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
343 { "h-trmbit", HW_H_TRMBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
344 { "h-invExcEnbit", HW_H_INVEXCENBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
345 { "h-ovfExcEnbit", HW_H_OVFEXCENBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
346 { "h-unExcEnbit", HW_H_UNEXCENBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
347 { "h-timer0bit0", HW_H_TIMER0BIT0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
348 { "h-timer0bit1", HW_H_TIMER0BIT1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
349 { "h-timer0bit2", HW_H_TIMER0BIT2, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
350 { "h-timer0bit3", HW_H_TIMER0BIT3, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
351 { "h-timer1bit0", HW_H_TIMER1BIT0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
352 { "h-timer1bit1", HW_H_TIMER1BIT1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
353 { "h-timer1bit2", HW_H_TIMER1BIT2, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
354 { "h-timer1bit3", HW_H_TIMER1BIT3, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
355 { "h-mbkptEnbit", HW_H_MBKPTENBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
356 { "h-clockGateEnbit", HW_H_CLOCKGATEENBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
357 { "h-coreCfgResBit12", HW_H_CORECFGRESBIT12, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
358 { "h-coreCfgResBit13", HW_H_CORECFGRESBIT13, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
359 { "h-coreCfgResBit14", HW_H_CORECFGRESBIT14, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
360 { "h-coreCfgResBit15", HW_H_CORECFGRESBIT15, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
361 { "h-coreCfgResBit16", HW_H_CORECFGRESBIT16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
362 { "h-coreCfgResBit20", HW_H_CORECFGRESBIT20, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
363 { "h-coreCfgResBit21", HW_H_CORECFGRESBIT21, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
364 { "h-coreCfgResBit24", HW_H_CORECFGRESBIT24, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
365 { "h-coreCfgResBit25", HW_H_CORECFGRESBIT25, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
366 { "h-coreCfgResBit26", HW_H_CORECFGRESBIT26, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
367 { "h-coreCfgResBit27", HW_H_CORECFGRESBIT27, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
368 { "h-coreCfgResBit28", HW_H_CORECFGRESBIT28, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
369 { "h-coreCfgResBit29", HW_H_CORECFGRESBIT29, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
370 { "h-coreCfgResBit30", HW_H_CORECFGRESBIT30, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
371 { "h-coreCfgResBit31", HW_H_CORECFGRESBIT31, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
372 { "h-arithmetic-modebit0", HW_H_ARITHMETIC_MODEBIT0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
373 { "h-arithmetic-modebit1", HW_H_ARITHMETIC_MODEBIT1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
374 { "h-arithmetic-modebit2", HW_H_ARITHMETIC_MODEBIT2, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
375 { "h-gidisablebit", HW_H_GIDISABLEBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
376 { "h-kmbit", HW_H_KMBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
377 { "h-caibit", HW_H_CAIBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
378 { "h-sflagbit", HW_H_SFLAGBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
379 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
380 { "h-memaddr", HW_H_MEMADDR, CGEN_ASM_NONE, 0, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
381 { "h-core-registers", HW_H_CORE_REGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
382 { "h-coredma-registers", HW_H_COREDMA_REGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_crdma_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
383 { "h-coremem-registers", HW_H_COREMEM_REGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_crmem_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
384 { "h-coremesh-registers", HW_H_COREMESH_REGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_crmesh_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
385 { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
386};
387
388#undef A
389
390
391/* The instruction field table. */
392
393#define A(a) (1 << CGEN_IFLD_##a)
394
395const CGEN_IFLD epiphany_cgen_ifld_table[] =
396{
397 { EPIPHANY_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
398 { EPIPHANY_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
399 { EPIPHANY_F_OPC, "f-opc", 0, 32, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
400 { EPIPHANY_F_OPC_4_1, "f-opc-4-1", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
401 { EPIPHANY_F_OPC_6_3, "f-opc-6-3", 0, 32, 6, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
402 { EPIPHANY_F_OPC_8_5, "f-opc-8-5", 0, 32, 8, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
403 { EPIPHANY_F_OPC_19_4, "f-opc-19-4", 0, 32, 19, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
404 { EPIPHANY_F_CONDCODE, "f-condcode", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
405 { EPIPHANY_F_SECONDARY_CCS, "f-secondary-ccs", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
406 { EPIPHANY_F_SHIFT, "f-shift", 0, 32, 9, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
407 { EPIPHANY_F_WORDSIZE, "f-wordsize", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
408 { EPIPHANY_F_STORE, "f-store", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
409 { EPIPHANY_F_OPC_8_1, "f-opc-8-1", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
410 { EPIPHANY_F_OPC_31_32, "f-opc-31-32", 0, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } } } } },
411 { EPIPHANY_F_SIMM8, "f-simm8", 0, 32, 15, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
412 { EPIPHANY_F_SIMM24, "f-simm24", 0, 32, 31, 24, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
413 { EPIPHANY_F_SDISP3, "f-sdisp3", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
414 { EPIPHANY_F_DISP3, "f-disp3", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
415 { EPIPHANY_F_DISP8, "f-disp8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
416 { EPIPHANY_F_IMM8, "f-imm8", 0, 32, 12, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
417 { EPIPHANY_F_IMM_27_8, "f-imm-27-8", 0, 32, 27, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
418 { EPIPHANY_F_ADDSUBX, "f-addsubx", 0, 32, 20, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
419 { EPIPHANY_F_SUBD, "f-subd", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
420 { EPIPHANY_F_PM, "f-pm", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
421 { EPIPHANY_F_RM, "f-rm", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
422 { EPIPHANY_F_RN, "f-rn", 0, 32, 12, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
423 { EPIPHANY_F_RD, "f-rd", 0, 32, 15, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
424 { EPIPHANY_F_RM_X, "f-rm-x", 0, 32, 25, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
425 { EPIPHANY_F_RN_X, "f-rn-x", 0, 32, 28, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
426 { EPIPHANY_F_RD_X, "f-rd-x", 0, 32, 31, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
427 { EPIPHANY_F_DC_9_1, "f-dc-9-1", 0, 32, 9, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
428 { EPIPHANY_F_SN, "f-sn", 0, 32, 12, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
429 { EPIPHANY_F_SD, "f-sd", 0, 32, 15, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
430 { EPIPHANY_F_SN_X, "f-sn-x", 0, 32, 28, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
431 { EPIPHANY_F_SD_X, "f-sd-x", 0, 32, 31, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
432 { EPIPHANY_F_DC_7_4, "f-dc-7-4", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
433 { EPIPHANY_F_TRAP_SWI_9_1, "f-trap-swi-9-1", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
434 { EPIPHANY_F_GIEN_GIDIS_9_1, "f-gien-gidis-9-1", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
435 { EPIPHANY_F_DC_15_3, "f-dc-15-3", 0, 32, 15, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
436 { EPIPHANY_F_DC_15_7, "f-dc-15-7", 0, 32, 15, 7, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
437 { EPIPHANY_F_DC_15_6, "f-dc-15-6", 0, 32, 15, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } },
438 { EPIPHANY_F_TRAP_NUM, "f-trap-num", 0, 32, 15, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } },
439 { EPIPHANY_F_DC_20_1, "f-dc-20-1", 0, 32, 20, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
440 { EPIPHANY_F_DC_21_1, "f-dc-21-1", 0, 32, 21, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
441 { EPIPHANY_F_DC_21_2, "f-dc-21-2", 0, 32, 21, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
442 { EPIPHANY_F_DC_22_3, "f-dc-22-3", 0, 32, 22, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
443 { EPIPHANY_F_DC_22_2, "f-dc-22-2", 0, 32, 22, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
444 { EPIPHANY_F_DC_22_1, "f-dc-22-1", 0, 32, 22, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
445 { EPIPHANY_F_DC_25_6, "f-dc-25-6", 0, 32, 25, 6, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
446 { EPIPHANY_F_DC_25_4, "f-dc-25-4", 0, 32, 25, 4, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
447 { EPIPHANY_F_DC_25_2, "f-dc-25-2", 0, 32, 25, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
448 { EPIPHANY_F_DC_25_1, "f-dc-25-1", 0, 32, 25, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
449 { EPIPHANY_F_DC_28_1, "f-dc-28-1", 0, 32, 28, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
450 { EPIPHANY_F_DC_31_3, "f-dc-31-3", 0, 32, 31, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
451 { EPIPHANY_F_DISP11, "f-disp11", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
452 { EPIPHANY_F_SDISP11, "f-sdisp11", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
453 { EPIPHANY_F_IMM16, "f-imm16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
454 { EPIPHANY_F_RD6, "f-rd6", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
455 { EPIPHANY_F_RN6, "f-rn6", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
456 { EPIPHANY_F_RM6, "f-rm6", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
457 { EPIPHANY_F_SD6, "f-sd6", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
458 { EPIPHANY_F_SN6, "f-sn6", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
459 { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
460};
461
462#undef A
463
464
465
466/* multi ifield declarations */
467
468const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_DISP11_MULTI_IFIELD [];
469const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SDISP11_MULTI_IFIELD [];
470const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_IMM16_MULTI_IFIELD [];
471const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RD6_MULTI_IFIELD [];
472const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RN6_MULTI_IFIELD [];
473const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RM6_MULTI_IFIELD [];
474const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SD6_MULTI_IFIELD [];
475const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SN6_MULTI_IFIELD [];
476
477
478/* multi ifield definitions */
479
480const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_DISP11_MULTI_IFIELD [] =
481{
482 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP3] } },
483 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP8] } },
484 { 0, { (const PTR) 0 } }
485};
486const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SDISP11_MULTI_IFIELD [] =
487{
488 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP3] } },
489 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP8] } },
490 { 0, { (const PTR) 0 } }
491};
492const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_IMM16_MULTI_IFIELD [] =
493{
494 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_IMM8] } },
495 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_IMM_27_8] } },
496 { 0, { (const PTR) 0 } }
497};
498const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RD6_MULTI_IFIELD [] =
499{
500 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD_X] } },
501 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } },
502 { 0, { (const PTR) 0 } }
503};
504const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RN6_MULTI_IFIELD [] =
505{
506 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN_X] } },
507 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } },
508 { 0, { (const PTR) 0 } }
509};
510const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RM6_MULTI_IFIELD [] =
511{
512 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM_X] } },
513 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } },
514 { 0, { (const PTR) 0 } }
515};
516const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SD6_MULTI_IFIELD [] =
517{
518 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SD_X] } },
519 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SD] } },
520 { 0, { (const PTR) 0 } }
521};
522const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SN6_MULTI_IFIELD [] =
523{
524 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SN_X] } },
525 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SN] } },
526 { 0, { (const PTR) 0 } }
527};
528
529/* The operand table. */
530
531#define A(a) (1 << CGEN_OPERAND_##a)
532#define OPERAND(op) EPIPHANY_OPERAND_##op
533
534const CGEN_OPERAND epiphany_cgen_operand_table[] =
535{
536/* pc: program counter */
537 { "pc", EPIPHANY_OPERAND_PC, HW_H_PC, 0, 0,
43e65147 538 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_NIL] } },
cfb8c092
NC		 539 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
540/* zbit: integer zero bit */
541 { "zbit", EPIPHANY_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
43e65147 542 { 0, { (const PTR) 0 } },
cfb8c092
NC		 543 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
544/* nbit: integer neg bit */
545 { "nbit", EPIPHANY_OPERAND_NBIT, HW_H_NBIT, 0, 0,
43e65147 546 { 0, { (const PTR) 0 } },
cfb8c092
NC		 547 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
548/* cbit: integer carry bit */
549 { "cbit", EPIPHANY_OPERAND_CBIT, HW_H_CBIT, 0, 0,
43e65147 550 { 0, { (const PTR) 0 } },
cfb8c092
NC		 551 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
552/* vbit: integer overflow bit */
553 { "vbit", EPIPHANY_OPERAND_VBIT, HW_H_VBIT, 0, 0,
43e65147 554 { 0, { (const PTR) 0 } },
cfb8c092
NC		 555 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
556/* bzbit: floating point zero bit */
557 { "bzbit", EPIPHANY_OPERAND_BZBIT, HW_H_BZBIT, 0, 0,
43e65147 558 { 0, { (const PTR) 0 } },
cfb8c092
NC		 559 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
560/* bnbit: floating point neg bit */
561 { "bnbit", EPIPHANY_OPERAND_BNBIT, HW_H_BNBIT, 0, 0,
43e65147 562 { 0, { (const PTR) 0 } },
cfb8c092
NC		 563 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
564/* bvbit: floating point ovfl bit */
565 { "bvbit", EPIPHANY_OPERAND_BVBIT, HW_H_BVBIT, 0, 0,
43e65147 566 { 0, { (const PTR) 0 } },
cfb8c092
NC		 567 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
568/* bcbit: floating point carry bit */
569 { "bcbit", EPIPHANY_OPERAND_BCBIT, HW_H_BCBIT, 0, 0,
43e65147 570 { 0, { (const PTR) 0 } },
cfb8c092
NC		 571 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
572/* bubit: floating point underfl bit */
573 { "bubit", EPIPHANY_OPERAND_BUBIT, HW_H_BUBIT, 0, 0,
43e65147 574 { 0, { (const PTR) 0 } },
cfb8c092
NC		 575 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
576/* bibit: floating point invalid bit */
577 { "bibit", EPIPHANY_OPERAND_BIBIT, HW_H_BIBIT, 0, 0,
43e65147 578 { 0, { (const PTR) 0 } },
cfb8c092
NC		 579 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
580/* vsbit: integer overflow sticky */
581 { "vsbit", EPIPHANY_OPERAND_VSBIT, HW_H_VSBIT, 0, 0,
43e65147 582 { 0, { (const PTR) 0 } },
cfb8c092
NC		 583 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
584/* bvsbit: floating point overflow sticky */
585 { "bvsbit", EPIPHANY_OPERAND_BVSBIT, HW_H_BVSBIT, 0, 0,
43e65147 586 { 0, { (const PTR) 0 } },
cfb8c092
NC		 587 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
588/* bisbit: floating point invalid sticky */
589 { "bisbit", EPIPHANY_OPERAND_BISBIT, HW_H_BISBIT, 0, 0,
43e65147 590 { 0, { (const PTR) 0 } },
cfb8c092
NC		 591 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
592/* busbit: floating point underflow sticky */
593 { "busbit", EPIPHANY_OPERAND_BUSBIT, HW_H_BUSBIT, 0, 0,
43e65147 594 { 0, { (const PTR) 0 } },
cfb8c092
NC		 595 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
596/* expcause0bit: exceprion cause bit0 */
597 { "expcause0bit", EPIPHANY_OPERAND_EXPCAUSE0BIT, HW_H_EXPCAUSE0BIT, 0, 0,
43e65147 598 { 0, { (const PTR) 0 } },
cfb8c092
NC		 599 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
600/* expcause1bit: exceprion cause bit1 */
601 { "expcause1bit", EPIPHANY_OPERAND_EXPCAUSE1BIT, HW_H_EXPCAUSE1BIT, 0, 0,
43e65147 602 { 0, { (const PTR) 0 } },
cfb8c092
NC		 603 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
604/* expcause2bit: external load stalled bit */
605 { "expcause2bit", EPIPHANY_OPERAND_EXPCAUSE2BIT, HW_H_EXPCAUSE2BIT, 0, 0,
43e65147 606 { 0, { (const PTR) 0 } },
cfb8c092
NC		 607 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
608/* extFstallbit: external fetch stalled bit */
609 { "extFstallbit", EPIPHANY_OPERAND_EXTFSTALLBIT, HW_H_EXTFSTALLBIT, 0, 0,
43e65147 610 { 0, { (const PTR) 0 } },
cfb8c092
NC		 611 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
612/* trmbit: 0=round to nearest, 1=trunacte selct bit */
613 { "trmbit", EPIPHANY_OPERAND_TRMBIT, HW_H_TRMBIT, 0, 0,
43e65147 614 { 0, { (const PTR) 0 } },
cfb8c092
NC		 615 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
616/* invExcEnbit: invalid exception enable bit */
617 { "invExcEnbit", EPIPHANY_OPERAND_INVEXCENBIT, HW_H_INVEXCENBIT, 0, 0,
43e65147 618 { 0, { (const PTR) 0 } },
cfb8c092
NC		 619 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
620/* ovfExcEnbit: overflow exception enable bit */
621 { "ovfExcEnbit", EPIPHANY_OPERAND_OVFEXCENBIT, HW_H_OVFEXCENBIT, 0, 0,
43e65147 622 { 0, { (const PTR) 0 } },
cfb8c092
NC		 623 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
624/* unExcEnbit: underflow exception enable bit */
625 { "unExcEnbit", EPIPHANY_OPERAND_UNEXCENBIT, HW_H_UNEXCENBIT, 0, 0,
43e65147 626 { 0, { (const PTR) 0 } },
cfb8c092
NC		 627 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
628/* timer0bit0: timer 0 mode selection 0 */
629 { "timer0bit0", EPIPHANY_OPERAND_TIMER0BIT0, HW_H_TIMER0BIT0, 0, 0,
43e65147 630 { 0, { (const PTR) 0 } },
cfb8c092
NC		 631 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
632/* timer0bit1: timer 0 mode selection 1 */
633 { "timer0bit1", EPIPHANY_OPERAND_TIMER0BIT1, HW_H_TIMER0BIT1, 0, 0,
43e65147 634 { 0, { (const PTR) 0 } },
cfb8c092
NC		 635 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
636/* timer0bit2: timer 0 mode selection 2 */
637 { "timer0bit2", EPIPHANY_OPERAND_TIMER0BIT2, HW_H_TIMER0BIT2, 0, 0,
43e65147 638 { 0, { (const PTR) 0 } },
cfb8c092
NC		 639 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
640/* timer0bit3: timer 0 mode selection 3 */
641 { "timer0bit3", EPIPHANY_OPERAND_TIMER0BIT3, HW_H_TIMER0BIT3, 0, 0,
43e65147 642 { 0, { (const PTR) 0 } },
cfb8c092
NC		 643 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
644/* timer1bit0: timer 1 mode selection 0 */
645 { "timer1bit0", EPIPHANY_OPERAND_TIMER1BIT0, HW_H_TIMER1BIT0, 0, 0,
43e65147 646 { 0, { (const PTR) 0 } },
cfb8c092
NC		 647 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
648/* timer1bit1: timer 1 mode selection 1 */
649 { "timer1bit1", EPIPHANY_OPERAND_TIMER1BIT1, HW_H_TIMER1BIT1, 0, 0,
43e65147 650 { 0, { (const PTR) 0 } },
cfb8c092
NC		 651 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
652/* timer1bit2: timer 1 mode selection 2 */
653 { "timer1bit2", EPIPHANY_OPERAND_TIMER1BIT2, HW_H_TIMER1BIT2, 0, 0,
43e65147 654 { 0, { (const PTR) 0 } },
cfb8c092
NC		 655 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
656/* timer1bit3: timer 1 mode selection 3 */
657 { "timer1bit3", EPIPHANY_OPERAND_TIMER1BIT3, HW_H_TIMER1BIT3, 0, 0,
43e65147 658 { 0, { (const PTR) 0 } },
cfb8c092
NC		 659 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
660/* mbkptEnbit: multicore bkpt enable */
661 { "mbkptEnbit", EPIPHANY_OPERAND_MBKPTENBIT, HW_H_MBKPTENBIT, 0, 0,
43e65147 662 { 0, { (const PTR) 0 } },
cfb8c092
NC		 663 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
664/* clockGateEnbit: clock gate enable enable */
665 { "clockGateEnbit", EPIPHANY_OPERAND_CLOCKGATEENBIT, HW_H_CLOCKGATEENBIT, 0, 0,
43e65147 666 { 0, { (const PTR) 0 } },
cfb8c092
NC		 667 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
668/* arithmetic-modebit0: arithmetic mode bit0 */
669 { "arithmetic-modebit0", EPIPHANY_OPERAND_ARITHMETIC_MODEBIT0, HW_H_ARITHMETIC_MODEBIT0, 0, 0,
43e65147 670 { 0, { (const PTR) 0 } },
cfb8c092
NC		 671 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
672/* arithmetic-modebit1: arithmetic mode bit1 */
673 { "arithmetic-modebit1", EPIPHANY_OPERAND_ARITHMETIC_MODEBIT1, HW_H_ARITHMETIC_MODEBIT1, 0, 0,
43e65147 674 { 0, { (const PTR) 0 } },
cfb8c092
NC		 675 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
676/* arithmetic-modebit2: arithmetic mode bit2 */
677 { "arithmetic-modebit2", EPIPHANY_OPERAND_ARITHMETIC_MODEBIT2, HW_H_ARITHMETIC_MODEBIT2, 0, 0,
43e65147 678 { 0, { (const PTR) 0 } },
cfb8c092
NC		 679 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
680/* coreCfgResBit12: core config bit 12 */
681 { "coreCfgResBit12", EPIPHANY_OPERAND_CORECFGRESBIT12, HW_H_CORECFGRESBIT12, 0, 0,
43e65147 682 { 0, { (const PTR) 0 } },
cfb8c092
NC		 683 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
684/* coreCfgResBit13: core config bit 13 */
685 { "coreCfgResBit13", EPIPHANY_OPERAND_CORECFGRESBIT13, HW_H_CORECFGRESBIT13, 0, 0,
43e65147 686 { 0, { (const PTR) 0 } },
cfb8c092
NC		 687 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
688/* coreCfgResBit14: core config bit 14 */
689 { "coreCfgResBit14", EPIPHANY_OPERAND_CORECFGRESBIT14, HW_H_CORECFGRESBIT14, 0, 0,
43e65147 690 { 0, { (const PTR) 0 } },
cfb8c092
NC		 691 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
692/* coreCfgResBit15: core config bit 15 */
693 { "coreCfgResBit15", EPIPHANY_OPERAND_CORECFGRESBIT15, HW_H_CORECFGRESBIT15, 0, 0,
43e65147 694 { 0, { (const PTR) 0 } },
cfb8c092
NC		 695 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
696/* coreCfgResBit16: core config bit 16 */
697 { "coreCfgResBit16", EPIPHANY_OPERAND_CORECFGRESBIT16, HW_H_CORECFGRESBIT16, 0, 0,
43e65147 698 { 0, { (const PTR) 0 } },
cfb8c092
NC		 699 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
700/* coreCfgResBit20: core config bit 20 */
701 { "coreCfgResBit20", EPIPHANY_OPERAND_CORECFGRESBIT20, HW_H_CORECFGRESBIT20, 0, 0,
43e65147 702 { 0, { (const PTR) 0 } },
cfb8c092
NC		 703 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
704/* coreCfgResBit21: core config bit 21 */
705 { "coreCfgResBit21", EPIPHANY_OPERAND_CORECFGRESBIT21, HW_H_CORECFGRESBIT21, 0, 0,
43e65147 706 { 0, { (const PTR) 0 } },
cfb8c092
NC		 707 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
708/* coreCfgResBit24: core config bit 24 */
709 { "coreCfgResBit24", EPIPHANY_OPERAND_CORECFGRESBIT24, HW_H_CORECFGRESBIT24, 0, 0,
43e65147 710 { 0, { (const PTR) 0 } },
cfb8c092
NC		 711 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
712/* coreCfgResBit25: core config bit 25 */
713 { "coreCfgResBit25", EPIPHANY_OPERAND_CORECFGRESBIT25, HW_H_CORECFGRESBIT25, 0, 0,
43e65147 714 { 0, { (const PTR) 0 } },
cfb8c092
NC		 715 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
716/* coreCfgResBit26: core config bit 26 */
717 { "coreCfgResBit26", EPIPHANY_OPERAND_CORECFGRESBIT26, HW_H_CORECFGRESBIT26, 0, 0,
43e65147 718 { 0, { (const PTR) 0 } },
cfb8c092
NC		 719 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
720/* coreCfgResBit27: core config bit 27 */
721 { "coreCfgResBit27", EPIPHANY_OPERAND_CORECFGRESBIT27, HW_H_CORECFGRESBIT27, 0, 0,
43e65147 722 { 0, { (const PTR) 0 } },
cfb8c092
NC		 723 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
724/* coreCfgResBit28: core config bit 28 */
725 { "coreCfgResBit28", EPIPHANY_OPERAND_CORECFGRESBIT28, HW_H_CORECFGRESBIT28, 0, 0,
43e65147 726 { 0, { (const PTR) 0 } },
cfb8c092
NC		 727 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
728/* coreCfgResBit29: core config bit 29 */
729 { "coreCfgResBit29", EPIPHANY_OPERAND_CORECFGRESBIT29, HW_H_CORECFGRESBIT29, 0, 0,
43e65147 730 { 0, { (const PTR) 0 } },
cfb8c092
NC		 731 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
732/* coreCfgResBit30: core config bit 30 */
733 { "coreCfgResBit30", EPIPHANY_OPERAND_CORECFGRESBIT30, HW_H_CORECFGRESBIT30, 0, 0,
43e65147 734 { 0, { (const PTR) 0 } },
cfb8c092
NC		 735 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
736/* coreCfgResBit31: core config bit 31 */
737 { "coreCfgResBit31", EPIPHANY_OPERAND_CORECFGRESBIT31, HW_H_CORECFGRESBIT31, 0, 0,
43e65147 738 { 0, { (const PTR) 0 } },
cfb8c092
NC		 739 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
740/* gidisablebit: global interrupt disable bit */
741 { "gidisablebit", EPIPHANY_OPERAND_GIDISABLEBIT, HW_H_GIDISABLEBIT, 0, 0,
43e65147 742 { 0, { (const PTR) 0 } },
cfb8c092
NC		 743 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
744/* kmbit: kernel mode bit */
745 { "kmbit", EPIPHANY_OPERAND_KMBIT, HW_H_KMBIT, 0, 0,
43e65147 746 { 0, { (const PTR) 0 } },
cfb8c092
NC		 747 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
748/* caibit: core actibe indicator bit */
749 { "caibit", EPIPHANY_OPERAND_CAIBIT, HW_H_CAIBIT, 0, 0,
43e65147 750 { 0, { (const PTR) 0 } },
cfb8c092
NC		 751 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
752/* sflagbit: sflag bit */
753 { "sflagbit", EPIPHANY_OPERAND_SFLAGBIT, HW_H_SFLAGBIT, 0, 0,
43e65147 754 { 0, { (const PTR) 0 } },
cfb8c092
NC		 755 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
756/* memaddr: memory effective address */
757 { "memaddr", EPIPHANY_OPERAND_MEMADDR, HW_H_MEMADDR, 0, 0,
43e65147 758 { 0, { (const PTR) 0 } },
cfb8c092
NC		 759 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
760/* simm24: branch address pc-relative */
761 { "simm24", EPIPHANY_OPERAND_SIMM24, HW_H_IADDR, 31, 24,
43e65147 762 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SIMM24] } },
cfb8c092
NC		 763 { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
764/* simm8: branch address pc-relative */
765 { "simm8", EPIPHANY_OPERAND_SIMM8, HW_H_IADDR, 15, 8,
43e65147 766 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SIMM8] } },
cfb8c092
NC		 767 { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
768/* rd: destination register */
769 { "rd", EPIPHANY_OPERAND_RD, HW_H_REGISTERS, 15, 3,
43e65147 770 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } },
cfb8c092
NC		 771 { 0, { { { (1<<MACH_BASE), 0 } } } } },
772/* rn: source register */
773 { "rn", EPIPHANY_OPERAND_RN, HW_H_REGISTERS, 12, 3,
43e65147 774 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } },
cfb8c092
NC		 775 { 0, { { { (1<<MACH_BASE), 0 } } } } },
776/* rm: source register */
777 { "rm", EPIPHANY_OPERAND_RM, HW_H_REGISTERS, 9, 3,
43e65147 778 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } },
cfb8c092
NC		 779 { 0, { { { (1<<MACH_BASE), 0 } } } } },
780/* frd: fp destination register */
781 { "frd", EPIPHANY_OPERAND_FRD, HW_H_FPREGISTERS, 15, 3,
43e65147 782 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } },
cfb8c092
NC		 783 { 0, { { { (1<<MACH_BASE), 0 } } } } },
784/* frn: fp source register */
785 { "frn", EPIPHANY_OPERAND_FRN, HW_H_FPREGISTERS, 12, 3,
43e65147 786 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } },
cfb8c092
NC		 787 { 0, { { { (1<<MACH_BASE), 0 } } } } },
788/* frm: fp source register */
789 { "frm", EPIPHANY_OPERAND_FRM, HW_H_FPREGISTERS, 9, 3,
43e65147 790 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } },
cfb8c092
NC		 791 { 0, { { { (1<<MACH_BASE), 0 } } } } },
792/* rd6: destination register */
793 { "rd6", EPIPHANY_OPERAND_RD6, HW_H_REGISTERS, 15, 6,
43e65147 794 { 2, { (const PTR) &EPIPHANY_F_RD6_MULTI_IFIELD[0] } },
cfb8c092
NC		 795 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
796/* rn6: source register */
797 { "rn6", EPIPHANY_OPERAND_RN6, HW_H_REGISTERS, 12, 6,
43e65147 798 { 2, { (const PTR) &EPIPHANY_F_RN6_MULTI_IFIELD[0] } },
cfb8c092
NC		 799 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
800/* rm6: source register */
801 { "rm6", EPIPHANY_OPERAND_RM6, HW_H_REGISTERS, 9, 6,
43e65147 802 { 2, { (const PTR) &EPIPHANY_F_RM6_MULTI_IFIELD[0] } },
cfb8c092
NC		 803 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
804/* frd6: fp destination register */
805 { "frd6", EPIPHANY_OPERAND_FRD6, HW_H_FPREGISTERS, 15, 6,
43e65147 806 { 2, { (const PTR) &EPIPHANY_F_RD6_MULTI_IFIELD[0] } },
cfb8c092
NC		 807 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
808/* frn6: fp source register */
809 { "frn6", EPIPHANY_OPERAND_FRN6, HW_H_FPREGISTERS, 12, 6,
43e65147 810 { 2, { (const PTR) &EPIPHANY_F_RN6_MULTI_IFIELD[0] } },
cfb8c092
NC		 811 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
812/* frm6: fp source register */
813 { "frm6", EPIPHANY_OPERAND_FRM6, HW_H_FPREGISTERS, 9, 6,
43e65147 814 { 2, { (const PTR) &EPIPHANY_F_RM6_MULTI_IFIELD[0] } },
cfb8c092
NC		 815 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
816/* sd: special destination */
817 { "sd", EPIPHANY_OPERAND_SD, HW_H_CORE_REGISTERS, 15, 3,
43e65147 818 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SD] } },
cfb8c092
NC		 819 { 0, { { { (1<<MACH_BASE), 0 } } } } },
820/* sn: special source */
821 { "sn", EPIPHANY_OPERAND_SN, HW_H_CORE_REGISTERS, 12, 3,
43e65147 822 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SN] } },
cfb8c092
NC		 823 { 0, { { { (1<<MACH_BASE), 0 } } } } },
824/* sd6: special destination register */
825 { "sd6", EPIPHANY_OPERAND_SD6, HW_H_CORE_REGISTERS, 15, 6,
43e65147 826 { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
cfb8c092
NC		 827 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
828/* sn6: special source register */
829 { "sn6", EPIPHANY_OPERAND_SN6, HW_H_CORE_REGISTERS, 12, 6,
43e65147 830 { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
cfb8c092
NC		 831 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
832/* sddma: dma register */
833 { "sddma", EPIPHANY_OPERAND_SDDMA, HW_H_COREDMA_REGISTERS, 15, 6,
43e65147 834 { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
cfb8c092
NC		 835 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
836/* sndma: dma register */
837 { "sndma", EPIPHANY_OPERAND_SNDMA, HW_H_COREDMA_REGISTERS, 12, 6,
43e65147 838 { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
cfb8c092
NC		 839 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
840/* sdmem: mem register */
841 { "sdmem", EPIPHANY_OPERAND_SDMEM, HW_H_COREMEM_REGISTERS, 15, 6,
43e65147 842 { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
cfb8c092
NC		 843 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
844/* snmem: mem register */
845 { "snmem", EPIPHANY_OPERAND_SNMEM, HW_H_COREMEM_REGISTERS, 12, 6,
43e65147 846 { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
cfb8c092
NC		 847 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
848/* sdmesh: mesh register */
849 { "sdmesh", EPIPHANY_OPERAND_SDMESH, HW_H_COREMESH_REGISTERS, 15, 6,
43e65147 850 { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
cfb8c092
NC		 851 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
852/* snmesh: mesh register */
853 { "snmesh", EPIPHANY_OPERAND_SNMESH, HW_H_COREMESH_REGISTERS, 12, 6,
43e65147 854 { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
cfb8c092
NC		 855 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
856/* simm3: signed 3-bit literal */
857 { "simm3", EPIPHANY_OPERAND_SIMM3, HW_H_SINT, 9, 3,
43e65147 858 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SDISP3] } },
cfb8c092
NC		 859 { 0|A(RELAX), { { { (1<<MACH_BASE), 0 } } } } },
860/* simm11: signed 11-bit literal */
861 { "simm11", EPIPHANY_OPERAND_SIMM11, HW_H_SINT, 9, 11,
43e65147 862 { 2, { (const PTR) &EPIPHANY_F_SDISP11_MULTI_IFIELD[0] } },
cfb8c092
NC		 863 { 0|A(RELAX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
864/* disp3: short data displacement */
865 { "disp3", EPIPHANY_OPERAND_DISP3, HW_H_UINT, 9, 3,
43e65147 866 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP3] } },
cfb8c092
NC		 867 { 0, { { { (1<<MACH_BASE), 0 } } } } },
868/* trapnum6: parameter for swi or trap */
869 { "trapnum6", EPIPHANY_OPERAND_TRAPNUM6, HW_H_UINT, 15, 6,
43e65147 870 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_TRAP_NUM] } },
cfb8c092
NC		 871 { 0, { { { (1<<MACH_BASE), 0 } } } } },
872/* swi_num: unsigned 6-bit swi# */
873 { "swi_num", EPIPHANY_OPERAND_SWI_NUM, HW_H_UINT, 15, 6,
43e65147 874 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_TRAP_NUM] } },
cfb8c092
NC		 875 { 0, { { { (1<<MACH_BASE), 0 } } } } },
876/* disp11: sign-magnitude data displacement */
877 { "disp11", EPIPHANY_OPERAND_DISP11, HW_H_UINT, 9, 11,
43e65147 878 { 2, { (const PTR) &EPIPHANY_F_DISP11_MULTI_IFIELD[0] } },
cfb8c092
NC		 879 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
880/* shift: immediate shift amount */
881 { "shift", EPIPHANY_OPERAND_SHIFT, HW_H_UINT, 9, 5,
43e65147 882 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SHIFT] } },
cfb8c092
NC		 883 { 0, { { { (1<<MACH_BASE), 0 } } } } },
884/* imm16: 16-bit unsigned literal */
885 { "imm16", EPIPHANY_OPERAND_IMM16, HW_H_ADDR, 12, 16,
43e65147 886 { 2, { (const PTR) &EPIPHANY_F_IMM16_MULTI_IFIELD[0] } },
cfb8c092
NC		 887 { 0|A(RELAX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
888/* imm8: 8-bit unsigned literal */
889 { "imm8", EPIPHANY_OPERAND_IMM8, HW_H_ADDR, 12, 8,
43e65147 890 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_IMM8] } },
cfb8c092
NC		 891 { 0|A(RELAX), { { { (1<<MACH_BASE), 0 } } } } },
892/* direction: +/- indexing */
893 { "direction", EPIPHANY_OPERAND_DIRECTION, HW_H_UINT, 20, 1,
43e65147 894 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_ADDSUBX] } },
cfb8c092
NC		 895 { 0, { { { (1<<MACH_BASE), 0 } } } } },
896/* dpmi: +/- magnitude immediate displacement */
897 { "dpmi", EPIPHANY_OPERAND_DPMI, HW_H_UINT, 24, 1,
43e65147 898 { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SUBD] } },
cfb8c092
NC		 899 { 0, { { { (1<<MACH_BASE), 0 } } } } },
900/* sentinel */
901 { 0, 0, 0, 0, 0,
902 { 0, { (const PTR) 0 } },
903 { 0, { { { (1<<MACH_BASE), 0 } } } } }
904};
905
906#undef A
907
908
909/* The instruction table. */
910
911#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
912#define A(a) (1 << CGEN_INSN_##a)
913
914static const CGEN_IBASE epiphany_cgen_insn_table[MAX_INSNS] =
915{
916 /* Special null first entry.
917 A `num' value of zero is thus invalid.
918 Also, the special `invalid' insn resides here. */
919 { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
920/* beq.s $simm8 */
921 {
922 EPIPHANY_INSN_BEQ16, "beq16", "beq.s", 16,
923 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
924 },
925/* beq.l $simm24 */
926 {
927 EPIPHANY_INSN_BEQ, "beq", "beq.l", 32,
928 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
929 },
930/* bne.s $simm8 */
931 {
932 EPIPHANY_INSN_BNE16, "bne16", "bne.s", 16,
933 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
934 },
935/* bne.l $simm24 */
936 {
937 EPIPHANY_INSN_BNE, "bne", "bne.l", 32,
938 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
939 },
940/* bgtu.s $simm8 */
941 {
942 EPIPHANY_INSN_BGTU16, "bgtu16", "bgtu.s", 16,
943 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
944 },
945/* bgtu.l $simm24 */
946 {
947 EPIPHANY_INSN_BGTU, "bgtu", "bgtu.l", 32,
948 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
949 },
950/* bgteu.s $simm8 */
951 {
952 EPIPHANY_INSN_BGTEU16, "bgteu16", "bgteu.s", 16,
953 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
954 },
955/* bgteu.l $simm24 */
956 {
957 EPIPHANY_INSN_BGTEU, "bgteu", "bgteu.l", 32,
958 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
959 },
960/* blteu.s $simm8 */
961 {
962 EPIPHANY_INSN_BLTEU16, "blteu16", "blteu.s", 16,
963 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
964 },
965/* blteu.l $simm24 */
966 {
967 EPIPHANY_INSN_BLTEU, "blteu", "blteu.l", 32,
968 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
969 },
970/* bltu.s $simm8 */
971 {
972 EPIPHANY_INSN_BLTU16, "bltu16", "bltu.s", 16,
973 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
974 },
975/* bltu.l $simm24 */
976 {
977 EPIPHANY_INSN_BLTU, "bltu", "bltu.l", 32,
978 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
979 },
980/* bgt.s $simm8 */
981 {
982 EPIPHANY_INSN_BGT16, "bgt16", "bgt.s", 16,
983 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
984 },
985/* bgt.l $simm24 */
986 {
987 EPIPHANY_INSN_BGT, "bgt", "bgt.l", 32,
988 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
989 },
990/* bgte.s $simm8 */
991 {
992 EPIPHANY_INSN_BGTE16, "bgte16", "bgte.s", 16,
993 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
994 },
995/* bgte.l $simm24 */
996 {
997 EPIPHANY_INSN_BGTE, "bgte", "bgte.l", 32,
998 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
999 },
1000/* blt.s $simm8 */
1001 {
1002 EPIPHANY_INSN_BLT16, "blt16", "blt.s", 16,
1003 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1004 },
1005/* blt.l $simm24 */
1006 {
1007 EPIPHANY_INSN_BLT, "blt", "blt.l", 32,
1008 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1009 },
1010/* blte.s $simm8 */
1011 {
1012 EPIPHANY_INSN_BLTE16, "blte16", "blte.s", 16,
1013 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1014 },
1015/* blte.l $simm24 */
1016 {
1017 EPIPHANY_INSN_BLTE, "blte", "blte.l", 32,
1018 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1019 },
1020/* bbeq.s $simm8 */
1021 {
1022 EPIPHANY_INSN_BBEQ16, "bbeq16", "bbeq.s", 16,
1023 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1024 },
1025/* bbeq.l $simm24 */
1026 {
1027 EPIPHANY_INSN_BBEQ, "bbeq", "bbeq.l", 32,
1028 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1029 },
1030/* bbne.s $simm8 */
1031 {
1032 EPIPHANY_INSN_BBNE16, "bbne16", "bbne.s", 16,
1033 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1034 },
1035/* bbne.l $simm24 */
1036 {
1037 EPIPHANY_INSN_BBNE, "bbne", "bbne.l", 32,
1038 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1039 },
1040/* bblt.s $simm8 */
1041 {
1042 EPIPHANY_INSN_BBLT16, "bblt16", "bblt.s", 16,
1043 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1044 },
1045/* bblt.l $simm24 */
1046 {
1047 EPIPHANY_INSN_BBLT, "bblt", "bblt.l", 32,
1048 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1049 },
1050/* bblte.s $simm8 */
1051 {
1052 EPIPHANY_INSN_BBLTE16, "bblte16", "bblte.s", 16,
1053 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1054 },
1055/* bblte.l $simm24 */
1056 {
1057 EPIPHANY_INSN_BBLTE, "bblte", "bblte.l", 32,
1058 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1059 },
1060/* b.s $simm8 */
1061 {
1062 EPIPHANY_INSN_B16, "b16", "b.s", 16,
1063 { 0|A(SHORT_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1064 },
1065/* b.l $simm24 */
1066 {
1067 EPIPHANY_INSN_B, "b", "b.l", 32,
1068 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1069 },
1070/* bl.s $simm8 */
1071 {
1072 EPIPHANY_INSN_BL16, "bl16", "bl.s", 16,
1073 { 0|A(SHORT_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1074 },
1075/* bl.l $simm24 */
1076 {
1077 EPIPHANY_INSN_BL, "bl", "bl.l", 32,
1078 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1079 },
1080/* jr $rn */
1081 {
1082 EPIPHANY_INSN_JR16, "jr16", "jr", 16,
1083 { 0|A(SHORT_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1084 },
1085/* rts */
1086 {
1087 -1, "rts", "rts", 32,
1088 { 0|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
1089 },
1090/* jr $rn6 */
1091 {
1092 EPIPHANY_INSN_JR, "jr", "jr", 32,
1093 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1094 },
1095/* jalr $rn */
1096 {
1097 EPIPHANY_INSN_JALR16, "jalr16", "jalr", 16,
1098 { 0|A(SHORT_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1099 },
1100/* jalr $rn6 */
1101 {
1102 EPIPHANY_INSN_JALR, "jalr", "jalr", 32,
1103 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1104 },
1105/* ldrb $rd,[$rn,$rm] */
1106 {
1107 EPIPHANY_INSN_LDRBX16_S, "ldrbx16.s", "ldrb", 16,
1108 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1109 },
1110/* ldrb $rd,[$rn],$rm */
1111 {
1112 EPIPHANY_INSN_LDRBP16_S, "ldrbp16.s", "ldrb", 16,
1113 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1114 },
1115/* ldrb $rd6,[$rn6,$direction$rm6] */
1116 {
1117 EPIPHANY_INSN_LDRBX_L, "ldrbx.l", "ldrb", 32,
1118 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1119 },
1120/* ldrb $rd6,[$rn6],$direction$rm6 */
1121 {
1122 EPIPHANY_INSN_LDRBP_L, "ldrbp.l", "ldrb", 32,
1123 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1124 },
1125/* ldrb $rd,[$rn,$disp3] */
1126 {
1127 EPIPHANY_INSN_LDRBD16_S, "ldrbd16.s", "ldrb", 16,
1128 { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1129 },
1130/* ldrb $rd6,[$rn6,$dpmi$disp11] */
1131 {
1132 EPIPHANY_INSN_LDRBD_L, "ldrbd.l", "ldrb", 32,
1133 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1134 },
1135/* ldrb $rd6,[$rn6],$dpmi$disp11 */
1136 {
1137 EPIPHANY_INSN_LDRBDPM_L, "ldrbdpm.l", "ldrb", 32,
1138 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1139 },
1140/* ldrh $rd,[$rn,$rm] */
1141 {
1142 EPIPHANY_INSN_LDRHX16_S, "ldrhx16.s", "ldrh", 16,
1143 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1144 },
1145/* ldrh $rd,[$rn],$rm */
1146 {
1147 EPIPHANY_INSN_LDRHP16_S, "ldrhp16.s", "ldrh", 16,
1148 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1149 },
1150/* ldrh $rd6,[$rn6,$direction$rm6] */
1151 {
1152 EPIPHANY_INSN_LDRHX_L, "ldrhx.l", "ldrh", 32,
1153 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1154 },
1155/* ldrh $rd6,[$rn6],$direction$rm6 */
1156 {
1157 EPIPHANY_INSN_LDRHP_L, "ldrhp.l", "ldrh", 32,
1158 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1159 },
1160/* ldrh $rd,[$rn,$disp3] */
1161 {
1162 EPIPHANY_INSN_LDRHD16_S, "ldrhd16.s", "ldrh", 16,
1163 { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1164 },
1165/* ldrh $rd6,[$rn6,$dpmi$disp11] */
1166 {
1167 EPIPHANY_INSN_LDRHD_L, "ldrhd.l", "ldrh", 32,
1168 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1169 },
1170/* ldrh $rd6,[$rn6],$dpmi$disp11 */
1171 {
1172 EPIPHANY_INSN_LDRHDPM_L, "ldrhdpm.l", "ldrh", 32,
1173 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1174 },
1175/* ldr $rd,[$rn,$rm] */
1176 {
1177 EPIPHANY_INSN_LDRX16_S, "ldrx16.s", "ldr", 16,
1178 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1179 },
1180/* ldr $rd,[$rn],$rm */
1181 {
1182 EPIPHANY_INSN_LDRP16_S, "ldrp16.s", "ldr", 16,
1183 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1184 },
1185/* ldr $rd6,[$rn6,$direction$rm6] */
1186 {
1187 EPIPHANY_INSN_LDRX_L, "ldrx.l", "ldr", 32,
1188 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1189 },
1190/* ldr $rd6,[$rn6],$direction$rm6 */
1191 {
1192 EPIPHANY_INSN_LDRP_L, "ldrp.l", "ldr", 32,
1193 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1194 },
1195/* ldr $rd,[$rn,$disp3] */
1196 {
1197 EPIPHANY_INSN_LDRD16_S, "ldrd16.s", "ldr", 16,
1198 { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1199 },
1200/* ldr $rd6,[$rn6,$dpmi$disp11] */
1201 {
1202 EPIPHANY_INSN_LDRD_L, "ldrd.l", "ldr", 32,
1203 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1204 },
1205/* ldr $rd6,[$rn6],$dpmi$disp11 */
1206 {
1207 EPIPHANY_INSN_LDRDPM_L, "ldrdpm.l", "ldr", 32,
1208 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1209 },
1210/* ldrd $rd,[$rn,$rm] */
1211 {
1212 EPIPHANY_INSN_LDRDX16_S, "ldrdx16.s", "ldrd", 16,
1213 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1214 },
1215/* ldrd $rd,[$rn],$rm */
1216 {
1217 EPIPHANY_INSN_LDRDP16_S, "ldrdp16.s", "ldrd", 16,
1218 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1219 },
1220/* ldrd $rd6,[$rn6,$direction$rm6] */
1221 {
1222 EPIPHANY_INSN_LDRDX_L, "ldrdx.l", "ldrd", 32,
1223 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1224 },
1225/* ldrd $rd6,[$rn6],$direction$rm6 */
1226 {
1227 EPIPHANY_INSN_LDRDP_L, "ldrdp.l", "ldrd", 32,
1228 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1229 },
1230/* ldrd $rd,[$rn,$disp3] */
1231 {
1232 EPIPHANY_INSN_LDRDD16_S, "ldrdd16.s", "ldrd", 16,
1233 { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1234 },
1235/* ldrd $rd6,[$rn6,$dpmi$disp11] */
1236 {
1237 EPIPHANY_INSN_LDRDD_L, "ldrdd.l", "ldrd", 32,
1238 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1239 },
1240/* ldrd $rd6,[$rn6],$dpmi$disp11 */
1241 {
1242 EPIPHANY_INSN_LDRDDPM_L, "ldrddpm.l", "ldrd", 32,
1243 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1244 },
1245/* testsetb $rd6,[$rn6,$direction$rm6] */
1246 {
1247 EPIPHANY_INSN_TESTSETBT, "testsetbt", "testsetb", 32,
1248 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1249 },
1250/* testseth $rd6,[$rn6,$direction$rm6] */
1251 {
1252 EPIPHANY_INSN_TESTSETHT, "testsetht", "testseth", 32,
1253 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1254 },
1255/* testset $rd6,[$rn6,$direction$rm6] */
1256 {
1257 EPIPHANY_INSN_TESTSETT, "testsett", "testset", 32,
1258 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1259 },
1260/* strb $rd,[$rn,$rm] */
1261 {
1262 EPIPHANY_INSN_STRBX16, "strbx16", "strb", 16,
1263 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1264 },
1265/* strb $rd6,[$rn6,$direction$rm6] */
1266 {
1267 EPIPHANY_INSN_STRBX, "strbx", "strb", 32,
1268 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1269 },
1270/* strb $rd,[$rn],$rm */
1271 {
1272 EPIPHANY_INSN_STRBP16, "strbp16", "strb", 16,
1273 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1274 },
1275/* strb $rd6,[$rn6],$direction$rm6 */
1276 {
1277 EPIPHANY_INSN_STRBP, "strbp", "strb", 32,
1278 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1279 },
1280/* strb $rd,[$rn,$disp3] */
1281 {
1282 EPIPHANY_INSN_STRBD16, "strbd16", "strb", 16,
1283 { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1284 },
1285/* strb $rd6,[$rn6,$dpmi$disp11] */
1286 {
1287 EPIPHANY_INSN_STRBD, "strbd", "strb", 32,
1288 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1289 },
1290/* strb $rd6,[$rn6],$dpmi$disp11 */
1291 {
1292 EPIPHANY_INSN_STRBDPM, "strbdpm", "strb", 32,
1293 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1294 },
1295/* strh $rd,[$rn,$rm] */
1296 {
1297 EPIPHANY_INSN_STRHX16, "strhx16", "strh", 16,
1298 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1299 },
1300/* strh $rd6,[$rn6,$direction$rm6] */
1301 {
1302 EPIPHANY_INSN_STRHX, "strhx", "strh", 32,
1303 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1304 },
1305/* strh $rd,[$rn],$rm */
1306 {
1307 EPIPHANY_INSN_STRHP16, "strhp16", "strh", 16,
1308 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1309 },
1310/* strh $rd6,[$rn6],$direction$rm6 */
1311 {
1312 EPIPHANY_INSN_STRHP, "strhp", "strh", 32,
1313 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1314 },
1315/* strh $rd,[$rn,$disp3] */
1316 {
1317 EPIPHANY_INSN_STRHD16, "strhd16", "strh", 16,
1318 { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1319 },
1320/* strh $rd6,[$rn6,$dpmi$disp11] */
1321 {
1322 EPIPHANY_INSN_STRHD, "strhd", "strh", 32,
1323 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1324 },
1325/* strh $rd6,[$rn6],$dpmi$disp11 */
1326 {
1327 EPIPHANY_INSN_STRHDPM, "strhdpm", "strh", 32,
1328 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1329 },
1330/* str $rd,[$rn,$rm] */
1331 {
1332 EPIPHANY_INSN_STRX16, "strx16", "str", 16,
1333 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1334 },
1335/* str $rd6,[$rn6,$direction$rm6] */
1336 {
1337 EPIPHANY_INSN_STRX, "strx", "str", 32,
1338 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1339 },
1340/* str $rd,[$rn],$rm */
1341 {
1342 EPIPHANY_INSN_STRP16, "strp16", "str", 16,
1343 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1344 },
1345/* str $rd6,[$rn6],$direction$rm6 */
1346 {
1347 EPIPHANY_INSN_STRP, "strp", "str", 32,
1348 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1349 },
1350/* str $rd,[$rn,$disp3] */
1351 {
1352 EPIPHANY_INSN_STRD16, "strd16", "str", 16,
1353 { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1354 },
1355/* str $rd6,[$rn6,$dpmi$disp11] */
1356 {
1357 EPIPHANY_INSN_STRD, "strd", "str", 32,
1358 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1359 },
1360/* str $rd6,[$rn6],$dpmi$disp11 */
1361 {
1362 EPIPHANY_INSN_STRDPM, "strdpm", "str", 32,
1363 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1364 },
1365/* strd $rd,[$rn,$rm] */
1366 {
1367 EPIPHANY_INSN_STRDX16, "strdx16", "strd", 16,
1368 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1369 },
1370/* strd $rd6,[$rn6,$direction$rm6] */
1371 {
1372 EPIPHANY_INSN_STRDX, "strdx", "strd", 32,
1373 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1374 },
1375/* strd $rd,[$rn],$rm */
1376 {
1377 EPIPHANY_INSN_STRDP16, "strdp16", "strd", 16,
1378 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1379 },
1380/* strd $rd6,[$rn6],$direction$rm6 */
1381 {
1382 EPIPHANY_INSN_STRDP, "strdp", "strd", 32,
1383 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1384 },
1385/* strd $rd,[$rn,$disp3] */
1386 {
1387 EPIPHANY_INSN_STRDD16, "strdd16", "strd", 16,
1388 { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1389 },
1390/* strd $rd6,[$rn6,$dpmi$disp11] */
1391 {
1392 EPIPHANY_INSN_STRDD, "strdd", "strd", 32,
1393 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1394 },
1395/* strd $rd6,[$rn6],$dpmi$disp11 */
1396 {
1397 EPIPHANY_INSN_STRDDPM, "strddpm", "strd", 32,
1398 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1399 },
1400/* moveq $rd,$rn */
1401 {
1402 EPIPHANY_INSN_CMOV16EQ, "cmov16EQ", "moveq", 16,
1403 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1404 },
1405/* moveq $rd6,$rn6 */
1406 {
1407 EPIPHANY_INSN_CMOVEQ, "cmovEQ", "moveq", 32,
1408 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1409 },
1410/* movne $rd,$rn */
1411 {
1412 EPIPHANY_INSN_CMOV16NE, "cmov16NE", "movne", 16,
1413 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1414 },
1415/* movne $rd6,$rn6 */
1416 {
1417 EPIPHANY_INSN_CMOVNE, "cmovNE", "movne", 32,
1418 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1419 },
1420/* movgtu $rd,$rn */
1421 {
1422 EPIPHANY_INSN_CMOV16GTU, "cmov16GTU", "movgtu", 16,
1423 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1424 },
1425/* movgtu $rd6,$rn6 */
1426 {
1427 EPIPHANY_INSN_CMOVGTU, "cmovGTU", "movgtu", 32,
1428 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1429 },
1430/* movgteu $rd,$rn */
1431 {
1432 EPIPHANY_INSN_CMOV16GTEU, "cmov16GTEU", "movgteu", 16,
1433 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1434 },
1435/* movgteu $rd6,$rn6 */
1436 {
1437 EPIPHANY_INSN_CMOVGTEU, "cmovGTEU", "movgteu", 32,
1438 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1439 },
1440/* movlteu $rd,$rn */
1441 {
1442 EPIPHANY_INSN_CMOV16LTEU, "cmov16LTEU", "movlteu", 16,
1443 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1444 },
1445/* movlteu $rd6,$rn6 */
1446 {
1447 EPIPHANY_INSN_CMOVLTEU, "cmovLTEU", "movlteu", 32,
1448 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1449 },
1450/* movltu $rd,$rn */
1451 {
1452 EPIPHANY_INSN_CMOV16LTU, "cmov16LTU", "movltu", 16,
1453 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1454 },
1455/* movltu $rd6,$rn6 */
1456 {
1457 EPIPHANY_INSN_CMOVLTU, "cmovLTU", "movltu", 32,
1458 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1459 },
1460/* movgt $rd,$rn */
1461 {
1462 EPIPHANY_INSN_CMOV16GT, "cmov16GT", "movgt", 16,
1463 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1464 },
1465/* movgt $rd6,$rn6 */
1466 {
1467 EPIPHANY_INSN_CMOVGT, "cmovGT", "movgt", 32,
1468 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1469 },
1470/* movgte $rd,$rn */
1471 {
1472 EPIPHANY_INSN_CMOV16GTE, "cmov16GTE", "movgte", 16,
1473 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1474 },
1475/* movgte $rd6,$rn6 */
1476 {
1477 EPIPHANY_INSN_CMOVGTE, "cmovGTE", "movgte", 32,
1478 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1479 },
1480/* movlt $rd,$rn */
1481 {
1482 EPIPHANY_INSN_CMOV16LT, "cmov16LT", "movlt", 16,
1483 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1484 },
1485/* movlt $rd6,$rn6 */
1486 {
1487 EPIPHANY_INSN_CMOVLT, "cmovLT", "movlt", 32,
1488 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1489 },
1490/* movlte $rd,$rn */
1491 {
1492 EPIPHANY_INSN_CMOV16LTE, "cmov16LTE", "movlte", 16,
1493 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1494 },
1495/* movlte $rd6,$rn6 */
1496 {
1497 EPIPHANY_INSN_CMOVLTE, "cmovLTE", "movlte", 32,
1498 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1499 },
1500/* mov $rd,$rn */
1501 {
1502 EPIPHANY_INSN_CMOV16B, "cmov16B", "mov", 16,
1503 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1504 },
1505/* mov $rd6,$rn6 */
1506 {
1507 EPIPHANY_INSN_CMOVB, "cmovB", "mov", 32,
1508 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1509 },
1510/* movbeq $rd,$rn */
1511 {
1512 EPIPHANY_INSN_CMOV16BEQ, "cmov16BEQ", "movbeq", 16,
1513 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1514 },
1515/* movbeq $rd6,$rn6 */
1516 {
1517 EPIPHANY_INSN_CMOVBEQ, "cmovBEQ", "movbeq", 32,
1518 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1519 },
1520/* movbne $rd,$rn */
1521 {
1522 EPIPHANY_INSN_CMOV16BNE, "cmov16BNE", "movbne", 16,
1523 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1524 },
1525/* movbne $rd6,$rn6 */
1526 {
1527 EPIPHANY_INSN_CMOVBNE, "cmovBNE", "movbne", 32,
1528 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1529 },
1530/* movblt $rd,$rn */
1531 {
1532 EPIPHANY_INSN_CMOV16BLT, "cmov16BLT", "movblt", 16,
1533 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1534 },
1535/* movblt $rd6,$rn6 */
1536 {
1537 EPIPHANY_INSN_CMOVBLT, "cmovBLT", "movblt", 32,
1538 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1539 },
1540/* movblte $rd,$rn */
1541 {
1542 EPIPHANY_INSN_CMOV16BLTE, "cmov16BLTE", "movblte", 16,
1543 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1544 },
1545/* movblte $rd6,$rn6 */
1546 {
1547 EPIPHANY_INSN_CMOVBLTE, "cmovBLTE", "movblte", 32,
1548 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1549 },
1550/* movts $sn,$rd */
1551 {
1552 EPIPHANY_INSN_MOVTS16, "movts16", "movts", 16,
1553 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1554 },
1555/* movts $sn6,$rd6 */
1556 {
1557 EPIPHANY_INSN_MOVTS6, "movts6", "movts", 32,
1558 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1559 },
1560/* movts $sndma,$rd6 */
1561 {
1562 EPIPHANY_INSN_MOVTSDMA, "movtsdma", "movts", 32,
1563 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1564 },
1565/* movts $snmem,$rd6 */
1566 {
1567 EPIPHANY_INSN_MOVTSMEM, "movtsmem", "movts", 32,
1568 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1569 },
1570/* movts $snmesh,$rd6 */
1571 {
1572 EPIPHANY_INSN_MOVTSMESH, "movtsmesh", "movts", 32,
1573 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1574 },
1575/* movfs $rd,$sn */
1576 {
1577 EPIPHANY_INSN_MOVFS16, "movfs16", "movfs", 16,
1578 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1579 },
1580/* movfs $rd6,$sn6 */
1581 {
1582 EPIPHANY_INSN_MOVFS6, "movfs6", "movfs", 32,
1583 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1584 },
1585/* movfs $rd6,$sndma */
1586 {
1587 EPIPHANY_INSN_MOVFSDMA, "movfsdma", "movfs", 32,
1588 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1589 },
1590/* movfs $rd6,$snmem */
1591 {
1592 EPIPHANY_INSN_MOVFSMEM, "movfsmem", "movfs", 32,
1593 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1594 },
1595/* movfs $rd6,$snmesh */
1596 {
1597 EPIPHANY_INSN_MOVFSMESH, "movfsmesh", "movfs", 32,
1598 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1599 },
1600/* nop */
1601 {
1602 EPIPHANY_INSN_NOP, "nop", "nop", 16,
1603 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1604 },
1605/* snop */
1606 {
1607 EPIPHANY_INSN_SNOP, "snop", "snop", 16,
1608 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1609 },
1610/* unimpl */
1611 {
1612 EPIPHANY_INSN_UNIMPL, "unimpl", "unimpl", 32,
1613 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1614 },
1615/* idle */
1616 {
1617 EPIPHANY_INSN_IDLE, "idle", "idle", 16,
1618 { 0, { { { (1<<MACH_BASE), 0 } } } }
1619 },
1620/* bkpt */
1621 {
1622 EPIPHANY_INSN_BKPT, "bkpt", "bkpt", 16,
1623 { 0|A(SHORT_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1624 },
1625/* mbkpt */
1626 {
1627 EPIPHANY_INSN_MBKPT, "mbkpt", "mbkpt", 16,
1628 { 0|A(SHORT_INSN), { { { (1<<MACH_BASE), 0 } } } }
1629 },
1630/* rti */
1631 {
1632 EPIPHANY_INSN_RTI, "rti", "rti", 16,
1633 { 0|A(UNCOND_CTI)|A(SHORT_INSN), { { { (1<<MACH_BASE), 0 } } } }
1634 },
1635/* wand */
1636 {
1637 EPIPHANY_INSN_WAND, "wand", "wand", 16,
1638 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1639 },
1640/* sync */
1641 {
1642 EPIPHANY_INSN_SYNC, "sync", "sync", 16,
1643 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1644 },
1645/* gie */
1646 {
1647 EPIPHANY_INSN_GIEN, "gien", "gie", 16,
1648 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1649 },
1650/* gid */
1651 {
1652 EPIPHANY_INSN_GIDIS, "gidis", "gid", 16,
1653 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1654 },
1655/* swi $swi_num */
1656 {
1657 EPIPHANY_INSN_SWI_NUM, "swi_num", "swi", 16,
1658 { 0|A(UNCOND_CTI)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1659 },
1660/* swi */
1661 {
1662 -1, "swi", "swi", 16,
1663 { 0|A(UNCOND_CTI)|A(SHORT_INSN)|A(ALIAS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1664 },
1665/* trap $trapnum6 */
1666 {
1667 EPIPHANY_INSN_TRAP16, "trap16", "trap", 16,
1668 { 0|A(UNCOND_CTI)|A(SHORT_INSN), { { { (1<<MACH_BASE), 0 } } } }
1669 },
1670/* add $rd,$rn,$rm */
1671 {
1672 EPIPHANY_INSN_ADD16, "add16", "add", 16,
1673 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1674 },
1675/* add $rd6,$rn6,$rm6 */
1676 {
1677 EPIPHANY_INSN_ADD, "add", "add", 32,
1678 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1679 },
1680/* sub $rd,$rn,$rm */
1681 {
1682 EPIPHANY_INSN_SUB16, "sub16", "sub", 16,
1683 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1684 },
1685/* sub $rd6,$rn6,$rm6 */
1686 {
1687 EPIPHANY_INSN_SUB, "sub", "sub", 32,
1688 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1689 },
1690/* and $rd,$rn,$rm */
1691 {
1692 EPIPHANY_INSN_AND16, "and16", "and", 16,
1693 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1694 },
1695/* and $rd6,$rn6,$rm6 */
1696 {
1697 EPIPHANY_INSN_AND, "and", "and", 32,
1698 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1699 },
1700/* orr $rd,$rn,$rm */
1701 {
1702 EPIPHANY_INSN_ORR16, "orr16", "orr", 16,
1703 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1704 },
1705/* orr $rd6,$rn6,$rm6 */
1706 {
1707 EPIPHANY_INSN_ORR, "orr", "orr", 32,
1708 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1709 },
1710/* eor $rd,$rn,$rm */
1711 {
1712 EPIPHANY_INSN_EOR16, "eor16", "eor", 16,
1713 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1714 },
1715/* eor $rd6,$rn6,$rm6 */
1716 {
1717 EPIPHANY_INSN_EOR, "eor", "eor", 32,
1718 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1719 },
1720/* add.s $rd,$rn,$simm3 */
1721 {
1722 EPIPHANY_INSN_ADDI16, "addi16", "add.s", 16,
1723 { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1724 },
1725/* add.l $rd6,$rn6,$simm11 */
1726 {
1727 EPIPHANY_INSN_ADDI, "addi", "add.l", 32,
1728 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1729 },
1730/* sub.s $rd,$rn,$simm3 */
1731 {
1732 EPIPHANY_INSN_SUBI16, "subi16", "sub.s", 16,
1733 { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1734 },
1735/* sub.l $rd6,$rn6,$simm11 */
1736 {
1737 EPIPHANY_INSN_SUBI, "subi", "sub.l", 32,
1738 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1739 },
1740/* asr $rd,$rn,$rm */
1741 {
1742 EPIPHANY_INSN_ASR16, "asr16", "asr", 16,
1743 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1744 },
1745/* asr $rd6,$rn6,$rm6 */
1746 {
1747 EPIPHANY_INSN_ASR, "asr", "asr", 32,
1748 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1749 },
1750/* lsr $rd,$rn,$rm */
1751 {
1752 EPIPHANY_INSN_LSR16, "lsr16", "lsr", 16,
1753 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1754 },
1755/* lsr $rd6,$rn6,$rm6 */
1756 {
1757 EPIPHANY_INSN_LSR, "lsr", "lsr", 32,
1758 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1759 },
1760/* lsl $rd,$rn,$rm */
1761 {
1762 EPIPHANY_INSN_LSL16, "lsl16", "lsl", 16,
1763 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1764 },
1765/* lsl $rd6,$rn6,$rm6 */
1766 {
1767 EPIPHANY_INSN_LSL, "lsl", "lsl", 32,
1768 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1769 },
1770/* lsr $rd,$rn,$shift */
1771 {
1772 EPIPHANY_INSN_LSRI16, "lsri16", "lsr", 16,
1773 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1774 },
1775/* lsr $rd6,$rn6,$shift */
1776 {
1777 EPIPHANY_INSN_LSRI32, "lsri32", "lsr", 32,
1778 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1779 },
1780/* lsl $rd,$rn,$shift */
1781 {
1782 EPIPHANY_INSN_LSLI16, "lsli16", "lsl", 16,
1783 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1784 },
1785/* lsl $rd6,$rn6,$shift */
1786 {
1787 EPIPHANY_INSN_LSLI32, "lsli32", "lsl", 32,
1788 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1789 },
1790/* asr $rd,$rn,$shift */
1791 {
1792 EPIPHANY_INSN_ASRI16, "asri16", "asr", 16,
1793 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1794 },
1795/* asr $rd6,$rn6,$shift */
1796 {
1797 EPIPHANY_INSN_ASRI32, "asri32", "asr", 32,
1798 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1799 },
1800/* bitr $rd,$rn */
1801 {
1802 EPIPHANY_INSN_BITR16, "bitr16", "bitr", 16,
1803 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1804 },
1805/* bitr $rd6,$rn6 */
1806 {
1807 EPIPHANY_INSN_BITR, "bitr", "bitr", 32,
1808 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1809 },
1810/* fext $rd6,$rn6,$rm6 */
1811 {
1812 EPIPHANY_INSN_FEXT, "fext", "fext", 32,
1813 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1814 },
1815/* fdep $rd6,$rn6,$rm6 */
1816 {
1817 EPIPHANY_INSN_FDEP, "fdep", "fdep", 32,
1818 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1819 },
1820/* lfsr $rd6,$rn6,$rm6 */
1821 {
1822 EPIPHANY_INSN_LFSR, "lfsr", "lfsr", 32,
1823 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1824 },
1825/* mov.b $rd,$imm8 */
1826 {
1827 EPIPHANY_INSN_MOV8, "mov8", "mov.b", 16,
1828 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1829 },
1830/* mov.l $rd6,$imm16 */
1831 {
1832 EPIPHANY_INSN_MOV16, "mov16", "mov.l", 32,
1833 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1834 },
1835/* movt $rd6,$imm16 */
1836 {
1837 EPIPHANY_INSN_MOVT, "movt", "movt", 32,
1838 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1839 },
1840/* fadd $rd,$rn,$rm */
1841 {
1842 EPIPHANY_INSN_F_ADDF16, "f_addf16", "fadd", 16,
1843 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1844 },
1845/* fadd $rd6,$rn6,$rm6 */
1846 {
1847 EPIPHANY_INSN_F_ADDF32, "f_addf32", "fadd", 32,
1848 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1849 },
1850/* fsub $rd,$rn,$rm */
1851 {
1852 EPIPHANY_INSN_F_SUBF16, "f_subf16", "fsub", 16,
1853 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1854 },
1855/* fsub $rd6,$rn6,$rm6 */
1856 {
1857 EPIPHANY_INSN_F_SUBF32, "f_subf32", "fsub", 32,
1858 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1859 },
1860/* fmul $rd,$rn,$rm */
1861 {
1862 EPIPHANY_INSN_F_MULF16, "f_mulf16", "fmul", 16,
1863 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1864 },
1865/* fmul $rd6,$rn6,$rm6 */
1866 {
1867 EPIPHANY_INSN_F_MULF32, "f_mulf32", "fmul", 32,
1868 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1869 },
1870/* fmadd $rd,$rn,$rm */
1871 {
1872 EPIPHANY_INSN_F_MADDF16, "f_maddf16", "fmadd", 16,
1873 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1874 },
1875/* fmadd $rd6,$rn6,$rm6 */
1876 {
1877 EPIPHANY_INSN_F_MADDF32, "f_maddf32", "fmadd", 32,
1878 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1879 },
1880/* fmsub $rd,$rn,$rm */
1881 {
1882 EPIPHANY_INSN_F_MSUBF16, "f_msubf16", "fmsub", 16,
1883 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1884 },
1885/* fmsub $rd6,$rn6,$rm6 */
1886 {
1887 EPIPHANY_INSN_F_MSUBF32, "f_msubf32", "fmsub", 32,
1888 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1889 },
1890/* fabs rd,rn */
1891 {
1892 EPIPHANY_INSN_F_ABSF16, "f_absf16", "fabs", 16,
1893 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1894 },
1895/* fabs $rd6,$rn6 */
1896 {
1897 EPIPHANY_INSN_F_ABSF32, "f_absf32", "fabs", 32,
1898 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1899 },
1900/* float $rd,$rn */
1901 {
1902 EPIPHANY_INSN_F_LOATF16, "f_loatf16", "float", 16,
1903 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1904 },
1905/* float $rd6,$rn6 */
1906 {
1907 EPIPHANY_INSN_F_LOATF32, "f_loatf32", "float", 32,
1908 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1909 },
1910/* fix $rd,$rn */
1911 {
1912 EPIPHANY_INSN_F_IXF16, "f_ixf16", "fix", 16,
1913 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1914 },
1915/* fix $rd6,$rn6 */
1916 {
1917 EPIPHANY_INSN_F_IXF32, "f_ixf32", "fix", 32,
1918 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1919 },
1920/* frecip $frd6,$frn6 */
1921 {
1922 EPIPHANY_INSN_F_RECIPF32, "f_recipf32", "frecip", 32,
1923 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1924 },
1925/* fsqrt $frd6,$frn6 */
1926 {
1927 EPIPHANY_INSN_F_SQRTF32, "f_sqrtf32", "fsqrt", 32,
1928 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1929 },
1930};
1931
1932#undef OP
1933#undef A
1934
1935/* Initialize anything needed to be done once, before any cpu_open call. */
1936
1937static void
1938init_tables (void)
1939{
1940}
1941
a6743a54
AM		 1942#ifndef opcodes_error_handler
1943#define opcodes_error_handler(...) \
1944 fprintf (stderr, __VA_ARGS__); fputc ('\n', stderr)
1945#endif
1946
cfb8c092
NC		 1947static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
1948static void build_hw_table (CGEN_CPU_TABLE *);
1949static void build_ifield_table (CGEN_CPU_TABLE *);
1950static void build_operand_table (CGEN_CPU_TABLE *);
1951static void build_insn_table (CGEN_CPU_TABLE *);
1952static void epiphany_cgen_rebuild_tables (CGEN_CPU_TABLE *);
1953
1954/* Subroutine of epiphany_cgen_cpu_open to look up a mach via its bfd name. */
1955
1956static const CGEN_MACH *
1957lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
1958{
1959 while (table->name)
1960 {
1961 if (strcmp (name, table->bfd_name) == 0)
1962 return table;
1963 ++table;
1964 }
42742084 1965 return NULL;
cfb8c092
NC		 1966}
1967
1968/* Subroutine of epiphany_cgen_cpu_open to build the hardware table. */
1969
1970static void
1971build_hw_table (CGEN_CPU_TABLE *cd)
1972{
1973 int i;
1974 int machs = cd->machs;
1975 const CGEN_HW_ENTRY *init = & epiphany_cgen_hw_table[0];
1976 /* MAX_HW is only an upper bound on the number of selected entries.
1977 However each entry is indexed by it's enum so there can be holes in
1978 the table. */
1979 const CGEN_HW_ENTRY **selected =
1980 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1981
1982 cd->hw_table.init_entries = init;
1983 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1984 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1985 /* ??? For now we just use machs to determine which ones we want. */
1986 for (i = 0; init[i].name != NULL; ++i)
1987 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1988 & machs)
1989 selected[init[i].type] = &init[i];
1990 cd->hw_table.entries = selected;
1991 cd->hw_table.num_entries = MAX_HW;
1992}
1993
1994/* Subroutine of epiphany_cgen_cpu_open to build the hardware table. */
1995
1996static void
1997build_ifield_table (CGEN_CPU_TABLE *cd)
1998{
1999 cd->ifld_table = & epiphany_cgen_ifld_table[0];
2000}
2001
2002/* Subroutine of epiphany_cgen_cpu_open to build the hardware table. */
2003
2004static void
2005build_operand_table (CGEN_CPU_TABLE *cd)
2006{
2007 int i;
2008 int machs = cd->machs;
2009 const CGEN_OPERAND *init = & epiphany_cgen_operand_table[0];
2010 /* MAX_OPERANDS is only an upper bound on the number of selected entries.
2011 However each entry is indexed by it's enum so there can be holes in
2012 the table. */
2013 const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
2014
2015 cd->operand_table.init_entries = init;
2016 cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
2017 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
2018 /* ??? For now we just use mach to determine which ones we want. */
2019 for (i = 0; init[i].name != NULL; ++i)
2020 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
2021 & machs)
2022 selected[init[i].type] = &init[i];
2023 cd->operand_table.entries = selected;
2024 cd->operand_table.num_entries = MAX_OPERANDS;
2025}
2026
2027/* Subroutine of epiphany_cgen_cpu_open to build the hardware table.
2028 ??? This could leave out insns not supported by the specified mach/isa,
2029 but that would cause errors like "foo only supported by bar" to become
2030 "unknown insn", so for now we include all insns and require the app to
2031 do the checking later.
2032 ??? On the other hand, parsing of such insns may require their hardware or
2033 operand elements to be in the table [which they mightn't be]. */
2034
2035static void
2036build_insn_table (CGEN_CPU_TABLE *cd)
2037{
2038 int i;
2039 const CGEN_IBASE *ib = & epiphany_cgen_insn_table[0];
2040 CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
2041
2042 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
2043 for (i = 0; i < MAX_INSNS; ++i)
2044 insns[i].base = &ib[i];
2045 cd->insn_table.init_entries = insns;
2046 cd->insn_table.entry_size = sizeof (CGEN_IBASE);
2047 cd->insn_table.num_init_entries = MAX_INSNS;
2048}
2049
2050/* Subroutine of epiphany_cgen_cpu_open to rebuild the tables. */
2051
2052static void
2053epiphany_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
2054{
2055 int i;
2056 CGEN_BITSET *isas = cd->isas;
2057 unsigned int machs = cd->machs;
2058
2059 cd->int_insn_p = CGEN_INT_INSN_P;
2060
2061 /* Data derived from the isa spec. */
2062#define UNSET (CGEN_SIZE_UNKNOWN + 1)
2063 cd->default_insn_bitsize = UNSET;
2064 cd->base_insn_bitsize = UNSET;
2065 cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
2066 cd->max_insn_bitsize = 0;
2067 for (i = 0; i < MAX_ISAS; ++i)
2068 if (cgen_bitset_contains (isas, i))
2069 {
2070 const CGEN_ISA *isa = & epiphany_cgen_isa_table[i];
2071
2072 /* Default insn sizes of all selected isas must be
2073 equal or we set the result to 0, meaning "unknown". */
2074 if (cd->default_insn_bitsize == UNSET)
2075 cd->default_insn_bitsize = isa->default_insn_bitsize;
2076 else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
2077 ; /* This is ok. */
2078 else
2079 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
2080
2081 /* Base insn sizes of all selected isas must be equal
2082 or we set the result to 0, meaning "unknown". */
2083 if (cd->base_insn_bitsize == UNSET)
2084 cd->base_insn_bitsize = isa->base_insn_bitsize;
2085 else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
2086 ; /* This is ok. */
2087 else
2088 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
2089
2090 /* Set min,max insn sizes. */
2091 if (isa->min_insn_bitsize < cd->min_insn_bitsize)
2092 cd->min_insn_bitsize = isa->min_insn_bitsize;
2093 if (isa->max_insn_bitsize > cd->max_insn_bitsize)
2094 cd->max_insn_bitsize = isa->max_insn_bitsize;
2095 }
2096
2097 /* Data derived from the mach spec. */
2098 for (i = 0; i < MAX_MACHS; ++i)
2099 if (((1 << i) & machs) != 0)
2100 {
2101 const CGEN_MACH *mach = & epiphany_cgen_mach_table[i];
2102
2103 if (mach->insn_chunk_bitsize != 0)
2104 {
2105 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
2106 {
a6743a54
AM		 2107 opcodes_error_handler
2108 (/* xgettext:c-format */
2109 _("internal error: epiphany_cgen_rebuild_tables: "
2110 "conflicting insn-chunk-bitsize values: `%d' vs. `%d'"),
2111 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
cfb8c092
NC		 2112 abort ();
2113 }
2114
2115 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
2116 }
2117 }
2118
2119 /* Determine which hw elements are used by MACH. */
2120 build_hw_table (cd);
2121
2122 /* Build the ifield table. */
2123 build_ifield_table (cd);
2124
2125 /* Determine which operands are used by MACH/ISA. */
2126 build_operand_table (cd);
2127
2128 /* Build the instruction table. */
2129 build_insn_table (cd);
2130}
2131
2132/* Initialize a cpu table and return a descriptor.
2133 It's much like opening a file, and must be the first function called.
2134 The arguments are a set of (type/value) pairs, terminated with
2135 CGEN_CPU_OPEN_END.
2136
2137 Currently supported values:
2138 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
2139 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
2140 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
2141 CGEN_CPU_OPEN_ENDIAN: specify endian choice
2142 CGEN_CPU_OPEN_END: terminates arguments
2143
2144 ??? Simultaneous multiple isas might not make sense, but it's not (yet)
2145 precluded. */
2146
2147CGEN_CPU_DESC
2148epiphany_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
2149{
2150 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
2151 static int init_p;
2152 CGEN_BITSET *isas = 0; /* 0 = "unspecified" */
2153 unsigned int machs = 0; /* 0 = "unspecified" */
2154 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
2155 va_list ap;
2156
2157 if (! init_p)
2158 {
2159 init_tables ();
2160 init_p = 1;
2161 }
2162
2163 memset (cd, 0, sizeof (*cd));
2164
2165 va_start (ap, arg_type);
2166 while (arg_type != CGEN_CPU_OPEN_END)
2167 {
2168 switch (arg_type)
2169 {
2170 case CGEN_CPU_OPEN_ISAS :
2171 isas = va_arg (ap, CGEN_BITSET *);
2172 break;
2173 case CGEN_CPU_OPEN_MACHS :
2174 machs = va_arg (ap, unsigned int);
2175 break;
2176 case CGEN_CPU_OPEN_BFDMACH :
2177 {
2178 const char *name = va_arg (ap, const char *);
2179 const CGEN_MACH *mach =
2180 lookup_mach_via_bfd_name (epiphany_cgen_mach_table, name);
2181
42742084
AM		 2182 if (mach != NULL)
2183 machs |= 1 << mach->num;
cfb8c092
NC		 2184 break;
2185 }
2186 case CGEN_CPU_OPEN_ENDIAN :
2187 endian = va_arg (ap, enum cgen_endian);
2188 break;
2189 default :
a6743a54
AM		 2190 opcodes_error_handler
2191 (/* xgettext:c-format */
2192 _("internal error: epiphany_cgen_cpu_open: "
2193 "unsupported argument `%d'"),
2194 arg_type);
cfb8c092
NC		 2195 abort (); /* ??? return NULL? */
2196 }
2197 arg_type = va_arg (ap, enum cgen_cpu_open_arg);
2198 }
2199 va_end (ap);
2200
2201 /* Mach unspecified means "all". */
2202 if (machs == 0)
2203 machs = (1 << MAX_MACHS) - 1;
2204 /* Base mach is always selected. */
2205 machs |= 1;
2206 if (endian == CGEN_ENDIAN_UNKNOWN)
2207 {
2208 /* ??? If target has only one, could have a default. */
a6743a54
AM		 2209 opcodes_error_handler
2210 (/* xgettext:c-format */
2211 _("internal error: epiphany_cgen_cpu_open: no endianness specified"));
cfb8c092
NC		 2212 abort ();
2213 }
2214
2215 cd->isas = cgen_bitset_copy (isas);
2216 cd->machs = machs;
2217 cd->endian = endian;
2218 /* FIXME: for the sparc case we can determine insn-endianness statically.
2219 The worry here is where both data and insn endian can be independently
2220 chosen, in which case this function will need another argument.
2221 Actually, will want to allow for more arguments in the future anyway. */
2222 cd->insn_endian = endian;
2223
2224 /* Table (re)builder. */
2225 cd->rebuild_tables = epiphany_cgen_rebuild_tables;
2226 epiphany_cgen_rebuild_tables (cd);
2227
2228 /* Default to not allowing signed overflow. */
2229 cd->signed_overflow_ok_p = 0;
43e65147 2230
cfb8c092
NC		 2231 return (CGEN_CPU_DESC) cd;
2232}
2233
2234/* Cover fn to epiphany_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
2235 MACH_NAME is the bfd name of the mach. */
2236
2237CGEN_CPU_DESC
2238epiphany_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
2239{
2240 return epiphany_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
2241 CGEN_CPU_OPEN_ENDIAN, endian,
2242 CGEN_CPU_OPEN_END);
2243}
2244
2245/* Close a cpu table.
2246 ??? This can live in a machine independent file, but there's currently
2247 no place to put this file (there's no libcgen). libopcodes is the wrong
2248 place as some simulator ports use this but they don't use libopcodes. */
2249
2250void
2251epiphany_cgen_cpu_close (CGEN_CPU_DESC cd)
2252{
2253 unsigned int i;
2254 const CGEN_INSN *insns;
2255
2256 if (cd->macro_insn_table.init_entries)
2257 {
2258 insns = cd->macro_insn_table.init_entries;
2259 for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
2260 if (CGEN_INSN_RX ((insns)))
2261 regfree (CGEN_INSN_RX (insns));
2262 }
2263
2264 if (cd->insn_table.init_entries)
2265 {
2266 insns = cd->insn_table.init_entries;
2267 for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
2268 if (CGEN_INSN_RX (insns))
2269 regfree (CGEN_INSN_RX (insns));
43e65147 2270 }
cfb8c092
NC		 2271
2272 if (cd->macro_insn_table.init_entries)
2273 free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
2274
2275 if (cd->insn_table.init_entries)
2276 free ((CGEN_INSN *) cd->insn_table.init_entries);
2277
2278 if (cd->hw_table.entries)
2279 free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
2280
2281 if (cd->operand_table.entries)
2282 free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
2283
2284 free (cd);
2285}
2286
GDB Binutils - Deliverables
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