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* config/obj-elf.c: (obj_elf_change_section): Add "group" param.
[deliverable/binutils-gdb.git] / opcodes / fr30-desc.c
CommitLineData
252b5132
RH		 1/* CPU data for fr30.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
060d22b0 5Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
252b5132
RH		 6
7This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License along
20with this program; if not, write to the Free Software Foundation, Inc.,
2159 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22
23*/
24
25#include "sysdep.h"
252b5132
RH		 26#include <stdio.h>
27#include <stdarg.h>
28#include "ansidecl.h"
29#include "bfd.h"
30#include "symcat.h"
31#include "fr30-desc.h"
32#include "fr30-opc.h"
33#include "opintl.h"
6bb95a0f 34#include "libiberty.h"
252b5132 35
d5b2f4d6
NC		 36static void init_tables PARAMS ((void));
37static const CGEN_MACH * lookup_mach_via_bfd_name PARAMS ((const CGEN_MACH *, const char *));
38static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
39static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
40static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
41static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
42static void fr30_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
43
252b5132
RH		 44/* Attributes. */
45
46static const CGEN_ATTR_ENTRY bool_attr[] =
47{
48 { "#f", 0 },
49 { "#t", 1 },
50 { 0, 0 }
51};
52
53static const CGEN_ATTR_ENTRY MACH_attr[] =
54{
55 { "base", MACH_BASE },
56 { "fr30", MACH_FR30 },
57 { "max", MACH_MAX },
58 { 0, 0 }
59};
60
61static const CGEN_ATTR_ENTRY ISA_attr[] =
62{
63 { "fr30", ISA_FR30 },
64 { "max", ISA_MAX },
65 { 0, 0 }
66};
67
68const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[] =
69{
6bb95a0f 70 { "MACH", & MACH_attr[0], & MACH_attr[0] },
252b5132
RH		 71 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
72 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
73 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
74 { "RESERVED", &bool_attr[0], &bool_attr[0] },
75 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
76 { "SIGNED", &bool_attr[0], &bool_attr[0] },
77 { 0, 0, 0 }
78};
79
80const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
81{
6bb95a0f 82 { "MACH", & MACH_attr[0], & MACH_attr[0] },
252b5132
RH		 83 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
84 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
85 { "PC", &bool_attr[0], &bool_attr[0] },
86 { "PROFILE", &bool_attr[0], &bool_attr[0] },
87 { 0, 0, 0 }
88};
89
90const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
91{
6bb95a0f 92 { "MACH", & MACH_attr[0], & MACH_attr[0] },
252b5132
RH		 93 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
94 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
95 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
96 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
97 { "SIGNED", &bool_attr[0], &bool_attr[0] },
98 { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
99 { "RELAX", &bool_attr[0], &bool_attr[0] },
100 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
101 { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
102 { 0, 0, 0 }
103};
104
105const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
106{
6bb95a0f 107 { "MACH", & MACH_attr[0], & MACH_attr[0] },
252b5132
RH		 108 { "ALIAS", &bool_attr[0], &bool_attr[0] },
109 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
110 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
111 { "COND-CTI", &bool_attr[0], &bool_attr[0] },
112 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
113 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
114 { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
115 { "RELAX", &bool_attr[0], &bool_attr[0] },
116 { "NO-DIS", &bool_attr[0], &bool_attr[0] },
117 { "PBB", &bool_attr[0], &bool_attr[0] },
118 { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
119 { 0, 0, 0 }
120};
121
122/* Instruction set variants. */
123
124static const CGEN_ISA fr30_cgen_isa_table[] = {
6bb95a0f
DB		 125 { "fr30", 16, 16, 16, 48 },
126 { 0, 0, 0, 0, 0 }
252b5132
RH		 127};
128
129/* Machine variants. */
130
131static const CGEN_MACH fr30_cgen_mach_table[] = {
fc7bc883
RH		 132 { "fr30", "fr30", MACH_FR30, 0 },
133 { 0, 0, 0, 0 }
252b5132
RH		 134};
135
136static CGEN_KEYWORD_ENTRY fr30_cgen_opval_gr_names_entries[] =
137{
6bb95a0f
DB		 138 { "r0", 0, {0, {0}}, 0, 0 },
139 { "r1", 1, {0, {0}}, 0, 0 },
140 { "r2", 2, {0, {0}}, 0, 0 },
141 { "r3", 3, {0, {0}}, 0, 0 },
142 { "r4", 4, {0, {0}}, 0, 0 },
143 { "r5", 5, {0, {0}}, 0, 0 },
144 { "r6", 6, {0, {0}}, 0, 0 },
145 { "r7", 7, {0, {0}}, 0, 0 },
146 { "r8", 8, {0, {0}}, 0, 0 },
147 { "r9", 9, {0, {0}}, 0, 0 },
148 { "r10", 10, {0, {0}}, 0, 0 },
149 { "r11", 11, {0, {0}}, 0, 0 },
150 { "r12", 12, {0, {0}}, 0, 0 },
151 { "r13", 13, {0, {0}}, 0, 0 },
152 { "r14", 14, {0, {0}}, 0, 0 },
153 { "r15", 15, {0, {0}}, 0, 0 },
154 { "ac", 13, {0, {0}}, 0, 0 },
155 { "fp", 14, {0, {0}}, 0, 0 },
156 { "sp", 15, {0, {0}}, 0, 0 }
252b5132
RH		 157};
158
159CGEN_KEYWORD fr30_cgen_opval_gr_names =
160{
161 & fr30_cgen_opval_gr_names_entries[0],
6bb95a0f 162 19,
fc7bc883 163 0, 0, 0, 0, ""
252b5132
RH		 164};
165
166static CGEN_KEYWORD_ENTRY fr30_cgen_opval_cr_names_entries[] =
167{
6bb95a0f
DB		 168 { "cr0", 0, {0, {0}}, 0, 0 },
169 { "cr1", 1, {0, {0}}, 0, 0 },
170 { "cr2", 2, {0, {0}}, 0, 0 },
171 { "cr3", 3, {0, {0}}, 0, 0 },
172 { "cr4", 4, {0, {0}}, 0, 0 },
173 { "cr5", 5, {0, {0}}, 0, 0 },
174 { "cr6", 6, {0, {0}}, 0, 0 },
175 { "cr7", 7, {0, {0}}, 0, 0 },
176 { "cr8", 8, {0, {0}}, 0, 0 },
177 { "cr9", 9, {0, {0}}, 0, 0 },
178 { "cr10", 10, {0, {0}}, 0, 0 },
179 { "cr11", 11, {0, {0}}, 0, 0 },
180 { "cr12", 12, {0, {0}}, 0, 0 },
181 { "cr13", 13, {0, {0}}, 0, 0 },
182 { "cr14", 14, {0, {0}}, 0, 0 },
183 { "cr15", 15, {0, {0}}, 0, 0 }
252b5132
RH		 184};
185
186CGEN_KEYWORD fr30_cgen_opval_cr_names =
187{
188 & fr30_cgen_opval_cr_names_entries[0],
6bb95a0f 189 16,
fc7bc883 190 0, 0, 0, 0, ""
252b5132
RH		 191};
192
193static CGEN_KEYWORD_ENTRY fr30_cgen_opval_dr_names_entries[] =
194{
6bb95a0f
DB		 195 { "tbr", 0, {0, {0}}, 0, 0 },
196 { "rp", 1, {0, {0}}, 0, 0 },
197 { "ssp", 2, {0, {0}}, 0, 0 },
198 { "usp", 3, {0, {0}}, 0, 0 },
199 { "mdh", 4, {0, {0}}, 0, 0 },
200 { "mdl", 5, {0, {0}}, 0, 0 }
252b5132
RH		 201};
202
203CGEN_KEYWORD fr30_cgen_opval_dr_names =
204{
205 & fr30_cgen_opval_dr_names_entries[0],
6bb95a0f 206 6,
fc7bc883 207 0, 0, 0, 0, ""
252b5132
RH		 208};
209
210static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] =
211{
6bb95a0f 212 { "ps", 0, {0, {0}}, 0, 0 }
252b5132
RH		 213};
214
215CGEN_KEYWORD fr30_cgen_opval_h_ps =
216{
217 & fr30_cgen_opval_h_ps_entries[0],
6bb95a0f 218 1,
fc7bc883 219 0, 0, 0, 0, ""
252b5132
RH		 220};
221
222static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] =
223{
6bb95a0f 224 { "r13", 0, {0, {0}}, 0, 0 }
252b5132
RH		 225};
226
227CGEN_KEYWORD fr30_cgen_opval_h_r13 =
228{
229 & fr30_cgen_opval_h_r13_entries[0],
6bb95a0f 230 1,
fc7bc883 231 0, 0, 0, 0, ""
252b5132
RH		 232};
233
234static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] =
235{
6bb95a0f 236 { "r14", 0, {0, {0}}, 0, 0 }
252b5132
RH		 237};
238
239CGEN_KEYWORD fr30_cgen_opval_h_r14 =
240{
241 & fr30_cgen_opval_h_r14_entries[0],
6bb95a0f 242 1,
fc7bc883 243 0, 0, 0, 0, ""
252b5132
RH		 244};
245
246static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] =
247{
6bb95a0f 248 { "r15", 0, {0, {0}}, 0, 0 }
252b5132
RH		 249};
250
251CGEN_KEYWORD fr30_cgen_opval_h_r15 =
252{
253 & fr30_cgen_opval_h_r15_entries[0],
6bb95a0f 254 1,
fc7bc883 255 0, 0, 0, 0, ""
252b5132
RH		 256};
257
258
252b5132
RH		 259/* The hardware table. */
260
b3466c39
DB		 261#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
262#define A(a) (1 << CGEN_HW_##a)
263#else
264#define A(a) (1 << CGEN_HW_/**/a)
265#endif
252b5132
RH		 266
267const CGEN_HW_ENTRY fr30_cgen_hw_table[] =
268{
269 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
270 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
271 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
272 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
273 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
274 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
275 { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
276 { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_cr_names, { 0, { (1<<MACH_BASE) } } },
277 { "h-dr", HW_H_DR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_dr_names, { 0, { (1<<MACH_BASE) } } },
278 { "h-ps", HW_H_PS, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, { (1<<MACH_BASE) } } },
279 { "h-r13", HW_H_R13, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, { (1<<MACH_BASE) } } },
280 { "h-r14", HW_H_R14, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, { (1<<MACH_BASE) } } },
281 { "h-r15", HW_H_R15, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, { (1<<MACH_BASE) } } },
282 { "h-nbit", HW_H_NBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
283 { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
284 { "h-vbit", HW_H_VBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
285 { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
286 { "h-ibit", HW_H_IBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
287 { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
288 { "h-tbit", HW_H_TBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
289 { "h-d0bit", HW_H_D0BIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
290 { "h-d1bit", HW_H_D1BIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
291 { "h-ccr", HW_H_CCR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
292 { "h-scr", HW_H_SCR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
293 { "h-ilm", HW_H_ILM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
6bb95a0f 294 { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
252b5132
RH		 295};
296
297#undef A
298
b3466c39 299
252b5132
RH		 300/* The instruction field table. */
301
b3466c39
DB		 302#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
303#define A(a) (1 << CGEN_IFLD_##a)
304#else
305#define A(a) (1 << CGEN_IFLD_/**/a)
306#endif
252b5132
RH		 307
308const CGEN_IFLD fr30_cgen_ifld_table[] =
309{
310 { FR30_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
6bb95a0f 311 { FR30_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
252b5132
RH		 312 { FR30_F_OP1, "f-op1", 0, 16, 0, 4, { 0, { (1<<MACH_BASE) } } },
313 { FR30_F_OP2, "f-op2", 0, 16, 4, 4, { 0, { (1<<MACH_BASE) } } },
314 { FR30_F_OP3, "f-op3", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } },
315 { FR30_F_OP4, "f-op4", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } } },
316 { FR30_F_OP5, "f-op5", 0, 16, 4, 1, { 0, { (1<<MACH_BASE) } } },
317 { FR30_F_CC, "f-cc", 0, 16, 4, 4, { 0, { (1<<MACH_BASE) } } },
318 { FR30_F_CCC, "f-ccc", 16, 16, 0, 8, { 0, { (1<<MACH_BASE) } } },
319 { FR30_F_RJ, "f-Rj", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } },
320 { FR30_F_RI, "f-Ri", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } } },
321 { FR30_F_RS1, "f-Rs1", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } },
322 { FR30_F_RS2, "f-Rs2", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } } },
323 { FR30_F_RJC, "f-Rjc", 16, 16, 8, 4, { 0, { (1<<MACH_BASE) } } },
324 { FR30_F_RIC, "f-Ric", 16, 16, 12, 4, { 0, { (1<<MACH_BASE) } } },
325 { FR30_F_CRJ, "f-CRj", 16, 16, 8, 4, { 0, { (1<<MACH_BASE) } } },
326 { FR30_F_CRI, "f-CRi", 16, 16, 12, 4, { 0, { (1<<MACH_BASE) } } },
327 { FR30_F_U4, "f-u4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } },
328 { FR30_F_U4C, "f-u4c", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } } },
329 { FR30_F_I4, "f-i4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } },
330 { FR30_F_M4, "f-m4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } },
331 { FR30_F_U8, "f-u8", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } },
332 { FR30_F_I8, "f-i8", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } } },
333 { FR30_F_I20_4, "f-i20-4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } },
334 { FR30_F_I20_16, "f-i20-16", 16, 16, 0, 16, { 0, { (1<<MACH_BASE) } } },
335 { FR30_F_I32, "f-i32", 16, 32, 0, 32, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
336 { FR30_F_UDISP6, "f-udisp6", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } },
337 { FR30_F_DISP8, "f-disp8", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } } },
338 { FR30_F_DISP9, "f-disp9", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } } },
339 { FR30_F_DISP10, "f-disp10", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } } },
340 { FR30_F_S10, "f-s10", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } },
341 { FR30_F_U10, "f-u10", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } },
342 { FR30_F_REL9, "f-rel9", 0, 16, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
343 { FR30_F_DIR8, "f-dir8", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } },
344 { FR30_F_DIR9, "f-dir9", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } },
345 { FR30_F_DIR10, "f-dir10", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } },
346 { FR30_F_REL12, "f-rel12", 0, 16, 5, 11, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
347 { FR30_F_REGLIST_HI_ST, "f-reglist_hi_st", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } },
348 { FR30_F_REGLIST_LOW_ST, "f-reglist_low_st", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } },
349 { FR30_F_REGLIST_HI_LD, "f-reglist_hi_ld", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } },
350 { FR30_F_REGLIST_LOW_LD, "f-reglist_low_ld", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } },
6bb95a0f 351 { 0, 0, 0, 0, 0, 0, {0, {0}} }
252b5132
RH		 352};
353
354#undef A
355
b3466c39 356
252b5132
RH		 357/* The operand table. */
358
b3466c39
DB		 359#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
360#define A(a) (1 << CGEN_OPERAND_##a)
361#else
362#define A(a) (1 << CGEN_OPERAND_/**/a)
363#endif
364#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
365#define OPERAND(op) FR30_OPERAND_##op
366#else
367#define OPERAND(op) FR30_OPERAND_/**/op
368#endif
252b5132
RH		 369
370const CGEN_OPERAND fr30_cgen_operand_table[] =
371{
372/* pc: program counter */
373 { "pc", FR30_OPERAND_PC, HW_H_PC, 0, 0,
374 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
375/* Ri: destination register */
376 { "Ri", FR30_OPERAND_RI, HW_H_GR, 12, 4,
377 { 0, { (1<<MACH_BASE) } } },
378/* Rj: source register */
379 { "Rj", FR30_OPERAND_RJ, HW_H_GR, 8, 4,
380 { 0, { (1<<MACH_BASE) } } },
381/* Ric: target register coproc insn */
382 { "Ric", FR30_OPERAND_RIC, HW_H_GR, 12, 4,
383 { 0, { (1<<MACH_BASE) } } },
384/* Rjc: source register coproc insn */
385 { "Rjc", FR30_OPERAND_RJC, HW_H_GR, 8, 4,
386 { 0, { (1<<MACH_BASE) } } },
387/* CRi: coprocessor register */
388 { "CRi", FR30_OPERAND_CRI, HW_H_CR, 12, 4,
389 { 0, { (1<<MACH_BASE) } } },
390/* CRj: coprocessor register */
391 { "CRj", FR30_OPERAND_CRJ, HW_H_CR, 8, 4,
392 { 0, { (1<<MACH_BASE) } } },
393/* Rs1: dedicated register */
394 { "Rs1", FR30_OPERAND_RS1, HW_H_DR, 8, 4,
395 { 0, { (1<<MACH_BASE) } } },
396/* Rs2: dedicated register */
397 { "Rs2", FR30_OPERAND_RS2, HW_H_DR, 12, 4,
398 { 0, { (1<<MACH_BASE) } } },
399/* R13: General Register 13 */
400 { "R13", FR30_OPERAND_R13, HW_H_R13, 0, 0,
401 { 0, { (1<<MACH_BASE) } } },
402/* R14: General Register 14 */
403 { "R14", FR30_OPERAND_R14, HW_H_R14, 0, 0,
404 { 0, { (1<<MACH_BASE) } } },
405/* R15: General Register 15 */
406 { "R15", FR30_OPERAND_R15, HW_H_R15, 0, 0,
407 { 0, { (1<<MACH_BASE) } } },
408/* ps: Program Status register */
409 { "ps", FR30_OPERAND_PS, HW_H_PS, 0, 0,
410 { 0, { (1<<MACH_BASE) } } },
411/* u4: 4 bit unsigned immediate */
412 { "u4", FR30_OPERAND_U4, HW_H_UINT, 8, 4,
413 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
414/* u4c: 4 bit unsigned immediate */
415 { "u4c", FR30_OPERAND_U4C, HW_H_UINT, 12, 4,
416 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
417/* u8: 8 bit unsigned immediate */
418 { "u8", FR30_OPERAND_U8, HW_H_UINT, 8, 8,
419 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
420/* i8: 8 bit unsigned immediate */
421 { "i8", FR30_OPERAND_I8, HW_H_UINT, 4, 8,
422 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
423/* udisp6: 6 bit unsigned immediate */
424 { "udisp6", FR30_OPERAND_UDISP6, HW_H_UINT, 8, 4,
425 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
426/* disp8: 8 bit signed immediate */
427 { "disp8", FR30_OPERAND_DISP8, HW_H_SINT, 4, 8,
428 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
429/* disp9: 9 bit signed immediate */
430 { "disp9", FR30_OPERAND_DISP9, HW_H_SINT, 4, 8,
431 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
432/* disp10: 10 bit signed immediate */
433 { "disp10", FR30_OPERAND_DISP10, HW_H_SINT, 4, 8,
434 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
435/* s10: 10 bit signed immediate */
436 { "s10", FR30_OPERAND_S10, HW_H_SINT, 8, 8,
437 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
438/* u10: 10 bit unsigned immediate */
439 { "u10", FR30_OPERAND_U10, HW_H_UINT, 8, 8,
440 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
441/* i32: 32 bit immediate */
442 { "i32", FR30_OPERAND_I32, HW_H_UINT, 0, 32,
443 { 0|A(HASH_PREFIX)|A(SIGN_OPT), { (1<<MACH_BASE) } } },
444/* m4: 4 bit negative immediate */
445 { "m4", FR30_OPERAND_M4, HW_H_SINT, 8, 4,
446 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
447/* i20: 20 bit immediate */
448 { "i20", FR30_OPERAND_I20, HW_H_UINT, 0, 20,
449 { 0|A(HASH_PREFIX)|A(VIRTUAL), { (1<<MACH_BASE) } } },
450/* dir8: 8 bit direct address */
451 { "dir8", FR30_OPERAND_DIR8, HW_H_UINT, 8, 8,
452 { 0, { (1<<MACH_BASE) } } },
453/* dir9: 9 bit direct address */
454 { "dir9", FR30_OPERAND_DIR9, HW_H_UINT, 8, 8,
455 { 0, { (1<<MACH_BASE) } } },
456/* dir10: 10 bit direct address */
457 { "dir10", FR30_OPERAND_DIR10, HW_H_UINT, 8, 8,
458 { 0, { (1<<MACH_BASE) } } },
459/* label9: 9 bit pc relative address */
460 { "label9", FR30_OPERAND_LABEL9, HW_H_IADDR, 8, 8,
461 { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
462/* label12: 12 bit pc relative address */
463 { "label12", FR30_OPERAND_LABEL12, HW_H_IADDR, 5, 11,
464 { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
465/* reglist_low_ld: 8 bit low register mask for ldm */
466 { "reglist_low_ld", FR30_OPERAND_REGLIST_LOW_LD, HW_H_UINT, 8, 8,
467 { 0, { (1<<MACH_BASE) } } },
468/* reglist_hi_ld: 8 bit high register mask for ldm */
469 { "reglist_hi_ld", FR30_OPERAND_REGLIST_HI_LD, HW_H_UINT, 8, 8,
470 { 0, { (1<<MACH_BASE) } } },
471/* reglist_low_st: 8 bit low register mask for stm */
472 { "reglist_low_st", FR30_OPERAND_REGLIST_LOW_ST, HW_H_UINT, 8, 8,
473 { 0, { (1<<MACH_BASE) } } },
474/* reglist_hi_st: 8 bit high register mask for stm */
475 { "reglist_hi_st", FR30_OPERAND_REGLIST_HI_ST, HW_H_UINT, 8, 8,
476 { 0, { (1<<MACH_BASE) } } },
477/* cc: condition codes */
478 { "cc", FR30_OPERAND_CC, HW_H_UINT, 4, 4,
479 { 0, { (1<<MACH_BASE) } } },
480/* ccc: coprocessor calc */
481 { "ccc", FR30_OPERAND_CCC, HW_H_UINT, 0, 8,
482 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
483/* nbit: negative bit */
484 { "nbit", FR30_OPERAND_NBIT, HW_H_NBIT, 0, 0,
485 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
486/* vbit: overflow bit */
487 { "vbit", FR30_OPERAND_VBIT, HW_H_VBIT, 0, 0,
488 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
489/* zbit: zero bit */
490 { "zbit", FR30_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
491 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
492/* cbit: carry bit */
493 { "cbit", FR30_OPERAND_CBIT, HW_H_CBIT, 0, 0,
494 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
495/* ibit: interrupt bit */
496 { "ibit", FR30_OPERAND_IBIT, HW_H_IBIT, 0, 0,
497 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
498/* sbit: stack bit */
499 { "sbit", FR30_OPERAND_SBIT, HW_H_SBIT, 0, 0,
500 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
501/* tbit: trace trap bit */
502 { "tbit", FR30_OPERAND_TBIT, HW_H_TBIT, 0, 0,
503 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
504/* d0bit: division 0 bit */
505 { "d0bit", FR30_OPERAND_D0BIT, HW_H_D0BIT, 0, 0,
506 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
507/* d1bit: division 1 bit */
508 { "d1bit", FR30_OPERAND_D1BIT, HW_H_D1BIT, 0, 0,
509 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
510/* ccr: condition code bits */
511 { "ccr", FR30_OPERAND_CCR, HW_H_CCR, 0, 0,
512 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
513/* scr: system condition bits */
514 { "scr", FR30_OPERAND_SCR, HW_H_SCR, 0, 0,
515 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
516/* ilm: interrupt level mask */
517 { "ilm", FR30_OPERAND_ILM, HW_H_ILM, 0, 0,
518 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
6bb95a0f 519 { 0, 0, 0, 0, 0, {0, {0}} }
252b5132
RH		 520};
521
522#undef A
523
252b5132
RH		 524
525/* The instruction table. */
526
b3466c39
DB		 527#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
528#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
529#define A(a) (1 << CGEN_INSN_##a)
530#else
531#define A(a) (1 << CGEN_INSN_/**/a)
532#endif
533
252b5132
RH		 534static const CGEN_IBASE fr30_cgen_insn_table[MAX_INSNS] =
535{
536 /* Special null first entry.
537 A `num' value of zero is thus invalid.
538 Also, the special `invalid' insn resides here. */
6bb95a0f 539 { 0, 0, 0, 0, {0, {0}} },
252b5132
RH		 540/* add $Rj,$Ri */
541 {
542 FR30_INSN_ADD, "add", "add", 16,
543 { 0, { (1<<MACH_BASE) } }
544 },
545/* add $u4,$Ri */
546 {
547 FR30_INSN_ADDI, "addi", "add", 16,
548 { 0, { (1<<MACH_BASE) } }
549 },
550/* add2 $m4,$Ri */
551 {
552 FR30_INSN_ADD2, "add2", "add2", 16,
553 { 0, { (1<<MACH_BASE) } }
554 },
555/* addc $Rj,$Ri */
556 {
557 FR30_INSN_ADDC, "addc", "addc", 16,
558 { 0, { (1<<MACH_BASE) } }
559 },
560/* addn $Rj,$Ri */
561 {
562 FR30_INSN_ADDN, "addn", "addn", 16,
563 { 0, { (1<<MACH_BASE) } }
564 },
565/* addn $u4,$Ri */
566 {
567 FR30_INSN_ADDNI, "addni", "addn", 16,
568 { 0, { (1<<MACH_BASE) } }
569 },
570/* addn2 $m4,$Ri */
571 {
572 FR30_INSN_ADDN2, "addn2", "addn2", 16,
573 { 0, { (1<<MACH_BASE) } }
574 },
575/* sub $Rj,$Ri */
576 {
577 FR30_INSN_SUB, "sub", "sub", 16,
578 { 0, { (1<<MACH_BASE) } }
579 },
580/* subc $Rj,$Ri */
581 {
582 FR30_INSN_SUBC, "subc", "subc", 16,
583 { 0, { (1<<MACH_BASE) } }
584 },
585/* subn $Rj,$Ri */
586 {
587 FR30_INSN_SUBN, "subn", "subn", 16,
588 { 0, { (1<<MACH_BASE) } }
589 },
590/* cmp $Rj,$Ri */
591 {
592 FR30_INSN_CMP, "cmp", "cmp", 16,
593 { 0, { (1<<MACH_BASE) } }
594 },
595/* cmp $u4,$Ri */
596 {
597 FR30_INSN_CMPI, "cmpi", "cmp", 16,
598 { 0, { (1<<MACH_BASE) } }
599 },
600/* cmp2 $m4,$Ri */
601 {
602 FR30_INSN_CMP2, "cmp2", "cmp2", 16,
603 { 0, { (1<<MACH_BASE) } }
604 },
605/* and $Rj,$Ri */
606 {
607 FR30_INSN_AND, "and", "and", 16,
608 { 0, { (1<<MACH_BASE) } }
609 },
610/* or $Rj,$Ri */
611 {
612 FR30_INSN_OR, "or", "or", 16,
613 { 0, { (1<<MACH_BASE) } }
614 },
615/* eor $Rj,$Ri */
616 {
617 FR30_INSN_EOR, "eor", "eor", 16,
618 { 0, { (1<<MACH_BASE) } }
619 },
620/* and $Rj,@$Ri */
621 {
622 FR30_INSN_ANDM, "andm", "and", 16,
623 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
624 },
625/* andh $Rj,@$Ri */
626 {
627 FR30_INSN_ANDH, "andh", "andh", 16,
628 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
629 },
630/* andb $Rj,@$Ri */
631 {
632 FR30_INSN_ANDB, "andb", "andb", 16,
633 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
634 },
635/* or $Rj,@$Ri */
636 {
637 FR30_INSN_ORM, "orm", "or", 16,
638 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
639 },
640/* orh $Rj,@$Ri */
641 {
642 FR30_INSN_ORH, "orh", "orh", 16,
643 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
644 },
645/* orb $Rj,@$Ri */
646 {
647 FR30_INSN_ORB, "orb", "orb", 16,
648 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
649 },
650/* eor $Rj,@$Ri */
651 {
652 FR30_INSN_EORM, "eorm", "eor", 16,
653 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
654 },
655/* eorh $Rj,@$Ri */
656 {
657 FR30_INSN_EORH, "eorh", "eorh", 16,
658 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
659 },
660/* eorb $Rj,@$Ri */
661 {
662 FR30_INSN_EORB, "eorb", "eorb", 16,
663 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
664 },
665/* bandl $u4,@$Ri */
666 {
667 FR30_INSN_BANDL, "bandl", "bandl", 16,
668 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
669 },
670/* borl $u4,@$Ri */
671 {
672 FR30_INSN_BORL, "borl", "borl", 16,
673 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
674 },
675/* beorl $u4,@$Ri */
676 {
677 FR30_INSN_BEORL, "beorl", "beorl", 16,
678 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
679 },
680/* bandh $u4,@$Ri */
681 {
682 FR30_INSN_BANDH, "bandh", "bandh", 16,
683 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
684 },
685/* borh $u4,@$Ri */
686 {
687 FR30_INSN_BORH, "borh", "borh", 16,
688 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
689 },
690/* beorh $u4,@$Ri */
691 {
692 FR30_INSN_BEORH, "beorh", "beorh", 16,
693 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
694 },
695/* btstl $u4,@$Ri */
696 {
697 FR30_INSN_BTSTL, "btstl", "btstl", 16,
698 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
699 },
700/* btsth $u4,@$Ri */
701 {
702 FR30_INSN_BTSTH, "btsth", "btsth", 16,
703 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
704 },
705/* mul $Rj,$Ri */
706 {
707 FR30_INSN_MUL, "mul", "mul", 16,
708 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
709 },
710/* mulu $Rj,$Ri */
711 {
712 FR30_INSN_MULU, "mulu", "mulu", 16,
713 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
714 },
715/* mulh $Rj,$Ri */
716 {
717 FR30_INSN_MULH, "mulh", "mulh", 16,
718 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
719 },
720/* muluh $Rj,$Ri */
721 {
722 FR30_INSN_MULUH, "muluh", "muluh", 16,
723 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
724 },
725/* div0s $Ri */
726 {
727 FR30_INSN_DIV0S, "div0s", "div0s", 16,
728 { 0, { (1<<MACH_BASE) } }
729 },
730/* div0u $Ri */
731 {
732 FR30_INSN_DIV0U, "div0u", "div0u", 16,
733 { 0, { (1<<MACH_BASE) } }
734 },
735/* div1 $Ri */
736 {
737 FR30_INSN_DIV1, "div1", "div1", 16,
738 { 0, { (1<<MACH_BASE) } }
739 },
740/* div2 $Ri */
741 {
742 FR30_INSN_DIV2, "div2", "div2", 16,
743 { 0, { (1<<MACH_BASE) } }
744 },
745/* div3 */
746 {
747 FR30_INSN_DIV3, "div3", "div3", 16,
748 { 0, { (1<<MACH_BASE) } }
749 },
750/* div4s */
751 {
752 FR30_INSN_DIV4S, "div4s", "div4s", 16,
753 { 0, { (1<<MACH_BASE) } }
754 },
755/* lsl $Rj,$Ri */
756 {
757 FR30_INSN_LSL, "lsl", "lsl", 16,
758 { 0, { (1<<MACH_BASE) } }
759 },
760/* lsl $u4,$Ri */
761 {
762 FR30_INSN_LSLI, "lsli", "lsl", 16,
763 { 0, { (1<<MACH_BASE) } }
764 },
765/* lsl2 $u4,$Ri */
766 {
767 FR30_INSN_LSL2, "lsl2", "lsl2", 16,
768 { 0, { (1<<MACH_BASE) } }
769 },
770/* lsr $Rj,$Ri */
771 {
772 FR30_INSN_LSR, "lsr", "lsr", 16,
773 { 0, { (1<<MACH_BASE) } }
774 },
775/* lsr $u4,$Ri */
776 {
777 FR30_INSN_LSRI, "lsri", "lsr", 16,
778 { 0, { (1<<MACH_BASE) } }
779 },
780/* lsr2 $u4,$Ri */
781 {
782 FR30_INSN_LSR2, "lsr2", "lsr2", 16,
783 { 0, { (1<<MACH_BASE) } }
784 },
785/* asr $Rj,$Ri */
786 {
787 FR30_INSN_ASR, "asr", "asr", 16,
788 { 0, { (1<<MACH_BASE) } }
789 },
790/* asr $u4,$Ri */
791 {
792 FR30_INSN_ASRI, "asri", "asr", 16,
793 { 0, { (1<<MACH_BASE) } }
794 },
795/* asr2 $u4,$Ri */
796 {
797 FR30_INSN_ASR2, "asr2", "asr2", 16,
798 { 0, { (1<<MACH_BASE) } }
799 },
800/* ldi:8 $i8,$Ri */
801 {
802 FR30_INSN_LDI8, "ldi8", "ldi:8", 16,
803 { 0, { (1<<MACH_BASE) } }
804 },
805/* ldi:20 $i20,$Ri */
806 {
807 FR30_INSN_LDI20, "ldi20", "ldi:20", 32,
808 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
809 },
810/* ldi:32 $i32,$Ri */
811 {
812 FR30_INSN_LDI32, "ldi32", "ldi:32", 48,
813 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
814 },
815/* ld @$Rj,$Ri */
816 {
817 FR30_INSN_LD, "ld", "ld", 16,
818 { 0, { (1<<MACH_BASE) } }
819 },
820/* lduh @$Rj,$Ri */
821 {
822 FR30_INSN_LDUH, "lduh", "lduh", 16,
823 { 0, { (1<<MACH_BASE) } }
824 },
825/* ldub @$Rj,$Ri */
826 {
827 FR30_INSN_LDUB, "ldub", "ldub", 16,
828 { 0, { (1<<MACH_BASE) } }
829 },
830/* ld @($R13,$Rj),$Ri */
831 {
832 FR30_INSN_LDR13, "ldr13", "ld", 16,
833 { 0, { (1<<MACH_BASE) } }
834 },
835/* lduh @($R13,$Rj),$Ri */
836 {
837 FR30_INSN_LDR13UH, "ldr13uh", "lduh", 16,
838 { 0, { (1<<MACH_BASE) } }
839 },
840/* ldub @($R13,$Rj),$Ri */
841 {
842 FR30_INSN_LDR13UB, "ldr13ub", "ldub", 16,
843 { 0, { (1<<MACH_BASE) } }
844 },
845/* ld @($R14,$disp10),$Ri */
846 {
847 FR30_INSN_LDR14, "ldr14", "ld", 16,
848 { 0, { (1<<MACH_BASE) } }
849 },
850/* lduh @($R14,$disp9),$Ri */
851 {
852 FR30_INSN_LDR14UH, "ldr14uh", "lduh", 16,
853 { 0, { (1<<MACH_BASE) } }
854 },
855/* ldub @($R14,$disp8),$Ri */
856 {
857 FR30_INSN_LDR14UB, "ldr14ub", "ldub", 16,
858 { 0, { (1<<MACH_BASE) } }
859 },
860/* ld @($R15,$udisp6),$Ri */
861 {
862 FR30_INSN_LDR15, "ldr15", "ld", 16,
863 { 0, { (1<<MACH_BASE) } }
864 },
865/* ld @$R15+,$Ri */
866 {
867 FR30_INSN_LDR15GR, "ldr15gr", "ld", 16,
868 { 0, { (1<<MACH_BASE) } }
869 },
870/* ld @$R15+,$Rs2 */
871 {
872 FR30_INSN_LDR15DR, "ldr15dr", "ld", 16,
873 { 0, { (1<<MACH_BASE) } }
874 },
875/* ld @$R15+,$ps */
876 {
877 FR30_INSN_LDR15PS, "ldr15ps", "ld", 16,
878 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
879 },
880/* st $Ri,@$Rj */
881 {
882 FR30_INSN_ST, "st", "st", 16,
883 { 0, { (1<<MACH_BASE) } }
884 },
885/* sth $Ri,@$Rj */
886 {
887 FR30_INSN_STH, "sth", "sth", 16,
888 { 0, { (1<<MACH_BASE) } }
889 },
890/* stb $Ri,@$Rj */
891 {
892 FR30_INSN_STB, "stb", "stb", 16,
893 { 0, { (1<<MACH_BASE) } }
894 },
895/* st $Ri,@($R13,$Rj) */
896 {
897 FR30_INSN_STR13, "str13", "st", 16,
898 { 0, { (1<<MACH_BASE) } }
899 },
900/* sth $Ri,@($R13,$Rj) */
901 {
902 FR30_INSN_STR13H, "str13h", "sth", 16,
903 { 0, { (1<<MACH_BASE) } }
904 },
905/* stb $Ri,@($R13,$Rj) */
906 {
907 FR30_INSN_STR13B, "str13b", "stb", 16,
908 { 0, { (1<<MACH_BASE) } }
909 },
910/* st $Ri,@($R14,$disp10) */
911 {
912 FR30_INSN_STR14, "str14", "st", 16,
913 { 0, { (1<<MACH_BASE) } }
914 },
915/* sth $Ri,@($R14,$disp9) */
916 {
917 FR30_INSN_STR14H, "str14h", "sth", 16,
918 { 0, { (1<<MACH_BASE) } }
919 },
920/* stb $Ri,@($R14,$disp8) */
921 {
922 FR30_INSN_STR14B, "str14b", "stb", 16,
923 { 0, { (1<<MACH_BASE) } }
924 },
925/* st $Ri,@($R15,$udisp6) */
926 {
927 FR30_INSN_STR15, "str15", "st", 16,
928 { 0, { (1<<MACH_BASE) } }
929 },
930/* st $Ri,@-$R15 */
931 {
932 FR30_INSN_STR15GR, "str15gr", "st", 16,
933 { 0, { (1<<MACH_BASE) } }
934 },
935/* st $Rs2,@-$R15 */
936 {
937 FR30_INSN_STR15DR, "str15dr", "st", 16,
938 { 0, { (1<<MACH_BASE) } }
939 },
940/* st $ps,@-$R15 */
941 {
942 FR30_INSN_STR15PS, "str15ps", "st", 16,
943 { 0, { (1<<MACH_BASE) } }
944 },
945/* mov $Rj,$Ri */
946 {
947 FR30_INSN_MOV, "mov", "mov", 16,
948 { 0, { (1<<MACH_BASE) } }
949 },
950/* mov $Rs1,$Ri */
951 {
952 FR30_INSN_MOVDR, "movdr", "mov", 16,
953 { 0, { (1<<MACH_BASE) } }
954 },
955/* mov $ps,$Ri */
956 {
957 FR30_INSN_MOVPS, "movps", "mov", 16,
958 { 0, { (1<<MACH_BASE) } }
959 },
960/* mov $Ri,$Rs1 */
961 {
962 FR30_INSN_MOV2DR, "mov2dr", "mov", 16,
963 { 0, { (1<<MACH_BASE) } }
964 },
965/* mov $Ri,$ps */
966 {
967 FR30_INSN_MOV2PS, "mov2ps", "mov", 16,
968 { 0, { (1<<MACH_BASE) } }
969 },
970/* jmp @$Ri */
971 {
972 FR30_INSN_JMP, "jmp", "jmp", 16,
973 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
974 },
975/* jmp:d @$Ri */
976 {
977 FR30_INSN_JMPD, "jmpd", "jmp:d", 16,
978 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
979 },
980/* call @$Ri */
981 {
982 FR30_INSN_CALLR, "callr", "call", 16,
983 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
984 },
985/* call:d @$Ri */
986 {
987 FR30_INSN_CALLRD, "callrd", "call:d", 16,
988 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
989 },
990/* call $label12 */
991 {
992 FR30_INSN_CALL, "call", "call", 16,
993 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
994 },
995/* call:d $label12 */
996 {
997 FR30_INSN_CALLD, "calld", "call:d", 16,
998 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
999 },
1000/* ret */
1001 {
1002 FR30_INSN_RET, "ret", "ret", 16,
1003 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1004 },
1005/* ret:d */
1006 {
1007 FR30_INSN_RET_D, "ret:d", "ret:d", 16,
1008 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1009 },
1010/* int $u8 */
1011 {
1012 FR30_INSN_INT, "int", "int", 16,
1013 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1014 },
1015/* inte */
1016 {
1017 FR30_INSN_INTE, "inte", "inte", 16,
1018 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1019 },
1020/* reti */
1021 {
1022 FR30_INSN_RETI, "reti", "reti", 16,
1023 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1024 },
1025/* bra:d $label9 */
1026 {
1027 FR30_INSN_BRAD, "brad", "bra:d", 16,
1028 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1029 },
1030/* bra $label9 */
1031 {
1032 FR30_INSN_BRA, "bra", "bra", 16,
1033 { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1034 },
1035/* bno:d $label9 */
1036 {
1037 FR30_INSN_BNOD, "bnod", "bno:d", 16,
1038 { 0|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1039 },
1040/* bno $label9 */
1041 {
1042 FR30_INSN_BNO, "bno", "bno", 16,
1043 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1044 },
1045/* beq:d $label9 */
1046 {
1047 FR30_INSN_BEQD, "beqd", "beq:d", 16,
1048 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1049 },
1050/* beq $label9 */
1051 {
1052 FR30_INSN_BEQ, "beq", "beq", 16,
1053 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1054 },
1055/* bne:d $label9 */
1056 {
1057 FR30_INSN_BNED, "bned", "bne:d", 16,
1058 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1059 },
1060/* bne $label9 */
1061 {
1062 FR30_INSN_BNE, "bne", "bne", 16,
1063 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1064 },
1065/* bc:d $label9 */
1066 {
1067 FR30_INSN_BCD, "bcd", "bc:d", 16,
1068 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1069 },
1070/* bc $label9 */
1071 {
1072 FR30_INSN_BC, "bc", "bc", 16,
1073 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1074 },
1075/* bnc:d $label9 */
1076 {
1077 FR30_INSN_BNCD, "bncd", "bnc:d", 16,
1078 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1079 },
1080/* bnc $label9 */
1081 {
1082 FR30_INSN_BNC, "bnc", "bnc", 16,
1083 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1084 },
1085/* bn:d $label9 */
1086 {
1087 FR30_INSN_BND, "bnd", "bn:d", 16,
1088 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1089 },
1090/* bn $label9 */
1091 {
1092 FR30_INSN_BN, "bn", "bn", 16,
1093 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1094 },
1095/* bp:d $label9 */
1096 {
1097 FR30_INSN_BPD, "bpd", "bp:d", 16,
1098 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1099 },
1100/* bp $label9 */
1101 {
1102 FR30_INSN_BP, "bp", "bp", 16,
1103 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1104 },
1105/* bv:d $label9 */
1106 {
1107 FR30_INSN_BVD, "bvd", "bv:d", 16,
1108 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1109 },
1110/* bv $label9 */
1111 {
1112 FR30_INSN_BV, "bv", "bv", 16,
1113 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1114 },
1115/* bnv:d $label9 */
1116 {
1117 FR30_INSN_BNVD, "bnvd", "bnv:d", 16,
1118 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1119 },
1120/* bnv $label9 */
1121 {
1122 FR30_INSN_BNV, "bnv", "bnv", 16,
1123 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1124 },
1125/* blt:d $label9 */
1126 {
1127 FR30_INSN_BLTD, "bltd", "blt:d", 16,
1128 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1129 },
1130/* blt $label9 */
1131 {
1132 FR30_INSN_BLT, "blt", "blt", 16,
1133 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1134 },
1135/* bge:d $label9 */
1136 {
1137 FR30_INSN_BGED, "bged", "bge:d", 16,
1138 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1139 },
1140/* bge $label9 */
1141 {
1142 FR30_INSN_BGE, "bge", "bge", 16,
1143 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1144 },
1145/* ble:d $label9 */
1146 {
1147 FR30_INSN_BLED, "bled", "ble:d", 16,
1148 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1149 },
1150/* ble $label9 */
1151 {
1152 FR30_INSN_BLE, "ble", "ble", 16,
1153 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1154 },
1155/* bgt:d $label9 */
1156 {
1157 FR30_INSN_BGTD, "bgtd", "bgt:d", 16,
1158 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1159 },
1160/* bgt $label9 */
1161 {
1162 FR30_INSN_BGT, "bgt", "bgt", 16,
1163 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1164 },
1165/* bls:d $label9 */
1166 {
1167 FR30_INSN_BLSD, "blsd", "bls:d", 16,
1168 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1169 },
1170/* bls $label9 */
1171 {
1172 FR30_INSN_BLS, "bls", "bls", 16,
1173 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1174 },
1175/* bhi:d $label9 */
1176 {
1177 FR30_INSN_BHID, "bhid", "bhi:d", 16,
1178 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1179 },
1180/* bhi $label9 */
1181 {
1182 FR30_INSN_BHI, "bhi", "bhi", 16,
1183 { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1184 },
1185/* dmov $R13,@$dir10 */
1186 {
1187 FR30_INSN_DMOVR13, "dmovr13", "dmov", 16,
1188 { 0, { (1<<MACH_BASE) } }
1189 },
1190/* dmovh $R13,@$dir9 */
1191 {
1192 FR30_INSN_DMOVR13H, "dmovr13h", "dmovh", 16,
1193 { 0, { (1<<MACH_BASE) } }
1194 },
1195/* dmovb $R13,@$dir8 */
1196 {
1197 FR30_INSN_DMOVR13B, "dmovr13b", "dmovb", 16,
1198 { 0, { (1<<MACH_BASE) } }
1199 },
1200/* dmov @$R13+,@$dir10 */
1201 {
1202 FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov", 16,
1203 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1204 },
1205/* dmovh @$R13+,@$dir9 */
1206 {
1207 FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh", 16,
1208 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1209 },
1210/* dmovb @$R13+,@$dir8 */
1211 {
1212 FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb", 16,
1213 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1214 },
1215/* dmov @$R15+,@$dir10 */
1216 {
1217 FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov", 16,
1218 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1219 },
1220/* dmov @$dir10,$R13 */
1221 {
1222 FR30_INSN_DMOV2R13, "dmov2r13", "dmov", 16,
1223 { 0, { (1<<MACH_BASE) } }
1224 },
1225/* dmovh @$dir9,$R13 */
1226 {
1227 FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh", 16,
1228 { 0, { (1<<MACH_BASE) } }
1229 },
1230/* dmovb @$dir8,$R13 */
1231 {
1232 FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb", 16,
1233 { 0, { (1<<MACH_BASE) } }
1234 },
1235/* dmov @$dir10,@$R13+ */
1236 {
1237 FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov", 16,
1238 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1239 },
1240/* dmovh @$dir9,@$R13+ */
1241 {
1242 FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh", 16,
1243 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1244 },
1245/* dmovb @$dir8,@$R13+ */
1246 {
1247 FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb", 16,
1248 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1249 },
1250/* dmov @$dir10,@-$R15 */
1251 {
1252 FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov", 16,
1253 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1254 },
1255/* ldres @$Ri+,$u4 */
1256 {
1257 FR30_INSN_LDRES, "ldres", "ldres", 16,
1258 { 0, { (1<<MACH_BASE) } }
1259 },
1260/* stres $u4,@$Ri+ */
1261 {
1262 FR30_INSN_STRES, "stres", "stres", 16,
1263 { 0, { (1<<MACH_BASE) } }
1264 },
1265/* copop $u4c,$ccc,$CRj,$CRi */
1266 {
1267 FR30_INSN_COPOP, "copop", "copop", 32,
1268 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1269 },
1270/* copld $u4c,$ccc,$Rjc,$CRi */
1271 {
1272 FR30_INSN_COPLD, "copld", "copld", 32,
1273 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1274 },
1275/* copst $u4c,$ccc,$CRj,$Ric */
1276 {
1277 FR30_INSN_COPST, "copst", "copst", 32,
1278 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1279 },
1280/* copsv $u4c,$ccc,$CRj,$Ric */
1281 {
1282 FR30_INSN_COPSV, "copsv", "copsv", 32,
1283 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1284 },
1285/* nop */
1286 {
1287 FR30_INSN_NOP, "nop", "nop", 16,
1288 { 0, { (1<<MACH_BASE) } }
1289 },
1290/* andccr $u8 */
1291 {
1292 FR30_INSN_ANDCCR, "andccr", "andccr", 16,
1293 { 0, { (1<<MACH_BASE) } }
1294 },
1295/* orccr $u8 */
1296 {
1297 FR30_INSN_ORCCR, "orccr", "orccr", 16,
1298 { 0, { (1<<MACH_BASE) } }
1299 },
1300/* stilm $u8 */
1301 {
1302 FR30_INSN_STILM, "stilm", "stilm", 16,
1303 { 0, { (1<<MACH_BASE) } }
1304 },
1305/* addsp $s10 */
1306 {
1307 FR30_INSN_ADDSP, "addsp", "addsp", 16,
1308 { 0, { (1<<MACH_BASE) } }
1309 },
1310/* extsb $Ri */
1311 {
1312 FR30_INSN_EXTSB, "extsb", "extsb", 16,
1313 { 0, { (1<<MACH_BASE) } }
1314 },
1315/* extub $Ri */
1316 {
1317 FR30_INSN_EXTUB, "extub", "extub", 16,
1318 { 0, { (1<<MACH_BASE) } }
1319 },
1320/* extsh $Ri */
1321 {
1322 FR30_INSN_EXTSH, "extsh", "extsh", 16,
1323 { 0, { (1<<MACH_BASE) } }
1324 },
1325/* extuh $Ri */
1326 {
1327 FR30_INSN_EXTUH, "extuh", "extuh", 16,
1328 { 0, { (1<<MACH_BASE) } }
1329 },
1330/* ldm0 ($reglist_low_ld) */
1331 {
1332 FR30_INSN_LDM0, "ldm0", "ldm0", 16,
1333 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1334 },
1335/* ldm1 ($reglist_hi_ld) */
1336 {
1337 FR30_INSN_LDM1, "ldm1", "ldm1", 16,
1338 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1339 },
1340/* stm0 ($reglist_low_st) */
1341 {
1342 FR30_INSN_STM0, "stm0", "stm0", 16,
1343 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1344 },
1345/* stm1 ($reglist_hi_st) */
1346 {
1347 FR30_INSN_STM1, "stm1", "stm1", 16,
1348 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1349 },
1350/* enter $u10 */
1351 {
1352 FR30_INSN_ENTER, "enter", "enter", 16,
1353 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1354 },
1355/* leave */
1356 {
1357 FR30_INSN_LEAVE, "leave", "leave", 16,
1358 { 0, { (1<<MACH_BASE) } }
1359 },
1360/* xchb @$Rj,$Ri */
1361 {
1362 FR30_INSN_XCHB, "xchb", "xchb", 16,
1363 { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1364 },
1365};
1366
252b5132 1367#undef OP
b3466c39 1368#undef A
252b5132
RH		 1369
1370/* Initialize anything needed to be done once, before any cpu_open call. */
1371
1372static void
1373init_tables ()
1374{
1375}
1376
1377/* Subroutine of fr30_cgen_cpu_open to look up a mach via its bfd name. */
1378
1379static const CGEN_MACH *
1380lookup_mach_via_bfd_name (table, name)
1381 const CGEN_MACH *table;
1382 const char *name;
1383{
1384 while (table->name)
1385 {
1386 if (strcmp (name, table->bfd_name) == 0)
1387 return table;
1388 ++table;
1389 }
1390 abort ();
1391}
1392
1393/* Subroutine of fr30_cgen_cpu_open to build the hardware table. */
1394
1395static void
1396build_hw_table (cd)
1397 CGEN_CPU_TABLE *cd;
1398{
1399 int i;
1400 int machs = cd->machs;
1401 const CGEN_HW_ENTRY *init = & fr30_cgen_hw_table[0];
1402 /* MAX_HW is only an upper bound on the number of selected entries.
1403 However each entry is indexed by it's enum so there can be holes in
1404 the table. */
1405 const CGEN_HW_ENTRY **selected =
1406 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1407
1408 cd->hw_table.init_entries = init;
1409 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1410 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1411 /* ??? For now we just use machs to determine which ones we want. */
1412 for (i = 0; init[i].name != NULL; ++i)
1413 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1414 & machs)
1415 selected[init[i].type] = &init[i];
1416 cd->hw_table.entries = selected;
1417 cd->hw_table.num_entries = MAX_HW;
1418}
1419
1420/* Subroutine of fr30_cgen_cpu_open to build the hardware table. */
1421
1422static void
1423build_ifield_table (cd)
1424 CGEN_CPU_TABLE *cd;
1425{
1426 cd->ifld_table = & fr30_cgen_ifld_table[0];
1427}
1428
1429/* Subroutine of fr30_cgen_cpu_open to build the hardware table. */
1430
1431static void
1432build_operand_table (cd)
1433 CGEN_CPU_TABLE *cd;
1434{
1435 int i;
1436 int machs = cd->machs;
1437 const CGEN_OPERAND *init = & fr30_cgen_operand_table[0];
1438 /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1439 However each entry is indexed by it's enum so there can be holes in
1440 the table. */
1441 const CGEN_OPERAND **selected =
1442 (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1443
1444 cd->operand_table.init_entries = init;
1445 cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1446 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1447 /* ??? For now we just use mach to determine which ones we want. */
1448 for (i = 0; init[i].name != NULL; ++i)
1449 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1450 & machs)
1451 selected[init[i].type] = &init[i];
1452 cd->operand_table.entries = selected;
1453 cd->operand_table.num_entries = MAX_OPERANDS;
1454}
1455
1456/* Subroutine of fr30_cgen_cpu_open to build the hardware table.
1457 ??? This could leave out insns not supported by the specified mach/isa,
1458 but that would cause errors like "foo only supported by bar" to become
1459 "unknown insn", so for now we include all insns and require the app to
1460 do the checking later.
1461 ??? On the other hand, parsing of such insns may require their hardware or
1462 operand elements to be in the table [which they mightn't be]. */
1463
1464static void
1465build_insn_table (cd)
1466 CGEN_CPU_TABLE *cd;
1467{
1468 int i;
1469 const CGEN_IBASE *ib = & fr30_cgen_insn_table[0];
1470 CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1471
1472 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1473 for (i = 0; i < MAX_INSNS; ++i)
1474 insns[i].base = &ib[i];
1475 cd->insn_table.init_entries = insns;
1476 cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1477 cd->insn_table.num_init_entries = MAX_INSNS;
1478}
1479
1480/* Subroutine of fr30_cgen_cpu_open to rebuild the tables. */
1481
1482static void
1483fr30_cgen_rebuild_tables (cd)
1484 CGEN_CPU_TABLE *cd;
1485{
fc7bc883 1486 int i;
252b5132
RH		 1487 unsigned int isas = cd->isas;
1488 unsigned int machs = cd->machs;
1489
1490 cd->int_insn_p = CGEN_INT_INSN_P;
1491
1492 /* Data derived from the isa spec. */
1493#define UNSET (CGEN_SIZE_UNKNOWN + 1)
1494 cd->default_insn_bitsize = UNSET;
1495 cd->base_insn_bitsize = UNSET;
1496 cd->min_insn_bitsize = 65535; /* some ridiculously big number */
1497 cd->max_insn_bitsize = 0;
1498 for (i = 0; i < MAX_ISAS; ++i)
1499 if (((1 << i) & isas) != 0)
1500 {
1501 const CGEN_ISA *isa = & fr30_cgen_isa_table[i];
1502
1503 /* Default insn sizes of all selected isas must be equal or we set
1504 the result to 0, meaning "unknown". */
1505 if (cd->default_insn_bitsize == UNSET)
1506 cd->default_insn_bitsize = isa->default_insn_bitsize;
1507 else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1508 ; /* this is ok */
1509 else
1510 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1511
1512 /* Base insn sizes of all selected isas must be equal or we set
1513 the result to 0, meaning "unknown". */
1514 if (cd->base_insn_bitsize == UNSET)
1515 cd->base_insn_bitsize = isa->base_insn_bitsize;
1516 else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1517 ; /* this is ok */
1518 else
1519 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1520
1521 /* Set min,max insn sizes. */
1522 if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1523 cd->min_insn_bitsize = isa->min_insn_bitsize;
1524 if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1525 cd->max_insn_bitsize = isa->max_insn_bitsize;
252b5132
RH		 1526 }
1527
1528 /* Data derived from the mach spec. */
1529 for (i = 0; i < MAX_MACHS; ++i)
1530 if (((1 << i) & machs) != 0)
1531 {
1532 const CGEN_MACH *mach = & fr30_cgen_mach_table[i];
1533
fc7bc883
RH		 1534 if (mach->insn_chunk_bitsize != 0)
1535 {
1536 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
1537 {
1538 fprintf (stderr, "fr30_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
1539 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
1540 abort ();
1541 }
1542
1543 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
1544 }
252b5132
RH		 1545 }
1546
1547 /* Determine which hw elements are used by MACH. */
1548 build_hw_table (cd);
1549
1550 /* Build the ifield table. */
1551 build_ifield_table (cd);
1552
1553 /* Determine which operands are used by MACH/ISA. */
1554 build_operand_table (cd);
1555
1556 /* Build the instruction table. */
1557 build_insn_table (cd);
1558}
1559
1560/* Initialize a cpu table and return a descriptor.
1561 It's much like opening a file, and must be the first function called.
1562 The arguments are a set of (type/value) pairs, terminated with
1563 CGEN_CPU_OPEN_END.
1564
1565 Currently supported values:
1566 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
1567 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
1568 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1569 CGEN_CPU_OPEN_ENDIAN: specify endian choice
1570 CGEN_CPU_OPEN_END: terminates arguments
1571
1572 ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1573 precluded.
1574
1575 ??? We only support ISO C stdargs here, not K&R.
1576 Laziness, plus experiment to see if anything requires K&R - eventually
1577 K&R will no longer be supported - e.g. GDB is currently trying this. */
1578
1579CGEN_CPU_DESC
1580fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1581{
1582 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1583 static int init_p;
1584 unsigned int isas = 0; /* 0 = "unspecified" */
1585 unsigned int machs = 0; /* 0 = "unspecified" */
1586 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1587 va_list ap;
1588
1589 if (! init_p)
1590 {
1591 init_tables ();
1592 init_p = 1;
1593 }
1594
1595 memset (cd, 0, sizeof (*cd));
1596
1597 va_start (ap, arg_type);
1598 while (arg_type != CGEN_CPU_OPEN_END)
1599 {
1600 switch (arg_type)
1601 {
1602 case CGEN_CPU_OPEN_ISAS :
1603 isas = va_arg (ap, unsigned int);
1604 break;
1605 case CGEN_CPU_OPEN_MACHS :
1606 machs = va_arg (ap, unsigned int);
1607 break;
1608 case CGEN_CPU_OPEN_BFDMACH :
1609 {
1610 const char *name = va_arg (ap, const char *);
1611 const CGEN_MACH *mach =
1612 lookup_mach_via_bfd_name (fr30_cgen_mach_table, name);
1613
27fca2d8 1614 machs |= 1 << mach->num;
252b5132
RH		 1615 break;
1616 }
1617 case CGEN_CPU_OPEN_ENDIAN :
1618 endian = va_arg (ap, enum cgen_endian);
1619 break;
1620 default :
1621 fprintf (stderr, "fr30_cgen_cpu_open: unsupported argument `%d'\n",
1622 arg_type);
1623 abort (); /* ??? return NULL? */
1624 }
1625 arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1626 }
1627 va_end (ap);
1628
1629 /* mach unspecified means "all" */
1630 if (machs == 0)
1631 machs = (1 << MAX_MACHS) - 1;
1632 /* base mach is always selected */
1633 machs |= 1;
1634 /* isa unspecified means "all" */
1635 if (isas == 0)
1636 isas = (1 << MAX_ISAS) - 1;
1637 if (endian == CGEN_ENDIAN_UNKNOWN)
1638 {
1639 /* ??? If target has only one, could have a default. */
1640 fprintf (stderr, "fr30_cgen_cpu_open: no endianness specified\n");
1641 abort ();
1642 }
1643
1644 cd->isas = isas;
1645 cd->machs = machs;
1646 cd->endian = endian;
1647 /* FIXME: for the sparc case we can determine insn-endianness statically.
1648 The worry here is where both data and insn endian can be independently
1649 chosen, in which case this function will need another argument.
1650 Actually, will want to allow for more arguments in the future anyway. */
1651 cd->insn_endian = endian;
1652
1653 /* Table (re)builder. */
1654 cd->rebuild_tables = fr30_cgen_rebuild_tables;
1655 fr30_cgen_rebuild_tables (cd);
1656
6bb95a0f 1657 /* Default to not allowing signed overflow. */
447b43fa
NC		 1658 cd->signed_overflow_ok_p = 0;
1659
252b5132
RH		 1660 return (CGEN_CPU_DESC) cd;
1661}
1662
1663/* Cover fn to fr30_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1664 MACH_NAME is the bfd name of the mach. */
1665
1666CGEN_CPU_DESC
1667fr30_cgen_cpu_open_1 (mach_name, endian)
1668 const char *mach_name;
1669 enum cgen_endian endian;
1670{
1671 return fr30_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1672 CGEN_CPU_OPEN_ENDIAN, endian,
1673 CGEN_CPU_OPEN_END);
1674}
1675
1676/* Close a cpu table.
1677 ??? This can live in a machine independent file, but there's currently
1678 no place to put this file (there's no libcgen). libopcodes is the wrong
1679 place as some simulator ports use this but they don't use libopcodes. */
1680
1681void
1682fr30_cgen_cpu_close (cd)
1683 CGEN_CPU_DESC cd;
1684{
1685 if (cd->insn_table.init_entries)
1686 free ((CGEN_INSN *) cd->insn_table.init_entries);
1687 if (cd->hw_table.entries)
1688 free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1689 free (cd);
1690}
1691
GDB Binutils - Deliverables
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