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252b5132 RH |
1 | /* Disassembler interface for targets using CGEN. -*- C -*- |
2 | CGEN: Cpu tools GENerator | |
3 | ||
4 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
5 | - the resultant file is machine generated, cgen-dis.in isn't | |
6 | ||
7 | Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. | |
8 | ||
9 | This file is part of the GNU Binutils and GDB, the GNU debugger. | |
10 | ||
11 | This program is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | This program is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with this program; if not, write to the Free Software Foundation, Inc., | |
23 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
24 | ||
25 | /* ??? Eventually more and more of this stuff can go to cpu-independent files. | |
26 | Keep that in mind. */ | |
27 | ||
28 | #include "sysdep.h" | |
29 | #include <stdio.h> | |
30 | #include "ansidecl.h" | |
31 | #include "dis-asm.h" | |
32 | #include "bfd.h" | |
33 | #include "symcat.h" | |
34 | #include "fr30-desc.h" | |
35 | #include "fr30-opc.h" | |
36 | #include "opintl.h" | |
37 | ||
38 | /* Default text to print if an instruction isn't recognized. */ | |
39 | #define UNKNOWN_INSN_MSG _("*unknown*") | |
40 | ||
41 | static void print_normal | |
42 | PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int)); | |
43 | static void print_address | |
44 | PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int)); | |
45 | static void print_keyword | |
46 | PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int)); | |
47 | static void print_insn_normal | |
48 | PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, | |
49 | bfd_vma, int)); | |
50 | static int print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, | |
51 | disassemble_info *, char *, int)); | |
52 | static int default_print_insn | |
53 | PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); | |
54 | \f | |
55 | /* -- disassembler routines inserted here */ | |
56 | ||
57 | /* -- dis.c */ | |
58 | ||
59 | static void | |
60 | print_register_list (dis_info, value, offset, load_store) | |
61 | PTR dis_info; | |
62 | long value; | |
63 | long offset; | |
64 | int load_store; /* 0 == load, 1 == store */ | |
65 | { | |
66 | disassemble_info *info = dis_info; | |
67 | int mask; | |
68 | int index = 0; | |
69 | char* comma = ""; | |
70 | ||
71 | if (load_store) | |
72 | mask = 0x80; | |
73 | else | |
74 | mask = 1; | |
75 | ||
76 | if (value & mask) | |
77 | { | |
78 | (*info->fprintf_func) (info->stream, "r%i", index + offset); | |
79 | comma = ","; | |
80 | } | |
81 | ||
82 | for (index = 1; index <= 7; ++index) | |
83 | { | |
84 | if (load_store) | |
85 | mask >>= 1; | |
86 | else | |
87 | mask <<= 1; | |
88 | ||
89 | if (value & mask) | |
90 | { | |
91 | (*info->fprintf_func) (info->stream, "%sr%i", comma, index + offset); | |
92 | comma = ","; | |
93 | } | |
94 | } | |
95 | } | |
96 | ||
97 | static void | |
98 | print_hi_register_list_ld (cd, dis_info, value, attrs, pc, length) | |
99 | CGEN_CPU_DESC cd; | |
100 | PTR dis_info; | |
101 | long value; | |
102 | unsigned int attrs; | |
103 | bfd_vma pc; | |
104 | int length; | |
105 | { | |
106 | print_register_list (dis_info, value, 8, 0/*load*/); | |
107 | } | |
108 | ||
109 | static void | |
110 | print_low_register_list_ld (cd, dis_info, value, attrs, pc, length) | |
111 | CGEN_CPU_DESC cd; | |
112 | PTR dis_info; | |
113 | long value; | |
114 | unsigned int attrs; | |
115 | bfd_vma pc; | |
116 | int length; | |
117 | { | |
118 | print_register_list (dis_info, value, 0, 0/*load*/); | |
119 | } | |
120 | ||
121 | static void | |
122 | print_hi_register_list_st (cd, dis_info, value, attrs, pc, length) | |
123 | CGEN_CPU_DESC cd; | |
124 | PTR dis_info; | |
125 | long value; | |
126 | unsigned int attrs; | |
127 | bfd_vma pc; | |
128 | int length; | |
129 | { | |
130 | print_register_list (dis_info, value, 8, 1/*store*/); | |
131 | } | |
132 | ||
133 | static void | |
134 | print_low_register_list_st (cd, dis_info, value, attrs, pc, length) | |
135 | CGEN_CPU_DESC cd; | |
136 | PTR dis_info; | |
137 | long value; | |
138 | unsigned int attrs; | |
139 | bfd_vma pc; | |
140 | int length; | |
141 | { | |
142 | print_register_list (dis_info, value, 0, 1/*store*/); | |
143 | } | |
144 | ||
145 | static void | |
146 | print_m4 (cd, dis_info, value, attrs, pc, length) | |
147 | CGEN_CPU_DESC cd; | |
148 | PTR dis_info; | |
149 | long value; | |
150 | unsigned int attrs; | |
151 | bfd_vma pc; | |
152 | int length; | |
153 | { | |
154 | disassemble_info *info = (disassemble_info *) dis_info; | |
155 | (*info->fprintf_func) (info->stream, "%ld", value); | |
156 | } | |
157 | /* -- */ | |
158 | ||
159 | /* Main entry point for printing operands. | |
160 | XINFO is a `void *' and not a `disassemble_info *' to not put a requirement | |
161 | of dis-asm.h on cgen.h. | |
162 | ||
163 | This function is basically just a big switch statement. Earlier versions | |
164 | used tables to look up the function to use, but | |
165 | - if the table contains both assembler and disassembler functions then | |
166 | the disassembler contains much of the assembler and vice-versa, | |
167 | - there's a lot of inlining possibilities as things grow, | |
168 | - using a switch statement avoids the function call overhead. | |
169 | ||
170 | This function could be moved into `print_insn_normal', but keeping it | |
171 | separate makes clear the interface between `print_insn_normal' and each of | |
172 | the handlers. | |
173 | */ | |
174 | ||
175 | void | |
176 | fr30_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) | |
177 | CGEN_CPU_DESC cd; | |
178 | int opindex; | |
179 | PTR xinfo; | |
180 | CGEN_FIELDS *fields; | |
181 | void const *attrs; | |
182 | bfd_vma pc; | |
183 | int length; | |
184 | { | |
185 | disassemble_info *info = (disassemble_info *) xinfo; | |
186 | ||
187 | switch (opindex) | |
188 | { | |
189 | case FR30_OPERAND_CRI : | |
190 | print_keyword (cd, info, & fr30_cgen_opval_cr_names, fields->f_CRi, 0); | |
191 | break; | |
192 | case FR30_OPERAND_CRJ : | |
193 | print_keyword (cd, info, & fr30_cgen_opval_cr_names, fields->f_CRj, 0); | |
194 | break; | |
195 | case FR30_OPERAND_R13 : | |
eb1b03df | 196 | print_keyword (cd, info, & fr30_cgen_opval_h_r13, 0, 0); |
252b5132 RH |
197 | break; |
198 | case FR30_OPERAND_R14 : | |
eb1b03df | 199 | print_keyword (cd, info, & fr30_cgen_opval_h_r14, 0, 0); |
252b5132 RH |
200 | break; |
201 | case FR30_OPERAND_R15 : | |
eb1b03df | 202 | print_keyword (cd, info, & fr30_cgen_opval_h_r15, 0, 0); |
252b5132 RH |
203 | break; |
204 | case FR30_OPERAND_RI : | |
205 | print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Ri, 0); | |
206 | break; | |
207 | case FR30_OPERAND_RIC : | |
208 | print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Ric, 0); | |
209 | break; | |
210 | case FR30_OPERAND_RJ : | |
211 | print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Rj, 0); | |
212 | break; | |
213 | case FR30_OPERAND_RJC : | |
214 | print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Rjc, 0); | |
215 | break; | |
216 | case FR30_OPERAND_RS1 : | |
217 | print_keyword (cd, info, & fr30_cgen_opval_dr_names, fields->f_Rs1, 0); | |
218 | break; | |
219 | case FR30_OPERAND_RS2 : | |
220 | print_keyword (cd, info, & fr30_cgen_opval_dr_names, fields->f_Rs2, 0); | |
221 | break; | |
222 | case FR30_OPERAND_CC : | |
223 | print_normal (cd, info, fields->f_cc, 0, pc, length); | |
224 | break; | |
225 | case FR30_OPERAND_CCC : | |
226 | print_normal (cd, info, fields->f_ccc, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
227 | break; | |
228 | case FR30_OPERAND_DIR10 : | |
229 | print_normal (cd, info, fields->f_dir10, 0, pc, length); | |
230 | break; | |
231 | case FR30_OPERAND_DIR8 : | |
232 | print_normal (cd, info, fields->f_dir8, 0, pc, length); | |
233 | break; | |
234 | case FR30_OPERAND_DIR9 : | |
235 | print_normal (cd, info, fields->f_dir9, 0, pc, length); | |
236 | break; | |
237 | case FR30_OPERAND_DISP10 : | |
238 | print_normal (cd, info, fields->f_disp10, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
239 | break; | |
240 | case FR30_OPERAND_DISP8 : | |
241 | print_normal (cd, info, fields->f_disp8, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
242 | break; | |
243 | case FR30_OPERAND_DISP9 : | |
244 | print_normal (cd, info, fields->f_disp9, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
245 | break; | |
246 | case FR30_OPERAND_I20 : | |
247 | print_normal (cd, info, fields->f_i20, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); | |
248 | break; | |
249 | case FR30_OPERAND_I32 : | |
250 | print_normal (cd, info, fields->f_i32, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT), pc, length); | |
251 | break; | |
252 | case FR30_OPERAND_I8 : | |
253 | print_normal (cd, info, fields->f_i8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
254 | break; | |
255 | case FR30_OPERAND_LABEL12 : | |
256 | print_address (cd, info, fields->f_rel12, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); | |
257 | break; | |
258 | case FR30_OPERAND_LABEL9 : | |
259 | print_address (cd, info, fields->f_rel9, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); | |
260 | break; | |
261 | case FR30_OPERAND_M4 : | |
262 | print_m4 (cd, info, fields->f_m4, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
263 | break; | |
264 | case FR30_OPERAND_PS : | |
eb1b03df | 265 | print_keyword (cd, info, & fr30_cgen_opval_h_ps, 0, 0); |
252b5132 RH |
266 | break; |
267 | case FR30_OPERAND_REGLIST_HI_LD : | |
268 | print_hi_register_list_ld (cd, info, fields->f_reglist_hi_ld, 0, pc, length); | |
269 | break; | |
270 | case FR30_OPERAND_REGLIST_HI_ST : | |
271 | print_hi_register_list_st (cd, info, fields->f_reglist_hi_st, 0, pc, length); | |
272 | break; | |
273 | case FR30_OPERAND_REGLIST_LOW_LD : | |
274 | print_low_register_list_ld (cd, info, fields->f_reglist_low_ld, 0, pc, length); | |
275 | break; | |
276 | case FR30_OPERAND_REGLIST_LOW_ST : | |
277 | print_low_register_list_st (cd, info, fields->f_reglist_low_st, 0, pc, length); | |
278 | break; | |
279 | case FR30_OPERAND_S10 : | |
280 | print_normal (cd, info, fields->f_s10, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
281 | break; | |
282 | case FR30_OPERAND_U10 : | |
283 | print_normal (cd, info, fields->f_u10, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
284 | break; | |
285 | case FR30_OPERAND_U4 : | |
286 | print_normal (cd, info, fields->f_u4, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
287 | break; | |
288 | case FR30_OPERAND_U4C : | |
289 | print_normal (cd, info, fields->f_u4c, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
290 | break; | |
291 | case FR30_OPERAND_U8 : | |
292 | print_normal (cd, info, fields->f_u8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
293 | break; | |
294 | case FR30_OPERAND_UDISP6 : | |
295 | print_normal (cd, info, fields->f_udisp6, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
296 | break; | |
297 | ||
298 | default : | |
299 | /* xgettext:c-format */ | |
300 | fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), | |
301 | opindex); | |
302 | abort (); | |
303 | } | |
304 | } | |
305 | ||
306 | cgen_print_fn * const fr30_cgen_print_handlers[] = | |
307 | { | |
308 | print_insn_normal, | |
309 | }; | |
310 | ||
311 | ||
312 | void | |
313 | fr30_cgen_init_dis (cd) | |
314 | CGEN_CPU_DESC cd; | |
315 | { | |
316 | fr30_cgen_init_opcode_table (cd); | |
317 | fr30_cgen_init_ibld_table (cd); | |
318 | cd->print_handlers = & fr30_cgen_print_handlers[0]; | |
319 | cd->print_operand = fr30_cgen_print_operand; | |
320 | } | |
321 | ||
322 | \f | |
323 | /* Default print handler. */ | |
324 | ||
325 | static void | |
326 | print_normal (cd, dis_info, value, attrs, pc, length) | |
6bb95a0f | 327 | #ifdef CGEN_PRINT_NORMAL |
252b5132 | 328 | CGEN_CPU_DESC cd; |
6bb95a0f DB |
329 | #else |
330 | CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; | |
331 | #endif | |
252b5132 RH |
332 | PTR dis_info; |
333 | long value; | |
334 | unsigned int attrs; | |
6bb95a0f | 335 | #ifdef CGEN_PRINT_NORMAL |
252b5132 RH |
336 | bfd_vma pc; |
337 | int length; | |
6bb95a0f DB |
338 | #else |
339 | bfd_vma pc ATTRIBUTE_UNUSED; | |
340 | int length ATTRIBUTE_UNUSED; | |
341 | #endif | |
252b5132 RH |
342 | { |
343 | disassemble_info *info = (disassemble_info *) dis_info; | |
344 | ||
345 | #ifdef CGEN_PRINT_NORMAL | |
346 | CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length); | |
347 | #endif | |
348 | ||
349 | /* Print the operand as directed by the attributes. */ | |
350 | if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) | |
351 | ; /* nothing to do */ | |
352 | else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) | |
353 | (*info->fprintf_func) (info->stream, "%ld", value); | |
354 | else | |
355 | (*info->fprintf_func) (info->stream, "0x%lx", value); | |
356 | } | |
357 | ||
358 | /* Default address handler. */ | |
359 | ||
360 | static void | |
361 | print_address (cd, dis_info, value, attrs, pc, length) | |
6bb95a0f | 362 | #ifdef CGEN_PRINT_NORMAL |
252b5132 | 363 | CGEN_CPU_DESC cd; |
6bb95a0f DB |
364 | #else |
365 | CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; | |
366 | #endif | |
252b5132 RH |
367 | PTR dis_info; |
368 | bfd_vma value; | |
369 | unsigned int attrs; | |
6bb95a0f | 370 | #ifdef CGEN_PRINT_NORMAL |
252b5132 RH |
371 | bfd_vma pc; |
372 | int length; | |
6bb95a0f DB |
373 | #else |
374 | bfd_vma pc ATTRIBUTE_UNUSED; | |
375 | int length ATTRIBUTE_UNUSED; | |
376 | #endif | |
252b5132 RH |
377 | { |
378 | disassemble_info *info = (disassemble_info *) dis_info; | |
379 | ||
380 | #ifdef CGEN_PRINT_ADDRESS | |
381 | CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length); | |
382 | #endif | |
383 | ||
384 | /* Print the operand as directed by the attributes. */ | |
385 | if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) | |
386 | ; /* nothing to do */ | |
387 | else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) | |
388 | (*info->print_address_func) (value, info); | |
389 | else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) | |
390 | (*info->print_address_func) (value, info); | |
391 | else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) | |
392 | (*info->fprintf_func) (info->stream, "%ld", (long) value); | |
393 | else | |
394 | (*info->fprintf_func) (info->stream, "0x%lx", (long) value); | |
395 | } | |
396 | ||
397 | /* Keyword print handler. */ | |
398 | ||
399 | static void | |
400 | print_keyword (cd, dis_info, keyword_table, value, attrs) | |
6bb95a0f | 401 | CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; |
252b5132 RH |
402 | PTR dis_info; |
403 | CGEN_KEYWORD *keyword_table; | |
404 | long value; | |
6bb95a0f | 405 | unsigned int attrs ATTRIBUTE_UNUSED; |
252b5132 RH |
406 | { |
407 | disassemble_info *info = (disassemble_info *) dis_info; | |
408 | const CGEN_KEYWORD_ENTRY *ke; | |
409 | ||
410 | ke = cgen_keyword_lookup_value (keyword_table, value); | |
411 | if (ke != NULL) | |
412 | (*info->fprintf_func) (info->stream, "%s", ke->name); | |
413 | else | |
414 | (*info->fprintf_func) (info->stream, "???"); | |
415 | } | |
416 | \f | |
417 | /* Default insn printer. | |
418 | ||
419 | DIS_INFO is defined as `PTR' so the disassembler needn't know anything | |
420 | about disassemble_info. */ | |
421 | ||
422 | static void | |
423 | print_insn_normal (cd, dis_info, insn, fields, pc, length) | |
424 | CGEN_CPU_DESC cd; | |
425 | PTR dis_info; | |
426 | const CGEN_INSN *insn; | |
427 | CGEN_FIELDS *fields; | |
428 | bfd_vma pc; | |
429 | int length; | |
430 | { | |
431 | const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); | |
432 | disassemble_info *info = (disassemble_info *) dis_info; | |
433 | const unsigned char *syn; | |
434 | ||
435 | CGEN_INIT_PRINT (cd); | |
436 | ||
437 | for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) | |
438 | { | |
439 | if (CGEN_SYNTAX_MNEMONIC_P (*syn)) | |
440 | { | |
441 | (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); | |
442 | continue; | |
443 | } | |
444 | if (CGEN_SYNTAX_CHAR_P (*syn)) | |
445 | { | |
446 | (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); | |
447 | continue; | |
448 | } | |
449 | ||
450 | /* We have an operand. */ | |
451 | fr30_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, | |
452 | fields, CGEN_INSN_ATTRS (insn), pc, length); | |
453 | } | |
454 | } | |
455 | \f | |
6bb95a0f DB |
456 | /* Subroutine of print_insn. Reads an insn into the given buffers and updates |
457 | the extract info. | |
458 | Returns 0 if all is well, non-zero otherwise. */ | |
252b5132 | 459 | static int |
6bb95a0f | 460 | read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) |
252b5132 RH |
461 | CGEN_CPU_DESC cd; |
462 | bfd_vma pc; | |
463 | disassemble_info *info; | |
464 | char *buf; | |
465 | int buflen; | |
6bb95a0f DB |
466 | CGEN_EXTRACT_INFO *ex_info; |
467 | unsigned long *insn_value; | |
252b5132 | 468 | { |
6bb95a0f DB |
469 | int status = (*info->read_memory_func) (pc, buf, buflen, info); |
470 | if (status != 0) | |
471 | { | |
472 | (*info->memory_error_func) (status, pc, info); | |
473 | return -1; | |
474 | } | |
252b5132 | 475 | |
6bb95a0f DB |
476 | ex_info->dis_info = info; |
477 | ex_info->valid = (1 << buflen) - 1; | |
478 | ex_info->insn_bytes = buf; | |
252b5132 RH |
479 | |
480 | switch (buflen) | |
481 | { | |
482 | case 1: | |
6bb95a0f | 483 | *insn_value = buf[0]; |
252b5132 RH |
484 | break; |
485 | case 2: | |
6bb95a0f | 486 | *insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb16 (buf) : bfd_getl16 (buf); |
252b5132 RH |
487 | break; |
488 | case 4: | |
6bb95a0f | 489 | *insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb32 (buf) : bfd_getl32 (buf); |
252b5132 RH |
490 | break; |
491 | default: | |
492 | abort (); | |
493 | } | |
494 | ||
6bb95a0f DB |
495 | return 0; |
496 | } | |
497 | ||
498 | /* Utility to print an insn. | |
499 | BUF is the base part of the insn, target byte order, BUFLEN bytes long. | |
500 | The result is the size of the insn in bytes or zero for an unknown insn | |
501 | or -1 if an error occurs fetching data (memory_error_func will have | |
502 | been called). */ | |
503 | ||
504 | static int | |
505 | print_insn (cd, pc, info, buf, buflen) | |
506 | CGEN_CPU_DESC cd; | |
507 | bfd_vma pc; | |
508 | disassemble_info *info; | |
509 | char *buf; | |
510 | int buflen; | |
511 | { | |
512 | unsigned long insn_value; | |
513 | const CGEN_INSN_LIST *insn_list; | |
514 | CGEN_EXTRACT_INFO ex_info; | |
515 | ||
516 | int rc = read_insn (cd, pc, info, buf, buflen, & ex_info, & insn_value); | |
517 | if (rc != 0) | |
518 | return rc; | |
519 | ||
252b5132 RH |
520 | /* The instructions are stored in hash lists. |
521 | Pick the first one and keep trying until we find the right one. */ | |
522 | ||
523 | insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value); | |
524 | while (insn_list != NULL) | |
525 | { | |
526 | const CGEN_INSN *insn = insn_list->insn; | |
527 | CGEN_FIELDS fields; | |
528 | int length; | |
529 | ||
6bb95a0f DB |
530 | #ifdef CGEN_VALIDATE_INSN_SUPPORTED |
531 | /* not needed as insn shouldn't be in hash lists if not supported */ | |
252b5132 RH |
532 | /* Supported by this cpu? */ |
533 | if (! fr30_cgen_insn_supported (cd, insn)) | |
6bb95a0f DB |
534 | { |
535 | insn_list = CGEN_DIS_NEXT_INSN (insn_list); | |
536 | continue; | |
537 | } | |
252b5132 RH |
538 | #endif |
539 | ||
540 | /* Basic bit mask must be correct. */ | |
541 | /* ??? May wish to allow target to defer this check until the extract | |
542 | handler. */ | |
543 | if ((insn_value & CGEN_INSN_BASE_MASK (insn)) | |
544 | == CGEN_INSN_BASE_VALUE (insn)) | |
545 | { | |
546 | /* Printing is handled in two passes. The first pass parses the | |
547 | machine insn and extracts the fields. The second pass prints | |
548 | them. */ | |
549 | ||
6bb95a0f DB |
550 | #if CGEN_INT_INSN_P |
551 | /* Make sure the entire insn is loaded into insn_value. */ | |
552 | if (CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) | |
553 | { | |
554 | unsigned long full_insn_value; | |
555 | int rc = read_insn (cd, pc, info, buf, | |
556 | CGEN_INSN_BITSIZE (insn) / 8, | |
557 | & ex_info, & full_insn_value); | |
558 | if (rc != 0) | |
559 | return rc; | |
560 | length = CGEN_EXTRACT_FN (cd, insn) | |
561 | (cd, insn, &ex_info, full_insn_value, &fields, pc); | |
562 | } | |
563 | else | |
564 | #endif | |
565 | ||
252b5132 RH |
566 | length = CGEN_EXTRACT_FN (cd, insn) |
567 | (cd, insn, &ex_info, insn_value, &fields, pc); | |
568 | /* length < 0 -> error */ | |
569 | if (length < 0) | |
570 | return length; | |
571 | if (length > 0) | |
572 | { | |
573 | CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); | |
574 | /* length is in bits, result is in bytes */ | |
575 | return length / 8; | |
576 | } | |
577 | } | |
578 | ||
579 | insn_list = CGEN_DIS_NEXT_INSN (insn_list); | |
580 | } | |
581 | ||
582 | return 0; | |
583 | } | |
584 | ||
585 | /* Default value for CGEN_PRINT_INSN. | |
586 | The result is the size of the insn in bytes or zero for an unknown insn | |
587 | or -1 if an error occured fetching bytes. */ | |
588 | ||
589 | #ifndef CGEN_PRINT_INSN | |
590 | #define CGEN_PRINT_INSN default_print_insn | |
591 | #endif | |
592 | ||
593 | static int | |
594 | default_print_insn (cd, pc, info) | |
595 | CGEN_CPU_DESC cd; | |
596 | bfd_vma pc; | |
597 | disassemble_info *info; | |
598 | { | |
599 | char buf[CGEN_MAX_INSN_SIZE]; | |
600 | int status; | |
601 | ||
602 | /* Read the base part of the insn. */ | |
603 | ||
604 | status = (*info->read_memory_func) (pc, buf, cd->base_insn_bitsize / 8, info); | |
605 | if (status != 0) | |
606 | { | |
607 | (*info->memory_error_func) (status, pc, info); | |
608 | return -1; | |
609 | } | |
610 | ||
611 | return print_insn (cd, pc, info, buf, cd->base_insn_bitsize / 8); | |
612 | } | |
613 | ||
614 | /* Main entry point. | |
615 | Print one instruction from PC on INFO->STREAM. | |
616 | Return the size of the instruction (in bytes). */ | |
617 | ||
618 | int | |
619 | print_insn_fr30 (pc, info) | |
620 | bfd_vma pc; | |
621 | disassemble_info *info; | |
622 | { | |
623 | static CGEN_CPU_DESC cd = 0; | |
6bb95a0f DB |
624 | static int prev_isa; |
625 | static int prev_mach; | |
626 | static int prev_endian; | |
252b5132 RH |
627 | int length; |
628 | int isa,mach; | |
629 | int endian = (info->endian == BFD_ENDIAN_BIG | |
630 | ? CGEN_ENDIAN_BIG | |
631 | : CGEN_ENDIAN_LITTLE); | |
632 | enum bfd_architecture arch; | |
633 | ||
634 | /* ??? gdb will set mach but leave the architecture as "unknown" */ | |
635 | #ifndef CGEN_BFD_ARCH | |
636 | #define CGEN_BFD_ARCH bfd_arch_fr30 | |
637 | #endif | |
638 | arch = info->arch; | |
639 | if (arch == bfd_arch_unknown) | |
640 | arch = CGEN_BFD_ARCH; | |
641 | ||
642 | /* There's no standard way to compute the isa number (e.g. for arm thumb) | |
643 | so we leave it to the target. */ | |
644 | #ifdef CGEN_COMPUTE_ISA | |
645 | isa = CGEN_COMPUTE_ISA (info); | |
646 | #else | |
647 | isa = 0; | |
648 | #endif | |
649 | ||
650 | mach = info->mach; | |
651 | ||
652 | /* If we've switched cpu's, close the current table and open a new one. */ | |
653 | if (cd | |
654 | && (isa != prev_isa | |
655 | || mach != prev_mach | |
656 | || endian != prev_endian)) | |
657 | { | |
658 | fr30_cgen_cpu_close (cd); | |
659 | cd = 0; | |
660 | } | |
661 | ||
662 | /* If we haven't initialized yet, initialize the opcode table. */ | |
663 | if (! cd) | |
664 | { | |
665 | const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); | |
666 | const char *mach_name; | |
667 | ||
668 | if (!arch_type) | |
669 | abort (); | |
670 | mach_name = arch_type->printable_name; | |
671 | ||
672 | prev_isa = isa; | |
673 | prev_mach = mach; | |
674 | prev_endian = endian; | |
675 | cd = fr30_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, | |
676 | CGEN_CPU_OPEN_BFDMACH, mach_name, | |
677 | CGEN_CPU_OPEN_ENDIAN, prev_endian, | |
678 | CGEN_CPU_OPEN_END); | |
679 | if (!cd) | |
680 | abort (); | |
681 | fr30_cgen_init_dis (cd); | |
682 | } | |
683 | ||
684 | /* We try to have as much common code as possible. | |
685 | But at this point some targets need to take over. */ | |
686 | /* ??? Some targets may need a hook elsewhere. Try to avoid this, | |
687 | but if not possible try to move this hook elsewhere rather than | |
688 | have two hooks. */ | |
689 | length = CGEN_PRINT_INSN (cd, pc, info); | |
690 | if (length > 0) | |
691 | return length; | |
692 | if (length < 0) | |
693 | return -1; | |
694 | ||
695 | (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); | |
696 | return cd->default_insn_bitsize / 8; | |
697 | } |