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252b5132 RH |
1 | /* Instruction building/extraction support for fr30. -*- C -*- |
2 | ||
3 | THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. | |
4 | - the resultant file is machine generated, cgen-ibld.in isn't | |
5 | ||
060d22b0 | 6 | Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. |
252b5132 RH |
7 | |
8 | This file is part of the GNU Binutils and GDB, the GNU debugger. | |
9 | ||
10 | This program is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | This program is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with this program; if not, write to the Free Software Foundation, Inc., | |
22 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
23 | ||
24 | /* ??? Eventually more and more of this stuff can go to cpu-independent files. | |
25 | Keep that in mind. */ | |
26 | ||
27 | #include "sysdep.h" | |
28 | #include <ctype.h> | |
29 | #include <stdio.h> | |
30 | #include "ansidecl.h" | |
31 | #include "dis-asm.h" | |
32 | #include "bfd.h" | |
33 | #include "symcat.h" | |
34 | #include "fr30-desc.h" | |
35 | #include "fr30-opc.h" | |
36 | #include "opintl.h" | |
37 | ||
38 | #undef min | |
39 | #define min(a,b) ((a) < (b) ? (a) : (b)) | |
40 | #undef max | |
41 | #define max(a,b) ((a) > (b) ? (a) : (b)) | |
42 | ||
43 | /* Used by the ifield rtx function. */ | |
44 | #define FLD(f) (fields->f) | |
45 | ||
46 | static const char * insert_normal | |
47 | PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, | |
48 | unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR)); | |
49 | static const char * insert_insn_normal | |
50 | PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, | |
51 | CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); | |
52 | ||
53 | static int extract_normal | |
54 | PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, | |
55 | unsigned int, unsigned int, unsigned int, unsigned int, | |
56 | unsigned int, unsigned int, bfd_vma, long *)); | |
57 | static int extract_insn_normal | |
58 | PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, | |
59 | CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); | |
6bb95a0f DB |
60 | static void put_insn_int_value |
61 | PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT)); | |
62 | ||
252b5132 RH |
63 | \f |
64 | /* Operand insertion. */ | |
65 | ||
66 | #if ! CGEN_INT_INSN_P | |
67 | ||
68 | /* Subroutine of insert_normal. */ | |
69 | ||
70 | static CGEN_INLINE void | |
71 | insert_1 (cd, value, start, length, word_length, bufp) | |
72 | CGEN_CPU_DESC cd; | |
73 | unsigned long value; | |
74 | int start,length,word_length; | |
75 | unsigned char *bufp; | |
76 | { | |
77 | unsigned long x,mask; | |
78 | int shift; | |
79 | int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; | |
80 | ||
b3466c39 | 81 | x = bfd_get_bits (bufp, word_length, big_p); |
252b5132 RH |
82 | |
83 | /* Written this way to avoid undefined behaviour. */ | |
84 | mask = (((1L << (length - 1)) - 1) << 1) | 1; | |
85 | if (CGEN_INSN_LSB0_P) | |
86 | shift = (start + 1) - length; | |
87 | else | |
88 | shift = (word_length - (start + length)); | |
89 | x = (x & ~(mask << shift)) | ((value & mask) << shift); | |
90 | ||
b3466c39 | 91 | bfd_put_bits ((bfd_vma) x, bufp, word_length, big_p); |
252b5132 RH |
92 | } |
93 | ||
94 | #endif /* ! CGEN_INT_INSN_P */ | |
95 | ||
96 | /* Default insertion routine. | |
97 | ||
98 | ATTRS is a mask of the boolean attributes. | |
99 | WORD_OFFSET is the offset in bits from the start of the insn of the value. | |
100 | WORD_LENGTH is the length of the word in bits in which the value resides. | |
101 | START is the starting bit number in the word, architecture origin. | |
102 | LENGTH is the length of VALUE in bits. | |
103 | TOTAL_LENGTH is the total length of the insn in bits. | |
104 | ||
105 | The result is an error message or NULL if success. */ | |
106 | ||
107 | /* ??? This duplicates functionality with bfd's howto table and | |
108 | bfd_install_relocation. */ | |
109 | /* ??? This doesn't handle bfd_vma's. Create another function when | |
110 | necessary. */ | |
111 | ||
112 | static const char * | |
113 | insert_normal (cd, value, attrs, word_offset, start, length, word_length, | |
114 | total_length, buffer) | |
115 | CGEN_CPU_DESC cd; | |
116 | long value; | |
117 | unsigned int attrs; | |
118 | unsigned int word_offset, start, length, word_length, total_length; | |
119 | CGEN_INSN_BYTES_PTR buffer; | |
120 | { | |
121 | static char errbuf[100]; | |
122 | /* Written this way to avoid undefined behaviour. */ | |
123 | unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; | |
124 | ||
125 | /* If LENGTH is zero, this operand doesn't contribute to the value. */ | |
126 | if (length == 0) | |
127 | return NULL; | |
128 | ||
6bb95a0f | 129 | #if 0 |
252b5132 RH |
130 | if (CGEN_INT_INSN_P |
131 | && word_offset != 0) | |
132 | abort (); | |
6bb95a0f | 133 | #endif |
252b5132 RH |
134 | |
135 | if (word_length > 32) | |
136 | abort (); | |
137 | ||
138 | /* For architectures with insns smaller than the base-insn-bitsize, | |
139 | word_length may be too big. */ | |
140 | if (cd->min_insn_bitsize < cd->base_insn_bitsize) | |
141 | { | |
142 | if (word_offset == 0 | |
143 | && word_length > total_length) | |
144 | word_length = total_length; | |
145 | } | |
146 | ||
147 | /* Ensure VALUE will fit. */ | |
fc7bc883 RH |
148 | if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) |
149 | { | |
150 | long minval = - (1L << (length - 1)); | |
151 | unsigned long maxval = mask; | |
152 | ||
153 | if ((value > 0 && (unsigned long) value > maxval) | |
154 | || value < minval) | |
155 | { | |
156 | /* xgettext:c-format */ | |
157 | sprintf (errbuf, | |
158 | _("operand out of range (%ld not between %ld and %lu)"), | |
159 | value, minval, maxval); | |
160 | return errbuf; | |
161 | } | |
162 | } | |
163 | else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) | |
252b5132 RH |
164 | { |
165 | unsigned long maxval = mask; | |
6bb95a0f | 166 | |
252b5132 RH |
167 | if ((unsigned long) value > maxval) |
168 | { | |
169 | /* xgettext:c-format */ | |
170 | sprintf (errbuf, | |
171 | _("operand out of range (%lu not between 0 and %lu)"), | |
172 | value, maxval); | |
173 | return errbuf; | |
174 | } | |
175 | } | |
176 | else | |
177 | { | |
6bb95a0f | 178 | if (! cgen_signed_overflow_ok_p (cd)) |
252b5132 | 179 | { |
6bb95a0f DB |
180 | long minval = - (1L << (length - 1)); |
181 | long maxval = (1L << (length - 1)) - 1; | |
182 | ||
183 | if (value < minval || value > maxval) | |
184 | { | |
185 | sprintf | |
186 | /* xgettext:c-format */ | |
187 | (errbuf, _("operand out of range (%ld not between %ld and %ld)"), | |
188 | value, minval, maxval); | |
189 | return errbuf; | |
190 | } | |
252b5132 RH |
191 | } |
192 | } | |
193 | ||
194 | #if CGEN_INT_INSN_P | |
195 | ||
196 | { | |
197 | int shift; | |
198 | ||
199 | if (CGEN_INSN_LSB0_P) | |
6bb95a0f | 200 | shift = (word_offset + start + 1) - length; |
252b5132 | 201 | else |
6bb95a0f | 202 | shift = total_length - (word_offset + start + length); |
252b5132 RH |
203 | *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); |
204 | } | |
205 | ||
206 | #else /* ! CGEN_INT_INSN_P */ | |
207 | ||
208 | { | |
209 | unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; | |
210 | ||
211 | insert_1 (cd, value, start, length, word_length, bufp); | |
212 | } | |
213 | ||
214 | #endif /* ! CGEN_INT_INSN_P */ | |
215 | ||
216 | return NULL; | |
217 | } | |
218 | ||
219 | /* Default insn builder (insert handler). | |
fc7bc883 RH |
220 | The instruction is recorded in CGEN_INT_INSN_P byte order (meaning |
221 | that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is | |
222 | recorded in host byte order, otherwise BUFFER is an array of bytes | |
223 | and the value is recorded in target byte order). | |
252b5132 RH |
224 | The result is an error message or NULL if success. */ |
225 | ||
226 | static const char * | |
227 | insert_insn_normal (cd, insn, fields, buffer, pc) | |
228 | CGEN_CPU_DESC cd; | |
229 | const CGEN_INSN * insn; | |
230 | CGEN_FIELDS * fields; | |
231 | CGEN_INSN_BYTES_PTR buffer; | |
232 | bfd_vma pc; | |
233 | { | |
234 | const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); | |
235 | unsigned long value; | |
b3466c39 | 236 | const CGEN_SYNTAX_CHAR_TYPE * syn; |
252b5132 RH |
237 | |
238 | CGEN_INIT_INSERT (cd); | |
239 | value = CGEN_INSN_BASE_VALUE (insn); | |
240 | ||
241 | /* If we're recording insns as numbers (rather than a string of bytes), | |
242 | target byte order handling is deferred until later. */ | |
243 | ||
244 | #if CGEN_INT_INSN_P | |
245 | ||
6bb95a0f DB |
246 | put_insn_int_value (cd, buffer, cd->base_insn_bitsize, |
247 | CGEN_FIELDS_BITSIZE (fields), value); | |
252b5132 RH |
248 | |
249 | #else | |
250 | ||
251 | cgen_put_insn_value (cd, buffer, min (cd->base_insn_bitsize, | |
252 | CGEN_FIELDS_BITSIZE (fields)), | |
253 | value); | |
254 | ||
255 | #endif /* ! CGEN_INT_INSN_P */ | |
256 | ||
257 | /* ??? It would be better to scan the format's fields. | |
258 | Still need to be able to insert a value based on the operand though; | |
259 | e.g. storing a branch displacement that got resolved later. | |
260 | Needs more thought first. */ | |
261 | ||
b3466c39 | 262 | for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) |
252b5132 RH |
263 | { |
264 | const char *errmsg; | |
265 | ||
266 | if (CGEN_SYNTAX_CHAR_P (* syn)) | |
267 | continue; | |
268 | ||
269 | errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), | |
270 | fields, buffer, pc); | |
271 | if (errmsg) | |
272 | return errmsg; | |
273 | } | |
274 | ||
275 | return NULL; | |
276 | } | |
6bb95a0f DB |
277 | |
278 | /* Cover function to store an insn value into an integral insn. Must go here | |
279 | because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ | |
280 | ||
281 | static void | |
282 | put_insn_int_value (cd, buf, length, insn_length, value) | |
fc7bc883 | 283 | CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; |
6bb95a0f DB |
284 | CGEN_INSN_BYTES_PTR buf; |
285 | int length; | |
286 | int insn_length; | |
287 | CGEN_INSN_INT value; | |
288 | { | |
289 | /* For architectures with insns smaller than the base-insn-bitsize, | |
290 | length may be too big. */ | |
291 | if (length > insn_length) | |
292 | *buf = value; | |
293 | else | |
294 | { | |
295 | int shift = insn_length - length; | |
296 | /* Written this way to avoid undefined behaviour. */ | |
297 | CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; | |
298 | *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); | |
299 | } | |
300 | } | |
252b5132 RH |
301 | \f |
302 | /* Operand extraction. */ | |
303 | ||
304 | #if ! CGEN_INT_INSN_P | |
305 | ||
306 | /* Subroutine of extract_normal. | |
307 | Ensure sufficient bytes are cached in EX_INFO. | |
308 | OFFSET is the offset in bytes from the start of the insn of the value. | |
309 | BYTES is the length of the needed value. | |
310 | Returns 1 for success, 0 for failure. */ | |
311 | ||
312 | static CGEN_INLINE int | |
313 | fill_cache (cd, ex_info, offset, bytes, pc) | |
314 | CGEN_CPU_DESC cd; | |
315 | CGEN_EXTRACT_INFO *ex_info; | |
316 | int offset, bytes; | |
317 | bfd_vma pc; | |
318 | { | |
319 | /* It's doubtful that the middle part has already been fetched so | |
320 | we don't optimize that case. kiss. */ | |
321 | int mask; | |
322 | disassemble_info *info = (disassemble_info *) ex_info->dis_info; | |
323 | ||
324 | /* First do a quick check. */ | |
325 | mask = (1 << bytes) - 1; | |
326 | if (((ex_info->valid >> offset) & mask) == mask) | |
327 | return 1; | |
328 | ||
329 | /* Search for the first byte we need to read. */ | |
330 | for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) | |
331 | if (! (mask & ex_info->valid)) | |
332 | break; | |
333 | ||
334 | if (bytes) | |
335 | { | |
336 | int status; | |
337 | ||
338 | pc += offset; | |
339 | status = (*info->read_memory_func) | |
340 | (pc, ex_info->insn_bytes + offset, bytes, info); | |
341 | ||
342 | if (status != 0) | |
343 | { | |
344 | (*info->memory_error_func) (status, pc, info); | |
345 | return 0; | |
346 | } | |
347 | ||
348 | ex_info->valid |= ((1 << bytes) - 1) << offset; | |
349 | } | |
350 | ||
351 | return 1; | |
352 | } | |
353 | ||
354 | /* Subroutine of extract_normal. */ | |
355 | ||
356 | static CGEN_INLINE long | |
357 | extract_1 (cd, ex_info, start, length, word_length, bufp, pc) | |
358 | CGEN_CPU_DESC cd; | |
359 | CGEN_EXTRACT_INFO *ex_info; | |
360 | int start,length,word_length; | |
361 | unsigned char *bufp; | |
362 | bfd_vma pc; | |
363 | { | |
b3466c39 | 364 | unsigned long x; |
252b5132 RH |
365 | int shift; |
366 | int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; | |
367 | ||
b3466c39 | 368 | x = bfd_get_bits (bufp, word_length, big_p); |
252b5132 | 369 | |
252b5132 RH |
370 | if (CGEN_INSN_LSB0_P) |
371 | shift = (start + 1) - length; | |
372 | else | |
373 | shift = (word_length - (start + length)); | |
b3466c39 | 374 | return x >> shift; |
252b5132 RH |
375 | } |
376 | ||
377 | #endif /* ! CGEN_INT_INSN_P */ | |
378 | ||
379 | /* Default extraction routine. | |
380 | ||
381 | INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, | |
382 | or sometimes less for cases like the m32r where the base insn size is 32 | |
383 | but some insns are 16 bits. | |
384 | ATTRS is a mask of the boolean attributes. We only need `SIGNED', | |
385 | but for generality we take a bitmask of all of them. | |
386 | WORD_OFFSET is the offset in bits from the start of the insn of the value. | |
387 | WORD_LENGTH is the length of the word in bits in which the value resides. | |
388 | START is the starting bit number in the word, architecture origin. | |
389 | LENGTH is the length of VALUE in bits. | |
390 | TOTAL_LENGTH is the total length of the insn in bits. | |
391 | ||
392 | Returns 1 for success, 0 for failure. */ | |
393 | ||
394 | /* ??? The return code isn't properly used. wip. */ | |
395 | ||
396 | /* ??? This doesn't handle bfd_vma's. Create another function when | |
397 | necessary. */ | |
398 | ||
399 | static int | |
400 | extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, | |
401 | word_length, total_length, pc, valuep) | |
402 | CGEN_CPU_DESC cd; | |
6bb95a0f | 403 | #if ! CGEN_INT_INSN_P |
252b5132 | 404 | CGEN_EXTRACT_INFO *ex_info; |
6bb95a0f DB |
405 | #else |
406 | CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; | |
407 | #endif | |
252b5132 RH |
408 | CGEN_INSN_INT insn_value; |
409 | unsigned int attrs; | |
410 | unsigned int word_offset, start, length, word_length, total_length; | |
6bb95a0f | 411 | #if ! CGEN_INT_INSN_P |
252b5132 | 412 | bfd_vma pc; |
6bb95a0f DB |
413 | #else |
414 | bfd_vma pc ATTRIBUTE_UNUSED; | |
415 | #endif | |
252b5132 RH |
416 | long *valuep; |
417 | { | |
fc7bc883 | 418 | long value, mask; |
252b5132 RH |
419 | |
420 | /* If LENGTH is zero, this operand doesn't contribute to the value | |
421 | so give it a standard value of zero. */ | |
422 | if (length == 0) | |
423 | { | |
424 | *valuep = 0; | |
425 | return 1; | |
426 | } | |
427 | ||
6bb95a0f | 428 | #if 0 |
252b5132 RH |
429 | if (CGEN_INT_INSN_P |
430 | && word_offset != 0) | |
431 | abort (); | |
6bb95a0f | 432 | #endif |
252b5132 RH |
433 | |
434 | if (word_length > 32) | |
435 | abort (); | |
436 | ||
437 | /* For architectures with insns smaller than the insn-base-bitsize, | |
438 | word_length may be too big. */ | |
439 | if (cd->min_insn_bitsize < cd->base_insn_bitsize) | |
440 | { | |
441 | if (word_offset == 0 | |
442 | && word_length > total_length) | |
443 | word_length = total_length; | |
444 | } | |
445 | ||
fc7bc883 | 446 | /* Does the value reside in INSN_VALUE, and at the right alignment? */ |
252b5132 | 447 | |
fc7bc883 | 448 | if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) |
252b5132 | 449 | { |
252b5132 | 450 | if (CGEN_INSN_LSB0_P) |
6bb95a0f | 451 | value = insn_value >> ((word_offset + start + 1) - length); |
252b5132 | 452 | else |
6bb95a0f | 453 | value = insn_value >> (total_length - ( word_offset + start + length)); |
252b5132 RH |
454 | } |
455 | ||
456 | #if ! CGEN_INT_INSN_P | |
457 | ||
458 | else | |
459 | { | |
460 | unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; | |
461 | ||
462 | if (word_length > 32) | |
463 | abort (); | |
464 | ||
465 | if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) | |
466 | return 0; | |
467 | ||
468 | value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); | |
469 | } | |
470 | ||
471 | #endif /* ! CGEN_INT_INSN_P */ | |
472 | ||
b3466c39 DB |
473 | /* Written this way to avoid undefined behaviour. */ |
474 | mask = (((1L << (length - 1)) - 1) << 1) | 1; | |
475 | ||
476 | value &= mask; | |
477 | /* sign extend? */ | |
478 | if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) | |
479 | && (value & (1L << (length - 1)))) | |
480 | value |= ~mask; | |
481 | ||
252b5132 RH |
482 | *valuep = value; |
483 | ||
484 | return 1; | |
485 | } | |
486 | ||
487 | /* Default insn extractor. | |
488 | ||
489 | INSN_VALUE is the first base_insn_bitsize bits, translated to host order. | |
490 | The extracted fields are stored in FIELDS. | |
491 | EX_INFO is used to handle reading variable length insns. | |
492 | Return the length of the insn in bits, or 0 if no match, | |
493 | or -1 if an error occurs fetching data (memory_error_func will have | |
494 | been called). */ | |
495 | ||
496 | static int | |
497 | extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc) | |
498 | CGEN_CPU_DESC cd; | |
499 | const CGEN_INSN *insn; | |
500 | CGEN_EXTRACT_INFO *ex_info; | |
501 | CGEN_INSN_INT insn_value; | |
502 | CGEN_FIELDS *fields; | |
503 | bfd_vma pc; | |
504 | { | |
505 | const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); | |
b3466c39 | 506 | const CGEN_SYNTAX_CHAR_TYPE *syn; |
252b5132 RH |
507 | |
508 | CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); | |
509 | ||
510 | CGEN_INIT_EXTRACT (cd); | |
511 | ||
512 | for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) | |
513 | { | |
514 | int length; | |
515 | ||
516 | if (CGEN_SYNTAX_CHAR_P (*syn)) | |
517 | continue; | |
518 | ||
519 | length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), | |
520 | ex_info, insn_value, fields, pc); | |
521 | if (length <= 0) | |
522 | return length; | |
523 | } | |
524 | ||
525 | /* We recognized and successfully extracted this insn. */ | |
526 | return CGEN_INSN_BITSIZE (insn); | |
527 | } | |
528 | \f | |
529 | /* machine generated code added here */ | |
530 | ||
531 | /* Main entry point for operand insertion. | |
532 | ||
533 | This function is basically just a big switch statement. Earlier versions | |
534 | used tables to look up the function to use, but | |
535 | - if the table contains both assembler and disassembler functions then | |
536 | the disassembler contains much of the assembler and vice-versa, | |
537 | - there's a lot of inlining possibilities as things grow, | |
538 | - using a switch statement avoids the function call overhead. | |
539 | ||
540 | This function could be moved into `parse_insn_normal', but keeping it | |
541 | separate makes clear the interface between `parse_insn_normal' and each of | |
542 | the handlers. It's also needed by GAS to insert operands that couldn't be | |
543 | resolved during parsing. | |
544 | */ | |
545 | ||
546 | const char * | |
547 | fr30_cgen_insert_operand (cd, opindex, fields, buffer, pc) | |
548 | CGEN_CPU_DESC cd; | |
549 | int opindex; | |
550 | CGEN_FIELDS * fields; | |
551 | CGEN_INSN_BYTES_PTR buffer; | |
552 | bfd_vma pc; | |
553 | { | |
eb1b03df | 554 | const char * errmsg = NULL; |
252b5132 RH |
555 | unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); |
556 | ||
557 | switch (opindex) | |
558 | { | |
559 | case FR30_OPERAND_CRI : | |
560 | errmsg = insert_normal (cd, fields->f_CRi, 0, 16, 12, 4, 16, total_length, buffer); | |
561 | break; | |
562 | case FR30_OPERAND_CRJ : | |
563 | errmsg = insert_normal (cd, fields->f_CRj, 0, 16, 8, 4, 16, total_length, buffer); | |
564 | break; | |
565 | case FR30_OPERAND_R13 : | |
252b5132 RH |
566 | break; |
567 | case FR30_OPERAND_R14 : | |
252b5132 RH |
568 | break; |
569 | case FR30_OPERAND_R15 : | |
252b5132 RH |
570 | break; |
571 | case FR30_OPERAND_RI : | |
572 | errmsg = insert_normal (cd, fields->f_Ri, 0, 0, 12, 4, 16, total_length, buffer); | |
573 | break; | |
574 | case FR30_OPERAND_RIC : | |
575 | errmsg = insert_normal (cd, fields->f_Ric, 0, 16, 12, 4, 16, total_length, buffer); | |
576 | break; | |
577 | case FR30_OPERAND_RJ : | |
578 | errmsg = insert_normal (cd, fields->f_Rj, 0, 0, 8, 4, 16, total_length, buffer); | |
579 | break; | |
580 | case FR30_OPERAND_RJC : | |
581 | errmsg = insert_normal (cd, fields->f_Rjc, 0, 16, 8, 4, 16, total_length, buffer); | |
582 | break; | |
583 | case FR30_OPERAND_RS1 : | |
584 | errmsg = insert_normal (cd, fields->f_Rs1, 0, 0, 8, 4, 16, total_length, buffer); | |
585 | break; | |
586 | case FR30_OPERAND_RS2 : | |
587 | errmsg = insert_normal (cd, fields->f_Rs2, 0, 0, 12, 4, 16, total_length, buffer); | |
588 | break; | |
589 | case FR30_OPERAND_CC : | |
590 | errmsg = insert_normal (cd, fields->f_cc, 0, 0, 4, 4, 16, total_length, buffer); | |
591 | break; | |
592 | case FR30_OPERAND_CCC : | |
593 | errmsg = insert_normal (cd, fields->f_ccc, 0, 16, 0, 8, 16, total_length, buffer); | |
594 | break; | |
595 | case FR30_OPERAND_DIR10 : | |
596 | { | |
597 | long value = fields->f_dir10; | |
598 | value = ((unsigned int) (value) >> (2)); | |
599 | errmsg = insert_normal (cd, value, 0, 0, 8, 8, 16, total_length, buffer); | |
600 | } | |
601 | break; | |
602 | case FR30_OPERAND_DIR8 : | |
603 | errmsg = insert_normal (cd, fields->f_dir8, 0, 0, 8, 8, 16, total_length, buffer); | |
604 | break; | |
605 | case FR30_OPERAND_DIR9 : | |
606 | { | |
607 | long value = fields->f_dir9; | |
608 | value = ((unsigned int) (value) >> (1)); | |
609 | errmsg = insert_normal (cd, value, 0, 0, 8, 8, 16, total_length, buffer); | |
610 | } | |
611 | break; | |
612 | case FR30_OPERAND_DISP10 : | |
613 | { | |
614 | long value = fields->f_disp10; | |
615 | value = ((int) (value) >> (2)); | |
616 | errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, buffer); | |
617 | } | |
618 | break; | |
619 | case FR30_OPERAND_DISP8 : | |
620 | errmsg = insert_normal (cd, fields->f_disp8, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, buffer); | |
621 | break; | |
622 | case FR30_OPERAND_DISP9 : | |
623 | { | |
624 | long value = fields->f_disp9; | |
625 | value = ((int) (value) >> (1)); | |
626 | errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, buffer); | |
627 | } | |
628 | break; | |
629 | case FR30_OPERAND_I20 : | |
630 | { | |
631 | { | |
632 | FLD (f_i20_4) = ((unsigned int) (FLD (f_i20)) >> (16)); | |
633 | FLD (f_i20_16) = ((FLD (f_i20)) & (65535)); | |
634 | } | |
635 | errmsg = insert_normal (cd, fields->f_i20_4, 0, 0, 8, 4, 16, total_length, buffer); | |
636 | if (errmsg) | |
637 | break; | |
638 | errmsg = insert_normal (cd, fields->f_i20_16, 0, 16, 0, 16, 16, total_length, buffer); | |
639 | if (errmsg) | |
640 | break; | |
641 | } | |
642 | break; | |
643 | case FR30_OPERAND_I32 : | |
644 | errmsg = insert_normal (cd, fields->f_i32, 0|(1<<CGEN_IFLD_SIGN_OPT), 16, 0, 32, 32, total_length, buffer); | |
645 | break; | |
646 | case FR30_OPERAND_I8 : | |
647 | errmsg = insert_normal (cd, fields->f_i8, 0, 0, 4, 8, 16, total_length, buffer); | |
648 | break; | |
649 | case FR30_OPERAND_LABEL12 : | |
650 | { | |
651 | long value = fields->f_rel12; | |
652 | value = ((int) (((value) - (((pc) + (2))))) >> (1)); | |
653 | errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 5, 11, 16, total_length, buffer); | |
654 | } | |
655 | break; | |
656 | case FR30_OPERAND_LABEL9 : | |
657 | { | |
658 | long value = fields->f_rel9; | |
659 | value = ((int) (((value) - (((pc) + (2))))) >> (1)); | |
660 | errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 16, total_length, buffer); | |
661 | } | |
662 | break; | |
663 | case FR30_OPERAND_M4 : | |
664 | { | |
665 | long value = fields->f_m4; | |
666 | value = ((value) & (15)); | |
667 | errmsg = insert_normal (cd, value, 0, 0, 8, 4, 16, total_length, buffer); | |
668 | } | |
669 | break; | |
670 | case FR30_OPERAND_PS : | |
252b5132 RH |
671 | break; |
672 | case FR30_OPERAND_REGLIST_HI_LD : | |
673 | errmsg = insert_normal (cd, fields->f_reglist_hi_ld, 0, 0, 8, 8, 16, total_length, buffer); | |
674 | break; | |
675 | case FR30_OPERAND_REGLIST_HI_ST : | |
676 | errmsg = insert_normal (cd, fields->f_reglist_hi_st, 0, 0, 8, 8, 16, total_length, buffer); | |
677 | break; | |
678 | case FR30_OPERAND_REGLIST_LOW_LD : | |
679 | errmsg = insert_normal (cd, fields->f_reglist_low_ld, 0, 0, 8, 8, 16, total_length, buffer); | |
680 | break; | |
681 | case FR30_OPERAND_REGLIST_LOW_ST : | |
682 | errmsg = insert_normal (cd, fields->f_reglist_low_st, 0, 0, 8, 8, 16, total_length, buffer); | |
683 | break; | |
684 | case FR30_OPERAND_S10 : | |
685 | { | |
686 | long value = fields->f_s10; | |
687 | value = ((int) (value) >> (2)); | |
688 | errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 16, total_length, buffer); | |
689 | } | |
690 | break; | |
691 | case FR30_OPERAND_U10 : | |
692 | { | |
693 | long value = fields->f_u10; | |
694 | value = ((unsigned int) (value) >> (2)); | |
695 | errmsg = insert_normal (cd, value, 0, 0, 8, 8, 16, total_length, buffer); | |
696 | } | |
697 | break; | |
698 | case FR30_OPERAND_U4 : | |
699 | errmsg = insert_normal (cd, fields->f_u4, 0, 0, 8, 4, 16, total_length, buffer); | |
700 | break; | |
701 | case FR30_OPERAND_U4C : | |
702 | errmsg = insert_normal (cd, fields->f_u4c, 0, 0, 12, 4, 16, total_length, buffer); | |
703 | break; | |
704 | case FR30_OPERAND_U8 : | |
705 | errmsg = insert_normal (cd, fields->f_u8, 0, 0, 8, 8, 16, total_length, buffer); | |
706 | break; | |
707 | case FR30_OPERAND_UDISP6 : | |
708 | { | |
709 | long value = fields->f_udisp6; | |
710 | value = ((unsigned int) (value) >> (2)); | |
711 | errmsg = insert_normal (cd, value, 0, 0, 8, 4, 16, total_length, buffer); | |
712 | } | |
713 | break; | |
714 | ||
715 | default : | |
716 | /* xgettext:c-format */ | |
717 | fprintf (stderr, _("Unrecognized field %d while building insn.\n"), | |
718 | opindex); | |
719 | abort (); | |
720 | } | |
721 | ||
722 | return errmsg; | |
723 | } | |
724 | ||
725 | /* Main entry point for operand extraction. | |
eb1b03df DE |
726 | The result is <= 0 for error, >0 for success. |
727 | ??? Actual values aren't well defined right now. | |
252b5132 RH |
728 | |
729 | This function is basically just a big switch statement. Earlier versions | |
730 | used tables to look up the function to use, but | |
731 | - if the table contains both assembler and disassembler functions then | |
732 | the disassembler contains much of the assembler and vice-versa, | |
733 | - there's a lot of inlining possibilities as things grow, | |
734 | - using a switch statement avoids the function call overhead. | |
735 | ||
736 | This function could be moved into `print_insn_normal', but keeping it | |
737 | separate makes clear the interface between `print_insn_normal' and each of | |
738 | the handlers. | |
739 | */ | |
740 | ||
741 | int | |
742 | fr30_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) | |
743 | CGEN_CPU_DESC cd; | |
744 | int opindex; | |
745 | CGEN_EXTRACT_INFO *ex_info; | |
746 | CGEN_INSN_INT insn_value; | |
747 | CGEN_FIELDS * fields; | |
748 | bfd_vma pc; | |
749 | { | |
eb1b03df DE |
750 | /* Assume success (for those operands that are nops). */ |
751 | int length = 1; | |
252b5132 RH |
752 | unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); |
753 | ||
754 | switch (opindex) | |
755 | { | |
756 | case FR30_OPERAND_CRI : | |
757 | length = extract_normal (cd, ex_info, insn_value, 0, 16, 12, 4, 16, total_length, pc, & fields->f_CRi); | |
758 | break; | |
759 | case FR30_OPERAND_CRJ : | |
760 | length = extract_normal (cd, ex_info, insn_value, 0, 16, 8, 4, 16, total_length, pc, & fields->f_CRj); | |
761 | break; | |
762 | case FR30_OPERAND_R13 : | |
252b5132 RH |
763 | break; |
764 | case FR30_OPERAND_R14 : | |
252b5132 RH |
765 | break; |
766 | case FR30_OPERAND_R15 : | |
252b5132 RH |
767 | break; |
768 | case FR30_OPERAND_RI : | |
769 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 16, total_length, pc, & fields->f_Ri); | |
770 | break; | |
771 | case FR30_OPERAND_RIC : | |
772 | length = extract_normal (cd, ex_info, insn_value, 0, 16, 12, 4, 16, total_length, pc, & fields->f_Ric); | |
773 | break; | |
774 | case FR30_OPERAND_RJ : | |
775 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & fields->f_Rj); | |
776 | break; | |
777 | case FR30_OPERAND_RJC : | |
778 | length = extract_normal (cd, ex_info, insn_value, 0, 16, 8, 4, 16, total_length, pc, & fields->f_Rjc); | |
779 | break; | |
780 | case FR30_OPERAND_RS1 : | |
781 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & fields->f_Rs1); | |
782 | break; | |
783 | case FR30_OPERAND_RS2 : | |
784 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 16, total_length, pc, & fields->f_Rs2); | |
785 | break; | |
786 | case FR30_OPERAND_CC : | |
787 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 16, total_length, pc, & fields->f_cc); | |
788 | break; | |
789 | case FR30_OPERAND_CCC : | |
790 | length = extract_normal (cd, ex_info, insn_value, 0, 16, 0, 8, 16, total_length, pc, & fields->f_ccc); | |
791 | break; | |
792 | case FR30_OPERAND_DIR10 : | |
793 | { | |
794 | long value; | |
795 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & value); | |
796 | value = ((value) << (2)); | |
797 | fields->f_dir10 = value; | |
798 | } | |
799 | break; | |
800 | case FR30_OPERAND_DIR8 : | |
801 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_dir8); | |
802 | break; | |
803 | case FR30_OPERAND_DIR9 : | |
804 | { | |
805 | long value; | |
806 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & value); | |
807 | value = ((value) << (1)); | |
808 | fields->f_dir9 = value; | |
809 | } | |
810 | break; | |
811 | case FR30_OPERAND_DISP10 : | |
812 | { | |
813 | long value; | |
814 | length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, pc, & value); | |
815 | value = ((value) << (2)); | |
816 | fields->f_disp10 = value; | |
817 | } | |
818 | break; | |
819 | case FR30_OPERAND_DISP8 : | |
820 | length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, pc, & fields->f_disp8); | |
821 | break; | |
822 | case FR30_OPERAND_DISP9 : | |
823 | { | |
824 | long value; | |
825 | length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, pc, & value); | |
826 | value = ((value) << (1)); | |
827 | fields->f_disp9 = value; | |
828 | } | |
829 | break; | |
830 | case FR30_OPERAND_I20 : | |
831 | { | |
832 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & fields->f_i20_4); | |
6bb95a0f | 833 | if (length <= 0) break; |
252b5132 | 834 | length = extract_normal (cd, ex_info, insn_value, 0, 16, 0, 16, 16, total_length, pc, & fields->f_i20_16); |
6bb95a0f | 835 | if (length <= 0) break; |
252b5132 RH |
836 | { |
837 | FLD (f_i20) = ((((FLD (f_i20_4)) << (16))) | (FLD (f_i20_16))); | |
838 | } | |
839 | } | |
840 | break; | |
841 | case FR30_OPERAND_I32 : | |
842 | length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGN_OPT), 16, 0, 32, 32, total_length, pc, & fields->f_i32); | |
843 | break; | |
844 | case FR30_OPERAND_I8 : | |
845 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 8, 16, total_length, pc, & fields->f_i8); | |
846 | break; | |
847 | case FR30_OPERAND_LABEL12 : | |
848 | { | |
849 | long value; | |
850 | length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 5, 11, 16, total_length, pc, & value); | |
851 | value = ((((value) << (1))) + (((pc) + (2)))); | |
852 | fields->f_rel12 = value; | |
853 | } | |
854 | break; | |
855 | case FR30_OPERAND_LABEL9 : | |
856 | { | |
857 | long value; | |
858 | length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 16, total_length, pc, & value); | |
859 | value = ((((value) << (1))) + (((pc) + (2)))); | |
860 | fields->f_rel9 = value; | |
861 | } | |
862 | break; | |
863 | case FR30_OPERAND_M4 : | |
864 | { | |
865 | long value; | |
866 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & value); | |
867 | value = ((value) | (((-1) << (4)))); | |
868 | fields->f_m4 = value; | |
869 | } | |
870 | break; | |
871 | case FR30_OPERAND_PS : | |
252b5132 RH |
872 | break; |
873 | case FR30_OPERAND_REGLIST_HI_LD : | |
874 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_reglist_hi_ld); | |
875 | break; | |
876 | case FR30_OPERAND_REGLIST_HI_ST : | |
877 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_reglist_hi_st); | |
878 | break; | |
879 | case FR30_OPERAND_REGLIST_LOW_LD : | |
880 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_reglist_low_ld); | |
881 | break; | |
882 | case FR30_OPERAND_REGLIST_LOW_ST : | |
883 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_reglist_low_st); | |
884 | break; | |
885 | case FR30_OPERAND_S10 : | |
886 | { | |
887 | long value; | |
888 | length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 16, total_length, pc, & value); | |
889 | value = ((value) << (2)); | |
890 | fields->f_s10 = value; | |
891 | } | |
892 | break; | |
893 | case FR30_OPERAND_U10 : | |
894 | { | |
895 | long value; | |
896 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & value); | |
897 | value = ((value) << (2)); | |
898 | fields->f_u10 = value; | |
899 | } | |
900 | break; | |
901 | case FR30_OPERAND_U4 : | |
902 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & fields->f_u4); | |
903 | break; | |
904 | case FR30_OPERAND_U4C : | |
905 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 16, total_length, pc, & fields->f_u4c); | |
906 | break; | |
907 | case FR30_OPERAND_U8 : | |
908 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_u8); | |
909 | break; | |
910 | case FR30_OPERAND_UDISP6 : | |
911 | { | |
912 | long value; | |
913 | length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & value); | |
914 | value = ((value) << (2)); | |
915 | fields->f_udisp6 = value; | |
916 | } | |
917 | break; | |
918 | ||
919 | default : | |
920 | /* xgettext:c-format */ | |
921 | fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), | |
922 | opindex); | |
923 | abort (); | |
924 | } | |
925 | ||
926 | return length; | |
927 | } | |
928 | ||
929 | cgen_insert_fn * const fr30_cgen_insert_handlers[] = | |
930 | { | |
931 | insert_insn_normal, | |
932 | }; | |
933 | ||
934 | cgen_extract_fn * const fr30_cgen_extract_handlers[] = | |
935 | { | |
936 | extract_insn_normal, | |
937 | }; | |
938 | ||
939 | /* Getting values from cgen_fields is handled by a collection of functions. | |
940 | They are distinguished by the type of the VALUE argument they return. | |
941 | TODO: floating point, inlining support, remove cases where result type | |
942 | not appropriate. */ | |
943 | ||
944 | int | |
945 | fr30_cgen_get_int_operand (cd, opindex, fields) | |
946 | CGEN_CPU_DESC cd; | |
947 | int opindex; | |
948 | const CGEN_FIELDS * fields; | |
949 | { | |
950 | int value; | |
951 | ||
952 | switch (opindex) | |
953 | { | |
954 | case FR30_OPERAND_CRI : | |
955 | value = fields->f_CRi; | |
956 | break; | |
957 | case FR30_OPERAND_CRJ : | |
958 | value = fields->f_CRj; | |
959 | break; | |
960 | case FR30_OPERAND_R13 : | |
eb1b03df | 961 | value = 0; |
252b5132 RH |
962 | break; |
963 | case FR30_OPERAND_R14 : | |
eb1b03df | 964 | value = 0; |
252b5132 RH |
965 | break; |
966 | case FR30_OPERAND_R15 : | |
eb1b03df | 967 | value = 0; |
252b5132 RH |
968 | break; |
969 | case FR30_OPERAND_RI : | |
970 | value = fields->f_Ri; | |
971 | break; | |
972 | case FR30_OPERAND_RIC : | |
973 | value = fields->f_Ric; | |
974 | break; | |
975 | case FR30_OPERAND_RJ : | |
976 | value = fields->f_Rj; | |
977 | break; | |
978 | case FR30_OPERAND_RJC : | |
979 | value = fields->f_Rjc; | |
980 | break; | |
981 | case FR30_OPERAND_RS1 : | |
982 | value = fields->f_Rs1; | |
983 | break; | |
984 | case FR30_OPERAND_RS2 : | |
985 | value = fields->f_Rs2; | |
986 | break; | |
987 | case FR30_OPERAND_CC : | |
988 | value = fields->f_cc; | |
989 | break; | |
990 | case FR30_OPERAND_CCC : | |
991 | value = fields->f_ccc; | |
992 | break; | |
993 | case FR30_OPERAND_DIR10 : | |
994 | value = fields->f_dir10; | |
995 | break; | |
996 | case FR30_OPERAND_DIR8 : | |
997 | value = fields->f_dir8; | |
998 | break; | |
999 | case FR30_OPERAND_DIR9 : | |
1000 | value = fields->f_dir9; | |
1001 | break; | |
1002 | case FR30_OPERAND_DISP10 : | |
1003 | value = fields->f_disp10; | |
1004 | break; | |
1005 | case FR30_OPERAND_DISP8 : | |
1006 | value = fields->f_disp8; | |
1007 | break; | |
1008 | case FR30_OPERAND_DISP9 : | |
1009 | value = fields->f_disp9; | |
1010 | break; | |
1011 | case FR30_OPERAND_I20 : | |
1012 | value = fields->f_i20; | |
1013 | break; | |
1014 | case FR30_OPERAND_I32 : | |
1015 | value = fields->f_i32; | |
1016 | break; | |
1017 | case FR30_OPERAND_I8 : | |
1018 | value = fields->f_i8; | |
1019 | break; | |
1020 | case FR30_OPERAND_LABEL12 : | |
1021 | value = fields->f_rel12; | |
1022 | break; | |
1023 | case FR30_OPERAND_LABEL9 : | |
1024 | value = fields->f_rel9; | |
1025 | break; | |
1026 | case FR30_OPERAND_M4 : | |
1027 | value = fields->f_m4; | |
1028 | break; | |
1029 | case FR30_OPERAND_PS : | |
eb1b03df | 1030 | value = 0; |
252b5132 RH |
1031 | break; |
1032 | case FR30_OPERAND_REGLIST_HI_LD : | |
1033 | value = fields->f_reglist_hi_ld; | |
1034 | break; | |
1035 | case FR30_OPERAND_REGLIST_HI_ST : | |
1036 | value = fields->f_reglist_hi_st; | |
1037 | break; | |
1038 | case FR30_OPERAND_REGLIST_LOW_LD : | |
1039 | value = fields->f_reglist_low_ld; | |
1040 | break; | |
1041 | case FR30_OPERAND_REGLIST_LOW_ST : | |
1042 | value = fields->f_reglist_low_st; | |
1043 | break; | |
1044 | case FR30_OPERAND_S10 : | |
1045 | value = fields->f_s10; | |
1046 | break; | |
1047 | case FR30_OPERAND_U10 : | |
1048 | value = fields->f_u10; | |
1049 | break; | |
1050 | case FR30_OPERAND_U4 : | |
1051 | value = fields->f_u4; | |
1052 | break; | |
1053 | case FR30_OPERAND_U4C : | |
1054 | value = fields->f_u4c; | |
1055 | break; | |
1056 | case FR30_OPERAND_U8 : | |
1057 | value = fields->f_u8; | |
1058 | break; | |
1059 | case FR30_OPERAND_UDISP6 : | |
1060 | value = fields->f_udisp6; | |
1061 | break; | |
1062 | ||
1063 | default : | |
1064 | /* xgettext:c-format */ | |
1065 | fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), | |
1066 | opindex); | |
1067 | abort (); | |
1068 | } | |
1069 | ||
1070 | return value; | |
1071 | } | |
1072 | ||
1073 | bfd_vma | |
1074 | fr30_cgen_get_vma_operand (cd, opindex, fields) | |
1075 | CGEN_CPU_DESC cd; | |
1076 | int opindex; | |
1077 | const CGEN_FIELDS * fields; | |
1078 | { | |
1079 | bfd_vma value; | |
1080 | ||
1081 | switch (opindex) | |
1082 | { | |
1083 | case FR30_OPERAND_CRI : | |
1084 | value = fields->f_CRi; | |
1085 | break; | |
1086 | case FR30_OPERAND_CRJ : | |
1087 | value = fields->f_CRj; | |
1088 | break; | |
1089 | case FR30_OPERAND_R13 : | |
eb1b03df | 1090 | value = 0; |
252b5132 RH |
1091 | break; |
1092 | case FR30_OPERAND_R14 : | |
eb1b03df | 1093 | value = 0; |
252b5132 RH |
1094 | break; |
1095 | case FR30_OPERAND_R15 : | |
eb1b03df | 1096 | value = 0; |
252b5132 RH |
1097 | break; |
1098 | case FR30_OPERAND_RI : | |
1099 | value = fields->f_Ri; | |
1100 | break; | |
1101 | case FR30_OPERAND_RIC : | |
1102 | value = fields->f_Ric; | |
1103 | break; | |
1104 | case FR30_OPERAND_RJ : | |
1105 | value = fields->f_Rj; | |
1106 | break; | |
1107 | case FR30_OPERAND_RJC : | |
1108 | value = fields->f_Rjc; | |
1109 | break; | |
1110 | case FR30_OPERAND_RS1 : | |
1111 | value = fields->f_Rs1; | |
1112 | break; | |
1113 | case FR30_OPERAND_RS2 : | |
1114 | value = fields->f_Rs2; | |
1115 | break; | |
1116 | case FR30_OPERAND_CC : | |
1117 | value = fields->f_cc; | |
1118 | break; | |
1119 | case FR30_OPERAND_CCC : | |
1120 | value = fields->f_ccc; | |
1121 | break; | |
1122 | case FR30_OPERAND_DIR10 : | |
1123 | value = fields->f_dir10; | |
1124 | break; | |
1125 | case FR30_OPERAND_DIR8 : | |
1126 | value = fields->f_dir8; | |
1127 | break; | |
1128 | case FR30_OPERAND_DIR9 : | |
1129 | value = fields->f_dir9; | |
1130 | break; | |
1131 | case FR30_OPERAND_DISP10 : | |
1132 | value = fields->f_disp10; | |
1133 | break; | |
1134 | case FR30_OPERAND_DISP8 : | |
1135 | value = fields->f_disp8; | |
1136 | break; | |
1137 | case FR30_OPERAND_DISP9 : | |
1138 | value = fields->f_disp9; | |
1139 | break; | |
1140 | case FR30_OPERAND_I20 : | |
1141 | value = fields->f_i20; | |
1142 | break; | |
1143 | case FR30_OPERAND_I32 : | |
1144 | value = fields->f_i32; | |
1145 | break; | |
1146 | case FR30_OPERAND_I8 : | |
1147 | value = fields->f_i8; | |
1148 | break; | |
1149 | case FR30_OPERAND_LABEL12 : | |
1150 | value = fields->f_rel12; | |
1151 | break; | |
1152 | case FR30_OPERAND_LABEL9 : | |
1153 | value = fields->f_rel9; | |
1154 | break; | |
1155 | case FR30_OPERAND_M4 : | |
1156 | value = fields->f_m4; | |
1157 | break; | |
1158 | case FR30_OPERAND_PS : | |
eb1b03df | 1159 | value = 0; |
252b5132 RH |
1160 | break; |
1161 | case FR30_OPERAND_REGLIST_HI_LD : | |
1162 | value = fields->f_reglist_hi_ld; | |
1163 | break; | |
1164 | case FR30_OPERAND_REGLIST_HI_ST : | |
1165 | value = fields->f_reglist_hi_st; | |
1166 | break; | |
1167 | case FR30_OPERAND_REGLIST_LOW_LD : | |
1168 | value = fields->f_reglist_low_ld; | |
1169 | break; | |
1170 | case FR30_OPERAND_REGLIST_LOW_ST : | |
1171 | value = fields->f_reglist_low_st; | |
1172 | break; | |
1173 | case FR30_OPERAND_S10 : | |
1174 | value = fields->f_s10; | |
1175 | break; | |
1176 | case FR30_OPERAND_U10 : | |
1177 | value = fields->f_u10; | |
1178 | break; | |
1179 | case FR30_OPERAND_U4 : | |
1180 | value = fields->f_u4; | |
1181 | break; | |
1182 | case FR30_OPERAND_U4C : | |
1183 | value = fields->f_u4c; | |
1184 | break; | |
1185 | case FR30_OPERAND_U8 : | |
1186 | value = fields->f_u8; | |
1187 | break; | |
1188 | case FR30_OPERAND_UDISP6 : | |
1189 | value = fields->f_udisp6; | |
1190 | break; | |
1191 | ||
1192 | default : | |
1193 | /* xgettext:c-format */ | |
1194 | fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), | |
1195 | opindex); | |
1196 | abort (); | |
1197 | } | |
1198 | ||
1199 | return value; | |
1200 | } | |
1201 | ||
1202 | /* Stuffing values in cgen_fields is handled by a collection of functions. | |
1203 | They are distinguished by the type of the VALUE argument they accept. | |
1204 | TODO: floating point, inlining support, remove cases where argument type | |
1205 | not appropriate. */ | |
1206 | ||
1207 | void | |
1208 | fr30_cgen_set_int_operand (cd, opindex, fields, value) | |
1209 | CGEN_CPU_DESC cd; | |
1210 | int opindex; | |
1211 | CGEN_FIELDS * fields; | |
1212 | int value; | |
1213 | { | |
1214 | switch (opindex) | |
1215 | { | |
1216 | case FR30_OPERAND_CRI : | |
1217 | fields->f_CRi = value; | |
1218 | break; | |
1219 | case FR30_OPERAND_CRJ : | |
1220 | fields->f_CRj = value; | |
1221 | break; | |
1222 | case FR30_OPERAND_R13 : | |
252b5132 RH |
1223 | break; |
1224 | case FR30_OPERAND_R14 : | |
252b5132 RH |
1225 | break; |
1226 | case FR30_OPERAND_R15 : | |
252b5132 RH |
1227 | break; |
1228 | case FR30_OPERAND_RI : | |
1229 | fields->f_Ri = value; | |
1230 | break; | |
1231 | case FR30_OPERAND_RIC : | |
1232 | fields->f_Ric = value; | |
1233 | break; | |
1234 | case FR30_OPERAND_RJ : | |
1235 | fields->f_Rj = value; | |
1236 | break; | |
1237 | case FR30_OPERAND_RJC : | |
1238 | fields->f_Rjc = value; | |
1239 | break; | |
1240 | case FR30_OPERAND_RS1 : | |
1241 | fields->f_Rs1 = value; | |
1242 | break; | |
1243 | case FR30_OPERAND_RS2 : | |
1244 | fields->f_Rs2 = value; | |
1245 | break; | |
1246 | case FR30_OPERAND_CC : | |
1247 | fields->f_cc = value; | |
1248 | break; | |
1249 | case FR30_OPERAND_CCC : | |
1250 | fields->f_ccc = value; | |
1251 | break; | |
1252 | case FR30_OPERAND_DIR10 : | |
1253 | fields->f_dir10 = value; | |
1254 | break; | |
1255 | case FR30_OPERAND_DIR8 : | |
1256 | fields->f_dir8 = value; | |
1257 | break; | |
1258 | case FR30_OPERAND_DIR9 : | |
1259 | fields->f_dir9 = value; | |
1260 | break; | |
1261 | case FR30_OPERAND_DISP10 : | |
1262 | fields->f_disp10 = value; | |
1263 | break; | |
1264 | case FR30_OPERAND_DISP8 : | |
1265 | fields->f_disp8 = value; | |
1266 | break; | |
1267 | case FR30_OPERAND_DISP9 : | |
1268 | fields->f_disp9 = value; | |
1269 | break; | |
1270 | case FR30_OPERAND_I20 : | |
1271 | fields->f_i20 = value; | |
1272 | break; | |
1273 | case FR30_OPERAND_I32 : | |
1274 | fields->f_i32 = value; | |
1275 | break; | |
1276 | case FR30_OPERAND_I8 : | |
1277 | fields->f_i8 = value; | |
1278 | break; | |
1279 | case FR30_OPERAND_LABEL12 : | |
1280 | fields->f_rel12 = value; | |
1281 | break; | |
1282 | case FR30_OPERAND_LABEL9 : | |
1283 | fields->f_rel9 = value; | |
1284 | break; | |
1285 | case FR30_OPERAND_M4 : | |
1286 | fields->f_m4 = value; | |
1287 | break; | |
1288 | case FR30_OPERAND_PS : | |
252b5132 RH |
1289 | break; |
1290 | case FR30_OPERAND_REGLIST_HI_LD : | |
1291 | fields->f_reglist_hi_ld = value; | |
1292 | break; | |
1293 | case FR30_OPERAND_REGLIST_HI_ST : | |
1294 | fields->f_reglist_hi_st = value; | |
1295 | break; | |
1296 | case FR30_OPERAND_REGLIST_LOW_LD : | |
1297 | fields->f_reglist_low_ld = value; | |
1298 | break; | |
1299 | case FR30_OPERAND_REGLIST_LOW_ST : | |
1300 | fields->f_reglist_low_st = value; | |
1301 | break; | |
1302 | case FR30_OPERAND_S10 : | |
1303 | fields->f_s10 = value; | |
1304 | break; | |
1305 | case FR30_OPERAND_U10 : | |
1306 | fields->f_u10 = value; | |
1307 | break; | |
1308 | case FR30_OPERAND_U4 : | |
1309 | fields->f_u4 = value; | |
1310 | break; | |
1311 | case FR30_OPERAND_U4C : | |
1312 | fields->f_u4c = value; | |
1313 | break; | |
1314 | case FR30_OPERAND_U8 : | |
1315 | fields->f_u8 = value; | |
1316 | break; | |
1317 | case FR30_OPERAND_UDISP6 : | |
1318 | fields->f_udisp6 = value; | |
1319 | break; | |
1320 | ||
1321 | default : | |
1322 | /* xgettext:c-format */ | |
1323 | fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), | |
1324 | opindex); | |
1325 | abort (); | |
1326 | } | |
1327 | } | |
1328 | ||
1329 | void | |
1330 | fr30_cgen_set_vma_operand (cd, opindex, fields, value) | |
1331 | CGEN_CPU_DESC cd; | |
1332 | int opindex; | |
1333 | CGEN_FIELDS * fields; | |
1334 | bfd_vma value; | |
1335 | { | |
1336 | switch (opindex) | |
1337 | { | |
1338 | case FR30_OPERAND_CRI : | |
1339 | fields->f_CRi = value; | |
1340 | break; | |
1341 | case FR30_OPERAND_CRJ : | |
1342 | fields->f_CRj = value; | |
1343 | break; | |
1344 | case FR30_OPERAND_R13 : | |
252b5132 RH |
1345 | break; |
1346 | case FR30_OPERAND_R14 : | |
252b5132 RH |
1347 | break; |
1348 | case FR30_OPERAND_R15 : | |
252b5132 RH |
1349 | break; |
1350 | case FR30_OPERAND_RI : | |
1351 | fields->f_Ri = value; | |
1352 | break; | |
1353 | case FR30_OPERAND_RIC : | |
1354 | fields->f_Ric = value; | |
1355 | break; | |
1356 | case FR30_OPERAND_RJ : | |
1357 | fields->f_Rj = value; | |
1358 | break; | |
1359 | case FR30_OPERAND_RJC : | |
1360 | fields->f_Rjc = value; | |
1361 | break; | |
1362 | case FR30_OPERAND_RS1 : | |
1363 | fields->f_Rs1 = value; | |
1364 | break; | |
1365 | case FR30_OPERAND_RS2 : | |
1366 | fields->f_Rs2 = value; | |
1367 | break; | |
1368 | case FR30_OPERAND_CC : | |
1369 | fields->f_cc = value; | |
1370 | break; | |
1371 | case FR30_OPERAND_CCC : | |
1372 | fields->f_ccc = value; | |
1373 | break; | |
1374 | case FR30_OPERAND_DIR10 : | |
1375 | fields->f_dir10 = value; | |
1376 | break; | |
1377 | case FR30_OPERAND_DIR8 : | |
1378 | fields->f_dir8 = value; | |
1379 | break; | |
1380 | case FR30_OPERAND_DIR9 : | |
1381 | fields->f_dir9 = value; | |
1382 | break; | |
1383 | case FR30_OPERAND_DISP10 : | |
1384 | fields->f_disp10 = value; | |
1385 | break; | |
1386 | case FR30_OPERAND_DISP8 : | |
1387 | fields->f_disp8 = value; | |
1388 | break; | |
1389 | case FR30_OPERAND_DISP9 : | |
1390 | fields->f_disp9 = value; | |
1391 | break; | |
1392 | case FR30_OPERAND_I20 : | |
1393 | fields->f_i20 = value; | |
1394 | break; | |
1395 | case FR30_OPERAND_I32 : | |
1396 | fields->f_i32 = value; | |
1397 | break; | |
1398 | case FR30_OPERAND_I8 : | |
1399 | fields->f_i8 = value; | |
1400 | break; | |
1401 | case FR30_OPERAND_LABEL12 : | |
1402 | fields->f_rel12 = value; | |
1403 | break; | |
1404 | case FR30_OPERAND_LABEL9 : | |
1405 | fields->f_rel9 = value; | |
1406 | break; | |
1407 | case FR30_OPERAND_M4 : | |
1408 | fields->f_m4 = value; | |
1409 | break; | |
1410 | case FR30_OPERAND_PS : | |
252b5132 RH |
1411 | break; |
1412 | case FR30_OPERAND_REGLIST_HI_LD : | |
1413 | fields->f_reglist_hi_ld = value; | |
1414 | break; | |
1415 | case FR30_OPERAND_REGLIST_HI_ST : | |
1416 | fields->f_reglist_hi_st = value; | |
1417 | break; | |
1418 | case FR30_OPERAND_REGLIST_LOW_LD : | |
1419 | fields->f_reglist_low_ld = value; | |
1420 | break; | |
1421 | case FR30_OPERAND_REGLIST_LOW_ST : | |
1422 | fields->f_reglist_low_st = value; | |
1423 | break; | |
1424 | case FR30_OPERAND_S10 : | |
1425 | fields->f_s10 = value; | |
1426 | break; | |
1427 | case FR30_OPERAND_U10 : | |
1428 | fields->f_u10 = value; | |
1429 | break; | |
1430 | case FR30_OPERAND_U4 : | |
1431 | fields->f_u4 = value; | |
1432 | break; | |
1433 | case FR30_OPERAND_U4C : | |
1434 | fields->f_u4c = value; | |
1435 | break; | |
1436 | case FR30_OPERAND_U8 : | |
1437 | fields->f_u8 = value; | |
1438 | break; | |
1439 | case FR30_OPERAND_UDISP6 : | |
1440 | fields->f_udisp6 = value; | |
1441 | break; | |
1442 | ||
1443 | default : | |
1444 | /* xgettext:c-format */ | |
1445 | fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), | |
1446 | opindex); | |
1447 | abort (); | |
1448 | } | |
1449 | } | |
1450 | ||
1451 | /* Function to call before using the instruction builder tables. */ | |
1452 | ||
1453 | void | |
1454 | fr30_cgen_init_ibld_table (cd) | |
1455 | CGEN_CPU_DESC cd; | |
1456 | { | |
1457 | cd->insert_handlers = & fr30_cgen_insert_handlers[0]; | |
1458 | cd->extract_handlers = & fr30_cgen_extract_handlers[0]; | |
1459 | ||
1460 | cd->insert_operand = fr30_cgen_insert_operand; | |
1461 | cd->extract_operand = fr30_cgen_extract_operand; | |
1462 | ||
1463 | cd->get_int_operand = fr30_cgen_get_int_operand; | |
1464 | cd->set_int_operand = fr30_cgen_set_int_operand; | |
1465 | cd->get_vma_operand = fr30_cgen_get_vma_operand; | |
1466 | cd->set_vma_operand = fr30_cgen_set_vma_operand; | |
1467 | } |