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2000-09-19 H.J. Lu <hjl@gnu.org>
[deliverable/binutils-gdb.git] / opcodes / fr30-ibld.c
CommitLineData
252b5132
RH		 1/* Instruction building/extraction support for fr30. -*- C -*-
2
3THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
4- the resultant file is machine generated, cgen-ibld.in isn't
5
060d22b0 6Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
252b5132
RH		 7
8This file is part of the GNU Binutils and GDB, the GNU debugger.
9
10This program is free software; you can redistribute it and/or modify
11it under the terms of the GNU General Public License as published by
12the Free Software Foundation; either version 2, or (at your option)
13any later version.
14
15This program is distributed in the hope that it will be useful,
16but WITHOUT ANY WARRANTY; without even the implied warranty of
17MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18GNU General Public License for more details.
19
20You should have received a copy of the GNU General Public License
21along with this program; if not, write to the Free Software Foundation, Inc.,
2259 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23
24/* ??? Eventually more and more of this stuff can go to cpu-independent files.
25 Keep that in mind. */
26
27#include "sysdep.h"
252b5132
RH		 28#include <stdio.h>
29#include "ansidecl.h"
30#include "dis-asm.h"
31#include "bfd.h"
32#include "symcat.h"
33#include "fr30-desc.h"
34#include "fr30-opc.h"
35#include "opintl.h"
36
37#undef min
38#define min(a,b) ((a) < (b) ? (a) : (b))
39#undef max
40#define max(a,b) ((a) > (b) ? (a) : (b))
41
42/* Used by the ifield rtx function. */
43#define FLD(f) (fields->f)
44
45static const char * insert_normal
46 PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
47 unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR));
48static const char * insert_insn_normal
49 PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *,
50 CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
51
52static int extract_normal
53 PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
54 unsigned int, unsigned int, unsigned int, unsigned int,
55 unsigned int, unsigned int, bfd_vma, long *));
56static int extract_insn_normal
57 PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
58 CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
6bb95a0f
DB		 59static void put_insn_int_value
60 PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT));
61
252b5132
RH		 62\f
63/* Operand insertion. */
64
65#if ! CGEN_INT_INSN_P
66
67/* Subroutine of insert_normal. */
68
69static CGEN_INLINE void
70insert_1 (cd, value, start, length, word_length, bufp)
71 CGEN_CPU_DESC cd;
72 unsigned long value;
73 int start,length,word_length;
74 unsigned char *bufp;
75{
76 unsigned long x,mask;
77 int shift;
78 int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
79
b3466c39 80 x = bfd_get_bits (bufp, word_length, big_p);
252b5132
RH		 81
82 /* Written this way to avoid undefined behaviour. */
83 mask = (((1L << (length - 1)) - 1) << 1) | 1;
84 if (CGEN_INSN_LSB0_P)
85 shift = (start + 1) - length;
86 else
87 shift = (word_length - (start + length));
88 x = (x & ~(mask << shift)) | ((value & mask) << shift);
89
b3466c39 90 bfd_put_bits ((bfd_vma) x, bufp, word_length, big_p);
252b5132
RH		 91}
92
93#endif /* ! CGEN_INT_INSN_P */
94
95/* Default insertion routine.
96
97 ATTRS is a mask of the boolean attributes.
98 WORD_OFFSET is the offset in bits from the start of the insn of the value.
99 WORD_LENGTH is the length of the word in bits in which the value resides.
100 START is the starting bit number in the word, architecture origin.
101 LENGTH is the length of VALUE in bits.
102 TOTAL_LENGTH is the total length of the insn in bits.
103
104 The result is an error message or NULL if success. */
105
106/* ??? This duplicates functionality with bfd's howto table and
107 bfd_install_relocation. */
108/* ??? This doesn't handle bfd_vma's. Create another function when
109 necessary. */
110
111static const char *
112insert_normal (cd, value, attrs, word_offset, start, length, word_length,
113 total_length, buffer)
114 CGEN_CPU_DESC cd;
115 long value;
116 unsigned int attrs;
117 unsigned int word_offset, start, length, word_length, total_length;
118 CGEN_INSN_BYTES_PTR buffer;
119{
120 static char errbuf[100];
121 /* Written this way to avoid undefined behaviour. */
122 unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
123
124 /* If LENGTH is zero, this operand doesn't contribute to the value. */
125 if (length == 0)
126 return NULL;
127
6bb95a0f 128#if 0
252b5132
RH		 129 if (CGEN_INT_INSN_P
130 && word_offset != 0)
131 abort ();
6bb95a0f 132#endif
252b5132
RH		 133
134 if (word_length > 32)
135 abort ();
136
137 /* For architectures with insns smaller than the base-insn-bitsize,
138 word_length may be too big. */
139 if (cd->min_insn_bitsize < cd->base_insn_bitsize)
140 {
141 if (word_offset == 0
142 && word_length > total_length)
143 word_length = total_length;
144 }
145
146 /* Ensure VALUE will fit. */
fc7bc883
RH		 147 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT))
148 {
149 long minval = - (1L << (length - 1));
150 unsigned long maxval = mask;
151
152 if ((value > 0 && (unsigned long) value > maxval)
153 || value < minval)
154 {
155 /* xgettext:c-format */
156 sprintf (errbuf,
157 _("operand out of range (%ld not between %ld and %lu)"),
158 value, minval, maxval);
159 return errbuf;
160 }
161 }
162 else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
252b5132
RH		 163 {
164 unsigned long maxval = mask;
6bb95a0f 165
252b5132
RH		 166 if ((unsigned long) value > maxval)
167 {
168 /* xgettext:c-format */
169 sprintf (errbuf,
170 _("operand out of range (%lu not between 0 and %lu)"),
171 value, maxval);
172 return errbuf;
173 }
174 }
175 else
176 {
6bb95a0f 177 if (! cgen_signed_overflow_ok_p (cd))
252b5132 178 {
6bb95a0f
DB		 179 long minval = - (1L << (length - 1));
180 long maxval = (1L << (length - 1)) - 1;
181
182 if (value < minval || value > maxval)
183 {
184 sprintf
185 /* xgettext:c-format */
186 (errbuf, _("operand out of range (%ld not between %ld and %ld)"),
187 value, minval, maxval);
188 return errbuf;
189 }
252b5132
RH		 190 }
191 }
192
193#if CGEN_INT_INSN_P
194
195 {
196 int shift;
197
198 if (CGEN_INSN_LSB0_P)
6bb95a0f 199 shift = (word_offset + start + 1) - length;
252b5132 200 else
6bb95a0f 201 shift = total_length - (word_offset + start + length);
252b5132
RH		 202 *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
203 }
204
205#else /* ! CGEN_INT_INSN_P */
206
207 {
208 unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
209
210 insert_1 (cd, value, start, length, word_length, bufp);
211 }
212
213#endif /* ! CGEN_INT_INSN_P */
214
215 return NULL;
216}
217
218/* Default insn builder (insert handler).
fc7bc883
RH		 219 The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
220 that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is
221 recorded in host byte order, otherwise BUFFER is an array of bytes
222 and the value is recorded in target byte order).
252b5132
RH		 223 The result is an error message or NULL if success. */
224
225static const char *
226insert_insn_normal (cd, insn, fields, buffer, pc)
227 CGEN_CPU_DESC cd;
228 const CGEN_INSN * insn;
229 CGEN_FIELDS * fields;
230 CGEN_INSN_BYTES_PTR buffer;
231 bfd_vma pc;
232{
233 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
234 unsigned long value;
b3466c39 235 const CGEN_SYNTAX_CHAR_TYPE * syn;
252b5132
RH		 236
237 CGEN_INIT_INSERT (cd);
238 value = CGEN_INSN_BASE_VALUE (insn);
239
240 /* If we're recording insns as numbers (rather than a string of bytes),
241 target byte order handling is deferred until later. */
242
243#if CGEN_INT_INSN_P
244
6bb95a0f
DB		 245 put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
246 CGEN_FIELDS_BITSIZE (fields), value);
252b5132
RH		 247
248#else
249
250 cgen_put_insn_value (cd, buffer, min (cd->base_insn_bitsize,
251 CGEN_FIELDS_BITSIZE (fields)),
252 value);
253
254#endif /* ! CGEN_INT_INSN_P */
255
256 /* ??? It would be better to scan the format's fields.
257 Still need to be able to insert a value based on the operand though;
258 e.g. storing a branch displacement that got resolved later.
259 Needs more thought first. */
260
b3466c39 261 for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
252b5132
RH		 262 {
263 const char *errmsg;
264
265 if (CGEN_SYNTAX_CHAR_P (* syn))
266 continue;
267
268 errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
269 fields, buffer, pc);
270 if (errmsg)
271 return errmsg;
272 }
273
274 return NULL;
275}
6bb95a0f
DB		 276
277/* Cover function to store an insn value into an integral insn. Must go here
278 because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
279
280static void
281put_insn_int_value (cd, buf, length, insn_length, value)
fc7bc883 282 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
6bb95a0f
DB		 283 CGEN_INSN_BYTES_PTR buf;
284 int length;
285 int insn_length;
286 CGEN_INSN_INT value;
287{
288 /* For architectures with insns smaller than the base-insn-bitsize,
289 length may be too big. */
290 if (length > insn_length)
291 *buf = value;
292 else
293 {
294 int shift = insn_length - length;
295 /* Written this way to avoid undefined behaviour. */
296 CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
297 *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
298 }
299}
252b5132
RH		 300\f
301/* Operand extraction. */
302
303#if ! CGEN_INT_INSN_P
304
305/* Subroutine of extract_normal.
306 Ensure sufficient bytes are cached in EX_INFO.
307 OFFSET is the offset in bytes from the start of the insn of the value.
308 BYTES is the length of the needed value.
309 Returns 1 for success, 0 for failure. */
310
311static CGEN_INLINE int
312fill_cache (cd, ex_info, offset, bytes, pc)
313 CGEN_CPU_DESC cd;
314 CGEN_EXTRACT_INFO *ex_info;
315 int offset, bytes;
316 bfd_vma pc;
317{
318 /* It's doubtful that the middle part has already been fetched so
319 we don't optimize that case. kiss. */
320 int mask;
321 disassemble_info *info = (disassemble_info *) ex_info->dis_info;
322
323 /* First do a quick check. */
324 mask = (1 << bytes) - 1;
325 if (((ex_info->valid >> offset) & mask) == mask)
326 return 1;
327
328 /* Search for the first byte we need to read. */
329 for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
330 if (! (mask & ex_info->valid))
331 break;
332
333 if (bytes)
334 {
335 int status;
336
337 pc += offset;
338 status = (*info->read_memory_func)
339 (pc, ex_info->insn_bytes + offset, bytes, info);
340
341 if (status != 0)
342 {
343 (*info->memory_error_func) (status, pc, info);
344 return 0;
345 }
346
347 ex_info->valid |= ((1 << bytes) - 1) << offset;
348 }
349
350 return 1;
351}
352
353/* Subroutine of extract_normal. */
354
355static CGEN_INLINE long
356extract_1 (cd, ex_info, start, length, word_length, bufp, pc)
357 CGEN_CPU_DESC cd;
358 CGEN_EXTRACT_INFO *ex_info;
359 int start,length,word_length;
360 unsigned char *bufp;
361 bfd_vma pc;
362{
b3466c39 363 unsigned long x;
252b5132
RH		 364 int shift;
365 int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
366
b3466c39 367 x = bfd_get_bits (bufp, word_length, big_p);
252b5132 368
252b5132
RH		 369 if (CGEN_INSN_LSB0_P)
370 shift = (start + 1) - length;
371 else
372 shift = (word_length - (start + length));
b3466c39 373 return x >> shift;
252b5132
RH		 374}
375
376#endif /* ! CGEN_INT_INSN_P */
377
378/* Default extraction routine.
379
380 INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
381 or sometimes less for cases like the m32r where the base insn size is 32
382 but some insns are 16 bits.
383 ATTRS is a mask of the boolean attributes. We only need `SIGNED',
384 but for generality we take a bitmask of all of them.
385 WORD_OFFSET is the offset in bits from the start of the insn of the value.
386 WORD_LENGTH is the length of the word in bits in which the value resides.
387 START is the starting bit number in the word, architecture origin.
388 LENGTH is the length of VALUE in bits.
389 TOTAL_LENGTH is the total length of the insn in bits.
390
391 Returns 1 for success, 0 for failure. */
392
393/* ??? The return code isn't properly used. wip. */
394
395/* ??? This doesn't handle bfd_vma's. Create another function when
396 necessary. */
397
398static int
399extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length,
400 word_length, total_length, pc, valuep)
401 CGEN_CPU_DESC cd;
6bb95a0f 402#if ! CGEN_INT_INSN_P
252b5132 403 CGEN_EXTRACT_INFO *ex_info;
6bb95a0f
DB		 404#else
405 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
406#endif
252b5132
RH		 407 CGEN_INSN_INT insn_value;
408 unsigned int attrs;
409 unsigned int word_offset, start, length, word_length, total_length;
6bb95a0f 410#if ! CGEN_INT_INSN_P
252b5132 411 bfd_vma pc;
6bb95a0f
DB		 412#else
413 bfd_vma pc ATTRIBUTE_UNUSED;
414#endif
252b5132
RH		 415 long *valuep;
416{
fc7bc883 417 long value, mask;
252b5132
RH		 418
419 /* If LENGTH is zero, this operand doesn't contribute to the value
420 so give it a standard value of zero. */
421 if (length == 0)
422 {
423 *valuep = 0;
424 return 1;
425 }
426
6bb95a0f 427#if 0
252b5132
RH		 428 if (CGEN_INT_INSN_P
429 && word_offset != 0)
430 abort ();
6bb95a0f 431#endif
252b5132
RH		 432
433 if (word_length > 32)
434 abort ();
435
436 /* For architectures with insns smaller than the insn-base-bitsize,
437 word_length may be too big. */
438 if (cd->min_insn_bitsize < cd->base_insn_bitsize)
439 {
440 if (word_offset == 0
441 && word_length > total_length)
442 word_length = total_length;
443 }
444
fc7bc883 445 /* Does the value reside in INSN_VALUE, and at the right alignment? */
252b5132 446
fc7bc883 447 if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length))
252b5132 448 {
252b5132 449 if (CGEN_INSN_LSB0_P)
6bb95a0f 450 value = insn_value >> ((word_offset + start + 1) - length);
252b5132 451 else
6bb95a0f 452 value = insn_value >> (total_length - ( word_offset + start + length));
252b5132
RH		 453 }
454
455#if ! CGEN_INT_INSN_P
456
457 else
458 {
459 unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
460
461 if (word_length > 32)
462 abort ();
463
464 if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
465 return 0;
466
467 value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
468 }
469
470#endif /* ! CGEN_INT_INSN_P */
471
b3466c39
DB		 472 /* Written this way to avoid undefined behaviour. */
473 mask = (((1L << (length - 1)) - 1) << 1) | 1;
474
475 value &= mask;
476 /* sign extend? */
477 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
478 && (value & (1L << (length - 1))))
479 value |= ~mask;
480
252b5132
RH		 481 *valuep = value;
482
483 return 1;
484}
485
486/* Default insn extractor.
487
488 INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
489 The extracted fields are stored in FIELDS.
490 EX_INFO is used to handle reading variable length insns.
491 Return the length of the insn in bits, or 0 if no match,
492 or -1 if an error occurs fetching data (memory_error_func will have
493 been called). */
494
495static int
496extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc)
497 CGEN_CPU_DESC cd;
498 const CGEN_INSN *insn;
499 CGEN_EXTRACT_INFO *ex_info;
500 CGEN_INSN_INT insn_value;
501 CGEN_FIELDS *fields;
502 bfd_vma pc;
503{
504 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
b3466c39 505 const CGEN_SYNTAX_CHAR_TYPE *syn;
252b5132
RH		 506
507 CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
508
509 CGEN_INIT_EXTRACT (cd);
510
511 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
512 {
513 int length;
514
515 if (CGEN_SYNTAX_CHAR_P (*syn))
516 continue;
517
518 length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
519 ex_info, insn_value, fields, pc);
520 if (length <= 0)
521 return length;
522 }
523
524 /* We recognized and successfully extracted this insn. */
525 return CGEN_INSN_BITSIZE (insn);
526}
527\f
528/* machine generated code added here */
529
530/* Main entry point for operand insertion.
531
532 This function is basically just a big switch statement. Earlier versions
533 used tables to look up the function to use, but
534 - if the table contains both assembler and disassembler functions then
535 the disassembler contains much of the assembler and vice-versa,
536 - there's a lot of inlining possibilities as things grow,
537 - using a switch statement avoids the function call overhead.
538
539 This function could be moved into `parse_insn_normal', but keeping it
540 separate makes clear the interface between `parse_insn_normal' and each of
541 the handlers. It's also needed by GAS to insert operands that couldn't be
542 resolved during parsing.
543*/
544
545const char *
546fr30_cgen_insert_operand (cd, opindex, fields, buffer, pc)
547 CGEN_CPU_DESC cd;
548 int opindex;
549 CGEN_FIELDS * fields;
550 CGEN_INSN_BYTES_PTR buffer;
551 bfd_vma pc;
552{
eb1b03df 553 const char * errmsg = NULL;
252b5132
RH		 554 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
555
556 switch (opindex)
557 {
558 case FR30_OPERAND_CRI :
559 errmsg = insert_normal (cd, fields->f_CRi, 0, 16, 12, 4, 16, total_length, buffer);
560 break;
561 case FR30_OPERAND_CRJ :
562 errmsg = insert_normal (cd, fields->f_CRj, 0, 16, 8, 4, 16, total_length, buffer);
563 break;
564 case FR30_OPERAND_R13 :
252b5132
RH		 565 break;
566 case FR30_OPERAND_R14 :
252b5132
RH		 567 break;
568 case FR30_OPERAND_R15 :
252b5132
RH		 569 break;
570 case FR30_OPERAND_RI :
571 errmsg = insert_normal (cd, fields->f_Ri, 0, 0, 12, 4, 16, total_length, buffer);
572 break;
573 case FR30_OPERAND_RIC :
574 errmsg = insert_normal (cd, fields->f_Ric, 0, 16, 12, 4, 16, total_length, buffer);
575 break;
576 case FR30_OPERAND_RJ :
577 errmsg = insert_normal (cd, fields->f_Rj, 0, 0, 8, 4, 16, total_length, buffer);
578 break;
579 case FR30_OPERAND_RJC :
580 errmsg = insert_normal (cd, fields->f_Rjc, 0, 16, 8, 4, 16, total_length, buffer);
581 break;
582 case FR30_OPERAND_RS1 :
583 errmsg = insert_normal (cd, fields->f_Rs1, 0, 0, 8, 4, 16, total_length, buffer);
584 break;
585 case FR30_OPERAND_RS2 :
586 errmsg = insert_normal (cd, fields->f_Rs2, 0, 0, 12, 4, 16, total_length, buffer);
587 break;
588 case FR30_OPERAND_CC :
589 errmsg = insert_normal (cd, fields->f_cc, 0, 0, 4, 4, 16, total_length, buffer);
590 break;
591 case FR30_OPERAND_CCC :
592 errmsg = insert_normal (cd, fields->f_ccc, 0, 16, 0, 8, 16, total_length, buffer);
593 break;
594 case FR30_OPERAND_DIR10 :
595 {
596 long value = fields->f_dir10;
597 value = ((unsigned int) (value) >> (2));
598 errmsg = insert_normal (cd, value, 0, 0, 8, 8, 16, total_length, buffer);
599 }
600 break;
601 case FR30_OPERAND_DIR8 :
602 errmsg = insert_normal (cd, fields->f_dir8, 0, 0, 8, 8, 16, total_length, buffer);
603 break;
604 case FR30_OPERAND_DIR9 :
605 {
606 long value = fields->f_dir9;
607 value = ((unsigned int) (value) >> (1));
608 errmsg = insert_normal (cd, value, 0, 0, 8, 8, 16, total_length, buffer);
609 }
610 break;
611 case FR30_OPERAND_DISP10 :
612 {
613 long value = fields->f_disp10;
614 value = ((int) (value) >> (2));
615 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, buffer);
616 }
617 break;
618 case FR30_OPERAND_DISP8 :
619 errmsg = insert_normal (cd, fields->f_disp8, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, buffer);
620 break;
621 case FR30_OPERAND_DISP9 :
622 {
623 long value = fields->f_disp9;
624 value = ((int) (value) >> (1));
625 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, buffer);
626 }
627 break;
628 case FR30_OPERAND_I20 :
629 {
630{
631 FLD (f_i20_4) = ((unsigned int) (FLD (f_i20)) >> (16));
632 FLD (f_i20_16) = ((FLD (f_i20)) & (65535));
633}
634 errmsg = insert_normal (cd, fields->f_i20_4, 0, 0, 8, 4, 16, total_length, buffer);
635 if (errmsg)
636 break;
637 errmsg = insert_normal (cd, fields->f_i20_16, 0, 16, 0, 16, 16, total_length, buffer);
638 if (errmsg)
639 break;
640 }
641 break;
642 case FR30_OPERAND_I32 :
643 errmsg = insert_normal (cd, fields->f_i32, 0|(1<<CGEN_IFLD_SIGN_OPT), 16, 0, 32, 32, total_length, buffer);
644 break;
645 case FR30_OPERAND_I8 :
646 errmsg = insert_normal (cd, fields->f_i8, 0, 0, 4, 8, 16, total_length, buffer);
647 break;
648 case FR30_OPERAND_LABEL12 :
649 {
650 long value = fields->f_rel12;
651 value = ((int) (((value) - (((pc) + (2))))) >> (1));
652 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 5, 11, 16, total_length, buffer);
653 }
654 break;
655 case FR30_OPERAND_LABEL9 :
656 {
657 long value = fields->f_rel9;
658 value = ((int) (((value) - (((pc) + (2))))) >> (1));
659 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 16, total_length, buffer);
660 }
661 break;
662 case FR30_OPERAND_M4 :
663 {
664 long value = fields->f_m4;
665 value = ((value) & (15));
666 errmsg = insert_normal (cd, value, 0, 0, 8, 4, 16, total_length, buffer);
667 }
668 break;
669 case FR30_OPERAND_PS :
252b5132
RH		 670 break;
671 case FR30_OPERAND_REGLIST_HI_LD :
672 errmsg = insert_normal (cd, fields->f_reglist_hi_ld, 0, 0, 8, 8, 16, total_length, buffer);
673 break;
674 case FR30_OPERAND_REGLIST_HI_ST :
675 errmsg = insert_normal (cd, fields->f_reglist_hi_st, 0, 0, 8, 8, 16, total_length, buffer);
676 break;
677 case FR30_OPERAND_REGLIST_LOW_LD :
678 errmsg = insert_normal (cd, fields->f_reglist_low_ld, 0, 0, 8, 8, 16, total_length, buffer);
679 break;
680 case FR30_OPERAND_REGLIST_LOW_ST :
681 errmsg = insert_normal (cd, fields->f_reglist_low_st, 0, 0, 8, 8, 16, total_length, buffer);
682 break;
683 case FR30_OPERAND_S10 :
684 {
685 long value = fields->f_s10;
686 value = ((int) (value) >> (2));
687 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 16, total_length, buffer);
688 }
689 break;
690 case FR30_OPERAND_U10 :
691 {
692 long value = fields->f_u10;
693 value = ((unsigned int) (value) >> (2));
694 errmsg = insert_normal (cd, value, 0, 0, 8, 8, 16, total_length, buffer);
695 }
696 break;
697 case FR30_OPERAND_U4 :
698 errmsg = insert_normal (cd, fields->f_u4, 0, 0, 8, 4, 16, total_length, buffer);
699 break;
700 case FR30_OPERAND_U4C :
701 errmsg = insert_normal (cd, fields->f_u4c, 0, 0, 12, 4, 16, total_length, buffer);
702 break;
703 case FR30_OPERAND_U8 :
704 errmsg = insert_normal (cd, fields->f_u8, 0, 0, 8, 8, 16, total_length, buffer);
705 break;
706 case FR30_OPERAND_UDISP6 :
707 {
708 long value = fields->f_udisp6;
709 value = ((unsigned int) (value) >> (2));
710 errmsg = insert_normal (cd, value, 0, 0, 8, 4, 16, total_length, buffer);
711 }
712 break;
713
714 default :
715 /* xgettext:c-format */
716 fprintf (stderr, _("Unrecognized field %d while building insn.\n"),
717 opindex);
718 abort ();
719 }
720
721 return errmsg;
722}
723
724/* Main entry point for operand extraction.
eb1b03df
DE		 725 The result is <= 0 for error, >0 for success.
726 ??? Actual values aren't well defined right now.
252b5132
RH		 727
728 This function is basically just a big switch statement. Earlier versions
729 used tables to look up the function to use, but
730 - if the table contains both assembler and disassembler functions then
731 the disassembler contains much of the assembler and vice-versa,
732 - there's a lot of inlining possibilities as things grow,
733 - using a switch statement avoids the function call overhead.
734
735 This function could be moved into `print_insn_normal', but keeping it
736 separate makes clear the interface between `print_insn_normal' and each of
737 the handlers.
738*/
739
740int
741fr30_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
742 CGEN_CPU_DESC cd;
743 int opindex;
744 CGEN_EXTRACT_INFO *ex_info;
745 CGEN_INSN_INT insn_value;
746 CGEN_FIELDS * fields;
747 bfd_vma pc;
748{
eb1b03df
DE		 749 /* Assume success (for those operands that are nops). */
750 int length = 1;
252b5132
RH		 751 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
752
753 switch (opindex)
754 {
755 case FR30_OPERAND_CRI :
756 length = extract_normal (cd, ex_info, insn_value, 0, 16, 12, 4, 16, total_length, pc, & fields->f_CRi);
757 break;
758 case FR30_OPERAND_CRJ :
759 length = extract_normal (cd, ex_info, insn_value, 0, 16, 8, 4, 16, total_length, pc, & fields->f_CRj);
760 break;
761 case FR30_OPERAND_R13 :
252b5132
RH		 762 break;
763 case FR30_OPERAND_R14 :
252b5132
RH		 764 break;
765 case FR30_OPERAND_R15 :
252b5132
RH		 766 break;
767 case FR30_OPERAND_RI :
768 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 16, total_length, pc, & fields->f_Ri);
769 break;
770 case FR30_OPERAND_RIC :
771 length = extract_normal (cd, ex_info, insn_value, 0, 16, 12, 4, 16, total_length, pc, & fields->f_Ric);
772 break;
773 case FR30_OPERAND_RJ :
774 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & fields->f_Rj);
775 break;
776 case FR30_OPERAND_RJC :
777 length = extract_normal (cd, ex_info, insn_value, 0, 16, 8, 4, 16, total_length, pc, & fields->f_Rjc);
778 break;
779 case FR30_OPERAND_RS1 :
780 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & fields->f_Rs1);
781 break;
782 case FR30_OPERAND_RS2 :
783 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 16, total_length, pc, & fields->f_Rs2);
784 break;
785 case FR30_OPERAND_CC :
786 length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 16, total_length, pc, & fields->f_cc);
787 break;
788 case FR30_OPERAND_CCC :
789 length = extract_normal (cd, ex_info, insn_value, 0, 16, 0, 8, 16, total_length, pc, & fields->f_ccc);
790 break;
791 case FR30_OPERAND_DIR10 :
792 {
793 long value;
794 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & value);
795 value = ((value) << (2));
796 fields->f_dir10 = value;
797 }
798 break;
799 case FR30_OPERAND_DIR8 :
800 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_dir8);
801 break;
802 case FR30_OPERAND_DIR9 :
803 {
804 long value;
805 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & value);
806 value = ((value) << (1));
807 fields->f_dir9 = value;
808 }
809 break;
810 case FR30_OPERAND_DISP10 :
811 {
812 long value;
813 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, pc, & value);
814 value = ((value) << (2));
815 fields->f_disp10 = value;
816 }
817 break;
818 case FR30_OPERAND_DISP8 :
819 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, pc, & fields->f_disp8);
820 break;
821 case FR30_OPERAND_DISP9 :
822 {
823 long value;
824 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, pc, & value);
825 value = ((value) << (1));
826 fields->f_disp9 = value;
827 }
828 break;
829 case FR30_OPERAND_I20 :
830 {
831 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & fields->f_i20_4);
6bb95a0f 832 if (length <= 0) break;
252b5132 833 length = extract_normal (cd, ex_info, insn_value, 0, 16, 0, 16, 16, total_length, pc, & fields->f_i20_16);
6bb95a0f 834 if (length <= 0) break;
252b5132
RH		 835{
836 FLD (f_i20) = ((((FLD (f_i20_4)) << (16))) | (FLD (f_i20_16)));
837}
838 }
839 break;
840 case FR30_OPERAND_I32 :
841 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGN_OPT), 16, 0, 32, 32, total_length, pc, & fields->f_i32);
842 break;
843 case FR30_OPERAND_I8 :
844 length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 8, 16, total_length, pc, & fields->f_i8);
845 break;
846 case FR30_OPERAND_LABEL12 :
847 {
848 long value;
849 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 5, 11, 16, total_length, pc, & value);
850 value = ((((value) << (1))) + (((pc) + (2))));
851 fields->f_rel12 = value;
852 }
853 break;
854 case FR30_OPERAND_LABEL9 :
855 {
856 long value;
857 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 16, total_length, pc, & value);
858 value = ((((value) << (1))) + (((pc) + (2))));
859 fields->f_rel9 = value;
860 }
861 break;
862 case FR30_OPERAND_M4 :
863 {
864 long value;
865 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & value);
866 value = ((value) | (((-1) << (4))));
867 fields->f_m4 = value;
868 }
869 break;
870 case FR30_OPERAND_PS :
252b5132
RH		 871 break;
872 case FR30_OPERAND_REGLIST_HI_LD :
873 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_reglist_hi_ld);
874 break;
875 case FR30_OPERAND_REGLIST_HI_ST :
876 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_reglist_hi_st);
877 break;
878 case FR30_OPERAND_REGLIST_LOW_LD :
879 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_reglist_low_ld);
880 break;
881 case FR30_OPERAND_REGLIST_LOW_ST :
882 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_reglist_low_st);
883 break;
884 case FR30_OPERAND_S10 :
885 {
886 long value;
887 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 16, total_length, pc, & value);
888 value = ((value) << (2));
889 fields->f_s10 = value;
890 }
891 break;
892 case FR30_OPERAND_U10 :
893 {
894 long value;
895 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & value);
896 value = ((value) << (2));
897 fields->f_u10 = value;
898 }
899 break;
900 case FR30_OPERAND_U4 :
901 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & fields->f_u4);
902 break;
903 case FR30_OPERAND_U4C :
904 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 16, total_length, pc, & fields->f_u4c);
905 break;
906 case FR30_OPERAND_U8 :
907 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_u8);
908 break;
909 case FR30_OPERAND_UDISP6 :
910 {
911 long value;
912 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & value);
913 value = ((value) << (2));
914 fields->f_udisp6 = value;
915 }
916 break;
917
918 default :
919 /* xgettext:c-format */
920 fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"),
921 opindex);
922 abort ();
923 }
924
925 return length;
926}
927
928cgen_insert_fn * const fr30_cgen_insert_handlers[] =
929{
930 insert_insn_normal,
931};
932
933cgen_extract_fn * const fr30_cgen_extract_handlers[] =
934{
935 extract_insn_normal,
936};
937
938/* Getting values from cgen_fields is handled by a collection of functions.
939 They are distinguished by the type of the VALUE argument they return.
940 TODO: floating point, inlining support, remove cases where result type
941 not appropriate. */
942
943int
944fr30_cgen_get_int_operand (cd, opindex, fields)
945 CGEN_CPU_DESC cd;
946 int opindex;
947 const CGEN_FIELDS * fields;
948{
949 int value;
950
951 switch (opindex)
952 {
953 case FR30_OPERAND_CRI :
954 value = fields->f_CRi;
955 break;
956 case FR30_OPERAND_CRJ :
957 value = fields->f_CRj;
958 break;
959 case FR30_OPERAND_R13 :
eb1b03df 960 value = 0;
252b5132
RH		 961 break;
962 case FR30_OPERAND_R14 :
eb1b03df 963 value = 0;
252b5132
RH		 964 break;
965 case FR30_OPERAND_R15 :
eb1b03df 966 value = 0;
252b5132
RH		 967 break;
968 case FR30_OPERAND_RI :
969 value = fields->f_Ri;
970 break;
971 case FR30_OPERAND_RIC :
972 value = fields->f_Ric;
973 break;
974 case FR30_OPERAND_RJ :
975 value = fields->f_Rj;
976 break;
977 case FR30_OPERAND_RJC :
978 value = fields->f_Rjc;
979 break;
980 case FR30_OPERAND_RS1 :
981 value = fields->f_Rs1;
982 break;
983 case FR30_OPERAND_RS2 :
984 value = fields->f_Rs2;
985 break;
986 case FR30_OPERAND_CC :
987 value = fields->f_cc;
988 break;
989 case FR30_OPERAND_CCC :
990 value = fields->f_ccc;
991 break;
992 case FR30_OPERAND_DIR10 :
993 value = fields->f_dir10;
994 break;
995 case FR30_OPERAND_DIR8 :
996 value = fields->f_dir8;
997 break;
998 case FR30_OPERAND_DIR9 :
999 value = fields->f_dir9;
1000 break;
1001 case FR30_OPERAND_DISP10 :
1002 value = fields->f_disp10;
1003 break;
1004 case FR30_OPERAND_DISP8 :
1005 value = fields->f_disp8;
1006 break;
1007 case FR30_OPERAND_DISP9 :
1008 value = fields->f_disp9;
1009 break;
1010 case FR30_OPERAND_I20 :
1011 value = fields->f_i20;
1012 break;
1013 case FR30_OPERAND_I32 :
1014 value = fields->f_i32;
1015 break;
1016 case FR30_OPERAND_I8 :
1017 value = fields->f_i8;
1018 break;
1019 case FR30_OPERAND_LABEL12 :
1020 value = fields->f_rel12;
1021 break;
1022 case FR30_OPERAND_LABEL9 :
1023 value = fields->f_rel9;
1024 break;
1025 case FR30_OPERAND_M4 :
1026 value = fields->f_m4;
1027 break;
1028 case FR30_OPERAND_PS :
eb1b03df 1029 value = 0;
252b5132
RH		 1030 break;
1031 case FR30_OPERAND_REGLIST_HI_LD :
1032 value = fields->f_reglist_hi_ld;
1033 break;
1034 case FR30_OPERAND_REGLIST_HI_ST :
1035 value = fields->f_reglist_hi_st;
1036 break;
1037 case FR30_OPERAND_REGLIST_LOW_LD :
1038 value = fields->f_reglist_low_ld;
1039 break;
1040 case FR30_OPERAND_REGLIST_LOW_ST :
1041 value = fields->f_reglist_low_st;
1042 break;
1043 case FR30_OPERAND_S10 :
1044 value = fields->f_s10;
1045 break;
1046 case FR30_OPERAND_U10 :
1047 value = fields->f_u10;
1048 break;
1049 case FR30_OPERAND_U4 :
1050 value = fields->f_u4;
1051 break;
1052 case FR30_OPERAND_U4C :
1053 value = fields->f_u4c;
1054 break;
1055 case FR30_OPERAND_U8 :
1056 value = fields->f_u8;
1057 break;
1058 case FR30_OPERAND_UDISP6 :
1059 value = fields->f_udisp6;
1060 break;
1061
1062 default :
1063 /* xgettext:c-format */
1064 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
1065 opindex);
1066 abort ();
1067 }
1068
1069 return value;
1070}
1071
1072bfd_vma
1073fr30_cgen_get_vma_operand (cd, opindex, fields)
1074 CGEN_CPU_DESC cd;
1075 int opindex;
1076 const CGEN_FIELDS * fields;
1077{
1078 bfd_vma value;
1079
1080 switch (opindex)
1081 {
1082 case FR30_OPERAND_CRI :
1083 value = fields->f_CRi;
1084 break;
1085 case FR30_OPERAND_CRJ :
1086 value = fields->f_CRj;
1087 break;
1088 case FR30_OPERAND_R13 :
eb1b03df 1089 value = 0;
252b5132
RH		 1090 break;
1091 case FR30_OPERAND_R14 :
eb1b03df 1092 value = 0;
252b5132
RH		 1093 break;
1094 case FR30_OPERAND_R15 :
eb1b03df 1095 value = 0;
252b5132
RH		 1096 break;
1097 case FR30_OPERAND_RI :
1098 value = fields->f_Ri;
1099 break;
1100 case FR30_OPERAND_RIC :
1101 value = fields->f_Ric;
1102 break;
1103 case FR30_OPERAND_RJ :
1104 value = fields->f_Rj;
1105 break;
1106 case FR30_OPERAND_RJC :
1107 value = fields->f_Rjc;
1108 break;
1109 case FR30_OPERAND_RS1 :
1110 value = fields->f_Rs1;
1111 break;
1112 case FR30_OPERAND_RS2 :
1113 value = fields->f_Rs2;
1114 break;
1115 case FR30_OPERAND_CC :
1116 value = fields->f_cc;
1117 break;
1118 case FR30_OPERAND_CCC :
1119 value = fields->f_ccc;
1120 break;
1121 case FR30_OPERAND_DIR10 :
1122 value = fields->f_dir10;
1123 break;
1124 case FR30_OPERAND_DIR8 :
1125 value = fields->f_dir8;
1126 break;
1127 case FR30_OPERAND_DIR9 :
1128 value = fields->f_dir9;
1129 break;
1130 case FR30_OPERAND_DISP10 :
1131 value = fields->f_disp10;
1132 break;
1133 case FR30_OPERAND_DISP8 :
1134 value = fields->f_disp8;
1135 break;
1136 case FR30_OPERAND_DISP9 :
1137 value = fields->f_disp9;
1138 break;
1139 case FR30_OPERAND_I20 :
1140 value = fields->f_i20;
1141 break;
1142 case FR30_OPERAND_I32 :
1143 value = fields->f_i32;
1144 break;
1145 case FR30_OPERAND_I8 :
1146 value = fields->f_i8;
1147 break;
1148 case FR30_OPERAND_LABEL12 :
1149 value = fields->f_rel12;
1150 break;
1151 case FR30_OPERAND_LABEL9 :
1152 value = fields->f_rel9;
1153 break;
1154 case FR30_OPERAND_M4 :
1155 value = fields->f_m4;
1156 break;
1157 case FR30_OPERAND_PS :
eb1b03df 1158 value = 0;
252b5132
RH		 1159 break;
1160 case FR30_OPERAND_REGLIST_HI_LD :
1161 value = fields->f_reglist_hi_ld;
1162 break;
1163 case FR30_OPERAND_REGLIST_HI_ST :
1164 value = fields->f_reglist_hi_st;
1165 break;
1166 case FR30_OPERAND_REGLIST_LOW_LD :
1167 value = fields->f_reglist_low_ld;
1168 break;
1169 case FR30_OPERAND_REGLIST_LOW_ST :
1170 value = fields->f_reglist_low_st;
1171 break;
1172 case FR30_OPERAND_S10 :
1173 value = fields->f_s10;
1174 break;
1175 case FR30_OPERAND_U10 :
1176 value = fields->f_u10;
1177 break;
1178 case FR30_OPERAND_U4 :
1179 value = fields->f_u4;
1180 break;
1181 case FR30_OPERAND_U4C :
1182 value = fields->f_u4c;
1183 break;
1184 case FR30_OPERAND_U8 :
1185 value = fields->f_u8;
1186 break;
1187 case FR30_OPERAND_UDISP6 :
1188 value = fields->f_udisp6;
1189 break;
1190
1191 default :
1192 /* xgettext:c-format */
1193 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
1194 opindex);
1195 abort ();
1196 }
1197
1198 return value;
1199}
1200
1201/* Stuffing values in cgen_fields is handled by a collection of functions.
1202 They are distinguished by the type of the VALUE argument they accept.
1203 TODO: floating point, inlining support, remove cases where argument type
1204 not appropriate. */
1205
1206void
1207fr30_cgen_set_int_operand (cd, opindex, fields, value)
1208 CGEN_CPU_DESC cd;
1209 int opindex;
1210 CGEN_FIELDS * fields;
1211 int value;
1212{
1213 switch (opindex)
1214 {
1215 case FR30_OPERAND_CRI :
1216 fields->f_CRi = value;
1217 break;
1218 case FR30_OPERAND_CRJ :
1219 fields->f_CRj = value;
1220 break;
1221 case FR30_OPERAND_R13 :
252b5132
RH		 1222 break;
1223 case FR30_OPERAND_R14 :
252b5132
RH		 1224 break;
1225 case FR30_OPERAND_R15 :
252b5132
RH		 1226 break;
1227 case FR30_OPERAND_RI :
1228 fields->f_Ri = value;
1229 break;
1230 case FR30_OPERAND_RIC :
1231 fields->f_Ric = value;
1232 break;
1233 case FR30_OPERAND_RJ :
1234 fields->f_Rj = value;
1235 break;
1236 case FR30_OPERAND_RJC :
1237 fields->f_Rjc = value;
1238 break;
1239 case FR30_OPERAND_RS1 :
1240 fields->f_Rs1 = value;
1241 break;
1242 case FR30_OPERAND_RS2 :
1243 fields->f_Rs2 = value;
1244 break;
1245 case FR30_OPERAND_CC :
1246 fields->f_cc = value;
1247 break;
1248 case FR30_OPERAND_CCC :
1249 fields->f_ccc = value;
1250 break;
1251 case FR30_OPERAND_DIR10 :
1252 fields->f_dir10 = value;
1253 break;
1254 case FR30_OPERAND_DIR8 :
1255 fields->f_dir8 = value;
1256 break;
1257 case FR30_OPERAND_DIR9 :
1258 fields->f_dir9 = value;
1259 break;
1260 case FR30_OPERAND_DISP10 :
1261 fields->f_disp10 = value;
1262 break;
1263 case FR30_OPERAND_DISP8 :
1264 fields->f_disp8 = value;
1265 break;
1266 case FR30_OPERAND_DISP9 :
1267 fields->f_disp9 = value;
1268 break;
1269 case FR30_OPERAND_I20 :
1270 fields->f_i20 = value;
1271 break;
1272 case FR30_OPERAND_I32 :
1273 fields->f_i32 = value;
1274 break;
1275 case FR30_OPERAND_I8 :
1276 fields->f_i8 = value;
1277 break;
1278 case FR30_OPERAND_LABEL12 :
1279 fields->f_rel12 = value;
1280 break;
1281 case FR30_OPERAND_LABEL9 :
1282 fields->f_rel9 = value;
1283 break;
1284 case FR30_OPERAND_M4 :
1285 fields->f_m4 = value;
1286 break;
1287 case FR30_OPERAND_PS :
252b5132
RH		 1288 break;
1289 case FR30_OPERAND_REGLIST_HI_LD :
1290 fields->f_reglist_hi_ld = value;
1291 break;
1292 case FR30_OPERAND_REGLIST_HI_ST :
1293 fields->f_reglist_hi_st = value;
1294 break;
1295 case FR30_OPERAND_REGLIST_LOW_LD :
1296 fields->f_reglist_low_ld = value;
1297 break;
1298 case FR30_OPERAND_REGLIST_LOW_ST :
1299 fields->f_reglist_low_st = value;
1300 break;
1301 case FR30_OPERAND_S10 :
1302 fields->f_s10 = value;
1303 break;
1304 case FR30_OPERAND_U10 :
1305 fields->f_u10 = value;
1306 break;
1307 case FR30_OPERAND_U4 :
1308 fields->f_u4 = value;
1309 break;
1310 case FR30_OPERAND_U4C :
1311 fields->f_u4c = value;
1312 break;
1313 case FR30_OPERAND_U8 :
1314 fields->f_u8 = value;
1315 break;
1316 case FR30_OPERAND_UDISP6 :
1317 fields->f_udisp6 = value;
1318 break;
1319
1320 default :
1321 /* xgettext:c-format */
1322 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
1323 opindex);
1324 abort ();
1325 }
1326}
1327
1328void
1329fr30_cgen_set_vma_operand (cd, opindex, fields, value)
1330 CGEN_CPU_DESC cd;
1331 int opindex;
1332 CGEN_FIELDS * fields;
1333 bfd_vma value;
1334{
1335 switch (opindex)
1336 {
1337 case FR30_OPERAND_CRI :
1338 fields->f_CRi = value;
1339 break;
1340 case FR30_OPERAND_CRJ :
1341 fields->f_CRj = value;
1342 break;
1343 case FR30_OPERAND_R13 :
252b5132
RH		 1344 break;
1345 case FR30_OPERAND_R14 :
252b5132
RH		 1346 break;
1347 case FR30_OPERAND_R15 :
252b5132
RH		 1348 break;
1349 case FR30_OPERAND_RI :
1350 fields->f_Ri = value;
1351 break;
1352 case FR30_OPERAND_RIC :
1353 fields->f_Ric = value;
1354 break;
1355 case FR30_OPERAND_RJ :
1356 fields->f_Rj = value;
1357 break;
1358 case FR30_OPERAND_RJC :
1359 fields->f_Rjc = value;
1360 break;
1361 case FR30_OPERAND_RS1 :
1362 fields->f_Rs1 = value;
1363 break;
1364 case FR30_OPERAND_RS2 :
1365 fields->f_Rs2 = value;
1366 break;
1367 case FR30_OPERAND_CC :
1368 fields->f_cc = value;
1369 break;
1370 case FR30_OPERAND_CCC :
1371 fields->f_ccc = value;
1372 break;
1373 case FR30_OPERAND_DIR10 :
1374 fields->f_dir10 = value;
1375 break;
1376 case FR30_OPERAND_DIR8 :
1377 fields->f_dir8 = value;
1378 break;
1379 case FR30_OPERAND_DIR9 :
1380 fields->f_dir9 = value;
1381 break;
1382 case FR30_OPERAND_DISP10 :
1383 fields->f_disp10 = value;
1384 break;
1385 case FR30_OPERAND_DISP8 :
1386 fields->f_disp8 = value;
1387 break;
1388 case FR30_OPERAND_DISP9 :
1389 fields->f_disp9 = value;
1390 break;
1391 case FR30_OPERAND_I20 :
1392 fields->f_i20 = value;
1393 break;
1394 case FR30_OPERAND_I32 :
1395 fields->f_i32 = value;
1396 break;
1397 case FR30_OPERAND_I8 :
1398 fields->f_i8 = value;
1399 break;
1400 case FR30_OPERAND_LABEL12 :
1401 fields->f_rel12 = value;
1402 break;
1403 case FR30_OPERAND_LABEL9 :
1404 fields->f_rel9 = value;
1405 break;
1406 case FR30_OPERAND_M4 :
1407 fields->f_m4 = value;
1408 break;
1409 case FR30_OPERAND_PS :
252b5132
RH		 1410 break;
1411 case FR30_OPERAND_REGLIST_HI_LD :
1412 fields->f_reglist_hi_ld = value;
1413 break;
1414 case FR30_OPERAND_REGLIST_HI_ST :
1415 fields->f_reglist_hi_st = value;
1416 break;
1417 case FR30_OPERAND_REGLIST_LOW_LD :
1418 fields->f_reglist_low_ld = value;
1419 break;
1420 case FR30_OPERAND_REGLIST_LOW_ST :
1421 fields->f_reglist_low_st = value;
1422 break;
1423 case FR30_OPERAND_S10 :
1424 fields->f_s10 = value;
1425 break;
1426 case FR30_OPERAND_U10 :
1427 fields->f_u10 = value;
1428 break;
1429 case FR30_OPERAND_U4 :
1430 fields->f_u4 = value;
1431 break;
1432 case FR30_OPERAND_U4C :
1433 fields->f_u4c = value;
1434 break;
1435 case FR30_OPERAND_U8 :
1436 fields->f_u8 = value;
1437 break;
1438 case FR30_OPERAND_UDISP6 :
1439 fields->f_udisp6 = value;
1440 break;
1441
1442 default :
1443 /* xgettext:c-format */
1444 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
1445 opindex);
1446 abort ();
1447 }
1448}
1449
1450/* Function to call before using the instruction builder tables. */
1451
1452void
1453fr30_cgen_init_ibld_table (cd)
1454 CGEN_CPU_DESC cd;
1455{
1456 cd->insert_handlers = & fr30_cgen_insert_handlers[0];
1457 cd->extract_handlers = & fr30_cgen_extract_handlers[0];
1458
1459 cd->insert_operand = fr30_cgen_insert_operand;
1460 cd->extract_operand = fr30_cgen_extract_operand;
1461
1462 cd->get_int_operand = fr30_cgen_get_int_operand;
1463 cd->set_int_operand = fr30_cgen_set_int_operand;
1464 cd->get_vma_operand = fr30_cgen_get_vma_operand;
1465 cd->set_vma_operand = fr30_cgen_set_vma_operand;
1466}
GDB Binutils - Deliverables
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