projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Wed Nov 18 18:18:43 1998 Geoffrey Noer <noer@cygnus.com>
[deliverable/binutils-gdb.git] / opcodes / fr30-opc.c
CommitLineData
a86481d3
DB		 1/* Generic opcode table support for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
3
4THIS FILE IS USED TO GENERATE fr30-opc.c.
5
6Copyright (C) 1998 Free Software Foundation, Inc.
7
8This file is part of the GNU Binutils and GDB, the GNU debugger.
9
10This program is free software; you can redistribute it and/or modify
11it under the terms of the GNU General Public License as published by
12the Free Software Foundation; either version 2, or (at your option)
13any later version.
14
15This program is distributed in the hope that it will be useful,
16but WITHOUT ANY WARRANTY; without even the implied warranty of
17MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18GNU General Public License for more details.
19
20You should have received a copy of the GNU General Public License
21along with this program; if not, write to the Free Software Foundation, Inc.,
2259 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23
24#include "sysdep.h"
25#include <stdio.h>
26#include "ansidecl.h"
27#include "libiberty.h"
28#include "bfd.h"
29#include "symcat.h"
30#include "fr30-opc.h"
31#include "opintl.h"
32
33/* The hash functions are recorded here to help keep assembler code out of
34 the disassembler and vice versa. */
35
36static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
37static unsigned int asm_hash_insn PARAMS ((const char *));
38static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
95b03313 39static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
a86481d3
DB		 40
41/* Look up instruction INSN_VALUE and extract its fields.
42 INSN, if non-null, is the insn table entry.
43 Otherwise INSN_VALUE is examined to compute it.
44 LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
45 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
46 If INSN != NULL, LENGTH must be valid.
47 ALIAS_P is non-zero if alias insns are to be included in the search.
48
95b03313 49 The result is a pointer to the insn table entry, or NULL if the instruction
a86481d3
DB		 50 wasn't recognized. */
51
52const CGEN_INSN *
53fr30_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
54 CGEN_OPCODE_DESC od;
55 const CGEN_INSN *insn;
56 CGEN_INSN_BYTES insn_value;
57 int length;
58 CGEN_FIELDS *fields;
59 int alias_p;
60{
95b03313 61 unsigned char buf[CGEN_MAX_INSN_SIZE];
a86481d3 62 unsigned char *bufp;
95b03313 63 CGEN_INSN_INT base_insn;
a86481d3
DB		 64#if CGEN_INT_INSN_P
65 CGEN_EXTRACT_INFO *info = NULL;
66#else
67 CGEN_EXTRACT_INFO ex_info;
68 CGEN_EXTRACT_INFO *info = &ex_info;
69#endif
70
95b03313
DE		 71#if CGEN_INT_INSN_P
72 cgen_put_insn_value (od, buf, length, insn_value);
73 bufp = buf;
74 base_insn = insn_value; /*???*/
75#else
a86481d3 76 ex_info.dis_info = NULL;
95b03313 77 ex_info.insn_bytes = insn_value;
a86481d3 78 ex_info.valid = -1;
95b03313
DE		 79 base_insn = cgen_get_insn_value (od, buf, length);
80 bufp = insn_value;
a86481d3
DB		 81#endif
82
83 if (!insn)
84 {
85 const CGEN_INSN_LIST *insn_list;
86
a86481d3
DB		 87 /* The instructions are stored in hash lists.
88 Pick the first one and keep trying until we find the right one. */
89
90 insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn);
91 while (insn_list != NULL)
92 {
93 insn = insn_list->insn;
94
95 if (alias_p
96 || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
97 {
98 /* Basic bit mask must be correct. */
99 /* ??? May wish to allow target to defer this check until the
100 extract handler. */
95b03313 101 if ((base_insn & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
a86481d3
DB		 102 {
103 /* ??? 0 is passed for `pc' */
104 int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
95b03313 105 base_insn, fields,
a86481d3
DB		 106 (bfd_vma) 0);
107 if (elength > 0)
108 {
109 /* sanity check */
110 if (length != 0 && length != elength)
111 abort ();
112 return insn;
113 }
114 }
115 }
116
117 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
118 }
119 }
120 else
121 {
122 /* Sanity check: can't pass an alias insn if ! alias_p. */
123 if (! alias_p
124 && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
125 abort ();
126 /* Sanity check: length must be correct. */
127 if (length != CGEN_INSN_BITSIZE (insn))
128 abort ();
129
130 /* ??? 0 is passed for `pc' */
95b03313 131 length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, base_insn, fields,
a86481d3
DB		 132 (bfd_vma) 0);
133 /* Sanity check: must succeed.
134 Could relax this later if it ever proves useful. */
135 if (length == 0)
136 abort ();
137 return insn;
138 }
139
140 return NULL;
141}
142
143/* Fill in the operand instances used by INSN whose operands are FIELDS.
144 INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
145 in. */
146
147void
148fr30_cgen_get_insn_operands (od, insn, fields, indices)
149 CGEN_OPCODE_DESC od;
150 const CGEN_INSN * insn;
151 const CGEN_FIELDS * fields;
152 int *indices;
153{
154 const CGEN_OPERAND_INSTANCE *opinst;
155 int i;
156
157 for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
158 opinst != NULL
159 && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
160 ++i, ++opinst)
161 {
162 const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
163 if (op == NULL)
164 indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
165 else
166 indices[i] = fr30_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
167 fields);
168 }
169}
170
171/* Cover function to fr30_cgen_get_insn_operands when either INSN or FIELDS
172 isn't known.
173 The INSN, INSN_VALUE, and LENGTH arguments are passed to
174 fr30_cgen_lookup_insn unchanged.
175
176 The result is the insn table entry or NULL if the instruction wasn't
177 recognized. */
178
179const CGEN_INSN *
180fr30_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
181 CGEN_OPCODE_DESC od;
182 const CGEN_INSN *insn;
183 CGEN_INSN_BYTES insn_value;
184 int length;
185 int *indices;
186{
187 CGEN_FIELDS fields;
188
189 /* Pass non-zero for ALIAS_P only if INSN != NULL.
190 If INSN == NULL, we want a real insn. */
191 insn = fr30_cgen_lookup_insn (od, insn, insn_value, length, &fields,
192 insn != NULL);
193 if (! insn)
194 return NULL;
195
196 fr30_cgen_get_insn_operands (od, insn, &fields, indices);
197 return insn;
198}
199/* Attributes. */
200
201static const CGEN_ATTR_ENTRY MACH_attr[] =
202{
203 { "base", MACH_BASE },
204 { "fr30", MACH_FR30 },
205 { "max", MACH_MAX },
206 { 0, 0 }
207};
208
209const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
210{
211 { "CACHE-ADDR", NULL },
212 { "PC", NULL },
213 { "PROFILE", NULL },
214 { 0, 0 }
215};
216
217const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
218{
219 { "ABS-ADDR", NULL },
7a0737c8 220 { "HASH-PREFIX", NULL },
a86481d3
DB		 221 { "NEGATIVE", NULL },
222 { "PCREL-ADDR", NULL },
223 { "RELAX", NULL },
1c8f439e 224 { "SEM-ONLY", NULL },
a86481d3 225 { "SIGN-OPT", NULL },
7a0737c8 226 { "SIGNED", NULL },
a86481d3
DB		 227 { "UNSIGNED", NULL },
228 { 0, 0 }
229};
230
231const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
232{
233 { "ALIAS", NULL },
234 { "COND-CTI", NULL },
235 { "NO-DIS", NULL },
236 { "RELAX", NULL },
237 { "RELAXABLE", NULL },
238 { "SKIP-CTI", NULL },
239 { "UNCOND-CTI", NULL },
240 { "VIRTUAL", NULL },
241 { 0, 0 }
242};
243
244CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_gr_entries[] =
245{
246 { "ac", 13 },
247 { "fp", 14 },
248 { "sp", 15 },
249 { "r0", 0 },
250 { "r1", 1 },
251 { "r2", 2 },
252 { "r3", 3 },
253 { "r4", 4 },
254 { "r5", 5 },
255 { "r6", 6 },
256 { "r7", 7 },
257 { "r8", 8 },
258 { "r9", 9 },
259 { "r10", 10 },
260 { "r11", 11 },
261 { "r12", 12 },
262 { "r13", 13 },
263 { "r14", 14 },
264 { "r15", 15 }
265};
266
267CGEN_KEYWORD fr30_cgen_opval_h_gr =
268{
269 & fr30_cgen_opval_h_gr_entries[0],
270 19
271};
272
6146431a
DB		 273CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_dr_entries[] =
274{
275 { "tbr", 0 },
276 { "rp", 1 },
277 { "ssp", 2 },
7a0737c8 278 { "usp", 3 },
6146431a
DB		 279 { "mdh", 4 },
280 { "mdl", 5 }
281};
282
7a0737c8 283CGEN_KEYWORD fr30_cgen_opval_h_dr =
6146431a 284{
7a0737c8
DB		 285 & fr30_cgen_opval_h_dr_entries[0],
286 6
6146431a
DB		 287};
288
6a1254af 289CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] =
6146431a 290{
6146431a
DB		 291 { "ps", 1 }
292};
293
6a1254af 294CGEN_KEYWORD fr30_cgen_opval_h_ps =
6146431a 295{
6a1254af
DB		 296 & fr30_cgen_opval_h_ps_entries[0],
297 1
298};
299
300CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] =
301{
302 { "r13", 13 }
303};
304
305CGEN_KEYWORD fr30_cgen_opval_h_r13 =
306{
307 & fr30_cgen_opval_h_r13_entries[0],
308 1
309};
310
311CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] =
312{
313 { "r14", 14 }
314};
315
316CGEN_KEYWORD fr30_cgen_opval_h_r14 =
317{
318 & fr30_cgen_opval_h_r14_entries[0],
319 1
320};
321
322CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] =
323{
324 { "r15", 15 }
325};
326
327CGEN_KEYWORD fr30_cgen_opval_h_r15 =
328{
329 & fr30_cgen_opval_h_r15_entries[0],
330 1
6146431a
DB		 331};
332
a86481d3
DB		 333
334/* The hardware table. */
335
336#define HW_ENT(n) fr30_cgen_hw_entries[n]
337static const CGEN_HW_ENTRY fr30_cgen_hw_entries[] =
338{
339 { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { 0 } } },
340 { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
341 { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
342 { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
343 { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
344 { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
345 { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_gr, { 0, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { 0 } } },
6146431a 346 { HW_H_DR, & HW_ENT (HW_H_DR + 1), "h-dr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_dr, { 0, 0, { 0 } } },
6a1254af
DB		 347 { HW_H_PS, & HW_ENT (HW_H_PS + 1), "h-ps", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, 0, { 0 } } },
348 { HW_H_R13, & HW_ENT (HW_H_R13 + 1), "h-r13", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, 0, { 0 } } },
349 { HW_H_R14, & HW_ENT (HW_H_R14 + 1), "h-r14", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, 0, { 0 } } },
350 { HW_H_R15, & HW_ENT (HW_H_R15 + 1), "h-r15", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, 0, { 0 } } },
7a0737c8
DB		 351 { HW_H_NBIT, & HW_ENT (HW_H_NBIT + 1), "h-nbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
352 { HW_H_ZBIT, & HW_ENT (HW_H_ZBIT + 1), "h-zbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
353 { HW_H_VBIT, & HW_ENT (HW_H_VBIT + 1), "h-vbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
354 { HW_H_CBIT, & HW_ENT (HW_H_CBIT + 1), "h-cbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
a86481d3
DB		 355 { 0 }
356};
357
358/* The operand table. */
359
360#define OPERAND(op) CONCAT2 (FR30_OPERAND_,op)
361#define OP_ENT(op) fr30_cgen_operand_table[OPERAND (op)]
362
363const CGEN_OPERAND fr30_cgen_operand_table[MAX_OPERANDS] =
364{
365/* pc: program counter */
366 { "pc", & HW_ENT (HW_H_PC), 0, 0,
1c8f439e 367 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
a86481d3
DB		 368/* Ri: destination register */
369 { "Ri", & HW_ENT (HW_H_GR), 12, 4,
370 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
371/* Rj: source register */
372 { "Rj", & HW_ENT (HW_H_GR), 8, 4,
373 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
7a0737c8
DB		 374/* Rs1: dedicated register */
375 { "Rs1", & HW_ENT (HW_H_DR), 8, 4,
376 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
377/* Rs2: dedicated register */
378 { "Rs2", & HW_ENT (HW_H_DR), 12, 4,
379 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
6a1254af
DB		 380/* R13: General Register 13 */
381 { "R13", & HW_ENT (HW_H_R13), 0, 0,
382 { 0, 0, { 0 } } },
383/* R14: General Register 14 */
384 { "R14", & HW_ENT (HW_H_R14), 0, 0,
385 { 0, 0, { 0 } } },
386/* R15: General Register 15 */
387 { "R15", & HW_ENT (HW_H_R15), 0, 0,
388 { 0, 0, { 0 } } },
7a0737c8 389/* ps: Program Status register */
6a1254af
DB		 390 { "ps", & HW_ENT (HW_H_PS), 0, 0,
391 { 0, 0, { 0 } } },
7a0737c8
DB		 392/* u4: 4 bit unsigned immediate */
393 { "u4", & HW_ENT (HW_H_UINT), 8, 4,
394 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
395/* m4: 4 bit negative immediate */
396 { "m4", & HW_ENT (HW_H_UINT), 8, 4,
397 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
7a0737c8
DB		 398/* u8: 8 bit unsigned immediate */
399 { "u8", & HW_ENT (HW_H_UINT), 8, 8,
400 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
6a1254af
DB		 401/* i8: 8 bit unsigned immediate */
402 { "i8", & HW_ENT (HW_H_UINT), 4, 8,
403 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
404/* udisp6: 6 bit unsigned immediate */
405 { "udisp6", & HW_ENT (HW_H_UINT), 8, 4,
7a0737c8 406 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
6a1254af
DB		 407/* disp8: 8 bit signed immediate */
408 { "disp8", & HW_ENT (HW_H_SINT), 4, 8,
409 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
410/* disp9: 9 bit signed immediate */
411 { "disp9", & HW_ENT (HW_H_SINT), 4, 8,
412 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
413/* disp10: 10 bit signed immediate */
414 { "disp10", & HW_ENT (HW_H_SINT), 4, 8,
415 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
7a0737c8
DB		 416/* s10: 10 bit signed immediate */
417 { "s10", & HW_ENT (HW_H_SINT), 8, 8,
418 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
419/* u10: 10 bit unsigned immediate */
420 { "u10", & HW_ENT (HW_H_UINT), 8, 8,
421 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
95b03313
DE		 422/* i32: 32 bit immediate */
423 { "i32", & HW_ENT (HW_H_UINT), 16, 32,
424 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
7a0737c8
DB		 425/* dir8: 8 bit direct address */
426 { "dir8", & HW_ENT (HW_H_UINT), 8, 8,
427 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
428/* dir9: 9 bit direct address */
429 { "dir9", & HW_ENT (HW_H_UINT), 8, 8,
430 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
431/* dir10: 10 bit direct address */
432 { "dir10", & HW_ENT (HW_H_UINT), 8, 8,
433 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
434/* label9: 9 bit pc relative address */
435 { "label9", & HW_ENT (HW_H_SINT), 8, 8,
436 { 0, 0|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
437/* label12: 12 bit pc relative address */
438 { "label12", & HW_ENT (HW_H_SINT), 5, 11,
439 { 0, 0|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
440/* cc: condition codes */
441 { "cc", & HW_ENT (HW_H_UINT), 4, 4,
442 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
6146431a
DB		 443/* nbit: negative bit */
444 { "nbit", & HW_ENT (HW_H_NBIT), 0, 0,
1c8f439e 445 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
6146431a
DB		 446/* vbit: overflow bit */
447 { "vbit", & HW_ENT (HW_H_VBIT), 0, 0,
1c8f439e 448 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
6146431a
DB		 449/* zbit: zero bit */
450 { "zbit", & HW_ENT (HW_H_ZBIT), 0, 0,
1c8f439e 451 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
6146431a
DB		 452/* cbit: carry bit */
453 { "cbit", & HW_ENT (HW_H_CBIT), 0, 0,
1c8f439e 454 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
a86481d3
DB		 455};
456
457/* Operand references. */
458
459#define INPUT CGEN_OPERAND_INSTANCE_INPUT
460#define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
95b03313 461#define COND_REF CGEN_OPERAND_INSTANCE_COND_REF
a86481d3 462
6146431a 463static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
95b03313
DE		 464 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
465 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
466 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
467 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
468 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
469 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
470 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
7a0737c8
DB		 471 { 0 }
472};
473
474static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
95b03313
DE		 475 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
476 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
477 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
478 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
479 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
480 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
481 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
7a0737c8
DB		 482 { 0 }
483};
484
485static const CGEN_OPERAND_INSTANCE fmt_add2_ops[] = {
95b03313
DE		 486 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
487 { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0, 0 },
488 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
489 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
490 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
491 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
492 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
7a0737c8
DB		 493 { 0 }
494};
495
496static const CGEN_OPERAND_INSTANCE fmt_addc_ops[] = {
95b03313
DE		 497 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
498 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
499 { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
500 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
501 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
502 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
503 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
504 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
7a0737c8
DB		 505 { 0 }
506};
507
508static const CGEN_OPERAND_INSTANCE fmt_addn_ops[] = {
95b03313
DE		 509 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
510 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
511 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
7a0737c8
DB		 512 { 0 }
513};
514
515static const CGEN_OPERAND_INSTANCE fmt_addni_ops[] = {
95b03313
DE		 516 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
517 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
518 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
7a0737c8
DB		 519 { 0 }
520};
521
522static const CGEN_OPERAND_INSTANCE fmt_addn2_ops[] = {
95b03313
DE		 523 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
524 { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0, 0 },
525 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
7a0737c8
DB		 526 { 0 }
527};
528
529static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
95b03313
DE		 530 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
531 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
532 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
533 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
534 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
535 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
7a0737c8
DB		 536 { 0 }
537};
538
539static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
95b03313
DE		 540 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
541 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
542 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
543 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
544 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
545 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
a86481d3
DB		 546 { 0 }
547};
548
7a0737c8 549static const CGEN_OPERAND_INSTANCE fmt_cmp2_ops[] = {
95b03313
DE		 550 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
551 { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0, 0 },
552 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
553 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
554 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
555 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
7a0737c8
DB		 556 { 0 }
557};
558
559static const CGEN_OPERAND_INSTANCE fmt_and_ops[] = {
95b03313
DE		 560 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
561 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
562 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
563 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
564 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
7a0737c8
DB		 565 { 0 }
566};
567
568static const CGEN_OPERAND_INSTANCE fmt_andm_ops[] = {
95b03313
DE		 569 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
570 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
571 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
572 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
573 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
574 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
7a0737c8
DB		 575 { 0 }
576};
577
578static const CGEN_OPERAND_INSTANCE fmt_andh_ops[] = {
95b03313
DE		 579 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
580 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
581 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (RJ), 0, 0 },
582 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
583 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
584 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
7a0737c8
DB		 585 { 0 }
586};
587
588static const CGEN_OPERAND_INSTANCE fmt_andb_ops[] = {
95b03313
DE		 589 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
590 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
591 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (RJ), 0, 0 },
592 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
593 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
594 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
595 { 0 }
596};
597
598static const CGEN_OPERAND_INSTANCE fmt_ldi32_ops[] = {
599 { INPUT, "i32", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I32), 0, 0 },
600 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
7a0737c8
DB		 601 { 0 }
602};
603
a86481d3
DB		 604#undef INPUT
605#undef OUTPUT
95b03313 606#undef COND_REF
a86481d3
DB		 607
608#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
609#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
610#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
611
612/* The instruction table.
613 This is currently non-static because the simulator accesses it
614 directly. */
615
616const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
617{
618 /* Special null first entry.
619 A `num' value of zero is thus invalid.
620 Also, the special `invalid' insn resides here. */
621 { { 0 }, 0 },
6146431a 622/* add $Rj,$Ri */
a86481d3
DB		 623 {
624 { 1, 1, 1, 1 },
7a0737c8
DB		 625 FR30_INSN_ADD, "add", "add",
626 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
627 { 16, 16, 0xff00 }, 0xa600,
628 (PTR) & fmt_add_ops[0],
629 { 0, 0, { 0 } }
630 },
631/* add $u4,$Ri */
632 {
633 { 1, 1, 1, 1 },
634 FR30_INSN_ADDI, "addi", "add",
635 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
636 { 16, 16, 0xff00 }, 0xa400,
637 (PTR) & fmt_addi_ops[0],
638 { 0, 0, { 0 } }
639 },
640/* add2 $m4,$Ri */
641 {
642 { 1, 1, 1, 1 },
643 FR30_INSN_ADD2, "add2", "add2",
644 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
645 { 16, 16, 0xff00 }, 0xa500,
646 (PTR) & fmt_add2_ops[0],
647 { 0, 0, { 0 } }
648 },
649/* addc $Rj,$Ri */
650 {
651 { 1, 1, 1, 1 },
652 FR30_INSN_ADDC, "addc", "addc",
653 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
654 { 16, 16, 0xff00 }, 0xa700,
655 (PTR) & fmt_addc_ops[0],
656 { 0, 0, { 0 } }
657 },
658/* addn $Rj,$Ri */
659 {
660 { 1, 1, 1, 1 },
661 FR30_INSN_ADDN, "addn", "addn",
662 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
663 { 16, 16, 0xff00 }, 0xa200,
664 (PTR) & fmt_addn_ops[0],
665 { 0, 0, { 0 } }
666 },
667/* addn $u4,$Ri */
668 {
669 { 1, 1, 1, 1 },
670 FR30_INSN_ADDNI, "addni", "addn",
671 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
672 { 16, 16, 0xff00 }, 0xa000,
673 (PTR) & fmt_addni_ops[0],
674 { 0, 0, { 0 } }
675 },
676/* addn2 $m4,$Ri */
677 {
678 { 1, 1, 1, 1 },
679 FR30_INSN_ADDN2, "addn2", "addn2",
680 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
681 { 16, 16, 0xff00 }, 0xa100,
682 (PTR) & fmt_addn2_ops[0],
683 { 0, 0, { 0 } }
684 },
685/* sub $Rj,$Ri */
686 {
687 { 1, 1, 1, 1 },
688 FR30_INSN_SUB, "sub", "sub",
689 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
690 { 16, 16, 0xff00 }, 0xac00,
691 (PTR) & fmt_add_ops[0],
692 { 0, 0, { 0 } }
693 },
694/* subc $Rj,$Ri */
695 {
696 { 1, 1, 1, 1 },
697 FR30_INSN_SUBC, "subc", "subc",
698 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
699 { 16, 16, 0xff00 }, 0xad00,
700 (PTR) & fmt_addc_ops[0],
701 { 0, 0, { 0 } }
702 },
703/* subn $Rj,$Ri */
704 {
705 { 1, 1, 1, 1 },
706 FR30_INSN_SUBN, "subn", "subn",
707 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
708 { 16, 16, 0xff00 }, 0xae00,
709 (PTR) & fmt_addn_ops[0],
710 { 0, 0, { 0 } }
711 },
712/* cmp $Rj,$Ri */
713 {
714 { 1, 1, 1, 1 },
715 FR30_INSN_CMP, "cmp", "cmp",
716 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
717 { 16, 16, 0xff00 }, 0xaa00,
718 (PTR) & fmt_cmp_ops[0],
719 { 0, 0, { 0 } }
720 },
721/* cmp $u4,$Ri */
722 {
723 { 1, 1, 1, 1 },
724 FR30_INSN_CMPI, "cmpi", "cmp",
725 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
726 { 16, 16, 0xff00 }, 0xa800,
727 (PTR) & fmt_cmpi_ops[0],
728 { 0, 0, { 0 } }
729 },
730/* cmp2 $m4,$Ri */
731 {
732 { 1, 1, 1, 1 },
733 FR30_INSN_CMP2, "cmp2", "cmp2",
734 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
735 { 16, 16, 0xff00 }, 0xa900,
736 (PTR) & fmt_cmp2_ops[0],
737 { 0, 0, { 0 } }
738 },
739/* and $Rj,$Ri */
740 {
741 { 1, 1, 1, 1 },
742 FR30_INSN_AND, "and", "and",
743 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
744 { 16, 16, 0xff00 }, 0x8200,
745 (PTR) & fmt_and_ops[0],
746 { 0, 0, { 0 } }
747 },
748/* or $Rj,$Ri */
749 {
750 { 1, 1, 1, 1 },
751 FR30_INSN_OR, "or", "or",
752 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
753 { 16, 16, 0xff00 }, 0x9200,
754 (PTR) & fmt_and_ops[0],
755 { 0, 0, { 0 } }
756 },
757/* eor $Rj,$Ri */
758 {
759 { 1, 1, 1, 1 },
760 FR30_INSN_EOR, "eor", "eor",
761 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
762 { 16, 16, 0xff00 }, 0x9a00,
763 (PTR) & fmt_and_ops[0],
764 { 0, 0, { 0 } }
765 },
766/* and $Rj,@$Ri */
767 {
768 { 1, 1, 1, 1 },
769 FR30_INSN_ANDM, "andm", "and",
770 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
771 { 16, 16, 0xff00 }, 0x8400,
772 (PTR) & fmt_andm_ops[0],
773 { 0, 0, { 0 } }
774 },
775/* andh $Rj,@$Ri */
776 {
777 { 1, 1, 1, 1 },
778 FR30_INSN_ANDH, "andh", "andh",
779 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
780 { 16, 16, 0xff00 }, 0x8500,
781 (PTR) & fmt_andh_ops[0],
782 { 0, 0, { 0 } }
783 },
784/* andb $Rj,@$Ri */
785 {
786 { 1, 1, 1, 1 },
787 FR30_INSN_ANDB, "andb", "andb",
788 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
789 { 16, 16, 0xff00 }, 0x8600,
790 (PTR) & fmt_andb_ops[0],
791 { 0, 0, { 0 } }
792 },
793/* or $Rj,@$Ri */
794 {
795 { 1, 1, 1, 1 },
796 FR30_INSN_ORM, "orm", "or",
797 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
798 { 16, 16, 0xff00 }, 0x9400,
799 (PTR) & fmt_andm_ops[0],
800 { 0, 0, { 0 } }
801 },
802/* orh $Rj,@$Ri */
803 {
804 { 1, 1, 1, 1 },
805 FR30_INSN_ORH, "orh", "orh",
806 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
807 { 16, 16, 0xff00 }, 0x9500,
808 (PTR) & fmt_andh_ops[0],
809 { 0, 0, { 0 } }
810 },
811/* orb $Rj,@$Ri */
812 {
813 { 1, 1, 1, 1 },
814 FR30_INSN_ORB, "orb", "orb",
815 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
816 { 16, 16, 0xff00 }, 0x9600,
817 (PTR) & fmt_andb_ops[0],
818 { 0, 0, { 0 } }
819 },
820/* eor $Rj,@$Ri */
821 {
822 { 1, 1, 1, 1 },
823 FR30_INSN_EORM, "eorm", "eor",
824 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
825 { 16, 16, 0xff00 }, 0x9c00,
826 (PTR) & fmt_andm_ops[0],
827 { 0, 0, { 0 } }
828 },
829/* eorh $Rj,@$Ri */
830 {
831 { 1, 1, 1, 1 },
832 FR30_INSN_EORH, "eorh", "eorh",
833 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
834 { 16, 16, 0xff00 }, 0x9d00,
835 (PTR) & fmt_andh_ops[0],
836 { 0, 0, { 0 } }
837 },
838/* eorb $Rj,@$Ri */
839 {
840 { 1, 1, 1, 1 },
841 FR30_INSN_EORB, "eorb", "eorb",
842 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
843 { 16, 16, 0xff00 }, 0x9e00,
844 (PTR) & fmt_andb_ops[0],
845 { 0, 0, { 0 } }
846 },
847/* bandl $u4,@$Ri */
848 {
849 { 1, 1, 1, 1 },
850 FR30_INSN_BANDL, "bandl", "bandl",
851 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
852 { 16, 16, 0xff00 }, 0x8000,
853 (PTR) 0,
854 { 0, 0, { 0 } }
855 },
856/* borl $u4,@$Ri */
857 {
858 { 1, 1, 1, 1 },
859 FR30_INSN_BORL, "borl", "borl",
860 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
861 { 16, 16, 0xff00 }, 0x9000,
862 (PTR) 0,
863 { 0, 0, { 0 } }
864 },
865/* beorl $u4,@$Ri */
866 {
867 { 1, 1, 1, 1 },
868 FR30_INSN_BEORL, "beorl", "beorl",
869 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
870 { 16, 16, 0xff00 }, 0x9800,
871 (PTR) 0,
872 { 0, 0, { 0 } }
873 },
874/* bandh $u4,@$Ri */
875 {
876 { 1, 1, 1, 1 },
877 FR30_INSN_BANDH, "bandh", "bandh",
878 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
879 { 16, 16, 0xff00 }, 0x8100,
880 (PTR) 0,
881 { 0, 0, { 0 } }
882 },
883/* borh $u4,@$Ri */
884 {
885 { 1, 1, 1, 1 },
886 FR30_INSN_BORH, "borh", "borh",
887 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
888 { 16, 16, 0xff00 }, 0x9100,
889 (PTR) 0,
890 { 0, 0, { 0 } }
891 },
892/* beorh $u4,@$Ri */
893 {
894 { 1, 1, 1, 1 },
895 FR30_INSN_BEORH, "beorh", "beorh",
896 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
897 { 16, 16, 0xff00 }, 0x9900,
898 (PTR) 0,
899 { 0, 0, { 0 } }
900 },
901/* btstl $u4,@$Ri */
902 {
903 { 1, 1, 1, 1 },
904 FR30_INSN_BTSTL, "btstl", "btstl",
905 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
906 { 16, 16, 0xff00 }, 0x8800,
907 (PTR) 0,
908 { 0, 0, { 0 } }
909 },
910/* btsth $u4,@$Ri */
911 {
912 { 1, 1, 1, 1 },
913 FR30_INSN_BTSTH, "btsth", "btsth",
914 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
915 { 16, 16, 0xff00 }, 0x8900,
916 (PTR) 0,
917 { 0, 0, { 0 } }
918 },
919/* mul $Rj,$Ri */
920 {
921 { 1, 1, 1, 1 },
922 FR30_INSN_MUL, "mul", "mul",
923 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
924 { 16, 16, 0xff00 }, 0xaf00,
925 (PTR) 0,
926 { 0, 0, { 0 } }
927 },
928/* mulu $Rj,$Ri */
929 {
930 { 1, 1, 1, 1 },
931 FR30_INSN_MULU, "mulu", "mulu",
932 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
933 { 16, 16, 0xff00 }, 0xab00,
934 (PTR) 0,
935 { 0, 0, { 0 } }
936 },
937/* mulh $Rj,$Ri */
938 {
939 { 1, 1, 1, 1 },
940 FR30_INSN_MULH, "mulh", "mulh",
941 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
942 { 16, 16, 0xff00 }, 0xbf00,
943 (PTR) 0,
944 { 0, 0, { 0 } }
945 },
946/* muluh $Rj,$Ri */
947 {
948 { 1, 1, 1, 1 },
949 FR30_INSN_MULUH, "muluh", "muluh",
950 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
951 { 16, 16, 0xff00 }, 0xbb00,
952 (PTR) 0,
953 { 0, 0, { 0 } }
954 },
955/* div0s $Ri */
956 {
957 { 1, 1, 1, 1 },
958 FR30_INSN_DIV0S, "div0s", "div0s",
959 { { MNEM, ' ', OP (RI), 0 } },
960 { 16, 16, 0xfff0 }, 0x9740,
961 (PTR) 0,
962 { 0, 0, { 0 } }
963 },
964/* div0u $Ri */
965 {
966 { 1, 1, 1, 1 },
967 FR30_INSN_DIV0U, "div0u", "div0u",
968 { { MNEM, ' ', OP (RI), 0 } },
969 { 16, 16, 0xfff0 }, 0x9750,
970 (PTR) 0,
971 { 0, 0, { 0 } }
972 },
973/* div1 $Ri */
974 {
975 { 1, 1, 1, 1 },
976 FR30_INSN_DIV1, "div1", "div1",
977 { { MNEM, ' ', OP (RI), 0 } },
978 { 16, 16, 0xfff0 }, 0x9760,
979 (PTR) 0,
980 { 0, 0, { 0 } }
981 },
982/* div2 $Ri */
983 {
984 { 1, 1, 1, 1 },
985 FR30_INSN_DIV2, "div2", "div2",
986 { { MNEM, ' ', OP (RI), 0 } },
987 { 16, 16, 0xfff0 }, 0x9770,
988 (PTR) 0,
989 { 0, 0, { 0 } }
990 },
991/* div3 */
992 {
993 { 1, 1, 1, 1 },
994 FR30_INSN_DIV3, "div3", "div3",
995 { { MNEM, 0 } },
996 { 16, 16, 0xffff }, 0x9f60,
997 (PTR) 0,
998 { 0, 0, { 0 } }
999 },
1000/* div4s */
1001 {
1002 { 1, 1, 1, 1 },
1003 FR30_INSN_DIV4S, "div4s", "div4s",
1004 { { MNEM, 0 } },
1005 { 16, 16, 0xffff }, 0x9f70,
1006 (PTR) 0,
1007 { 0, 0, { 0 } }
1008 },
1009/* lsl $Rj,$Ri */
1010 {
1011 { 1, 1, 1, 1 },
1012 FR30_INSN_LSL, "lsl", "lsl",
1013 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1014 { 16, 16, 0xff00 }, 0xb600,
1015 (PTR) 0,
1016 { 0, 0, { 0 } }
1017 },
1018/* lsl $u4,$Ri */
1019 {
1020 { 1, 1, 1, 1 },
1021 FR30_INSN_LSLI, "lsli", "lsl",
1022 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1023 { 16, 16, 0xff00 }, 0xb400,
1024 (PTR) 0,
1025 { 0, 0, { 0 } }
1026 },
1027/* lsl2 $u4,$Ri */
1028 {
1029 { 1, 1, 1, 1 },
1030 FR30_INSN_LSL2, "lsl2", "lsl2",
1031 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1032 { 16, 16, 0xff00 }, 0xb500,
1033 (PTR) 0,
1034 { 0, 0, { 0 } }
1035 },
1036/* lsr $Rj,$Ri */
1037 {
1038 { 1, 1, 1, 1 },
1039 FR30_INSN_LSR, "lsr", "lsr",
1040 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1041 { 16, 16, 0xff00 }, 0xb200,
1042 (PTR) 0,
1043 { 0, 0, { 0 } }
1044 },
1045/* lsr $u4,$Ri */
1046 {
1047 { 1, 1, 1, 1 },
1048 FR30_INSN_LSRI, "lsri", "lsr",
1049 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1050 { 16, 16, 0xff00 }, 0xb000,
1051 (PTR) 0,
1052 { 0, 0, { 0 } }
1053 },
1054/* lsr2 $u4,$Ri */
1055 {
1056 { 1, 1, 1, 1 },
1057 FR30_INSN_LSR2, "lsr2", "lsr2",
1058 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1059 { 16, 16, 0xff00 }, 0xb100,
1060 (PTR) 0,
1061 { 0, 0, { 0 } }
1062 },
1063/* asr $Rj,$Ri */
1064 {
1065 { 1, 1, 1, 1 },
1066 FR30_INSN_ASR, "asr", "asr",
1067 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1068 { 16, 16, 0xff00 }, 0xba00,
1069 (PTR) 0,
1070 { 0, 0, { 0 } }
1071 },
1072/* asr $u4,$Ri */
1073 {
1074 { 1, 1, 1, 1 },
1075 FR30_INSN_ASRI, "asri", "asr",
1076 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1077 { 16, 16, 0xff00 }, 0xb800,
1078 (PTR) 0,
1079 { 0, 0, { 0 } }
1080 },
1081/* asr2 $u4,$Ri */
1082 {
1083 { 1, 1, 1, 1 },
1084 FR30_INSN_ASR2, "asr2", "asr2",
1085 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1086 { 16, 16, 0xff00 }, 0xb900,
1087 (PTR) 0,
1088 { 0, 0, { 0 } }
1089 },
1090/* ldi:8 $i8,$Ri */
1091 {
1092 { 1, 1, 1, 1 },
1093 FR30_INSN_LDI_8, "ldi:8", "ldi:8",
1094 { { MNEM, ' ', OP (I8), ',', OP (RI), 0 } },
1095 { 16, 16, 0xf000 }, 0xc000,
1096 (PTR) 0,
1097 { 0, 0, { 0 } }
1098 },
95b03313
DE		 1099/* ldi:32 $i32,$Ri */
1100 {
1101 { 1, 1, 1, 1 },
1102 FR30_INSN_LDI32, "ldi32", "ldi:32",
1103 { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
1104 { 16, 48, 0xfff0 }, 0x9f80,
1105 (PTR) & fmt_ldi32_ops[0],
1106 { 0, 0, { 0 } }
1107 },
7a0737c8
DB		 1108/* ld @$Rj,$Ri */
1109 {
1110 { 1, 1, 1, 1 },
1111 FR30_INSN_LD, "ld", "ld",
1112 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1113 { 16, 16, 0xff00 }, 0x400,
1114 (PTR) 0,
1115 { 0, 0, { 0 } }
1116 },
1117/* lduh @$Rj,$Ri */
1118 {
1119 { 1, 1, 1, 1 },
1120 FR30_INSN_LDUH, "lduh", "lduh",
1121 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1122 { 16, 16, 0xff00 }, 0x500,
1123 (PTR) 0,
1124 { 0, 0, { 0 } }
1125 },
1126/* ldub @$Rj,$Ri */
1127 {
1128 { 1, 1, 1, 1 },
1129 FR30_INSN_LDUB, "ldub", "ldub",
1130 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1131 { 16, 16, 0xff00 }, 0x600,
1132 (PTR) 0,
1133 { 0, 0, { 0 } }
1134 },
6a1254af 1135/* ld @($r13,$Rj),$Ri */
7a0737c8
DB		 1136 {
1137 { 1, 1, 1, 1 },
1138 FR30_INSN_LDR13, "ldr13", "ld",
6a1254af 1139 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
7a0737c8
DB		 1140 { 16, 16, 0xff00 }, 0x0,
1141 (PTR) 0,
1142 { 0, 0, { 0 } }
1143 },
6a1254af 1144/* lduh @($r13,$Rj),$Ri */
7a0737c8
DB		 1145 {
1146 { 1, 1, 1, 1 },
1147 FR30_INSN_LDR13UH, "ldr13uh", "lduh",
6a1254af 1148 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
7a0737c8
DB		 1149 { 16, 16, 0xff00 }, 0x100,
1150 (PTR) 0,
1151 { 0, 0, { 0 } }
1152 },
6a1254af 1153/* ldub @($r13,$Rj),$Ri */
7a0737c8
DB		 1154 {
1155 { 1, 1, 1, 1 },
1156 FR30_INSN_LDR13UB, "ldr13ub", "ldub",
6a1254af 1157 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
7a0737c8
DB		 1158 { 16, 16, 0xff00 }, 0x200,
1159 (PTR) 0,
1160 { 0, 0, { 0 } }
1161 },
6a1254af 1162/* ld @($r14,$disp10),$Ri */
7a0737c8
DB		 1163 {
1164 { 1, 1, 1, 1 },
1165 FR30_INSN_LDR14, "ldr14", "ld",
6a1254af 1166 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP10), ')', ',', OP (RI), 0 } },
7a0737c8
DB		 1167 { 16, 16, 0xf000 }, 0x2000,
1168 (PTR) 0,
1169 { 0, 0, { 0 } }
1170 },
6a1254af 1171/* lduh @($r14,$disp9),$Ri */
7a0737c8
DB		 1172 {
1173 { 1, 1, 1, 1 },
1174 FR30_INSN_LDR14UH, "ldr14uh", "lduh",
6a1254af 1175 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP9), ')', ',', OP (RI), 0 } },
7a0737c8
DB		 1176 { 16, 16, 0xf000 }, 0x4000,
1177 (PTR) 0,
1178 { 0, 0, { 0 } }
1179 },
6a1254af 1180/* ldub @($r14,$disp8),$Ri */
7a0737c8
DB		 1181 {
1182 { 1, 1, 1, 1 },
1183 FR30_INSN_LDR14UB, "ldr14ub", "ldub",
6a1254af 1184 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP8), ')', ',', OP (RI), 0 } },
7a0737c8
DB		 1185 { 16, 16, 0xf000 }, 0x6000,
1186 (PTR) 0,
1187 { 0, 0, { 0 } }
1188 },
6a1254af 1189/* ld @($r15,$udisp6),$Ri */
7a0737c8
DB		 1190 {
1191 { 1, 1, 1, 1 },
1192 FR30_INSN_LDR15, "ldr15", "ld",
6a1254af 1193 { { MNEM, ' ', '@', '(', OP (R15), ',', OP (UDISP6), ')', ',', OP (RI), 0 } },
7a0737c8
DB		 1194 { 16, 16, 0xff00 }, 0x300,
1195 (PTR) 0,
1196 { 0, 0, { 0 } }
1197 },
6a1254af 1198/* ld @$r15+,$Ri */
7a0737c8
DB		 1199 {
1200 { 1, 1, 1, 1 },
1201 FR30_INSN_LDR15GR, "ldr15gr", "ld",
6a1254af 1202 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RI), 0 } },
7a0737c8
DB		 1203 { 16, 16, 0xfff0 }, 0x700,
1204 (PTR) 0,
1205 { 0, 0, { 0 } }
1206 },
6a1254af 1207/* ld @$r15+,$Rs2 */
7a0737c8
DB		 1208 {
1209 { 1, 1, 1, 1 },
1210 FR30_INSN_LDR15DR, "ldr15dr", "ld",
6a1254af 1211 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RS2), 0 } },
7a0737c8
DB		 1212 { 16, 16, 0xfff0 }, 0x780,
1213 (PTR) 0,
1214 { 0, 0, { 0 } }
1215 },
6a1254af 1216/* ld @$r15+,$ps */
7a0737c8
DB		 1217 {
1218 { 1, 1, 1, 1 },
1219 FR30_INSN_LDR15PS, "ldr15ps", "ld",
6a1254af 1220 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (PS), 0 } },
7a0737c8
DB		 1221 { 16, 16, 0xffff }, 0x790,
1222 (PTR) 0,
1223 { 0, 0, { 0 } }
1224 },
6a1254af 1225/* st $Ri,@$Rj */
7a0737c8
DB		 1226 {
1227 { 1, 1, 1, 1 },
1228 FR30_INSN_ST, "st", "st",
6a1254af 1229 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
7a0737c8
DB		 1230 { 16, 16, 0xff00 }, 0x1400,
1231 (PTR) 0,
1232 { 0, 0, { 0 } }
1233 },
6a1254af 1234/* sth $Ri,@$Rj */
7a0737c8
DB		 1235 {
1236 { 1, 1, 1, 1 },
1237 FR30_INSN_STH, "sth", "sth",
6a1254af 1238 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
7a0737c8
DB		 1239 { 16, 16, 0xff00 }, 0x1500,
1240 (PTR) 0,
1241 { 0, 0, { 0 } }
1242 },
6a1254af 1243/* stb $Ri,@$Rj */
7a0737c8
DB		 1244 {
1245 { 1, 1, 1, 1 },
1246 FR30_INSN_STB, "stb", "stb",
6a1254af 1247 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
7a0737c8
DB		 1248 { 16, 16, 0xff00 }, 0x1600,
1249 (PTR) 0,
1250 { 0, 0, { 0 } }
1251 },
6a1254af 1252/* st $Ri,@($r13,$Rj) */
7a0737c8
DB		 1253 {
1254 { 1, 1, 1, 1 },
1255 FR30_INSN_STR13, "str13", "st",
6a1254af 1256 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
7a0737c8
DB		 1257 { 16, 16, 0xff00 }, 0x1000,
1258 (PTR) 0,
1259 { 0, 0, { 0 } }
1260 },
6a1254af 1261/* sth $Ri,@($r13,$Rj) */
7a0737c8
DB		 1262 {
1263 { 1, 1, 1, 1 },
1264 FR30_INSN_STR13H, "str13h", "sth",
6a1254af 1265 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
7a0737c8
DB		 1266 { 16, 16, 0xff00 }, 0x1100,
1267 (PTR) 0,
1268 { 0, 0, { 0 } }
1269 },
6a1254af 1270/* stb $Ri,@($r13,$Rj) */
7a0737c8
DB		 1271 {
1272 { 1, 1, 1, 1 },
6a1254af
DB		 1273 FR30_INSN_STR13B, "stR13b", "stb",
1274 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
7a0737c8
DB		 1275 { 16, 16, 0xff00 }, 0x1200,
1276 (PTR) 0,
1277 { 0, 0, { 0 } }
1278 },
6a1254af 1279/* st $Ri,@($r14,$disp10) */
7a0737c8
DB		 1280 {
1281 { 1, 1, 1, 1 },
1282 FR30_INSN_STR14, "str14", "st",
6a1254af 1283 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP10), ')', 0 } },
7a0737c8
DB		 1284 { 16, 16, 0xf000 }, 0x3000,
1285 (PTR) 0,
1286 { 0, 0, { 0 } }
1287 },
6a1254af 1288/* sth $Ri,@($r14,$disp9) */
7a0737c8
DB		 1289 {
1290 { 1, 1, 1, 1 },
1291 FR30_INSN_STR14H, "str14h", "sth",
6a1254af 1292 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP9), ')', 0 } },
7a0737c8
DB		 1293 { 16, 16, 0xf000 }, 0x5000,
1294 (PTR) 0,
1295 { 0, 0, { 0 } }
1296 },
6a1254af 1297/* stb $Ri,@($r14,$disp8) */
7a0737c8
DB		 1298 {
1299 { 1, 1, 1, 1 },
1300 FR30_INSN_STR14B, "str14b", "stb",
6a1254af 1301 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP8), ')', 0 } },
7a0737c8
DB		 1302 { 16, 16, 0xf000 }, 0x7000,
1303 (PTR) 0,
1304 { 0, 0, { 0 } }
1305 },
6a1254af 1306/* st $Ri,@($r15,$udisp6) */
7a0737c8
DB		 1307 {
1308 { 1, 1, 1, 1 },
1309 FR30_INSN_STR15, "str15", "st",
6a1254af 1310 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R15), ',', OP (UDISP6), ')', 0 } },
7a0737c8
DB		 1311 { 16, 16, 0xff00 }, 0x1300,
1312 (PTR) 0,
1313 { 0, 0, { 0 } }
1314 },
6a1254af 1315/* st $Ri,@-$r15 */
7a0737c8
DB		 1316 {
1317 { 1, 1, 1, 1 },
1318 FR30_INSN_STR15GR, "str15gr", "st",
6a1254af 1319 { { MNEM, ' ', OP (RI), ',', '@', '-', OP (R15), 0 } },
7a0737c8
DB		 1320 { 16, 16, 0xfff0 }, 0x1700,
1321 (PTR) 0,
1322 { 0, 0, { 0 } }
1323 },
6a1254af 1324/* st $Rs2,@-$r15 */
7a0737c8
DB		 1325 {
1326 { 1, 1, 1, 1 },
1327 FR30_INSN_STR15DR, "str15dr", "st",
6a1254af 1328 { { MNEM, ' ', OP (RS2), ',', '@', '-', OP (R15), 0 } },
7a0737c8
DB		 1329 { 16, 16, 0xfff0 }, 0x1780,
1330 (PTR) 0,
1331 { 0, 0, { 0 } }
1332 },
6a1254af 1333/* st $ps,@-$r15 */
7a0737c8
DB		 1334 {
1335 { 1, 1, 1, 1 },
1336 FR30_INSN_STR15PS, "str15ps", "st",
6a1254af 1337 { { MNEM, ' ', OP (PS), ',', '@', '-', OP (R15), 0 } },
7a0737c8
DB		 1338 { 16, 16, 0xffff }, 0x1790,
1339 (PTR) 0,
1340 { 0, 0, { 0 } }
1341 },
1342/* mov $Rj,$Ri */
1343 {
1344 { 1, 1, 1, 1 },
1345 FR30_INSN_MOV, "mov", "mov",
1346 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1347 { 16, 16, 0xff00 }, 0x8b00,
1348 (PTR) 0,
1349 { 0, 0, { 0 } }
1350 },
1351/* mov $Rs1,$Ri */
1352 {
1353 { 1, 1, 1, 1 },
1354 FR30_INSN_MOVDR, "movdr", "mov",
1355 { { MNEM, ' ', OP (RS1), ',', OP (RI), 0 } },
1356 { 16, 16, 0xff00 }, 0xb700,
1357 (PTR) 0,
1358 { 0, 0, { 0 } }
1359 },
6a1254af 1360/* mov $ps,$Ri */
7a0737c8
DB		 1361 {
1362 { 1, 1, 1, 1 },
1363 FR30_INSN_MOVPS, "movps", "mov",
6a1254af 1364 { { MNEM, ' ', OP (PS), ',', OP (RI), 0 } },
7a0737c8
DB		 1365 { 16, 16, 0xfff0 }, 0x1710,
1366 (PTR) 0,
1367 { 0, 0, { 0 } }
1368 },
1369/* mov $Ri,$Rs1 */
1370 {
1371 { 1, 1, 1, 1 },
1372 FR30_INSN_MOV2DR, "mov2dr", "mov",
1373 { { MNEM, ' ', OP (RI), ',', OP (RS1), 0 } },
1374 { 16, 16, 0xff00 }, 0xb300,
1375 (PTR) 0,
1376 { 0, 0, { 0 } }
1377 },
6a1254af 1378/* mov $Ri,$ps */
7a0737c8
DB		 1379 {
1380 { 1, 1, 1, 1 },
1381 FR30_INSN_MOV2PS, "mov2ps", "mov",
6a1254af 1382 { { MNEM, ' ', OP (RI), ',', OP (PS), 0 } },
7a0737c8
DB		 1383 { 16, 16, 0xfff0 }, 0x710,
1384 (PTR) 0,
1385 { 0, 0, { 0 } }
1386 },
1387/* jmp @$Ri */
1388 {
1389 { 1, 1, 1, 1 },
1390 FR30_INSN_JMP, "jmp", "jmp",
1391 { { MNEM, ' ', '@', OP (RI), 0 } },
1392 { 16, 16, 0xfff0 }, 0x9700,
1393 (PTR) 0,
1394 { 0, 0, { 0 } }
1395 },
6a1254af
DB		 1396/* jmp:D @$Ri */
1397 {
1398 { 1, 1, 1, 1 },
1399 FR30_INSN_JMPD, "jmpd", "jmp:D",
1400 { { MNEM, ' ', '@', OP (RI), 0 } },
1401 { 16, 16, 0xfff0 }, 0x9f00,
1402 (PTR) 0,
1403 { 0, 0, { 0 } }
1404 },
7a0737c8
DB		 1405/* call $label12 */
1406 {
1407 { 1, 1, 1, 1 },
1408 FR30_INSN_CALL, "call", "call",
1409 { { MNEM, ' ', OP (LABEL12), 0 } },
1410 { 16, 16, 0xf400 }, 0xd000,
1411 (PTR) 0,
1412 { 0, 0, { 0 } }
1413 },
6a1254af
DB		 1414/* call:D $label12 */
1415 {
1416 { 1, 1, 1, 1 },
1417 FR30_INSN_CALLD, "calld", "call:D",
1418 { { MNEM, ' ', OP (LABEL12), 0 } },
1419 { 16, 16, 0xf400 }, 0xd400,
1420 (PTR) 0,
1421 { 0, 0, { 0 } }
1422 },
7a0737c8
DB		 1423/* call @$Ri */
1424 {
1425 { 1, 1, 1, 1 },
1426 FR30_INSN_CALLR, "callr", "call",
1427 { { MNEM, ' ', '@', OP (RI), 0 } },
1428 { 16, 16, 0xfff0 }, 0x9710,
1429 (PTR) 0,
1430 { 0, 0, { 0 } }
1431 },
6a1254af
DB		 1432/* call:D @$Ri */
1433 {
1434 { 1, 1, 1, 1 },
1435 FR30_INSN_CALLRD, "callrd", "call:D",
1436 { { MNEM, ' ', '@', OP (RI), 0 } },
1437 { 16, 16, 0xfff0 }, 0x9f10,
1438 (PTR) 0,
1439 { 0, 0, { 0 } }
1440 },
7a0737c8
DB		 1441/* ret */
1442 {
1443 { 1, 1, 1, 1 },
1444 FR30_INSN_RET, "ret", "ret",
1445 { { MNEM, 0 } },
1446 { 16, 16, 0xffff }, 0x9720,
1447 (PTR) 0,
1448 { 0, 0, { 0 } }
1449 },
6a1254af
DB		 1450/* ret:D */
1451 {
1452 { 1, 1, 1, 1 },
1453 FR30_INSN_RETD, "retd", "ret:D",
1454 { { MNEM, 0 } },
1455 { 16, 16, 0xffff }, 0x9f20,
1456 (PTR) 0,
1457 { 0, 0, { 0 } }
1458 },
7a0737c8
DB		 1459/* int $u8 */
1460 {
1461 { 1, 1, 1, 1 },
1462 FR30_INSN_INT, "int", "int",
1463 { { MNEM, ' ', OP (U8), 0 } },
1464 { 16, 16, 0xff00 }, 0x1f00,
1465 (PTR) 0,
1466 { 0, 0, { 0 } }
1467 },
6a1254af 1468/* inte */
7a0737c8
DB		 1469 {
1470 { 1, 1, 1, 1 },
6a1254af 1471 FR30_INSN_INTE, "inte", "inte",
7a0737c8
DB		 1472 { { MNEM, 0 } },
1473 { 16, 16, 0xffff }, 0x9f30,
1474 (PTR) 0,
1475 { 0, 0, { 0 } }
1476 },
1477/* reti */
1478 {
1479 { 1, 1, 1, 1 },
1480 FR30_INSN_RETI, "reti", "reti",
1481 { { MNEM, 0 } },
1482 { 16, 16, 0xffff }, 0x9730,
1483 (PTR) 0,
1484 { 0, 0, { 0 } }
1485 },
6a1254af 1486/* bra $label9 */
7a0737c8
DB		 1487 {
1488 { 1, 1, 1, 1 },
6a1254af 1489 FR30_INSN_BRA, "bra", "bra",
7a0737c8
DB		 1490 { { MNEM, ' ', OP (LABEL9), 0 } },
1491 { 16, 16, 0xff00 }, 0xe000,
1492 (PTR) 0,
1493 { 0, 0, { 0 } }
1494 },
6a1254af 1495/* bno $label9 */
7a0737c8
DB		 1496 {
1497 { 1, 1, 1, 1 },
6a1254af 1498 FR30_INSN_BNO, "bno", "bno",
7a0737c8
DB		 1499 { { MNEM, ' ', OP (LABEL9), 0 } },
1500 { 16, 16, 0xff00 }, 0xe100,
1501 (PTR) 0,
1502 { 0, 0, { 0 } }
1503 },
6a1254af 1504/* beq $label9 */
7a0737c8
DB		 1505 {
1506 { 1, 1, 1, 1 },
6a1254af 1507 FR30_INSN_BEQ, "beq", "beq",
7a0737c8
DB		 1508 { { MNEM, ' ', OP (LABEL9), 0 } },
1509 { 16, 16, 0xff00 }, 0xe200,
1510 (PTR) 0,
1511 { 0, 0, { 0 } }
1512 },
6a1254af 1513/* bne $label9 */
7a0737c8
DB		 1514 {
1515 { 1, 1, 1, 1 },
6a1254af 1516 FR30_INSN_BNE, "bne", "bne",
7a0737c8
DB		 1517 { { MNEM, ' ', OP (LABEL9), 0 } },
1518 { 16, 16, 0xff00 }, 0xe300,
1519 (PTR) 0,
1520 { 0, 0, { 0 } }
1521 },
6a1254af 1522/* bc $label9 */
7a0737c8
DB		 1523 {
1524 { 1, 1, 1, 1 },
6a1254af 1525 FR30_INSN_BC, "bc", "bc",
7a0737c8
DB		 1526 { { MNEM, ' ', OP (LABEL9), 0 } },
1527 { 16, 16, 0xff00 }, 0xe400,
1528 (PTR) 0,
1529 { 0, 0, { 0 } }
1530 },
6a1254af 1531/* bnc $label9 */
7a0737c8
DB		 1532 {
1533 { 1, 1, 1, 1 },
6a1254af 1534 FR30_INSN_BNC, "bnc", "bnc",
7a0737c8
DB		 1535 { { MNEM, ' ', OP (LABEL9), 0 } },
1536 { 16, 16, 0xff00 }, 0xe500,
1537 (PTR) 0,
1538 { 0, 0, { 0 } }
1539 },
6a1254af 1540/* bn $label9 */
7a0737c8
DB		 1541 {
1542 { 1, 1, 1, 1 },
6a1254af 1543 FR30_INSN_BN, "bn", "bn",
7a0737c8
DB		 1544 { { MNEM, ' ', OP (LABEL9), 0 } },
1545 { 16, 16, 0xff00 }, 0xe600,
1546 (PTR) 0,
1547 { 0, 0, { 0 } }
1548 },
6a1254af 1549/* bp $label9 */
7a0737c8
DB		 1550 {
1551 { 1, 1, 1, 1 },
6a1254af 1552 FR30_INSN_BP, "bp", "bp",
7a0737c8
DB		 1553 { { MNEM, ' ', OP (LABEL9), 0 } },
1554 { 16, 16, 0xff00 }, 0xe700,
1555 (PTR) 0,
1556 { 0, 0, { 0 } }
1557 },
6a1254af 1558/* bv $label9 */
7a0737c8
DB		 1559 {
1560 { 1, 1, 1, 1 },
6a1254af 1561 FR30_INSN_BV, "bv", "bv",
7a0737c8
DB		 1562 { { MNEM, ' ', OP (LABEL9), 0 } },
1563 { 16, 16, 0xff00 }, 0xe800,
1564 (PTR) 0,
1565 { 0, 0, { 0 } }
1566 },
6a1254af 1567/* bnv $label9 */
7a0737c8
DB		 1568 {
1569 { 1, 1, 1, 1 },
6a1254af 1570 FR30_INSN_BNV, "bnv", "bnv",
7a0737c8
DB		 1571 { { MNEM, ' ', OP (LABEL9), 0 } },
1572 { 16, 16, 0xff00 }, 0xe900,
1573 (PTR) 0,
1574 { 0, 0, { 0 } }
1575 },
6a1254af 1576/* blt $label9 */
7a0737c8
DB		 1577 {
1578 { 1, 1, 1, 1 },
6a1254af 1579 FR30_INSN_BLT, "blt", "blt",
7a0737c8
DB		 1580 { { MNEM, ' ', OP (LABEL9), 0 } },
1581 { 16, 16, 0xff00 }, 0xea00,
1582 (PTR) 0,
1583 { 0, 0, { 0 } }
1584 },
6a1254af 1585/* bge $label9 */
7a0737c8
DB		 1586 {
1587 { 1, 1, 1, 1 },
6a1254af 1588 FR30_INSN_BGE, "bge", "bge",
7a0737c8
DB		 1589 { { MNEM, ' ', OP (LABEL9), 0 } },
1590 { 16, 16, 0xff00 }, 0xeb00,
1591 (PTR) 0,
1592 { 0, 0, { 0 } }
1593 },
6a1254af 1594/* ble $label9 */
7a0737c8
DB		 1595 {
1596 { 1, 1, 1, 1 },
6a1254af 1597 FR30_INSN_BLE, "ble", "ble",
7a0737c8
DB		 1598 { { MNEM, ' ', OP (LABEL9), 0 } },
1599 { 16, 16, 0xff00 }, 0xec00,
1600 (PTR) 0,
1601 { 0, 0, { 0 } }
1602 },
6a1254af 1603/* bgt $label9 */
7a0737c8
DB		 1604 {
1605 { 1, 1, 1, 1 },
6a1254af 1606 FR30_INSN_BGT, "bgt", "bgt",
7a0737c8
DB		 1607 { { MNEM, ' ', OP (LABEL9), 0 } },
1608 { 16, 16, 0xff00 }, 0xed00,
1609 (PTR) 0,
1610 { 0, 0, { 0 } }
1611 },
6a1254af 1612/* bls $label9 */
7a0737c8
DB		 1613 {
1614 { 1, 1, 1, 1 },
6a1254af 1615 FR30_INSN_BLS, "bls", "bls",
7a0737c8
DB		 1616 { { MNEM, ' ', OP (LABEL9), 0 } },
1617 { 16, 16, 0xff00 }, 0xee00,
1618 (PTR) 0,
1619 { 0, 0, { 0 } }
1620 },
6a1254af 1621/* bhi $label9 */
7a0737c8
DB		 1622 {
1623 { 1, 1, 1, 1 },
6a1254af 1624 FR30_INSN_BHI, "bhi", "bhi",
7a0737c8
DB		 1625 { { MNEM, ' ', OP (LABEL9), 0 } },
1626 { 16, 16, 0xff00 }, 0xef00,
1627 (PTR) 0,
1628 { 0, 0, { 0 } }
1629 },
6a1254af
DB		 1630/* bra:D $label9 */
1631 {
1632 { 1, 1, 1, 1 },
1633 FR30_INSN_BRAD, "brad", "bra:D",
1634 { { MNEM, ' ', OP (LABEL9), 0 } },
1635 { 16, 16, 0xff00 }, 0xf000,
1636 (PTR) 0,
1637 { 0, 0, { 0 } }
1638 },
1639/* bno:D $label9 */
1640 {
1641 { 1, 1, 1, 1 },
1642 FR30_INSN_BNOD, "bnod", "bno:D",
1643 { { MNEM, ' ', OP (LABEL9), 0 } },
1644 { 16, 16, 0xff00 }, 0xf100,
1645 (PTR) 0,
1646 { 0, 0, { 0 } }
1647 },
1648/* beq:D $label9 */
1649 {
1650 { 1, 1, 1, 1 },
1651 FR30_INSN_BEQD, "beqd", "beq:D",
1652 { { MNEM, ' ', OP (LABEL9), 0 } },
1653 { 16, 16, 0xff00 }, 0xf200,
1654 (PTR) 0,
1655 { 0, 0, { 0 } }
1656 },
1657/* bne:D $label9 */
1658 {
1659 { 1, 1, 1, 1 },
1660 FR30_INSN_BNED, "bned", "bne:D",
1661 { { MNEM, ' ', OP (LABEL9), 0 } },
1662 { 16, 16, 0xff00 }, 0xf300,
1663 (PTR) 0,
1664 { 0, 0, { 0 } }
1665 },
1666/* bc:D $label9 */
1667 {
1668 { 1, 1, 1, 1 },
1669 FR30_INSN_BCD, "bcd", "bc:D",
1670 { { MNEM, ' ', OP (LABEL9), 0 } },
1671 { 16, 16, 0xff00 }, 0xf400,
1672 (PTR) 0,
1673 { 0, 0, { 0 } }
1674 },
1675/* bnc:D $label9 */
1676 {
1677 { 1, 1, 1, 1 },
1678 FR30_INSN_BNCD, "bncd", "bnc:D",
1679 { { MNEM, ' ', OP (LABEL9), 0 } },
1680 { 16, 16, 0xff00 }, 0xf500,
1681 (PTR) 0,
1682 { 0, 0, { 0 } }
1683 },
1684/* bn:D $label9 */
1685 {
1686 { 1, 1, 1, 1 },
1687 FR30_INSN_BND, "bnd", "bn:D",
1688 { { MNEM, ' ', OP (LABEL9), 0 } },
1689 { 16, 16, 0xff00 }, 0xf600,
1690 (PTR) 0,
1691 { 0, 0, { 0 } }
1692 },
1693/* bp:D $label9 */
1694 {
1695 { 1, 1, 1, 1 },
1696 FR30_INSN_BPD, "bpd", "bp:D",
1697 { { MNEM, ' ', OP (LABEL9), 0 } },
1698 { 16, 16, 0xff00 }, 0xf700,
1699 (PTR) 0,
1700 { 0, 0, { 0 } }
1701 },
1702/* bv:D $label9 */
1703 {
1704 { 1, 1, 1, 1 },
1705 FR30_INSN_BVD, "bvd", "bv:D",
1706 { { MNEM, ' ', OP (LABEL9), 0 } },
1707 { 16, 16, 0xff00 }, 0xf800,
1708 (PTR) 0,
1709 { 0, 0, { 0 } }
1710 },
1711/* bnv:D $label9 */
1712 {
1713 { 1, 1, 1, 1 },
1714 FR30_INSN_BNVD, "bnvd", "bnv:D",
1715 { { MNEM, ' ', OP (LABEL9), 0 } },
1716 { 16, 16, 0xff00 }, 0xf900,
1717 (PTR) 0,
1718 { 0, 0, { 0 } }
1719 },
1720/* blt:D $label9 */
1721 {
1722 { 1, 1, 1, 1 },
1723 FR30_INSN_BLTD, "bltd", "blt:D",
1724 { { MNEM, ' ', OP (LABEL9), 0 } },
1725 { 16, 16, 0xff00 }, 0xfa00,
1726 (PTR) 0,
1727 { 0, 0, { 0 } }
1728 },
1729/* bge:D $label9 */
1730 {
1731 { 1, 1, 1, 1 },
1732 FR30_INSN_BGED, "bged", "bge:D",
1733 { { MNEM, ' ', OP (LABEL9), 0 } },
1734 { 16, 16, 0xff00 }, 0xfb00,
1735 (PTR) 0,
1736 { 0, 0, { 0 } }
1737 },
1738/* ble:D $label9 */
1739 {
1740 { 1, 1, 1, 1 },
1741 FR30_INSN_BLED, "bled", "ble:D",
1742 { { MNEM, ' ', OP (LABEL9), 0 } },
1743 { 16, 16, 0xff00 }, 0xfc00,
1744 (PTR) 0,
1745 { 0, 0, { 0 } }
1746 },
1747/* bgt:D $label9 */
1748 {
1749 { 1, 1, 1, 1 },
1750 FR30_INSN_BGTD, "bgtd", "bgt:D",
1751 { { MNEM, ' ', OP (LABEL9), 0 } },
1752 { 16, 16, 0xff00 }, 0xfd00,
1753 (PTR) 0,
1754 { 0, 0, { 0 } }
1755 },
1756/* bls:D $label9 */
1757 {
1758 { 1, 1, 1, 1 },
1759 FR30_INSN_BLSD, "blsd", "bls:D",
1760 { { MNEM, ' ', OP (LABEL9), 0 } },
1761 { 16, 16, 0xff00 }, 0xfe00,
1762 (PTR) 0,
1763 { 0, 0, { 0 } }
1764 },
1765/* bhi:D $label9 */
1766 {
1767 { 1, 1, 1, 1 },
1768 FR30_INSN_BHID, "bhid", "bhi:D",
1769 { { MNEM, ' ', OP (LABEL9), 0 } },
1770 { 16, 16, 0xff00 }, 0xff00,
1771 (PTR) 0,
1772 { 0, 0, { 0 } }
1773 },
1774/* dmov @$dir10,$R13 */
7a0737c8
DB		 1775 {
1776 { 1, 1, 1, 1 },
1777 FR30_INSN_DMOV2R13, "dmov2r13", "dmov",
6a1254af 1778 { { MNEM, ' ', '@', OP (DIR10), ',', OP (R13), 0 } },
7a0737c8
DB		 1779 { 16, 16, 0xff00 }, 0x800,
1780 (PTR) 0,
1781 { 0, 0, { 0 } }
1782 },
6a1254af 1783/* dmovh @$dir9,$R13 */
7a0737c8
DB		 1784 {
1785 { 1, 1, 1, 1 },
1786 FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh",
6a1254af 1787 { { MNEM, ' ', '@', OP (DIR9), ',', OP (R13), 0 } },
7a0737c8
DB		 1788 { 16, 16, 0xff00 }, 0x900,
1789 (PTR) 0,
1790 { 0, 0, { 0 } }
1791 },
6a1254af 1792/* dmovb @$dir8,$R13 */
7a0737c8
DB		 1793 {
1794 { 1, 1, 1, 1 },
1795 FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb",
6a1254af 1796 { { MNEM, ' ', '@', OP (DIR8), ',', OP (R13), 0 } },
7a0737c8
DB		 1797 { 16, 16, 0xff00 }, 0xa00,
1798 (PTR) 0,
1799 { 0, 0, { 0 } }
1800 },
6a1254af 1801/* dmov $R13,@$dir10 */
7a0737c8
DB		 1802 {
1803 { 1, 1, 1, 1 },
1804 FR30_INSN_DMOVR13, "dmovr13", "dmov",
6a1254af 1805 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR10), 0 } },
7a0737c8
DB		 1806 { 16, 16, 0xff00 }, 0x1800,
1807 (PTR) 0,
1808 { 0, 0, { 0 } }
1809 },
6a1254af 1810/* dmovh $R13,@$dir9 */
7a0737c8
DB		 1811 {
1812 { 1, 1, 1, 1 },
1813 FR30_INSN_DMOVR13H, "dmovr13h", "dmovh",
6a1254af 1814 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR9), 0 } },
7a0737c8
DB		 1815 { 16, 16, 0xff00 }, 0x1900,
1816 (PTR) 0,
1817 { 0, 0, { 0 } }
1818 },
6a1254af 1819/* dmovb $R13,@$dir8 */
7a0737c8
DB		 1820 {
1821 { 1, 1, 1, 1 },
1822 FR30_INSN_DMOVR13B, "dmovr13b", "dmovb",
6a1254af 1823 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR8), 0 } },
7a0737c8
DB		 1824 { 16, 16, 0xff00 }, 0x1a00,
1825 (PTR) 0,
1826 { 0, 0, { 0 } }
1827 },
6a1254af 1828/* dmov @$dir10,@$R13+ */
7a0737c8
DB		 1829 {
1830 { 1, 1, 1, 1 },
1831 FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov",
6a1254af 1832 { { MNEM, ' ', '@', OP (DIR10), ',', '@', OP (R13), '+', 0 } },
7a0737c8
DB		 1833 { 16, 16, 0xff00 }, 0xc00,
1834 (PTR) 0,
1835 { 0, 0, { 0 } }
1836 },
6a1254af 1837/* dmovh @$dir9,@$R13+ */
7a0737c8
DB		 1838 {
1839 { 1, 1, 1, 1 },
1840 FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh",
6a1254af 1841 { { MNEM, ' ', '@', OP (DIR9), ',', '@', OP (R13), '+', 0 } },
7a0737c8
DB		 1842 { 16, 16, 0xff00 }, 0xd00,
1843 (PTR) 0,
1844 { 0, 0, { 0 } }
1845 },
6a1254af 1846/* dmovb @$dir8,@$R13+ */
7a0737c8
DB		 1847 {
1848 { 1, 1, 1, 1 },
1849 FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb",
6a1254af 1850 { { MNEM, ' ', '@', OP (DIR8), ',', '@', OP (R13), '+', 0 } },
7a0737c8
DB		 1851 { 16, 16, 0xff00 }, 0xe00,
1852 (PTR) 0,
1853 { 0, 0, { 0 } }
1854 },
6a1254af 1855/* dmov @$R13+,@$dir10 */
7a0737c8
DB		 1856 {
1857 { 1, 1, 1, 1 },
6a1254af
DB		 1858 FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov",
1859 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR10), 0 } },
7a0737c8
DB		 1860 { 16, 16, 0xff00 }, 0x1c00,
1861 (PTR) 0,
1862 { 0, 0, { 0 } }
1863 },
6a1254af 1864/* dmovh @$R13+,@$dir9 */
7a0737c8
DB		 1865 {
1866 { 1, 1, 1, 1 },
6a1254af
DB		 1867 FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh",
1868 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR9), 0 } },
7a0737c8
DB		 1869 { 16, 16, 0xff00 }, 0x1d00,
1870 (PTR) 0,
1871 { 0, 0, { 0 } }
1872 },
6a1254af 1873/* dmovb @$R13+,@$dir8 */
7a0737c8
DB		 1874 {
1875 { 1, 1, 1, 1 },
6a1254af
DB		 1876 FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb",
1877 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR8), 0 } },
7a0737c8
DB		 1878 { 16, 16, 0xff00 }, 0x1e00,
1879 (PTR) 0,
1880 { 0, 0, { 0 } }
1881 },
cdb89f92 1882/* dmov @$dir10,@-$R15 */
7a0737c8
DB		 1883 {
1884 { 1, 1, 1, 1 },
1885 FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov",
cdb89f92 1886 { { MNEM, ' ', '@', OP (DIR10), ',', '@', '-', OP (R15), 0 } },
7a0737c8
DB		 1887 { 16, 16, 0xff00 }, 0xb00,
1888 (PTR) 0,
1889 { 0, 0, { 0 } }
1890 },
6a1254af 1891/* dmov @$R15+,@$dir10 */
7a0737c8
DB		 1892 {
1893 { 1, 1, 1, 1 },
6a1254af
DB		 1894 FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov",
1895 { { MNEM, ' ', '@', OP (R15), '+', ',', '@', OP (DIR10), 0 } },
7a0737c8
DB		 1896 { 16, 16, 0xff00 }, 0x1b00,
1897 (PTR) 0,
1898 { 0, 0, { 0 } }
1899 },
1900/* ldres @$Ri+,$u4 */
1901 {
1902 { 1, 1, 1, 1 },
1903 FR30_INSN_LDRES, "ldres", "ldres",
1904 { { MNEM, ' ', '@', OP (RI), '+', ',', OP (U4), 0 } },
1905 { 16, 16, 0xff00 }, 0xbc00,
1906 (PTR) 0,
1907 { 0, 0, { 0 } }
1908 },
6a1254af 1909/* stres $u4,@$Ri+ */
7a0737c8
DB		 1910 {
1911 { 1, 1, 1, 1 },
6a1254af 1912 FR30_INSN_STRES, "stres", "stres",
7a0737c8
DB		 1913 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), '+', 0 } },
1914 { 16, 16, 0xff00 }, 0xbd00,
1915 (PTR) 0,
1916 { 0, 0, { 0 } }
1917 },
1918/* nop */
1919 {
1920 { 1, 1, 1, 1 },
1921 FR30_INSN_NOP, "nop", "nop",
1922 { { MNEM, 0 } },
1923 { 16, 16, 0xffff }, 0x9fa0,
1924 (PTR) 0,
1925 { 0, 0, { 0 } }
1926 },
1927/* andccr $u8 */
1928 {
1929 { 1, 1, 1, 1 },
1930 FR30_INSN_ANDCCR, "andccr", "andccr",
1931 { { MNEM, ' ', OP (U8), 0 } },
1932 { 16, 16, 0xff00 }, 0x8300,
1933 (PTR) 0,
1934 { 0, 0, { 0 } }
1935 },
1936/* orccr $u8 */
1937 {
1938 { 1, 1, 1, 1 },
1939 FR30_INSN_ORCCR, "orccr", "orccr",
1940 { { MNEM, ' ', OP (U8), 0 } },
1941 { 16, 16, 0xff00 }, 0x9300,
1942 (PTR) 0,
1943 { 0, 0, { 0 } }
1944 },
1945/* stilm $u8 */
1946 {
1947 { 1, 1, 1, 1 },
1948 FR30_INSN_STILM, "stilm", "stilm",
1949 { { MNEM, ' ', OP (U8), 0 } },
1950 { 16, 16, 0xff00 }, 0x8700,
1951 (PTR) 0,
1952 { 0, 0, { 0 } }
1953 },
1954/* addsp $s10 */
1955 {
1956 { 1, 1, 1, 1 },
1957 FR30_INSN_ADDSP, "addsp", "addsp",
1958 { { MNEM, ' ', OP (S10), 0 } },
1959 { 16, 16, 0xff00 }, 0xa300,
1960 (PTR) 0,
1961 { 0, 0, { 0 } }
1962 },
1963/* extsb $Ri */
1964 {
1965 { 1, 1, 1, 1 },
1966 FR30_INSN_EXTSB, "extsb", "extsb",
1967 { { MNEM, ' ', OP (RI), 0 } },
1968 { 16, 16, 0xfff0 }, 0x9780,
1969 (PTR) 0,
1970 { 0, 0, { 0 } }
1971 },
1972/* extub $Ri */
1973 {
1974 { 1, 1, 1, 1 },
1975 FR30_INSN_EXTUB, "extub", "extub",
1976 { { MNEM, ' ', OP (RI), 0 } },
1977 { 16, 16, 0xfff0 }, 0x9790,
1978 (PTR) 0,
1979 { 0, 0, { 0 } }
1980 },
1981/* extsh $Ri */
1982 {
1983 { 1, 1, 1, 1 },
1984 FR30_INSN_EXTSH, "extsh", "extsh",
1985 { { MNEM, ' ', OP (RI), 0 } },
1986 { 16, 16, 0xfff0 }, 0x97a0,
1987 (PTR) 0,
1988 { 0, 0, { 0 } }
1989 },
1990/* extuh $Ri */
1991 {
1992 { 1, 1, 1, 1 },
1993 FR30_INSN_EXTUH, "extuh", "extuh",
1994 { { MNEM, ' ', OP (RI), 0 } },
1995 { 16, 16, 0xfff0 }, 0x97b0,
1996 (PTR) 0,
1997 { 0, 0, { 0 } }
1998 },
1999/* enter $u10 */
2000 {
2001 { 1, 1, 1, 1 },
2002 FR30_INSN_ENTER, "enter", "enter",
2003 { { MNEM, ' ', OP (U10), 0 } },
2004 { 16, 16, 0xff00 }, 0xf00,
2005 (PTR) 0,
2006 { 0, 0, { 0 } }
2007 },
2008/* leave */
2009 {
2010 { 1, 1, 1, 1 },
2011 FR30_INSN_LEAVE, "leave", "leave",
2012 { { MNEM, 0 } },
2013 { 16, 16, 0xffff }, 0x9f90,
2014 (PTR) 0,
2015 { 0, 0, { 0 } }
2016 },
2017/* xchb @$Rj,$Ri */
2018 {
2019 { 1, 1, 1, 1 },
2020 FR30_INSN_XCHB, "xchb", "xchb",
2021 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
2022 { 16, 16, 0xff00 }, 0x8a00,
2023 (PTR) 0,
a86481d3
DB		 2024 { 0, 0, { 0 } }
2025 },
2026};
2027
2028#undef A
2029#undef MNEM
2030#undef OP
2031
2032static const CGEN_INSN_TABLE insn_table =
2033{
2034 & fr30_cgen_insn_table_entries[0],
2035 sizeof (CGEN_INSN),
2036 MAX_INSNS,
2037 NULL
2038};
2039
2040/* Each non-simple macro entry points to an array of expansion possibilities. */
2041
2042#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
2043#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
2044#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2045
2046/* The macro instruction table. */
2047
2048static const CGEN_INSN macro_insn_table_entries[] =
2049{
911701b7
DE		 2050/* ldi32 $i32,$Ri */
2051 {
2052 { 1, 1, 1, 1 },
2053 -1, "ldi32m", "ldi32",
2054 { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
2055 { 16, 48, 0xfff0 }, 0x9f80,
2056 (PTR) 0,
2057 { 0, 0|A(ALIAS), { 0 } }
2058 },
a86481d3
DB		 2059};
2060
2061#undef A
2062#undef MNEM
2063#undef OP
2064
2065static const CGEN_INSN_TABLE macro_insn_table =
2066{
2067 & macro_insn_table_entries[0],
2068 sizeof (CGEN_INSN),
2069 (sizeof (macro_insn_table_entries) /
2070 sizeof (macro_insn_table_entries[0])),
2071 NULL
2072};
2073
2074static void
2075init_tables ()
2076{
2077}
2078
2079/* Return non-zero if INSN is to be added to the hash table.
2080 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
2081
2082static int
2083asm_hash_insn_p (insn)
2084 const CGEN_INSN * insn;
2085{
2086 return CGEN_ASM_HASH_P (insn);
2087}
2088
2089static int
2090dis_hash_insn_p (insn)
2091 const CGEN_INSN * insn;
2092{
2093 /* If building the hash table and the NO-DIS attribute is present,
2094 ignore. */
2095 if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
2096 return 0;
2097 return CGEN_DIS_HASH_P (insn);
2098}
2099
2100/* The result is the hash value of the insn.
2101 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
2102
2103static unsigned int
2104asm_hash_insn (mnem)
2105 const char * mnem;
2106{
2107 return CGEN_ASM_HASH (mnem);
2108}
2109
2110/* BUF is a pointer to the insn's bytes in target order.
2111 VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
2112 host order. */
2113
2114static unsigned int
2115dis_hash_insn (buf, value)
2116 const char * buf;
95b03313 2117 CGEN_INSN_INT value;
a86481d3
DB		 2118{
2119 return CGEN_DIS_HASH (buf, value);
2120}
2121
2122/* Initialize an opcode table and return a descriptor.
2123 It's much like opening a file, and must be the first function called. */
2124
2125CGEN_OPCODE_DESC
2126fr30_cgen_opcode_open (mach, endian)
2127 int mach;
2128 enum cgen_endian endian;
2129{
2130 CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE));
2131 static int init_p;
2132
2133 if (! init_p)
2134 {
2135 init_tables ();
2136 init_p = 1;
2137 }
2138
2139 memset (table, 0, sizeof (*table));
2140
2141 CGEN_OPCODE_MACH (table) = mach;
2142 CGEN_OPCODE_ENDIAN (table) = endian;
2143 /* FIXME: for the sparc case we can determine insn-endianness statically.
2144 The worry here is where both data and insn endian can be independently
2145 chosen, in which case this function will need another argument.
2146 Actually, will want to allow for more arguments in the future anyway. */
2147 CGEN_OPCODE_INSN_ENDIAN (table) = endian;
2148
2149 CGEN_OPCODE_HW_LIST (table) = & fr30_cgen_hw_entries[0];
2150
2151 CGEN_OPCODE_OPERAND_TABLE (table) = & fr30_cgen_operand_table[0];
2152
2153 * CGEN_OPCODE_INSN_TABLE (table) = insn_table;
2154
2155 * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table;
2156
2157 CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p;
2158 CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn;
2159 CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE;
2160
2161 CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p;
2162 CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn;
2163 CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE;
2164
2165 return (CGEN_OPCODE_DESC) table;
2166}
2167
2168/* Close an opcode table. */
2169
2170void
2171fr30_cgen_opcode_close (desc)
2172 CGEN_OPCODE_DESC desc;
2173{
2174 free (desc);
2175}
2176
2177/* Getting values from cgen_fields is handled by a collection of functions.
2178 They are distinguished by the type of the VALUE argument they return.
2179 TODO: floating point, inlining support, remove cases where result type
2180 not appropriate. */
2181
2182int
2183fr30_cgen_get_int_operand (opindex, fields)
2184 int opindex;
2185 const CGEN_FIELDS * fields;
2186{
2187 int value;
2188
2189 switch (opindex)
2190 {
2191 case FR30_OPERAND_RI :
2192 value = fields->f_Ri;
2193 break;
2194 case FR30_OPERAND_RJ :
2195 value = fields->f_Rj;
2196 break;
7a0737c8
DB		 2197 case FR30_OPERAND_RS1 :
2198 value = fields->f_Rs1;
2199 break;
2200 case FR30_OPERAND_RS2 :
2201 value = fields->f_Rs2;
2202 break;
6a1254af
DB		 2203 case FR30_OPERAND_R13 :
2204 value = fields->f_nil;
2205 break;
2206 case FR30_OPERAND_R14 :
2207 value = fields->f_nil;
2208 break;
2209 case FR30_OPERAND_R15 :
2210 value = fields->f_nil;
2211 break;
2212 case FR30_OPERAND_PS :
2213 value = fields->f_nil;
2214 break;
7a0737c8
DB		 2215 case FR30_OPERAND_U4 :
2216 value = fields->f_u4;
2217 break;
2218 case FR30_OPERAND_M4 :
2219 value = fields->f_m4;
2220 break;
6a1254af
DB		 2221 case FR30_OPERAND_U8 :
2222 value = fields->f_u8;
2223 break;
7a0737c8
DB		 2224 case FR30_OPERAND_I8 :
2225 value = fields->f_i8;
2226 break;
6a1254af
DB		 2227 case FR30_OPERAND_UDISP6 :
2228 value = fields->f_udisp6;
7a0737c8 2229 break;
6a1254af
DB		 2230 case FR30_OPERAND_DISP8 :
2231 value = fields->f_disp8;
2232 break;
2233 case FR30_OPERAND_DISP9 :
2234 value = fields->f_disp9;
2235 break;
2236 case FR30_OPERAND_DISP10 :
2237 value = fields->f_disp10;
7a0737c8
DB		 2238 break;
2239 case FR30_OPERAND_S10 :
2240 value = fields->f_s10;
2241 break;
2242 case FR30_OPERAND_U10 :
2243 value = fields->f_u10;
2244 break;
95b03313
DE		 2245 case FR30_OPERAND_I32 :
2246 value = fields->f_i32;
2247 break;
7a0737c8
DB		 2248 case FR30_OPERAND_DIR8 :
2249 value = fields->f_dir8;
2250 break;
2251 case FR30_OPERAND_DIR9 :
2252 value = fields->f_dir9;
2253 break;
2254 case FR30_OPERAND_DIR10 :
2255 value = fields->f_dir10;
2256 break;
2257 case FR30_OPERAND_LABEL9 :
6a1254af 2258 value = fields->f_rel9;
7a0737c8
DB		 2259 break;
2260 case FR30_OPERAND_LABEL12 :
6a1254af 2261 value = fields->f_rel12;
7a0737c8
DB		 2262 break;
2263 case FR30_OPERAND_CC :
2264 value = fields->f_cc;
2265 break;
a86481d3
DB		 2266
2267 default :
2268 /* xgettext:c-format */
2269 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
2270 opindex);
2271 abort ();
2272 }
2273
2274 return value;
2275}
2276
2277bfd_vma
2278fr30_cgen_get_vma_operand (opindex, fields)
2279 int opindex;
2280 const CGEN_FIELDS * fields;
2281{
2282 bfd_vma value;
2283
2284 switch (opindex)
2285 {
2286 case FR30_OPERAND_RI :
2287 value = fields->f_Ri;
2288 break;
2289 case FR30_OPERAND_RJ :
2290 value = fields->f_Rj;
2291 break;
7a0737c8
DB		 2292 case FR30_OPERAND_RS1 :
2293 value = fields->f_Rs1;
2294 break;
2295 case FR30_OPERAND_RS2 :
2296 value = fields->f_Rs2;
2297 break;
6a1254af
DB		 2298 case FR30_OPERAND_R13 :
2299 value = fields->f_nil;
2300 break;
2301 case FR30_OPERAND_R14 :
2302 value = fields->f_nil;
2303 break;
2304 case FR30_OPERAND_R15 :
2305 value = fields->f_nil;
2306 break;
2307 case FR30_OPERAND_PS :
2308 value = fields->f_nil;
2309 break;
7a0737c8
DB		 2310 case FR30_OPERAND_U4 :
2311 value = fields->f_u4;
2312 break;
2313 case FR30_OPERAND_M4 :
2314 value = fields->f_m4;
2315 break;
6a1254af
DB		 2316 case FR30_OPERAND_U8 :
2317 value = fields->f_u8;
2318 break;
7a0737c8
DB		 2319 case FR30_OPERAND_I8 :
2320 value = fields->f_i8;
2321 break;
6a1254af
DB		 2322 case FR30_OPERAND_UDISP6 :
2323 value = fields->f_udisp6;
7a0737c8 2324 break;
6a1254af
DB		 2325 case FR30_OPERAND_DISP8 :
2326 value = fields->f_disp8;
2327 break;
2328 case FR30_OPERAND_DISP9 :
2329 value = fields->f_disp9;
2330 break;
2331 case FR30_OPERAND_DISP10 :
2332 value = fields->f_disp10;
7a0737c8
DB		 2333 break;
2334 case FR30_OPERAND_S10 :
2335 value = fields->f_s10;
2336 break;
2337 case FR30_OPERAND_U10 :
2338 value = fields->f_u10;
2339 break;
95b03313
DE		 2340 case FR30_OPERAND_I32 :
2341 value = fields->f_i32;
2342 break;
7a0737c8
DB		 2343 case FR30_OPERAND_DIR8 :
2344 value = fields->f_dir8;
2345 break;
2346 case FR30_OPERAND_DIR9 :
2347 value = fields->f_dir9;
2348 break;
2349 case FR30_OPERAND_DIR10 :
2350 value = fields->f_dir10;
2351 break;
2352 case FR30_OPERAND_LABEL9 :
6a1254af 2353 value = fields->f_rel9;
7a0737c8
DB		 2354 break;
2355 case FR30_OPERAND_LABEL12 :
6a1254af 2356 value = fields->f_rel12;
7a0737c8
DB		 2357 break;
2358 case FR30_OPERAND_CC :
2359 value = fields->f_cc;
2360 break;
a86481d3
DB		 2361
2362 default :
2363 /* xgettext:c-format */
2364 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
2365 opindex);
2366 abort ();
2367 }
2368
2369 return value;
2370}
2371
2372/* Stuffing values in cgen_fields is handled by a collection of functions.
2373 They are distinguished by the type of the VALUE argument they accept.
2374 TODO: floating point, inlining support, remove cases where argument type
2375 not appropriate. */
2376
2377void
2378fr30_cgen_set_int_operand (opindex, fields, value)
2379 int opindex;
2380 CGEN_FIELDS * fields;
2381 int value;
2382{
2383 switch (opindex)
2384 {
2385 case FR30_OPERAND_RI :
2386 fields->f_Ri = value;
2387 break;
2388 case FR30_OPERAND_RJ :
2389 fields->f_Rj = value;
2390 break;
7a0737c8
DB		 2391 case FR30_OPERAND_RS1 :
2392 fields->f_Rs1 = value;
2393 break;
2394 case FR30_OPERAND_RS2 :
2395 fields->f_Rs2 = value;
2396 break;
6a1254af
DB		 2397 case FR30_OPERAND_R13 :
2398 fields->f_nil = value;
2399 break;
2400 case FR30_OPERAND_R14 :
2401 fields->f_nil = value;
2402 break;
2403 case FR30_OPERAND_R15 :
2404 fields->f_nil = value;
2405 break;
2406 case FR30_OPERAND_PS :
2407 fields->f_nil = value;
2408 break;
7a0737c8
DB		 2409 case FR30_OPERAND_U4 :
2410 fields->f_u4 = value;
2411 break;
2412 case FR30_OPERAND_M4 :
2413 fields->f_m4 = value;
2414 break;
6a1254af
DB		 2415 case FR30_OPERAND_U8 :
2416 fields->f_u8 = value;
2417 break;
7a0737c8
DB		 2418 case FR30_OPERAND_I8 :
2419 fields->f_i8 = value;
2420 break;
6a1254af
DB		 2421 case FR30_OPERAND_UDISP6 :
2422 fields->f_udisp6 = value;
2423 break;
2424 case FR30_OPERAND_DISP8 :
2425 fields->f_disp8 = value;
7a0737c8 2426 break;
6a1254af
DB		 2427 case FR30_OPERAND_DISP9 :
2428 fields->f_disp9 = value;
2429 break;
2430 case FR30_OPERAND_DISP10 :
2431 fields->f_disp10 = value;
7a0737c8
DB		 2432 break;
2433 case FR30_OPERAND_S10 :
2434 fields->f_s10 = value;
2435 break;
2436 case FR30_OPERAND_U10 :
2437 fields->f_u10 = value;
2438 break;
95b03313
DE		 2439 case FR30_OPERAND_I32 :
2440 fields->f_i32 = value;
2441 break;
7a0737c8
DB		 2442 case FR30_OPERAND_DIR8 :
2443 fields->f_dir8 = value;
2444 break;
2445 case FR30_OPERAND_DIR9 :
2446 fields->f_dir9 = value;
2447 break;
2448 case FR30_OPERAND_DIR10 :
2449 fields->f_dir10 = value;
2450 break;
2451 case FR30_OPERAND_LABEL9 :
6a1254af 2452 fields->f_rel9 = value;
7a0737c8
DB		 2453 break;
2454 case FR30_OPERAND_LABEL12 :
6a1254af 2455 fields->f_rel12 = value;
7a0737c8
DB		 2456 break;
2457 case FR30_OPERAND_CC :
2458 fields->f_cc = value;
2459 break;
a86481d3
DB		 2460
2461 default :
2462 /* xgettext:c-format */
2463 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
2464 opindex);
2465 abort ();
2466 }
2467}
2468
2469void
2470fr30_cgen_set_vma_operand (opindex, fields, value)
2471 int opindex;
2472 CGEN_FIELDS * fields;
2473 bfd_vma value;
2474{
2475 switch (opindex)
2476 {
2477 case FR30_OPERAND_RI :
2478 fields->f_Ri = value;
2479 break;
2480 case FR30_OPERAND_RJ :
2481 fields->f_Rj = value;
2482 break;
7a0737c8
DB		 2483 case FR30_OPERAND_RS1 :
2484 fields->f_Rs1 = value;
2485 break;
2486 case FR30_OPERAND_RS2 :
2487 fields->f_Rs2 = value;
2488 break;
6a1254af
DB		 2489 case FR30_OPERAND_R13 :
2490 fields->f_nil = value;
2491 break;
2492 case FR30_OPERAND_R14 :
2493 fields->f_nil = value;
2494 break;
2495 case FR30_OPERAND_R15 :
2496 fields->f_nil = value;
2497 break;
2498 case FR30_OPERAND_PS :
2499 fields->f_nil = value;
2500 break;
7a0737c8
DB		 2501 case FR30_OPERAND_U4 :
2502 fields->f_u4 = value;
2503 break;
2504 case FR30_OPERAND_M4 :
2505 fields->f_m4 = value;
2506 break;
6a1254af
DB		 2507 case FR30_OPERAND_U8 :
2508 fields->f_u8 = value;
2509 break;
7a0737c8
DB		 2510 case FR30_OPERAND_I8 :
2511 fields->f_i8 = value;
2512 break;
6a1254af
DB		 2513 case FR30_OPERAND_UDISP6 :
2514 fields->f_udisp6 = value;
2515 break;
2516 case FR30_OPERAND_DISP8 :
2517 fields->f_disp8 = value;
2518 break;
2519 case FR30_OPERAND_DISP9 :
2520 fields->f_disp9 = value;
7a0737c8 2521 break;
6a1254af
DB		 2522 case FR30_OPERAND_DISP10 :
2523 fields->f_disp10 = value;
7a0737c8
DB		 2524 break;
2525 case FR30_OPERAND_S10 :
2526 fields->f_s10 = value;
2527 break;
2528 case FR30_OPERAND_U10 :
2529 fields->f_u10 = value;
2530 break;
95b03313
DE		 2531 case FR30_OPERAND_I32 :
2532 fields->f_i32 = value;
2533 break;
7a0737c8
DB		 2534 case FR30_OPERAND_DIR8 :
2535 fields->f_dir8 = value;
2536 break;
2537 case FR30_OPERAND_DIR9 :
2538 fields->f_dir9 = value;
2539 break;
2540 case FR30_OPERAND_DIR10 :
2541 fields->f_dir10 = value;
2542 break;
2543 case FR30_OPERAND_LABEL9 :
6a1254af 2544 fields->f_rel9 = value;
7a0737c8
DB		 2545 break;
2546 case FR30_OPERAND_LABEL12 :
6a1254af 2547 fields->f_rel12 = value;
7a0737c8
DB		 2548 break;
2549 case FR30_OPERAND_CC :
2550 fields->f_cc = value;
2551 break;
a86481d3
DB		 2552
2553 default :
2554 /* xgettext:c-format */
2555 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
2556 opindex);
2557 abort ();
2558 }
2559}
2560
GDB Binutils - Deliverables
This page took 0.129317 seconds and 4 git commands to generate.