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1998-12-15 Dave Brolley <brolley@cygnus.com>
[deliverable/binutils-gdb.git] / opcodes / fr30-opc.c
CommitLineData
a86481d3
DB		 1/* Generic opcode table support for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
3
4THIS FILE IS USED TO GENERATE fr30-opc.c.
5
6Copyright (C) 1998 Free Software Foundation, Inc.
7
8This file is part of the GNU Binutils and GDB, the GNU debugger.
9
10This program is free software; you can redistribute it and/or modify
11it under the terms of the GNU General Public License as published by
12the Free Software Foundation; either version 2, or (at your option)
13any later version.
14
15This program is distributed in the hope that it will be useful,
16but WITHOUT ANY WARRANTY; without even the implied warranty of
17MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18GNU General Public License for more details.
19
20You should have received a copy of the GNU General Public License
21along with this program; if not, write to the Free Software Foundation, Inc.,
2259 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23
24#include "sysdep.h"
25#include <stdio.h>
26#include "ansidecl.h"
27#include "libiberty.h"
28#include "bfd.h"
29#include "symcat.h"
30#include "fr30-opc.h"
31#include "opintl.h"
32
a73911a7
DE		 33/* Used by the ifield rtx function. */
34#define FLD(f) (fields->f)
35
a86481d3
DB		 36/* The hash functions are recorded here to help keep assembler code out of
37 the disassembler and vice versa. */
38
39static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
40static unsigned int asm_hash_insn PARAMS ((const char *));
41static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
95b03313 42static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
a86481d3
DB		 43
44/* Look up instruction INSN_VALUE and extract its fields.
45 INSN, if non-null, is the insn table entry.
46 Otherwise INSN_VALUE is examined to compute it.
47 LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
48 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
49 If INSN != NULL, LENGTH must be valid.
50 ALIAS_P is non-zero if alias insns are to be included in the search.
51
95b03313 52 The result is a pointer to the insn table entry, or NULL if the instruction
a86481d3
DB		 53 wasn't recognized. */
54
55const CGEN_INSN *
56fr30_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
57 CGEN_OPCODE_DESC od;
58 const CGEN_INSN *insn;
59 CGEN_INSN_BYTES insn_value;
60 int length;
61 CGEN_FIELDS *fields;
62 int alias_p;
63{
95b03313 64 unsigned char buf[CGEN_MAX_INSN_SIZE];
a86481d3 65 unsigned char *bufp;
95b03313 66 CGEN_INSN_INT base_insn;
a86481d3
DB		 67#if CGEN_INT_INSN_P
68 CGEN_EXTRACT_INFO *info = NULL;
69#else
70 CGEN_EXTRACT_INFO ex_info;
71 CGEN_EXTRACT_INFO *info = &ex_info;
72#endif
73
95b03313
DE		 74#if CGEN_INT_INSN_P
75 cgen_put_insn_value (od, buf, length, insn_value);
76 bufp = buf;
77 base_insn = insn_value; /*???*/
78#else
a86481d3 79 ex_info.dis_info = NULL;
95b03313 80 ex_info.insn_bytes = insn_value;
a86481d3 81 ex_info.valid = -1;
95b03313
DE		 82 base_insn = cgen_get_insn_value (od, buf, length);
83 bufp = insn_value;
a86481d3
DB		 84#endif
85
86 if (!insn)
87 {
88 const CGEN_INSN_LIST *insn_list;
89
a86481d3
DB		 90 /* The instructions are stored in hash lists.
91 Pick the first one and keep trying until we find the right one. */
92
93 insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn);
94 while (insn_list != NULL)
95 {
96 insn = insn_list->insn;
97
98 if (alias_p
99 || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
100 {
101 /* Basic bit mask must be correct. */
102 /* ??? May wish to allow target to defer this check until the
103 extract handler. */
a73911a7
DE		 104 if ((base_insn & CGEN_INSN_BASE_MASK (insn))
105 == CGEN_INSN_BASE_VALUE (insn))
a86481d3
DB		 106 {
107 /* ??? 0 is passed for `pc' */
108 int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
95b03313 109 base_insn, fields,
a86481d3
DB		 110 (bfd_vma) 0);
111 if (elength > 0)
112 {
113 /* sanity check */
114 if (length != 0 && length != elength)
115 abort ();
116 return insn;
117 }
118 }
119 }
120
121 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
122 }
123 }
124 else
125 {
126 /* Sanity check: can't pass an alias insn if ! alias_p. */
127 if (! alias_p
128 && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
129 abort ();
130 /* Sanity check: length must be correct. */
131 if (length != CGEN_INSN_BITSIZE (insn))
132 abort ();
133
134 /* ??? 0 is passed for `pc' */
95b03313 135 length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, base_insn, fields,
a86481d3
DB		 136 (bfd_vma) 0);
137 /* Sanity check: must succeed.
138 Could relax this later if it ever proves useful. */
139 if (length == 0)
140 abort ();
141 return insn;
142 }
143
144 return NULL;
145}
146
147/* Fill in the operand instances used by INSN whose operands are FIELDS.
148 INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
149 in. */
150
151void
152fr30_cgen_get_insn_operands (od, insn, fields, indices)
153 CGEN_OPCODE_DESC od;
154 const CGEN_INSN * insn;
155 const CGEN_FIELDS * fields;
156 int *indices;
157{
158 const CGEN_OPERAND_INSTANCE *opinst;
159 int i;
160
161 for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
162 opinst != NULL
163 && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
164 ++i, ++opinst)
165 {
166 const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
167 if (op == NULL)
168 indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
169 else
170 indices[i] = fr30_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
171 fields);
172 }
173}
174
175/* Cover function to fr30_cgen_get_insn_operands when either INSN or FIELDS
176 isn't known.
177 The INSN, INSN_VALUE, and LENGTH arguments are passed to
178 fr30_cgen_lookup_insn unchanged.
179
180 The result is the insn table entry or NULL if the instruction wasn't
181 recognized. */
182
183const CGEN_INSN *
184fr30_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
185 CGEN_OPCODE_DESC od;
186 const CGEN_INSN *insn;
187 CGEN_INSN_BYTES insn_value;
188 int length;
189 int *indices;
190{
191 CGEN_FIELDS fields;
192
193 /* Pass non-zero for ALIAS_P only if INSN != NULL.
194 If INSN == NULL, we want a real insn. */
195 insn = fr30_cgen_lookup_insn (od, insn, insn_value, length, &fields,
196 insn != NULL);
197 if (! insn)
198 return NULL;
199
200 fr30_cgen_get_insn_operands (od, insn, &fields, indices);
201 return insn;
202}
203/* Attributes. */
204
205static const CGEN_ATTR_ENTRY MACH_attr[] =
206{
207 { "base", MACH_BASE },
208 { "fr30", MACH_FR30 },
209 { "max", MACH_MAX },
210 { 0, 0 }
211};
212
213const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
214{
215 { "CACHE-ADDR", NULL },
9225e69c 216 { "FUN-ACCESS", NULL },
a86481d3
DB		 217 { "PC", NULL },
218 { "PROFILE", NULL },
219 { 0, 0 }
220};
221
222const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
223{
224 { "ABS-ADDR", NULL },
7a0737c8 225 { "HASH-PREFIX", NULL },
a86481d3
DB		 226 { "NEGATIVE", NULL },
227 { "PCREL-ADDR", NULL },
228 { "RELAX", NULL },
1c8f439e 229 { "SEM-ONLY", NULL },
a86481d3 230 { "SIGN-OPT", NULL },
7a0737c8 231 { "SIGNED", NULL },
a86481d3 232 { "UNSIGNED", NULL },
a73911a7 233 { "VIRTUAL", NULL },
a86481d3
DB		 234 { 0, 0 }
235};
236
237const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
238{
239 { "ALIAS", NULL },
240 { "COND-CTI", NULL },
a73911a7 241 { "DELAY-SLOT", NULL },
a86481d3 242 { "NO-DIS", NULL },
a73911a7 243 { "NOT-IN-DELAY-SLOT", NULL },
a86481d3
DB		 244 { "RELAX", NULL },
245 { "RELAXABLE", NULL },
246 { "SKIP-CTI", NULL },
247 { "UNCOND-CTI", NULL },
248 { "VIRTUAL", NULL },
249 { 0, 0 }
250};
251
252CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_gr_entries[] =
253{
a86481d3
DB		 254 { "r0", 0 },
255 { "r1", 1 },
256 { "r2", 2 },
257 { "r3", 3 },
258 { "r4", 4 },
259 { "r5", 5 },
260 { "r6", 6 },
261 { "r7", 7 },
262 { "r8", 8 },
263 { "r9", 9 },
264 { "r10", 10 },
265 { "r11", 11 },
266 { "r12", 12 },
267 { "r13", 13 },
268 { "r14", 14 },
6a12a5f3
DB		 269 { "r15", 15 },
270 { "ac", 13 },
271 { "fp", 14 },
272 { "sp", 15 }
a86481d3
DB		 273};
274
275CGEN_KEYWORD fr30_cgen_opval_h_gr =
276{
277 & fr30_cgen_opval_h_gr_entries[0],
278 19
279};
280
e17387a5
DB		 281CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_cr_entries[] =
282{
283 { "cr0", 0 },
284 { "cr1", 1 },
285 { "cr2", 2 },
286 { "cr3", 3 },
287 { "cr4", 4 },
288 { "cr5", 5 },
289 { "cr6", 6 },
290 { "cr7", 7 },
291 { "cr8", 8 },
292 { "cr9", 9 },
293 { "cr10", 10 },
294 { "cr11", 11 },
295 { "cr12", 12 },
296 { "cr13", 13 },
297 { "cr14", 14 },
298 { "cr15", 15 }
299};
300
301CGEN_KEYWORD fr30_cgen_opval_h_cr =
302{
303 & fr30_cgen_opval_h_cr_entries[0],
304 16
305};
306
6146431a
DB		 307CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_dr_entries[] =
308{
309 { "tbr", 0 },
310 { "rp", 1 },
311 { "ssp", 2 },
7a0737c8 312 { "usp", 3 },
6146431a
DB		 313 { "mdh", 4 },
314 { "mdl", 5 }
315};
316
7a0737c8 317CGEN_KEYWORD fr30_cgen_opval_h_dr =
6146431a 318{
7a0737c8
DB		 319 & fr30_cgen_opval_h_dr_entries[0],
320 6
6146431a
DB		 321};
322
6a1254af 323CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] =
6146431a 324{
9225e69c 325 { "ps", 0 }
6146431a
DB		 326};
327
6a1254af 328CGEN_KEYWORD fr30_cgen_opval_h_ps =
6146431a 329{
6a1254af
DB		 330 & fr30_cgen_opval_h_ps_entries[0],
331 1
332};
333
334CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] =
335{
9225e69c 336 { "r13", 0 }
6a1254af
DB		 337};
338
339CGEN_KEYWORD fr30_cgen_opval_h_r13 =
340{
341 & fr30_cgen_opval_h_r13_entries[0],
342 1
343};
344
345CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] =
346{
9225e69c 347 { "r14", 0 }
6a1254af
DB		 348};
349
350CGEN_KEYWORD fr30_cgen_opval_h_r14 =
351{
352 & fr30_cgen_opval_h_r14_entries[0],
353 1
354};
355
356CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] =
357{
9225e69c 358 { "r15", 0 }
6a1254af
DB		 359};
360
361CGEN_KEYWORD fr30_cgen_opval_h_r15 =
362{
363 & fr30_cgen_opval_h_r15_entries[0],
364 1
6146431a
DB		 365};
366
a86481d3
DB		 367
368/* The hardware table. */
369
370#define HW_ENT(n) fr30_cgen_hw_entries[n]
371static const CGEN_HW_ENTRY fr30_cgen_hw_entries[] =
372{
373 { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { 0 } } },
374 { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
375 { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
376 { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
377 { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
378 { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
379 { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_gr, { 0, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { 0 } } },
9657e7fd
DE		 380 { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_cr, { 0, 0, { 0 } } },
381 { HW_H_DR, & HW_ENT (HW_H_DR + 1), "h-dr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_dr, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
9225e69c 382 { HW_H_PS, & HW_ENT (HW_H_PS + 1), "h-ps", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
6a1254af
DB		 383 { HW_H_R13, & HW_ENT (HW_H_R13 + 1), "h-r13", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, 0, { 0 } } },
384 { HW_H_R14, & HW_ENT (HW_H_R14 + 1), "h-r14", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, 0, { 0 } } },
385 { HW_H_R15, & HW_ENT (HW_H_R15 + 1), "h-r15", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, 0, { 0 } } },
7a0737c8
DB		 386 { HW_H_NBIT, & HW_ENT (HW_H_NBIT + 1), "h-nbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
387 { HW_H_ZBIT, & HW_ENT (HW_H_ZBIT + 1), "h-zbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
388 { HW_H_VBIT, & HW_ENT (HW_H_VBIT + 1), "h-vbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
389 { HW_H_CBIT, & HW_ENT (HW_H_CBIT + 1), "h-cbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
9225e69c 390 { HW_H_IBIT, & HW_ENT (HW_H_IBIT + 1), "h-ibit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
6a12a5f3 391 { HW_H_SBIT, & HW_ENT (HW_H_SBIT + 1), "h-sbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
767d2de5
DB		 392 { HW_H_TBIT, & HW_ENT (HW_H_TBIT + 1), "h-tbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
393 { HW_H_D0BIT, & HW_ENT (HW_H_D0BIT + 1), "h-d0bit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
394 { HW_H_D1BIT, & HW_ENT (HW_H_D1BIT + 1), "h-d1bit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
7862c6cf 395 { HW_H_CCR, & HW_ENT (HW_H_CCR + 1), "h-ccr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
ac1b0e6d
DB		 396 { HW_H_SCR, & HW_ENT (HW_H_SCR + 1), "h-scr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
397 { HW_H_ILM, & HW_ENT (HW_H_ILM + 1), "h-ilm", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
a86481d3
DB		 398 { 0 }
399};
400
a73911a7
DE		 401/* The instruction field table. */
402
403static const CGEN_IFLD fr30_cgen_ifld_table[] =
404{
405 { FR30_F_NIL, "f-nil", 0, 0, 0, 0, { 0, 0, { 0 } } },
406 { FR30_F_OP1, "f-op1", 0, 16, 0, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
407 { FR30_F_OP2, "f-op2", 0, 16, 4, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
408 { FR30_F_OP3, "f-op3", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
409 { FR30_F_OP4, "f-op4", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
c8faefbe 410 { FR30_F_OP5, "f-op5", 0, 16, 4, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
a73911a7
DE		 411 { FR30_F_CC, "f-cc", 0, 16, 4, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
412 { FR30_F_CCC, "f-ccc", 16, 16, 0, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
413 { FR30_F_RJ, "f-Rj", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
414 { FR30_F_RI, "f-Ri", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
415 { FR30_F_RS1, "f-Rs1", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
416 { FR30_F_RS2, "f-Rs2", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
417 { FR30_F_RJC, "f-Rjc", 16, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
418 { FR30_F_RIC, "f-Ric", 16, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
419 { FR30_F_CRJ, "f-CRj", 16, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
420 { FR30_F_CRI, "f-CRi", 16, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
421 { FR30_F_U4, "f-u4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
422 { FR30_F_U4C, "f-u4c", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
423 { FR30_F_I4, "f-i4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
424 { FR30_F_M4, "f-m4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
425 { FR30_F_U8, "f-u8", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
426 { FR30_F_I8, "f-i8", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
427 { FR30_F_I20_4, "f-i20-4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
428 { FR30_F_I20_16, "f-i20-16", 16, 16, 0, 16, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
429 { FR30_F_I32, "f-i32", 16, 32, 0, 32, { 0, 0|(1<<CGEN_IFLD_SIGN_OPT)|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
430 { FR30_F_UDISP6, "f-udisp6", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
431 { FR30_F_DISP8, "f-disp8", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
432 { FR30_F_DISP9, "f-disp9", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
433 { FR30_F_DISP10, "f-disp10", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
434 { FR30_F_S10, "f-s10", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
435 { FR30_F_U10, "f-u10", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
436 { FR30_F_REL9, "f-rel9", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_PCREL_ADDR)|(1<<CGEN_IFLD_SIGNED), { 0 } } },
437 { FR30_F_DIR8, "f-dir8", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
438 { FR30_F_DIR9, "f-dir9", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
439 { FR30_F_DIR10, "f-dir10", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
440 { FR30_F_REL12, "f-rel12", 0, 16, 5, 11, { 0, 0|(1<<CGEN_IFLD_PCREL_ADDR)|(1<<CGEN_IFLD_SIGNED), { 0 } } },
bfebcfbf
DB		 441 { FR30_F_REGLIST_HI_ST, "f-reglist_hi_st", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
442 { FR30_F_REGLIST_LOW_ST, "f-reglist_low_st", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
443 { FR30_F_REGLIST_HI_LD, "f-reglist_hi_ld", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
444 { FR30_F_REGLIST_LOW_LD, "f-reglist_low_ld", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
a73911a7
DE		 445 { 0 }
446};
447
a86481d3
DB		 448/* The operand table. */
449
450#define OPERAND(op) CONCAT2 (FR30_OPERAND_,op)
451#define OP_ENT(op) fr30_cgen_operand_table[OPERAND (op)]
452
453const CGEN_OPERAND fr30_cgen_operand_table[MAX_OPERANDS] =
454{
455/* pc: program counter */
456 { "pc", & HW_ENT (HW_H_PC), 0, 0,
1c8f439e 457 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
a86481d3
DB		 458/* Ri: destination register */
459 { "Ri", & HW_ENT (HW_H_GR), 12, 4,
460 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
461/* Rj: source register */
462 { "Rj", & HW_ENT (HW_H_GR), 8, 4,
463 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
e17387a5 464/* Ric: target register coproc insn */
a73911a7 465 { "Ric", & HW_ENT (HW_H_GR), 12, 4,
e17387a5
DB		 466 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
467/* Rjc: source register coproc insn */
a73911a7 468 { "Rjc", & HW_ENT (HW_H_GR), 8, 4,
e17387a5
DB		 469 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
470/* CRi: coprocessor register */
a73911a7 471 { "CRi", & HW_ENT (HW_H_CR), 12, 4,
e17387a5
DB		 472 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
473/* CRj: coprocessor register */
a73911a7 474 { "CRj", & HW_ENT (HW_H_CR), 8, 4,
e17387a5 475 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
7a0737c8
DB		 476/* Rs1: dedicated register */
477 { "Rs1", & HW_ENT (HW_H_DR), 8, 4,
478 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
479/* Rs2: dedicated register */
480 { "Rs2", & HW_ENT (HW_H_DR), 12, 4,
481 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
6a1254af
DB		 482/* R13: General Register 13 */
483 { "R13", & HW_ENT (HW_H_R13), 0, 0,
484 { 0, 0, { 0 } } },
485/* R14: General Register 14 */
486 { "R14", & HW_ENT (HW_H_R14), 0, 0,
487 { 0, 0, { 0 } } },
488/* R15: General Register 15 */
489 { "R15", & HW_ENT (HW_H_R15), 0, 0,
490 { 0, 0, { 0 } } },
7a0737c8 491/* ps: Program Status register */
6a1254af
DB		 492 { "ps", & HW_ENT (HW_H_PS), 0, 0,
493 { 0, 0, { 0 } } },
7a0737c8
DB		 494/* u4: 4 bit unsigned immediate */
495 { "u4", & HW_ENT (HW_H_UINT), 8, 4,
496 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
e17387a5
DB		 497/* u4c: 4 bit unsigned immediate */
498 { "u4c", & HW_ENT (HW_H_UINT), 12, 4,
499 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
7a0737c8
DB		 500/* u8: 8 bit unsigned immediate */
501 { "u8", & HW_ENT (HW_H_UINT), 8, 8,
502 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
6a1254af
DB		 503/* i8: 8 bit unsigned immediate */
504 { "i8", & HW_ENT (HW_H_UINT), 4, 8,
505 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
506/* udisp6: 6 bit unsigned immediate */
507 { "udisp6", & HW_ENT (HW_H_UINT), 8, 4,
7a0737c8 508 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
6a1254af
DB		 509/* disp8: 8 bit signed immediate */
510 { "disp8", & HW_ENT (HW_H_SINT), 4, 8,
511 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
512/* disp9: 9 bit signed immediate */
513 { "disp9", & HW_ENT (HW_H_SINT), 4, 8,
514 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
515/* disp10: 10 bit signed immediate */
516 { "disp10", & HW_ENT (HW_H_SINT), 4, 8,
517 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
7a0737c8
DB		 518/* s10: 10 bit signed immediate */
519 { "s10", & HW_ENT (HW_H_SINT), 8, 8,
520 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
521/* u10: 10 bit unsigned immediate */
522 { "u10", & HW_ENT (HW_H_UINT), 8, 8,
523 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
95b03313 524/* i32: 32 bit immediate */
a73911a7 525 { "i32", & HW_ENT (HW_H_UINT), 0, 32,
95b03313 526 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
7862c6cf
DB		 527/* m4: 4 bit negative immediate */
528 { "m4", & HW_ENT (HW_H_SINT), 8, 4,
529 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
a73911a7
DE		 530/* i20: 20 bit immediate */
531 { "i20", & HW_ENT (HW_H_UINT), 0, 20,
532 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED)|(1<<CGEN_OPERAND_VIRTUAL), { 0 } } },
7a0737c8
DB		 533/* dir8: 8 bit direct address */
534 { "dir8", & HW_ENT (HW_H_UINT), 8, 8,
535 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
536/* dir9: 9 bit direct address */
537 { "dir9", & HW_ENT (HW_H_UINT), 8, 8,
538 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
539/* dir10: 10 bit direct address */
540 { "dir10", & HW_ENT (HW_H_UINT), 8, 8,
541 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
ac1b0e6d
DB		 542/* label9: 9 bit pc relative address */
543 { "label9", & HW_ENT (HW_H_IADDR), 8, 8,
544 { 0, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
7a0737c8 545/* label12: 12 bit pc relative address */
a73911a7 546 { "label12", & HW_ENT (HW_H_IADDR), 5, 11,
b42d4375 547 { 0, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
bfebcfbf
DB		 548/* reglist_low_ld: 8 bit register mask for ldm */
549 { "reglist_low_ld", & HW_ENT (HW_H_UINT), 8, 8,
e17387a5 550 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
bfebcfbf
DB		 551/* reglist_hi_ld: 8 bit register mask for ldm */
552 { "reglist_hi_ld", & HW_ENT (HW_H_UINT), 8, 8,
553 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
554/* reglist_low_st: 8 bit register mask for ldm */
555 { "reglist_low_st", & HW_ENT (HW_H_UINT), 8, 8,
556 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
557/* reglist_hi_st: 8 bit register mask for ldm */
558 { "reglist_hi_st", & HW_ENT (HW_H_UINT), 8, 8,
e17387a5 559 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
7a0737c8
DB		 560/* cc: condition codes */
561 { "cc", & HW_ENT (HW_H_UINT), 4, 4,
562 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
e17387a5 563/* ccc: coprocessor calc */
a73911a7 564 { "ccc", & HW_ENT (HW_H_UINT), 0, 8,
e17387a5 565 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
767d2de5 566/* nbit: negative bit */
6146431a 567 { "nbit", & HW_ENT (HW_H_NBIT), 0, 0,
1c8f439e 568 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
767d2de5 569/* vbit: overflow bit */
6146431a 570 { "vbit", & HW_ENT (HW_H_VBIT), 0, 0,
1c8f439e 571 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
767d2de5 572/* zbit: zero bit */
6146431a 573 { "zbit", & HW_ENT (HW_H_ZBIT), 0, 0,
1c8f439e 574 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
767d2de5 575/* cbit: carry bit */
6146431a 576 { "cbit", & HW_ENT (HW_H_CBIT), 0, 0,
1c8f439e 577 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
767d2de5 578/* ibit: interrupt bit */
9225e69c
DB		 579 { "ibit", & HW_ENT (HW_H_IBIT), 0, 0,
580 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
767d2de5 581/* sbit: stack bit */
9225e69c
DB		 582 { "sbit", & HW_ENT (HW_H_SBIT), 0, 0,
583 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
767d2de5
DB		 584/* tbit: trace trap bit */
585 { "tbit", & HW_ENT (HW_H_TBIT), 0, 0,
586 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
587/* d0bit: division 0 bit */
588 { "d0bit", & HW_ENT (HW_H_D0BIT), 0, 0,
589 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
590/* d1bit: division 1 bit */
591 { "d1bit", & HW_ENT (HW_H_D1BIT), 0, 0,
592 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
7862c6cf
DB		 593/* ccr: condition code bits */
594 { "ccr", & HW_ENT (HW_H_CCR), 0, 0,
595 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
ac1b0e6d
DB		 596/* scr: system condition bits */
597 { "scr", & HW_ENT (HW_H_SCR), 0, 0,
598 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
599/* ilm: condition code bits */
600 { "ilm", & HW_ENT (HW_H_ILM), 0, 0,
601 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
a86481d3
DB		 602};
603
604/* Operand references. */
605
606#define INPUT CGEN_OPERAND_INSTANCE_INPUT
607#define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
95b03313 608#define COND_REF CGEN_OPERAND_INSTANCE_COND_REF
a86481d3 609
6146431a 610static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
95b03313
DE		 611 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
612 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
613 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
614 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
615 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
616 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
617 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
7a0737c8
DB		 618 { 0 }
619};
620
621static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
95b03313
DE		 622 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
623 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
624 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
625 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
626 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
627 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
628 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
7a0737c8
DB		 629 { 0 }
630};
631
632static const CGEN_OPERAND_INSTANCE fmt_add2_ops[] = {
95b03313 633 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
7862c6cf 634 { INPUT, "m4", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (M4), 0, 0 },
95b03313
DE		 635 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
636 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
637 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
638 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
639 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
7a0737c8
DB		 640 { 0 }
641};
642
643static const CGEN_OPERAND_INSTANCE fmt_addc_ops[] = {
95b03313
DE		 644 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
645 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
646 { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
647 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
648 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
649 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
650 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
651 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
7a0737c8
DB		 652 { 0 }
653};
654
655static const CGEN_OPERAND_INSTANCE fmt_addn_ops[] = {
95b03313
DE		 656 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
657 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
658 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
7a0737c8
DB		 659 { 0 }
660};
661
662static const CGEN_OPERAND_INSTANCE fmt_addni_ops[] = {
95b03313
DE		 663 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
664 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
665 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
7a0737c8
DB		 666 { 0 }
667};
668
669static const CGEN_OPERAND_INSTANCE fmt_addn2_ops[] = {
95b03313 670 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
7862c6cf 671 { INPUT, "m4", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (M4), 0, 0 },
95b03313 672 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
7a0737c8
DB		 673 { 0 }
674};
675
676static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
95b03313
DE		 677 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
678 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
679 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
680 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
681 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
682 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
7a0737c8
DB		 683 { 0 }
684};
685
686static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
95b03313
DE		 687 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
688 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
689 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
690 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
691 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
692 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
a86481d3
DB		 693 { 0 }
694};
695
7a0737c8 696static const CGEN_OPERAND_INSTANCE fmt_cmp2_ops[] = {
95b03313 697 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
7862c6cf 698 { INPUT, "m4", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (M4), 0, 0 },
95b03313
DE		 699 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
700 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
701 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
702 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
7a0737c8
DB		 703 { 0 }
704};
705
706static const CGEN_OPERAND_INSTANCE fmt_and_ops[] = {
95b03313
DE		 707 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
708 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
709 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
710 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
711 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
7a0737c8
DB		 712 { 0 }
713};
714
715static const CGEN_OPERAND_INSTANCE fmt_andm_ops[] = {
95b03313
DE		 716 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
717 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
718 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
719 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
720 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
721 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
7a0737c8
DB		 722 { 0 }
723};
724
725static const CGEN_OPERAND_INSTANCE fmt_andh_ops[] = {
95b03313
DE		 726 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
727 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
728 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (RJ), 0, 0 },
729 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
730 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
731 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
7a0737c8
DB		 732 { 0 }
733};
734
735static const CGEN_OPERAND_INSTANCE fmt_andb_ops[] = {
95b03313
DE		 736 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
737 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
738 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (RJ), 0, 0 },
739 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
740 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
741 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
742 { 0 }
743};
744
b42d4375
DB		 745static const CGEN_OPERAND_INSTANCE fmt_bandl_ops[] = {
746 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
747 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_QI, & OP_ENT (U4), 0, 0 },
748 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
749 { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
750 { 0 }
751};
752
753static const CGEN_OPERAND_INSTANCE fmt_btstl_ops[] = {
754 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_QI, & OP_ENT (U4), 0, 0 },
755 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
756 { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
757 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
758 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
759 { 0 }
760};
761
7862c6cf
DB		 762static const CGEN_OPERAND_INSTANCE fmt_mul_ops[] = {
763 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
764 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
765 { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
766 { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
767 { OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
768 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
769 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
770 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
771 { 0 }
772};
773
774static const CGEN_OPERAND_INSTANCE fmt_mulu_ops[] = {
775 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
776 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
777 { INPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
778 { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
779 { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
780 { OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
781 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
782 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
783 { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
784 { 0 }
785};
786
787static const CGEN_OPERAND_INSTANCE fmt_mulh_ops[] = {
788 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
789 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
790 { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
791 { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
792 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
793 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
794 { 0 }
795};
796
767d2de5
DB		 797static const CGEN_OPERAND_INSTANCE fmt_div0s_ops[] = {
798 { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
799 { INPUT, "d0bit", & HW_ENT (HW_H_D0BIT), CGEN_MODE_BI, 0, 0, 0 },
800 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
801 { OUTPUT, "d0bit", & HW_ENT (HW_H_D0BIT), CGEN_MODE_BI, 0, 0, 0 },
802 { OUTPUT, "d1bit", & HW_ENT (HW_H_D1BIT), CGEN_MODE_BI, 0, 0, 0 },
803 { OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, COND_REF },
804 { 0 }
805};
806
807static const CGEN_OPERAND_INSTANCE fmt_div0u_ops[] = {
808 { OUTPUT, "d0bit", & HW_ENT (HW_H_D0BIT), CGEN_MODE_BI, 0, 0, 0 },
809 { OUTPUT, "d1bit", & HW_ENT (HW_H_D1BIT), CGEN_MODE_BI, 0, 0, 0 },
810 { OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
811 { 0 }
812};
813
814static const CGEN_OPERAND_INSTANCE fmt_div1_ops[] = {
815 { INPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
816 { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
817 { INPUT, "d1bit", & HW_ENT (HW_H_D1BIT), CGEN_MODE_BI, 0, 0, 0 },
818 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
767d2de5 819 { INPUT, "d0bit", & HW_ENT (HW_H_D0BIT), CGEN_MODE_BI, 0, 0, 0 },
06d74950 820 { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
767d2de5
DB		 821 { OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, 0 },
822 { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, 0 },
823 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, COND_REF },
824 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
825 { 0 }
826};
827
828static const CGEN_OPERAND_INSTANCE fmt_div2_ops[] = {
829 { INPUT, "d1bit", & HW_ENT (HW_H_D1BIT), CGEN_MODE_BI, 0, 0, 0 },
830 { INPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, COND_REF },
831 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
767d2de5
DB		 832 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, COND_REF },
833 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, COND_REF },
834 { OUTPUT, "h_dr_4", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 4, COND_REF },
835 { 0 }
836};
837
838static const CGEN_OPERAND_INSTANCE fmt_div3_ops[] = {
839 { INPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
840 { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, COND_REF },
841 { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, COND_REF },
842 { 0 }
843};
844
845static const CGEN_OPERAND_INSTANCE fmt_div4s_ops[] = {
846 { INPUT, "d1bit", & HW_ENT (HW_H_D1BIT), CGEN_MODE_BI, 0, 0, 0 },
847 { INPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, COND_REF },
848 { OUTPUT, "h_dr_5", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 5, COND_REF },
849 { 0 }
850};
851
7862c6cf
DB		 852static const CGEN_OPERAND_INSTANCE fmt_lsl_ops[] = {
853 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
854 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
855 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, COND_REF },
856 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
857 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
858 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
859 { 0 }
860};
861
862static const CGEN_OPERAND_INSTANCE fmt_lsli_ops[] = {
863 { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
864 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
865 { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, COND_REF },
866 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, COND_REF },
867 { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
868 { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
869 { 0 }
870};
871
a73911a7
DE		 872static const CGEN_OPERAND_INSTANCE fmt_ldi8_ops[] = {
873 { INPUT, "i8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I8), 0, 0 },
874 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
875 { 0 }
876};
877
878static const CGEN_OPERAND_INSTANCE fmt_ldi20_ops[] = {
879 { INPUT, "i20", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I20), 0, 0 },
880 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
881 { 0 }
882};
883
95b03313
DE		 884static const CGEN_OPERAND_INSTANCE fmt_ldi32_ops[] = {
885 { INPUT, "i32", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I32), 0, 0 },
886 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
7a0737c8
DB		 887 { 0 }
888};
889
7862c6cf
DB		 890static const CGEN_OPERAND_INSTANCE fmt_ld_ops[] = {
891 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
892 { INPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
893 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
894 { 0 }
895};
896
897static const CGEN_OPERAND_INSTANCE fmt_lduh_ops[] = {
898 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
899 { INPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
900 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
901 { 0 }
902};
903
904static const CGEN_OPERAND_INSTANCE fmt_ldub_ops[] = {
905 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
906 { INPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
907 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
908 { 0 }
909};
910
911static const CGEN_OPERAND_INSTANCE fmt_ldr13_ops[] = {
912 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
913 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
914 { INPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
915 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
916 { 0 }
917};
918
919static const CGEN_OPERAND_INSTANCE fmt_ldr13uh_ops[] = {
920 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
921 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
922 { INPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
923 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
924 { 0 }
925};
926
927static const CGEN_OPERAND_INSTANCE fmt_ldr13ub_ops[] = {
928 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
929 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
930 { INPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
931 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
932 { 0 }
933};
934
935static const CGEN_OPERAND_INSTANCE fmt_ldr14_ops[] = {
936 { INPUT, "disp10", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP10), 0, 0 },
937 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
938 { INPUT, "h_memory_add__VM_disp10_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
939 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
940 { 0 }
941};
942
943static const CGEN_OPERAND_INSTANCE fmt_ldr14uh_ops[] = {
944 { INPUT, "disp9", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP9), 0, 0 },
945 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
946 { INPUT, "h_memory_add__VM_disp9_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
947 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
948 { 0 }
949};
950
951static const CGEN_OPERAND_INSTANCE fmt_ldr14ub_ops[] = {
952 { INPUT, "disp8", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP8), 0, 0 },
953 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
954 { INPUT, "h_memory_add__VM_disp8_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
955 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
956 { 0 }
957};
958
959static const CGEN_OPERAND_INSTANCE fmt_ldr15_ops[] = {
960 { INPUT, "udisp6", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UDISP6), 0, 0 },
961 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
962 { INPUT, "h_memory_add__VM_udisp6_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
963 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
964 { 0 }
965};
966
967static const CGEN_OPERAND_INSTANCE fmt_ldr15gr_ops[] = {
968 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
969 { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
ac1b0e6d 970 { INPUT, "f_Ri", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
7862c6cf 971 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
ac1b0e6d
DB		 972 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
973 { 0 }
974};
975
976static const CGEN_OPERAND_INSTANCE fmt_ldr15dr_ops[] = {
977 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
978 { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
ac1b0e6d 979 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
bfebcfbf 980 { OUTPUT, "Rs2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, & OP_ENT (RS2), 0, 0 },
ac1b0e6d
DB		 981 { 0 }
982};
983
984static const CGEN_OPERAND_INSTANCE fmt_ldr15ps_ops[] = {
985 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
986 { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
987 { OUTPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
7862c6cf
DB		 988 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
989 { 0 }
990};
991
992static const CGEN_OPERAND_INSTANCE fmt_st_ops[] = {
993 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
994 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
995 { OUTPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
996 { 0 }
997};
998
ac1b0e6d
DB		 999static const CGEN_OPERAND_INSTANCE fmt_sth_ops[] = {
1000 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
1001 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1002 { OUTPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1003 { 0 }
1004};
1005
1006static const CGEN_OPERAND_INSTANCE fmt_stb_ops[] = {
1007 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
1008 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1009 { OUTPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1010 { 0 }
1011};
1012
1013static const CGEN_OPERAND_INSTANCE fmt_str13_ops[] = {
1014 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
1015 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1016 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1017 { OUTPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1018 { 0 }
1019};
1020
1021static const CGEN_OPERAND_INSTANCE fmt_str13h_ops[] = {
1022 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
1023 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1024 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1025 { OUTPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1026 { 0 }
1027};
1028
1029static const CGEN_OPERAND_INSTANCE fmt_str13b_ops[] = {
1030 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
1031 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1032 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1033 { OUTPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1034 { 0 }
1035};
1036
1037static const CGEN_OPERAND_INSTANCE fmt_str14_ops[] = {
1038 { INPUT, "disp10", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP10), 0, 0 },
1039 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
1040 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1041 { OUTPUT, "h_memory_add__VM_disp10_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1042 { 0 }
1043};
1044
1045static const CGEN_OPERAND_INSTANCE fmt_str14h_ops[] = {
1046 { INPUT, "disp9", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP9), 0, 0 },
1047 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
1048 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1049 { OUTPUT, "h_memory_add__VM_disp9_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1050 { 0 }
1051};
1052
1053static const CGEN_OPERAND_INSTANCE fmt_str14b_ops[] = {
1054 { INPUT, "disp8", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP8), 0, 0 },
1055 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
1056 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1057 { OUTPUT, "h_memory_add__VM_disp8_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1058 { 0 }
1059};
1060
1061static const CGEN_OPERAND_INSTANCE fmt_str15_ops[] = {
1062 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1063 { INPUT, "udisp6", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UDISP6), 0, 0 },
1064 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1065 { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_15_udisp6", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1066 { 0 }
1067};
1068
1069static const CGEN_OPERAND_INSTANCE fmt_str15gr_ops[] = {
1070 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1071 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1072 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1073 { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1074 { 0 }
1075};
1076
1077static const CGEN_OPERAND_INSTANCE fmt_str15dr_ops[] = {
1078 { INPUT, "Rs2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, & OP_ENT (RS2), 0, 0 },
1079 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1080 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1081 { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1082 { 0 }
1083};
1084
1085static const CGEN_OPERAND_INSTANCE fmt_str15ps_ops[] = {
1086 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1087 { INPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
1088 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1089 { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1090 { 0 }
1091};
1092
7862c6cf
DB		 1093static const CGEN_OPERAND_INSTANCE fmt_mov_ops[] = {
1094 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
1095 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1096 { 0 }
1097};
1098
1099static const CGEN_OPERAND_INSTANCE fmt_movdr_ops[] = {
1100 { INPUT, "Rs1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, & OP_ENT (RS1), 0, 0 },
1101 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1102 { 0 }
1103};
1104
ac1b0e6d
DB		 1105static const CGEN_OPERAND_INSTANCE fmt_movps_ops[] = {
1106 { INPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
1107 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1108 { 0 }
1109};
1110
9225e69c
DB		 1111static const CGEN_OPERAND_INSTANCE fmt_mov2dr_ops[] = {
1112 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
7862c6cf 1113 { OUTPUT, "Rs1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, & OP_ENT (RS1), 0, 0 },
9225e69c
DB		 1114 { 0 }
1115};
1116
ac1b0e6d 1117static const CGEN_OPERAND_INSTANCE fmt_mov2ps_ops[] = {
a73911a7 1118 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
ac1b0e6d
DB		 1119 { OUTPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
1120 { 0 }
1121};
1122
1123static const CGEN_OPERAND_INSTANCE fmt_jmp_ops[] = {
1124 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1125 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1126 { 0 }
1127};
1128
1129static const CGEN_OPERAND_INSTANCE fmt_callr_ops[] = {
1130 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1131 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1132 { OUTPUT, "h_dr_1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 1, 0 },
1133 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1134 { 0 }
1135};
1136
1137static const CGEN_OPERAND_INSTANCE fmt_call_ops[] = {
1138 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1139 { INPUT, "label12", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL12), 0, 0 },
1140 { OUTPUT, "h_dr_1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 1, 0 },
1141 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1142 { 0 }
1143};
1144
1145static const CGEN_OPERAND_INSTANCE fmt_ret_ops[] = {
1146 { INPUT, "h_dr_1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 1, 0 },
a73911a7
DE		 1147 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1148 { 0 }
1149};
1150
9225e69c 1151static const CGEN_OPERAND_INSTANCE fmt_int_ops[] = {
367e0392 1152 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
9225e69c 1153 { INPUT, "u8", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (U8), 0, 0 },
7862c6cf 1154 { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 2, 0 },
9225e69c
DB		 1155 { OUTPUT, "ibit", & HW_ENT (HW_H_IBIT), CGEN_MODE_BI, 0, 0, 0 },
1156 { OUTPUT, "sbit", & HW_ENT (HW_H_SBIT), CGEN_MODE_BI, 0, 0, 0 },
1157 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
1158 { 0 }
1159};
1160
9e986b97
DB		 1161static const CGEN_OPERAND_INSTANCE fmt_inte_ops[] = {
1162 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
1163 { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 2, 0 },
1164 { OUTPUT, "ibit", & HW_ENT (HW_H_IBIT), CGEN_MODE_BI, 0, 0, 0 },
1165 { OUTPUT, "ilm", & HW_ENT (HW_H_ILM), CGEN_MODE_UQI, 0, 0, 0 },
1166 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
1167 { 0 }
1168};
1169
9225e69c
DB		 1170static const CGEN_OPERAND_INSTANCE fmt_reti_ops[] = {
1171 { INPUT, "sbit", & HW_ENT (HW_H_SBIT), CGEN_MODE_BI, 0, 0, 0 },
7862c6cf 1172 { INPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 2, COND_REF },
9225e69c 1173 { INPUT, "h_memory_reg__VM_h_dr_2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_USI, 0, 0, COND_REF },
7862c6cf 1174 { INPUT, "h_dr_3", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 3, COND_REF },
9225e69c
DB		 1175 { INPUT, "h_memory_reg__VM_h_dr_3", & HW_ENT (HW_H_MEMORY), CGEN_MODE_USI, 0, 0, COND_REF },
1176 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
7862c6cf 1177 { OUTPUT, "h_dr_2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 2, COND_REF },
9225e69c 1178 { OUTPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, COND_REF },
7862c6cf 1179 { OUTPUT, "h_dr_3", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 3, COND_REF },
9225e69c
DB		 1180 { 0 }
1181};
1182
06d74950 1183static const CGEN_OPERAND_INSTANCE fmt_brad_ops[] = {
7862c6cf
DB		 1184 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1185 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1186 { 0 }
1187};
1188
06d74950 1189static const CGEN_OPERAND_INSTANCE fmt_beqd_ops[] = {
7862c6cf
DB		 1190 { INPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
1191 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1192 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1193 { 0 }
1194};
1195
06d74950 1196static const CGEN_OPERAND_INSTANCE fmt_bcd_ops[] = {
7862c6cf
DB		 1197 { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
1198 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1199 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1200 { 0 }
1201};
1202
06d74950 1203static const CGEN_OPERAND_INSTANCE fmt_bnd_ops[] = {
7862c6cf
DB		 1204 { INPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
1205 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1206 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1207 { 0 }
1208};
1209
06d74950 1210static const CGEN_OPERAND_INSTANCE fmt_bvd_ops[] = {
7862c6cf
DB		 1211 { INPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
1212 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1213 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1214 { 0 }
1215};
1216
06d74950 1217static const CGEN_OPERAND_INSTANCE fmt_bltd_ops[] = {
7862c6cf
DB		 1218 { INPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
1219 { INPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
1220 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1221 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1222 { 0 }
1223};
1224
06d74950 1225static const CGEN_OPERAND_INSTANCE fmt_bled_ops[] = {
7862c6cf
DB		 1226 { INPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
1227 { INPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
1228 { INPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
1229 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1230 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1231 { 0 }
1232};
1233
06d74950 1234static const CGEN_OPERAND_INSTANCE fmt_blsd_ops[] = {
7862c6cf
DB		 1235 { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
1236 { INPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
1237 { INPUT, "label9", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL9), 0, COND_REF },
1238 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
1239 { 0 }
1240};
1241
9e986b97
DB		 1242static const CGEN_OPERAND_INSTANCE fmt_dmovr13_ops[] = {
1243 { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
1244 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1245 { OUTPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1246 { 0 }
1247};
1248
1249static const CGEN_OPERAND_INSTANCE fmt_dmovr13h_ops[] = {
1250 { INPUT, "dir9", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR9), 0, 0 },
1251 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1252 { OUTPUT, "h_memory_dir9", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1253 { 0 }
1254};
1255
1256static const CGEN_OPERAND_INSTANCE fmt_dmovr13b_ops[] = {
1257 { INPUT, "dir8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR8), 0, 0 },
1258 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1259 { OUTPUT, "h_memory_dir8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1260 { 0 }
1261};
1262
1263static const CGEN_OPERAND_INSTANCE fmt_dmovr13pi_ops[] = {
1264 { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
1265 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1266 { INPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1267 { OUTPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1268 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1269 { 0 }
1270};
1271
1272static const CGEN_OPERAND_INSTANCE fmt_dmovr13pih_ops[] = {
1273 { INPUT, "dir9", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR9), 0, 0 },
1274 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1275 { INPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1276 { OUTPUT, "h_memory_dir9", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1277 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1278 { 0 }
1279};
1280
1281static const CGEN_OPERAND_INSTANCE fmt_dmovr13pib_ops[] = {
1282 { INPUT, "dir8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR8), 0, 0 },
1283 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1284 { INPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1285 { OUTPUT, "h_memory_dir8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1286 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1287 { 0 }
1288};
1289
1290static const CGEN_OPERAND_INSTANCE fmt_dmovr15pi_ops[] = {
1291 { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
1292 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1293 { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1294 { OUTPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1295 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1296 { 0 }
1297};
1298
1299static const CGEN_OPERAND_INSTANCE fmt_dmov2r13_ops[] = {
1300 { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
1301 { INPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1302 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1303 { 0 }
1304};
1305
1306static const CGEN_OPERAND_INSTANCE fmt_dmov2r13h_ops[] = {
1307 { INPUT, "dir9", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR9), 0, 0 },
1308 { INPUT, "h_memory_dir9", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1309 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1310 { 0 }
1311};
1312
1313static const CGEN_OPERAND_INSTANCE fmt_dmov2r13b_ops[] = {
1314 { INPUT, "dir8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR8), 0, 0 },
1315 { INPUT, "h_memory_dir8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1316 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1317 { 0 }
1318};
1319
1320static const CGEN_OPERAND_INSTANCE fmt_dmov2r13pi_ops[] = {
1321 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1322 { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
1323 { INPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1324 { OUTPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1325 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1326 { 0 }
1327};
1328
1329static const CGEN_OPERAND_INSTANCE fmt_dmov2r13pih_ops[] = {
1330 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1331 { INPUT, "dir9", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR9), 0, 0 },
1332 { INPUT, "h_memory_dir9", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1333 { OUTPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
1334 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1335 { 0 }
1336};
1337
1338static const CGEN_OPERAND_INSTANCE fmt_dmov2r13pib_ops[] = {
1339 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1340 { INPUT, "dir8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR8), 0, 0 },
1341 { INPUT, "h_memory_dir8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1342 { OUTPUT, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
1343 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
1344 { 0 }
1345};
1346
1347static const CGEN_OPERAND_INSTANCE fmt_dmov2r15pd_ops[] = {
1348 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1349 { INPUT, "dir10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (DIR10), 0, 0 },
1350 { INPUT, "h_memory_dir10", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1351 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1352 { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1353 { 0 }
1354};
1355
6a12a5f3
DB		 1356static const CGEN_OPERAND_INSTANCE fmt_ldres_ops[] = {
1357 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1358 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1359 { 0 }
1360};
1361
7862c6cf
DB		 1362static const CGEN_OPERAND_INSTANCE fmt_andccr_ops[] = {
1363 { INPUT, "ccr", & HW_ENT (HW_H_CCR), CGEN_MODE_UQI, 0, 0, 0 },
1364 { INPUT, "u8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U8), 0, 0 },
1365 { OUTPUT, "ccr", & HW_ENT (HW_H_CCR), CGEN_MODE_UQI, 0, 0, 0 },
b42d4375
DB		 1366 { 0 }
1367};
1368
9e986b97
DB		 1369static const CGEN_OPERAND_INSTANCE fmt_stilm_ops[] = {
1370 { INPUT, "u8", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U8), 0, 0 },
1371 { OUTPUT, "ilm", & HW_ENT (HW_H_ILM), CGEN_MODE_UQI, 0, 0, 0 },
1372 { 0 }
1373};
1374
1375static const CGEN_OPERAND_INSTANCE fmt_addsp_ops[] = {
1376 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1377 { INPUT, "s10", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (S10), 0, 0 },
1378 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1379 { 0 }
1380};
1381
1382static const CGEN_OPERAND_INSTANCE fmt_extsb_ops[] = {
1383 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (RI), 0, 0 },
1384 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1385 { 0 }
1386};
1387
1388static const CGEN_OPERAND_INSTANCE fmt_extub_ops[] = {
1389 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_UQI, & OP_ENT (RI), 0, 0 },
1390 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1391 { 0 }
1392};
1393
1394static const CGEN_OPERAND_INSTANCE fmt_extsh_ops[] = {
1395 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (RI), 0, 0 },
1396 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1397 { 0 }
1398};
1399
1400static const CGEN_OPERAND_INSTANCE fmt_extuh_ops[] = {
1401 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_UHI, & OP_ENT (RI), 0, 0 },
1402 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1403 { 0 }
1404};
1405
bfebcfbf
DB		 1406static const CGEN_OPERAND_INSTANCE fmt_ldm0_ops[] = {
1407 { INPUT, "reglist_low_ld", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (REGLIST_LOW_LD), 0, 0 },
1408 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
1409 { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, COND_REF },
1410 { OUTPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, COND_REF },
1411 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
1412 { OUTPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, COND_REF },
1413 { OUTPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, COND_REF },
1414 { OUTPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, COND_REF },
1415 { OUTPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, COND_REF },
1416 { OUTPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, COND_REF },
1417 { OUTPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, COND_REF },
1418 { OUTPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, COND_REF },
1419 { 0 }
1420};
1421
1422static const CGEN_OPERAND_INSTANCE fmt_ldm1_ops[] = {
1423 { INPUT, "reglist_hi_ld", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (REGLIST_HI_LD), 0, 0 },
1424 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
1425 { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, COND_REF },
1426 { OUTPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, COND_REF },
1427 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
1428 { OUTPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, COND_REF },
1429 { OUTPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, COND_REF },
1430 { OUTPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, COND_REF },
1431 { OUTPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, COND_REF },
1432 { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, COND_REF },
1433 { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, COND_REF },
1434 { 0 }
1435};
1436
9e986b97 1437static const CGEN_OPERAND_INSTANCE fmt_stm0_ops[] = {
bfebcfbf 1438 { INPUT, "reglist_low_st", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (REGLIST_LOW_ST), 0, 0 },
9e986b97 1439 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
bfebcfbf
DB		 1440 { INPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, COND_REF },
1441 { INPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, COND_REF },
1442 { INPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, COND_REF },
1443 { INPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, COND_REF },
1444 { INPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, COND_REF },
1445 { INPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, COND_REF },
1446 { INPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, COND_REF },
9e986b97
DB		 1447 { INPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, COND_REF },
1448 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
1449 { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, COND_REF },
1450 { 0 }
1451};
1452
bfebcfbf
DB		 1453static const CGEN_OPERAND_INSTANCE fmt_stm1_ops[] = {
1454 { INPUT, "reglist_hi_st", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (REGLIST_HI_ST), 0, 0 },
1455 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
1456 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, COND_REF },
1457 { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, COND_REF },
1458 { INPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, COND_REF },
1459 { INPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, COND_REF },
1460 { INPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, COND_REF },
1461 { INPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, COND_REF },
1462 { INPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, COND_REF },
1463 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
1464 { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, COND_REF },
1465 { 0 }
1466};
1467
9e986b97
DB		 1468static const CGEN_OPERAND_INSTANCE fmt_enter_ops[] = {
1469 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1470 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
1471 { INPUT, "u10", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U10), 0, 0 },
1472 { OUTPUT, "h_memory_tmp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1473 { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
1474 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1475 { 0 }
1476};
1477
1478static const CGEN_OPERAND_INSTANCE fmt_leave_ops[] = {
1479 { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
1480 { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1481 { INPUT, "h_memory_sub__VM_reg__VM_h_gr_15_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1482 { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
1483 { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
1484 { 0 }
1485};
1486
1487static const CGEN_OPERAND_INSTANCE fmt_xchb_ops[] = {
1488 { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1489 { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
1490 { INPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
1491 { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
1492 { OUTPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
1493 { 0 }
1494};
1495
a86481d3
DB		 1496#undef INPUT
1497#undef OUTPUT
95b03313 1498#undef COND_REF
a86481d3 1499
a73911a7
DE		 1500/* Instruction formats. */
1501
1502#define F(f) & fr30_cgen_ifld_table[CONCAT2 (FR30_,f)]
1503
1504static const CGEN_IFMT fmt_add = {
1505 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1506};
1507
1508static const CGEN_IFMT fmt_addi = {
1509 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1510};
1511
1512static const CGEN_IFMT fmt_add2 = {
1513 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_M4), F (F_RI), 0 }
1514};
1515
1516static const CGEN_IFMT fmt_addc = {
1517 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1518};
1519
1520static const CGEN_IFMT fmt_addn = {
1521 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1522};
1523
1524static const CGEN_IFMT fmt_addni = {
1525 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1526};
1527
1528static const CGEN_IFMT fmt_addn2 = {
1529 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_M4), F (F_RI), 0 }
1530};
1531
1532static const CGEN_IFMT fmt_cmp = {
1533 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1534};
1535
1536static const CGEN_IFMT fmt_cmpi = {
1537 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1538};
1539
1540static const CGEN_IFMT fmt_cmp2 = {
1541 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_M4), F (F_RI), 0 }
1542};
1543
1544static const CGEN_IFMT fmt_and = {
1545 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1546};
1547
1548static const CGEN_IFMT fmt_andm = {
1549 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1550};
1551
1552static const CGEN_IFMT fmt_andh = {
1553 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1554};
1555
1556static const CGEN_IFMT fmt_andb = {
1557 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1558};
1559
1560static const CGEN_IFMT fmt_bandl = {
1561 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1562};
1563
1564static const CGEN_IFMT fmt_btstl = {
1565 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1566};
1567
1568static const CGEN_IFMT fmt_mul = {
1569 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1570};
1571
7862c6cf
DB		 1572static const CGEN_IFMT fmt_mulu = {
1573 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1574};
1575
1576static const CGEN_IFMT fmt_mulh = {
1577 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1578};
1579
a73911a7
DE		 1580static const CGEN_IFMT fmt_div0s = {
1581 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1582};
1583
767d2de5
DB		 1584static const CGEN_IFMT fmt_div0u = {
1585 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1586};
1587
1588static const CGEN_IFMT fmt_div1 = {
1589 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1590};
1591
1592static const CGEN_IFMT fmt_div2 = {
1593 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1594};
1595
a73911a7
DE		 1596static const CGEN_IFMT fmt_div3 = {
1597 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1598};
1599
767d2de5
DB		 1600static const CGEN_IFMT fmt_div4s = {
1601 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1602};
1603
7862c6cf
DB		 1604static const CGEN_IFMT fmt_lsl = {
1605 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1606};
1607
a73911a7
DE		 1608static const CGEN_IFMT fmt_lsli = {
1609 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1610};
1611
1612static const CGEN_IFMT fmt_ldi8 = {
1613 16, 16, 0xf000, { F (F_OP1), F (F_I8), F (F_RI), 0 }
1614};
1615
1616static const CGEN_IFMT fmt_ldi20 = {
1617 16, 32, 0xff00, { F (F_OP1), F (F_I20), F (F_OP2), F (F_RI), 0 }
1618};
1619
1620static const CGEN_IFMT fmt_ldi32 = {
1621 16, 48, 0xfff0, { F (F_OP1), F (F_I32), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1622};
1623
7862c6cf
DB		 1624static const CGEN_IFMT fmt_ld = {
1625 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1626};
1627
1628static const CGEN_IFMT fmt_lduh = {
1629 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1630};
1631
1632static const CGEN_IFMT fmt_ldub = {
1633 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1634};
1635
1636static const CGEN_IFMT fmt_ldr13 = {
1637 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1638};
1639
1640static const CGEN_IFMT fmt_ldr13uh = {
1641 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1642};
1643
1644static const CGEN_IFMT fmt_ldr13ub = {
1645 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1646};
1647
a73911a7
DE		 1648static const CGEN_IFMT fmt_ldr14 = {
1649 16, 16, 0xf000, { F (F_OP1), F (F_DISP10), F (F_RI), 0 }
1650};
1651
1652static const CGEN_IFMT fmt_ldr14uh = {
1653 16, 16, 0xf000, { F (F_OP1), F (F_DISP9), F (F_RI), 0 }
1654};
1655
1656static const CGEN_IFMT fmt_ldr14ub = {
1657 16, 16, 0xf000, { F (F_OP1), F (F_DISP8), F (F_RI), 0 }
1658};
1659
1660static const CGEN_IFMT fmt_ldr15 = {
1661 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_UDISP6), F (F_RI), 0 }
1662};
1663
7862c6cf
DB		 1664static const CGEN_IFMT fmt_ldr15gr = {
1665 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1666};
1667
a73911a7
DE		 1668static const CGEN_IFMT fmt_ldr15dr = {
1669 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RS2), 0 }
1670};
1671
ac1b0e6d
DB		 1672static const CGEN_IFMT fmt_ldr15ps = {
1673 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1674};
1675
7862c6cf
DB		 1676static const CGEN_IFMT fmt_st = {
1677 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1678};
1679
1680static const CGEN_IFMT fmt_sth = {
1681 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1682};
1683
ac1b0e6d
DB		 1684static const CGEN_IFMT fmt_stb = {
1685 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1686};
1687
1688static const CGEN_IFMT fmt_str13 = {
1689 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1690};
1691
1692static const CGEN_IFMT fmt_str13h = {
1693 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1694};
1695
1696static const CGEN_IFMT fmt_str13b = {
1697 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1698};
1699
7862c6cf
DB		 1700static const CGEN_IFMT fmt_str14 = {
1701 16, 16, 0xf000, { F (F_OP1), F (F_DISP10), F (F_RI), 0 }
1702};
1703
1704static const CGEN_IFMT fmt_str14h = {
1705 16, 16, 0xf000, { F (F_OP1), F (F_DISP9), F (F_RI), 0 }
1706};
1707
1708static const CGEN_IFMT fmt_str14b = {
1709 16, 16, 0xf000, { F (F_OP1), F (F_DISP8), F (F_RI), 0 }
1710};
1711
1712static const CGEN_IFMT fmt_str15 = {
1713 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_UDISP6), F (F_RI), 0 }
1714};
1715
ac1b0e6d
DB		 1716static const CGEN_IFMT fmt_str15gr = {
1717 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1718};
1719
1720static const CGEN_IFMT fmt_str15dr = {
1721 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RS2), 0 }
1722};
1723
1724static const CGEN_IFMT fmt_str15ps = {
1725 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1726};
1727
7862c6cf
DB		 1728static const CGEN_IFMT fmt_mov = {
1729 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1730};
1731
a73911a7
DE		 1732static const CGEN_IFMT fmt_movdr = {
1733 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RS1), F (F_RI), 0 }
1734};
1735
ac1b0e6d
DB		 1736static const CGEN_IFMT fmt_movps = {
1737 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1738};
1739
a73911a7
DE		 1740static const CGEN_IFMT fmt_mov2dr = {
1741 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RS1), F (F_RI), 0 }
1742};
1743
ac1b0e6d
DB		 1744static const CGEN_IFMT fmt_mov2ps = {
1745 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1746};
1747
1748static const CGEN_IFMT fmt_jmp = {
1749 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1750};
1751
1752static const CGEN_IFMT fmt_callr = {
a73911a7
DE		 1753 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1754};
1755
1756static const CGEN_IFMT fmt_call = {
c8faefbe 1757 16, 16, 0xf800, { F (F_OP1), F (F_OP5), F (F_REL12), 0 }
a73911a7
DE		 1758};
1759
ac1b0e6d
DB		 1760static const CGEN_IFMT fmt_ret = {
1761 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1762};
1763
a73911a7
DE		 1764static const CGEN_IFMT fmt_int = {
1765 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 }
1766};
1767
9e986b97
DB		 1768static const CGEN_IFMT fmt_inte = {
1769 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1770};
1771
a73911a7
DE		 1772static const CGEN_IFMT fmt_reti = {
1773 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1774};
1775
06d74950 1776static const CGEN_IFMT fmt_brad = {
a73911a7
DE		 1777 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1778};
1779
06d74950 1780static const CGEN_IFMT fmt_beqd = {
7862c6cf
DB		 1781 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1782};
1783
06d74950 1784static const CGEN_IFMT fmt_bcd = {
7862c6cf
DB		 1785 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1786};
1787
06d74950 1788static const CGEN_IFMT fmt_bnd = {
7862c6cf
DB		 1789 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1790};
1791
06d74950 1792static const CGEN_IFMT fmt_bvd = {
7862c6cf
DB		 1793 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1794};
1795
06d74950 1796static const CGEN_IFMT fmt_bltd = {
7862c6cf
DB		 1797 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1798};
1799
06d74950 1800static const CGEN_IFMT fmt_bled = {
7862c6cf
DB		 1801 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1802};
1803
06d74950 1804static const CGEN_IFMT fmt_blsd = {
7862c6cf
DB		 1805 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
1806};
1807
a73911a7
DE		 1808static const CGEN_IFMT fmt_dmovr13 = {
1809 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
1810};
1811
1812static const CGEN_IFMT fmt_dmovr13h = {
1813 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 }
1814};
1815
1816static const CGEN_IFMT fmt_dmovr13b = {
1817 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 }
1818};
1819
9e986b97
DB		 1820static const CGEN_IFMT fmt_dmovr13pi = {
1821 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
1822};
1823
1824static const CGEN_IFMT fmt_dmovr13pih = {
1825 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 }
1826};
1827
1828static const CGEN_IFMT fmt_dmovr13pib = {
1829 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 }
1830};
1831
1832static const CGEN_IFMT fmt_dmovr15pi = {
1833 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
1834};
1835
1836static const CGEN_IFMT fmt_dmov2r13 = {
1837 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
1838};
1839
1840static const CGEN_IFMT fmt_dmov2r13h = {
1841 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 }
1842};
1843
1844static const CGEN_IFMT fmt_dmov2r13b = {
1845 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 }
1846};
1847
1848static const CGEN_IFMT fmt_dmov2r13pi = {
1849 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
1850};
1851
1852static const CGEN_IFMT fmt_dmov2r13pih = {
1853 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 }
1854};
1855
1856static const CGEN_IFMT fmt_dmov2r13pib = {
1857 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 }
1858};
1859
1860static const CGEN_IFMT fmt_dmov2r15pd = {
1861 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
1862};
1863
7862c6cf
DB		 1864static const CGEN_IFMT fmt_ldres = {
1865 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
1866};
1867
a73911a7
DE		 1868static const CGEN_IFMT fmt_copop = {
1869 16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_CRJ), F (F_U4C), F (F_CRI), 0 }
1870};
1871
1872static const CGEN_IFMT fmt_copld = {
1873 16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_RJC), F (F_U4C), F (F_CRI), 0 }
1874};
1875
1876static const CGEN_IFMT fmt_copst = {
1877 16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_CRJ), F (F_U4C), F (F_RIC), 0 }
1878};
1879
767d2de5
DB		 1880static const CGEN_IFMT fmt_nop = {
1881 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1882};
1883
a73911a7
DE		 1884static const CGEN_IFMT fmt_andccr = {
1885 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 }
1886};
1887
7862c6cf
DB		 1888static const CGEN_IFMT fmt_stilm = {
1889 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 }
1890};
1891
a73911a7
DE		 1892static const CGEN_IFMT fmt_addsp = {
1893 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_S10), 0 }
1894};
1895
9e986b97
DB		 1896static const CGEN_IFMT fmt_extsb = {
1897 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1898};
1899
1900static const CGEN_IFMT fmt_extub = {
1901 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1902};
1903
1904static const CGEN_IFMT fmt_extsh = {
1905 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1906};
1907
1908static const CGEN_IFMT fmt_extuh = {
1909 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1910};
1911
a73911a7 1912static const CGEN_IFMT fmt_ldm0 = {
bfebcfbf 1913 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_LOW_LD), 0 }
a73911a7
DE		 1914};
1915
1916static const CGEN_IFMT fmt_ldm1 = {
bfebcfbf 1917 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_HI_LD), 0 }
a73911a7
DE		 1918};
1919
9e986b97 1920static const CGEN_IFMT fmt_stm0 = {
bfebcfbf
DB		 1921 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_LOW_ST), 0 }
1922};
1923
1924static const CGEN_IFMT fmt_stm1 = {
1925 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_HI_ST), 0 }
9e986b97
DB		 1926};
1927
a73911a7
DE		 1928static const CGEN_IFMT fmt_enter = {
1929 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U10), 0 }
1930};
1931
9e986b97
DB		 1932static const CGEN_IFMT fmt_leave = {
1933 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1934};
1935
ac1b0e6d
DB		 1936static const CGEN_IFMT fmt_xchb = {
1937 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1938};
1939
a73911a7
DE		 1940#undef F
1941
a86481d3
DB		 1942#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
1943#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
1944#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1945
1946/* The instruction table.
1947 This is currently non-static because the simulator accesses it
1948 directly. */
1949
1950const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
1951{
1952 /* Special null first entry.
1953 A `num' value of zero is thus invalid.
1954 Also, the special `invalid' insn resides here. */
1955 { { 0 }, 0 },
6146431a 1956/* add $Rj,$Ri */
a86481d3
DB		 1957 {
1958 { 1, 1, 1, 1 },
7a0737c8
DB		 1959 FR30_INSN_ADD, "add", "add",
1960 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
a73911a7 1961 & fmt_add, { 0xa600 },
7a0737c8
DB		 1962 (PTR) & fmt_add_ops[0],
1963 { 0, 0, { 0 } }
1964 },
1965/* add $u4,$Ri */
1966 {
1967 { 1, 1, 1, 1 },
1968 FR30_INSN_ADDI, "addi", "add",
1969 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
a73911a7 1970 & fmt_addi, { 0xa400 },
7a0737c8
DB		 1971 (PTR) & fmt_addi_ops[0],
1972 { 0, 0, { 0 } }
1973 },
1974/* add2 $m4,$Ri */
1975 {
1976 { 1, 1, 1, 1 },
1977 FR30_INSN_ADD2, "add2", "add2",
1978 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
a73911a7 1979 & fmt_add2, { 0xa500 },
7a0737c8
DB		 1980 (PTR) & fmt_add2_ops[0],
1981 { 0, 0, { 0 } }
1982 },
1983/* addc $Rj,$Ri */
1984 {
1985 { 1, 1, 1, 1 },
1986 FR30_INSN_ADDC, "addc", "addc",
1987 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
a73911a7 1988 & fmt_addc, { 0xa700 },
7a0737c8
DB		 1989 (PTR) & fmt_addc_ops[0],
1990 { 0, 0, { 0 } }
1991 },
1992/* addn $Rj,$Ri */
1993 {
1994 { 1, 1, 1, 1 },
1995 FR30_INSN_ADDN, "addn", "addn",
1996 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
a73911a7 1997 & fmt_addn, { 0xa200 },
7a0737c8
DB		 1998 (PTR) & fmt_addn_ops[0],
1999 { 0, 0, { 0 } }
2000 },
2001/* addn $u4,$Ri */
2002 {
2003 { 1, 1, 1, 1 },
2004 FR30_INSN_ADDNI, "addni", "addn",
2005 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
a73911a7 2006 & fmt_addni, { 0xa000 },
7a0737c8
DB		 2007 (PTR) & fmt_addni_ops[0],
2008 { 0, 0, { 0 } }
2009 },
2010/* addn2 $m4,$Ri */
2011 {
2012 { 1, 1, 1, 1 },
2013 FR30_INSN_ADDN2, "addn2", "addn2",
2014 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
a73911a7 2015 & fmt_addn2, { 0xa100 },
7a0737c8
DB		 2016 (PTR) & fmt_addn2_ops[0],
2017 { 0, 0, { 0 } }
2018 },
2019/* sub $Rj,$Ri */
2020 {
2021 { 1, 1, 1, 1 },
2022 FR30_INSN_SUB, "sub", "sub",
2023 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
a73911a7 2024 & fmt_add, { 0xac00 },
7a0737c8
DB		 2025 (PTR) & fmt_add_ops[0],
2026 { 0, 0, { 0 } }
2027 },
2028/* subc $Rj,$Ri */
2029 {
2030 { 1, 1, 1, 1 },
2031 FR30_INSN_SUBC, "subc", "subc",
2032 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
a73911a7 2033 & fmt_addc, { 0xad00 },
7a0737c8
DB		 2034 (PTR) & fmt_addc_ops[0],
2035 { 0, 0, { 0 } }
2036 },
2037/* subn $Rj,$Ri */
2038 {
2039 { 1, 1, 1, 1 },
2040 FR30_INSN_SUBN, "subn", "subn",
2041 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
a73911a7 2042 & fmt_addn, { 0xae00 },
7a0737c8
DB		 2043 (PTR) & fmt_addn_ops[0],
2044 { 0, 0, { 0 } }
2045 },
2046/* cmp $Rj,$Ri */
2047 {
2048 { 1, 1, 1, 1 },
2049 FR30_INSN_CMP, "cmp", "cmp",
2050 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
a73911a7 2051 & fmt_cmp, { 0xaa00 },
7a0737c8
DB		 2052 (PTR) & fmt_cmp_ops[0],
2053 { 0, 0, { 0 } }
2054 },
2055/* cmp $u4,$Ri */
2056 {
2057 { 1, 1, 1, 1 },
2058 FR30_INSN_CMPI, "cmpi", "cmp",
2059 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
a73911a7 2060 & fmt_cmpi, { 0xa800 },
7a0737c8
DB		 2061 (PTR) & fmt_cmpi_ops[0],
2062 { 0, 0, { 0 } }
2063 },
2064/* cmp2 $m4,$Ri */
2065 {
2066 { 1, 1, 1, 1 },
2067 FR30_INSN_CMP2, "cmp2", "cmp2",
2068 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
a73911a7 2069 & fmt_cmp2, { 0xa900 },
7a0737c8
DB		 2070 (PTR) & fmt_cmp2_ops[0],
2071 { 0, 0, { 0 } }
2072 },
2073/* and $Rj,$Ri */
2074 {
2075 { 1, 1, 1, 1 },
2076 FR30_INSN_AND, "and", "and",
2077 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
a73911a7 2078 & fmt_and, { 0x8200 },
7a0737c8
DB		 2079 (PTR) & fmt_and_ops[0],
2080 { 0, 0, { 0 } }
2081 },
2082/* or $Rj,$Ri */
2083 {
2084 { 1, 1, 1, 1 },
2085 FR30_INSN_OR, "or", "or",
2086 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
a73911a7 2087 & fmt_and, { 0x9200 },
7a0737c8
DB		 2088 (PTR) & fmt_and_ops[0],
2089 { 0, 0, { 0 } }
2090 },
2091/* eor $Rj,$Ri */
2092 {
2093 { 1, 1, 1, 1 },
2094 FR30_INSN_EOR, "eor", "eor",
2095 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
a73911a7 2096 & fmt_and, { 0x9a00 },
7a0737c8
DB		 2097 (PTR) & fmt_and_ops[0],
2098 { 0, 0, { 0 } }
2099 },
2100/* and $Rj,@$Ri */
2101 {
2102 { 1, 1, 1, 1 },
2103 FR30_INSN_ANDM, "andm", "and",
2104 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
a73911a7 2105 & fmt_andm, { 0x8400 },
7a0737c8 2106 (PTR) & fmt_andm_ops[0],
6a12a5f3 2107 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
7a0737c8
DB		 2108 },
2109/* andh $Rj,@$Ri */
2110 {
2111 { 1, 1, 1, 1 },
2112 FR30_INSN_ANDH, "andh", "andh",
2113 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
a73911a7 2114 & fmt_andh, { 0x8500 },
7a0737c8 2115 (PTR) & fmt_andh_ops[0],
6a12a5f3 2116 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
7a0737c8
DB		 2117 },
2118/* andb $Rj,@$Ri */
2119 {
2120 { 1, 1, 1, 1 },
2121 FR30_INSN_ANDB, "andb", "andb",
2122 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
a73911a7 2123 & fmt_andb, { 0x8600 },
7a0737c8 2124 (PTR) & fmt_andb_ops[0],
6a12a5f3 2125 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
7a0737c8
DB		 2126 },
2127/* or $Rj,@$Ri */
2128 {
2129 { 1, 1, 1, 1 },
2130 FR30_INSN_ORM, "orm", "or",
2131 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
a73911a7 2132 & fmt_andm, { 0x9400 },
7a0737c8 2133 (PTR) & fmt_andm_ops[0],
6a12a5f3 2134 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
7a0737c8
DB		 2135 },
2136/* orh $Rj,@$Ri */
2137 {
2138 { 1, 1, 1, 1 },
2139 FR30_INSN_ORH, "orh", "orh",
2140 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
a73911a7 2141 & fmt_andh, { 0x9500 },
7a0737c8 2142 (PTR) & fmt_andh_ops[0],
6a12a5f3 2143 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
7a0737c8
DB		 2144 },
2145/* orb $Rj,@$Ri */
2146 {
2147 { 1, 1, 1, 1 },
2148 FR30_INSN_ORB, "orb", "orb",
2149 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
a73911a7 2150 & fmt_andb, { 0x9600 },
7a0737c8 2151 (PTR) & fmt_andb_ops[0],
6a12a5f3 2152 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
7a0737c8
DB		 2153 },
2154/* eor $Rj,@$Ri */
2155 {
2156 { 1, 1, 1, 1 },
2157 FR30_INSN_EORM, "eorm", "eor",
2158 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
a73911a7 2159 & fmt_andm, { 0x9c00 },
7a0737c8 2160 (PTR) & fmt_andm_ops[0],
6a12a5f3 2161 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
7a0737c8
DB		 2162 },
2163/* eorh $Rj,@$Ri */
2164 {
2165 { 1, 1, 1, 1 },
2166 FR30_INSN_EORH, "eorh", "eorh",
2167 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
a73911a7 2168 & fmt_andh, { 0x9d00 },
7a0737c8 2169 (PTR) & fmt_andh_ops[0],
6a12a5f3 2170 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
7a0737c8
DB		 2171 },
2172/* eorb $Rj,@$Ri */
2173 {
2174 { 1, 1, 1, 1 },
2175 FR30_INSN_EORB, "eorb", "eorb",
2176 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
a73911a7 2177 & fmt_andb, { 0x9e00 },
7a0737c8 2178 (PTR) & fmt_andb_ops[0],
6a12a5f3 2179 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
7a0737c8
DB		 2180 },
2181/* bandl $u4,@$Ri */
2182 {
2183 { 1, 1, 1, 1 },
2184 FR30_INSN_BANDL, "bandl", "bandl",
2185 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
a73911a7 2186 & fmt_bandl, { 0x8000 },
b42d4375 2187 (PTR) & fmt_bandl_ops[0],
6a12a5f3 2188 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
7a0737c8
DB		 2189 },
2190/* borl $u4,@$Ri */
2191 {
2192 { 1, 1, 1, 1 },
2193 FR30_INSN_BORL, "borl", "borl",
2194 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
a73911a7 2195 & fmt_bandl, { 0x9000 },
b42d4375 2196 (PTR) & fmt_bandl_ops[0],
6a12a5f3 2197 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
7a0737c8
DB		 2198 },
2199/* beorl $u4,@$Ri */
2200 {
2201 { 1, 1, 1, 1 },
2202 FR30_INSN_BEORL, "beorl", "beorl",
2203 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
a73911a7 2204 & fmt_bandl, { 0x9800 },
b42d4375 2205 (PTR) & fmt_bandl_ops[0],
6a12a5f3 2206 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
7a0737c8
DB		 2207 },
2208/* bandh $u4,@$Ri */
2209 {
2210 { 1, 1, 1, 1 },
2211 FR30_INSN_BANDH, "bandh", "bandh",
2212 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
a73911a7 2213 & fmt_bandl, { 0x8100 },
b42d4375 2214 (PTR) & fmt_bandl_ops[0],
6a12a5f3 2215 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
7a0737c8
DB		 2216 },
2217/* borh $u4,@$Ri */
2218 {
2219 { 1, 1, 1, 1 },
2220 FR30_INSN_BORH, "borh", "borh",
2221 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
a73911a7 2222 & fmt_bandl, { 0x9100 },
b42d4375 2223 (PTR) & fmt_bandl_ops[0],
6a12a5f3 2224 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
7a0737c8
DB		 2225 },
2226/* beorh $u4,@$Ri */
2227 {
2228 { 1, 1, 1, 1 },
2229 FR30_INSN_BEORH, "beorh", "beorh",
2230 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
a73911a7 2231 & fmt_bandl, { 0x9900 },
b42d4375 2232 (PTR) & fmt_bandl_ops[0],
6a12a5f3 2233 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
7a0737c8
DB		 2234 },
2235/* btstl $u4,@$Ri */
2236 {
2237 { 1, 1, 1, 1 },
2238 FR30_INSN_BTSTL, "btstl", "btstl",
2239 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
a73911a7 2240 & fmt_btstl, { 0x8800 },
b42d4375 2241 (PTR) & fmt_btstl_ops[0],
6a12a5f3 2242 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
7a0737c8
DB		 2243 },
2244/* btsth $u4,@$Ri */
2245 {
2246 { 1, 1, 1, 1 },
2247 FR30_INSN_BTSTH, "btsth", "btsth",
2248 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
a73911a7 2249 & fmt_btstl, { 0x8900 },
b42d4375 2250 (PTR) & fmt_btstl_ops[0],
6a12a5f3 2251 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
7a0737c8
DB		 2252 },
2253/* mul $Rj,$Ri */
2254 {
2255 { 1, 1, 1, 1 },
2256 FR30_INSN_MUL, "mul", "mul",
2257 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
a73911a7 2258 & fmt_mul, { 0xaf00 },
7862c6cf 2259 (PTR) & fmt_mul_ops[0],
6a12a5f3 2260 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
7a0737c8
DB		 2261 },
2262/* mulu $Rj,$Ri */
2263 {
2264 { 1, 1, 1, 1 },
2265 FR30_INSN_MULU, "mulu", "mulu",
2266 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
7862c6cf
DB		 2267 & fmt_mulu, { 0xab00 },
2268 (PTR) & fmt_mulu_ops[0],
6a12a5f3 2269 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
7a0737c8
DB		 2270 },
2271/* mulh $Rj,$Ri */
2272 {
2273 { 1, 1, 1, 1 },
2274 FR30_INSN_MULH, "mulh", "mulh",
2275 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
7862c6cf
DB		 2276 & fmt_mulh, { 0xbf00 },
2277 (PTR) & fmt_mulh_ops[0],
6a12a5f3 2278 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
7a0737c8
DB		 2279 },
2280/* muluh $Rj,$Ri */
2281 {
2282 { 1, 1, 1, 1 },
2283 FR30_INSN_MULUH, "muluh", "muluh",
2284 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
7862c6cf
DB		 2285 & fmt_mulh, { 0xbb00 },
2286 (PTR) & fmt_mulh_ops[0],
6a12a5f3 2287 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
7a0737c8
DB		 2288 },
2289/* div0s $Ri */
2290 {
2291 { 1, 1, 1, 1 },
2292 FR30_INSN_DIV0S, "div0s", "div0s",
2293 { { MNEM, ' ', OP (RI), 0 } },
a73911a7 2294 & fmt_div0s, { 0x9740 },
767d2de5 2295 (PTR) & fmt_div0s_ops[0],
7a0737c8
DB		 2296 { 0, 0, { 0 } }
2297 },
2298/* div0u $Ri */
2299 {
2300 { 1, 1, 1, 1 },
2301 FR30_INSN_DIV0U, "div0u", "div0u",
2302 { { MNEM, ' ', OP (RI), 0 } },
767d2de5
DB		 2303 & fmt_div0u, { 0x9750 },
2304 (PTR) & fmt_div0u_ops[0],
7a0737c8
DB		 2305 { 0, 0, { 0 } }
2306 },
2307/* div1 $Ri */
2308 {
2309 { 1, 1, 1, 1 },
2310 FR30_INSN_DIV1, "div1", "div1",
2311 { { MNEM, ' ', OP (RI), 0 } },
767d2de5
DB		 2312 & fmt_div1, { 0x9760 },
2313 (PTR) & fmt_div1_ops[0],
7a0737c8
DB		 2314 { 0, 0, { 0 } }
2315 },
2316/* div2 $Ri */
2317 {
2318 { 1, 1, 1, 1 },
2319 FR30_INSN_DIV2, "div2", "div2",
2320 { { MNEM, ' ', OP (RI), 0 } },
767d2de5
DB		 2321 & fmt_div2, { 0x9770 },
2322 (PTR) & fmt_div2_ops[0],
7a0737c8
DB		 2323 { 0, 0, { 0 } }
2324 },
2325/* div3 */
2326 {
2327 { 1, 1, 1, 1 },
2328 FR30_INSN_DIV3, "div3", "div3",
2329 { { MNEM, 0 } },
a73911a7 2330 & fmt_div3, { 0x9f60 },
767d2de5 2331 (PTR) & fmt_div3_ops[0],
7a0737c8
DB		 2332 { 0, 0, { 0 } }
2333 },
2334/* div4s */
2335 {
2336 { 1, 1, 1, 1 },
2337 FR30_INSN_DIV4S, "div4s", "div4s",
2338 { { MNEM, 0 } },
767d2de5
DB		 2339 & fmt_div4s, { 0x9f70 },
2340 (PTR) & fmt_div4s_ops[0],
7a0737c8
DB		 2341 { 0, 0, { 0 } }
2342 },
2343/* lsl $Rj,$Ri */
2344 {
2345 { 1, 1, 1, 1 },
2346 FR30_INSN_LSL, "lsl", "lsl",
2347 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
7862c6cf
DB		 2348 & fmt_lsl, { 0xb600 },
2349 (PTR) & fmt_lsl_ops[0],
7a0737c8
DB		 2350 { 0, 0, { 0 } }
2351 },
2352/* lsl $u4,$Ri */
2353 {
2354 { 1, 1, 1, 1 },
2355 FR30_INSN_LSLI, "lsli", "lsl",
2356 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
a73911a7 2357 & fmt_lsli, { 0xb400 },
7862c6cf 2358 (PTR) & fmt_lsli_ops[0],
7a0737c8
DB		 2359 { 0, 0, { 0 } }
2360 },
2361/* lsl2 $u4,$Ri */
2362 {
2363 { 1, 1, 1, 1 },
2364 FR30_INSN_LSL2, "lsl2", "lsl2",
2365 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
a73911a7 2366 & fmt_lsli, { 0xb500 },
7862c6cf 2367 (PTR) & fmt_lsli_ops[0],
7a0737c8
DB		 2368 { 0, 0, { 0 } }
2369 },
2370/* lsr $Rj,$Ri */
2371 {
2372 { 1, 1, 1, 1 },
2373 FR30_INSN_LSR, "lsr", "lsr",
2374 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
7862c6cf
DB		 2375 & fmt_lsl, { 0xb200 },
2376 (PTR) & fmt_lsl_ops[0],
7a0737c8
DB		 2377 { 0, 0, { 0 } }
2378 },
2379/* lsr $u4,$Ri */
2380 {
2381 { 1, 1, 1, 1 },
2382 FR30_INSN_LSRI, "lsri", "lsr",
2383 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
a73911a7 2384 & fmt_lsli, { 0xb000 },
7862c6cf 2385 (PTR) & fmt_lsli_ops[0],
7a0737c8
DB		 2386 { 0, 0, { 0 } }
2387 },
2388/* lsr2 $u4,$Ri */
2389 {
2390 { 1, 1, 1, 1 },
2391 FR30_INSN_LSR2, "lsr2", "lsr2",
2392 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
a73911a7 2393 & fmt_lsli, { 0xb100 },
7862c6cf 2394 (PTR) & fmt_lsli_ops[0],
7a0737c8
DB		 2395 { 0, 0, { 0 } }
2396 },
2397/* asr $Rj,$Ri */
2398 {
2399 { 1, 1, 1, 1 },
2400 FR30_INSN_ASR, "asr", "asr",
2401 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
7862c6cf
DB		 2402 & fmt_lsl, { 0xba00 },
2403 (PTR) & fmt_lsl_ops[0],
7a0737c8
DB		 2404 { 0, 0, { 0 } }
2405 },
2406/* asr $u4,$Ri */
2407 {
2408 { 1, 1, 1, 1 },
2409 FR30_INSN_ASRI, "asri", "asr",
2410 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
a73911a7 2411 & fmt_lsli, { 0xb800 },
7862c6cf 2412 (PTR) & fmt_lsli_ops[0],
7a0737c8
DB		 2413 { 0, 0, { 0 } }
2414 },
2415/* asr2 $u4,$Ri */
2416 {
2417 { 1, 1, 1, 1 },
2418 FR30_INSN_ASR2, "asr2", "asr2",
2419 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
a73911a7 2420 & fmt_lsli, { 0xb900 },
7862c6cf 2421 (PTR) & fmt_lsli_ops[0],
7a0737c8
DB		 2422 { 0, 0, { 0 } }
2423 },
2424/* ldi:8 $i8,$Ri */
2425 {
2426 { 1, 1, 1, 1 },
a73911a7 2427 FR30_INSN_LDI8, "ldi8", "ldi:8",
7a0737c8 2428 { { MNEM, ' ', OP (I8), ',', OP (RI), 0 } },
a73911a7
DE		 2429 & fmt_ldi8, { 0xc000 },
2430 (PTR) & fmt_ldi8_ops[0],
7a0737c8
DB		 2431 { 0, 0, { 0 } }
2432 },
a73911a7
DE		 2433/* ldi:20 $i20,$Ri */
2434 {
2435 { 1, 1, 1, 1 },
2436 FR30_INSN_LDI20, "ldi20", "ldi:20",
2437 { { MNEM, ' ', OP (I20), ',', OP (RI), 0 } },
2438 & fmt_ldi20, { 0x9b00 },
2439 (PTR) & fmt_ldi20_ops[0],
2440 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
2441 },
95b03313
DE		 2442/* ldi:32 $i32,$Ri */
2443 {
2444 { 1, 1, 1, 1 },
2445 FR30_INSN_LDI32, "ldi32", "ldi:32",
2446 { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
a73911a7 2447 & fmt_ldi32, { 0x9f80 },
95b03313 2448 (PTR) & fmt_ldi32_ops[0],
6a12a5f3 2449 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
95b03313 2450 },
7a0737c8
DB		 2451/* ld @$Rj,$Ri */
2452 {
2453 { 1, 1, 1, 1 },
2454 FR30_INSN_LD, "ld", "ld",
2455 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
7862c6cf
DB		 2456 & fmt_ld, { 0x400 },
2457 (PTR) & fmt_ld_ops[0],
7a0737c8
DB		 2458 { 0, 0, { 0 } }
2459 },
2460/* lduh @$Rj,$Ri */
2461 {
2462 { 1, 1, 1, 1 },
2463 FR30_INSN_LDUH, "lduh", "lduh",
2464 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
7862c6cf
DB		 2465 & fmt_lduh, { 0x500 },
2466 (PTR) & fmt_lduh_ops[0],
7a0737c8
DB		 2467 { 0, 0, { 0 } }
2468 },
2469/* ldub @$Rj,$Ri */
2470 {
2471 { 1, 1, 1, 1 },
2472 FR30_INSN_LDUB, "ldub", "ldub",
2473 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
7862c6cf
DB		 2474 & fmt_ldub, { 0x600 },
2475 (PTR) & fmt_ldub_ops[0],
7a0737c8
DB		 2476 { 0, 0, { 0 } }
2477 },
b42d4375 2478/* ld @($R13,$Rj),$Ri */
7a0737c8
DB		 2479 {
2480 { 1, 1, 1, 1 },
2481 FR30_INSN_LDR13, "ldr13", "ld",
6a1254af 2482 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
7862c6cf
DB		 2483 & fmt_ldr13, { 0x0 },
2484 (PTR) & fmt_ldr13_ops[0],
7a0737c8
DB		 2485 { 0, 0, { 0 } }
2486 },
b42d4375 2487/* lduh @($R13,$Rj),$Ri */
7a0737c8
DB		 2488 {
2489 { 1, 1, 1, 1 },
2490 FR30_INSN_LDR13UH, "ldr13uh", "lduh",
6a1254af 2491 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
7862c6cf
DB		 2492 & fmt_ldr13uh, { 0x100 },
2493 (PTR) & fmt_ldr13uh_ops[0],
7a0737c8
DB		 2494 { 0, 0, { 0 } }
2495 },
b42d4375 2496/* ldub @($R13,$Rj),$Ri */
7a0737c8
DB		 2497 {
2498 { 1, 1, 1, 1 },
2499 FR30_INSN_LDR13UB, "ldr13ub", "ldub",
6a1254af 2500 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
7862c6cf
DB		 2501 & fmt_ldr13ub, { 0x200 },
2502 (PTR) & fmt_ldr13ub_ops[0],
7a0737c8
DB		 2503 { 0, 0, { 0 } }
2504 },
b42d4375 2505/* ld @($R14,$disp10),$Ri */
7a0737c8
DB		 2506 {
2507 { 1, 1, 1, 1 },
2508 FR30_INSN_LDR14, "ldr14", "ld",
6a1254af 2509 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP10), ')', ',', OP (RI), 0 } },
a73911a7 2510 & fmt_ldr14, { 0x2000 },
7862c6cf 2511 (PTR) & fmt_ldr14_ops[0],
7a0737c8
DB		 2512 { 0, 0, { 0 } }
2513 },
b42d4375 2514/* lduh @($R14,$disp9),$Ri */
7a0737c8
DB		 2515 {
2516 { 1, 1, 1, 1 },
2517 FR30_INSN_LDR14UH, "ldr14uh", "lduh",
6a1254af 2518 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP9), ')', ',', OP (RI), 0 } },
a73911a7 2519 & fmt_ldr14uh, { 0x4000 },
7862c6cf 2520 (PTR) & fmt_ldr14uh_ops[0],
7a0737c8
DB		 2521 { 0, 0, { 0 } }
2522 },
b42d4375 2523/* ldub @($R14,$disp8),$Ri */
7a0737c8
DB		 2524 {
2525 { 1, 1, 1, 1 },
2526 FR30_INSN_LDR14UB, "ldr14ub", "ldub",
6a1254af 2527 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP8), ')', ',', OP (RI), 0 } },
a73911a7 2528 & fmt_ldr14ub, { 0x6000 },
7862c6cf 2529 (PTR) & fmt_ldr14ub_ops[0],
7a0737c8
DB		 2530 { 0, 0, { 0 } }
2531 },
b42d4375 2532/* ld @($R15,$udisp6),$Ri */
7a0737c8
DB		 2533 {
2534 { 1, 1, 1, 1 },
2535 FR30_INSN_LDR15, "ldr15", "ld",
6a1254af 2536 { { MNEM, ' ', '@', '(', OP (R15), ',', OP (UDISP6), ')', ',', OP (RI), 0 } },
a73911a7 2537 & fmt_ldr15, { 0x300 },
7862c6cf 2538 (PTR) & fmt_ldr15_ops[0],
7a0737c8
DB		 2539 { 0, 0, { 0 } }
2540 },
b42d4375 2541/* ld @$R15+,$Ri */
7a0737c8
DB		 2542 {
2543 { 1, 1, 1, 1 },
2544 FR30_INSN_LDR15GR, "ldr15gr", "ld",
6a1254af 2545 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RI), 0 } },
7862c6cf
DB		 2546 & fmt_ldr15gr, { 0x700 },
2547 (PTR) & fmt_ldr15gr_ops[0],
7a0737c8
DB		 2548 { 0, 0, { 0 } }
2549 },
b42d4375 2550/* ld @$R15+,$Rs2 */
7a0737c8
DB		 2551 {
2552 { 1, 1, 1, 1 },
2553 FR30_INSN_LDR15DR, "ldr15dr", "ld",
6a1254af 2554 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RS2), 0 } },
a73911a7 2555 & fmt_ldr15dr, { 0x780 },
ac1b0e6d 2556 (PTR) & fmt_ldr15dr_ops[0],
7a0737c8
DB		 2557 { 0, 0, { 0 } }
2558 },
b42d4375 2559/* ld @$R15+,$ps */
7a0737c8
DB		 2560 {
2561 { 1, 1, 1, 1 },
2562 FR30_INSN_LDR15PS, "ldr15ps", "ld",
6a1254af 2563 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (PS), 0 } },
ac1b0e6d
DB		 2564 & fmt_ldr15ps, { 0x790 },
2565 (PTR) & fmt_ldr15ps_ops[0],
6a12a5f3 2566 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
7a0737c8 2567 },
6a1254af 2568/* st $Ri,@$Rj */
7a0737c8
DB		 2569 {
2570 { 1, 1, 1, 1 },
2571 FR30_INSN_ST, "st", "st",
6a1254af 2572 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
7862c6cf
DB		 2573 & fmt_st, { 0x1400 },
2574 (PTR) & fmt_st_ops[0],
7a0737c8
DB		 2575 { 0, 0, { 0 } }
2576 },
6a1254af 2577/* sth $Ri,@$Rj */
7a0737c8
DB		 2578 {
2579 { 1, 1, 1, 1 },
2580 FR30_INSN_STH, "sth", "sth",
6a1254af 2581 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
7862c6cf 2582 & fmt_sth, { 0x1500 },
ac1b0e6d 2583 (PTR) & fmt_sth_ops[0],
7a0737c8
DB		 2584 { 0, 0, { 0 } }
2585 },
6a1254af 2586/* stb $Ri,@$Rj */
7a0737c8
DB		 2587 {
2588 { 1, 1, 1, 1 },
2589 FR30_INSN_STB, "stb", "stb",
6a1254af 2590 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
ac1b0e6d
DB		 2591 & fmt_stb, { 0x1600 },
2592 (PTR) & fmt_stb_ops[0],
7a0737c8
DB		 2593 { 0, 0, { 0 } }
2594 },
b42d4375 2595/* st $Ri,@($R13,$Rj) */
7a0737c8
DB		 2596 {
2597 { 1, 1, 1, 1 },
2598 FR30_INSN_STR13, "str13", "st",
6a1254af 2599 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
ac1b0e6d
DB		 2600 & fmt_str13, { 0x1000 },
2601 (PTR) & fmt_str13_ops[0],
7a0737c8
DB		 2602 { 0, 0, { 0 } }
2603 },
b42d4375 2604/* sth $Ri,@($R13,$Rj) */
7a0737c8
DB		 2605 {
2606 { 1, 1, 1, 1 },
2607 FR30_INSN_STR13H, "str13h", "sth",
6a1254af 2608 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
ac1b0e6d
DB		 2609 & fmt_str13h, { 0x1100 },
2610 (PTR) & fmt_str13h_ops[0],
7a0737c8
DB		 2611 { 0, 0, { 0 } }
2612 },
b42d4375 2613/* stb $Ri,@($R13,$Rj) */
7a0737c8
DB		 2614 {
2615 { 1, 1, 1, 1 },
ac1b0e6d 2616 FR30_INSN_STR13B, "str13b", "stb",
6a1254af 2617 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
ac1b0e6d
DB		 2618 & fmt_str13b, { 0x1200 },
2619 (PTR) & fmt_str13b_ops[0],
7a0737c8
DB		 2620 { 0, 0, { 0 } }
2621 },
9e986b97 2622/* st $Ri,@($R14,$disp10) */
7a0737c8
DB		 2623 {
2624 { 1, 1, 1, 1 },
2625 FR30_INSN_STR14, "str14", "st",
9e986b97 2626 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP10), ')', 0 } },
7862c6cf 2627 & fmt_str14, { 0x3000 },
ac1b0e6d 2628 (PTR) & fmt_str14_ops[0],
7a0737c8
DB		 2629 { 0, 0, { 0 } }
2630 },
9e986b97 2631/* sth $Ri,@($R14,$disp9) */
7a0737c8
DB		 2632 {
2633 { 1, 1, 1, 1 },
2634 FR30_INSN_STR14H, "str14h", "sth",
9e986b97 2635 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP9), ')', 0 } },
7862c6cf 2636 & fmt_str14h, { 0x5000 },
ac1b0e6d 2637 (PTR) & fmt_str14h_ops[0],
7a0737c8
DB		 2638 { 0, 0, { 0 } }
2639 },
9e986b97 2640/* stb $Ri,@($R14,$disp8) */
7a0737c8
DB		 2641 {
2642 { 1, 1, 1, 1 },
2643 FR30_INSN_STR14B, "str14b", "stb",
9e986b97 2644 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP8), ')', 0 } },
7862c6cf 2645 & fmt_str14b, { 0x7000 },
ac1b0e6d 2646 (PTR) & fmt_str14b_ops[0],
7a0737c8
DB		 2647 { 0, 0, { 0 } }
2648 },
b42d4375 2649/* st $Ri,@($R15,$udisp6) */
7a0737c8
DB		 2650 {
2651 { 1, 1, 1, 1 },
2652 FR30_INSN_STR15, "str15", "st",
6a1254af 2653 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R15), ',', OP (UDISP6), ')', 0 } },
7862c6cf 2654 & fmt_str15, { 0x1300 },
ac1b0e6d 2655 (PTR) & fmt_str15_ops[0],
7a0737c8
DB		 2656 { 0, 0, { 0 } }
2657 },
b42d4375 2658/* st $Ri,@-$R15 */
7a0737c8
DB		 2659 {
2660 { 1, 1, 1, 1 },
2661 FR30_INSN_STR15GR, "str15gr", "st",
6a1254af 2662 { { MNEM, ' ', OP (RI), ',', '@', '-', OP (R15), 0 } },
ac1b0e6d
DB		 2663 & fmt_str15gr, { 0x1700 },
2664 (PTR) & fmt_str15gr_ops[0],
7a0737c8
DB		 2665 { 0, 0, { 0 } }
2666 },
b42d4375 2667/* st $Rs2,@-$R15 */
7a0737c8
DB		 2668 {
2669 { 1, 1, 1, 1 },
2670 FR30_INSN_STR15DR, "str15dr", "st",
6a1254af 2671 { { MNEM, ' ', OP (RS2), ',', '@', '-', OP (R15), 0 } },
ac1b0e6d
DB		 2672 & fmt_str15dr, { 0x1780 },
2673 (PTR) & fmt_str15dr_ops[0],
7a0737c8
DB		 2674 { 0, 0, { 0 } }
2675 },
b42d4375 2676/* st $ps,@-$R15 */
7a0737c8
DB		 2677 {
2678 { 1, 1, 1, 1 },
2679 FR30_INSN_STR15PS, "str15ps", "st",
6a1254af 2680 { { MNEM, ' ', OP (PS), ',', '@', '-', OP (R15), 0 } },
ac1b0e6d
DB		 2681 & fmt_str15ps, { 0x1790 },
2682 (PTR) & fmt_str15ps_ops[0],
7a0737c8
DB		 2683 { 0, 0, { 0 } }
2684 },
2685/* mov $Rj,$Ri */
2686 {
2687 { 1, 1, 1, 1 },
2688 FR30_INSN_MOV, "mov", "mov",
2689 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
7862c6cf
DB		 2690 & fmt_mov, { 0x8b00 },
2691 (PTR) & fmt_mov_ops[0],
7a0737c8
DB		 2692 { 0, 0, { 0 } }
2693 },
2694/* mov $Rs1,$Ri */
2695 {
2696 { 1, 1, 1, 1 },
2697 FR30_INSN_MOVDR, "movdr", "mov",
2698 { { MNEM, ' ', OP (RS1), ',', OP (RI), 0 } },
a73911a7 2699 & fmt_movdr, { 0xb700 },
7862c6cf 2700 (PTR) & fmt_movdr_ops[0],
7a0737c8
DB		 2701 { 0, 0, { 0 } }
2702 },
6a1254af 2703/* mov $ps,$Ri */
7a0737c8
DB		 2704 {
2705 { 1, 1, 1, 1 },
2706 FR30_INSN_MOVPS, "movps", "mov",
6a1254af 2707 { { MNEM, ' ', OP (PS), ',', OP (RI), 0 } },
ac1b0e6d
DB		 2708 & fmt_movps, { 0x1710 },
2709 (PTR) & fmt_movps_ops[0],
7a0737c8
DB		 2710 { 0, 0, { 0 } }
2711 },
2712/* mov $Ri,$Rs1 */
2713 {
2714 { 1, 1, 1, 1 },
2715 FR30_INSN_MOV2DR, "mov2dr", "mov",
2716 { { MNEM, ' ', OP (RI), ',', OP (RS1), 0 } },
a73911a7 2717 & fmt_mov2dr, { 0xb300 },
9225e69c 2718 (PTR) & fmt_mov2dr_ops[0],
7a0737c8
DB		 2719 { 0, 0, { 0 } }
2720 },
6a1254af 2721/* mov $Ri,$ps */
7a0737c8
DB		 2722 {
2723 { 1, 1, 1, 1 },
2724 FR30_INSN_MOV2PS, "mov2ps", "mov",
6a1254af 2725 { { MNEM, ' ', OP (RI), ',', OP (PS), 0 } },
ac1b0e6d
DB		 2726 & fmt_mov2ps, { 0x710 },
2727 (PTR) & fmt_mov2ps_ops[0],
7a0737c8
DB		 2728 { 0, 0, { 0 } }
2729 },
2730/* jmp @$Ri */
2731 {
2732 { 1, 1, 1, 1 },
2733 FR30_INSN_JMP, "jmp", "jmp",
2734 { { MNEM, ' ', '@', OP (RI), 0 } },
ac1b0e6d
DB		 2735 & fmt_jmp, { 0x9700 },
2736 (PTR) & fmt_jmp_ops[0],
6a12a5f3 2737 { 0, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
7a0737c8 2738 },
a73911a7 2739/* jmp:d @$Ri */
6a1254af
DB		 2740 {
2741 { 1, 1, 1, 1 },
a73911a7 2742 FR30_INSN_JMPD, "jmpd", "jmp:d",
6a1254af 2743 { { MNEM, ' ', '@', OP (RI), 0 } },
ac1b0e6d
DB		 2744 & fmt_jmp, { 0x9f00 },
2745 (PTR) & fmt_jmp_ops[0],
a73911a7 2746 { 0, 0|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
6a1254af 2747 },
e17387a5 2748/* call @$Ri */
7a0737c8
DB		 2749 {
2750 { 1, 1, 1, 1 },
e17387a5
DB		 2751 FR30_INSN_CALLR, "callr", "call",
2752 { { MNEM, ' ', '@', OP (RI), 0 } },
ac1b0e6d
DB		 2753 & fmt_callr, { 0x9710 },
2754 (PTR) & fmt_callr_ops[0],
6a12a5f3 2755 { 0, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
7a0737c8 2756 },
ac1b0e6d 2757/* call:d @$Ri */
6a1254af
DB		 2758 {
2759 { 1, 1, 1, 1 },
ac1b0e6d 2760 FR30_INSN_CALLRD, "callrd", "call:d",
e17387a5 2761 { { MNEM, ' ', '@', OP (RI), 0 } },
ac1b0e6d
DB		 2762 & fmt_callr, { 0x9f10 },
2763 (PTR) & fmt_callr_ops[0],
6a12a5f3 2764 { 0, 0|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
6a1254af 2765 },
e17387a5 2766/* call $label12 */
7a0737c8
DB		 2767 {
2768 { 1, 1, 1, 1 },
e17387a5
DB		 2769 FR30_INSN_CALL, "call", "call",
2770 { { MNEM, ' ', OP (LABEL12), 0 } },
a73911a7 2771 & fmt_call, { 0xd000 },
ac1b0e6d 2772 (PTR) & fmt_call_ops[0],
6a12a5f3 2773 { 0, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
7a0737c8 2774 },
ac1b0e6d 2775/* call:d $label12 */
6a1254af
DB		 2776 {
2777 { 1, 1, 1, 1 },
ac1b0e6d 2778 FR30_INSN_CALLD, "calld", "call:d",
e17387a5 2779 { { MNEM, ' ', OP (LABEL12), 0 } },
c8faefbe 2780 & fmt_call, { 0xd800 },
ac1b0e6d 2781 (PTR) & fmt_call_ops[0],
6a12a5f3 2782 { 0, 0|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
6a1254af 2783 },
7a0737c8
DB		 2784/* ret */
2785 {
2786 { 1, 1, 1, 1 },
2787 FR30_INSN_RET, "ret", "ret",
2788 { { MNEM, 0 } },
ac1b0e6d
DB		 2789 & fmt_ret, { 0x9720 },
2790 (PTR) & fmt_ret_ops[0],
6a12a5f3 2791 { 0, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
7a0737c8 2792 },
ac1b0e6d 2793/* ret:d */
6a1254af
DB		 2794 {
2795 { 1, 1, 1, 1 },
ac1b0e6d 2796 FR30_INSN_RET_D, "ret:d", "ret:d",
6a1254af 2797 { { MNEM, 0 } },
ac1b0e6d
DB		 2798 & fmt_ret, { 0x9f20 },
2799 (PTR) & fmt_ret_ops[0],
6a12a5f3 2800 { 0, 0|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
6a1254af 2801 },
7a0737c8
DB		 2802/* int $u8 */
2803 {
2804 { 1, 1, 1, 1 },
2805 FR30_INSN_INT, "int", "int",
2806 { { MNEM, ' ', OP (U8), 0 } },
a73911a7 2807 & fmt_int, { 0x1f00 },
9225e69c 2808 (PTR) & fmt_int_ops[0],
6a12a5f3 2809 { 0, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
7a0737c8 2810 },
6a1254af 2811/* inte */
7a0737c8
DB		 2812 {
2813 { 1, 1, 1, 1 },
6a1254af 2814 FR30_INSN_INTE, "inte", "inte",
7a0737c8 2815 { { MNEM, 0 } },
9e986b97
DB		 2816 & fmt_inte, { 0x9f30 },
2817 (PTR) & fmt_inte_ops[0],
6a12a5f3 2818 { 0, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
7a0737c8
DB		 2819 },
2820/* reti */
2821 {
2822 { 1, 1, 1, 1 },
2823 FR30_INSN_RETI, "reti", "reti",
2824 { { MNEM, 0 } },
a73911a7 2825 & fmt_reti, { 0x9730 },
9225e69c 2826 (PTR) & fmt_reti_ops[0],
6a12a5f3 2827 { 0, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(COND_CTI), { 0 } }
7a0737c8 2828 },
ac1b0e6d 2829/* bra:d $label9 */
7a0737c8
DB		 2830 {
2831 { 1, 1, 1, 1 },
ac1b0e6d 2832 FR30_INSN_BRAD, "brad", "bra:d",
7a0737c8 2833 { { MNEM, ' ', OP (LABEL9), 0 } },
06d74950
DB		 2834 & fmt_brad, { 0xf000 },
2835 (PTR) & fmt_brad_ops[0],
9e986b97 2836 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
7a0737c8 2837 },
06d74950 2838/* bra $label9 */
7a0737c8
DB		 2839 {
2840 { 1, 1, 1, 1 },
06d74950 2841 FR30_INSN_BRA, "bra", "bra",
7a0737c8 2842 { { MNEM, ' ', OP (LABEL9), 0 } },
06d74950
DB		 2843 & fmt_brad, { 0xe000 },
2844 (PTR) & fmt_brad_ops[0],
7862c6cf 2845 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
7a0737c8 2846 },
ac1b0e6d 2847/* bno:d $label9 */
7a0737c8
DB		 2848 {
2849 { 1, 1, 1, 1 },
ac1b0e6d 2850 FR30_INSN_BNOD, "bnod", "bno:d",
7a0737c8 2851 { { MNEM, ' ', OP (LABEL9), 0 } },
06d74950
DB		 2852 & fmt_brad, { 0xf100 },
2853 (PTR) & fmt_brad_ops[0],
9e986b97 2854 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
7a0737c8 2855 },
06d74950 2856/* bno $label9 */
7a0737c8
DB		 2857 {
2858 { 1, 1, 1, 1 },
06d74950 2859 FR30_INSN_BNO, "bno", "bno",
7a0737c8 2860 { { MNEM, ' ', OP (LABEL9), 0 } },
06d74950
DB		 2861 & fmt_brad, { 0xe100 },
2862 (PTR) & fmt_brad_ops[0],
7862c6cf 2863 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
7a0737c8 2864 },
ac1b0e6d 2865/* beq:d $label9 */
7a0737c8
DB		 2866 {
2867 { 1, 1, 1, 1 },
ac1b0e6d 2868 FR30_INSN_BEQD, "beqd", "beq:d",
7a0737c8 2869 { { MNEM, ' ', OP (LABEL9), 0 } },
06d74950
DB		 2870 & fmt_beqd, { 0xf200 },
2871 (PTR) & fmt_beqd_ops[0],
9e986b97 2872 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
7a0737c8 2873 },
06d74950 2874/* beq $label9 */
7a0737c8
DB		 2875 {
2876 { 1, 1, 1, 1 },
06d74950 2877 FR30_INSN_BEQ, "beq", "beq",
7a0737c8 2878 { { MNEM, ' ', OP (LABEL9), 0 } },
06d74950
DB		 2879 & fmt_beqd, { 0xe200 },
2880 (PTR) & fmt_beqd_ops[0],
7862c6cf 2881 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
7a0737c8 2882 },
ac1b0e6d 2883/* bne:d $label9 */
7a0737c8
DB		 2884 {
2885 { 1, 1, 1, 1 },
ac1b0e6d 2886 FR30_INSN_BNED, "bned", "bne:d",
7a0737c8 2887 { { MNEM, ' ', OP (LABEL9), 0 } },
06d74950
DB		 2888 & fmt_beqd, { 0xf300 },
2889 (PTR) & fmt_beqd_ops[0],
9e986b97 2890 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
7a0737c8 2891 },
06d74950 2892/* bne $label9 */
7a0737c8
DB		 2893 {
2894 { 1, 1, 1, 1 },
06d74950 2895 FR30_INSN_BNE, "bne", "bne",
7a0737c8 2896 { { MNEM, ' ', OP (LABEL9), 0 } },
06d74950
DB		 2897 & fmt_beqd, { 0xe300 },
2898 (PTR) & fmt_beqd_ops[0],
7862c6cf 2899 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
7a0737c8 2900 },
ac1b0e6d 2901/* bc:d $label9 */
7a0737c8
DB		 2902 {
2903 { 1, 1, 1, 1 },
ac1b0e6d 2904 FR30_INSN_BCD, "bcd", "bc:d",
7a0737c8 2905 { { MNEM, ' ', OP (LABEL9), 0 } },
06d74950
DB		 2906 & fmt_bcd, { 0xf400 },
2907 (PTR) & fmt_bcd_ops[0],
9e986b97 2908 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
7a0737c8 2909 },
06d74950 2910/* bc $label9 */
7a0737c8
DB		 2911 {
2912 { 1, 1, 1, 1 },
06d74950 2913 FR30_INSN_BC, "bc", "bc",
7a0737c8 2914 { { MNEM, ' ', OP (LABEL9), 0 } },
06d74950
DB		 2915 & fmt_bcd, { 0xe400 },
2916 (PTR) & fmt_bcd_ops[0],
7862c6cf 2917 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
7a0737c8 2918 },
ac1b0e6d 2919/* bnc:d $label9 */
7a0737c8
DB		 2920 {
2921 { 1, 1, 1, 1 },
ac1b0e6d 2922 FR30_INSN_BNCD, "bncd", "bnc:d",
7a0737c8 2923 { { MNEM, ' ', OP (LABEL9), 0 } },
06d74950
DB		 2924 & fmt_bcd, { 0xf500 },
2925 (PTR) & fmt_bcd_ops[0],
9e986b97 2926 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
7a0737c8 2927 },
06d74950 2928/* bnc $label9 */
7a0737c8
DB		 2929 {
2930 { 1, 1, 1, 1 },
06d74950 2931 FR30_INSN_BNC, "bnc", "bnc",
7a0737c8 2932 { { MNEM, ' ', OP (LABEL9), 0 } },
06d74950
DB		 2933 & fmt_bcd, { 0xe500 },
2934 (PTR) & fmt_bcd_ops[0],
7862c6cf 2935 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
7a0737c8 2936 },
ac1b0e6d 2937/* bn:d $label9 */
7a0737c8
DB		 2938 {
2939 { 1, 1, 1, 1 },
ac1b0e6d 2940 FR30_INSN_BND, "bnd", "bn:d",
7a0737c8 2941 { { MNEM, ' ', OP (LABEL9), 0 } },
06d74950
DB		 2942 & fmt_bnd, { 0xf600 },
2943 (PTR) & fmt_bnd_ops[0],
9e986b97 2944 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
7a0737c8 2945 },
06d74950 2946/* bn $label9 */
7a0737c8
DB		 2947 {
2948 { 1, 1, 1, 1 },
06d74950 2949 FR30_INSN_BN, "bn", "bn",
7a0737c8 2950 { { MNEM, ' ', OP (LABEL9), 0 } },
06d74950
DB		 2951 & fmt_bnd, { 0xe600 },
2952 (PTR) & fmt_bnd_ops[0],
7862c6cf 2953 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
7a0737c8 2954 },
ac1b0e6d 2955/* bp:d $label9 */
7a0737c8
DB		 2956 {
2957 { 1, 1, 1, 1 },
ac1b0e6d 2958 FR30_INSN_BPD, "bpd", "bp:d",
7a0737c8 2959 { { MNEM, ' ', OP (LABEL9), 0 } },
06d74950
DB		 2960 & fmt_bnd, { 0xf700 },
2961 (PTR) & fmt_bnd_ops[0],
9e986b97 2962 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
7a0737c8 2963 },
06d74950 2964/* bp $label9 */
6a1254af
DB		 2965 {
2966 { 1, 1, 1, 1 },
06d74950 2967 FR30_INSN_BP, "bp", "bp",
6a1254af 2968 { { MNEM, ' ', OP (LABEL9), 0 } },
06d74950
DB		 2969 & fmt_bnd, { 0xe700 },
2970 (PTR) & fmt_bnd_ops[0],
7862c6cf 2971 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
6a1254af 2972 },
ac1b0e6d 2973/* bv:d $label9 */
6a1254af
DB		 2974 {
2975 { 1, 1, 1, 1 },
ac1b0e6d 2976 FR30_INSN_BVD, "bvd", "bv:d",
6a1254af 2977 { { MNEM, ' ', OP (LABEL9), 0 } },
06d74950
DB		 2978 & fmt_bvd, { 0xf800 },
2979 (PTR) & fmt_bvd_ops[0],
9e986b97 2980 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
6a1254af 2981 },
06d74950 2982/* bv $label9 */
6a1254af
DB		 2983 {
2984 { 1, 1, 1, 1 },
06d74950 2985 FR30_INSN_BV, "bv", "bv",
6a1254af 2986 { { MNEM, ' ', OP (LABEL9), 0 } },
06d74950
DB		 2987 & fmt_bvd, { 0xe800 },
2988 (PTR) & fmt_bvd_ops[0],
7862c6cf 2989 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
6a1254af 2990 },
ac1b0e6d 2991/* bnv:d $label9 */
6a1254af
DB		 2992 {
2993 { 1, 1, 1, 1 },
ac1b0e6d 2994 FR30_INSN_BNVD, "bnvd", "bnv:d",
6a1254af 2995 { { MNEM, ' ', OP (LABEL9), 0 } },
06d74950
DB		 2996 & fmt_bvd, { 0xf900 },
2997 (PTR) & fmt_bvd_ops[0],
9e986b97 2998 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
6a1254af 2999 },
06d74950 3000/* bnv $label9 */
6a1254af
DB		 3001 {
3002 { 1, 1, 1, 1 },
06d74950 3003 FR30_INSN_BNV, "bnv", "bnv",
6a1254af 3004 { { MNEM, ' ', OP (LABEL9), 0 } },
06d74950
DB		 3005 & fmt_bvd, { 0xe900 },
3006 (PTR) & fmt_bvd_ops[0],
7862c6cf 3007 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
6a1254af 3008 },
ac1b0e6d 3009/* blt:d $label9 */
6a1254af
DB		 3010 {
3011 { 1, 1, 1, 1 },
ac1b0e6d 3012 FR30_INSN_BLTD, "bltd", "blt:d",
6a1254af 3013 { { MNEM, ' ', OP (LABEL9), 0 } },
06d74950
DB		 3014 & fmt_bltd, { 0xfa00 },
3015 (PTR) & fmt_bltd_ops[0],
9e986b97 3016 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
6a1254af 3017 },
06d74950 3018/* blt $label9 */
6a1254af
DB		 3019 {
3020 { 1, 1, 1, 1 },
06d74950 3021 FR30_INSN_BLT, "blt", "blt",
6a1254af 3022 { { MNEM, ' ', OP (LABEL9), 0 } },
06d74950
DB		 3023 & fmt_bltd, { 0xea00 },
3024 (PTR) & fmt_bltd_ops[0],
7862c6cf 3025 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
6a1254af 3026 },
ac1b0e6d 3027/* bge:d $label9 */
6a1254af
DB		 3028 {
3029 { 1, 1, 1, 1 },
ac1b0e6d 3030 FR30_INSN_BGED, "bged", "bge:d",
6a1254af 3031 { { MNEM, ' ', OP (LABEL9), 0 } },
06d74950
DB		 3032 & fmt_bltd, { 0xfb00 },
3033 (PTR) & fmt_bltd_ops[0],
9e986b97 3034 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
6a1254af 3035 },
06d74950 3036/* bge $label9 */
6a1254af
DB		 3037 {
3038 { 1, 1, 1, 1 },
06d74950 3039 FR30_INSN_BGE, "bge", "bge",
6a1254af 3040 { { MNEM, ' ', OP (LABEL9), 0 } },
06d74950
DB		 3041 & fmt_bltd, { 0xeb00 },
3042 (PTR) & fmt_bltd_ops[0],
7862c6cf 3043 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
6a1254af 3044 },
ac1b0e6d 3045/* ble:d $label9 */
6a1254af
DB		 3046 {
3047 { 1, 1, 1, 1 },
ac1b0e6d 3048 FR30_INSN_BLED, "bled", "ble:d",
6a1254af 3049 { { MNEM, ' ', OP (LABEL9), 0 } },
06d74950
DB		 3050 & fmt_bled, { 0xfc00 },
3051 (PTR) & fmt_bled_ops[0],
9e986b97 3052 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
6a1254af 3053 },
06d74950 3054/* ble $label9 */
6a1254af
DB		 3055 {
3056 { 1, 1, 1, 1 },
06d74950 3057 FR30_INSN_BLE, "ble", "ble",
6a1254af 3058 { { MNEM, ' ', OP (LABEL9), 0 } },
06d74950
DB		 3059 & fmt_bled, { 0xec00 },
3060 (PTR) & fmt_bled_ops[0],
7862c6cf 3061 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
6a1254af 3062 },
ac1b0e6d 3063/* bgt:d $label9 */
6a1254af
DB		 3064 {
3065 { 1, 1, 1, 1 },
ac1b0e6d 3066 FR30_INSN_BGTD, "bgtd", "bgt:d",
6a1254af 3067 { { MNEM, ' ', OP (LABEL9), 0 } },
06d74950
DB		 3068 & fmt_bled, { 0xfd00 },
3069 (PTR) & fmt_bled_ops[0],
9e986b97 3070 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
6a1254af 3071 },
06d74950 3072/* bgt $label9 */
6a1254af
DB		 3073 {
3074 { 1, 1, 1, 1 },
06d74950 3075 FR30_INSN_BGT, "bgt", "bgt",
6a1254af 3076 { { MNEM, ' ', OP (LABEL9), 0 } },
06d74950
DB		 3077 & fmt_bled, { 0xed00 },
3078 (PTR) & fmt_bled_ops[0],
7862c6cf 3079 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
6a1254af 3080 },
ac1b0e6d 3081/* bls:d $label9 */
6a1254af
DB		 3082 {
3083 { 1, 1, 1, 1 },
ac1b0e6d 3084 FR30_INSN_BLSD, "blsd", "bls:d",
6a1254af 3085 { { MNEM, ' ', OP (LABEL9), 0 } },
06d74950
DB		 3086 & fmt_blsd, { 0xfe00 },
3087 (PTR) & fmt_blsd_ops[0],
9e986b97 3088 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
6a1254af 3089 },
06d74950 3090/* bls $label9 */
6a1254af
DB		 3091 {
3092 { 1, 1, 1, 1 },
06d74950 3093 FR30_INSN_BLS, "bls", "bls",
6a1254af 3094 { { MNEM, ' ', OP (LABEL9), 0 } },
06d74950
DB		 3095 & fmt_blsd, { 0xee00 },
3096 (PTR) & fmt_blsd_ops[0],
7862c6cf 3097 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
6a1254af 3098 },
ac1b0e6d 3099/* bhi:d $label9 */
6a1254af
DB		 3100 {
3101 { 1, 1, 1, 1 },
ac1b0e6d 3102 FR30_INSN_BHID, "bhid", "bhi:d",
6a1254af 3103 { { MNEM, ' ', OP (LABEL9), 0 } },
06d74950
DB		 3104 & fmt_blsd, { 0xff00 },
3105 (PTR) & fmt_blsd_ops[0],
9e986b97 3106 { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
6a1254af 3107 },
06d74950
DB		 3108/* bhi $label9 */
3109 {
3110 { 1, 1, 1, 1 },
3111 FR30_INSN_BHI, "bhi", "bhi",
3112 { { MNEM, ' ', OP (LABEL9), 0 } },
3113 & fmt_blsd, { 0xef00 },
3114 (PTR) & fmt_blsd_ops[0],
3115 { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
3116 },
e17387a5 3117/* dmov $R13,@$dir10 */
7a0737c8
DB		 3118 {
3119 { 1, 1, 1, 1 },
e17387a5
DB		 3120 FR30_INSN_DMOVR13, "dmovr13", "dmov",
3121 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR10), 0 } },
a73911a7 3122 & fmt_dmovr13, { 0x1800 },
9e986b97 3123 (PTR) & fmt_dmovr13_ops[0],
7a0737c8
DB		 3124 { 0, 0, { 0 } }
3125 },
e17387a5 3126/* dmovh $R13,@$dir9 */
7a0737c8
DB		 3127 {
3128 { 1, 1, 1, 1 },
e17387a5
DB		 3129 FR30_INSN_DMOVR13H, "dmovr13h", "dmovh",
3130 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR9), 0 } },
a73911a7 3131 & fmt_dmovr13h, { 0x1900 },
9e986b97 3132 (PTR) & fmt_dmovr13h_ops[0],
7a0737c8
DB		 3133 { 0, 0, { 0 } }
3134 },
e17387a5 3135/* dmovb $R13,@$dir8 */
7a0737c8
DB		 3136 {
3137 { 1, 1, 1, 1 },
e17387a5
DB		 3138 FR30_INSN_DMOVR13B, "dmovr13b", "dmovb",
3139 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR8), 0 } },
a73911a7 3140 & fmt_dmovr13b, { 0x1a00 },
9e986b97 3141 (PTR) & fmt_dmovr13b_ops[0],
7a0737c8
DB		 3142 { 0, 0, { 0 } }
3143 },
e17387a5 3144/* dmov @$R13+,@$dir10 */
7a0737c8
DB		 3145 {
3146 { 1, 1, 1, 1 },
e17387a5
DB		 3147 FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov",
3148 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR10), 0 } },
9e986b97
DB		 3149 & fmt_dmovr13pi, { 0x1c00 },
3150 (PTR) & fmt_dmovr13pi_ops[0],
6a12a5f3 3151 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
7a0737c8 3152 },
e17387a5 3153/* dmovh @$R13+,@$dir9 */
7a0737c8
DB		 3154 {
3155 { 1, 1, 1, 1 },
e17387a5
DB		 3156 FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh",
3157 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR9), 0 } },
9e986b97
DB		 3158 & fmt_dmovr13pih, { 0x1d00 },
3159 (PTR) & fmt_dmovr13pih_ops[0],
6a12a5f3 3160 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
7a0737c8 3161 },
e17387a5 3162/* dmovb @$R13+,@$dir8 */
7a0737c8
DB		 3163 {
3164 { 1, 1, 1, 1 },
e17387a5
DB		 3165 FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb",
3166 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR8), 0 } },
9e986b97
DB		 3167 & fmt_dmovr13pib, { 0x1e00 },
3168 (PTR) & fmt_dmovr13pib_ops[0],
6a12a5f3 3169 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
e17387a5
DB		 3170 },
3171/* dmov @$R15+,@$dir10 */
3172 {
3173 { 1, 1, 1, 1 },
3174 FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov",
3175 { { MNEM, ' ', '@', OP (R15), '+', ',', '@', OP (DIR10), 0 } },
9e986b97
DB		 3176 & fmt_dmovr15pi, { 0x1b00 },
3177 (PTR) & fmt_dmovr15pi_ops[0],
6a12a5f3 3178 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
e17387a5
DB		 3179 },
3180/* dmov @$dir10,$R13 */
3181 {
3182 { 1, 1, 1, 1 },
3183 FR30_INSN_DMOV2R13, "dmov2r13", "dmov",
3184 { { MNEM, ' ', '@', OP (DIR10), ',', OP (R13), 0 } },
9e986b97
DB		 3185 & fmt_dmov2r13, { 0x800 },
3186 (PTR) & fmt_dmov2r13_ops[0],
e17387a5
DB		 3187 { 0, 0, { 0 } }
3188 },
3189/* dmovh @$dir9,$R13 */
3190 {
3191 { 1, 1, 1, 1 },
3192 FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh",
3193 { { MNEM, ' ', '@', OP (DIR9), ',', OP (R13), 0 } },
9e986b97
DB		 3194 & fmt_dmov2r13h, { 0x900 },
3195 (PTR) & fmt_dmov2r13h_ops[0],
e17387a5
DB		 3196 { 0, 0, { 0 } }
3197 },
3198/* dmovb @$dir8,$R13 */
3199 {
3200 { 1, 1, 1, 1 },
3201 FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb",
3202 { { MNEM, ' ', '@', OP (DIR8), ',', OP (R13), 0 } },
9e986b97
DB		 3203 & fmt_dmov2r13b, { 0xa00 },
3204 (PTR) & fmt_dmov2r13b_ops[0],
7a0737c8
DB		 3205 { 0, 0, { 0 } }
3206 },
6a1254af 3207/* dmov @$dir10,@$R13+ */
7a0737c8
DB		 3208 {
3209 { 1, 1, 1, 1 },
3210 FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov",
6a1254af 3211 { { MNEM, ' ', '@', OP (DIR10), ',', '@', OP (R13), '+', 0 } },
9e986b97
DB		 3212 & fmt_dmov2r13pi, { 0xc00 },
3213 (PTR) & fmt_dmov2r13pi_ops[0],
6a12a5f3 3214 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
7a0737c8 3215 },
6a1254af 3216/* dmovh @$dir9,@$R13+ */
7a0737c8
DB		 3217 {
3218 { 1, 1, 1, 1 },
3219 FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh",
6a1254af 3220 { { MNEM, ' ', '@', OP (DIR9), ',', '@', OP (R13), '+', 0 } },
9e986b97
DB		 3221 & fmt_dmov2r13pih, { 0xd00 },
3222 (PTR) & fmt_dmov2r13pih_ops[0],
6a12a5f3 3223 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
7a0737c8 3224 },
6a1254af 3225/* dmovb @$dir8,@$R13+ */
7a0737c8
DB		 3226 {
3227 { 1, 1, 1, 1 },
3228 FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb",
6a1254af 3229 { { MNEM, ' ', '@', OP (DIR8), ',', '@', OP (R13), '+', 0 } },
9e986b97
DB		 3230 & fmt_dmov2r13pib, { 0xe00 },
3231 (PTR) & fmt_dmov2r13pib_ops[0],
6a12a5f3 3232 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
7a0737c8 3233 },
e17387a5 3234/* dmov @$dir10,@-$R15 */
7a0737c8
DB		 3235 {
3236 { 1, 1, 1, 1 },
e17387a5
DB		 3237 FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov",
3238 { { MNEM, ' ', '@', OP (DIR10), ',', '@', '-', OP (R15), 0 } },
9e986b97
DB		 3239 & fmt_dmov2r15pd, { 0xb00 },
3240 (PTR) & fmt_dmov2r15pd_ops[0],
6a12a5f3 3241 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
7a0737c8 3242 },
e17387a5 3243/* ldres @$Ri+,$u4 */
7a0737c8
DB		 3244 {
3245 { 1, 1, 1, 1 },
e17387a5
DB		 3246 FR30_INSN_LDRES, "ldres", "ldres",
3247 { { MNEM, ' ', '@', OP (RI), '+', ',', OP (U4), 0 } },
7862c6cf 3248 & fmt_ldres, { 0xbc00 },
6a12a5f3 3249 (PTR) & fmt_ldres_ops[0],
7a0737c8
DB		 3250 { 0, 0, { 0 } }
3251 },
e17387a5 3252/* stres $u4,@$Ri+ */
7a0737c8
DB		 3253 {
3254 { 1, 1, 1, 1 },
e17387a5
DB		 3255 FR30_INSN_STRES, "stres", "stres",
3256 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), '+', 0 } },
7862c6cf 3257 & fmt_ldres, { 0xbd00 },
6a12a5f3 3258 (PTR) & fmt_ldres_ops[0],
7a0737c8
DB		 3259 { 0, 0, { 0 } }
3260 },
e17387a5 3261/* copop $u4c,$ccc,$CRj,$CRi */
7a0737c8
DB		 3262 {
3263 { 1, 1, 1, 1 },
e17387a5
DB		 3264 FR30_INSN_COPOP, "copop", "copop",
3265 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (CRI), 0 } },
a73911a7 3266 & fmt_copop, { 0x9fc0 },
7a0737c8 3267 (PTR) 0,
6a12a5f3 3268 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
7a0737c8 3269 },
e17387a5 3270/* copld $u4c,$ccc,$Rjc,$CRi */
7a0737c8
DB		 3271 {
3272 { 1, 1, 1, 1 },
e17387a5
DB		 3273 FR30_INSN_COPLD, "copld", "copld",
3274 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (RJC), ',', OP (CRI), 0 } },
a73911a7 3275 & fmt_copld, { 0x9fd0 },
7a0737c8 3276 (PTR) 0,
6a12a5f3 3277 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
7a0737c8 3278 },
e17387a5 3279/* copst $u4c,$ccc,$CRj,$Ric */
7a0737c8
DB		 3280 {
3281 { 1, 1, 1, 1 },
e17387a5
DB		 3282 FR30_INSN_COPST, "copst", "copst",
3283 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } },
a73911a7 3284 & fmt_copst, { 0x9fe0 },
7a0737c8 3285 (PTR) 0,
6a12a5f3 3286 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
7a0737c8 3287 },
e17387a5 3288/* copsv $u4c,$ccc,$CRj,$Ric */
7a0737c8
DB		 3289 {
3290 { 1, 1, 1, 1 },
e17387a5
DB		 3291 FR30_INSN_COPSV, "copsv", "copsv",
3292 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } },
a73911a7 3293 & fmt_copst, { 0x9ff0 },
7a0737c8 3294 (PTR) 0,
6a12a5f3 3295 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
7a0737c8
DB		 3296 },
3297/* nop */
3298 {
3299 { 1, 1, 1, 1 },
3300 FR30_INSN_NOP, "nop", "nop",
3301 { { MNEM, 0 } },
767d2de5 3302 & fmt_nop, { 0x9fa0 },
7a0737c8
DB		 3303 (PTR) 0,
3304 { 0, 0, { 0 } }
3305 },
3306/* andccr $u8 */
3307 {
3308 { 1, 1, 1, 1 },
3309 FR30_INSN_ANDCCR, "andccr", "andccr",
3310 { { MNEM, ' ', OP (U8), 0 } },
a73911a7 3311 & fmt_andccr, { 0x8300 },
7862c6cf 3312 (PTR) & fmt_andccr_ops[0],
7a0737c8
DB		 3313 { 0, 0, { 0 } }
3314 },
3315/* orccr $u8 */
3316 {
3317 { 1, 1, 1, 1 },
3318 FR30_INSN_ORCCR, "orccr", "orccr",
3319 { { MNEM, ' ', OP (U8), 0 } },
a73911a7 3320 & fmt_andccr, { 0x9300 },
7862c6cf 3321 (PTR) & fmt_andccr_ops[0],
7a0737c8
DB		 3322 { 0, 0, { 0 } }
3323 },
3324/* stilm $u8 */
3325 {
3326 { 1, 1, 1, 1 },
3327 FR30_INSN_STILM, "stilm", "stilm",
3328 { { MNEM, ' ', OP (U8), 0 } },
7862c6cf 3329 & fmt_stilm, { 0x8700 },
9e986b97 3330 (PTR) & fmt_stilm_ops[0],
7a0737c8
DB		 3331 { 0, 0, { 0 } }
3332 },
3333/* addsp $s10 */
3334 {
3335 { 1, 1, 1, 1 },
3336 FR30_INSN_ADDSP, "addsp", "addsp",
3337 { { MNEM, ' ', OP (S10), 0 } },
a73911a7 3338 & fmt_addsp, { 0xa300 },
9e986b97 3339 (PTR) & fmt_addsp_ops[0],
7a0737c8
DB		 3340 { 0, 0, { 0 } }
3341 },
3342/* extsb $Ri */
3343 {
3344 { 1, 1, 1, 1 },
3345 FR30_INSN_EXTSB, "extsb", "extsb",
3346 { { MNEM, ' ', OP (RI), 0 } },
9e986b97
DB		 3347 & fmt_extsb, { 0x9780 },
3348 (PTR) & fmt_extsb_ops[0],
7a0737c8
DB		 3349 { 0, 0, { 0 } }
3350 },
3351/* extub $Ri */
3352 {
3353 { 1, 1, 1, 1 },
3354 FR30_INSN_EXTUB, "extub", "extub",
3355 { { MNEM, ' ', OP (RI), 0 } },
9e986b97
DB		 3356 & fmt_extub, { 0x9790 },
3357 (PTR) & fmt_extub_ops[0],
7a0737c8
DB		 3358 { 0, 0, { 0 } }
3359 },
3360/* extsh $Ri */
3361 {
3362 { 1, 1, 1, 1 },
3363 FR30_INSN_EXTSH, "extsh", "extsh",
3364 { { MNEM, ' ', OP (RI), 0 } },
9e986b97
DB		 3365 & fmt_extsh, { 0x97a0 },
3366 (PTR) & fmt_extsh_ops[0],
7a0737c8
DB		 3367 { 0, 0, { 0 } }
3368 },
3369/* extuh $Ri */
3370 {
3371 { 1, 1, 1, 1 },
3372 FR30_INSN_EXTUH, "extuh", "extuh",
3373 { { MNEM, ' ', OP (RI), 0 } },
9e986b97
DB		 3374 & fmt_extuh, { 0x97b0 },
3375 (PTR) & fmt_extuh_ops[0],
7a0737c8
DB		 3376 { 0, 0, { 0 } }
3377 },
bfebcfbf 3378/* ldm0 ($reglist_low_ld) */
e17387a5
DB		 3379 {
3380 { 1, 1, 1, 1 },
3381 FR30_INSN_LDM0, "ldm0", "ldm0",
bfebcfbf 3382 { { MNEM, ' ', '(', OP (REGLIST_LOW_LD), ')', 0 } },
a73911a7 3383 & fmt_ldm0, { 0x8c00 },
bfebcfbf 3384 (PTR) & fmt_ldm0_ops[0],
6a12a5f3 3385 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
e17387a5 3386 },
bfebcfbf 3387/* ldm1 ($reglist_hi_ld) */
e17387a5
DB		 3388 {
3389 { 1, 1, 1, 1 },
3390 FR30_INSN_LDM1, "ldm1", "ldm1",
bfebcfbf 3391 { { MNEM, ' ', '(', OP (REGLIST_HI_LD), ')', 0 } },
a73911a7 3392 & fmt_ldm1, { 0x8d00 },
bfebcfbf 3393 (PTR) & fmt_ldm1_ops[0],
6a12a5f3 3394 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
e17387a5 3395 },
bfebcfbf 3396/* stm0 ($reglist_low_st) */
e17387a5
DB		 3397 {
3398 { 1, 1, 1, 1 },
3399 FR30_INSN_STM0, "stm0", "stm0",
bfebcfbf 3400 { { MNEM, ' ', '(', OP (REGLIST_LOW_ST), ')', 0 } },
9e986b97
DB		 3401 & fmt_stm0, { 0x8e00 },
3402 (PTR) & fmt_stm0_ops[0],
6a12a5f3 3403 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
e17387a5 3404 },
bfebcfbf 3405/* stm1 ($reglist_hi_st) */
e17387a5
DB		 3406 {
3407 { 1, 1, 1, 1 },
3408 FR30_INSN_STM1, "stm1", "stm1",
bfebcfbf
DB		 3409 { { MNEM, ' ', '(', OP (REGLIST_HI_ST), ')', 0 } },
3410 & fmt_stm1, { 0x8f00 },
3411 (PTR) & fmt_stm1_ops[0],
6a12a5f3 3412 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
e17387a5 3413 },
7a0737c8
DB		 3414/* enter $u10 */
3415 {
3416 { 1, 1, 1, 1 },
3417 FR30_INSN_ENTER, "enter", "enter",
3418 { { MNEM, ' ', OP (U10), 0 } },
a73911a7 3419 & fmt_enter, { 0xf00 },
9e986b97 3420 (PTR) & fmt_enter_ops[0],
6a12a5f3 3421 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
7a0737c8
DB		 3422 },
3423/* leave */
3424 {
3425 { 1, 1, 1, 1 },
3426 FR30_INSN_LEAVE, "leave", "leave",
3427 { { MNEM, 0 } },
9e986b97
DB		 3428 & fmt_leave, { 0x9f90 },
3429 (PTR) & fmt_leave_ops[0],
7a0737c8
DB		 3430 { 0, 0, { 0 } }
3431 },
3432/* xchb @$Rj,$Ri */
3433 {
3434 { 1, 1, 1, 1 },
3435 FR30_INSN_XCHB, "xchb", "xchb",
3436 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
ac1b0e6d 3437 & fmt_xchb, { 0x8a00 },
9e986b97 3438 (PTR) & fmt_xchb_ops[0],
6a12a5f3 3439 { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
a86481d3
DB		 3440 },
3441};
3442
3443#undef A
3444#undef MNEM
3445#undef OP
3446
3447static const CGEN_INSN_TABLE insn_table =
3448{
3449 & fr30_cgen_insn_table_entries[0],
3450 sizeof (CGEN_INSN),
3451 MAX_INSNS,
3452 NULL
3453};
3454
a73911a7
DE		 3455/* Formats for ALIAS macro-insns. */
3456
3457#define F(f) & fr30_cgen_ifld_table[CONCAT2 (FR30_,f)]
3458
7862c6cf
DB		 3459static const CGEN_IFMT fmt_ldi8m = {
3460 16, 16, 0xf000, { F (F_OP1), F (F_I8), F (F_RI), 0 }
3461};
3462
3463static const CGEN_IFMT fmt_ldi20m = {
3464 16, 32, 0xff00, { F (F_OP1), F (F_I20), F (F_OP2), F (F_RI), 0 }
3465};
3466
3467static const CGEN_IFMT fmt_ldi32m = {
3468 16, 48, 0xfff0, { F (F_OP1), F (F_I32), F (F_OP2), F (F_OP3), F (F_RI), 0 }
3469};
3470
a73911a7
DE		 3471#undef F
3472
a86481d3
DB		 3473/* Each non-simple macro entry points to an array of expansion possibilities. */
3474
3475#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
3476#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
3477#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
3478
3479/* The macro instruction table. */
3480
3481static const CGEN_INSN macro_insn_table_entries[] =
3482{
7862c6cf
DB		 3483/* ldi8 $i8,$Ri */
3484 {
3485 { 1, 1, 1, 1 },
3486 -1, "ldi8m", "ldi8",
3487 { { MNEM, ' ', OP (I8), ',', OP (RI), 0 } },
3488 & fmt_ldi8m, { 0xc000 },
3489 (PTR) 0,
3490 { 0, 0|A(NO_DIS)|A(ALIAS), { 0 } }
3491 },
3492/* ldi20 $i20,$Ri */
3493 {
3494 { 1, 1, 1, 1 },
3495 -1, "ldi20m", "ldi20",
3496 { { MNEM, ' ', OP (I20), ',', OP (RI), 0 } },
3497 & fmt_ldi20m, { 0x9b00 },
3498 (PTR) 0,
3499 { 0, 0|A(NO_DIS)|A(ALIAS), { 0 } }
3500 },
3501/* ldi32 $i32,$Ri */
3502 {
3503 { 1, 1, 1, 1 },
3504 -1, "ldi32m", "ldi32",
3505 { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
3506 & fmt_ldi32m, { 0x9f80 },
3507 (PTR) 0,
3508 { 0, 0|A(NO_DIS)|A(ALIAS), { 0 } }
3509 },
a86481d3
DB		 3510};
3511
3512#undef A
3513#undef MNEM
3514#undef OP
3515
3516static const CGEN_INSN_TABLE macro_insn_table =
3517{
3518 & macro_insn_table_entries[0],
3519 sizeof (CGEN_INSN),
3520 (sizeof (macro_insn_table_entries) /
3521 sizeof (macro_insn_table_entries[0])),
3522 NULL
3523};
3524
3525static void
3526init_tables ()
3527{
3528}
3529
3530/* Return non-zero if INSN is to be added to the hash table.
3531 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
3532
3533static int
3534asm_hash_insn_p (insn)
3535 const CGEN_INSN * insn;
3536{
3537 return CGEN_ASM_HASH_P (insn);
3538}
3539
3540static int
3541dis_hash_insn_p (insn)
3542 const CGEN_INSN * insn;
3543{
3544 /* If building the hash table and the NO-DIS attribute is present,
3545 ignore. */
3546 if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
3547 return 0;
3548 return CGEN_DIS_HASH_P (insn);
3549}
3550
3551/* The result is the hash value of the insn.
3552 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
3553
3554static unsigned int
3555asm_hash_insn (mnem)
3556 const char * mnem;
3557{
3558 return CGEN_ASM_HASH (mnem);
3559}
3560
3561/* BUF is a pointer to the insn's bytes in target order.
3562 VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
3563 host order. */
3564
3565static unsigned int
3566dis_hash_insn (buf, value)
3567 const char * buf;
95b03313 3568 CGEN_INSN_INT value;
a86481d3
DB		 3569{
3570 return CGEN_DIS_HASH (buf, value);
3571}
3572
3573/* Initialize an opcode table and return a descriptor.
3574 It's much like opening a file, and must be the first function called. */
3575
3576CGEN_OPCODE_DESC
3577fr30_cgen_opcode_open (mach, endian)
3578 int mach;
3579 enum cgen_endian endian;
3580{
3581 CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE));
3582 static int init_p;
3583
3584 if (! init_p)
3585 {
3586 init_tables ();
3587 init_p = 1;
3588 }
3589
3590 memset (table, 0, sizeof (*table));
3591
3592 CGEN_OPCODE_MACH (table) = mach;
3593 CGEN_OPCODE_ENDIAN (table) = endian;
3594 /* FIXME: for the sparc case we can determine insn-endianness statically.
3595 The worry here is where both data and insn endian can be independently
3596 chosen, in which case this function will need another argument.
3597 Actually, will want to allow for more arguments in the future anyway. */
3598 CGEN_OPCODE_INSN_ENDIAN (table) = endian;
3599
3600 CGEN_OPCODE_HW_LIST (table) = & fr30_cgen_hw_entries[0];
3601
a73911a7
DE		 3602 CGEN_OPCODE_IFLD_TABLE (table) = & fr30_cgen_ifld_table[0];
3603
a86481d3
DB		 3604 CGEN_OPCODE_OPERAND_TABLE (table) = & fr30_cgen_operand_table[0];
3605
3606 * CGEN_OPCODE_INSN_TABLE (table) = insn_table;
3607
3608 * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table;
3609
3610 CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p;
3611 CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn;
3612 CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE;
3613
3614 CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p;
3615 CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn;
3616 CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE;
3617
3618 return (CGEN_OPCODE_DESC) table;
3619}
3620
3621/* Close an opcode table. */
3622
3623void
3624fr30_cgen_opcode_close (desc)
3625 CGEN_OPCODE_DESC desc;
3626{
3627 free (desc);
3628}
3629
3630/* Getting values from cgen_fields is handled by a collection of functions.
3631 They are distinguished by the type of the VALUE argument they return.
3632 TODO: floating point, inlining support, remove cases where result type
3633 not appropriate. */
3634
3635int
3636fr30_cgen_get_int_operand (opindex, fields)
3637 int opindex;
3638 const CGEN_FIELDS * fields;
3639{
3640 int value;
3641
3642 switch (opindex)
3643 {
3644 case FR30_OPERAND_RI :
3645 value = fields->f_Ri;
3646 break;
3647 case FR30_OPERAND_RJ :
3648 value = fields->f_Rj;
3649 break;
e17387a5
DB		 3650 case FR30_OPERAND_RIC :
3651 value = fields->f_Ric;
3652 break;
3653 case FR30_OPERAND_RJC :
3654 value = fields->f_Rjc;
3655 break;
3656 case FR30_OPERAND_CRI :
3657 value = fields->f_CRi;
3658 break;
3659 case FR30_OPERAND_CRJ :
3660 value = fields->f_CRj;
3661 break;
7a0737c8
DB		 3662 case FR30_OPERAND_RS1 :
3663 value = fields->f_Rs1;
3664 break;
3665 case FR30_OPERAND_RS2 :
3666 value = fields->f_Rs2;
3667 break;
6a1254af
DB		 3668 case FR30_OPERAND_R13 :
3669 value = fields->f_nil;
3670 break;
3671 case FR30_OPERAND_R14 :
3672 value = fields->f_nil;
3673 break;
3674 case FR30_OPERAND_R15 :
3675 value = fields->f_nil;
3676 break;
3677 case FR30_OPERAND_PS :
3678 value = fields->f_nil;
3679 break;
7a0737c8
DB		 3680 case FR30_OPERAND_U4 :
3681 value = fields->f_u4;
3682 break;
e17387a5
DB		 3683 case FR30_OPERAND_U4C :
3684 value = fields->f_u4c;
3685 break;
6a1254af
DB		 3686 case FR30_OPERAND_U8 :
3687 value = fields->f_u8;
3688 break;
7a0737c8
DB		 3689 case FR30_OPERAND_I8 :
3690 value = fields->f_i8;
3691 break;
6a1254af
DB		 3692 case FR30_OPERAND_UDISP6 :
3693 value = fields->f_udisp6;
7a0737c8 3694 break;
6a1254af
DB		 3695 case FR30_OPERAND_DISP8 :
3696 value = fields->f_disp8;
3697 break;
3698 case FR30_OPERAND_DISP9 :
3699 value = fields->f_disp9;
3700 break;
3701 case FR30_OPERAND_DISP10 :
3702 value = fields->f_disp10;
7a0737c8
DB		 3703 break;
3704 case FR30_OPERAND_S10 :
3705 value = fields->f_s10;
3706 break;
3707 case FR30_OPERAND_U10 :
3708 value = fields->f_u10;
3709 break;
95b03313
DE		 3710 case FR30_OPERAND_I32 :
3711 value = fields->f_i32;
3712 break;
7862c6cf
DB		 3713 case FR30_OPERAND_M4 :
3714 value = fields->f_m4;
3715 break;
a73911a7
DE		 3716 case FR30_OPERAND_I20 :
3717 value = fields->f_i20;
3718 break;
7a0737c8
DB		 3719 case FR30_OPERAND_DIR8 :
3720 value = fields->f_dir8;
3721 break;
3722 case FR30_OPERAND_DIR9 :
3723 value = fields->f_dir9;
3724 break;
3725 case FR30_OPERAND_DIR10 :
3726 value = fields->f_dir10;
3727 break;
ac1b0e6d
DB		 3728 case FR30_OPERAND_LABEL9 :
3729 value = fields->f_rel9;
3730 break;
7a0737c8 3731 case FR30_OPERAND_LABEL12 :
6a1254af 3732 value = fields->f_rel12;
7a0737c8 3733 break;
bfebcfbf
DB		 3734 case FR30_OPERAND_REGLIST_LOW_LD :
3735 value = fields->f_reglist_low_ld;
e17387a5 3736 break;
bfebcfbf
DB		 3737 case FR30_OPERAND_REGLIST_HI_LD :
3738 value = fields->f_reglist_hi_ld;
3739 break;
3740 case FR30_OPERAND_REGLIST_LOW_ST :
3741 value = fields->f_reglist_low_st;
3742 break;
3743 case FR30_OPERAND_REGLIST_HI_ST :
3744 value = fields->f_reglist_hi_st;
e17387a5 3745 break;
7a0737c8
DB		 3746 case FR30_OPERAND_CC :
3747 value = fields->f_cc;
3748 break;
e17387a5
DB		 3749 case FR30_OPERAND_CCC :
3750 value = fields->f_ccc;
3751 break;
a86481d3
DB		 3752
3753 default :
3754 /* xgettext:c-format */
3755 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
3756 opindex);
3757 abort ();
3758 }
3759
3760 return value;
3761}
3762
3763bfd_vma
3764fr30_cgen_get_vma_operand (opindex, fields)
3765 int opindex;
3766 const CGEN_FIELDS * fields;
3767{
3768 bfd_vma value;
3769
3770 switch (opindex)
3771 {
3772 case FR30_OPERAND_RI :
3773 value = fields->f_Ri;
3774 break;
3775 case FR30_OPERAND_RJ :
3776 value = fields->f_Rj;
3777 break;
e17387a5
DB		 3778 case FR30_OPERAND_RIC :
3779 value = fields->f_Ric;
3780 break;
3781 case FR30_OPERAND_RJC :
3782 value = fields->f_Rjc;
3783 break;
3784 case FR30_OPERAND_CRI :
3785 value = fields->f_CRi;
3786 break;
3787 case FR30_OPERAND_CRJ :
3788 value = fields->f_CRj;
3789 break;
7a0737c8
DB		 3790 case FR30_OPERAND_RS1 :
3791 value = fields->f_Rs1;
3792 break;
3793 case FR30_OPERAND_RS2 :
3794 value = fields->f_Rs2;
3795 break;
6a1254af
DB		 3796 case FR30_OPERAND_R13 :
3797 value = fields->f_nil;
3798 break;
3799 case FR30_OPERAND_R14 :
3800 value = fields->f_nil;
3801 break;
3802 case FR30_OPERAND_R15 :
3803 value = fields->f_nil;
3804 break;
3805 case FR30_OPERAND_PS :
3806 value = fields->f_nil;
3807 break;
7a0737c8
DB		 3808 case FR30_OPERAND_U4 :
3809 value = fields->f_u4;
3810 break;
e17387a5
DB		 3811 case FR30_OPERAND_U4C :
3812 value = fields->f_u4c;
3813 break;
6a1254af
DB		 3814 case FR30_OPERAND_U8 :
3815 value = fields->f_u8;
3816 break;
7a0737c8
DB		 3817 case FR30_OPERAND_I8 :
3818 value = fields->f_i8;
3819 break;
6a1254af
DB		 3820 case FR30_OPERAND_UDISP6 :
3821 value = fields->f_udisp6;
7a0737c8 3822 break;
6a1254af
DB		 3823 case FR30_OPERAND_DISP8 :
3824 value = fields->f_disp8;
3825 break;
3826 case FR30_OPERAND_DISP9 :
3827 value = fields->f_disp9;
3828 break;
3829 case FR30_OPERAND_DISP10 :
3830 value = fields->f_disp10;
7a0737c8
DB		 3831 break;
3832 case FR30_OPERAND_S10 :
3833 value = fields->f_s10;
3834 break;
3835 case FR30_OPERAND_U10 :
3836 value = fields->f_u10;
3837 break;
95b03313
DE		 3838 case FR30_OPERAND_I32 :
3839 value = fields->f_i32;
3840 break;
7862c6cf
DB		 3841 case FR30_OPERAND_M4 :
3842 value = fields->f_m4;
3843 break;
a73911a7
DE		 3844 case FR30_OPERAND_I20 :
3845 value = fields->f_i20;
3846 break;
7a0737c8
DB		 3847 case FR30_OPERAND_DIR8 :
3848 value = fields->f_dir8;
3849 break;
3850 case FR30_OPERAND_DIR9 :
3851 value = fields->f_dir9;
3852 break;
3853 case FR30_OPERAND_DIR10 :
3854 value = fields->f_dir10;
3855 break;
ac1b0e6d
DB		 3856 case FR30_OPERAND_LABEL9 :
3857 value = fields->f_rel9;
3858 break;
7a0737c8 3859 case FR30_OPERAND_LABEL12 :
6a1254af 3860 value = fields->f_rel12;
7a0737c8 3861 break;
bfebcfbf
DB		 3862 case FR30_OPERAND_REGLIST_LOW_LD :
3863 value = fields->f_reglist_low_ld;
3864 break;
3865 case FR30_OPERAND_REGLIST_HI_LD :
3866 value = fields->f_reglist_hi_ld;
3867 break;
3868 case FR30_OPERAND_REGLIST_LOW_ST :
3869 value = fields->f_reglist_low_st;
e17387a5 3870 break;
bfebcfbf
DB		 3871 case FR30_OPERAND_REGLIST_HI_ST :
3872 value = fields->f_reglist_hi_st;
e17387a5 3873 break;
7a0737c8
DB		 3874 case FR30_OPERAND_CC :
3875 value = fields->f_cc;
3876 break;
e17387a5
DB		 3877 case FR30_OPERAND_CCC :
3878 value = fields->f_ccc;
3879 break;
a86481d3
DB		 3880
3881 default :
3882 /* xgettext:c-format */
3883 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
3884 opindex);
3885 abort ();
3886 }
3887
3888 return value;
3889}
3890
3891/* Stuffing values in cgen_fields is handled by a collection of functions.
3892 They are distinguished by the type of the VALUE argument they accept.
3893 TODO: floating point, inlining support, remove cases where argument type
3894 not appropriate. */
3895
3896void
3897fr30_cgen_set_int_operand (opindex, fields, value)
3898 int opindex;
3899 CGEN_FIELDS * fields;
3900 int value;
3901{
3902 switch (opindex)
3903 {
3904 case FR30_OPERAND_RI :
3905 fields->f_Ri = value;
3906 break;
3907 case FR30_OPERAND_RJ :
3908 fields->f_Rj = value;
3909 break;
e17387a5
DB		 3910 case FR30_OPERAND_RIC :
3911 fields->f_Ric = value;
3912 break;
3913 case FR30_OPERAND_RJC :
3914 fields->f_Rjc = value;
3915 break;
3916 case FR30_OPERAND_CRI :
3917 fields->f_CRi = value;
3918 break;
3919 case FR30_OPERAND_CRJ :
3920 fields->f_CRj = value;
3921 break;
7a0737c8
DB		 3922 case FR30_OPERAND_RS1 :
3923 fields->f_Rs1 = value;
3924 break;
3925 case FR30_OPERAND_RS2 :
3926 fields->f_Rs2 = value;
3927 break;
6a1254af
DB		 3928 case FR30_OPERAND_R13 :
3929 fields->f_nil = value;
3930 break;
3931 case FR30_OPERAND_R14 :
3932 fields->f_nil = value;
3933 break;
3934 case FR30_OPERAND_R15 :
3935 fields->f_nil = value;
3936 break;
3937 case FR30_OPERAND_PS :
3938 fields->f_nil = value;
3939 break;
7a0737c8
DB		 3940 case FR30_OPERAND_U4 :
3941 fields->f_u4 = value;
3942 break;
e17387a5
DB		 3943 case FR30_OPERAND_U4C :
3944 fields->f_u4c = value;
3945 break;
6a1254af
DB		 3946 case FR30_OPERAND_U8 :
3947 fields->f_u8 = value;
3948 break;
7a0737c8
DB		 3949 case FR30_OPERAND_I8 :
3950 fields->f_i8 = value;
3951 break;
6a1254af
DB		 3952 case FR30_OPERAND_UDISP6 :
3953 fields->f_udisp6 = value;
3954 break;
3955 case FR30_OPERAND_DISP8 :
3956 fields->f_disp8 = value;
7a0737c8 3957 break;
6a1254af
DB		 3958 case FR30_OPERAND_DISP9 :
3959 fields->f_disp9 = value;
3960 break;
3961 case FR30_OPERAND_DISP10 :
3962 fields->f_disp10 = value;
7a0737c8
DB		 3963 break;
3964 case FR30_OPERAND_S10 :
3965 fields->f_s10 = value;
3966 break;
3967 case FR30_OPERAND_U10 :
3968 fields->f_u10 = value;
3969 break;
95b03313
DE		 3970 case FR30_OPERAND_I32 :
3971 fields->f_i32 = value;
3972 break;
7862c6cf
DB		 3973 case FR30_OPERAND_M4 :
3974 fields->f_m4 = value;
3975 break;
a73911a7
DE		 3976 case FR30_OPERAND_I20 :
3977 fields->f_i20 = value;
3978 break;
7a0737c8
DB		 3979 case FR30_OPERAND_DIR8 :
3980 fields->f_dir8 = value;
3981 break;
3982 case FR30_OPERAND_DIR9 :
3983 fields->f_dir9 = value;
3984 break;
3985 case FR30_OPERAND_DIR10 :
3986 fields->f_dir10 = value;
3987 break;
ac1b0e6d
DB		 3988 case FR30_OPERAND_LABEL9 :
3989 fields->f_rel9 = value;
3990 break;
7a0737c8 3991 case FR30_OPERAND_LABEL12 :
6a1254af 3992 fields->f_rel12 = value;
7a0737c8 3993 break;
bfebcfbf
DB		 3994 case FR30_OPERAND_REGLIST_LOW_LD :
3995 fields->f_reglist_low_ld = value;
e17387a5 3996 break;
bfebcfbf
DB		 3997 case FR30_OPERAND_REGLIST_HI_LD :
3998 fields->f_reglist_hi_ld = value;
3999 break;
4000 case FR30_OPERAND_REGLIST_LOW_ST :
4001 fields->f_reglist_low_st = value;
4002 break;
4003 case FR30_OPERAND_REGLIST_HI_ST :
4004 fields->f_reglist_hi_st = value;
e17387a5 4005 break;
7a0737c8
DB		 4006 case FR30_OPERAND_CC :
4007 fields->f_cc = value;
4008 break;
e17387a5
DB		 4009 case FR30_OPERAND_CCC :
4010 fields->f_ccc = value;
4011 break;
a86481d3
DB		 4012
4013 default :
4014 /* xgettext:c-format */
4015 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
4016 opindex);
4017 abort ();
4018 }
4019}
4020
4021void
4022fr30_cgen_set_vma_operand (opindex, fields, value)
4023 int opindex;
4024 CGEN_FIELDS * fields;
4025 bfd_vma value;
4026{
4027 switch (opindex)
4028 {
4029 case FR30_OPERAND_RI :
4030 fields->f_Ri = value;
4031 break;
4032 case FR30_OPERAND_RJ :
4033 fields->f_Rj = value;
4034 break;
e17387a5
DB		 4035 case FR30_OPERAND_RIC :
4036 fields->f_Ric = value;
4037 break;
4038 case FR30_OPERAND_RJC :
4039 fields->f_Rjc = value;
4040 break;
4041 case FR30_OPERAND_CRI :
4042 fields->f_CRi = value;
4043 break;
4044 case FR30_OPERAND_CRJ :
4045 fields->f_CRj = value;
4046 break;
7a0737c8
DB		 4047 case FR30_OPERAND_RS1 :
4048 fields->f_Rs1 = value;
4049 break;
4050 case FR30_OPERAND_RS2 :
4051 fields->f_Rs2 = value;
4052 break;
6a1254af
DB		 4053 case FR30_OPERAND_R13 :
4054 fields->f_nil = value;
4055 break;
4056 case FR30_OPERAND_R14 :
4057 fields->f_nil = value;
4058 break;
4059 case FR30_OPERAND_R15 :
4060 fields->f_nil = value;
4061 break;
4062 case FR30_OPERAND_PS :
4063 fields->f_nil = value;
4064 break;
7a0737c8
DB		 4065 case FR30_OPERAND_U4 :
4066 fields->f_u4 = value;
4067 break;
e17387a5
DB		 4068 case FR30_OPERAND_U4C :
4069 fields->f_u4c = value;
4070 break;
6a1254af
DB		 4071 case FR30_OPERAND_U8 :
4072 fields->f_u8 = value;
4073 break;
7a0737c8
DB		 4074 case FR30_OPERAND_I8 :
4075 fields->f_i8 = value;
4076 break;
6a1254af
DB		 4077 case FR30_OPERAND_UDISP6 :
4078 fields->f_udisp6 = value;
4079 break;
4080 case FR30_OPERAND_DISP8 :
4081 fields->f_disp8 = value;
4082 break;
4083 case FR30_OPERAND_DISP9 :
4084 fields->f_disp9 = value;
7a0737c8 4085 break;
6a1254af
DB		 4086 case FR30_OPERAND_DISP10 :
4087 fields->f_disp10 = value;
7a0737c8
DB		 4088 break;
4089 case FR30_OPERAND_S10 :
4090 fields->f_s10 = value;
4091 break;
4092 case FR30_OPERAND_U10 :
4093 fields->f_u10 = value;
4094 break;
95b03313
DE		 4095 case FR30_OPERAND_I32 :
4096 fields->f_i32 = value;
4097 break;
7862c6cf
DB		 4098 case FR30_OPERAND_M4 :
4099 fields->f_m4 = value;
4100 break;
a73911a7
DE		 4101 case FR30_OPERAND_I20 :
4102 fields->f_i20 = value;
4103 break;
7a0737c8
DB		 4104 case FR30_OPERAND_DIR8 :
4105 fields->f_dir8 = value;
4106 break;
4107 case FR30_OPERAND_DIR9 :
4108 fields->f_dir9 = value;
4109 break;
4110 case FR30_OPERAND_DIR10 :
4111 fields->f_dir10 = value;
4112 break;
ac1b0e6d
DB		 4113 case FR30_OPERAND_LABEL9 :
4114 fields->f_rel9 = value;
4115 break;
7a0737c8 4116 case FR30_OPERAND_LABEL12 :
6a1254af 4117 fields->f_rel12 = value;
7a0737c8 4118 break;
bfebcfbf
DB		 4119 case FR30_OPERAND_REGLIST_LOW_LD :
4120 fields->f_reglist_low_ld = value;
4121 break;
4122 case FR30_OPERAND_REGLIST_HI_LD :
4123 fields->f_reglist_hi_ld = value;
4124 break;
4125 case FR30_OPERAND_REGLIST_LOW_ST :
4126 fields->f_reglist_low_st = value;
e17387a5 4127 break;
bfebcfbf
DB		 4128 case FR30_OPERAND_REGLIST_HI_ST :
4129 fields->f_reglist_hi_st = value;
e17387a5 4130 break;
7a0737c8
DB		 4131 case FR30_OPERAND_CC :
4132 fields->f_cc = value;
4133 break;
e17387a5
DB		 4134 case FR30_OPERAND_CCC :
4135 fields->f_ccc = value;
4136 break;
a86481d3
DB		 4137
4138 default :
4139 /* xgettext:c-format */
4140 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
4141 opindex);
4142 abort ();
4143 }
4144}
4145
GDB Binutils - Deliverables
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