[deliverable/binutils-gdb.git] / opcodes / fr30-opc.h

/* Instruction description for fr30.

THIS FILE IS MACHINE GENERATED WITH CGEN.

Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.

This file is part of the GNU Binutils and/or GDB, the GNU debugger.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.

*/

#ifndef FR30_OPC_H
#define FR30_OPC_H

#define CGEN_ARCH fr30

/* Given symbol S, return fr30_cgen_<s>.  */
#define CGEN_SYM(s) CONCAT3 (fr30,_cgen_,s)

/* Selected cpu families.  */
#define HAVE_CPU_FR30BF

#define CGEN_INSN_LSB0_P 0
#define CGEN_WORD_BITSIZE 32
#define CGEN_DEFAULT_INSN_BITSIZE 16
#define CGEN_BASE_INSN_BITSIZE 16
#define CGEN_MIN_INSN_BITSIZE 16
#define CGEN_MAX_INSN_BITSIZE 48
#define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8)
#define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8)
#define CGEN_MIN_INSN_SIZE (CGEN_MIN_INSN_BITSIZE / 8)
#define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8)
#define CGEN_INT_INSN_P 0

/* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES.  */

/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
   e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
   we can't hash on everything up to the space.  */
#define CGEN_MNEMONIC_OPERANDS
/* Maximum number of operands any insn or macro-insn has.  */
#define CGEN_MAX_INSN_OPERANDS 16

/* Enums.  */

/* Enum declaration for insn op1 enums.  */
typedef enum insn_op1 {
  OP1_0, OP1_1, OP1_2, OP1_3
 , OP1_4, OP1_5, OP1_6, OP1_7
 , OP1_8, OP1_9, OP1_A, OP1_B
 , OP1_C, OP1_D, OP1_E, OP1_F
} INSN_OP1;

/* Enum declaration for insn op2 enums.  */
typedef enum insn_op2 {
  OP2_0, OP2_1, OP2_2, OP2_3
 , OP2_4, OP2_5, OP2_6, OP2_7
 , OP2_8, OP2_9, OP2_A, OP2_B
 , OP2_C, OP2_D, OP2_E, OP2_F
} INSN_OP2;

/* Enum declaration for insn op3 enums.  */
typedef enum insn_op3 {
  OP3_0, OP3_1, OP3_2, OP3_3
 , OP3_4, OP3_5, OP3_6, OP3_7
 , OP3_8, OP3_9, OP3_A, OP3_B
 , OP3_C, OP3_D, OP3_E, OP3_F
} INSN_OP3;

/* Enum declaration for insn op4 enums.  */
typedef enum insn_op4 {
  OP4_0
} INSN_OP4;

/* Enum declaration for insn op5 enums.  */
typedef enum insn_op5 {
  OP5_0, OP5_1
} INSN_OP5;

/* Enum declaration for insn cc enums.  */
typedef enum insn_cc {
  CC_RA, CC_NO, CC_EQ, CC_NE
 , CC_C, CC_NC, CC_N, CC_P
 , CC_V, CC_NV, CC_LT, CC_GE
 , CC_LE, CC_GT, CC_LS, CC_HI
} INSN_CC;

/* Enum declaration for general registers.  */
typedef enum h_gr {
  H_GR_AC = 13, H_GR_FP = 14, H_GR_SP = 15, H_GR_R0 = 0
 , H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4
 , H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8
 , H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12
 , H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15
} H_GR;

/* Enum declaration for dedicated registers.  */
typedef enum h_dr {
  H_DR_TBR, H_DR_RP, H_DR_SSP, H_DR_USP
 , H_DR_MDH, H_DR_MDL
} H_DR;

/* Enum declaration for program status.  */
typedef enum h_ps {
  H_PS_PS = 1
} H_PS;

/* Enum declaration for General Register 13 explicitely required.  */
typedef enum h_r13 {
  H_R13_R13 = 13
} H_R13;

/* Enum declaration for General Register 14 explicitely required.  */
typedef enum h_r14 {
  H_R14_R14 = 14
} H_R14;

/* Enum declaration for General Register 15 explicitely required.  */
typedef enum h_r15 {
  H_R15_R15 = 15
} H_R15;

/* Enum declaration for fr30 operand types.  */
typedef enum cgen_operand_type {
  FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_RS1
 , FR30_OPERAND_RS2, FR30_OPERAND_R13, FR30_OPERAND_R14, FR30_OPERAND_R15
 , FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_M4, FR30_OPERAND_U8
 , FR30_OPERAND_I8, FR30_OPERAND_UDISP6, FR30_OPERAND_DISP8, FR30_OPERAND_DISP9
 , FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10, FR30_OPERAND_I32
 , FR30_OPERAND_DIR8, FR30_OPERAND_DIR9, FR30_OPERAND_DIR10, FR30_OPERAND_LABEL9
 , FR30_OPERAND_LABEL12, FR30_OPERAND_CC, FR30_OPERAND_NBIT, FR30_OPERAND_VBIT
 , FR30_OPERAND_ZBIT, FR30_OPERAND_CBIT, FR30_OPERAND_MAX
} CGEN_OPERAND_TYPE;

/* Non-boolean attributes.  */

/* Enum declaration for machine type selection.  */
typedef enum mach_attr {
  MACH_BASE, MACH_FR30, MACH_MAX
} MACH_ATTR;

/* Number of architecture variants.  */
#define MAX_MACHS ((int) MACH_MAX)

/* Number of operands types.  */
#define MAX_OPERANDS ((int) FR30_OPERAND_MAX)

/* Maximum number of operands referenced by any insn.  */
#define MAX_OPERAND_INSTANCES 8

/* Hardware, operand and instruction attribute indices.  */

/* Enum declaration for cgen_hw attrs.  */
typedef enum cgen_hw_attr {
  CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
} CGEN_HW_ATTR;

/* Number of non-boolean elements in cgen_hw.  */
#define CGEN_HW_NBOOL_ATTRS ((int) CGEN_HW_CACHE_ADDR)

/* Enum declaration for cgen_operand attrs.  */
typedef enum cgen_operand_attr {
  CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_PCREL_ADDR
 , CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_SIGNED
 , CGEN_OPERAND_UNSIGNED
} CGEN_OPERAND_ATTR;

/* Number of non-boolean elements in cgen_operand.  */
#define CGEN_OPERAND_NBOOL_ATTRS ((int) CGEN_OPERAND_ABS_ADDR)

/* Enum declaration for cgen_insn attrs.  */
typedef enum cgen_insn_attr {
  CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI, CGEN_INSN_NO_DIS, CGEN_INSN_RELAX
 , CGEN_INSN_RELAXABLE, CGEN_INSN_SKIP_CTI, CGEN_INSN_UNCOND_CTI, CGEN_INSN_VIRTUAL
} CGEN_INSN_ATTR;

/* Number of non-boolean elements in cgen_insn.  */
#define CGEN_INSN_NBOOL_ATTRS ((int) CGEN_INSN_ALIAS)

/* Enum declaration for fr30 instruction types.  */
typedef enum cgen_insn_type {
  FR30_INSN_INVALID, FR30_INSN_ADD, FR30_INSN_ADDI, FR30_INSN_ADD2
 , FR30_INSN_ADDC, FR30_INSN_ADDN, FR30_INSN_ADDNI, FR30_INSN_ADDN2
 , FR30_INSN_SUB, FR30_INSN_SUBC, FR30_INSN_SUBN, FR30_INSN_CMP
 , FR30_INSN_CMPI, FR30_INSN_CMP2, FR30_INSN_AND, FR30_INSN_OR
 , FR30_INSN_EOR, FR30_INSN_ANDM, FR30_INSN_ANDH, FR30_INSN_ANDB
 , FR30_INSN_ORM, FR30_INSN_ORH, FR30_INSN_ORB, FR30_INSN_EORM
 , FR30_INSN_EORH, FR30_INSN_EORB, FR30_INSN_BANDL, FR30_INSN_BORL
 , FR30_INSN_BEORL, FR30_INSN_BANDH, FR30_INSN_BORH, FR30_INSN_BEORH
 , FR30_INSN_BTSTL, FR30_INSN_BTSTH, FR30_INSN_MUL, FR30_INSN_MULU
 , FR30_INSN_MULH, FR30_INSN_MULUH, FR30_INSN_DIV0S, FR30_INSN_DIV0U
 , FR30_INSN_DIV1, FR30_INSN_DIV2, FR30_INSN_DIV3, FR30_INSN_DIV4S
 , FR30_INSN_LSL, FR30_INSN_LSLI, FR30_INSN_LSL2, FR30_INSN_LSR
 , FR30_INSN_LSRI, FR30_INSN_LSR2, FR30_INSN_ASR, FR30_INSN_ASRI
 , FR30_INSN_ASR2, FR30_INSN_LDI_8, FR30_INSN_LDI32, FR30_INSN_LD
 , FR30_INSN_LDUH, FR30_INSN_LDUB, FR30_INSN_LDR13, FR30_INSN_LDR13UH
 , FR30_INSN_LDR13UB, FR30_INSN_LDR14, FR30_INSN_LDR14UH, FR30_INSN_LDR14UB
 , FR30_INSN_LDR15, FR30_INSN_LDR15GR, FR30_INSN_LDR15DR, FR30_INSN_LDR15PS
 , FR30_INSN_ST, FR30_INSN_STH, FR30_INSN_STB, FR30_INSN_STR13
 , FR30_INSN_STR13H, FR30_INSN_STR13B, FR30_INSN_STR14, FR30_INSN_STR14H
 , FR30_INSN_STR14B, FR30_INSN_STR15, FR30_INSN_STR15GR, FR30_INSN_STR15DR
 , FR30_INSN_STR15PS, FR30_INSN_MOV, FR30_INSN_MOVDR, FR30_INSN_MOVPS
 , FR30_INSN_MOV2DR, FR30_INSN_MOV2PS, FR30_INSN_JMP, FR30_INSN_JMPD
 , FR30_INSN_CALL, FR30_INSN_CALLD, FR30_INSN_CALLR, FR30_INSN_CALLRD
 , FR30_INSN_RET, FR30_INSN_RETD, FR30_INSN_INT, FR30_INSN_INTE
 , FR30_INSN_RETI, FR30_INSN_BRA, FR30_INSN_BNO, FR30_INSN_BEQ
 , FR30_INSN_BNE, FR30_INSN_BC, FR30_INSN_BNC, FR30_INSN_BN
 , FR30_INSN_BP, FR30_INSN_BV, FR30_INSN_BNV, FR30_INSN_BLT
 , FR30_INSN_BGE, FR30_INSN_BLE, FR30_INSN_BGT, FR30_INSN_BLS
 , FR30_INSN_BHI, FR30_INSN_BRAD, FR30_INSN_BNOD, FR30_INSN_BEQD
 , FR30_INSN_BNED, FR30_INSN_BCD, FR30_INSN_BNCD, FR30_INSN_BND
 , FR30_INSN_BPD, FR30_INSN_BVD, FR30_INSN_BNVD, FR30_INSN_BLTD
 , FR30_INSN_BGED, FR30_INSN_BLED, FR30_INSN_BGTD, FR30_INSN_BLSD
 , FR30_INSN_BHID, FR30_INSN_DMOV2R13, FR30_INSN_DMOV2R13H, FR30_INSN_DMOV2R13B
 , FR30_INSN_DMOVR13, FR30_INSN_DMOVR13H, FR30_INSN_DMOVR13B, FR30_INSN_DMOV2R13PI
 , FR30_INSN_DMOV2R13PIH, FR30_INSN_DMOV2R13PIB, FR30_INSN_DMOVR13PI, FR30_INSN_DMOVR13PIH
 , FR30_INSN_DMOVR13PIB, FR30_INSN_DMOV2R15PD, FR30_INSN_DMOVR15PI, FR30_INSN_LDRES
 , FR30_INSN_STRES, FR30_INSN_NOP, FR30_INSN_ANDCCR, FR30_INSN_ORCCR
 , FR30_INSN_STILM, FR30_INSN_ADDSP, FR30_INSN_EXTSB, FR30_INSN_EXTUB
 , FR30_INSN_EXTSH, FR30_INSN_EXTUH, FR30_INSN_ENTER, FR30_INSN_LEAVE
 , FR30_INSN_XCHB, FR30_INSN_MAX
} CGEN_INSN_TYPE;

/* Index of `invalid' insn place holder.  */
#define CGEN_INSN_INVALID FR30_INSN_INVALID
/* Total number of insns in table.  */
#define MAX_INSNS ((int) FR30_INSN_MAX)

/* cgen.h uses things we just defined.  */
#include "opcode/cgen.h"

/* This struct records data prior to insertion or after extraction.  */
struct cgen_fields 
{
  long f_nil;
  long f_op1;
  long f_op2;
  long f_op3;
  long f_op4;
  long f_op5;
  long f_cc;
  long f_Rj;
  long f_Ri;
  long f_Rs1;
  long f_Rs2;
  long f_u4;
  long f_i4;
  long f_m4;
  long f_u8;
  long f_i8;
  long f_i32;
  long f_udisp6;
  long f_disp8;
  long f_disp9;
  long f_disp10;
  long f_s10;
  long f_u10;
  long f_rel9;
  long f_dir8;
  long f_dir9;
  long f_dir10;
  long f_rel12;
  int length;
};

/* Attributes.  */
extern const CGEN_ATTR_TABLE fr30_cgen_hw_attr_table[];
extern const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[];
extern const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[];

/* Enum declaration for fr30 hardware types.  */
typedef enum hw_type {
  HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT
 , HW_H_ADDR, HW_H_IADDR, HW_H_GR, HW_H_DR
 , HW_H_PS, HW_H_R13, HW_H_R14, HW_H_R15
 , HW_H_NBIT, HW_H_ZBIT, HW_H_VBIT, HW_H_CBIT
 , HW_MAX
} HW_TYPE;

#define MAX_HW ((int) HW_MAX)

/* Hardware decls.  */

extern CGEN_KEYWORD fr30_cgen_opval_h_gr;
extern CGEN_KEYWORD fr30_cgen_opval_h_dr;
extern CGEN_KEYWORD fr30_cgen_opval_h_ps;
extern CGEN_KEYWORD fr30_cgen_opval_h_r13;
extern CGEN_KEYWORD fr30_cgen_opval_h_r14;
extern CGEN_KEYWORD fr30_cgen_opval_h_r15;

#define CGEN_INIT_PARSE(od) \
{\
}
#define CGEN_INIT_INSERT(od) \
{\
}
#define CGEN_INIT_EXTRACT(od) \
{\
}
#define CGEN_INIT_PRINT(od) \
{\
}


#endif /* FR30_OPC_H */
Commit	Line	Data
a86481d3 DB	1	/* Instruction description for fr30.
	2
	3	THIS FILE IS MACHINE GENERATED WITH CGEN.
	4
	5	Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
	6
	7	This file is part of the GNU Binutils and/or GDB, the GNU debugger.
	8
	9	This program is free software; you can redistribute it and/or modify
	10	it under the terms of the GNU General Public License as published by
	11	the Free Software Foundation; either version 2, or (at your option)
	12	any later version.
	13
	14	This program is distributed in the hope that it will be useful,
	15	but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	GNU General Public License for more details.
	18
	19	You should have received a copy of the GNU General Public License along
	20	with this program; if not, write to the Free Software Foundation, Inc.,
	21	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	22
	23	*/
	24
	25	#ifndef FR30_OPC_H
	26	#define FR30_OPC_H
	27
	28	#define CGEN_ARCH fr30
	29
	30	/* Given symbol S, return fr30_cgen_<s>. */
	31	#define CGEN_SYM(s) CONCAT3 (fr30,_cgen_,s)
	32
	33	/* Selected cpu families. */
	34	#define HAVE_CPU_FR30BF
	35
	36	#define CGEN_INSN_LSB0_P 0
	37	#define CGEN_WORD_BITSIZE 32
	38	#define CGEN_DEFAULT_INSN_BITSIZE 16
	39	#define CGEN_BASE_INSN_BITSIZE 16
	40	#define CGEN_MIN_INSN_BITSIZE 16
95b03313	41	#define CGEN_MAX_INSN_BITSIZE 48
a86481d3 DB	42	#define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8)
	43	#define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8)
	44	#define CGEN_MIN_INSN_SIZE (CGEN_MIN_INSN_BITSIZE / 8)
	45	#define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8)
95b03313	46	#define CGEN_INT_INSN_P 0
a86481d3 DB	47
	48	/* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES. */
	49
	50	/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
	51	e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
	52	we can't hash on everything up to the space. */
	53	#define CGEN_MNEMONIC_OPERANDS
	54	/* Maximum number of operands any insn or macro-insn has. */
	55	#define CGEN_MAX_INSN_OPERANDS 16
	56
	57	/* Enums. */
	58
	59	/* Enum declaration for insn op1 enums. */
	60	typedef enum insn_op1 {
	61	OP1_0, OP1_1, OP1_2, OP1_3
	62	, OP1_4, OP1_5, OP1_6, OP1_7
	63	, OP1_8, OP1_9, OP1_A, OP1_B
	64	, OP1_C, OP1_D, OP1_E, OP1_F
	65	} INSN_OP1;
	66
	67	/* Enum declaration for insn op2 enums. */
	68	typedef enum insn_op2 {
	69	OP2_0, OP2_1, OP2_2, OP2_3
	70	, OP2_4, OP2_5, OP2_6, OP2_7
	71	, OP2_8, OP2_9, OP2_A, OP2_B
	72	, OP2_C, OP2_D, OP2_E, OP2_F
	73	} INSN_OP2;
	74
	75	/* Enum declaration for insn op3 enums. */
	76	typedef enum insn_op3 {
	77	OP3_0, OP3_1, OP3_2, OP3_3
	78	, OP3_4, OP3_5, OP3_6, OP3_7
	79	, OP3_8, OP3_9, OP3_A, OP3_B
	80	, OP3_C, OP3_D, OP3_E, OP3_F
	81	} INSN_OP3;
	82
7a0737c8 DB	83	/* Enum declaration for insn op4 enums. */
	84	typedef enum insn_op4 {
	85	OP4_0
	86	} INSN_OP4;
	87
a86481d3 DB	88	/* Enum declaration for insn op5 enums. */
	89	typedef enum insn_op5 {
	90	OP5_0, OP5_1
	91	} INSN_OP5;
	92
7a0737c8 DB	93	/* Enum declaration for insn cc enums. */
	94	typedef enum insn_cc {
	95	CC_RA, CC_NO, CC_EQ, CC_NE
	96	, CC_C, CC_NC, CC_N, CC_P
	97	, CC_V, CC_NV, CC_LT, CC_GE
	98	, CC_LE, CC_GT, CC_LS, CC_HI
	99	} INSN_CC;
	100
a86481d3 DB	101	/* Enum declaration for general registers. */
	102	typedef enum h_gr {
	103	H_GR_AC = 13, H_GR_FP = 14, H_GR_SP = 15, H_GR_R0 = 0
	104	, H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4
	105	, H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8
	106	, H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12
	107	, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15
	108	} H_GR;
	109
6146431a DB	110	/* Enum declaration for dedicated registers. */
	111	typedef enum h_dr {
	112	H_DR_TBR, H_DR_RP, H_DR_SSP, H_DR_USP
7a0737c8	113	, H_DR_MDH, H_DR_MDL
6146431a DB	114	} H_DR;
6146431a DB	115
6a1254af DB	116	/* Enum declaration for program status. */
	117	typedef enum h_ps {
	118	H_PS_PS = 1
	119	} H_PS;
	120
	121	/* Enum declaration for General Register 13 explicitely required. */
	122	typedef enum h_r13 {
	123	H_R13_R13 = 13
	124	} H_R13;
	125
	126	/* Enum declaration for General Register 14 explicitely required. */
	127	typedef enum h_r14 {
	128	H_R14_R14 = 14
	129	} H_R14;
	130
	131	/* Enum declaration for General Register 15 explicitely required. */
	132	typedef enum h_r15 {
	133	H_R15_R15 = 15
	134	} H_R15;
6146431a	135
a86481d3 DB	136	/* Enum declaration for fr30 operand types. */
a86481d3 DB	137	typedef enum cgen_operand_type {
7a0737c8	138	FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_RS1
6a1254af DB	139	, FR30_OPERAND_RS2, FR30_OPERAND_R13, FR30_OPERAND_R14, FR30_OPERAND_R15
	140	, FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_M4, FR30_OPERAND_U8
	141	, FR30_OPERAND_I8, FR30_OPERAND_UDISP6, FR30_OPERAND_DISP8, FR30_OPERAND_DISP9
95b03313 DE	142	, FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10, FR30_OPERAND_I32
	143	, FR30_OPERAND_DIR8, FR30_OPERAND_DIR9, FR30_OPERAND_DIR10, FR30_OPERAND_LABEL9
	144	, FR30_OPERAND_LABEL12, FR30_OPERAND_CC, FR30_OPERAND_NBIT, FR30_OPERAND_VBIT
	145	, FR30_OPERAND_ZBIT, FR30_OPERAND_CBIT, FR30_OPERAND_MAX
a86481d3 DB	146	} CGEN_OPERAND_TYPE;
	147
	148	/* Non-boolean attributes. */
	149
	150	/* Enum declaration for machine type selection. */
	151	typedef enum mach_attr {
	152	MACH_BASE, MACH_FR30, MACH_MAX
	153	} MACH_ATTR;
	154
	155	/* Number of architecture variants. */
	156	#define MAX_MACHS ((int) MACH_MAX)
	157
	158	/* Number of operands types. */
	159	#define MAX_OPERANDS ((int) FR30_OPERAND_MAX)
	160
	161	/* Maximum number of operands referenced by any insn. */
7a0737c8	162	#define MAX_OPERAND_INSTANCES 8
a86481d3 DB	163
	164	/* Hardware, operand and instruction attribute indices. */
	165
	166	/* Enum declaration for cgen_hw attrs. */
	167	typedef enum cgen_hw_attr {
7a0737c8	168	CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
a86481d3 DB	169	} CGEN_HW_ATTR;
	170
	171	/* Number of non-boolean elements in cgen_hw. */
	172	#define CGEN_HW_NBOOL_ATTRS ((int) CGEN_HW_CACHE_ADDR)
	173
	174	/* Enum declaration for cgen_operand attrs. */
	175	typedef enum cgen_operand_attr {
7a0737c8 DB	176	CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_PCREL_ADDR
	177	, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_SIGNED
	178	, CGEN_OPERAND_UNSIGNED
a86481d3 DB	179	} CGEN_OPERAND_ATTR;
	180
	181	/* Number of non-boolean elements in cgen_operand. */
	182	#define CGEN_OPERAND_NBOOL_ATTRS ((int) CGEN_OPERAND_ABS_ADDR)
	183
	184	/* Enum declaration for cgen_insn attrs. */
	185	typedef enum cgen_insn_attr {
	186	CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI, CGEN_INSN_NO_DIS, CGEN_INSN_RELAX
	187	, CGEN_INSN_RELAXABLE, CGEN_INSN_SKIP_CTI, CGEN_INSN_UNCOND_CTI, CGEN_INSN_VIRTUAL
	188	} CGEN_INSN_ATTR;
	189
	190	/* Number of non-boolean elements in cgen_insn. */
	191	#define CGEN_INSN_NBOOL_ATTRS ((int) CGEN_INSN_ALIAS)
	192
	193	/* Enum declaration for fr30 instruction types. */
	194	typedef enum cgen_insn_type {
7a0737c8 DB	195	FR30_INSN_INVALID, FR30_INSN_ADD, FR30_INSN_ADDI, FR30_INSN_ADD2
	196	, FR30_INSN_ADDC, FR30_INSN_ADDN, FR30_INSN_ADDNI, FR30_INSN_ADDN2
	197	, FR30_INSN_SUB, FR30_INSN_SUBC, FR30_INSN_SUBN, FR30_INSN_CMP
	198	, FR30_INSN_CMPI, FR30_INSN_CMP2, FR30_INSN_AND, FR30_INSN_OR
	199	, FR30_INSN_EOR, FR30_INSN_ANDM, FR30_INSN_ANDH, FR30_INSN_ANDB
	200	, FR30_INSN_ORM, FR30_INSN_ORH, FR30_INSN_ORB, FR30_INSN_EORM
	201	, FR30_INSN_EORH, FR30_INSN_EORB, FR30_INSN_BANDL, FR30_INSN_BORL
	202	, FR30_INSN_BEORL, FR30_INSN_BANDH, FR30_INSN_BORH, FR30_INSN_BEORH
	203	, FR30_INSN_BTSTL, FR30_INSN_BTSTH, FR30_INSN_MUL, FR30_INSN_MULU
	204	, FR30_INSN_MULH, FR30_INSN_MULUH, FR30_INSN_DIV0S, FR30_INSN_DIV0U
	205	, FR30_INSN_DIV1, FR30_INSN_DIV2, FR30_INSN_DIV3, FR30_INSN_DIV4S
	206	, FR30_INSN_LSL, FR30_INSN_LSLI, FR30_INSN_LSL2, FR30_INSN_LSR
	207	, FR30_INSN_LSRI, FR30_INSN_LSR2, FR30_INSN_ASR, FR30_INSN_ASRI
95b03313 DE	208	, FR30_INSN_ASR2, FR30_INSN_LDI_8, FR30_INSN_LDI32, FR30_INSN_LD
	209	, FR30_INSN_LDUH, FR30_INSN_LDUB, FR30_INSN_LDR13, FR30_INSN_LDR13UH
	210	, FR30_INSN_LDR13UB, FR30_INSN_LDR14, FR30_INSN_LDR14UH, FR30_INSN_LDR14UB
	211	, FR30_INSN_LDR15, FR30_INSN_LDR15GR, FR30_INSN_LDR15DR, FR30_INSN_LDR15PS
	212	, FR30_INSN_ST, FR30_INSN_STH, FR30_INSN_STB, FR30_INSN_STR13
	213	, FR30_INSN_STR13H, FR30_INSN_STR13B, FR30_INSN_STR14, FR30_INSN_STR14H
	214	, FR30_INSN_STR14B, FR30_INSN_STR15, FR30_INSN_STR15GR, FR30_INSN_STR15DR
	215	, FR30_INSN_STR15PS, FR30_INSN_MOV, FR30_INSN_MOVDR, FR30_INSN_MOVPS
	216	, FR30_INSN_MOV2DR, FR30_INSN_MOV2PS, FR30_INSN_JMP, FR30_INSN_JMPD
	217	, FR30_INSN_CALL, FR30_INSN_CALLD, FR30_INSN_CALLR, FR30_INSN_CALLRD
	218	, FR30_INSN_RET, FR30_INSN_RETD, FR30_INSN_INT, FR30_INSN_INTE
	219	, FR30_INSN_RETI, FR30_INSN_BRA, FR30_INSN_BNO, FR30_INSN_BEQ
	220	, FR30_INSN_BNE, FR30_INSN_BC, FR30_INSN_BNC, FR30_INSN_BN
	221	, FR30_INSN_BP, FR30_INSN_BV, FR30_INSN_BNV, FR30_INSN_BLT
	222	, FR30_INSN_BGE, FR30_INSN_BLE, FR30_INSN_BGT, FR30_INSN_BLS
	223	, FR30_INSN_BHI, FR30_INSN_BRAD, FR30_INSN_BNOD, FR30_INSN_BEQD
	224	, FR30_INSN_BNED, FR30_INSN_BCD, FR30_INSN_BNCD, FR30_INSN_BND
	225	, FR30_INSN_BPD, FR30_INSN_BVD, FR30_INSN_BNVD, FR30_INSN_BLTD
	226	, FR30_INSN_BGED, FR30_INSN_BLED, FR30_INSN_BGTD, FR30_INSN_BLSD
	227	, FR30_INSN_BHID, FR30_INSN_DMOV2R13, FR30_INSN_DMOV2R13H, FR30_INSN_DMOV2R13B
	228	, FR30_INSN_DMOVR13, FR30_INSN_DMOVR13H, FR30_INSN_DMOVR13B, FR30_INSN_DMOV2R13PI
	229	, FR30_INSN_DMOV2R13PIH, FR30_INSN_DMOV2R13PIB, FR30_INSN_DMOVR13PI, FR30_INSN_DMOVR13PIH
	230	, FR30_INSN_DMOVR13PIB, FR30_INSN_DMOV2R15PD, FR30_INSN_DMOVR15PI, FR30_INSN_LDRES
	231	, FR30_INSN_STRES, FR30_INSN_NOP, FR30_INSN_ANDCCR, FR30_INSN_ORCCR
	232	, FR30_INSN_STILM, FR30_INSN_ADDSP, FR30_INSN_EXTSB, FR30_INSN_EXTUB
	233	, FR30_INSN_EXTSH, FR30_INSN_EXTUH, FR30_INSN_ENTER, FR30_INSN_LEAVE
	234	, FR30_INSN_XCHB, FR30_INSN_MAX
a86481d3 DB	235	} CGEN_INSN_TYPE;
	236
	237	/* Index of `invalid' insn place holder. */
	238	#define CGEN_INSN_INVALID FR30_INSN_INVALID
	239	/* Total number of insns in table. */
	240	#define MAX_INSNS ((int) FR30_INSN_MAX)
	241
	242	/* cgen.h uses things we just defined. */
	243	#include "opcode/cgen.h"
	244
	245	/* This struct records data prior to insertion or after extraction. */
	246	struct cgen_fields
	247	{
	248	long f_nil;
	249	long f_op1;
	250	long f_op2;
	251	long f_op3;
7a0737c8	252	long f_op4;
a86481d3	253	long f_op5;
7a0737c8	254	long f_cc;
a86481d3 DB	255	long f_Rj;
a86481d3 DB	256	long f_Ri;
7a0737c8 DB	257	long f_Rs1;
7a0737c8 DB	258	long f_Rs2;
a86481d3 DB	259	long f_u4;
	260	long f_i4;
	261	long f_m4;
	262	long f_u8;
	263	long f_i8;
95b03313	264	long f_i32;
6a1254af DB	265	long f_udisp6;
	266	long f_disp8;
	267	long f_disp9;
	268	long f_disp10;
7a0737c8 DB	269	long f_s10;
7a0737c8 DB	270	long f_u10;
6a1254af	271	long f_rel9;
7a0737c8 DB	272	long f_dir8;
	273	long f_dir9;
	274	long f_dir10;
6a1254af	275	long f_rel12;
a86481d3 DB	276	int length;
	277	};
	278
	279	/* Attributes. */
	280	extern const CGEN_ATTR_TABLE fr30_cgen_hw_attr_table[];
	281	extern const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[];
	282	extern const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[];
	283
	284	/* Enum declaration for fr30 hardware types. */
	285	typedef enum hw_type {
	286	HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT
6146431a	287	, HW_H_ADDR, HW_H_IADDR, HW_H_GR, HW_H_DR
6a1254af DB	288	, HW_H_PS, HW_H_R13, HW_H_R14, HW_H_R15
	289	, HW_H_NBIT, HW_H_ZBIT, HW_H_VBIT, HW_H_CBIT
	290	, HW_MAX
a86481d3 DB	291	} HW_TYPE;
	292
	293	#define MAX_HW ((int) HW_MAX)
	294
	295	/* Hardware decls. */
	296
	297	extern CGEN_KEYWORD fr30_cgen_opval_h_gr;
6146431a	298	extern CGEN_KEYWORD fr30_cgen_opval_h_dr;
6a1254af DB	299	extern CGEN_KEYWORD fr30_cgen_opval_h_ps;
	300	extern CGEN_KEYWORD fr30_cgen_opval_h_r13;
	301	extern CGEN_KEYWORD fr30_cgen_opval_h_r14;
	302	extern CGEN_KEYWORD fr30_cgen_opval_h_r15;
a86481d3 DB	303
	304	#define CGEN_INIT_PARSE(od) \
	305	{\
	306	}
	307	#define CGEN_INIT_INSERT(od) \
	308	{\
	309	}
	310	#define CGEN_INIT_EXTRACT(od) \
	311	{\
	312	}
	313	#define CGEN_INIT_PRINT(od) \
	314	{\
	315	}
	316
	317
	318
	319	#endif /* FR30_OPC_H */