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fd3c93d5 DB |
1 | /* Disassembler interface for targets using CGEN. -*- C -*- |
2 | CGEN: Cpu tools GENerator | |
3 | ||
4 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
5 | - the resultant file is machine generated, cgen-dis.in isn't | |
6 | ||
98f70fc4 AM |
7 | Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 |
8 | Free Software Foundation, Inc. | |
fd3c93d5 DB |
9 | |
10 | This file is part of the GNU Binutils and GDB, the GNU debugger. | |
11 | ||
12 | This program is free software; you can redistribute it and/or modify | |
13 | it under the terms of the GNU General Public License as published by | |
14 | the Free Software Foundation; either version 2, or (at your option) | |
15 | any later version. | |
16 | ||
17 | This program is distributed in the hope that it will be useful, | |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
21 | ||
22 | You should have received a copy of the GNU General Public License | |
23 | along with this program; if not, write to the Free Software Foundation, Inc., | |
24 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
25 | ||
26 | /* ??? Eventually more and more of this stuff can go to cpu-independent files. | |
27 | Keep that in mind. */ | |
28 | ||
29 | #include "sysdep.h" | |
30 | #include <stdio.h> | |
31 | #include "ansidecl.h" | |
32 | #include "dis-asm.h" | |
33 | #include "bfd.h" | |
34 | #include "symcat.h" | |
98f70fc4 | 35 | #include "libiberty.h" |
fd3c93d5 DB |
36 | #include "frv-desc.h" |
37 | #include "frv-opc.h" | |
38 | #include "opintl.h" | |
39 | ||
40 | /* Default text to print if an instruction isn't recognized. */ | |
41 | #define UNKNOWN_INSN_MSG _("*unknown*") | |
42 | ||
43 | static void print_normal | |
ffead7ae | 44 | (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); |
fd3c93d5 | 45 | static void print_address |
ffead7ae | 46 | (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int); |
fd3c93d5 | 47 | static void print_keyword |
ffead7ae | 48 | (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int); |
fd3c93d5 | 49 | static void print_insn_normal |
ffead7ae | 50 | (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); |
fd3c93d5 | 51 | static int print_insn |
ffead7ae | 52 | (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned); |
fd3c93d5 | 53 | static int default_print_insn |
ffead7ae | 54 | (CGEN_CPU_DESC, bfd_vma, disassemble_info *); |
fd3c93d5 | 55 | static int read_insn |
ffead7ae MM |
56 | (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, CGEN_EXTRACT_INFO *, |
57 | unsigned long *); | |
fd3c93d5 DB |
58 | \f |
59 | /* -- disassembler routines inserted here */ | |
60 | ||
61 | /* -- dis.c */ | |
62 | static void print_spr | |
63 | PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned)); | |
64 | static void print_hi | |
65 | PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); | |
66 | static void print_lo | |
67 | PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); | |
68 | ||
69 | static void | |
70 | print_spr (cd, dis_info, names, regno, attrs) | |
71 | CGEN_CPU_DESC cd; | |
72 | PTR dis_info; | |
73 | CGEN_KEYWORD *names; | |
74 | long regno; | |
75 | unsigned int attrs; | |
76 | { | |
77 | /* Use the register index format for any unnamed registers. */ | |
78 | if (cgen_keyword_lookup_value (names, regno) == NULL) | |
79 | { | |
80 | disassemble_info *info = (disassemble_info *) dis_info; | |
81 | (*info->fprintf_func) (info->stream, "spr[%ld]", regno); | |
82 | } | |
83 | else | |
84 | print_keyword (cd, dis_info, names, regno, attrs); | |
85 | } | |
86 | ||
87 | static void | |
88 | print_hi (cd, dis_info, value, attrs, pc, length) | |
89 | CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; | |
90 | PTR dis_info; | |
91 | long value; | |
92 | unsigned int attrs ATTRIBUTE_UNUSED; | |
93 | bfd_vma pc ATTRIBUTE_UNUSED; | |
94 | int length ATTRIBUTE_UNUSED; | |
95 | { | |
96 | disassemble_info *info = (disassemble_info *) dis_info; | |
97 | if (value) | |
98 | (*info->fprintf_func) (info->stream, "0x%lx", value); | |
99 | else | |
100 | (*info->fprintf_func) (info->stream, "hi(0x%lx)", value); | |
101 | } | |
102 | ||
103 | static void | |
104 | print_lo (cd, dis_info, value, attrs, pc, length) | |
105 | CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; | |
106 | PTR dis_info; | |
107 | long value; | |
108 | unsigned int attrs ATTRIBUTE_UNUSED; | |
109 | bfd_vma pc ATTRIBUTE_UNUSED; | |
110 | int length ATTRIBUTE_UNUSED; | |
111 | { | |
112 | disassemble_info *info = (disassemble_info *) dis_info; | |
113 | if (value) | |
114 | (*info->fprintf_func) (info->stream, "0x%lx", value); | |
115 | else | |
116 | (*info->fprintf_func) (info->stream, "lo(0x%lx)", value); | |
117 | } | |
118 | ||
119 | /* -- */ | |
120 | ||
121 | void frv_cgen_print_operand | |
122 | PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, | |
123 | void const *, bfd_vma, int)); | |
124 | ||
125 | /* Main entry point for printing operands. | |
126 | XINFO is a `void *' and not a `disassemble_info *' to not put a requirement | |
127 | of dis-asm.h on cgen.h. | |
128 | ||
129 | This function is basically just a big switch statement. Earlier versions | |
130 | used tables to look up the function to use, but | |
131 | - if the table contains both assembler and disassembler functions then | |
132 | the disassembler contains much of the assembler and vice-versa, | |
133 | - there's a lot of inlining possibilities as things grow, | |
134 | - using a switch statement avoids the function call overhead. | |
135 | ||
136 | This function could be moved into `print_insn_normal', but keeping it | |
137 | separate makes clear the interface between `print_insn_normal' and each of | |
138 | the handlers. */ | |
139 | ||
140 | void | |
141 | frv_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) | |
142 | CGEN_CPU_DESC cd; | |
143 | int opindex; | |
144 | PTR xinfo; | |
145 | CGEN_FIELDS *fields; | |
146 | void const *attrs ATTRIBUTE_UNUSED; | |
147 | bfd_vma pc; | |
148 | int length; | |
149 | { | |
150 | disassemble_info *info = (disassemble_info *) xinfo; | |
151 | ||
152 | switch (opindex) | |
153 | { | |
ecd51ad3 DB |
154 | case FRV_OPERAND_A0 : |
155 | print_normal (cd, info, fields->f_A, 0, pc, length); | |
156 | break; | |
157 | case FRV_OPERAND_A1 : | |
158 | print_normal (cd, info, fields->f_A, 0, pc, length); | |
fd3c93d5 DB |
159 | break; |
160 | case FRV_OPERAND_ACC40SI : | |
161 | print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Si, 0); | |
162 | break; | |
163 | case FRV_OPERAND_ACC40SK : | |
164 | print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Sk, 0); | |
165 | break; | |
166 | case FRV_OPERAND_ACC40UI : | |
167 | print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Ui, 0); | |
168 | break; | |
169 | case FRV_OPERAND_ACC40UK : | |
170 | print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Uk, 0); | |
171 | break; | |
172 | case FRV_OPERAND_ACCGI : | |
173 | print_keyword (cd, info, & frv_cgen_opval_accg_names, fields->f_ACCGi, 0); | |
174 | break; | |
175 | case FRV_OPERAND_ACCGK : | |
176 | print_keyword (cd, info, & frv_cgen_opval_accg_names, fields->f_ACCGk, 0); | |
177 | break; | |
178 | case FRV_OPERAND_CCI : | |
179 | print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CCi, 0); | |
180 | break; | |
181 | case FRV_OPERAND_CPRDOUBLEK : | |
182 | print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRk, 0); | |
183 | break; | |
184 | case FRV_OPERAND_CPRI : | |
185 | print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRi, 0); | |
186 | break; | |
187 | case FRV_OPERAND_CPRJ : | |
188 | print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRj, 0); | |
189 | break; | |
190 | case FRV_OPERAND_CPRK : | |
191 | print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRk, 0); | |
192 | break; | |
193 | case FRV_OPERAND_CRI : | |
194 | print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRi, 0); | |
195 | break; | |
196 | case FRV_OPERAND_CRJ : | |
197 | print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRj, 0); | |
198 | break; | |
199 | case FRV_OPERAND_CRJ_FLOAT : | |
200 | print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRj_float, 0); | |
201 | break; | |
202 | case FRV_OPERAND_CRJ_INT : | |
203 | print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRj_int, 0); | |
204 | break; | |
205 | case FRV_OPERAND_CRK : | |
206 | print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRk, 0); | |
207 | break; | |
208 | case FRV_OPERAND_FCCI_1 : | |
209 | print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCi_1, 0); | |
210 | break; | |
211 | case FRV_OPERAND_FCCI_2 : | |
212 | print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCi_2, 0); | |
213 | break; | |
214 | case FRV_OPERAND_FCCI_3 : | |
215 | print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCi_3, 0); | |
216 | break; | |
217 | case FRV_OPERAND_FCCK : | |
218 | print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCk, 0); | |
219 | break; | |
220 | case FRV_OPERAND_FRDOUBLEI : | |
221 | print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0); | |
222 | break; | |
223 | case FRV_OPERAND_FRDOUBLEJ : | |
224 | print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0); | |
225 | break; | |
226 | case FRV_OPERAND_FRDOUBLEK : | |
227 | print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0); | |
228 | break; | |
229 | case FRV_OPERAND_FRI : | |
230 | print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0); | |
231 | break; | |
232 | case FRV_OPERAND_FRINTI : | |
233 | print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0); | |
234 | break; | |
36c3ae24 NC |
235 | case FRV_OPERAND_FRINTIEVEN : |
236 | print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0); | |
237 | break; | |
fd3c93d5 DB |
238 | case FRV_OPERAND_FRINTJ : |
239 | print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0); | |
240 | break; | |
36c3ae24 NC |
241 | case FRV_OPERAND_FRINTJEVEN : |
242 | print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0); | |
243 | break; | |
fd3c93d5 DB |
244 | case FRV_OPERAND_FRINTK : |
245 | print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0); | |
246 | break; | |
36c3ae24 NC |
247 | case FRV_OPERAND_FRINTKEVEN : |
248 | print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0); | |
249 | break; | |
fd3c93d5 DB |
250 | case FRV_OPERAND_FRJ : |
251 | print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0); | |
252 | break; | |
253 | case FRV_OPERAND_FRK : | |
254 | print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0); | |
255 | break; | |
256 | case FRV_OPERAND_FRKHI : | |
257 | print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0); | |
258 | break; | |
259 | case FRV_OPERAND_FRKLO : | |
260 | print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0); | |
261 | break; | |
262 | case FRV_OPERAND_GRDOUBLEK : | |
263 | print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0); | |
264 | break; | |
265 | case FRV_OPERAND_GRI : | |
266 | print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRi, 0); | |
267 | break; | |
268 | case FRV_OPERAND_GRJ : | |
269 | print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRj, 0); | |
270 | break; | |
271 | case FRV_OPERAND_GRK : | |
272 | print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0); | |
273 | break; | |
274 | case FRV_OPERAND_GRKHI : | |
275 | print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0); | |
276 | break; | |
277 | case FRV_OPERAND_GRKLO : | |
278 | print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0); | |
279 | break; | |
280 | case FRV_OPERAND_ICCI_1 : | |
281 | print_keyword (cd, info, & frv_cgen_opval_iccr_names, fields->f_ICCi_1, 0); | |
282 | break; | |
283 | case FRV_OPERAND_ICCI_2 : | |
284 | print_keyword (cd, info, & frv_cgen_opval_iccr_names, fields->f_ICCi_2, 0); | |
285 | break; | |
286 | case FRV_OPERAND_ICCI_3 : | |
287 | print_keyword (cd, info, & frv_cgen_opval_iccr_names, fields->f_ICCi_3, 0); | |
288 | break; | |
289 | case FRV_OPERAND_LI : | |
290 | print_normal (cd, info, fields->f_LI, 0, pc, length); | |
291 | break; | |
676a64f4 RS |
292 | case FRV_OPERAND_LRAD : |
293 | print_normal (cd, info, fields->f_LRAD, 0, pc, length); | |
294 | break; | |
295 | case FRV_OPERAND_LRAE : | |
296 | print_normal (cd, info, fields->f_LRAE, 0, pc, length); | |
297 | break; | |
298 | case FRV_OPERAND_LRAS : | |
299 | print_normal (cd, info, fields->f_LRAS, 0, pc, length); | |
300 | break; | |
301 | case FRV_OPERAND_TLBPRL : | |
302 | print_normal (cd, info, fields->f_TLBPRL, 0, pc, length); | |
303 | break; | |
304 | case FRV_OPERAND_TLBPROPX : | |
305 | print_normal (cd, info, fields->f_TLBPRopx, 0, pc, length); | |
306 | break; | |
fd3c93d5 DB |
307 | case FRV_OPERAND_AE : |
308 | print_normal (cd, info, fields->f_ae, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
309 | break; | |
310 | case FRV_OPERAND_CCOND : | |
311 | print_normal (cd, info, fields->f_ccond, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
312 | break; | |
313 | case FRV_OPERAND_COND : | |
314 | print_normal (cd, info, fields->f_cond, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
315 | break; | |
316 | case FRV_OPERAND_D12 : | |
317 | print_normal (cd, info, fields->f_d12, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); | |
318 | break; | |
319 | case FRV_OPERAND_DEBUG : | |
320 | print_normal (cd, info, fields->f_debug, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
321 | break; | |
322 | case FRV_OPERAND_EIR : | |
323 | print_normal (cd, info, fields->f_eir, 0, pc, length); | |
324 | break; | |
325 | case FRV_OPERAND_HINT : | |
326 | print_normal (cd, info, fields->f_hint, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
327 | break; | |
328 | case FRV_OPERAND_HINT_NOT_TAKEN : | |
329 | print_keyword (cd, info, & frv_cgen_opval_h_hint_not_taken, fields->f_hint, 0); | |
330 | break; | |
331 | case FRV_OPERAND_HINT_TAKEN : | |
332 | print_keyword (cd, info, & frv_cgen_opval_h_hint_taken, fields->f_hint, 0); | |
333 | break; | |
334 | case FRV_OPERAND_LABEL16 : | |
335 | print_address (cd, info, fields->f_label16, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); | |
336 | break; | |
337 | case FRV_OPERAND_LABEL24 : | |
338 | print_address (cd, info, fields->f_label24, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); | |
339 | break; | |
340 | case FRV_OPERAND_LOCK : | |
341 | print_normal (cd, info, fields->f_lock, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
342 | break; | |
343 | case FRV_OPERAND_PACK : | |
344 | print_keyword (cd, info, & frv_cgen_opval_h_pack, fields->f_pack, 0); | |
345 | break; | |
346 | case FRV_OPERAND_S10 : | |
347 | print_normal (cd, info, fields->f_s10, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
348 | break; | |
349 | case FRV_OPERAND_S12 : | |
350 | print_normal (cd, info, fields->f_d12, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
351 | break; | |
352 | case FRV_OPERAND_S16 : | |
353 | print_normal (cd, info, fields->f_s16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
354 | break; | |
355 | case FRV_OPERAND_S5 : | |
356 | print_normal (cd, info, fields->f_s5, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
357 | break; | |
358 | case FRV_OPERAND_S6 : | |
359 | print_normal (cd, info, fields->f_s6, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
360 | break; | |
361 | case FRV_OPERAND_S6_1 : | |
362 | print_normal (cd, info, fields->f_s6_1, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
363 | break; | |
364 | case FRV_OPERAND_SLO16 : | |
365 | print_lo (cd, info, fields->f_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); | |
366 | break; | |
367 | case FRV_OPERAND_SPR : | |
368 | print_spr (cd, info, & frv_cgen_opval_spr_names, fields->f_spr, 0|(1<<CGEN_OPERAND_VIRTUAL)); | |
369 | break; | |
370 | case FRV_OPERAND_U12 : | |
371 | print_normal (cd, info, fields->f_u12, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); | |
372 | break; | |
373 | case FRV_OPERAND_U16 : | |
374 | print_normal (cd, info, fields->f_u16, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
375 | break; | |
376 | case FRV_OPERAND_U6 : | |
377 | print_normal (cd, info, fields->f_u6, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); | |
378 | break; | |
379 | case FRV_OPERAND_UHI16 : | |
380 | print_hi (cd, info, fields->f_u16, 0, pc, length); | |
381 | break; | |
382 | case FRV_OPERAND_ULO16 : | |
383 | print_lo (cd, info, fields->f_u16, 0, pc, length); | |
384 | break; | |
385 | ||
386 | default : | |
387 | /* xgettext:c-format */ | |
388 | fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), | |
389 | opindex); | |
390 | abort (); | |
391 | } | |
392 | } | |
393 | ||
394 | cgen_print_fn * const frv_cgen_print_handlers[] = | |
395 | { | |
396 | print_insn_normal, | |
397 | }; | |
398 | ||
399 | ||
400 | void | |
401 | frv_cgen_init_dis (cd) | |
402 | CGEN_CPU_DESC cd; | |
403 | { | |
404 | frv_cgen_init_opcode_table (cd); | |
405 | frv_cgen_init_ibld_table (cd); | |
406 | cd->print_handlers = & frv_cgen_print_handlers[0]; | |
407 | cd->print_operand = frv_cgen_print_operand; | |
408 | } | |
409 | ||
410 | \f | |
411 | /* Default print handler. */ | |
412 | ||
413 | static void | |
ffead7ae MM |
414 | print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, |
415 | void *dis_info, | |
416 | long value, | |
417 | unsigned int attrs, | |
418 | bfd_vma pc ATTRIBUTE_UNUSED, | |
419 | int length ATTRIBUTE_UNUSED) | |
fd3c93d5 DB |
420 | { |
421 | disassemble_info *info = (disassemble_info *) dis_info; | |
422 | ||
423 | #ifdef CGEN_PRINT_NORMAL | |
424 | CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length); | |
425 | #endif | |
426 | ||
427 | /* Print the operand as directed by the attributes. */ | |
428 | if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) | |
429 | ; /* nothing to do */ | |
430 | else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) | |
431 | (*info->fprintf_func) (info->stream, "%ld", value); | |
432 | else | |
433 | (*info->fprintf_func) (info->stream, "0x%lx", value); | |
434 | } | |
435 | ||
436 | /* Default address handler. */ | |
437 | ||
438 | static void | |
ffead7ae MM |
439 | print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, |
440 | void *dis_info, | |
441 | bfd_vma value, | |
442 | unsigned int attrs, | |
443 | bfd_vma pc ATTRIBUTE_UNUSED, | |
444 | int length ATTRIBUTE_UNUSED) | |
fd3c93d5 DB |
445 | { |
446 | disassemble_info *info = (disassemble_info *) dis_info; | |
447 | ||
448 | #ifdef CGEN_PRINT_ADDRESS | |
449 | CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length); | |
450 | #endif | |
451 | ||
452 | /* Print the operand as directed by the attributes. */ | |
453 | if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) | |
454 | ; /* nothing to do */ | |
455 | else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) | |
456 | (*info->print_address_func) (value, info); | |
457 | else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) | |
458 | (*info->print_address_func) (value, info); | |
459 | else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) | |
460 | (*info->fprintf_func) (info->stream, "%ld", (long) value); | |
461 | else | |
462 | (*info->fprintf_func) (info->stream, "0x%lx", (long) value); | |
463 | } | |
464 | ||
465 | /* Keyword print handler. */ | |
466 | ||
467 | static void | |
ffead7ae MM |
468 | print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, |
469 | void *dis_info, | |
470 | CGEN_KEYWORD *keyword_table, | |
471 | long value, | |
472 | unsigned int attrs ATTRIBUTE_UNUSED) | |
fd3c93d5 DB |
473 | { |
474 | disassemble_info *info = (disassemble_info *) dis_info; | |
475 | const CGEN_KEYWORD_ENTRY *ke; | |
476 | ||
477 | ke = cgen_keyword_lookup_value (keyword_table, value); | |
478 | if (ke != NULL) | |
479 | (*info->fprintf_func) (info->stream, "%s", ke->name); | |
480 | else | |
481 | (*info->fprintf_func) (info->stream, "???"); | |
482 | } | |
483 | \f | |
484 | /* Default insn printer. | |
485 | ||
ffead7ae | 486 | DIS_INFO is defined as `void *' so the disassembler needn't know anything |
fd3c93d5 DB |
487 | about disassemble_info. */ |
488 | ||
489 | static void | |
ffead7ae MM |
490 | print_insn_normal (CGEN_CPU_DESC cd, |
491 | void *dis_info, | |
492 | const CGEN_INSN *insn, | |
493 | CGEN_FIELDS *fields, | |
494 | bfd_vma pc, | |
495 | int length) | |
fd3c93d5 DB |
496 | { |
497 | const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); | |
498 | disassemble_info *info = (disassemble_info *) dis_info; | |
499 | const CGEN_SYNTAX_CHAR_TYPE *syn; | |
500 | ||
501 | CGEN_INIT_PRINT (cd); | |
502 | ||
503 | for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) | |
504 | { | |
505 | if (CGEN_SYNTAX_MNEMONIC_P (*syn)) | |
506 | { | |
507 | (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); | |
508 | continue; | |
509 | } | |
510 | if (CGEN_SYNTAX_CHAR_P (*syn)) | |
511 | { | |
512 | (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); | |
513 | continue; | |
514 | } | |
515 | ||
516 | /* We have an operand. */ | |
517 | frv_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, | |
518 | fields, CGEN_INSN_ATTRS (insn), pc, length); | |
519 | } | |
520 | } | |
521 | \f | |
522 | /* Subroutine of print_insn. Reads an insn into the given buffers and updates | |
523 | the extract info. | |
524 | Returns 0 if all is well, non-zero otherwise. */ | |
525 | ||
526 | static int | |
ffead7ae MM |
527 | read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, |
528 | bfd_vma pc, | |
529 | disassemble_info *info, | |
530 | char *buf, | |
531 | int buflen, | |
532 | CGEN_EXTRACT_INFO *ex_info, | |
533 | unsigned long *insn_value) | |
fd3c93d5 DB |
534 | { |
535 | int status = (*info->read_memory_func) (pc, buf, buflen, info); | |
536 | if (status != 0) | |
537 | { | |
538 | (*info->memory_error_func) (status, pc, info); | |
539 | return -1; | |
540 | } | |
541 | ||
542 | ex_info->dis_info = info; | |
543 | ex_info->valid = (1 << buflen) - 1; | |
544 | ex_info->insn_bytes = buf; | |
545 | ||
546 | *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); | |
547 | return 0; | |
548 | } | |
549 | ||
550 | /* Utility to print an insn. | |
551 | BUF is the base part of the insn, target byte order, BUFLEN bytes long. | |
552 | The result is the size of the insn in bytes or zero for an unknown insn | |
553 | or -1 if an error occurs fetching data (memory_error_func will have | |
554 | been called). */ | |
555 | ||
556 | static int | |
ffead7ae MM |
557 | print_insn (CGEN_CPU_DESC cd, |
558 | bfd_vma pc, | |
559 | disassemble_info *info, | |
560 | char *buf, | |
561 | unsigned int buflen) | |
fd3c93d5 DB |
562 | { |
563 | CGEN_INSN_INT insn_value; | |
564 | const CGEN_INSN_LIST *insn_list; | |
565 | CGEN_EXTRACT_INFO ex_info; | |
566 | int basesize; | |
567 | ||
568 | /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ | |
569 | basesize = cd->base_insn_bitsize < buflen * 8 ? | |
570 | cd->base_insn_bitsize : buflen * 8; | |
571 | insn_value = cgen_get_insn_value (cd, buf, basesize); | |
572 | ||
573 | ||
574 | /* Fill in ex_info fields like read_insn would. Don't actually call | |
575 | read_insn, since the incoming buffer is already read (and possibly | |
576 | modified a la m32r). */ | |
577 | ex_info.valid = (1 << buflen) - 1; | |
578 | ex_info.dis_info = info; | |
579 | ex_info.insn_bytes = buf; | |
580 | ||
581 | /* The instructions are stored in hash lists. | |
582 | Pick the first one and keep trying until we find the right one. */ | |
583 | ||
584 | insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value); | |
585 | while (insn_list != NULL) | |
586 | { | |
587 | const CGEN_INSN *insn = insn_list->insn; | |
588 | CGEN_FIELDS fields; | |
589 | int length; | |
590 | unsigned long insn_value_cropped; | |
591 | ||
592 | #ifdef CGEN_VALIDATE_INSN_SUPPORTED | |
593 | /* Not needed as insn shouldn't be in hash lists if not supported. */ | |
594 | /* Supported by this cpu? */ | |
595 | if (! frv_cgen_insn_supported (cd, insn)) | |
596 | { | |
597 | insn_list = CGEN_DIS_NEXT_INSN (insn_list); | |
598 | continue; | |
599 | } | |
600 | #endif | |
601 | ||
602 | /* Basic bit mask must be correct. */ | |
603 | /* ??? May wish to allow target to defer this check until the extract | |
604 | handler. */ | |
605 | ||
606 | /* Base size may exceed this instruction's size. Extract the | |
607 | relevant part from the buffer. */ | |
608 | if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && | |
609 | (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) | |
610 | insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), | |
611 | info->endian == BFD_ENDIAN_BIG); | |
612 | else | |
613 | insn_value_cropped = insn_value; | |
614 | ||
615 | if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) | |
616 | == CGEN_INSN_BASE_VALUE (insn)) | |
617 | { | |
618 | /* Printing is handled in two passes. The first pass parses the | |
619 | machine insn and extracts the fields. The second pass prints | |
620 | them. */ | |
621 | ||
622 | /* Make sure the entire insn is loaded into insn_value, if it | |
623 | can fit. */ | |
624 | if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && | |
625 | (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) | |
626 | { | |
627 | unsigned long full_insn_value; | |
628 | int rc = read_insn (cd, pc, info, buf, | |
629 | CGEN_INSN_BITSIZE (insn) / 8, | |
630 | & ex_info, & full_insn_value); | |
631 | if (rc != 0) | |
632 | return rc; | |
633 | length = CGEN_EXTRACT_FN (cd, insn) | |
634 | (cd, insn, &ex_info, full_insn_value, &fields, pc); | |
635 | } | |
636 | else | |
637 | length = CGEN_EXTRACT_FN (cd, insn) | |
638 | (cd, insn, &ex_info, insn_value_cropped, &fields, pc); | |
639 | ||
640 | /* length < 0 -> error */ | |
641 | if (length < 0) | |
642 | return length; | |
643 | if (length > 0) | |
644 | { | |
645 | CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); | |
646 | /* length is in bits, result is in bytes */ | |
647 | return length / 8; | |
648 | } | |
649 | } | |
650 | ||
651 | insn_list = CGEN_DIS_NEXT_INSN (insn_list); | |
652 | } | |
653 | ||
654 | return 0; | |
655 | } | |
656 | ||
657 | /* Default value for CGEN_PRINT_INSN. | |
658 | The result is the size of the insn in bytes or zero for an unknown insn | |
659 | or -1 if an error occured fetching bytes. */ | |
660 | ||
661 | #ifndef CGEN_PRINT_INSN | |
662 | #define CGEN_PRINT_INSN default_print_insn | |
663 | #endif | |
664 | ||
665 | static int | |
ffead7ae | 666 | default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) |
fd3c93d5 DB |
667 | { |
668 | char buf[CGEN_MAX_INSN_SIZE]; | |
669 | int buflen; | |
670 | int status; | |
671 | ||
672 | /* Attempt to read the base part of the insn. */ | |
673 | buflen = cd->base_insn_bitsize / 8; | |
674 | status = (*info->read_memory_func) (pc, buf, buflen, info); | |
675 | ||
676 | /* Try again with the minimum part, if min < base. */ | |
677 | if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) | |
678 | { | |
679 | buflen = cd->min_insn_bitsize / 8; | |
680 | status = (*info->read_memory_func) (pc, buf, buflen, info); | |
681 | } | |
682 | ||
683 | if (status != 0) | |
684 | { | |
685 | (*info->memory_error_func) (status, pc, info); | |
686 | return -1; | |
687 | } | |
688 | ||
689 | return print_insn (cd, pc, info, buf, buflen); | |
690 | } | |
691 | ||
692 | /* Main entry point. | |
693 | Print one instruction from PC on INFO->STREAM. | |
694 | Return the size of the instruction (in bytes). */ | |
695 | ||
696 | typedef struct cpu_desc_list { | |
697 | struct cpu_desc_list *next; | |
698 | int isa; | |
699 | int mach; | |
700 | int endian; | |
701 | CGEN_CPU_DESC cd; | |
702 | } cpu_desc_list; | |
703 | ||
704 | int | |
ffead7ae | 705 | print_insn_frv (bfd_vma pc, disassemble_info *info) |
fd3c93d5 DB |
706 | { |
707 | static cpu_desc_list *cd_list = 0; | |
708 | cpu_desc_list *cl = 0; | |
709 | static CGEN_CPU_DESC cd = 0; | |
710 | static int prev_isa; | |
711 | static int prev_mach; | |
712 | static int prev_endian; | |
713 | int length; | |
714 | int isa,mach; | |
715 | int endian = (info->endian == BFD_ENDIAN_BIG | |
716 | ? CGEN_ENDIAN_BIG | |
717 | : CGEN_ENDIAN_LITTLE); | |
718 | enum bfd_architecture arch; | |
719 | ||
720 | /* ??? gdb will set mach but leave the architecture as "unknown" */ | |
721 | #ifndef CGEN_BFD_ARCH | |
722 | #define CGEN_BFD_ARCH bfd_arch_frv | |
723 | #endif | |
724 | arch = info->arch; | |
725 | if (arch == bfd_arch_unknown) | |
726 | arch = CGEN_BFD_ARCH; | |
727 | ||
728 | /* There's no standard way to compute the machine or isa number | |
729 | so we leave it to the target. */ | |
730 | #ifdef CGEN_COMPUTE_MACH | |
731 | mach = CGEN_COMPUTE_MACH (info); | |
732 | #else | |
733 | mach = info->mach; | |
734 | #endif | |
735 | ||
736 | #ifdef CGEN_COMPUTE_ISA | |
737 | isa = CGEN_COMPUTE_ISA (info); | |
738 | #else | |
739 | isa = info->insn_sets; | |
740 | #endif | |
741 | ||
742 | /* If we've switched cpu's, try to find a handle we've used before */ | |
743 | if (cd | |
744 | && (isa != prev_isa | |
745 | || mach != prev_mach | |
746 | || endian != prev_endian)) | |
747 | { | |
748 | cd = 0; | |
749 | for (cl = cd_list; cl; cl = cl->next) | |
750 | { | |
751 | if (cl->isa == isa && | |
752 | cl->mach == mach && | |
753 | cl->endian == endian) | |
754 | { | |
755 | cd = cl->cd; | |
756 | break; | |
757 | } | |
758 | } | |
759 | } | |
760 | ||
761 | /* If we haven't initialized yet, initialize the opcode table. */ | |
762 | if (! cd) | |
763 | { | |
764 | const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); | |
765 | const char *mach_name; | |
766 | ||
767 | if (!arch_type) | |
768 | abort (); | |
769 | mach_name = arch_type->printable_name; | |
770 | ||
771 | prev_isa = isa; | |
772 | prev_mach = mach; | |
773 | prev_endian = endian; | |
774 | cd = frv_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, | |
775 | CGEN_CPU_OPEN_BFDMACH, mach_name, | |
776 | CGEN_CPU_OPEN_ENDIAN, prev_endian, | |
777 | CGEN_CPU_OPEN_END); | |
778 | if (!cd) | |
779 | abort (); | |
780 | ||
781 | /* save this away for future reference */ | |
782 | cl = xmalloc (sizeof (struct cpu_desc_list)); | |
783 | cl->cd = cd; | |
784 | cl->isa = isa; | |
785 | cl->mach = mach; | |
786 | cl->endian = endian; | |
787 | cl->next = cd_list; | |
788 | cd_list = cl; | |
789 | ||
790 | frv_cgen_init_dis (cd); | |
791 | } | |
792 | ||
793 | /* We try to have as much common code as possible. | |
794 | But at this point some targets need to take over. */ | |
795 | /* ??? Some targets may need a hook elsewhere. Try to avoid this, | |
796 | but if not possible try to move this hook elsewhere rather than | |
797 | have two hooks. */ | |
798 | length = CGEN_PRINT_INSN (cd, pc, info); | |
799 | if (length > 0) | |
800 | return length; | |
801 | if (length < 0) | |
802 | return -1; | |
803 | ||
804 | (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); | |
805 | return cd->default_insn_bitsize / 8; | |
806 | } |