Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
4b95cf5c | 2 | Copyright (C) 1988-2014 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
20f0a1fc | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
8 | the Free Software Foundation; either version 3, or (at your option) |
9 | any later version. | |
20f0a1fc | 10 | |
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
20f0a1fc NC |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
20 | ||
20f0a1fc NC |
21 | |
22 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
23 | July 1988 | |
24 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
25 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
27 | ||
28 | /* The main tables describing the instructions is essentially a copy | |
29 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
30 | Programmers Manual. Usually, there is a capital letter, followed | |
31 | by a small letter. The capital letter tell the addressing mode, | |
32 | and the small letter tells about the operand size. Refer to | |
33 | the Intel manual for details. */ | |
252b5132 | 34 | |
252b5132 | 35 | #include "sysdep.h" |
dabbade6 | 36 | #include "dis-asm.h" |
252b5132 | 37 | #include "opintl.h" |
0b1cf022 | 38 | #include "opcode/i386.h" |
85f10a01 | 39 | #include "libiberty.h" |
252b5132 RH |
40 | |
41 | #include <setjmp.h> | |
42 | ||
26ca5450 AJ |
43 | static int print_insn (bfd_vma, disassemble_info *); |
44 | static void dofloat (int); | |
45 | static void OP_ST (int, int); | |
46 | static void OP_STi (int, int); | |
47 | static int putop (const char *, int); | |
48 | static void oappend (const char *); | |
49 | static void append_seg (void); | |
50 | static void OP_indirE (int, int); | |
51 | static void print_operand_value (char *, int, bfd_vma); | |
c0f3af97 | 52 | static void OP_E_register (int, int); |
c1e679ec | 53 | static void OP_E_memory (int, int); |
5d669648 | 54 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
55 | static void OP_E (int, int); |
56 | static void OP_G (int, int); | |
57 | static bfd_vma get64 (void); | |
58 | static bfd_signed_vma get32 (void); | |
59 | static bfd_signed_vma get32s (void); | |
60 | static int get16 (void); | |
61 | static void set_op (bfd_vma, int); | |
b844680a | 62 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
63 | static void OP_REG (int, int); |
64 | static void OP_IMREG (int, int); | |
65 | static void OP_I (int, int); | |
66 | static void OP_I64 (int, int); | |
67 | static void OP_sI (int, int); | |
68 | static void OP_J (int, int); | |
69 | static void OP_SEG (int, int); | |
70 | static void OP_DIR (int, int); | |
71 | static void OP_OFF (int, int); | |
72 | static void OP_OFF64 (int, int); | |
73 | static void ptr_reg (int, int); | |
74 | static void OP_ESreg (int, int); | |
75 | static void OP_DSreg (int, int); | |
76 | static void OP_C (int, int); | |
77 | static void OP_D (int, int); | |
78 | static void OP_T (int, int); | |
6f74c397 | 79 | static void OP_R (int, int); |
26ca5450 AJ |
80 | static void OP_MMX (int, int); |
81 | static void OP_XMM (int, int); | |
82 | static void OP_EM (int, int); | |
83 | static void OP_EX (int, int); | |
4d9567e0 MM |
84 | static void OP_EMC (int,int); |
85 | static void OP_MXC (int,int); | |
26ca5450 AJ |
86 | static void OP_MS (int, int); |
87 | static void OP_XS (int, int); | |
cc0ec051 | 88 | static void OP_M (int, int); |
c0f3af97 L |
89 | static void OP_VEX (int, int); |
90 | static void OP_EX_Vex (int, int); | |
922d8de8 | 91 | static void OP_EX_VexW (int, int); |
a683cc34 | 92 | static void OP_EX_VexImmW (int, int); |
c0f3af97 | 93 | static void OP_XMM_Vex (int, int); |
922d8de8 | 94 | static void OP_XMM_VexW (int, int); |
43234a1e | 95 | static void OP_Rounding (int, int); |
c0f3af97 L |
96 | static void OP_REG_VexI4 (int, int); |
97 | static void PCLMUL_Fixup (int, int); | |
922d8de8 | 98 | static void VEXI4_Fixup (int, int); |
c0f3af97 L |
99 | static void VZERO_Fixup (int, int); |
100 | static void VCMP_Fixup (int, int); | |
43234a1e | 101 | static void VPCMP_Fixup (int, int); |
cc0ec051 | 102 | static void OP_0f07 (int, int); |
b844680a L |
103 | static void OP_Monitor (int, int); |
104 | static void OP_Mwait (int, int); | |
46e883c5 L |
105 | static void NOP_Fixup1 (int, int); |
106 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 107 | static void OP_3DNowSuffix (int, int); |
ad19981d | 108 | static void CMP_Fixup (int, int); |
26ca5450 | 109 | static void BadOp (void); |
35c52694 | 110 | static void REP_Fixup (int, int); |
7e8b059b | 111 | static void BND_Fixup (int, int); |
42164a71 L |
112 | static void HLE_Fixup1 (int, int); |
113 | static void HLE_Fixup2 (int, int); | |
114 | static void HLE_Fixup3 (int, int); | |
f5804c90 | 115 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 116 | static void XMM_Fixup (int, int); |
381d071f | 117 | static void CRC32_Fixup (int, int); |
eacc9c89 | 118 | static void FXSAVE_Fixup (int, int); |
f88c9eb0 SP |
119 | static void OP_LWPCB_E (int, int); |
120 | static void OP_LWP_E (int, int); | |
5dd85c99 SP |
121 | static void OP_Vex_2src_1 (int, int); |
122 | static void OP_Vex_2src_2 (int, int); | |
c1e679ec | 123 | |
f1f8f695 | 124 | static void MOVBE_Fixup (int, int); |
252b5132 | 125 | |
43234a1e L |
126 | static void OP_Mask (int, int); |
127 | ||
6608db57 | 128 | struct dis_private { |
252b5132 RH |
129 | /* Points to first byte not fetched. */ |
130 | bfd_byte *max_fetched; | |
0b1cf022 | 131 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 132 | bfd_vma insn_start; |
e396998b | 133 | int orig_sizeflag; |
252b5132 RH |
134 | jmp_buf bailout; |
135 | }; | |
136 | ||
cb712a9e L |
137 | enum address_mode |
138 | { | |
139 | mode_16bit, | |
140 | mode_32bit, | |
141 | mode_64bit | |
142 | }; | |
143 | ||
144 | enum address_mode address_mode; | |
52b15da3 | 145 | |
5076851f ILT |
146 | /* Flags for the prefixes for the current instruction. See below. */ |
147 | static int prefixes; | |
148 | ||
52b15da3 JH |
149 | /* REX prefix the current instruction. See below. */ |
150 | static int rex; | |
151 | /* Bits of REX we've already used. */ | |
152 | static int rex_used; | |
d869730d | 153 | /* REX bits in original REX prefix ignored. */ |
c0f3af97 | 154 | static int rex_ignored; |
52b15da3 JH |
155 | /* Mark parts used in the REX prefix. When we are testing for |
156 | empty prefix (for 8bit register REX extension), just mask it | |
157 | out. Otherwise test for REX bit is excuse for existence of REX | |
158 | only in case value is nonzero. */ | |
159 | #define USED_REX(value) \ | |
160 | { \ | |
161 | if (value) \ | |
161a04f6 L |
162 | { \ |
163 | if ((rex & value)) \ | |
164 | rex_used |= (value) | REX_OPCODE; \ | |
165 | } \ | |
52b15da3 | 166 | else \ |
161a04f6 | 167 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
168 | } |
169 | ||
7d421014 ILT |
170 | /* Flags for prefixes which we somehow handled when printing the |
171 | current instruction. */ | |
172 | static int used_prefixes; | |
173 | ||
5076851f ILT |
174 | /* Flags stored in PREFIXES. */ |
175 | #define PREFIX_REPZ 1 | |
176 | #define PREFIX_REPNZ 2 | |
177 | #define PREFIX_LOCK 4 | |
178 | #define PREFIX_CS 8 | |
179 | #define PREFIX_SS 0x10 | |
180 | #define PREFIX_DS 0x20 | |
181 | #define PREFIX_ES 0x40 | |
182 | #define PREFIX_FS 0x80 | |
183 | #define PREFIX_GS 0x100 | |
184 | #define PREFIX_DATA 0x200 | |
185 | #define PREFIX_ADDR 0x400 | |
186 | #define PREFIX_FWAIT 0x800 | |
187 | ||
252b5132 RH |
188 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
189 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
190 | on error. */ | |
191 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 192 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
193 | ? 1 : fetch_data ((info), (addr))) |
194 | ||
195 | static int | |
26ca5450 | 196 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
197 | { |
198 | int status; | |
6608db57 | 199 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
200 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
201 | ||
0b1cf022 | 202 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
203 | status = (*info->read_memory_func) (start, |
204 | priv->max_fetched, | |
205 | addr - priv->max_fetched, | |
206 | info); | |
207 | else | |
208 | status = -1; | |
252b5132 RH |
209 | if (status != 0) |
210 | { | |
7d421014 | 211 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
212 | print_insn_i386 will do something sensible. Otherwise, print |
213 | an error. We do that here because this is where we know | |
214 | STATUS. */ | |
7d421014 | 215 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 216 | (*info->memory_error_func) (status, start, info); |
252b5132 RH |
217 | longjmp (priv->bailout, 1); |
218 | } | |
219 | else | |
220 | priv->max_fetched = addr; | |
221 | return 1; | |
222 | } | |
223 | ||
ce518a5f | 224 | #define XX { NULL, 0 } |
592d1631 | 225 | #define Bad_Opcode NULL, { { NULL, 0 } } |
ce518a5f L |
226 | |
227 | #define Eb { OP_E, b_mode } | |
7e8b059b | 228 | #define Ebnd { OP_E, bnd_mode } |
b6169b20 | 229 | #define EbS { OP_E, b_swap_mode } |
ce518a5f | 230 | #define Ev { OP_E, v_mode } |
7e8b059b | 231 | #define Ev_bnd { OP_E, v_bnd_mode } |
b6169b20 | 232 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
233 | #define Ed { OP_E, d_mode } |
234 | #define Edq { OP_E, dq_mode } | |
235 | #define Edqw { OP_E, dqw_mode } | |
42903f7f L |
236 | #define Edqb { OP_E, dqb_mode } |
237 | #define Edqd { OP_E, dqd_mode } | |
09335d05 | 238 | #define Eq { OP_E, q_mode } |
ce518a5f L |
239 | #define indirEv { OP_indirE, stack_v_mode } |
240 | #define indirEp { OP_indirE, f_mode } | |
241 | #define stackEv { OP_E, stack_v_mode } | |
242 | #define Em { OP_E, m_mode } | |
243 | #define Ew { OP_E, w_mode } | |
244 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 245 | #define Ma { OP_M, a_mode } |
b844680a | 246 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 247 | #define Md { OP_M, d_mode } |
f1f8f695 | 248 | #define Mo { OP_M, o_mode } |
ce518a5f L |
249 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
250 | #define Mq { OP_M, q_mode } | |
4ee52178 | 251 | #define Mx { OP_M, x_mode } |
c0f3af97 | 252 | #define Mxmm { OP_M, xmm_mode } |
ce518a5f | 253 | #define Gb { OP_G, b_mode } |
7e8b059b | 254 | #define Gbnd { OP_G, bnd_mode } |
ce518a5f L |
255 | #define Gv { OP_G, v_mode } |
256 | #define Gd { OP_G, d_mode } | |
257 | #define Gdq { OP_G, dq_mode } | |
258 | #define Gm { OP_G, m_mode } | |
259 | #define Gw { OP_G, w_mode } | |
6f74c397 | 260 | #define Rd { OP_R, d_mode } |
43234a1e | 261 | #define Rdq { OP_R, dq_mode } |
6f74c397 | 262 | #define Rm { OP_R, m_mode } |
ce518a5f L |
263 | #define Ib { OP_I, b_mode } |
264 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
e3949f17 | 265 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
ce518a5f | 266 | #define Iv { OP_I, v_mode } |
7bb15c6f | 267 | #define sIv { OP_sI, v_mode } |
ce518a5f L |
268 | #define Iq { OP_I, q_mode } |
269 | #define Iv64 { OP_I64, v_mode } | |
270 | #define Iw { OP_I, w_mode } | |
271 | #define I1 { OP_I, const_1_mode } | |
272 | #define Jb { OP_J, b_mode } | |
273 | #define Jv { OP_J, v_mode } | |
274 | #define Cm { OP_C, m_mode } | |
275 | #define Dm { OP_D, m_mode } | |
276 | #define Td { OP_T, d_mode } | |
b844680a | 277 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
278 | |
279 | #define RMeAX { OP_REG, eAX_reg } | |
280 | #define RMeBX { OP_REG, eBX_reg } | |
281 | #define RMeCX { OP_REG, eCX_reg } | |
282 | #define RMeDX { OP_REG, eDX_reg } | |
283 | #define RMeSP { OP_REG, eSP_reg } | |
284 | #define RMeBP { OP_REG, eBP_reg } | |
285 | #define RMeSI { OP_REG, eSI_reg } | |
286 | #define RMeDI { OP_REG, eDI_reg } | |
287 | #define RMrAX { OP_REG, rAX_reg } | |
288 | #define RMrBX { OP_REG, rBX_reg } | |
289 | #define RMrCX { OP_REG, rCX_reg } | |
290 | #define RMrDX { OP_REG, rDX_reg } | |
291 | #define RMrSP { OP_REG, rSP_reg } | |
292 | #define RMrBP { OP_REG, rBP_reg } | |
293 | #define RMrSI { OP_REG, rSI_reg } | |
294 | #define RMrDI { OP_REG, rDI_reg } | |
295 | #define RMAL { OP_REG, al_reg } | |
ce518a5f L |
296 | #define RMCL { OP_REG, cl_reg } |
297 | #define RMDL { OP_REG, dl_reg } | |
298 | #define RMBL { OP_REG, bl_reg } | |
299 | #define RMAH { OP_REG, ah_reg } | |
300 | #define RMCH { OP_REG, ch_reg } | |
301 | #define RMDH { OP_REG, dh_reg } | |
302 | #define RMBH { OP_REG, bh_reg } | |
303 | #define RMAX { OP_REG, ax_reg } | |
304 | #define RMDX { OP_REG, dx_reg } | |
305 | ||
306 | #define eAX { OP_IMREG, eAX_reg } | |
307 | #define eBX { OP_IMREG, eBX_reg } | |
308 | #define eCX { OP_IMREG, eCX_reg } | |
309 | #define eDX { OP_IMREG, eDX_reg } | |
310 | #define eSP { OP_IMREG, eSP_reg } | |
311 | #define eBP { OP_IMREG, eBP_reg } | |
312 | #define eSI { OP_IMREG, eSI_reg } | |
313 | #define eDI { OP_IMREG, eDI_reg } | |
314 | #define AL { OP_IMREG, al_reg } | |
315 | #define CL { OP_IMREG, cl_reg } | |
316 | #define DL { OP_IMREG, dl_reg } | |
317 | #define BL { OP_IMREG, bl_reg } | |
318 | #define AH { OP_IMREG, ah_reg } | |
319 | #define CH { OP_IMREG, ch_reg } | |
320 | #define DH { OP_IMREG, dh_reg } | |
321 | #define BH { OP_IMREG, bh_reg } | |
322 | #define AX { OP_IMREG, ax_reg } | |
323 | #define DX { OP_IMREG, dx_reg } | |
324 | #define zAX { OP_IMREG, z_mode_ax_reg } | |
325 | #define indirDX { OP_IMREG, indir_dx_reg } | |
326 | ||
327 | #define Sw { OP_SEG, w_mode } | |
328 | #define Sv { OP_SEG, v_mode } | |
329 | #define Ap { OP_DIR, 0 } | |
330 | #define Ob { OP_OFF64, b_mode } | |
331 | #define Ov { OP_OFF64, v_mode } | |
332 | #define Xb { OP_DSreg, eSI_reg } | |
333 | #define Xv { OP_DSreg, eSI_reg } | |
334 | #define Xz { OP_DSreg, eSI_reg } | |
335 | #define Yb { OP_ESreg, eDI_reg } | |
336 | #define Yv { OP_ESreg, eDI_reg } | |
337 | #define DSBX { OP_DSreg, eBX_reg } | |
338 | ||
339 | #define es { OP_REG, es_reg } | |
340 | #define ss { OP_REG, ss_reg } | |
341 | #define cs { OP_REG, cs_reg } | |
342 | #define ds { OP_REG, ds_reg } | |
343 | #define fs { OP_REG, fs_reg } | |
344 | #define gs { OP_REG, gs_reg } | |
345 | ||
346 | #define MX { OP_MMX, 0 } | |
347 | #define XM { OP_XMM, 0 } | |
539f890d | 348 | #define XMScalar { OP_XMM, scalar_mode } |
6c30d220 | 349 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
c0f3af97 | 350 | #define XMM { OP_XMM, xmm_mode } |
43234a1e | 351 | #define XMxmmq { OP_XMM, xmmq_mode } |
ce518a5f | 352 | #define EM { OP_EM, v_mode } |
b6169b20 | 353 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 354 | #define EMd { OP_EM, d_mode } |
14051056 | 355 | #define EMx { OP_EM, x_mode } |
8976381e | 356 | #define EXw { OP_EX, w_mode } |
09a2c6cf | 357 | #define EXd { OP_EX, d_mode } |
539f890d | 358 | #define EXdScalar { OP_EX, d_scalar_mode } |
fa99fab2 | 359 | #define EXdS { OP_EX, d_swap_mode } |
43234a1e | 360 | #define EXdScalarS { OP_EX, d_scalar_swap_mode } |
09a2c6cf | 361 | #define EXq { OP_EX, q_mode } |
539f890d L |
362 | #define EXqScalar { OP_EX, q_scalar_mode } |
363 | #define EXqScalarS { OP_EX, q_scalar_swap_mode } | |
b6169b20 | 364 | #define EXqS { OP_EX, q_swap_mode } |
09a2c6cf | 365 | #define EXx { OP_EX, x_mode } |
b6169b20 | 366 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 | 367 | #define EXxmm { OP_EX, xmm_mode } |
43234a1e | 368 | #define EXymm { OP_EX, ymm_mode } |
c0f3af97 | 369 | #define EXxmmq { OP_EX, xmmq_mode } |
43234a1e | 370 | #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } |
6c30d220 L |
371 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
372 | #define EXxmm_mw { OP_EX, xmm_mw_mode } | |
373 | #define EXxmm_md { OP_EX, xmm_md_mode } | |
374 | #define EXxmm_mq { OP_EX, xmm_mq_mode } | |
43234a1e | 375 | #define EXxmm_mdq { OP_EX, xmm_mdq_mode } |
6c30d220 L |
376 | #define EXxmmdw { OP_EX, xmmdw_mode } |
377 | #define EXxmmqd { OP_EX, xmmqd_mode } | |
c0f3af97 | 378 | #define EXymmq { OP_EX, ymmq_mode } |
0bfee649 | 379 | #define EXVexWdq { OP_EX, vex_w_dq_mode } |
1c480963 | 380 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
43234a1e L |
381 | #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } |
382 | #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } | |
ce518a5f L |
383 | #define MS { OP_MS, v_mode } |
384 | #define XS { OP_XS, v_mode } | |
09335d05 | 385 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 386 | #define MXC { OP_MXC, 0 } |
ce518a5f | 387 | #define OPSUF { OP_3DNowSuffix, 0 } |
ad19981d | 388 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 389 | #define XMM0 { XMM_Fixup, 0 } |
eacc9c89 | 390 | #define FXSAVE { FXSAVE_Fixup, 0 } |
5dd85c99 SP |
391 | #define Vex_2src_1 { OP_Vex_2src_1, 0 } |
392 | #define Vex_2src_2 { OP_Vex_2src_2, 0 } | |
252b5132 | 393 | |
c0f3af97 | 394 | #define Vex { OP_VEX, vex_mode } |
539f890d | 395 | #define VexScalar { OP_VEX, vex_scalar_mode } |
6c30d220 | 396 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
c0f3af97 L |
397 | #define Vex128 { OP_VEX, vex128_mode } |
398 | #define Vex256 { OP_VEX, vex256_mode } | |
cb21baef | 399 | #define VexGdq { OP_VEX, dq_mode } |
922d8de8 | 400 | #define VexI4 { VEXI4_Fixup, 0} |
c0f3af97 | 401 | #define EXdVex { OP_EX_Vex, d_mode } |
fa99fab2 | 402 | #define EXdVexS { OP_EX_Vex, d_swap_mode } |
539f890d | 403 | #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } |
c0f3af97 | 404 | #define EXqVex { OP_EX_Vex, q_mode } |
fa99fab2 | 405 | #define EXqVexS { OP_EX_Vex, q_swap_mode } |
539f890d | 406 | #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } |
922d8de8 DR |
407 | #define EXVexW { OP_EX_VexW, x_mode } |
408 | #define EXdVexW { OP_EX_VexW, d_mode } | |
409 | #define EXqVexW { OP_EX_VexW, q_mode } | |
a683cc34 | 410 | #define EXVexImmW { OP_EX_VexImmW, x_mode } |
c0f3af97 | 411 | #define XMVex { OP_XMM_Vex, 0 } |
539f890d | 412 | #define XMVexScalar { OP_XMM_Vex, scalar_mode } |
922d8de8 | 413 | #define XMVexW { OP_XMM_VexW, 0 } |
c0f3af97 L |
414 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
415 | #define PCLMUL { PCLMUL_Fixup, 0 } | |
416 | #define VZERO { VZERO_Fixup, 0 } | |
417 | #define VCMP { VCMP_Fixup, 0 } | |
43234a1e L |
418 | #define VPCMP { VPCMP_Fixup, 0 } |
419 | ||
420 | #define EXxEVexR { OP_Rounding, evex_rounding_mode } | |
421 | #define EXxEVexS { OP_Rounding, evex_sae_mode } | |
422 | ||
423 | #define XMask { OP_Mask, mask_mode } | |
424 | #define MaskG { OP_G, mask_mode } | |
425 | #define MaskE { OP_E, mask_mode } | |
426 | #define MaskR { OP_R, mask_mode } | |
427 | #define MaskVex { OP_VEX, mask_mode } | |
c0f3af97 | 428 | |
6c30d220 | 429 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
5fc35d96 | 430 | #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } |
6c30d220 | 431 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
5fc35d96 | 432 | #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } |
6c30d220 | 433 | |
35c52694 | 434 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
435 | #define Xbr { REP_Fixup, eSI_reg } |
436 | #define Xvr { REP_Fixup, eSI_reg } | |
437 | #define Ybr { REP_Fixup, eDI_reg } | |
438 | #define Yvr { REP_Fixup, eDI_reg } | |
439 | #define Yzr { REP_Fixup, eDI_reg } | |
440 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
441 | #define ALr { REP_Fixup, al_reg } | |
442 | #define eAXr { REP_Fixup, eAX_reg } | |
443 | ||
42164a71 L |
444 | /* Used handle HLE prefix for lockable instructions. */ |
445 | #define Ebh1 { HLE_Fixup1, b_mode } | |
446 | #define Evh1 { HLE_Fixup1, v_mode } | |
447 | #define Ebh2 { HLE_Fixup2, b_mode } | |
448 | #define Evh2 { HLE_Fixup2, v_mode } | |
449 | #define Ebh3 { HLE_Fixup3, b_mode } | |
450 | #define Evh3 { HLE_Fixup3, v_mode } | |
451 | ||
7e8b059b L |
452 | #define BND { BND_Fixup, 0 } |
453 | ||
ce518a5f L |
454 | #define cond_jump_flag { NULL, cond_jump_mode } |
455 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 456 | |
252b5132 | 457 | /* bits in sizeflag */ |
252b5132 | 458 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
459 | #define AFLAG 2 |
460 | #define DFLAG 1 | |
461 | ||
51e7da1b L |
462 | enum |
463 | { | |
464 | /* byte operand */ | |
465 | b_mode = 1, | |
466 | /* byte operand with operand swapped */ | |
3873ba12 | 467 | b_swap_mode, |
e3949f17 L |
468 | /* byte operand, sign extend like 'T' suffix */ |
469 | b_T_mode, | |
51e7da1b | 470 | /* operand size depends on prefixes */ |
3873ba12 | 471 | v_mode, |
51e7da1b | 472 | /* operand size depends on prefixes with operand swapped */ |
3873ba12 | 473 | v_swap_mode, |
51e7da1b | 474 | /* word operand */ |
3873ba12 | 475 | w_mode, |
51e7da1b | 476 | /* double word operand */ |
3873ba12 | 477 | d_mode, |
51e7da1b | 478 | /* double word operand with operand swapped */ |
3873ba12 | 479 | d_swap_mode, |
51e7da1b | 480 | /* quad word operand */ |
3873ba12 | 481 | q_mode, |
51e7da1b | 482 | /* quad word operand with operand swapped */ |
3873ba12 | 483 | q_swap_mode, |
51e7da1b | 484 | /* ten-byte operand */ |
3873ba12 | 485 | t_mode, |
43234a1e L |
486 | /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
487 | broadcast enabled. */ | |
3873ba12 | 488 | x_mode, |
43234a1e L |
489 | /* Similar to x_mode, but with different EVEX mem shifts. */ |
490 | evex_x_gscat_mode, | |
491 | /* Similar to x_mode, but with disabled broadcast. */ | |
492 | evex_x_nobcst_mode, | |
493 | /* Similar to x_mode, but with operands swapped and disabled broadcast | |
494 | in EVEX. */ | |
3873ba12 | 495 | x_swap_mode, |
51e7da1b | 496 | /* 16-byte XMM operand */ |
3873ba12 | 497 | xmm_mode, |
43234a1e L |
498 | /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
499 | memory operand (depending on vector length). Broadcast isn't | |
500 | allowed. */ | |
3873ba12 | 501 | xmmq_mode, |
43234a1e L |
502 | /* Same as xmmq_mode, but broadcast is allowed. */ |
503 | evex_half_bcst_xmmq_mode, | |
6c30d220 L |
504 | /* XMM register or byte memory operand */ |
505 | xmm_mb_mode, | |
506 | /* XMM register or word memory operand */ | |
507 | xmm_mw_mode, | |
508 | /* XMM register or double word memory operand */ | |
509 | xmm_md_mode, | |
510 | /* XMM register or quad word memory operand */ | |
511 | xmm_mq_mode, | |
43234a1e L |
512 | /* XMM register or double/quad word memory operand, depending on |
513 | VEX.W. */ | |
514 | xmm_mdq_mode, | |
515 | /* 16-byte XMM, word, double word or quad word operand. */ | |
6c30d220 | 516 | xmmdw_mode, |
43234a1e | 517 | /* 16-byte XMM, double word, quad word operand or xmm word operand. */ |
6c30d220 | 518 | xmmqd_mode, |
43234a1e L |
519 | /* 32-byte YMM operand */ |
520 | ymm_mode, | |
521 | /* quad word, ymmword or zmmword memory operand. */ | |
3873ba12 | 522 | ymmq_mode, |
6c30d220 L |
523 | /* 32-byte YMM or 16-byte word operand */ |
524 | ymmxmm_mode, | |
51e7da1b | 525 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
3873ba12 | 526 | m_mode, |
51e7da1b | 527 | /* pair of v_mode operands */ |
3873ba12 L |
528 | a_mode, |
529 | cond_jump_mode, | |
530 | loop_jcxz_mode, | |
7e8b059b | 531 | v_bnd_mode, |
51e7da1b | 532 | /* operand size depends on REX prefixes. */ |
3873ba12 | 533 | dq_mode, |
51e7da1b | 534 | /* registers like dq_mode, memory like w_mode. */ |
3873ba12 | 535 | dqw_mode, |
7e8b059b | 536 | bnd_mode, |
51e7da1b | 537 | /* 4- or 6-byte pointer operand */ |
3873ba12 L |
538 | f_mode, |
539 | const_1_mode, | |
51e7da1b | 540 | /* v_mode for stack-related opcodes. */ |
3873ba12 | 541 | stack_v_mode, |
51e7da1b | 542 | /* non-quad operand size depends on prefixes */ |
3873ba12 | 543 | z_mode, |
51e7da1b | 544 | /* 16-byte operand */ |
3873ba12 | 545 | o_mode, |
51e7da1b | 546 | /* registers like dq_mode, memory like b_mode. */ |
3873ba12 | 547 | dqb_mode, |
51e7da1b | 548 | /* registers like dq_mode, memory like d_mode. */ |
3873ba12 | 549 | dqd_mode, |
51e7da1b | 550 | /* normal vex mode */ |
3873ba12 | 551 | vex_mode, |
51e7da1b | 552 | /* 128bit vex mode */ |
3873ba12 | 553 | vex128_mode, |
51e7da1b | 554 | /* 256bit vex mode */ |
3873ba12 | 555 | vex256_mode, |
51e7da1b | 556 | /* operand size depends on the VEX.W bit. */ |
3873ba12 | 557 | vex_w_dq_mode, |
d55ee72f | 558 | |
6c30d220 L |
559 | /* Similar to vex_w_dq_mode, with VSIB dword indices. */ |
560 | vex_vsib_d_w_dq_mode, | |
5fc35d96 IT |
561 | /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ |
562 | vex_vsib_d_w_d_mode, | |
6c30d220 L |
563 | /* Similar to vex_w_dq_mode, with VSIB qword indices. */ |
564 | vex_vsib_q_w_dq_mode, | |
5fc35d96 IT |
565 | /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ |
566 | vex_vsib_q_w_d_mode, | |
6c30d220 | 567 | |
539f890d L |
568 | /* scalar, ignore vector length. */ |
569 | scalar_mode, | |
570 | /* like d_mode, ignore vector length. */ | |
571 | d_scalar_mode, | |
572 | /* like d_swap_mode, ignore vector length. */ | |
573 | d_scalar_swap_mode, | |
574 | /* like q_mode, ignore vector length. */ | |
575 | q_scalar_mode, | |
576 | /* like q_swap_mode, ignore vector length. */ | |
577 | q_scalar_swap_mode, | |
578 | /* like vex_mode, ignore vector length. */ | |
579 | vex_scalar_mode, | |
1c480963 L |
580 | /* like vex_w_dq_mode, ignore vector length. */ |
581 | vex_scalar_w_dq_mode, | |
539f890d | 582 | |
43234a1e L |
583 | /* Static rounding. */ |
584 | evex_rounding_mode, | |
585 | /* Supress all exceptions. */ | |
586 | evex_sae_mode, | |
587 | ||
588 | /* Mask register operand. */ | |
589 | mask_mode, | |
590 | ||
3873ba12 L |
591 | es_reg, |
592 | cs_reg, | |
593 | ss_reg, | |
594 | ds_reg, | |
595 | fs_reg, | |
596 | gs_reg, | |
d55ee72f | 597 | |
3873ba12 L |
598 | eAX_reg, |
599 | eCX_reg, | |
600 | eDX_reg, | |
601 | eBX_reg, | |
602 | eSP_reg, | |
603 | eBP_reg, | |
604 | eSI_reg, | |
605 | eDI_reg, | |
d55ee72f | 606 | |
3873ba12 L |
607 | al_reg, |
608 | cl_reg, | |
609 | dl_reg, | |
610 | bl_reg, | |
611 | ah_reg, | |
612 | ch_reg, | |
613 | dh_reg, | |
614 | bh_reg, | |
d55ee72f | 615 | |
3873ba12 L |
616 | ax_reg, |
617 | cx_reg, | |
618 | dx_reg, | |
619 | bx_reg, | |
620 | sp_reg, | |
621 | bp_reg, | |
622 | si_reg, | |
623 | di_reg, | |
d55ee72f | 624 | |
3873ba12 L |
625 | rAX_reg, |
626 | rCX_reg, | |
627 | rDX_reg, | |
628 | rBX_reg, | |
629 | rSP_reg, | |
630 | rBP_reg, | |
631 | rSI_reg, | |
632 | rDI_reg, | |
d55ee72f | 633 | |
3873ba12 L |
634 | z_mode_ax_reg, |
635 | indir_dx_reg | |
51e7da1b | 636 | }; |
252b5132 | 637 | |
51e7da1b L |
638 | enum |
639 | { | |
640 | FLOATCODE = 1, | |
3873ba12 L |
641 | USE_REG_TABLE, |
642 | USE_MOD_TABLE, | |
643 | USE_RM_TABLE, | |
644 | USE_PREFIX_TABLE, | |
645 | USE_X86_64_TABLE, | |
646 | USE_3BYTE_TABLE, | |
f88c9eb0 | 647 | USE_XOP_8F_TABLE, |
3873ba12 L |
648 | USE_VEX_C4_TABLE, |
649 | USE_VEX_C5_TABLE, | |
9e30b8e0 | 650 | USE_VEX_LEN_TABLE, |
43234a1e L |
651 | USE_VEX_W_TABLE, |
652 | USE_EVEX_TABLE | |
51e7da1b | 653 | }; |
6439fc28 | 654 | |
1ceb70f8 | 655 | #define FLOAT NULL, { { NULL, FLOATCODE } } |
4efba78c | 656 | |
4e7d34a6 | 657 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } } |
1ceb70f8 L |
658 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
659 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
660 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
661 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
662 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
663 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
f88c9eb0 | 664 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
c0f3af97 L |
665 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
666 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) | |
667 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) | |
9e30b8e0 | 668 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
43234a1e | 669 | #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) |
1ceb70f8 | 670 | |
51e7da1b L |
671 | enum |
672 | { | |
673 | REG_80 = 0, | |
3873ba12 L |
674 | REG_81, |
675 | REG_82, | |
676 | REG_8F, | |
677 | REG_C0, | |
678 | REG_C1, | |
679 | REG_C6, | |
680 | REG_C7, | |
681 | REG_D0, | |
682 | REG_D1, | |
683 | REG_D2, | |
684 | REG_D3, | |
685 | REG_F6, | |
686 | REG_F7, | |
687 | REG_FE, | |
688 | REG_FF, | |
689 | REG_0F00, | |
690 | REG_0F01, | |
691 | REG_0F0D, | |
692 | REG_0F18, | |
693 | REG_0F71, | |
694 | REG_0F72, | |
695 | REG_0F73, | |
696 | REG_0FA6, | |
697 | REG_0FA7, | |
698 | REG_0FAE, | |
699 | REG_0FBA, | |
700 | REG_0FC7, | |
592a252b L |
701 | REG_VEX_0F71, |
702 | REG_VEX_0F72, | |
703 | REG_VEX_0F73, | |
704 | REG_VEX_0FAE, | |
f12dc422 | 705 | REG_VEX_0F38F3, |
f88c9eb0 | 706 | REG_XOP_LWPCB, |
2a2a0f38 QN |
707 | REG_XOP_LWP, |
708 | REG_XOP_TBM_01, | |
43234a1e L |
709 | REG_XOP_TBM_02, |
710 | ||
711 | REG_EVEX_0F72, | |
712 | REG_EVEX_0F73, | |
713 | REG_EVEX_0F38C6, | |
714 | REG_EVEX_0F38C7 | |
51e7da1b | 715 | }; |
1ceb70f8 | 716 | |
51e7da1b L |
717 | enum |
718 | { | |
719 | MOD_8D = 0, | |
42164a71 L |
720 | MOD_C6_REG_7, |
721 | MOD_C7_REG_7, | |
4a357820 MZ |
722 | MOD_FF_REG_3, |
723 | MOD_FF_REG_5, | |
3873ba12 L |
724 | MOD_0F01_REG_0, |
725 | MOD_0F01_REG_1, | |
726 | MOD_0F01_REG_2, | |
727 | MOD_0F01_REG_3, | |
728 | MOD_0F01_REG_7, | |
729 | MOD_0F12_PREFIX_0, | |
730 | MOD_0F13, | |
731 | MOD_0F16_PREFIX_0, | |
732 | MOD_0F17, | |
733 | MOD_0F18_REG_0, | |
734 | MOD_0F18_REG_1, | |
735 | MOD_0F18_REG_2, | |
736 | MOD_0F18_REG_3, | |
d7189fa5 RM |
737 | MOD_0F18_REG_4, |
738 | MOD_0F18_REG_5, | |
739 | MOD_0F18_REG_6, | |
740 | MOD_0F18_REG_7, | |
7e8b059b L |
741 | MOD_0F1A_PREFIX_0, |
742 | MOD_0F1B_PREFIX_0, | |
743 | MOD_0F1B_PREFIX_1, | |
3873ba12 L |
744 | MOD_0F20, |
745 | MOD_0F21, | |
746 | MOD_0F22, | |
747 | MOD_0F23, | |
748 | MOD_0F24, | |
749 | MOD_0F26, | |
750 | MOD_0F2B_PREFIX_0, | |
751 | MOD_0F2B_PREFIX_1, | |
752 | MOD_0F2B_PREFIX_2, | |
753 | MOD_0F2B_PREFIX_3, | |
754 | MOD_0F51, | |
755 | MOD_0F71_REG_2, | |
756 | MOD_0F71_REG_4, | |
757 | MOD_0F71_REG_6, | |
758 | MOD_0F72_REG_2, | |
759 | MOD_0F72_REG_4, | |
760 | MOD_0F72_REG_6, | |
761 | MOD_0F73_REG_2, | |
762 | MOD_0F73_REG_3, | |
763 | MOD_0F73_REG_6, | |
764 | MOD_0F73_REG_7, | |
765 | MOD_0FAE_REG_0, | |
766 | MOD_0FAE_REG_1, | |
767 | MOD_0FAE_REG_2, | |
768 | MOD_0FAE_REG_3, | |
769 | MOD_0FAE_REG_4, | |
770 | MOD_0FAE_REG_5, | |
771 | MOD_0FAE_REG_6, | |
772 | MOD_0FAE_REG_7, | |
773 | MOD_0FB2, | |
774 | MOD_0FB4, | |
775 | MOD_0FB5, | |
963f3586 IT |
776 | MOD_0FC7_REG_3, |
777 | MOD_0FC7_REG_4, | |
778 | MOD_0FC7_REG_5, | |
3873ba12 L |
779 | MOD_0FC7_REG_6, |
780 | MOD_0FC7_REG_7, | |
781 | MOD_0FD7, | |
782 | MOD_0FE7_PREFIX_2, | |
783 | MOD_0FF0_PREFIX_3, | |
784 | MOD_0F382A_PREFIX_2, | |
785 | MOD_62_32BIT, | |
786 | MOD_C4_32BIT, | |
787 | MOD_C5_32BIT, | |
592a252b L |
788 | MOD_VEX_0F12_PREFIX_0, |
789 | MOD_VEX_0F13, | |
790 | MOD_VEX_0F16_PREFIX_0, | |
791 | MOD_VEX_0F17, | |
792 | MOD_VEX_0F2B, | |
793 | MOD_VEX_0F50, | |
794 | MOD_VEX_0F71_REG_2, | |
795 | MOD_VEX_0F71_REG_4, | |
796 | MOD_VEX_0F71_REG_6, | |
797 | MOD_VEX_0F72_REG_2, | |
798 | MOD_VEX_0F72_REG_4, | |
799 | MOD_VEX_0F72_REG_6, | |
800 | MOD_VEX_0F73_REG_2, | |
801 | MOD_VEX_0F73_REG_3, | |
802 | MOD_VEX_0F73_REG_6, | |
803 | MOD_VEX_0F73_REG_7, | |
804 | MOD_VEX_0FAE_REG_2, | |
805 | MOD_VEX_0FAE_REG_3, | |
806 | MOD_VEX_0FD7_PREFIX_2, | |
807 | MOD_VEX_0FE7_PREFIX_2, | |
808 | MOD_VEX_0FF0_PREFIX_3, | |
592a252b L |
809 | MOD_VEX_0F381A_PREFIX_2, |
810 | MOD_VEX_0F382A_PREFIX_2, | |
811 | MOD_VEX_0F382C_PREFIX_2, | |
812 | MOD_VEX_0F382D_PREFIX_2, | |
813 | MOD_VEX_0F382E_PREFIX_2, | |
6c30d220 L |
814 | MOD_VEX_0F382F_PREFIX_2, |
815 | MOD_VEX_0F385A_PREFIX_2, | |
816 | MOD_VEX_0F388C_PREFIX_2, | |
817 | MOD_VEX_0F388E_PREFIX_2, | |
43234a1e L |
818 | |
819 | MOD_EVEX_0F10_PREFIX_1, | |
820 | MOD_EVEX_0F10_PREFIX_3, | |
821 | MOD_EVEX_0F11_PREFIX_1, | |
822 | MOD_EVEX_0F11_PREFIX_3, | |
823 | MOD_EVEX_0F12_PREFIX_0, | |
824 | MOD_EVEX_0F16_PREFIX_0, | |
825 | MOD_EVEX_0F38C6_REG_1, | |
826 | MOD_EVEX_0F38C6_REG_2, | |
827 | MOD_EVEX_0F38C6_REG_5, | |
828 | MOD_EVEX_0F38C6_REG_6, | |
829 | MOD_EVEX_0F38C7_REG_1, | |
830 | MOD_EVEX_0F38C7_REG_2, | |
831 | MOD_EVEX_0F38C7_REG_5, | |
832 | MOD_EVEX_0F38C7_REG_6 | |
51e7da1b | 833 | }; |
1ceb70f8 | 834 | |
51e7da1b L |
835 | enum |
836 | { | |
42164a71 L |
837 | RM_C6_REG_7 = 0, |
838 | RM_C7_REG_7, | |
839 | RM_0F01_REG_0, | |
3873ba12 L |
840 | RM_0F01_REG_1, |
841 | RM_0F01_REG_2, | |
842 | RM_0F01_REG_3, | |
843 | RM_0F01_REG_7, | |
844 | RM_0FAE_REG_5, | |
845 | RM_0FAE_REG_6, | |
846 | RM_0FAE_REG_7 | |
51e7da1b | 847 | }; |
1ceb70f8 | 848 | |
51e7da1b L |
849 | enum |
850 | { | |
851 | PREFIX_90 = 0, | |
3873ba12 L |
852 | PREFIX_0F10, |
853 | PREFIX_0F11, | |
854 | PREFIX_0F12, | |
855 | PREFIX_0F16, | |
7e8b059b L |
856 | PREFIX_0F1A, |
857 | PREFIX_0F1B, | |
3873ba12 L |
858 | PREFIX_0F2A, |
859 | PREFIX_0F2B, | |
860 | PREFIX_0F2C, | |
861 | PREFIX_0F2D, | |
862 | PREFIX_0F2E, | |
863 | PREFIX_0F2F, | |
864 | PREFIX_0F51, | |
865 | PREFIX_0F52, | |
866 | PREFIX_0F53, | |
867 | PREFIX_0F58, | |
868 | PREFIX_0F59, | |
869 | PREFIX_0F5A, | |
870 | PREFIX_0F5B, | |
871 | PREFIX_0F5C, | |
872 | PREFIX_0F5D, | |
873 | PREFIX_0F5E, | |
874 | PREFIX_0F5F, | |
875 | PREFIX_0F60, | |
876 | PREFIX_0F61, | |
877 | PREFIX_0F62, | |
878 | PREFIX_0F6C, | |
879 | PREFIX_0F6D, | |
880 | PREFIX_0F6F, | |
881 | PREFIX_0F70, | |
882 | PREFIX_0F73_REG_3, | |
883 | PREFIX_0F73_REG_7, | |
884 | PREFIX_0F78, | |
885 | PREFIX_0F79, | |
886 | PREFIX_0F7C, | |
887 | PREFIX_0F7D, | |
888 | PREFIX_0F7E, | |
889 | PREFIX_0F7F, | |
c7b8aa3a L |
890 | PREFIX_0FAE_REG_0, |
891 | PREFIX_0FAE_REG_1, | |
892 | PREFIX_0FAE_REG_2, | |
893 | PREFIX_0FAE_REG_3, | |
963f3586 | 894 | PREFIX_0FAE_REG_7, |
3873ba12 | 895 | PREFIX_0FB8, |
f12dc422 | 896 | PREFIX_0FBC, |
3873ba12 L |
897 | PREFIX_0FBD, |
898 | PREFIX_0FC2, | |
899 | PREFIX_0FC3, | |
900 | PREFIX_0FC7_REG_6, | |
901 | PREFIX_0FD0, | |
902 | PREFIX_0FD6, | |
903 | PREFIX_0FE6, | |
904 | PREFIX_0FE7, | |
905 | PREFIX_0FF0, | |
906 | PREFIX_0FF7, | |
907 | PREFIX_0F3810, | |
908 | PREFIX_0F3814, | |
909 | PREFIX_0F3815, | |
910 | PREFIX_0F3817, | |
911 | PREFIX_0F3820, | |
912 | PREFIX_0F3821, | |
913 | PREFIX_0F3822, | |
914 | PREFIX_0F3823, | |
915 | PREFIX_0F3824, | |
916 | PREFIX_0F3825, | |
917 | PREFIX_0F3828, | |
918 | PREFIX_0F3829, | |
919 | PREFIX_0F382A, | |
920 | PREFIX_0F382B, | |
921 | PREFIX_0F3830, | |
922 | PREFIX_0F3831, | |
923 | PREFIX_0F3832, | |
924 | PREFIX_0F3833, | |
925 | PREFIX_0F3834, | |
926 | PREFIX_0F3835, | |
927 | PREFIX_0F3837, | |
928 | PREFIX_0F3838, | |
929 | PREFIX_0F3839, | |
930 | PREFIX_0F383A, | |
931 | PREFIX_0F383B, | |
932 | PREFIX_0F383C, | |
933 | PREFIX_0F383D, | |
934 | PREFIX_0F383E, | |
935 | PREFIX_0F383F, | |
936 | PREFIX_0F3840, | |
937 | PREFIX_0F3841, | |
938 | PREFIX_0F3880, | |
939 | PREFIX_0F3881, | |
6c30d220 | 940 | PREFIX_0F3882, |
a0046408 L |
941 | PREFIX_0F38C8, |
942 | PREFIX_0F38C9, | |
943 | PREFIX_0F38CA, | |
944 | PREFIX_0F38CB, | |
945 | PREFIX_0F38CC, | |
946 | PREFIX_0F38CD, | |
3873ba12 L |
947 | PREFIX_0F38DB, |
948 | PREFIX_0F38DC, | |
949 | PREFIX_0F38DD, | |
950 | PREFIX_0F38DE, | |
951 | PREFIX_0F38DF, | |
952 | PREFIX_0F38F0, | |
953 | PREFIX_0F38F1, | |
e2e1fcde | 954 | PREFIX_0F38F6, |
3873ba12 L |
955 | PREFIX_0F3A08, |
956 | PREFIX_0F3A09, | |
957 | PREFIX_0F3A0A, | |
958 | PREFIX_0F3A0B, | |
959 | PREFIX_0F3A0C, | |
960 | PREFIX_0F3A0D, | |
961 | PREFIX_0F3A0E, | |
962 | PREFIX_0F3A14, | |
963 | PREFIX_0F3A15, | |
964 | PREFIX_0F3A16, | |
965 | PREFIX_0F3A17, | |
966 | PREFIX_0F3A20, | |
967 | PREFIX_0F3A21, | |
968 | PREFIX_0F3A22, | |
969 | PREFIX_0F3A40, | |
970 | PREFIX_0F3A41, | |
971 | PREFIX_0F3A42, | |
972 | PREFIX_0F3A44, | |
973 | PREFIX_0F3A60, | |
974 | PREFIX_0F3A61, | |
975 | PREFIX_0F3A62, | |
976 | PREFIX_0F3A63, | |
a0046408 | 977 | PREFIX_0F3ACC, |
3873ba12 | 978 | PREFIX_0F3ADF, |
592a252b L |
979 | PREFIX_VEX_0F10, |
980 | PREFIX_VEX_0F11, | |
981 | PREFIX_VEX_0F12, | |
982 | PREFIX_VEX_0F16, | |
983 | PREFIX_VEX_0F2A, | |
984 | PREFIX_VEX_0F2C, | |
985 | PREFIX_VEX_0F2D, | |
986 | PREFIX_VEX_0F2E, | |
987 | PREFIX_VEX_0F2F, | |
43234a1e L |
988 | PREFIX_VEX_0F41, |
989 | PREFIX_VEX_0F42, | |
990 | PREFIX_VEX_0F44, | |
991 | PREFIX_VEX_0F45, | |
992 | PREFIX_VEX_0F46, | |
993 | PREFIX_VEX_0F47, | |
994 | PREFIX_VEX_0F4B, | |
592a252b L |
995 | PREFIX_VEX_0F51, |
996 | PREFIX_VEX_0F52, | |
997 | PREFIX_VEX_0F53, | |
998 | PREFIX_VEX_0F58, | |
999 | PREFIX_VEX_0F59, | |
1000 | PREFIX_VEX_0F5A, | |
1001 | PREFIX_VEX_0F5B, | |
1002 | PREFIX_VEX_0F5C, | |
1003 | PREFIX_VEX_0F5D, | |
1004 | PREFIX_VEX_0F5E, | |
1005 | PREFIX_VEX_0F5F, | |
1006 | PREFIX_VEX_0F60, | |
1007 | PREFIX_VEX_0F61, | |
1008 | PREFIX_VEX_0F62, | |
1009 | PREFIX_VEX_0F63, | |
1010 | PREFIX_VEX_0F64, | |
1011 | PREFIX_VEX_0F65, | |
1012 | PREFIX_VEX_0F66, | |
1013 | PREFIX_VEX_0F67, | |
1014 | PREFIX_VEX_0F68, | |
1015 | PREFIX_VEX_0F69, | |
1016 | PREFIX_VEX_0F6A, | |
1017 | PREFIX_VEX_0F6B, | |
1018 | PREFIX_VEX_0F6C, | |
1019 | PREFIX_VEX_0F6D, | |
1020 | PREFIX_VEX_0F6E, | |
1021 | PREFIX_VEX_0F6F, | |
1022 | PREFIX_VEX_0F70, | |
1023 | PREFIX_VEX_0F71_REG_2, | |
1024 | PREFIX_VEX_0F71_REG_4, | |
1025 | PREFIX_VEX_0F71_REG_6, | |
1026 | PREFIX_VEX_0F72_REG_2, | |
1027 | PREFIX_VEX_0F72_REG_4, | |
1028 | PREFIX_VEX_0F72_REG_6, | |
1029 | PREFIX_VEX_0F73_REG_2, | |
1030 | PREFIX_VEX_0F73_REG_3, | |
1031 | PREFIX_VEX_0F73_REG_6, | |
1032 | PREFIX_VEX_0F73_REG_7, | |
1033 | PREFIX_VEX_0F74, | |
1034 | PREFIX_VEX_0F75, | |
1035 | PREFIX_VEX_0F76, | |
1036 | PREFIX_VEX_0F77, | |
1037 | PREFIX_VEX_0F7C, | |
1038 | PREFIX_VEX_0F7D, | |
1039 | PREFIX_VEX_0F7E, | |
1040 | PREFIX_VEX_0F7F, | |
43234a1e L |
1041 | PREFIX_VEX_0F90, |
1042 | PREFIX_VEX_0F91, | |
1043 | PREFIX_VEX_0F92, | |
1044 | PREFIX_VEX_0F93, | |
1045 | PREFIX_VEX_0F98, | |
592a252b L |
1046 | PREFIX_VEX_0FC2, |
1047 | PREFIX_VEX_0FC4, | |
1048 | PREFIX_VEX_0FC5, | |
1049 | PREFIX_VEX_0FD0, | |
1050 | PREFIX_VEX_0FD1, | |
1051 | PREFIX_VEX_0FD2, | |
1052 | PREFIX_VEX_0FD3, | |
1053 | PREFIX_VEX_0FD4, | |
1054 | PREFIX_VEX_0FD5, | |
1055 | PREFIX_VEX_0FD6, | |
1056 | PREFIX_VEX_0FD7, | |
1057 | PREFIX_VEX_0FD8, | |
1058 | PREFIX_VEX_0FD9, | |
1059 | PREFIX_VEX_0FDA, | |
1060 | PREFIX_VEX_0FDB, | |
1061 | PREFIX_VEX_0FDC, | |
1062 | PREFIX_VEX_0FDD, | |
1063 | PREFIX_VEX_0FDE, | |
1064 | PREFIX_VEX_0FDF, | |
1065 | PREFIX_VEX_0FE0, | |
1066 | PREFIX_VEX_0FE1, | |
1067 | PREFIX_VEX_0FE2, | |
1068 | PREFIX_VEX_0FE3, | |
1069 | PREFIX_VEX_0FE4, | |
1070 | PREFIX_VEX_0FE5, | |
1071 | PREFIX_VEX_0FE6, | |
1072 | PREFIX_VEX_0FE7, | |
1073 | PREFIX_VEX_0FE8, | |
1074 | PREFIX_VEX_0FE9, | |
1075 | PREFIX_VEX_0FEA, | |
1076 | PREFIX_VEX_0FEB, | |
1077 | PREFIX_VEX_0FEC, | |
1078 | PREFIX_VEX_0FED, | |
1079 | PREFIX_VEX_0FEE, | |
1080 | PREFIX_VEX_0FEF, | |
1081 | PREFIX_VEX_0FF0, | |
1082 | PREFIX_VEX_0FF1, | |
1083 | PREFIX_VEX_0FF2, | |
1084 | PREFIX_VEX_0FF3, | |
1085 | PREFIX_VEX_0FF4, | |
1086 | PREFIX_VEX_0FF5, | |
1087 | PREFIX_VEX_0FF6, | |
1088 | PREFIX_VEX_0FF7, | |
1089 | PREFIX_VEX_0FF8, | |
1090 | PREFIX_VEX_0FF9, | |
1091 | PREFIX_VEX_0FFA, | |
1092 | PREFIX_VEX_0FFB, | |
1093 | PREFIX_VEX_0FFC, | |
1094 | PREFIX_VEX_0FFD, | |
1095 | PREFIX_VEX_0FFE, | |
1096 | PREFIX_VEX_0F3800, | |
1097 | PREFIX_VEX_0F3801, | |
1098 | PREFIX_VEX_0F3802, | |
1099 | PREFIX_VEX_0F3803, | |
1100 | PREFIX_VEX_0F3804, | |
1101 | PREFIX_VEX_0F3805, | |
1102 | PREFIX_VEX_0F3806, | |
1103 | PREFIX_VEX_0F3807, | |
1104 | PREFIX_VEX_0F3808, | |
1105 | PREFIX_VEX_0F3809, | |
1106 | PREFIX_VEX_0F380A, | |
1107 | PREFIX_VEX_0F380B, | |
1108 | PREFIX_VEX_0F380C, | |
1109 | PREFIX_VEX_0F380D, | |
1110 | PREFIX_VEX_0F380E, | |
1111 | PREFIX_VEX_0F380F, | |
1112 | PREFIX_VEX_0F3813, | |
6c30d220 | 1113 | PREFIX_VEX_0F3816, |
592a252b L |
1114 | PREFIX_VEX_0F3817, |
1115 | PREFIX_VEX_0F3818, | |
1116 | PREFIX_VEX_0F3819, | |
1117 | PREFIX_VEX_0F381A, | |
1118 | PREFIX_VEX_0F381C, | |
1119 | PREFIX_VEX_0F381D, | |
1120 | PREFIX_VEX_0F381E, | |
1121 | PREFIX_VEX_0F3820, | |
1122 | PREFIX_VEX_0F3821, | |
1123 | PREFIX_VEX_0F3822, | |
1124 | PREFIX_VEX_0F3823, | |
1125 | PREFIX_VEX_0F3824, | |
1126 | PREFIX_VEX_0F3825, | |
1127 | PREFIX_VEX_0F3828, | |
1128 | PREFIX_VEX_0F3829, | |
1129 | PREFIX_VEX_0F382A, | |
1130 | PREFIX_VEX_0F382B, | |
1131 | PREFIX_VEX_0F382C, | |
1132 | PREFIX_VEX_0F382D, | |
1133 | PREFIX_VEX_0F382E, | |
1134 | PREFIX_VEX_0F382F, | |
1135 | PREFIX_VEX_0F3830, | |
1136 | PREFIX_VEX_0F3831, | |
1137 | PREFIX_VEX_0F3832, | |
1138 | PREFIX_VEX_0F3833, | |
1139 | PREFIX_VEX_0F3834, | |
1140 | PREFIX_VEX_0F3835, | |
6c30d220 | 1141 | PREFIX_VEX_0F3836, |
592a252b L |
1142 | PREFIX_VEX_0F3837, |
1143 | PREFIX_VEX_0F3838, | |
1144 | PREFIX_VEX_0F3839, | |
1145 | PREFIX_VEX_0F383A, | |
1146 | PREFIX_VEX_0F383B, | |
1147 | PREFIX_VEX_0F383C, | |
1148 | PREFIX_VEX_0F383D, | |
1149 | PREFIX_VEX_0F383E, | |
1150 | PREFIX_VEX_0F383F, | |
1151 | PREFIX_VEX_0F3840, | |
1152 | PREFIX_VEX_0F3841, | |
6c30d220 L |
1153 | PREFIX_VEX_0F3845, |
1154 | PREFIX_VEX_0F3846, | |
1155 | PREFIX_VEX_0F3847, | |
1156 | PREFIX_VEX_0F3858, | |
1157 | PREFIX_VEX_0F3859, | |
1158 | PREFIX_VEX_0F385A, | |
1159 | PREFIX_VEX_0F3878, | |
1160 | PREFIX_VEX_0F3879, | |
1161 | PREFIX_VEX_0F388C, | |
1162 | PREFIX_VEX_0F388E, | |
1163 | PREFIX_VEX_0F3890, | |
1164 | PREFIX_VEX_0F3891, | |
1165 | PREFIX_VEX_0F3892, | |
1166 | PREFIX_VEX_0F3893, | |
592a252b L |
1167 | PREFIX_VEX_0F3896, |
1168 | PREFIX_VEX_0F3897, | |
1169 | PREFIX_VEX_0F3898, | |
1170 | PREFIX_VEX_0F3899, | |
1171 | PREFIX_VEX_0F389A, | |
1172 | PREFIX_VEX_0F389B, | |
1173 | PREFIX_VEX_0F389C, | |
1174 | PREFIX_VEX_0F389D, | |
1175 | PREFIX_VEX_0F389E, | |
1176 | PREFIX_VEX_0F389F, | |
1177 | PREFIX_VEX_0F38A6, | |
1178 | PREFIX_VEX_0F38A7, | |
1179 | PREFIX_VEX_0F38A8, | |
1180 | PREFIX_VEX_0F38A9, | |
1181 | PREFIX_VEX_0F38AA, | |
1182 | PREFIX_VEX_0F38AB, | |
1183 | PREFIX_VEX_0F38AC, | |
1184 | PREFIX_VEX_0F38AD, | |
1185 | PREFIX_VEX_0F38AE, | |
1186 | PREFIX_VEX_0F38AF, | |
1187 | PREFIX_VEX_0F38B6, | |
1188 | PREFIX_VEX_0F38B7, | |
1189 | PREFIX_VEX_0F38B8, | |
1190 | PREFIX_VEX_0F38B9, | |
1191 | PREFIX_VEX_0F38BA, | |
1192 | PREFIX_VEX_0F38BB, | |
1193 | PREFIX_VEX_0F38BC, | |
1194 | PREFIX_VEX_0F38BD, | |
1195 | PREFIX_VEX_0F38BE, | |
1196 | PREFIX_VEX_0F38BF, | |
1197 | PREFIX_VEX_0F38DB, | |
1198 | PREFIX_VEX_0F38DC, | |
1199 | PREFIX_VEX_0F38DD, | |
1200 | PREFIX_VEX_0F38DE, | |
1201 | PREFIX_VEX_0F38DF, | |
f12dc422 L |
1202 | PREFIX_VEX_0F38F2, |
1203 | PREFIX_VEX_0F38F3_REG_1, | |
1204 | PREFIX_VEX_0F38F3_REG_2, | |
1205 | PREFIX_VEX_0F38F3_REG_3, | |
6c30d220 L |
1206 | PREFIX_VEX_0F38F5, |
1207 | PREFIX_VEX_0F38F6, | |
f12dc422 | 1208 | PREFIX_VEX_0F38F7, |
6c30d220 L |
1209 | PREFIX_VEX_0F3A00, |
1210 | PREFIX_VEX_0F3A01, | |
1211 | PREFIX_VEX_0F3A02, | |
592a252b L |
1212 | PREFIX_VEX_0F3A04, |
1213 | PREFIX_VEX_0F3A05, | |
1214 | PREFIX_VEX_0F3A06, | |
1215 | PREFIX_VEX_0F3A08, | |
1216 | PREFIX_VEX_0F3A09, | |
1217 | PREFIX_VEX_0F3A0A, | |
1218 | PREFIX_VEX_0F3A0B, | |
1219 | PREFIX_VEX_0F3A0C, | |
1220 | PREFIX_VEX_0F3A0D, | |
1221 | PREFIX_VEX_0F3A0E, | |
1222 | PREFIX_VEX_0F3A0F, | |
1223 | PREFIX_VEX_0F3A14, | |
1224 | PREFIX_VEX_0F3A15, | |
1225 | PREFIX_VEX_0F3A16, | |
1226 | PREFIX_VEX_0F3A17, | |
1227 | PREFIX_VEX_0F3A18, | |
1228 | PREFIX_VEX_0F3A19, | |
1229 | PREFIX_VEX_0F3A1D, | |
1230 | PREFIX_VEX_0F3A20, | |
1231 | PREFIX_VEX_0F3A21, | |
1232 | PREFIX_VEX_0F3A22, | |
43234a1e L |
1233 | PREFIX_VEX_0F3A30, |
1234 | PREFIX_VEX_0F3A32, | |
6c30d220 L |
1235 | PREFIX_VEX_0F3A38, |
1236 | PREFIX_VEX_0F3A39, | |
592a252b L |
1237 | PREFIX_VEX_0F3A40, |
1238 | PREFIX_VEX_0F3A41, | |
1239 | PREFIX_VEX_0F3A42, | |
1240 | PREFIX_VEX_0F3A44, | |
6c30d220 | 1241 | PREFIX_VEX_0F3A46, |
592a252b L |
1242 | PREFIX_VEX_0F3A48, |
1243 | PREFIX_VEX_0F3A49, | |
1244 | PREFIX_VEX_0F3A4A, | |
1245 | PREFIX_VEX_0F3A4B, | |
1246 | PREFIX_VEX_0F3A4C, | |
1247 | PREFIX_VEX_0F3A5C, | |
1248 | PREFIX_VEX_0F3A5D, | |
1249 | PREFIX_VEX_0F3A5E, | |
1250 | PREFIX_VEX_0F3A5F, | |
1251 | PREFIX_VEX_0F3A60, | |
1252 | PREFIX_VEX_0F3A61, | |
1253 | PREFIX_VEX_0F3A62, | |
1254 | PREFIX_VEX_0F3A63, | |
1255 | PREFIX_VEX_0F3A68, | |
1256 | PREFIX_VEX_0F3A69, | |
1257 | PREFIX_VEX_0F3A6A, | |
1258 | PREFIX_VEX_0F3A6B, | |
1259 | PREFIX_VEX_0F3A6C, | |
1260 | PREFIX_VEX_0F3A6D, | |
1261 | PREFIX_VEX_0F3A6E, | |
1262 | PREFIX_VEX_0F3A6F, | |
1263 | PREFIX_VEX_0F3A78, | |
1264 | PREFIX_VEX_0F3A79, | |
1265 | PREFIX_VEX_0F3A7A, | |
1266 | PREFIX_VEX_0F3A7B, | |
1267 | PREFIX_VEX_0F3A7C, | |
1268 | PREFIX_VEX_0F3A7D, | |
1269 | PREFIX_VEX_0F3A7E, | |
1270 | PREFIX_VEX_0F3A7F, | |
6c30d220 | 1271 | PREFIX_VEX_0F3ADF, |
43234a1e L |
1272 | PREFIX_VEX_0F3AF0, |
1273 | ||
1274 | PREFIX_EVEX_0F10, | |
1275 | PREFIX_EVEX_0F11, | |
1276 | PREFIX_EVEX_0F12, | |
1277 | PREFIX_EVEX_0F13, | |
1278 | PREFIX_EVEX_0F14, | |
1279 | PREFIX_EVEX_0F15, | |
1280 | PREFIX_EVEX_0F16, | |
1281 | PREFIX_EVEX_0F17, | |
1282 | PREFIX_EVEX_0F28, | |
1283 | PREFIX_EVEX_0F29, | |
1284 | PREFIX_EVEX_0F2A, | |
1285 | PREFIX_EVEX_0F2B, | |
1286 | PREFIX_EVEX_0F2C, | |
1287 | PREFIX_EVEX_0F2D, | |
1288 | PREFIX_EVEX_0F2E, | |
1289 | PREFIX_EVEX_0F2F, | |
1290 | PREFIX_EVEX_0F51, | |
1291 | PREFIX_EVEX_0F58, | |
1292 | PREFIX_EVEX_0F59, | |
1293 | PREFIX_EVEX_0F5A, | |
1294 | PREFIX_EVEX_0F5B, | |
1295 | PREFIX_EVEX_0F5C, | |
1296 | PREFIX_EVEX_0F5D, | |
1297 | PREFIX_EVEX_0F5E, | |
1298 | PREFIX_EVEX_0F5F, | |
1299 | PREFIX_EVEX_0F62, | |
1300 | PREFIX_EVEX_0F66, | |
1301 | PREFIX_EVEX_0F6A, | |
1302 | PREFIX_EVEX_0F6C, | |
1303 | PREFIX_EVEX_0F6D, | |
1304 | PREFIX_EVEX_0F6E, | |
1305 | PREFIX_EVEX_0F6F, | |
1306 | PREFIX_EVEX_0F70, | |
1307 | PREFIX_EVEX_0F72_REG_0, | |
1308 | PREFIX_EVEX_0F72_REG_1, | |
1309 | PREFIX_EVEX_0F72_REG_2, | |
1310 | PREFIX_EVEX_0F72_REG_4, | |
1311 | PREFIX_EVEX_0F72_REG_6, | |
1312 | PREFIX_EVEX_0F73_REG_2, | |
1313 | PREFIX_EVEX_0F73_REG_6, | |
1314 | PREFIX_EVEX_0F76, | |
1315 | PREFIX_EVEX_0F78, | |
1316 | PREFIX_EVEX_0F79, | |
1317 | PREFIX_EVEX_0F7A, | |
1318 | PREFIX_EVEX_0F7B, | |
1319 | PREFIX_EVEX_0F7E, | |
1320 | PREFIX_EVEX_0F7F, | |
1321 | PREFIX_EVEX_0FC2, | |
1322 | PREFIX_EVEX_0FC6, | |
1323 | PREFIX_EVEX_0FD2, | |
1324 | PREFIX_EVEX_0FD3, | |
1325 | PREFIX_EVEX_0FD4, | |
1326 | PREFIX_EVEX_0FD6, | |
1327 | PREFIX_EVEX_0FDB, | |
1328 | PREFIX_EVEX_0FDF, | |
1329 | PREFIX_EVEX_0FE2, | |
1330 | PREFIX_EVEX_0FE6, | |
1331 | PREFIX_EVEX_0FE7, | |
1332 | PREFIX_EVEX_0FEB, | |
1333 | PREFIX_EVEX_0FEF, | |
1334 | PREFIX_EVEX_0FF2, | |
1335 | PREFIX_EVEX_0FF3, | |
1336 | PREFIX_EVEX_0FF4, | |
1337 | PREFIX_EVEX_0FFA, | |
1338 | PREFIX_EVEX_0FFB, | |
1339 | PREFIX_EVEX_0FFE, | |
1340 | PREFIX_EVEX_0F380C, | |
1341 | PREFIX_EVEX_0F380D, | |
1342 | PREFIX_EVEX_0F3811, | |
1343 | PREFIX_EVEX_0F3812, | |
1344 | PREFIX_EVEX_0F3813, | |
1345 | PREFIX_EVEX_0F3814, | |
1346 | PREFIX_EVEX_0F3815, | |
1347 | PREFIX_EVEX_0F3816, | |
1348 | PREFIX_EVEX_0F3818, | |
1349 | PREFIX_EVEX_0F3819, | |
1350 | PREFIX_EVEX_0F381A, | |
1351 | PREFIX_EVEX_0F381B, | |
1352 | PREFIX_EVEX_0F381E, | |
1353 | PREFIX_EVEX_0F381F, | |
1354 | PREFIX_EVEX_0F3821, | |
1355 | PREFIX_EVEX_0F3822, | |
1356 | PREFIX_EVEX_0F3823, | |
1357 | PREFIX_EVEX_0F3824, | |
1358 | PREFIX_EVEX_0F3825, | |
1359 | PREFIX_EVEX_0F3827, | |
1360 | PREFIX_EVEX_0F3828, | |
1361 | PREFIX_EVEX_0F3829, | |
1362 | PREFIX_EVEX_0F382A, | |
1363 | PREFIX_EVEX_0F382C, | |
1364 | PREFIX_EVEX_0F382D, | |
1365 | PREFIX_EVEX_0F3831, | |
1366 | PREFIX_EVEX_0F3832, | |
1367 | PREFIX_EVEX_0F3833, | |
1368 | PREFIX_EVEX_0F3834, | |
1369 | PREFIX_EVEX_0F3835, | |
1370 | PREFIX_EVEX_0F3836, | |
1371 | PREFIX_EVEX_0F3837, | |
1372 | PREFIX_EVEX_0F3839, | |
1373 | PREFIX_EVEX_0F383A, | |
1374 | PREFIX_EVEX_0F383B, | |
1375 | PREFIX_EVEX_0F383D, | |
1376 | PREFIX_EVEX_0F383F, | |
1377 | PREFIX_EVEX_0F3840, | |
1378 | PREFIX_EVEX_0F3842, | |
1379 | PREFIX_EVEX_0F3843, | |
1380 | PREFIX_EVEX_0F3844, | |
1381 | PREFIX_EVEX_0F3845, | |
1382 | PREFIX_EVEX_0F3846, | |
1383 | PREFIX_EVEX_0F3847, | |
1384 | PREFIX_EVEX_0F384C, | |
1385 | PREFIX_EVEX_0F384D, | |
1386 | PREFIX_EVEX_0F384E, | |
1387 | PREFIX_EVEX_0F384F, | |
1388 | PREFIX_EVEX_0F3858, | |
1389 | PREFIX_EVEX_0F3859, | |
1390 | PREFIX_EVEX_0F385A, | |
1391 | PREFIX_EVEX_0F385B, | |
1392 | PREFIX_EVEX_0F3864, | |
1393 | PREFIX_EVEX_0F3865, | |
1394 | PREFIX_EVEX_0F3876, | |
1395 | PREFIX_EVEX_0F3877, | |
1396 | PREFIX_EVEX_0F387C, | |
1397 | PREFIX_EVEX_0F387E, | |
1398 | PREFIX_EVEX_0F387F, | |
1399 | PREFIX_EVEX_0F3888, | |
1400 | PREFIX_EVEX_0F3889, | |
1401 | PREFIX_EVEX_0F388A, | |
1402 | PREFIX_EVEX_0F388B, | |
1403 | PREFIX_EVEX_0F3890, | |
1404 | PREFIX_EVEX_0F3891, | |
1405 | PREFIX_EVEX_0F3892, | |
1406 | PREFIX_EVEX_0F3893, | |
1407 | PREFIX_EVEX_0F3896, | |
1408 | PREFIX_EVEX_0F3897, | |
1409 | PREFIX_EVEX_0F3898, | |
1410 | PREFIX_EVEX_0F3899, | |
1411 | PREFIX_EVEX_0F389A, | |
1412 | PREFIX_EVEX_0F389B, | |
1413 | PREFIX_EVEX_0F389C, | |
1414 | PREFIX_EVEX_0F389D, | |
1415 | PREFIX_EVEX_0F389E, | |
1416 | PREFIX_EVEX_0F389F, | |
1417 | PREFIX_EVEX_0F38A0, | |
1418 | PREFIX_EVEX_0F38A1, | |
1419 | PREFIX_EVEX_0F38A2, | |
1420 | PREFIX_EVEX_0F38A3, | |
1421 | PREFIX_EVEX_0F38A6, | |
1422 | PREFIX_EVEX_0F38A7, | |
1423 | PREFIX_EVEX_0F38A8, | |
1424 | PREFIX_EVEX_0F38A9, | |
1425 | PREFIX_EVEX_0F38AA, | |
1426 | PREFIX_EVEX_0F38AB, | |
1427 | PREFIX_EVEX_0F38AC, | |
1428 | PREFIX_EVEX_0F38AD, | |
1429 | PREFIX_EVEX_0F38AE, | |
1430 | PREFIX_EVEX_0F38AF, | |
1431 | PREFIX_EVEX_0F38B6, | |
1432 | PREFIX_EVEX_0F38B7, | |
1433 | PREFIX_EVEX_0F38B8, | |
1434 | PREFIX_EVEX_0F38B9, | |
1435 | PREFIX_EVEX_0F38BA, | |
1436 | PREFIX_EVEX_0F38BB, | |
1437 | PREFIX_EVEX_0F38BC, | |
1438 | PREFIX_EVEX_0F38BD, | |
1439 | PREFIX_EVEX_0F38BE, | |
1440 | PREFIX_EVEX_0F38BF, | |
1441 | PREFIX_EVEX_0F38C4, | |
1442 | PREFIX_EVEX_0F38C6_REG_1, | |
1443 | PREFIX_EVEX_0F38C6_REG_2, | |
1444 | PREFIX_EVEX_0F38C6_REG_5, | |
1445 | PREFIX_EVEX_0F38C6_REG_6, | |
1446 | PREFIX_EVEX_0F38C7_REG_1, | |
1447 | PREFIX_EVEX_0F38C7_REG_2, | |
1448 | PREFIX_EVEX_0F38C7_REG_5, | |
1449 | PREFIX_EVEX_0F38C7_REG_6, | |
1450 | PREFIX_EVEX_0F38C8, | |
1451 | PREFIX_EVEX_0F38CA, | |
1452 | PREFIX_EVEX_0F38CB, | |
1453 | PREFIX_EVEX_0F38CC, | |
1454 | PREFIX_EVEX_0F38CD, | |
1455 | ||
1456 | PREFIX_EVEX_0F3A00, | |
1457 | PREFIX_EVEX_0F3A01, | |
1458 | PREFIX_EVEX_0F3A03, | |
1459 | PREFIX_EVEX_0F3A04, | |
1460 | PREFIX_EVEX_0F3A05, | |
1461 | PREFIX_EVEX_0F3A08, | |
1462 | PREFIX_EVEX_0F3A09, | |
1463 | PREFIX_EVEX_0F3A0A, | |
1464 | PREFIX_EVEX_0F3A0B, | |
1465 | PREFIX_EVEX_0F3A17, | |
1466 | PREFIX_EVEX_0F3A18, | |
1467 | PREFIX_EVEX_0F3A19, | |
1468 | PREFIX_EVEX_0F3A1A, | |
1469 | PREFIX_EVEX_0F3A1B, | |
1470 | PREFIX_EVEX_0F3A1D, | |
1471 | PREFIX_EVEX_0F3A1E, | |
1472 | PREFIX_EVEX_0F3A1F, | |
1473 | PREFIX_EVEX_0F3A21, | |
1474 | PREFIX_EVEX_0F3A23, | |
1475 | PREFIX_EVEX_0F3A25, | |
1476 | PREFIX_EVEX_0F3A26, | |
1477 | PREFIX_EVEX_0F3A27, | |
1478 | PREFIX_EVEX_0F3A38, | |
1479 | PREFIX_EVEX_0F3A39, | |
1480 | PREFIX_EVEX_0F3A3A, | |
1481 | PREFIX_EVEX_0F3A3B, | |
43234a1e L |
1482 | PREFIX_EVEX_0F3A43, |
1483 | PREFIX_EVEX_0F3A54, | |
1484 | PREFIX_EVEX_0F3A55, | |
51e7da1b | 1485 | }; |
4e7d34a6 | 1486 | |
51e7da1b L |
1487 | enum |
1488 | { | |
1489 | X86_64_06 = 0, | |
3873ba12 L |
1490 | X86_64_07, |
1491 | X86_64_0D, | |
1492 | X86_64_16, | |
1493 | X86_64_17, | |
1494 | X86_64_1E, | |
1495 | X86_64_1F, | |
1496 | X86_64_27, | |
1497 | X86_64_2F, | |
1498 | X86_64_37, | |
1499 | X86_64_3F, | |
1500 | X86_64_60, | |
1501 | X86_64_61, | |
1502 | X86_64_62, | |
1503 | X86_64_63, | |
1504 | X86_64_6D, | |
1505 | X86_64_6F, | |
1506 | X86_64_9A, | |
1507 | X86_64_C4, | |
1508 | X86_64_C5, | |
1509 | X86_64_CE, | |
1510 | X86_64_D4, | |
1511 | X86_64_D5, | |
1512 | X86_64_EA, | |
1513 | X86_64_0F01_REG_0, | |
1514 | X86_64_0F01_REG_1, | |
1515 | X86_64_0F01_REG_2, | |
1516 | X86_64_0F01_REG_3 | |
51e7da1b | 1517 | }; |
4e7d34a6 | 1518 | |
51e7da1b L |
1519 | enum |
1520 | { | |
1521 | THREE_BYTE_0F38 = 0, | |
3873ba12 L |
1522 | THREE_BYTE_0F3A, |
1523 | THREE_BYTE_0F7A | |
51e7da1b | 1524 | }; |
4e7d34a6 | 1525 | |
f88c9eb0 SP |
1526 | enum |
1527 | { | |
5dd85c99 SP |
1528 | XOP_08 = 0, |
1529 | XOP_09, | |
f88c9eb0 SP |
1530 | XOP_0A |
1531 | }; | |
1532 | ||
51e7da1b L |
1533 | enum |
1534 | { | |
1535 | VEX_0F = 0, | |
3873ba12 L |
1536 | VEX_0F38, |
1537 | VEX_0F3A | |
51e7da1b | 1538 | }; |
c0f3af97 | 1539 | |
43234a1e L |
1540 | enum |
1541 | { | |
1542 | EVEX_0F = 0, | |
1543 | EVEX_0F38, | |
1544 | EVEX_0F3A | |
1545 | }; | |
1546 | ||
51e7da1b L |
1547 | enum |
1548 | { | |
592a252b L |
1549 | VEX_LEN_0F10_P_1 = 0, |
1550 | VEX_LEN_0F10_P_3, | |
1551 | VEX_LEN_0F11_P_1, | |
1552 | VEX_LEN_0F11_P_3, | |
1553 | VEX_LEN_0F12_P_0_M_0, | |
1554 | VEX_LEN_0F12_P_0_M_1, | |
1555 | VEX_LEN_0F12_P_2, | |
1556 | VEX_LEN_0F13_M_0, | |
1557 | VEX_LEN_0F16_P_0_M_0, | |
1558 | VEX_LEN_0F16_P_0_M_1, | |
1559 | VEX_LEN_0F16_P_2, | |
1560 | VEX_LEN_0F17_M_0, | |
1561 | VEX_LEN_0F2A_P_1, | |
1562 | VEX_LEN_0F2A_P_3, | |
1563 | VEX_LEN_0F2C_P_1, | |
1564 | VEX_LEN_0F2C_P_3, | |
1565 | VEX_LEN_0F2D_P_1, | |
1566 | VEX_LEN_0F2D_P_3, | |
1567 | VEX_LEN_0F2E_P_0, | |
1568 | VEX_LEN_0F2E_P_2, | |
1569 | VEX_LEN_0F2F_P_0, | |
1570 | VEX_LEN_0F2F_P_2, | |
43234a1e L |
1571 | VEX_LEN_0F41_P_0, |
1572 | VEX_LEN_0F42_P_0, | |
1573 | VEX_LEN_0F44_P_0, | |
1574 | VEX_LEN_0F45_P_0, | |
1575 | VEX_LEN_0F46_P_0, | |
1576 | VEX_LEN_0F47_P_0, | |
1577 | VEX_LEN_0F4B_P_2, | |
592a252b L |
1578 | VEX_LEN_0F51_P_1, |
1579 | VEX_LEN_0F51_P_3, | |
1580 | VEX_LEN_0F52_P_1, | |
1581 | VEX_LEN_0F53_P_1, | |
1582 | VEX_LEN_0F58_P_1, | |
1583 | VEX_LEN_0F58_P_3, | |
1584 | VEX_LEN_0F59_P_1, | |
1585 | VEX_LEN_0F59_P_3, | |
1586 | VEX_LEN_0F5A_P_1, | |
1587 | VEX_LEN_0F5A_P_3, | |
1588 | VEX_LEN_0F5C_P_1, | |
1589 | VEX_LEN_0F5C_P_3, | |
1590 | VEX_LEN_0F5D_P_1, | |
1591 | VEX_LEN_0F5D_P_3, | |
1592 | VEX_LEN_0F5E_P_1, | |
1593 | VEX_LEN_0F5E_P_3, | |
1594 | VEX_LEN_0F5F_P_1, | |
1595 | VEX_LEN_0F5F_P_3, | |
592a252b | 1596 | VEX_LEN_0F6E_P_2, |
592a252b L |
1597 | VEX_LEN_0F7E_P_1, |
1598 | VEX_LEN_0F7E_P_2, | |
43234a1e L |
1599 | VEX_LEN_0F90_P_0, |
1600 | VEX_LEN_0F91_P_0, | |
1601 | VEX_LEN_0F92_P_0, | |
1602 | VEX_LEN_0F93_P_0, | |
1603 | VEX_LEN_0F98_P_0, | |
592a252b L |
1604 | VEX_LEN_0FAE_R_2_M_0, |
1605 | VEX_LEN_0FAE_R_3_M_0, | |
1606 | VEX_LEN_0FC2_P_1, | |
1607 | VEX_LEN_0FC2_P_3, | |
1608 | VEX_LEN_0FC4_P_2, | |
1609 | VEX_LEN_0FC5_P_2, | |
592a252b | 1610 | VEX_LEN_0FD6_P_2, |
592a252b | 1611 | VEX_LEN_0FF7_P_2, |
6c30d220 L |
1612 | VEX_LEN_0F3816_P_2, |
1613 | VEX_LEN_0F3819_P_2, | |
592a252b | 1614 | VEX_LEN_0F381A_P_2_M_0, |
6c30d220 | 1615 | VEX_LEN_0F3836_P_2, |
592a252b | 1616 | VEX_LEN_0F3841_P_2, |
6c30d220 | 1617 | VEX_LEN_0F385A_P_2_M_0, |
592a252b L |
1618 | VEX_LEN_0F38DB_P_2, |
1619 | VEX_LEN_0F38DC_P_2, | |
1620 | VEX_LEN_0F38DD_P_2, | |
1621 | VEX_LEN_0F38DE_P_2, | |
1622 | VEX_LEN_0F38DF_P_2, | |
f12dc422 L |
1623 | VEX_LEN_0F38F2_P_0, |
1624 | VEX_LEN_0F38F3_R_1_P_0, | |
1625 | VEX_LEN_0F38F3_R_2_P_0, | |
1626 | VEX_LEN_0F38F3_R_3_P_0, | |
6c30d220 L |
1627 | VEX_LEN_0F38F5_P_0, |
1628 | VEX_LEN_0F38F5_P_1, | |
1629 | VEX_LEN_0F38F5_P_3, | |
1630 | VEX_LEN_0F38F6_P_3, | |
f12dc422 | 1631 | VEX_LEN_0F38F7_P_0, |
6c30d220 L |
1632 | VEX_LEN_0F38F7_P_1, |
1633 | VEX_LEN_0F38F7_P_2, | |
1634 | VEX_LEN_0F38F7_P_3, | |
1635 | VEX_LEN_0F3A00_P_2, | |
1636 | VEX_LEN_0F3A01_P_2, | |
592a252b L |
1637 | VEX_LEN_0F3A06_P_2, |
1638 | VEX_LEN_0F3A0A_P_2, | |
1639 | VEX_LEN_0F3A0B_P_2, | |
592a252b L |
1640 | VEX_LEN_0F3A14_P_2, |
1641 | VEX_LEN_0F3A15_P_2, | |
1642 | VEX_LEN_0F3A16_P_2, | |
1643 | VEX_LEN_0F3A17_P_2, | |
1644 | VEX_LEN_0F3A18_P_2, | |
1645 | VEX_LEN_0F3A19_P_2, | |
1646 | VEX_LEN_0F3A20_P_2, | |
1647 | VEX_LEN_0F3A21_P_2, | |
1648 | VEX_LEN_0F3A22_P_2, | |
43234a1e L |
1649 | VEX_LEN_0F3A30_P_2, |
1650 | VEX_LEN_0F3A32_P_2, | |
6c30d220 L |
1651 | VEX_LEN_0F3A38_P_2, |
1652 | VEX_LEN_0F3A39_P_2, | |
592a252b | 1653 | VEX_LEN_0F3A41_P_2, |
592a252b | 1654 | VEX_LEN_0F3A44_P_2, |
6c30d220 | 1655 | VEX_LEN_0F3A46_P_2, |
592a252b L |
1656 | VEX_LEN_0F3A60_P_2, |
1657 | VEX_LEN_0F3A61_P_2, | |
1658 | VEX_LEN_0F3A62_P_2, | |
1659 | VEX_LEN_0F3A63_P_2, | |
1660 | VEX_LEN_0F3A6A_P_2, | |
1661 | VEX_LEN_0F3A6B_P_2, | |
1662 | VEX_LEN_0F3A6E_P_2, | |
1663 | VEX_LEN_0F3A6F_P_2, | |
1664 | VEX_LEN_0F3A7A_P_2, | |
1665 | VEX_LEN_0F3A7B_P_2, | |
1666 | VEX_LEN_0F3A7E_P_2, | |
1667 | VEX_LEN_0F3A7F_P_2, | |
1668 | VEX_LEN_0F3ADF_P_2, | |
6c30d220 | 1669 | VEX_LEN_0F3AF0_P_3, |
ff688e1f L |
1670 | VEX_LEN_0FXOP_08_CC, |
1671 | VEX_LEN_0FXOP_08_CD, | |
1672 | VEX_LEN_0FXOP_08_CE, | |
1673 | VEX_LEN_0FXOP_08_CF, | |
1674 | VEX_LEN_0FXOP_08_EC, | |
1675 | VEX_LEN_0FXOP_08_ED, | |
1676 | VEX_LEN_0FXOP_08_EE, | |
1677 | VEX_LEN_0FXOP_08_EF, | |
592a252b L |
1678 | VEX_LEN_0FXOP_09_80, |
1679 | VEX_LEN_0FXOP_09_81 | |
51e7da1b | 1680 | }; |
c0f3af97 | 1681 | |
9e30b8e0 L |
1682 | enum |
1683 | { | |
592a252b L |
1684 | VEX_W_0F10_P_0 = 0, |
1685 | VEX_W_0F10_P_1, | |
1686 | VEX_W_0F10_P_2, | |
1687 | VEX_W_0F10_P_3, | |
1688 | VEX_W_0F11_P_0, | |
1689 | VEX_W_0F11_P_1, | |
1690 | VEX_W_0F11_P_2, | |
1691 | VEX_W_0F11_P_3, | |
1692 | VEX_W_0F12_P_0_M_0, | |
1693 | VEX_W_0F12_P_0_M_1, | |
1694 | VEX_W_0F12_P_1, | |
1695 | VEX_W_0F12_P_2, | |
1696 | VEX_W_0F12_P_3, | |
1697 | VEX_W_0F13_M_0, | |
1698 | VEX_W_0F14, | |
1699 | VEX_W_0F15, | |
1700 | VEX_W_0F16_P_0_M_0, | |
1701 | VEX_W_0F16_P_0_M_1, | |
1702 | VEX_W_0F16_P_1, | |
1703 | VEX_W_0F16_P_2, | |
1704 | VEX_W_0F17_M_0, | |
1705 | VEX_W_0F28, | |
1706 | VEX_W_0F29, | |
1707 | VEX_W_0F2B_M_0, | |
1708 | VEX_W_0F2E_P_0, | |
1709 | VEX_W_0F2E_P_2, | |
1710 | VEX_W_0F2F_P_0, | |
1711 | VEX_W_0F2F_P_2, | |
43234a1e L |
1712 | VEX_W_0F41_P_0_LEN_1, |
1713 | VEX_W_0F42_P_0_LEN_1, | |
1714 | VEX_W_0F44_P_0_LEN_0, | |
1715 | VEX_W_0F45_P_0_LEN_1, | |
1716 | VEX_W_0F46_P_0_LEN_1, | |
1717 | VEX_W_0F47_P_0_LEN_1, | |
1718 | VEX_W_0F4B_P_2_LEN_1, | |
592a252b L |
1719 | VEX_W_0F50_M_0, |
1720 | VEX_W_0F51_P_0, | |
1721 | VEX_W_0F51_P_1, | |
1722 | VEX_W_0F51_P_2, | |
1723 | VEX_W_0F51_P_3, | |
1724 | VEX_W_0F52_P_0, | |
1725 | VEX_W_0F52_P_1, | |
1726 | VEX_W_0F53_P_0, | |
1727 | VEX_W_0F53_P_1, | |
1728 | VEX_W_0F58_P_0, | |
1729 | VEX_W_0F58_P_1, | |
1730 | VEX_W_0F58_P_2, | |
1731 | VEX_W_0F58_P_3, | |
1732 | VEX_W_0F59_P_0, | |
1733 | VEX_W_0F59_P_1, | |
1734 | VEX_W_0F59_P_2, | |
1735 | VEX_W_0F59_P_3, | |
1736 | VEX_W_0F5A_P_0, | |
1737 | VEX_W_0F5A_P_1, | |
1738 | VEX_W_0F5A_P_3, | |
1739 | VEX_W_0F5B_P_0, | |
1740 | VEX_W_0F5B_P_1, | |
1741 | VEX_W_0F5B_P_2, | |
1742 | VEX_W_0F5C_P_0, | |
1743 | VEX_W_0F5C_P_1, | |
1744 | VEX_W_0F5C_P_2, | |
1745 | VEX_W_0F5C_P_3, | |
1746 | VEX_W_0F5D_P_0, | |
1747 | VEX_W_0F5D_P_1, | |
1748 | VEX_W_0F5D_P_2, | |
1749 | VEX_W_0F5D_P_3, | |
1750 | VEX_W_0F5E_P_0, | |
1751 | VEX_W_0F5E_P_1, | |
1752 | VEX_W_0F5E_P_2, | |
1753 | VEX_W_0F5E_P_3, | |
1754 | VEX_W_0F5F_P_0, | |
1755 | VEX_W_0F5F_P_1, | |
1756 | VEX_W_0F5F_P_2, | |
1757 | VEX_W_0F5F_P_3, | |
1758 | VEX_W_0F60_P_2, | |
1759 | VEX_W_0F61_P_2, | |
1760 | VEX_W_0F62_P_2, | |
1761 | VEX_W_0F63_P_2, | |
1762 | VEX_W_0F64_P_2, | |
1763 | VEX_W_0F65_P_2, | |
1764 | VEX_W_0F66_P_2, | |
1765 | VEX_W_0F67_P_2, | |
1766 | VEX_W_0F68_P_2, | |
1767 | VEX_W_0F69_P_2, | |
1768 | VEX_W_0F6A_P_2, | |
1769 | VEX_W_0F6B_P_2, | |
1770 | VEX_W_0F6C_P_2, | |
1771 | VEX_W_0F6D_P_2, | |
1772 | VEX_W_0F6F_P_1, | |
1773 | VEX_W_0F6F_P_2, | |
1774 | VEX_W_0F70_P_1, | |
1775 | VEX_W_0F70_P_2, | |
1776 | VEX_W_0F70_P_3, | |
1777 | VEX_W_0F71_R_2_P_2, | |
1778 | VEX_W_0F71_R_4_P_2, | |
1779 | VEX_W_0F71_R_6_P_2, | |
1780 | VEX_W_0F72_R_2_P_2, | |
1781 | VEX_W_0F72_R_4_P_2, | |
1782 | VEX_W_0F72_R_6_P_2, | |
1783 | VEX_W_0F73_R_2_P_2, | |
1784 | VEX_W_0F73_R_3_P_2, | |
1785 | VEX_W_0F73_R_6_P_2, | |
1786 | VEX_W_0F73_R_7_P_2, | |
1787 | VEX_W_0F74_P_2, | |
1788 | VEX_W_0F75_P_2, | |
1789 | VEX_W_0F76_P_2, | |
1790 | VEX_W_0F77_P_0, | |
1791 | VEX_W_0F7C_P_2, | |
1792 | VEX_W_0F7C_P_3, | |
1793 | VEX_W_0F7D_P_2, | |
1794 | VEX_W_0F7D_P_3, | |
1795 | VEX_W_0F7E_P_1, | |
1796 | VEX_W_0F7F_P_1, | |
1797 | VEX_W_0F7F_P_2, | |
43234a1e L |
1798 | VEX_W_0F90_P_0_LEN_0, |
1799 | VEX_W_0F91_P_0_LEN_0, | |
1800 | VEX_W_0F92_P_0_LEN_0, | |
1801 | VEX_W_0F93_P_0_LEN_0, | |
1802 | VEX_W_0F98_P_0_LEN_0, | |
592a252b L |
1803 | VEX_W_0FAE_R_2_M_0, |
1804 | VEX_W_0FAE_R_3_M_0, | |
1805 | VEX_W_0FC2_P_0, | |
1806 | VEX_W_0FC2_P_1, | |
1807 | VEX_W_0FC2_P_2, | |
1808 | VEX_W_0FC2_P_3, | |
1809 | VEX_W_0FC4_P_2, | |
1810 | VEX_W_0FC5_P_2, | |
1811 | VEX_W_0FD0_P_2, | |
1812 | VEX_W_0FD0_P_3, | |
1813 | VEX_W_0FD1_P_2, | |
1814 | VEX_W_0FD2_P_2, | |
1815 | VEX_W_0FD3_P_2, | |
1816 | VEX_W_0FD4_P_2, | |
1817 | VEX_W_0FD5_P_2, | |
1818 | VEX_W_0FD6_P_2, | |
1819 | VEX_W_0FD7_P_2_M_1, | |
1820 | VEX_W_0FD8_P_2, | |
1821 | VEX_W_0FD9_P_2, | |
1822 | VEX_W_0FDA_P_2, | |
1823 | VEX_W_0FDB_P_2, | |
1824 | VEX_W_0FDC_P_2, | |
1825 | VEX_W_0FDD_P_2, | |
1826 | VEX_W_0FDE_P_2, | |
1827 | VEX_W_0FDF_P_2, | |
1828 | VEX_W_0FE0_P_2, | |
1829 | VEX_W_0FE1_P_2, | |
1830 | VEX_W_0FE2_P_2, | |
1831 | VEX_W_0FE3_P_2, | |
1832 | VEX_W_0FE4_P_2, | |
1833 | VEX_W_0FE5_P_2, | |
1834 | VEX_W_0FE6_P_1, | |
1835 | VEX_W_0FE6_P_2, | |
1836 | VEX_W_0FE6_P_3, | |
1837 | VEX_W_0FE7_P_2_M_0, | |
1838 | VEX_W_0FE8_P_2, | |
1839 | VEX_W_0FE9_P_2, | |
1840 | VEX_W_0FEA_P_2, | |
1841 | VEX_W_0FEB_P_2, | |
1842 | VEX_W_0FEC_P_2, | |
1843 | VEX_W_0FED_P_2, | |
1844 | VEX_W_0FEE_P_2, | |
1845 | VEX_W_0FEF_P_2, | |
1846 | VEX_W_0FF0_P_3_M_0, | |
1847 | VEX_W_0FF1_P_2, | |
1848 | VEX_W_0FF2_P_2, | |
1849 | VEX_W_0FF3_P_2, | |
1850 | VEX_W_0FF4_P_2, | |
1851 | VEX_W_0FF5_P_2, | |
1852 | VEX_W_0FF6_P_2, | |
1853 | VEX_W_0FF7_P_2, | |
1854 | VEX_W_0FF8_P_2, | |
1855 | VEX_W_0FF9_P_2, | |
1856 | VEX_W_0FFA_P_2, | |
1857 | VEX_W_0FFB_P_2, | |
1858 | VEX_W_0FFC_P_2, | |
1859 | VEX_W_0FFD_P_2, | |
1860 | VEX_W_0FFE_P_2, | |
1861 | VEX_W_0F3800_P_2, | |
1862 | VEX_W_0F3801_P_2, | |
1863 | VEX_W_0F3802_P_2, | |
1864 | VEX_W_0F3803_P_2, | |
1865 | VEX_W_0F3804_P_2, | |
1866 | VEX_W_0F3805_P_2, | |
1867 | VEX_W_0F3806_P_2, | |
1868 | VEX_W_0F3807_P_2, | |
1869 | VEX_W_0F3808_P_2, | |
1870 | VEX_W_0F3809_P_2, | |
1871 | VEX_W_0F380A_P_2, | |
1872 | VEX_W_0F380B_P_2, | |
1873 | VEX_W_0F380C_P_2, | |
1874 | VEX_W_0F380D_P_2, | |
1875 | VEX_W_0F380E_P_2, | |
1876 | VEX_W_0F380F_P_2, | |
6c30d220 | 1877 | VEX_W_0F3816_P_2, |
592a252b | 1878 | VEX_W_0F3817_P_2, |
6c30d220 L |
1879 | VEX_W_0F3818_P_2, |
1880 | VEX_W_0F3819_P_2, | |
592a252b L |
1881 | VEX_W_0F381A_P_2_M_0, |
1882 | VEX_W_0F381C_P_2, | |
1883 | VEX_W_0F381D_P_2, | |
1884 | VEX_W_0F381E_P_2, | |
1885 | VEX_W_0F3820_P_2, | |
1886 | VEX_W_0F3821_P_2, | |
1887 | VEX_W_0F3822_P_2, | |
1888 | VEX_W_0F3823_P_2, | |
1889 | VEX_W_0F3824_P_2, | |
1890 | VEX_W_0F3825_P_2, | |
1891 | VEX_W_0F3828_P_2, | |
1892 | VEX_W_0F3829_P_2, | |
1893 | VEX_W_0F382A_P_2_M_0, | |
1894 | VEX_W_0F382B_P_2, | |
1895 | VEX_W_0F382C_P_2_M_0, | |
1896 | VEX_W_0F382D_P_2_M_0, | |
1897 | VEX_W_0F382E_P_2_M_0, | |
1898 | VEX_W_0F382F_P_2_M_0, | |
1899 | VEX_W_0F3830_P_2, | |
1900 | VEX_W_0F3831_P_2, | |
1901 | VEX_W_0F3832_P_2, | |
1902 | VEX_W_0F3833_P_2, | |
1903 | VEX_W_0F3834_P_2, | |
1904 | VEX_W_0F3835_P_2, | |
6c30d220 | 1905 | VEX_W_0F3836_P_2, |
592a252b L |
1906 | VEX_W_0F3837_P_2, |
1907 | VEX_W_0F3838_P_2, | |
1908 | VEX_W_0F3839_P_2, | |
1909 | VEX_W_0F383A_P_2, | |
1910 | VEX_W_0F383B_P_2, | |
1911 | VEX_W_0F383C_P_2, | |
1912 | VEX_W_0F383D_P_2, | |
1913 | VEX_W_0F383E_P_2, | |
1914 | VEX_W_0F383F_P_2, | |
1915 | VEX_W_0F3840_P_2, | |
1916 | VEX_W_0F3841_P_2, | |
6c30d220 L |
1917 | VEX_W_0F3846_P_2, |
1918 | VEX_W_0F3858_P_2, | |
1919 | VEX_W_0F3859_P_2, | |
1920 | VEX_W_0F385A_P_2_M_0, | |
1921 | VEX_W_0F3878_P_2, | |
1922 | VEX_W_0F3879_P_2, | |
592a252b L |
1923 | VEX_W_0F38DB_P_2, |
1924 | VEX_W_0F38DC_P_2, | |
1925 | VEX_W_0F38DD_P_2, | |
1926 | VEX_W_0F38DE_P_2, | |
1927 | VEX_W_0F38DF_P_2, | |
6c30d220 L |
1928 | VEX_W_0F3A00_P_2, |
1929 | VEX_W_0F3A01_P_2, | |
1930 | VEX_W_0F3A02_P_2, | |
592a252b L |
1931 | VEX_W_0F3A04_P_2, |
1932 | VEX_W_0F3A05_P_2, | |
1933 | VEX_W_0F3A06_P_2, | |
1934 | VEX_W_0F3A08_P_2, | |
1935 | VEX_W_0F3A09_P_2, | |
1936 | VEX_W_0F3A0A_P_2, | |
1937 | VEX_W_0F3A0B_P_2, | |
1938 | VEX_W_0F3A0C_P_2, | |
1939 | VEX_W_0F3A0D_P_2, | |
1940 | VEX_W_0F3A0E_P_2, | |
1941 | VEX_W_0F3A0F_P_2, | |
1942 | VEX_W_0F3A14_P_2, | |
1943 | VEX_W_0F3A15_P_2, | |
1944 | VEX_W_0F3A18_P_2, | |
1945 | VEX_W_0F3A19_P_2, | |
1946 | VEX_W_0F3A20_P_2, | |
1947 | VEX_W_0F3A21_P_2, | |
43234a1e L |
1948 | VEX_W_0F3A30_P_2_LEN_0, |
1949 | VEX_W_0F3A32_P_2_LEN_0, | |
6c30d220 L |
1950 | VEX_W_0F3A38_P_2, |
1951 | VEX_W_0F3A39_P_2, | |
592a252b L |
1952 | VEX_W_0F3A40_P_2, |
1953 | VEX_W_0F3A41_P_2, | |
1954 | VEX_W_0F3A42_P_2, | |
1955 | VEX_W_0F3A44_P_2, | |
6c30d220 | 1956 | VEX_W_0F3A46_P_2, |
592a252b L |
1957 | VEX_W_0F3A48_P_2, |
1958 | VEX_W_0F3A49_P_2, | |
1959 | VEX_W_0F3A4A_P_2, | |
1960 | VEX_W_0F3A4B_P_2, | |
1961 | VEX_W_0F3A4C_P_2, | |
1962 | VEX_W_0F3A60_P_2, | |
1963 | VEX_W_0F3A61_P_2, | |
1964 | VEX_W_0F3A62_P_2, | |
1965 | VEX_W_0F3A63_P_2, | |
43234a1e L |
1966 | VEX_W_0F3ADF_P_2, |
1967 | ||
1968 | EVEX_W_0F10_P_0, | |
1969 | EVEX_W_0F10_P_1_M_0, | |
1970 | EVEX_W_0F10_P_1_M_1, | |
1971 | EVEX_W_0F10_P_2, | |
1972 | EVEX_W_0F10_P_3_M_0, | |
1973 | EVEX_W_0F10_P_3_M_1, | |
1974 | EVEX_W_0F11_P_0, | |
1975 | EVEX_W_0F11_P_1_M_0, | |
1976 | EVEX_W_0F11_P_1_M_1, | |
1977 | EVEX_W_0F11_P_2, | |
1978 | EVEX_W_0F11_P_3_M_0, | |
1979 | EVEX_W_0F11_P_3_M_1, | |
1980 | EVEX_W_0F12_P_0_M_0, | |
1981 | EVEX_W_0F12_P_0_M_1, | |
1982 | EVEX_W_0F12_P_1, | |
1983 | EVEX_W_0F12_P_2, | |
1984 | EVEX_W_0F12_P_3, | |
1985 | EVEX_W_0F13_P_0, | |
1986 | EVEX_W_0F13_P_2, | |
1987 | EVEX_W_0F14_P_0, | |
1988 | EVEX_W_0F14_P_2, | |
1989 | EVEX_W_0F15_P_0, | |
1990 | EVEX_W_0F15_P_2, | |
1991 | EVEX_W_0F16_P_0_M_0, | |
1992 | EVEX_W_0F16_P_0_M_1, | |
1993 | EVEX_W_0F16_P_1, | |
1994 | EVEX_W_0F16_P_2, | |
1995 | EVEX_W_0F17_P_0, | |
1996 | EVEX_W_0F17_P_2, | |
1997 | EVEX_W_0F28_P_0, | |
1998 | EVEX_W_0F28_P_2, | |
1999 | EVEX_W_0F29_P_0, | |
2000 | EVEX_W_0F29_P_2, | |
2001 | EVEX_W_0F2A_P_1, | |
2002 | EVEX_W_0F2A_P_3, | |
2003 | EVEX_W_0F2B_P_0, | |
2004 | EVEX_W_0F2B_P_2, | |
2005 | EVEX_W_0F2E_P_0, | |
2006 | EVEX_W_0F2E_P_2, | |
2007 | EVEX_W_0F2F_P_0, | |
2008 | EVEX_W_0F2F_P_2, | |
2009 | EVEX_W_0F51_P_0, | |
2010 | EVEX_W_0F51_P_1, | |
2011 | EVEX_W_0F51_P_2, | |
2012 | EVEX_W_0F51_P_3, | |
2013 | EVEX_W_0F58_P_0, | |
2014 | EVEX_W_0F58_P_1, | |
2015 | EVEX_W_0F58_P_2, | |
2016 | EVEX_W_0F58_P_3, | |
2017 | EVEX_W_0F59_P_0, | |
2018 | EVEX_W_0F59_P_1, | |
2019 | EVEX_W_0F59_P_2, | |
2020 | EVEX_W_0F59_P_3, | |
2021 | EVEX_W_0F5A_P_0, | |
2022 | EVEX_W_0F5A_P_1, | |
2023 | EVEX_W_0F5A_P_2, | |
2024 | EVEX_W_0F5A_P_3, | |
2025 | EVEX_W_0F5B_P_0, | |
2026 | EVEX_W_0F5B_P_1, | |
2027 | EVEX_W_0F5B_P_2, | |
2028 | EVEX_W_0F5C_P_0, | |
2029 | EVEX_W_0F5C_P_1, | |
2030 | EVEX_W_0F5C_P_2, | |
2031 | EVEX_W_0F5C_P_3, | |
2032 | EVEX_W_0F5D_P_0, | |
2033 | EVEX_W_0F5D_P_1, | |
2034 | EVEX_W_0F5D_P_2, | |
2035 | EVEX_W_0F5D_P_3, | |
2036 | EVEX_W_0F5E_P_0, | |
2037 | EVEX_W_0F5E_P_1, | |
2038 | EVEX_W_0F5E_P_2, | |
2039 | EVEX_W_0F5E_P_3, | |
2040 | EVEX_W_0F5F_P_0, | |
2041 | EVEX_W_0F5F_P_1, | |
2042 | EVEX_W_0F5F_P_2, | |
2043 | EVEX_W_0F5F_P_3, | |
2044 | EVEX_W_0F62_P_2, | |
2045 | EVEX_W_0F66_P_2, | |
2046 | EVEX_W_0F6A_P_2, | |
2047 | EVEX_W_0F6C_P_2, | |
2048 | EVEX_W_0F6D_P_2, | |
2049 | EVEX_W_0F6E_P_2, | |
2050 | EVEX_W_0F6F_P_1, | |
2051 | EVEX_W_0F6F_P_2, | |
2052 | EVEX_W_0F70_P_2, | |
2053 | EVEX_W_0F72_R_2_P_2, | |
2054 | EVEX_W_0F72_R_6_P_2, | |
2055 | EVEX_W_0F73_R_2_P_2, | |
2056 | EVEX_W_0F73_R_6_P_2, | |
2057 | EVEX_W_0F76_P_2, | |
2058 | EVEX_W_0F78_P_0, | |
2059 | EVEX_W_0F79_P_0, | |
2060 | EVEX_W_0F7A_P_1, | |
2061 | EVEX_W_0F7A_P_3, | |
2062 | EVEX_W_0F7B_P_1, | |
2063 | EVEX_W_0F7B_P_3, | |
2064 | EVEX_W_0F7E_P_1, | |
2065 | EVEX_W_0F7E_P_2, | |
2066 | EVEX_W_0F7F_P_1, | |
2067 | EVEX_W_0F7F_P_2, | |
2068 | EVEX_W_0FC2_P_0, | |
2069 | EVEX_W_0FC2_P_1, | |
2070 | EVEX_W_0FC2_P_2, | |
2071 | EVEX_W_0FC2_P_3, | |
2072 | EVEX_W_0FC6_P_0, | |
2073 | EVEX_W_0FC6_P_2, | |
2074 | EVEX_W_0FD2_P_2, | |
2075 | EVEX_W_0FD3_P_2, | |
2076 | EVEX_W_0FD4_P_2, | |
2077 | EVEX_W_0FD6_P_2, | |
2078 | EVEX_W_0FE6_P_1, | |
2079 | EVEX_W_0FE6_P_2, | |
2080 | EVEX_W_0FE6_P_3, | |
2081 | EVEX_W_0FE7_P_2, | |
2082 | EVEX_W_0FF2_P_2, | |
2083 | EVEX_W_0FF3_P_2, | |
2084 | EVEX_W_0FF4_P_2, | |
2085 | EVEX_W_0FFA_P_2, | |
2086 | EVEX_W_0FFB_P_2, | |
2087 | EVEX_W_0FFE_P_2, | |
2088 | EVEX_W_0F380C_P_2, | |
2089 | EVEX_W_0F380D_P_2, | |
2090 | EVEX_W_0F3811_P_1, | |
2091 | EVEX_W_0F3812_P_1, | |
2092 | EVEX_W_0F3813_P_1, | |
2093 | EVEX_W_0F3813_P_2, | |
2094 | EVEX_W_0F3814_P_1, | |
2095 | EVEX_W_0F3815_P_1, | |
2096 | EVEX_W_0F3818_P_2, | |
2097 | EVEX_W_0F3819_P_2, | |
2098 | EVEX_W_0F381A_P_2, | |
2099 | EVEX_W_0F381B_P_2, | |
2100 | EVEX_W_0F381E_P_2, | |
2101 | EVEX_W_0F381F_P_2, | |
2102 | EVEX_W_0F3821_P_1, | |
2103 | EVEX_W_0F3822_P_1, | |
2104 | EVEX_W_0F3823_P_1, | |
2105 | EVEX_W_0F3824_P_1, | |
2106 | EVEX_W_0F3825_P_1, | |
2107 | EVEX_W_0F3825_P_2, | |
2108 | EVEX_W_0F3828_P_2, | |
2109 | EVEX_W_0F3829_P_2, | |
2110 | EVEX_W_0F382A_P_1, | |
2111 | EVEX_W_0F382A_P_2, | |
2112 | EVEX_W_0F3831_P_1, | |
2113 | EVEX_W_0F3832_P_1, | |
2114 | EVEX_W_0F3833_P_1, | |
2115 | EVEX_W_0F3834_P_1, | |
2116 | EVEX_W_0F3835_P_1, | |
2117 | EVEX_W_0F3835_P_2, | |
2118 | EVEX_W_0F3837_P_2, | |
2119 | EVEX_W_0F383A_P_1, | |
2120 | EVEX_W_0F3840_P_2, | |
2121 | EVEX_W_0F3858_P_2, | |
2122 | EVEX_W_0F3859_P_2, | |
2123 | EVEX_W_0F385A_P_2, | |
2124 | EVEX_W_0F385B_P_2, | |
2125 | EVEX_W_0F3891_P_2, | |
2126 | EVEX_W_0F3893_P_2, | |
2127 | EVEX_W_0F38A1_P_2, | |
2128 | EVEX_W_0F38A3_P_2, | |
2129 | EVEX_W_0F38C7_R_1_P_2, | |
2130 | EVEX_W_0F38C7_R_2_P_2, | |
2131 | EVEX_W_0F38C7_R_5_P_2, | |
2132 | EVEX_W_0F38C7_R_6_P_2, | |
2133 | ||
2134 | EVEX_W_0F3A00_P_2, | |
2135 | EVEX_W_0F3A01_P_2, | |
2136 | EVEX_W_0F3A04_P_2, | |
2137 | EVEX_W_0F3A05_P_2, | |
2138 | EVEX_W_0F3A08_P_2, | |
2139 | EVEX_W_0F3A09_P_2, | |
2140 | EVEX_W_0F3A0A_P_2, | |
2141 | EVEX_W_0F3A0B_P_2, | |
2142 | EVEX_W_0F3A18_P_2, | |
2143 | EVEX_W_0F3A19_P_2, | |
2144 | EVEX_W_0F3A1A_P_2, | |
2145 | EVEX_W_0F3A1B_P_2, | |
2146 | EVEX_W_0F3A1D_P_2, | |
2147 | EVEX_W_0F3A21_P_2, | |
2148 | EVEX_W_0F3A23_P_2, | |
2149 | EVEX_W_0F3A38_P_2, | |
2150 | EVEX_W_0F3A39_P_2, | |
2151 | EVEX_W_0F3A3A_P_2, | |
2152 | EVEX_W_0F3A3B_P_2, | |
2153 | EVEX_W_0F3A43_P_2, | |
9e30b8e0 L |
2154 | }; |
2155 | ||
26ca5450 | 2156 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
2157 | |
2158 | struct dis386 { | |
2da11e11 | 2159 | const char *name; |
ce518a5f L |
2160 | struct |
2161 | { | |
2162 | op_rtn rtn; | |
2163 | int bytemode; | |
2164 | } op[MAX_OPERANDS]; | |
252b5132 RH |
2165 | }; |
2166 | ||
2167 | /* Upper case letters in the instruction names here are macros. | |
2168 | 'A' => print 'b' if no register operands or suffix_always is true | |
2169 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 2170 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 2171 | size prefix |
ed7841b3 | 2172 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 2173 | suffix_always is true |
252b5132 | 2174 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 2175 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 2176 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 2177 | 'H' => print ",pt" or ",pn" branch hint |
9306ca4a | 2178 | 'I' => honor following macro letter even in Intel mode (implemented only |
98b528ac | 2179 | for some of the macro letters) |
9306ca4a | 2180 | 'J' => print 'l' |
42903f7f | 2181 | 'K' => print 'd' or 'q' if rex prefix is present. |
252b5132 | 2182 | 'L' => print 'l' if suffix_always is true |
9d141669 | 2183 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 2184 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 2185 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
52b15da3 | 2186 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
98b528ac L |
2187 | or suffix_always is true. print 'q' if rex prefix is present. |
2188 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always | |
2189 | is true | |
a35ca55a | 2190 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 2191 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
6439fc28 AM |
2192 | 'T' => print 'q' in 64bit mode and behave as 'P' otherwise |
2193 | 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise | |
1a114b12 | 2194 | 'V' => print 'q' in 64bit mode and behave as 'S' otherwise |
a35ca55a | 2195 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 2196 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
8a72226a L |
2197 | 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and |
2198 | suffix_always is true. | |
6dd5059a | 2199 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
9d141669 | 2200 | '!' => change condition from true to false or from false to true. |
98b528ac L |
2201 | '%' => add 1 upper case letter to the macro. |
2202 | ||
2203 | 2 upper case letter macros: | |
c0f3af97 L |
2204 | "XY" => print 'x' or 'y' if no register operands or suffix_always |
2205 | is true. | |
4b06377f L |
2206 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
2207 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand | |
98b528ac | 2208 | or suffix_always is true |
4b06377f L |
2209 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
2210 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise | |
2211 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise | |
6c30d220 | 2212 | "LW" => print 'd', 'q' depending on the VEX.W bit |
52b15da3 | 2213 | |
6439fc28 AM |
2214 | Many of the above letters print nothing in Intel mode. See "putop" |
2215 | for the details. | |
52b15da3 | 2216 | |
6439fc28 | 2217 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 2218 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 2219 | |
6439fc28 | 2220 | static const struct dis386 dis386[] = { |
252b5132 | 2221 | /* 00 */ |
42164a71 L |
2222 | { "addB", { Ebh1, Gb } }, |
2223 | { "addS", { Evh1, Gv } }, | |
c7532693 L |
2224 | { "addB", { Gb, EbS } }, |
2225 | { "addS", { Gv, EvS } }, | |
ce518a5f L |
2226 | { "addB", { AL, Ib } }, |
2227 | { "addS", { eAX, Iv } }, | |
4e7d34a6 L |
2228 | { X86_64_TABLE (X86_64_06) }, |
2229 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 2230 | /* 08 */ |
42164a71 L |
2231 | { "orB", { Ebh1, Gb } }, |
2232 | { "orS", { Evh1, Gv } }, | |
c7532693 L |
2233 | { "orB", { Gb, EbS } }, |
2234 | { "orS", { Gv, EvS } }, | |
ce518a5f L |
2235 | { "orB", { AL, Ib } }, |
2236 | { "orS", { eAX, Iv } }, | |
4e7d34a6 | 2237 | { X86_64_TABLE (X86_64_0D) }, |
592d1631 | 2238 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
252b5132 | 2239 | /* 10 */ |
42164a71 L |
2240 | { "adcB", { Ebh1, Gb } }, |
2241 | { "adcS", { Evh1, Gv } }, | |
c7532693 L |
2242 | { "adcB", { Gb, EbS } }, |
2243 | { "adcS", { Gv, EvS } }, | |
ce518a5f L |
2244 | { "adcB", { AL, Ib } }, |
2245 | { "adcS", { eAX, Iv } }, | |
4e7d34a6 L |
2246 | { X86_64_TABLE (X86_64_16) }, |
2247 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 2248 | /* 18 */ |
42164a71 L |
2249 | { "sbbB", { Ebh1, Gb } }, |
2250 | { "sbbS", { Evh1, Gv } }, | |
c7532693 L |
2251 | { "sbbB", { Gb, EbS } }, |
2252 | { "sbbS", { Gv, EvS } }, | |
ce518a5f L |
2253 | { "sbbB", { AL, Ib } }, |
2254 | { "sbbS", { eAX, Iv } }, | |
4e7d34a6 L |
2255 | { X86_64_TABLE (X86_64_1E) }, |
2256 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 2257 | /* 20 */ |
42164a71 L |
2258 | { "andB", { Ebh1, Gb } }, |
2259 | { "andS", { Evh1, Gv } }, | |
c7532693 L |
2260 | { "andB", { Gb, EbS } }, |
2261 | { "andS", { Gv, EvS } }, | |
ce518a5f L |
2262 | { "andB", { AL, Ib } }, |
2263 | { "andS", { eAX, Iv } }, | |
592d1631 | 2264 | { Bad_Opcode }, /* SEG ES prefix */ |
4e7d34a6 | 2265 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 2266 | /* 28 */ |
42164a71 L |
2267 | { "subB", { Ebh1, Gb } }, |
2268 | { "subS", { Evh1, Gv } }, | |
c7532693 L |
2269 | { "subB", { Gb, EbS } }, |
2270 | { "subS", { Gv, EvS } }, | |
ce518a5f L |
2271 | { "subB", { AL, Ib } }, |
2272 | { "subS", { eAX, Iv } }, | |
592d1631 | 2273 | { Bad_Opcode }, /* SEG CS prefix */ |
4e7d34a6 | 2274 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 2275 | /* 30 */ |
42164a71 L |
2276 | { "xorB", { Ebh1, Gb } }, |
2277 | { "xorS", { Evh1, Gv } }, | |
c7532693 L |
2278 | { "xorB", { Gb, EbS } }, |
2279 | { "xorS", { Gv, EvS } }, | |
ce518a5f L |
2280 | { "xorB", { AL, Ib } }, |
2281 | { "xorS", { eAX, Iv } }, | |
592d1631 | 2282 | { Bad_Opcode }, /* SEG SS prefix */ |
4e7d34a6 | 2283 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 2284 | /* 38 */ |
ce518a5f L |
2285 | { "cmpB", { Eb, Gb } }, |
2286 | { "cmpS", { Ev, Gv } }, | |
c7532693 L |
2287 | { "cmpB", { Gb, EbS } }, |
2288 | { "cmpS", { Gv, EvS } }, | |
ce518a5f L |
2289 | { "cmpB", { AL, Ib } }, |
2290 | { "cmpS", { eAX, Iv } }, | |
592d1631 | 2291 | { Bad_Opcode }, /* SEG DS prefix */ |
4e7d34a6 | 2292 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 2293 | /* 40 */ |
ce518a5f L |
2294 | { "inc{S|}", { RMeAX } }, |
2295 | { "inc{S|}", { RMeCX } }, | |
2296 | { "inc{S|}", { RMeDX } }, | |
2297 | { "inc{S|}", { RMeBX } }, | |
2298 | { "inc{S|}", { RMeSP } }, | |
2299 | { "inc{S|}", { RMeBP } }, | |
2300 | { "inc{S|}", { RMeSI } }, | |
2301 | { "inc{S|}", { RMeDI } }, | |
252b5132 | 2302 | /* 48 */ |
ce518a5f L |
2303 | { "dec{S|}", { RMeAX } }, |
2304 | { "dec{S|}", { RMeCX } }, | |
2305 | { "dec{S|}", { RMeDX } }, | |
2306 | { "dec{S|}", { RMeBX } }, | |
2307 | { "dec{S|}", { RMeSP } }, | |
2308 | { "dec{S|}", { RMeBP } }, | |
2309 | { "dec{S|}", { RMeSI } }, | |
2310 | { "dec{S|}", { RMeDI } }, | |
252b5132 | 2311 | /* 50 */ |
ce518a5f L |
2312 | { "pushV", { RMrAX } }, |
2313 | { "pushV", { RMrCX } }, | |
2314 | { "pushV", { RMrDX } }, | |
2315 | { "pushV", { RMrBX } }, | |
2316 | { "pushV", { RMrSP } }, | |
2317 | { "pushV", { RMrBP } }, | |
2318 | { "pushV", { RMrSI } }, | |
2319 | { "pushV", { RMrDI } }, | |
252b5132 | 2320 | /* 58 */ |
ce518a5f L |
2321 | { "popV", { RMrAX } }, |
2322 | { "popV", { RMrCX } }, | |
2323 | { "popV", { RMrDX } }, | |
2324 | { "popV", { RMrBX } }, | |
2325 | { "popV", { RMrSP } }, | |
2326 | { "popV", { RMrBP } }, | |
2327 | { "popV", { RMrSI } }, | |
2328 | { "popV", { RMrDI } }, | |
252b5132 | 2329 | /* 60 */ |
4e7d34a6 L |
2330 | { X86_64_TABLE (X86_64_60) }, |
2331 | { X86_64_TABLE (X86_64_61) }, | |
2332 | { X86_64_TABLE (X86_64_62) }, | |
2333 | { X86_64_TABLE (X86_64_63) }, | |
592d1631 L |
2334 | { Bad_Opcode }, /* seg fs */ |
2335 | { Bad_Opcode }, /* seg gs */ | |
2336 | { Bad_Opcode }, /* op size prefix */ | |
2337 | { Bad_Opcode }, /* adr size prefix */ | |
252b5132 | 2338 | /* 68 */ |
d9e3625e | 2339 | { "pushT", { sIv } }, |
ce518a5f | 2340 | { "imulS", { Gv, Ev, Iv } }, |
e3949f17 | 2341 | { "pushT", { sIbT } }, |
ce518a5f | 2342 | { "imulS", { Gv, Ev, sIb } }, |
7c52e0e8 | 2343 | { "ins{b|}", { Ybr, indirDX } }, |
4e7d34a6 | 2344 | { X86_64_TABLE (X86_64_6D) }, |
7c52e0e8 | 2345 | { "outs{b|}", { indirDXr, Xb } }, |
4e7d34a6 | 2346 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 2347 | /* 70 */ |
7e8b059b L |
2348 | { "joH", { Jb, BND, cond_jump_flag } }, |
2349 | { "jnoH", { Jb, BND, cond_jump_flag } }, | |
2350 | { "jbH", { Jb, BND, cond_jump_flag } }, | |
2351 | { "jaeH", { Jb, BND, cond_jump_flag } }, | |
2352 | { "jeH", { Jb, BND, cond_jump_flag } }, | |
2353 | { "jneH", { Jb, BND, cond_jump_flag } }, | |
2354 | { "jbeH", { Jb, BND, cond_jump_flag } }, | |
2355 | { "jaH", { Jb, BND, cond_jump_flag } }, | |
252b5132 | 2356 | /* 78 */ |
7e8b059b L |
2357 | { "jsH", { Jb, BND, cond_jump_flag } }, |
2358 | { "jnsH", { Jb, BND, cond_jump_flag } }, | |
2359 | { "jpH", { Jb, BND, cond_jump_flag } }, | |
2360 | { "jnpH", { Jb, BND, cond_jump_flag } }, | |
2361 | { "jlH", { Jb, BND, cond_jump_flag } }, | |
2362 | { "jgeH", { Jb, BND, cond_jump_flag } }, | |
2363 | { "jleH", { Jb, BND, cond_jump_flag } }, | |
2364 | { "jgH", { Jb, BND, cond_jump_flag } }, | |
252b5132 | 2365 | /* 80 */ |
1ceb70f8 L |
2366 | { REG_TABLE (REG_80) }, |
2367 | { REG_TABLE (REG_81) }, | |
592d1631 | 2368 | { Bad_Opcode }, |
1ceb70f8 | 2369 | { REG_TABLE (REG_82) }, |
ce518a5f L |
2370 | { "testB", { Eb, Gb } }, |
2371 | { "testS", { Ev, Gv } }, | |
42164a71 L |
2372 | { "xchgB", { Ebh2, Gb } }, |
2373 | { "xchgS", { Evh2, Gv } }, | |
252b5132 | 2374 | /* 88 */ |
42164a71 L |
2375 | { "movB", { Ebh3, Gb } }, |
2376 | { "movS", { Evh3, Gv } }, | |
b6169b20 L |
2377 | { "movB", { Gb, EbS } }, |
2378 | { "movS", { Gv, EvS } }, | |
ce518a5f | 2379 | { "movD", { Sv, Sw } }, |
1ceb70f8 | 2380 | { MOD_TABLE (MOD_8D) }, |
ce518a5f | 2381 | { "movD", { Sw, Sv } }, |
1ceb70f8 | 2382 | { REG_TABLE (REG_8F) }, |
252b5132 | 2383 | /* 90 */ |
1ceb70f8 | 2384 | { PREFIX_TABLE (PREFIX_90) }, |
ce518a5f L |
2385 | { "xchgS", { RMeCX, eAX } }, |
2386 | { "xchgS", { RMeDX, eAX } }, | |
2387 | { "xchgS", { RMeBX, eAX } }, | |
2388 | { "xchgS", { RMeSP, eAX } }, | |
2389 | { "xchgS", { RMeBP, eAX } }, | |
2390 | { "xchgS", { RMeSI, eAX } }, | |
2391 | { "xchgS", { RMeDI, eAX } }, | |
252b5132 | 2392 | /* 98 */ |
7c52e0e8 L |
2393 | { "cW{t|}R", { XX } }, |
2394 | { "cR{t|}O", { XX } }, | |
4e7d34a6 | 2395 | { X86_64_TABLE (X86_64_9A) }, |
592d1631 | 2396 | { Bad_Opcode }, /* fwait */ |
ce518a5f L |
2397 | { "pushfT", { XX } }, |
2398 | { "popfT", { XX } }, | |
7c52e0e8 L |
2399 | { "sahf", { XX } }, |
2400 | { "lahf", { XX } }, | |
252b5132 | 2401 | /* a0 */ |
4b06377f L |
2402 | { "mov%LB", { AL, Ob } }, |
2403 | { "mov%LS", { eAX, Ov } }, | |
2404 | { "mov%LB", { Ob, AL } }, | |
2405 | { "mov%LS", { Ov, eAX } }, | |
7c52e0e8 L |
2406 | { "movs{b|}", { Ybr, Xb } }, |
2407 | { "movs{R|}", { Yvr, Xv } }, | |
2408 | { "cmps{b|}", { Xb, Yb } }, | |
2409 | { "cmps{R|}", { Xv, Yv } }, | |
252b5132 | 2410 | /* a8 */ |
ce518a5f L |
2411 | { "testB", { AL, Ib } }, |
2412 | { "testS", { eAX, Iv } }, | |
2413 | { "stosB", { Ybr, AL } }, | |
2414 | { "stosS", { Yvr, eAX } }, | |
2415 | { "lodsB", { ALr, Xb } }, | |
2416 | { "lodsS", { eAXr, Xv } }, | |
2417 | { "scasB", { AL, Yb } }, | |
2418 | { "scasS", { eAX, Yv } }, | |
252b5132 | 2419 | /* b0 */ |
ce518a5f L |
2420 | { "movB", { RMAL, Ib } }, |
2421 | { "movB", { RMCL, Ib } }, | |
2422 | { "movB", { RMDL, Ib } }, | |
2423 | { "movB", { RMBL, Ib } }, | |
2424 | { "movB", { RMAH, Ib } }, | |
2425 | { "movB", { RMCH, Ib } }, | |
2426 | { "movB", { RMDH, Ib } }, | |
2427 | { "movB", { RMBH, Ib } }, | |
252b5132 | 2428 | /* b8 */ |
4b06377f L |
2429 | { "mov%LV", { RMeAX, Iv64 } }, |
2430 | { "mov%LV", { RMeCX, Iv64 } }, | |
2431 | { "mov%LV", { RMeDX, Iv64 } }, | |
2432 | { "mov%LV", { RMeBX, Iv64 } }, | |
2433 | { "mov%LV", { RMeSP, Iv64 } }, | |
2434 | { "mov%LV", { RMeBP, Iv64 } }, | |
2435 | { "mov%LV", { RMeSI, Iv64 } }, | |
2436 | { "mov%LV", { RMeDI, Iv64 } }, | |
252b5132 | 2437 | /* c0 */ |
1ceb70f8 L |
2438 | { REG_TABLE (REG_C0) }, |
2439 | { REG_TABLE (REG_C1) }, | |
7e8b059b L |
2440 | { "retT", { Iw, BND } }, |
2441 | { "retT", { BND } }, | |
4e7d34a6 L |
2442 | { X86_64_TABLE (X86_64_C4) }, |
2443 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
2444 | { REG_TABLE (REG_C6) }, |
2445 | { REG_TABLE (REG_C7) }, | |
252b5132 | 2446 | /* c8 */ |
ce518a5f L |
2447 | { "enterT", { Iw, Ib } }, |
2448 | { "leaveT", { XX } }, | |
ddab3d59 JB |
2449 | { "Jret{|f}P", { Iw } }, |
2450 | { "Jret{|f}P", { XX } }, | |
ce518a5f L |
2451 | { "int3", { XX } }, |
2452 | { "int", { Ib } }, | |
4e7d34a6 | 2453 | { X86_64_TABLE (X86_64_CE) }, |
ce518a5f | 2454 | { "iretP", { XX } }, |
252b5132 | 2455 | /* d0 */ |
1ceb70f8 L |
2456 | { REG_TABLE (REG_D0) }, |
2457 | { REG_TABLE (REG_D1) }, | |
2458 | { REG_TABLE (REG_D2) }, | |
2459 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
2460 | { X86_64_TABLE (X86_64_D4) }, |
2461 | { X86_64_TABLE (X86_64_D5) }, | |
592d1631 | 2462 | { Bad_Opcode }, |
ce518a5f | 2463 | { "xlat", { DSBX } }, |
252b5132 RH |
2464 | /* d8 */ |
2465 | { FLOAT }, | |
2466 | { FLOAT }, | |
2467 | { FLOAT }, | |
2468 | { FLOAT }, | |
2469 | { FLOAT }, | |
2470 | { FLOAT }, | |
2471 | { FLOAT }, | |
2472 | { FLOAT }, | |
2473 | /* e0 */ | |
ce518a5f L |
2474 | { "loopneFH", { Jb, XX, loop_jcxz_flag } }, |
2475 | { "loopeFH", { Jb, XX, loop_jcxz_flag } }, | |
2476 | { "loopFH", { Jb, XX, loop_jcxz_flag } }, | |
2477 | { "jEcxzH", { Jb, XX, loop_jcxz_flag } }, | |
2478 | { "inB", { AL, Ib } }, | |
2479 | { "inG", { zAX, Ib } }, | |
2480 | { "outB", { Ib, AL } }, | |
2481 | { "outG", { Ib, zAX } }, | |
252b5132 | 2482 | /* e8 */ |
7e8b059b L |
2483 | { "callT", { Jv, BND } }, |
2484 | { "jmpT", { Jv, BND } }, | |
4e7d34a6 | 2485 | { X86_64_TABLE (X86_64_EA) }, |
7e8b059b | 2486 | { "jmp", { Jb, BND } }, |
ce518a5f L |
2487 | { "inB", { AL, indirDX } }, |
2488 | { "inG", { zAX, indirDX } }, | |
2489 | { "outB", { indirDX, AL } }, | |
2490 | { "outG", { indirDX, zAX } }, | |
252b5132 | 2491 | /* f0 */ |
592d1631 | 2492 | { Bad_Opcode }, /* lock prefix */ |
ce518a5f | 2493 | { "icebp", { XX } }, |
592d1631 L |
2494 | { Bad_Opcode }, /* repne */ |
2495 | { Bad_Opcode }, /* repz */ | |
ce518a5f L |
2496 | { "hlt", { XX } }, |
2497 | { "cmc", { XX } }, | |
1ceb70f8 L |
2498 | { REG_TABLE (REG_F6) }, |
2499 | { REG_TABLE (REG_F7) }, | |
252b5132 | 2500 | /* f8 */ |
ce518a5f L |
2501 | { "clc", { XX } }, |
2502 | { "stc", { XX } }, | |
2503 | { "cli", { XX } }, | |
2504 | { "sti", { XX } }, | |
2505 | { "cld", { XX } }, | |
2506 | { "std", { XX } }, | |
1ceb70f8 L |
2507 | { REG_TABLE (REG_FE) }, |
2508 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
2509 | }; |
2510 | ||
6439fc28 | 2511 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 2512 | /* 00 */ |
1ceb70f8 L |
2513 | { REG_TABLE (REG_0F00 ) }, |
2514 | { REG_TABLE (REG_0F01 ) }, | |
ce518a5f L |
2515 | { "larS", { Gv, Ew } }, |
2516 | { "lslS", { Gv, Ew } }, | |
592d1631 | 2517 | { Bad_Opcode }, |
ce518a5f L |
2518 | { "syscall", { XX } }, |
2519 | { "clts", { XX } }, | |
2520 | { "sysretP", { XX } }, | |
252b5132 | 2521 | /* 08 */ |
ce518a5f L |
2522 | { "invd", { XX } }, |
2523 | { "wbinvd", { XX } }, | |
592d1631 | 2524 | { Bad_Opcode }, |
b414985b | 2525 | { "ud2", { XX } }, |
592d1631 | 2526 | { Bad_Opcode }, |
b5b1fc4f | 2527 | { REG_TABLE (REG_0F0D) }, |
ce518a5f L |
2528 | { "femms", { XX } }, |
2529 | { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */ | |
252b5132 | 2530 | /* 10 */ |
1ceb70f8 L |
2531 | { PREFIX_TABLE (PREFIX_0F10) }, |
2532 | { PREFIX_TABLE (PREFIX_0F11) }, | |
2533 | { PREFIX_TABLE (PREFIX_0F12) }, | |
2534 | { MOD_TABLE (MOD_0F13) }, | |
f2a421c4 L |
2535 | { "unpcklpX", { XM, EXx } }, |
2536 | { "unpckhpX", { XM, EXx } }, | |
1ceb70f8 L |
2537 | { PREFIX_TABLE (PREFIX_0F16) }, |
2538 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 2539 | /* 18 */ |
1ceb70f8 | 2540 | { REG_TABLE (REG_0F18) }, |
b5b1fc4f | 2541 | { "nopQ", { Ev } }, |
7e8b059b L |
2542 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2543 | { PREFIX_TABLE (PREFIX_0F1B) }, | |
b5b1fc4f L |
2544 | { "nopQ", { Ev } }, |
2545 | { "nopQ", { Ev } }, | |
2546 | { "nopQ", { Ev } }, | |
ce518a5f | 2547 | { "nopQ", { Ev } }, |
252b5132 | 2548 | /* 20 */ |
1ceb70f8 L |
2549 | { MOD_TABLE (MOD_0F20) }, |
2550 | { MOD_TABLE (MOD_0F21) }, | |
2551 | { MOD_TABLE (MOD_0F22) }, | |
2552 | { MOD_TABLE (MOD_0F23) }, | |
2553 | { MOD_TABLE (MOD_0F24) }, | |
592d1631 | 2554 | { Bad_Opcode }, |
1ceb70f8 | 2555 | { MOD_TABLE (MOD_0F26) }, |
592d1631 | 2556 | { Bad_Opcode }, |
252b5132 | 2557 | /* 28 */ |
09a2c6cf | 2558 | { "movapX", { XM, EXx } }, |
b6169b20 | 2559 | { "movapX", { EXxS, XM } }, |
1ceb70f8 L |
2560 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2561 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
2562 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
2563 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
2564 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
2565 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 2566 | /* 30 */ |
ce518a5f L |
2567 | { "wrmsr", { XX } }, |
2568 | { "rdtsc", { XX } }, | |
2569 | { "rdmsr", { XX } }, | |
2570 | { "rdpmc", { XX } }, | |
2571 | { "sysenter", { XX } }, | |
2572 | { "sysexit", { XX } }, | |
592d1631 | 2573 | { Bad_Opcode }, |
47dd174c | 2574 | { "getsec", { XX } }, |
252b5132 | 2575 | /* 38 */ |
4e7d34a6 | 2576 | { THREE_BYTE_TABLE (THREE_BYTE_0F38) }, |
592d1631 | 2577 | { Bad_Opcode }, |
4e7d34a6 | 2578 | { THREE_BYTE_TABLE (THREE_BYTE_0F3A) }, |
592d1631 L |
2579 | { Bad_Opcode }, |
2580 | { Bad_Opcode }, | |
2581 | { Bad_Opcode }, | |
2582 | { Bad_Opcode }, | |
2583 | { Bad_Opcode }, | |
252b5132 | 2584 | /* 40 */ |
b19d5385 JB |
2585 | { "cmovoS", { Gv, Ev } }, |
2586 | { "cmovnoS", { Gv, Ev } }, | |
2587 | { "cmovbS", { Gv, Ev } }, | |
2588 | { "cmovaeS", { Gv, Ev } }, | |
2589 | { "cmoveS", { Gv, Ev } }, | |
2590 | { "cmovneS", { Gv, Ev } }, | |
2591 | { "cmovbeS", { Gv, Ev } }, | |
2592 | { "cmovaS", { Gv, Ev } }, | |
252b5132 | 2593 | /* 48 */ |
b19d5385 JB |
2594 | { "cmovsS", { Gv, Ev } }, |
2595 | { "cmovnsS", { Gv, Ev } }, | |
2596 | { "cmovpS", { Gv, Ev } }, | |
2597 | { "cmovnpS", { Gv, Ev } }, | |
2598 | { "cmovlS", { Gv, Ev } }, | |
2599 | { "cmovgeS", { Gv, Ev } }, | |
2600 | { "cmovleS", { Gv, Ev } }, | |
2601 | { "cmovgS", { Gv, Ev } }, | |
252b5132 | 2602 | /* 50 */ |
75c135a8 | 2603 | { MOD_TABLE (MOD_0F51) }, |
1ceb70f8 L |
2604 | { PREFIX_TABLE (PREFIX_0F51) }, |
2605 | { PREFIX_TABLE (PREFIX_0F52) }, | |
2606 | { PREFIX_TABLE (PREFIX_0F53) }, | |
09a2c6cf L |
2607 | { "andpX", { XM, EXx } }, |
2608 | { "andnpX", { XM, EXx } }, | |
2609 | { "orpX", { XM, EXx } }, | |
2610 | { "xorpX", { XM, EXx } }, | |
252b5132 | 2611 | /* 58 */ |
1ceb70f8 L |
2612 | { PREFIX_TABLE (PREFIX_0F58) }, |
2613 | { PREFIX_TABLE (PREFIX_0F59) }, | |
2614 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
2615 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
2616 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
2617 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
2618 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
2619 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 2620 | /* 60 */ |
1ceb70f8 L |
2621 | { PREFIX_TABLE (PREFIX_0F60) }, |
2622 | { PREFIX_TABLE (PREFIX_0F61) }, | |
2623 | { PREFIX_TABLE (PREFIX_0F62) }, | |
ce518a5f L |
2624 | { "packsswb", { MX, EM } }, |
2625 | { "pcmpgtb", { MX, EM } }, | |
2626 | { "pcmpgtw", { MX, EM } }, | |
2627 | { "pcmpgtd", { MX, EM } }, | |
2628 | { "packuswb", { MX, EM } }, | |
252b5132 | 2629 | /* 68 */ |
ce518a5f L |
2630 | { "punpckhbw", { MX, EM } }, |
2631 | { "punpckhwd", { MX, EM } }, | |
2632 | { "punpckhdq", { MX, EM } }, | |
2633 | { "packssdw", { MX, EM } }, | |
1ceb70f8 L |
2634 | { PREFIX_TABLE (PREFIX_0F6C) }, |
2635 | { PREFIX_TABLE (PREFIX_0F6D) }, | |
231af070 | 2636 | { "movK", { MX, Edq } }, |
1ceb70f8 | 2637 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 2638 | /* 70 */ |
1ceb70f8 L |
2639 | { PREFIX_TABLE (PREFIX_0F70) }, |
2640 | { REG_TABLE (REG_0F71) }, | |
2641 | { REG_TABLE (REG_0F72) }, | |
2642 | { REG_TABLE (REG_0F73) }, | |
ce518a5f L |
2643 | { "pcmpeqb", { MX, EM } }, |
2644 | { "pcmpeqw", { MX, EM } }, | |
2645 | { "pcmpeqd", { MX, EM } }, | |
2646 | { "emms", { XX } }, | |
252b5132 | 2647 | /* 78 */ |
1ceb70f8 L |
2648 | { PREFIX_TABLE (PREFIX_0F78) }, |
2649 | { PREFIX_TABLE (PREFIX_0F79) }, | |
4e7d34a6 | 2650 | { THREE_BYTE_TABLE (THREE_BYTE_0F7A) }, |
592d1631 | 2651 | { Bad_Opcode }, |
1ceb70f8 L |
2652 | { PREFIX_TABLE (PREFIX_0F7C) }, |
2653 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
2654 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
2655 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 2656 | /* 80 */ |
7e8b059b L |
2657 | { "joH", { Jv, BND, cond_jump_flag } }, |
2658 | { "jnoH", { Jv, BND, cond_jump_flag } }, | |
2659 | { "jbH", { Jv, BND, cond_jump_flag } }, | |
2660 | { "jaeH", { Jv, BND, cond_jump_flag } }, | |
2661 | { "jeH", { Jv, BND, cond_jump_flag } }, | |
2662 | { "jneH", { Jv, BND, cond_jump_flag } }, | |
2663 | { "jbeH", { Jv, BND, cond_jump_flag } }, | |
2664 | { "jaH", { Jv, BND, cond_jump_flag } }, | |
252b5132 | 2665 | /* 88 */ |
7e8b059b L |
2666 | { "jsH", { Jv, BND, cond_jump_flag } }, |
2667 | { "jnsH", { Jv, BND, cond_jump_flag } }, | |
2668 | { "jpH", { Jv, BND, cond_jump_flag } }, | |
2669 | { "jnpH", { Jv, BND, cond_jump_flag } }, | |
2670 | { "jlH", { Jv, BND, cond_jump_flag } }, | |
2671 | { "jgeH", { Jv, BND, cond_jump_flag } }, | |
2672 | { "jleH", { Jv, BND, cond_jump_flag } }, | |
2673 | { "jgH", { Jv, BND, cond_jump_flag } }, | |
252b5132 | 2674 | /* 90 */ |
ce518a5f L |
2675 | { "seto", { Eb } }, |
2676 | { "setno", { Eb } }, | |
2677 | { "setb", { Eb } }, | |
2678 | { "setae", { Eb } }, | |
2679 | { "sete", { Eb } }, | |
2680 | { "setne", { Eb } }, | |
2681 | { "setbe", { Eb } }, | |
2682 | { "seta", { Eb } }, | |
252b5132 | 2683 | /* 98 */ |
ce518a5f L |
2684 | { "sets", { Eb } }, |
2685 | { "setns", { Eb } }, | |
2686 | { "setp", { Eb } }, | |
2687 | { "setnp", { Eb } }, | |
2688 | { "setl", { Eb } }, | |
2689 | { "setge", { Eb } }, | |
2690 | { "setle", { Eb } }, | |
2691 | { "setg", { Eb } }, | |
252b5132 | 2692 | /* a0 */ |
ce518a5f L |
2693 | { "pushT", { fs } }, |
2694 | { "popT", { fs } }, | |
2695 | { "cpuid", { XX } }, | |
2696 | { "btS", { Ev, Gv } }, | |
2697 | { "shldS", { Ev, Gv, Ib } }, | |
2698 | { "shldS", { Ev, Gv, CL } }, | |
1ceb70f8 L |
2699 | { REG_TABLE (REG_0FA6) }, |
2700 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 2701 | /* a8 */ |
ce518a5f L |
2702 | { "pushT", { gs } }, |
2703 | { "popT", { gs } }, | |
2704 | { "rsm", { XX } }, | |
42164a71 | 2705 | { "btsS", { Evh1, Gv } }, |
ce518a5f L |
2706 | { "shrdS", { Ev, Gv, Ib } }, |
2707 | { "shrdS", { Ev, Gv, CL } }, | |
1ceb70f8 | 2708 | { REG_TABLE (REG_0FAE) }, |
ce518a5f | 2709 | { "imulS", { Gv, Ev } }, |
252b5132 | 2710 | /* b0 */ |
42164a71 L |
2711 | { "cmpxchgB", { Ebh1, Gb } }, |
2712 | { "cmpxchgS", { Evh1, Gv } }, | |
1ceb70f8 | 2713 | { MOD_TABLE (MOD_0FB2) }, |
42164a71 | 2714 | { "btrS", { Evh1, Gv } }, |
1ceb70f8 L |
2715 | { MOD_TABLE (MOD_0FB4) }, |
2716 | { MOD_TABLE (MOD_0FB5) }, | |
7c52e0e8 L |
2717 | { "movz{bR|x}", { Gv, Eb } }, |
2718 | { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */ | |
252b5132 | 2719 | /* b8 */ |
1ceb70f8 | 2720 | { PREFIX_TABLE (PREFIX_0FB8) }, |
b414985b | 2721 | { "ud1", { XX } }, |
1ceb70f8 | 2722 | { REG_TABLE (REG_0FBA) }, |
42164a71 | 2723 | { "btcS", { Evh1, Gv } }, |
f12dc422 | 2724 | { PREFIX_TABLE (PREFIX_0FBC) }, |
1ceb70f8 | 2725 | { PREFIX_TABLE (PREFIX_0FBD) }, |
7c52e0e8 L |
2726 | { "movs{bR|x}", { Gv, Eb } }, |
2727 | { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */ | |
252b5132 | 2728 | /* c0 */ |
42164a71 L |
2729 | { "xaddB", { Ebh1, Gb } }, |
2730 | { "xaddS", { Evh1, Gv } }, | |
1ceb70f8 | 2731 | { PREFIX_TABLE (PREFIX_0FC2) }, |
4ee52178 | 2732 | { PREFIX_TABLE (PREFIX_0FC3) }, |
ce518a5f L |
2733 | { "pinsrw", { MX, Edqw, Ib } }, |
2734 | { "pextrw", { Gdq, MS, Ib } }, | |
09a2c6cf | 2735 | { "shufpX", { XM, EXx, Ib } }, |
1ceb70f8 | 2736 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 2737 | /* c8 */ |
ce518a5f L |
2738 | { "bswap", { RMeAX } }, |
2739 | { "bswap", { RMeCX } }, | |
2740 | { "bswap", { RMeDX } }, | |
2741 | { "bswap", { RMeBX } }, | |
2742 | { "bswap", { RMeSP } }, | |
2743 | { "bswap", { RMeBP } }, | |
2744 | { "bswap", { RMeSI } }, | |
2745 | { "bswap", { RMeDI } }, | |
252b5132 | 2746 | /* d0 */ |
1ceb70f8 | 2747 | { PREFIX_TABLE (PREFIX_0FD0) }, |
ce518a5f L |
2748 | { "psrlw", { MX, EM } }, |
2749 | { "psrld", { MX, EM } }, | |
2750 | { "psrlq", { MX, EM } }, | |
2751 | { "paddq", { MX, EM } }, | |
2752 | { "pmullw", { MX, EM } }, | |
1ceb70f8 | 2753 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 2754 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 2755 | /* d8 */ |
ce518a5f L |
2756 | { "psubusb", { MX, EM } }, |
2757 | { "psubusw", { MX, EM } }, | |
2758 | { "pminub", { MX, EM } }, | |
2759 | { "pand", { MX, EM } }, | |
2760 | { "paddusb", { MX, EM } }, | |
2761 | { "paddusw", { MX, EM } }, | |
2762 | { "pmaxub", { MX, EM } }, | |
2763 | { "pandn", { MX, EM } }, | |
252b5132 | 2764 | /* e0 */ |
ce518a5f L |
2765 | { "pavgb", { MX, EM } }, |
2766 | { "psraw", { MX, EM } }, | |
2767 | { "psrad", { MX, EM } }, | |
2768 | { "pavgw", { MX, EM } }, | |
2769 | { "pmulhuw", { MX, EM } }, | |
2770 | { "pmulhw", { MX, EM } }, | |
1ceb70f8 L |
2771 | { PREFIX_TABLE (PREFIX_0FE6) }, |
2772 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 2773 | /* e8 */ |
ce518a5f L |
2774 | { "psubsb", { MX, EM } }, |
2775 | { "psubsw", { MX, EM } }, | |
2776 | { "pminsw", { MX, EM } }, | |
2777 | { "por", { MX, EM } }, | |
2778 | { "paddsb", { MX, EM } }, | |
2779 | { "paddsw", { MX, EM } }, | |
2780 | { "pmaxsw", { MX, EM } }, | |
2781 | { "pxor", { MX, EM } }, | |
252b5132 | 2782 | /* f0 */ |
1ceb70f8 | 2783 | { PREFIX_TABLE (PREFIX_0FF0) }, |
ce518a5f L |
2784 | { "psllw", { MX, EM } }, |
2785 | { "pslld", { MX, EM } }, | |
2786 | { "psllq", { MX, EM } }, | |
2787 | { "pmuludq", { MX, EM } }, | |
2788 | { "pmaddwd", { MX, EM } }, | |
2789 | { "psadbw", { MX, EM } }, | |
1ceb70f8 | 2790 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 2791 | /* f8 */ |
ce518a5f L |
2792 | { "psubb", { MX, EM } }, |
2793 | { "psubw", { MX, EM } }, | |
2794 | { "psubd", { MX, EM } }, | |
2795 | { "psubq", { MX, EM } }, | |
2796 | { "paddb", { MX, EM } }, | |
2797 | { "paddw", { MX, EM } }, | |
2798 | { "paddd", { MX, EM } }, | |
592d1631 | 2799 | { Bad_Opcode }, |
252b5132 RH |
2800 | }; |
2801 | ||
2802 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
2803 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2804 | /* ------------------------------- */ | |
2805 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
2806 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
2807 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
2808 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
2809 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
2810 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
2811 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
2812 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
2813 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
2814 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
2815 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
2816 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
2817 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
2818 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
2819 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
2820 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
2821 | /* ------------------------------- */ | |
2822 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
2823 | }; |
2824 | ||
2825 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
2826 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2827 | /* ------------------------------- */ | |
252b5132 | 2828 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 2829 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 2830 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 2831 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 2832 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
2833 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
2834 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 2835 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
2836 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
2837 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 2838 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
050dfa73 | 2839 | /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ |
252b5132 | 2840 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 2841 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 2842 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
ca164297 | 2843 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ |
c608c12e AM |
2844 | /* ------------------------------- */ |
2845 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
2846 | }; | |
2847 | ||
252b5132 RH |
2848 | static char obuf[100]; |
2849 | static char *obufp; | |
ea397f5b | 2850 | static char *mnemonicendp; |
252b5132 RH |
2851 | static char scratchbuf[100]; |
2852 | static unsigned char *start_codep; | |
2853 | static unsigned char *insn_codep; | |
2854 | static unsigned char *codep; | |
f16cd0d5 L |
2855 | static int last_lock_prefix; |
2856 | static int last_repz_prefix; | |
2857 | static int last_repnz_prefix; | |
2858 | static int last_data_prefix; | |
2859 | static int last_addr_prefix; | |
2860 | static int last_rex_prefix; | |
2861 | static int last_seg_prefix; | |
2862 | #define MAX_CODE_LENGTH 15 | |
2863 | /* We can up to 14 prefixes since the maximum instruction length is | |
2864 | 15bytes. */ | |
2865 | static int all_prefixes[MAX_CODE_LENGTH - 1]; | |
252b5132 | 2866 | static disassemble_info *the_info; |
7967e09e L |
2867 | static struct |
2868 | { | |
2869 | int mod; | |
7967e09e | 2870 | int reg; |
484c222e | 2871 | int rm; |
7967e09e L |
2872 | } |
2873 | modrm; | |
4bba6815 | 2874 | static unsigned char need_modrm; |
dfc8cf43 L |
2875 | static struct |
2876 | { | |
2877 | int scale; | |
2878 | int index; | |
2879 | int base; | |
2880 | } | |
2881 | sib; | |
c0f3af97 L |
2882 | static struct |
2883 | { | |
2884 | int register_specifier; | |
2885 | int length; | |
2886 | int prefix; | |
2887 | int w; | |
43234a1e L |
2888 | int evex; |
2889 | int r; | |
2890 | int v; | |
2891 | int mask_register_specifier; | |
2892 | int zeroing; | |
2893 | int ll; | |
2894 | int b; | |
c0f3af97 L |
2895 | } |
2896 | vex; | |
2897 | static unsigned char need_vex; | |
2898 | static unsigned char need_vex_reg; | |
dae39acc | 2899 | static unsigned char vex_w_done; |
252b5132 | 2900 | |
ea397f5b L |
2901 | struct op |
2902 | { | |
2903 | const char *name; | |
2904 | unsigned int len; | |
2905 | }; | |
2906 | ||
4bba6815 AM |
2907 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
2908 | values are stale. Hitting this abort likely indicates that you | |
2909 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
2910 | #define MODRM_CHECK if (!need_modrm) abort () | |
2911 | ||
d708bcba AM |
2912 | static const char **names64; |
2913 | static const char **names32; | |
2914 | static const char **names16; | |
2915 | static const char **names8; | |
2916 | static const char **names8rex; | |
2917 | static const char **names_seg; | |
db51cc60 L |
2918 | static const char *index64; |
2919 | static const char *index32; | |
d708bcba | 2920 | static const char **index16; |
7e8b059b | 2921 | static const char **names_bnd; |
d708bcba AM |
2922 | |
2923 | static const char *intel_names64[] = { | |
2924 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
2925 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
2926 | }; | |
2927 | static const char *intel_names32[] = { | |
2928 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
2929 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
2930 | }; | |
2931 | static const char *intel_names16[] = { | |
2932 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
2933 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
2934 | }; | |
2935 | static const char *intel_names8[] = { | |
2936 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
2937 | }; | |
2938 | static const char *intel_names8rex[] = { | |
2939 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
2940 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
2941 | }; | |
2942 | static const char *intel_names_seg[] = { | |
2943 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
2944 | }; | |
db51cc60 L |
2945 | static const char *intel_index64 = "riz"; |
2946 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
2947 | static const char *intel_index16[] = { |
2948 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
2949 | }; | |
2950 | ||
2951 | static const char *att_names64[] = { | |
2952 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
2953 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
2954 | }; | |
d708bcba AM |
2955 | static const char *att_names32[] = { |
2956 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 2957 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 2958 | }; |
d708bcba AM |
2959 | static const char *att_names16[] = { |
2960 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 2961 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 2962 | }; |
d708bcba AM |
2963 | static const char *att_names8[] = { |
2964 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 2965 | }; |
d708bcba AM |
2966 | static const char *att_names8rex[] = { |
2967 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
2968 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
2969 | }; | |
d708bcba AM |
2970 | static const char *att_names_seg[] = { |
2971 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 2972 | }; |
db51cc60 L |
2973 | static const char *att_index64 = "%riz"; |
2974 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
2975 | static const char *att_index16[] = { |
2976 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
2977 | }; |
2978 | ||
b9733481 L |
2979 | static const char **names_mm; |
2980 | static const char *intel_names_mm[] = { | |
2981 | "mm0", "mm1", "mm2", "mm3", | |
2982 | "mm4", "mm5", "mm6", "mm7" | |
2983 | }; | |
2984 | static const char *att_names_mm[] = { | |
2985 | "%mm0", "%mm1", "%mm2", "%mm3", | |
2986 | "%mm4", "%mm5", "%mm6", "%mm7" | |
2987 | }; | |
2988 | ||
7e8b059b L |
2989 | static const char *intel_names_bnd[] = { |
2990 | "bnd0", "bnd1", "bnd2", "bnd3" | |
2991 | }; | |
2992 | ||
2993 | static const char *att_names_bnd[] = { | |
2994 | "%bnd0", "%bnd1", "%bnd2", "%bnd3" | |
2995 | }; | |
2996 | ||
b9733481 L |
2997 | static const char **names_xmm; |
2998 | static const char *intel_names_xmm[] = { | |
2999 | "xmm0", "xmm1", "xmm2", "xmm3", | |
3000 | "xmm4", "xmm5", "xmm6", "xmm7", | |
3001 | "xmm8", "xmm9", "xmm10", "xmm11", | |
43234a1e L |
3002 | "xmm12", "xmm13", "xmm14", "xmm15", |
3003 | "xmm16", "xmm17", "xmm18", "xmm19", | |
3004 | "xmm20", "xmm21", "xmm22", "xmm23", | |
3005 | "xmm24", "xmm25", "xmm26", "xmm27", | |
3006 | "xmm28", "xmm29", "xmm30", "xmm31" | |
b9733481 L |
3007 | }; |
3008 | static const char *att_names_xmm[] = { | |
3009 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", | |
3010 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", | |
3011 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", | |
43234a1e L |
3012 | "%xmm12", "%xmm13", "%xmm14", "%xmm15", |
3013 | "%xmm16", "%xmm17", "%xmm18", "%xmm19", | |
3014 | "%xmm20", "%xmm21", "%xmm22", "%xmm23", | |
3015 | "%xmm24", "%xmm25", "%xmm26", "%xmm27", | |
3016 | "%xmm28", "%xmm29", "%xmm30", "%xmm31" | |
b9733481 L |
3017 | }; |
3018 | ||
3019 | static const char **names_ymm; | |
3020 | static const char *intel_names_ymm[] = { | |
3021 | "ymm0", "ymm1", "ymm2", "ymm3", | |
3022 | "ymm4", "ymm5", "ymm6", "ymm7", | |
3023 | "ymm8", "ymm9", "ymm10", "ymm11", | |
43234a1e L |
3024 | "ymm12", "ymm13", "ymm14", "ymm15", |
3025 | "ymm16", "ymm17", "ymm18", "ymm19", | |
3026 | "ymm20", "ymm21", "ymm22", "ymm23", | |
3027 | "ymm24", "ymm25", "ymm26", "ymm27", | |
3028 | "ymm28", "ymm29", "ymm30", "ymm31" | |
b9733481 L |
3029 | }; |
3030 | static const char *att_names_ymm[] = { | |
3031 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", | |
3032 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", | |
3033 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", | |
43234a1e L |
3034 | "%ymm12", "%ymm13", "%ymm14", "%ymm15", |
3035 | "%ymm16", "%ymm17", "%ymm18", "%ymm19", | |
3036 | "%ymm20", "%ymm21", "%ymm22", "%ymm23", | |
3037 | "%ymm24", "%ymm25", "%ymm26", "%ymm27", | |
3038 | "%ymm28", "%ymm29", "%ymm30", "%ymm31" | |
3039 | }; | |
3040 | ||
3041 | static const char **names_zmm; | |
3042 | static const char *intel_names_zmm[] = { | |
3043 | "zmm0", "zmm1", "zmm2", "zmm3", | |
3044 | "zmm4", "zmm5", "zmm6", "zmm7", | |
3045 | "zmm8", "zmm9", "zmm10", "zmm11", | |
3046 | "zmm12", "zmm13", "zmm14", "zmm15", | |
3047 | "zmm16", "zmm17", "zmm18", "zmm19", | |
3048 | "zmm20", "zmm21", "zmm22", "zmm23", | |
3049 | "zmm24", "zmm25", "zmm26", "zmm27", | |
3050 | "zmm28", "zmm29", "zmm30", "zmm31" | |
3051 | }; | |
3052 | static const char *att_names_zmm[] = { | |
3053 | "%zmm0", "%zmm1", "%zmm2", "%zmm3", | |
3054 | "%zmm4", "%zmm5", "%zmm6", "%zmm7", | |
3055 | "%zmm8", "%zmm9", "%zmm10", "%zmm11", | |
3056 | "%zmm12", "%zmm13", "%zmm14", "%zmm15", | |
3057 | "%zmm16", "%zmm17", "%zmm18", "%zmm19", | |
3058 | "%zmm20", "%zmm21", "%zmm22", "%zmm23", | |
3059 | "%zmm24", "%zmm25", "%zmm26", "%zmm27", | |
3060 | "%zmm28", "%zmm29", "%zmm30", "%zmm31" | |
3061 | }; | |
3062 | ||
3063 | static const char **names_mask; | |
3064 | static const char *intel_names_mask[] = { | |
3065 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" | |
3066 | }; | |
3067 | static const char *att_names_mask[] = { | |
3068 | "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" | |
3069 | }; | |
3070 | ||
3071 | static const char *names_rounding[] = | |
3072 | { | |
3073 | "{rn-sae}", | |
3074 | "{rd-sae}", | |
3075 | "{ru-sae}", | |
3076 | "{rz-sae}" | |
b9733481 L |
3077 | }; |
3078 | ||
1ceb70f8 L |
3079 | static const struct dis386 reg_table[][8] = { |
3080 | /* REG_80 */ | |
252b5132 | 3081 | { |
42164a71 L |
3082 | { "addA", { Ebh1, Ib } }, |
3083 | { "orA", { Ebh1, Ib } }, | |
3084 | { "adcA", { Ebh1, Ib } }, | |
3085 | { "sbbA", { Ebh1, Ib } }, | |
3086 | { "andA", { Ebh1, Ib } }, | |
3087 | { "subA", { Ebh1, Ib } }, | |
3088 | { "xorA", { Ebh1, Ib } }, | |
ce518a5f | 3089 | { "cmpA", { Eb, Ib } }, |
252b5132 | 3090 | }, |
1ceb70f8 | 3091 | /* REG_81 */ |
252b5132 | 3092 | { |
42164a71 L |
3093 | { "addQ", { Evh1, Iv } }, |
3094 | { "orQ", { Evh1, Iv } }, | |
3095 | { "adcQ", { Evh1, Iv } }, | |
3096 | { "sbbQ", { Evh1, Iv } }, | |
3097 | { "andQ", { Evh1, Iv } }, | |
3098 | { "subQ", { Evh1, Iv } }, | |
3099 | { "xorQ", { Evh1, Iv } }, | |
ce518a5f | 3100 | { "cmpQ", { Ev, Iv } }, |
252b5132 | 3101 | }, |
1ceb70f8 | 3102 | /* REG_82 */ |
252b5132 | 3103 | { |
42164a71 L |
3104 | { "addQ", { Evh1, sIb } }, |
3105 | { "orQ", { Evh1, sIb } }, | |
3106 | { "adcQ", { Evh1, sIb } }, | |
3107 | { "sbbQ", { Evh1, sIb } }, | |
3108 | { "andQ", { Evh1, sIb } }, | |
3109 | { "subQ", { Evh1, sIb } }, | |
3110 | { "xorQ", { Evh1, sIb } }, | |
ce518a5f | 3111 | { "cmpQ", { Ev, sIb } }, |
252b5132 | 3112 | }, |
1ceb70f8 | 3113 | /* REG_8F */ |
4e7d34a6 L |
3114 | { |
3115 | { "popU", { stackEv } }, | |
c48244a5 | 3116 | { XOP_8F_TABLE (XOP_09) }, |
592d1631 L |
3117 | { Bad_Opcode }, |
3118 | { Bad_Opcode }, | |
3119 | { Bad_Opcode }, | |
f88c9eb0 | 3120 | { XOP_8F_TABLE (XOP_09) }, |
4e7d34a6 | 3121 | }, |
1ceb70f8 | 3122 | /* REG_C0 */ |
252b5132 | 3123 | { |
ce518a5f L |
3124 | { "rolA", { Eb, Ib } }, |
3125 | { "rorA", { Eb, Ib } }, | |
3126 | { "rclA", { Eb, Ib } }, | |
3127 | { "rcrA", { Eb, Ib } }, | |
3128 | { "shlA", { Eb, Ib } }, | |
3129 | { "shrA", { Eb, Ib } }, | |
592d1631 | 3130 | { Bad_Opcode }, |
ce518a5f | 3131 | { "sarA", { Eb, Ib } }, |
252b5132 | 3132 | }, |
1ceb70f8 | 3133 | /* REG_C1 */ |
252b5132 | 3134 | { |
ce518a5f L |
3135 | { "rolQ", { Ev, Ib } }, |
3136 | { "rorQ", { Ev, Ib } }, | |
3137 | { "rclQ", { Ev, Ib } }, | |
3138 | { "rcrQ", { Ev, Ib } }, | |
3139 | { "shlQ", { Ev, Ib } }, | |
3140 | { "shrQ", { Ev, Ib } }, | |
592d1631 | 3141 | { Bad_Opcode }, |
ce518a5f | 3142 | { "sarQ", { Ev, Ib } }, |
252b5132 | 3143 | }, |
1ceb70f8 | 3144 | /* REG_C6 */ |
4e7d34a6 | 3145 | { |
42164a71 L |
3146 | { "movA", { Ebh3, Ib } }, |
3147 | { Bad_Opcode }, | |
3148 | { Bad_Opcode }, | |
3149 | { Bad_Opcode }, | |
3150 | { Bad_Opcode }, | |
3151 | { Bad_Opcode }, | |
3152 | { Bad_Opcode }, | |
3153 | { MOD_TABLE (MOD_C6_REG_7) }, | |
4e7d34a6 | 3154 | }, |
1ceb70f8 | 3155 | /* REG_C7 */ |
4e7d34a6 | 3156 | { |
42164a71 L |
3157 | { "movQ", { Evh3, Iv } }, |
3158 | { Bad_Opcode }, | |
3159 | { Bad_Opcode }, | |
3160 | { Bad_Opcode }, | |
3161 | { Bad_Opcode }, | |
3162 | { Bad_Opcode }, | |
3163 | { Bad_Opcode }, | |
3164 | { MOD_TABLE (MOD_C7_REG_7) }, | |
4e7d34a6 | 3165 | }, |
1ceb70f8 | 3166 | /* REG_D0 */ |
252b5132 | 3167 | { |
ce518a5f L |
3168 | { "rolA", { Eb, I1 } }, |
3169 | { "rorA", { Eb, I1 } }, | |
3170 | { "rclA", { Eb, I1 } }, | |
3171 | { "rcrA", { Eb, I1 } }, | |
3172 | { "shlA", { Eb, I1 } }, | |
3173 | { "shrA", { Eb, I1 } }, | |
592d1631 | 3174 | { Bad_Opcode }, |
ce518a5f | 3175 | { "sarA", { Eb, I1 } }, |
252b5132 | 3176 | }, |
1ceb70f8 | 3177 | /* REG_D1 */ |
252b5132 | 3178 | { |
ce518a5f L |
3179 | { "rolQ", { Ev, I1 } }, |
3180 | { "rorQ", { Ev, I1 } }, | |
3181 | { "rclQ", { Ev, I1 } }, | |
3182 | { "rcrQ", { Ev, I1 } }, | |
3183 | { "shlQ", { Ev, I1 } }, | |
3184 | { "shrQ", { Ev, I1 } }, | |
592d1631 | 3185 | { Bad_Opcode }, |
ce518a5f | 3186 | { "sarQ", { Ev, I1 } }, |
252b5132 | 3187 | }, |
1ceb70f8 | 3188 | /* REG_D2 */ |
252b5132 | 3189 | { |
ce518a5f L |
3190 | { "rolA", { Eb, CL } }, |
3191 | { "rorA", { Eb, CL } }, | |
3192 | { "rclA", { Eb, CL } }, | |
3193 | { "rcrA", { Eb, CL } }, | |
3194 | { "shlA", { Eb, CL } }, | |
3195 | { "shrA", { Eb, CL } }, | |
592d1631 | 3196 | { Bad_Opcode }, |
ce518a5f | 3197 | { "sarA", { Eb, CL } }, |
252b5132 | 3198 | }, |
1ceb70f8 | 3199 | /* REG_D3 */ |
252b5132 | 3200 | { |
ce518a5f L |
3201 | { "rolQ", { Ev, CL } }, |
3202 | { "rorQ", { Ev, CL } }, | |
3203 | { "rclQ", { Ev, CL } }, | |
3204 | { "rcrQ", { Ev, CL } }, | |
3205 | { "shlQ", { Ev, CL } }, | |
3206 | { "shrQ", { Ev, CL } }, | |
592d1631 | 3207 | { Bad_Opcode }, |
ce518a5f | 3208 | { "sarQ", { Ev, CL } }, |
252b5132 | 3209 | }, |
1ceb70f8 | 3210 | /* REG_F6 */ |
252b5132 | 3211 | { |
ce518a5f | 3212 | { "testA", { Eb, Ib } }, |
592d1631 | 3213 | { Bad_Opcode }, |
42164a71 L |
3214 | { "notA", { Ebh1 } }, |
3215 | { "negA", { Ebh1 } }, | |
ce518a5f L |
3216 | { "mulA", { Eb } }, /* Don't print the implicit %al register, */ |
3217 | { "imulA", { Eb } }, /* to distinguish these opcodes from other */ | |
3218 | { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */ | |
3219 | { "idivA", { Eb } }, /* and idiv for consistency. */ | |
252b5132 | 3220 | }, |
1ceb70f8 | 3221 | /* REG_F7 */ |
252b5132 | 3222 | { |
ce518a5f | 3223 | { "testQ", { Ev, Iv } }, |
592d1631 | 3224 | { Bad_Opcode }, |
42164a71 L |
3225 | { "notQ", { Evh1 } }, |
3226 | { "negQ", { Evh1 } }, | |
ce518a5f L |
3227 | { "mulQ", { Ev } }, /* Don't print the implicit register. */ |
3228 | { "imulQ", { Ev } }, | |
3229 | { "divQ", { Ev } }, | |
3230 | { "idivQ", { Ev } }, | |
252b5132 | 3231 | }, |
1ceb70f8 | 3232 | /* REG_FE */ |
252b5132 | 3233 | { |
42164a71 L |
3234 | { "incA", { Ebh1 } }, |
3235 | { "decA", { Ebh1 } }, | |
252b5132 | 3236 | }, |
1ceb70f8 | 3237 | /* REG_FF */ |
252b5132 | 3238 | { |
42164a71 L |
3239 | { "incQ", { Evh1 } }, |
3240 | { "decQ", { Evh1 } }, | |
7e8b059b | 3241 | { "call{T|}", { indirEv, BND } }, |
4a357820 | 3242 | { MOD_TABLE (MOD_FF_REG_3) }, |
7e8b059b | 3243 | { "jmp{T|}", { indirEv, BND } }, |
4a357820 | 3244 | { MOD_TABLE (MOD_FF_REG_5) }, |
ce518a5f | 3245 | { "pushU", { stackEv } }, |
592d1631 | 3246 | { Bad_Opcode }, |
252b5132 | 3247 | }, |
1ceb70f8 | 3248 | /* REG_0F00 */ |
252b5132 | 3249 | { |
ce518a5f L |
3250 | { "sldtD", { Sv } }, |
3251 | { "strD", { Sv } }, | |
3252 | { "lldt", { Ew } }, | |
3253 | { "ltr", { Ew } }, | |
3254 | { "verr", { Ew } }, | |
3255 | { "verw", { Ew } }, | |
592d1631 L |
3256 | { Bad_Opcode }, |
3257 | { Bad_Opcode }, | |
252b5132 | 3258 | }, |
1ceb70f8 | 3259 | /* REG_0F01 */ |
252b5132 | 3260 | { |
1ceb70f8 L |
3261 | { MOD_TABLE (MOD_0F01_REG_0) }, |
3262 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
3263 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
3264 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
ce518a5f | 3265 | { "smswD", { Sv } }, |
592d1631 | 3266 | { Bad_Opcode }, |
ce518a5f | 3267 | { "lmsw", { Ew } }, |
1ceb70f8 | 3268 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 3269 | }, |
b5b1fc4f | 3270 | /* REG_0F0D */ |
252b5132 | 3271 | { |
1ab03f4b L |
3272 | { "prefetch", { Mb } }, |
3273 | { "prefetchw", { Mb } }, | |
43234a1e | 3274 | { "prefetchwt1", { Mb } }, |
d7189fa5 RM |
3275 | { "prefetch", { Mb } }, |
3276 | { "prefetch", { Mb } }, | |
3277 | { "prefetch", { Mb } }, | |
3278 | { "prefetch", { Mb } }, | |
3279 | { "prefetch", { Mb } }, | |
252b5132 | 3280 | }, |
1ceb70f8 | 3281 | /* REG_0F18 */ |
252b5132 | 3282 | { |
1ceb70f8 L |
3283 | { MOD_TABLE (MOD_0F18_REG_0) }, |
3284 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
3285 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
3286 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
d7189fa5 RM |
3287 | { MOD_TABLE (MOD_0F18_REG_4) }, |
3288 | { MOD_TABLE (MOD_0F18_REG_5) }, | |
3289 | { MOD_TABLE (MOD_0F18_REG_6) }, | |
3290 | { MOD_TABLE (MOD_0F18_REG_7) }, | |
252b5132 | 3291 | }, |
1ceb70f8 | 3292 | /* REG_0F71 */ |
a6bd098c | 3293 | { |
592d1631 L |
3294 | { Bad_Opcode }, |
3295 | { Bad_Opcode }, | |
1ceb70f8 | 3296 | { MOD_TABLE (MOD_0F71_REG_2) }, |
592d1631 | 3297 | { Bad_Opcode }, |
1ceb70f8 | 3298 | { MOD_TABLE (MOD_0F71_REG_4) }, |
592d1631 | 3299 | { Bad_Opcode }, |
1ceb70f8 | 3300 | { MOD_TABLE (MOD_0F71_REG_6) }, |
a6bd098c | 3301 | }, |
1ceb70f8 | 3302 | /* REG_0F72 */ |
a6bd098c | 3303 | { |
592d1631 L |
3304 | { Bad_Opcode }, |
3305 | { Bad_Opcode }, | |
1ceb70f8 | 3306 | { MOD_TABLE (MOD_0F72_REG_2) }, |
592d1631 | 3307 | { Bad_Opcode }, |
1ceb70f8 | 3308 | { MOD_TABLE (MOD_0F72_REG_4) }, |
592d1631 | 3309 | { Bad_Opcode }, |
1ceb70f8 | 3310 | { MOD_TABLE (MOD_0F72_REG_6) }, |
a6bd098c | 3311 | }, |
1ceb70f8 | 3312 | /* REG_0F73 */ |
252b5132 | 3313 | { |
592d1631 L |
3314 | { Bad_Opcode }, |
3315 | { Bad_Opcode }, | |
1ceb70f8 L |
3316 | { MOD_TABLE (MOD_0F73_REG_2) }, |
3317 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
592d1631 L |
3318 | { Bad_Opcode }, |
3319 | { Bad_Opcode }, | |
1ceb70f8 L |
3320 | { MOD_TABLE (MOD_0F73_REG_6) }, |
3321 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 3322 | }, |
1ceb70f8 | 3323 | /* REG_0FA6 */ |
252b5132 | 3324 | { |
4e7d34a6 L |
3325 | { "montmul", { { OP_0f07, 0 } } }, |
3326 | { "xsha1", { { OP_0f07, 0 } } }, | |
3327 | { "xsha256", { { OP_0f07, 0 } } }, | |
4e7d34a6 | 3328 | }, |
1ceb70f8 | 3329 | /* REG_0FA7 */ |
4e7d34a6 L |
3330 | { |
3331 | { "xstore-rng", { { OP_0f07, 0 } } }, | |
3332 | { "xcrypt-ecb", { { OP_0f07, 0 } } }, | |
3333 | { "xcrypt-cbc", { { OP_0f07, 0 } } }, | |
3334 | { "xcrypt-ctr", { { OP_0f07, 0 } } }, | |
3335 | { "xcrypt-cfb", { { OP_0f07, 0 } } }, | |
3336 | { "xcrypt-ofb", { { OP_0f07, 0 } } }, | |
4e7d34a6 | 3337 | }, |
1ceb70f8 | 3338 | /* REG_0FAE */ |
4e7d34a6 | 3339 | { |
1ceb70f8 L |
3340 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
3341 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
3342 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
3343 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 3344 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
3345 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
3346 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
3347 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 3348 | }, |
1ceb70f8 | 3349 | /* REG_0FBA */ |
252b5132 | 3350 | { |
592d1631 L |
3351 | { Bad_Opcode }, |
3352 | { Bad_Opcode }, | |
3353 | { Bad_Opcode }, | |
3354 | { Bad_Opcode }, | |
4e7d34a6 | 3355 | { "btQ", { Ev, Ib } }, |
42164a71 L |
3356 | { "btsQ", { Evh1, Ib } }, |
3357 | { "btrQ", { Evh1, Ib } }, | |
3358 | { "btcQ", { Evh1, Ib } }, | |
c608c12e | 3359 | }, |
1ceb70f8 | 3360 | /* REG_0FC7 */ |
c608c12e | 3361 | { |
592d1631 | 3362 | { Bad_Opcode }, |
4e7d34a6 | 3363 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } }, |
592d1631 | 3364 | { Bad_Opcode }, |
963f3586 IT |
3365 | { MOD_TABLE (MOD_0FC7_REG_3) }, |
3366 | { MOD_TABLE (MOD_0FC7_REG_4) }, | |
3367 | { MOD_TABLE (MOD_0FC7_REG_5) }, | |
1ceb70f8 L |
3368 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
3369 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 3370 | }, |
592a252b | 3371 | /* REG_VEX_0F71 */ |
c0f3af97 | 3372 | { |
592d1631 L |
3373 | { Bad_Opcode }, |
3374 | { Bad_Opcode }, | |
592a252b | 3375 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
592d1631 | 3376 | { Bad_Opcode }, |
592a252b | 3377 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
592d1631 | 3378 | { Bad_Opcode }, |
592a252b | 3379 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
c0f3af97 | 3380 | }, |
592a252b | 3381 | /* REG_VEX_0F72 */ |
c0f3af97 | 3382 | { |
592d1631 L |
3383 | { Bad_Opcode }, |
3384 | { Bad_Opcode }, | |
592a252b | 3385 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
592d1631 | 3386 | { Bad_Opcode }, |
592a252b | 3387 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
592d1631 | 3388 | { Bad_Opcode }, |
592a252b | 3389 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
c0f3af97 | 3390 | }, |
592a252b | 3391 | /* REG_VEX_0F73 */ |
c0f3af97 | 3392 | { |
592d1631 L |
3393 | { Bad_Opcode }, |
3394 | { Bad_Opcode }, | |
592a252b L |
3395 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
3396 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, | |
592d1631 L |
3397 | { Bad_Opcode }, |
3398 | { Bad_Opcode }, | |
592a252b L |
3399 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
3400 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, | |
c0f3af97 | 3401 | }, |
592a252b | 3402 | /* REG_VEX_0FAE */ |
c0f3af97 | 3403 | { |
592d1631 L |
3404 | { Bad_Opcode }, |
3405 | { Bad_Opcode }, | |
592a252b L |
3406 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
3407 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, | |
c0f3af97 | 3408 | }, |
f12dc422 L |
3409 | /* REG_VEX_0F38F3 */ |
3410 | { | |
3411 | { Bad_Opcode }, | |
3412 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, | |
3413 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, | |
3414 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, | |
3415 | }, | |
f88c9eb0 SP |
3416 | /* REG_XOP_LWPCB */ |
3417 | { | |
3418 | { "llwpcb", { { OP_LWPCB_E, 0 } } }, | |
3419 | { "slwpcb", { { OP_LWPCB_E, 0 } } }, | |
f88c9eb0 SP |
3420 | }, |
3421 | /* REG_XOP_LWP */ | |
3422 | { | |
ce7d077e SP |
3423 | { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } }, |
3424 | { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } }, | |
f88c9eb0 | 3425 | }, |
2a2a0f38 QN |
3426 | /* REG_XOP_TBM_01 */ |
3427 | { | |
3428 | { Bad_Opcode }, | |
3429 | { "blcfill", { { OP_LWP_E, 0 }, Ev } }, | |
3430 | { "blsfill", { { OP_LWP_E, 0 }, Ev } }, | |
3431 | { "blcs", { { OP_LWP_E, 0 }, Ev } }, | |
3432 | { "tzmsk", { { OP_LWP_E, 0 }, Ev } }, | |
3433 | { "blcic", { { OP_LWP_E, 0 }, Ev } }, | |
3434 | { "blsic", { { OP_LWP_E, 0 }, Ev } }, | |
3435 | { "t1mskc", { { OP_LWP_E, 0 }, Ev } }, | |
3436 | }, | |
3437 | /* REG_XOP_TBM_02 */ | |
3438 | { | |
3439 | { Bad_Opcode }, | |
3440 | { "blcmsk", { { OP_LWP_E, 0 }, Ev } }, | |
3441 | { Bad_Opcode }, | |
3442 | { Bad_Opcode }, | |
3443 | { Bad_Opcode }, | |
3444 | { Bad_Opcode }, | |
3445 | { "blci", { { OP_LWP_E, 0 }, Ev } }, | |
3446 | }, | |
43234a1e L |
3447 | #define NEED_REG_TABLE |
3448 | #include "i386-dis-evex.h" | |
3449 | #undef NEED_REG_TABLE | |
4e7d34a6 L |
3450 | }; |
3451 | ||
1ceb70f8 L |
3452 | static const struct dis386 prefix_table[][4] = { |
3453 | /* PREFIX_90 */ | |
252b5132 | 3454 | { |
4e7d34a6 L |
3455 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, |
3456 | { "pause", { XX } }, | |
3457 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, | |
0f10071e | 3458 | }, |
4e7d34a6 | 3459 | |
1ceb70f8 | 3460 | /* PREFIX_0F10 */ |
cc0ec051 | 3461 | { |
4e7d34a6 L |
3462 | { "movups", { XM, EXx } }, |
3463 | { "movss", { XM, EXd } }, | |
3464 | { "movupd", { XM, EXx } }, | |
3465 | { "movsd", { XM, EXq } }, | |
30d1c836 | 3466 | }, |
4e7d34a6 | 3467 | |
1ceb70f8 | 3468 | /* PREFIX_0F11 */ |
30d1c836 | 3469 | { |
b6169b20 | 3470 | { "movups", { EXxS, XM } }, |
fa99fab2 | 3471 | { "movss", { EXdS, XM } }, |
b6169b20 | 3472 | { "movupd", { EXxS, XM } }, |
fa99fab2 | 3473 | { "movsd", { EXqS, XM } }, |
4e7d34a6 | 3474 | }, |
252b5132 | 3475 | |
1ceb70f8 | 3476 | /* PREFIX_0F12 */ |
c608c12e | 3477 | { |
1ceb70f8 | 3478 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
4e7d34a6 L |
3479 | { "movsldup", { XM, EXx } }, |
3480 | { "movlpd", { XM, EXq } }, | |
3481 | { "movddup", { XM, EXq } }, | |
c608c12e | 3482 | }, |
4e7d34a6 | 3483 | |
1ceb70f8 | 3484 | /* PREFIX_0F16 */ |
c608c12e | 3485 | { |
1ceb70f8 | 3486 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
4e7d34a6 L |
3487 | { "movshdup", { XM, EXx } }, |
3488 | { "movhpd", { XM, EXq } }, | |
c608c12e | 3489 | }, |
4e7d34a6 | 3490 | |
7e8b059b L |
3491 | /* PREFIX_0F1A */ |
3492 | { | |
3493 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, | |
3494 | { "bndcl", { Gbnd, Ev_bnd } }, | |
3495 | { "bndmov", { Gbnd, Ebnd } }, | |
3496 | { "bndcu", { Gbnd, Ev_bnd } }, | |
3497 | }, | |
3498 | ||
3499 | /* PREFIX_0F1B */ | |
3500 | { | |
3501 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, | |
3502 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, | |
3503 | { "bndmov", { Ebnd, Gbnd } }, | |
3504 | { "bndcn", { Gbnd, Ev_bnd } }, | |
3505 | }, | |
3506 | ||
1ceb70f8 | 3507 | /* PREFIX_0F2A */ |
c608c12e | 3508 | { |
09335d05 | 3509 | { "cvtpi2ps", { XM, EMCq } }, |
98b528ac | 3510 | { "cvtsi2ss%LQ", { XM, Ev } }, |
09335d05 | 3511 | { "cvtpi2pd", { XM, EMCq } }, |
98b528ac | 3512 | { "cvtsi2sd%LQ", { XM, Ev } }, |
c608c12e | 3513 | }, |
4e7d34a6 | 3514 | |
1ceb70f8 | 3515 | /* PREFIX_0F2B */ |
c608c12e | 3516 | { |
75c135a8 L |
3517 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
3518 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
3519 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
3520 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 3521 | }, |
4e7d34a6 | 3522 | |
1ceb70f8 | 3523 | /* PREFIX_0F2C */ |
c608c12e | 3524 | { |
09335d05 L |
3525 | { "cvttps2pi", { MXC, EXq } }, |
3526 | { "cvttss2siY", { Gv, EXd } }, | |
09a2c6cf | 3527 | { "cvttpd2pi", { MXC, EXx } }, |
09335d05 | 3528 | { "cvttsd2siY", { Gv, EXq } }, |
c608c12e | 3529 | }, |
4e7d34a6 | 3530 | |
1ceb70f8 | 3531 | /* PREFIX_0F2D */ |
c608c12e | 3532 | { |
4e7d34a6 L |
3533 | { "cvtps2pi", { MXC, EXq } }, |
3534 | { "cvtss2siY", { Gv, EXd } }, | |
3535 | { "cvtpd2pi", { MXC, EXx } }, | |
3536 | { "cvtsd2siY", { Gv, EXq } }, | |
c608c12e | 3537 | }, |
4e7d34a6 | 3538 | |
1ceb70f8 | 3539 | /* PREFIX_0F2E */ |
c608c12e | 3540 | { |
7bb15c6f | 3541 | { "ucomiss",{ XM, EXd } }, |
592d1631 | 3542 | { Bad_Opcode }, |
7bb15c6f | 3543 | { "ucomisd",{ XM, EXq } }, |
c608c12e | 3544 | }, |
4e7d34a6 | 3545 | |
1ceb70f8 | 3546 | /* PREFIX_0F2F */ |
c608c12e | 3547 | { |
4e7d34a6 | 3548 | { "comiss", { XM, EXd } }, |
592d1631 | 3549 | { Bad_Opcode }, |
4e7d34a6 | 3550 | { "comisd", { XM, EXq } }, |
c608c12e | 3551 | }, |
4e7d34a6 | 3552 | |
1ceb70f8 | 3553 | /* PREFIX_0F51 */ |
c608c12e | 3554 | { |
4e7d34a6 L |
3555 | { "sqrtps", { XM, EXx } }, |
3556 | { "sqrtss", { XM, EXd } }, | |
3557 | { "sqrtpd", { XM, EXx } }, | |
3558 | { "sqrtsd", { XM, EXq } }, | |
c608c12e | 3559 | }, |
4e7d34a6 | 3560 | |
1ceb70f8 | 3561 | /* PREFIX_0F52 */ |
c608c12e | 3562 | { |
4e7d34a6 L |
3563 | { "rsqrtps",{ XM, EXx } }, |
3564 | { "rsqrtss",{ XM, EXd } }, | |
c608c12e | 3565 | }, |
4e7d34a6 | 3566 | |
1ceb70f8 | 3567 | /* PREFIX_0F53 */ |
c608c12e | 3568 | { |
4e7d34a6 L |
3569 | { "rcpps", { XM, EXx } }, |
3570 | { "rcpss", { XM, EXd } }, | |
c608c12e | 3571 | }, |
4e7d34a6 | 3572 | |
1ceb70f8 | 3573 | /* PREFIX_0F58 */ |
c608c12e | 3574 | { |
4e7d34a6 L |
3575 | { "addps", { XM, EXx } }, |
3576 | { "addss", { XM, EXd } }, | |
3577 | { "addpd", { XM, EXx } }, | |
3578 | { "addsd", { XM, EXq } }, | |
c608c12e | 3579 | }, |
4e7d34a6 | 3580 | |
1ceb70f8 | 3581 | /* PREFIX_0F59 */ |
c608c12e | 3582 | { |
4e7d34a6 L |
3583 | { "mulps", { XM, EXx } }, |
3584 | { "mulss", { XM, EXd } }, | |
3585 | { "mulpd", { XM, EXx } }, | |
3586 | { "mulsd", { XM, EXq } }, | |
041bd2e0 | 3587 | }, |
4e7d34a6 | 3588 | |
1ceb70f8 | 3589 | /* PREFIX_0F5A */ |
041bd2e0 | 3590 | { |
4e7d34a6 L |
3591 | { "cvtps2pd", { XM, EXq } }, |
3592 | { "cvtss2sd", { XM, EXd } }, | |
3593 | { "cvtpd2ps", { XM, EXx } }, | |
3594 | { "cvtsd2ss", { XM, EXq } }, | |
041bd2e0 | 3595 | }, |
4e7d34a6 | 3596 | |
1ceb70f8 | 3597 | /* PREFIX_0F5B */ |
041bd2e0 | 3598 | { |
09a2c6cf L |
3599 | { "cvtdq2ps", { XM, EXx } }, |
3600 | { "cvttps2dq", { XM, EXx } }, | |
3601 | { "cvtps2dq", { XM, EXx } }, | |
041bd2e0 | 3602 | }, |
4e7d34a6 | 3603 | |
1ceb70f8 | 3604 | /* PREFIX_0F5C */ |
041bd2e0 | 3605 | { |
4e7d34a6 L |
3606 | { "subps", { XM, EXx } }, |
3607 | { "subss", { XM, EXd } }, | |
3608 | { "subpd", { XM, EXx } }, | |
3609 | { "subsd", { XM, EXq } }, | |
041bd2e0 | 3610 | }, |
4e7d34a6 | 3611 | |
1ceb70f8 | 3612 | /* PREFIX_0F5D */ |
041bd2e0 | 3613 | { |
4e7d34a6 L |
3614 | { "minps", { XM, EXx } }, |
3615 | { "minss", { XM, EXd } }, | |
3616 | { "minpd", { XM, EXx } }, | |
3617 | { "minsd", { XM, EXq } }, | |
041bd2e0 | 3618 | }, |
4e7d34a6 | 3619 | |
1ceb70f8 | 3620 | /* PREFIX_0F5E */ |
041bd2e0 | 3621 | { |
4e7d34a6 L |
3622 | { "divps", { XM, EXx } }, |
3623 | { "divss", { XM, EXd } }, | |
3624 | { "divpd", { XM, EXx } }, | |
3625 | { "divsd", { XM, EXq } }, | |
041bd2e0 | 3626 | }, |
4e7d34a6 | 3627 | |
1ceb70f8 | 3628 | /* PREFIX_0F5F */ |
041bd2e0 | 3629 | { |
4e7d34a6 L |
3630 | { "maxps", { XM, EXx } }, |
3631 | { "maxss", { XM, EXd } }, | |
3632 | { "maxpd", { XM, EXx } }, | |
3633 | { "maxsd", { XM, EXq } }, | |
041bd2e0 | 3634 | }, |
4e7d34a6 | 3635 | |
1ceb70f8 | 3636 | /* PREFIX_0F60 */ |
041bd2e0 | 3637 | { |
4e7d34a6 | 3638 | { "punpcklbw",{ MX, EMd } }, |
592d1631 | 3639 | { Bad_Opcode }, |
4e7d34a6 | 3640 | { "punpcklbw",{ MX, EMx } }, |
041bd2e0 | 3641 | }, |
4e7d34a6 | 3642 | |
1ceb70f8 | 3643 | /* PREFIX_0F61 */ |
041bd2e0 | 3644 | { |
4e7d34a6 | 3645 | { "punpcklwd",{ MX, EMd } }, |
592d1631 | 3646 | { Bad_Opcode }, |
4e7d34a6 | 3647 | { "punpcklwd",{ MX, EMx } }, |
041bd2e0 | 3648 | }, |
4e7d34a6 | 3649 | |
1ceb70f8 | 3650 | /* PREFIX_0F62 */ |
041bd2e0 | 3651 | { |
4e7d34a6 | 3652 | { "punpckldq",{ MX, EMd } }, |
592d1631 | 3653 | { Bad_Opcode }, |
4e7d34a6 | 3654 | { "punpckldq",{ MX, EMx } }, |
041bd2e0 | 3655 | }, |
4e7d34a6 | 3656 | |
1ceb70f8 | 3657 | /* PREFIX_0F6C */ |
041bd2e0 | 3658 | { |
592d1631 L |
3659 | { Bad_Opcode }, |
3660 | { Bad_Opcode }, | |
4e7d34a6 | 3661 | { "punpcklqdq", { XM, EXx } }, |
0f17484f | 3662 | }, |
4e7d34a6 | 3663 | |
1ceb70f8 | 3664 | /* PREFIX_0F6D */ |
0f17484f | 3665 | { |
592d1631 L |
3666 | { Bad_Opcode }, |
3667 | { Bad_Opcode }, | |
4e7d34a6 | 3668 | { "punpckhqdq", { XM, EXx } }, |
041bd2e0 | 3669 | }, |
4e7d34a6 | 3670 | |
1ceb70f8 | 3671 | /* PREFIX_0F6F */ |
ca164297 | 3672 | { |
4e7d34a6 L |
3673 | { "movq", { MX, EM } }, |
3674 | { "movdqu", { XM, EXx } }, | |
3675 | { "movdqa", { XM, EXx } }, | |
ca164297 | 3676 | }, |
4e7d34a6 | 3677 | |
1ceb70f8 | 3678 | /* PREFIX_0F70 */ |
4e7d34a6 L |
3679 | { |
3680 | { "pshufw", { MX, EM, Ib } }, | |
3681 | { "pshufhw",{ XM, EXx, Ib } }, | |
3682 | { "pshufd", { XM, EXx, Ib } }, | |
3683 | { "pshuflw",{ XM, EXx, Ib } }, | |
3684 | }, | |
3685 | ||
92fddf8e L |
3686 | /* PREFIX_0F73_REG_3 */ |
3687 | { | |
592d1631 L |
3688 | { Bad_Opcode }, |
3689 | { Bad_Opcode }, | |
92fddf8e | 3690 | { "psrldq", { XS, Ib } }, |
92fddf8e L |
3691 | }, |
3692 | ||
3693 | /* PREFIX_0F73_REG_7 */ | |
3694 | { | |
592d1631 L |
3695 | { Bad_Opcode }, |
3696 | { Bad_Opcode }, | |
92fddf8e | 3697 | { "pslldq", { XS, Ib } }, |
92fddf8e L |
3698 | }, |
3699 | ||
1ceb70f8 | 3700 | /* PREFIX_0F78 */ |
4e7d34a6 L |
3701 | { |
3702 | {"vmread", { Em, Gm } }, | |
592d1631 | 3703 | { Bad_Opcode }, |
4e7d34a6 L |
3704 | {"extrq", { XS, Ib, Ib } }, |
3705 | {"insertq", { XM, XS, Ib, Ib } }, | |
3706 | }, | |
3707 | ||
1ceb70f8 | 3708 | /* PREFIX_0F79 */ |
4e7d34a6 L |
3709 | { |
3710 | {"vmwrite", { Gm, Em } }, | |
592d1631 | 3711 | { Bad_Opcode }, |
4e7d34a6 L |
3712 | {"extrq", { XM, XS } }, |
3713 | {"insertq", { XM, XS } }, | |
3714 | }, | |
3715 | ||
1ceb70f8 | 3716 | /* PREFIX_0F7C */ |
ca164297 | 3717 | { |
592d1631 L |
3718 | { Bad_Opcode }, |
3719 | { Bad_Opcode }, | |
09a2c6cf L |
3720 | { "haddpd", { XM, EXx } }, |
3721 | { "haddps", { XM, EXx } }, | |
ca164297 | 3722 | }, |
4e7d34a6 | 3723 | |
1ceb70f8 | 3724 | /* PREFIX_0F7D */ |
ca164297 | 3725 | { |
592d1631 L |
3726 | { Bad_Opcode }, |
3727 | { Bad_Opcode }, | |
09a2c6cf L |
3728 | { "hsubpd", { XM, EXx } }, |
3729 | { "hsubps", { XM, EXx } }, | |
ca164297 | 3730 | }, |
4e7d34a6 | 3731 | |
1ceb70f8 | 3732 | /* PREFIX_0F7E */ |
ca164297 | 3733 | { |
4e7d34a6 L |
3734 | { "movK", { Edq, MX } }, |
3735 | { "movq", { XM, EXq } }, | |
3736 | { "movK", { Edq, XM } }, | |
ca164297 | 3737 | }, |
4e7d34a6 | 3738 | |
1ceb70f8 | 3739 | /* PREFIX_0F7F */ |
ca164297 | 3740 | { |
b6169b20 L |
3741 | { "movq", { EMS, MX } }, |
3742 | { "movdqu", { EXxS, XM } }, | |
3743 | { "movdqa", { EXxS, XM } }, | |
ca164297 | 3744 | }, |
4e7d34a6 | 3745 | |
c7b8aa3a L |
3746 | /* PREFIX_0FAE_REG_0 */ |
3747 | { | |
3748 | { Bad_Opcode }, | |
3749 | { "rdfsbase", { Ev } }, | |
3750 | }, | |
3751 | ||
3752 | /* PREFIX_0FAE_REG_1 */ | |
3753 | { | |
3754 | { Bad_Opcode }, | |
3755 | { "rdgsbase", { Ev } }, | |
3756 | }, | |
3757 | ||
3758 | /* PREFIX_0FAE_REG_2 */ | |
3759 | { | |
3760 | { Bad_Opcode }, | |
3761 | { "wrfsbase", { Ev } }, | |
3762 | }, | |
3763 | ||
3764 | /* PREFIX_0FAE_REG_3 */ | |
3765 | { | |
3766 | { Bad_Opcode }, | |
3767 | { "wrgsbase", { Ev } }, | |
3768 | }, | |
3769 | ||
963f3586 IT |
3770 | /* PREFIX_0FAE_REG_7 */ |
3771 | { | |
3772 | { "clflush", { Mb } }, | |
3773 | { Bad_Opcode }, | |
3774 | { "clflushopt", { Mb } }, | |
3775 | }, | |
3776 | ||
1ceb70f8 | 3777 | /* PREFIX_0FB8 */ |
ca164297 | 3778 | { |
592d1631 | 3779 | { Bad_Opcode }, |
4e7d34a6 | 3780 | { "popcntS", { Gv, Ev } }, |
ca164297 | 3781 | }, |
4e7d34a6 | 3782 | |
f12dc422 L |
3783 | /* PREFIX_0FBC */ |
3784 | { | |
3785 | { "bsfS", { Gv, Ev } }, | |
3786 | { "tzcntS", { Gv, Ev } }, | |
3787 | { "bsfS", { Gv, Ev } }, | |
3788 | }, | |
3789 | ||
1ceb70f8 | 3790 | /* PREFIX_0FBD */ |
050dfa73 | 3791 | { |
4e7d34a6 L |
3792 | { "bsrS", { Gv, Ev } }, |
3793 | { "lzcntS", { Gv, Ev } }, | |
3794 | { "bsrS", { Gv, Ev } }, | |
050dfa73 MM |
3795 | }, |
3796 | ||
1ceb70f8 | 3797 | /* PREFIX_0FC2 */ |
050dfa73 | 3798 | { |
ad19981d L |
3799 | { "cmpps", { XM, EXx, CMP } }, |
3800 | { "cmpss", { XM, EXd, CMP } }, | |
3801 | { "cmppd", { XM, EXx, CMP } }, | |
3802 | { "cmpsd", { XM, EXq, CMP } }, | |
050dfa73 | 3803 | }, |
246c51aa | 3804 | |
4ee52178 L |
3805 | /* PREFIX_0FC3 */ |
3806 | { | |
3807 | { "movntiS", { Ma, Gv } }, | |
4ee52178 L |
3808 | }, |
3809 | ||
92fddf8e L |
3810 | /* PREFIX_0FC7_REG_6 */ |
3811 | { | |
3812 | { "vmptrld",{ Mq } }, | |
3813 | { "vmxon", { Mq } }, | |
3814 | { "vmclear",{ Mq } }, | |
92fddf8e L |
3815 | }, |
3816 | ||
1ceb70f8 | 3817 | /* PREFIX_0FD0 */ |
050dfa73 | 3818 | { |
592d1631 L |
3819 | { Bad_Opcode }, |
3820 | { Bad_Opcode }, | |
4e7d34a6 L |
3821 | { "addsubpd", { XM, EXx } }, |
3822 | { "addsubps", { XM, EXx } }, | |
246c51aa | 3823 | }, |
050dfa73 | 3824 | |
1ceb70f8 | 3825 | /* PREFIX_0FD6 */ |
050dfa73 | 3826 | { |
592d1631 | 3827 | { Bad_Opcode }, |
4e7d34a6 | 3828 | { "movq2dq",{ XM, MS } }, |
b6169b20 | 3829 | { "movq", { EXqS, XM } }, |
4e7d34a6 | 3830 | { "movdq2q",{ MX, XS } }, |
050dfa73 MM |
3831 | }, |
3832 | ||
1ceb70f8 | 3833 | /* PREFIX_0FE6 */ |
7918206c | 3834 | { |
592d1631 | 3835 | { Bad_Opcode }, |
4e7d34a6 L |
3836 | { "cvtdq2pd", { XM, EXq } }, |
3837 | { "cvttpd2dq", { XM, EXx } }, | |
3838 | { "cvtpd2dq", { XM, EXx } }, | |
7918206c | 3839 | }, |
8b38ad71 | 3840 | |
1ceb70f8 | 3841 | /* PREFIX_0FE7 */ |
8b38ad71 | 3842 | { |
4ee52178 | 3843 | { "movntq", { Mq, MX } }, |
592d1631 | 3844 | { Bad_Opcode }, |
75c135a8 | 3845 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
4e7d34a6 L |
3846 | }, |
3847 | ||
1ceb70f8 | 3848 | /* PREFIX_0FF0 */ |
4e7d34a6 | 3849 | { |
592d1631 L |
3850 | { Bad_Opcode }, |
3851 | { Bad_Opcode }, | |
3852 | { Bad_Opcode }, | |
1ceb70f8 | 3853 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
3854 | }, |
3855 | ||
1ceb70f8 | 3856 | /* PREFIX_0FF7 */ |
4e7d34a6 L |
3857 | { |
3858 | { "maskmovq", { MX, MS } }, | |
592d1631 | 3859 | { Bad_Opcode }, |
4e7d34a6 | 3860 | { "maskmovdqu", { XM, XS } }, |
8b38ad71 | 3861 | }, |
42903f7f | 3862 | |
1ceb70f8 | 3863 | /* PREFIX_0F3810 */ |
42903f7f | 3864 | { |
592d1631 L |
3865 | { Bad_Opcode }, |
3866 | { Bad_Opcode }, | |
88a94849 | 3867 | { "pblendvb", { XM, EXx, XMM0 } }, |
42903f7f L |
3868 | }, |
3869 | ||
1ceb70f8 | 3870 | /* PREFIX_0F3814 */ |
42903f7f | 3871 | { |
592d1631 L |
3872 | { Bad_Opcode }, |
3873 | { Bad_Opcode }, | |
88a94849 | 3874 | { "blendvps", { XM, EXx, XMM0 } }, |
42903f7f L |
3875 | }, |
3876 | ||
1ceb70f8 | 3877 | /* PREFIX_0F3815 */ |
42903f7f | 3878 | { |
592d1631 L |
3879 | { Bad_Opcode }, |
3880 | { Bad_Opcode }, | |
09a2c6cf | 3881 | { "blendvpd", { XM, EXx, XMM0 } }, |
42903f7f L |
3882 | }, |
3883 | ||
1ceb70f8 | 3884 | /* PREFIX_0F3817 */ |
42903f7f | 3885 | { |
592d1631 L |
3886 | { Bad_Opcode }, |
3887 | { Bad_Opcode }, | |
09a2c6cf | 3888 | { "ptest", { XM, EXx } }, |
42903f7f L |
3889 | }, |
3890 | ||
1ceb70f8 | 3891 | /* PREFIX_0F3820 */ |
42903f7f | 3892 | { |
592d1631 L |
3893 | { Bad_Opcode }, |
3894 | { Bad_Opcode }, | |
8976381e | 3895 | { "pmovsxbw", { XM, EXq } }, |
42903f7f L |
3896 | }, |
3897 | ||
1ceb70f8 | 3898 | /* PREFIX_0F3821 */ |
42903f7f | 3899 | { |
592d1631 L |
3900 | { Bad_Opcode }, |
3901 | { Bad_Opcode }, | |
8976381e | 3902 | { "pmovsxbd", { XM, EXd } }, |
42903f7f L |
3903 | }, |
3904 | ||
1ceb70f8 | 3905 | /* PREFIX_0F3822 */ |
42903f7f | 3906 | { |
592d1631 L |
3907 | { Bad_Opcode }, |
3908 | { Bad_Opcode }, | |
8976381e | 3909 | { "pmovsxbq", { XM, EXw } }, |
42903f7f L |
3910 | }, |
3911 | ||
1ceb70f8 | 3912 | /* PREFIX_0F3823 */ |
42903f7f | 3913 | { |
592d1631 L |
3914 | { Bad_Opcode }, |
3915 | { Bad_Opcode }, | |
8976381e | 3916 | { "pmovsxwd", { XM, EXq } }, |
42903f7f L |
3917 | }, |
3918 | ||
1ceb70f8 | 3919 | /* PREFIX_0F3824 */ |
42903f7f | 3920 | { |
592d1631 L |
3921 | { Bad_Opcode }, |
3922 | { Bad_Opcode }, | |
8976381e | 3923 | { "pmovsxwq", { XM, EXd } }, |
42903f7f L |
3924 | }, |
3925 | ||
1ceb70f8 | 3926 | /* PREFIX_0F3825 */ |
42903f7f | 3927 | { |
592d1631 L |
3928 | { Bad_Opcode }, |
3929 | { Bad_Opcode }, | |
8976381e | 3930 | { "pmovsxdq", { XM, EXq } }, |
42903f7f L |
3931 | }, |
3932 | ||
1ceb70f8 | 3933 | /* PREFIX_0F3828 */ |
42903f7f | 3934 | { |
592d1631 L |
3935 | { Bad_Opcode }, |
3936 | { Bad_Opcode }, | |
09a2c6cf | 3937 | { "pmuldq", { XM, EXx } }, |
42903f7f L |
3938 | }, |
3939 | ||
1ceb70f8 | 3940 | /* PREFIX_0F3829 */ |
42903f7f | 3941 | { |
592d1631 L |
3942 | { Bad_Opcode }, |
3943 | { Bad_Opcode }, | |
09a2c6cf | 3944 | { "pcmpeqq", { XM, EXx } }, |
42903f7f L |
3945 | }, |
3946 | ||
1ceb70f8 | 3947 | /* PREFIX_0F382A */ |
42903f7f | 3948 | { |
592d1631 L |
3949 | { Bad_Opcode }, |
3950 | { Bad_Opcode }, | |
75c135a8 | 3951 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
42903f7f L |
3952 | }, |
3953 | ||
1ceb70f8 | 3954 | /* PREFIX_0F382B */ |
42903f7f | 3955 | { |
592d1631 L |
3956 | { Bad_Opcode }, |
3957 | { Bad_Opcode }, | |
09a2c6cf | 3958 | { "packusdw", { XM, EXx } }, |
42903f7f L |
3959 | }, |
3960 | ||
1ceb70f8 | 3961 | /* PREFIX_0F3830 */ |
42903f7f | 3962 | { |
592d1631 L |
3963 | { Bad_Opcode }, |
3964 | { Bad_Opcode }, | |
8976381e | 3965 | { "pmovzxbw", { XM, EXq } }, |
42903f7f L |
3966 | }, |
3967 | ||
1ceb70f8 | 3968 | /* PREFIX_0F3831 */ |
42903f7f | 3969 | { |
592d1631 L |
3970 | { Bad_Opcode }, |
3971 | { Bad_Opcode }, | |
8976381e | 3972 | { "pmovzxbd", { XM, EXd } }, |
42903f7f L |
3973 | }, |
3974 | ||
1ceb70f8 | 3975 | /* PREFIX_0F3832 */ |
42903f7f | 3976 | { |
592d1631 L |
3977 | { Bad_Opcode }, |
3978 | { Bad_Opcode }, | |
8976381e | 3979 | { "pmovzxbq", { XM, EXw } }, |
42903f7f L |
3980 | }, |
3981 | ||
1ceb70f8 | 3982 | /* PREFIX_0F3833 */ |
42903f7f | 3983 | { |
592d1631 L |
3984 | { Bad_Opcode }, |
3985 | { Bad_Opcode }, | |
8976381e | 3986 | { "pmovzxwd", { XM, EXq } }, |
42903f7f L |
3987 | }, |
3988 | ||
1ceb70f8 | 3989 | /* PREFIX_0F3834 */ |
42903f7f | 3990 | { |
592d1631 L |
3991 | { Bad_Opcode }, |
3992 | { Bad_Opcode }, | |
8976381e | 3993 | { "pmovzxwq", { XM, EXd } }, |
42903f7f L |
3994 | }, |
3995 | ||
1ceb70f8 | 3996 | /* PREFIX_0F3835 */ |
42903f7f | 3997 | { |
592d1631 L |
3998 | { Bad_Opcode }, |
3999 | { Bad_Opcode }, | |
8976381e | 4000 | { "pmovzxdq", { XM, EXq } }, |
42903f7f L |
4001 | }, |
4002 | ||
1ceb70f8 | 4003 | /* PREFIX_0F3837 */ |
4e7d34a6 | 4004 | { |
592d1631 L |
4005 | { Bad_Opcode }, |
4006 | { Bad_Opcode }, | |
4e7d34a6 | 4007 | { "pcmpgtq", { XM, EXx } }, |
4e7d34a6 L |
4008 | }, |
4009 | ||
1ceb70f8 | 4010 | /* PREFIX_0F3838 */ |
42903f7f | 4011 | { |
592d1631 L |
4012 | { Bad_Opcode }, |
4013 | { Bad_Opcode }, | |
09a2c6cf | 4014 | { "pminsb", { XM, EXx } }, |
42903f7f L |
4015 | }, |
4016 | ||
1ceb70f8 | 4017 | /* PREFIX_0F3839 */ |
42903f7f | 4018 | { |
592d1631 L |
4019 | { Bad_Opcode }, |
4020 | { Bad_Opcode }, | |
09a2c6cf | 4021 | { "pminsd", { XM, EXx } }, |
42903f7f L |
4022 | }, |
4023 | ||
1ceb70f8 | 4024 | /* PREFIX_0F383A */ |
42903f7f | 4025 | { |
592d1631 L |
4026 | { Bad_Opcode }, |
4027 | { Bad_Opcode }, | |
09a2c6cf | 4028 | { "pminuw", { XM, EXx } }, |
42903f7f L |
4029 | }, |
4030 | ||
1ceb70f8 | 4031 | /* PREFIX_0F383B */ |
42903f7f | 4032 | { |
592d1631 L |
4033 | { Bad_Opcode }, |
4034 | { Bad_Opcode }, | |
09a2c6cf | 4035 | { "pminud", { XM, EXx } }, |
42903f7f L |
4036 | }, |
4037 | ||
1ceb70f8 | 4038 | /* PREFIX_0F383C */ |
42903f7f | 4039 | { |
592d1631 L |
4040 | { Bad_Opcode }, |
4041 | { Bad_Opcode }, | |
09a2c6cf | 4042 | { "pmaxsb", { XM, EXx } }, |
42903f7f L |
4043 | }, |
4044 | ||
1ceb70f8 | 4045 | /* PREFIX_0F383D */ |
42903f7f | 4046 | { |
592d1631 L |
4047 | { Bad_Opcode }, |
4048 | { Bad_Opcode }, | |
09a2c6cf | 4049 | { "pmaxsd", { XM, EXx } }, |
42903f7f L |
4050 | }, |
4051 | ||
1ceb70f8 | 4052 | /* PREFIX_0F383E */ |
42903f7f | 4053 | { |
592d1631 L |
4054 | { Bad_Opcode }, |
4055 | { Bad_Opcode }, | |
09a2c6cf | 4056 | { "pmaxuw", { XM, EXx } }, |
42903f7f L |
4057 | }, |
4058 | ||
1ceb70f8 | 4059 | /* PREFIX_0F383F */ |
42903f7f | 4060 | { |
592d1631 L |
4061 | { Bad_Opcode }, |
4062 | { Bad_Opcode }, | |
09a2c6cf | 4063 | { "pmaxud", { XM, EXx } }, |
42903f7f L |
4064 | }, |
4065 | ||
1ceb70f8 | 4066 | /* PREFIX_0F3840 */ |
42903f7f | 4067 | { |
592d1631 L |
4068 | { Bad_Opcode }, |
4069 | { Bad_Opcode }, | |
09a2c6cf | 4070 | { "pmulld", { XM, EXx } }, |
42903f7f L |
4071 | }, |
4072 | ||
1ceb70f8 | 4073 | /* PREFIX_0F3841 */ |
42903f7f | 4074 | { |
592d1631 L |
4075 | { Bad_Opcode }, |
4076 | { Bad_Opcode }, | |
09a2c6cf | 4077 | { "phminposuw", { XM, EXx } }, |
42903f7f L |
4078 | }, |
4079 | ||
f1f8f695 L |
4080 | /* PREFIX_0F3880 */ |
4081 | { | |
592d1631 L |
4082 | { Bad_Opcode }, |
4083 | { Bad_Opcode }, | |
f1f8f695 | 4084 | { "invept", { Gm, Mo } }, |
f1f8f695 L |
4085 | }, |
4086 | ||
4087 | /* PREFIX_0F3881 */ | |
4088 | { | |
592d1631 L |
4089 | { Bad_Opcode }, |
4090 | { Bad_Opcode }, | |
f1f8f695 | 4091 | { "invvpid", { Gm, Mo } }, |
f1f8f695 L |
4092 | }, |
4093 | ||
6c30d220 L |
4094 | /* PREFIX_0F3882 */ |
4095 | { | |
4096 | { Bad_Opcode }, | |
4097 | { Bad_Opcode }, | |
4098 | { "invpcid", { Gm, M } }, | |
4099 | }, | |
4100 | ||
a0046408 L |
4101 | /* PREFIX_0F38C8 */ |
4102 | { | |
4103 | { "sha1nexte", { XM, EXxmm } }, | |
4104 | }, | |
4105 | ||
4106 | /* PREFIX_0F38C9 */ | |
4107 | { | |
4108 | { "sha1msg1", { XM, EXxmm } }, | |
4109 | }, | |
4110 | ||
4111 | /* PREFIX_0F38CA */ | |
4112 | { | |
4113 | { "sha1msg2", { XM, EXxmm } }, | |
4114 | }, | |
4115 | ||
4116 | /* PREFIX_0F38CB */ | |
4117 | { | |
4118 | { "sha256rnds2", { XM, EXxmm, XMM0 } }, | |
4119 | }, | |
4120 | ||
4121 | /* PREFIX_0F38CC */ | |
4122 | { | |
4123 | { "sha256msg1", { XM, EXxmm } }, | |
4124 | }, | |
4125 | ||
4126 | /* PREFIX_0F38CD */ | |
4127 | { | |
4128 | { "sha256msg2", { XM, EXxmm } }, | |
4129 | }, | |
4130 | ||
c0f3af97 L |
4131 | /* PREFIX_0F38DB */ |
4132 | { | |
592d1631 L |
4133 | { Bad_Opcode }, |
4134 | { Bad_Opcode }, | |
c0f3af97 | 4135 | { "aesimc", { XM, EXx } }, |
c0f3af97 L |
4136 | }, |
4137 | ||
4138 | /* PREFIX_0F38DC */ | |
4139 | { | |
592d1631 L |
4140 | { Bad_Opcode }, |
4141 | { Bad_Opcode }, | |
c0f3af97 | 4142 | { "aesenc", { XM, EXx } }, |
c0f3af97 L |
4143 | }, |
4144 | ||
4145 | /* PREFIX_0F38DD */ | |
4146 | { | |
592d1631 L |
4147 | { Bad_Opcode }, |
4148 | { Bad_Opcode }, | |
c0f3af97 | 4149 | { "aesenclast", { XM, EXx } }, |
c0f3af97 L |
4150 | }, |
4151 | ||
4152 | /* PREFIX_0F38DE */ | |
4153 | { | |
592d1631 L |
4154 | { Bad_Opcode }, |
4155 | { Bad_Opcode }, | |
c0f3af97 | 4156 | { "aesdec", { XM, EXx } }, |
c0f3af97 L |
4157 | }, |
4158 | ||
4159 | /* PREFIX_0F38DF */ | |
4160 | { | |
592d1631 L |
4161 | { Bad_Opcode }, |
4162 | { Bad_Opcode }, | |
c0f3af97 | 4163 | { "aesdeclast", { XM, EXx } }, |
c0f3af97 L |
4164 | }, |
4165 | ||
1ceb70f8 | 4166 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 4167 | { |
f1f8f695 | 4168 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } }, |
592d1631 | 4169 | { Bad_Opcode }, |
f1f8f695 | 4170 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } }, |
7bb15c6f | 4171 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } } }, |
4e7d34a6 L |
4172 | }, |
4173 | ||
1ceb70f8 | 4174 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 4175 | { |
f1f8f695 | 4176 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } }, |
592d1631 | 4177 | { Bad_Opcode }, |
f1f8f695 | 4178 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } }, |
7bb15c6f | 4179 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } } }, |
4e7d34a6 L |
4180 | }, |
4181 | ||
e2e1fcde L |
4182 | /* PREFIX_0F38F6 */ |
4183 | { | |
4184 | { Bad_Opcode }, | |
4185 | { "adoxS", { Gdq, Edq} }, | |
4186 | { "adcxS", { Gdq, Edq} }, | |
4187 | { Bad_Opcode }, | |
4188 | }, | |
4189 | ||
1ceb70f8 | 4190 | /* PREFIX_0F3A08 */ |
42903f7f | 4191 | { |
592d1631 L |
4192 | { Bad_Opcode }, |
4193 | { Bad_Opcode }, | |
09a2c6cf | 4194 | { "roundps", { XM, EXx, Ib } }, |
42903f7f L |
4195 | }, |
4196 | ||
1ceb70f8 | 4197 | /* PREFIX_0F3A09 */ |
42903f7f | 4198 | { |
592d1631 L |
4199 | { Bad_Opcode }, |
4200 | { Bad_Opcode }, | |
09a2c6cf | 4201 | { "roundpd", { XM, EXx, Ib } }, |
42903f7f L |
4202 | }, |
4203 | ||
1ceb70f8 | 4204 | /* PREFIX_0F3A0A */ |
42903f7f | 4205 | { |
592d1631 L |
4206 | { Bad_Opcode }, |
4207 | { Bad_Opcode }, | |
09335d05 | 4208 | { "roundss", { XM, EXd, Ib } }, |
42903f7f L |
4209 | }, |
4210 | ||
1ceb70f8 | 4211 | /* PREFIX_0F3A0B */ |
42903f7f | 4212 | { |
592d1631 L |
4213 | { Bad_Opcode }, |
4214 | { Bad_Opcode }, | |
09335d05 | 4215 | { "roundsd", { XM, EXq, Ib } }, |
42903f7f L |
4216 | }, |
4217 | ||
1ceb70f8 | 4218 | /* PREFIX_0F3A0C */ |
42903f7f | 4219 | { |
592d1631 L |
4220 | { Bad_Opcode }, |
4221 | { Bad_Opcode }, | |
09a2c6cf | 4222 | { "blendps", { XM, EXx, Ib } }, |
42903f7f L |
4223 | }, |
4224 | ||
1ceb70f8 | 4225 | /* PREFIX_0F3A0D */ |
42903f7f | 4226 | { |
592d1631 L |
4227 | { Bad_Opcode }, |
4228 | { Bad_Opcode }, | |
09a2c6cf | 4229 | { "blendpd", { XM, EXx, Ib } }, |
42903f7f L |
4230 | }, |
4231 | ||
1ceb70f8 | 4232 | /* PREFIX_0F3A0E */ |
42903f7f | 4233 | { |
592d1631 L |
4234 | { Bad_Opcode }, |
4235 | { Bad_Opcode }, | |
09a2c6cf | 4236 | { "pblendw", { XM, EXx, Ib } }, |
42903f7f L |
4237 | }, |
4238 | ||
1ceb70f8 | 4239 | /* PREFIX_0F3A14 */ |
42903f7f | 4240 | { |
592d1631 L |
4241 | { Bad_Opcode }, |
4242 | { Bad_Opcode }, | |
42903f7f | 4243 | { "pextrb", { Edqb, XM, Ib } }, |
42903f7f L |
4244 | }, |
4245 | ||
1ceb70f8 | 4246 | /* PREFIX_0F3A15 */ |
42903f7f | 4247 | { |
592d1631 L |
4248 | { Bad_Opcode }, |
4249 | { Bad_Opcode }, | |
42903f7f | 4250 | { "pextrw", { Edqw, XM, Ib } }, |
42903f7f L |
4251 | }, |
4252 | ||
1ceb70f8 | 4253 | /* PREFIX_0F3A16 */ |
42903f7f | 4254 | { |
592d1631 L |
4255 | { Bad_Opcode }, |
4256 | { Bad_Opcode }, | |
42903f7f | 4257 | { "pextrK", { Edq, XM, Ib } }, |
42903f7f L |
4258 | }, |
4259 | ||
1ceb70f8 | 4260 | /* PREFIX_0F3A17 */ |
42903f7f | 4261 | { |
592d1631 L |
4262 | { Bad_Opcode }, |
4263 | { Bad_Opcode }, | |
42903f7f | 4264 | { "extractps", { Edqd, XM, Ib } }, |
42903f7f L |
4265 | }, |
4266 | ||
1ceb70f8 | 4267 | /* PREFIX_0F3A20 */ |
42903f7f | 4268 | { |
592d1631 L |
4269 | { Bad_Opcode }, |
4270 | { Bad_Opcode }, | |
42903f7f | 4271 | { "pinsrb", { XM, Edqb, Ib } }, |
42903f7f L |
4272 | }, |
4273 | ||
1ceb70f8 | 4274 | /* PREFIX_0F3A21 */ |
42903f7f | 4275 | { |
592d1631 L |
4276 | { Bad_Opcode }, |
4277 | { Bad_Opcode }, | |
8976381e | 4278 | { "insertps", { XM, EXd, Ib } }, |
42903f7f L |
4279 | }, |
4280 | ||
1ceb70f8 | 4281 | /* PREFIX_0F3A22 */ |
42903f7f | 4282 | { |
592d1631 L |
4283 | { Bad_Opcode }, |
4284 | { Bad_Opcode }, | |
42903f7f | 4285 | { "pinsrK", { XM, Edq, Ib } }, |
42903f7f L |
4286 | }, |
4287 | ||
1ceb70f8 | 4288 | /* PREFIX_0F3A40 */ |
42903f7f | 4289 | { |
592d1631 L |
4290 | { Bad_Opcode }, |
4291 | { Bad_Opcode }, | |
09a2c6cf | 4292 | { "dpps", { XM, EXx, Ib } }, |
42903f7f L |
4293 | }, |
4294 | ||
1ceb70f8 | 4295 | /* PREFIX_0F3A41 */ |
42903f7f | 4296 | { |
592d1631 L |
4297 | { Bad_Opcode }, |
4298 | { Bad_Opcode }, | |
09a2c6cf | 4299 | { "dppd", { XM, EXx, Ib } }, |
42903f7f L |
4300 | }, |
4301 | ||
1ceb70f8 | 4302 | /* PREFIX_0F3A42 */ |
42903f7f | 4303 | { |
592d1631 L |
4304 | { Bad_Opcode }, |
4305 | { Bad_Opcode }, | |
09a2c6cf | 4306 | { "mpsadbw", { XM, EXx, Ib } }, |
42903f7f | 4307 | }, |
381d071f | 4308 | |
c0f3af97 L |
4309 | /* PREFIX_0F3A44 */ |
4310 | { | |
592d1631 L |
4311 | { Bad_Opcode }, |
4312 | { Bad_Opcode }, | |
c0f3af97 | 4313 | { "pclmulqdq", { XM, EXx, PCLMUL } }, |
c0f3af97 L |
4314 | }, |
4315 | ||
1ceb70f8 | 4316 | /* PREFIX_0F3A60 */ |
381d071f | 4317 | { |
592d1631 L |
4318 | { Bad_Opcode }, |
4319 | { Bad_Opcode }, | |
4e7d34a6 | 4320 | { "pcmpestrm", { XM, EXx, Ib } }, |
381d071f L |
4321 | }, |
4322 | ||
1ceb70f8 | 4323 | /* PREFIX_0F3A61 */ |
381d071f | 4324 | { |
592d1631 L |
4325 | { Bad_Opcode }, |
4326 | { Bad_Opcode }, | |
4e7d34a6 | 4327 | { "pcmpestri", { XM, EXx, Ib } }, |
381d071f L |
4328 | }, |
4329 | ||
1ceb70f8 | 4330 | /* PREFIX_0F3A62 */ |
381d071f | 4331 | { |
592d1631 L |
4332 | { Bad_Opcode }, |
4333 | { Bad_Opcode }, | |
4e7d34a6 | 4334 | { "pcmpistrm", { XM, EXx, Ib } }, |
381d071f L |
4335 | }, |
4336 | ||
1ceb70f8 | 4337 | /* PREFIX_0F3A63 */ |
381d071f | 4338 | { |
592d1631 L |
4339 | { Bad_Opcode }, |
4340 | { Bad_Opcode }, | |
4e7d34a6 | 4341 | { "pcmpistri", { XM, EXx, Ib } }, |
381d071f | 4342 | }, |
09a2c6cf | 4343 | |
a0046408 L |
4344 | /* PREFIX_0F3ACC */ |
4345 | { | |
4346 | { "sha1rnds4", { XM, EXxmm, Ib } }, | |
4347 | }, | |
4348 | ||
c0f3af97 | 4349 | /* PREFIX_0F3ADF */ |
09a2c6cf | 4350 | { |
592d1631 L |
4351 | { Bad_Opcode }, |
4352 | { Bad_Opcode }, | |
c0f3af97 | 4353 | { "aeskeygenassist", { XM, EXx, Ib } }, |
09a2c6cf L |
4354 | }, |
4355 | ||
592a252b | 4356 | /* PREFIX_VEX_0F10 */ |
09a2c6cf | 4357 | { |
592a252b L |
4358 | { VEX_W_TABLE (VEX_W_0F10_P_0) }, |
4359 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) }, | |
4360 | { VEX_W_TABLE (VEX_W_0F10_P_2) }, | |
4361 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) }, | |
09a2c6cf L |
4362 | }, |
4363 | ||
592a252b | 4364 | /* PREFIX_VEX_0F11 */ |
09a2c6cf | 4365 | { |
592a252b L |
4366 | { VEX_W_TABLE (VEX_W_0F11_P_0) }, |
4367 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) }, | |
4368 | { VEX_W_TABLE (VEX_W_0F11_P_2) }, | |
4369 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) }, | |
09a2c6cf L |
4370 | }, |
4371 | ||
592a252b | 4372 | /* PREFIX_VEX_0F12 */ |
09a2c6cf | 4373 | { |
592a252b L |
4374 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
4375 | { VEX_W_TABLE (VEX_W_0F12_P_1) }, | |
4376 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) }, | |
4377 | { VEX_W_TABLE (VEX_W_0F12_P_3) }, | |
09a2c6cf L |
4378 | }, |
4379 | ||
592a252b | 4380 | /* PREFIX_VEX_0F16 */ |
09a2c6cf | 4381 | { |
592a252b L |
4382 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
4383 | { VEX_W_TABLE (VEX_W_0F16_P_1) }, | |
4384 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) }, | |
5f754f58 | 4385 | }, |
7c52e0e8 | 4386 | |
592a252b | 4387 | /* PREFIX_VEX_0F2A */ |
5f754f58 | 4388 | { |
592d1631 | 4389 | { Bad_Opcode }, |
592a252b | 4390 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) }, |
592d1631 | 4391 | { Bad_Opcode }, |
592a252b | 4392 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) }, |
5f754f58 | 4393 | }, |
7c52e0e8 | 4394 | |
592a252b | 4395 | /* PREFIX_VEX_0F2C */ |
5f754f58 | 4396 | { |
592d1631 | 4397 | { Bad_Opcode }, |
592a252b | 4398 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) }, |
592d1631 | 4399 | { Bad_Opcode }, |
592a252b | 4400 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) }, |
5f754f58 | 4401 | }, |
7c52e0e8 | 4402 | |
592a252b | 4403 | /* PREFIX_VEX_0F2D */ |
7c52e0e8 | 4404 | { |
592d1631 | 4405 | { Bad_Opcode }, |
592a252b | 4406 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) }, |
592d1631 | 4407 | { Bad_Opcode }, |
592a252b | 4408 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) }, |
7c52e0e8 L |
4409 | }, |
4410 | ||
592a252b | 4411 | /* PREFIX_VEX_0F2E */ |
7c52e0e8 | 4412 | { |
592a252b | 4413 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) }, |
592d1631 | 4414 | { Bad_Opcode }, |
592a252b | 4415 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) }, |
7c52e0e8 L |
4416 | }, |
4417 | ||
592a252b | 4418 | /* PREFIX_VEX_0F2F */ |
7c52e0e8 | 4419 | { |
592a252b | 4420 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) }, |
592d1631 | 4421 | { Bad_Opcode }, |
592a252b | 4422 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) }, |
7c52e0e8 L |
4423 | }, |
4424 | ||
43234a1e L |
4425 | /* PREFIX_VEX_0F41 */ |
4426 | { | |
4427 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, | |
4428 | }, | |
4429 | ||
4430 | /* PREFIX_VEX_0F42 */ | |
4431 | { | |
4432 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, | |
4433 | }, | |
4434 | ||
4435 | /* PREFIX_VEX_0F44 */ | |
4436 | { | |
4437 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, | |
4438 | }, | |
4439 | ||
4440 | /* PREFIX_VEX_0F45 */ | |
4441 | { | |
4442 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, | |
4443 | }, | |
4444 | ||
4445 | /* PREFIX_VEX_0F46 */ | |
4446 | { | |
4447 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, | |
4448 | }, | |
4449 | ||
4450 | /* PREFIX_VEX_0F47 */ | |
4451 | { | |
4452 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, | |
4453 | }, | |
4454 | ||
4455 | /* PREFIX_VEX_0F4B */ | |
4456 | { | |
4457 | { Bad_Opcode }, | |
4458 | { Bad_Opcode }, | |
4459 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, | |
4460 | }, | |
4461 | ||
592a252b | 4462 | /* PREFIX_VEX_0F51 */ |
7c52e0e8 | 4463 | { |
592a252b L |
4464 | { VEX_W_TABLE (VEX_W_0F51_P_0) }, |
4465 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) }, | |
4466 | { VEX_W_TABLE (VEX_W_0F51_P_2) }, | |
4467 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) }, | |
7c52e0e8 L |
4468 | }, |
4469 | ||
592a252b | 4470 | /* PREFIX_VEX_0F52 */ |
7c52e0e8 | 4471 | { |
592a252b L |
4472 | { VEX_W_TABLE (VEX_W_0F52_P_0) }, |
4473 | { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) }, | |
7c52e0e8 L |
4474 | }, |
4475 | ||
592a252b | 4476 | /* PREFIX_VEX_0F53 */ |
7c52e0e8 | 4477 | { |
592a252b L |
4478 | { VEX_W_TABLE (VEX_W_0F53_P_0) }, |
4479 | { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) }, | |
7c52e0e8 L |
4480 | }, |
4481 | ||
592a252b | 4482 | /* PREFIX_VEX_0F58 */ |
7c52e0e8 | 4483 | { |
592a252b L |
4484 | { VEX_W_TABLE (VEX_W_0F58_P_0) }, |
4485 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) }, | |
4486 | { VEX_W_TABLE (VEX_W_0F58_P_2) }, | |
4487 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) }, | |
7c52e0e8 L |
4488 | }, |
4489 | ||
592a252b | 4490 | /* PREFIX_VEX_0F59 */ |
7c52e0e8 | 4491 | { |
592a252b L |
4492 | { VEX_W_TABLE (VEX_W_0F59_P_0) }, |
4493 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) }, | |
4494 | { VEX_W_TABLE (VEX_W_0F59_P_2) }, | |
4495 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) }, | |
7c52e0e8 L |
4496 | }, |
4497 | ||
592a252b | 4498 | /* PREFIX_VEX_0F5A */ |
7c52e0e8 | 4499 | { |
592a252b L |
4500 | { VEX_W_TABLE (VEX_W_0F5A_P_0) }, |
4501 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) }, | |
c0f3af97 | 4502 | { "vcvtpd2ps%XY", { XMM, EXx } }, |
592a252b | 4503 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) }, |
7c52e0e8 L |
4504 | }, |
4505 | ||
592a252b | 4506 | /* PREFIX_VEX_0F5B */ |
7c52e0e8 | 4507 | { |
592a252b L |
4508 | { VEX_W_TABLE (VEX_W_0F5B_P_0) }, |
4509 | { VEX_W_TABLE (VEX_W_0F5B_P_1) }, | |
4510 | { VEX_W_TABLE (VEX_W_0F5B_P_2) }, | |
7c52e0e8 L |
4511 | }, |
4512 | ||
592a252b | 4513 | /* PREFIX_VEX_0F5C */ |
7c52e0e8 | 4514 | { |
592a252b L |
4515 | { VEX_W_TABLE (VEX_W_0F5C_P_0) }, |
4516 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) }, | |
4517 | { VEX_W_TABLE (VEX_W_0F5C_P_2) }, | |
4518 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) }, | |
7c52e0e8 L |
4519 | }, |
4520 | ||
592a252b | 4521 | /* PREFIX_VEX_0F5D */ |
7c52e0e8 | 4522 | { |
592a252b L |
4523 | { VEX_W_TABLE (VEX_W_0F5D_P_0) }, |
4524 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) }, | |
4525 | { VEX_W_TABLE (VEX_W_0F5D_P_2) }, | |
4526 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) }, | |
7c52e0e8 L |
4527 | }, |
4528 | ||
592a252b | 4529 | /* PREFIX_VEX_0F5E */ |
7c52e0e8 | 4530 | { |
592a252b L |
4531 | { VEX_W_TABLE (VEX_W_0F5E_P_0) }, |
4532 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) }, | |
4533 | { VEX_W_TABLE (VEX_W_0F5E_P_2) }, | |
4534 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) }, | |
7c52e0e8 L |
4535 | }, |
4536 | ||
592a252b | 4537 | /* PREFIX_VEX_0F5F */ |
7c52e0e8 | 4538 | { |
592a252b L |
4539 | { VEX_W_TABLE (VEX_W_0F5F_P_0) }, |
4540 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) }, | |
4541 | { VEX_W_TABLE (VEX_W_0F5F_P_2) }, | |
4542 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) }, | |
7c52e0e8 L |
4543 | }, |
4544 | ||
592a252b | 4545 | /* PREFIX_VEX_0F60 */ |
7c52e0e8 | 4546 | { |
592d1631 L |
4547 | { Bad_Opcode }, |
4548 | { Bad_Opcode }, | |
6c30d220 | 4549 | { VEX_W_TABLE (VEX_W_0F60_P_2) }, |
7c52e0e8 L |
4550 | }, |
4551 | ||
592a252b | 4552 | /* PREFIX_VEX_0F61 */ |
7c52e0e8 | 4553 | { |
592d1631 L |
4554 | { Bad_Opcode }, |
4555 | { Bad_Opcode }, | |
6c30d220 | 4556 | { VEX_W_TABLE (VEX_W_0F61_P_2) }, |
7c52e0e8 L |
4557 | }, |
4558 | ||
592a252b | 4559 | /* PREFIX_VEX_0F62 */ |
7c52e0e8 | 4560 | { |
592d1631 L |
4561 | { Bad_Opcode }, |
4562 | { Bad_Opcode }, | |
6c30d220 | 4563 | { VEX_W_TABLE (VEX_W_0F62_P_2) }, |
7c52e0e8 L |
4564 | }, |
4565 | ||
592a252b | 4566 | /* PREFIX_VEX_0F63 */ |
7c52e0e8 | 4567 | { |
592d1631 L |
4568 | { Bad_Opcode }, |
4569 | { Bad_Opcode }, | |
6c30d220 | 4570 | { VEX_W_TABLE (VEX_W_0F63_P_2) }, |
7c52e0e8 L |
4571 | }, |
4572 | ||
592a252b | 4573 | /* PREFIX_VEX_0F64 */ |
7c52e0e8 | 4574 | { |
592d1631 L |
4575 | { Bad_Opcode }, |
4576 | { Bad_Opcode }, | |
6c30d220 | 4577 | { VEX_W_TABLE (VEX_W_0F64_P_2) }, |
7c52e0e8 L |
4578 | }, |
4579 | ||
592a252b | 4580 | /* PREFIX_VEX_0F65 */ |
7c52e0e8 | 4581 | { |
592d1631 L |
4582 | { Bad_Opcode }, |
4583 | { Bad_Opcode }, | |
6c30d220 | 4584 | { VEX_W_TABLE (VEX_W_0F65_P_2) }, |
7c52e0e8 L |
4585 | }, |
4586 | ||
592a252b | 4587 | /* PREFIX_VEX_0F66 */ |
7c52e0e8 | 4588 | { |
592d1631 L |
4589 | { Bad_Opcode }, |
4590 | { Bad_Opcode }, | |
6c30d220 | 4591 | { VEX_W_TABLE (VEX_W_0F66_P_2) }, |
7c52e0e8 | 4592 | }, |
6439fc28 | 4593 | |
592a252b | 4594 | /* PREFIX_VEX_0F67 */ |
331d2d0d | 4595 | { |
592d1631 L |
4596 | { Bad_Opcode }, |
4597 | { Bad_Opcode }, | |
6c30d220 | 4598 | { VEX_W_TABLE (VEX_W_0F67_P_2) }, |
c0f3af97 L |
4599 | }, |
4600 | ||
592a252b | 4601 | /* PREFIX_VEX_0F68 */ |
c0f3af97 | 4602 | { |
592d1631 L |
4603 | { Bad_Opcode }, |
4604 | { Bad_Opcode }, | |
6c30d220 | 4605 | { VEX_W_TABLE (VEX_W_0F68_P_2) }, |
c0f3af97 L |
4606 | }, |
4607 | ||
592a252b | 4608 | /* PREFIX_VEX_0F69 */ |
c0f3af97 | 4609 | { |
592d1631 L |
4610 | { Bad_Opcode }, |
4611 | { Bad_Opcode }, | |
6c30d220 | 4612 | { VEX_W_TABLE (VEX_W_0F69_P_2) }, |
c0f3af97 L |
4613 | }, |
4614 | ||
592a252b | 4615 | /* PREFIX_VEX_0F6A */ |
c0f3af97 | 4616 | { |
592d1631 L |
4617 | { Bad_Opcode }, |
4618 | { Bad_Opcode }, | |
6c30d220 | 4619 | { VEX_W_TABLE (VEX_W_0F6A_P_2) }, |
c0f3af97 L |
4620 | }, |
4621 | ||
592a252b | 4622 | /* PREFIX_VEX_0F6B */ |
c0f3af97 | 4623 | { |
592d1631 L |
4624 | { Bad_Opcode }, |
4625 | { Bad_Opcode }, | |
6c30d220 | 4626 | { VEX_W_TABLE (VEX_W_0F6B_P_2) }, |
c0f3af97 L |
4627 | }, |
4628 | ||
592a252b | 4629 | /* PREFIX_VEX_0F6C */ |
c0f3af97 | 4630 | { |
592d1631 L |
4631 | { Bad_Opcode }, |
4632 | { Bad_Opcode }, | |
6c30d220 | 4633 | { VEX_W_TABLE (VEX_W_0F6C_P_2) }, |
c0f3af97 L |
4634 | }, |
4635 | ||
592a252b | 4636 | /* PREFIX_VEX_0F6D */ |
c0f3af97 | 4637 | { |
592d1631 L |
4638 | { Bad_Opcode }, |
4639 | { Bad_Opcode }, | |
6c30d220 | 4640 | { VEX_W_TABLE (VEX_W_0F6D_P_2) }, |
c0f3af97 L |
4641 | }, |
4642 | ||
592a252b | 4643 | /* PREFIX_VEX_0F6E */ |
c0f3af97 | 4644 | { |
592d1631 L |
4645 | { Bad_Opcode }, |
4646 | { Bad_Opcode }, | |
592a252b | 4647 | { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, |
c0f3af97 L |
4648 | }, |
4649 | ||
592a252b | 4650 | /* PREFIX_VEX_0F6F */ |
c0f3af97 | 4651 | { |
592d1631 | 4652 | { Bad_Opcode }, |
592a252b L |
4653 | { VEX_W_TABLE (VEX_W_0F6F_P_1) }, |
4654 | { VEX_W_TABLE (VEX_W_0F6F_P_2) }, | |
c0f3af97 L |
4655 | }, |
4656 | ||
592a252b | 4657 | /* PREFIX_VEX_0F70 */ |
c0f3af97 | 4658 | { |
592d1631 | 4659 | { Bad_Opcode }, |
6c30d220 L |
4660 | { VEX_W_TABLE (VEX_W_0F70_P_1) }, |
4661 | { VEX_W_TABLE (VEX_W_0F70_P_2) }, | |
4662 | { VEX_W_TABLE (VEX_W_0F70_P_3) }, | |
c0f3af97 L |
4663 | }, |
4664 | ||
592a252b | 4665 | /* PREFIX_VEX_0F71_REG_2 */ |
c0f3af97 | 4666 | { |
592d1631 L |
4667 | { Bad_Opcode }, |
4668 | { Bad_Opcode }, | |
6c30d220 | 4669 | { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) }, |
c0f3af97 L |
4670 | }, |
4671 | ||
592a252b | 4672 | /* PREFIX_VEX_0F71_REG_4 */ |
c0f3af97 | 4673 | { |
592d1631 L |
4674 | { Bad_Opcode }, |
4675 | { Bad_Opcode }, | |
6c30d220 | 4676 | { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) }, |
c0f3af97 L |
4677 | }, |
4678 | ||
592a252b | 4679 | /* PREFIX_VEX_0F71_REG_6 */ |
c0f3af97 | 4680 | { |
592d1631 L |
4681 | { Bad_Opcode }, |
4682 | { Bad_Opcode }, | |
6c30d220 | 4683 | { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) }, |
c0f3af97 L |
4684 | }, |
4685 | ||
592a252b | 4686 | /* PREFIX_VEX_0F72_REG_2 */ |
c0f3af97 | 4687 | { |
592d1631 L |
4688 | { Bad_Opcode }, |
4689 | { Bad_Opcode }, | |
6c30d220 | 4690 | { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) }, |
c0f3af97 L |
4691 | }, |
4692 | ||
592a252b | 4693 | /* PREFIX_VEX_0F72_REG_4 */ |
c0f3af97 | 4694 | { |
592d1631 L |
4695 | { Bad_Opcode }, |
4696 | { Bad_Opcode }, | |
6c30d220 | 4697 | { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) }, |
c0f3af97 L |
4698 | }, |
4699 | ||
592a252b | 4700 | /* PREFIX_VEX_0F72_REG_6 */ |
c0f3af97 | 4701 | { |
592d1631 L |
4702 | { Bad_Opcode }, |
4703 | { Bad_Opcode }, | |
6c30d220 | 4704 | { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) }, |
c0f3af97 L |
4705 | }, |
4706 | ||
592a252b | 4707 | /* PREFIX_VEX_0F73_REG_2 */ |
c0f3af97 | 4708 | { |
592d1631 L |
4709 | { Bad_Opcode }, |
4710 | { Bad_Opcode }, | |
6c30d220 | 4711 | { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) }, |
c0f3af97 L |
4712 | }, |
4713 | ||
592a252b | 4714 | /* PREFIX_VEX_0F73_REG_3 */ |
c0f3af97 | 4715 | { |
592d1631 L |
4716 | { Bad_Opcode }, |
4717 | { Bad_Opcode }, | |
6c30d220 | 4718 | { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) }, |
c0f3af97 L |
4719 | }, |
4720 | ||
592a252b | 4721 | /* PREFIX_VEX_0F73_REG_6 */ |
c0f3af97 | 4722 | { |
592d1631 L |
4723 | { Bad_Opcode }, |
4724 | { Bad_Opcode }, | |
6c30d220 | 4725 | { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) }, |
c0f3af97 L |
4726 | }, |
4727 | ||
592a252b | 4728 | /* PREFIX_VEX_0F73_REG_7 */ |
c0f3af97 | 4729 | { |
592d1631 L |
4730 | { Bad_Opcode }, |
4731 | { Bad_Opcode }, | |
6c30d220 | 4732 | { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) }, |
c0f3af97 L |
4733 | }, |
4734 | ||
592a252b | 4735 | /* PREFIX_VEX_0F74 */ |
c0f3af97 | 4736 | { |
592d1631 L |
4737 | { Bad_Opcode }, |
4738 | { Bad_Opcode }, | |
6c30d220 | 4739 | { VEX_W_TABLE (VEX_W_0F74_P_2) }, |
c0f3af97 L |
4740 | }, |
4741 | ||
592a252b | 4742 | /* PREFIX_VEX_0F75 */ |
c0f3af97 | 4743 | { |
592d1631 L |
4744 | { Bad_Opcode }, |
4745 | { Bad_Opcode }, | |
6c30d220 | 4746 | { VEX_W_TABLE (VEX_W_0F75_P_2) }, |
c0f3af97 L |
4747 | }, |
4748 | ||
592a252b | 4749 | /* PREFIX_VEX_0F76 */ |
c0f3af97 | 4750 | { |
592d1631 L |
4751 | { Bad_Opcode }, |
4752 | { Bad_Opcode }, | |
6c30d220 | 4753 | { VEX_W_TABLE (VEX_W_0F76_P_2) }, |
c0f3af97 L |
4754 | }, |
4755 | ||
592a252b | 4756 | /* PREFIX_VEX_0F77 */ |
c0f3af97 | 4757 | { |
592a252b | 4758 | { VEX_W_TABLE (VEX_W_0F77_P_0) }, |
c0f3af97 L |
4759 | }, |
4760 | ||
592a252b | 4761 | /* PREFIX_VEX_0F7C */ |
c0f3af97 | 4762 | { |
592d1631 L |
4763 | { Bad_Opcode }, |
4764 | { Bad_Opcode }, | |
592a252b L |
4765 | { VEX_W_TABLE (VEX_W_0F7C_P_2) }, |
4766 | { VEX_W_TABLE (VEX_W_0F7C_P_3) }, | |
c0f3af97 L |
4767 | }, |
4768 | ||
592a252b | 4769 | /* PREFIX_VEX_0F7D */ |
c0f3af97 | 4770 | { |
592d1631 L |
4771 | { Bad_Opcode }, |
4772 | { Bad_Opcode }, | |
592a252b L |
4773 | { VEX_W_TABLE (VEX_W_0F7D_P_2) }, |
4774 | { VEX_W_TABLE (VEX_W_0F7D_P_3) }, | |
c0f3af97 L |
4775 | }, |
4776 | ||
592a252b | 4777 | /* PREFIX_VEX_0F7E */ |
c0f3af97 | 4778 | { |
592d1631 | 4779 | { Bad_Opcode }, |
592a252b L |
4780 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
4781 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, | |
c0f3af97 L |
4782 | }, |
4783 | ||
592a252b | 4784 | /* PREFIX_VEX_0F7F */ |
c0f3af97 | 4785 | { |
592d1631 | 4786 | { Bad_Opcode }, |
592a252b L |
4787 | { VEX_W_TABLE (VEX_W_0F7F_P_1) }, |
4788 | { VEX_W_TABLE (VEX_W_0F7F_P_2) }, | |
c0f3af97 L |
4789 | }, |
4790 | ||
43234a1e L |
4791 | /* PREFIX_VEX_0F90 */ |
4792 | { | |
4793 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, | |
4794 | }, | |
4795 | ||
4796 | /* PREFIX_VEX_0F91 */ | |
4797 | { | |
4798 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, | |
4799 | }, | |
4800 | ||
4801 | /* PREFIX_VEX_0F92 */ | |
4802 | { | |
4803 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, | |
4804 | }, | |
4805 | ||
4806 | /* PREFIX_VEX_0F93 */ | |
4807 | { | |
4808 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, | |
4809 | }, | |
4810 | ||
4811 | /* PREFIX_VEX_0F98 */ | |
4812 | { | |
4813 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, | |
4814 | }, | |
4815 | ||
592a252b | 4816 | /* PREFIX_VEX_0FC2 */ |
c0f3af97 | 4817 | { |
592a252b L |
4818 | { VEX_W_TABLE (VEX_W_0FC2_P_0) }, |
4819 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) }, | |
4820 | { VEX_W_TABLE (VEX_W_0FC2_P_2) }, | |
4821 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) }, | |
c0f3af97 L |
4822 | }, |
4823 | ||
592a252b | 4824 | /* PREFIX_VEX_0FC4 */ |
c0f3af97 | 4825 | { |
592d1631 L |
4826 | { Bad_Opcode }, |
4827 | { Bad_Opcode }, | |
592a252b | 4828 | { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, |
c0f3af97 L |
4829 | }, |
4830 | ||
592a252b | 4831 | /* PREFIX_VEX_0FC5 */ |
c0f3af97 | 4832 | { |
592d1631 L |
4833 | { Bad_Opcode }, |
4834 | { Bad_Opcode }, | |
592a252b | 4835 | { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, |
c0f3af97 L |
4836 | }, |
4837 | ||
592a252b | 4838 | /* PREFIX_VEX_0FD0 */ |
c0f3af97 | 4839 | { |
592d1631 L |
4840 | { Bad_Opcode }, |
4841 | { Bad_Opcode }, | |
592a252b L |
4842 | { VEX_W_TABLE (VEX_W_0FD0_P_2) }, |
4843 | { VEX_W_TABLE (VEX_W_0FD0_P_3) }, | |
c0f3af97 L |
4844 | }, |
4845 | ||
592a252b | 4846 | /* PREFIX_VEX_0FD1 */ |
c0f3af97 | 4847 | { |
592d1631 L |
4848 | { Bad_Opcode }, |
4849 | { Bad_Opcode }, | |
6c30d220 | 4850 | { VEX_W_TABLE (VEX_W_0FD1_P_2) }, |
c0f3af97 L |
4851 | }, |
4852 | ||
592a252b | 4853 | /* PREFIX_VEX_0FD2 */ |
c0f3af97 | 4854 | { |
592d1631 L |
4855 | { Bad_Opcode }, |
4856 | { Bad_Opcode }, | |
6c30d220 | 4857 | { VEX_W_TABLE (VEX_W_0FD2_P_2) }, |
c0f3af97 L |
4858 | }, |
4859 | ||
592a252b | 4860 | /* PREFIX_VEX_0FD3 */ |
c0f3af97 | 4861 | { |
592d1631 L |
4862 | { Bad_Opcode }, |
4863 | { Bad_Opcode }, | |
6c30d220 | 4864 | { VEX_W_TABLE (VEX_W_0FD3_P_2) }, |
c0f3af97 L |
4865 | }, |
4866 | ||
592a252b | 4867 | /* PREFIX_VEX_0FD4 */ |
c0f3af97 | 4868 | { |
592d1631 L |
4869 | { Bad_Opcode }, |
4870 | { Bad_Opcode }, | |
6c30d220 | 4871 | { VEX_W_TABLE (VEX_W_0FD4_P_2) }, |
c0f3af97 L |
4872 | }, |
4873 | ||
592a252b | 4874 | /* PREFIX_VEX_0FD5 */ |
c0f3af97 | 4875 | { |
592d1631 L |
4876 | { Bad_Opcode }, |
4877 | { Bad_Opcode }, | |
6c30d220 | 4878 | { VEX_W_TABLE (VEX_W_0FD5_P_2) }, |
c0f3af97 L |
4879 | }, |
4880 | ||
592a252b | 4881 | /* PREFIX_VEX_0FD6 */ |
c0f3af97 | 4882 | { |
592d1631 L |
4883 | { Bad_Opcode }, |
4884 | { Bad_Opcode }, | |
592a252b | 4885 | { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, |
c0f3af97 L |
4886 | }, |
4887 | ||
592a252b | 4888 | /* PREFIX_VEX_0FD7 */ |
c0f3af97 | 4889 | { |
592d1631 L |
4890 | { Bad_Opcode }, |
4891 | { Bad_Opcode }, | |
592a252b | 4892 | { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, |
c0f3af97 L |
4893 | }, |
4894 | ||
592a252b | 4895 | /* PREFIX_VEX_0FD8 */ |
c0f3af97 | 4896 | { |
592d1631 L |
4897 | { Bad_Opcode }, |
4898 | { Bad_Opcode }, | |
6c30d220 | 4899 | { VEX_W_TABLE (VEX_W_0FD8_P_2) }, |
c0f3af97 L |
4900 | }, |
4901 | ||
592a252b | 4902 | /* PREFIX_VEX_0FD9 */ |
c0f3af97 | 4903 | { |
592d1631 L |
4904 | { Bad_Opcode }, |
4905 | { Bad_Opcode }, | |
6c30d220 | 4906 | { VEX_W_TABLE (VEX_W_0FD9_P_2) }, |
c0f3af97 L |
4907 | }, |
4908 | ||
592a252b | 4909 | /* PREFIX_VEX_0FDA */ |
c0f3af97 | 4910 | { |
592d1631 L |
4911 | { Bad_Opcode }, |
4912 | { Bad_Opcode }, | |
6c30d220 | 4913 | { VEX_W_TABLE (VEX_W_0FDA_P_2) }, |
c0f3af97 L |
4914 | }, |
4915 | ||
592a252b | 4916 | /* PREFIX_VEX_0FDB */ |
c0f3af97 | 4917 | { |
592d1631 L |
4918 | { Bad_Opcode }, |
4919 | { Bad_Opcode }, | |
6c30d220 | 4920 | { VEX_W_TABLE (VEX_W_0FDB_P_2) }, |
c0f3af97 L |
4921 | }, |
4922 | ||
592a252b | 4923 | /* PREFIX_VEX_0FDC */ |
c0f3af97 | 4924 | { |
592d1631 L |
4925 | { Bad_Opcode }, |
4926 | { Bad_Opcode }, | |
6c30d220 | 4927 | { VEX_W_TABLE (VEX_W_0FDC_P_2) }, |
c0f3af97 L |
4928 | }, |
4929 | ||
592a252b | 4930 | /* PREFIX_VEX_0FDD */ |
c0f3af97 | 4931 | { |
592d1631 L |
4932 | { Bad_Opcode }, |
4933 | { Bad_Opcode }, | |
6c30d220 | 4934 | { VEX_W_TABLE (VEX_W_0FDD_P_2) }, |
c0f3af97 L |
4935 | }, |
4936 | ||
592a252b | 4937 | /* PREFIX_VEX_0FDE */ |
c0f3af97 | 4938 | { |
592d1631 L |
4939 | { Bad_Opcode }, |
4940 | { Bad_Opcode }, | |
6c30d220 | 4941 | { VEX_W_TABLE (VEX_W_0FDE_P_2) }, |
c0f3af97 L |
4942 | }, |
4943 | ||
592a252b | 4944 | /* PREFIX_VEX_0FDF */ |
c0f3af97 | 4945 | { |
592d1631 L |
4946 | { Bad_Opcode }, |
4947 | { Bad_Opcode }, | |
6c30d220 | 4948 | { VEX_W_TABLE (VEX_W_0FDF_P_2) }, |
c0f3af97 L |
4949 | }, |
4950 | ||
592a252b | 4951 | /* PREFIX_VEX_0FE0 */ |
c0f3af97 | 4952 | { |
592d1631 L |
4953 | { Bad_Opcode }, |
4954 | { Bad_Opcode }, | |
6c30d220 | 4955 | { VEX_W_TABLE (VEX_W_0FE0_P_2) }, |
c0f3af97 L |
4956 | }, |
4957 | ||
592a252b | 4958 | /* PREFIX_VEX_0FE1 */ |
c0f3af97 | 4959 | { |
592d1631 L |
4960 | { Bad_Opcode }, |
4961 | { Bad_Opcode }, | |
6c30d220 | 4962 | { VEX_W_TABLE (VEX_W_0FE1_P_2) }, |
c0f3af97 L |
4963 | }, |
4964 | ||
592a252b | 4965 | /* PREFIX_VEX_0FE2 */ |
c0f3af97 | 4966 | { |
592d1631 L |
4967 | { Bad_Opcode }, |
4968 | { Bad_Opcode }, | |
6c30d220 | 4969 | { VEX_W_TABLE (VEX_W_0FE2_P_2) }, |
c0f3af97 L |
4970 | }, |
4971 | ||
592a252b | 4972 | /* PREFIX_VEX_0FE3 */ |
c0f3af97 | 4973 | { |
592d1631 L |
4974 | { Bad_Opcode }, |
4975 | { Bad_Opcode }, | |
6c30d220 | 4976 | { VEX_W_TABLE (VEX_W_0FE3_P_2) }, |
c0f3af97 L |
4977 | }, |
4978 | ||
592a252b | 4979 | /* PREFIX_VEX_0FE4 */ |
c0f3af97 | 4980 | { |
592d1631 L |
4981 | { Bad_Opcode }, |
4982 | { Bad_Opcode }, | |
6c30d220 | 4983 | { VEX_W_TABLE (VEX_W_0FE4_P_2) }, |
c0f3af97 L |
4984 | }, |
4985 | ||
592a252b | 4986 | /* PREFIX_VEX_0FE5 */ |
c0f3af97 | 4987 | { |
592d1631 L |
4988 | { Bad_Opcode }, |
4989 | { Bad_Opcode }, | |
6c30d220 | 4990 | { VEX_W_TABLE (VEX_W_0FE5_P_2) }, |
c0f3af97 L |
4991 | }, |
4992 | ||
592a252b | 4993 | /* PREFIX_VEX_0FE6 */ |
c0f3af97 | 4994 | { |
592d1631 | 4995 | { Bad_Opcode }, |
592a252b L |
4996 | { VEX_W_TABLE (VEX_W_0FE6_P_1) }, |
4997 | { VEX_W_TABLE (VEX_W_0FE6_P_2) }, | |
4998 | { VEX_W_TABLE (VEX_W_0FE6_P_3) }, | |
c0f3af97 L |
4999 | }, |
5000 | ||
592a252b | 5001 | /* PREFIX_VEX_0FE7 */ |
c0f3af97 | 5002 | { |
592d1631 L |
5003 | { Bad_Opcode }, |
5004 | { Bad_Opcode }, | |
592a252b | 5005 | { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, |
c0f3af97 L |
5006 | }, |
5007 | ||
592a252b | 5008 | /* PREFIX_VEX_0FE8 */ |
c0f3af97 | 5009 | { |
592d1631 L |
5010 | { Bad_Opcode }, |
5011 | { Bad_Opcode }, | |
6c30d220 | 5012 | { VEX_W_TABLE (VEX_W_0FE8_P_2) }, |
c0f3af97 L |
5013 | }, |
5014 | ||
592a252b | 5015 | /* PREFIX_VEX_0FE9 */ |
c0f3af97 | 5016 | { |
592d1631 L |
5017 | { Bad_Opcode }, |
5018 | { Bad_Opcode }, | |
6c30d220 | 5019 | { VEX_W_TABLE (VEX_W_0FE9_P_2) }, |
c0f3af97 L |
5020 | }, |
5021 | ||
592a252b | 5022 | /* PREFIX_VEX_0FEA */ |
c0f3af97 | 5023 | { |
592d1631 L |
5024 | { Bad_Opcode }, |
5025 | { Bad_Opcode }, | |
6c30d220 | 5026 | { VEX_W_TABLE (VEX_W_0FEA_P_2) }, |
c0f3af97 L |
5027 | }, |
5028 | ||
592a252b | 5029 | /* PREFIX_VEX_0FEB */ |
c0f3af97 | 5030 | { |
592d1631 L |
5031 | { Bad_Opcode }, |
5032 | { Bad_Opcode }, | |
6c30d220 | 5033 | { VEX_W_TABLE (VEX_W_0FEB_P_2) }, |
c0f3af97 L |
5034 | }, |
5035 | ||
592a252b | 5036 | /* PREFIX_VEX_0FEC */ |
c0f3af97 | 5037 | { |
592d1631 L |
5038 | { Bad_Opcode }, |
5039 | { Bad_Opcode }, | |
6c30d220 | 5040 | { VEX_W_TABLE (VEX_W_0FEC_P_2) }, |
c0f3af97 L |
5041 | }, |
5042 | ||
592a252b | 5043 | /* PREFIX_VEX_0FED */ |
c0f3af97 | 5044 | { |
592d1631 L |
5045 | { Bad_Opcode }, |
5046 | { Bad_Opcode }, | |
6c30d220 | 5047 | { VEX_W_TABLE (VEX_W_0FED_P_2) }, |
c0f3af97 L |
5048 | }, |
5049 | ||
592a252b | 5050 | /* PREFIX_VEX_0FEE */ |
c0f3af97 | 5051 | { |
592d1631 L |
5052 | { Bad_Opcode }, |
5053 | { Bad_Opcode }, | |
6c30d220 | 5054 | { VEX_W_TABLE (VEX_W_0FEE_P_2) }, |
c0f3af97 L |
5055 | }, |
5056 | ||
592a252b | 5057 | /* PREFIX_VEX_0FEF */ |
c0f3af97 | 5058 | { |
592d1631 L |
5059 | { Bad_Opcode }, |
5060 | { Bad_Opcode }, | |
6c30d220 | 5061 | { VEX_W_TABLE (VEX_W_0FEF_P_2) }, |
c0f3af97 L |
5062 | }, |
5063 | ||
592a252b | 5064 | /* PREFIX_VEX_0FF0 */ |
c0f3af97 | 5065 | { |
592d1631 L |
5066 | { Bad_Opcode }, |
5067 | { Bad_Opcode }, | |
5068 | { Bad_Opcode }, | |
592a252b | 5069 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, |
c0f3af97 L |
5070 | }, |
5071 | ||
592a252b | 5072 | /* PREFIX_VEX_0FF1 */ |
c0f3af97 | 5073 | { |
592d1631 L |
5074 | { Bad_Opcode }, |
5075 | { Bad_Opcode }, | |
6c30d220 | 5076 | { VEX_W_TABLE (VEX_W_0FF1_P_2) }, |
c0f3af97 L |
5077 | }, |
5078 | ||
592a252b | 5079 | /* PREFIX_VEX_0FF2 */ |
c0f3af97 | 5080 | { |
592d1631 L |
5081 | { Bad_Opcode }, |
5082 | { Bad_Opcode }, | |
6c30d220 | 5083 | { VEX_W_TABLE (VEX_W_0FF2_P_2) }, |
c0f3af97 L |
5084 | }, |
5085 | ||
592a252b | 5086 | /* PREFIX_VEX_0FF3 */ |
c0f3af97 | 5087 | { |
592d1631 L |
5088 | { Bad_Opcode }, |
5089 | { Bad_Opcode }, | |
6c30d220 | 5090 | { VEX_W_TABLE (VEX_W_0FF3_P_2) }, |
c0f3af97 L |
5091 | }, |
5092 | ||
592a252b | 5093 | /* PREFIX_VEX_0FF4 */ |
c0f3af97 | 5094 | { |
592d1631 L |
5095 | { Bad_Opcode }, |
5096 | { Bad_Opcode }, | |
6c30d220 | 5097 | { VEX_W_TABLE (VEX_W_0FF4_P_2) }, |
c0f3af97 L |
5098 | }, |
5099 | ||
592a252b | 5100 | /* PREFIX_VEX_0FF5 */ |
c0f3af97 | 5101 | { |
592d1631 L |
5102 | { Bad_Opcode }, |
5103 | { Bad_Opcode }, | |
6c30d220 | 5104 | { VEX_W_TABLE (VEX_W_0FF5_P_2) }, |
c0f3af97 L |
5105 | }, |
5106 | ||
592a252b | 5107 | /* PREFIX_VEX_0FF6 */ |
c0f3af97 | 5108 | { |
592d1631 L |
5109 | { Bad_Opcode }, |
5110 | { Bad_Opcode }, | |
6c30d220 | 5111 | { VEX_W_TABLE (VEX_W_0FF6_P_2) }, |
c0f3af97 L |
5112 | }, |
5113 | ||
592a252b | 5114 | /* PREFIX_VEX_0FF7 */ |
c0f3af97 | 5115 | { |
592d1631 L |
5116 | { Bad_Opcode }, |
5117 | { Bad_Opcode }, | |
592a252b | 5118 | { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, |
c0f3af97 L |
5119 | }, |
5120 | ||
592a252b | 5121 | /* PREFIX_VEX_0FF8 */ |
c0f3af97 | 5122 | { |
592d1631 L |
5123 | { Bad_Opcode }, |
5124 | { Bad_Opcode }, | |
6c30d220 | 5125 | { VEX_W_TABLE (VEX_W_0FF8_P_2) }, |
c0f3af97 L |
5126 | }, |
5127 | ||
592a252b | 5128 | /* PREFIX_VEX_0FF9 */ |
c0f3af97 | 5129 | { |
592d1631 L |
5130 | { Bad_Opcode }, |
5131 | { Bad_Opcode }, | |
6c30d220 | 5132 | { VEX_W_TABLE (VEX_W_0FF9_P_2) }, |
c0f3af97 L |
5133 | }, |
5134 | ||
592a252b | 5135 | /* PREFIX_VEX_0FFA */ |
c0f3af97 | 5136 | { |
592d1631 L |
5137 | { Bad_Opcode }, |
5138 | { Bad_Opcode }, | |
6c30d220 | 5139 | { VEX_W_TABLE (VEX_W_0FFA_P_2) }, |
c0f3af97 L |
5140 | }, |
5141 | ||
592a252b | 5142 | /* PREFIX_VEX_0FFB */ |
c0f3af97 | 5143 | { |
592d1631 L |
5144 | { Bad_Opcode }, |
5145 | { Bad_Opcode }, | |
6c30d220 | 5146 | { VEX_W_TABLE (VEX_W_0FFB_P_2) }, |
c0f3af97 L |
5147 | }, |
5148 | ||
592a252b | 5149 | /* PREFIX_VEX_0FFC */ |
c0f3af97 | 5150 | { |
592d1631 L |
5151 | { Bad_Opcode }, |
5152 | { Bad_Opcode }, | |
6c30d220 | 5153 | { VEX_W_TABLE (VEX_W_0FFC_P_2) }, |
c0f3af97 L |
5154 | }, |
5155 | ||
592a252b | 5156 | /* PREFIX_VEX_0FFD */ |
c0f3af97 | 5157 | { |
592d1631 L |
5158 | { Bad_Opcode }, |
5159 | { Bad_Opcode }, | |
6c30d220 | 5160 | { VEX_W_TABLE (VEX_W_0FFD_P_2) }, |
c0f3af97 L |
5161 | }, |
5162 | ||
592a252b | 5163 | /* PREFIX_VEX_0FFE */ |
c0f3af97 | 5164 | { |
592d1631 L |
5165 | { Bad_Opcode }, |
5166 | { Bad_Opcode }, | |
6c30d220 | 5167 | { VEX_W_TABLE (VEX_W_0FFE_P_2) }, |
c0f3af97 L |
5168 | }, |
5169 | ||
592a252b | 5170 | /* PREFIX_VEX_0F3800 */ |
c0f3af97 | 5171 | { |
592d1631 L |
5172 | { Bad_Opcode }, |
5173 | { Bad_Opcode }, | |
6c30d220 | 5174 | { VEX_W_TABLE (VEX_W_0F3800_P_2) }, |
c0f3af97 L |
5175 | }, |
5176 | ||
592a252b | 5177 | /* PREFIX_VEX_0F3801 */ |
c0f3af97 | 5178 | { |
592d1631 L |
5179 | { Bad_Opcode }, |
5180 | { Bad_Opcode }, | |
6c30d220 | 5181 | { VEX_W_TABLE (VEX_W_0F3801_P_2) }, |
c0f3af97 L |
5182 | }, |
5183 | ||
592a252b | 5184 | /* PREFIX_VEX_0F3802 */ |
c0f3af97 | 5185 | { |
592d1631 L |
5186 | { Bad_Opcode }, |
5187 | { Bad_Opcode }, | |
6c30d220 | 5188 | { VEX_W_TABLE (VEX_W_0F3802_P_2) }, |
c0f3af97 L |
5189 | }, |
5190 | ||
592a252b | 5191 | /* PREFIX_VEX_0F3803 */ |
c0f3af97 | 5192 | { |
592d1631 L |
5193 | { Bad_Opcode }, |
5194 | { Bad_Opcode }, | |
6c30d220 | 5195 | { VEX_W_TABLE (VEX_W_0F3803_P_2) }, |
c0f3af97 L |
5196 | }, |
5197 | ||
592a252b | 5198 | /* PREFIX_VEX_0F3804 */ |
c0f3af97 | 5199 | { |
592d1631 L |
5200 | { Bad_Opcode }, |
5201 | { Bad_Opcode }, | |
6c30d220 | 5202 | { VEX_W_TABLE (VEX_W_0F3804_P_2) }, |
c0f3af97 L |
5203 | }, |
5204 | ||
592a252b | 5205 | /* PREFIX_VEX_0F3805 */ |
c0f3af97 | 5206 | { |
592d1631 L |
5207 | { Bad_Opcode }, |
5208 | { Bad_Opcode }, | |
6c30d220 | 5209 | { VEX_W_TABLE (VEX_W_0F3805_P_2) }, |
c0f3af97 L |
5210 | }, |
5211 | ||
592a252b | 5212 | /* PREFIX_VEX_0F3806 */ |
c0f3af97 | 5213 | { |
592d1631 L |
5214 | { Bad_Opcode }, |
5215 | { Bad_Opcode }, | |
6c30d220 | 5216 | { VEX_W_TABLE (VEX_W_0F3806_P_2) }, |
c0f3af97 L |
5217 | }, |
5218 | ||
592a252b | 5219 | /* PREFIX_VEX_0F3807 */ |
c0f3af97 | 5220 | { |
592d1631 L |
5221 | { Bad_Opcode }, |
5222 | { Bad_Opcode }, | |
6c30d220 | 5223 | { VEX_W_TABLE (VEX_W_0F3807_P_2) }, |
c0f3af97 L |
5224 | }, |
5225 | ||
592a252b | 5226 | /* PREFIX_VEX_0F3808 */ |
c0f3af97 | 5227 | { |
592d1631 L |
5228 | { Bad_Opcode }, |
5229 | { Bad_Opcode }, | |
6c30d220 | 5230 | { VEX_W_TABLE (VEX_W_0F3808_P_2) }, |
c0f3af97 L |
5231 | }, |
5232 | ||
592a252b | 5233 | /* PREFIX_VEX_0F3809 */ |
c0f3af97 | 5234 | { |
592d1631 L |
5235 | { Bad_Opcode }, |
5236 | { Bad_Opcode }, | |
6c30d220 | 5237 | { VEX_W_TABLE (VEX_W_0F3809_P_2) }, |
c0f3af97 L |
5238 | }, |
5239 | ||
592a252b | 5240 | /* PREFIX_VEX_0F380A */ |
c0f3af97 | 5241 | { |
592d1631 L |
5242 | { Bad_Opcode }, |
5243 | { Bad_Opcode }, | |
6c30d220 | 5244 | { VEX_W_TABLE (VEX_W_0F380A_P_2) }, |
c0f3af97 L |
5245 | }, |
5246 | ||
592a252b | 5247 | /* PREFIX_VEX_0F380B */ |
c0f3af97 | 5248 | { |
592d1631 L |
5249 | { Bad_Opcode }, |
5250 | { Bad_Opcode }, | |
6c30d220 | 5251 | { VEX_W_TABLE (VEX_W_0F380B_P_2) }, |
c0f3af97 L |
5252 | }, |
5253 | ||
592a252b | 5254 | /* PREFIX_VEX_0F380C */ |
c0f3af97 | 5255 | { |
592d1631 L |
5256 | { Bad_Opcode }, |
5257 | { Bad_Opcode }, | |
592a252b | 5258 | { VEX_W_TABLE (VEX_W_0F380C_P_2) }, |
c0f3af97 L |
5259 | }, |
5260 | ||
592a252b | 5261 | /* PREFIX_VEX_0F380D */ |
c0f3af97 | 5262 | { |
592d1631 L |
5263 | { Bad_Opcode }, |
5264 | { Bad_Opcode }, | |
592a252b | 5265 | { VEX_W_TABLE (VEX_W_0F380D_P_2) }, |
c0f3af97 L |
5266 | }, |
5267 | ||
592a252b | 5268 | /* PREFIX_VEX_0F380E */ |
c0f3af97 | 5269 | { |
592d1631 L |
5270 | { Bad_Opcode }, |
5271 | { Bad_Opcode }, | |
592a252b | 5272 | { VEX_W_TABLE (VEX_W_0F380E_P_2) }, |
c0f3af97 L |
5273 | }, |
5274 | ||
592a252b | 5275 | /* PREFIX_VEX_0F380F */ |
c0f3af97 | 5276 | { |
592d1631 L |
5277 | { Bad_Opcode }, |
5278 | { Bad_Opcode }, | |
592a252b | 5279 | { VEX_W_TABLE (VEX_W_0F380F_P_2) }, |
c0f3af97 L |
5280 | }, |
5281 | ||
592a252b | 5282 | /* PREFIX_VEX_0F3813 */ |
c7b8aa3a L |
5283 | { |
5284 | { Bad_Opcode }, | |
5285 | { Bad_Opcode }, | |
5286 | { "vcvtph2ps", { XM, EXxmmq } }, | |
5287 | }, | |
5288 | ||
6c30d220 L |
5289 | /* PREFIX_VEX_0F3816 */ |
5290 | { | |
5291 | { Bad_Opcode }, | |
5292 | { Bad_Opcode }, | |
5293 | { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) }, | |
5294 | }, | |
5295 | ||
592a252b | 5296 | /* PREFIX_VEX_0F3817 */ |
c0f3af97 | 5297 | { |
592d1631 L |
5298 | { Bad_Opcode }, |
5299 | { Bad_Opcode }, | |
592a252b | 5300 | { VEX_W_TABLE (VEX_W_0F3817_P_2) }, |
c0f3af97 L |
5301 | }, |
5302 | ||
592a252b | 5303 | /* PREFIX_VEX_0F3818 */ |
c0f3af97 | 5304 | { |
592d1631 L |
5305 | { Bad_Opcode }, |
5306 | { Bad_Opcode }, | |
6c30d220 | 5307 | { VEX_W_TABLE (VEX_W_0F3818_P_2) }, |
c0f3af97 L |
5308 | }, |
5309 | ||
592a252b | 5310 | /* PREFIX_VEX_0F3819 */ |
c0f3af97 | 5311 | { |
592d1631 L |
5312 | { Bad_Opcode }, |
5313 | { Bad_Opcode }, | |
6c30d220 | 5314 | { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) }, |
c0f3af97 L |
5315 | }, |
5316 | ||
592a252b | 5317 | /* PREFIX_VEX_0F381A */ |
c0f3af97 | 5318 | { |
592d1631 L |
5319 | { Bad_Opcode }, |
5320 | { Bad_Opcode }, | |
592a252b | 5321 | { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, |
c0f3af97 L |
5322 | }, |
5323 | ||
592a252b | 5324 | /* PREFIX_VEX_0F381C */ |
c0f3af97 | 5325 | { |
592d1631 L |
5326 | { Bad_Opcode }, |
5327 | { Bad_Opcode }, | |
6c30d220 | 5328 | { VEX_W_TABLE (VEX_W_0F381C_P_2) }, |
c0f3af97 L |
5329 | }, |
5330 | ||
592a252b | 5331 | /* PREFIX_VEX_0F381D */ |
c0f3af97 | 5332 | { |
592d1631 L |
5333 | { Bad_Opcode }, |
5334 | { Bad_Opcode }, | |
6c30d220 | 5335 | { VEX_W_TABLE (VEX_W_0F381D_P_2) }, |
c0f3af97 L |
5336 | }, |
5337 | ||
592a252b | 5338 | /* PREFIX_VEX_0F381E */ |
c0f3af97 | 5339 | { |
592d1631 L |
5340 | { Bad_Opcode }, |
5341 | { Bad_Opcode }, | |
6c30d220 | 5342 | { VEX_W_TABLE (VEX_W_0F381E_P_2) }, |
c0f3af97 L |
5343 | }, |
5344 | ||
592a252b | 5345 | /* PREFIX_VEX_0F3820 */ |
c0f3af97 | 5346 | { |
592d1631 L |
5347 | { Bad_Opcode }, |
5348 | { Bad_Opcode }, | |
6c30d220 | 5349 | { VEX_W_TABLE (VEX_W_0F3820_P_2) }, |
c0f3af97 L |
5350 | }, |
5351 | ||
592a252b | 5352 | /* PREFIX_VEX_0F3821 */ |
c0f3af97 | 5353 | { |
592d1631 L |
5354 | { Bad_Opcode }, |
5355 | { Bad_Opcode }, | |
6c30d220 | 5356 | { VEX_W_TABLE (VEX_W_0F3821_P_2) }, |
c0f3af97 L |
5357 | }, |
5358 | ||
592a252b | 5359 | /* PREFIX_VEX_0F3822 */ |
c0f3af97 | 5360 | { |
592d1631 L |
5361 | { Bad_Opcode }, |
5362 | { Bad_Opcode }, | |
6c30d220 | 5363 | { VEX_W_TABLE (VEX_W_0F3822_P_2) }, |
c0f3af97 L |
5364 | }, |
5365 | ||
592a252b | 5366 | /* PREFIX_VEX_0F3823 */ |
c0f3af97 | 5367 | { |
592d1631 L |
5368 | { Bad_Opcode }, |
5369 | { Bad_Opcode }, | |
6c30d220 | 5370 | { VEX_W_TABLE (VEX_W_0F3823_P_2) }, |
c0f3af97 L |
5371 | }, |
5372 | ||
592a252b | 5373 | /* PREFIX_VEX_0F3824 */ |
c0f3af97 | 5374 | { |
592d1631 L |
5375 | { Bad_Opcode }, |
5376 | { Bad_Opcode }, | |
6c30d220 | 5377 | { VEX_W_TABLE (VEX_W_0F3824_P_2) }, |
c0f3af97 L |
5378 | }, |
5379 | ||
592a252b | 5380 | /* PREFIX_VEX_0F3825 */ |
c0f3af97 | 5381 | { |
592d1631 L |
5382 | { Bad_Opcode }, |
5383 | { Bad_Opcode }, | |
6c30d220 | 5384 | { VEX_W_TABLE (VEX_W_0F3825_P_2) }, |
c0f3af97 L |
5385 | }, |
5386 | ||
592a252b | 5387 | /* PREFIX_VEX_0F3828 */ |
c0f3af97 | 5388 | { |
592d1631 L |
5389 | { Bad_Opcode }, |
5390 | { Bad_Opcode }, | |
6c30d220 | 5391 | { VEX_W_TABLE (VEX_W_0F3828_P_2) }, |
c0f3af97 L |
5392 | }, |
5393 | ||
592a252b | 5394 | /* PREFIX_VEX_0F3829 */ |
c0f3af97 | 5395 | { |
592d1631 L |
5396 | { Bad_Opcode }, |
5397 | { Bad_Opcode }, | |
6c30d220 | 5398 | { VEX_W_TABLE (VEX_W_0F3829_P_2) }, |
c0f3af97 L |
5399 | }, |
5400 | ||
592a252b | 5401 | /* PREFIX_VEX_0F382A */ |
c0f3af97 | 5402 | { |
592d1631 L |
5403 | { Bad_Opcode }, |
5404 | { Bad_Opcode }, | |
592a252b | 5405 | { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, |
c0f3af97 L |
5406 | }, |
5407 | ||
592a252b | 5408 | /* PREFIX_VEX_0F382B */ |
c0f3af97 | 5409 | { |
592d1631 L |
5410 | { Bad_Opcode }, |
5411 | { Bad_Opcode }, | |
6c30d220 | 5412 | { VEX_W_TABLE (VEX_W_0F382B_P_2) }, |
c0f3af97 L |
5413 | }, |
5414 | ||
592a252b | 5415 | /* PREFIX_VEX_0F382C */ |
c0f3af97 | 5416 | { |
592d1631 L |
5417 | { Bad_Opcode }, |
5418 | { Bad_Opcode }, | |
592a252b | 5419 | { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, |
c0f3af97 L |
5420 | }, |
5421 | ||
592a252b | 5422 | /* PREFIX_VEX_0F382D */ |
c0f3af97 | 5423 | { |
592d1631 L |
5424 | { Bad_Opcode }, |
5425 | { Bad_Opcode }, | |
592a252b | 5426 | { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, |
c0f3af97 L |
5427 | }, |
5428 | ||
592a252b | 5429 | /* PREFIX_VEX_0F382E */ |
c0f3af97 | 5430 | { |
592d1631 L |
5431 | { Bad_Opcode }, |
5432 | { Bad_Opcode }, | |
592a252b | 5433 | { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, |
c0f3af97 L |
5434 | }, |
5435 | ||
592a252b | 5436 | /* PREFIX_VEX_0F382F */ |
c0f3af97 | 5437 | { |
592d1631 L |
5438 | { Bad_Opcode }, |
5439 | { Bad_Opcode }, | |
592a252b | 5440 | { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, |
c0f3af97 L |
5441 | }, |
5442 | ||
592a252b | 5443 | /* PREFIX_VEX_0F3830 */ |
c0f3af97 | 5444 | { |
592d1631 L |
5445 | { Bad_Opcode }, |
5446 | { Bad_Opcode }, | |
6c30d220 | 5447 | { VEX_W_TABLE (VEX_W_0F3830_P_2) }, |
c0f3af97 L |
5448 | }, |
5449 | ||
592a252b | 5450 | /* PREFIX_VEX_0F3831 */ |
c0f3af97 | 5451 | { |
592d1631 L |
5452 | { Bad_Opcode }, |
5453 | { Bad_Opcode }, | |
6c30d220 | 5454 | { VEX_W_TABLE (VEX_W_0F3831_P_2) }, |
c0f3af97 L |
5455 | }, |
5456 | ||
592a252b | 5457 | /* PREFIX_VEX_0F3832 */ |
c0f3af97 | 5458 | { |
592d1631 L |
5459 | { Bad_Opcode }, |
5460 | { Bad_Opcode }, | |
6c30d220 | 5461 | { VEX_W_TABLE (VEX_W_0F3832_P_2) }, |
c0f3af97 L |
5462 | }, |
5463 | ||
592a252b | 5464 | /* PREFIX_VEX_0F3833 */ |
c0f3af97 | 5465 | { |
592d1631 L |
5466 | { Bad_Opcode }, |
5467 | { Bad_Opcode }, | |
6c30d220 | 5468 | { VEX_W_TABLE (VEX_W_0F3833_P_2) }, |
c0f3af97 L |
5469 | }, |
5470 | ||
592a252b | 5471 | /* PREFIX_VEX_0F3834 */ |
c0f3af97 | 5472 | { |
592d1631 L |
5473 | { Bad_Opcode }, |
5474 | { Bad_Opcode }, | |
6c30d220 | 5475 | { VEX_W_TABLE (VEX_W_0F3834_P_2) }, |
c0f3af97 L |
5476 | }, |
5477 | ||
592a252b | 5478 | /* PREFIX_VEX_0F3835 */ |
c0f3af97 | 5479 | { |
592d1631 L |
5480 | { Bad_Opcode }, |
5481 | { Bad_Opcode }, | |
6c30d220 L |
5482 | { VEX_W_TABLE (VEX_W_0F3835_P_2) }, |
5483 | }, | |
5484 | ||
5485 | /* PREFIX_VEX_0F3836 */ | |
5486 | { | |
5487 | { Bad_Opcode }, | |
5488 | { Bad_Opcode }, | |
5489 | { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) }, | |
c0f3af97 L |
5490 | }, |
5491 | ||
592a252b | 5492 | /* PREFIX_VEX_0F3837 */ |
c0f3af97 | 5493 | { |
592d1631 L |
5494 | { Bad_Opcode }, |
5495 | { Bad_Opcode }, | |
6c30d220 | 5496 | { VEX_W_TABLE (VEX_W_0F3837_P_2) }, |
c0f3af97 L |
5497 | }, |
5498 | ||
592a252b | 5499 | /* PREFIX_VEX_0F3838 */ |
c0f3af97 | 5500 | { |
592d1631 L |
5501 | { Bad_Opcode }, |
5502 | { Bad_Opcode }, | |
6c30d220 | 5503 | { VEX_W_TABLE (VEX_W_0F3838_P_2) }, |
c0f3af97 L |
5504 | }, |
5505 | ||
592a252b | 5506 | /* PREFIX_VEX_0F3839 */ |
c0f3af97 | 5507 | { |
592d1631 L |
5508 | { Bad_Opcode }, |
5509 | { Bad_Opcode }, | |
6c30d220 | 5510 | { VEX_W_TABLE (VEX_W_0F3839_P_2) }, |
c0f3af97 L |
5511 | }, |
5512 | ||
592a252b | 5513 | /* PREFIX_VEX_0F383A */ |
c0f3af97 | 5514 | { |
592d1631 L |
5515 | { Bad_Opcode }, |
5516 | { Bad_Opcode }, | |
6c30d220 | 5517 | { VEX_W_TABLE (VEX_W_0F383A_P_2) }, |
c0f3af97 L |
5518 | }, |
5519 | ||
592a252b | 5520 | /* PREFIX_VEX_0F383B */ |
c0f3af97 | 5521 | { |
592d1631 L |
5522 | { Bad_Opcode }, |
5523 | { Bad_Opcode }, | |
6c30d220 | 5524 | { VEX_W_TABLE (VEX_W_0F383B_P_2) }, |
c0f3af97 L |
5525 | }, |
5526 | ||
592a252b | 5527 | /* PREFIX_VEX_0F383C */ |
c0f3af97 | 5528 | { |
592d1631 L |
5529 | { Bad_Opcode }, |
5530 | { Bad_Opcode }, | |
6c30d220 | 5531 | { VEX_W_TABLE (VEX_W_0F383C_P_2) }, |
c0f3af97 L |
5532 | }, |
5533 | ||
592a252b | 5534 | /* PREFIX_VEX_0F383D */ |
c0f3af97 | 5535 | { |
592d1631 L |
5536 | { Bad_Opcode }, |
5537 | { Bad_Opcode }, | |
6c30d220 | 5538 | { VEX_W_TABLE (VEX_W_0F383D_P_2) }, |
c0f3af97 L |
5539 | }, |
5540 | ||
592a252b | 5541 | /* PREFIX_VEX_0F383E */ |
c0f3af97 | 5542 | { |
592d1631 L |
5543 | { Bad_Opcode }, |
5544 | { Bad_Opcode }, | |
6c30d220 | 5545 | { VEX_W_TABLE (VEX_W_0F383E_P_2) }, |
c0f3af97 L |
5546 | }, |
5547 | ||
592a252b | 5548 | /* PREFIX_VEX_0F383F */ |
c0f3af97 | 5549 | { |
592d1631 L |
5550 | { Bad_Opcode }, |
5551 | { Bad_Opcode }, | |
6c30d220 | 5552 | { VEX_W_TABLE (VEX_W_0F383F_P_2) }, |
c0f3af97 L |
5553 | }, |
5554 | ||
592a252b | 5555 | /* PREFIX_VEX_0F3840 */ |
c0f3af97 | 5556 | { |
592d1631 L |
5557 | { Bad_Opcode }, |
5558 | { Bad_Opcode }, | |
6c30d220 | 5559 | { VEX_W_TABLE (VEX_W_0F3840_P_2) }, |
c0f3af97 L |
5560 | }, |
5561 | ||
592a252b | 5562 | /* PREFIX_VEX_0F3841 */ |
c0f3af97 | 5563 | { |
592d1631 L |
5564 | { Bad_Opcode }, |
5565 | { Bad_Opcode }, | |
592a252b | 5566 | { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, |
c0f3af97 L |
5567 | }, |
5568 | ||
6c30d220 L |
5569 | /* PREFIX_VEX_0F3845 */ |
5570 | { | |
5571 | { Bad_Opcode }, | |
5572 | { Bad_Opcode }, | |
5573 | { "vpsrlv%LW", { XM, Vex, EXx } }, | |
5574 | }, | |
5575 | ||
5576 | /* PREFIX_VEX_0F3846 */ | |
5577 | { | |
5578 | { Bad_Opcode }, | |
5579 | { Bad_Opcode }, | |
5580 | { VEX_W_TABLE (VEX_W_0F3846_P_2) }, | |
5581 | }, | |
5582 | ||
5583 | /* PREFIX_VEX_0F3847 */ | |
5584 | { | |
5585 | { Bad_Opcode }, | |
5586 | { Bad_Opcode }, | |
5587 | { "vpsllv%LW", { XM, Vex, EXx } }, | |
5588 | }, | |
5589 | ||
5590 | /* PREFIX_VEX_0F3858 */ | |
5591 | { | |
5592 | { Bad_Opcode }, | |
5593 | { Bad_Opcode }, | |
5594 | { VEX_W_TABLE (VEX_W_0F3858_P_2) }, | |
5595 | }, | |
5596 | ||
5597 | /* PREFIX_VEX_0F3859 */ | |
5598 | { | |
5599 | { Bad_Opcode }, | |
5600 | { Bad_Opcode }, | |
5601 | { VEX_W_TABLE (VEX_W_0F3859_P_2) }, | |
5602 | }, | |
5603 | ||
5604 | /* PREFIX_VEX_0F385A */ | |
5605 | { | |
5606 | { Bad_Opcode }, | |
5607 | { Bad_Opcode }, | |
5608 | { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) }, | |
5609 | }, | |
5610 | ||
5611 | /* PREFIX_VEX_0F3878 */ | |
5612 | { | |
5613 | { Bad_Opcode }, | |
5614 | { Bad_Opcode }, | |
5615 | { VEX_W_TABLE (VEX_W_0F3878_P_2) }, | |
5616 | }, | |
5617 | ||
5618 | /* PREFIX_VEX_0F3879 */ | |
5619 | { | |
5620 | { Bad_Opcode }, | |
5621 | { Bad_Opcode }, | |
5622 | { VEX_W_TABLE (VEX_W_0F3879_P_2) }, | |
5623 | }, | |
5624 | ||
5625 | /* PREFIX_VEX_0F388C */ | |
5626 | { | |
5627 | { Bad_Opcode }, | |
5628 | { Bad_Opcode }, | |
f7002f42 | 5629 | { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) }, |
6c30d220 L |
5630 | }, |
5631 | ||
5632 | /* PREFIX_VEX_0F388E */ | |
5633 | { | |
5634 | { Bad_Opcode }, | |
5635 | { Bad_Opcode }, | |
f7002f42 | 5636 | { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) }, |
6c30d220 L |
5637 | }, |
5638 | ||
5639 | /* PREFIX_VEX_0F3890 */ | |
5640 | { | |
5641 | { Bad_Opcode }, | |
5642 | { Bad_Opcode }, | |
5643 | { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } }, | |
5644 | }, | |
5645 | ||
5646 | /* PREFIX_VEX_0F3891 */ | |
5647 | { | |
5648 | { Bad_Opcode }, | |
5649 | { Bad_Opcode }, | |
5650 | { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } }, | |
5651 | }, | |
5652 | ||
5653 | /* PREFIX_VEX_0F3892 */ | |
5654 | { | |
5655 | { Bad_Opcode }, | |
5656 | { Bad_Opcode }, | |
5657 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } }, | |
5658 | }, | |
5659 | ||
5660 | /* PREFIX_VEX_0F3893 */ | |
5661 | { | |
5662 | { Bad_Opcode }, | |
5663 | { Bad_Opcode }, | |
5664 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } }, | |
5665 | }, | |
5666 | ||
592a252b | 5667 | /* PREFIX_VEX_0F3896 */ |
a5ff0eb2 | 5668 | { |
592d1631 L |
5669 | { Bad_Opcode }, |
5670 | { Bad_Opcode }, | |
0bfee649 | 5671 | { "vfmaddsub132p%XW", { XM, Vex, EXx } }, |
a5ff0eb2 L |
5672 | }, |
5673 | ||
592a252b | 5674 | /* PREFIX_VEX_0F3897 */ |
a5ff0eb2 | 5675 | { |
592d1631 L |
5676 | { Bad_Opcode }, |
5677 | { Bad_Opcode }, | |
0bfee649 | 5678 | { "vfmsubadd132p%XW", { XM, Vex, EXx } }, |
a5ff0eb2 L |
5679 | }, |
5680 | ||
592a252b | 5681 | /* PREFIX_VEX_0F3898 */ |
a5ff0eb2 | 5682 | { |
592d1631 L |
5683 | { Bad_Opcode }, |
5684 | { Bad_Opcode }, | |
0bfee649 | 5685 | { "vfmadd132p%XW", { XM, Vex, EXx } }, |
a5ff0eb2 L |
5686 | }, |
5687 | ||
592a252b | 5688 | /* PREFIX_VEX_0F3899 */ |
a5ff0eb2 | 5689 | { |
592d1631 L |
5690 | { Bad_Opcode }, |
5691 | { Bad_Opcode }, | |
1c480963 | 5692 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
a5ff0eb2 L |
5693 | }, |
5694 | ||
592a252b | 5695 | /* PREFIX_VEX_0F389A */ |
a5ff0eb2 | 5696 | { |
592d1631 L |
5697 | { Bad_Opcode }, |
5698 | { Bad_Opcode }, | |
0bfee649 | 5699 | { "vfmsub132p%XW", { XM, Vex, EXx } }, |
a5ff0eb2 L |
5700 | }, |
5701 | ||
592a252b | 5702 | /* PREFIX_VEX_0F389B */ |
c0f3af97 | 5703 | { |
592d1631 L |
5704 | { Bad_Opcode }, |
5705 | { Bad_Opcode }, | |
1c480963 | 5706 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5707 | }, |
5708 | ||
592a252b | 5709 | /* PREFIX_VEX_0F389C */ |
c0f3af97 | 5710 | { |
592d1631 L |
5711 | { Bad_Opcode }, |
5712 | { Bad_Opcode }, | |
0bfee649 | 5713 | { "vfnmadd132p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5714 | }, |
5715 | ||
592a252b | 5716 | /* PREFIX_VEX_0F389D */ |
c0f3af97 | 5717 | { |
592d1631 L |
5718 | { Bad_Opcode }, |
5719 | { Bad_Opcode }, | |
1c480963 | 5720 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5721 | }, |
5722 | ||
592a252b | 5723 | /* PREFIX_VEX_0F389E */ |
c0f3af97 | 5724 | { |
592d1631 L |
5725 | { Bad_Opcode }, |
5726 | { Bad_Opcode }, | |
0bfee649 | 5727 | { "vfnmsub132p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5728 | }, |
5729 | ||
592a252b | 5730 | /* PREFIX_VEX_0F389F */ |
c0f3af97 | 5731 | { |
592d1631 L |
5732 | { Bad_Opcode }, |
5733 | { Bad_Opcode }, | |
1c480963 | 5734 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5735 | }, |
5736 | ||
592a252b | 5737 | /* PREFIX_VEX_0F38A6 */ |
c0f3af97 | 5738 | { |
592d1631 L |
5739 | { Bad_Opcode }, |
5740 | { Bad_Opcode }, | |
0bfee649 | 5741 | { "vfmaddsub213p%XW", { XM, Vex, EXx } }, |
592d1631 | 5742 | { Bad_Opcode }, |
c0f3af97 L |
5743 | }, |
5744 | ||
592a252b | 5745 | /* PREFIX_VEX_0F38A7 */ |
c0f3af97 | 5746 | { |
592d1631 L |
5747 | { Bad_Opcode }, |
5748 | { Bad_Opcode }, | |
0bfee649 | 5749 | { "vfmsubadd213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5750 | }, |
5751 | ||
592a252b | 5752 | /* PREFIX_VEX_0F38A8 */ |
c0f3af97 | 5753 | { |
592d1631 L |
5754 | { Bad_Opcode }, |
5755 | { Bad_Opcode }, | |
0bfee649 | 5756 | { "vfmadd213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5757 | }, |
5758 | ||
592a252b | 5759 | /* PREFIX_VEX_0F38A9 */ |
c0f3af97 | 5760 | { |
592d1631 L |
5761 | { Bad_Opcode }, |
5762 | { Bad_Opcode }, | |
1c480963 | 5763 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5764 | }, |
5765 | ||
592a252b | 5766 | /* PREFIX_VEX_0F38AA */ |
c0f3af97 | 5767 | { |
592d1631 L |
5768 | { Bad_Opcode }, |
5769 | { Bad_Opcode }, | |
0bfee649 | 5770 | { "vfmsub213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5771 | }, |
5772 | ||
592a252b | 5773 | /* PREFIX_VEX_0F38AB */ |
c0f3af97 | 5774 | { |
592d1631 L |
5775 | { Bad_Opcode }, |
5776 | { Bad_Opcode }, | |
1c480963 | 5777 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5778 | }, |
5779 | ||
592a252b | 5780 | /* PREFIX_VEX_0F38AC */ |
c0f3af97 | 5781 | { |
592d1631 L |
5782 | { Bad_Opcode }, |
5783 | { Bad_Opcode }, | |
0bfee649 | 5784 | { "vfnmadd213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5785 | }, |
5786 | ||
592a252b | 5787 | /* PREFIX_VEX_0F38AD */ |
c0f3af97 | 5788 | { |
592d1631 L |
5789 | { Bad_Opcode }, |
5790 | { Bad_Opcode }, | |
1c480963 | 5791 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5792 | }, |
5793 | ||
592a252b | 5794 | /* PREFIX_VEX_0F38AE */ |
c0f3af97 | 5795 | { |
592d1631 L |
5796 | { Bad_Opcode }, |
5797 | { Bad_Opcode }, | |
0bfee649 | 5798 | { "vfnmsub213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5799 | }, |
5800 | ||
592a252b | 5801 | /* PREFIX_VEX_0F38AF */ |
c0f3af97 | 5802 | { |
592d1631 L |
5803 | { Bad_Opcode }, |
5804 | { Bad_Opcode }, | |
1c480963 | 5805 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5806 | }, |
5807 | ||
592a252b | 5808 | /* PREFIX_VEX_0F38B6 */ |
c0f3af97 | 5809 | { |
592d1631 L |
5810 | { Bad_Opcode }, |
5811 | { Bad_Opcode }, | |
0bfee649 | 5812 | { "vfmaddsub231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5813 | }, |
5814 | ||
592a252b | 5815 | /* PREFIX_VEX_0F38B7 */ |
c0f3af97 | 5816 | { |
592d1631 L |
5817 | { Bad_Opcode }, |
5818 | { Bad_Opcode }, | |
0bfee649 | 5819 | { "vfmsubadd231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5820 | }, |
5821 | ||
592a252b | 5822 | /* PREFIX_VEX_0F38B8 */ |
c0f3af97 | 5823 | { |
592d1631 L |
5824 | { Bad_Opcode }, |
5825 | { Bad_Opcode }, | |
0bfee649 | 5826 | { "vfmadd231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5827 | }, |
5828 | ||
592a252b | 5829 | /* PREFIX_VEX_0F38B9 */ |
c0f3af97 | 5830 | { |
592d1631 L |
5831 | { Bad_Opcode }, |
5832 | { Bad_Opcode }, | |
1c480963 | 5833 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5834 | }, |
5835 | ||
592a252b | 5836 | /* PREFIX_VEX_0F38BA */ |
c0f3af97 | 5837 | { |
592d1631 L |
5838 | { Bad_Opcode }, |
5839 | { Bad_Opcode }, | |
0bfee649 | 5840 | { "vfmsub231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5841 | }, |
5842 | ||
592a252b | 5843 | /* PREFIX_VEX_0F38BB */ |
c0f3af97 | 5844 | { |
592d1631 L |
5845 | { Bad_Opcode }, |
5846 | { Bad_Opcode }, | |
1c480963 | 5847 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5848 | }, |
5849 | ||
592a252b | 5850 | /* PREFIX_VEX_0F38BC */ |
c0f3af97 | 5851 | { |
592d1631 L |
5852 | { Bad_Opcode }, |
5853 | { Bad_Opcode }, | |
0bfee649 | 5854 | { "vfnmadd231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5855 | }, |
5856 | ||
592a252b | 5857 | /* PREFIX_VEX_0F38BD */ |
c0f3af97 | 5858 | { |
592d1631 L |
5859 | { Bad_Opcode }, |
5860 | { Bad_Opcode }, | |
1c480963 | 5861 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5862 | }, |
5863 | ||
592a252b | 5864 | /* PREFIX_VEX_0F38BE */ |
c0f3af97 | 5865 | { |
592d1631 L |
5866 | { Bad_Opcode }, |
5867 | { Bad_Opcode }, | |
0bfee649 | 5868 | { "vfnmsub231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5869 | }, |
5870 | ||
592a252b | 5871 | /* PREFIX_VEX_0F38BF */ |
c0f3af97 | 5872 | { |
592d1631 L |
5873 | { Bad_Opcode }, |
5874 | { Bad_Opcode }, | |
1c480963 | 5875 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5876 | }, |
5877 | ||
592a252b | 5878 | /* PREFIX_VEX_0F38DB */ |
c0f3af97 | 5879 | { |
592d1631 L |
5880 | { Bad_Opcode }, |
5881 | { Bad_Opcode }, | |
592a252b | 5882 | { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, |
c0f3af97 L |
5883 | }, |
5884 | ||
592a252b | 5885 | /* PREFIX_VEX_0F38DC */ |
c0f3af97 | 5886 | { |
592d1631 L |
5887 | { Bad_Opcode }, |
5888 | { Bad_Opcode }, | |
592a252b | 5889 | { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) }, |
c0f3af97 L |
5890 | }, |
5891 | ||
592a252b | 5892 | /* PREFIX_VEX_0F38DD */ |
c0f3af97 | 5893 | { |
592d1631 L |
5894 | { Bad_Opcode }, |
5895 | { Bad_Opcode }, | |
592a252b | 5896 | { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) }, |
c0f3af97 L |
5897 | }, |
5898 | ||
592a252b | 5899 | /* PREFIX_VEX_0F38DE */ |
c0f3af97 | 5900 | { |
592d1631 L |
5901 | { Bad_Opcode }, |
5902 | { Bad_Opcode }, | |
592a252b | 5903 | { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) }, |
c0f3af97 L |
5904 | }, |
5905 | ||
592a252b | 5906 | /* PREFIX_VEX_0F38DF */ |
c0f3af97 | 5907 | { |
592d1631 L |
5908 | { Bad_Opcode }, |
5909 | { Bad_Opcode }, | |
592a252b | 5910 | { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) }, |
c0f3af97 L |
5911 | }, |
5912 | ||
f12dc422 L |
5913 | /* PREFIX_VEX_0F38F2 */ |
5914 | { | |
5915 | { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, | |
5916 | }, | |
5917 | ||
5918 | /* PREFIX_VEX_0F38F3_REG_1 */ | |
5919 | { | |
5920 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, | |
5921 | }, | |
5922 | ||
5923 | /* PREFIX_VEX_0F38F3_REG_2 */ | |
5924 | { | |
5925 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, | |
5926 | }, | |
5927 | ||
5928 | /* PREFIX_VEX_0F38F3_REG_3 */ | |
5929 | { | |
5930 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, | |
5931 | }, | |
5932 | ||
6c30d220 L |
5933 | /* PREFIX_VEX_0F38F5 */ |
5934 | { | |
5935 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, | |
5936 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, | |
5937 | { Bad_Opcode }, | |
5938 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, | |
5939 | }, | |
5940 | ||
5941 | /* PREFIX_VEX_0F38F6 */ | |
5942 | { | |
5943 | { Bad_Opcode }, | |
5944 | { Bad_Opcode }, | |
5945 | { Bad_Opcode }, | |
5946 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, | |
5947 | }, | |
5948 | ||
f12dc422 L |
5949 | /* PREFIX_VEX_0F38F7 */ |
5950 | { | |
5951 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, | |
6c30d220 L |
5952 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, |
5953 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, | |
5954 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, | |
5955 | }, | |
5956 | ||
5957 | /* PREFIX_VEX_0F3A00 */ | |
5958 | { | |
5959 | { Bad_Opcode }, | |
5960 | { Bad_Opcode }, | |
5961 | { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) }, | |
5962 | }, | |
5963 | ||
5964 | /* PREFIX_VEX_0F3A01 */ | |
5965 | { | |
5966 | { Bad_Opcode }, | |
5967 | { Bad_Opcode }, | |
5968 | { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) }, | |
5969 | }, | |
5970 | ||
5971 | /* PREFIX_VEX_0F3A02 */ | |
5972 | { | |
5973 | { Bad_Opcode }, | |
5974 | { Bad_Opcode }, | |
5975 | { VEX_W_TABLE (VEX_W_0F3A02_P_2) }, | |
f12dc422 L |
5976 | }, |
5977 | ||
592a252b | 5978 | /* PREFIX_VEX_0F3A04 */ |
c0f3af97 | 5979 | { |
592d1631 L |
5980 | { Bad_Opcode }, |
5981 | { Bad_Opcode }, | |
592a252b | 5982 | { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, |
c0f3af97 L |
5983 | }, |
5984 | ||
592a252b | 5985 | /* PREFIX_VEX_0F3A05 */ |
c0f3af97 | 5986 | { |
592d1631 L |
5987 | { Bad_Opcode }, |
5988 | { Bad_Opcode }, | |
592a252b | 5989 | { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, |
c0f3af97 L |
5990 | }, |
5991 | ||
592a252b | 5992 | /* PREFIX_VEX_0F3A06 */ |
c0f3af97 | 5993 | { |
592d1631 L |
5994 | { Bad_Opcode }, |
5995 | { Bad_Opcode }, | |
592a252b | 5996 | { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, |
c0f3af97 L |
5997 | }, |
5998 | ||
592a252b | 5999 | /* PREFIX_VEX_0F3A08 */ |
c0f3af97 | 6000 | { |
592d1631 L |
6001 | { Bad_Opcode }, |
6002 | { Bad_Opcode }, | |
592a252b | 6003 | { VEX_W_TABLE (VEX_W_0F3A08_P_2) }, |
c0f3af97 L |
6004 | }, |
6005 | ||
592a252b | 6006 | /* PREFIX_VEX_0F3A09 */ |
c0f3af97 | 6007 | { |
592d1631 L |
6008 | { Bad_Opcode }, |
6009 | { Bad_Opcode }, | |
592a252b | 6010 | { VEX_W_TABLE (VEX_W_0F3A09_P_2) }, |
c0f3af97 L |
6011 | }, |
6012 | ||
592a252b | 6013 | /* PREFIX_VEX_0F3A0A */ |
c0f3af97 | 6014 | { |
592d1631 L |
6015 | { Bad_Opcode }, |
6016 | { Bad_Opcode }, | |
592a252b | 6017 | { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) }, |
0bfee649 L |
6018 | }, |
6019 | ||
592a252b | 6020 | /* PREFIX_VEX_0F3A0B */ |
0bfee649 | 6021 | { |
592d1631 L |
6022 | { Bad_Opcode }, |
6023 | { Bad_Opcode }, | |
592a252b | 6024 | { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) }, |
0bfee649 L |
6025 | }, |
6026 | ||
592a252b | 6027 | /* PREFIX_VEX_0F3A0C */ |
0bfee649 | 6028 | { |
592d1631 L |
6029 | { Bad_Opcode }, |
6030 | { Bad_Opcode }, | |
592a252b | 6031 | { VEX_W_TABLE (VEX_W_0F3A0C_P_2) }, |
0bfee649 L |
6032 | }, |
6033 | ||
592a252b | 6034 | /* PREFIX_VEX_0F3A0D */ |
0bfee649 | 6035 | { |
592d1631 L |
6036 | { Bad_Opcode }, |
6037 | { Bad_Opcode }, | |
592a252b | 6038 | { VEX_W_TABLE (VEX_W_0F3A0D_P_2) }, |
c0f3af97 L |
6039 | }, |
6040 | ||
592a252b | 6041 | /* PREFIX_VEX_0F3A0E */ |
0bfee649 | 6042 | { |
592d1631 L |
6043 | { Bad_Opcode }, |
6044 | { Bad_Opcode }, | |
6c30d220 | 6045 | { VEX_W_TABLE (VEX_W_0F3A0E_P_2) }, |
0bfee649 L |
6046 | }, |
6047 | ||
592a252b | 6048 | /* PREFIX_VEX_0F3A0F */ |
0bfee649 | 6049 | { |
592d1631 L |
6050 | { Bad_Opcode }, |
6051 | { Bad_Opcode }, | |
6c30d220 | 6052 | { VEX_W_TABLE (VEX_W_0F3A0F_P_2) }, |
0bfee649 L |
6053 | }, |
6054 | ||
592a252b | 6055 | /* PREFIX_VEX_0F3A14 */ |
0bfee649 | 6056 | { |
592d1631 L |
6057 | { Bad_Opcode }, |
6058 | { Bad_Opcode }, | |
592a252b | 6059 | { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, |
0bfee649 L |
6060 | }, |
6061 | ||
592a252b | 6062 | /* PREFIX_VEX_0F3A15 */ |
0bfee649 | 6063 | { |
592d1631 L |
6064 | { Bad_Opcode }, |
6065 | { Bad_Opcode }, | |
592a252b | 6066 | { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, |
0bfee649 L |
6067 | }, |
6068 | ||
592a252b | 6069 | /* PREFIX_VEX_0F3A16 */ |
c0f3af97 | 6070 | { |
592d1631 L |
6071 | { Bad_Opcode }, |
6072 | { Bad_Opcode }, | |
592a252b | 6073 | { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, |
c0f3af97 L |
6074 | }, |
6075 | ||
592a252b | 6076 | /* PREFIX_VEX_0F3A17 */ |
c0f3af97 | 6077 | { |
592d1631 L |
6078 | { Bad_Opcode }, |
6079 | { Bad_Opcode }, | |
592a252b | 6080 | { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, |
c0f3af97 L |
6081 | }, |
6082 | ||
592a252b | 6083 | /* PREFIX_VEX_0F3A18 */ |
c0f3af97 | 6084 | { |
592d1631 L |
6085 | { Bad_Opcode }, |
6086 | { Bad_Opcode }, | |
592a252b | 6087 | { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, |
c0f3af97 L |
6088 | }, |
6089 | ||
592a252b | 6090 | /* PREFIX_VEX_0F3A19 */ |
c0f3af97 | 6091 | { |
592d1631 L |
6092 | { Bad_Opcode }, |
6093 | { Bad_Opcode }, | |
592a252b | 6094 | { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, |
c0f3af97 L |
6095 | }, |
6096 | ||
592a252b | 6097 | /* PREFIX_VEX_0F3A1D */ |
c7b8aa3a L |
6098 | { |
6099 | { Bad_Opcode }, | |
6100 | { Bad_Opcode }, | |
6101 | { "vcvtps2ph", { EXxmmq, XM, Ib } }, | |
6102 | }, | |
6103 | ||
592a252b | 6104 | /* PREFIX_VEX_0F3A20 */ |
c0f3af97 | 6105 | { |
592d1631 L |
6106 | { Bad_Opcode }, |
6107 | { Bad_Opcode }, | |
592a252b | 6108 | { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, |
c0f3af97 L |
6109 | }, |
6110 | ||
592a252b | 6111 | /* PREFIX_VEX_0F3A21 */ |
c0f3af97 | 6112 | { |
592d1631 L |
6113 | { Bad_Opcode }, |
6114 | { Bad_Opcode }, | |
592a252b | 6115 | { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, |
c0f3af97 L |
6116 | }, |
6117 | ||
592a252b | 6118 | /* PREFIX_VEX_0F3A22 */ |
0bfee649 | 6119 | { |
592d1631 L |
6120 | { Bad_Opcode }, |
6121 | { Bad_Opcode }, | |
592a252b | 6122 | { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, |
0bfee649 L |
6123 | }, |
6124 | ||
43234a1e L |
6125 | /* PREFIX_VEX_0F3A30 */ |
6126 | { | |
6127 | { Bad_Opcode }, | |
6128 | { Bad_Opcode }, | |
6129 | { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) }, | |
6130 | }, | |
6131 | ||
6132 | /* PREFIX_VEX_0F3A32 */ | |
6133 | { | |
6134 | { Bad_Opcode }, | |
6135 | { Bad_Opcode }, | |
6136 | { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) }, | |
6137 | }, | |
6138 | ||
6c30d220 L |
6139 | /* PREFIX_VEX_0F3A38 */ |
6140 | { | |
6141 | { Bad_Opcode }, | |
6142 | { Bad_Opcode }, | |
6143 | { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) }, | |
6144 | }, | |
6145 | ||
6146 | /* PREFIX_VEX_0F3A39 */ | |
6147 | { | |
6148 | { Bad_Opcode }, | |
6149 | { Bad_Opcode }, | |
6150 | { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) }, | |
6151 | }, | |
6152 | ||
592a252b | 6153 | /* PREFIX_VEX_0F3A40 */ |
c0f3af97 | 6154 | { |
592d1631 L |
6155 | { Bad_Opcode }, |
6156 | { Bad_Opcode }, | |
592a252b | 6157 | { VEX_W_TABLE (VEX_W_0F3A40_P_2) }, |
c0f3af97 L |
6158 | }, |
6159 | ||
592a252b | 6160 | /* PREFIX_VEX_0F3A41 */ |
c0f3af97 | 6161 | { |
592d1631 L |
6162 | { Bad_Opcode }, |
6163 | { Bad_Opcode }, | |
592a252b | 6164 | { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, |
c0f3af97 L |
6165 | }, |
6166 | ||
592a252b | 6167 | /* PREFIX_VEX_0F3A42 */ |
c0f3af97 | 6168 | { |
592d1631 L |
6169 | { Bad_Opcode }, |
6170 | { Bad_Opcode }, | |
6c30d220 | 6171 | { VEX_W_TABLE (VEX_W_0F3A42_P_2) }, |
c0f3af97 L |
6172 | }, |
6173 | ||
592a252b | 6174 | /* PREFIX_VEX_0F3A44 */ |
ce2f5b3c | 6175 | { |
592d1631 L |
6176 | { Bad_Opcode }, |
6177 | { Bad_Opcode }, | |
592a252b | 6178 | { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) }, |
ce2f5b3c L |
6179 | }, |
6180 | ||
6c30d220 L |
6181 | /* PREFIX_VEX_0F3A46 */ |
6182 | { | |
6183 | { Bad_Opcode }, | |
6184 | { Bad_Opcode }, | |
6185 | { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) }, | |
6186 | }, | |
6187 | ||
592a252b | 6188 | /* PREFIX_VEX_0F3A48 */ |
a683cc34 SP |
6189 | { |
6190 | { Bad_Opcode }, | |
6191 | { Bad_Opcode }, | |
592a252b | 6192 | { VEX_W_TABLE (VEX_W_0F3A48_P_2) }, |
a683cc34 SP |
6193 | }, |
6194 | ||
592a252b | 6195 | /* PREFIX_VEX_0F3A49 */ |
a683cc34 SP |
6196 | { |
6197 | { Bad_Opcode }, | |
6198 | { Bad_Opcode }, | |
592a252b | 6199 | { VEX_W_TABLE (VEX_W_0F3A49_P_2) }, |
a683cc34 SP |
6200 | }, |
6201 | ||
592a252b | 6202 | /* PREFIX_VEX_0F3A4A */ |
c0f3af97 | 6203 | { |
592d1631 L |
6204 | { Bad_Opcode }, |
6205 | { Bad_Opcode }, | |
592a252b | 6206 | { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, |
c0f3af97 L |
6207 | }, |
6208 | ||
592a252b | 6209 | /* PREFIX_VEX_0F3A4B */ |
c0f3af97 | 6210 | { |
592d1631 L |
6211 | { Bad_Opcode }, |
6212 | { Bad_Opcode }, | |
592a252b | 6213 | { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, |
c0f3af97 L |
6214 | }, |
6215 | ||
592a252b | 6216 | /* PREFIX_VEX_0F3A4C */ |
c0f3af97 | 6217 | { |
592d1631 L |
6218 | { Bad_Opcode }, |
6219 | { Bad_Opcode }, | |
6c30d220 | 6220 | { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, |
c0f3af97 L |
6221 | }, |
6222 | ||
592a252b | 6223 | /* PREFIX_VEX_0F3A5C */ |
922d8de8 | 6224 | { |
592d1631 L |
6225 | { Bad_Opcode }, |
6226 | { Bad_Opcode }, | |
206c2556 | 6227 | { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
6228 | }, |
6229 | ||
592a252b | 6230 | /* PREFIX_VEX_0F3A5D */ |
922d8de8 | 6231 | { |
592d1631 L |
6232 | { Bad_Opcode }, |
6233 | { Bad_Opcode }, | |
206c2556 | 6234 | { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
6235 | }, |
6236 | ||
592a252b | 6237 | /* PREFIX_VEX_0F3A5E */ |
922d8de8 | 6238 | { |
592d1631 L |
6239 | { Bad_Opcode }, |
6240 | { Bad_Opcode }, | |
206c2556 | 6241 | { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
6242 | }, |
6243 | ||
592a252b | 6244 | /* PREFIX_VEX_0F3A5F */ |
922d8de8 | 6245 | { |
592d1631 L |
6246 | { Bad_Opcode }, |
6247 | { Bad_Opcode }, | |
206c2556 | 6248 | { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
6249 | }, |
6250 | ||
592a252b | 6251 | /* PREFIX_VEX_0F3A60 */ |
c0f3af97 | 6252 | { |
592d1631 L |
6253 | { Bad_Opcode }, |
6254 | { Bad_Opcode }, | |
592a252b | 6255 | { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, |
592d1631 | 6256 | { Bad_Opcode }, |
c0f3af97 L |
6257 | }, |
6258 | ||
592a252b | 6259 | /* PREFIX_VEX_0F3A61 */ |
c0f3af97 | 6260 | { |
592d1631 L |
6261 | { Bad_Opcode }, |
6262 | { Bad_Opcode }, | |
592a252b | 6263 | { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, |
c0f3af97 L |
6264 | }, |
6265 | ||
592a252b | 6266 | /* PREFIX_VEX_0F3A62 */ |
c0f3af97 | 6267 | { |
592d1631 L |
6268 | { Bad_Opcode }, |
6269 | { Bad_Opcode }, | |
592a252b | 6270 | { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, |
c0f3af97 L |
6271 | }, |
6272 | ||
592a252b | 6273 | /* PREFIX_VEX_0F3A63 */ |
c0f3af97 | 6274 | { |
592d1631 L |
6275 | { Bad_Opcode }, |
6276 | { Bad_Opcode }, | |
592a252b | 6277 | { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, |
c0f3af97 | 6278 | }, |
a5ff0eb2 | 6279 | |
592a252b | 6280 | /* PREFIX_VEX_0F3A68 */ |
922d8de8 | 6281 | { |
592d1631 L |
6282 | { Bad_Opcode }, |
6283 | { Bad_Opcode }, | |
206c2556 | 6284 | { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
6285 | }, |
6286 | ||
592a252b | 6287 | /* PREFIX_VEX_0F3A69 */ |
922d8de8 | 6288 | { |
592d1631 L |
6289 | { Bad_Opcode }, |
6290 | { Bad_Opcode }, | |
206c2556 | 6291 | { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
6292 | }, |
6293 | ||
592a252b | 6294 | /* PREFIX_VEX_0F3A6A */ |
922d8de8 | 6295 | { |
592d1631 L |
6296 | { Bad_Opcode }, |
6297 | { Bad_Opcode }, | |
592a252b | 6298 | { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) }, |
922d8de8 DR |
6299 | }, |
6300 | ||
592a252b | 6301 | /* PREFIX_VEX_0F3A6B */ |
922d8de8 | 6302 | { |
592d1631 L |
6303 | { Bad_Opcode }, |
6304 | { Bad_Opcode }, | |
592a252b | 6305 | { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) }, |
922d8de8 DR |
6306 | }, |
6307 | ||
592a252b | 6308 | /* PREFIX_VEX_0F3A6C */ |
922d8de8 | 6309 | { |
592d1631 L |
6310 | { Bad_Opcode }, |
6311 | { Bad_Opcode }, | |
206c2556 | 6312 | { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
6313 | }, |
6314 | ||
592a252b | 6315 | /* PREFIX_VEX_0F3A6D */ |
922d8de8 | 6316 | { |
592d1631 L |
6317 | { Bad_Opcode }, |
6318 | { Bad_Opcode }, | |
206c2556 | 6319 | { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
6320 | }, |
6321 | ||
592a252b | 6322 | /* PREFIX_VEX_0F3A6E */ |
922d8de8 | 6323 | { |
592d1631 L |
6324 | { Bad_Opcode }, |
6325 | { Bad_Opcode }, | |
592a252b | 6326 | { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) }, |
922d8de8 DR |
6327 | }, |
6328 | ||
592a252b | 6329 | /* PREFIX_VEX_0F3A6F */ |
922d8de8 | 6330 | { |
592d1631 L |
6331 | { Bad_Opcode }, |
6332 | { Bad_Opcode }, | |
592a252b | 6333 | { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) }, |
922d8de8 DR |
6334 | }, |
6335 | ||
592a252b | 6336 | /* PREFIX_VEX_0F3A78 */ |
922d8de8 | 6337 | { |
592d1631 L |
6338 | { Bad_Opcode }, |
6339 | { Bad_Opcode }, | |
206c2556 | 6340 | { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
6341 | }, |
6342 | ||
592a252b | 6343 | /* PREFIX_VEX_0F3A79 */ |
922d8de8 | 6344 | { |
592d1631 L |
6345 | { Bad_Opcode }, |
6346 | { Bad_Opcode }, | |
206c2556 | 6347 | { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
6348 | }, |
6349 | ||
592a252b | 6350 | /* PREFIX_VEX_0F3A7A */ |
922d8de8 | 6351 | { |
592d1631 L |
6352 | { Bad_Opcode }, |
6353 | { Bad_Opcode }, | |
592a252b | 6354 | { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) }, |
922d8de8 DR |
6355 | }, |
6356 | ||
592a252b | 6357 | /* PREFIX_VEX_0F3A7B */ |
922d8de8 | 6358 | { |
592d1631 L |
6359 | { Bad_Opcode }, |
6360 | { Bad_Opcode }, | |
592a252b | 6361 | { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) }, |
922d8de8 DR |
6362 | }, |
6363 | ||
592a252b | 6364 | /* PREFIX_VEX_0F3A7C */ |
922d8de8 | 6365 | { |
592d1631 L |
6366 | { Bad_Opcode }, |
6367 | { Bad_Opcode }, | |
206c2556 | 6368 | { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
592d1631 | 6369 | { Bad_Opcode }, |
922d8de8 DR |
6370 | }, |
6371 | ||
592a252b | 6372 | /* PREFIX_VEX_0F3A7D */ |
922d8de8 | 6373 | { |
592d1631 L |
6374 | { Bad_Opcode }, |
6375 | { Bad_Opcode }, | |
206c2556 | 6376 | { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
6377 | }, |
6378 | ||
592a252b | 6379 | /* PREFIX_VEX_0F3A7E */ |
922d8de8 | 6380 | { |
592d1631 L |
6381 | { Bad_Opcode }, |
6382 | { Bad_Opcode }, | |
592a252b | 6383 | { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) }, |
922d8de8 DR |
6384 | }, |
6385 | ||
592a252b | 6386 | /* PREFIX_VEX_0F3A7F */ |
922d8de8 | 6387 | { |
592d1631 L |
6388 | { Bad_Opcode }, |
6389 | { Bad_Opcode }, | |
592a252b | 6390 | { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) }, |
922d8de8 DR |
6391 | }, |
6392 | ||
592a252b | 6393 | /* PREFIX_VEX_0F3ADF */ |
a5ff0eb2 | 6394 | { |
592d1631 L |
6395 | { Bad_Opcode }, |
6396 | { Bad_Opcode }, | |
592a252b | 6397 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, |
a5ff0eb2 | 6398 | }, |
6c30d220 L |
6399 | |
6400 | /* PREFIX_VEX_0F3AF0 */ | |
6401 | { | |
6402 | { Bad_Opcode }, | |
6403 | { Bad_Opcode }, | |
6404 | { Bad_Opcode }, | |
6405 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, | |
6406 | }, | |
43234a1e L |
6407 | |
6408 | #define NEED_PREFIX_TABLE | |
6409 | #include "i386-dis-evex.h" | |
6410 | #undef NEED_PREFIX_TABLE | |
c0f3af97 L |
6411 | }; |
6412 | ||
6413 | static const struct dis386 x86_64_table[][2] = { | |
6414 | /* X86_64_06 */ | |
6415 | { | |
d9e3625e | 6416 | { "pushP", { es } }, |
c0f3af97 L |
6417 | }, |
6418 | ||
6419 | /* X86_64_07 */ | |
6420 | { | |
d9e3625e | 6421 | { "popP", { es } }, |
c0f3af97 L |
6422 | }, |
6423 | ||
6424 | /* X86_64_0D */ | |
6425 | { | |
d9e3625e | 6426 | { "pushP", { cs } }, |
c0f3af97 L |
6427 | }, |
6428 | ||
6429 | /* X86_64_16 */ | |
6430 | { | |
d9e3625e | 6431 | { "pushP", { ss } }, |
c0f3af97 L |
6432 | }, |
6433 | ||
6434 | /* X86_64_17 */ | |
6435 | { | |
d9e3625e | 6436 | { "popP", { ss } }, |
c0f3af97 L |
6437 | }, |
6438 | ||
6439 | /* X86_64_1E */ | |
6440 | { | |
d9e3625e | 6441 | { "pushP", { ds } }, |
c0f3af97 L |
6442 | }, |
6443 | ||
6444 | /* X86_64_1F */ | |
6445 | { | |
d9e3625e | 6446 | { "popP", { ds } }, |
c0f3af97 L |
6447 | }, |
6448 | ||
6449 | /* X86_64_27 */ | |
6450 | { | |
6451 | { "daa", { XX } }, | |
c0f3af97 L |
6452 | }, |
6453 | ||
6454 | /* X86_64_2F */ | |
6455 | { | |
6456 | { "das", { XX } }, | |
c0f3af97 L |
6457 | }, |
6458 | ||
6459 | /* X86_64_37 */ | |
6460 | { | |
6461 | { "aaa", { XX } }, | |
c0f3af97 L |
6462 | }, |
6463 | ||
6464 | /* X86_64_3F */ | |
6465 | { | |
6466 | { "aas", { XX } }, | |
c0f3af97 L |
6467 | }, |
6468 | ||
6469 | /* X86_64_60 */ | |
6470 | { | |
d9e3625e | 6471 | { "pushaP", { XX } }, |
c0f3af97 L |
6472 | }, |
6473 | ||
6474 | /* X86_64_61 */ | |
6475 | { | |
d9e3625e | 6476 | { "popaP", { XX } }, |
c0f3af97 L |
6477 | }, |
6478 | ||
6479 | /* X86_64_62 */ | |
6480 | { | |
6481 | { MOD_TABLE (MOD_62_32BIT) }, | |
43234a1e | 6482 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
6483 | }, |
6484 | ||
6485 | /* X86_64_63 */ | |
6486 | { | |
6487 | { "arpl", { Ew, Gw } }, | |
6488 | { "movs{lq|xd}", { Gv, Ed } }, | |
6489 | }, | |
6490 | ||
6491 | /* X86_64_6D */ | |
6492 | { | |
6493 | { "ins{R|}", { Yzr, indirDX } }, | |
6494 | { "ins{G|}", { Yzr, indirDX } }, | |
6495 | }, | |
6496 | ||
6497 | /* X86_64_6F */ | |
6498 | { | |
6499 | { "outs{R|}", { indirDXr, Xz } }, | |
6500 | { "outs{G|}", { indirDXr, Xz } }, | |
6501 | }, | |
6502 | ||
6503 | /* X86_64_9A */ | |
6504 | { | |
6505 | { "Jcall{T|}", { Ap } }, | |
c0f3af97 L |
6506 | }, |
6507 | ||
6508 | /* X86_64_C4 */ | |
6509 | { | |
6510 | { MOD_TABLE (MOD_C4_32BIT) }, | |
6511 | { VEX_C4_TABLE (VEX_0F) }, | |
6512 | }, | |
6513 | ||
6514 | /* X86_64_C5 */ | |
6515 | { | |
6516 | { MOD_TABLE (MOD_C5_32BIT) }, | |
6517 | { VEX_C5_TABLE (VEX_0F) }, | |
6518 | }, | |
6519 | ||
6520 | /* X86_64_CE */ | |
6521 | { | |
6522 | { "into", { XX } }, | |
c0f3af97 L |
6523 | }, |
6524 | ||
6525 | /* X86_64_D4 */ | |
6526 | { | |
e3949f17 | 6527 | { "aam", { Ib } }, |
c0f3af97 L |
6528 | }, |
6529 | ||
6530 | /* X86_64_D5 */ | |
6531 | { | |
e3949f17 | 6532 | { "aad", { Ib } }, |
c0f3af97 L |
6533 | }, |
6534 | ||
6535 | /* X86_64_EA */ | |
6536 | { | |
6537 | { "Jjmp{T|}", { Ap } }, | |
c0f3af97 L |
6538 | }, |
6539 | ||
6540 | /* X86_64_0F01_REG_0 */ | |
6541 | { | |
6542 | { "sgdt{Q|IQ}", { M } }, | |
6543 | { "sgdt", { M } }, | |
6544 | }, | |
6545 | ||
6546 | /* X86_64_0F01_REG_1 */ | |
6547 | { | |
6548 | { "sidt{Q|IQ}", { M } }, | |
6549 | { "sidt", { M } }, | |
6550 | }, | |
6551 | ||
6552 | /* X86_64_0F01_REG_2 */ | |
6553 | { | |
6554 | { "lgdt{Q|Q}", { M } }, | |
6555 | { "lgdt", { M } }, | |
6556 | }, | |
6557 | ||
6558 | /* X86_64_0F01_REG_3 */ | |
6559 | { | |
6560 | { "lidt{Q|Q}", { M } }, | |
6561 | { "lidt", { M } }, | |
6562 | }, | |
6563 | }; | |
6564 | ||
6565 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
6566 | |
6567 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
6568 | { |
6569 | /* 00 */ | |
c1e679ec DR |
6570 | { "pshufb", { MX, EM } }, |
6571 | { "phaddw", { MX, EM } }, | |
6572 | { "phaddd", { MX, EM } }, | |
6573 | { "phaddsw", { MX, EM } }, | |
6574 | { "pmaddubsw", { MX, EM } }, | |
6575 | { "phsubw", { MX, EM } }, | |
6576 | { "phsubd", { MX, EM } }, | |
6577 | { "phsubsw", { MX, EM } }, | |
c0f3af97 | 6578 | /* 08 */ |
c1e679ec DR |
6579 | { "psignb", { MX, EM } }, |
6580 | { "psignw", { MX, EM } }, | |
6581 | { "psignd", { MX, EM } }, | |
6582 | { "pmulhrsw", { MX, EM } }, | |
592d1631 L |
6583 | { Bad_Opcode }, |
6584 | { Bad_Opcode }, | |
6585 | { Bad_Opcode }, | |
6586 | { Bad_Opcode }, | |
f88c9eb0 SP |
6587 | /* 10 */ |
6588 | { PREFIX_TABLE (PREFIX_0F3810) }, | |
592d1631 L |
6589 | { Bad_Opcode }, |
6590 | { Bad_Opcode }, | |
6591 | { Bad_Opcode }, | |
f88c9eb0 SP |
6592 | { PREFIX_TABLE (PREFIX_0F3814) }, |
6593 | { PREFIX_TABLE (PREFIX_0F3815) }, | |
592d1631 | 6594 | { Bad_Opcode }, |
f88c9eb0 SP |
6595 | { PREFIX_TABLE (PREFIX_0F3817) }, |
6596 | /* 18 */ | |
592d1631 L |
6597 | { Bad_Opcode }, |
6598 | { Bad_Opcode }, | |
6599 | { Bad_Opcode }, | |
6600 | { Bad_Opcode }, | |
f88c9eb0 SP |
6601 | { "pabsb", { MX, EM } }, |
6602 | { "pabsw", { MX, EM } }, | |
6603 | { "pabsd", { MX, EM } }, | |
592d1631 | 6604 | { Bad_Opcode }, |
f88c9eb0 SP |
6605 | /* 20 */ |
6606 | { PREFIX_TABLE (PREFIX_0F3820) }, | |
6607 | { PREFIX_TABLE (PREFIX_0F3821) }, | |
6608 | { PREFIX_TABLE (PREFIX_0F3822) }, | |
6609 | { PREFIX_TABLE (PREFIX_0F3823) }, | |
6610 | { PREFIX_TABLE (PREFIX_0F3824) }, | |
6611 | { PREFIX_TABLE (PREFIX_0F3825) }, | |
592d1631 L |
6612 | { Bad_Opcode }, |
6613 | { Bad_Opcode }, | |
f88c9eb0 SP |
6614 | /* 28 */ |
6615 | { PREFIX_TABLE (PREFIX_0F3828) }, | |
6616 | { PREFIX_TABLE (PREFIX_0F3829) }, | |
6617 | { PREFIX_TABLE (PREFIX_0F382A) }, | |
6618 | { PREFIX_TABLE (PREFIX_0F382B) }, | |
592d1631 L |
6619 | { Bad_Opcode }, |
6620 | { Bad_Opcode }, | |
6621 | { Bad_Opcode }, | |
6622 | { Bad_Opcode }, | |
f88c9eb0 SP |
6623 | /* 30 */ |
6624 | { PREFIX_TABLE (PREFIX_0F3830) }, | |
6625 | { PREFIX_TABLE (PREFIX_0F3831) }, | |
6626 | { PREFIX_TABLE (PREFIX_0F3832) }, | |
6627 | { PREFIX_TABLE (PREFIX_0F3833) }, | |
6628 | { PREFIX_TABLE (PREFIX_0F3834) }, | |
6629 | { PREFIX_TABLE (PREFIX_0F3835) }, | |
592d1631 | 6630 | { Bad_Opcode }, |
f88c9eb0 SP |
6631 | { PREFIX_TABLE (PREFIX_0F3837) }, |
6632 | /* 38 */ | |
6633 | { PREFIX_TABLE (PREFIX_0F3838) }, | |
6634 | { PREFIX_TABLE (PREFIX_0F3839) }, | |
6635 | { PREFIX_TABLE (PREFIX_0F383A) }, | |
6636 | { PREFIX_TABLE (PREFIX_0F383B) }, | |
6637 | { PREFIX_TABLE (PREFIX_0F383C) }, | |
6638 | { PREFIX_TABLE (PREFIX_0F383D) }, | |
6639 | { PREFIX_TABLE (PREFIX_0F383E) }, | |
6640 | { PREFIX_TABLE (PREFIX_0F383F) }, | |
6641 | /* 40 */ | |
6642 | { PREFIX_TABLE (PREFIX_0F3840) }, | |
6643 | { PREFIX_TABLE (PREFIX_0F3841) }, | |
592d1631 L |
6644 | { Bad_Opcode }, |
6645 | { Bad_Opcode }, | |
6646 | { Bad_Opcode }, | |
6647 | { Bad_Opcode }, | |
6648 | { Bad_Opcode }, | |
6649 | { Bad_Opcode }, | |
f88c9eb0 | 6650 | /* 48 */ |
592d1631 L |
6651 | { Bad_Opcode }, |
6652 | { Bad_Opcode }, | |
6653 | { Bad_Opcode }, | |
6654 | { Bad_Opcode }, | |
6655 | { Bad_Opcode }, | |
6656 | { Bad_Opcode }, | |
6657 | { Bad_Opcode }, | |
6658 | { Bad_Opcode }, | |
f88c9eb0 | 6659 | /* 50 */ |
592d1631 L |
6660 | { Bad_Opcode }, |
6661 | { Bad_Opcode }, | |
6662 | { Bad_Opcode }, | |
6663 | { Bad_Opcode }, | |
6664 | { Bad_Opcode }, | |
6665 | { Bad_Opcode }, | |
6666 | { Bad_Opcode }, | |
6667 | { Bad_Opcode }, | |
f88c9eb0 | 6668 | /* 58 */ |
592d1631 L |
6669 | { Bad_Opcode }, |
6670 | { Bad_Opcode }, | |
6671 | { Bad_Opcode }, | |
6672 | { Bad_Opcode }, | |
6673 | { Bad_Opcode }, | |
6674 | { Bad_Opcode }, | |
6675 | { Bad_Opcode }, | |
6676 | { Bad_Opcode }, | |
f88c9eb0 | 6677 | /* 60 */ |
592d1631 L |
6678 | { Bad_Opcode }, |
6679 | { Bad_Opcode }, | |
6680 | { Bad_Opcode }, | |
6681 | { Bad_Opcode }, | |
6682 | { Bad_Opcode }, | |
6683 | { Bad_Opcode }, | |
6684 | { Bad_Opcode }, | |
6685 | { Bad_Opcode }, | |
f88c9eb0 | 6686 | /* 68 */ |
592d1631 L |
6687 | { Bad_Opcode }, |
6688 | { Bad_Opcode }, | |
6689 | { Bad_Opcode }, | |
6690 | { Bad_Opcode }, | |
6691 | { Bad_Opcode }, | |
6692 | { Bad_Opcode }, | |
6693 | { Bad_Opcode }, | |
6694 | { Bad_Opcode }, | |
f88c9eb0 | 6695 | /* 70 */ |
592d1631 L |
6696 | { Bad_Opcode }, |
6697 | { Bad_Opcode }, | |
6698 | { Bad_Opcode }, | |
6699 | { Bad_Opcode }, | |
6700 | { Bad_Opcode }, | |
6701 | { Bad_Opcode }, | |
6702 | { Bad_Opcode }, | |
6703 | { Bad_Opcode }, | |
f88c9eb0 | 6704 | /* 78 */ |
592d1631 L |
6705 | { Bad_Opcode }, |
6706 | { Bad_Opcode }, | |
6707 | { Bad_Opcode }, | |
6708 | { Bad_Opcode }, | |
6709 | { Bad_Opcode }, | |
6710 | { Bad_Opcode }, | |
6711 | { Bad_Opcode }, | |
6712 | { Bad_Opcode }, | |
f88c9eb0 SP |
6713 | /* 80 */ |
6714 | { PREFIX_TABLE (PREFIX_0F3880) }, | |
6715 | { PREFIX_TABLE (PREFIX_0F3881) }, | |
6c30d220 | 6716 | { PREFIX_TABLE (PREFIX_0F3882) }, |
592d1631 L |
6717 | { Bad_Opcode }, |
6718 | { Bad_Opcode }, | |
6719 | { Bad_Opcode }, | |
6720 | { Bad_Opcode }, | |
6721 | { Bad_Opcode }, | |
f88c9eb0 | 6722 | /* 88 */ |
592d1631 L |
6723 | { Bad_Opcode }, |
6724 | { Bad_Opcode }, | |
6725 | { Bad_Opcode }, | |
6726 | { Bad_Opcode }, | |
6727 | { Bad_Opcode }, | |
6728 | { Bad_Opcode }, | |
6729 | { Bad_Opcode }, | |
6730 | { Bad_Opcode }, | |
f88c9eb0 | 6731 | /* 90 */ |
592d1631 L |
6732 | { Bad_Opcode }, |
6733 | { Bad_Opcode }, | |
6734 | { Bad_Opcode }, | |
6735 | { Bad_Opcode }, | |
6736 | { Bad_Opcode }, | |
6737 | { Bad_Opcode }, | |
6738 | { Bad_Opcode }, | |
6739 | { Bad_Opcode }, | |
f88c9eb0 | 6740 | /* 98 */ |
592d1631 L |
6741 | { Bad_Opcode }, |
6742 | { Bad_Opcode }, | |
6743 | { Bad_Opcode }, | |
6744 | { Bad_Opcode }, | |
6745 | { Bad_Opcode }, | |
6746 | { Bad_Opcode }, | |
6747 | { Bad_Opcode }, | |
6748 | { Bad_Opcode }, | |
f88c9eb0 | 6749 | /* a0 */ |
592d1631 L |
6750 | { Bad_Opcode }, |
6751 | { Bad_Opcode }, | |
6752 | { Bad_Opcode }, | |
6753 | { Bad_Opcode }, | |
6754 | { Bad_Opcode }, | |
6755 | { Bad_Opcode }, | |
6756 | { Bad_Opcode }, | |
6757 | { Bad_Opcode }, | |
f88c9eb0 | 6758 | /* a8 */ |
592d1631 L |
6759 | { Bad_Opcode }, |
6760 | { Bad_Opcode }, | |
6761 | { Bad_Opcode }, | |
6762 | { Bad_Opcode }, | |
6763 | { Bad_Opcode }, | |
6764 | { Bad_Opcode }, | |
6765 | { Bad_Opcode }, | |
6766 | { Bad_Opcode }, | |
f88c9eb0 | 6767 | /* b0 */ |
592d1631 L |
6768 | { Bad_Opcode }, |
6769 | { Bad_Opcode }, | |
6770 | { Bad_Opcode }, | |
6771 | { Bad_Opcode }, | |
6772 | { Bad_Opcode }, | |
6773 | { Bad_Opcode }, | |
6774 | { Bad_Opcode }, | |
6775 | { Bad_Opcode }, | |
f88c9eb0 | 6776 | /* b8 */ |
592d1631 L |
6777 | { Bad_Opcode }, |
6778 | { Bad_Opcode }, | |
6779 | { Bad_Opcode }, | |
6780 | { Bad_Opcode }, | |
6781 | { Bad_Opcode }, | |
6782 | { Bad_Opcode }, | |
6783 | { Bad_Opcode }, | |
6784 | { Bad_Opcode }, | |
f88c9eb0 | 6785 | /* c0 */ |
592d1631 L |
6786 | { Bad_Opcode }, |
6787 | { Bad_Opcode }, | |
6788 | { Bad_Opcode }, | |
6789 | { Bad_Opcode }, | |
6790 | { Bad_Opcode }, | |
6791 | { Bad_Opcode }, | |
6792 | { Bad_Opcode }, | |
6793 | { Bad_Opcode }, | |
f88c9eb0 | 6794 | /* c8 */ |
a0046408 L |
6795 | { PREFIX_TABLE (PREFIX_0F38C8) }, |
6796 | { PREFIX_TABLE (PREFIX_0F38C9) }, | |
6797 | { PREFIX_TABLE (PREFIX_0F38CA) }, | |
6798 | { PREFIX_TABLE (PREFIX_0F38CB) }, | |
6799 | { PREFIX_TABLE (PREFIX_0F38CC) }, | |
6800 | { PREFIX_TABLE (PREFIX_0F38CD) }, | |
592d1631 L |
6801 | { Bad_Opcode }, |
6802 | { Bad_Opcode }, | |
f88c9eb0 | 6803 | /* d0 */ |
592d1631 L |
6804 | { Bad_Opcode }, |
6805 | { Bad_Opcode }, | |
6806 | { Bad_Opcode }, | |
6807 | { Bad_Opcode }, | |
6808 | { Bad_Opcode }, | |
6809 | { Bad_Opcode }, | |
6810 | { Bad_Opcode }, | |
6811 | { Bad_Opcode }, | |
f88c9eb0 | 6812 | /* d8 */ |
592d1631 L |
6813 | { Bad_Opcode }, |
6814 | { Bad_Opcode }, | |
6815 | { Bad_Opcode }, | |
f88c9eb0 SP |
6816 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
6817 | { PREFIX_TABLE (PREFIX_0F38DC) }, | |
6818 | { PREFIX_TABLE (PREFIX_0F38DD) }, | |
6819 | { PREFIX_TABLE (PREFIX_0F38DE) }, | |
6820 | { PREFIX_TABLE (PREFIX_0F38DF) }, | |
6821 | /* e0 */ | |
592d1631 L |
6822 | { Bad_Opcode }, |
6823 | { Bad_Opcode }, | |
6824 | { Bad_Opcode }, | |
6825 | { Bad_Opcode }, | |
6826 | { Bad_Opcode }, | |
6827 | { Bad_Opcode }, | |
6828 | { Bad_Opcode }, | |
6829 | { Bad_Opcode }, | |
f88c9eb0 | 6830 | /* e8 */ |
592d1631 L |
6831 | { Bad_Opcode }, |
6832 | { Bad_Opcode }, | |
6833 | { Bad_Opcode }, | |
6834 | { Bad_Opcode }, | |
6835 | { Bad_Opcode }, | |
6836 | { Bad_Opcode }, | |
6837 | { Bad_Opcode }, | |
6838 | { Bad_Opcode }, | |
f88c9eb0 SP |
6839 | /* f0 */ |
6840 | { PREFIX_TABLE (PREFIX_0F38F0) }, | |
6841 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
592d1631 L |
6842 | { Bad_Opcode }, |
6843 | { Bad_Opcode }, | |
6844 | { Bad_Opcode }, | |
6845 | { Bad_Opcode }, | |
e2e1fcde | 6846 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
592d1631 | 6847 | { Bad_Opcode }, |
f88c9eb0 | 6848 | /* f8 */ |
592d1631 L |
6849 | { Bad_Opcode }, |
6850 | { Bad_Opcode }, | |
6851 | { Bad_Opcode }, | |
6852 | { Bad_Opcode }, | |
6853 | { Bad_Opcode }, | |
6854 | { Bad_Opcode }, | |
6855 | { Bad_Opcode }, | |
6856 | { Bad_Opcode }, | |
f88c9eb0 SP |
6857 | }, |
6858 | /* THREE_BYTE_0F3A */ | |
6859 | { | |
6860 | /* 00 */ | |
592d1631 L |
6861 | { Bad_Opcode }, |
6862 | { Bad_Opcode }, | |
6863 | { Bad_Opcode }, | |
6864 | { Bad_Opcode }, | |
6865 | { Bad_Opcode }, | |
6866 | { Bad_Opcode }, | |
6867 | { Bad_Opcode }, | |
6868 | { Bad_Opcode }, | |
f88c9eb0 SP |
6869 | /* 08 */ |
6870 | { PREFIX_TABLE (PREFIX_0F3A08) }, | |
6871 | { PREFIX_TABLE (PREFIX_0F3A09) }, | |
6872 | { PREFIX_TABLE (PREFIX_0F3A0A) }, | |
6873 | { PREFIX_TABLE (PREFIX_0F3A0B) }, | |
6874 | { PREFIX_TABLE (PREFIX_0F3A0C) }, | |
6875 | { PREFIX_TABLE (PREFIX_0F3A0D) }, | |
6876 | { PREFIX_TABLE (PREFIX_0F3A0E) }, | |
6877 | { "palignr", { MX, EM, Ib } }, | |
6878 | /* 10 */ | |
592d1631 L |
6879 | { Bad_Opcode }, |
6880 | { Bad_Opcode }, | |
6881 | { Bad_Opcode }, | |
6882 | { Bad_Opcode }, | |
f88c9eb0 SP |
6883 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
6884 | { PREFIX_TABLE (PREFIX_0F3A15) }, | |
6885 | { PREFIX_TABLE (PREFIX_0F3A16) }, | |
6886 | { PREFIX_TABLE (PREFIX_0F3A17) }, | |
6887 | /* 18 */ | |
592d1631 L |
6888 | { Bad_Opcode }, |
6889 | { Bad_Opcode }, | |
6890 | { Bad_Opcode }, | |
6891 | { Bad_Opcode }, | |
6892 | { Bad_Opcode }, | |
6893 | { Bad_Opcode }, | |
6894 | { Bad_Opcode }, | |
6895 | { Bad_Opcode }, | |
f88c9eb0 SP |
6896 | /* 20 */ |
6897 | { PREFIX_TABLE (PREFIX_0F3A20) }, | |
6898 | { PREFIX_TABLE (PREFIX_0F3A21) }, | |
6899 | { PREFIX_TABLE (PREFIX_0F3A22) }, | |
592d1631 L |
6900 | { Bad_Opcode }, |
6901 | { Bad_Opcode }, | |
6902 | { Bad_Opcode }, | |
6903 | { Bad_Opcode }, | |
6904 | { Bad_Opcode }, | |
f88c9eb0 | 6905 | /* 28 */ |
592d1631 L |
6906 | { Bad_Opcode }, |
6907 | { Bad_Opcode }, | |
6908 | { Bad_Opcode }, | |
6909 | { Bad_Opcode }, | |
6910 | { Bad_Opcode }, | |
6911 | { Bad_Opcode }, | |
6912 | { Bad_Opcode }, | |
6913 | { Bad_Opcode }, | |
f88c9eb0 | 6914 | /* 30 */ |
592d1631 L |
6915 | { Bad_Opcode }, |
6916 | { Bad_Opcode }, | |
6917 | { Bad_Opcode }, | |
6918 | { Bad_Opcode }, | |
6919 | { Bad_Opcode }, | |
6920 | { Bad_Opcode }, | |
6921 | { Bad_Opcode }, | |
6922 | { Bad_Opcode }, | |
f88c9eb0 | 6923 | /* 38 */ |
592d1631 L |
6924 | { Bad_Opcode }, |
6925 | { Bad_Opcode }, | |
6926 | { Bad_Opcode }, | |
6927 | { Bad_Opcode }, | |
6928 | { Bad_Opcode }, | |
6929 | { Bad_Opcode }, | |
6930 | { Bad_Opcode }, | |
6931 | { Bad_Opcode }, | |
f88c9eb0 SP |
6932 | /* 40 */ |
6933 | { PREFIX_TABLE (PREFIX_0F3A40) }, | |
6934 | { PREFIX_TABLE (PREFIX_0F3A41) }, | |
6935 | { PREFIX_TABLE (PREFIX_0F3A42) }, | |
592d1631 | 6936 | { Bad_Opcode }, |
f88c9eb0 | 6937 | { PREFIX_TABLE (PREFIX_0F3A44) }, |
592d1631 L |
6938 | { Bad_Opcode }, |
6939 | { Bad_Opcode }, | |
6940 | { Bad_Opcode }, | |
f88c9eb0 | 6941 | /* 48 */ |
592d1631 L |
6942 | { Bad_Opcode }, |
6943 | { Bad_Opcode }, | |
6944 | { Bad_Opcode }, | |
6945 | { Bad_Opcode }, | |
6946 | { Bad_Opcode }, | |
6947 | { Bad_Opcode }, | |
6948 | { Bad_Opcode }, | |
6949 | { Bad_Opcode }, | |
f88c9eb0 | 6950 | /* 50 */ |
592d1631 L |
6951 | { Bad_Opcode }, |
6952 | { Bad_Opcode }, | |
6953 | { Bad_Opcode }, | |
6954 | { Bad_Opcode }, | |
6955 | { Bad_Opcode }, | |
6956 | { Bad_Opcode }, | |
6957 | { Bad_Opcode }, | |
6958 | { Bad_Opcode }, | |
f88c9eb0 | 6959 | /* 58 */ |
592d1631 L |
6960 | { Bad_Opcode }, |
6961 | { Bad_Opcode }, | |
6962 | { Bad_Opcode }, | |
6963 | { Bad_Opcode }, | |
6964 | { Bad_Opcode }, | |
6965 | { Bad_Opcode }, | |
6966 | { Bad_Opcode }, | |
6967 | { Bad_Opcode }, | |
f88c9eb0 SP |
6968 | /* 60 */ |
6969 | { PREFIX_TABLE (PREFIX_0F3A60) }, | |
6970 | { PREFIX_TABLE (PREFIX_0F3A61) }, | |
6971 | { PREFIX_TABLE (PREFIX_0F3A62) }, | |
6972 | { PREFIX_TABLE (PREFIX_0F3A63) }, | |
592d1631 L |
6973 | { Bad_Opcode }, |
6974 | { Bad_Opcode }, | |
6975 | { Bad_Opcode }, | |
6976 | { Bad_Opcode }, | |
f88c9eb0 | 6977 | /* 68 */ |
592d1631 L |
6978 | { Bad_Opcode }, |
6979 | { Bad_Opcode }, | |
6980 | { Bad_Opcode }, | |
6981 | { Bad_Opcode }, | |
6982 | { Bad_Opcode }, | |
6983 | { Bad_Opcode }, | |
6984 | { Bad_Opcode }, | |
6985 | { Bad_Opcode }, | |
f88c9eb0 | 6986 | /* 70 */ |
592d1631 L |
6987 | { Bad_Opcode }, |
6988 | { Bad_Opcode }, | |
6989 | { Bad_Opcode }, | |
6990 | { Bad_Opcode }, | |
6991 | { Bad_Opcode }, | |
6992 | { Bad_Opcode }, | |
6993 | { Bad_Opcode }, | |
6994 | { Bad_Opcode }, | |
f88c9eb0 | 6995 | /* 78 */ |
592d1631 L |
6996 | { Bad_Opcode }, |
6997 | { Bad_Opcode }, | |
6998 | { Bad_Opcode }, | |
6999 | { Bad_Opcode }, | |
7000 | { Bad_Opcode }, | |
7001 | { Bad_Opcode }, | |
7002 | { Bad_Opcode }, | |
7003 | { Bad_Opcode }, | |
f88c9eb0 | 7004 | /* 80 */ |
592d1631 L |
7005 | { Bad_Opcode }, |
7006 | { Bad_Opcode }, | |
7007 | { Bad_Opcode }, | |
7008 | { Bad_Opcode }, | |
7009 | { Bad_Opcode }, | |
7010 | { Bad_Opcode }, | |
7011 | { Bad_Opcode }, | |
7012 | { Bad_Opcode }, | |
f88c9eb0 | 7013 | /* 88 */ |
592d1631 L |
7014 | { Bad_Opcode }, |
7015 | { Bad_Opcode }, | |
7016 | { Bad_Opcode }, | |
7017 | { Bad_Opcode }, | |
7018 | { Bad_Opcode }, | |
7019 | { Bad_Opcode }, | |
7020 | { Bad_Opcode }, | |
7021 | { Bad_Opcode }, | |
f88c9eb0 | 7022 | /* 90 */ |
592d1631 L |
7023 | { Bad_Opcode }, |
7024 | { Bad_Opcode }, | |
7025 | { Bad_Opcode }, | |
7026 | { Bad_Opcode }, | |
7027 | { Bad_Opcode }, | |
7028 | { Bad_Opcode }, | |
7029 | { Bad_Opcode }, | |
7030 | { Bad_Opcode }, | |
f88c9eb0 | 7031 | /* 98 */ |
592d1631 L |
7032 | { Bad_Opcode }, |
7033 | { Bad_Opcode }, | |
7034 | { Bad_Opcode }, | |
7035 | { Bad_Opcode }, | |
7036 | { Bad_Opcode }, | |
7037 | { Bad_Opcode }, | |
7038 | { Bad_Opcode }, | |
7039 | { Bad_Opcode }, | |
f88c9eb0 | 7040 | /* a0 */ |
592d1631 L |
7041 | { Bad_Opcode }, |
7042 | { Bad_Opcode }, | |
7043 | { Bad_Opcode }, | |
7044 | { Bad_Opcode }, | |
7045 | { Bad_Opcode }, | |
7046 | { Bad_Opcode }, | |
7047 | { Bad_Opcode }, | |
7048 | { Bad_Opcode }, | |
f88c9eb0 | 7049 | /* a8 */ |
592d1631 L |
7050 | { Bad_Opcode }, |
7051 | { Bad_Opcode }, | |
7052 | { Bad_Opcode }, | |
7053 | { Bad_Opcode }, | |
7054 | { Bad_Opcode }, | |
7055 | { Bad_Opcode }, | |
7056 | { Bad_Opcode }, | |
7057 | { Bad_Opcode }, | |
f88c9eb0 | 7058 | /* b0 */ |
592d1631 L |
7059 | { Bad_Opcode }, |
7060 | { Bad_Opcode }, | |
7061 | { Bad_Opcode }, | |
7062 | { Bad_Opcode }, | |
7063 | { Bad_Opcode }, | |
7064 | { Bad_Opcode }, | |
7065 | { Bad_Opcode }, | |
7066 | { Bad_Opcode }, | |
f88c9eb0 | 7067 | /* b8 */ |
592d1631 L |
7068 | { Bad_Opcode }, |
7069 | { Bad_Opcode }, | |
7070 | { Bad_Opcode }, | |
7071 | { Bad_Opcode }, | |
7072 | { Bad_Opcode }, | |
7073 | { Bad_Opcode }, | |
7074 | { Bad_Opcode }, | |
7075 | { Bad_Opcode }, | |
f88c9eb0 | 7076 | /* c0 */ |
592d1631 L |
7077 | { Bad_Opcode }, |
7078 | { Bad_Opcode }, | |
7079 | { Bad_Opcode }, | |
7080 | { Bad_Opcode }, | |
7081 | { Bad_Opcode }, | |
7082 | { Bad_Opcode }, | |
7083 | { Bad_Opcode }, | |
7084 | { Bad_Opcode }, | |
f88c9eb0 | 7085 | /* c8 */ |
592d1631 L |
7086 | { Bad_Opcode }, |
7087 | { Bad_Opcode }, | |
7088 | { Bad_Opcode }, | |
7089 | { Bad_Opcode }, | |
a0046408 | 7090 | { PREFIX_TABLE (PREFIX_0F3ACC) }, |
592d1631 L |
7091 | { Bad_Opcode }, |
7092 | { Bad_Opcode }, | |
7093 | { Bad_Opcode }, | |
f88c9eb0 | 7094 | /* d0 */ |
592d1631 L |
7095 | { Bad_Opcode }, |
7096 | { Bad_Opcode }, | |
7097 | { Bad_Opcode }, | |
7098 | { Bad_Opcode }, | |
7099 | { Bad_Opcode }, | |
7100 | { Bad_Opcode }, | |
7101 | { Bad_Opcode }, | |
7102 | { Bad_Opcode }, | |
f88c9eb0 | 7103 | /* d8 */ |
592d1631 L |
7104 | { Bad_Opcode }, |
7105 | { Bad_Opcode }, | |
7106 | { Bad_Opcode }, | |
7107 | { Bad_Opcode }, | |
7108 | { Bad_Opcode }, | |
7109 | { Bad_Opcode }, | |
7110 | { Bad_Opcode }, | |
f88c9eb0 SP |
7111 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
7112 | /* e0 */ | |
592d1631 L |
7113 | { Bad_Opcode }, |
7114 | { Bad_Opcode }, | |
7115 | { Bad_Opcode }, | |
7116 | { Bad_Opcode }, | |
7117 | { Bad_Opcode }, | |
7118 | { Bad_Opcode }, | |
7119 | { Bad_Opcode }, | |
7120 | { Bad_Opcode }, | |
f88c9eb0 | 7121 | /* e8 */ |
592d1631 L |
7122 | { Bad_Opcode }, |
7123 | { Bad_Opcode }, | |
7124 | { Bad_Opcode }, | |
7125 | { Bad_Opcode }, | |
7126 | { Bad_Opcode }, | |
7127 | { Bad_Opcode }, | |
7128 | { Bad_Opcode }, | |
7129 | { Bad_Opcode }, | |
f88c9eb0 | 7130 | /* f0 */ |
592d1631 L |
7131 | { Bad_Opcode }, |
7132 | { Bad_Opcode }, | |
7133 | { Bad_Opcode }, | |
7134 | { Bad_Opcode }, | |
7135 | { Bad_Opcode }, | |
7136 | { Bad_Opcode }, | |
7137 | { Bad_Opcode }, | |
7138 | { Bad_Opcode }, | |
f88c9eb0 | 7139 | /* f8 */ |
592d1631 L |
7140 | { Bad_Opcode }, |
7141 | { Bad_Opcode }, | |
7142 | { Bad_Opcode }, | |
7143 | { Bad_Opcode }, | |
7144 | { Bad_Opcode }, | |
7145 | { Bad_Opcode }, | |
7146 | { Bad_Opcode }, | |
7147 | { Bad_Opcode }, | |
f88c9eb0 SP |
7148 | }, |
7149 | ||
7150 | /* THREE_BYTE_0F7A */ | |
7151 | { | |
7152 | /* 00 */ | |
592d1631 L |
7153 | { Bad_Opcode }, |
7154 | { Bad_Opcode }, | |
7155 | { Bad_Opcode }, | |
7156 | { Bad_Opcode }, | |
7157 | { Bad_Opcode }, | |
7158 | { Bad_Opcode }, | |
7159 | { Bad_Opcode }, | |
7160 | { Bad_Opcode }, | |
f88c9eb0 | 7161 | /* 08 */ |
592d1631 L |
7162 | { Bad_Opcode }, |
7163 | { Bad_Opcode }, | |
7164 | { Bad_Opcode }, | |
7165 | { Bad_Opcode }, | |
7166 | { Bad_Opcode }, | |
7167 | { Bad_Opcode }, | |
7168 | { Bad_Opcode }, | |
7169 | { Bad_Opcode }, | |
f88c9eb0 | 7170 | /* 10 */ |
592d1631 L |
7171 | { Bad_Opcode }, |
7172 | { Bad_Opcode }, | |
7173 | { Bad_Opcode }, | |
7174 | { Bad_Opcode }, | |
7175 | { Bad_Opcode }, | |
7176 | { Bad_Opcode }, | |
7177 | { Bad_Opcode }, | |
7178 | { Bad_Opcode }, | |
f88c9eb0 | 7179 | /* 18 */ |
592d1631 L |
7180 | { Bad_Opcode }, |
7181 | { Bad_Opcode }, | |
7182 | { Bad_Opcode }, | |
7183 | { Bad_Opcode }, | |
7184 | { Bad_Opcode }, | |
7185 | { Bad_Opcode }, | |
7186 | { Bad_Opcode }, | |
7187 | { Bad_Opcode }, | |
f88c9eb0 SP |
7188 | /* 20 */ |
7189 | { "ptest", { XX } }, | |
592d1631 L |
7190 | { Bad_Opcode }, |
7191 | { Bad_Opcode }, | |
7192 | { Bad_Opcode }, | |
7193 | { Bad_Opcode }, | |
7194 | { Bad_Opcode }, | |
7195 | { Bad_Opcode }, | |
7196 | { Bad_Opcode }, | |
f88c9eb0 | 7197 | /* 28 */ |
592d1631 L |
7198 | { Bad_Opcode }, |
7199 | { Bad_Opcode }, | |
7200 | { Bad_Opcode }, | |
7201 | { Bad_Opcode }, | |
7202 | { Bad_Opcode }, | |
7203 | { Bad_Opcode }, | |
7204 | { Bad_Opcode }, | |
7205 | { Bad_Opcode }, | |
f88c9eb0 | 7206 | /* 30 */ |
592d1631 L |
7207 | { Bad_Opcode }, |
7208 | { Bad_Opcode }, | |
7209 | { Bad_Opcode }, | |
7210 | { Bad_Opcode }, | |
7211 | { Bad_Opcode }, | |
7212 | { Bad_Opcode }, | |
7213 | { Bad_Opcode }, | |
7214 | { Bad_Opcode }, | |
f88c9eb0 | 7215 | /* 38 */ |
592d1631 L |
7216 | { Bad_Opcode }, |
7217 | { Bad_Opcode }, | |
7218 | { Bad_Opcode }, | |
7219 | { Bad_Opcode }, | |
7220 | { Bad_Opcode }, | |
7221 | { Bad_Opcode }, | |
7222 | { Bad_Opcode }, | |
7223 | { Bad_Opcode }, | |
f88c9eb0 | 7224 | /* 40 */ |
592d1631 | 7225 | { Bad_Opcode }, |
f88c9eb0 SP |
7226 | { "phaddbw", { XM, EXq } }, |
7227 | { "phaddbd", { XM, EXq } }, | |
7228 | { "phaddbq", { XM, EXq } }, | |
592d1631 L |
7229 | { Bad_Opcode }, |
7230 | { Bad_Opcode }, | |
f88c9eb0 SP |
7231 | { "phaddwd", { XM, EXq } }, |
7232 | { "phaddwq", { XM, EXq } }, | |
7233 | /* 48 */ | |
592d1631 L |
7234 | { Bad_Opcode }, |
7235 | { Bad_Opcode }, | |
7236 | { Bad_Opcode }, | |
f88c9eb0 | 7237 | { "phadddq", { XM, EXq } }, |
592d1631 L |
7238 | { Bad_Opcode }, |
7239 | { Bad_Opcode }, | |
7240 | { Bad_Opcode }, | |
7241 | { Bad_Opcode }, | |
f88c9eb0 | 7242 | /* 50 */ |
592d1631 | 7243 | { Bad_Opcode }, |
f88c9eb0 SP |
7244 | { "phaddubw", { XM, EXq } }, |
7245 | { "phaddubd", { XM, EXq } }, | |
7246 | { "phaddubq", { XM, EXq } }, | |
592d1631 L |
7247 | { Bad_Opcode }, |
7248 | { Bad_Opcode }, | |
f88c9eb0 SP |
7249 | { "phadduwd", { XM, EXq } }, |
7250 | { "phadduwq", { XM, EXq } }, | |
7251 | /* 58 */ | |
592d1631 L |
7252 | { Bad_Opcode }, |
7253 | { Bad_Opcode }, | |
7254 | { Bad_Opcode }, | |
f88c9eb0 | 7255 | { "phaddudq", { XM, EXq } }, |
592d1631 L |
7256 | { Bad_Opcode }, |
7257 | { Bad_Opcode }, | |
7258 | { Bad_Opcode }, | |
7259 | { Bad_Opcode }, | |
f88c9eb0 | 7260 | /* 60 */ |
592d1631 | 7261 | { Bad_Opcode }, |
f88c9eb0 SP |
7262 | { "phsubbw", { XM, EXq } }, |
7263 | { "phsubbd", { XM, EXq } }, | |
7264 | { "phsubbq", { XM, EXq } }, | |
592d1631 L |
7265 | { Bad_Opcode }, |
7266 | { Bad_Opcode }, | |
7267 | { Bad_Opcode }, | |
7268 | { Bad_Opcode }, | |
4e7d34a6 | 7269 | /* 68 */ |
592d1631 L |
7270 | { Bad_Opcode }, |
7271 | { Bad_Opcode }, | |
7272 | { Bad_Opcode }, | |
7273 | { Bad_Opcode }, | |
7274 | { Bad_Opcode }, | |
7275 | { Bad_Opcode }, | |
7276 | { Bad_Opcode }, | |
7277 | { Bad_Opcode }, | |
85f10a01 | 7278 | /* 70 */ |
592d1631 L |
7279 | { Bad_Opcode }, |
7280 | { Bad_Opcode }, | |
7281 | { Bad_Opcode }, | |
7282 | { Bad_Opcode }, | |
7283 | { Bad_Opcode }, | |
7284 | { Bad_Opcode }, | |
7285 | { Bad_Opcode }, | |
7286 | { Bad_Opcode }, | |
85f10a01 | 7287 | /* 78 */ |
592d1631 L |
7288 | { Bad_Opcode }, |
7289 | { Bad_Opcode }, | |
7290 | { Bad_Opcode }, | |
7291 | { Bad_Opcode }, | |
7292 | { Bad_Opcode }, | |
7293 | { Bad_Opcode }, | |
7294 | { Bad_Opcode }, | |
7295 | { Bad_Opcode }, | |
85f10a01 | 7296 | /* 80 */ |
592d1631 L |
7297 | { Bad_Opcode }, |
7298 | { Bad_Opcode }, | |
7299 | { Bad_Opcode }, | |
7300 | { Bad_Opcode }, | |
7301 | { Bad_Opcode }, | |
7302 | { Bad_Opcode }, | |
7303 | { Bad_Opcode }, | |
7304 | { Bad_Opcode }, | |
85f10a01 | 7305 | /* 88 */ |
592d1631 L |
7306 | { Bad_Opcode }, |
7307 | { Bad_Opcode }, | |
7308 | { Bad_Opcode }, | |
7309 | { Bad_Opcode }, | |
7310 | { Bad_Opcode }, | |
7311 | { Bad_Opcode }, | |
7312 | { Bad_Opcode }, | |
7313 | { Bad_Opcode }, | |
85f10a01 | 7314 | /* 90 */ |
592d1631 L |
7315 | { Bad_Opcode }, |
7316 | { Bad_Opcode }, | |
7317 | { Bad_Opcode }, | |
7318 | { Bad_Opcode }, | |
7319 | { Bad_Opcode }, | |
7320 | { Bad_Opcode }, | |
7321 | { Bad_Opcode }, | |
7322 | { Bad_Opcode }, | |
85f10a01 | 7323 | /* 98 */ |
592d1631 L |
7324 | { Bad_Opcode }, |
7325 | { Bad_Opcode }, | |
7326 | { Bad_Opcode }, | |
7327 | { Bad_Opcode }, | |
7328 | { Bad_Opcode }, | |
7329 | { Bad_Opcode }, | |
7330 | { Bad_Opcode }, | |
7331 | { Bad_Opcode }, | |
85f10a01 | 7332 | /* a0 */ |
592d1631 L |
7333 | { Bad_Opcode }, |
7334 | { Bad_Opcode }, | |
7335 | { Bad_Opcode }, | |
7336 | { Bad_Opcode }, | |
7337 | { Bad_Opcode }, | |
7338 | { Bad_Opcode }, | |
7339 | { Bad_Opcode }, | |
7340 | { Bad_Opcode }, | |
85f10a01 | 7341 | /* a8 */ |
592d1631 L |
7342 | { Bad_Opcode }, |
7343 | { Bad_Opcode }, | |
7344 | { Bad_Opcode }, | |
7345 | { Bad_Opcode }, | |
7346 | { Bad_Opcode }, | |
7347 | { Bad_Opcode }, | |
7348 | { Bad_Opcode }, | |
7349 | { Bad_Opcode }, | |
85f10a01 | 7350 | /* b0 */ |
592d1631 L |
7351 | { Bad_Opcode }, |
7352 | { Bad_Opcode }, | |
7353 | { Bad_Opcode }, | |
7354 | { Bad_Opcode }, | |
7355 | { Bad_Opcode }, | |
7356 | { Bad_Opcode }, | |
7357 | { Bad_Opcode }, | |
7358 | { Bad_Opcode }, | |
85f10a01 | 7359 | /* b8 */ |
592d1631 L |
7360 | { Bad_Opcode }, |
7361 | { Bad_Opcode }, | |
7362 | { Bad_Opcode }, | |
7363 | { Bad_Opcode }, | |
7364 | { Bad_Opcode }, | |
7365 | { Bad_Opcode }, | |
7366 | { Bad_Opcode }, | |
7367 | { Bad_Opcode }, | |
85f10a01 | 7368 | /* c0 */ |
592d1631 L |
7369 | { Bad_Opcode }, |
7370 | { Bad_Opcode }, | |
7371 | { Bad_Opcode }, | |
7372 | { Bad_Opcode }, | |
7373 | { Bad_Opcode }, | |
7374 | { Bad_Opcode }, | |
7375 | { Bad_Opcode }, | |
7376 | { Bad_Opcode }, | |
85f10a01 | 7377 | /* c8 */ |
592d1631 L |
7378 | { Bad_Opcode }, |
7379 | { Bad_Opcode }, | |
7380 | { Bad_Opcode }, | |
7381 | { Bad_Opcode }, | |
7382 | { Bad_Opcode }, | |
7383 | { Bad_Opcode }, | |
7384 | { Bad_Opcode }, | |
7385 | { Bad_Opcode }, | |
85f10a01 | 7386 | /* d0 */ |
592d1631 L |
7387 | { Bad_Opcode }, |
7388 | { Bad_Opcode }, | |
7389 | { Bad_Opcode }, | |
7390 | { Bad_Opcode }, | |
7391 | { Bad_Opcode }, | |
7392 | { Bad_Opcode }, | |
7393 | { Bad_Opcode }, | |
7394 | { Bad_Opcode }, | |
85f10a01 | 7395 | /* d8 */ |
592d1631 L |
7396 | { Bad_Opcode }, |
7397 | { Bad_Opcode }, | |
7398 | { Bad_Opcode }, | |
7399 | { Bad_Opcode }, | |
7400 | { Bad_Opcode }, | |
7401 | { Bad_Opcode }, | |
7402 | { Bad_Opcode }, | |
7403 | { Bad_Opcode }, | |
85f10a01 | 7404 | /* e0 */ |
592d1631 L |
7405 | { Bad_Opcode }, |
7406 | { Bad_Opcode }, | |
7407 | { Bad_Opcode }, | |
7408 | { Bad_Opcode }, | |
7409 | { Bad_Opcode }, | |
7410 | { Bad_Opcode }, | |
7411 | { Bad_Opcode }, | |
7412 | { Bad_Opcode }, | |
85f10a01 | 7413 | /* e8 */ |
592d1631 L |
7414 | { Bad_Opcode }, |
7415 | { Bad_Opcode }, | |
7416 | { Bad_Opcode }, | |
7417 | { Bad_Opcode }, | |
7418 | { Bad_Opcode }, | |
7419 | { Bad_Opcode }, | |
7420 | { Bad_Opcode }, | |
7421 | { Bad_Opcode }, | |
85f10a01 | 7422 | /* f0 */ |
592d1631 L |
7423 | { Bad_Opcode }, |
7424 | { Bad_Opcode }, | |
7425 | { Bad_Opcode }, | |
7426 | { Bad_Opcode }, | |
7427 | { Bad_Opcode }, | |
7428 | { Bad_Opcode }, | |
7429 | { Bad_Opcode }, | |
7430 | { Bad_Opcode }, | |
85f10a01 | 7431 | /* f8 */ |
592d1631 L |
7432 | { Bad_Opcode }, |
7433 | { Bad_Opcode }, | |
7434 | { Bad_Opcode }, | |
7435 | { Bad_Opcode }, | |
7436 | { Bad_Opcode }, | |
7437 | { Bad_Opcode }, | |
7438 | { Bad_Opcode }, | |
7439 | { Bad_Opcode }, | |
85f10a01 | 7440 | }, |
f88c9eb0 SP |
7441 | }; |
7442 | ||
7443 | static const struct dis386 xop_table[][256] = { | |
5dd85c99 | 7444 | /* XOP_08 */ |
85f10a01 MM |
7445 | { |
7446 | /* 00 */ | |
592d1631 L |
7447 | { Bad_Opcode }, |
7448 | { Bad_Opcode }, | |
7449 | { Bad_Opcode }, | |
7450 | { Bad_Opcode }, | |
7451 | { Bad_Opcode }, | |
7452 | { Bad_Opcode }, | |
7453 | { Bad_Opcode }, | |
7454 | { Bad_Opcode }, | |
85f10a01 | 7455 | /* 08 */ |
592d1631 L |
7456 | { Bad_Opcode }, |
7457 | { Bad_Opcode }, | |
7458 | { Bad_Opcode }, | |
7459 | { Bad_Opcode }, | |
7460 | { Bad_Opcode }, | |
7461 | { Bad_Opcode }, | |
7462 | { Bad_Opcode }, | |
7463 | { Bad_Opcode }, | |
85f10a01 | 7464 | /* 10 */ |
3929df09 | 7465 | { Bad_Opcode }, |
592d1631 L |
7466 | { Bad_Opcode }, |
7467 | { Bad_Opcode }, | |
7468 | { Bad_Opcode }, | |
7469 | { Bad_Opcode }, | |
7470 | { Bad_Opcode }, | |
7471 | { Bad_Opcode }, | |
7472 | { Bad_Opcode }, | |
85f10a01 | 7473 | /* 18 */ |
592d1631 L |
7474 | { Bad_Opcode }, |
7475 | { Bad_Opcode }, | |
7476 | { Bad_Opcode }, | |
7477 | { Bad_Opcode }, | |
7478 | { Bad_Opcode }, | |
7479 | { Bad_Opcode }, | |
7480 | { Bad_Opcode }, | |
7481 | { Bad_Opcode }, | |
85f10a01 | 7482 | /* 20 */ |
592d1631 L |
7483 | { Bad_Opcode }, |
7484 | { Bad_Opcode }, | |
7485 | { Bad_Opcode }, | |
7486 | { Bad_Opcode }, | |
7487 | { Bad_Opcode }, | |
7488 | { Bad_Opcode }, | |
7489 | { Bad_Opcode }, | |
7490 | { Bad_Opcode }, | |
85f10a01 | 7491 | /* 28 */ |
592d1631 L |
7492 | { Bad_Opcode }, |
7493 | { Bad_Opcode }, | |
7494 | { Bad_Opcode }, | |
7495 | { Bad_Opcode }, | |
7496 | { Bad_Opcode }, | |
7497 | { Bad_Opcode }, | |
7498 | { Bad_Opcode }, | |
7499 | { Bad_Opcode }, | |
c0f3af97 | 7500 | /* 30 */ |
592d1631 L |
7501 | { Bad_Opcode }, |
7502 | { Bad_Opcode }, | |
7503 | { Bad_Opcode }, | |
7504 | { Bad_Opcode }, | |
7505 | { Bad_Opcode }, | |
7506 | { Bad_Opcode }, | |
7507 | { Bad_Opcode }, | |
7508 | { Bad_Opcode }, | |
c0f3af97 | 7509 | /* 38 */ |
592d1631 L |
7510 | { Bad_Opcode }, |
7511 | { Bad_Opcode }, | |
7512 | { Bad_Opcode }, | |
7513 | { Bad_Opcode }, | |
7514 | { Bad_Opcode }, | |
7515 | { Bad_Opcode }, | |
7516 | { Bad_Opcode }, | |
7517 | { Bad_Opcode }, | |
c0f3af97 | 7518 | /* 40 */ |
592d1631 L |
7519 | { Bad_Opcode }, |
7520 | { Bad_Opcode }, | |
7521 | { Bad_Opcode }, | |
7522 | { Bad_Opcode }, | |
7523 | { Bad_Opcode }, | |
7524 | { Bad_Opcode }, | |
7525 | { Bad_Opcode }, | |
7526 | { Bad_Opcode }, | |
85f10a01 | 7527 | /* 48 */ |
592d1631 L |
7528 | { Bad_Opcode }, |
7529 | { Bad_Opcode }, | |
7530 | { Bad_Opcode }, | |
7531 | { Bad_Opcode }, | |
7532 | { Bad_Opcode }, | |
7533 | { Bad_Opcode }, | |
7534 | { Bad_Opcode }, | |
7535 | { Bad_Opcode }, | |
c0f3af97 | 7536 | /* 50 */ |
592d1631 L |
7537 | { Bad_Opcode }, |
7538 | { Bad_Opcode }, | |
7539 | { Bad_Opcode }, | |
7540 | { Bad_Opcode }, | |
7541 | { Bad_Opcode }, | |
7542 | { Bad_Opcode }, | |
7543 | { Bad_Opcode }, | |
7544 | { Bad_Opcode }, | |
85f10a01 | 7545 | /* 58 */ |
592d1631 L |
7546 | { Bad_Opcode }, |
7547 | { Bad_Opcode }, | |
7548 | { Bad_Opcode }, | |
7549 | { Bad_Opcode }, | |
7550 | { Bad_Opcode }, | |
7551 | { Bad_Opcode }, | |
7552 | { Bad_Opcode }, | |
7553 | { Bad_Opcode }, | |
c1e679ec | 7554 | /* 60 */ |
592d1631 L |
7555 | { Bad_Opcode }, |
7556 | { Bad_Opcode }, | |
7557 | { Bad_Opcode }, | |
7558 | { Bad_Opcode }, | |
7559 | { Bad_Opcode }, | |
7560 | { Bad_Opcode }, | |
7561 | { Bad_Opcode }, | |
7562 | { Bad_Opcode }, | |
c0f3af97 | 7563 | /* 68 */ |
592d1631 L |
7564 | { Bad_Opcode }, |
7565 | { Bad_Opcode }, | |
7566 | { Bad_Opcode }, | |
7567 | { Bad_Opcode }, | |
7568 | { Bad_Opcode }, | |
7569 | { Bad_Opcode }, | |
7570 | { Bad_Opcode }, | |
7571 | { Bad_Opcode }, | |
85f10a01 | 7572 | /* 70 */ |
592d1631 L |
7573 | { Bad_Opcode }, |
7574 | { Bad_Opcode }, | |
7575 | { Bad_Opcode }, | |
7576 | { Bad_Opcode }, | |
7577 | { Bad_Opcode }, | |
7578 | { Bad_Opcode }, | |
7579 | { Bad_Opcode }, | |
7580 | { Bad_Opcode }, | |
85f10a01 | 7581 | /* 78 */ |
592d1631 L |
7582 | { Bad_Opcode }, |
7583 | { Bad_Opcode }, | |
7584 | { Bad_Opcode }, | |
7585 | { Bad_Opcode }, | |
7586 | { Bad_Opcode }, | |
7587 | { Bad_Opcode }, | |
7588 | { Bad_Opcode }, | |
7589 | { Bad_Opcode }, | |
85f10a01 | 7590 | /* 80 */ |
592d1631 L |
7591 | { Bad_Opcode }, |
7592 | { Bad_Opcode }, | |
7593 | { Bad_Opcode }, | |
7594 | { Bad_Opcode }, | |
7595 | { Bad_Opcode }, | |
5dd85c99 SP |
7596 | { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
7597 | { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
7598 | { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
7599 | /* 88 */ | |
592d1631 L |
7600 | { Bad_Opcode }, |
7601 | { Bad_Opcode }, | |
7602 | { Bad_Opcode }, | |
7603 | { Bad_Opcode }, | |
7604 | { Bad_Opcode }, | |
7605 | { Bad_Opcode }, | |
5dd85c99 SP |
7606 | { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
7607 | { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
7608 | /* 90 */ | |
592d1631 L |
7609 | { Bad_Opcode }, |
7610 | { Bad_Opcode }, | |
7611 | { Bad_Opcode }, | |
7612 | { Bad_Opcode }, | |
7613 | { Bad_Opcode }, | |
5dd85c99 SP |
7614 | { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
7615 | { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
7616 | { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
7617 | /* 98 */ | |
592d1631 L |
7618 | { Bad_Opcode }, |
7619 | { Bad_Opcode }, | |
7620 | { Bad_Opcode }, | |
7621 | { Bad_Opcode }, | |
7622 | { Bad_Opcode }, | |
7623 | { Bad_Opcode }, | |
5dd85c99 SP |
7624 | { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
7625 | { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
7626 | /* a0 */ | |
592d1631 L |
7627 | { Bad_Opcode }, |
7628 | { Bad_Opcode }, | |
5dd85c99 SP |
7629 | { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
7630 | { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
592d1631 L |
7631 | { Bad_Opcode }, |
7632 | { Bad_Opcode }, | |
5dd85c99 | 7633 | { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
592d1631 | 7634 | { Bad_Opcode }, |
5dd85c99 | 7635 | /* a8 */ |
592d1631 L |
7636 | { Bad_Opcode }, |
7637 | { Bad_Opcode }, | |
7638 | { Bad_Opcode }, | |
7639 | { Bad_Opcode }, | |
7640 | { Bad_Opcode }, | |
7641 | { Bad_Opcode }, | |
7642 | { Bad_Opcode }, | |
7643 | { Bad_Opcode }, | |
5dd85c99 | 7644 | /* b0 */ |
592d1631 L |
7645 | { Bad_Opcode }, |
7646 | { Bad_Opcode }, | |
7647 | { Bad_Opcode }, | |
7648 | { Bad_Opcode }, | |
7649 | { Bad_Opcode }, | |
7650 | { Bad_Opcode }, | |
5dd85c99 | 7651 | { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
592d1631 | 7652 | { Bad_Opcode }, |
5dd85c99 | 7653 | /* b8 */ |
592d1631 L |
7654 | { Bad_Opcode }, |
7655 | { Bad_Opcode }, | |
7656 | { Bad_Opcode }, | |
7657 | { Bad_Opcode }, | |
7658 | { Bad_Opcode }, | |
7659 | { Bad_Opcode }, | |
7660 | { Bad_Opcode }, | |
7661 | { Bad_Opcode }, | |
5dd85c99 SP |
7662 | /* c0 */ |
7663 | { "vprotb", { XM, Vex_2src_1, Ib } }, | |
7664 | { "vprotw", { XM, Vex_2src_1, Ib } }, | |
7665 | { "vprotd", { XM, Vex_2src_1, Ib } }, | |
7666 | { "vprotq", { XM, Vex_2src_1, Ib } }, | |
592d1631 L |
7667 | { Bad_Opcode }, |
7668 | { Bad_Opcode }, | |
7669 | { Bad_Opcode }, | |
7670 | { Bad_Opcode }, | |
5dd85c99 | 7671 | /* c8 */ |
592d1631 L |
7672 | { Bad_Opcode }, |
7673 | { Bad_Opcode }, | |
7674 | { Bad_Opcode }, | |
7675 | { Bad_Opcode }, | |
ff688e1f L |
7676 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, |
7677 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, | |
7678 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, | |
7679 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, | |
5dd85c99 | 7680 | /* d0 */ |
592d1631 L |
7681 | { Bad_Opcode }, |
7682 | { Bad_Opcode }, | |
7683 | { Bad_Opcode }, | |
7684 | { Bad_Opcode }, | |
7685 | { Bad_Opcode }, | |
7686 | { Bad_Opcode }, | |
7687 | { Bad_Opcode }, | |
7688 | { Bad_Opcode }, | |
5dd85c99 | 7689 | /* d8 */ |
592d1631 L |
7690 | { Bad_Opcode }, |
7691 | { Bad_Opcode }, | |
7692 | { Bad_Opcode }, | |
7693 | { Bad_Opcode }, | |
7694 | { Bad_Opcode }, | |
7695 | { Bad_Opcode }, | |
7696 | { Bad_Opcode }, | |
7697 | { Bad_Opcode }, | |
5dd85c99 | 7698 | /* e0 */ |
592d1631 L |
7699 | { Bad_Opcode }, |
7700 | { Bad_Opcode }, | |
7701 | { Bad_Opcode }, | |
7702 | { Bad_Opcode }, | |
7703 | { Bad_Opcode }, | |
7704 | { Bad_Opcode }, | |
7705 | { Bad_Opcode }, | |
7706 | { Bad_Opcode }, | |
5dd85c99 | 7707 | /* e8 */ |
592d1631 L |
7708 | { Bad_Opcode }, |
7709 | { Bad_Opcode }, | |
7710 | { Bad_Opcode }, | |
7711 | { Bad_Opcode }, | |
ff688e1f L |
7712 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, |
7713 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, | |
7714 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, | |
7715 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, | |
5dd85c99 | 7716 | /* f0 */ |
592d1631 L |
7717 | { Bad_Opcode }, |
7718 | { Bad_Opcode }, | |
7719 | { Bad_Opcode }, | |
7720 | { Bad_Opcode }, | |
7721 | { Bad_Opcode }, | |
7722 | { Bad_Opcode }, | |
7723 | { Bad_Opcode }, | |
7724 | { Bad_Opcode }, | |
5dd85c99 | 7725 | /* f8 */ |
592d1631 L |
7726 | { Bad_Opcode }, |
7727 | { Bad_Opcode }, | |
7728 | { Bad_Opcode }, | |
7729 | { Bad_Opcode }, | |
7730 | { Bad_Opcode }, | |
7731 | { Bad_Opcode }, | |
7732 | { Bad_Opcode }, | |
7733 | { Bad_Opcode }, | |
5dd85c99 SP |
7734 | }, |
7735 | /* XOP_09 */ | |
7736 | { | |
7737 | /* 00 */ | |
592d1631 | 7738 | { Bad_Opcode }, |
2a2a0f38 QN |
7739 | { REG_TABLE (REG_XOP_TBM_01) }, |
7740 | { REG_TABLE (REG_XOP_TBM_02) }, | |
592d1631 L |
7741 | { Bad_Opcode }, |
7742 | { Bad_Opcode }, | |
7743 | { Bad_Opcode }, | |
7744 | { Bad_Opcode }, | |
7745 | { Bad_Opcode }, | |
5dd85c99 | 7746 | /* 08 */ |
592d1631 L |
7747 | { Bad_Opcode }, |
7748 | { Bad_Opcode }, | |
7749 | { Bad_Opcode }, | |
7750 | { Bad_Opcode }, | |
7751 | { Bad_Opcode }, | |
7752 | { Bad_Opcode }, | |
7753 | { Bad_Opcode }, | |
7754 | { Bad_Opcode }, | |
5dd85c99 | 7755 | /* 10 */ |
592d1631 L |
7756 | { Bad_Opcode }, |
7757 | { Bad_Opcode }, | |
5dd85c99 | 7758 | { REG_TABLE (REG_XOP_LWPCB) }, |
592d1631 L |
7759 | { Bad_Opcode }, |
7760 | { Bad_Opcode }, | |
7761 | { Bad_Opcode }, | |
7762 | { Bad_Opcode }, | |
7763 | { Bad_Opcode }, | |
5dd85c99 | 7764 | /* 18 */ |
592d1631 L |
7765 | { Bad_Opcode }, |
7766 | { Bad_Opcode }, | |
7767 | { Bad_Opcode }, | |
7768 | { Bad_Opcode }, | |
7769 | { Bad_Opcode }, | |
7770 | { Bad_Opcode }, | |
7771 | { Bad_Opcode }, | |
7772 | { Bad_Opcode }, | |
5dd85c99 | 7773 | /* 20 */ |
592d1631 L |
7774 | { Bad_Opcode }, |
7775 | { Bad_Opcode }, | |
7776 | { Bad_Opcode }, | |
7777 | { Bad_Opcode }, | |
7778 | { Bad_Opcode }, | |
7779 | { Bad_Opcode }, | |
7780 | { Bad_Opcode }, | |
7781 | { Bad_Opcode }, | |
5dd85c99 | 7782 | /* 28 */ |
592d1631 L |
7783 | { Bad_Opcode }, |
7784 | { Bad_Opcode }, | |
7785 | { Bad_Opcode }, | |
7786 | { Bad_Opcode }, | |
7787 | { Bad_Opcode }, | |
7788 | { Bad_Opcode }, | |
7789 | { Bad_Opcode }, | |
7790 | { Bad_Opcode }, | |
5dd85c99 | 7791 | /* 30 */ |
592d1631 L |
7792 | { Bad_Opcode }, |
7793 | { Bad_Opcode }, | |
7794 | { Bad_Opcode }, | |
7795 | { Bad_Opcode }, | |
7796 | { Bad_Opcode }, | |
7797 | { Bad_Opcode }, | |
7798 | { Bad_Opcode }, | |
7799 | { Bad_Opcode }, | |
5dd85c99 | 7800 | /* 38 */ |
592d1631 L |
7801 | { Bad_Opcode }, |
7802 | { Bad_Opcode }, | |
7803 | { Bad_Opcode }, | |
7804 | { Bad_Opcode }, | |
7805 | { Bad_Opcode }, | |
7806 | { Bad_Opcode }, | |
7807 | { Bad_Opcode }, | |
7808 | { Bad_Opcode }, | |
5dd85c99 | 7809 | /* 40 */ |
592d1631 L |
7810 | { Bad_Opcode }, |
7811 | { Bad_Opcode }, | |
7812 | { Bad_Opcode }, | |
7813 | { Bad_Opcode }, | |
7814 | { Bad_Opcode }, | |
7815 | { Bad_Opcode }, | |
7816 | { Bad_Opcode }, | |
7817 | { Bad_Opcode }, | |
5dd85c99 | 7818 | /* 48 */ |
592d1631 L |
7819 | { Bad_Opcode }, |
7820 | { Bad_Opcode }, | |
7821 | { Bad_Opcode }, | |
7822 | { Bad_Opcode }, | |
7823 | { Bad_Opcode }, | |
7824 | { Bad_Opcode }, | |
7825 | { Bad_Opcode }, | |
7826 | { Bad_Opcode }, | |
5dd85c99 | 7827 | /* 50 */ |
592d1631 L |
7828 | { Bad_Opcode }, |
7829 | { Bad_Opcode }, | |
7830 | { Bad_Opcode }, | |
7831 | { Bad_Opcode }, | |
7832 | { Bad_Opcode }, | |
7833 | { Bad_Opcode }, | |
7834 | { Bad_Opcode }, | |
7835 | { Bad_Opcode }, | |
5dd85c99 | 7836 | /* 58 */ |
592d1631 L |
7837 | { Bad_Opcode }, |
7838 | { Bad_Opcode }, | |
7839 | { Bad_Opcode }, | |
7840 | { Bad_Opcode }, | |
7841 | { Bad_Opcode }, | |
7842 | { Bad_Opcode }, | |
7843 | { Bad_Opcode }, | |
7844 | { Bad_Opcode }, | |
5dd85c99 | 7845 | /* 60 */ |
592d1631 L |
7846 | { Bad_Opcode }, |
7847 | { Bad_Opcode }, | |
7848 | { Bad_Opcode }, | |
7849 | { Bad_Opcode }, | |
7850 | { Bad_Opcode }, | |
7851 | { Bad_Opcode }, | |
7852 | { Bad_Opcode }, | |
7853 | { Bad_Opcode }, | |
5dd85c99 | 7854 | /* 68 */ |
592d1631 L |
7855 | { Bad_Opcode }, |
7856 | { Bad_Opcode }, | |
7857 | { Bad_Opcode }, | |
7858 | { Bad_Opcode }, | |
7859 | { Bad_Opcode }, | |
7860 | { Bad_Opcode }, | |
7861 | { Bad_Opcode }, | |
7862 | { Bad_Opcode }, | |
5dd85c99 | 7863 | /* 70 */ |
592d1631 L |
7864 | { Bad_Opcode }, |
7865 | { Bad_Opcode }, | |
7866 | { Bad_Opcode }, | |
7867 | { Bad_Opcode }, | |
7868 | { Bad_Opcode }, | |
7869 | { Bad_Opcode }, | |
7870 | { Bad_Opcode }, | |
7871 | { Bad_Opcode }, | |
5dd85c99 | 7872 | /* 78 */ |
592d1631 L |
7873 | { Bad_Opcode }, |
7874 | { Bad_Opcode }, | |
7875 | { Bad_Opcode }, | |
7876 | { Bad_Opcode }, | |
7877 | { Bad_Opcode }, | |
7878 | { Bad_Opcode }, | |
7879 | { Bad_Opcode }, | |
7880 | { Bad_Opcode }, | |
5dd85c99 | 7881 | /* 80 */ |
592a252b L |
7882 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, |
7883 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, | |
5dd85c99 SP |
7884 | { "vfrczss", { XM, EXd } }, |
7885 | { "vfrczsd", { XM, EXq } }, | |
592d1631 L |
7886 | { Bad_Opcode }, |
7887 | { Bad_Opcode }, | |
7888 | { Bad_Opcode }, | |
7889 | { Bad_Opcode }, | |
5dd85c99 | 7890 | /* 88 */ |
592d1631 L |
7891 | { Bad_Opcode }, |
7892 | { Bad_Opcode }, | |
7893 | { Bad_Opcode }, | |
7894 | { Bad_Opcode }, | |
7895 | { Bad_Opcode }, | |
7896 | { Bad_Opcode }, | |
7897 | { Bad_Opcode }, | |
7898 | { Bad_Opcode }, | |
5dd85c99 SP |
7899 | /* 90 */ |
7900 | { "vprotb", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7901 | { "vprotw", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7902 | { "vprotd", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7903 | { "vprotq", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7904 | { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7905 | { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7906 | { "vpshld", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7907 | { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7908 | /* 98 */ | |
7909 | { "vpshab", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7910 | { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7911 | { "vpshad", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7912 | { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 } }, | |
592d1631 L |
7913 | { Bad_Opcode }, |
7914 | { Bad_Opcode }, | |
7915 | { Bad_Opcode }, | |
7916 | { Bad_Opcode }, | |
5dd85c99 | 7917 | /* a0 */ |
592d1631 L |
7918 | { Bad_Opcode }, |
7919 | { Bad_Opcode }, | |
7920 | { Bad_Opcode }, | |
7921 | { Bad_Opcode }, | |
7922 | { Bad_Opcode }, | |
7923 | { Bad_Opcode }, | |
7924 | { Bad_Opcode }, | |
7925 | { Bad_Opcode }, | |
5dd85c99 | 7926 | /* a8 */ |
592d1631 L |
7927 | { Bad_Opcode }, |
7928 | { Bad_Opcode }, | |
7929 | { Bad_Opcode }, | |
7930 | { Bad_Opcode }, | |
7931 | { Bad_Opcode }, | |
7932 | { Bad_Opcode }, | |
7933 | { Bad_Opcode }, | |
7934 | { Bad_Opcode }, | |
5dd85c99 | 7935 | /* b0 */ |
592d1631 L |
7936 | { Bad_Opcode }, |
7937 | { Bad_Opcode }, | |
7938 | { Bad_Opcode }, | |
7939 | { Bad_Opcode }, | |
7940 | { Bad_Opcode }, | |
7941 | { Bad_Opcode }, | |
7942 | { Bad_Opcode }, | |
7943 | { Bad_Opcode }, | |
5dd85c99 | 7944 | /* b8 */ |
592d1631 L |
7945 | { Bad_Opcode }, |
7946 | { Bad_Opcode }, | |
7947 | { Bad_Opcode }, | |
7948 | { Bad_Opcode }, | |
7949 | { Bad_Opcode }, | |
7950 | { Bad_Opcode }, | |
7951 | { Bad_Opcode }, | |
7952 | { Bad_Opcode }, | |
5dd85c99 | 7953 | /* c0 */ |
592d1631 | 7954 | { Bad_Opcode }, |
5dd85c99 SP |
7955 | { "vphaddbw", { XM, EXxmm } }, |
7956 | { "vphaddbd", { XM, EXxmm } }, | |
7957 | { "vphaddbq", { XM, EXxmm } }, | |
592d1631 L |
7958 | { Bad_Opcode }, |
7959 | { Bad_Opcode }, | |
5dd85c99 SP |
7960 | { "vphaddwd", { XM, EXxmm } }, |
7961 | { "vphaddwq", { XM, EXxmm } }, | |
7962 | /* c8 */ | |
592d1631 L |
7963 | { Bad_Opcode }, |
7964 | { Bad_Opcode }, | |
7965 | { Bad_Opcode }, | |
5dd85c99 | 7966 | { "vphadddq", { XM, EXxmm } }, |
592d1631 L |
7967 | { Bad_Opcode }, |
7968 | { Bad_Opcode }, | |
7969 | { Bad_Opcode }, | |
7970 | { Bad_Opcode }, | |
5dd85c99 | 7971 | /* d0 */ |
592d1631 | 7972 | { Bad_Opcode }, |
5dd85c99 SP |
7973 | { "vphaddubw", { XM, EXxmm } }, |
7974 | { "vphaddubd", { XM, EXxmm } }, | |
7975 | { "vphaddubq", { XM, EXxmm } }, | |
592d1631 L |
7976 | { Bad_Opcode }, |
7977 | { Bad_Opcode }, | |
5dd85c99 SP |
7978 | { "vphadduwd", { XM, EXxmm } }, |
7979 | { "vphadduwq", { XM, EXxmm } }, | |
7980 | /* d8 */ | |
592d1631 L |
7981 | { Bad_Opcode }, |
7982 | { Bad_Opcode }, | |
7983 | { Bad_Opcode }, | |
5dd85c99 | 7984 | { "vphaddudq", { XM, EXxmm } }, |
592d1631 L |
7985 | { Bad_Opcode }, |
7986 | { Bad_Opcode }, | |
7987 | { Bad_Opcode }, | |
7988 | { Bad_Opcode }, | |
5dd85c99 | 7989 | /* e0 */ |
592d1631 | 7990 | { Bad_Opcode }, |
5dd85c99 SP |
7991 | { "vphsubbw", { XM, EXxmm } }, |
7992 | { "vphsubwd", { XM, EXxmm } }, | |
7993 | { "vphsubdq", { XM, EXxmm } }, | |
592d1631 L |
7994 | { Bad_Opcode }, |
7995 | { Bad_Opcode }, | |
7996 | { Bad_Opcode }, | |
7997 | { Bad_Opcode }, | |
4e7d34a6 | 7998 | /* e8 */ |
592d1631 L |
7999 | { Bad_Opcode }, |
8000 | { Bad_Opcode }, | |
8001 | { Bad_Opcode }, | |
8002 | { Bad_Opcode }, | |
8003 | { Bad_Opcode }, | |
8004 | { Bad_Opcode }, | |
8005 | { Bad_Opcode }, | |
8006 | { Bad_Opcode }, | |
4e7d34a6 | 8007 | /* f0 */ |
592d1631 L |
8008 | { Bad_Opcode }, |
8009 | { Bad_Opcode }, | |
8010 | { Bad_Opcode }, | |
8011 | { Bad_Opcode }, | |
8012 | { Bad_Opcode }, | |
8013 | { Bad_Opcode }, | |
8014 | { Bad_Opcode }, | |
8015 | { Bad_Opcode }, | |
4e7d34a6 | 8016 | /* f8 */ |
592d1631 L |
8017 | { Bad_Opcode }, |
8018 | { Bad_Opcode }, | |
8019 | { Bad_Opcode }, | |
8020 | { Bad_Opcode }, | |
8021 | { Bad_Opcode }, | |
8022 | { Bad_Opcode }, | |
8023 | { Bad_Opcode }, | |
8024 | { Bad_Opcode }, | |
4e7d34a6 | 8025 | }, |
f88c9eb0 | 8026 | /* XOP_0A */ |
4e7d34a6 L |
8027 | { |
8028 | /* 00 */ | |
592d1631 L |
8029 | { Bad_Opcode }, |
8030 | { Bad_Opcode }, | |
8031 | { Bad_Opcode }, | |
8032 | { Bad_Opcode }, | |
8033 | { Bad_Opcode }, | |
8034 | { Bad_Opcode }, | |
8035 | { Bad_Opcode }, | |
8036 | { Bad_Opcode }, | |
4e7d34a6 | 8037 | /* 08 */ |
592d1631 L |
8038 | { Bad_Opcode }, |
8039 | { Bad_Opcode }, | |
8040 | { Bad_Opcode }, | |
8041 | { Bad_Opcode }, | |
8042 | { Bad_Opcode }, | |
8043 | { Bad_Opcode }, | |
8044 | { Bad_Opcode }, | |
8045 | { Bad_Opcode }, | |
4e7d34a6 | 8046 | /* 10 */ |
2a2a0f38 | 8047 | { "bextr", { Gv, Ev, Iq } }, |
592d1631 | 8048 | { Bad_Opcode }, |
f88c9eb0 | 8049 | { REG_TABLE (REG_XOP_LWP) }, |
592d1631 L |
8050 | { Bad_Opcode }, |
8051 | { Bad_Opcode }, | |
8052 | { Bad_Opcode }, | |
8053 | { Bad_Opcode }, | |
8054 | { Bad_Opcode }, | |
4e7d34a6 | 8055 | /* 18 */ |
592d1631 L |
8056 | { Bad_Opcode }, |
8057 | { Bad_Opcode }, | |
8058 | { Bad_Opcode }, | |
8059 | { Bad_Opcode }, | |
8060 | { Bad_Opcode }, | |
8061 | { Bad_Opcode }, | |
8062 | { Bad_Opcode }, | |
8063 | { Bad_Opcode }, | |
4e7d34a6 | 8064 | /* 20 */ |
592d1631 L |
8065 | { Bad_Opcode }, |
8066 | { Bad_Opcode }, | |
8067 | { Bad_Opcode }, | |
8068 | { Bad_Opcode }, | |
8069 | { Bad_Opcode }, | |
8070 | { Bad_Opcode }, | |
8071 | { Bad_Opcode }, | |
8072 | { Bad_Opcode }, | |
4e7d34a6 | 8073 | /* 28 */ |
592d1631 L |
8074 | { Bad_Opcode }, |
8075 | { Bad_Opcode }, | |
8076 | { Bad_Opcode }, | |
8077 | { Bad_Opcode }, | |
8078 | { Bad_Opcode }, | |
8079 | { Bad_Opcode }, | |
8080 | { Bad_Opcode }, | |
8081 | { Bad_Opcode }, | |
4e7d34a6 | 8082 | /* 30 */ |
592d1631 L |
8083 | { Bad_Opcode }, |
8084 | { Bad_Opcode }, | |
8085 | { Bad_Opcode }, | |
8086 | { Bad_Opcode }, | |
8087 | { Bad_Opcode }, | |
8088 | { Bad_Opcode }, | |
8089 | { Bad_Opcode }, | |
8090 | { Bad_Opcode }, | |
c0f3af97 | 8091 | /* 38 */ |
592d1631 L |
8092 | { Bad_Opcode }, |
8093 | { Bad_Opcode }, | |
8094 | { Bad_Opcode }, | |
8095 | { Bad_Opcode }, | |
8096 | { Bad_Opcode }, | |
8097 | { Bad_Opcode }, | |
8098 | { Bad_Opcode }, | |
8099 | { Bad_Opcode }, | |
c0f3af97 | 8100 | /* 40 */ |
592d1631 L |
8101 | { Bad_Opcode }, |
8102 | { Bad_Opcode }, | |
8103 | { Bad_Opcode }, | |
8104 | { Bad_Opcode }, | |
8105 | { Bad_Opcode }, | |
8106 | { Bad_Opcode }, | |
8107 | { Bad_Opcode }, | |
8108 | { Bad_Opcode }, | |
c1e679ec | 8109 | /* 48 */ |
592d1631 L |
8110 | { Bad_Opcode }, |
8111 | { Bad_Opcode }, | |
8112 | { Bad_Opcode }, | |
8113 | { Bad_Opcode }, | |
8114 | { Bad_Opcode }, | |
8115 | { Bad_Opcode }, | |
8116 | { Bad_Opcode }, | |
8117 | { Bad_Opcode }, | |
c1e679ec | 8118 | /* 50 */ |
592d1631 L |
8119 | { Bad_Opcode }, |
8120 | { Bad_Opcode }, | |
8121 | { Bad_Opcode }, | |
8122 | { Bad_Opcode }, | |
8123 | { Bad_Opcode }, | |
8124 | { Bad_Opcode }, | |
8125 | { Bad_Opcode }, | |
8126 | { Bad_Opcode }, | |
4e7d34a6 | 8127 | /* 58 */ |
592d1631 L |
8128 | { Bad_Opcode }, |
8129 | { Bad_Opcode }, | |
8130 | { Bad_Opcode }, | |
8131 | { Bad_Opcode }, | |
8132 | { Bad_Opcode }, | |
8133 | { Bad_Opcode }, | |
8134 | { Bad_Opcode }, | |
8135 | { Bad_Opcode }, | |
4e7d34a6 | 8136 | /* 60 */ |
592d1631 L |
8137 | { Bad_Opcode }, |
8138 | { Bad_Opcode }, | |
8139 | { Bad_Opcode }, | |
8140 | { Bad_Opcode }, | |
8141 | { Bad_Opcode }, | |
8142 | { Bad_Opcode }, | |
8143 | { Bad_Opcode }, | |
8144 | { Bad_Opcode }, | |
4e7d34a6 | 8145 | /* 68 */ |
592d1631 L |
8146 | { Bad_Opcode }, |
8147 | { Bad_Opcode }, | |
8148 | { Bad_Opcode }, | |
8149 | { Bad_Opcode }, | |
8150 | { Bad_Opcode }, | |
8151 | { Bad_Opcode }, | |
8152 | { Bad_Opcode }, | |
8153 | { Bad_Opcode }, | |
4e7d34a6 | 8154 | /* 70 */ |
592d1631 L |
8155 | { Bad_Opcode }, |
8156 | { Bad_Opcode }, | |
8157 | { Bad_Opcode }, | |
8158 | { Bad_Opcode }, | |
8159 | { Bad_Opcode }, | |
8160 | { Bad_Opcode }, | |
8161 | { Bad_Opcode }, | |
8162 | { Bad_Opcode }, | |
4e7d34a6 | 8163 | /* 78 */ |
592d1631 L |
8164 | { Bad_Opcode }, |
8165 | { Bad_Opcode }, | |
8166 | { Bad_Opcode }, | |
8167 | { Bad_Opcode }, | |
8168 | { Bad_Opcode }, | |
8169 | { Bad_Opcode }, | |
8170 | { Bad_Opcode }, | |
8171 | { Bad_Opcode }, | |
4e7d34a6 | 8172 | /* 80 */ |
592d1631 L |
8173 | { Bad_Opcode }, |
8174 | { Bad_Opcode }, | |
8175 | { Bad_Opcode }, | |
8176 | { Bad_Opcode }, | |
8177 | { Bad_Opcode }, | |
8178 | { Bad_Opcode }, | |
8179 | { Bad_Opcode }, | |
8180 | { Bad_Opcode }, | |
4e7d34a6 | 8181 | /* 88 */ |
592d1631 L |
8182 | { Bad_Opcode }, |
8183 | { Bad_Opcode }, | |
8184 | { Bad_Opcode }, | |
8185 | { Bad_Opcode }, | |
8186 | { Bad_Opcode }, | |
8187 | { Bad_Opcode }, | |
8188 | { Bad_Opcode }, | |
8189 | { Bad_Opcode }, | |
4e7d34a6 | 8190 | /* 90 */ |
592d1631 L |
8191 | { Bad_Opcode }, |
8192 | { Bad_Opcode }, | |
8193 | { Bad_Opcode }, | |
8194 | { Bad_Opcode }, | |
8195 | { Bad_Opcode }, | |
8196 | { Bad_Opcode }, | |
8197 | { Bad_Opcode }, | |
8198 | { Bad_Opcode }, | |
4e7d34a6 | 8199 | /* 98 */ |
592d1631 L |
8200 | { Bad_Opcode }, |
8201 | { Bad_Opcode }, | |
8202 | { Bad_Opcode }, | |
8203 | { Bad_Opcode }, | |
8204 | { Bad_Opcode }, | |
8205 | { Bad_Opcode }, | |
8206 | { Bad_Opcode }, | |
8207 | { Bad_Opcode }, | |
4e7d34a6 | 8208 | /* a0 */ |
592d1631 L |
8209 | { Bad_Opcode }, |
8210 | { Bad_Opcode }, | |
8211 | { Bad_Opcode }, | |
8212 | { Bad_Opcode }, | |
8213 | { Bad_Opcode }, | |
8214 | { Bad_Opcode }, | |
8215 | { Bad_Opcode }, | |
8216 | { Bad_Opcode }, | |
4e7d34a6 | 8217 | /* a8 */ |
592d1631 L |
8218 | { Bad_Opcode }, |
8219 | { Bad_Opcode }, | |
8220 | { Bad_Opcode }, | |
8221 | { Bad_Opcode }, | |
8222 | { Bad_Opcode }, | |
8223 | { Bad_Opcode }, | |
8224 | { Bad_Opcode }, | |
8225 | { Bad_Opcode }, | |
d5d7db8e | 8226 | /* b0 */ |
592d1631 L |
8227 | { Bad_Opcode }, |
8228 | { Bad_Opcode }, | |
8229 | { Bad_Opcode }, | |
8230 | { Bad_Opcode }, | |
8231 | { Bad_Opcode }, | |
8232 | { Bad_Opcode }, | |
8233 | { Bad_Opcode }, | |
8234 | { Bad_Opcode }, | |
85f10a01 | 8235 | /* b8 */ |
592d1631 L |
8236 | { Bad_Opcode }, |
8237 | { Bad_Opcode }, | |
8238 | { Bad_Opcode }, | |
8239 | { Bad_Opcode }, | |
8240 | { Bad_Opcode }, | |
8241 | { Bad_Opcode }, | |
8242 | { Bad_Opcode }, | |
8243 | { Bad_Opcode }, | |
85f10a01 | 8244 | /* c0 */ |
592d1631 L |
8245 | { Bad_Opcode }, |
8246 | { Bad_Opcode }, | |
8247 | { Bad_Opcode }, | |
8248 | { Bad_Opcode }, | |
8249 | { Bad_Opcode }, | |
8250 | { Bad_Opcode }, | |
8251 | { Bad_Opcode }, | |
8252 | { Bad_Opcode }, | |
85f10a01 | 8253 | /* c8 */ |
592d1631 L |
8254 | { Bad_Opcode }, |
8255 | { Bad_Opcode }, | |
8256 | { Bad_Opcode }, | |
8257 | { Bad_Opcode }, | |
8258 | { Bad_Opcode }, | |
8259 | { Bad_Opcode }, | |
8260 | { Bad_Opcode }, | |
8261 | { Bad_Opcode }, | |
85f10a01 | 8262 | /* d0 */ |
592d1631 L |
8263 | { Bad_Opcode }, |
8264 | { Bad_Opcode }, | |
8265 | { Bad_Opcode }, | |
8266 | { Bad_Opcode }, | |
8267 | { Bad_Opcode }, | |
8268 | { Bad_Opcode }, | |
8269 | { Bad_Opcode }, | |
8270 | { Bad_Opcode }, | |
85f10a01 | 8271 | /* d8 */ |
592d1631 L |
8272 | { Bad_Opcode }, |
8273 | { Bad_Opcode }, | |
8274 | { Bad_Opcode }, | |
8275 | { Bad_Opcode }, | |
8276 | { Bad_Opcode }, | |
8277 | { Bad_Opcode }, | |
8278 | { Bad_Opcode }, | |
8279 | { Bad_Opcode }, | |
85f10a01 | 8280 | /* e0 */ |
592d1631 L |
8281 | { Bad_Opcode }, |
8282 | { Bad_Opcode }, | |
8283 | { Bad_Opcode }, | |
8284 | { Bad_Opcode }, | |
8285 | { Bad_Opcode }, | |
8286 | { Bad_Opcode }, | |
8287 | { Bad_Opcode }, | |
8288 | { Bad_Opcode }, | |
85f10a01 | 8289 | /* e8 */ |
592d1631 L |
8290 | { Bad_Opcode }, |
8291 | { Bad_Opcode }, | |
8292 | { Bad_Opcode }, | |
8293 | { Bad_Opcode }, | |
8294 | { Bad_Opcode }, | |
8295 | { Bad_Opcode }, | |
8296 | { Bad_Opcode }, | |
8297 | { Bad_Opcode }, | |
85f10a01 | 8298 | /* f0 */ |
592d1631 L |
8299 | { Bad_Opcode }, |
8300 | { Bad_Opcode }, | |
8301 | { Bad_Opcode }, | |
8302 | { Bad_Opcode }, | |
8303 | { Bad_Opcode }, | |
8304 | { Bad_Opcode }, | |
8305 | { Bad_Opcode }, | |
8306 | { Bad_Opcode }, | |
85f10a01 | 8307 | /* f8 */ |
592d1631 L |
8308 | { Bad_Opcode }, |
8309 | { Bad_Opcode }, | |
8310 | { Bad_Opcode }, | |
8311 | { Bad_Opcode }, | |
8312 | { Bad_Opcode }, | |
8313 | { Bad_Opcode }, | |
8314 | { Bad_Opcode }, | |
8315 | { Bad_Opcode }, | |
85f10a01 | 8316 | }, |
c0f3af97 L |
8317 | }; |
8318 | ||
8319 | static const struct dis386 vex_table[][256] = { | |
8320 | /* VEX_0F */ | |
85f10a01 MM |
8321 | { |
8322 | /* 00 */ | |
592d1631 L |
8323 | { Bad_Opcode }, |
8324 | { Bad_Opcode }, | |
8325 | { Bad_Opcode }, | |
8326 | { Bad_Opcode }, | |
8327 | { Bad_Opcode }, | |
8328 | { Bad_Opcode }, | |
8329 | { Bad_Opcode }, | |
8330 | { Bad_Opcode }, | |
85f10a01 | 8331 | /* 08 */ |
592d1631 L |
8332 | { Bad_Opcode }, |
8333 | { Bad_Opcode }, | |
8334 | { Bad_Opcode }, | |
8335 | { Bad_Opcode }, | |
8336 | { Bad_Opcode }, | |
8337 | { Bad_Opcode }, | |
8338 | { Bad_Opcode }, | |
8339 | { Bad_Opcode }, | |
c0f3af97 | 8340 | /* 10 */ |
592a252b L |
8341 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
8342 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, | |
8343 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, | |
8344 | { MOD_TABLE (MOD_VEX_0F13) }, | |
8345 | { VEX_W_TABLE (VEX_W_0F14) }, | |
8346 | { VEX_W_TABLE (VEX_W_0F15) }, | |
8347 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, | |
8348 | { MOD_TABLE (MOD_VEX_0F17) }, | |
c0f3af97 | 8349 | /* 18 */ |
592d1631 L |
8350 | { Bad_Opcode }, |
8351 | { Bad_Opcode }, | |
8352 | { Bad_Opcode }, | |
8353 | { Bad_Opcode }, | |
8354 | { Bad_Opcode }, | |
8355 | { Bad_Opcode }, | |
8356 | { Bad_Opcode }, | |
8357 | { Bad_Opcode }, | |
c0f3af97 | 8358 | /* 20 */ |
592d1631 L |
8359 | { Bad_Opcode }, |
8360 | { Bad_Opcode }, | |
8361 | { Bad_Opcode }, | |
8362 | { Bad_Opcode }, | |
8363 | { Bad_Opcode }, | |
8364 | { Bad_Opcode }, | |
8365 | { Bad_Opcode }, | |
8366 | { Bad_Opcode }, | |
c0f3af97 | 8367 | /* 28 */ |
592a252b L |
8368 | { VEX_W_TABLE (VEX_W_0F28) }, |
8369 | { VEX_W_TABLE (VEX_W_0F29) }, | |
8370 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, | |
8371 | { MOD_TABLE (MOD_VEX_0F2B) }, | |
8372 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, | |
8373 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, | |
8374 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, | |
8375 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, | |
85f10a01 | 8376 | /* 30 */ |
592d1631 L |
8377 | { Bad_Opcode }, |
8378 | { Bad_Opcode }, | |
8379 | { Bad_Opcode }, | |
8380 | { Bad_Opcode }, | |
8381 | { Bad_Opcode }, | |
8382 | { Bad_Opcode }, | |
8383 | { Bad_Opcode }, | |
8384 | { Bad_Opcode }, | |
4e7d34a6 | 8385 | /* 38 */ |
592d1631 L |
8386 | { Bad_Opcode }, |
8387 | { Bad_Opcode }, | |
8388 | { Bad_Opcode }, | |
8389 | { Bad_Opcode }, | |
8390 | { Bad_Opcode }, | |
8391 | { Bad_Opcode }, | |
8392 | { Bad_Opcode }, | |
8393 | { Bad_Opcode }, | |
d5d7db8e | 8394 | /* 40 */ |
592d1631 | 8395 | { Bad_Opcode }, |
43234a1e L |
8396 | { PREFIX_TABLE (PREFIX_VEX_0F41) }, |
8397 | { PREFIX_TABLE (PREFIX_VEX_0F42) }, | |
592d1631 | 8398 | { Bad_Opcode }, |
43234a1e L |
8399 | { PREFIX_TABLE (PREFIX_VEX_0F44) }, |
8400 | { PREFIX_TABLE (PREFIX_VEX_0F45) }, | |
8401 | { PREFIX_TABLE (PREFIX_VEX_0F46) }, | |
8402 | { PREFIX_TABLE (PREFIX_VEX_0F47) }, | |
85f10a01 | 8403 | /* 48 */ |
592d1631 L |
8404 | { Bad_Opcode }, |
8405 | { Bad_Opcode }, | |
8406 | { Bad_Opcode }, | |
43234a1e | 8407 | { PREFIX_TABLE (PREFIX_VEX_0F4B) }, |
592d1631 L |
8408 | { Bad_Opcode }, |
8409 | { Bad_Opcode }, | |
8410 | { Bad_Opcode }, | |
8411 | { Bad_Opcode }, | |
d5d7db8e | 8412 | /* 50 */ |
592a252b L |
8413 | { MOD_TABLE (MOD_VEX_0F50) }, |
8414 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, | |
8415 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, | |
8416 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, | |
c0f3af97 L |
8417 | { "vandpX", { XM, Vex, EXx } }, |
8418 | { "vandnpX", { XM, Vex, EXx } }, | |
8419 | { "vorpX", { XM, Vex, EXx } }, | |
8420 | { "vxorpX", { XM, Vex, EXx } }, | |
8421 | /* 58 */ | |
592a252b L |
8422 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
8423 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, | |
8424 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, | |
8425 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, | |
8426 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, | |
8427 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, | |
8428 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, | |
8429 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, | |
c0f3af97 | 8430 | /* 60 */ |
592a252b L |
8431 | { PREFIX_TABLE (PREFIX_VEX_0F60) }, |
8432 | { PREFIX_TABLE (PREFIX_VEX_0F61) }, | |
8433 | { PREFIX_TABLE (PREFIX_VEX_0F62) }, | |
8434 | { PREFIX_TABLE (PREFIX_VEX_0F63) }, | |
8435 | { PREFIX_TABLE (PREFIX_VEX_0F64) }, | |
8436 | { PREFIX_TABLE (PREFIX_VEX_0F65) }, | |
8437 | { PREFIX_TABLE (PREFIX_VEX_0F66) }, | |
8438 | { PREFIX_TABLE (PREFIX_VEX_0F67) }, | |
c0f3af97 | 8439 | /* 68 */ |
592a252b L |
8440 | { PREFIX_TABLE (PREFIX_VEX_0F68) }, |
8441 | { PREFIX_TABLE (PREFIX_VEX_0F69) }, | |
8442 | { PREFIX_TABLE (PREFIX_VEX_0F6A) }, | |
8443 | { PREFIX_TABLE (PREFIX_VEX_0F6B) }, | |
8444 | { PREFIX_TABLE (PREFIX_VEX_0F6C) }, | |
8445 | { PREFIX_TABLE (PREFIX_VEX_0F6D) }, | |
8446 | { PREFIX_TABLE (PREFIX_VEX_0F6E) }, | |
8447 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, | |
c0f3af97 | 8448 | /* 70 */ |
592a252b L |
8449 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
8450 | { REG_TABLE (REG_VEX_0F71) }, | |
8451 | { REG_TABLE (REG_VEX_0F72) }, | |
8452 | { REG_TABLE (REG_VEX_0F73) }, | |
8453 | { PREFIX_TABLE (PREFIX_VEX_0F74) }, | |
8454 | { PREFIX_TABLE (PREFIX_VEX_0F75) }, | |
8455 | { PREFIX_TABLE (PREFIX_VEX_0F76) }, | |
8456 | { PREFIX_TABLE (PREFIX_VEX_0F77) }, | |
c0f3af97 | 8457 | /* 78 */ |
592d1631 L |
8458 | { Bad_Opcode }, |
8459 | { Bad_Opcode }, | |
8460 | { Bad_Opcode }, | |
8461 | { Bad_Opcode }, | |
592a252b L |
8462 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
8463 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, | |
8464 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, | |
8465 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, | |
c0f3af97 | 8466 | /* 80 */ |
592d1631 L |
8467 | { Bad_Opcode }, |
8468 | { Bad_Opcode }, | |
8469 | { Bad_Opcode }, | |
8470 | { Bad_Opcode }, | |
8471 | { Bad_Opcode }, | |
8472 | { Bad_Opcode }, | |
8473 | { Bad_Opcode }, | |
8474 | { Bad_Opcode }, | |
c0f3af97 | 8475 | /* 88 */ |
592d1631 L |
8476 | { Bad_Opcode }, |
8477 | { Bad_Opcode }, | |
8478 | { Bad_Opcode }, | |
8479 | { Bad_Opcode }, | |
8480 | { Bad_Opcode }, | |
8481 | { Bad_Opcode }, | |
8482 | { Bad_Opcode }, | |
8483 | { Bad_Opcode }, | |
c0f3af97 | 8484 | /* 90 */ |
43234a1e L |
8485 | { PREFIX_TABLE (PREFIX_VEX_0F90) }, |
8486 | { PREFIX_TABLE (PREFIX_VEX_0F91) }, | |
8487 | { PREFIX_TABLE (PREFIX_VEX_0F92) }, | |
8488 | { PREFIX_TABLE (PREFIX_VEX_0F93) }, | |
592d1631 L |
8489 | { Bad_Opcode }, |
8490 | { Bad_Opcode }, | |
8491 | { Bad_Opcode }, | |
8492 | { Bad_Opcode }, | |
c0f3af97 | 8493 | /* 98 */ |
43234a1e | 8494 | { PREFIX_TABLE (PREFIX_VEX_0F98) }, |
592d1631 L |
8495 | { Bad_Opcode }, |
8496 | { Bad_Opcode }, | |
8497 | { Bad_Opcode }, | |
8498 | { Bad_Opcode }, | |
8499 | { Bad_Opcode }, | |
8500 | { Bad_Opcode }, | |
8501 | { Bad_Opcode }, | |
c0f3af97 | 8502 | /* a0 */ |
592d1631 L |
8503 | { Bad_Opcode }, |
8504 | { Bad_Opcode }, | |
8505 | { Bad_Opcode }, | |
8506 | { Bad_Opcode }, | |
8507 | { Bad_Opcode }, | |
8508 | { Bad_Opcode }, | |
8509 | { Bad_Opcode }, | |
8510 | { Bad_Opcode }, | |
c0f3af97 | 8511 | /* a8 */ |
592d1631 L |
8512 | { Bad_Opcode }, |
8513 | { Bad_Opcode }, | |
8514 | { Bad_Opcode }, | |
8515 | { Bad_Opcode }, | |
8516 | { Bad_Opcode }, | |
8517 | { Bad_Opcode }, | |
592a252b | 8518 | { REG_TABLE (REG_VEX_0FAE) }, |
592d1631 | 8519 | { Bad_Opcode }, |
c0f3af97 | 8520 | /* b0 */ |
592d1631 L |
8521 | { Bad_Opcode }, |
8522 | { Bad_Opcode }, | |
8523 | { Bad_Opcode }, | |
8524 | { Bad_Opcode }, | |
8525 | { Bad_Opcode }, | |
8526 | { Bad_Opcode }, | |
8527 | { Bad_Opcode }, | |
8528 | { Bad_Opcode }, | |
c0f3af97 | 8529 | /* b8 */ |
592d1631 L |
8530 | { Bad_Opcode }, |
8531 | { Bad_Opcode }, | |
8532 | { Bad_Opcode }, | |
8533 | { Bad_Opcode }, | |
8534 | { Bad_Opcode }, | |
8535 | { Bad_Opcode }, | |
8536 | { Bad_Opcode }, | |
8537 | { Bad_Opcode }, | |
c0f3af97 | 8538 | /* c0 */ |
592d1631 L |
8539 | { Bad_Opcode }, |
8540 | { Bad_Opcode }, | |
592a252b | 8541 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
592d1631 | 8542 | { Bad_Opcode }, |
592a252b L |
8543 | { PREFIX_TABLE (PREFIX_VEX_0FC4) }, |
8544 | { PREFIX_TABLE (PREFIX_VEX_0FC5) }, | |
c0f3af97 | 8545 | { "vshufpX", { XM, Vex, EXx, Ib } }, |
592d1631 | 8546 | { Bad_Opcode }, |
c0f3af97 | 8547 | /* c8 */ |
592d1631 L |
8548 | { Bad_Opcode }, |
8549 | { Bad_Opcode }, | |
8550 | { Bad_Opcode }, | |
8551 | { Bad_Opcode }, | |
8552 | { Bad_Opcode }, | |
8553 | { Bad_Opcode }, | |
8554 | { Bad_Opcode }, | |
8555 | { Bad_Opcode }, | |
c0f3af97 | 8556 | /* d0 */ |
592a252b L |
8557 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
8558 | { PREFIX_TABLE (PREFIX_VEX_0FD1) }, | |
8559 | { PREFIX_TABLE (PREFIX_VEX_0FD2) }, | |
8560 | { PREFIX_TABLE (PREFIX_VEX_0FD3) }, | |
8561 | { PREFIX_TABLE (PREFIX_VEX_0FD4) }, | |
8562 | { PREFIX_TABLE (PREFIX_VEX_0FD5) }, | |
8563 | { PREFIX_TABLE (PREFIX_VEX_0FD6) }, | |
8564 | { PREFIX_TABLE (PREFIX_VEX_0FD7) }, | |
c0f3af97 | 8565 | /* d8 */ |
592a252b L |
8566 | { PREFIX_TABLE (PREFIX_VEX_0FD8) }, |
8567 | { PREFIX_TABLE (PREFIX_VEX_0FD9) }, | |
8568 | { PREFIX_TABLE (PREFIX_VEX_0FDA) }, | |
8569 | { PREFIX_TABLE (PREFIX_VEX_0FDB) }, | |
8570 | { PREFIX_TABLE (PREFIX_VEX_0FDC) }, | |
8571 | { PREFIX_TABLE (PREFIX_VEX_0FDD) }, | |
8572 | { PREFIX_TABLE (PREFIX_VEX_0FDE) }, | |
8573 | { PREFIX_TABLE (PREFIX_VEX_0FDF) }, | |
c0f3af97 | 8574 | /* e0 */ |
592a252b L |
8575 | { PREFIX_TABLE (PREFIX_VEX_0FE0) }, |
8576 | { PREFIX_TABLE (PREFIX_VEX_0FE1) }, | |
8577 | { PREFIX_TABLE (PREFIX_VEX_0FE2) }, | |
8578 | { PREFIX_TABLE (PREFIX_VEX_0FE3) }, | |
8579 | { PREFIX_TABLE (PREFIX_VEX_0FE4) }, | |
8580 | { PREFIX_TABLE (PREFIX_VEX_0FE5) }, | |
8581 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, | |
8582 | { PREFIX_TABLE (PREFIX_VEX_0FE7) }, | |
c0f3af97 | 8583 | /* e8 */ |
592a252b L |
8584 | { PREFIX_TABLE (PREFIX_VEX_0FE8) }, |
8585 | { PREFIX_TABLE (PREFIX_VEX_0FE9) }, | |
8586 | { PREFIX_TABLE (PREFIX_VEX_0FEA) }, | |
8587 | { PREFIX_TABLE (PREFIX_VEX_0FEB) }, | |
8588 | { PREFIX_TABLE (PREFIX_VEX_0FEC) }, | |
8589 | { PREFIX_TABLE (PREFIX_VEX_0FED) }, | |
8590 | { PREFIX_TABLE (PREFIX_VEX_0FEE) }, | |
8591 | { PREFIX_TABLE (PREFIX_VEX_0FEF) }, | |
c0f3af97 | 8592 | /* f0 */ |
592a252b L |
8593 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
8594 | { PREFIX_TABLE (PREFIX_VEX_0FF1) }, | |
8595 | { PREFIX_TABLE (PREFIX_VEX_0FF2) }, | |
8596 | { PREFIX_TABLE (PREFIX_VEX_0FF3) }, | |
8597 | { PREFIX_TABLE (PREFIX_VEX_0FF4) }, | |
8598 | { PREFIX_TABLE (PREFIX_VEX_0FF5) }, | |
8599 | { PREFIX_TABLE (PREFIX_VEX_0FF6) }, | |
8600 | { PREFIX_TABLE (PREFIX_VEX_0FF7) }, | |
c0f3af97 | 8601 | /* f8 */ |
592a252b L |
8602 | { PREFIX_TABLE (PREFIX_VEX_0FF8) }, |
8603 | { PREFIX_TABLE (PREFIX_VEX_0FF9) }, | |
8604 | { PREFIX_TABLE (PREFIX_VEX_0FFA) }, | |
8605 | { PREFIX_TABLE (PREFIX_VEX_0FFB) }, | |
8606 | { PREFIX_TABLE (PREFIX_VEX_0FFC) }, | |
8607 | { PREFIX_TABLE (PREFIX_VEX_0FFD) }, | |
8608 | { PREFIX_TABLE (PREFIX_VEX_0FFE) }, | |
592d1631 | 8609 | { Bad_Opcode }, |
c0f3af97 L |
8610 | }, |
8611 | /* VEX_0F38 */ | |
8612 | { | |
8613 | /* 00 */ | |
592a252b L |
8614 | { PREFIX_TABLE (PREFIX_VEX_0F3800) }, |
8615 | { PREFIX_TABLE (PREFIX_VEX_0F3801) }, | |
8616 | { PREFIX_TABLE (PREFIX_VEX_0F3802) }, | |
8617 | { PREFIX_TABLE (PREFIX_VEX_0F3803) }, | |
8618 | { PREFIX_TABLE (PREFIX_VEX_0F3804) }, | |
8619 | { PREFIX_TABLE (PREFIX_VEX_0F3805) }, | |
8620 | { PREFIX_TABLE (PREFIX_VEX_0F3806) }, | |
8621 | { PREFIX_TABLE (PREFIX_VEX_0F3807) }, | |
c0f3af97 | 8622 | /* 08 */ |
592a252b L |
8623 | { PREFIX_TABLE (PREFIX_VEX_0F3808) }, |
8624 | { PREFIX_TABLE (PREFIX_VEX_0F3809) }, | |
8625 | { PREFIX_TABLE (PREFIX_VEX_0F380A) }, | |
8626 | { PREFIX_TABLE (PREFIX_VEX_0F380B) }, | |
8627 | { PREFIX_TABLE (PREFIX_VEX_0F380C) }, | |
8628 | { PREFIX_TABLE (PREFIX_VEX_0F380D) }, | |
8629 | { PREFIX_TABLE (PREFIX_VEX_0F380E) }, | |
8630 | { PREFIX_TABLE (PREFIX_VEX_0F380F) }, | |
c0f3af97 | 8631 | /* 10 */ |
592d1631 L |
8632 | { Bad_Opcode }, |
8633 | { Bad_Opcode }, | |
8634 | { Bad_Opcode }, | |
592a252b | 8635 | { PREFIX_TABLE (PREFIX_VEX_0F3813) }, |
592d1631 L |
8636 | { Bad_Opcode }, |
8637 | { Bad_Opcode }, | |
6c30d220 | 8638 | { PREFIX_TABLE (PREFIX_VEX_0F3816) }, |
592a252b | 8639 | { PREFIX_TABLE (PREFIX_VEX_0F3817) }, |
c0f3af97 | 8640 | /* 18 */ |
592a252b L |
8641 | { PREFIX_TABLE (PREFIX_VEX_0F3818) }, |
8642 | { PREFIX_TABLE (PREFIX_VEX_0F3819) }, | |
8643 | { PREFIX_TABLE (PREFIX_VEX_0F381A) }, | |
592d1631 | 8644 | { Bad_Opcode }, |
592a252b L |
8645 | { PREFIX_TABLE (PREFIX_VEX_0F381C) }, |
8646 | { PREFIX_TABLE (PREFIX_VEX_0F381D) }, | |
8647 | { PREFIX_TABLE (PREFIX_VEX_0F381E) }, | |
592d1631 | 8648 | { Bad_Opcode }, |
c0f3af97 | 8649 | /* 20 */ |
592a252b L |
8650 | { PREFIX_TABLE (PREFIX_VEX_0F3820) }, |
8651 | { PREFIX_TABLE (PREFIX_VEX_0F3821) }, | |
8652 | { PREFIX_TABLE (PREFIX_VEX_0F3822) }, | |
8653 | { PREFIX_TABLE (PREFIX_VEX_0F3823) }, | |
8654 | { PREFIX_TABLE (PREFIX_VEX_0F3824) }, | |
8655 | { PREFIX_TABLE (PREFIX_VEX_0F3825) }, | |
592d1631 L |
8656 | { Bad_Opcode }, |
8657 | { Bad_Opcode }, | |
c0f3af97 | 8658 | /* 28 */ |
592a252b L |
8659 | { PREFIX_TABLE (PREFIX_VEX_0F3828) }, |
8660 | { PREFIX_TABLE (PREFIX_VEX_0F3829) }, | |
8661 | { PREFIX_TABLE (PREFIX_VEX_0F382A) }, | |
8662 | { PREFIX_TABLE (PREFIX_VEX_0F382B) }, | |
8663 | { PREFIX_TABLE (PREFIX_VEX_0F382C) }, | |
8664 | { PREFIX_TABLE (PREFIX_VEX_0F382D) }, | |
8665 | { PREFIX_TABLE (PREFIX_VEX_0F382E) }, | |
8666 | { PREFIX_TABLE (PREFIX_VEX_0F382F) }, | |
c0f3af97 | 8667 | /* 30 */ |
592a252b L |
8668 | { PREFIX_TABLE (PREFIX_VEX_0F3830) }, |
8669 | { PREFIX_TABLE (PREFIX_VEX_0F3831) }, | |
8670 | { PREFIX_TABLE (PREFIX_VEX_0F3832) }, | |
8671 | { PREFIX_TABLE (PREFIX_VEX_0F3833) }, | |
8672 | { PREFIX_TABLE (PREFIX_VEX_0F3834) }, | |
8673 | { PREFIX_TABLE (PREFIX_VEX_0F3835) }, | |
6c30d220 | 8674 | { PREFIX_TABLE (PREFIX_VEX_0F3836) }, |
592a252b | 8675 | { PREFIX_TABLE (PREFIX_VEX_0F3837) }, |
c0f3af97 | 8676 | /* 38 */ |
592a252b L |
8677 | { PREFIX_TABLE (PREFIX_VEX_0F3838) }, |
8678 | { PREFIX_TABLE (PREFIX_VEX_0F3839) }, | |
8679 | { PREFIX_TABLE (PREFIX_VEX_0F383A) }, | |
8680 | { PREFIX_TABLE (PREFIX_VEX_0F383B) }, | |
8681 | { PREFIX_TABLE (PREFIX_VEX_0F383C) }, | |
8682 | { PREFIX_TABLE (PREFIX_VEX_0F383D) }, | |
8683 | { PREFIX_TABLE (PREFIX_VEX_0F383E) }, | |
8684 | { PREFIX_TABLE (PREFIX_VEX_0F383F) }, | |
c0f3af97 | 8685 | /* 40 */ |
592a252b L |
8686 | { PREFIX_TABLE (PREFIX_VEX_0F3840) }, |
8687 | { PREFIX_TABLE (PREFIX_VEX_0F3841) }, | |
592d1631 L |
8688 | { Bad_Opcode }, |
8689 | { Bad_Opcode }, | |
8690 | { Bad_Opcode }, | |
6c30d220 L |
8691 | { PREFIX_TABLE (PREFIX_VEX_0F3845) }, |
8692 | { PREFIX_TABLE (PREFIX_VEX_0F3846) }, | |
8693 | { PREFIX_TABLE (PREFIX_VEX_0F3847) }, | |
c0f3af97 | 8694 | /* 48 */ |
592d1631 L |
8695 | { Bad_Opcode }, |
8696 | { Bad_Opcode }, | |
8697 | { Bad_Opcode }, | |
8698 | { Bad_Opcode }, | |
8699 | { Bad_Opcode }, | |
8700 | { Bad_Opcode }, | |
8701 | { Bad_Opcode }, | |
8702 | { Bad_Opcode }, | |
c0f3af97 | 8703 | /* 50 */ |
592d1631 L |
8704 | { Bad_Opcode }, |
8705 | { Bad_Opcode }, | |
8706 | { Bad_Opcode }, | |
8707 | { Bad_Opcode }, | |
8708 | { Bad_Opcode }, | |
8709 | { Bad_Opcode }, | |
8710 | { Bad_Opcode }, | |
8711 | { Bad_Opcode }, | |
c0f3af97 | 8712 | /* 58 */ |
6c30d220 L |
8713 | { PREFIX_TABLE (PREFIX_VEX_0F3858) }, |
8714 | { PREFIX_TABLE (PREFIX_VEX_0F3859) }, | |
8715 | { PREFIX_TABLE (PREFIX_VEX_0F385A) }, | |
592d1631 L |
8716 | { Bad_Opcode }, |
8717 | { Bad_Opcode }, | |
8718 | { Bad_Opcode }, | |
8719 | { Bad_Opcode }, | |
8720 | { Bad_Opcode }, | |
c0f3af97 | 8721 | /* 60 */ |
592d1631 L |
8722 | { Bad_Opcode }, |
8723 | { Bad_Opcode }, | |
8724 | { Bad_Opcode }, | |
8725 | { Bad_Opcode }, | |
8726 | { Bad_Opcode }, | |
8727 | { Bad_Opcode }, | |
8728 | { Bad_Opcode }, | |
8729 | { Bad_Opcode }, | |
c0f3af97 | 8730 | /* 68 */ |
592d1631 L |
8731 | { Bad_Opcode }, |
8732 | { Bad_Opcode }, | |
8733 | { Bad_Opcode }, | |
8734 | { Bad_Opcode }, | |
8735 | { Bad_Opcode }, | |
8736 | { Bad_Opcode }, | |
8737 | { Bad_Opcode }, | |
8738 | { Bad_Opcode }, | |
c0f3af97 | 8739 | /* 70 */ |
592d1631 L |
8740 | { Bad_Opcode }, |
8741 | { Bad_Opcode }, | |
8742 | { Bad_Opcode }, | |
8743 | { Bad_Opcode }, | |
8744 | { Bad_Opcode }, | |
8745 | { Bad_Opcode }, | |
8746 | { Bad_Opcode }, | |
8747 | { Bad_Opcode }, | |
c0f3af97 | 8748 | /* 78 */ |
6c30d220 L |
8749 | { PREFIX_TABLE (PREFIX_VEX_0F3878) }, |
8750 | { PREFIX_TABLE (PREFIX_VEX_0F3879) }, | |
592d1631 L |
8751 | { Bad_Opcode }, |
8752 | { Bad_Opcode }, | |
8753 | { Bad_Opcode }, | |
8754 | { Bad_Opcode }, | |
8755 | { Bad_Opcode }, | |
8756 | { Bad_Opcode }, | |
c0f3af97 | 8757 | /* 80 */ |
592d1631 L |
8758 | { Bad_Opcode }, |
8759 | { Bad_Opcode }, | |
8760 | { Bad_Opcode }, | |
8761 | { Bad_Opcode }, | |
8762 | { Bad_Opcode }, | |
8763 | { Bad_Opcode }, | |
8764 | { Bad_Opcode }, | |
8765 | { Bad_Opcode }, | |
c0f3af97 | 8766 | /* 88 */ |
592d1631 L |
8767 | { Bad_Opcode }, |
8768 | { Bad_Opcode }, | |
8769 | { Bad_Opcode }, | |
8770 | { Bad_Opcode }, | |
6c30d220 | 8771 | { PREFIX_TABLE (PREFIX_VEX_0F388C) }, |
592d1631 | 8772 | { Bad_Opcode }, |
6c30d220 | 8773 | { PREFIX_TABLE (PREFIX_VEX_0F388E) }, |
592d1631 | 8774 | { Bad_Opcode }, |
c0f3af97 | 8775 | /* 90 */ |
6c30d220 L |
8776 | { PREFIX_TABLE (PREFIX_VEX_0F3890) }, |
8777 | { PREFIX_TABLE (PREFIX_VEX_0F3891) }, | |
8778 | { PREFIX_TABLE (PREFIX_VEX_0F3892) }, | |
8779 | { PREFIX_TABLE (PREFIX_VEX_0F3893) }, | |
592d1631 L |
8780 | { Bad_Opcode }, |
8781 | { Bad_Opcode }, | |
592a252b L |
8782 | { PREFIX_TABLE (PREFIX_VEX_0F3896) }, |
8783 | { PREFIX_TABLE (PREFIX_VEX_0F3897) }, | |
c0f3af97 | 8784 | /* 98 */ |
592a252b L |
8785 | { PREFIX_TABLE (PREFIX_VEX_0F3898) }, |
8786 | { PREFIX_TABLE (PREFIX_VEX_0F3899) }, | |
8787 | { PREFIX_TABLE (PREFIX_VEX_0F389A) }, | |
8788 | { PREFIX_TABLE (PREFIX_VEX_0F389B) }, | |
8789 | { PREFIX_TABLE (PREFIX_VEX_0F389C) }, | |
8790 | { PREFIX_TABLE (PREFIX_VEX_0F389D) }, | |
8791 | { PREFIX_TABLE (PREFIX_VEX_0F389E) }, | |
8792 | { PREFIX_TABLE (PREFIX_VEX_0F389F) }, | |
c0f3af97 | 8793 | /* a0 */ |
592d1631 L |
8794 | { Bad_Opcode }, |
8795 | { Bad_Opcode }, | |
8796 | { Bad_Opcode }, | |
8797 | { Bad_Opcode }, | |
8798 | { Bad_Opcode }, | |
8799 | { Bad_Opcode }, | |
592a252b L |
8800 | { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, |
8801 | { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, | |
c0f3af97 | 8802 | /* a8 */ |
592a252b L |
8803 | { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, |
8804 | { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, | |
8805 | { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, | |
8806 | { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, | |
8807 | { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, | |
8808 | { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, | |
8809 | { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, | |
8810 | { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, | |
c0f3af97 | 8811 | /* b0 */ |
592d1631 L |
8812 | { Bad_Opcode }, |
8813 | { Bad_Opcode }, | |
8814 | { Bad_Opcode }, | |
8815 | { Bad_Opcode }, | |
8816 | { Bad_Opcode }, | |
8817 | { Bad_Opcode }, | |
592a252b L |
8818 | { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, |
8819 | { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, | |
c0f3af97 | 8820 | /* b8 */ |
592a252b L |
8821 | { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, |
8822 | { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, | |
8823 | { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, | |
8824 | { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, | |
8825 | { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, | |
8826 | { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, | |
8827 | { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, | |
8828 | { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, | |
c0f3af97 | 8829 | /* c0 */ |
592d1631 L |
8830 | { Bad_Opcode }, |
8831 | { Bad_Opcode }, | |
8832 | { Bad_Opcode }, | |
8833 | { Bad_Opcode }, | |
8834 | { Bad_Opcode }, | |
8835 | { Bad_Opcode }, | |
8836 | { Bad_Opcode }, | |
8837 | { Bad_Opcode }, | |
c0f3af97 | 8838 | /* c8 */ |
592d1631 L |
8839 | { Bad_Opcode }, |
8840 | { Bad_Opcode }, | |
8841 | { Bad_Opcode }, | |
8842 | { Bad_Opcode }, | |
8843 | { Bad_Opcode }, | |
8844 | { Bad_Opcode }, | |
8845 | { Bad_Opcode }, | |
8846 | { Bad_Opcode }, | |
c0f3af97 | 8847 | /* d0 */ |
592d1631 L |
8848 | { Bad_Opcode }, |
8849 | { Bad_Opcode }, | |
8850 | { Bad_Opcode }, | |
8851 | { Bad_Opcode }, | |
8852 | { Bad_Opcode }, | |
8853 | { Bad_Opcode }, | |
8854 | { Bad_Opcode }, | |
8855 | { Bad_Opcode }, | |
c0f3af97 | 8856 | /* d8 */ |
592d1631 L |
8857 | { Bad_Opcode }, |
8858 | { Bad_Opcode }, | |
8859 | { Bad_Opcode }, | |
592a252b L |
8860 | { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, |
8861 | { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, | |
8862 | { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, | |
8863 | { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, | |
8864 | { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, | |
c0f3af97 | 8865 | /* e0 */ |
592d1631 L |
8866 | { Bad_Opcode }, |
8867 | { Bad_Opcode }, | |
8868 | { Bad_Opcode }, | |
8869 | { Bad_Opcode }, | |
8870 | { Bad_Opcode }, | |
8871 | { Bad_Opcode }, | |
8872 | { Bad_Opcode }, | |
8873 | { Bad_Opcode }, | |
c0f3af97 | 8874 | /* e8 */ |
592d1631 L |
8875 | { Bad_Opcode }, |
8876 | { Bad_Opcode }, | |
8877 | { Bad_Opcode }, | |
8878 | { Bad_Opcode }, | |
8879 | { Bad_Opcode }, | |
8880 | { Bad_Opcode }, | |
8881 | { Bad_Opcode }, | |
8882 | { Bad_Opcode }, | |
c0f3af97 | 8883 | /* f0 */ |
592d1631 L |
8884 | { Bad_Opcode }, |
8885 | { Bad_Opcode }, | |
f12dc422 L |
8886 | { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, |
8887 | { REG_TABLE (REG_VEX_0F38F3) }, | |
592d1631 | 8888 | { Bad_Opcode }, |
6c30d220 L |
8889 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
8890 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, | |
f12dc422 | 8891 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
c0f3af97 | 8892 | /* f8 */ |
592d1631 L |
8893 | { Bad_Opcode }, |
8894 | { Bad_Opcode }, | |
8895 | { Bad_Opcode }, | |
8896 | { Bad_Opcode }, | |
8897 | { Bad_Opcode }, | |
8898 | { Bad_Opcode }, | |
8899 | { Bad_Opcode }, | |
8900 | { Bad_Opcode }, | |
c0f3af97 L |
8901 | }, |
8902 | /* VEX_0F3A */ | |
8903 | { | |
8904 | /* 00 */ | |
6c30d220 L |
8905 | { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, |
8906 | { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, | |
8907 | { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, | |
592d1631 | 8908 | { Bad_Opcode }, |
592a252b L |
8909 | { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, |
8910 | { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, | |
8911 | { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, | |
592d1631 | 8912 | { Bad_Opcode }, |
c0f3af97 | 8913 | /* 08 */ |
592a252b L |
8914 | { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, |
8915 | { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, | |
8916 | { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, | |
8917 | { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, | |
8918 | { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, | |
8919 | { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, | |
8920 | { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, | |
8921 | { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, | |
c0f3af97 | 8922 | /* 10 */ |
592d1631 L |
8923 | { Bad_Opcode }, |
8924 | { Bad_Opcode }, | |
8925 | { Bad_Opcode }, | |
8926 | { Bad_Opcode }, | |
592a252b L |
8927 | { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, |
8928 | { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, | |
8929 | { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, | |
8930 | { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, | |
c0f3af97 | 8931 | /* 18 */ |
592a252b L |
8932 | { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, |
8933 | { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, | |
592d1631 L |
8934 | { Bad_Opcode }, |
8935 | { Bad_Opcode }, | |
8936 | { Bad_Opcode }, | |
592a252b | 8937 | { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, |
592d1631 L |
8938 | { Bad_Opcode }, |
8939 | { Bad_Opcode }, | |
c0f3af97 | 8940 | /* 20 */ |
592a252b L |
8941 | { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, |
8942 | { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, | |
8943 | { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, | |
592d1631 L |
8944 | { Bad_Opcode }, |
8945 | { Bad_Opcode }, | |
8946 | { Bad_Opcode }, | |
8947 | { Bad_Opcode }, | |
8948 | { Bad_Opcode }, | |
c0f3af97 | 8949 | /* 28 */ |
592d1631 L |
8950 | { Bad_Opcode }, |
8951 | { Bad_Opcode }, | |
8952 | { Bad_Opcode }, | |
8953 | { Bad_Opcode }, | |
8954 | { Bad_Opcode }, | |
8955 | { Bad_Opcode }, | |
8956 | { Bad_Opcode }, | |
8957 | { Bad_Opcode }, | |
c0f3af97 | 8958 | /* 30 */ |
43234a1e | 8959 | { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, |
592d1631 | 8960 | { Bad_Opcode }, |
43234a1e | 8961 | { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, |
592d1631 L |
8962 | { Bad_Opcode }, |
8963 | { Bad_Opcode }, | |
8964 | { Bad_Opcode }, | |
8965 | { Bad_Opcode }, | |
8966 | { Bad_Opcode }, | |
c0f3af97 | 8967 | /* 38 */ |
6c30d220 L |
8968 | { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, |
8969 | { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, | |
592d1631 L |
8970 | { Bad_Opcode }, |
8971 | { Bad_Opcode }, | |
8972 | { Bad_Opcode }, | |
8973 | { Bad_Opcode }, | |
8974 | { Bad_Opcode }, | |
8975 | { Bad_Opcode }, | |
c0f3af97 | 8976 | /* 40 */ |
592a252b L |
8977 | { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, |
8978 | { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, | |
8979 | { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, | |
592d1631 | 8980 | { Bad_Opcode }, |
592a252b | 8981 | { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, |
592d1631 | 8982 | { Bad_Opcode }, |
6c30d220 | 8983 | { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, |
592d1631 | 8984 | { Bad_Opcode }, |
c0f3af97 | 8985 | /* 48 */ |
592a252b L |
8986 | { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, |
8987 | { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, | |
8988 | { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, | |
8989 | { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, | |
8990 | { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, | |
592d1631 L |
8991 | { Bad_Opcode }, |
8992 | { Bad_Opcode }, | |
8993 | { Bad_Opcode }, | |
c0f3af97 | 8994 | /* 50 */ |
592d1631 L |
8995 | { Bad_Opcode }, |
8996 | { Bad_Opcode }, | |
8997 | { Bad_Opcode }, | |
8998 | { Bad_Opcode }, | |
8999 | { Bad_Opcode }, | |
9000 | { Bad_Opcode }, | |
9001 | { Bad_Opcode }, | |
9002 | { Bad_Opcode }, | |
c0f3af97 | 9003 | /* 58 */ |
592d1631 L |
9004 | { Bad_Opcode }, |
9005 | { Bad_Opcode }, | |
9006 | { Bad_Opcode }, | |
9007 | { Bad_Opcode }, | |
592a252b L |
9008 | { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, |
9009 | { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, | |
9010 | { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, | |
9011 | { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, | |
c0f3af97 | 9012 | /* 60 */ |
592a252b L |
9013 | { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, |
9014 | { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, | |
9015 | { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, | |
9016 | { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, | |
592d1631 L |
9017 | { Bad_Opcode }, |
9018 | { Bad_Opcode }, | |
9019 | { Bad_Opcode }, | |
9020 | { Bad_Opcode }, | |
c0f3af97 | 9021 | /* 68 */ |
592a252b L |
9022 | { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, |
9023 | { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, | |
9024 | { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, | |
9025 | { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, | |
9026 | { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, | |
9027 | { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, | |
9028 | { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, | |
9029 | { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, | |
c0f3af97 | 9030 | /* 70 */ |
592d1631 L |
9031 | { Bad_Opcode }, |
9032 | { Bad_Opcode }, | |
9033 | { Bad_Opcode }, | |
9034 | { Bad_Opcode }, | |
9035 | { Bad_Opcode }, | |
9036 | { Bad_Opcode }, | |
9037 | { Bad_Opcode }, | |
9038 | { Bad_Opcode }, | |
c0f3af97 | 9039 | /* 78 */ |
592a252b L |
9040 | { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, |
9041 | { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, | |
9042 | { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, | |
9043 | { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, | |
9044 | { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, | |
9045 | { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, | |
9046 | { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, | |
9047 | { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, | |
c0f3af97 | 9048 | /* 80 */ |
592d1631 L |
9049 | { Bad_Opcode }, |
9050 | { Bad_Opcode }, | |
9051 | { Bad_Opcode }, | |
9052 | { Bad_Opcode }, | |
9053 | { Bad_Opcode }, | |
9054 | { Bad_Opcode }, | |
9055 | { Bad_Opcode }, | |
9056 | { Bad_Opcode }, | |
c0f3af97 | 9057 | /* 88 */ |
592d1631 L |
9058 | { Bad_Opcode }, |
9059 | { Bad_Opcode }, | |
9060 | { Bad_Opcode }, | |
9061 | { Bad_Opcode }, | |
9062 | { Bad_Opcode }, | |
9063 | { Bad_Opcode }, | |
9064 | { Bad_Opcode }, | |
9065 | { Bad_Opcode }, | |
c0f3af97 | 9066 | /* 90 */ |
592d1631 L |
9067 | { Bad_Opcode }, |
9068 | { Bad_Opcode }, | |
9069 | { Bad_Opcode }, | |
9070 | { Bad_Opcode }, | |
9071 | { Bad_Opcode }, | |
9072 | { Bad_Opcode }, | |
9073 | { Bad_Opcode }, | |
9074 | { Bad_Opcode }, | |
c0f3af97 | 9075 | /* 98 */ |
592d1631 L |
9076 | { Bad_Opcode }, |
9077 | { Bad_Opcode }, | |
9078 | { Bad_Opcode }, | |
9079 | { Bad_Opcode }, | |
9080 | { Bad_Opcode }, | |
9081 | { Bad_Opcode }, | |
9082 | { Bad_Opcode }, | |
9083 | { Bad_Opcode }, | |
c0f3af97 | 9084 | /* a0 */ |
592d1631 L |
9085 | { Bad_Opcode }, |
9086 | { Bad_Opcode }, | |
9087 | { Bad_Opcode }, | |
9088 | { Bad_Opcode }, | |
9089 | { Bad_Opcode }, | |
9090 | { Bad_Opcode }, | |
9091 | { Bad_Opcode }, | |
9092 | { Bad_Opcode }, | |
c0f3af97 | 9093 | /* a8 */ |
592d1631 L |
9094 | { Bad_Opcode }, |
9095 | { Bad_Opcode }, | |
9096 | { Bad_Opcode }, | |
9097 | { Bad_Opcode }, | |
9098 | { Bad_Opcode }, | |
9099 | { Bad_Opcode }, | |
9100 | { Bad_Opcode }, | |
9101 | { Bad_Opcode }, | |
c0f3af97 | 9102 | /* b0 */ |
592d1631 L |
9103 | { Bad_Opcode }, |
9104 | { Bad_Opcode }, | |
9105 | { Bad_Opcode }, | |
9106 | { Bad_Opcode }, | |
9107 | { Bad_Opcode }, | |
9108 | { Bad_Opcode }, | |
9109 | { Bad_Opcode }, | |
9110 | { Bad_Opcode }, | |
c0f3af97 | 9111 | /* b8 */ |
592d1631 L |
9112 | { Bad_Opcode }, |
9113 | { Bad_Opcode }, | |
9114 | { Bad_Opcode }, | |
9115 | { Bad_Opcode }, | |
9116 | { Bad_Opcode }, | |
9117 | { Bad_Opcode }, | |
9118 | { Bad_Opcode }, | |
9119 | { Bad_Opcode }, | |
c0f3af97 | 9120 | /* c0 */ |
592d1631 L |
9121 | { Bad_Opcode }, |
9122 | { Bad_Opcode }, | |
9123 | { Bad_Opcode }, | |
9124 | { Bad_Opcode }, | |
9125 | { Bad_Opcode }, | |
9126 | { Bad_Opcode }, | |
9127 | { Bad_Opcode }, | |
9128 | { Bad_Opcode }, | |
c0f3af97 | 9129 | /* c8 */ |
592d1631 L |
9130 | { Bad_Opcode }, |
9131 | { Bad_Opcode }, | |
9132 | { Bad_Opcode }, | |
9133 | { Bad_Opcode }, | |
9134 | { Bad_Opcode }, | |
9135 | { Bad_Opcode }, | |
9136 | { Bad_Opcode }, | |
9137 | { Bad_Opcode }, | |
c0f3af97 | 9138 | /* d0 */ |
592d1631 L |
9139 | { Bad_Opcode }, |
9140 | { Bad_Opcode }, | |
9141 | { Bad_Opcode }, | |
9142 | { Bad_Opcode }, | |
9143 | { Bad_Opcode }, | |
9144 | { Bad_Opcode }, | |
9145 | { Bad_Opcode }, | |
9146 | { Bad_Opcode }, | |
c0f3af97 | 9147 | /* d8 */ |
592d1631 L |
9148 | { Bad_Opcode }, |
9149 | { Bad_Opcode }, | |
9150 | { Bad_Opcode }, | |
9151 | { Bad_Opcode }, | |
9152 | { Bad_Opcode }, | |
9153 | { Bad_Opcode }, | |
9154 | { Bad_Opcode }, | |
592a252b | 9155 | { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, |
c0f3af97 | 9156 | /* e0 */ |
592d1631 L |
9157 | { Bad_Opcode }, |
9158 | { Bad_Opcode }, | |
9159 | { Bad_Opcode }, | |
9160 | { Bad_Opcode }, | |
9161 | { Bad_Opcode }, | |
9162 | { Bad_Opcode }, | |
9163 | { Bad_Opcode }, | |
9164 | { Bad_Opcode }, | |
c0f3af97 | 9165 | /* e8 */ |
592d1631 L |
9166 | { Bad_Opcode }, |
9167 | { Bad_Opcode }, | |
9168 | { Bad_Opcode }, | |
9169 | { Bad_Opcode }, | |
9170 | { Bad_Opcode }, | |
9171 | { Bad_Opcode }, | |
9172 | { Bad_Opcode }, | |
9173 | { Bad_Opcode }, | |
c0f3af97 | 9174 | /* f0 */ |
6c30d220 | 9175 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
592d1631 L |
9176 | { Bad_Opcode }, |
9177 | { Bad_Opcode }, | |
9178 | { Bad_Opcode }, | |
9179 | { Bad_Opcode }, | |
9180 | { Bad_Opcode }, | |
9181 | { Bad_Opcode }, | |
9182 | { Bad_Opcode }, | |
c0f3af97 | 9183 | /* f8 */ |
592d1631 L |
9184 | { Bad_Opcode }, |
9185 | { Bad_Opcode }, | |
9186 | { Bad_Opcode }, | |
9187 | { Bad_Opcode }, | |
9188 | { Bad_Opcode }, | |
9189 | { Bad_Opcode }, | |
9190 | { Bad_Opcode }, | |
9191 | { Bad_Opcode }, | |
c0f3af97 L |
9192 | }, |
9193 | }; | |
9194 | ||
43234a1e L |
9195 | #define NEED_OPCODE_TABLE |
9196 | #include "i386-dis-evex.h" | |
9197 | #undef NEED_OPCODE_TABLE | |
c0f3af97 | 9198 | static const struct dis386 vex_len_table[][2] = { |
592a252b | 9199 | /* VEX_LEN_0F10_P_1 */ |
c0f3af97 | 9200 | { |
592a252b L |
9201 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, |
9202 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, | |
c0f3af97 L |
9203 | }, |
9204 | ||
592a252b | 9205 | /* VEX_LEN_0F10_P_3 */ |
c0f3af97 | 9206 | { |
592a252b L |
9207 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, |
9208 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, | |
c0f3af97 L |
9209 | }, |
9210 | ||
592a252b | 9211 | /* VEX_LEN_0F11_P_1 */ |
c0f3af97 | 9212 | { |
592a252b L |
9213 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, |
9214 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, | |
c0f3af97 L |
9215 | }, |
9216 | ||
592a252b | 9217 | /* VEX_LEN_0F11_P_3 */ |
c0f3af97 | 9218 | { |
592a252b L |
9219 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, |
9220 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, | |
c0f3af97 L |
9221 | }, |
9222 | ||
592a252b | 9223 | /* VEX_LEN_0F12_P_0_M_0 */ |
c0f3af97 | 9224 | { |
592a252b | 9225 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) }, |
c0f3af97 L |
9226 | }, |
9227 | ||
592a252b | 9228 | /* VEX_LEN_0F12_P_0_M_1 */ |
c0f3af97 | 9229 | { |
592a252b | 9230 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) }, |
c0f3af97 L |
9231 | }, |
9232 | ||
592a252b | 9233 | /* VEX_LEN_0F12_P_2 */ |
c0f3af97 | 9234 | { |
592a252b | 9235 | { VEX_W_TABLE (VEX_W_0F12_P_2) }, |
c0f3af97 L |
9236 | }, |
9237 | ||
592a252b | 9238 | /* VEX_LEN_0F13_M_0 */ |
c0f3af97 | 9239 | { |
592a252b | 9240 | { VEX_W_TABLE (VEX_W_0F13_M_0) }, |
c0f3af97 L |
9241 | }, |
9242 | ||
592a252b | 9243 | /* VEX_LEN_0F16_P_0_M_0 */ |
c0f3af97 | 9244 | { |
592a252b | 9245 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) }, |
c0f3af97 L |
9246 | }, |
9247 | ||
592a252b | 9248 | /* VEX_LEN_0F16_P_0_M_1 */ |
c0f3af97 | 9249 | { |
592a252b | 9250 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) }, |
c0f3af97 L |
9251 | }, |
9252 | ||
592a252b | 9253 | /* VEX_LEN_0F16_P_2 */ |
c0f3af97 | 9254 | { |
592a252b | 9255 | { VEX_W_TABLE (VEX_W_0F16_P_2) }, |
c0f3af97 L |
9256 | }, |
9257 | ||
592a252b | 9258 | /* VEX_LEN_0F17_M_0 */ |
c0f3af97 | 9259 | { |
592a252b | 9260 | { VEX_W_TABLE (VEX_W_0F17_M_0) }, |
c0f3af97 L |
9261 | }, |
9262 | ||
592a252b | 9263 | /* VEX_LEN_0F2A_P_1 */ |
c0f3af97 | 9264 | { |
539f890d L |
9265 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } }, |
9266 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } }, | |
c0f3af97 L |
9267 | }, |
9268 | ||
592a252b | 9269 | /* VEX_LEN_0F2A_P_3 */ |
c0f3af97 | 9270 | { |
539f890d L |
9271 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } }, |
9272 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } }, | |
c0f3af97 L |
9273 | }, |
9274 | ||
592a252b | 9275 | /* VEX_LEN_0F2C_P_1 */ |
c0f3af97 | 9276 | { |
539f890d L |
9277 | { "vcvttss2siY", { Gv, EXdScalar } }, |
9278 | { "vcvttss2siY", { Gv, EXdScalar } }, | |
c0f3af97 L |
9279 | }, |
9280 | ||
592a252b | 9281 | /* VEX_LEN_0F2C_P_3 */ |
c0f3af97 | 9282 | { |
539f890d L |
9283 | { "vcvttsd2siY", { Gv, EXqScalar } }, |
9284 | { "vcvttsd2siY", { Gv, EXqScalar } }, | |
c0f3af97 L |
9285 | }, |
9286 | ||
592a252b | 9287 | /* VEX_LEN_0F2D_P_1 */ |
c0f3af97 | 9288 | { |
539f890d L |
9289 | { "vcvtss2siY", { Gv, EXdScalar } }, |
9290 | { "vcvtss2siY", { Gv, EXdScalar } }, | |
c0f3af97 L |
9291 | }, |
9292 | ||
592a252b | 9293 | /* VEX_LEN_0F2D_P_3 */ |
c0f3af97 | 9294 | { |
539f890d L |
9295 | { "vcvtsd2siY", { Gv, EXqScalar } }, |
9296 | { "vcvtsd2siY", { Gv, EXqScalar } }, | |
c0f3af97 L |
9297 | }, |
9298 | ||
592a252b | 9299 | /* VEX_LEN_0F2E_P_0 */ |
c0f3af97 | 9300 | { |
592a252b L |
9301 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, |
9302 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, | |
c0f3af97 L |
9303 | }, |
9304 | ||
592a252b | 9305 | /* VEX_LEN_0F2E_P_2 */ |
c0f3af97 | 9306 | { |
592a252b L |
9307 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, |
9308 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, | |
c0f3af97 L |
9309 | }, |
9310 | ||
592a252b | 9311 | /* VEX_LEN_0F2F_P_0 */ |
c0f3af97 | 9312 | { |
592a252b L |
9313 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, |
9314 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, | |
c0f3af97 L |
9315 | }, |
9316 | ||
592a252b | 9317 | /* VEX_LEN_0F2F_P_2 */ |
c0f3af97 | 9318 | { |
592a252b L |
9319 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, |
9320 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, | |
c0f3af97 L |
9321 | }, |
9322 | ||
43234a1e L |
9323 | /* VEX_LEN_0F41_P_0 */ |
9324 | { | |
9325 | { Bad_Opcode }, | |
9326 | { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, | |
9327 | }, | |
9328 | /* VEX_LEN_0F42_P_0 */ | |
9329 | { | |
9330 | { Bad_Opcode }, | |
9331 | { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, | |
9332 | }, | |
9333 | /* VEX_LEN_0F44_P_0 */ | |
9334 | { | |
9335 | { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, | |
9336 | }, | |
9337 | /* VEX_LEN_0F45_P_0 */ | |
9338 | { | |
9339 | { Bad_Opcode }, | |
9340 | { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, | |
9341 | }, | |
9342 | /* VEX_LEN_0F46_P_0 */ | |
9343 | { | |
9344 | { Bad_Opcode }, | |
9345 | { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, | |
9346 | }, | |
9347 | /* VEX_LEN_0F47_P_0 */ | |
9348 | { | |
9349 | { Bad_Opcode }, | |
9350 | { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, | |
9351 | }, | |
9352 | /* VEX_LEN_0F4B_P_2 */ | |
9353 | { | |
9354 | { Bad_Opcode }, | |
9355 | { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, | |
9356 | }, | |
9357 | ||
592a252b | 9358 | /* VEX_LEN_0F51_P_1 */ |
c0f3af97 | 9359 | { |
592a252b L |
9360 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, |
9361 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, | |
c0f3af97 L |
9362 | }, |
9363 | ||
592a252b | 9364 | /* VEX_LEN_0F51_P_3 */ |
c0f3af97 | 9365 | { |
592a252b L |
9366 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, |
9367 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, | |
c0f3af97 L |
9368 | }, |
9369 | ||
592a252b | 9370 | /* VEX_LEN_0F52_P_1 */ |
c0f3af97 | 9371 | { |
592a252b L |
9372 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, |
9373 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, | |
c0f3af97 L |
9374 | }, |
9375 | ||
592a252b | 9376 | /* VEX_LEN_0F53_P_1 */ |
c0f3af97 | 9377 | { |
592a252b L |
9378 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, |
9379 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, | |
c0f3af97 L |
9380 | }, |
9381 | ||
592a252b | 9382 | /* VEX_LEN_0F58_P_1 */ |
c0f3af97 | 9383 | { |
592a252b L |
9384 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, |
9385 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, | |
c0f3af97 L |
9386 | }, |
9387 | ||
592a252b | 9388 | /* VEX_LEN_0F58_P_3 */ |
c0f3af97 | 9389 | { |
592a252b L |
9390 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, |
9391 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, | |
c0f3af97 L |
9392 | }, |
9393 | ||
592a252b | 9394 | /* VEX_LEN_0F59_P_1 */ |
c0f3af97 | 9395 | { |
592a252b L |
9396 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, |
9397 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, | |
c0f3af97 L |
9398 | }, |
9399 | ||
592a252b | 9400 | /* VEX_LEN_0F59_P_3 */ |
c0f3af97 | 9401 | { |
592a252b L |
9402 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, |
9403 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, | |
c0f3af97 L |
9404 | }, |
9405 | ||
592a252b | 9406 | /* VEX_LEN_0F5A_P_1 */ |
c0f3af97 | 9407 | { |
592a252b L |
9408 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, |
9409 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, | |
c0f3af97 L |
9410 | }, |
9411 | ||
592a252b | 9412 | /* VEX_LEN_0F5A_P_3 */ |
c0f3af97 | 9413 | { |
592a252b L |
9414 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, |
9415 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, | |
c0f3af97 L |
9416 | }, |
9417 | ||
592a252b | 9418 | /* VEX_LEN_0F5C_P_1 */ |
c0f3af97 | 9419 | { |
592a252b L |
9420 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, |
9421 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, | |
c0f3af97 L |
9422 | }, |
9423 | ||
592a252b | 9424 | /* VEX_LEN_0F5C_P_3 */ |
c0f3af97 | 9425 | { |
592a252b L |
9426 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, |
9427 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, | |
c0f3af97 L |
9428 | }, |
9429 | ||
592a252b | 9430 | /* VEX_LEN_0F5D_P_1 */ |
c0f3af97 | 9431 | { |
592a252b L |
9432 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, |
9433 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, | |
c0f3af97 L |
9434 | }, |
9435 | ||
592a252b | 9436 | /* VEX_LEN_0F5D_P_3 */ |
c0f3af97 | 9437 | { |
592a252b L |
9438 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, |
9439 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, | |
c0f3af97 L |
9440 | }, |
9441 | ||
592a252b | 9442 | /* VEX_LEN_0F5E_P_1 */ |
c0f3af97 | 9443 | { |
592a252b L |
9444 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, |
9445 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, | |
c0f3af97 L |
9446 | }, |
9447 | ||
592a252b | 9448 | /* VEX_LEN_0F5E_P_3 */ |
c0f3af97 | 9449 | { |
592a252b L |
9450 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, |
9451 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, | |
c0f3af97 L |
9452 | }, |
9453 | ||
592a252b | 9454 | /* VEX_LEN_0F5F_P_1 */ |
c0f3af97 | 9455 | { |
592a252b L |
9456 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, |
9457 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, | |
c0f3af97 L |
9458 | }, |
9459 | ||
592a252b | 9460 | /* VEX_LEN_0F5F_P_3 */ |
c0f3af97 | 9461 | { |
592a252b L |
9462 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, |
9463 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, | |
c0f3af97 L |
9464 | }, |
9465 | ||
592a252b | 9466 | /* VEX_LEN_0F6E_P_2 */ |
c0f3af97 | 9467 | { |
539f890d L |
9468 | { "vmovK", { XMScalar, Edq } }, |
9469 | { "vmovK", { XMScalar, Edq } }, | |
c0f3af97 L |
9470 | }, |
9471 | ||
592a252b | 9472 | /* VEX_LEN_0F7E_P_1 */ |
c0f3af97 | 9473 | { |
592a252b L |
9474 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, |
9475 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, | |
c0f3af97 L |
9476 | }, |
9477 | ||
592a252b | 9478 | /* VEX_LEN_0F7E_P_2 */ |
c0f3af97 | 9479 | { |
539f890d | 9480 | { "vmovK", { Edq, XMScalar } }, |
6c30d220 | 9481 | { "vmovK", { Edq, XMScalar } }, |
c0f3af97 L |
9482 | }, |
9483 | ||
43234a1e L |
9484 | /* VEX_LEN_0F90_P_0 */ |
9485 | { | |
9486 | { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, | |
9487 | }, | |
9488 | ||
9489 | /* VEX_LEN_0F91_P_0 */ | |
9490 | { | |
9491 | { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, | |
9492 | }, | |
9493 | ||
9494 | /* VEX_LEN_0F92_P_0 */ | |
9495 | { | |
9496 | { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, | |
9497 | }, | |
9498 | ||
9499 | /* VEX_LEN_0F93_P_0 */ | |
9500 | { | |
9501 | { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, | |
9502 | }, | |
9503 | ||
9504 | /* VEX_LEN_0F98_P_0 */ | |
9505 | { | |
9506 | { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, | |
9507 | }, | |
9508 | ||
6c30d220 | 9509 | /* VEX_LEN_0FAE_R_2_M_0 */ |
c0f3af97 | 9510 | { |
6c30d220 | 9511 | { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) }, |
c0f3af97 L |
9512 | }, |
9513 | ||
6c30d220 | 9514 | /* VEX_LEN_0FAE_R_3_M_0 */ |
c0f3af97 | 9515 | { |
6c30d220 | 9516 | { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) }, |
c0f3af97 L |
9517 | }, |
9518 | ||
6c30d220 | 9519 | /* VEX_LEN_0FC2_P_1 */ |
c0f3af97 | 9520 | { |
6c30d220 L |
9521 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, |
9522 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, | |
c0f3af97 L |
9523 | }, |
9524 | ||
6c30d220 | 9525 | /* VEX_LEN_0FC2_P_3 */ |
c0f3af97 | 9526 | { |
6c30d220 L |
9527 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, |
9528 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, | |
c0f3af97 L |
9529 | }, |
9530 | ||
6c30d220 | 9531 | /* VEX_LEN_0FC4_P_2 */ |
c0f3af97 | 9532 | { |
6c30d220 | 9533 | { VEX_W_TABLE (VEX_W_0FC4_P_2) }, |
c0f3af97 L |
9534 | }, |
9535 | ||
6c30d220 | 9536 | /* VEX_LEN_0FC5_P_2 */ |
c0f3af97 | 9537 | { |
6c30d220 | 9538 | { VEX_W_TABLE (VEX_W_0FC5_P_2) }, |
c0f3af97 L |
9539 | }, |
9540 | ||
6c30d220 | 9541 | /* VEX_LEN_0FD6_P_2 */ |
c0f3af97 | 9542 | { |
6c30d220 L |
9543 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, |
9544 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, | |
c0f3af97 L |
9545 | }, |
9546 | ||
6c30d220 | 9547 | /* VEX_LEN_0FF7_P_2 */ |
c0f3af97 | 9548 | { |
6c30d220 | 9549 | { VEX_W_TABLE (VEX_W_0FF7_P_2) }, |
c0f3af97 L |
9550 | }, |
9551 | ||
6c30d220 | 9552 | /* VEX_LEN_0F3816_P_2 */ |
c0f3af97 | 9553 | { |
6c30d220 L |
9554 | { Bad_Opcode }, |
9555 | { VEX_W_TABLE (VEX_W_0F3816_P_2) }, | |
c0f3af97 L |
9556 | }, |
9557 | ||
6c30d220 | 9558 | /* VEX_LEN_0F3819_P_2 */ |
c0f3af97 | 9559 | { |
6c30d220 L |
9560 | { Bad_Opcode }, |
9561 | { VEX_W_TABLE (VEX_W_0F3819_P_2) }, | |
c0f3af97 L |
9562 | }, |
9563 | ||
6c30d220 | 9564 | /* VEX_LEN_0F381A_P_2_M_0 */ |
c0f3af97 | 9565 | { |
6c30d220 L |
9566 | { Bad_Opcode }, |
9567 | { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, | |
c0f3af97 L |
9568 | }, |
9569 | ||
6c30d220 | 9570 | /* VEX_LEN_0F3836_P_2 */ |
c0f3af97 | 9571 | { |
6c30d220 L |
9572 | { Bad_Opcode }, |
9573 | { VEX_W_TABLE (VEX_W_0F3836_P_2) }, | |
c0f3af97 L |
9574 | }, |
9575 | ||
592a252b | 9576 | /* VEX_LEN_0F3841_P_2 */ |
c0f3af97 | 9577 | { |
592a252b | 9578 | { VEX_W_TABLE (VEX_W_0F3841_P_2) }, |
c0f3af97 L |
9579 | }, |
9580 | ||
6c30d220 L |
9581 | /* VEX_LEN_0F385A_P_2_M_0 */ |
9582 | { | |
9583 | { Bad_Opcode }, | |
9584 | { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) }, | |
9585 | }, | |
9586 | ||
592a252b | 9587 | /* VEX_LEN_0F38DB_P_2 */ |
a5ff0eb2 | 9588 | { |
592a252b | 9589 | { VEX_W_TABLE (VEX_W_0F38DB_P_2) }, |
a5ff0eb2 L |
9590 | }, |
9591 | ||
592a252b | 9592 | /* VEX_LEN_0F38DC_P_2 */ |
a5ff0eb2 | 9593 | { |
592a252b | 9594 | { VEX_W_TABLE (VEX_W_0F38DC_P_2) }, |
a5ff0eb2 L |
9595 | }, |
9596 | ||
592a252b | 9597 | /* VEX_LEN_0F38DD_P_2 */ |
a5ff0eb2 | 9598 | { |
592a252b | 9599 | { VEX_W_TABLE (VEX_W_0F38DD_P_2) }, |
a5ff0eb2 L |
9600 | }, |
9601 | ||
592a252b | 9602 | /* VEX_LEN_0F38DE_P_2 */ |
a5ff0eb2 | 9603 | { |
592a252b | 9604 | { VEX_W_TABLE (VEX_W_0F38DE_P_2) }, |
a5ff0eb2 L |
9605 | }, |
9606 | ||
592a252b | 9607 | /* VEX_LEN_0F38DF_P_2 */ |
a5ff0eb2 | 9608 | { |
592a252b | 9609 | { VEX_W_TABLE (VEX_W_0F38DF_P_2) }, |
a5ff0eb2 L |
9610 | }, |
9611 | ||
f12dc422 L |
9612 | /* VEX_LEN_0F38F2_P_0 */ |
9613 | { | |
9614 | { "andnS", { Gdq, VexGdq, Edq } }, | |
9615 | }, | |
9616 | ||
9617 | /* VEX_LEN_0F38F3_R_1_P_0 */ | |
9618 | { | |
9619 | { "blsrS", { VexGdq, Edq } }, | |
9620 | }, | |
9621 | ||
9622 | /* VEX_LEN_0F38F3_R_2_P_0 */ | |
9623 | { | |
9624 | { "blsmskS", { VexGdq, Edq } }, | |
9625 | }, | |
9626 | ||
9627 | /* VEX_LEN_0F38F3_R_3_P_0 */ | |
9628 | { | |
9629 | { "blsiS", { VexGdq, Edq } }, | |
9630 | }, | |
9631 | ||
6c30d220 L |
9632 | /* VEX_LEN_0F38F5_P_0 */ |
9633 | { | |
9634 | { "bzhiS", { Gdq, Edq, VexGdq } }, | |
9635 | }, | |
9636 | ||
9637 | /* VEX_LEN_0F38F5_P_1 */ | |
9638 | { | |
9639 | { "pextS", { Gdq, VexGdq, Edq } }, | |
9640 | }, | |
9641 | ||
9642 | /* VEX_LEN_0F38F5_P_3 */ | |
9643 | { | |
9644 | { "pdepS", { Gdq, VexGdq, Edq } }, | |
9645 | }, | |
9646 | ||
9647 | /* VEX_LEN_0F38F6_P_3 */ | |
9648 | { | |
9649 | { "mulxS", { Gdq, VexGdq, Edq } }, | |
9650 | }, | |
9651 | ||
f12dc422 L |
9652 | /* VEX_LEN_0F38F7_P_0 */ |
9653 | { | |
9654 | { "bextrS", { Gdq, Edq, VexGdq } }, | |
9655 | }, | |
9656 | ||
6c30d220 L |
9657 | /* VEX_LEN_0F38F7_P_1 */ |
9658 | { | |
9659 | { "sarxS", { Gdq, Edq, VexGdq } }, | |
9660 | }, | |
9661 | ||
9662 | /* VEX_LEN_0F38F7_P_2 */ | |
9663 | { | |
9664 | { "shlxS", { Gdq, Edq, VexGdq } }, | |
9665 | }, | |
9666 | ||
9667 | /* VEX_LEN_0F38F7_P_3 */ | |
9668 | { | |
9669 | { "shrxS", { Gdq, Edq, VexGdq } }, | |
9670 | }, | |
9671 | ||
9672 | /* VEX_LEN_0F3A00_P_2 */ | |
9673 | { | |
9674 | { Bad_Opcode }, | |
9675 | { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, | |
9676 | }, | |
9677 | ||
9678 | /* VEX_LEN_0F3A01_P_2 */ | |
9679 | { | |
9680 | { Bad_Opcode }, | |
9681 | { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, | |
9682 | }, | |
9683 | ||
592a252b | 9684 | /* VEX_LEN_0F3A06_P_2 */ |
c0f3af97 | 9685 | { |
592d1631 | 9686 | { Bad_Opcode }, |
592a252b | 9687 | { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, |
c0f3af97 L |
9688 | }, |
9689 | ||
592a252b | 9690 | /* VEX_LEN_0F3A0A_P_2 */ |
c0f3af97 | 9691 | { |
592a252b L |
9692 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, |
9693 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, | |
c0f3af97 L |
9694 | }, |
9695 | ||
592a252b | 9696 | /* VEX_LEN_0F3A0B_P_2 */ |
c0f3af97 | 9697 | { |
592a252b L |
9698 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, |
9699 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, | |
c0f3af97 L |
9700 | }, |
9701 | ||
592a252b | 9702 | /* VEX_LEN_0F3A14_P_2 */ |
c0f3af97 | 9703 | { |
592a252b | 9704 | { VEX_W_TABLE (VEX_W_0F3A14_P_2) }, |
c0f3af97 L |
9705 | }, |
9706 | ||
592a252b | 9707 | /* VEX_LEN_0F3A15_P_2 */ |
c0f3af97 | 9708 | { |
592a252b | 9709 | { VEX_W_TABLE (VEX_W_0F3A15_P_2) }, |
c0f3af97 L |
9710 | }, |
9711 | ||
592a252b | 9712 | /* VEX_LEN_0F3A16_P_2 */ |
c0f3af97 L |
9713 | { |
9714 | { "vpextrK", { Edq, XM, Ib } }, | |
c0f3af97 L |
9715 | }, |
9716 | ||
592a252b | 9717 | /* VEX_LEN_0F3A17_P_2 */ |
c0f3af97 L |
9718 | { |
9719 | { "vextractps", { Edqd, XM, Ib } }, | |
c0f3af97 L |
9720 | }, |
9721 | ||
592a252b | 9722 | /* VEX_LEN_0F3A18_P_2 */ |
c0f3af97 | 9723 | { |
592d1631 | 9724 | { Bad_Opcode }, |
592a252b | 9725 | { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, |
c0f3af97 L |
9726 | }, |
9727 | ||
592a252b | 9728 | /* VEX_LEN_0F3A19_P_2 */ |
c0f3af97 | 9729 | { |
592d1631 | 9730 | { Bad_Opcode }, |
592a252b | 9731 | { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, |
c0f3af97 L |
9732 | }, |
9733 | ||
592a252b | 9734 | /* VEX_LEN_0F3A20_P_2 */ |
c0f3af97 | 9735 | { |
592a252b | 9736 | { VEX_W_TABLE (VEX_W_0F3A20_P_2) }, |
c0f3af97 L |
9737 | }, |
9738 | ||
592a252b | 9739 | /* VEX_LEN_0F3A21_P_2 */ |
c0f3af97 | 9740 | { |
592a252b | 9741 | { VEX_W_TABLE (VEX_W_0F3A21_P_2) }, |
c0f3af97 L |
9742 | }, |
9743 | ||
592a252b | 9744 | /* VEX_LEN_0F3A22_P_2 */ |
c0f3af97 L |
9745 | { |
9746 | { "vpinsrK", { XM, Vex128, Edq, Ib } }, | |
c0f3af97 L |
9747 | }, |
9748 | ||
43234a1e L |
9749 | /* VEX_LEN_0F3A30_P_2 */ |
9750 | { | |
9751 | { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, | |
9752 | }, | |
9753 | ||
9754 | /* VEX_LEN_0F3A32_P_2 */ | |
9755 | { | |
9756 | { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, | |
9757 | }, | |
9758 | ||
6c30d220 | 9759 | /* VEX_LEN_0F3A38_P_2 */ |
c0f3af97 | 9760 | { |
6c30d220 L |
9761 | { Bad_Opcode }, |
9762 | { VEX_W_TABLE (VEX_W_0F3A38_P_2) }, | |
c0f3af97 L |
9763 | }, |
9764 | ||
6c30d220 | 9765 | /* VEX_LEN_0F3A39_P_2 */ |
c0f3af97 | 9766 | { |
6c30d220 L |
9767 | { Bad_Opcode }, |
9768 | { VEX_W_TABLE (VEX_W_0F3A39_P_2) }, | |
9769 | }, | |
9770 | ||
9771 | /* VEX_LEN_0F3A41_P_2 */ | |
9772 | { | |
9773 | { VEX_W_TABLE (VEX_W_0F3A41_P_2) }, | |
c0f3af97 L |
9774 | }, |
9775 | ||
592a252b | 9776 | /* VEX_LEN_0F3A44_P_2 */ |
ce2f5b3c | 9777 | { |
592a252b | 9778 | { VEX_W_TABLE (VEX_W_0F3A44_P_2) }, |
ce2f5b3c L |
9779 | }, |
9780 | ||
6c30d220 | 9781 | /* VEX_LEN_0F3A46_P_2 */ |
c0f3af97 | 9782 | { |
6c30d220 L |
9783 | { Bad_Opcode }, |
9784 | { VEX_W_TABLE (VEX_W_0F3A46_P_2) }, | |
c0f3af97 L |
9785 | }, |
9786 | ||
592a252b | 9787 | /* VEX_LEN_0F3A60_P_2 */ |
c0f3af97 | 9788 | { |
592a252b | 9789 | { VEX_W_TABLE (VEX_W_0F3A60_P_2) }, |
c0f3af97 L |
9790 | }, |
9791 | ||
592a252b | 9792 | /* VEX_LEN_0F3A61_P_2 */ |
c0f3af97 | 9793 | { |
592a252b | 9794 | { VEX_W_TABLE (VEX_W_0F3A61_P_2) }, |
c0f3af97 L |
9795 | }, |
9796 | ||
592a252b | 9797 | /* VEX_LEN_0F3A62_P_2 */ |
c0f3af97 | 9798 | { |
592a252b | 9799 | { VEX_W_TABLE (VEX_W_0F3A62_P_2) }, |
c0f3af97 L |
9800 | }, |
9801 | ||
592a252b | 9802 | /* VEX_LEN_0F3A63_P_2 */ |
c0f3af97 | 9803 | { |
592a252b | 9804 | { VEX_W_TABLE (VEX_W_0F3A63_P_2) }, |
c0f3af97 L |
9805 | }, |
9806 | ||
592a252b | 9807 | /* VEX_LEN_0F3A6A_P_2 */ |
922d8de8 | 9808 | { |
206c2556 | 9809 | { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
922d8de8 DR |
9810 | }, |
9811 | ||
592a252b | 9812 | /* VEX_LEN_0F3A6B_P_2 */ |
922d8de8 | 9813 | { |
206c2556 | 9814 | { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
922d8de8 DR |
9815 | }, |
9816 | ||
592a252b | 9817 | /* VEX_LEN_0F3A6E_P_2 */ |
922d8de8 | 9818 | { |
206c2556 | 9819 | { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
922d8de8 DR |
9820 | }, |
9821 | ||
592a252b | 9822 | /* VEX_LEN_0F3A6F_P_2 */ |
922d8de8 | 9823 | { |
206c2556 | 9824 | { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
922d8de8 DR |
9825 | }, |
9826 | ||
592a252b | 9827 | /* VEX_LEN_0F3A7A_P_2 */ |
922d8de8 | 9828 | { |
206c2556 | 9829 | { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
922d8de8 DR |
9830 | }, |
9831 | ||
592a252b | 9832 | /* VEX_LEN_0F3A7B_P_2 */ |
922d8de8 | 9833 | { |
206c2556 | 9834 | { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
922d8de8 DR |
9835 | }, |
9836 | ||
592a252b | 9837 | /* VEX_LEN_0F3A7E_P_2 */ |
922d8de8 | 9838 | { |
206c2556 | 9839 | { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
922d8de8 DR |
9840 | }, |
9841 | ||
592a252b | 9842 | /* VEX_LEN_0F3A7F_P_2 */ |
922d8de8 | 9843 | { |
206c2556 | 9844 | { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
922d8de8 DR |
9845 | }, |
9846 | ||
592a252b | 9847 | /* VEX_LEN_0F3ADF_P_2 */ |
a5ff0eb2 | 9848 | { |
592a252b | 9849 | { VEX_W_TABLE (VEX_W_0F3ADF_P_2) }, |
a5ff0eb2 | 9850 | }, |
4c807e72 | 9851 | |
6c30d220 L |
9852 | /* VEX_LEN_0F3AF0_P_3 */ |
9853 | { | |
182ae480 | 9854 | { "rorxS", { Gdq, Edq, Ib } }, |
6c30d220 L |
9855 | }, |
9856 | ||
ff688e1f L |
9857 | /* VEX_LEN_0FXOP_08_CC */ |
9858 | { | |
9859 | { "vpcomb", { XM, Vex128, EXx, Ib } }, | |
9860 | }, | |
9861 | ||
9862 | /* VEX_LEN_0FXOP_08_CD */ | |
9863 | { | |
9864 | { "vpcomw", { XM, Vex128, EXx, Ib } }, | |
9865 | }, | |
9866 | ||
9867 | /* VEX_LEN_0FXOP_08_CE */ | |
9868 | { | |
9869 | { "vpcomd", { XM, Vex128, EXx, Ib } }, | |
9870 | }, | |
9871 | ||
9872 | /* VEX_LEN_0FXOP_08_CF */ | |
9873 | { | |
9874 | { "vpcomq", { XM, Vex128, EXx, Ib } }, | |
9875 | }, | |
9876 | ||
9877 | /* VEX_LEN_0FXOP_08_EC */ | |
9878 | { | |
9879 | { "vpcomub", { XM, Vex128, EXx, Ib } }, | |
9880 | }, | |
9881 | ||
9882 | /* VEX_LEN_0FXOP_08_ED */ | |
9883 | { | |
9884 | { "vpcomuw", { XM, Vex128, EXx, Ib } }, | |
9885 | }, | |
9886 | ||
9887 | /* VEX_LEN_0FXOP_08_EE */ | |
9888 | { | |
9889 | { "vpcomud", { XM, Vex128, EXx, Ib } }, | |
9890 | }, | |
9891 | ||
9892 | /* VEX_LEN_0FXOP_08_EF */ | |
9893 | { | |
9894 | { "vpcomuq", { XM, Vex128, EXx, Ib } }, | |
9895 | }, | |
9896 | ||
592a252b | 9897 | /* VEX_LEN_0FXOP_09_80 */ |
5dd85c99 | 9898 | { |
4c807e72 L |
9899 | { "vfrczps", { XM, EXxmm } }, |
9900 | { "vfrczps", { XM, EXymmq } }, | |
5dd85c99 | 9901 | }, |
4c807e72 | 9902 | |
592a252b | 9903 | /* VEX_LEN_0FXOP_09_81 */ |
5dd85c99 | 9904 | { |
4c807e72 L |
9905 | { "vfrczpd", { XM, EXxmm } }, |
9906 | { "vfrczpd", { XM, EXymmq } }, | |
5dd85c99 | 9907 | }, |
331d2d0d L |
9908 | }; |
9909 | ||
9e30b8e0 | 9910 | static const struct dis386 vex_w_table[][2] = { |
b844680a | 9911 | { |
592a252b | 9912 | /* VEX_W_0F10_P_0 */ |
9e30b8e0 | 9913 | { "vmovups", { XM, EXx } }, |
d8faab4e L |
9914 | }, |
9915 | { | |
592a252b | 9916 | /* VEX_W_0F10_P_1 */ |
539f890d | 9917 | { "vmovss", { XMVexScalar, VexScalar, EXdScalar } }, |
d8faab4e L |
9918 | }, |
9919 | { | |
592a252b | 9920 | /* VEX_W_0F10_P_2 */ |
9e30b8e0 | 9921 | { "vmovupd", { XM, EXx } }, |
d8faab4e L |
9922 | }, |
9923 | { | |
592a252b | 9924 | /* VEX_W_0F10_P_3 */ |
539f890d | 9925 | { "vmovsd", { XMVexScalar, VexScalar, EXqScalar } }, |
d8faab4e L |
9926 | }, |
9927 | { | |
592a252b | 9928 | /* VEX_W_0F11_P_0 */ |
9e30b8e0 | 9929 | { "vmovups", { EXxS, XM } }, |
d8faab4e L |
9930 | }, |
9931 | { | |
592a252b | 9932 | /* VEX_W_0F11_P_1 */ |
539f890d | 9933 | { "vmovss", { EXdVexScalarS, VexScalar, XMScalar } }, |
b844680a L |
9934 | }, |
9935 | { | |
592a252b | 9936 | /* VEX_W_0F11_P_2 */ |
9e30b8e0 | 9937 | { "vmovupd", { EXxS, XM } }, |
b844680a L |
9938 | }, |
9939 | { | |
592a252b | 9940 | /* VEX_W_0F11_P_3 */ |
539f890d | 9941 | { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar } }, |
d8faab4e L |
9942 | }, |
9943 | { | |
592a252b | 9944 | /* VEX_W_0F12_P_0_M_0 */ |
9e30b8e0 | 9945 | { "vmovlps", { XM, Vex128, EXq } }, |
b844680a L |
9946 | }, |
9947 | { | |
592a252b | 9948 | /* VEX_W_0F12_P_0_M_1 */ |
9e30b8e0 | 9949 | { "vmovhlps", { XM, Vex128, EXq } }, |
b844680a L |
9950 | }, |
9951 | { | |
592a252b | 9952 | /* VEX_W_0F12_P_1 */ |
9e30b8e0 | 9953 | { "vmovsldup", { XM, EXx } }, |
b844680a L |
9954 | }, |
9955 | { | |
592a252b | 9956 | /* VEX_W_0F12_P_2 */ |
9e30b8e0 | 9957 | { "vmovlpd", { XM, Vex128, EXq } }, |
b844680a L |
9958 | }, |
9959 | { | |
592a252b | 9960 | /* VEX_W_0F12_P_3 */ |
9e30b8e0 | 9961 | { "vmovddup", { XM, EXymmq } }, |
b844680a L |
9962 | }, |
9963 | { | |
592a252b | 9964 | /* VEX_W_0F13_M_0 */ |
9e30b8e0 | 9965 | { "vmovlpX", { EXq, XM } }, |
b844680a L |
9966 | }, |
9967 | { | |
592a252b | 9968 | /* VEX_W_0F14 */ |
9e30b8e0 | 9969 | { "vunpcklpX", { XM, Vex, EXx } }, |
b844680a L |
9970 | }, |
9971 | { | |
592a252b | 9972 | /* VEX_W_0F15 */ |
9e30b8e0 | 9973 | { "vunpckhpX", { XM, Vex, EXx } }, |
b844680a L |
9974 | }, |
9975 | { | |
592a252b | 9976 | /* VEX_W_0F16_P_0_M_0 */ |
9e30b8e0 | 9977 | { "vmovhps", { XM, Vex128, EXq } }, |
9e30b8e0 L |
9978 | }, |
9979 | { | |
592a252b | 9980 | /* VEX_W_0F16_P_0_M_1 */ |
9e30b8e0 | 9981 | { "vmovlhps", { XM, Vex128, EXq } }, |
9e30b8e0 L |
9982 | }, |
9983 | { | |
592a252b | 9984 | /* VEX_W_0F16_P_1 */ |
9e30b8e0 | 9985 | { "vmovshdup", { XM, EXx } }, |
9e30b8e0 L |
9986 | }, |
9987 | { | |
592a252b | 9988 | /* VEX_W_0F16_P_2 */ |
9e30b8e0 | 9989 | { "vmovhpd", { XM, Vex128, EXq } }, |
9e30b8e0 L |
9990 | }, |
9991 | { | |
592a252b | 9992 | /* VEX_W_0F17_M_0 */ |
9e30b8e0 | 9993 | { "vmovhpX", { EXq, XM } }, |
9e30b8e0 L |
9994 | }, |
9995 | { | |
592a252b | 9996 | /* VEX_W_0F28 */ |
9e30b8e0 | 9997 | { "vmovapX", { XM, EXx } }, |
9e30b8e0 L |
9998 | }, |
9999 | { | |
592a252b | 10000 | /* VEX_W_0F29 */ |
9e30b8e0 | 10001 | { "vmovapX", { EXxS, XM } }, |
9e30b8e0 L |
10002 | }, |
10003 | { | |
592a252b | 10004 | /* VEX_W_0F2B_M_0 */ |
9e30b8e0 | 10005 | { "vmovntpX", { Mx, XM } }, |
9e30b8e0 L |
10006 | }, |
10007 | { | |
592a252b | 10008 | /* VEX_W_0F2E_P_0 */ |
7bb15c6f | 10009 | { "vucomiss", { XMScalar, EXdScalar } }, |
9e30b8e0 L |
10010 | }, |
10011 | { | |
592a252b | 10012 | /* VEX_W_0F2E_P_2 */ |
7bb15c6f | 10013 | { "vucomisd", { XMScalar, EXqScalar } }, |
9e30b8e0 L |
10014 | }, |
10015 | { | |
592a252b | 10016 | /* VEX_W_0F2F_P_0 */ |
539f890d | 10017 | { "vcomiss", { XMScalar, EXdScalar } }, |
9e30b8e0 L |
10018 | }, |
10019 | { | |
592a252b | 10020 | /* VEX_W_0F2F_P_2 */ |
539f890d | 10021 | { "vcomisd", { XMScalar, EXqScalar } }, |
9e30b8e0 | 10022 | }, |
43234a1e L |
10023 | { |
10024 | /* VEX_W_0F41_P_0_LEN_1 */ | |
10025 | { "kandw", { MaskG, MaskVex, MaskR } }, | |
10026 | }, | |
10027 | { | |
10028 | /* VEX_W_0F42_P_0_LEN_1 */ | |
10029 | { "kandnw", { MaskG, MaskVex, MaskR } }, | |
10030 | }, | |
10031 | { | |
10032 | /* VEX_W_0F44_P_0_LEN_0 */ | |
10033 | { "knotw", { MaskG, MaskR } }, | |
10034 | }, | |
10035 | { | |
10036 | /* VEX_W_0F45_P_0_LEN_1 */ | |
10037 | { "korw", { MaskG, MaskVex, MaskR } }, | |
10038 | }, | |
10039 | { | |
10040 | /* VEX_W_0F46_P_0_LEN_1 */ | |
10041 | { "kxnorw", { MaskG, MaskVex, MaskR } }, | |
10042 | }, | |
10043 | { | |
10044 | /* VEX_W_0F47_P_0_LEN_1 */ | |
10045 | { "kxorw", { MaskG, MaskVex, MaskR } }, | |
10046 | }, | |
10047 | { | |
10048 | /* VEX_W_0F4B_P_2_LEN_1 */ | |
10049 | { "kunpckbw", { MaskG, MaskVex, MaskR } }, | |
10050 | }, | |
9e30b8e0 | 10051 | { |
592a252b | 10052 | /* VEX_W_0F50_M_0 */ |
9e30b8e0 | 10053 | { "vmovmskpX", { Gdq, XS } }, |
9e30b8e0 L |
10054 | }, |
10055 | { | |
592a252b | 10056 | /* VEX_W_0F51_P_0 */ |
9e30b8e0 | 10057 | { "vsqrtps", { XM, EXx } }, |
9e30b8e0 L |
10058 | }, |
10059 | { | |
592a252b | 10060 | /* VEX_W_0F51_P_1 */ |
539f890d | 10061 | { "vsqrtss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
10062 | }, |
10063 | { | |
592a252b | 10064 | /* VEX_W_0F51_P_2 */ |
9e30b8e0 | 10065 | { "vsqrtpd", { XM, EXx } }, |
9e30b8e0 L |
10066 | }, |
10067 | { | |
592a252b | 10068 | /* VEX_W_0F51_P_3 */ |
539f890d | 10069 | { "vsqrtsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
10070 | }, |
10071 | { | |
592a252b | 10072 | /* VEX_W_0F52_P_0 */ |
9e30b8e0 | 10073 | { "vrsqrtps", { XM, EXx } }, |
9e30b8e0 L |
10074 | }, |
10075 | { | |
592a252b | 10076 | /* VEX_W_0F52_P_1 */ |
539f890d | 10077 | { "vrsqrtss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
10078 | }, |
10079 | { | |
592a252b | 10080 | /* VEX_W_0F53_P_0 */ |
9e30b8e0 | 10081 | { "vrcpps", { XM, EXx } }, |
9e30b8e0 L |
10082 | }, |
10083 | { | |
592a252b | 10084 | /* VEX_W_0F53_P_1 */ |
539f890d | 10085 | { "vrcpss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
10086 | }, |
10087 | { | |
592a252b | 10088 | /* VEX_W_0F58_P_0 */ |
9e30b8e0 | 10089 | { "vaddps", { XM, Vex, EXx } }, |
9e30b8e0 L |
10090 | }, |
10091 | { | |
592a252b | 10092 | /* VEX_W_0F58_P_1 */ |
539f890d | 10093 | { "vaddss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
10094 | }, |
10095 | { | |
592a252b | 10096 | /* VEX_W_0F58_P_2 */ |
9e30b8e0 | 10097 | { "vaddpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10098 | }, |
10099 | { | |
592a252b | 10100 | /* VEX_W_0F58_P_3 */ |
539f890d | 10101 | { "vaddsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
10102 | }, |
10103 | { | |
592a252b | 10104 | /* VEX_W_0F59_P_0 */ |
9e30b8e0 | 10105 | { "vmulps", { XM, Vex, EXx } }, |
9e30b8e0 L |
10106 | }, |
10107 | { | |
592a252b | 10108 | /* VEX_W_0F59_P_1 */ |
539f890d | 10109 | { "vmulss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
10110 | }, |
10111 | { | |
592a252b | 10112 | /* VEX_W_0F59_P_2 */ |
9e30b8e0 | 10113 | { "vmulpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10114 | }, |
10115 | { | |
592a252b | 10116 | /* VEX_W_0F59_P_3 */ |
539f890d | 10117 | { "vmulsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
10118 | }, |
10119 | { | |
592a252b | 10120 | /* VEX_W_0F5A_P_0 */ |
9e30b8e0 | 10121 | { "vcvtps2pd", { XM, EXxmmq } }, |
9e30b8e0 L |
10122 | }, |
10123 | { | |
592a252b | 10124 | /* VEX_W_0F5A_P_1 */ |
539f890d | 10125 | { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
10126 | }, |
10127 | { | |
592a252b | 10128 | /* VEX_W_0F5A_P_3 */ |
539f890d | 10129 | { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
10130 | }, |
10131 | { | |
592a252b | 10132 | /* VEX_W_0F5B_P_0 */ |
9e30b8e0 | 10133 | { "vcvtdq2ps", { XM, EXx } }, |
9e30b8e0 L |
10134 | }, |
10135 | { | |
592a252b | 10136 | /* VEX_W_0F5B_P_1 */ |
9e30b8e0 | 10137 | { "vcvttps2dq", { XM, EXx } }, |
9e30b8e0 L |
10138 | }, |
10139 | { | |
592a252b | 10140 | /* VEX_W_0F5B_P_2 */ |
9e30b8e0 | 10141 | { "vcvtps2dq", { XM, EXx } }, |
9e30b8e0 L |
10142 | }, |
10143 | { | |
592a252b | 10144 | /* VEX_W_0F5C_P_0 */ |
9e30b8e0 | 10145 | { "vsubps", { XM, Vex, EXx } }, |
9e30b8e0 L |
10146 | }, |
10147 | { | |
592a252b | 10148 | /* VEX_W_0F5C_P_1 */ |
539f890d | 10149 | { "vsubss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
10150 | }, |
10151 | { | |
592a252b | 10152 | /* VEX_W_0F5C_P_2 */ |
9e30b8e0 | 10153 | { "vsubpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10154 | }, |
10155 | { | |
592a252b | 10156 | /* VEX_W_0F5C_P_3 */ |
539f890d | 10157 | { "vsubsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
10158 | }, |
10159 | { | |
592a252b | 10160 | /* VEX_W_0F5D_P_0 */ |
9e30b8e0 | 10161 | { "vminps", { XM, Vex, EXx } }, |
9e30b8e0 L |
10162 | }, |
10163 | { | |
592a252b | 10164 | /* VEX_W_0F5D_P_1 */ |
539f890d | 10165 | { "vminss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
10166 | }, |
10167 | { | |
592a252b | 10168 | /* VEX_W_0F5D_P_2 */ |
9e30b8e0 | 10169 | { "vminpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10170 | }, |
10171 | { | |
592a252b | 10172 | /* VEX_W_0F5D_P_3 */ |
539f890d | 10173 | { "vminsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
10174 | }, |
10175 | { | |
592a252b | 10176 | /* VEX_W_0F5E_P_0 */ |
9e30b8e0 | 10177 | { "vdivps", { XM, Vex, EXx } }, |
9e30b8e0 L |
10178 | }, |
10179 | { | |
592a252b | 10180 | /* VEX_W_0F5E_P_1 */ |
539f890d | 10181 | { "vdivss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
10182 | }, |
10183 | { | |
592a252b | 10184 | /* VEX_W_0F5E_P_2 */ |
9e30b8e0 | 10185 | { "vdivpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10186 | }, |
10187 | { | |
592a252b | 10188 | /* VEX_W_0F5E_P_3 */ |
539f890d | 10189 | { "vdivsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
10190 | }, |
10191 | { | |
592a252b | 10192 | /* VEX_W_0F5F_P_0 */ |
9e30b8e0 | 10193 | { "vmaxps", { XM, Vex, EXx } }, |
9e30b8e0 L |
10194 | }, |
10195 | { | |
592a252b | 10196 | /* VEX_W_0F5F_P_1 */ |
539f890d | 10197 | { "vmaxss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
10198 | }, |
10199 | { | |
592a252b | 10200 | /* VEX_W_0F5F_P_2 */ |
9e30b8e0 | 10201 | { "vmaxpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10202 | }, |
10203 | { | |
592a252b | 10204 | /* VEX_W_0F5F_P_3 */ |
539f890d | 10205 | { "vmaxsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
10206 | }, |
10207 | { | |
592a252b | 10208 | /* VEX_W_0F60_P_2 */ |
6c30d220 | 10209 | { "vpunpcklbw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10210 | }, |
10211 | { | |
592a252b | 10212 | /* VEX_W_0F61_P_2 */ |
6c30d220 | 10213 | { "vpunpcklwd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10214 | }, |
10215 | { | |
592a252b | 10216 | /* VEX_W_0F62_P_2 */ |
6c30d220 | 10217 | { "vpunpckldq", { XM, Vex, EXx } }, |
9e30b8e0 L |
10218 | }, |
10219 | { | |
592a252b | 10220 | /* VEX_W_0F63_P_2 */ |
6c30d220 | 10221 | { "vpacksswb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10222 | }, |
10223 | { | |
592a252b | 10224 | /* VEX_W_0F64_P_2 */ |
6c30d220 | 10225 | { "vpcmpgtb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10226 | }, |
10227 | { | |
592a252b | 10228 | /* VEX_W_0F65_P_2 */ |
6c30d220 | 10229 | { "vpcmpgtw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10230 | }, |
10231 | { | |
592a252b | 10232 | /* VEX_W_0F66_P_2 */ |
6c30d220 | 10233 | { "vpcmpgtd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10234 | }, |
10235 | { | |
592a252b | 10236 | /* VEX_W_0F67_P_2 */ |
6c30d220 | 10237 | { "vpackuswb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10238 | }, |
10239 | { | |
592a252b | 10240 | /* VEX_W_0F68_P_2 */ |
6c30d220 | 10241 | { "vpunpckhbw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10242 | }, |
10243 | { | |
592a252b | 10244 | /* VEX_W_0F69_P_2 */ |
6c30d220 | 10245 | { "vpunpckhwd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10246 | }, |
10247 | { | |
592a252b | 10248 | /* VEX_W_0F6A_P_2 */ |
6c30d220 | 10249 | { "vpunpckhdq", { XM, Vex, EXx } }, |
9e30b8e0 L |
10250 | }, |
10251 | { | |
592a252b | 10252 | /* VEX_W_0F6B_P_2 */ |
6c30d220 | 10253 | { "vpackssdw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10254 | }, |
10255 | { | |
592a252b | 10256 | /* VEX_W_0F6C_P_2 */ |
6c30d220 | 10257 | { "vpunpcklqdq", { XM, Vex, EXx } }, |
9e30b8e0 L |
10258 | }, |
10259 | { | |
592a252b | 10260 | /* VEX_W_0F6D_P_2 */ |
6c30d220 | 10261 | { "vpunpckhqdq", { XM, Vex, EXx } }, |
9e30b8e0 L |
10262 | }, |
10263 | { | |
592a252b | 10264 | /* VEX_W_0F6F_P_1 */ |
efdb52b7 | 10265 | { "vmovdqu", { XM, EXx } }, |
9e30b8e0 L |
10266 | }, |
10267 | { | |
592a252b | 10268 | /* VEX_W_0F6F_P_2 */ |
efdb52b7 | 10269 | { "vmovdqa", { XM, EXx } }, |
9e30b8e0 L |
10270 | }, |
10271 | { | |
592a252b | 10272 | /* VEX_W_0F70_P_1 */ |
9e30b8e0 | 10273 | { "vpshufhw", { XM, EXx, Ib } }, |
9e30b8e0 L |
10274 | }, |
10275 | { | |
592a252b | 10276 | /* VEX_W_0F70_P_2 */ |
9e30b8e0 | 10277 | { "vpshufd", { XM, EXx, Ib } }, |
9e30b8e0 L |
10278 | }, |
10279 | { | |
592a252b | 10280 | /* VEX_W_0F70_P_3 */ |
9e30b8e0 | 10281 | { "vpshuflw", { XM, EXx, Ib } }, |
9e30b8e0 L |
10282 | }, |
10283 | { | |
592a252b | 10284 | /* VEX_W_0F71_R_2_P_2 */ |
6c30d220 | 10285 | { "vpsrlw", { Vex, XS, Ib } }, |
9e30b8e0 L |
10286 | }, |
10287 | { | |
592a252b | 10288 | /* VEX_W_0F71_R_4_P_2 */ |
6c30d220 | 10289 | { "vpsraw", { Vex, XS, Ib } }, |
9e30b8e0 L |
10290 | }, |
10291 | { | |
592a252b | 10292 | /* VEX_W_0F71_R_6_P_2 */ |
6c30d220 | 10293 | { "vpsllw", { Vex, XS, Ib } }, |
9e30b8e0 L |
10294 | }, |
10295 | { | |
592a252b | 10296 | /* VEX_W_0F72_R_2_P_2 */ |
6c30d220 | 10297 | { "vpsrld", { Vex, XS, Ib } }, |
9e30b8e0 L |
10298 | }, |
10299 | { | |
592a252b | 10300 | /* VEX_W_0F72_R_4_P_2 */ |
6c30d220 | 10301 | { "vpsrad", { Vex, XS, Ib } }, |
9e30b8e0 L |
10302 | }, |
10303 | { | |
592a252b | 10304 | /* VEX_W_0F72_R_6_P_2 */ |
6c30d220 | 10305 | { "vpslld", { Vex, XS, Ib } }, |
9e30b8e0 L |
10306 | }, |
10307 | { | |
592a252b | 10308 | /* VEX_W_0F73_R_2_P_2 */ |
6c30d220 | 10309 | { "vpsrlq", { Vex, XS, Ib } }, |
9e30b8e0 L |
10310 | }, |
10311 | { | |
592a252b | 10312 | /* VEX_W_0F73_R_3_P_2 */ |
6c30d220 | 10313 | { "vpsrldq", { Vex, XS, Ib } }, |
9e30b8e0 L |
10314 | }, |
10315 | { | |
592a252b | 10316 | /* VEX_W_0F73_R_6_P_2 */ |
6c30d220 | 10317 | { "vpsllq", { Vex, XS, Ib } }, |
9e30b8e0 L |
10318 | }, |
10319 | { | |
592a252b | 10320 | /* VEX_W_0F73_R_7_P_2 */ |
6c30d220 | 10321 | { "vpslldq", { Vex, XS, Ib } }, |
9e30b8e0 L |
10322 | }, |
10323 | { | |
592a252b | 10324 | /* VEX_W_0F74_P_2 */ |
6c30d220 | 10325 | { "vpcmpeqb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10326 | }, |
10327 | { | |
592a252b | 10328 | /* VEX_W_0F75_P_2 */ |
6c30d220 | 10329 | { "vpcmpeqw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10330 | }, |
10331 | { | |
592a252b | 10332 | /* VEX_W_0F76_P_2 */ |
6c30d220 | 10333 | { "vpcmpeqd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10334 | }, |
10335 | { | |
592a252b | 10336 | /* VEX_W_0F77_P_0 */ |
9e30b8e0 | 10337 | { "", { VZERO } }, |
9e30b8e0 L |
10338 | }, |
10339 | { | |
592a252b | 10340 | /* VEX_W_0F7C_P_2 */ |
9e30b8e0 | 10341 | { "vhaddpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10342 | }, |
10343 | { | |
592a252b | 10344 | /* VEX_W_0F7C_P_3 */ |
9e30b8e0 | 10345 | { "vhaddps", { XM, Vex, EXx } }, |
9e30b8e0 L |
10346 | }, |
10347 | { | |
592a252b | 10348 | /* VEX_W_0F7D_P_2 */ |
9e30b8e0 | 10349 | { "vhsubpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10350 | }, |
10351 | { | |
592a252b | 10352 | /* VEX_W_0F7D_P_3 */ |
9e30b8e0 | 10353 | { "vhsubps", { XM, Vex, EXx } }, |
9e30b8e0 L |
10354 | }, |
10355 | { | |
592a252b | 10356 | /* VEX_W_0F7E_P_1 */ |
539f890d | 10357 | { "vmovq", { XMScalar, EXqScalar } }, |
9e30b8e0 L |
10358 | }, |
10359 | { | |
592a252b | 10360 | /* VEX_W_0F7F_P_1 */ |
9e30b8e0 | 10361 | { "vmovdqu", { EXxS, XM } }, |
9e30b8e0 L |
10362 | }, |
10363 | { | |
592a252b | 10364 | /* VEX_W_0F7F_P_2 */ |
9e30b8e0 | 10365 | { "vmovdqa", { EXxS, XM } }, |
9e30b8e0 | 10366 | }, |
43234a1e L |
10367 | { |
10368 | /* VEX_W_0F90_P_0_LEN_0 */ | |
10369 | { "kmovw", { MaskG, MaskE } }, | |
10370 | }, | |
10371 | { | |
10372 | /* VEX_W_0F91_P_0_LEN_0 */ | |
10373 | { "kmovw", { Ew, MaskG } }, | |
10374 | }, | |
10375 | { | |
10376 | /* VEX_W_0F92_P_0_LEN_0 */ | |
10377 | { "kmovw", { MaskG, Rdq } }, | |
10378 | }, | |
10379 | { | |
10380 | /* VEX_W_0F93_P_0_LEN_0 */ | |
10381 | { "kmovw", { Gdq, MaskR } }, | |
10382 | }, | |
10383 | { | |
10384 | /* VEX_W_0F98_P_0_LEN_0 */ | |
10385 | { "kortestw", { MaskG, MaskR } }, | |
10386 | }, | |
9e30b8e0 | 10387 | { |
592a252b | 10388 | /* VEX_W_0FAE_R_2_M_0 */ |
9e30b8e0 | 10389 | { "vldmxcsr", { Md } }, |
9e30b8e0 L |
10390 | }, |
10391 | { | |
592a252b | 10392 | /* VEX_W_0FAE_R_3_M_0 */ |
9e30b8e0 | 10393 | { "vstmxcsr", { Md } }, |
9e30b8e0 L |
10394 | }, |
10395 | { | |
592a252b | 10396 | /* VEX_W_0FC2_P_0 */ |
9e30b8e0 | 10397 | { "vcmpps", { XM, Vex, EXx, VCMP } }, |
9e30b8e0 L |
10398 | }, |
10399 | { | |
592a252b | 10400 | /* VEX_W_0FC2_P_1 */ |
539f890d | 10401 | { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP } }, |
9e30b8e0 L |
10402 | }, |
10403 | { | |
592a252b | 10404 | /* VEX_W_0FC2_P_2 */ |
9e30b8e0 | 10405 | { "vcmppd", { XM, Vex, EXx, VCMP } }, |
9e30b8e0 L |
10406 | }, |
10407 | { | |
592a252b | 10408 | /* VEX_W_0FC2_P_3 */ |
539f890d | 10409 | { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP } }, |
9e30b8e0 L |
10410 | }, |
10411 | { | |
592a252b | 10412 | /* VEX_W_0FC4_P_2 */ |
9e30b8e0 | 10413 | { "vpinsrw", { XM, Vex128, Edqw, Ib } }, |
9e30b8e0 L |
10414 | }, |
10415 | { | |
592a252b | 10416 | /* VEX_W_0FC5_P_2 */ |
9e30b8e0 | 10417 | { "vpextrw", { Gdq, XS, Ib } }, |
9e30b8e0 L |
10418 | }, |
10419 | { | |
592a252b | 10420 | /* VEX_W_0FD0_P_2 */ |
9e30b8e0 | 10421 | { "vaddsubpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10422 | }, |
10423 | { | |
592a252b | 10424 | /* VEX_W_0FD0_P_3 */ |
9e30b8e0 | 10425 | { "vaddsubps", { XM, Vex, EXx } }, |
9e30b8e0 L |
10426 | }, |
10427 | { | |
592a252b | 10428 | /* VEX_W_0FD1_P_2 */ |
6c30d220 | 10429 | { "vpsrlw", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
10430 | }, |
10431 | { | |
592a252b | 10432 | /* VEX_W_0FD2_P_2 */ |
6c30d220 | 10433 | { "vpsrld", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
10434 | }, |
10435 | { | |
592a252b | 10436 | /* VEX_W_0FD3_P_2 */ |
6c30d220 | 10437 | { "vpsrlq", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
10438 | }, |
10439 | { | |
592a252b | 10440 | /* VEX_W_0FD4_P_2 */ |
6c30d220 | 10441 | { "vpaddq", { XM, Vex, EXx } }, |
9e30b8e0 L |
10442 | }, |
10443 | { | |
592a252b | 10444 | /* VEX_W_0FD5_P_2 */ |
6c30d220 | 10445 | { "vpmullw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10446 | }, |
10447 | { | |
592a252b | 10448 | /* VEX_W_0FD6_P_2 */ |
539f890d | 10449 | { "vmovq", { EXqScalarS, XMScalar } }, |
9e30b8e0 L |
10450 | }, |
10451 | { | |
592a252b | 10452 | /* VEX_W_0FD7_P_2_M_1 */ |
9e30b8e0 | 10453 | { "vpmovmskb", { Gdq, XS } }, |
9e30b8e0 L |
10454 | }, |
10455 | { | |
592a252b | 10456 | /* VEX_W_0FD8_P_2 */ |
6c30d220 | 10457 | { "vpsubusb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10458 | }, |
10459 | { | |
592a252b | 10460 | /* VEX_W_0FD9_P_2 */ |
6c30d220 | 10461 | { "vpsubusw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10462 | }, |
10463 | { | |
592a252b | 10464 | /* VEX_W_0FDA_P_2 */ |
6c30d220 | 10465 | { "vpminub", { XM, Vex, EXx } }, |
9e30b8e0 L |
10466 | }, |
10467 | { | |
592a252b | 10468 | /* VEX_W_0FDB_P_2 */ |
6c30d220 | 10469 | { "vpand", { XM, Vex, EXx } }, |
9e30b8e0 L |
10470 | }, |
10471 | { | |
592a252b | 10472 | /* VEX_W_0FDC_P_2 */ |
6c30d220 | 10473 | { "vpaddusb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10474 | }, |
10475 | { | |
592a252b | 10476 | /* VEX_W_0FDD_P_2 */ |
6c30d220 | 10477 | { "vpaddusw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10478 | }, |
10479 | { | |
592a252b | 10480 | /* VEX_W_0FDE_P_2 */ |
6c30d220 | 10481 | { "vpmaxub", { XM, Vex, EXx } }, |
9e30b8e0 L |
10482 | }, |
10483 | { | |
592a252b | 10484 | /* VEX_W_0FDF_P_2 */ |
6c30d220 | 10485 | { "vpandn", { XM, Vex, EXx } }, |
9e30b8e0 L |
10486 | }, |
10487 | { | |
592a252b | 10488 | /* VEX_W_0FE0_P_2 */ |
6c30d220 | 10489 | { "vpavgb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10490 | }, |
10491 | { | |
592a252b | 10492 | /* VEX_W_0FE1_P_2 */ |
6c30d220 | 10493 | { "vpsraw", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
10494 | }, |
10495 | { | |
592a252b | 10496 | /* VEX_W_0FE2_P_2 */ |
6c30d220 | 10497 | { "vpsrad", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
10498 | }, |
10499 | { | |
592a252b | 10500 | /* VEX_W_0FE3_P_2 */ |
6c30d220 | 10501 | { "vpavgw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10502 | }, |
10503 | { | |
592a252b | 10504 | /* VEX_W_0FE4_P_2 */ |
6c30d220 | 10505 | { "vpmulhuw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10506 | }, |
10507 | { | |
592a252b | 10508 | /* VEX_W_0FE5_P_2 */ |
6c30d220 | 10509 | { "vpmulhw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10510 | }, |
10511 | { | |
592a252b | 10512 | /* VEX_W_0FE6_P_1 */ |
efdb52b7 | 10513 | { "vcvtdq2pd", { XM, EXxmmq } }, |
9e30b8e0 L |
10514 | }, |
10515 | { | |
592a252b | 10516 | /* VEX_W_0FE6_P_2 */ |
a179a9fd | 10517 | { "vcvttpd2dq%XY", { XMM, EXx } }, |
9e30b8e0 L |
10518 | }, |
10519 | { | |
592a252b | 10520 | /* VEX_W_0FE6_P_3 */ |
a179a9fd | 10521 | { "vcvtpd2dq%XY", { XMM, EXx } }, |
9e30b8e0 L |
10522 | }, |
10523 | { | |
592a252b | 10524 | /* VEX_W_0FE7_P_2_M_0 */ |
9e30b8e0 | 10525 | { "vmovntdq", { Mx, XM } }, |
9e30b8e0 L |
10526 | }, |
10527 | { | |
592a252b | 10528 | /* VEX_W_0FE8_P_2 */ |
6c30d220 | 10529 | { "vpsubsb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10530 | }, |
10531 | { | |
592a252b | 10532 | /* VEX_W_0FE9_P_2 */ |
6c30d220 | 10533 | { "vpsubsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10534 | }, |
10535 | { | |
592a252b | 10536 | /* VEX_W_0FEA_P_2 */ |
6c30d220 | 10537 | { "vpminsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10538 | }, |
10539 | { | |
592a252b | 10540 | /* VEX_W_0FEB_P_2 */ |
6c30d220 | 10541 | { "vpor", { XM, Vex, EXx } }, |
9e30b8e0 L |
10542 | }, |
10543 | { | |
592a252b | 10544 | /* VEX_W_0FEC_P_2 */ |
6c30d220 | 10545 | { "vpaddsb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10546 | }, |
10547 | { | |
592a252b | 10548 | /* VEX_W_0FED_P_2 */ |
6c30d220 | 10549 | { "vpaddsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10550 | }, |
10551 | { | |
592a252b | 10552 | /* VEX_W_0FEE_P_2 */ |
6c30d220 | 10553 | { "vpmaxsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10554 | }, |
10555 | { | |
592a252b | 10556 | /* VEX_W_0FEF_P_2 */ |
6c30d220 | 10557 | { "vpxor", { XM, Vex, EXx } }, |
9e30b8e0 L |
10558 | }, |
10559 | { | |
592a252b | 10560 | /* VEX_W_0FF0_P_3_M_0 */ |
9e30b8e0 | 10561 | { "vlddqu", { XM, M } }, |
9e30b8e0 L |
10562 | }, |
10563 | { | |
592a252b | 10564 | /* VEX_W_0FF1_P_2 */ |
6c30d220 | 10565 | { "vpsllw", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
10566 | }, |
10567 | { | |
592a252b | 10568 | /* VEX_W_0FF2_P_2 */ |
6c30d220 | 10569 | { "vpslld", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
10570 | }, |
10571 | { | |
592a252b | 10572 | /* VEX_W_0FF3_P_2 */ |
6c30d220 | 10573 | { "vpsllq", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
10574 | }, |
10575 | { | |
592a252b | 10576 | /* VEX_W_0FF4_P_2 */ |
6c30d220 | 10577 | { "vpmuludq", { XM, Vex, EXx } }, |
9e30b8e0 L |
10578 | }, |
10579 | { | |
592a252b | 10580 | /* VEX_W_0FF5_P_2 */ |
6c30d220 | 10581 | { "vpmaddwd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10582 | }, |
10583 | { | |
592a252b | 10584 | /* VEX_W_0FF6_P_2 */ |
6c30d220 | 10585 | { "vpsadbw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10586 | }, |
10587 | { | |
592a252b | 10588 | /* VEX_W_0FF7_P_2 */ |
9e30b8e0 | 10589 | { "vmaskmovdqu", { XM, XS } }, |
9e30b8e0 L |
10590 | }, |
10591 | { | |
592a252b | 10592 | /* VEX_W_0FF8_P_2 */ |
6c30d220 | 10593 | { "vpsubb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10594 | }, |
10595 | { | |
592a252b | 10596 | /* VEX_W_0FF9_P_2 */ |
6c30d220 | 10597 | { "vpsubw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10598 | }, |
10599 | { | |
592a252b | 10600 | /* VEX_W_0FFA_P_2 */ |
6c30d220 | 10601 | { "vpsubd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10602 | }, |
10603 | { | |
592a252b | 10604 | /* VEX_W_0FFB_P_2 */ |
6c30d220 | 10605 | { "vpsubq", { XM, Vex, EXx } }, |
9e30b8e0 L |
10606 | }, |
10607 | { | |
592a252b | 10608 | /* VEX_W_0FFC_P_2 */ |
6c30d220 | 10609 | { "vpaddb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10610 | }, |
10611 | { | |
592a252b | 10612 | /* VEX_W_0FFD_P_2 */ |
6c30d220 | 10613 | { "vpaddw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10614 | }, |
10615 | { | |
592a252b | 10616 | /* VEX_W_0FFE_P_2 */ |
6c30d220 | 10617 | { "vpaddd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10618 | }, |
10619 | { | |
592a252b | 10620 | /* VEX_W_0F3800_P_2 */ |
6c30d220 | 10621 | { "vpshufb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10622 | }, |
10623 | { | |
592a252b | 10624 | /* VEX_W_0F3801_P_2 */ |
6c30d220 | 10625 | { "vphaddw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10626 | }, |
10627 | { | |
592a252b | 10628 | /* VEX_W_0F3802_P_2 */ |
6c30d220 | 10629 | { "vphaddd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10630 | }, |
10631 | { | |
592a252b | 10632 | /* VEX_W_0F3803_P_2 */ |
6c30d220 | 10633 | { "vphaddsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10634 | }, |
10635 | { | |
592a252b | 10636 | /* VEX_W_0F3804_P_2 */ |
6c30d220 | 10637 | { "vpmaddubsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10638 | }, |
10639 | { | |
592a252b | 10640 | /* VEX_W_0F3805_P_2 */ |
6c30d220 | 10641 | { "vphsubw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10642 | }, |
10643 | { | |
592a252b | 10644 | /* VEX_W_0F3806_P_2 */ |
6c30d220 | 10645 | { "vphsubd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10646 | }, |
10647 | { | |
592a252b | 10648 | /* VEX_W_0F3807_P_2 */ |
6c30d220 | 10649 | { "vphsubsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10650 | }, |
10651 | { | |
592a252b | 10652 | /* VEX_W_0F3808_P_2 */ |
6c30d220 | 10653 | { "vpsignb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10654 | }, |
10655 | { | |
592a252b | 10656 | /* VEX_W_0F3809_P_2 */ |
6c30d220 | 10657 | { "vpsignw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10658 | }, |
10659 | { | |
592a252b | 10660 | /* VEX_W_0F380A_P_2 */ |
6c30d220 | 10661 | { "vpsignd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10662 | }, |
10663 | { | |
592a252b | 10664 | /* VEX_W_0F380B_P_2 */ |
6c30d220 | 10665 | { "vpmulhrsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10666 | }, |
10667 | { | |
592a252b | 10668 | /* VEX_W_0F380C_P_2 */ |
9e30b8e0 | 10669 | { "vpermilps", { XM, Vex, EXx } }, |
9e30b8e0 L |
10670 | }, |
10671 | { | |
592a252b | 10672 | /* VEX_W_0F380D_P_2 */ |
9e30b8e0 | 10673 | { "vpermilpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10674 | }, |
10675 | { | |
592a252b | 10676 | /* VEX_W_0F380E_P_2 */ |
9e30b8e0 | 10677 | { "vtestps", { XM, EXx } }, |
9e30b8e0 L |
10678 | }, |
10679 | { | |
592a252b | 10680 | /* VEX_W_0F380F_P_2 */ |
9e30b8e0 | 10681 | { "vtestpd", { XM, EXx } }, |
9e30b8e0 | 10682 | }, |
6c30d220 L |
10683 | { |
10684 | /* VEX_W_0F3816_P_2 */ | |
10685 | { "vpermps", { XM, Vex, EXx } }, | |
10686 | }, | |
9e30b8e0 | 10687 | { |
592a252b | 10688 | /* VEX_W_0F3817_P_2 */ |
9e30b8e0 | 10689 | { "vptest", { XM, EXx } }, |
9e30b8e0 | 10690 | }, |
bcf2684f | 10691 | { |
6c30d220 L |
10692 | /* VEX_W_0F3818_P_2 */ |
10693 | { "vbroadcastss", { XM, EXxmm_md } }, | |
bcf2684f | 10694 | }, |
9e30b8e0 | 10695 | { |
6c30d220 L |
10696 | /* VEX_W_0F3819_P_2 */ |
10697 | { "vbroadcastsd", { XM, EXxmm_mq } }, | |
9e30b8e0 L |
10698 | }, |
10699 | { | |
592a252b | 10700 | /* VEX_W_0F381A_P_2_M_0 */ |
9e30b8e0 | 10701 | { "vbroadcastf128", { XM, Mxmm } }, |
9e30b8e0 L |
10702 | }, |
10703 | { | |
592a252b | 10704 | /* VEX_W_0F381C_P_2 */ |
9e30b8e0 | 10705 | { "vpabsb", { XM, EXx } }, |
9e30b8e0 L |
10706 | }, |
10707 | { | |
592a252b | 10708 | /* VEX_W_0F381D_P_2 */ |
9e30b8e0 | 10709 | { "vpabsw", { XM, EXx } }, |
9e30b8e0 L |
10710 | }, |
10711 | { | |
592a252b | 10712 | /* VEX_W_0F381E_P_2 */ |
9e30b8e0 | 10713 | { "vpabsd", { XM, EXx } }, |
9e30b8e0 L |
10714 | }, |
10715 | { | |
592a252b | 10716 | /* VEX_W_0F3820_P_2 */ |
6c30d220 | 10717 | { "vpmovsxbw", { XM, EXxmmq } }, |
9e30b8e0 L |
10718 | }, |
10719 | { | |
592a252b | 10720 | /* VEX_W_0F3821_P_2 */ |
6c30d220 | 10721 | { "vpmovsxbd", { XM, EXxmmqd } }, |
9e30b8e0 L |
10722 | }, |
10723 | { | |
592a252b | 10724 | /* VEX_W_0F3822_P_2 */ |
6c30d220 | 10725 | { "vpmovsxbq", { XM, EXxmmdw } }, |
9e30b8e0 L |
10726 | }, |
10727 | { | |
592a252b | 10728 | /* VEX_W_0F3823_P_2 */ |
6c30d220 | 10729 | { "vpmovsxwd", { XM, EXxmmq } }, |
9e30b8e0 L |
10730 | }, |
10731 | { | |
592a252b | 10732 | /* VEX_W_0F3824_P_2 */ |
6c30d220 | 10733 | { "vpmovsxwq", { XM, EXxmmqd } }, |
9e30b8e0 L |
10734 | }, |
10735 | { | |
592a252b | 10736 | /* VEX_W_0F3825_P_2 */ |
6c30d220 | 10737 | { "vpmovsxdq", { XM, EXxmmq } }, |
9e30b8e0 L |
10738 | }, |
10739 | { | |
592a252b | 10740 | /* VEX_W_0F3828_P_2 */ |
6c30d220 | 10741 | { "vpmuldq", { XM, Vex, EXx } }, |
9e30b8e0 L |
10742 | }, |
10743 | { | |
592a252b | 10744 | /* VEX_W_0F3829_P_2 */ |
6c30d220 | 10745 | { "vpcmpeqq", { XM, Vex, EXx } }, |
9e30b8e0 L |
10746 | }, |
10747 | { | |
592a252b | 10748 | /* VEX_W_0F382A_P_2_M_0 */ |
9e30b8e0 | 10749 | { "vmovntdqa", { XM, Mx } }, |
9e30b8e0 L |
10750 | }, |
10751 | { | |
592a252b | 10752 | /* VEX_W_0F382B_P_2 */ |
6c30d220 | 10753 | { "vpackusdw", { XM, Vex, EXx } }, |
9e30b8e0 | 10754 | }, |
53aa04a0 | 10755 | { |
592a252b | 10756 | /* VEX_W_0F382C_P_2_M_0 */ |
53aa04a0 | 10757 | { "vmaskmovps", { XM, Vex, Mx } }, |
53aa04a0 L |
10758 | }, |
10759 | { | |
592a252b | 10760 | /* VEX_W_0F382D_P_2_M_0 */ |
53aa04a0 | 10761 | { "vmaskmovpd", { XM, Vex, Mx } }, |
53aa04a0 L |
10762 | }, |
10763 | { | |
592a252b | 10764 | /* VEX_W_0F382E_P_2_M_0 */ |
53aa04a0 | 10765 | { "vmaskmovps", { Mx, Vex, XM } }, |
53aa04a0 L |
10766 | }, |
10767 | { | |
592a252b | 10768 | /* VEX_W_0F382F_P_2_M_0 */ |
53aa04a0 | 10769 | { "vmaskmovpd", { Mx, Vex, XM } }, |
53aa04a0 | 10770 | }, |
9e30b8e0 | 10771 | { |
592a252b | 10772 | /* VEX_W_0F3830_P_2 */ |
6c30d220 | 10773 | { "vpmovzxbw", { XM, EXxmmq } }, |
9e30b8e0 L |
10774 | }, |
10775 | { | |
592a252b | 10776 | /* VEX_W_0F3831_P_2 */ |
6c30d220 | 10777 | { "vpmovzxbd", { XM, EXxmmqd } }, |
9e30b8e0 L |
10778 | }, |
10779 | { | |
592a252b | 10780 | /* VEX_W_0F3832_P_2 */ |
6c30d220 | 10781 | { "vpmovzxbq", { XM, EXxmmdw } }, |
9e30b8e0 L |
10782 | }, |
10783 | { | |
592a252b | 10784 | /* VEX_W_0F3833_P_2 */ |
6c30d220 | 10785 | { "vpmovzxwd", { XM, EXxmmq } }, |
9e30b8e0 L |
10786 | }, |
10787 | { | |
592a252b | 10788 | /* VEX_W_0F3834_P_2 */ |
6c30d220 | 10789 | { "vpmovzxwq", { XM, EXxmmqd } }, |
9e30b8e0 L |
10790 | }, |
10791 | { | |
592a252b | 10792 | /* VEX_W_0F3835_P_2 */ |
6c30d220 L |
10793 | { "vpmovzxdq", { XM, EXxmmq } }, |
10794 | }, | |
10795 | { | |
10796 | /* VEX_W_0F3836_P_2 */ | |
10797 | { "vpermd", { XM, Vex, EXx } }, | |
9e30b8e0 L |
10798 | }, |
10799 | { | |
592a252b | 10800 | /* VEX_W_0F3837_P_2 */ |
6c30d220 | 10801 | { "vpcmpgtq", { XM, Vex, EXx } }, |
9e30b8e0 L |
10802 | }, |
10803 | { | |
592a252b | 10804 | /* VEX_W_0F3838_P_2 */ |
6c30d220 | 10805 | { "vpminsb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10806 | }, |
10807 | { | |
592a252b | 10808 | /* VEX_W_0F3839_P_2 */ |
6c30d220 | 10809 | { "vpminsd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10810 | }, |
10811 | { | |
592a252b | 10812 | /* VEX_W_0F383A_P_2 */ |
6c30d220 | 10813 | { "vpminuw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10814 | }, |
10815 | { | |
592a252b | 10816 | /* VEX_W_0F383B_P_2 */ |
6c30d220 | 10817 | { "vpminud", { XM, Vex, EXx } }, |
9e30b8e0 L |
10818 | }, |
10819 | { | |
592a252b | 10820 | /* VEX_W_0F383C_P_2 */ |
6c30d220 | 10821 | { "vpmaxsb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10822 | }, |
10823 | { | |
592a252b | 10824 | /* VEX_W_0F383D_P_2 */ |
6c30d220 | 10825 | { "vpmaxsd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10826 | }, |
10827 | { | |
592a252b | 10828 | /* VEX_W_0F383E_P_2 */ |
6c30d220 | 10829 | { "vpmaxuw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10830 | }, |
10831 | { | |
592a252b | 10832 | /* VEX_W_0F383F_P_2 */ |
6c30d220 | 10833 | { "vpmaxud", { XM, Vex, EXx } }, |
9e30b8e0 L |
10834 | }, |
10835 | { | |
592a252b | 10836 | /* VEX_W_0F3840_P_2 */ |
6c30d220 | 10837 | { "vpmulld", { XM, Vex, EXx } }, |
9e30b8e0 L |
10838 | }, |
10839 | { | |
592a252b | 10840 | /* VEX_W_0F3841_P_2 */ |
9e30b8e0 | 10841 | { "vphminposuw", { XM, EXx } }, |
9e30b8e0 | 10842 | }, |
6c30d220 L |
10843 | { |
10844 | /* VEX_W_0F3846_P_2 */ | |
10845 | { "vpsravd", { XM, Vex, EXx } }, | |
10846 | }, | |
10847 | { | |
10848 | /* VEX_W_0F3858_P_2 */ | |
10849 | { "vpbroadcastd", { XM, EXxmm_md } }, | |
10850 | }, | |
10851 | { | |
10852 | /* VEX_W_0F3859_P_2 */ | |
10853 | { "vpbroadcastq", { XM, EXxmm_mq } }, | |
10854 | }, | |
10855 | { | |
10856 | /* VEX_W_0F385A_P_2_M_0 */ | |
10857 | { "vbroadcasti128", { XM, Mxmm } }, | |
10858 | }, | |
10859 | { | |
10860 | /* VEX_W_0F3878_P_2 */ | |
10861 | { "vpbroadcastb", { XM, EXxmm_mb } }, | |
10862 | }, | |
10863 | { | |
10864 | /* VEX_W_0F3879_P_2 */ | |
10865 | { "vpbroadcastw", { XM, EXxmm_mw } }, | |
10866 | }, | |
9e30b8e0 | 10867 | { |
592a252b | 10868 | /* VEX_W_0F38DB_P_2 */ |
9e30b8e0 | 10869 | { "vaesimc", { XM, EXx } }, |
9e30b8e0 L |
10870 | }, |
10871 | { | |
592a252b | 10872 | /* VEX_W_0F38DC_P_2 */ |
9e30b8e0 | 10873 | { "vaesenc", { XM, Vex128, EXx } }, |
9e30b8e0 L |
10874 | }, |
10875 | { | |
592a252b | 10876 | /* VEX_W_0F38DD_P_2 */ |
9e30b8e0 | 10877 | { "vaesenclast", { XM, Vex128, EXx } }, |
9e30b8e0 L |
10878 | }, |
10879 | { | |
592a252b | 10880 | /* VEX_W_0F38DE_P_2 */ |
9e30b8e0 | 10881 | { "vaesdec", { XM, Vex128, EXx } }, |
9e30b8e0 L |
10882 | }, |
10883 | { | |
592a252b | 10884 | /* VEX_W_0F38DF_P_2 */ |
9e30b8e0 | 10885 | { "vaesdeclast", { XM, Vex128, EXx } }, |
9e30b8e0 | 10886 | }, |
6c30d220 L |
10887 | { |
10888 | /* VEX_W_0F3A00_P_2 */ | |
10889 | { Bad_Opcode }, | |
10890 | { "vpermq", { XM, EXx, Ib } }, | |
10891 | }, | |
10892 | { | |
10893 | /* VEX_W_0F3A01_P_2 */ | |
10894 | { Bad_Opcode }, | |
10895 | { "vpermpd", { XM, EXx, Ib } }, | |
10896 | }, | |
10897 | { | |
10898 | /* VEX_W_0F3A02_P_2 */ | |
10899 | { "vpblendd", { XM, Vex, EXx, Ib } }, | |
10900 | }, | |
9e30b8e0 | 10901 | { |
592a252b | 10902 | /* VEX_W_0F3A04_P_2 */ |
9e30b8e0 | 10903 | { "vpermilps", { XM, EXx, Ib } }, |
9e30b8e0 L |
10904 | }, |
10905 | { | |
592a252b | 10906 | /* VEX_W_0F3A05_P_2 */ |
9e30b8e0 | 10907 | { "vpermilpd", { XM, EXx, Ib } }, |
9e30b8e0 L |
10908 | }, |
10909 | { | |
592a252b | 10910 | /* VEX_W_0F3A06_P_2 */ |
9e30b8e0 | 10911 | { "vperm2f128", { XM, Vex256, EXx, Ib } }, |
9e30b8e0 L |
10912 | }, |
10913 | { | |
592a252b | 10914 | /* VEX_W_0F3A08_P_2 */ |
9e30b8e0 | 10915 | { "vroundps", { XM, EXx, Ib } }, |
9e30b8e0 L |
10916 | }, |
10917 | { | |
592a252b | 10918 | /* VEX_W_0F3A09_P_2 */ |
9e30b8e0 | 10919 | { "vroundpd", { XM, EXx, Ib } }, |
9e30b8e0 L |
10920 | }, |
10921 | { | |
592a252b | 10922 | /* VEX_W_0F3A0A_P_2 */ |
539f890d | 10923 | { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib } }, |
9e30b8e0 L |
10924 | }, |
10925 | { | |
592a252b | 10926 | /* VEX_W_0F3A0B_P_2 */ |
539f890d | 10927 | { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib } }, |
9e30b8e0 L |
10928 | }, |
10929 | { | |
592a252b | 10930 | /* VEX_W_0F3A0C_P_2 */ |
9e30b8e0 | 10931 | { "vblendps", { XM, Vex, EXx, Ib } }, |
9e30b8e0 L |
10932 | }, |
10933 | { | |
592a252b | 10934 | /* VEX_W_0F3A0D_P_2 */ |
9e30b8e0 | 10935 | { "vblendpd", { XM, Vex, EXx, Ib } }, |
9e30b8e0 L |
10936 | }, |
10937 | { | |
592a252b | 10938 | /* VEX_W_0F3A0E_P_2 */ |
6c30d220 | 10939 | { "vpblendw", { XM, Vex, EXx, Ib } }, |
9e30b8e0 L |
10940 | }, |
10941 | { | |
592a252b | 10942 | /* VEX_W_0F3A0F_P_2 */ |
6c30d220 | 10943 | { "vpalignr", { XM, Vex, EXx, Ib } }, |
9e30b8e0 L |
10944 | }, |
10945 | { | |
592a252b | 10946 | /* VEX_W_0F3A14_P_2 */ |
9e30b8e0 | 10947 | { "vpextrb", { Edqb, XM, Ib } }, |
9e30b8e0 L |
10948 | }, |
10949 | { | |
592a252b | 10950 | /* VEX_W_0F3A15_P_2 */ |
9e30b8e0 | 10951 | { "vpextrw", { Edqw, XM, Ib } }, |
9e30b8e0 L |
10952 | }, |
10953 | { | |
592a252b | 10954 | /* VEX_W_0F3A18_P_2 */ |
9e30b8e0 | 10955 | { "vinsertf128", { XM, Vex256, EXxmm, Ib } }, |
9e30b8e0 L |
10956 | }, |
10957 | { | |
592a252b | 10958 | /* VEX_W_0F3A19_P_2 */ |
9e30b8e0 | 10959 | { "vextractf128", { EXxmm, XM, Ib } }, |
9e30b8e0 L |
10960 | }, |
10961 | { | |
592a252b | 10962 | /* VEX_W_0F3A20_P_2 */ |
9e30b8e0 | 10963 | { "vpinsrb", { XM, Vex128, Edqb, Ib } }, |
9e30b8e0 L |
10964 | }, |
10965 | { | |
592a252b | 10966 | /* VEX_W_0F3A21_P_2 */ |
9e30b8e0 | 10967 | { "vinsertps", { XM, Vex128, EXd, Ib } }, |
9e30b8e0 | 10968 | }, |
43234a1e L |
10969 | { |
10970 | /* VEX_W_0F3A30_P_2 */ | |
10971 | { Bad_Opcode }, | |
10972 | { "kshiftrw", { MaskG, MaskR, Ib } }, | |
10973 | }, | |
10974 | { | |
10975 | /* VEX_W_0F3A32_P_2 */ | |
10976 | { Bad_Opcode }, | |
10977 | { "kshiftlw", { MaskG, MaskR, Ib } }, | |
10978 | }, | |
6c30d220 L |
10979 | { |
10980 | /* VEX_W_0F3A38_P_2 */ | |
10981 | { "vinserti128", { XM, Vex256, EXxmm, Ib } }, | |
10982 | }, | |
10983 | { | |
10984 | /* VEX_W_0F3A39_P_2 */ | |
10985 | { "vextracti128", { EXxmm, XM, Ib } }, | |
10986 | }, | |
9e30b8e0 | 10987 | { |
592a252b | 10988 | /* VEX_W_0F3A40_P_2 */ |
9e30b8e0 | 10989 | { "vdpps", { XM, Vex, EXx, Ib } }, |
9e30b8e0 L |
10990 | }, |
10991 | { | |
592a252b | 10992 | /* VEX_W_0F3A41_P_2 */ |
9e30b8e0 | 10993 | { "vdppd", { XM, Vex128, EXx, Ib } }, |
9e30b8e0 L |
10994 | }, |
10995 | { | |
592a252b | 10996 | /* VEX_W_0F3A42_P_2 */ |
6c30d220 | 10997 | { "vmpsadbw", { XM, Vex, EXx, Ib } }, |
9e30b8e0 L |
10998 | }, |
10999 | { | |
592a252b | 11000 | /* VEX_W_0F3A44_P_2 */ |
9e30b8e0 | 11001 | { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } }, |
9e30b8e0 | 11002 | }, |
6c30d220 L |
11003 | { |
11004 | /* VEX_W_0F3A46_P_2 */ | |
11005 | { "vperm2i128", { XM, Vex256, EXx, Ib } }, | |
11006 | }, | |
a683cc34 | 11007 | { |
592a252b | 11008 | /* VEX_W_0F3A48_P_2 */ |
a683cc34 SP |
11009 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, |
11010 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, | |
11011 | }, | |
11012 | { | |
592a252b | 11013 | /* VEX_W_0F3A49_P_2 */ |
a683cc34 SP |
11014 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, |
11015 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, | |
11016 | }, | |
9e30b8e0 | 11017 | { |
592a252b | 11018 | /* VEX_W_0F3A4A_P_2 */ |
9e30b8e0 | 11019 | { "vblendvps", { XM, Vex, EXx, XMVexI4 } }, |
9e30b8e0 L |
11020 | }, |
11021 | { | |
592a252b | 11022 | /* VEX_W_0F3A4B_P_2 */ |
9e30b8e0 | 11023 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 } }, |
9e30b8e0 L |
11024 | }, |
11025 | { | |
592a252b | 11026 | /* VEX_W_0F3A4C_P_2 */ |
6c30d220 | 11027 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 } }, |
9e30b8e0 L |
11028 | }, |
11029 | { | |
592a252b | 11030 | /* VEX_W_0F3A60_P_2 */ |
9e30b8e0 | 11031 | { "vpcmpestrm", { XM, EXx, Ib } }, |
9e30b8e0 L |
11032 | }, |
11033 | { | |
592a252b | 11034 | /* VEX_W_0F3A61_P_2 */ |
9e30b8e0 | 11035 | { "vpcmpestri", { XM, EXx, Ib } }, |
9e30b8e0 L |
11036 | }, |
11037 | { | |
592a252b | 11038 | /* VEX_W_0F3A62_P_2 */ |
9e30b8e0 | 11039 | { "vpcmpistrm", { XM, EXx, Ib } }, |
9e30b8e0 L |
11040 | }, |
11041 | { | |
592a252b | 11042 | /* VEX_W_0F3A63_P_2 */ |
9e30b8e0 | 11043 | { "vpcmpistri", { XM, EXx, Ib } }, |
9e30b8e0 L |
11044 | }, |
11045 | { | |
592a252b | 11046 | /* VEX_W_0F3ADF_P_2 */ |
9e30b8e0 | 11047 | { "vaeskeygenassist", { XM, EXx, Ib } }, |
9e30b8e0 | 11048 | }, |
43234a1e L |
11049 | #define NEED_VEX_W_TABLE |
11050 | #include "i386-dis-evex.h" | |
11051 | #undef NEED_VEX_W_TABLE | |
9e30b8e0 L |
11052 | }; |
11053 | ||
11054 | static const struct dis386 mod_table[][2] = { | |
11055 | { | |
11056 | /* MOD_8D */ | |
11057 | { "leaS", { Gv, M } }, | |
9e30b8e0 | 11058 | }, |
42164a71 L |
11059 | { |
11060 | /* MOD_C6_REG_7 */ | |
11061 | { Bad_Opcode }, | |
11062 | { RM_TABLE (RM_C6_REG_7) }, | |
11063 | }, | |
11064 | { | |
11065 | /* MOD_C7_REG_7 */ | |
11066 | { Bad_Opcode }, | |
11067 | { RM_TABLE (RM_C7_REG_7) }, | |
11068 | }, | |
4a357820 MZ |
11069 | { |
11070 | /* MOD_FF_REG_3 */ | |
11071 | { "Jcall{T|}", { indirEp } }, | |
11072 | }, | |
11073 | { | |
11074 | /* MOD_FF_REG_5 */ | |
11075 | { "Jjmp{T|}", { indirEp } }, | |
11076 | }, | |
9e30b8e0 L |
11077 | { |
11078 | /* MOD_0F01_REG_0 */ | |
11079 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
11080 | { RM_TABLE (RM_0F01_REG_0) }, | |
11081 | }, | |
11082 | { | |
11083 | /* MOD_0F01_REG_1 */ | |
11084 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
11085 | { RM_TABLE (RM_0F01_REG_1) }, | |
11086 | }, | |
11087 | { | |
11088 | /* MOD_0F01_REG_2 */ | |
11089 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
11090 | { RM_TABLE (RM_0F01_REG_2) }, | |
11091 | }, | |
11092 | { | |
11093 | /* MOD_0F01_REG_3 */ | |
11094 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
11095 | { RM_TABLE (RM_0F01_REG_3) }, | |
11096 | }, | |
11097 | { | |
11098 | /* MOD_0F01_REG_7 */ | |
11099 | { "invlpg", { Mb } }, | |
11100 | { RM_TABLE (RM_0F01_REG_7) }, | |
11101 | }, | |
11102 | { | |
11103 | /* MOD_0F12_PREFIX_0 */ | |
11104 | { "movlps", { XM, EXq } }, | |
11105 | { "movhlps", { XM, EXq } }, | |
11106 | }, | |
11107 | { | |
11108 | /* MOD_0F13 */ | |
11109 | { "movlpX", { EXq, XM } }, | |
9e30b8e0 L |
11110 | }, |
11111 | { | |
11112 | /* MOD_0F16_PREFIX_0 */ | |
11113 | { "movhps", { XM, EXq } }, | |
11114 | { "movlhps", { XM, EXq } }, | |
11115 | }, | |
11116 | { | |
11117 | /* MOD_0F17 */ | |
11118 | { "movhpX", { EXq, XM } }, | |
9e30b8e0 L |
11119 | }, |
11120 | { | |
11121 | /* MOD_0F18_REG_0 */ | |
11122 | { "prefetchnta", { Mb } }, | |
9e30b8e0 L |
11123 | }, |
11124 | { | |
11125 | /* MOD_0F18_REG_1 */ | |
11126 | { "prefetcht0", { Mb } }, | |
9e30b8e0 L |
11127 | }, |
11128 | { | |
11129 | /* MOD_0F18_REG_2 */ | |
11130 | { "prefetcht1", { Mb } }, | |
9e30b8e0 L |
11131 | }, |
11132 | { | |
11133 | /* MOD_0F18_REG_3 */ | |
11134 | { "prefetcht2", { Mb } }, | |
9e30b8e0 | 11135 | }, |
d7189fa5 RM |
11136 | { |
11137 | /* MOD_0F18_REG_4 */ | |
11138 | { "nop/reserved", { Mb } }, | |
11139 | }, | |
11140 | { | |
11141 | /* MOD_0F18_REG_5 */ | |
11142 | { "nop/reserved", { Mb } }, | |
11143 | }, | |
11144 | { | |
11145 | /* MOD_0F18_REG_6 */ | |
11146 | { "nop/reserved", { Mb } }, | |
11147 | }, | |
11148 | { | |
11149 | /* MOD_0F18_REG_7 */ | |
11150 | { "nop/reserved", { Mb } }, | |
11151 | }, | |
7e8b059b L |
11152 | { |
11153 | /* MOD_0F1A_PREFIX_0 */ | |
11154 | { "bndldx", { Gbnd, Ev_bnd } }, | |
11155 | { "nopQ", { Ev } }, | |
11156 | }, | |
11157 | { | |
11158 | /* MOD_0F1B_PREFIX_0 */ | |
11159 | { "bndstx", { Ev_bnd, Gbnd } }, | |
11160 | { "nopQ", { Ev } }, | |
11161 | }, | |
11162 | { | |
11163 | /* MOD_0F1B_PREFIX_1 */ | |
11164 | { "bndmk", { Gbnd, Ev_bnd } }, | |
11165 | { "nopQ", { Ev } }, | |
11166 | }, | |
9e30b8e0 L |
11167 | { |
11168 | /* MOD_0F20 */ | |
592d1631 | 11169 | { Bad_Opcode }, |
9e30b8e0 L |
11170 | { "movZ", { Rm, Cm } }, |
11171 | }, | |
11172 | { | |
11173 | /* MOD_0F21 */ | |
592d1631 | 11174 | { Bad_Opcode }, |
9e30b8e0 L |
11175 | { "movZ", { Rm, Dm } }, |
11176 | }, | |
11177 | { | |
11178 | /* MOD_0F22 */ | |
592d1631 | 11179 | { Bad_Opcode }, |
9e30b8e0 | 11180 | { "movZ", { Cm, Rm } }, |
b844680a L |
11181 | }, |
11182 | { | |
92fddf8e | 11183 | /* MOD_0F23 */ |
592d1631 | 11184 | { Bad_Opcode }, |
92fddf8e | 11185 | { "movZ", { Dm, Rm } }, |
b844680a L |
11186 | }, |
11187 | { | |
92fddf8e | 11188 | /* MOD_0F24 */ |
7bb15c6f | 11189 | { Bad_Opcode }, |
92fddf8e | 11190 | { "movL", { Rd, Td } }, |
b844680a L |
11191 | }, |
11192 | { | |
92fddf8e | 11193 | /* MOD_0F26 */ |
592d1631 | 11194 | { Bad_Opcode }, |
92fddf8e | 11195 | { "movL", { Td, Rd } }, |
b844680a | 11196 | }, |
75c135a8 L |
11197 | { |
11198 | /* MOD_0F2B_PREFIX_0 */ | |
4ee52178 | 11199 | {"movntps", { Mx, XM } }, |
75c135a8 L |
11200 | }, |
11201 | { | |
11202 | /* MOD_0F2B_PREFIX_1 */ | |
4ee52178 | 11203 | {"movntss", { Md, XM } }, |
75c135a8 L |
11204 | }, |
11205 | { | |
11206 | /* MOD_0F2B_PREFIX_2 */ | |
4ee52178 | 11207 | {"movntpd", { Mx, XM } }, |
75c135a8 L |
11208 | }, |
11209 | { | |
11210 | /* MOD_0F2B_PREFIX_3 */ | |
4ee52178 | 11211 | {"movntsd", { Mq, XM } }, |
75c135a8 L |
11212 | }, |
11213 | { | |
11214 | /* MOD_0F51 */ | |
592d1631 | 11215 | { Bad_Opcode }, |
75c135a8 L |
11216 | { "movmskpX", { Gdq, XS } }, |
11217 | }, | |
b844680a | 11218 | { |
1ceb70f8 | 11219 | /* MOD_0F71_REG_2 */ |
592d1631 | 11220 | { Bad_Opcode }, |
4e7d34a6 | 11221 | { "psrlw", { MS, Ib } }, |
b844680a L |
11222 | }, |
11223 | { | |
1ceb70f8 | 11224 | /* MOD_0F71_REG_4 */ |
592d1631 | 11225 | { Bad_Opcode }, |
4e7d34a6 | 11226 | { "psraw", { MS, Ib } }, |
b844680a L |
11227 | }, |
11228 | { | |
1ceb70f8 | 11229 | /* MOD_0F71_REG_6 */ |
592d1631 | 11230 | { Bad_Opcode }, |
4e7d34a6 | 11231 | { "psllw", { MS, Ib } }, |
b844680a L |
11232 | }, |
11233 | { | |
1ceb70f8 | 11234 | /* MOD_0F72_REG_2 */ |
592d1631 | 11235 | { Bad_Opcode }, |
4e7d34a6 | 11236 | { "psrld", { MS, Ib } }, |
b844680a L |
11237 | }, |
11238 | { | |
1ceb70f8 | 11239 | /* MOD_0F72_REG_4 */ |
592d1631 | 11240 | { Bad_Opcode }, |
4e7d34a6 | 11241 | { "psrad", { MS, Ib } }, |
b844680a L |
11242 | }, |
11243 | { | |
1ceb70f8 | 11244 | /* MOD_0F72_REG_6 */ |
592d1631 | 11245 | { Bad_Opcode }, |
4e7d34a6 | 11246 | { "pslld", { MS, Ib } }, |
b844680a L |
11247 | }, |
11248 | { | |
1ceb70f8 | 11249 | /* MOD_0F73_REG_2 */ |
592d1631 | 11250 | { Bad_Opcode }, |
4e7d34a6 | 11251 | { "psrlq", { MS, Ib } }, |
b844680a L |
11252 | }, |
11253 | { | |
1ceb70f8 | 11254 | /* MOD_0F73_REG_3 */ |
592d1631 | 11255 | { Bad_Opcode }, |
c0f3af97 L |
11256 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
11257 | }, | |
11258 | { | |
11259 | /* MOD_0F73_REG_6 */ | |
592d1631 | 11260 | { Bad_Opcode }, |
c0f3af97 L |
11261 | { "psllq", { MS, Ib } }, |
11262 | }, | |
11263 | { | |
11264 | /* MOD_0F73_REG_7 */ | |
592d1631 | 11265 | { Bad_Opcode }, |
c0f3af97 L |
11266 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
11267 | }, | |
11268 | { | |
11269 | /* MOD_0FAE_REG_0 */ | |
eacc9c89 | 11270 | { "fxsave", { FXSAVE } }, |
c7b8aa3a | 11271 | { PREFIX_TABLE (PREFIX_0FAE_REG_0) }, |
c0f3af97 L |
11272 | }, |
11273 | { | |
11274 | /* MOD_0FAE_REG_1 */ | |
eacc9c89 | 11275 | { "fxrstor", { FXSAVE } }, |
c7b8aa3a | 11276 | { PREFIX_TABLE (PREFIX_0FAE_REG_1) }, |
c0f3af97 L |
11277 | }, |
11278 | { | |
11279 | /* MOD_0FAE_REG_2 */ | |
11280 | { "ldmxcsr", { Md } }, | |
c7b8aa3a | 11281 | { PREFIX_TABLE (PREFIX_0FAE_REG_2) }, |
c0f3af97 L |
11282 | }, |
11283 | { | |
11284 | /* MOD_0FAE_REG_3 */ | |
11285 | { "stmxcsr", { Md } }, | |
c7b8aa3a | 11286 | { PREFIX_TABLE (PREFIX_0FAE_REG_3) }, |
c0f3af97 L |
11287 | }, |
11288 | { | |
11289 | /* MOD_0FAE_REG_4 */ | |
73bb6729 | 11290 | { "xsave", { FXSAVE } }, |
c0f3af97 L |
11291 | }, |
11292 | { | |
11293 | /* MOD_0FAE_REG_5 */ | |
73bb6729 | 11294 | { "xrstor", { FXSAVE } }, |
c0f3af97 L |
11295 | { RM_TABLE (RM_0FAE_REG_5) }, |
11296 | }, | |
11297 | { | |
11298 | /* MOD_0FAE_REG_6 */ | |
c7b8aa3a | 11299 | { "xsaveopt", { FXSAVE } }, |
c0f3af97 L |
11300 | { RM_TABLE (RM_0FAE_REG_6) }, |
11301 | }, | |
11302 | { | |
11303 | /* MOD_0FAE_REG_7 */ | |
963f3586 | 11304 | { PREFIX_TABLE (PREFIX_0FAE_REG_7) }, |
c0f3af97 L |
11305 | { RM_TABLE (RM_0FAE_REG_7) }, |
11306 | }, | |
11307 | { | |
11308 | /* MOD_0FB2 */ | |
11309 | { "lssS", { Gv, Mp } }, | |
c0f3af97 L |
11310 | }, |
11311 | { | |
11312 | /* MOD_0FB4 */ | |
11313 | { "lfsS", { Gv, Mp } }, | |
c0f3af97 L |
11314 | }, |
11315 | { | |
11316 | /* MOD_0FB5 */ | |
11317 | { "lgsS", { Gv, Mp } }, | |
c0f3af97 | 11318 | }, |
963f3586 IT |
11319 | { |
11320 | /* MOD_0FC7_REG_3 */ | |
11321 | { "xrstors", { FXSAVE } }, | |
11322 | }, | |
11323 | { | |
11324 | /* MOD_0FC7_REG_4 */ | |
11325 | { "xsavec", { FXSAVE } }, | |
11326 | }, | |
11327 | { | |
11328 | /* MOD_0FC7_REG_5 */ | |
11329 | { "xsaves", { FXSAVE } }, | |
11330 | }, | |
c0f3af97 L |
11331 | { |
11332 | /* MOD_0FC7_REG_6 */ | |
11333 | { PREFIX_TABLE (PREFIX_0FC7_REG_6) }, | |
d7d9a9f8 | 11334 | { "rdrand", { Ev } }, |
c0f3af97 L |
11335 | }, |
11336 | { | |
11337 | /* MOD_0FC7_REG_7 */ | |
11338 | { "vmptrst", { Mq } }, | |
e2e1fcde | 11339 | { "rdseed", { Ev } }, |
c0f3af97 L |
11340 | }, |
11341 | { | |
11342 | /* MOD_0FD7 */ | |
592d1631 | 11343 | { Bad_Opcode }, |
c0f3af97 L |
11344 | { "pmovmskb", { Gdq, MS } }, |
11345 | }, | |
11346 | { | |
11347 | /* MOD_0FE7_PREFIX_2 */ | |
11348 | { "movntdq", { Mx, XM } }, | |
c0f3af97 L |
11349 | }, |
11350 | { | |
11351 | /* MOD_0FF0_PREFIX_3 */ | |
11352 | { "lddqu", { XM, M } }, | |
c0f3af97 L |
11353 | }, |
11354 | { | |
11355 | /* MOD_0F382A_PREFIX_2 */ | |
11356 | { "movntdqa", { XM, Mx } }, | |
c0f3af97 L |
11357 | }, |
11358 | { | |
11359 | /* MOD_62_32BIT */ | |
11360 | { "bound{S|}", { Gv, Ma } }, | |
43234a1e | 11361 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
11362 | }, |
11363 | { | |
11364 | /* MOD_C4_32BIT */ | |
11365 | { "lesS", { Gv, Mp } }, | |
11366 | { VEX_C4_TABLE (VEX_0F) }, | |
11367 | }, | |
11368 | { | |
11369 | /* MOD_C5_32BIT */ | |
11370 | { "ldsS", { Gv, Mp } }, | |
11371 | { VEX_C5_TABLE (VEX_0F) }, | |
11372 | }, | |
11373 | { | |
592a252b L |
11374 | /* MOD_VEX_0F12_PREFIX_0 */ |
11375 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, | |
11376 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, | |
c0f3af97 L |
11377 | }, |
11378 | { | |
592a252b L |
11379 | /* MOD_VEX_0F13 */ |
11380 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, | |
c0f3af97 L |
11381 | }, |
11382 | { | |
592a252b L |
11383 | /* MOD_VEX_0F16_PREFIX_0 */ |
11384 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, | |
11385 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, | |
c0f3af97 L |
11386 | }, |
11387 | { | |
592a252b L |
11388 | /* MOD_VEX_0F17 */ |
11389 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, | |
c0f3af97 L |
11390 | }, |
11391 | { | |
592a252b L |
11392 | /* MOD_VEX_0F2B */ |
11393 | { VEX_W_TABLE (VEX_W_0F2B_M_0) }, | |
c0f3af97 L |
11394 | }, |
11395 | { | |
592a252b | 11396 | /* MOD_VEX_0F50 */ |
592d1631 | 11397 | { Bad_Opcode }, |
592a252b | 11398 | { VEX_W_TABLE (VEX_W_0F50_M_0) }, |
c0f3af97 L |
11399 | }, |
11400 | { | |
592a252b | 11401 | /* MOD_VEX_0F71_REG_2 */ |
592d1631 | 11402 | { Bad_Opcode }, |
592a252b | 11403 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, |
b844680a L |
11404 | }, |
11405 | { | |
592a252b | 11406 | /* MOD_VEX_0F71_REG_4 */ |
592d1631 | 11407 | { Bad_Opcode }, |
592a252b | 11408 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, |
b844680a L |
11409 | }, |
11410 | { | |
592a252b | 11411 | /* MOD_VEX_0F71_REG_6 */ |
592d1631 | 11412 | { Bad_Opcode }, |
592a252b | 11413 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, |
b844680a L |
11414 | }, |
11415 | { | |
592a252b | 11416 | /* MOD_VEX_0F72_REG_2 */ |
592d1631 | 11417 | { Bad_Opcode }, |
592a252b | 11418 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, |
b844680a | 11419 | }, |
d8faab4e | 11420 | { |
592a252b | 11421 | /* MOD_VEX_0F72_REG_4 */ |
592d1631 | 11422 | { Bad_Opcode }, |
592a252b | 11423 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, |
d8faab4e L |
11424 | }, |
11425 | { | |
592a252b | 11426 | /* MOD_VEX_0F72_REG_6 */ |
592d1631 | 11427 | { Bad_Opcode }, |
592a252b | 11428 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, |
d8faab4e | 11429 | }, |
876d4bfa | 11430 | { |
592a252b | 11431 | /* MOD_VEX_0F73_REG_2 */ |
592d1631 | 11432 | { Bad_Opcode }, |
592a252b | 11433 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, |
876d4bfa L |
11434 | }, |
11435 | { | |
592a252b | 11436 | /* MOD_VEX_0F73_REG_3 */ |
592d1631 | 11437 | { Bad_Opcode }, |
592a252b | 11438 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, |
475a2301 L |
11439 | }, |
11440 | { | |
592a252b | 11441 | /* MOD_VEX_0F73_REG_6 */ |
592d1631 | 11442 | { Bad_Opcode }, |
592a252b | 11443 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, |
876d4bfa L |
11444 | }, |
11445 | { | |
592a252b | 11446 | /* MOD_VEX_0F73_REG_7 */ |
592d1631 | 11447 | { Bad_Opcode }, |
592a252b | 11448 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, |
876d4bfa L |
11449 | }, |
11450 | { | |
592a252b L |
11451 | /* MOD_VEX_0FAE_REG_2 */ |
11452 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, | |
876d4bfa | 11453 | }, |
bbedc832 | 11454 | { |
592a252b L |
11455 | /* MOD_VEX_0FAE_REG_3 */ |
11456 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, | |
bbedc832 | 11457 | }, |
144c41d9 | 11458 | { |
592a252b | 11459 | /* MOD_VEX_0FD7_PREFIX_2 */ |
592d1631 | 11460 | { Bad_Opcode }, |
6c30d220 | 11461 | { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) }, |
144c41d9 | 11462 | }, |
1afd85e3 | 11463 | { |
592a252b L |
11464 | /* MOD_VEX_0FE7_PREFIX_2 */ |
11465 | { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) }, | |
1afd85e3 L |
11466 | }, |
11467 | { | |
592a252b L |
11468 | /* MOD_VEX_0FF0_PREFIX_3 */ |
11469 | { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) }, | |
92fddf8e | 11470 | }, |
75c135a8 | 11471 | { |
592a252b L |
11472 | /* MOD_VEX_0F381A_PREFIX_2 */ |
11473 | { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, | |
75c135a8 | 11474 | }, |
1afd85e3 | 11475 | { |
592a252b | 11476 | /* MOD_VEX_0F382A_PREFIX_2 */ |
6c30d220 | 11477 | { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) }, |
1afd85e3 | 11478 | }, |
75c135a8 | 11479 | { |
592a252b L |
11480 | /* MOD_VEX_0F382C_PREFIX_2 */ |
11481 | { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, | |
75c135a8 | 11482 | }, |
1afd85e3 | 11483 | { |
592a252b L |
11484 | /* MOD_VEX_0F382D_PREFIX_2 */ |
11485 | { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, | |
1afd85e3 L |
11486 | }, |
11487 | { | |
592a252b L |
11488 | /* MOD_VEX_0F382E_PREFIX_2 */ |
11489 | { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, | |
1afd85e3 L |
11490 | }, |
11491 | { | |
592a252b L |
11492 | /* MOD_VEX_0F382F_PREFIX_2 */ |
11493 | { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, | |
1afd85e3 | 11494 | }, |
6c30d220 L |
11495 | { |
11496 | /* MOD_VEX_0F385A_PREFIX_2 */ | |
11497 | { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, | |
11498 | }, | |
11499 | { | |
11500 | /* MOD_VEX_0F388C_PREFIX_2 */ | |
11501 | { "vpmaskmov%LW", { XM, Vex, Mx } }, | |
11502 | }, | |
11503 | { | |
11504 | /* MOD_VEX_0F388E_PREFIX_2 */ | |
11505 | { "vpmaskmov%LW", { Mx, Vex, XM } }, | |
11506 | }, | |
43234a1e L |
11507 | #define NEED_MOD_TABLE |
11508 | #include "i386-dis-evex.h" | |
11509 | #undef NEED_MOD_TABLE | |
b844680a L |
11510 | }; |
11511 | ||
1ceb70f8 | 11512 | static const struct dis386 rm_table[][8] = { |
42164a71 L |
11513 | { |
11514 | /* RM_C6_REG_7 */ | |
11515 | { "xabort", { Skip_MODRM, Ib } }, | |
11516 | }, | |
11517 | { | |
11518 | /* RM_C7_REG_7 */ | |
11519 | { "xbeginT", { Skip_MODRM, Jv } }, | |
11520 | }, | |
b844680a | 11521 | { |
1ceb70f8 | 11522 | /* RM_0F01_REG_0 */ |
592d1631 | 11523 | { Bad_Opcode }, |
b844680a L |
11524 | { "vmcall", { Skip_MODRM } }, |
11525 | { "vmlaunch", { Skip_MODRM } }, | |
11526 | { "vmresume", { Skip_MODRM } }, | |
11527 | { "vmxoff", { Skip_MODRM } }, | |
b844680a L |
11528 | }, |
11529 | { | |
1ceb70f8 | 11530 | /* RM_0F01_REG_1 */ |
b844680a L |
11531 | { "monitor", { { OP_Monitor, 0 } } }, |
11532 | { "mwait", { { OP_Mwait, 0 } } }, | |
5c111e37 L |
11533 | { "clac", { Skip_MODRM } }, |
11534 | { "stac", { Skip_MODRM } }, | |
2cf200a4 IT |
11535 | { Bad_Opcode }, |
11536 | { Bad_Opcode }, | |
11537 | { Bad_Opcode }, | |
11538 | { "encls", { Skip_MODRM } }, | |
b844680a | 11539 | }, |
475a2301 L |
11540 | { |
11541 | /* RM_0F01_REG_2 */ | |
11542 | { "xgetbv", { Skip_MODRM } }, | |
11543 | { "xsetbv", { Skip_MODRM } }, | |
8729a6f6 L |
11544 | { Bad_Opcode }, |
11545 | { Bad_Opcode }, | |
11546 | { "vmfunc", { Skip_MODRM } }, | |
42164a71 L |
11547 | { "xend", { Skip_MODRM } }, |
11548 | { "xtest", { Skip_MODRM } }, | |
2cf200a4 | 11549 | { "enclu", { Skip_MODRM } }, |
475a2301 | 11550 | }, |
b844680a | 11551 | { |
1ceb70f8 | 11552 | /* RM_0F01_REG_3 */ |
4e7d34a6 L |
11553 | { "vmrun", { Skip_MODRM } }, |
11554 | { "vmmcall", { Skip_MODRM } }, | |
11555 | { "vmload", { Skip_MODRM } }, | |
11556 | { "vmsave", { Skip_MODRM } }, | |
11557 | { "stgi", { Skip_MODRM } }, | |
11558 | { "clgi", { Skip_MODRM } }, | |
11559 | { "skinit", { Skip_MODRM } }, | |
11560 | { "invlpga", { Skip_MODRM } }, | |
11561 | }, | |
11562 | { | |
1ceb70f8 | 11563 | /* RM_0F01_REG_7 */ |
4e7d34a6 L |
11564 | { "swapgs", { Skip_MODRM } }, |
11565 | { "rdtscp", { Skip_MODRM } }, | |
b844680a L |
11566 | }, |
11567 | { | |
1ceb70f8 | 11568 | /* RM_0FAE_REG_5 */ |
4e7d34a6 | 11569 | { "lfence", { Skip_MODRM } }, |
b844680a L |
11570 | }, |
11571 | { | |
1ceb70f8 | 11572 | /* RM_0FAE_REG_6 */ |
4e7d34a6 | 11573 | { "mfence", { Skip_MODRM } }, |
b844680a | 11574 | }, |
bbedc832 | 11575 | { |
1ceb70f8 | 11576 | /* RM_0FAE_REG_7 */ |
4e7d34a6 | 11577 | { "sfence", { Skip_MODRM } }, |
144c41d9 | 11578 | }, |
b844680a L |
11579 | }; |
11580 | ||
c608c12e AM |
11581 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
11582 | ||
f16cd0d5 L |
11583 | /* We use the high bit to indicate different name for the same |
11584 | prefix. */ | |
11585 | #define ADDR16_PREFIX (0x67 | 0x100) | |
11586 | #define ADDR32_PREFIX (0x67 | 0x200) | |
11587 | #define DATA16_PREFIX (0x66 | 0x100) | |
11588 | #define DATA32_PREFIX (0x66 | 0x200) | |
11589 | #define REP_PREFIX (0xf3 | 0x100) | |
42164a71 L |
11590 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
11591 | #define XRELEASE_PREFIX (0xf3 | 0x400) | |
7e8b059b | 11592 | #define BND_PREFIX (0xf2 | 0x400) |
f16cd0d5 L |
11593 | |
11594 | static int | |
26ca5450 | 11595 | ckprefix (void) |
252b5132 | 11596 | { |
f16cd0d5 | 11597 | int newrex, i, length; |
52b15da3 | 11598 | rex = 0; |
c0f3af97 | 11599 | rex_ignored = 0; |
252b5132 | 11600 | prefixes = 0; |
7d421014 | 11601 | used_prefixes = 0; |
52b15da3 | 11602 | rex_used = 0; |
f16cd0d5 L |
11603 | last_lock_prefix = -1; |
11604 | last_repz_prefix = -1; | |
11605 | last_repnz_prefix = -1; | |
11606 | last_data_prefix = -1; | |
11607 | last_addr_prefix = -1; | |
11608 | last_rex_prefix = -1; | |
11609 | last_seg_prefix = -1; | |
f310f33d L |
11610 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
11611 | all_prefixes[i] = 0; | |
11612 | i = 0; | |
f16cd0d5 L |
11613 | length = 0; |
11614 | /* The maximum instruction length is 15bytes. */ | |
11615 | while (length < MAX_CODE_LENGTH - 1) | |
252b5132 RH |
11616 | { |
11617 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 11618 | newrex = 0; |
252b5132 RH |
11619 | switch (*codep) |
11620 | { | |
52b15da3 JH |
11621 | /* REX prefixes family. */ |
11622 | case 0x40: | |
11623 | case 0x41: | |
11624 | case 0x42: | |
11625 | case 0x43: | |
11626 | case 0x44: | |
11627 | case 0x45: | |
11628 | case 0x46: | |
11629 | case 0x47: | |
11630 | case 0x48: | |
11631 | case 0x49: | |
11632 | case 0x4a: | |
11633 | case 0x4b: | |
11634 | case 0x4c: | |
11635 | case 0x4d: | |
11636 | case 0x4e: | |
11637 | case 0x4f: | |
f16cd0d5 L |
11638 | if (address_mode == mode_64bit) |
11639 | newrex = *codep; | |
11640 | else | |
11641 | return 1; | |
11642 | last_rex_prefix = i; | |
52b15da3 | 11643 | break; |
252b5132 RH |
11644 | case 0xf3: |
11645 | prefixes |= PREFIX_REPZ; | |
f16cd0d5 | 11646 | last_repz_prefix = i; |
252b5132 RH |
11647 | break; |
11648 | case 0xf2: | |
11649 | prefixes |= PREFIX_REPNZ; | |
f16cd0d5 | 11650 | last_repnz_prefix = i; |
252b5132 RH |
11651 | break; |
11652 | case 0xf0: | |
11653 | prefixes |= PREFIX_LOCK; | |
f16cd0d5 | 11654 | last_lock_prefix = i; |
252b5132 RH |
11655 | break; |
11656 | case 0x2e: | |
11657 | prefixes |= PREFIX_CS; | |
f16cd0d5 | 11658 | last_seg_prefix = i; |
252b5132 RH |
11659 | break; |
11660 | case 0x36: | |
11661 | prefixes |= PREFIX_SS; | |
f16cd0d5 | 11662 | last_seg_prefix = i; |
252b5132 RH |
11663 | break; |
11664 | case 0x3e: | |
11665 | prefixes |= PREFIX_DS; | |
f16cd0d5 | 11666 | last_seg_prefix = i; |
252b5132 RH |
11667 | break; |
11668 | case 0x26: | |
11669 | prefixes |= PREFIX_ES; | |
f16cd0d5 | 11670 | last_seg_prefix = i; |
252b5132 RH |
11671 | break; |
11672 | case 0x64: | |
11673 | prefixes |= PREFIX_FS; | |
f16cd0d5 | 11674 | last_seg_prefix = i; |
252b5132 RH |
11675 | break; |
11676 | case 0x65: | |
11677 | prefixes |= PREFIX_GS; | |
f16cd0d5 | 11678 | last_seg_prefix = i; |
252b5132 RH |
11679 | break; |
11680 | case 0x66: | |
11681 | prefixes |= PREFIX_DATA; | |
f16cd0d5 | 11682 | last_data_prefix = i; |
252b5132 RH |
11683 | break; |
11684 | case 0x67: | |
11685 | prefixes |= PREFIX_ADDR; | |
f16cd0d5 | 11686 | last_addr_prefix = i; |
252b5132 | 11687 | break; |
5076851f | 11688 | case FWAIT_OPCODE: |
252b5132 RH |
11689 | /* fwait is really an instruction. If there are prefixes |
11690 | before the fwait, they belong to the fwait, *not* to the | |
11691 | following instruction. */ | |
3e7d61b2 | 11692 | if (prefixes || rex) |
252b5132 RH |
11693 | { |
11694 | prefixes |= PREFIX_FWAIT; | |
11695 | codep++; | |
6c067bbb RM |
11696 | /* This ensures that the previous REX prefixes are noticed |
11697 | as unused prefixes, as in the return case below. */ | |
11698 | rex_used = rex; | |
f16cd0d5 | 11699 | return 1; |
252b5132 RH |
11700 | } |
11701 | prefixes = PREFIX_FWAIT; | |
11702 | break; | |
11703 | default: | |
f16cd0d5 | 11704 | return 1; |
252b5132 | 11705 | } |
52b15da3 JH |
11706 | /* Rex is ignored when followed by another prefix. */ |
11707 | if (rex) | |
11708 | { | |
3e7d61b2 | 11709 | rex_used = rex; |
f16cd0d5 | 11710 | return 1; |
52b15da3 | 11711 | } |
f16cd0d5 L |
11712 | if (*codep != FWAIT_OPCODE) |
11713 | all_prefixes[i++] = *codep; | |
52b15da3 | 11714 | rex = newrex; |
252b5132 | 11715 | codep++; |
f16cd0d5 L |
11716 | length++; |
11717 | } | |
11718 | return 0; | |
11719 | } | |
11720 | ||
11721 | static int | |
11722 | seg_prefix (int pref) | |
11723 | { | |
11724 | switch (pref) | |
11725 | { | |
11726 | case 0x2e: | |
11727 | return PREFIX_CS; | |
11728 | case 0x36: | |
11729 | return PREFIX_SS; | |
11730 | case 0x3e: | |
11731 | return PREFIX_DS; | |
11732 | case 0x26: | |
11733 | return PREFIX_ES; | |
11734 | case 0x64: | |
11735 | return PREFIX_FS; | |
11736 | case 0x65: | |
11737 | return PREFIX_GS; | |
11738 | default: | |
11739 | return 0; | |
252b5132 RH |
11740 | } |
11741 | } | |
11742 | ||
7d421014 ILT |
11743 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
11744 | prefix byte. */ | |
11745 | ||
11746 | static const char * | |
26ca5450 | 11747 | prefix_name (int pref, int sizeflag) |
7d421014 | 11748 | { |
0003779b L |
11749 | static const char *rexes [16] = |
11750 | { | |
11751 | "rex", /* 0x40 */ | |
11752 | "rex.B", /* 0x41 */ | |
11753 | "rex.X", /* 0x42 */ | |
11754 | "rex.XB", /* 0x43 */ | |
11755 | "rex.R", /* 0x44 */ | |
11756 | "rex.RB", /* 0x45 */ | |
11757 | "rex.RX", /* 0x46 */ | |
11758 | "rex.RXB", /* 0x47 */ | |
11759 | "rex.W", /* 0x48 */ | |
11760 | "rex.WB", /* 0x49 */ | |
11761 | "rex.WX", /* 0x4a */ | |
11762 | "rex.WXB", /* 0x4b */ | |
11763 | "rex.WR", /* 0x4c */ | |
11764 | "rex.WRB", /* 0x4d */ | |
11765 | "rex.WRX", /* 0x4e */ | |
11766 | "rex.WRXB", /* 0x4f */ | |
11767 | }; | |
11768 | ||
7d421014 ILT |
11769 | switch (pref) |
11770 | { | |
52b15da3 JH |
11771 | /* REX prefixes family. */ |
11772 | case 0x40: | |
52b15da3 | 11773 | case 0x41: |
52b15da3 | 11774 | case 0x42: |
52b15da3 | 11775 | case 0x43: |
52b15da3 | 11776 | case 0x44: |
52b15da3 | 11777 | case 0x45: |
52b15da3 | 11778 | case 0x46: |
52b15da3 | 11779 | case 0x47: |
52b15da3 | 11780 | case 0x48: |
52b15da3 | 11781 | case 0x49: |
52b15da3 | 11782 | case 0x4a: |
52b15da3 | 11783 | case 0x4b: |
52b15da3 | 11784 | case 0x4c: |
52b15da3 | 11785 | case 0x4d: |
52b15da3 | 11786 | case 0x4e: |
52b15da3 | 11787 | case 0x4f: |
0003779b | 11788 | return rexes [pref - 0x40]; |
7d421014 ILT |
11789 | case 0xf3: |
11790 | return "repz"; | |
11791 | case 0xf2: | |
11792 | return "repnz"; | |
11793 | case 0xf0: | |
11794 | return "lock"; | |
11795 | case 0x2e: | |
11796 | return "cs"; | |
11797 | case 0x36: | |
11798 | return "ss"; | |
11799 | case 0x3e: | |
11800 | return "ds"; | |
11801 | case 0x26: | |
11802 | return "es"; | |
11803 | case 0x64: | |
11804 | return "fs"; | |
11805 | case 0x65: | |
11806 | return "gs"; | |
11807 | case 0x66: | |
11808 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
11809 | case 0x67: | |
cb712a9e | 11810 | if (address_mode == mode_64bit) |
db6eb5be | 11811 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 11812 | else |
2888cb7a | 11813 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
11814 | case FWAIT_OPCODE: |
11815 | return "fwait"; | |
f16cd0d5 L |
11816 | case ADDR16_PREFIX: |
11817 | return "addr16"; | |
11818 | case ADDR32_PREFIX: | |
11819 | return "addr32"; | |
11820 | case DATA16_PREFIX: | |
11821 | return "data16"; | |
11822 | case DATA32_PREFIX: | |
11823 | return "data32"; | |
11824 | case REP_PREFIX: | |
11825 | return "rep"; | |
42164a71 L |
11826 | case XACQUIRE_PREFIX: |
11827 | return "xacquire"; | |
11828 | case XRELEASE_PREFIX: | |
11829 | return "xrelease"; | |
7e8b059b L |
11830 | case BND_PREFIX: |
11831 | return "bnd"; | |
7d421014 ILT |
11832 | default: |
11833 | return NULL; | |
11834 | } | |
11835 | } | |
11836 | ||
ce518a5f L |
11837 | static char op_out[MAX_OPERANDS][100]; |
11838 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 11839 | static int two_source_ops; |
ce518a5f L |
11840 | static bfd_vma op_address[MAX_OPERANDS]; |
11841 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 11842 | static bfd_vma start_pc; |
ce518a5f | 11843 | |
252b5132 RH |
11844 | /* |
11845 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
11846 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
11847 | * section of the "Virtual 8086 Mode" chapter.) | |
11848 | * 'pc' should be the address of this instruction, it will | |
11849 | * be used to print the target address if this is a relative jump or call | |
11850 | * The function returns the length of this instruction in bytes. | |
11851 | */ | |
11852 | ||
252b5132 | 11853 | static char intel_syntax; |
9d141669 | 11854 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
11855 | static char open_char; |
11856 | static char close_char; | |
11857 | static char separator_char; | |
11858 | static char scale_char; | |
11859 | ||
e396998b AM |
11860 | /* Here for backwards compatibility. When gdb stops using |
11861 | print_insn_i386_att and print_insn_i386_intel these functions can | |
11862 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 11863 | int |
26ca5450 | 11864 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
11865 | { |
11866 | intel_syntax = 0; | |
e396998b AM |
11867 | |
11868 | return print_insn (pc, info); | |
252b5132 RH |
11869 | } |
11870 | ||
11871 | int | |
26ca5450 | 11872 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
11873 | { |
11874 | intel_syntax = 1; | |
e396998b AM |
11875 | |
11876 | return print_insn (pc, info); | |
252b5132 RH |
11877 | } |
11878 | ||
e396998b | 11879 | int |
26ca5450 | 11880 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
11881 | { |
11882 | intel_syntax = -1; | |
11883 | ||
11884 | return print_insn (pc, info); | |
11885 | } | |
11886 | ||
f59a29b9 L |
11887 | void |
11888 | print_i386_disassembler_options (FILE *stream) | |
11889 | { | |
11890 | fprintf (stream, _("\n\ | |
11891 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
11892 | with the -M switch (multiple options should be separated by commas):\n")); | |
11893 | ||
11894 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
11895 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
11896 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
11897 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
11898 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
11899 | fprintf (stream, _(" att-mnemonic\n" |
11900 | " Display instruction in AT&T mnemonic\n")); | |
11901 | fprintf (stream, _(" intel-mnemonic\n" | |
11902 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
11903 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
11904 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
11905 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
11906 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
11907 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
11908 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
11909 | } | |
11910 | ||
592d1631 L |
11911 | /* Bad opcode. */ |
11912 | static const struct dis386 bad_opcode = { "(bad)", { XX } }; | |
11913 | ||
b844680a L |
11914 | /* Get a pointer to struct dis386 with a valid name. */ |
11915 | ||
11916 | static const struct dis386 * | |
8bb15339 | 11917 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a | 11918 | { |
91d6fa6a | 11919 | int vindex, vex_table_index; |
b844680a L |
11920 | |
11921 | if (dp->name != NULL) | |
11922 | return dp; | |
11923 | ||
11924 | switch (dp->op[0].bytemode) | |
11925 | { | |
1ceb70f8 L |
11926 | case USE_REG_TABLE: |
11927 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
11928 | break; | |
11929 | ||
11930 | case USE_MOD_TABLE: | |
91d6fa6a NC |
11931 | vindex = modrm.mod == 0x3 ? 1 : 0; |
11932 | dp = &mod_table[dp->op[1].bytemode][vindex]; | |
1ceb70f8 L |
11933 | break; |
11934 | ||
11935 | case USE_RM_TABLE: | |
11936 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
11937 | break; |
11938 | ||
4e7d34a6 | 11939 | case USE_PREFIX_TABLE: |
c0f3af97 | 11940 | if (need_vex) |
b844680a | 11941 | { |
c0f3af97 L |
11942 | /* The prefix in VEX is implicit. */ |
11943 | switch (vex.prefix) | |
11944 | { | |
11945 | case 0: | |
91d6fa6a | 11946 | vindex = 0; |
c0f3af97 L |
11947 | break; |
11948 | case REPE_PREFIX_OPCODE: | |
91d6fa6a | 11949 | vindex = 1; |
c0f3af97 L |
11950 | break; |
11951 | case DATA_PREFIX_OPCODE: | |
91d6fa6a | 11952 | vindex = 2; |
c0f3af97 L |
11953 | break; |
11954 | case REPNE_PREFIX_OPCODE: | |
91d6fa6a | 11955 | vindex = 3; |
c0f3af97 L |
11956 | break; |
11957 | default: | |
11958 | abort (); | |
11959 | break; | |
11960 | } | |
b844680a | 11961 | } |
7bb15c6f | 11962 | else |
b844680a | 11963 | { |
91d6fa6a | 11964 | vindex = 0; |
c0f3af97 L |
11965 | used_prefixes |= (prefixes & PREFIX_REPZ); |
11966 | if (prefixes & PREFIX_REPZ) | |
b844680a | 11967 | { |
91d6fa6a | 11968 | vindex = 1; |
f16cd0d5 | 11969 | all_prefixes[last_repz_prefix] = 0; |
b844680a L |
11970 | } |
11971 | else | |
11972 | { | |
c0f3af97 L |
11973 | /* We should check PREFIX_REPNZ and PREFIX_REPZ before |
11974 | PREFIX_DATA. */ | |
11975 | used_prefixes |= (prefixes & PREFIX_REPNZ); | |
11976 | if (prefixes & PREFIX_REPNZ) | |
11977 | { | |
91d6fa6a | 11978 | vindex = 3; |
f16cd0d5 | 11979 | all_prefixes[last_repnz_prefix] = 0; |
c0f3af97 L |
11980 | } |
11981 | else | |
b844680a | 11982 | { |
c0f3af97 L |
11983 | used_prefixes |= (prefixes & PREFIX_DATA); |
11984 | if (prefixes & PREFIX_DATA) | |
11985 | { | |
91d6fa6a | 11986 | vindex = 2; |
f16cd0d5 | 11987 | all_prefixes[last_data_prefix] = 0; |
c0f3af97 | 11988 | } |
b844680a L |
11989 | } |
11990 | } | |
11991 | } | |
91d6fa6a | 11992 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
b844680a L |
11993 | break; |
11994 | ||
4e7d34a6 | 11995 | case USE_X86_64_TABLE: |
91d6fa6a NC |
11996 | vindex = address_mode == mode_64bit ? 1 : 0; |
11997 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; | |
b844680a L |
11998 | break; |
11999 | ||
4e7d34a6 | 12000 | case USE_3BYTE_TABLE: |
8bb15339 | 12001 | FETCH_DATA (info, codep + 2); |
91d6fa6a NC |
12002 | vindex = *codep++; |
12003 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; | |
8bb15339 L |
12004 | modrm.mod = (*codep >> 6) & 3; |
12005 | modrm.reg = (*codep >> 3) & 7; | |
12006 | modrm.rm = *codep & 7; | |
12007 | break; | |
12008 | ||
c0f3af97 L |
12009 | case USE_VEX_LEN_TABLE: |
12010 | if (!need_vex) | |
12011 | abort (); | |
12012 | ||
12013 | switch (vex.length) | |
12014 | { | |
12015 | case 128: | |
91d6fa6a | 12016 | vindex = 0; |
c0f3af97 L |
12017 | break; |
12018 | case 256: | |
91d6fa6a | 12019 | vindex = 1; |
c0f3af97 L |
12020 | break; |
12021 | default: | |
12022 | abort (); | |
12023 | break; | |
12024 | } | |
12025 | ||
91d6fa6a | 12026 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
c0f3af97 L |
12027 | break; |
12028 | ||
f88c9eb0 SP |
12029 | case USE_XOP_8F_TABLE: |
12030 | FETCH_DATA (info, codep + 3); | |
12031 | /* All bits in the REX prefix are ignored. */ | |
12032 | rex_ignored = rex; | |
12033 | rex = ~(*codep >> 5) & 0x7; | |
12034 | ||
12035 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ | |
12036 | switch ((*codep & 0x1f)) | |
12037 | { | |
12038 | default: | |
f07af43e L |
12039 | dp = &bad_opcode; |
12040 | return dp; | |
5dd85c99 SP |
12041 | case 0x8: |
12042 | vex_table_index = XOP_08; | |
12043 | break; | |
f88c9eb0 SP |
12044 | case 0x9: |
12045 | vex_table_index = XOP_09; | |
12046 | break; | |
12047 | case 0xa: | |
12048 | vex_table_index = XOP_0A; | |
12049 | break; | |
12050 | } | |
12051 | codep++; | |
12052 | vex.w = *codep & 0x80; | |
12053 | if (vex.w && address_mode == mode_64bit) | |
12054 | rex |= REX_W; | |
12055 | ||
12056 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
12057 | if (address_mode != mode_64bit | |
12058 | && vex.register_specifier > 0x7) | |
f07af43e L |
12059 | { |
12060 | dp = &bad_opcode; | |
12061 | return dp; | |
12062 | } | |
f88c9eb0 SP |
12063 | |
12064 | vex.length = (*codep & 0x4) ? 256 : 128; | |
12065 | switch ((*codep & 0x3)) | |
12066 | { | |
12067 | case 0: | |
12068 | vex.prefix = 0; | |
12069 | break; | |
12070 | case 1: | |
12071 | vex.prefix = DATA_PREFIX_OPCODE; | |
12072 | break; | |
12073 | case 2: | |
12074 | vex.prefix = REPE_PREFIX_OPCODE; | |
12075 | break; | |
12076 | case 3: | |
12077 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12078 | break; | |
12079 | } | |
12080 | need_vex = 1; | |
12081 | need_vex_reg = 1; | |
12082 | codep++; | |
91d6fa6a NC |
12083 | vindex = *codep++; |
12084 | dp = &xop_table[vex_table_index][vindex]; | |
c48244a5 SP |
12085 | |
12086 | FETCH_DATA (info, codep + 1); | |
12087 | modrm.mod = (*codep >> 6) & 3; | |
12088 | modrm.reg = (*codep >> 3) & 7; | |
12089 | modrm.rm = *codep & 7; | |
f88c9eb0 SP |
12090 | break; |
12091 | ||
c0f3af97 | 12092 | case USE_VEX_C4_TABLE: |
43234a1e | 12093 | /* VEX prefix. */ |
c0f3af97 L |
12094 | FETCH_DATA (info, codep + 3); |
12095 | /* All bits in the REX prefix are ignored. */ | |
12096 | rex_ignored = rex; | |
12097 | rex = ~(*codep >> 5) & 0x7; | |
12098 | switch ((*codep & 0x1f)) | |
12099 | { | |
12100 | default: | |
f07af43e L |
12101 | dp = &bad_opcode; |
12102 | return dp; | |
c0f3af97 | 12103 | case 0x1: |
f88c9eb0 | 12104 | vex_table_index = VEX_0F; |
c0f3af97 L |
12105 | break; |
12106 | case 0x2: | |
f88c9eb0 | 12107 | vex_table_index = VEX_0F38; |
c0f3af97 L |
12108 | break; |
12109 | case 0x3: | |
f88c9eb0 | 12110 | vex_table_index = VEX_0F3A; |
c0f3af97 L |
12111 | break; |
12112 | } | |
12113 | codep++; | |
12114 | vex.w = *codep & 0x80; | |
12115 | if (vex.w && address_mode == mode_64bit) | |
12116 | rex |= REX_W; | |
12117 | ||
12118 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
12119 | if (address_mode != mode_64bit | |
12120 | && vex.register_specifier > 0x7) | |
f07af43e L |
12121 | { |
12122 | dp = &bad_opcode; | |
12123 | return dp; | |
12124 | } | |
c0f3af97 L |
12125 | |
12126 | vex.length = (*codep & 0x4) ? 256 : 128; | |
12127 | switch ((*codep & 0x3)) | |
12128 | { | |
12129 | case 0: | |
12130 | vex.prefix = 0; | |
12131 | break; | |
12132 | case 1: | |
12133 | vex.prefix = DATA_PREFIX_OPCODE; | |
12134 | break; | |
12135 | case 2: | |
12136 | vex.prefix = REPE_PREFIX_OPCODE; | |
12137 | break; | |
12138 | case 3: | |
12139 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12140 | break; | |
12141 | } | |
12142 | need_vex = 1; | |
12143 | need_vex_reg = 1; | |
12144 | codep++; | |
91d6fa6a NC |
12145 | vindex = *codep++; |
12146 | dp = &vex_table[vex_table_index][vindex]; | |
c0f3af97 | 12147 | /* There is no MODRM byte for VEX [82|77]. */ |
91d6fa6a | 12148 | if (vindex != 0x77 && vindex != 0x82) |
c0f3af97 L |
12149 | { |
12150 | FETCH_DATA (info, codep + 1); | |
12151 | modrm.mod = (*codep >> 6) & 3; | |
12152 | modrm.reg = (*codep >> 3) & 7; | |
12153 | modrm.rm = *codep & 7; | |
12154 | } | |
12155 | break; | |
12156 | ||
12157 | case USE_VEX_C5_TABLE: | |
43234a1e | 12158 | /* VEX prefix. */ |
c0f3af97 L |
12159 | FETCH_DATA (info, codep + 2); |
12160 | /* All bits in the REX prefix are ignored. */ | |
12161 | rex_ignored = rex; | |
12162 | rex = (*codep & 0x80) ? 0 : REX_R; | |
12163 | ||
12164 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
12165 | if (address_mode != mode_64bit | |
12166 | && vex.register_specifier > 0x7) | |
f07af43e L |
12167 | { |
12168 | dp = &bad_opcode; | |
12169 | return dp; | |
12170 | } | |
c0f3af97 | 12171 | |
759a05ce L |
12172 | vex.w = 0; |
12173 | ||
c0f3af97 L |
12174 | vex.length = (*codep & 0x4) ? 256 : 128; |
12175 | switch ((*codep & 0x3)) | |
12176 | { | |
12177 | case 0: | |
12178 | vex.prefix = 0; | |
12179 | break; | |
12180 | case 1: | |
12181 | vex.prefix = DATA_PREFIX_OPCODE; | |
12182 | break; | |
12183 | case 2: | |
12184 | vex.prefix = REPE_PREFIX_OPCODE; | |
12185 | break; | |
12186 | case 3: | |
12187 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12188 | break; | |
12189 | } | |
12190 | need_vex = 1; | |
12191 | need_vex_reg = 1; | |
12192 | codep++; | |
91d6fa6a NC |
12193 | vindex = *codep++; |
12194 | dp = &vex_table[dp->op[1].bytemode][vindex]; | |
c0f3af97 | 12195 | /* There is no MODRM byte for VEX [82|77]. */ |
91d6fa6a | 12196 | if (vindex != 0x77 && vindex != 0x82) |
c0f3af97 L |
12197 | { |
12198 | FETCH_DATA (info, codep + 1); | |
12199 | modrm.mod = (*codep >> 6) & 3; | |
12200 | modrm.reg = (*codep >> 3) & 7; | |
12201 | modrm.rm = *codep & 7; | |
12202 | } | |
12203 | break; | |
12204 | ||
9e30b8e0 L |
12205 | case USE_VEX_W_TABLE: |
12206 | if (!need_vex) | |
12207 | abort (); | |
12208 | ||
12209 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; | |
12210 | break; | |
12211 | ||
43234a1e L |
12212 | case USE_EVEX_TABLE: |
12213 | two_source_ops = 0; | |
12214 | /* EVEX prefix. */ | |
12215 | vex.evex = 1; | |
12216 | FETCH_DATA (info, codep + 4); | |
12217 | /* All bits in the REX prefix are ignored. */ | |
12218 | rex_ignored = rex; | |
12219 | /* The first byte after 0x62. */ | |
12220 | rex = ~(*codep >> 5) & 0x7; | |
12221 | vex.r = *codep & 0x10; | |
12222 | switch ((*codep & 0xf)) | |
12223 | { | |
12224 | default: | |
12225 | return &bad_opcode; | |
12226 | case 0x1: | |
12227 | vex_table_index = EVEX_0F; | |
12228 | break; | |
12229 | case 0x2: | |
12230 | vex_table_index = EVEX_0F38; | |
12231 | break; | |
12232 | case 0x3: | |
12233 | vex_table_index = EVEX_0F3A; | |
12234 | break; | |
12235 | } | |
12236 | ||
12237 | /* The second byte after 0x62. */ | |
12238 | codep++; | |
12239 | vex.w = *codep & 0x80; | |
12240 | if (vex.w && address_mode == mode_64bit) | |
12241 | rex |= REX_W; | |
12242 | ||
12243 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
12244 | if (address_mode != mode_64bit) | |
12245 | { | |
12246 | /* In 16/32-bit mode silently ignore following bits. */ | |
12247 | rex &= ~REX_B; | |
12248 | vex.r = 1; | |
12249 | vex.v = 1; | |
12250 | vex.register_specifier &= 0x7; | |
12251 | } | |
12252 | ||
12253 | /* The U bit. */ | |
12254 | if (!(*codep & 0x4)) | |
12255 | return &bad_opcode; | |
12256 | ||
12257 | switch ((*codep & 0x3)) | |
12258 | { | |
12259 | case 0: | |
12260 | vex.prefix = 0; | |
12261 | break; | |
12262 | case 1: | |
12263 | vex.prefix = DATA_PREFIX_OPCODE; | |
12264 | break; | |
12265 | case 2: | |
12266 | vex.prefix = REPE_PREFIX_OPCODE; | |
12267 | break; | |
12268 | case 3: | |
12269 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12270 | break; | |
12271 | } | |
12272 | ||
12273 | /* The third byte after 0x62. */ | |
12274 | codep++; | |
12275 | ||
12276 | /* Remember the static rounding bits. */ | |
12277 | vex.ll = (*codep >> 5) & 3; | |
12278 | vex.b = (*codep & 0x10) != 0; | |
12279 | ||
12280 | vex.v = *codep & 0x8; | |
12281 | vex.mask_register_specifier = *codep & 0x7; | |
12282 | vex.zeroing = *codep & 0x80; | |
12283 | ||
12284 | need_vex = 1; | |
12285 | need_vex_reg = 1; | |
12286 | codep++; | |
12287 | vindex = *codep++; | |
12288 | dp = &evex_table[vex_table_index][vindex]; | |
12289 | FETCH_DATA (info, codep + 1); | |
12290 | modrm.mod = (*codep >> 6) & 3; | |
12291 | modrm.reg = (*codep >> 3) & 7; | |
12292 | modrm.rm = *codep & 7; | |
12293 | ||
12294 | /* Set vector length. */ | |
12295 | if (modrm.mod == 3 && vex.b) | |
12296 | vex.length = 512; | |
12297 | else | |
12298 | { | |
12299 | switch (vex.ll) | |
12300 | { | |
12301 | case 0x0: | |
12302 | vex.length = 128; | |
12303 | break; | |
12304 | case 0x1: | |
12305 | vex.length = 256; | |
12306 | break; | |
12307 | case 0x2: | |
12308 | vex.length = 512; | |
12309 | break; | |
12310 | default: | |
12311 | return &bad_opcode; | |
12312 | } | |
12313 | } | |
12314 | break; | |
12315 | ||
592d1631 L |
12316 | case 0: |
12317 | dp = &bad_opcode; | |
12318 | break; | |
12319 | ||
b844680a | 12320 | default: |
d34b5006 | 12321 | abort (); |
b844680a L |
12322 | } |
12323 | ||
12324 | if (dp->name != NULL) | |
12325 | return dp; | |
12326 | else | |
8bb15339 | 12327 | return get_valid_dis386 (dp, info); |
b844680a L |
12328 | } |
12329 | ||
dfc8cf43 | 12330 | static void |
55cf16e1 | 12331 | get_sib (disassemble_info *info, int sizeflag) |
dfc8cf43 L |
12332 | { |
12333 | /* If modrm.mod == 3, operand must be register. */ | |
12334 | if (need_modrm | |
55cf16e1 | 12335 | && ((sizeflag & AFLAG) || address_mode == mode_64bit) |
dfc8cf43 L |
12336 | && modrm.mod != 3 |
12337 | && modrm.rm == 4) | |
12338 | { | |
12339 | FETCH_DATA (info, codep + 2); | |
12340 | sib.index = (codep [1] >> 3) & 7; | |
12341 | sib.scale = (codep [1] >> 6) & 3; | |
12342 | sib.base = codep [1] & 7; | |
12343 | } | |
12344 | } | |
12345 | ||
e396998b | 12346 | static int |
26ca5450 | 12347 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 12348 | { |
2da11e11 | 12349 | const struct dis386 *dp; |
252b5132 | 12350 | int i; |
ce518a5f | 12351 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 12352 | int needcomma; |
e396998b AM |
12353 | int sizeflag; |
12354 | const char *p; | |
252b5132 | 12355 | struct dis_private priv; |
f16cd0d5 L |
12356 | int prefix_length; |
12357 | int default_prefixes; | |
252b5132 | 12358 | |
d7921315 L |
12359 | priv.orig_sizeflag = AFLAG | DFLAG; |
12360 | if ((info->mach & bfd_mach_i386_i386) != 0) | |
cb712a9e | 12361 | address_mode = mode_32bit; |
2da11e11 | 12362 | else if (info->mach == bfd_mach_i386_i8086) |
d7921315 L |
12363 | { |
12364 | address_mode = mode_16bit; | |
12365 | priv.orig_sizeflag = 0; | |
12366 | } | |
2da11e11 | 12367 | else |
d7921315 L |
12368 | address_mode = mode_64bit; |
12369 | ||
12370 | if (intel_syntax == (char) -1) | |
12371 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; | |
e396998b AM |
12372 | |
12373 | for (p = info->disassembler_options; p != NULL; ) | |
12374 | { | |
0112cd26 | 12375 | if (CONST_STRNEQ (p, "x86-64")) |
e396998b | 12376 | { |
cb712a9e | 12377 | address_mode = mode_64bit; |
e396998b AM |
12378 | priv.orig_sizeflag = AFLAG | DFLAG; |
12379 | } | |
0112cd26 | 12380 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 12381 | { |
cb712a9e | 12382 | address_mode = mode_32bit; |
e396998b AM |
12383 | priv.orig_sizeflag = AFLAG | DFLAG; |
12384 | } | |
0112cd26 | 12385 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 12386 | { |
cb712a9e | 12387 | address_mode = mode_16bit; |
e396998b AM |
12388 | priv.orig_sizeflag = 0; |
12389 | } | |
0112cd26 | 12390 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
12391 | { |
12392 | intel_syntax = 1; | |
9d141669 L |
12393 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
12394 | intel_mnemonic = 1; | |
e396998b | 12395 | } |
0112cd26 | 12396 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
12397 | { |
12398 | intel_syntax = 0; | |
9d141669 L |
12399 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
12400 | intel_mnemonic = 0; | |
e396998b | 12401 | } |
0112cd26 | 12402 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 12403 | { |
f59a29b9 L |
12404 | if (address_mode == mode_64bit) |
12405 | { | |
12406 | if (p[4] == '3' && p[5] == '2') | |
12407 | priv.orig_sizeflag &= ~AFLAG; | |
12408 | else if (p[4] == '6' && p[5] == '4') | |
12409 | priv.orig_sizeflag |= AFLAG; | |
12410 | } | |
12411 | else | |
12412 | { | |
12413 | if (p[4] == '1' && p[5] == '6') | |
12414 | priv.orig_sizeflag &= ~AFLAG; | |
12415 | else if (p[4] == '3' && p[5] == '2') | |
12416 | priv.orig_sizeflag |= AFLAG; | |
12417 | } | |
e396998b | 12418 | } |
0112cd26 | 12419 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
12420 | { |
12421 | if (p[4] == '1' && p[5] == '6') | |
12422 | priv.orig_sizeflag &= ~DFLAG; | |
12423 | else if (p[4] == '3' && p[5] == '2') | |
12424 | priv.orig_sizeflag |= DFLAG; | |
12425 | } | |
0112cd26 | 12426 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
12427 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
12428 | ||
12429 | p = strchr (p, ','); | |
12430 | if (p != NULL) | |
12431 | p++; | |
12432 | } | |
12433 | ||
12434 | if (intel_syntax) | |
12435 | { | |
12436 | names64 = intel_names64; | |
12437 | names32 = intel_names32; | |
12438 | names16 = intel_names16; | |
12439 | names8 = intel_names8; | |
12440 | names8rex = intel_names8rex; | |
12441 | names_seg = intel_names_seg; | |
b9733481 | 12442 | names_mm = intel_names_mm; |
7e8b059b | 12443 | names_bnd = intel_names_bnd; |
b9733481 L |
12444 | names_xmm = intel_names_xmm; |
12445 | names_ymm = intel_names_ymm; | |
43234a1e | 12446 | names_zmm = intel_names_zmm; |
db51cc60 L |
12447 | index64 = intel_index64; |
12448 | index32 = intel_index32; | |
43234a1e | 12449 | names_mask = intel_names_mask; |
e396998b AM |
12450 | index16 = intel_index16; |
12451 | open_char = '['; | |
12452 | close_char = ']'; | |
12453 | separator_char = '+'; | |
12454 | scale_char = '*'; | |
12455 | } | |
12456 | else | |
12457 | { | |
12458 | names64 = att_names64; | |
12459 | names32 = att_names32; | |
12460 | names16 = att_names16; | |
12461 | names8 = att_names8; | |
12462 | names8rex = att_names8rex; | |
12463 | names_seg = att_names_seg; | |
b9733481 | 12464 | names_mm = att_names_mm; |
7e8b059b | 12465 | names_bnd = att_names_bnd; |
b9733481 L |
12466 | names_xmm = att_names_xmm; |
12467 | names_ymm = att_names_ymm; | |
43234a1e | 12468 | names_zmm = att_names_zmm; |
db51cc60 L |
12469 | index64 = att_index64; |
12470 | index32 = att_index32; | |
43234a1e | 12471 | names_mask = att_names_mask; |
e396998b AM |
12472 | index16 = att_index16; |
12473 | open_char = '('; | |
12474 | close_char = ')'; | |
12475 | separator_char = ','; | |
12476 | scale_char = ','; | |
12477 | } | |
2da11e11 | 12478 | |
4fe53c98 | 12479 | /* The output looks better if we put 7 bytes on a line, since that |
8a9036a4 L |
12480 | puts most long word instructions on a single line. Use 8 bytes |
12481 | for Intel L1OM. */ | |
d7921315 | 12482 | if ((info->mach & bfd_mach_l1om) != 0) |
8a9036a4 L |
12483 | info->bytes_per_line = 8; |
12484 | else | |
12485 | info->bytes_per_line = 7; | |
252b5132 | 12486 | |
26ca5450 | 12487 | info->private_data = &priv; |
252b5132 RH |
12488 | priv.max_fetched = priv.the_buffer; |
12489 | priv.insn_start = pc; | |
252b5132 RH |
12490 | |
12491 | obuf[0] = 0; | |
ce518a5f L |
12492 | for (i = 0; i < MAX_OPERANDS; ++i) |
12493 | { | |
12494 | op_out[i][0] = 0; | |
12495 | op_index[i] = -1; | |
12496 | } | |
252b5132 RH |
12497 | |
12498 | the_info = info; | |
12499 | start_pc = pc; | |
e396998b AM |
12500 | start_codep = priv.the_buffer; |
12501 | codep = priv.the_buffer; | |
252b5132 | 12502 | |
5076851f ILT |
12503 | if (setjmp (priv.bailout) != 0) |
12504 | { | |
7d421014 ILT |
12505 | const char *name; |
12506 | ||
5076851f | 12507 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
12508 | means we have an incomplete instruction of some sort. Just |
12509 | print the first byte as a prefix or a .byte pseudo-op. */ | |
12510 | if (codep > priv.the_buffer) | |
5076851f | 12511 | { |
e396998b | 12512 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
12513 | if (name != NULL) |
12514 | (*info->fprintf_func) (info->stream, "%s", name); | |
12515 | else | |
5076851f | 12516 | { |
7d421014 ILT |
12517 | /* Just print the first byte as a .byte instruction. */ |
12518 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 12519 | (unsigned int) priv.the_buffer[0]); |
5076851f | 12520 | } |
5076851f | 12521 | |
7d421014 | 12522 | return 1; |
5076851f ILT |
12523 | } |
12524 | ||
12525 | return -1; | |
12526 | } | |
12527 | ||
52b15da3 | 12528 | obufp = obuf; |
f16cd0d5 L |
12529 | sizeflag = priv.orig_sizeflag; |
12530 | ||
12531 | if (!ckprefix () || rex_used) | |
12532 | { | |
12533 | /* Too many prefixes or unused REX prefixes. */ | |
12534 | for (i = 0; | |
f6dd4781 | 12535 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
f16cd0d5 | 12536 | i++) |
de882298 | 12537 | (*info->fprintf_func) (info->stream, "%s%s", |
6c067bbb | 12538 | i == 0 ? "" : " ", |
f16cd0d5 | 12539 | prefix_name (all_prefixes[i], sizeflag)); |
de882298 | 12540 | return i; |
f16cd0d5 | 12541 | } |
252b5132 RH |
12542 | |
12543 | insn_codep = codep; | |
12544 | ||
12545 | FETCH_DATA (info, codep + 1); | |
12546 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
12547 | ||
3e7d61b2 | 12548 | if (((prefixes & PREFIX_FWAIT) |
f16cd0d5 | 12549 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
252b5132 | 12550 | { |
f16cd0d5 | 12551 | (*info->fprintf_func) (info->stream, "fwait"); |
7d421014 | 12552 | return 1; |
252b5132 RH |
12553 | } |
12554 | ||
252b5132 RH |
12555 | if (*codep == 0x0f) |
12556 | { | |
eec0f4ca | 12557 | unsigned char threebyte; |
252b5132 | 12558 | FETCH_DATA (info, codep + 2); |
eec0f4ca L |
12559 | threebyte = *++codep; |
12560 | dp = &dis386_twobyte[threebyte]; | |
252b5132 | 12561 | need_modrm = twobyte_has_modrm[*codep]; |
eec0f4ca | 12562 | codep++; |
252b5132 RH |
12563 | } |
12564 | else | |
12565 | { | |
6439fc28 | 12566 | dp = &dis386[*codep]; |
252b5132 | 12567 | need_modrm = onebyte_has_modrm[*codep]; |
eec0f4ca | 12568 | codep++; |
252b5132 | 12569 | } |
246c51aa | 12570 | |
b844680a | 12571 | if ((prefixes & PREFIX_REPZ)) |
f16cd0d5 | 12572 | used_prefixes |= PREFIX_REPZ; |
b844680a | 12573 | if ((prefixes & PREFIX_REPNZ)) |
f16cd0d5 | 12574 | used_prefixes |= PREFIX_REPNZ; |
b844680a | 12575 | if ((prefixes & PREFIX_LOCK)) |
f16cd0d5 | 12576 | used_prefixes |= PREFIX_LOCK; |
c608c12e | 12577 | |
f16cd0d5 | 12578 | default_prefixes = 0; |
c608c12e AM |
12579 | if (prefixes & PREFIX_ADDR) |
12580 | { | |
12581 | sizeflag ^= AFLAG; | |
ce518a5f | 12582 | if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax) |
3ffd33cf | 12583 | { |
cb712a9e | 12584 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
f16cd0d5 | 12585 | all_prefixes[last_addr_prefix] = ADDR32_PREFIX; |
3ffd33cf | 12586 | else |
f16cd0d5 L |
12587 | all_prefixes[last_addr_prefix] = ADDR16_PREFIX; |
12588 | default_prefixes |= PREFIX_ADDR; | |
3ffd33cf AM |
12589 | } |
12590 | } | |
12591 | ||
b844680a | 12592 | if ((prefixes & PREFIX_DATA)) |
3ffd33cf AM |
12593 | { |
12594 | sizeflag ^= DFLAG; | |
ce518a5f L |
12595 | if (dp->op[2].bytemode == cond_jump_mode |
12596 | && dp->op[0].bytemode == v_mode | |
6439fc28 | 12597 | && !intel_syntax) |
3ffd33cf AM |
12598 | { |
12599 | if (sizeflag & DFLAG) | |
f16cd0d5 | 12600 | all_prefixes[last_data_prefix] = DATA32_PREFIX; |
3ffd33cf | 12601 | else |
f16cd0d5 L |
12602 | all_prefixes[last_data_prefix] = DATA16_PREFIX; |
12603 | default_prefixes |= PREFIX_DATA; | |
12604 | } | |
12605 | else if (rex & REX_W) | |
12606 | { | |
12607 | /* REX_W will override PREFIX_DATA. */ | |
12608 | default_prefixes |= PREFIX_DATA; | |
3ffd33cf AM |
12609 | } |
12610 | } | |
12611 | ||
8bb15339 | 12612 | if (need_modrm) |
252b5132 RH |
12613 | { |
12614 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
12615 | modrm.mod = (*codep >> 6) & 3; |
12616 | modrm.reg = (*codep >> 3) & 7; | |
12617 | modrm.rm = *codep & 7; | |
252b5132 RH |
12618 | } |
12619 | ||
42d5f9c6 MS |
12620 | need_vex = 0; |
12621 | need_vex_reg = 0; | |
12622 | vex_w_done = 0; | |
43234a1e | 12623 | vex.evex = 0; |
55b126d4 | 12624 | |
ce518a5f | 12625 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 | 12626 | { |
55cf16e1 | 12627 | get_sib (info, sizeflag); |
252b5132 RH |
12628 | dofloat (sizeflag); |
12629 | } | |
12630 | else | |
12631 | { | |
8bb15339 | 12632 | dp = get_valid_dis386 (dp, info); |
b844680a | 12633 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
6c067bbb | 12634 | { |
55cf16e1 | 12635 | get_sib (info, sizeflag); |
ce518a5f L |
12636 | for (i = 0; i < MAX_OPERANDS; ++i) |
12637 | { | |
246c51aa | 12638 | obufp = op_out[i]; |
ce518a5f L |
12639 | op_ad = MAX_OPERANDS - 1 - i; |
12640 | if (dp->op[i].rtn) | |
12641 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
43234a1e L |
12642 | /* For EVEX instruction after the last operand masking |
12643 | should be printed. */ | |
12644 | if (i == 0 && vex.evex) | |
12645 | { | |
12646 | /* Don't print {%k0}. */ | |
12647 | if (vex.mask_register_specifier) | |
12648 | { | |
12649 | oappend ("{"); | |
12650 | oappend (names_mask[vex.mask_register_specifier]); | |
12651 | oappend ("}"); | |
12652 | } | |
12653 | if (vex.zeroing) | |
12654 | oappend ("{z}"); | |
12655 | } | |
ce518a5f | 12656 | } |
6439fc28 | 12657 | } |
252b5132 RH |
12658 | } |
12659 | ||
7d421014 ILT |
12660 | /* See if any prefixes were not used. If so, print the first one |
12661 | separately. If we don't do this, we'll wind up printing an | |
12662 | instruction stream which does not precisely correspond to the | |
12663 | bytes we are disassembling. */ | |
f16cd0d5 | 12664 | if ((prefixes & ~(used_prefixes | default_prefixes)) != 0) |
7d421014 | 12665 | { |
f16cd0d5 L |
12666 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
12667 | if (all_prefixes[i]) | |
12668 | { | |
12669 | const char *name; | |
12670 | name = prefix_name (all_prefixes[i], priv.orig_sizeflag); | |
12671 | if (name == NULL) | |
12672 | name = INTERNAL_DISASSEMBLER_ERROR; | |
12673 | (*info->fprintf_func) (info->stream, "%s", name); | |
12674 | return 1; | |
12675 | } | |
52b15da3 | 12676 | } |
7d421014 | 12677 | |
d869730d | 12678 | /* Check if the REX prefix is used. */ |
e2e6193d | 12679 | if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0) |
f16cd0d5 L |
12680 | all_prefixes[last_rex_prefix] = 0; |
12681 | ||
5e6718e4 | 12682 | /* Check if the SEG prefix is used. */ |
f16cd0d5 L |
12683 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
12684 | | PREFIX_FS | PREFIX_GS)) != 0 | |
12685 | && (used_prefixes | |
12686 | & seg_prefix (all_prefixes[last_seg_prefix])) != 0) | |
12687 | all_prefixes[last_seg_prefix] = 0; | |
12688 | ||
5e6718e4 | 12689 | /* Check if the ADDR prefix is used. */ |
f16cd0d5 L |
12690 | if ((prefixes & PREFIX_ADDR) != 0 |
12691 | && (used_prefixes & PREFIX_ADDR) != 0) | |
12692 | all_prefixes[last_addr_prefix] = 0; | |
12693 | ||
5e6718e4 | 12694 | /* Check if the DATA prefix is used. */ |
f16cd0d5 L |
12695 | if ((prefixes & PREFIX_DATA) != 0 |
12696 | && (used_prefixes & PREFIX_DATA) != 0) | |
12697 | all_prefixes[last_data_prefix] = 0; | |
12698 | ||
12699 | prefix_length = 0; | |
f310f33d | 12700 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
f16cd0d5 L |
12701 | if (all_prefixes[i]) |
12702 | { | |
12703 | const char *name; | |
12704 | name = prefix_name (all_prefixes[i], sizeflag); | |
12705 | if (name == NULL) | |
12706 | abort (); | |
12707 | prefix_length += strlen (name) + 1; | |
12708 | (*info->fprintf_func) (info->stream, "%s ", name); | |
12709 | } | |
b844680a | 12710 | |
f16cd0d5 L |
12711 | /* Check maximum code length. */ |
12712 | if ((codep - start_codep) > MAX_CODE_LENGTH) | |
12713 | { | |
12714 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12715 | return MAX_CODE_LENGTH; | |
12716 | } | |
b844680a | 12717 | |
ea397f5b | 12718 | obufp = mnemonicendp; |
f16cd0d5 | 12719 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
252b5132 RH |
12720 | oappend (" "); |
12721 | oappend (" "); | |
12722 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
12723 | ||
12724 | /* The enter and bound instructions are printed with operands in the same | |
12725 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 12726 | if (intel_syntax || two_source_ops) |
252b5132 | 12727 | { |
185b1163 L |
12728 | bfd_vma riprel; |
12729 | ||
ce518a5f | 12730 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 12731 | op_txt[i] = op_out[i]; |
246c51aa | 12732 | |
ce518a5f L |
12733 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
12734 | { | |
6c067bbb RM |
12735 | op_ad = op_index[i]; |
12736 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
12737 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
12738 | riprel = op_riprel[i]; |
12739 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
12740 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 12741 | } |
252b5132 RH |
12742 | } |
12743 | else | |
12744 | { | |
ce518a5f | 12745 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 12746 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; |
050dfa73 MM |
12747 | } |
12748 | ||
ce518a5f L |
12749 | needcomma = 0; |
12750 | for (i = 0; i < MAX_OPERANDS; ++i) | |
12751 | if (*op_txt[i]) | |
12752 | { | |
12753 | if (needcomma) | |
12754 | (*info->fprintf_func) (info->stream, ","); | |
12755 | if (op_index[i] != -1 && !op_riprel[i]) | |
12756 | (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info); | |
12757 | else | |
12758 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
12759 | needcomma = 1; | |
12760 | } | |
050dfa73 | 12761 | |
ce518a5f | 12762 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
12763 | if (op_index[i] != -1 && op_riprel[i]) |
12764 | { | |
12765 | (*info->fprintf_func) (info->stream, " # "); | |
12766 | (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep | |
12767 | + op_address[op_index[i]]), info); | |
185b1163 | 12768 | break; |
52b15da3 | 12769 | } |
e396998b | 12770 | return codep - priv.the_buffer; |
252b5132 RH |
12771 | } |
12772 | ||
6439fc28 | 12773 | static const char *float_mem[] = { |
252b5132 | 12774 | /* d8 */ |
7c52e0e8 L |
12775 | "fadd{s|}", |
12776 | "fmul{s|}", | |
12777 | "fcom{s|}", | |
12778 | "fcomp{s|}", | |
12779 | "fsub{s|}", | |
12780 | "fsubr{s|}", | |
12781 | "fdiv{s|}", | |
12782 | "fdivr{s|}", | |
db6eb5be | 12783 | /* d9 */ |
7c52e0e8 | 12784 | "fld{s|}", |
252b5132 | 12785 | "(bad)", |
7c52e0e8 L |
12786 | "fst{s|}", |
12787 | "fstp{s|}", | |
9306ca4a | 12788 | "fldenvIC", |
252b5132 | 12789 | "fldcw", |
9306ca4a | 12790 | "fNstenvIC", |
252b5132 RH |
12791 | "fNstcw", |
12792 | /* da */ | |
7c52e0e8 L |
12793 | "fiadd{l|}", |
12794 | "fimul{l|}", | |
12795 | "ficom{l|}", | |
12796 | "ficomp{l|}", | |
12797 | "fisub{l|}", | |
12798 | "fisubr{l|}", | |
12799 | "fidiv{l|}", | |
12800 | "fidivr{l|}", | |
252b5132 | 12801 | /* db */ |
7c52e0e8 L |
12802 | "fild{l|}", |
12803 | "fisttp{l|}", | |
12804 | "fist{l|}", | |
12805 | "fistp{l|}", | |
252b5132 | 12806 | "(bad)", |
6439fc28 | 12807 | "fld{t||t|}", |
252b5132 | 12808 | "(bad)", |
6439fc28 | 12809 | "fstp{t||t|}", |
252b5132 | 12810 | /* dc */ |
7c52e0e8 L |
12811 | "fadd{l|}", |
12812 | "fmul{l|}", | |
12813 | "fcom{l|}", | |
12814 | "fcomp{l|}", | |
12815 | "fsub{l|}", | |
12816 | "fsubr{l|}", | |
12817 | "fdiv{l|}", | |
12818 | "fdivr{l|}", | |
252b5132 | 12819 | /* dd */ |
7c52e0e8 L |
12820 | "fld{l|}", |
12821 | "fisttp{ll|}", | |
12822 | "fst{l||}", | |
12823 | "fstp{l|}", | |
9306ca4a | 12824 | "frstorIC", |
252b5132 | 12825 | "(bad)", |
9306ca4a | 12826 | "fNsaveIC", |
252b5132 RH |
12827 | "fNstsw", |
12828 | /* de */ | |
12829 | "fiadd", | |
12830 | "fimul", | |
12831 | "ficom", | |
12832 | "ficomp", | |
12833 | "fisub", | |
12834 | "fisubr", | |
12835 | "fidiv", | |
12836 | "fidivr", | |
12837 | /* df */ | |
12838 | "fild", | |
ca164297 | 12839 | "fisttp", |
252b5132 RH |
12840 | "fist", |
12841 | "fistp", | |
12842 | "fbld", | |
7c52e0e8 | 12843 | "fild{ll|}", |
252b5132 | 12844 | "fbstp", |
7c52e0e8 | 12845 | "fistp{ll|}", |
1d9f512f AM |
12846 | }; |
12847 | ||
12848 | static const unsigned char float_mem_mode[] = { | |
12849 | /* d8 */ | |
12850 | d_mode, | |
12851 | d_mode, | |
12852 | d_mode, | |
12853 | d_mode, | |
12854 | d_mode, | |
12855 | d_mode, | |
12856 | d_mode, | |
12857 | d_mode, | |
12858 | /* d9 */ | |
12859 | d_mode, | |
12860 | 0, | |
12861 | d_mode, | |
12862 | d_mode, | |
12863 | 0, | |
12864 | w_mode, | |
12865 | 0, | |
12866 | w_mode, | |
12867 | /* da */ | |
12868 | d_mode, | |
12869 | d_mode, | |
12870 | d_mode, | |
12871 | d_mode, | |
12872 | d_mode, | |
12873 | d_mode, | |
12874 | d_mode, | |
12875 | d_mode, | |
12876 | /* db */ | |
12877 | d_mode, | |
12878 | d_mode, | |
12879 | d_mode, | |
12880 | d_mode, | |
12881 | 0, | |
9306ca4a | 12882 | t_mode, |
1d9f512f | 12883 | 0, |
9306ca4a | 12884 | t_mode, |
1d9f512f AM |
12885 | /* dc */ |
12886 | q_mode, | |
12887 | q_mode, | |
12888 | q_mode, | |
12889 | q_mode, | |
12890 | q_mode, | |
12891 | q_mode, | |
12892 | q_mode, | |
12893 | q_mode, | |
12894 | /* dd */ | |
12895 | q_mode, | |
12896 | q_mode, | |
12897 | q_mode, | |
12898 | q_mode, | |
12899 | 0, | |
12900 | 0, | |
12901 | 0, | |
12902 | w_mode, | |
12903 | /* de */ | |
12904 | w_mode, | |
12905 | w_mode, | |
12906 | w_mode, | |
12907 | w_mode, | |
12908 | w_mode, | |
12909 | w_mode, | |
12910 | w_mode, | |
12911 | w_mode, | |
12912 | /* df */ | |
12913 | w_mode, | |
12914 | w_mode, | |
12915 | w_mode, | |
12916 | w_mode, | |
9306ca4a | 12917 | t_mode, |
1d9f512f | 12918 | q_mode, |
9306ca4a | 12919 | t_mode, |
1d9f512f | 12920 | q_mode |
252b5132 RH |
12921 | }; |
12922 | ||
ce518a5f L |
12923 | #define ST { OP_ST, 0 } |
12924 | #define STi { OP_STi, 0 } | |
252b5132 | 12925 | |
4efba78c L |
12926 | #define FGRPd9_2 NULL, { { NULL, 0 } } |
12927 | #define FGRPd9_4 NULL, { { NULL, 1 } } | |
12928 | #define FGRPd9_5 NULL, { { NULL, 2 } } | |
12929 | #define FGRPd9_6 NULL, { { NULL, 3 } } | |
12930 | #define FGRPd9_7 NULL, { { NULL, 4 } } | |
12931 | #define FGRPda_5 NULL, { { NULL, 5 } } | |
12932 | #define FGRPdb_4 NULL, { { NULL, 6 } } | |
12933 | #define FGRPde_3 NULL, { { NULL, 7 } } | |
12934 | #define FGRPdf_4 NULL, { { NULL, 8 } } | |
252b5132 | 12935 | |
2da11e11 | 12936 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
12937 | /* d8 */ |
12938 | { | |
ce518a5f L |
12939 | { "fadd", { ST, STi } }, |
12940 | { "fmul", { ST, STi } }, | |
12941 | { "fcom", { STi } }, | |
12942 | { "fcomp", { STi } }, | |
12943 | { "fsub", { ST, STi } }, | |
12944 | { "fsubr", { ST, STi } }, | |
12945 | { "fdiv", { ST, STi } }, | |
12946 | { "fdivr", { ST, STi } }, | |
252b5132 RH |
12947 | }, |
12948 | /* d9 */ | |
12949 | { | |
ce518a5f L |
12950 | { "fld", { STi } }, |
12951 | { "fxch", { STi } }, | |
252b5132 | 12952 | { FGRPd9_2 }, |
592d1631 | 12953 | { Bad_Opcode }, |
252b5132 RH |
12954 | { FGRPd9_4 }, |
12955 | { FGRPd9_5 }, | |
12956 | { FGRPd9_6 }, | |
12957 | { FGRPd9_7 }, | |
12958 | }, | |
12959 | /* da */ | |
12960 | { | |
ce518a5f L |
12961 | { "fcmovb", { ST, STi } }, |
12962 | { "fcmove", { ST, STi } }, | |
12963 | { "fcmovbe",{ ST, STi } }, | |
12964 | { "fcmovu", { ST, STi } }, | |
592d1631 | 12965 | { Bad_Opcode }, |
252b5132 | 12966 | { FGRPda_5 }, |
592d1631 L |
12967 | { Bad_Opcode }, |
12968 | { Bad_Opcode }, | |
252b5132 RH |
12969 | }, |
12970 | /* db */ | |
12971 | { | |
ce518a5f L |
12972 | { "fcmovnb",{ ST, STi } }, |
12973 | { "fcmovne",{ ST, STi } }, | |
12974 | { "fcmovnbe",{ ST, STi } }, | |
12975 | { "fcmovnu",{ ST, STi } }, | |
252b5132 | 12976 | { FGRPdb_4 }, |
ce518a5f L |
12977 | { "fucomi", { ST, STi } }, |
12978 | { "fcomi", { ST, STi } }, | |
592d1631 | 12979 | { Bad_Opcode }, |
252b5132 RH |
12980 | }, |
12981 | /* dc */ | |
12982 | { | |
ce518a5f L |
12983 | { "fadd", { STi, ST } }, |
12984 | { "fmul", { STi, ST } }, | |
592d1631 L |
12985 | { Bad_Opcode }, |
12986 | { Bad_Opcode }, | |
9d141669 L |
12987 | { "fsub!M", { STi, ST } }, |
12988 | { "fsubM", { STi, ST } }, | |
12989 | { "fdiv!M", { STi, ST } }, | |
12990 | { "fdivM", { STi, ST } }, | |
252b5132 RH |
12991 | }, |
12992 | /* dd */ | |
12993 | { | |
ce518a5f | 12994 | { "ffree", { STi } }, |
592d1631 | 12995 | { Bad_Opcode }, |
ce518a5f L |
12996 | { "fst", { STi } }, |
12997 | { "fstp", { STi } }, | |
12998 | { "fucom", { STi } }, | |
12999 | { "fucomp", { STi } }, | |
592d1631 L |
13000 | { Bad_Opcode }, |
13001 | { Bad_Opcode }, | |
252b5132 RH |
13002 | }, |
13003 | /* de */ | |
13004 | { | |
ce518a5f L |
13005 | { "faddp", { STi, ST } }, |
13006 | { "fmulp", { STi, ST } }, | |
592d1631 | 13007 | { Bad_Opcode }, |
252b5132 | 13008 | { FGRPde_3 }, |
9d141669 L |
13009 | { "fsub!Mp", { STi, ST } }, |
13010 | { "fsubMp", { STi, ST } }, | |
13011 | { "fdiv!Mp", { STi, ST } }, | |
13012 | { "fdivMp", { STi, ST } }, | |
252b5132 RH |
13013 | }, |
13014 | /* df */ | |
13015 | { | |
ce518a5f | 13016 | { "ffreep", { STi } }, |
592d1631 L |
13017 | { Bad_Opcode }, |
13018 | { Bad_Opcode }, | |
13019 | { Bad_Opcode }, | |
252b5132 | 13020 | { FGRPdf_4 }, |
ce518a5f L |
13021 | { "fucomip", { ST, STi } }, |
13022 | { "fcomip", { ST, STi } }, | |
592d1631 | 13023 | { Bad_Opcode }, |
252b5132 RH |
13024 | }, |
13025 | }; | |
13026 | ||
252b5132 RH |
13027 | static char *fgrps[][8] = { |
13028 | /* d9_2 0 */ | |
13029 | { | |
13030 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13031 | }, | |
13032 | ||
13033 | /* d9_4 1 */ | |
13034 | { | |
13035 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
13036 | }, | |
13037 | ||
13038 | /* d9_5 2 */ | |
13039 | { | |
13040 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
13041 | }, | |
13042 | ||
13043 | /* d9_6 3 */ | |
13044 | { | |
13045 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
13046 | }, | |
13047 | ||
13048 | /* d9_7 4 */ | |
13049 | { | |
13050 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
13051 | }, | |
13052 | ||
13053 | /* da_5 5 */ | |
13054 | { | |
13055 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13056 | }, | |
13057 | ||
13058 | /* db_4 6 */ | |
13059 | { | |
309d3373 JB |
13060 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
13061 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", | |
252b5132 RH |
13062 | }, |
13063 | ||
13064 | /* de_3 7 */ | |
13065 | { | |
13066 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13067 | }, | |
13068 | ||
13069 | /* df_4 8 */ | |
13070 | { | |
13071 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13072 | }, | |
13073 | }; | |
13074 | ||
b6169b20 L |
13075 | static void |
13076 | swap_operand (void) | |
13077 | { | |
13078 | mnemonicendp[0] = '.'; | |
13079 | mnemonicendp[1] = 's'; | |
13080 | mnemonicendp += 2; | |
13081 | } | |
13082 | ||
b844680a L |
13083 | static void |
13084 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
13085 | int sizeflag ATTRIBUTE_UNUSED) | |
13086 | { | |
13087 | /* Skip mod/rm byte. */ | |
13088 | MODRM_CHECK; | |
13089 | codep++; | |
13090 | } | |
13091 | ||
252b5132 | 13092 | static void |
26ca5450 | 13093 | dofloat (int sizeflag) |
252b5132 | 13094 | { |
2da11e11 | 13095 | const struct dis386 *dp; |
252b5132 RH |
13096 | unsigned char floatop; |
13097 | ||
13098 | floatop = codep[-1]; | |
13099 | ||
7967e09e | 13100 | if (modrm.mod != 3) |
252b5132 | 13101 | { |
7967e09e | 13102 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
13103 | |
13104 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 13105 | obufp = op_out[0]; |
6e50d963 | 13106 | op_ad = 2; |
1d9f512f | 13107 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
13108 | return; |
13109 | } | |
6608db57 | 13110 | /* Skip mod/rm byte. */ |
4bba6815 | 13111 | MODRM_CHECK; |
252b5132 RH |
13112 | codep++; |
13113 | ||
7967e09e | 13114 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
13115 | if (dp->name == NULL) |
13116 | { | |
7967e09e | 13117 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 13118 | |
6608db57 | 13119 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 13120 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 13121 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
13122 | } |
13123 | else | |
13124 | { | |
13125 | putop (dp->name, sizeflag); | |
13126 | ||
ce518a5f | 13127 | obufp = op_out[0]; |
6e50d963 | 13128 | op_ad = 2; |
ce518a5f L |
13129 | if (dp->op[0].rtn) |
13130 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 13131 | |
ce518a5f | 13132 | obufp = op_out[1]; |
6e50d963 | 13133 | op_ad = 1; |
ce518a5f L |
13134 | if (dp->op[1].rtn) |
13135 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
13136 | } |
13137 | } | |
13138 | ||
9ce09ba2 RM |
13139 | /* Like oappend (below), but S is a string starting with '%'. |
13140 | In Intel syntax, the '%' is elided. */ | |
13141 | static void | |
13142 | oappend_maybe_intel (const char *s) | |
13143 | { | |
13144 | oappend (s + intel_syntax); | |
13145 | } | |
13146 | ||
252b5132 | 13147 | static void |
26ca5450 | 13148 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13149 | { |
9ce09ba2 | 13150 | oappend_maybe_intel ("%st"); |
252b5132 RH |
13151 | } |
13152 | ||
252b5132 | 13153 | static void |
26ca5450 | 13154 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13155 | { |
7967e09e | 13156 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
9ce09ba2 | 13157 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
13158 | } |
13159 | ||
6608db57 | 13160 | /* Capital letters in template are macros. */ |
6439fc28 | 13161 | static int |
d3ce72d0 | 13162 | putop (const char *in_template, int sizeflag) |
252b5132 | 13163 | { |
2da11e11 | 13164 | const char *p; |
9306ca4a | 13165 | int alt = 0; |
9d141669 | 13166 | int cond = 1; |
98b528ac L |
13167 | unsigned int l = 0, len = 1; |
13168 | char last[4]; | |
13169 | ||
13170 | #define SAVE_LAST(c) \ | |
13171 | if (l < len && l < sizeof (last)) \ | |
13172 | last[l++] = c; \ | |
13173 | else \ | |
13174 | abort (); | |
252b5132 | 13175 | |
d3ce72d0 | 13176 | for (p = in_template; *p; p++) |
252b5132 RH |
13177 | { |
13178 | switch (*p) | |
13179 | { | |
13180 | default: | |
13181 | *obufp++ = *p; | |
13182 | break; | |
98b528ac L |
13183 | case '%': |
13184 | len++; | |
13185 | break; | |
9d141669 L |
13186 | case '!': |
13187 | cond = 0; | |
13188 | break; | |
6439fc28 AM |
13189 | case '{': |
13190 | alt = 0; | |
13191 | if (intel_syntax) | |
6439fc28 AM |
13192 | { |
13193 | while (*++p != '|') | |
7c52e0e8 L |
13194 | if (*p == '}' || *p == '\0') |
13195 | abort (); | |
6439fc28 | 13196 | } |
9306ca4a JB |
13197 | /* Fall through. */ |
13198 | case 'I': | |
13199 | alt = 1; | |
13200 | continue; | |
6439fc28 AM |
13201 | case '|': |
13202 | while (*++p != '}') | |
13203 | { | |
13204 | if (*p == '\0') | |
13205 | abort (); | |
13206 | } | |
13207 | break; | |
13208 | case '}': | |
13209 | break; | |
252b5132 | 13210 | case 'A': |
db6eb5be AM |
13211 | if (intel_syntax) |
13212 | break; | |
7967e09e | 13213 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 RH |
13214 | *obufp++ = 'b'; |
13215 | break; | |
13216 | case 'B': | |
4b06377f L |
13217 | if (l == 0 && len == 1) |
13218 | { | |
13219 | case_B: | |
13220 | if (intel_syntax) | |
13221 | break; | |
13222 | if (sizeflag & SUFFIX_ALWAYS) | |
13223 | *obufp++ = 'b'; | |
13224 | } | |
13225 | else | |
13226 | { | |
13227 | if (l != 1 | |
13228 | || len != 2 | |
13229 | || last[0] != 'L') | |
13230 | { | |
13231 | SAVE_LAST (*p); | |
13232 | break; | |
13233 | } | |
13234 | ||
13235 | if (address_mode == mode_64bit | |
13236 | && !(prefixes & PREFIX_ADDR)) | |
13237 | { | |
13238 | *obufp++ = 'a'; | |
13239 | *obufp++ = 'b'; | |
13240 | *obufp++ = 's'; | |
13241 | } | |
13242 | ||
13243 | goto case_B; | |
13244 | } | |
252b5132 | 13245 | break; |
9306ca4a JB |
13246 | case 'C': |
13247 | if (intel_syntax && !alt) | |
13248 | break; | |
13249 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
13250 | { | |
13251 | if (sizeflag & DFLAG) | |
13252 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13253 | else | |
13254 | *obufp++ = intel_syntax ? 'w' : 's'; | |
13255 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13256 | } | |
13257 | break; | |
ed7841b3 JB |
13258 | case 'D': |
13259 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
13260 | break; | |
161a04f6 | 13261 | USED_REX (REX_W); |
7967e09e | 13262 | if (modrm.mod == 3) |
ed7841b3 | 13263 | { |
161a04f6 | 13264 | if (rex & REX_W) |
ed7841b3 | 13265 | *obufp++ = 'q'; |
ed7841b3 | 13266 | else |
f16cd0d5 L |
13267 | { |
13268 | if (sizeflag & DFLAG) | |
13269 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13270 | else | |
13271 | *obufp++ = 'w'; | |
13272 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13273 | } | |
ed7841b3 JB |
13274 | } |
13275 | else | |
13276 | *obufp++ = 'w'; | |
13277 | break; | |
252b5132 | 13278 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 13279 | if (address_mode == mode_64bit) |
c1a64871 JH |
13280 | { |
13281 | if (sizeflag & AFLAG) | |
13282 | *obufp++ = 'r'; | |
13283 | else | |
13284 | *obufp++ = 'e'; | |
13285 | } | |
13286 | else | |
13287 | if (sizeflag & AFLAG) | |
13288 | *obufp++ = 'e'; | |
3ffd33cf AM |
13289 | used_prefixes |= (prefixes & PREFIX_ADDR); |
13290 | break; | |
13291 | case 'F': | |
db6eb5be AM |
13292 | if (intel_syntax) |
13293 | break; | |
e396998b | 13294 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
13295 | { |
13296 | if (sizeflag & AFLAG) | |
cb712a9e | 13297 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 13298 | else |
cb712a9e | 13299 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
13300 | used_prefixes |= (prefixes & PREFIX_ADDR); |
13301 | } | |
252b5132 | 13302 | break; |
52fd6d94 JB |
13303 | case 'G': |
13304 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
13305 | break; | |
161a04f6 | 13306 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
13307 | *obufp++ = 'l'; |
13308 | else | |
13309 | *obufp++ = 'w'; | |
161a04f6 | 13310 | if (!(rex & REX_W)) |
52fd6d94 JB |
13311 | used_prefixes |= (prefixes & PREFIX_DATA); |
13312 | break; | |
5dd0794d | 13313 | case 'H': |
db6eb5be AM |
13314 | if (intel_syntax) |
13315 | break; | |
5dd0794d AM |
13316 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
13317 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
13318 | { | |
13319 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
13320 | *obufp++ = ','; | |
13321 | *obufp++ = 'p'; | |
13322 | if (prefixes & PREFIX_DS) | |
13323 | *obufp++ = 't'; | |
13324 | else | |
13325 | *obufp++ = 'n'; | |
13326 | } | |
13327 | break; | |
9306ca4a JB |
13328 | case 'J': |
13329 | if (intel_syntax) | |
13330 | break; | |
13331 | *obufp++ = 'l'; | |
13332 | break; | |
42903f7f L |
13333 | case 'K': |
13334 | USED_REX (REX_W); | |
13335 | if (rex & REX_W) | |
13336 | *obufp++ = 'q'; | |
13337 | else | |
13338 | *obufp++ = 'd'; | |
13339 | break; | |
6dd5059a L |
13340 | case 'Z': |
13341 | if (intel_syntax) | |
13342 | break; | |
13343 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) | |
13344 | { | |
13345 | *obufp++ = 'q'; | |
13346 | break; | |
13347 | } | |
13348 | /* Fall through. */ | |
98b528ac | 13349 | goto case_L; |
252b5132 | 13350 | case 'L': |
98b528ac L |
13351 | if (l != 0 || len != 1) |
13352 | { | |
13353 | SAVE_LAST (*p); | |
13354 | break; | |
13355 | } | |
13356 | case_L: | |
db6eb5be AM |
13357 | if (intel_syntax) |
13358 | break; | |
252b5132 RH |
13359 | if (sizeflag & SUFFIX_ALWAYS) |
13360 | *obufp++ = 'l'; | |
252b5132 | 13361 | break; |
9d141669 L |
13362 | case 'M': |
13363 | if (intel_mnemonic != cond) | |
13364 | *obufp++ = 'r'; | |
13365 | break; | |
252b5132 RH |
13366 | case 'N': |
13367 | if ((prefixes & PREFIX_FWAIT) == 0) | |
13368 | *obufp++ = 'n'; | |
7d421014 ILT |
13369 | else |
13370 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 13371 | break; |
52b15da3 | 13372 | case 'O': |
161a04f6 L |
13373 | USED_REX (REX_W); |
13374 | if (rex & REX_W) | |
6439fc28 | 13375 | *obufp++ = 'o'; |
a35ca55a JB |
13376 | else if (intel_syntax && (sizeflag & DFLAG)) |
13377 | *obufp++ = 'q'; | |
52b15da3 JH |
13378 | else |
13379 | *obufp++ = 'd'; | |
161a04f6 | 13380 | if (!(rex & REX_W)) |
a35ca55a | 13381 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 13382 | break; |
6439fc28 | 13383 | case 'T': |
d9e3625e L |
13384 | if (!intel_syntax |
13385 | && address_mode == mode_64bit | |
7bb15c6f | 13386 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
13387 | { |
13388 | *obufp++ = 'q'; | |
13389 | break; | |
13390 | } | |
6608db57 | 13391 | /* Fall through. */ |
252b5132 | 13392 | case 'P': |
db6eb5be | 13393 | if (intel_syntax) |
d9e3625e L |
13394 | { |
13395 | if ((rex & REX_W) == 0 | |
13396 | && (prefixes & PREFIX_DATA)) | |
13397 | { | |
13398 | if ((sizeflag & DFLAG) == 0) | |
13399 | *obufp++ = 'w'; | |
13400 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13401 | } | |
13402 | break; | |
13403 | } | |
252b5132 | 13404 | if ((prefixes & PREFIX_DATA) |
161a04f6 | 13405 | || (rex & REX_W) |
e396998b | 13406 | || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 | 13407 | { |
161a04f6 L |
13408 | USED_REX (REX_W); |
13409 | if (rex & REX_W) | |
52b15da3 | 13410 | *obufp++ = 'q'; |
c2419411 | 13411 | else |
52b15da3 JH |
13412 | { |
13413 | if (sizeflag & DFLAG) | |
13414 | *obufp++ = 'l'; | |
13415 | else | |
13416 | *obufp++ = 'w'; | |
f16cd0d5 | 13417 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 13418 | } |
252b5132 RH |
13419 | } |
13420 | break; | |
6439fc28 | 13421 | case 'U': |
db6eb5be AM |
13422 | if (intel_syntax) |
13423 | break; | |
7bb15c6f | 13424 | if (address_mode == mode_64bit |
6c067bbb | 13425 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 | 13426 | { |
7967e09e | 13427 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
1a114b12 | 13428 | *obufp++ = 'q'; |
6439fc28 AM |
13429 | break; |
13430 | } | |
6608db57 | 13431 | /* Fall through. */ |
98b528ac | 13432 | goto case_Q; |
252b5132 | 13433 | case 'Q': |
98b528ac | 13434 | if (l == 0 && len == 1) |
252b5132 | 13435 | { |
98b528ac L |
13436 | case_Q: |
13437 | if (intel_syntax && !alt) | |
13438 | break; | |
13439 | USED_REX (REX_W); | |
13440 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 13441 | { |
98b528ac L |
13442 | if (rex & REX_W) |
13443 | *obufp++ = 'q'; | |
52b15da3 | 13444 | else |
98b528ac L |
13445 | { |
13446 | if (sizeflag & DFLAG) | |
13447 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13448 | else | |
13449 | *obufp++ = 'w'; | |
f16cd0d5 | 13450 | used_prefixes |= (prefixes & PREFIX_DATA); |
98b528ac | 13451 | } |
52b15da3 | 13452 | } |
98b528ac L |
13453 | } |
13454 | else | |
13455 | { | |
13456 | if (l != 1 || len != 2 || last[0] != 'L') | |
13457 | { | |
13458 | SAVE_LAST (*p); | |
13459 | break; | |
13460 | } | |
13461 | if (intel_syntax | |
13462 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) | |
13463 | break; | |
13464 | if ((rex & REX_W)) | |
13465 | { | |
13466 | USED_REX (REX_W); | |
13467 | *obufp++ = 'q'; | |
13468 | } | |
13469 | else | |
13470 | *obufp++ = 'l'; | |
252b5132 RH |
13471 | } |
13472 | break; | |
13473 | case 'R': | |
161a04f6 L |
13474 | USED_REX (REX_W); |
13475 | if (rex & REX_W) | |
a35ca55a JB |
13476 | *obufp++ = 'q'; |
13477 | else if (sizeflag & DFLAG) | |
c608c12e | 13478 | { |
a35ca55a | 13479 | if (intel_syntax) |
c608c12e | 13480 | *obufp++ = 'd'; |
c608c12e | 13481 | else |
a35ca55a | 13482 | *obufp++ = 'l'; |
c608c12e | 13483 | } |
252b5132 | 13484 | else |
a35ca55a JB |
13485 | *obufp++ = 'w'; |
13486 | if (intel_syntax && !p[1] | |
161a04f6 | 13487 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 13488 | *obufp++ = 'e'; |
161a04f6 | 13489 | if (!(rex & REX_W)) |
52b15da3 | 13490 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 13491 | break; |
1a114b12 | 13492 | case 'V': |
4b06377f | 13493 | if (l == 0 && len == 1) |
1a114b12 | 13494 | { |
4b06377f L |
13495 | if (intel_syntax) |
13496 | break; | |
7bb15c6f | 13497 | if (address_mode == mode_64bit |
6c067bbb | 13498 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
4b06377f L |
13499 | { |
13500 | if (sizeflag & SUFFIX_ALWAYS) | |
13501 | *obufp++ = 'q'; | |
13502 | break; | |
13503 | } | |
13504 | } | |
13505 | else | |
13506 | { | |
13507 | if (l != 1 | |
13508 | || len != 2 | |
13509 | || last[0] != 'L') | |
13510 | { | |
13511 | SAVE_LAST (*p); | |
13512 | break; | |
13513 | } | |
13514 | ||
13515 | if (rex & REX_W) | |
13516 | { | |
13517 | *obufp++ = 'a'; | |
13518 | *obufp++ = 'b'; | |
13519 | *obufp++ = 's'; | |
13520 | } | |
1a114b12 JB |
13521 | } |
13522 | /* Fall through. */ | |
4b06377f | 13523 | goto case_S; |
252b5132 | 13524 | case 'S': |
4b06377f | 13525 | if (l == 0 && len == 1) |
252b5132 | 13526 | { |
4b06377f L |
13527 | case_S: |
13528 | if (intel_syntax) | |
13529 | break; | |
13530 | if (sizeflag & SUFFIX_ALWAYS) | |
52b15da3 | 13531 | { |
4b06377f L |
13532 | if (rex & REX_W) |
13533 | *obufp++ = 'q'; | |
52b15da3 | 13534 | else |
4b06377f L |
13535 | { |
13536 | if (sizeflag & DFLAG) | |
13537 | *obufp++ = 'l'; | |
13538 | else | |
13539 | *obufp++ = 'w'; | |
13540 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13541 | } | |
13542 | } | |
13543 | } | |
13544 | else | |
13545 | { | |
13546 | if (l != 1 | |
13547 | || len != 2 | |
13548 | || last[0] != 'L') | |
13549 | { | |
13550 | SAVE_LAST (*p); | |
13551 | break; | |
52b15da3 | 13552 | } |
4b06377f L |
13553 | |
13554 | if (address_mode == mode_64bit | |
13555 | && !(prefixes & PREFIX_ADDR)) | |
13556 | { | |
13557 | *obufp++ = 'a'; | |
13558 | *obufp++ = 'b'; | |
13559 | *obufp++ = 's'; | |
13560 | } | |
13561 | ||
13562 | goto case_S; | |
252b5132 | 13563 | } |
252b5132 | 13564 | break; |
041bd2e0 | 13565 | case 'X': |
c0f3af97 L |
13566 | if (l != 0 || len != 1) |
13567 | { | |
13568 | SAVE_LAST (*p); | |
13569 | break; | |
13570 | } | |
13571 | if (need_vex && vex.prefix) | |
13572 | { | |
13573 | if (vex.prefix == DATA_PREFIX_OPCODE) | |
13574 | *obufp++ = 'd'; | |
13575 | else | |
13576 | *obufp++ = 's'; | |
13577 | } | |
041bd2e0 | 13578 | else |
f16cd0d5 L |
13579 | { |
13580 | if (prefixes & PREFIX_DATA) | |
13581 | *obufp++ = 'd'; | |
13582 | else | |
13583 | *obufp++ = 's'; | |
13584 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13585 | } | |
041bd2e0 | 13586 | break; |
76f227a5 | 13587 | case 'Y': |
c0f3af97 | 13588 | if (l == 0 && len == 1) |
76f227a5 | 13589 | { |
c0f3af97 L |
13590 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) |
13591 | break; | |
13592 | if (rex & REX_W) | |
13593 | { | |
13594 | USED_REX (REX_W); | |
13595 | *obufp++ = 'q'; | |
13596 | } | |
13597 | break; | |
13598 | } | |
13599 | else | |
13600 | { | |
13601 | if (l != 1 || len != 2 || last[0] != 'X') | |
13602 | { | |
13603 | SAVE_LAST (*p); | |
13604 | break; | |
13605 | } | |
13606 | if (!need_vex) | |
13607 | abort (); | |
13608 | if (intel_syntax | |
13609 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) | |
13610 | break; | |
13611 | switch (vex.length) | |
13612 | { | |
13613 | case 128: | |
13614 | *obufp++ = 'x'; | |
13615 | break; | |
13616 | case 256: | |
13617 | *obufp++ = 'y'; | |
13618 | break; | |
13619 | default: | |
13620 | abort (); | |
13621 | } | |
76f227a5 JH |
13622 | } |
13623 | break; | |
252b5132 | 13624 | case 'W': |
0bfee649 | 13625 | if (l == 0 && len == 1) |
a35ca55a | 13626 | { |
0bfee649 L |
13627 | /* operand size flag for cwtl, cbtw */ |
13628 | USED_REX (REX_W); | |
13629 | if (rex & REX_W) | |
13630 | { | |
13631 | if (intel_syntax) | |
13632 | *obufp++ = 'd'; | |
13633 | else | |
13634 | *obufp++ = 'l'; | |
13635 | } | |
13636 | else if (sizeflag & DFLAG) | |
13637 | *obufp++ = 'w'; | |
a35ca55a | 13638 | else |
0bfee649 L |
13639 | *obufp++ = 'b'; |
13640 | if (!(rex & REX_W)) | |
13641 | used_prefixes |= (prefixes & PREFIX_DATA); | |
a35ca55a | 13642 | } |
252b5132 | 13643 | else |
0bfee649 | 13644 | { |
6c30d220 L |
13645 | if (l != 1 |
13646 | || len != 2 | |
13647 | || (last[0] != 'X' | |
13648 | && last[0] != 'L')) | |
0bfee649 L |
13649 | { |
13650 | SAVE_LAST (*p); | |
13651 | break; | |
13652 | } | |
13653 | if (!need_vex) | |
13654 | abort (); | |
6c30d220 L |
13655 | if (last[0] == 'X') |
13656 | *obufp++ = vex.w ? 'd': 's'; | |
13657 | else | |
13658 | *obufp++ = vex.w ? 'q': 'd'; | |
0bfee649 | 13659 | } |
252b5132 RH |
13660 | break; |
13661 | } | |
9306ca4a | 13662 | alt = 0; |
252b5132 RH |
13663 | } |
13664 | *obufp = 0; | |
ea397f5b | 13665 | mnemonicendp = obufp; |
6439fc28 | 13666 | return 0; |
252b5132 RH |
13667 | } |
13668 | ||
13669 | static void | |
26ca5450 | 13670 | oappend (const char *s) |
252b5132 | 13671 | { |
ea397f5b | 13672 | obufp = stpcpy (obufp, s); |
252b5132 RH |
13673 | } |
13674 | ||
13675 | static void | |
26ca5450 | 13676 | append_seg (void) |
252b5132 RH |
13677 | { |
13678 | if (prefixes & PREFIX_CS) | |
7d421014 | 13679 | { |
7d421014 | 13680 | used_prefixes |= PREFIX_CS; |
9ce09ba2 | 13681 | oappend_maybe_intel ("%cs:"); |
7d421014 | 13682 | } |
252b5132 | 13683 | if (prefixes & PREFIX_DS) |
7d421014 | 13684 | { |
7d421014 | 13685 | used_prefixes |= PREFIX_DS; |
9ce09ba2 | 13686 | oappend_maybe_intel ("%ds:"); |
7d421014 | 13687 | } |
252b5132 | 13688 | if (prefixes & PREFIX_SS) |
7d421014 | 13689 | { |
7d421014 | 13690 | used_prefixes |= PREFIX_SS; |
9ce09ba2 | 13691 | oappend_maybe_intel ("%ss:"); |
7d421014 | 13692 | } |
252b5132 | 13693 | if (prefixes & PREFIX_ES) |
7d421014 | 13694 | { |
7d421014 | 13695 | used_prefixes |= PREFIX_ES; |
9ce09ba2 | 13696 | oappend_maybe_intel ("%es:"); |
7d421014 | 13697 | } |
252b5132 | 13698 | if (prefixes & PREFIX_FS) |
7d421014 | 13699 | { |
7d421014 | 13700 | used_prefixes |= PREFIX_FS; |
9ce09ba2 | 13701 | oappend_maybe_intel ("%fs:"); |
7d421014 | 13702 | } |
252b5132 | 13703 | if (prefixes & PREFIX_GS) |
7d421014 | 13704 | { |
7d421014 | 13705 | used_prefixes |= PREFIX_GS; |
9ce09ba2 | 13706 | oappend_maybe_intel ("%gs:"); |
7d421014 | 13707 | } |
252b5132 RH |
13708 | } |
13709 | ||
13710 | static void | |
26ca5450 | 13711 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
13712 | { |
13713 | if (!intel_syntax) | |
13714 | oappend ("*"); | |
13715 | OP_E (bytemode, sizeflag); | |
13716 | } | |
13717 | ||
52b15da3 | 13718 | static void |
26ca5450 | 13719 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 13720 | { |
cb712a9e | 13721 | if (address_mode == mode_64bit) |
52b15da3 JH |
13722 | { |
13723 | if (hex) | |
13724 | { | |
13725 | char tmp[30]; | |
13726 | int i; | |
13727 | buf[0] = '0'; | |
13728 | buf[1] = 'x'; | |
13729 | sprintf_vma (tmp, disp); | |
6608db57 | 13730 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
13731 | strcpy (buf + 2, tmp + i); |
13732 | } | |
13733 | else | |
13734 | { | |
13735 | bfd_signed_vma v = disp; | |
13736 | char tmp[30]; | |
13737 | int i; | |
13738 | if (v < 0) | |
13739 | { | |
13740 | *(buf++) = '-'; | |
13741 | v = -disp; | |
6608db57 | 13742 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
13743 | if (v < 0) |
13744 | { | |
13745 | strcpy (buf, "9223372036854775808"); | |
13746 | return; | |
13747 | } | |
13748 | } | |
13749 | if (!v) | |
13750 | { | |
13751 | strcpy (buf, "0"); | |
13752 | return; | |
13753 | } | |
13754 | ||
13755 | i = 0; | |
13756 | tmp[29] = 0; | |
13757 | while (v) | |
13758 | { | |
6608db57 | 13759 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
13760 | v /= 10; |
13761 | i++; | |
13762 | } | |
13763 | strcpy (buf, tmp + 29 - i); | |
13764 | } | |
13765 | } | |
13766 | else | |
13767 | { | |
13768 | if (hex) | |
13769 | sprintf (buf, "0x%x", (unsigned int) disp); | |
13770 | else | |
13771 | sprintf (buf, "%d", (int) disp); | |
13772 | } | |
13773 | } | |
13774 | ||
5d669648 L |
13775 | /* Put DISP in BUF as signed hex number. */ |
13776 | ||
13777 | static void | |
13778 | print_displacement (char *buf, bfd_vma disp) | |
13779 | { | |
13780 | bfd_signed_vma val = disp; | |
13781 | char tmp[30]; | |
13782 | int i, j = 0; | |
13783 | ||
13784 | if (val < 0) | |
13785 | { | |
13786 | buf[j++] = '-'; | |
13787 | val = -disp; | |
13788 | ||
13789 | /* Check for possible overflow. */ | |
13790 | if (val < 0) | |
13791 | { | |
13792 | switch (address_mode) | |
13793 | { | |
13794 | case mode_64bit: | |
13795 | strcpy (buf + j, "0x8000000000000000"); | |
13796 | break; | |
13797 | case mode_32bit: | |
13798 | strcpy (buf + j, "0x80000000"); | |
13799 | break; | |
13800 | case mode_16bit: | |
13801 | strcpy (buf + j, "0x8000"); | |
13802 | break; | |
13803 | } | |
13804 | return; | |
13805 | } | |
13806 | } | |
13807 | ||
13808 | buf[j++] = '0'; | |
13809 | buf[j++] = 'x'; | |
13810 | ||
0af1713e | 13811 | sprintf_vma (tmp, (bfd_vma) val); |
5d669648 L |
13812 | for (i = 0; tmp[i] == '0'; i++) |
13813 | continue; | |
13814 | if (tmp[i] == '\0') | |
13815 | i--; | |
13816 | strcpy (buf + j, tmp + i); | |
13817 | } | |
13818 | ||
3f31e633 JB |
13819 | static void |
13820 | intel_operand_size (int bytemode, int sizeflag) | |
13821 | { | |
43234a1e L |
13822 | if (vex.evex |
13823 | && vex.b | |
13824 | && (bytemode == x_mode | |
13825 | || bytemode == evex_half_bcst_xmmq_mode)) | |
13826 | { | |
13827 | if (vex.w) | |
13828 | oappend ("QWORD PTR "); | |
13829 | else | |
13830 | oappend ("DWORD PTR "); | |
13831 | return; | |
13832 | } | |
3f31e633 JB |
13833 | switch (bytemode) |
13834 | { | |
13835 | case b_mode: | |
b6169b20 | 13836 | case b_swap_mode: |
42903f7f | 13837 | case dqb_mode: |
3f31e633 JB |
13838 | oappend ("BYTE PTR "); |
13839 | break; | |
13840 | case w_mode: | |
13841 | case dqw_mode: | |
13842 | oappend ("WORD PTR "); | |
13843 | break; | |
1a114b12 | 13844 | case stack_v_mode: |
7bb15c6f | 13845 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
3f31e633 JB |
13846 | { |
13847 | oappend ("QWORD PTR "); | |
3f31e633 JB |
13848 | break; |
13849 | } | |
13850 | /* FALLTHRU */ | |
13851 | case v_mode: | |
b6169b20 | 13852 | case v_swap_mode: |
3f31e633 | 13853 | case dq_mode: |
161a04f6 L |
13854 | USED_REX (REX_W); |
13855 | if (rex & REX_W) | |
3f31e633 | 13856 | oappend ("QWORD PTR "); |
3f31e633 | 13857 | else |
f16cd0d5 L |
13858 | { |
13859 | if ((sizeflag & DFLAG) || bytemode == dq_mode) | |
13860 | oappend ("DWORD PTR "); | |
13861 | else | |
13862 | oappend ("WORD PTR "); | |
13863 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13864 | } | |
3f31e633 | 13865 | break; |
52fd6d94 | 13866 | case z_mode: |
161a04f6 | 13867 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
13868 | *obufp++ = 'D'; |
13869 | oappend ("WORD PTR "); | |
161a04f6 | 13870 | if (!(rex & REX_W)) |
52fd6d94 JB |
13871 | used_prefixes |= (prefixes & PREFIX_DATA); |
13872 | break; | |
34b772a6 JB |
13873 | case a_mode: |
13874 | if (sizeflag & DFLAG) | |
13875 | oappend ("QWORD PTR "); | |
13876 | else | |
13877 | oappend ("DWORD PTR "); | |
13878 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13879 | break; | |
3f31e633 | 13880 | case d_mode: |
539f890d L |
13881 | case d_scalar_mode: |
13882 | case d_scalar_swap_mode: | |
fa99fab2 | 13883 | case d_swap_mode: |
42903f7f | 13884 | case dqd_mode: |
3f31e633 JB |
13885 | oappend ("DWORD PTR "); |
13886 | break; | |
13887 | case q_mode: | |
539f890d L |
13888 | case q_scalar_mode: |
13889 | case q_scalar_swap_mode: | |
b6169b20 | 13890 | case q_swap_mode: |
3f31e633 JB |
13891 | oappend ("QWORD PTR "); |
13892 | break; | |
13893 | case m_mode: | |
cb712a9e | 13894 | if (address_mode == mode_64bit) |
3f31e633 JB |
13895 | oappend ("QWORD PTR "); |
13896 | else | |
13897 | oappend ("DWORD PTR "); | |
13898 | break; | |
13899 | case f_mode: | |
13900 | if (sizeflag & DFLAG) | |
13901 | oappend ("FWORD PTR "); | |
13902 | else | |
13903 | oappend ("DWORD PTR "); | |
13904 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13905 | break; | |
13906 | case t_mode: | |
13907 | oappend ("TBYTE PTR "); | |
13908 | break; | |
13909 | case x_mode: | |
b6169b20 | 13910 | case x_swap_mode: |
43234a1e L |
13911 | case evex_x_gscat_mode: |
13912 | case evex_x_nobcst_mode: | |
c0f3af97 L |
13913 | if (need_vex) |
13914 | { | |
13915 | switch (vex.length) | |
13916 | { | |
13917 | case 128: | |
13918 | oappend ("XMMWORD PTR "); | |
13919 | break; | |
13920 | case 256: | |
13921 | oappend ("YMMWORD PTR "); | |
13922 | break; | |
43234a1e L |
13923 | case 512: |
13924 | oappend ("ZMMWORD PTR "); | |
13925 | break; | |
c0f3af97 L |
13926 | default: |
13927 | abort (); | |
13928 | } | |
13929 | } | |
13930 | else | |
13931 | oappend ("XMMWORD PTR "); | |
13932 | break; | |
13933 | case xmm_mode: | |
3f31e633 JB |
13934 | oappend ("XMMWORD PTR "); |
13935 | break; | |
43234a1e L |
13936 | case ymm_mode: |
13937 | oappend ("YMMWORD PTR "); | |
13938 | break; | |
c0f3af97 | 13939 | case xmmq_mode: |
43234a1e | 13940 | case evex_half_bcst_xmmq_mode: |
c0f3af97 L |
13941 | if (!need_vex) |
13942 | abort (); | |
13943 | ||
13944 | switch (vex.length) | |
13945 | { | |
13946 | case 128: | |
13947 | oappend ("QWORD PTR "); | |
13948 | break; | |
13949 | case 256: | |
13950 | oappend ("XMMWORD PTR "); | |
13951 | break; | |
43234a1e L |
13952 | case 512: |
13953 | oappend ("YMMWORD PTR "); | |
13954 | break; | |
c0f3af97 L |
13955 | default: |
13956 | abort (); | |
13957 | } | |
13958 | break; | |
6c30d220 L |
13959 | case xmm_mb_mode: |
13960 | if (!need_vex) | |
13961 | abort (); | |
13962 | ||
13963 | switch (vex.length) | |
13964 | { | |
13965 | case 128: | |
13966 | case 256: | |
43234a1e | 13967 | case 512: |
6c30d220 L |
13968 | oappend ("BYTE PTR "); |
13969 | break; | |
13970 | default: | |
13971 | abort (); | |
13972 | } | |
13973 | break; | |
13974 | case xmm_mw_mode: | |
13975 | if (!need_vex) | |
13976 | abort (); | |
13977 | ||
13978 | switch (vex.length) | |
13979 | { | |
13980 | case 128: | |
13981 | case 256: | |
43234a1e | 13982 | case 512: |
6c30d220 L |
13983 | oappend ("WORD PTR "); |
13984 | break; | |
13985 | default: | |
13986 | abort (); | |
13987 | } | |
13988 | break; | |
13989 | case xmm_md_mode: | |
13990 | if (!need_vex) | |
13991 | abort (); | |
13992 | ||
13993 | switch (vex.length) | |
13994 | { | |
13995 | case 128: | |
13996 | case 256: | |
43234a1e | 13997 | case 512: |
6c30d220 L |
13998 | oappend ("DWORD PTR "); |
13999 | break; | |
14000 | default: | |
14001 | abort (); | |
14002 | } | |
14003 | break; | |
14004 | case xmm_mq_mode: | |
14005 | if (!need_vex) | |
14006 | abort (); | |
14007 | ||
14008 | switch (vex.length) | |
14009 | { | |
14010 | case 128: | |
14011 | case 256: | |
43234a1e | 14012 | case 512: |
6c30d220 L |
14013 | oappend ("QWORD PTR "); |
14014 | break; | |
14015 | default: | |
14016 | abort (); | |
14017 | } | |
14018 | break; | |
14019 | case xmmdw_mode: | |
14020 | if (!need_vex) | |
14021 | abort (); | |
14022 | ||
14023 | switch (vex.length) | |
14024 | { | |
14025 | case 128: | |
14026 | oappend ("WORD PTR "); | |
14027 | break; | |
14028 | case 256: | |
14029 | oappend ("DWORD PTR "); | |
14030 | break; | |
43234a1e L |
14031 | case 512: |
14032 | oappend ("QWORD PTR "); | |
14033 | break; | |
6c30d220 L |
14034 | default: |
14035 | abort (); | |
14036 | } | |
14037 | break; | |
14038 | case xmmqd_mode: | |
14039 | if (!need_vex) | |
14040 | abort (); | |
14041 | ||
14042 | switch (vex.length) | |
14043 | { | |
14044 | case 128: | |
14045 | oappend ("DWORD PTR "); | |
14046 | break; | |
14047 | case 256: | |
14048 | oappend ("QWORD PTR "); | |
14049 | break; | |
43234a1e L |
14050 | case 512: |
14051 | oappend ("XMMWORD PTR "); | |
14052 | break; | |
6c30d220 L |
14053 | default: |
14054 | abort (); | |
14055 | } | |
14056 | break; | |
c0f3af97 L |
14057 | case ymmq_mode: |
14058 | if (!need_vex) | |
14059 | abort (); | |
14060 | ||
14061 | switch (vex.length) | |
14062 | { | |
14063 | case 128: | |
14064 | oappend ("QWORD PTR "); | |
14065 | break; | |
14066 | case 256: | |
14067 | oappend ("YMMWORD PTR "); | |
14068 | break; | |
43234a1e L |
14069 | case 512: |
14070 | oappend ("ZMMWORD PTR "); | |
14071 | break; | |
c0f3af97 L |
14072 | default: |
14073 | abort (); | |
14074 | } | |
14075 | break; | |
6c30d220 L |
14076 | case ymmxmm_mode: |
14077 | if (!need_vex) | |
14078 | abort (); | |
14079 | ||
14080 | switch (vex.length) | |
14081 | { | |
14082 | case 128: | |
14083 | case 256: | |
14084 | oappend ("XMMWORD PTR "); | |
14085 | break; | |
14086 | default: | |
14087 | abort (); | |
14088 | } | |
14089 | break; | |
fb9c77c7 L |
14090 | case o_mode: |
14091 | oappend ("OWORD PTR "); | |
14092 | break; | |
43234a1e | 14093 | case xmm_mdq_mode: |
0bfee649 | 14094 | case vex_w_dq_mode: |
1c480963 | 14095 | case vex_scalar_w_dq_mode: |
0bfee649 L |
14096 | if (!need_vex) |
14097 | abort (); | |
14098 | ||
14099 | if (vex.w) | |
14100 | oappend ("QWORD PTR "); | |
14101 | else | |
14102 | oappend ("DWORD PTR "); | |
14103 | break; | |
43234a1e L |
14104 | case vex_vsib_d_w_dq_mode: |
14105 | case vex_vsib_q_w_dq_mode: | |
14106 | if (!need_vex) | |
14107 | abort (); | |
14108 | ||
14109 | if (!vex.evex) | |
14110 | { | |
14111 | if (vex.w) | |
14112 | oappend ("QWORD PTR "); | |
14113 | else | |
14114 | oappend ("DWORD PTR "); | |
14115 | } | |
14116 | else | |
14117 | { | |
14118 | if (vex.length != 512) | |
14119 | abort (); | |
14120 | oappend ("ZMMWORD PTR "); | |
14121 | } | |
14122 | break; | |
5fc35d96 IT |
14123 | case vex_vsib_q_w_d_mode: |
14124 | case vex_vsib_d_w_d_mode: | |
14125 | if (!need_vex || !vex.evex || vex.length != 512) | |
14126 | abort (); | |
14127 | ||
14128 | oappend ("YMMWORD PTR "); | |
14129 | ||
14130 | break; | |
43234a1e L |
14131 | case mask_mode: |
14132 | if (!need_vex) | |
14133 | abort (); | |
14134 | /* Currently the only instructions, which allows either mask or | |
14135 | memory operand, are AVX512's KMOVW instructions. They need | |
14136 | Word-sized operand. */ | |
14137 | if (vex.w || vex.length != 128) | |
14138 | abort (); | |
14139 | oappend ("WORD PTR "); | |
14140 | break; | |
6c75cc62 | 14141 | case v_bnd_mode: |
3f31e633 JB |
14142 | default: |
14143 | break; | |
14144 | } | |
14145 | } | |
14146 | ||
252b5132 | 14147 | static void |
c0f3af97 | 14148 | OP_E_register (int bytemode, int sizeflag) |
252b5132 | 14149 | { |
c0f3af97 L |
14150 | int reg = modrm.rm; |
14151 | const char **names; | |
252b5132 | 14152 | |
c0f3af97 L |
14153 | USED_REX (REX_B); |
14154 | if ((rex & REX_B)) | |
14155 | reg += 8; | |
252b5132 | 14156 | |
b6169b20 L |
14157 | if ((sizeflag & SUFFIX_ALWAYS) |
14158 | && (bytemode == b_swap_mode || bytemode == v_swap_mode)) | |
14159 | swap_operand (); | |
14160 | ||
c0f3af97 | 14161 | switch (bytemode) |
252b5132 | 14162 | { |
c0f3af97 | 14163 | case b_mode: |
b6169b20 | 14164 | case b_swap_mode: |
c0f3af97 L |
14165 | USED_REX (0); |
14166 | if (rex) | |
14167 | names = names8rex; | |
14168 | else | |
14169 | names = names8; | |
14170 | break; | |
14171 | case w_mode: | |
14172 | names = names16; | |
14173 | break; | |
14174 | case d_mode: | |
14175 | names = names32; | |
14176 | break; | |
14177 | case q_mode: | |
14178 | names = names64; | |
14179 | break; | |
14180 | case m_mode: | |
6c75cc62 | 14181 | case v_bnd_mode: |
c0f3af97 L |
14182 | names = address_mode == mode_64bit ? names64 : names32; |
14183 | break; | |
7e8b059b L |
14184 | case bnd_mode: |
14185 | names = names_bnd; | |
14186 | break; | |
c0f3af97 | 14187 | case stack_v_mode: |
7bb15c6f | 14188 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
252b5132 | 14189 | { |
c0f3af97 | 14190 | names = names64; |
252b5132 | 14191 | break; |
252b5132 | 14192 | } |
c0f3af97 L |
14193 | bytemode = v_mode; |
14194 | /* FALLTHRU */ | |
14195 | case v_mode: | |
b6169b20 | 14196 | case v_swap_mode: |
c0f3af97 L |
14197 | case dq_mode: |
14198 | case dqb_mode: | |
14199 | case dqd_mode: | |
14200 | case dqw_mode: | |
14201 | USED_REX (REX_W); | |
14202 | if (rex & REX_W) | |
14203 | names = names64; | |
c0f3af97 | 14204 | else |
f16cd0d5 | 14205 | { |
7bb15c6f | 14206 | if ((sizeflag & DFLAG) |
f16cd0d5 L |
14207 | || (bytemode != v_mode |
14208 | && bytemode != v_swap_mode)) | |
14209 | names = names32; | |
14210 | else | |
14211 | names = names16; | |
14212 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14213 | } | |
c0f3af97 | 14214 | break; |
43234a1e L |
14215 | case mask_mode: |
14216 | names = names_mask; | |
14217 | break; | |
c0f3af97 L |
14218 | case 0: |
14219 | return; | |
14220 | default: | |
14221 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
252b5132 RH |
14222 | return; |
14223 | } | |
c0f3af97 L |
14224 | oappend (names[reg]); |
14225 | } | |
14226 | ||
14227 | static void | |
c1e679ec | 14228 | OP_E_memory (int bytemode, int sizeflag) |
c0f3af97 L |
14229 | { |
14230 | bfd_vma disp = 0; | |
14231 | int add = (rex & REX_B) ? 8 : 0; | |
14232 | int riprel = 0; | |
43234a1e L |
14233 | int shift; |
14234 | ||
14235 | if (vex.evex) | |
14236 | { | |
14237 | /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ | |
14238 | if (vex.b | |
14239 | && bytemode != x_mode | |
14240 | && bytemode != evex_half_bcst_xmmq_mode) | |
14241 | { | |
14242 | BadOp (); | |
14243 | return; | |
14244 | } | |
14245 | switch (bytemode) | |
14246 | { | |
14247 | case vex_vsib_d_w_dq_mode: | |
5fc35d96 | 14248 | case vex_vsib_d_w_d_mode: |
eaa9d1ad | 14249 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 14250 | case vex_vsib_q_w_d_mode: |
43234a1e L |
14251 | case evex_x_gscat_mode: |
14252 | case xmm_mdq_mode: | |
14253 | shift = vex.w ? 3 : 2; | |
14254 | break; | |
43234a1e L |
14255 | case x_mode: |
14256 | case evex_half_bcst_xmmq_mode: | |
14257 | if (vex.b) | |
14258 | { | |
14259 | shift = vex.w ? 3 : 2; | |
14260 | break; | |
14261 | } | |
14262 | /* Fall through if vex.b == 0. */ | |
14263 | case xmmqd_mode: | |
14264 | case xmmdw_mode: | |
14265 | case xmmq_mode: | |
14266 | case ymmq_mode: | |
14267 | case evex_x_nobcst_mode: | |
14268 | case x_swap_mode: | |
14269 | switch (vex.length) | |
14270 | { | |
14271 | case 128: | |
14272 | shift = 4; | |
14273 | break; | |
14274 | case 256: | |
14275 | shift = 5; | |
14276 | break; | |
14277 | case 512: | |
14278 | shift = 6; | |
14279 | break; | |
14280 | default: | |
14281 | abort (); | |
14282 | } | |
14283 | break; | |
14284 | case ymm_mode: | |
14285 | shift = 5; | |
14286 | break; | |
14287 | case xmm_mode: | |
14288 | shift = 4; | |
14289 | break; | |
14290 | case xmm_mq_mode: | |
14291 | case q_mode: | |
14292 | case q_scalar_mode: | |
14293 | case q_swap_mode: | |
14294 | case q_scalar_swap_mode: | |
14295 | shift = 3; | |
14296 | break; | |
14297 | case dqd_mode: | |
14298 | case xmm_md_mode: | |
14299 | case d_mode: | |
14300 | case d_scalar_mode: | |
14301 | case d_swap_mode: | |
14302 | case d_scalar_swap_mode: | |
14303 | shift = 2; | |
14304 | break; | |
14305 | case xmm_mw_mode: | |
14306 | shift = 1; | |
14307 | break; | |
14308 | case xmm_mb_mode: | |
14309 | shift = 0; | |
14310 | break; | |
14311 | default: | |
14312 | abort (); | |
14313 | } | |
14314 | /* Make necessary corrections to shift for modes that need it. | |
14315 | For these modes we currently have shift 4, 5 or 6 depending on | |
14316 | vex.length (it corresponds to xmmword, ymmword or zmmword | |
14317 | operand). We might want to make it 3, 4 or 5 (e.g. for | |
14318 | xmmq_mode). In case of broadcast enabled the corrections | |
14319 | aren't needed, as element size is always 32 or 64 bits. */ | |
14320 | if (bytemode == xmmq_mode | |
14321 | || (bytemode == evex_half_bcst_xmmq_mode | |
14322 | && !vex.b)) | |
14323 | shift -= 1; | |
14324 | else if (bytemode == xmmqd_mode) | |
14325 | shift -= 2; | |
14326 | else if (bytemode == xmmdw_mode) | |
14327 | shift -= 3; | |
14328 | } | |
14329 | else | |
14330 | shift = 0; | |
252b5132 | 14331 | |
c0f3af97 | 14332 | USED_REX (REX_B); |
3f31e633 JB |
14333 | if (intel_syntax) |
14334 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
14335 | append_seg (); |
14336 | ||
5d669648 | 14337 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 14338 | { |
5d669648 L |
14339 | /* 32/64 bit address mode */ |
14340 | int havedisp; | |
252b5132 RH |
14341 | int havesib; |
14342 | int havebase; | |
0f7da397 | 14343 | int haveindex; |
20afcfb7 | 14344 | int needindex; |
82c18208 | 14345 | int base, rbase; |
91d6fa6a | 14346 | int vindex = 0; |
252b5132 | 14347 | int scale = 0; |
7e8b059b L |
14348 | int addr32flag = !((sizeflag & AFLAG) |
14349 | || bytemode == v_bnd_mode | |
14350 | || bytemode == bnd_mode); | |
6c30d220 L |
14351 | const char **indexes64 = names64; |
14352 | const char **indexes32 = names32; | |
252b5132 RH |
14353 | |
14354 | havesib = 0; | |
14355 | havebase = 1; | |
0f7da397 | 14356 | haveindex = 0; |
7967e09e | 14357 | base = modrm.rm; |
252b5132 RH |
14358 | |
14359 | if (base == 4) | |
14360 | { | |
14361 | havesib = 1; | |
dfc8cf43 | 14362 | vindex = sib.index; |
161a04f6 L |
14363 | USED_REX (REX_X); |
14364 | if (rex & REX_X) | |
91d6fa6a | 14365 | vindex += 8; |
6c30d220 L |
14366 | switch (bytemode) |
14367 | { | |
14368 | case vex_vsib_d_w_dq_mode: | |
5fc35d96 | 14369 | case vex_vsib_d_w_d_mode: |
6c30d220 | 14370 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 14371 | case vex_vsib_q_w_d_mode: |
6c30d220 L |
14372 | if (!need_vex) |
14373 | abort (); | |
43234a1e L |
14374 | if (vex.evex) |
14375 | { | |
14376 | if (!vex.v) | |
14377 | vindex += 16; | |
14378 | } | |
6c30d220 L |
14379 | |
14380 | haveindex = 1; | |
14381 | switch (vex.length) | |
14382 | { | |
14383 | case 128: | |
7bb15c6f | 14384 | indexes64 = indexes32 = names_xmm; |
6c30d220 L |
14385 | break; |
14386 | case 256: | |
5fc35d96 IT |
14387 | if (!vex.w |
14388 | || bytemode == vex_vsib_q_w_dq_mode | |
14389 | || bytemode == vex_vsib_q_w_d_mode) | |
7bb15c6f | 14390 | indexes64 = indexes32 = names_ymm; |
6c30d220 | 14391 | else |
7bb15c6f | 14392 | indexes64 = indexes32 = names_xmm; |
6c30d220 | 14393 | break; |
43234a1e | 14394 | case 512: |
5fc35d96 IT |
14395 | if (!vex.w |
14396 | || bytemode == vex_vsib_q_w_dq_mode | |
14397 | || bytemode == vex_vsib_q_w_d_mode) | |
43234a1e L |
14398 | indexes64 = indexes32 = names_zmm; |
14399 | else | |
14400 | indexes64 = indexes32 = names_ymm; | |
14401 | break; | |
6c30d220 L |
14402 | default: |
14403 | abort (); | |
14404 | } | |
14405 | break; | |
14406 | default: | |
14407 | haveindex = vindex != 4; | |
14408 | break; | |
14409 | } | |
14410 | scale = sib.scale; | |
14411 | base = sib.base; | |
252b5132 RH |
14412 | codep++; |
14413 | } | |
82c18208 | 14414 | rbase = base + add; |
252b5132 | 14415 | |
7967e09e | 14416 | switch (modrm.mod) |
252b5132 RH |
14417 | { |
14418 | case 0: | |
82c18208 | 14419 | if (base == 5) |
252b5132 RH |
14420 | { |
14421 | havebase = 0; | |
cb712a9e | 14422 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
14423 | riprel = 1; |
14424 | disp = get32s (); | |
252b5132 RH |
14425 | } |
14426 | break; | |
14427 | case 1: | |
14428 | FETCH_DATA (the_info, codep + 1); | |
14429 | disp = *codep++; | |
14430 | if ((disp & 0x80) != 0) | |
14431 | disp -= 0x100; | |
43234a1e L |
14432 | if (vex.evex && shift > 0) |
14433 | disp <<= shift; | |
252b5132 RH |
14434 | break; |
14435 | case 2: | |
52b15da3 | 14436 | disp = get32s (); |
252b5132 RH |
14437 | break; |
14438 | } | |
14439 | ||
20afcfb7 L |
14440 | /* In 32bit mode, we need index register to tell [offset] from |
14441 | [eiz*1 + offset]. */ | |
14442 | needindex = (havesib | |
14443 | && !havebase | |
14444 | && !haveindex | |
14445 | && address_mode == mode_32bit); | |
14446 | havedisp = (havebase | |
14447 | || needindex | |
14448 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 14449 | |
252b5132 | 14450 | if (!intel_syntax) |
82c18208 | 14451 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 14452 | { |
5d669648 L |
14453 | if (havedisp || riprel) |
14454 | print_displacement (scratchbuf, disp); | |
14455 | else | |
14456 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 14457 | oappend (scratchbuf); |
52b15da3 JH |
14458 | if (riprel) |
14459 | { | |
14460 | set_op (disp, 1); | |
87767711 | 14461 | oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)"); |
52b15da3 | 14462 | } |
db6eb5be | 14463 | } |
2da11e11 | 14464 | |
7e8b059b L |
14465 | if ((havebase || haveindex || riprel) |
14466 | && (bytemode != v_bnd_mode) | |
14467 | && (bytemode != bnd_mode)) | |
87767711 JB |
14468 | used_prefixes |= PREFIX_ADDR; |
14469 | ||
5d669648 | 14470 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 14471 | { |
252b5132 | 14472 | *obufp++ = open_char; |
52b15da3 | 14473 | if (intel_syntax && riprel) |
185b1163 L |
14474 | { |
14475 | set_op (disp, 1); | |
87767711 | 14476 | oappend (sizeflag & AFLAG ? "rip" : "eip"); |
185b1163 | 14477 | } |
db6eb5be | 14478 | *obufp = '\0'; |
252b5132 | 14479 | if (havebase) |
7e8b059b | 14480 | oappend (address_mode == mode_64bit && !addr32flag |
82c18208 | 14481 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
14482 | if (havesib) |
14483 | { | |
db51cc60 L |
14484 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
14485 | print index to tell base + index from base. */ | |
14486 | if (scale != 0 | |
20afcfb7 | 14487 | || needindex |
db51cc60 L |
14488 | || haveindex |
14489 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 14490 | { |
9306ca4a | 14491 | if (!intel_syntax || havebase) |
db6eb5be | 14492 | { |
9306ca4a JB |
14493 | *obufp++ = separator_char; |
14494 | *obufp = '\0'; | |
db6eb5be | 14495 | } |
db51cc60 | 14496 | if (haveindex) |
7e8b059b | 14497 | oappend (address_mode == mode_64bit && !addr32flag |
6c30d220 | 14498 | ? indexes64[vindex] : indexes32[vindex]); |
db51cc60 | 14499 | else |
7e8b059b | 14500 | oappend (address_mode == mode_64bit && !addr32flag |
db51cc60 L |
14501 | ? index64 : index32); |
14502 | ||
db6eb5be AM |
14503 | *obufp++ = scale_char; |
14504 | *obufp = '\0'; | |
14505 | sprintf (scratchbuf, "%d", 1 << scale); | |
14506 | oappend (scratchbuf); | |
14507 | } | |
252b5132 | 14508 | } |
185b1163 | 14509 | if (intel_syntax |
82c18208 | 14510 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 14511 | { |
db51cc60 | 14512 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
14513 | { |
14514 | *obufp++ = '+'; | |
14515 | *obufp = '\0'; | |
14516 | } | |
05203043 | 14517 | else if (modrm.mod != 1 && disp != -disp) |
3d456fa1 JB |
14518 | { |
14519 | *obufp++ = '-'; | |
14520 | *obufp = '\0'; | |
14521 | disp = - (bfd_signed_vma) disp; | |
14522 | } | |
14523 | ||
db51cc60 L |
14524 | if (havedisp) |
14525 | print_displacement (scratchbuf, disp); | |
14526 | else | |
14527 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
14528 | oappend (scratchbuf); |
14529 | } | |
252b5132 RH |
14530 | |
14531 | *obufp++ = close_char; | |
db6eb5be | 14532 | *obufp = '\0'; |
252b5132 RH |
14533 | } |
14534 | else if (intel_syntax) | |
db6eb5be | 14535 | { |
82c18208 | 14536 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 14537 | { |
252b5132 RH |
14538 | if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS |
14539 | | PREFIX_ES | PREFIX_FS | PREFIX_GS)) | |
14540 | ; | |
14541 | else | |
14542 | { | |
d708bcba | 14543 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
14544 | oappend (":"); |
14545 | } | |
52b15da3 | 14546 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
14547 | oappend (scratchbuf); |
14548 | } | |
14549 | } | |
252b5132 RH |
14550 | } |
14551 | else | |
f16cd0d5 L |
14552 | { |
14553 | /* 16 bit address mode */ | |
14554 | used_prefixes |= prefixes & PREFIX_ADDR; | |
7967e09e | 14555 | switch (modrm.mod) |
252b5132 RH |
14556 | { |
14557 | case 0: | |
7967e09e | 14558 | if (modrm.rm == 6) |
252b5132 RH |
14559 | { |
14560 | disp = get16 (); | |
14561 | if ((disp & 0x8000) != 0) | |
14562 | disp -= 0x10000; | |
14563 | } | |
14564 | break; | |
14565 | case 1: | |
14566 | FETCH_DATA (the_info, codep + 1); | |
14567 | disp = *codep++; | |
14568 | if ((disp & 0x80) != 0) | |
14569 | disp -= 0x100; | |
14570 | break; | |
14571 | case 2: | |
14572 | disp = get16 (); | |
14573 | if ((disp & 0x8000) != 0) | |
14574 | disp -= 0x10000; | |
14575 | break; | |
14576 | } | |
14577 | ||
14578 | if (!intel_syntax) | |
7967e09e | 14579 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 14580 | { |
5d669648 | 14581 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
14582 | oappend (scratchbuf); |
14583 | } | |
252b5132 | 14584 | |
7967e09e | 14585 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
14586 | { |
14587 | *obufp++ = open_char; | |
db6eb5be | 14588 | *obufp = '\0'; |
7967e09e | 14589 | oappend (index16[modrm.rm]); |
5d669648 L |
14590 | if (intel_syntax |
14591 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 14592 | { |
5d669648 | 14593 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
14594 | { |
14595 | *obufp++ = '+'; | |
14596 | *obufp = '\0'; | |
14597 | } | |
7967e09e | 14598 | else if (modrm.mod != 1) |
3d456fa1 JB |
14599 | { |
14600 | *obufp++ = '-'; | |
14601 | *obufp = '\0'; | |
14602 | disp = - (bfd_signed_vma) disp; | |
14603 | } | |
14604 | ||
5d669648 | 14605 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
14606 | oappend (scratchbuf); |
14607 | } | |
14608 | ||
db6eb5be AM |
14609 | *obufp++ = close_char; |
14610 | *obufp = '\0'; | |
252b5132 | 14611 | } |
3d456fa1 JB |
14612 | else if (intel_syntax) |
14613 | { | |
14614 | if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | |
14615 | | PREFIX_ES | PREFIX_FS | PREFIX_GS)) | |
14616 | ; | |
14617 | else | |
14618 | { | |
14619 | oappend (names_seg[ds_reg - es_reg]); | |
14620 | oappend (":"); | |
14621 | } | |
14622 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
14623 | oappend (scratchbuf); | |
14624 | } | |
252b5132 | 14625 | } |
43234a1e L |
14626 | if (vex.evex && vex.b |
14627 | && (bytemode == x_mode | |
14628 | || bytemode == evex_half_bcst_xmmq_mode)) | |
14629 | { | |
14630 | if (vex.w || bytemode == evex_half_bcst_xmmq_mode) | |
14631 | oappend ("{1to8}"); | |
14632 | else | |
14633 | oappend ("{1to16}"); | |
14634 | } | |
252b5132 RH |
14635 | } |
14636 | ||
c0f3af97 | 14637 | static void |
8b3f93e7 | 14638 | OP_E (int bytemode, int sizeflag) |
c0f3af97 L |
14639 | { |
14640 | /* Skip mod/rm byte. */ | |
14641 | MODRM_CHECK; | |
14642 | codep++; | |
14643 | ||
14644 | if (modrm.mod == 3) | |
14645 | OP_E_register (bytemode, sizeflag); | |
14646 | else | |
c1e679ec | 14647 | OP_E_memory (bytemode, sizeflag); |
c0f3af97 L |
14648 | } |
14649 | ||
252b5132 | 14650 | static void |
26ca5450 | 14651 | OP_G (int bytemode, int sizeflag) |
252b5132 | 14652 | { |
52b15da3 | 14653 | int add = 0; |
161a04f6 L |
14654 | USED_REX (REX_R); |
14655 | if (rex & REX_R) | |
52b15da3 | 14656 | add += 8; |
252b5132 RH |
14657 | switch (bytemode) |
14658 | { | |
14659 | case b_mode: | |
52b15da3 JH |
14660 | USED_REX (0); |
14661 | if (rex) | |
7967e09e | 14662 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 14663 | else |
7967e09e | 14664 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
14665 | break; |
14666 | case w_mode: | |
7967e09e | 14667 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
14668 | break; |
14669 | case d_mode: | |
7967e09e | 14670 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
14671 | break; |
14672 | case q_mode: | |
7967e09e | 14673 | oappend (names64[modrm.reg + add]); |
252b5132 | 14674 | break; |
7e8b059b L |
14675 | case bnd_mode: |
14676 | oappend (names_bnd[modrm.reg]); | |
14677 | break; | |
252b5132 | 14678 | case v_mode: |
9306ca4a | 14679 | case dq_mode: |
42903f7f L |
14680 | case dqb_mode: |
14681 | case dqd_mode: | |
9306ca4a | 14682 | case dqw_mode: |
161a04f6 L |
14683 | USED_REX (REX_W); |
14684 | if (rex & REX_W) | |
7967e09e | 14685 | oappend (names64[modrm.reg + add]); |
252b5132 | 14686 | else |
f16cd0d5 L |
14687 | { |
14688 | if ((sizeflag & DFLAG) || bytemode != v_mode) | |
14689 | oappend (names32[modrm.reg + add]); | |
14690 | else | |
14691 | oappend (names16[modrm.reg + add]); | |
14692 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14693 | } | |
252b5132 | 14694 | break; |
90700ea2 | 14695 | case m_mode: |
cb712a9e | 14696 | if (address_mode == mode_64bit) |
7967e09e | 14697 | oappend (names64[modrm.reg + add]); |
90700ea2 | 14698 | else |
7967e09e | 14699 | oappend (names32[modrm.reg + add]); |
90700ea2 | 14700 | break; |
43234a1e L |
14701 | case mask_mode: |
14702 | oappend (names_mask[modrm.reg + add]); | |
14703 | break; | |
252b5132 RH |
14704 | default: |
14705 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14706 | break; | |
14707 | } | |
14708 | } | |
14709 | ||
52b15da3 | 14710 | static bfd_vma |
26ca5450 | 14711 | get64 (void) |
52b15da3 | 14712 | { |
5dd0794d | 14713 | bfd_vma x; |
52b15da3 | 14714 | #ifdef BFD64 |
5dd0794d AM |
14715 | unsigned int a; |
14716 | unsigned int b; | |
14717 | ||
52b15da3 JH |
14718 | FETCH_DATA (the_info, codep + 8); |
14719 | a = *codep++ & 0xff; | |
14720 | a |= (*codep++ & 0xff) << 8; | |
14721 | a |= (*codep++ & 0xff) << 16; | |
14722 | a |= (*codep++ & 0xff) << 24; | |
5dd0794d | 14723 | b = *codep++ & 0xff; |
52b15da3 JH |
14724 | b |= (*codep++ & 0xff) << 8; |
14725 | b |= (*codep++ & 0xff) << 16; | |
14726 | b |= (*codep++ & 0xff) << 24; | |
14727 | x = a + ((bfd_vma) b << 32); | |
14728 | #else | |
6608db57 | 14729 | abort (); |
5dd0794d | 14730 | x = 0; |
52b15da3 JH |
14731 | #endif |
14732 | return x; | |
14733 | } | |
14734 | ||
14735 | static bfd_signed_vma | |
26ca5450 | 14736 | get32 (void) |
252b5132 | 14737 | { |
52b15da3 | 14738 | bfd_signed_vma x = 0; |
252b5132 RH |
14739 | |
14740 | FETCH_DATA (the_info, codep + 4); | |
52b15da3 JH |
14741 | x = *codep++ & (bfd_signed_vma) 0xff; |
14742 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
14743 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
14744 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
14745 | return x; | |
14746 | } | |
14747 | ||
14748 | static bfd_signed_vma | |
26ca5450 | 14749 | get32s (void) |
52b15da3 JH |
14750 | { |
14751 | bfd_signed_vma x = 0; | |
14752 | ||
14753 | FETCH_DATA (the_info, codep + 4); | |
14754 | x = *codep++ & (bfd_signed_vma) 0xff; | |
14755 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
14756 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
14757 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
14758 | ||
14759 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); | |
14760 | ||
252b5132 RH |
14761 | return x; |
14762 | } | |
14763 | ||
14764 | static int | |
26ca5450 | 14765 | get16 (void) |
252b5132 RH |
14766 | { |
14767 | int x = 0; | |
14768 | ||
14769 | FETCH_DATA (the_info, codep + 2); | |
14770 | x = *codep++ & 0xff; | |
14771 | x |= (*codep++ & 0xff) << 8; | |
14772 | return x; | |
14773 | } | |
14774 | ||
14775 | static void | |
26ca5450 | 14776 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
14777 | { |
14778 | op_index[op_ad] = op_ad; | |
cb712a9e | 14779 | if (address_mode == mode_64bit) |
7081ff04 AJ |
14780 | { |
14781 | op_address[op_ad] = op; | |
14782 | op_riprel[op_ad] = riprel; | |
14783 | } | |
14784 | else | |
14785 | { | |
14786 | /* Mask to get a 32-bit address. */ | |
14787 | op_address[op_ad] = op & 0xffffffff; | |
14788 | op_riprel[op_ad] = riprel & 0xffffffff; | |
14789 | } | |
252b5132 RH |
14790 | } |
14791 | ||
14792 | static void | |
26ca5450 | 14793 | OP_REG (int code, int sizeflag) |
252b5132 | 14794 | { |
2da11e11 | 14795 | const char *s; |
9b60702d | 14796 | int add; |
de882298 RM |
14797 | |
14798 | switch (code) | |
14799 | { | |
14800 | case es_reg: case ss_reg: case cs_reg: | |
14801 | case ds_reg: case fs_reg: case gs_reg: | |
14802 | oappend (names_seg[code - es_reg]); | |
14803 | return; | |
14804 | } | |
14805 | ||
161a04f6 L |
14806 | USED_REX (REX_B); |
14807 | if (rex & REX_B) | |
52b15da3 | 14808 | add = 8; |
9b60702d L |
14809 | else |
14810 | add = 0; | |
52b15da3 JH |
14811 | |
14812 | switch (code) | |
14813 | { | |
52b15da3 JH |
14814 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
14815 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
14816 | s = names16[code - ax_reg + add]; | |
14817 | break; | |
52b15da3 JH |
14818 | case al_reg: case ah_reg: case cl_reg: case ch_reg: |
14819 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
14820 | USED_REX (0); | |
14821 | if (rex) | |
14822 | s = names8rex[code - al_reg + add]; | |
14823 | else | |
14824 | s = names8[code - al_reg]; | |
14825 | break; | |
6439fc28 AM |
14826 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
14827 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
7bb15c6f | 14828 | if (address_mode == mode_64bit |
6c067bbb | 14829 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
14830 | { |
14831 | s = names64[code - rAX_reg + add]; | |
14832 | break; | |
14833 | } | |
14834 | code += eAX_reg - rAX_reg; | |
6608db57 | 14835 | /* Fall through. */ |
52b15da3 JH |
14836 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
14837 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
14838 | USED_REX (REX_W); |
14839 | if (rex & REX_W) | |
52b15da3 | 14840 | s = names64[code - eAX_reg + add]; |
52b15da3 | 14841 | else |
f16cd0d5 L |
14842 | { |
14843 | if (sizeflag & DFLAG) | |
14844 | s = names32[code - eAX_reg + add]; | |
14845 | else | |
14846 | s = names16[code - eAX_reg + add]; | |
14847 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14848 | } | |
52b15da3 | 14849 | break; |
52b15da3 JH |
14850 | default: |
14851 | s = INTERNAL_DISASSEMBLER_ERROR; | |
14852 | break; | |
14853 | } | |
14854 | oappend (s); | |
14855 | } | |
14856 | ||
14857 | static void | |
26ca5450 | 14858 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
14859 | { |
14860 | const char *s; | |
252b5132 RH |
14861 | |
14862 | switch (code) | |
14863 | { | |
14864 | case indir_dx_reg: | |
d708bcba | 14865 | if (intel_syntax) |
52fd6d94 | 14866 | s = "dx"; |
d708bcba | 14867 | else |
db6eb5be | 14868 | s = "(%dx)"; |
252b5132 RH |
14869 | break; |
14870 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: | |
14871 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
14872 | s = names16[code - ax_reg]; | |
14873 | break; | |
14874 | case es_reg: case ss_reg: case cs_reg: | |
14875 | case ds_reg: case fs_reg: case gs_reg: | |
14876 | s = names_seg[code - es_reg]; | |
14877 | break; | |
14878 | case al_reg: case ah_reg: case cl_reg: case ch_reg: | |
14879 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
52b15da3 JH |
14880 | USED_REX (0); |
14881 | if (rex) | |
14882 | s = names8rex[code - al_reg]; | |
14883 | else | |
14884 | s = names8[code - al_reg]; | |
252b5132 RH |
14885 | break; |
14886 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: | |
14887 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
14888 | USED_REX (REX_W); |
14889 | if (rex & REX_W) | |
52b15da3 | 14890 | s = names64[code - eAX_reg]; |
252b5132 | 14891 | else |
f16cd0d5 L |
14892 | { |
14893 | if (sizeflag & DFLAG) | |
14894 | s = names32[code - eAX_reg]; | |
14895 | else | |
14896 | s = names16[code - eAX_reg]; | |
14897 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14898 | } | |
252b5132 | 14899 | break; |
52fd6d94 | 14900 | case z_mode_ax_reg: |
161a04f6 | 14901 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
14902 | s = *names32; |
14903 | else | |
14904 | s = *names16; | |
161a04f6 | 14905 | if (!(rex & REX_W)) |
52fd6d94 JB |
14906 | used_prefixes |= (prefixes & PREFIX_DATA); |
14907 | break; | |
252b5132 RH |
14908 | default: |
14909 | s = INTERNAL_DISASSEMBLER_ERROR; | |
14910 | break; | |
14911 | } | |
14912 | oappend (s); | |
14913 | } | |
14914 | ||
14915 | static void | |
26ca5450 | 14916 | OP_I (int bytemode, int sizeflag) |
252b5132 | 14917 | { |
52b15da3 JH |
14918 | bfd_signed_vma op; |
14919 | bfd_signed_vma mask = -1; | |
252b5132 RH |
14920 | |
14921 | switch (bytemode) | |
14922 | { | |
14923 | case b_mode: | |
14924 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
14925 | op = *codep++; |
14926 | mask = 0xff; | |
14927 | break; | |
14928 | case q_mode: | |
cb712a9e | 14929 | if (address_mode == mode_64bit) |
6439fc28 AM |
14930 | { |
14931 | op = get32s (); | |
14932 | break; | |
14933 | } | |
6608db57 | 14934 | /* Fall through. */ |
252b5132 | 14935 | case v_mode: |
161a04f6 L |
14936 | USED_REX (REX_W); |
14937 | if (rex & REX_W) | |
52b15da3 | 14938 | op = get32s (); |
252b5132 | 14939 | else |
52b15da3 | 14940 | { |
f16cd0d5 L |
14941 | if (sizeflag & DFLAG) |
14942 | { | |
14943 | op = get32 (); | |
14944 | mask = 0xffffffff; | |
14945 | } | |
14946 | else | |
14947 | { | |
14948 | op = get16 (); | |
14949 | mask = 0xfffff; | |
14950 | } | |
14951 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 14952 | } |
252b5132 RH |
14953 | break; |
14954 | case w_mode: | |
52b15da3 | 14955 | mask = 0xfffff; |
252b5132 RH |
14956 | op = get16 (); |
14957 | break; | |
9306ca4a JB |
14958 | case const_1_mode: |
14959 | if (intel_syntax) | |
6c067bbb | 14960 | oappend ("1"); |
9306ca4a | 14961 | return; |
252b5132 RH |
14962 | default: |
14963 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14964 | return; | |
14965 | } | |
14966 | ||
52b15da3 JH |
14967 | op &= mask; |
14968 | scratchbuf[0] = '$'; | |
d708bcba | 14969 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 14970 | oappend_maybe_intel (scratchbuf); |
52b15da3 JH |
14971 | scratchbuf[0] = '\0'; |
14972 | } | |
14973 | ||
14974 | static void | |
26ca5450 | 14975 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 JH |
14976 | { |
14977 | bfd_signed_vma op; | |
14978 | bfd_signed_vma mask = -1; | |
14979 | ||
cb712a9e | 14980 | if (address_mode != mode_64bit) |
6439fc28 AM |
14981 | { |
14982 | OP_I (bytemode, sizeflag); | |
14983 | return; | |
14984 | } | |
14985 | ||
52b15da3 JH |
14986 | switch (bytemode) |
14987 | { | |
14988 | case b_mode: | |
14989 | FETCH_DATA (the_info, codep + 1); | |
14990 | op = *codep++; | |
14991 | mask = 0xff; | |
14992 | break; | |
14993 | case v_mode: | |
161a04f6 L |
14994 | USED_REX (REX_W); |
14995 | if (rex & REX_W) | |
52b15da3 | 14996 | op = get64 (); |
52b15da3 JH |
14997 | else |
14998 | { | |
f16cd0d5 L |
14999 | if (sizeflag & DFLAG) |
15000 | { | |
15001 | op = get32 (); | |
15002 | mask = 0xffffffff; | |
15003 | } | |
15004 | else | |
15005 | { | |
15006 | op = get16 (); | |
15007 | mask = 0xfffff; | |
15008 | } | |
15009 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 15010 | } |
52b15da3 JH |
15011 | break; |
15012 | case w_mode: | |
15013 | mask = 0xfffff; | |
15014 | op = get16 (); | |
15015 | break; | |
15016 | default: | |
15017 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15018 | return; | |
15019 | } | |
15020 | ||
15021 | op &= mask; | |
15022 | scratchbuf[0] = '$'; | |
d708bcba | 15023 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 15024 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15025 | scratchbuf[0] = '\0'; |
15026 | } | |
15027 | ||
15028 | static void | |
26ca5450 | 15029 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 15030 | { |
52b15da3 | 15031 | bfd_signed_vma op; |
252b5132 RH |
15032 | |
15033 | switch (bytemode) | |
15034 | { | |
15035 | case b_mode: | |
e3949f17 | 15036 | case b_T_mode: |
252b5132 RH |
15037 | FETCH_DATA (the_info, codep + 1); |
15038 | op = *codep++; | |
15039 | if ((op & 0x80) != 0) | |
15040 | op -= 0x100; | |
e3949f17 L |
15041 | if (bytemode == b_T_mode) |
15042 | { | |
15043 | if (address_mode != mode_64bit | |
7bb15c6f | 15044 | || !((sizeflag & DFLAG) || (rex & REX_W))) |
e3949f17 | 15045 | { |
6c067bbb RM |
15046 | /* The operand-size prefix is overridden by a REX prefix. */ |
15047 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
e3949f17 L |
15048 | op &= 0xffffffff; |
15049 | else | |
15050 | op &= 0xffff; | |
15051 | } | |
15052 | } | |
15053 | else | |
15054 | { | |
15055 | if (!(rex & REX_W)) | |
15056 | { | |
15057 | if (sizeflag & DFLAG) | |
15058 | op &= 0xffffffff; | |
15059 | else | |
15060 | op &= 0xffff; | |
15061 | } | |
15062 | } | |
252b5132 RH |
15063 | break; |
15064 | case v_mode: | |
7bb15c6f RM |
15065 | /* The operand-size prefix is overridden by a REX prefix. */ |
15066 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
52b15da3 | 15067 | op = get32s (); |
252b5132 | 15068 | else |
d9e3625e | 15069 | op = get16 (); |
252b5132 RH |
15070 | break; |
15071 | default: | |
15072 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15073 | return; | |
15074 | } | |
52b15da3 JH |
15075 | |
15076 | scratchbuf[0] = '$'; | |
15077 | print_operand_value (scratchbuf + 1, 1, op); | |
9ce09ba2 | 15078 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15079 | } |
15080 | ||
15081 | static void | |
26ca5450 | 15082 | OP_J (int bytemode, int sizeflag) |
252b5132 | 15083 | { |
52b15da3 | 15084 | bfd_vma disp; |
7081ff04 | 15085 | bfd_vma mask = -1; |
65ca155d | 15086 | bfd_vma segment = 0; |
252b5132 RH |
15087 | |
15088 | switch (bytemode) | |
15089 | { | |
15090 | case b_mode: | |
15091 | FETCH_DATA (the_info, codep + 1); | |
15092 | disp = *codep++; | |
15093 | if ((disp & 0x80) != 0) | |
15094 | disp -= 0x100; | |
15095 | break; | |
15096 | case v_mode: | |
f16cd0d5 | 15097 | USED_REX (REX_W); |
161a04f6 | 15098 | if ((sizeflag & DFLAG) || (rex & REX_W)) |
52b15da3 | 15099 | disp = get32s (); |
252b5132 RH |
15100 | else |
15101 | { | |
15102 | disp = get16 (); | |
206717e8 L |
15103 | if ((disp & 0x8000) != 0) |
15104 | disp -= 0x10000; | |
65ca155d L |
15105 | /* In 16bit mode, address is wrapped around at 64k within |
15106 | the same segment. Otherwise, a data16 prefix on a jump | |
15107 | instruction means that the pc is masked to 16 bits after | |
15108 | the displacement is added! */ | |
15109 | mask = 0xffff; | |
15110 | if ((prefixes & PREFIX_DATA) == 0) | |
15111 | segment = ((start_pc + codep - start_codep) | |
15112 | & ~((bfd_vma) 0xffff)); | |
252b5132 | 15113 | } |
f16cd0d5 L |
15114 | if (!(rex & REX_W)) |
15115 | used_prefixes |= (prefixes & PREFIX_DATA); | |
252b5132 RH |
15116 | break; |
15117 | default: | |
15118 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15119 | return; | |
15120 | } | |
42d5f9c6 | 15121 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
52b15da3 JH |
15122 | set_op (disp, 0); |
15123 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
15124 | oappend (scratchbuf); |
15125 | } | |
15126 | ||
252b5132 | 15127 | static void |
ed7841b3 | 15128 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 15129 | { |
ed7841b3 | 15130 | if (bytemode == w_mode) |
7967e09e | 15131 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 15132 | else |
7967e09e | 15133 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
15134 | } |
15135 | ||
15136 | static void | |
26ca5450 | 15137 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
15138 | { |
15139 | int seg, offset; | |
15140 | ||
c608c12e | 15141 | if (sizeflag & DFLAG) |
252b5132 | 15142 | { |
c608c12e AM |
15143 | offset = get32 (); |
15144 | seg = get16 (); | |
252b5132 | 15145 | } |
c608c12e AM |
15146 | else |
15147 | { | |
15148 | offset = get16 (); | |
15149 | seg = get16 (); | |
15150 | } | |
7d421014 | 15151 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 15152 | if (intel_syntax) |
3f31e633 | 15153 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
15154 | else |
15155 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 15156 | oappend (scratchbuf); |
252b5132 RH |
15157 | } |
15158 | ||
252b5132 | 15159 | static void |
3f31e633 | 15160 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 15161 | { |
52b15da3 | 15162 | bfd_vma off; |
252b5132 | 15163 | |
3f31e633 JB |
15164 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
15165 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
15166 | append_seg (); |
15167 | ||
cb712a9e | 15168 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
15169 | off = get32 (); |
15170 | else | |
15171 | off = get16 (); | |
15172 | ||
15173 | if (intel_syntax) | |
15174 | { | |
15175 | if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | |
db6eb5be | 15176 | | PREFIX_ES | PREFIX_FS | PREFIX_GS))) |
252b5132 | 15177 | { |
d708bcba | 15178 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
15179 | oappend (":"); |
15180 | } | |
15181 | } | |
52b15da3 JH |
15182 | print_operand_value (scratchbuf, 1, off); |
15183 | oappend (scratchbuf); | |
15184 | } | |
6439fc28 | 15185 | |
52b15da3 | 15186 | static void |
3f31e633 | 15187 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
15188 | { |
15189 | bfd_vma off; | |
15190 | ||
539e75ad L |
15191 | if (address_mode != mode_64bit |
15192 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
15193 | { |
15194 | OP_OFF (bytemode, sizeflag); | |
15195 | return; | |
15196 | } | |
15197 | ||
3f31e633 JB |
15198 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
15199 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
15200 | append_seg (); |
15201 | ||
6608db57 | 15202 | off = get64 (); |
52b15da3 JH |
15203 | |
15204 | if (intel_syntax) | |
15205 | { | |
15206 | if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | |
db6eb5be | 15207 | | PREFIX_ES | PREFIX_FS | PREFIX_GS))) |
52b15da3 | 15208 | { |
d708bcba | 15209 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
15210 | oappend (":"); |
15211 | } | |
15212 | } | |
15213 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
15214 | oappend (scratchbuf); |
15215 | } | |
15216 | ||
15217 | static void | |
26ca5450 | 15218 | ptr_reg (int code, int sizeflag) |
252b5132 | 15219 | { |
2da11e11 | 15220 | const char *s; |
d708bcba | 15221 | |
1d9f512f | 15222 | *obufp++ = open_char; |
20f0a1fc | 15223 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 15224 | if (address_mode == mode_64bit) |
c1a64871 JH |
15225 | { |
15226 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 15227 | s = names32[code - eAX_reg]; |
c1a64871 | 15228 | else |
db6eb5be | 15229 | s = names64[code - eAX_reg]; |
c1a64871 | 15230 | } |
52b15da3 | 15231 | else if (sizeflag & AFLAG) |
252b5132 RH |
15232 | s = names32[code - eAX_reg]; |
15233 | else | |
15234 | s = names16[code - eAX_reg]; | |
15235 | oappend (s); | |
1d9f512f AM |
15236 | *obufp++ = close_char; |
15237 | *obufp = 0; | |
252b5132 RH |
15238 | } |
15239 | ||
15240 | static void | |
26ca5450 | 15241 | OP_ESreg (int code, int sizeflag) |
252b5132 | 15242 | { |
9306ca4a | 15243 | if (intel_syntax) |
52fd6d94 JB |
15244 | { |
15245 | switch (codep[-1]) | |
15246 | { | |
15247 | case 0x6d: /* insw/insl */ | |
15248 | intel_operand_size (z_mode, sizeflag); | |
15249 | break; | |
15250 | case 0xa5: /* movsw/movsl/movsq */ | |
15251 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
15252 | case 0xab: /* stosw/stosl */ | |
15253 | case 0xaf: /* scasw/scasl */ | |
15254 | intel_operand_size (v_mode, sizeflag); | |
15255 | break; | |
15256 | default: | |
15257 | intel_operand_size (b_mode, sizeflag); | |
15258 | } | |
15259 | } | |
9ce09ba2 | 15260 | oappend_maybe_intel ("%es:"); |
252b5132 RH |
15261 | ptr_reg (code, sizeflag); |
15262 | } | |
15263 | ||
15264 | static void | |
26ca5450 | 15265 | OP_DSreg (int code, int sizeflag) |
252b5132 | 15266 | { |
9306ca4a | 15267 | if (intel_syntax) |
52fd6d94 JB |
15268 | { |
15269 | switch (codep[-1]) | |
15270 | { | |
15271 | case 0x6f: /* outsw/outsl */ | |
15272 | intel_operand_size (z_mode, sizeflag); | |
15273 | break; | |
15274 | case 0xa5: /* movsw/movsl/movsq */ | |
15275 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
15276 | case 0xad: /* lodsw/lodsl/lodsq */ | |
15277 | intel_operand_size (v_mode, sizeflag); | |
15278 | break; | |
15279 | default: | |
15280 | intel_operand_size (b_mode, sizeflag); | |
15281 | } | |
15282 | } | |
252b5132 RH |
15283 | if ((prefixes |
15284 | & (PREFIX_CS | |
15285 | | PREFIX_DS | |
15286 | | PREFIX_SS | |
15287 | | PREFIX_ES | |
15288 | | PREFIX_FS | |
15289 | | PREFIX_GS)) == 0) | |
15290 | prefixes |= PREFIX_DS; | |
6608db57 | 15291 | append_seg (); |
252b5132 RH |
15292 | ptr_reg (code, sizeflag); |
15293 | } | |
15294 | ||
252b5132 | 15295 | static void |
26ca5450 | 15296 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15297 | { |
9b60702d | 15298 | int add; |
161a04f6 | 15299 | if (rex & REX_R) |
c4a530c5 | 15300 | { |
161a04f6 | 15301 | USED_REX (REX_R); |
c4a530c5 JB |
15302 | add = 8; |
15303 | } | |
cb712a9e | 15304 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 15305 | { |
f16cd0d5 | 15306 | all_prefixes[last_lock_prefix] = 0; |
c4a530c5 JB |
15307 | used_prefixes |= PREFIX_LOCK; |
15308 | add = 8; | |
15309 | } | |
9b60702d L |
15310 | else |
15311 | add = 0; | |
7967e09e | 15312 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
9ce09ba2 | 15313 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15314 | } |
15315 | ||
252b5132 | 15316 | static void |
26ca5450 | 15317 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15318 | { |
9b60702d | 15319 | int add; |
161a04f6 L |
15320 | USED_REX (REX_R); |
15321 | if (rex & REX_R) | |
52b15da3 | 15322 | add = 8; |
9b60702d L |
15323 | else |
15324 | add = 0; | |
d708bcba | 15325 | if (intel_syntax) |
7967e09e | 15326 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
d708bcba | 15327 | else |
7967e09e | 15328 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
15329 | oappend (scratchbuf); |
15330 | } | |
15331 | ||
252b5132 | 15332 | static void |
26ca5450 | 15333 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15334 | { |
7967e09e | 15335 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
9ce09ba2 | 15336 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15337 | } |
15338 | ||
15339 | static void | |
6f74c397 | 15340 | OP_R (int bytemode, int sizeflag) |
252b5132 | 15341 | { |
7967e09e | 15342 | if (modrm.mod == 3) |
2da11e11 AM |
15343 | OP_E (bytemode, sizeflag); |
15344 | else | |
6608db57 | 15345 | BadOp (); |
252b5132 RH |
15346 | } |
15347 | ||
15348 | static void | |
26ca5450 | 15349 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15350 | { |
b9733481 L |
15351 | int reg = modrm.reg; |
15352 | const char **names; | |
15353 | ||
041bd2e0 JH |
15354 | used_prefixes |= (prefixes & PREFIX_DATA); |
15355 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 15356 | { |
b9733481 | 15357 | names = names_xmm; |
161a04f6 L |
15358 | USED_REX (REX_R); |
15359 | if (rex & REX_R) | |
b9733481 | 15360 | reg += 8; |
20f0a1fc | 15361 | } |
041bd2e0 | 15362 | else |
b9733481 L |
15363 | names = names_mm; |
15364 | oappend (names[reg]); | |
252b5132 RH |
15365 | } |
15366 | ||
c608c12e | 15367 | static void |
c0f3af97 | 15368 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 15369 | { |
b9733481 L |
15370 | int reg = modrm.reg; |
15371 | const char **names; | |
15372 | ||
161a04f6 L |
15373 | USED_REX (REX_R); |
15374 | if (rex & REX_R) | |
b9733481 | 15375 | reg += 8; |
43234a1e L |
15376 | if (vex.evex) |
15377 | { | |
15378 | if (!vex.r) | |
15379 | reg += 16; | |
15380 | } | |
15381 | ||
539f890d L |
15382 | if (need_vex |
15383 | && bytemode != xmm_mode | |
43234a1e L |
15384 | && bytemode != xmmq_mode |
15385 | && bytemode != evex_half_bcst_xmmq_mode | |
15386 | && bytemode != ymm_mode | |
539f890d | 15387 | && bytemode != scalar_mode) |
c0f3af97 L |
15388 | { |
15389 | switch (vex.length) | |
15390 | { | |
15391 | case 128: | |
b9733481 | 15392 | names = names_xmm; |
c0f3af97 L |
15393 | break; |
15394 | case 256: | |
5fc35d96 IT |
15395 | if (vex.w |
15396 | || (bytemode != vex_vsib_q_w_dq_mode | |
15397 | && bytemode != vex_vsib_q_w_d_mode)) | |
6c30d220 L |
15398 | names = names_ymm; |
15399 | else | |
15400 | names = names_xmm; | |
c0f3af97 | 15401 | break; |
43234a1e L |
15402 | case 512: |
15403 | names = names_zmm; | |
15404 | break; | |
c0f3af97 L |
15405 | default: |
15406 | abort (); | |
15407 | } | |
15408 | } | |
43234a1e L |
15409 | else if (bytemode == xmmq_mode |
15410 | || bytemode == evex_half_bcst_xmmq_mode) | |
15411 | { | |
15412 | switch (vex.length) | |
15413 | { | |
15414 | case 128: | |
15415 | case 256: | |
15416 | names = names_xmm; | |
15417 | break; | |
15418 | case 512: | |
15419 | names = names_ymm; | |
15420 | break; | |
15421 | default: | |
15422 | abort (); | |
15423 | } | |
15424 | } | |
15425 | else if (bytemode == ymm_mode) | |
15426 | names = names_ymm; | |
c0f3af97 | 15427 | else |
b9733481 L |
15428 | names = names_xmm; |
15429 | oappend (names[reg]); | |
c608c12e AM |
15430 | } |
15431 | ||
252b5132 | 15432 | static void |
26ca5450 | 15433 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 15434 | { |
b9733481 L |
15435 | int reg; |
15436 | const char **names; | |
15437 | ||
7967e09e | 15438 | if (modrm.mod != 3) |
252b5132 | 15439 | { |
b6169b20 L |
15440 | if (intel_syntax |
15441 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
9306ca4a JB |
15442 | { |
15443 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
15444 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 15445 | } |
252b5132 RH |
15446 | OP_E (bytemode, sizeflag); |
15447 | return; | |
15448 | } | |
15449 | ||
b6169b20 L |
15450 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
15451 | swap_operand (); | |
15452 | ||
6608db57 | 15453 | /* Skip mod/rm byte. */ |
4bba6815 | 15454 | MODRM_CHECK; |
252b5132 | 15455 | codep++; |
041bd2e0 | 15456 | used_prefixes |= (prefixes & PREFIX_DATA); |
b9733481 | 15457 | reg = modrm.rm; |
041bd2e0 | 15458 | if (prefixes & PREFIX_DATA) |
20f0a1fc | 15459 | { |
b9733481 | 15460 | names = names_xmm; |
161a04f6 L |
15461 | USED_REX (REX_B); |
15462 | if (rex & REX_B) | |
b9733481 | 15463 | reg += 8; |
20f0a1fc | 15464 | } |
041bd2e0 | 15465 | else |
b9733481 L |
15466 | names = names_mm; |
15467 | oappend (names[reg]); | |
252b5132 RH |
15468 | } |
15469 | ||
246c51aa L |
15470 | /* cvt* are the only instructions in sse2 which have |
15471 | both SSE and MMX operands and also have 0x66 prefix | |
15472 | in their opcode. 0x66 was originally used to differentiate | |
15473 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
15474 | cvt* separately using OP_EMC and OP_MXC */ |
15475 | static void | |
15476 | OP_EMC (int bytemode, int sizeflag) | |
15477 | { | |
7967e09e | 15478 | if (modrm.mod != 3) |
4d9567e0 MM |
15479 | { |
15480 | if (intel_syntax && bytemode == v_mode) | |
15481 | { | |
15482 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
15483 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 15484 | } |
4d9567e0 MM |
15485 | OP_E (bytemode, sizeflag); |
15486 | return; | |
15487 | } | |
246c51aa | 15488 | |
4d9567e0 MM |
15489 | /* Skip mod/rm byte. */ |
15490 | MODRM_CHECK; | |
15491 | codep++; | |
15492 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 15493 | oappend (names_mm[modrm.rm]); |
4d9567e0 MM |
15494 | } |
15495 | ||
15496 | static void | |
15497 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15498 | { | |
15499 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 15500 | oappend (names_mm[modrm.reg]); |
4d9567e0 MM |
15501 | } |
15502 | ||
c608c12e | 15503 | static void |
26ca5450 | 15504 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 15505 | { |
b9733481 L |
15506 | int reg; |
15507 | const char **names; | |
d6f574e0 L |
15508 | |
15509 | /* Skip mod/rm byte. */ | |
15510 | MODRM_CHECK; | |
15511 | codep++; | |
15512 | ||
7967e09e | 15513 | if (modrm.mod != 3) |
c608c12e | 15514 | { |
c1e679ec | 15515 | OP_E_memory (bytemode, sizeflag); |
c608c12e AM |
15516 | return; |
15517 | } | |
d6f574e0 | 15518 | |
b9733481 | 15519 | reg = modrm.rm; |
161a04f6 L |
15520 | USED_REX (REX_B); |
15521 | if (rex & REX_B) | |
b9733481 | 15522 | reg += 8; |
43234a1e L |
15523 | if (vex.evex) |
15524 | { | |
15525 | USED_REX (REX_X); | |
15526 | if ((rex & REX_X)) | |
15527 | reg += 16; | |
15528 | } | |
c608c12e | 15529 | |
b6169b20 | 15530 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 L |
15531 | && (bytemode == x_swap_mode |
15532 | || bytemode == d_swap_mode | |
7bb15c6f | 15533 | || bytemode == d_scalar_swap_mode |
539f890d L |
15534 | || bytemode == q_swap_mode |
15535 | || bytemode == q_scalar_swap_mode)) | |
b6169b20 L |
15536 | swap_operand (); |
15537 | ||
c0f3af97 L |
15538 | if (need_vex |
15539 | && bytemode != xmm_mode | |
6c30d220 L |
15540 | && bytemode != xmmdw_mode |
15541 | && bytemode != xmmqd_mode | |
15542 | && bytemode != xmm_mb_mode | |
15543 | && bytemode != xmm_mw_mode | |
15544 | && bytemode != xmm_md_mode | |
15545 | && bytemode != xmm_mq_mode | |
43234a1e | 15546 | && bytemode != xmm_mdq_mode |
539f890d | 15547 | && bytemode != xmmq_mode |
43234a1e L |
15548 | && bytemode != evex_half_bcst_xmmq_mode |
15549 | && bytemode != ymm_mode | |
539f890d | 15550 | && bytemode != d_scalar_mode |
7bb15c6f | 15551 | && bytemode != d_scalar_swap_mode |
539f890d | 15552 | && bytemode != q_scalar_mode |
1c480963 L |
15553 | && bytemode != q_scalar_swap_mode |
15554 | && bytemode != vex_scalar_w_dq_mode) | |
c0f3af97 L |
15555 | { |
15556 | switch (vex.length) | |
15557 | { | |
15558 | case 128: | |
b9733481 | 15559 | names = names_xmm; |
c0f3af97 L |
15560 | break; |
15561 | case 256: | |
b9733481 | 15562 | names = names_ymm; |
c0f3af97 | 15563 | break; |
43234a1e L |
15564 | case 512: |
15565 | names = names_zmm; | |
15566 | break; | |
c0f3af97 L |
15567 | default: |
15568 | abort (); | |
15569 | } | |
15570 | } | |
43234a1e L |
15571 | else if (bytemode == xmmq_mode |
15572 | || bytemode == evex_half_bcst_xmmq_mode) | |
15573 | { | |
15574 | switch (vex.length) | |
15575 | { | |
15576 | case 128: | |
15577 | case 256: | |
15578 | names = names_xmm; | |
15579 | break; | |
15580 | case 512: | |
15581 | names = names_ymm; | |
15582 | break; | |
15583 | default: | |
15584 | abort (); | |
15585 | } | |
15586 | } | |
15587 | else if (bytemode == ymm_mode) | |
15588 | names = names_ymm; | |
c0f3af97 | 15589 | else |
b9733481 L |
15590 | names = names_xmm; |
15591 | oappend (names[reg]); | |
c608c12e AM |
15592 | } |
15593 | ||
252b5132 | 15594 | static void |
26ca5450 | 15595 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 15596 | { |
7967e09e | 15597 | if (modrm.mod == 3) |
2da11e11 AM |
15598 | OP_EM (bytemode, sizeflag); |
15599 | else | |
6608db57 | 15600 | BadOp (); |
252b5132 RH |
15601 | } |
15602 | ||
992aaec9 | 15603 | static void |
26ca5450 | 15604 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 15605 | { |
7967e09e | 15606 | if (modrm.mod == 3) |
992aaec9 AM |
15607 | OP_EX (bytemode, sizeflag); |
15608 | else | |
6608db57 | 15609 | BadOp (); |
992aaec9 AM |
15610 | } |
15611 | ||
cc0ec051 AM |
15612 | static void |
15613 | OP_M (int bytemode, int sizeflag) | |
15614 | { | |
7967e09e | 15615 | if (modrm.mod == 3) |
75413a22 L |
15616 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
15617 | BadOp (); | |
cc0ec051 AM |
15618 | else |
15619 | OP_E (bytemode, sizeflag); | |
15620 | } | |
15621 | ||
15622 | static void | |
15623 | OP_0f07 (int bytemode, int sizeflag) | |
15624 | { | |
7967e09e | 15625 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
15626 | BadOp (); |
15627 | else | |
15628 | OP_E (bytemode, sizeflag); | |
15629 | } | |
15630 | ||
46e883c5 | 15631 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 15632 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 15633 | |
cc0ec051 | 15634 | static void |
46e883c5 | 15635 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 15636 | { |
8b38ad71 L |
15637 | if ((prefixes & PREFIX_DATA) != 0 |
15638 | || (rex != 0 | |
15639 | && rex != 0x48 | |
15640 | && address_mode == mode_64bit)) | |
46e883c5 L |
15641 | OP_REG (bytemode, sizeflag); |
15642 | else | |
15643 | strcpy (obuf, "nop"); | |
15644 | } | |
15645 | ||
15646 | static void | |
15647 | NOP_Fixup2 (int bytemode, int sizeflag) | |
15648 | { | |
8b38ad71 L |
15649 | if ((prefixes & PREFIX_DATA) != 0 |
15650 | || (rex != 0 | |
15651 | && rex != 0x48 | |
15652 | && address_mode == mode_64bit)) | |
46e883c5 | 15653 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
15654 | } |
15655 | ||
84037f8c | 15656 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
15657 | /* 00 */ NULL, NULL, NULL, NULL, |
15658 | /* 04 */ NULL, NULL, NULL, NULL, | |
15659 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 15660 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
15661 | /* 10 */ NULL, NULL, NULL, NULL, |
15662 | /* 14 */ NULL, NULL, NULL, NULL, | |
15663 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 15664 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
15665 | /* 20 */ NULL, NULL, NULL, NULL, |
15666 | /* 24 */ NULL, NULL, NULL, NULL, | |
15667 | /* 28 */ NULL, NULL, NULL, NULL, | |
15668 | /* 2C */ NULL, NULL, NULL, NULL, | |
15669 | /* 30 */ NULL, NULL, NULL, NULL, | |
15670 | /* 34 */ NULL, NULL, NULL, NULL, | |
15671 | /* 38 */ NULL, NULL, NULL, NULL, | |
15672 | /* 3C */ NULL, NULL, NULL, NULL, | |
15673 | /* 40 */ NULL, NULL, NULL, NULL, | |
15674 | /* 44 */ NULL, NULL, NULL, NULL, | |
15675 | /* 48 */ NULL, NULL, NULL, NULL, | |
15676 | /* 4C */ NULL, NULL, NULL, NULL, | |
15677 | /* 50 */ NULL, NULL, NULL, NULL, | |
15678 | /* 54 */ NULL, NULL, NULL, NULL, | |
15679 | /* 58 */ NULL, NULL, NULL, NULL, | |
15680 | /* 5C */ NULL, NULL, NULL, NULL, | |
15681 | /* 60 */ NULL, NULL, NULL, NULL, | |
15682 | /* 64 */ NULL, NULL, NULL, NULL, | |
15683 | /* 68 */ NULL, NULL, NULL, NULL, | |
15684 | /* 6C */ NULL, NULL, NULL, NULL, | |
15685 | /* 70 */ NULL, NULL, NULL, NULL, | |
15686 | /* 74 */ NULL, NULL, NULL, NULL, | |
15687 | /* 78 */ NULL, NULL, NULL, NULL, | |
15688 | /* 7C */ NULL, NULL, NULL, NULL, | |
15689 | /* 80 */ NULL, NULL, NULL, NULL, | |
15690 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
15691 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
15692 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
15693 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
15694 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
15695 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
15696 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
15697 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
15698 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
15699 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
15700 | /* AC */ NULL, NULL, "pfacc", NULL, | |
15701 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 15702 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 15703 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
15704 | /* BC */ NULL, NULL, NULL, "pavgusb", |
15705 | /* C0 */ NULL, NULL, NULL, NULL, | |
15706 | /* C4 */ NULL, NULL, NULL, NULL, | |
15707 | /* C8 */ NULL, NULL, NULL, NULL, | |
15708 | /* CC */ NULL, NULL, NULL, NULL, | |
15709 | /* D0 */ NULL, NULL, NULL, NULL, | |
15710 | /* D4 */ NULL, NULL, NULL, NULL, | |
15711 | /* D8 */ NULL, NULL, NULL, NULL, | |
15712 | /* DC */ NULL, NULL, NULL, NULL, | |
15713 | /* E0 */ NULL, NULL, NULL, NULL, | |
15714 | /* E4 */ NULL, NULL, NULL, NULL, | |
15715 | /* E8 */ NULL, NULL, NULL, NULL, | |
15716 | /* EC */ NULL, NULL, NULL, NULL, | |
15717 | /* F0 */ NULL, NULL, NULL, NULL, | |
15718 | /* F4 */ NULL, NULL, NULL, NULL, | |
15719 | /* F8 */ NULL, NULL, NULL, NULL, | |
15720 | /* FC */ NULL, NULL, NULL, NULL, | |
15721 | }; | |
15722 | ||
15723 | static void | |
26ca5450 | 15724 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
15725 | { |
15726 | const char *mnemonic; | |
15727 | ||
15728 | FETCH_DATA (the_info, codep + 1); | |
15729 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
15730 | place where an 8-bit immediate would normally go. ie. the last | |
15731 | byte of the instruction. */ | |
ea397f5b | 15732 | obufp = mnemonicendp; |
c608c12e | 15733 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 15734 | if (mnemonic) |
2da11e11 | 15735 | oappend (mnemonic); |
252b5132 RH |
15736 | else |
15737 | { | |
15738 | /* Since a variable sized modrm/sib chunk is between the start | |
15739 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
15740 | all the modrm processing first, and don't know until now that | |
15741 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
15742 | op_out[0][0] = '\0'; |
15743 | op_out[1][0] = '\0'; | |
6608db57 | 15744 | BadOp (); |
252b5132 | 15745 | } |
ea397f5b | 15746 | mnemonicendp = obufp; |
252b5132 | 15747 | } |
c608c12e | 15748 | |
ea397f5b L |
15749 | static struct op simd_cmp_op[] = |
15750 | { | |
15751 | { STRING_COMMA_LEN ("eq") }, | |
15752 | { STRING_COMMA_LEN ("lt") }, | |
15753 | { STRING_COMMA_LEN ("le") }, | |
15754 | { STRING_COMMA_LEN ("unord") }, | |
15755 | { STRING_COMMA_LEN ("neq") }, | |
15756 | { STRING_COMMA_LEN ("nlt") }, | |
15757 | { STRING_COMMA_LEN ("nle") }, | |
15758 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
15759 | }; |
15760 | ||
15761 | static void | |
ad19981d | 15762 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
15763 | { |
15764 | unsigned int cmp_type; | |
15765 | ||
15766 | FETCH_DATA (the_info, codep + 1); | |
15767 | cmp_type = *codep++ & 0xff; | |
c0f3af97 | 15768 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 15769 | { |
ad19981d | 15770 | char suffix [3]; |
ea397f5b | 15771 | char *p = mnemonicendp - 2; |
ad19981d L |
15772 | suffix[0] = p[0]; |
15773 | suffix[1] = p[1]; | |
15774 | suffix[2] = '\0'; | |
ea397f5b L |
15775 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
15776 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
c608c12e AM |
15777 | } |
15778 | else | |
15779 | { | |
ad19981d L |
15780 | /* We have a reserved extension byte. Output it directly. */ |
15781 | scratchbuf[0] = '$'; | |
15782 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 15783 | oappend_maybe_intel (scratchbuf); |
ad19981d | 15784 | scratchbuf[0] = '\0'; |
c608c12e AM |
15785 | } |
15786 | } | |
15787 | ||
ca164297 | 15788 | static void |
b844680a L |
15789 | OP_Mwait (int bytemode ATTRIBUTE_UNUSED, |
15790 | int sizeflag ATTRIBUTE_UNUSED) | |
15791 | { | |
15792 | /* mwait %eax,%ecx */ | |
15793 | if (!intel_syntax) | |
15794 | { | |
15795 | const char **names = (address_mode == mode_64bit | |
15796 | ? names64 : names32); | |
15797 | strcpy (op_out[0], names[0]); | |
15798 | strcpy (op_out[1], names[1]); | |
15799 | two_source_ops = 1; | |
15800 | } | |
15801 | /* Skip mod/rm byte. */ | |
15802 | MODRM_CHECK; | |
15803 | codep++; | |
15804 | } | |
15805 | ||
15806 | static void | |
15807 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
15808 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 15809 | { |
b844680a L |
15810 | /* monitor %eax,%ecx,%edx" */ |
15811 | if (!intel_syntax) | |
ca164297 | 15812 | { |
b844680a | 15813 | const char **op1_names; |
cb712a9e L |
15814 | const char **names = (address_mode == mode_64bit |
15815 | ? names64 : names32); | |
1d9f512f | 15816 | |
b844680a L |
15817 | if (!(prefixes & PREFIX_ADDR)) |
15818 | op1_names = (address_mode == mode_16bit | |
15819 | ? names16 : names); | |
ca164297 L |
15820 | else |
15821 | { | |
b844680a | 15822 | /* Remove "addr16/addr32". */ |
f16cd0d5 | 15823 | all_prefixes[last_addr_prefix] = 0; |
b844680a L |
15824 | op1_names = (address_mode != mode_32bit |
15825 | ? names32 : names16); | |
15826 | used_prefixes |= PREFIX_ADDR; | |
ca164297 | 15827 | } |
b844680a L |
15828 | strcpy (op_out[0], op1_names[0]); |
15829 | strcpy (op_out[1], names[1]); | |
15830 | strcpy (op_out[2], names[2]); | |
15831 | two_source_ops = 1; | |
ca164297 | 15832 | } |
b844680a L |
15833 | /* Skip mod/rm byte. */ |
15834 | MODRM_CHECK; | |
15835 | codep++; | |
30123838 JB |
15836 | } |
15837 | ||
6608db57 KH |
15838 | static void |
15839 | BadOp (void) | |
2da11e11 | 15840 | { |
6608db57 KH |
15841 | /* Throw away prefixes and 1st. opcode byte. */ |
15842 | codep = insn_codep + 1; | |
2da11e11 AM |
15843 | oappend ("(bad)"); |
15844 | } | |
4cc91dba | 15845 | |
35c52694 L |
15846 | static void |
15847 | REP_Fixup (int bytemode, int sizeflag) | |
15848 | { | |
15849 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
15850 | lods and stos. */ | |
35c52694 | 15851 | if (prefixes & PREFIX_REPZ) |
f16cd0d5 | 15852 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
35c52694 L |
15853 | |
15854 | switch (bytemode) | |
15855 | { | |
15856 | case al_reg: | |
15857 | case eAX_reg: | |
15858 | case indir_dx_reg: | |
15859 | OP_IMREG (bytemode, sizeflag); | |
15860 | break; | |
15861 | case eDI_reg: | |
15862 | OP_ESreg (bytemode, sizeflag); | |
15863 | break; | |
15864 | case eSI_reg: | |
15865 | OP_DSreg (bytemode, sizeflag); | |
15866 | break; | |
15867 | default: | |
15868 | abort (); | |
15869 | break; | |
15870 | } | |
15871 | } | |
f5804c90 | 15872 | |
7e8b059b L |
15873 | /* For BND-prefixed instructions 0xF2 prefix should be displayed as |
15874 | "bnd". */ | |
15875 | ||
15876 | static void | |
15877 | BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15878 | { | |
15879 | if (prefixes & PREFIX_REPNZ) | |
15880 | all_prefixes[last_repnz_prefix] = BND_PREFIX; | |
15881 | } | |
15882 | ||
42164a71 L |
15883 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
15884 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. | |
15885 | */ | |
15886 | ||
15887 | static void | |
15888 | HLE_Fixup1 (int bytemode, int sizeflag) | |
15889 | { | |
15890 | if (modrm.mod != 3 | |
15891 | && (prefixes & PREFIX_LOCK) != 0) | |
15892 | { | |
15893 | if (prefixes & PREFIX_REPZ) | |
15894 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15895 | if (prefixes & PREFIX_REPNZ) | |
15896 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15897 | } | |
15898 | ||
15899 | OP_E (bytemode, sizeflag); | |
15900 | } | |
15901 | ||
15902 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as | |
15903 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. | |
15904 | */ | |
15905 | ||
15906 | static void | |
15907 | HLE_Fixup2 (int bytemode, int sizeflag) | |
15908 | { | |
15909 | if (modrm.mod != 3) | |
15910 | { | |
15911 | if (prefixes & PREFIX_REPZ) | |
15912 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15913 | if (prefixes & PREFIX_REPNZ) | |
15914 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15915 | } | |
15916 | ||
15917 | OP_E (bytemode, sizeflag); | |
15918 | } | |
15919 | ||
15920 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as | |
15921 | "xrelease" for memory operand. No check for LOCK prefix. */ | |
15922 | ||
15923 | static void | |
15924 | HLE_Fixup3 (int bytemode, int sizeflag) | |
15925 | { | |
15926 | if (modrm.mod != 3 | |
15927 | && last_repz_prefix > last_repnz_prefix | |
15928 | && (prefixes & PREFIX_REPZ) != 0) | |
15929 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15930 | ||
15931 | OP_E (bytemode, sizeflag); | |
15932 | } | |
15933 | ||
f5804c90 L |
15934 | static void |
15935 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
15936 | { | |
161a04f6 L |
15937 | USED_REX (REX_W); |
15938 | if (rex & REX_W) | |
f5804c90 L |
15939 | { |
15940 | /* Change cmpxchg8b to cmpxchg16b. */ | |
ea397f5b L |
15941 | char *p = mnemonicendp - 2; |
15942 | mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 15943 | bytemode = o_mode; |
f5804c90 | 15944 | } |
42164a71 L |
15945 | else if ((prefixes & PREFIX_LOCK) != 0) |
15946 | { | |
15947 | if (prefixes & PREFIX_REPZ) | |
15948 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15949 | if (prefixes & PREFIX_REPNZ) | |
15950 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15951 | } | |
15952 | ||
f5804c90 L |
15953 | OP_M (bytemode, sizeflag); |
15954 | } | |
42903f7f L |
15955 | |
15956 | static void | |
15957 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
15958 | { | |
b9733481 L |
15959 | const char **names; |
15960 | ||
c0f3af97 L |
15961 | if (need_vex) |
15962 | { | |
15963 | switch (vex.length) | |
15964 | { | |
15965 | case 128: | |
b9733481 | 15966 | names = names_xmm; |
c0f3af97 L |
15967 | break; |
15968 | case 256: | |
b9733481 | 15969 | names = names_ymm; |
c0f3af97 L |
15970 | break; |
15971 | default: | |
15972 | abort (); | |
15973 | } | |
15974 | } | |
15975 | else | |
b9733481 L |
15976 | names = names_xmm; |
15977 | oappend (names[reg]); | |
42903f7f | 15978 | } |
381d071f L |
15979 | |
15980 | static void | |
15981 | CRC32_Fixup (int bytemode, int sizeflag) | |
15982 | { | |
15983 | /* Add proper suffix to "crc32". */ | |
ea397f5b | 15984 | char *p = mnemonicendp; |
381d071f L |
15985 | |
15986 | switch (bytemode) | |
15987 | { | |
15988 | case b_mode: | |
20592a94 | 15989 | if (intel_syntax) |
ea397f5b | 15990 | goto skip; |
20592a94 | 15991 | |
381d071f L |
15992 | *p++ = 'b'; |
15993 | break; | |
15994 | case v_mode: | |
20592a94 | 15995 | if (intel_syntax) |
ea397f5b | 15996 | goto skip; |
20592a94 | 15997 | |
381d071f L |
15998 | USED_REX (REX_W); |
15999 | if (rex & REX_W) | |
16000 | *p++ = 'q'; | |
7bb15c6f | 16001 | else |
f16cd0d5 L |
16002 | { |
16003 | if (sizeflag & DFLAG) | |
16004 | *p++ = 'l'; | |
16005 | else | |
16006 | *p++ = 'w'; | |
16007 | used_prefixes |= (prefixes & PREFIX_DATA); | |
16008 | } | |
381d071f L |
16009 | break; |
16010 | default: | |
16011 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16012 | break; | |
16013 | } | |
ea397f5b | 16014 | mnemonicendp = p; |
381d071f L |
16015 | *p = '\0'; |
16016 | ||
ea397f5b | 16017 | skip: |
381d071f L |
16018 | if (modrm.mod == 3) |
16019 | { | |
16020 | int add; | |
16021 | ||
16022 | /* Skip mod/rm byte. */ | |
16023 | MODRM_CHECK; | |
16024 | codep++; | |
16025 | ||
16026 | USED_REX (REX_B); | |
16027 | add = (rex & REX_B) ? 8 : 0; | |
16028 | if (bytemode == b_mode) | |
16029 | { | |
16030 | USED_REX (0); | |
16031 | if (rex) | |
16032 | oappend (names8rex[modrm.rm + add]); | |
16033 | else | |
16034 | oappend (names8[modrm.rm + add]); | |
16035 | } | |
16036 | else | |
16037 | { | |
16038 | USED_REX (REX_W); | |
16039 | if (rex & REX_W) | |
16040 | oappend (names64[modrm.rm + add]); | |
16041 | else if ((prefixes & PREFIX_DATA)) | |
16042 | oappend (names16[modrm.rm + add]); | |
16043 | else | |
16044 | oappend (names32[modrm.rm + add]); | |
16045 | } | |
16046 | } | |
16047 | else | |
9344ff29 | 16048 | OP_E (bytemode, sizeflag); |
381d071f | 16049 | } |
85f10a01 | 16050 | |
eacc9c89 L |
16051 | static void |
16052 | FXSAVE_Fixup (int bytemode, int sizeflag) | |
16053 | { | |
16054 | /* Add proper suffix to "fxsave" and "fxrstor". */ | |
16055 | USED_REX (REX_W); | |
16056 | if (rex & REX_W) | |
16057 | { | |
16058 | char *p = mnemonicendp; | |
16059 | *p++ = '6'; | |
16060 | *p++ = '4'; | |
16061 | *p = '\0'; | |
16062 | mnemonicendp = p; | |
16063 | } | |
16064 | OP_M (bytemode, sizeflag); | |
16065 | } | |
16066 | ||
c0f3af97 L |
16067 | /* Display the destination register operand for instructions with |
16068 | VEX. */ | |
16069 | ||
16070 | static void | |
16071 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16072 | { | |
539f890d | 16073 | int reg; |
b9733481 L |
16074 | const char **names; |
16075 | ||
c0f3af97 L |
16076 | if (!need_vex) |
16077 | abort (); | |
16078 | ||
16079 | if (!need_vex_reg) | |
16080 | return; | |
16081 | ||
539f890d | 16082 | reg = vex.register_specifier; |
43234a1e L |
16083 | if (vex.evex) |
16084 | { | |
16085 | if (!vex.v) | |
16086 | reg += 16; | |
16087 | } | |
16088 | ||
539f890d L |
16089 | if (bytemode == vex_scalar_mode) |
16090 | { | |
16091 | oappend (names_xmm[reg]); | |
16092 | return; | |
16093 | } | |
16094 | ||
c0f3af97 L |
16095 | switch (vex.length) |
16096 | { | |
16097 | case 128: | |
16098 | switch (bytemode) | |
16099 | { | |
16100 | case vex_mode: | |
16101 | case vex128_mode: | |
6c30d220 | 16102 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 16103 | case vex_vsib_q_w_d_mode: |
cb21baef L |
16104 | names = names_xmm; |
16105 | break; | |
16106 | case dq_mode: | |
16107 | if (vex.w) | |
16108 | names = names64; | |
16109 | else | |
16110 | names = names32; | |
c0f3af97 | 16111 | break; |
43234a1e L |
16112 | case mask_mode: |
16113 | names = names_mask; | |
16114 | break; | |
c0f3af97 L |
16115 | default: |
16116 | abort (); | |
16117 | return; | |
16118 | } | |
c0f3af97 L |
16119 | break; |
16120 | case 256: | |
16121 | switch (bytemode) | |
16122 | { | |
16123 | case vex_mode: | |
16124 | case vex256_mode: | |
6c30d220 L |
16125 | names = names_ymm; |
16126 | break; | |
16127 | case vex_vsib_q_w_dq_mode: | |
5fc35d96 | 16128 | case vex_vsib_q_w_d_mode: |
6c30d220 | 16129 | names = vex.w ? names_ymm : names_xmm; |
c0f3af97 | 16130 | break; |
43234a1e L |
16131 | case mask_mode: |
16132 | names = names_mask; | |
16133 | break; | |
c0f3af97 L |
16134 | default: |
16135 | abort (); | |
16136 | return; | |
16137 | } | |
c0f3af97 | 16138 | break; |
43234a1e L |
16139 | case 512: |
16140 | names = names_zmm; | |
16141 | break; | |
c0f3af97 L |
16142 | default: |
16143 | abort (); | |
16144 | break; | |
16145 | } | |
539f890d | 16146 | oappend (names[reg]); |
c0f3af97 L |
16147 | } |
16148 | ||
922d8de8 DR |
16149 | /* Get the VEX immediate byte without moving codep. */ |
16150 | ||
16151 | static unsigned char | |
ccc5981b | 16152 | get_vex_imm8 (int sizeflag, int opnum) |
922d8de8 DR |
16153 | { |
16154 | int bytes_before_imm = 0; | |
16155 | ||
922d8de8 DR |
16156 | if (modrm.mod != 3) |
16157 | { | |
16158 | /* There are SIB/displacement bytes. */ | |
16159 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) | |
6c067bbb | 16160 | { |
922d8de8 | 16161 | /* 32/64 bit address mode */ |
6c067bbb | 16162 | int base = modrm.rm; |
922d8de8 DR |
16163 | |
16164 | /* Check SIB byte. */ | |
6c067bbb RM |
16165 | if (base == 4) |
16166 | { | |
16167 | FETCH_DATA (the_info, codep + 1); | |
16168 | base = *codep & 7; | |
16169 | /* When decoding the third source, don't increase | |
16170 | bytes_before_imm as this has already been incremented | |
16171 | by one in OP_E_memory while decoding the second | |
16172 | source operand. */ | |
16173 | if (opnum == 0) | |
16174 | bytes_before_imm++; | |
16175 | } | |
16176 | ||
16177 | /* Don't increase bytes_before_imm when decoding the third source, | |
16178 | it has already been incremented by OP_E_memory while decoding | |
16179 | the second source operand. */ | |
16180 | if (opnum == 0) | |
16181 | { | |
16182 | switch (modrm.mod) | |
16183 | { | |
16184 | case 0: | |
16185 | /* When modrm.rm == 5 or modrm.rm == 4 and base in | |
16186 | SIB == 5, there is a 4 byte displacement. */ | |
16187 | if (base != 5) | |
16188 | /* No displacement. */ | |
16189 | break; | |
16190 | case 2: | |
16191 | /* 4 byte displacement. */ | |
16192 | bytes_before_imm += 4; | |
16193 | break; | |
16194 | case 1: | |
16195 | /* 1 byte displacement. */ | |
16196 | bytes_before_imm++; | |
16197 | break; | |
16198 | } | |
16199 | } | |
16200 | } | |
922d8de8 | 16201 | else |
02e647f9 SP |
16202 | { |
16203 | /* 16 bit address mode */ | |
6c067bbb RM |
16204 | /* Don't increase bytes_before_imm when decoding the third source, |
16205 | it has already been incremented by OP_E_memory while decoding | |
16206 | the second source operand. */ | |
16207 | if (opnum == 0) | |
16208 | { | |
02e647f9 SP |
16209 | switch (modrm.mod) |
16210 | { | |
16211 | case 0: | |
16212 | /* When modrm.rm == 6, there is a 2 byte displacement. */ | |
16213 | if (modrm.rm != 6) | |
16214 | /* No displacement. */ | |
16215 | break; | |
16216 | case 2: | |
16217 | /* 2 byte displacement. */ | |
16218 | bytes_before_imm += 2; | |
16219 | break; | |
16220 | case 1: | |
16221 | /* 1 byte displacement: when decoding the third source, | |
16222 | don't increase bytes_before_imm as this has already | |
16223 | been incremented by one in OP_E_memory while decoding | |
16224 | the second source operand. */ | |
16225 | if (opnum == 0) | |
16226 | bytes_before_imm++; | |
ccc5981b | 16227 | |
02e647f9 SP |
16228 | break; |
16229 | } | |
922d8de8 DR |
16230 | } |
16231 | } | |
16232 | } | |
16233 | ||
16234 | FETCH_DATA (the_info, codep + bytes_before_imm + 1); | |
16235 | return codep [bytes_before_imm]; | |
16236 | } | |
16237 | ||
16238 | static void | |
16239 | OP_EX_VexReg (int bytemode, int sizeflag, int reg) | |
16240 | { | |
b9733481 L |
16241 | const char **names; |
16242 | ||
922d8de8 DR |
16243 | if (reg == -1 && modrm.mod != 3) |
16244 | { | |
16245 | OP_E_memory (bytemode, sizeflag); | |
16246 | return; | |
16247 | } | |
16248 | else | |
16249 | { | |
16250 | if (reg == -1) | |
16251 | { | |
16252 | reg = modrm.rm; | |
16253 | USED_REX (REX_B); | |
16254 | if (rex & REX_B) | |
16255 | reg += 8; | |
16256 | } | |
16257 | else if (reg > 7 && address_mode != mode_64bit) | |
16258 | BadOp (); | |
16259 | } | |
16260 | ||
16261 | switch (vex.length) | |
16262 | { | |
16263 | case 128: | |
b9733481 | 16264 | names = names_xmm; |
922d8de8 DR |
16265 | break; |
16266 | case 256: | |
b9733481 | 16267 | names = names_ymm; |
922d8de8 DR |
16268 | break; |
16269 | default: | |
16270 | abort (); | |
16271 | } | |
b9733481 | 16272 | oappend (names[reg]); |
922d8de8 DR |
16273 | } |
16274 | ||
a683cc34 SP |
16275 | static void |
16276 | OP_EX_VexImmW (int bytemode, int sizeflag) | |
16277 | { | |
16278 | int reg = -1; | |
16279 | static unsigned char vex_imm8; | |
16280 | ||
16281 | if (vex_w_done == 0) | |
16282 | { | |
16283 | vex_w_done = 1; | |
16284 | ||
16285 | /* Skip mod/rm byte. */ | |
16286 | MODRM_CHECK; | |
16287 | codep++; | |
16288 | ||
16289 | vex_imm8 = get_vex_imm8 (sizeflag, 0); | |
16290 | ||
16291 | if (vex.w) | |
16292 | reg = vex_imm8 >> 4; | |
16293 | ||
16294 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
16295 | } | |
16296 | else if (vex_w_done == 1) | |
16297 | { | |
16298 | vex_w_done = 2; | |
16299 | ||
16300 | if (!vex.w) | |
16301 | reg = vex_imm8 >> 4; | |
16302 | ||
16303 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
16304 | } | |
16305 | else | |
16306 | { | |
16307 | /* Output the imm8 directly. */ | |
16308 | scratchbuf[0] = '$'; | |
16309 | print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf); | |
9ce09ba2 | 16310 | oappend_maybe_intel (scratchbuf); |
a683cc34 SP |
16311 | scratchbuf[0] = '\0'; |
16312 | codep++; | |
16313 | } | |
16314 | } | |
16315 | ||
5dd85c99 SP |
16316 | static void |
16317 | OP_Vex_2src (int bytemode, int sizeflag) | |
16318 | { | |
16319 | if (modrm.mod == 3) | |
16320 | { | |
b9733481 | 16321 | int reg = modrm.rm; |
5dd85c99 | 16322 | USED_REX (REX_B); |
b9733481 L |
16323 | if (rex & REX_B) |
16324 | reg += 8; | |
16325 | oappend (names_xmm[reg]); | |
5dd85c99 SP |
16326 | } |
16327 | else | |
16328 | { | |
16329 | if (intel_syntax | |
16330 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
16331 | { | |
16332 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
16333 | used_prefixes |= (prefixes & PREFIX_DATA); | |
16334 | } | |
16335 | OP_E (bytemode, sizeflag); | |
16336 | } | |
16337 | } | |
16338 | ||
16339 | static void | |
16340 | OP_Vex_2src_1 (int bytemode, int sizeflag) | |
16341 | { | |
16342 | if (modrm.mod == 3) | |
16343 | { | |
16344 | /* Skip mod/rm byte. */ | |
16345 | MODRM_CHECK; | |
16346 | codep++; | |
16347 | } | |
16348 | ||
16349 | if (vex.w) | |
b9733481 | 16350 | oappend (names_xmm[vex.register_specifier]); |
5dd85c99 SP |
16351 | else |
16352 | OP_Vex_2src (bytemode, sizeflag); | |
16353 | } | |
16354 | ||
16355 | static void | |
16356 | OP_Vex_2src_2 (int bytemode, int sizeflag) | |
16357 | { | |
16358 | if (vex.w) | |
16359 | OP_Vex_2src (bytemode, sizeflag); | |
16360 | else | |
b9733481 | 16361 | oappend (names_xmm[vex.register_specifier]); |
5dd85c99 SP |
16362 | } |
16363 | ||
922d8de8 DR |
16364 | static void |
16365 | OP_EX_VexW (int bytemode, int sizeflag) | |
16366 | { | |
16367 | int reg = -1; | |
16368 | ||
16369 | if (!vex_w_done) | |
16370 | { | |
16371 | vex_w_done = 1; | |
41effecb SP |
16372 | |
16373 | /* Skip mod/rm byte. */ | |
16374 | MODRM_CHECK; | |
16375 | codep++; | |
16376 | ||
922d8de8 | 16377 | if (vex.w) |
ccc5981b | 16378 | reg = get_vex_imm8 (sizeflag, 0) >> 4; |
922d8de8 DR |
16379 | } |
16380 | else | |
16381 | { | |
16382 | if (!vex.w) | |
ccc5981b | 16383 | reg = get_vex_imm8 (sizeflag, 1) >> 4; |
922d8de8 DR |
16384 | } |
16385 | ||
16386 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
16387 | } | |
16388 | ||
922d8de8 DR |
16389 | static void |
16390 | VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16391 | int sizeflag ATTRIBUTE_UNUSED) | |
16392 | { | |
16393 | /* Skip the immediate byte and check for invalid bits. */ | |
16394 | FETCH_DATA (the_info, codep + 1); | |
16395 | if (*codep++ & 0xf) | |
16396 | BadOp (); | |
16397 | } | |
16398 | ||
c0f3af97 L |
16399 | static void |
16400 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16401 | { | |
16402 | int reg; | |
b9733481 L |
16403 | const char **names; |
16404 | ||
c0f3af97 L |
16405 | FETCH_DATA (the_info, codep + 1); |
16406 | reg = *codep++; | |
16407 | ||
16408 | if (bytemode != x_mode) | |
16409 | abort (); | |
16410 | ||
16411 | if (reg & 0xf) | |
16412 | BadOp (); | |
16413 | ||
16414 | reg >>= 4; | |
dae39acc L |
16415 | if (reg > 7 && address_mode != mode_64bit) |
16416 | BadOp (); | |
16417 | ||
c0f3af97 L |
16418 | switch (vex.length) |
16419 | { | |
16420 | case 128: | |
b9733481 | 16421 | names = names_xmm; |
c0f3af97 L |
16422 | break; |
16423 | case 256: | |
b9733481 | 16424 | names = names_ymm; |
c0f3af97 L |
16425 | break; |
16426 | default: | |
16427 | abort (); | |
16428 | } | |
b9733481 | 16429 | oappend (names[reg]); |
c0f3af97 L |
16430 | } |
16431 | ||
922d8de8 DR |
16432 | static void |
16433 | OP_XMM_VexW (int bytemode, int sizeflag) | |
16434 | { | |
16435 | /* Turn off the REX.W bit since it is used for swapping operands | |
16436 | now. */ | |
16437 | rex &= ~REX_W; | |
16438 | OP_XMM (bytemode, sizeflag); | |
16439 | } | |
16440 | ||
c0f3af97 L |
16441 | static void |
16442 | OP_EX_Vex (int bytemode, int sizeflag) | |
16443 | { | |
16444 | if (modrm.mod != 3) | |
16445 | { | |
16446 | if (vex.register_specifier != 0) | |
16447 | BadOp (); | |
16448 | need_vex_reg = 0; | |
16449 | } | |
16450 | OP_EX (bytemode, sizeflag); | |
16451 | } | |
16452 | ||
16453 | static void | |
16454 | OP_XMM_Vex (int bytemode, int sizeflag) | |
16455 | { | |
16456 | if (modrm.mod != 3) | |
16457 | { | |
16458 | if (vex.register_specifier != 0) | |
16459 | BadOp (); | |
16460 | need_vex_reg = 0; | |
16461 | } | |
16462 | OP_XMM (bytemode, sizeflag); | |
16463 | } | |
16464 | ||
16465 | static void | |
16466 | VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16467 | { | |
16468 | switch (vex.length) | |
16469 | { | |
16470 | case 128: | |
ea397f5b | 16471 | mnemonicendp = stpcpy (obuf, "vzeroupper"); |
c0f3af97 L |
16472 | break; |
16473 | case 256: | |
ea397f5b | 16474 | mnemonicendp = stpcpy (obuf, "vzeroall"); |
c0f3af97 L |
16475 | break; |
16476 | default: | |
16477 | abort (); | |
16478 | } | |
16479 | } | |
16480 | ||
ea397f5b L |
16481 | static struct op vex_cmp_op[] = |
16482 | { | |
16483 | { STRING_COMMA_LEN ("eq") }, | |
16484 | { STRING_COMMA_LEN ("lt") }, | |
16485 | { STRING_COMMA_LEN ("le") }, | |
16486 | { STRING_COMMA_LEN ("unord") }, | |
16487 | { STRING_COMMA_LEN ("neq") }, | |
16488 | { STRING_COMMA_LEN ("nlt") }, | |
16489 | { STRING_COMMA_LEN ("nle") }, | |
16490 | { STRING_COMMA_LEN ("ord") }, | |
16491 | { STRING_COMMA_LEN ("eq_uq") }, | |
16492 | { STRING_COMMA_LEN ("nge") }, | |
16493 | { STRING_COMMA_LEN ("ngt") }, | |
16494 | { STRING_COMMA_LEN ("false") }, | |
16495 | { STRING_COMMA_LEN ("neq_oq") }, | |
16496 | { STRING_COMMA_LEN ("ge") }, | |
16497 | { STRING_COMMA_LEN ("gt") }, | |
16498 | { STRING_COMMA_LEN ("true") }, | |
16499 | { STRING_COMMA_LEN ("eq_os") }, | |
16500 | { STRING_COMMA_LEN ("lt_oq") }, | |
16501 | { STRING_COMMA_LEN ("le_oq") }, | |
16502 | { STRING_COMMA_LEN ("unord_s") }, | |
16503 | { STRING_COMMA_LEN ("neq_us") }, | |
16504 | { STRING_COMMA_LEN ("nlt_uq") }, | |
16505 | { STRING_COMMA_LEN ("nle_uq") }, | |
16506 | { STRING_COMMA_LEN ("ord_s") }, | |
16507 | { STRING_COMMA_LEN ("eq_us") }, | |
16508 | { STRING_COMMA_LEN ("nge_uq") }, | |
16509 | { STRING_COMMA_LEN ("ngt_uq") }, | |
16510 | { STRING_COMMA_LEN ("false_os") }, | |
16511 | { STRING_COMMA_LEN ("neq_os") }, | |
16512 | { STRING_COMMA_LEN ("ge_oq") }, | |
16513 | { STRING_COMMA_LEN ("gt_oq") }, | |
16514 | { STRING_COMMA_LEN ("true_us") }, | |
c0f3af97 L |
16515 | }; |
16516 | ||
16517 | static void | |
16518 | VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16519 | { | |
16520 | unsigned int cmp_type; | |
16521 | ||
16522 | FETCH_DATA (the_info, codep + 1); | |
16523 | cmp_type = *codep++ & 0xff; | |
16524 | if (cmp_type < ARRAY_SIZE (vex_cmp_op)) | |
16525 | { | |
16526 | char suffix [3]; | |
ea397f5b | 16527 | char *p = mnemonicendp - 2; |
c0f3af97 L |
16528 | suffix[0] = p[0]; |
16529 | suffix[1] = p[1]; | |
16530 | suffix[2] = '\0'; | |
ea397f5b L |
16531 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); |
16532 | mnemonicendp += vex_cmp_op[cmp_type].len; | |
c0f3af97 L |
16533 | } |
16534 | else | |
16535 | { | |
16536 | /* We have a reserved extension byte. Output it directly. */ | |
16537 | scratchbuf[0] = '$'; | |
16538 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16539 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
16540 | scratchbuf[0] = '\0'; |
16541 | } | |
16542 | } | |
16543 | ||
43234a1e L |
16544 | static void |
16545 | VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16546 | int sizeflag ATTRIBUTE_UNUSED) | |
16547 | { | |
16548 | unsigned int cmp_type; | |
16549 | ||
16550 | if (!vex.evex) | |
16551 | abort (); | |
16552 | ||
16553 | FETCH_DATA (the_info, codep + 1); | |
16554 | cmp_type = *codep++ & 0xff; | |
16555 | /* There are aliases for immediates 0, 1, 2, 4, 5, 6. | |
16556 | If it's the case, print suffix, otherwise - print the immediate. */ | |
16557 | if (cmp_type < ARRAY_SIZE (simd_cmp_op) | |
16558 | && cmp_type != 3 | |
16559 | && cmp_type != 7) | |
16560 | { | |
16561 | char suffix [3]; | |
16562 | char *p = mnemonicendp - 2; | |
16563 | ||
16564 | /* vpcmp* can have both one- and two-lettered suffix. */ | |
16565 | if (p[0] == 'p') | |
16566 | { | |
16567 | p++; | |
16568 | suffix[0] = p[0]; | |
16569 | suffix[1] = '\0'; | |
16570 | } | |
16571 | else | |
16572 | { | |
16573 | suffix[0] = p[0]; | |
16574 | suffix[1] = p[1]; | |
16575 | suffix[2] = '\0'; | |
16576 | } | |
16577 | ||
16578 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); | |
16579 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
16580 | } | |
16581 | else | |
16582 | { | |
16583 | /* We have a reserved extension byte. Output it directly. */ | |
16584 | scratchbuf[0] = '$'; | |
16585 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16586 | oappend_maybe_intel (scratchbuf); |
43234a1e L |
16587 | scratchbuf[0] = '\0'; |
16588 | } | |
16589 | } | |
16590 | ||
ea397f5b L |
16591 | static const struct op pclmul_op[] = |
16592 | { | |
16593 | { STRING_COMMA_LEN ("lql") }, | |
16594 | { STRING_COMMA_LEN ("hql") }, | |
16595 | { STRING_COMMA_LEN ("lqh") }, | |
16596 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
16597 | }; |
16598 | ||
16599 | static void | |
16600 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16601 | int sizeflag ATTRIBUTE_UNUSED) | |
16602 | { | |
16603 | unsigned int pclmul_type; | |
16604 | ||
16605 | FETCH_DATA (the_info, codep + 1); | |
16606 | pclmul_type = *codep++ & 0xff; | |
16607 | switch (pclmul_type) | |
16608 | { | |
16609 | case 0x10: | |
16610 | pclmul_type = 2; | |
16611 | break; | |
16612 | case 0x11: | |
16613 | pclmul_type = 3; | |
16614 | break; | |
16615 | default: | |
16616 | break; | |
7bb15c6f | 16617 | } |
c0f3af97 L |
16618 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
16619 | { | |
16620 | char suffix [4]; | |
ea397f5b | 16621 | char *p = mnemonicendp - 3; |
c0f3af97 L |
16622 | suffix[0] = p[0]; |
16623 | suffix[1] = p[1]; | |
16624 | suffix[2] = p[2]; | |
16625 | suffix[3] = '\0'; | |
ea397f5b L |
16626 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
16627 | mnemonicendp += pclmul_op[pclmul_type].len; | |
c0f3af97 L |
16628 | } |
16629 | else | |
16630 | { | |
16631 | /* We have a reserved extension byte. Output it directly. */ | |
16632 | scratchbuf[0] = '$'; | |
16633 | print_operand_value (scratchbuf + 1, 1, pclmul_type); | |
9ce09ba2 | 16634 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
16635 | scratchbuf[0] = '\0'; |
16636 | } | |
16637 | } | |
16638 | ||
f1f8f695 L |
16639 | static void |
16640 | MOVBE_Fixup (int bytemode, int sizeflag) | |
16641 | { | |
16642 | /* Add proper suffix to "movbe". */ | |
ea397f5b | 16643 | char *p = mnemonicendp; |
f1f8f695 L |
16644 | |
16645 | switch (bytemode) | |
16646 | { | |
16647 | case v_mode: | |
16648 | if (intel_syntax) | |
ea397f5b | 16649 | goto skip; |
f1f8f695 L |
16650 | |
16651 | USED_REX (REX_W); | |
16652 | if (sizeflag & SUFFIX_ALWAYS) | |
16653 | { | |
16654 | if (rex & REX_W) | |
16655 | *p++ = 'q'; | |
f1f8f695 | 16656 | else |
f16cd0d5 L |
16657 | { |
16658 | if (sizeflag & DFLAG) | |
16659 | *p++ = 'l'; | |
16660 | else | |
16661 | *p++ = 'w'; | |
16662 | used_prefixes |= (prefixes & PREFIX_DATA); | |
16663 | } | |
f1f8f695 | 16664 | } |
f1f8f695 L |
16665 | break; |
16666 | default: | |
16667 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16668 | break; | |
16669 | } | |
ea397f5b | 16670 | mnemonicendp = p; |
f1f8f695 L |
16671 | *p = '\0'; |
16672 | ||
ea397f5b | 16673 | skip: |
f1f8f695 L |
16674 | OP_M (bytemode, sizeflag); |
16675 | } | |
f88c9eb0 SP |
16676 | |
16677 | static void | |
16678 | OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16679 | { | |
16680 | int reg; | |
16681 | const char **names; | |
16682 | ||
16683 | /* Skip mod/rm byte. */ | |
16684 | MODRM_CHECK; | |
16685 | codep++; | |
16686 | ||
16687 | if (vex.w) | |
16688 | names = names64; | |
f88c9eb0 | 16689 | else |
ce7d077e | 16690 | names = names32; |
f88c9eb0 SP |
16691 | |
16692 | reg = modrm.rm; | |
16693 | USED_REX (REX_B); | |
16694 | if (rex & REX_B) | |
16695 | reg += 8; | |
16696 | ||
16697 | oappend (names[reg]); | |
16698 | } | |
16699 | ||
16700 | static void | |
16701 | OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16702 | { | |
16703 | const char **names; | |
16704 | ||
16705 | if (vex.w) | |
16706 | names = names64; | |
f88c9eb0 | 16707 | else |
ce7d077e | 16708 | names = names32; |
f88c9eb0 SP |
16709 | |
16710 | oappend (names[vex.register_specifier]); | |
16711 | } | |
43234a1e L |
16712 | |
16713 | static void | |
16714 | OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16715 | { | |
16716 | if (!vex.evex | |
16717 | || bytemode != mask_mode) | |
16718 | abort (); | |
16719 | ||
16720 | USED_REX (REX_R); | |
16721 | if ((rex & REX_R) != 0 || !vex.r) | |
16722 | { | |
16723 | BadOp (); | |
16724 | return; | |
16725 | } | |
16726 | ||
16727 | oappend (names_mask [modrm.reg]); | |
16728 | } | |
16729 | ||
16730 | static void | |
16731 | OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16732 | { | |
16733 | if (!vex.evex | |
16734 | || (bytemode != evex_rounding_mode | |
16735 | && bytemode != evex_sae_mode)) | |
16736 | abort (); | |
16737 | if (modrm.mod == 3 && vex.b) | |
16738 | switch (bytemode) | |
16739 | { | |
16740 | case evex_rounding_mode: | |
16741 | oappend (names_rounding[vex.ll]); | |
16742 | break; | |
16743 | case evex_sae_mode: | |
16744 | oappend ("{sae}"); | |
16745 | break; | |
16746 | default: | |
16747 | break; | |
16748 | } | |
16749 | } |