Commit | Line | Data |
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252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
060d22b0 | 2 | Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
7bb15c6f | 3 | 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012 |
0af1713e | 4 | Free Software Foundation, Inc. |
252b5132 | 5 | |
9b201bb5 | 6 | This file is part of the GNU opcodes library. |
20f0a1fc | 7 | |
9b201bb5 | 8 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 9 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
10 | the Free Software Foundation; either version 3, or (at your option) |
11 | any later version. | |
20f0a1fc | 12 | |
9b201bb5 NC |
13 | It is distributed in the hope that it will be useful, but WITHOUT |
14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | License for more details. | |
20f0a1fc NC |
17 | |
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
20 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
21 | MA 02110-1301, USA. */ | |
22 | ||
20f0a1fc NC |
23 | |
24 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
25 | July 1988 | |
26 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
27 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
28 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
29 | ||
30 | /* The main tables describing the instructions is essentially a copy | |
31 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
32 | Programmers Manual. Usually, there is a capital letter, followed | |
33 | by a small letter. The capital letter tell the addressing mode, | |
34 | and the small letter tells about the operand size. Refer to | |
35 | the Intel manual for details. */ | |
252b5132 | 36 | |
252b5132 | 37 | #include "sysdep.h" |
dabbade6 | 38 | #include "dis-asm.h" |
252b5132 | 39 | #include "opintl.h" |
0b1cf022 | 40 | #include "opcode/i386.h" |
85f10a01 | 41 | #include "libiberty.h" |
252b5132 RH |
42 | |
43 | #include <setjmp.h> | |
44 | ||
26ca5450 AJ |
45 | static int print_insn (bfd_vma, disassemble_info *); |
46 | static void dofloat (int); | |
47 | static void OP_ST (int, int); | |
48 | static void OP_STi (int, int); | |
49 | static int putop (const char *, int); | |
50 | static void oappend (const char *); | |
51 | static void append_seg (void); | |
52 | static void OP_indirE (int, int); | |
53 | static void print_operand_value (char *, int, bfd_vma); | |
c0f3af97 | 54 | static void OP_E_register (int, int); |
c1e679ec | 55 | static void OP_E_memory (int, int); |
5d669648 | 56 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
57 | static void OP_E (int, int); |
58 | static void OP_G (int, int); | |
59 | static bfd_vma get64 (void); | |
60 | static bfd_signed_vma get32 (void); | |
61 | static bfd_signed_vma get32s (void); | |
62 | static int get16 (void); | |
63 | static void set_op (bfd_vma, int); | |
b844680a | 64 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
65 | static void OP_REG (int, int); |
66 | static void OP_IMREG (int, int); | |
67 | static void OP_I (int, int); | |
68 | static void OP_I64 (int, int); | |
69 | static void OP_sI (int, int); | |
70 | static void OP_J (int, int); | |
71 | static void OP_SEG (int, int); | |
72 | static void OP_DIR (int, int); | |
73 | static void OP_OFF (int, int); | |
74 | static void OP_OFF64 (int, int); | |
75 | static void ptr_reg (int, int); | |
76 | static void OP_ESreg (int, int); | |
77 | static void OP_DSreg (int, int); | |
78 | static void OP_C (int, int); | |
79 | static void OP_D (int, int); | |
80 | static void OP_T (int, int); | |
6f74c397 | 81 | static void OP_R (int, int); |
26ca5450 AJ |
82 | static void OP_MMX (int, int); |
83 | static void OP_XMM (int, int); | |
84 | static void OP_EM (int, int); | |
85 | static void OP_EX (int, int); | |
4d9567e0 MM |
86 | static void OP_EMC (int,int); |
87 | static void OP_MXC (int,int); | |
26ca5450 AJ |
88 | static void OP_MS (int, int); |
89 | static void OP_XS (int, int); | |
cc0ec051 | 90 | static void OP_M (int, int); |
c0f3af97 L |
91 | static void OP_VEX (int, int); |
92 | static void OP_EX_Vex (int, int); | |
922d8de8 | 93 | static void OP_EX_VexW (int, int); |
a683cc34 | 94 | static void OP_EX_VexImmW (int, int); |
c0f3af97 | 95 | static void OP_XMM_Vex (int, int); |
922d8de8 | 96 | static void OP_XMM_VexW (int, int); |
c0f3af97 L |
97 | static void OP_REG_VexI4 (int, int); |
98 | static void PCLMUL_Fixup (int, int); | |
922d8de8 | 99 | static void VEXI4_Fixup (int, int); |
c0f3af97 L |
100 | static void VZERO_Fixup (int, int); |
101 | static void VCMP_Fixup (int, int); | |
cc0ec051 | 102 | static void OP_0f07 (int, int); |
b844680a L |
103 | static void OP_Monitor (int, int); |
104 | static void OP_Mwait (int, int); | |
46e883c5 L |
105 | static void NOP_Fixup1 (int, int); |
106 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 107 | static void OP_3DNowSuffix (int, int); |
ad19981d | 108 | static void CMP_Fixup (int, int); |
26ca5450 | 109 | static void BadOp (void); |
35c52694 | 110 | static void REP_Fixup (int, int); |
42164a71 L |
111 | static void HLE_Fixup1 (int, int); |
112 | static void HLE_Fixup2 (int, int); | |
113 | static void HLE_Fixup3 (int, int); | |
f5804c90 | 114 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 115 | static void XMM_Fixup (int, int); |
381d071f | 116 | static void CRC32_Fixup (int, int); |
eacc9c89 | 117 | static void FXSAVE_Fixup (int, int); |
f88c9eb0 SP |
118 | static void OP_LWPCB_E (int, int); |
119 | static void OP_LWP_E (int, int); | |
5dd85c99 SP |
120 | static void OP_Vex_2src_1 (int, int); |
121 | static void OP_Vex_2src_2 (int, int); | |
c1e679ec | 122 | |
f1f8f695 | 123 | static void MOVBE_Fixup (int, int); |
252b5132 | 124 | |
6608db57 | 125 | struct dis_private { |
252b5132 RH |
126 | /* Points to first byte not fetched. */ |
127 | bfd_byte *max_fetched; | |
0b1cf022 | 128 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 129 | bfd_vma insn_start; |
e396998b | 130 | int orig_sizeflag; |
252b5132 RH |
131 | jmp_buf bailout; |
132 | }; | |
133 | ||
cb712a9e L |
134 | enum address_mode |
135 | { | |
136 | mode_16bit, | |
137 | mode_32bit, | |
138 | mode_64bit | |
139 | }; | |
140 | ||
141 | enum address_mode address_mode; | |
52b15da3 | 142 | |
5076851f ILT |
143 | /* Flags for the prefixes for the current instruction. See below. */ |
144 | static int prefixes; | |
145 | ||
52b15da3 JH |
146 | /* REX prefix the current instruction. See below. */ |
147 | static int rex; | |
148 | /* Bits of REX we've already used. */ | |
149 | static int rex_used; | |
d869730d | 150 | /* REX bits in original REX prefix ignored. */ |
c0f3af97 | 151 | static int rex_ignored; |
52b15da3 JH |
152 | /* Mark parts used in the REX prefix. When we are testing for |
153 | empty prefix (for 8bit register REX extension), just mask it | |
154 | out. Otherwise test for REX bit is excuse for existence of REX | |
155 | only in case value is nonzero. */ | |
156 | #define USED_REX(value) \ | |
157 | { \ | |
158 | if (value) \ | |
161a04f6 L |
159 | { \ |
160 | if ((rex & value)) \ | |
161 | rex_used |= (value) | REX_OPCODE; \ | |
162 | } \ | |
52b15da3 | 163 | else \ |
161a04f6 | 164 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
165 | } |
166 | ||
7d421014 ILT |
167 | /* Flags for prefixes which we somehow handled when printing the |
168 | current instruction. */ | |
169 | static int used_prefixes; | |
170 | ||
5076851f ILT |
171 | /* Flags stored in PREFIXES. */ |
172 | #define PREFIX_REPZ 1 | |
173 | #define PREFIX_REPNZ 2 | |
174 | #define PREFIX_LOCK 4 | |
175 | #define PREFIX_CS 8 | |
176 | #define PREFIX_SS 0x10 | |
177 | #define PREFIX_DS 0x20 | |
178 | #define PREFIX_ES 0x40 | |
179 | #define PREFIX_FS 0x80 | |
180 | #define PREFIX_GS 0x100 | |
181 | #define PREFIX_DATA 0x200 | |
182 | #define PREFIX_ADDR 0x400 | |
183 | #define PREFIX_FWAIT 0x800 | |
184 | ||
252b5132 RH |
185 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
186 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
187 | on error. */ | |
188 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 189 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
190 | ? 1 : fetch_data ((info), (addr))) |
191 | ||
192 | static int | |
26ca5450 | 193 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
194 | { |
195 | int status; | |
6608db57 | 196 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
197 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
198 | ||
0b1cf022 | 199 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
200 | status = (*info->read_memory_func) (start, |
201 | priv->max_fetched, | |
202 | addr - priv->max_fetched, | |
203 | info); | |
204 | else | |
205 | status = -1; | |
252b5132 RH |
206 | if (status != 0) |
207 | { | |
7d421014 | 208 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
209 | print_insn_i386 will do something sensible. Otherwise, print |
210 | an error. We do that here because this is where we know | |
211 | STATUS. */ | |
7d421014 | 212 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 213 | (*info->memory_error_func) (status, start, info); |
252b5132 RH |
214 | longjmp (priv->bailout, 1); |
215 | } | |
216 | else | |
217 | priv->max_fetched = addr; | |
218 | return 1; | |
219 | } | |
220 | ||
ce518a5f | 221 | #define XX { NULL, 0 } |
592d1631 | 222 | #define Bad_Opcode NULL, { { NULL, 0 } } |
ce518a5f L |
223 | |
224 | #define Eb { OP_E, b_mode } | |
b6169b20 | 225 | #define EbS { OP_E, b_swap_mode } |
ce518a5f | 226 | #define Ev { OP_E, v_mode } |
b6169b20 | 227 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
228 | #define Ed { OP_E, d_mode } |
229 | #define Edq { OP_E, dq_mode } | |
230 | #define Edqw { OP_E, dqw_mode } | |
42903f7f L |
231 | #define Edqb { OP_E, dqb_mode } |
232 | #define Edqd { OP_E, dqd_mode } | |
09335d05 | 233 | #define Eq { OP_E, q_mode } |
ce518a5f L |
234 | #define indirEv { OP_indirE, stack_v_mode } |
235 | #define indirEp { OP_indirE, f_mode } | |
236 | #define stackEv { OP_E, stack_v_mode } | |
237 | #define Em { OP_E, m_mode } | |
238 | #define Ew { OP_E, w_mode } | |
239 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 240 | #define Ma { OP_M, a_mode } |
b844680a | 241 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 242 | #define Md { OP_M, d_mode } |
f1f8f695 | 243 | #define Mo { OP_M, o_mode } |
ce518a5f L |
244 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
245 | #define Mq { OP_M, q_mode } | |
4ee52178 | 246 | #define Mx { OP_M, x_mode } |
c0f3af97 | 247 | #define Mxmm { OP_M, xmm_mode } |
ce518a5f L |
248 | #define Gb { OP_G, b_mode } |
249 | #define Gv { OP_G, v_mode } | |
250 | #define Gd { OP_G, d_mode } | |
251 | #define Gdq { OP_G, dq_mode } | |
252 | #define Gm { OP_G, m_mode } | |
253 | #define Gw { OP_G, w_mode } | |
6f74c397 L |
254 | #define Rd { OP_R, d_mode } |
255 | #define Rm { OP_R, m_mode } | |
ce518a5f L |
256 | #define Ib { OP_I, b_mode } |
257 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
e3949f17 | 258 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
ce518a5f | 259 | #define Iv { OP_I, v_mode } |
7bb15c6f | 260 | #define sIv { OP_sI, v_mode } |
ce518a5f L |
261 | #define Iq { OP_I, q_mode } |
262 | #define Iv64 { OP_I64, v_mode } | |
263 | #define Iw { OP_I, w_mode } | |
264 | #define I1 { OP_I, const_1_mode } | |
265 | #define Jb { OP_J, b_mode } | |
266 | #define Jv { OP_J, v_mode } | |
267 | #define Cm { OP_C, m_mode } | |
268 | #define Dm { OP_D, m_mode } | |
269 | #define Td { OP_T, d_mode } | |
b844680a | 270 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
271 | |
272 | #define RMeAX { OP_REG, eAX_reg } | |
273 | #define RMeBX { OP_REG, eBX_reg } | |
274 | #define RMeCX { OP_REG, eCX_reg } | |
275 | #define RMeDX { OP_REG, eDX_reg } | |
276 | #define RMeSP { OP_REG, eSP_reg } | |
277 | #define RMeBP { OP_REG, eBP_reg } | |
278 | #define RMeSI { OP_REG, eSI_reg } | |
279 | #define RMeDI { OP_REG, eDI_reg } | |
280 | #define RMrAX { OP_REG, rAX_reg } | |
281 | #define RMrBX { OP_REG, rBX_reg } | |
282 | #define RMrCX { OP_REG, rCX_reg } | |
283 | #define RMrDX { OP_REG, rDX_reg } | |
284 | #define RMrSP { OP_REG, rSP_reg } | |
285 | #define RMrBP { OP_REG, rBP_reg } | |
286 | #define RMrSI { OP_REG, rSI_reg } | |
287 | #define RMrDI { OP_REG, rDI_reg } | |
288 | #define RMAL { OP_REG, al_reg } | |
ce518a5f L |
289 | #define RMCL { OP_REG, cl_reg } |
290 | #define RMDL { OP_REG, dl_reg } | |
291 | #define RMBL { OP_REG, bl_reg } | |
292 | #define RMAH { OP_REG, ah_reg } | |
293 | #define RMCH { OP_REG, ch_reg } | |
294 | #define RMDH { OP_REG, dh_reg } | |
295 | #define RMBH { OP_REG, bh_reg } | |
296 | #define RMAX { OP_REG, ax_reg } | |
297 | #define RMDX { OP_REG, dx_reg } | |
298 | ||
299 | #define eAX { OP_IMREG, eAX_reg } | |
300 | #define eBX { OP_IMREG, eBX_reg } | |
301 | #define eCX { OP_IMREG, eCX_reg } | |
302 | #define eDX { OP_IMREG, eDX_reg } | |
303 | #define eSP { OP_IMREG, eSP_reg } | |
304 | #define eBP { OP_IMREG, eBP_reg } | |
305 | #define eSI { OP_IMREG, eSI_reg } | |
306 | #define eDI { OP_IMREG, eDI_reg } | |
307 | #define AL { OP_IMREG, al_reg } | |
308 | #define CL { OP_IMREG, cl_reg } | |
309 | #define DL { OP_IMREG, dl_reg } | |
310 | #define BL { OP_IMREG, bl_reg } | |
311 | #define AH { OP_IMREG, ah_reg } | |
312 | #define CH { OP_IMREG, ch_reg } | |
313 | #define DH { OP_IMREG, dh_reg } | |
314 | #define BH { OP_IMREG, bh_reg } | |
315 | #define AX { OP_IMREG, ax_reg } | |
316 | #define DX { OP_IMREG, dx_reg } | |
317 | #define zAX { OP_IMREG, z_mode_ax_reg } | |
318 | #define indirDX { OP_IMREG, indir_dx_reg } | |
319 | ||
320 | #define Sw { OP_SEG, w_mode } | |
321 | #define Sv { OP_SEG, v_mode } | |
322 | #define Ap { OP_DIR, 0 } | |
323 | #define Ob { OP_OFF64, b_mode } | |
324 | #define Ov { OP_OFF64, v_mode } | |
325 | #define Xb { OP_DSreg, eSI_reg } | |
326 | #define Xv { OP_DSreg, eSI_reg } | |
327 | #define Xz { OP_DSreg, eSI_reg } | |
328 | #define Yb { OP_ESreg, eDI_reg } | |
329 | #define Yv { OP_ESreg, eDI_reg } | |
330 | #define DSBX { OP_DSreg, eBX_reg } | |
331 | ||
332 | #define es { OP_REG, es_reg } | |
333 | #define ss { OP_REG, ss_reg } | |
334 | #define cs { OP_REG, cs_reg } | |
335 | #define ds { OP_REG, ds_reg } | |
336 | #define fs { OP_REG, fs_reg } | |
337 | #define gs { OP_REG, gs_reg } | |
338 | ||
339 | #define MX { OP_MMX, 0 } | |
340 | #define XM { OP_XMM, 0 } | |
539f890d | 341 | #define XMScalar { OP_XMM, scalar_mode } |
6c30d220 | 342 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
c0f3af97 | 343 | #define XMM { OP_XMM, xmm_mode } |
ce518a5f | 344 | #define EM { OP_EM, v_mode } |
b6169b20 | 345 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 346 | #define EMd { OP_EM, d_mode } |
14051056 | 347 | #define EMx { OP_EM, x_mode } |
8976381e | 348 | #define EXw { OP_EX, w_mode } |
09a2c6cf | 349 | #define EXd { OP_EX, d_mode } |
539f890d | 350 | #define EXdScalar { OP_EX, d_scalar_mode } |
fa99fab2 | 351 | #define EXdS { OP_EX, d_swap_mode } |
09a2c6cf | 352 | #define EXq { OP_EX, q_mode } |
539f890d L |
353 | #define EXqScalar { OP_EX, q_scalar_mode } |
354 | #define EXqScalarS { OP_EX, q_scalar_swap_mode } | |
b6169b20 | 355 | #define EXqS { OP_EX, q_swap_mode } |
09a2c6cf | 356 | #define EXx { OP_EX, x_mode } |
b6169b20 | 357 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 L |
358 | #define EXxmm { OP_EX, xmm_mode } |
359 | #define EXxmmq { OP_EX, xmmq_mode } | |
6c30d220 L |
360 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
361 | #define EXxmm_mw { OP_EX, xmm_mw_mode } | |
362 | #define EXxmm_md { OP_EX, xmm_md_mode } | |
363 | #define EXxmm_mq { OP_EX, xmm_mq_mode } | |
364 | #define EXxmmdw { OP_EX, xmmdw_mode } | |
365 | #define EXxmmqd { OP_EX, xmmqd_mode } | |
c0f3af97 | 366 | #define EXymmq { OP_EX, ymmq_mode } |
0bfee649 | 367 | #define EXVexWdq { OP_EX, vex_w_dq_mode } |
1c480963 | 368 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
ce518a5f L |
369 | #define MS { OP_MS, v_mode } |
370 | #define XS { OP_XS, v_mode } | |
09335d05 | 371 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 372 | #define MXC { OP_MXC, 0 } |
ce518a5f | 373 | #define OPSUF { OP_3DNowSuffix, 0 } |
ad19981d | 374 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 375 | #define XMM0 { XMM_Fixup, 0 } |
eacc9c89 | 376 | #define FXSAVE { FXSAVE_Fixup, 0 } |
5dd85c99 SP |
377 | #define Vex_2src_1 { OP_Vex_2src_1, 0 } |
378 | #define Vex_2src_2 { OP_Vex_2src_2, 0 } | |
252b5132 | 379 | |
c0f3af97 | 380 | #define Vex { OP_VEX, vex_mode } |
539f890d | 381 | #define VexScalar { OP_VEX, vex_scalar_mode } |
6c30d220 | 382 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
c0f3af97 L |
383 | #define Vex128 { OP_VEX, vex128_mode } |
384 | #define Vex256 { OP_VEX, vex256_mode } | |
cb21baef | 385 | #define VexGdq { OP_VEX, dq_mode } |
922d8de8 | 386 | #define VexI4 { VEXI4_Fixup, 0} |
c0f3af97 | 387 | #define EXdVex { OP_EX_Vex, d_mode } |
fa99fab2 | 388 | #define EXdVexS { OP_EX_Vex, d_swap_mode } |
539f890d | 389 | #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } |
c0f3af97 | 390 | #define EXqVex { OP_EX_Vex, q_mode } |
fa99fab2 | 391 | #define EXqVexS { OP_EX_Vex, q_swap_mode } |
539f890d | 392 | #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } |
922d8de8 DR |
393 | #define EXVexW { OP_EX_VexW, x_mode } |
394 | #define EXdVexW { OP_EX_VexW, d_mode } | |
395 | #define EXqVexW { OP_EX_VexW, q_mode } | |
a683cc34 | 396 | #define EXVexImmW { OP_EX_VexImmW, x_mode } |
c0f3af97 | 397 | #define XMVex { OP_XMM_Vex, 0 } |
539f890d | 398 | #define XMVexScalar { OP_XMM_Vex, scalar_mode } |
922d8de8 | 399 | #define XMVexW { OP_XMM_VexW, 0 } |
c0f3af97 L |
400 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
401 | #define PCLMUL { PCLMUL_Fixup, 0 } | |
402 | #define VZERO { VZERO_Fixup, 0 } | |
403 | #define VCMP { VCMP_Fixup, 0 } | |
c0f3af97 | 404 | |
6c30d220 L |
405 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
406 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } | |
407 | ||
35c52694 | 408 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
409 | #define Xbr { REP_Fixup, eSI_reg } |
410 | #define Xvr { REP_Fixup, eSI_reg } | |
411 | #define Ybr { REP_Fixup, eDI_reg } | |
412 | #define Yvr { REP_Fixup, eDI_reg } | |
413 | #define Yzr { REP_Fixup, eDI_reg } | |
414 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
415 | #define ALr { REP_Fixup, al_reg } | |
416 | #define eAXr { REP_Fixup, eAX_reg } | |
417 | ||
42164a71 L |
418 | /* Used handle HLE prefix for lockable instructions. */ |
419 | #define Ebh1 { HLE_Fixup1, b_mode } | |
420 | #define Evh1 { HLE_Fixup1, v_mode } | |
421 | #define Ebh2 { HLE_Fixup2, b_mode } | |
422 | #define Evh2 { HLE_Fixup2, v_mode } | |
423 | #define Ebh3 { HLE_Fixup3, b_mode } | |
424 | #define Evh3 { HLE_Fixup3, v_mode } | |
425 | ||
ce518a5f L |
426 | #define cond_jump_flag { NULL, cond_jump_mode } |
427 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 428 | |
252b5132 | 429 | /* bits in sizeflag */ |
252b5132 | 430 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
431 | #define AFLAG 2 |
432 | #define DFLAG 1 | |
433 | ||
51e7da1b L |
434 | enum |
435 | { | |
436 | /* byte operand */ | |
437 | b_mode = 1, | |
438 | /* byte operand with operand swapped */ | |
3873ba12 | 439 | b_swap_mode, |
e3949f17 L |
440 | /* byte operand, sign extend like 'T' suffix */ |
441 | b_T_mode, | |
51e7da1b | 442 | /* operand size depends on prefixes */ |
3873ba12 | 443 | v_mode, |
51e7da1b | 444 | /* operand size depends on prefixes with operand swapped */ |
3873ba12 | 445 | v_swap_mode, |
51e7da1b | 446 | /* word operand */ |
3873ba12 | 447 | w_mode, |
51e7da1b | 448 | /* double word operand */ |
3873ba12 | 449 | d_mode, |
51e7da1b | 450 | /* double word operand with operand swapped */ |
3873ba12 | 451 | d_swap_mode, |
51e7da1b | 452 | /* quad word operand */ |
3873ba12 | 453 | q_mode, |
51e7da1b | 454 | /* quad word operand with operand swapped */ |
3873ba12 | 455 | q_swap_mode, |
51e7da1b | 456 | /* ten-byte operand */ |
3873ba12 | 457 | t_mode, |
51e7da1b | 458 | /* 16-byte XMM or 32-byte YMM operand */ |
3873ba12 | 459 | x_mode, |
51e7da1b | 460 | /* 16-byte XMM or 32-byte YMM operand with operand swapped */ |
3873ba12 | 461 | x_swap_mode, |
51e7da1b | 462 | /* 16-byte XMM operand */ |
3873ba12 | 463 | xmm_mode, |
51e7da1b | 464 | /* 16-byte XMM or quad word operand */ |
3873ba12 | 465 | xmmq_mode, |
6c30d220 L |
466 | /* XMM register or byte memory operand */ |
467 | xmm_mb_mode, | |
468 | /* XMM register or word memory operand */ | |
469 | xmm_mw_mode, | |
470 | /* XMM register or double word memory operand */ | |
471 | xmm_md_mode, | |
472 | /* XMM register or quad word memory operand */ | |
473 | xmm_mq_mode, | |
474 | /* 16-byte XMM, word or double word operand */ | |
475 | xmmdw_mode, | |
476 | /* 16-byte XMM, double word or quad word operand */ | |
477 | xmmqd_mode, | |
51e7da1b | 478 | /* 32-byte YMM or quad word operand */ |
3873ba12 | 479 | ymmq_mode, |
6c30d220 L |
480 | /* 32-byte YMM or 16-byte word operand */ |
481 | ymmxmm_mode, | |
51e7da1b | 482 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
3873ba12 | 483 | m_mode, |
51e7da1b | 484 | /* pair of v_mode operands */ |
3873ba12 L |
485 | a_mode, |
486 | cond_jump_mode, | |
487 | loop_jcxz_mode, | |
51e7da1b | 488 | /* operand size depends on REX prefixes. */ |
3873ba12 | 489 | dq_mode, |
51e7da1b | 490 | /* registers like dq_mode, memory like w_mode. */ |
3873ba12 | 491 | dqw_mode, |
51e7da1b | 492 | /* 4- or 6-byte pointer operand */ |
3873ba12 L |
493 | f_mode, |
494 | const_1_mode, | |
51e7da1b | 495 | /* v_mode for stack-related opcodes. */ |
3873ba12 | 496 | stack_v_mode, |
51e7da1b | 497 | /* non-quad operand size depends on prefixes */ |
3873ba12 | 498 | z_mode, |
51e7da1b | 499 | /* 16-byte operand */ |
3873ba12 | 500 | o_mode, |
51e7da1b | 501 | /* registers like dq_mode, memory like b_mode. */ |
3873ba12 | 502 | dqb_mode, |
51e7da1b | 503 | /* registers like dq_mode, memory like d_mode. */ |
3873ba12 | 504 | dqd_mode, |
51e7da1b | 505 | /* normal vex mode */ |
3873ba12 | 506 | vex_mode, |
51e7da1b | 507 | /* 128bit vex mode */ |
3873ba12 | 508 | vex128_mode, |
51e7da1b | 509 | /* 256bit vex mode */ |
3873ba12 | 510 | vex256_mode, |
51e7da1b | 511 | /* operand size depends on the VEX.W bit. */ |
3873ba12 | 512 | vex_w_dq_mode, |
d55ee72f | 513 | |
6c30d220 L |
514 | /* Similar to vex_w_dq_mode, with VSIB dword indices. */ |
515 | vex_vsib_d_w_dq_mode, | |
516 | /* Similar to vex_w_dq_mode, with VSIB qword indices. */ | |
517 | vex_vsib_q_w_dq_mode, | |
518 | ||
539f890d L |
519 | /* scalar, ignore vector length. */ |
520 | scalar_mode, | |
521 | /* like d_mode, ignore vector length. */ | |
522 | d_scalar_mode, | |
523 | /* like d_swap_mode, ignore vector length. */ | |
524 | d_scalar_swap_mode, | |
525 | /* like q_mode, ignore vector length. */ | |
526 | q_scalar_mode, | |
527 | /* like q_swap_mode, ignore vector length. */ | |
528 | q_scalar_swap_mode, | |
529 | /* like vex_mode, ignore vector length. */ | |
530 | vex_scalar_mode, | |
1c480963 L |
531 | /* like vex_w_dq_mode, ignore vector length. */ |
532 | vex_scalar_w_dq_mode, | |
539f890d | 533 | |
3873ba12 L |
534 | es_reg, |
535 | cs_reg, | |
536 | ss_reg, | |
537 | ds_reg, | |
538 | fs_reg, | |
539 | gs_reg, | |
d55ee72f | 540 | |
3873ba12 L |
541 | eAX_reg, |
542 | eCX_reg, | |
543 | eDX_reg, | |
544 | eBX_reg, | |
545 | eSP_reg, | |
546 | eBP_reg, | |
547 | eSI_reg, | |
548 | eDI_reg, | |
d55ee72f | 549 | |
3873ba12 L |
550 | al_reg, |
551 | cl_reg, | |
552 | dl_reg, | |
553 | bl_reg, | |
554 | ah_reg, | |
555 | ch_reg, | |
556 | dh_reg, | |
557 | bh_reg, | |
d55ee72f | 558 | |
3873ba12 L |
559 | ax_reg, |
560 | cx_reg, | |
561 | dx_reg, | |
562 | bx_reg, | |
563 | sp_reg, | |
564 | bp_reg, | |
565 | si_reg, | |
566 | di_reg, | |
d55ee72f | 567 | |
3873ba12 L |
568 | rAX_reg, |
569 | rCX_reg, | |
570 | rDX_reg, | |
571 | rBX_reg, | |
572 | rSP_reg, | |
573 | rBP_reg, | |
574 | rSI_reg, | |
575 | rDI_reg, | |
d55ee72f | 576 | |
3873ba12 L |
577 | z_mode_ax_reg, |
578 | indir_dx_reg | |
51e7da1b | 579 | }; |
252b5132 | 580 | |
51e7da1b L |
581 | enum |
582 | { | |
583 | FLOATCODE = 1, | |
3873ba12 L |
584 | USE_REG_TABLE, |
585 | USE_MOD_TABLE, | |
586 | USE_RM_TABLE, | |
587 | USE_PREFIX_TABLE, | |
588 | USE_X86_64_TABLE, | |
589 | USE_3BYTE_TABLE, | |
f88c9eb0 | 590 | USE_XOP_8F_TABLE, |
3873ba12 L |
591 | USE_VEX_C4_TABLE, |
592 | USE_VEX_C5_TABLE, | |
9e30b8e0 L |
593 | USE_VEX_LEN_TABLE, |
594 | USE_VEX_W_TABLE | |
51e7da1b | 595 | }; |
6439fc28 | 596 | |
1ceb70f8 | 597 | #define FLOAT NULL, { { NULL, FLOATCODE } } |
4efba78c | 598 | |
4e7d34a6 | 599 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } } |
1ceb70f8 L |
600 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
601 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
602 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
603 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
604 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
605 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
f88c9eb0 | 606 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
c0f3af97 L |
607 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
608 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) | |
609 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) | |
9e30b8e0 | 610 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
1ceb70f8 | 611 | |
51e7da1b L |
612 | enum |
613 | { | |
614 | REG_80 = 0, | |
3873ba12 L |
615 | REG_81, |
616 | REG_82, | |
617 | REG_8F, | |
618 | REG_C0, | |
619 | REG_C1, | |
620 | REG_C6, | |
621 | REG_C7, | |
622 | REG_D0, | |
623 | REG_D1, | |
624 | REG_D2, | |
625 | REG_D3, | |
626 | REG_F6, | |
627 | REG_F7, | |
628 | REG_FE, | |
629 | REG_FF, | |
630 | REG_0F00, | |
631 | REG_0F01, | |
632 | REG_0F0D, | |
633 | REG_0F18, | |
634 | REG_0F71, | |
635 | REG_0F72, | |
636 | REG_0F73, | |
637 | REG_0FA6, | |
638 | REG_0FA7, | |
639 | REG_0FAE, | |
640 | REG_0FBA, | |
641 | REG_0FC7, | |
592a252b L |
642 | REG_VEX_0F71, |
643 | REG_VEX_0F72, | |
644 | REG_VEX_0F73, | |
645 | REG_VEX_0FAE, | |
f12dc422 | 646 | REG_VEX_0F38F3, |
f88c9eb0 | 647 | REG_XOP_LWPCB, |
2a2a0f38 QN |
648 | REG_XOP_LWP, |
649 | REG_XOP_TBM_01, | |
650 | REG_XOP_TBM_02 | |
51e7da1b | 651 | }; |
1ceb70f8 | 652 | |
51e7da1b L |
653 | enum |
654 | { | |
655 | MOD_8D = 0, | |
42164a71 L |
656 | MOD_C6_REG_7, |
657 | MOD_C7_REG_7, | |
3873ba12 L |
658 | MOD_0F01_REG_0, |
659 | MOD_0F01_REG_1, | |
660 | MOD_0F01_REG_2, | |
661 | MOD_0F01_REG_3, | |
662 | MOD_0F01_REG_7, | |
663 | MOD_0F12_PREFIX_0, | |
664 | MOD_0F13, | |
665 | MOD_0F16_PREFIX_0, | |
666 | MOD_0F17, | |
667 | MOD_0F18_REG_0, | |
668 | MOD_0F18_REG_1, | |
669 | MOD_0F18_REG_2, | |
670 | MOD_0F18_REG_3, | |
d7189fa5 RM |
671 | MOD_0F18_REG_4, |
672 | MOD_0F18_REG_5, | |
673 | MOD_0F18_REG_6, | |
674 | MOD_0F18_REG_7, | |
3873ba12 L |
675 | MOD_0F20, |
676 | MOD_0F21, | |
677 | MOD_0F22, | |
678 | MOD_0F23, | |
679 | MOD_0F24, | |
680 | MOD_0F26, | |
681 | MOD_0F2B_PREFIX_0, | |
682 | MOD_0F2B_PREFIX_1, | |
683 | MOD_0F2B_PREFIX_2, | |
684 | MOD_0F2B_PREFIX_3, | |
685 | MOD_0F51, | |
686 | MOD_0F71_REG_2, | |
687 | MOD_0F71_REG_4, | |
688 | MOD_0F71_REG_6, | |
689 | MOD_0F72_REG_2, | |
690 | MOD_0F72_REG_4, | |
691 | MOD_0F72_REG_6, | |
692 | MOD_0F73_REG_2, | |
693 | MOD_0F73_REG_3, | |
694 | MOD_0F73_REG_6, | |
695 | MOD_0F73_REG_7, | |
696 | MOD_0FAE_REG_0, | |
697 | MOD_0FAE_REG_1, | |
698 | MOD_0FAE_REG_2, | |
699 | MOD_0FAE_REG_3, | |
700 | MOD_0FAE_REG_4, | |
701 | MOD_0FAE_REG_5, | |
702 | MOD_0FAE_REG_6, | |
703 | MOD_0FAE_REG_7, | |
704 | MOD_0FB2, | |
705 | MOD_0FB4, | |
706 | MOD_0FB5, | |
707 | MOD_0FC7_REG_6, | |
708 | MOD_0FC7_REG_7, | |
709 | MOD_0FD7, | |
710 | MOD_0FE7_PREFIX_2, | |
711 | MOD_0FF0_PREFIX_3, | |
712 | MOD_0F382A_PREFIX_2, | |
713 | MOD_62_32BIT, | |
714 | MOD_C4_32BIT, | |
715 | MOD_C5_32BIT, | |
592a252b L |
716 | MOD_VEX_0F12_PREFIX_0, |
717 | MOD_VEX_0F13, | |
718 | MOD_VEX_0F16_PREFIX_0, | |
719 | MOD_VEX_0F17, | |
720 | MOD_VEX_0F2B, | |
721 | MOD_VEX_0F50, | |
722 | MOD_VEX_0F71_REG_2, | |
723 | MOD_VEX_0F71_REG_4, | |
724 | MOD_VEX_0F71_REG_6, | |
725 | MOD_VEX_0F72_REG_2, | |
726 | MOD_VEX_0F72_REG_4, | |
727 | MOD_VEX_0F72_REG_6, | |
728 | MOD_VEX_0F73_REG_2, | |
729 | MOD_VEX_0F73_REG_3, | |
730 | MOD_VEX_0F73_REG_6, | |
731 | MOD_VEX_0F73_REG_7, | |
732 | MOD_VEX_0FAE_REG_2, | |
733 | MOD_VEX_0FAE_REG_3, | |
734 | MOD_VEX_0FD7_PREFIX_2, | |
735 | MOD_VEX_0FE7_PREFIX_2, | |
736 | MOD_VEX_0FF0_PREFIX_3, | |
592a252b L |
737 | MOD_VEX_0F381A_PREFIX_2, |
738 | MOD_VEX_0F382A_PREFIX_2, | |
739 | MOD_VEX_0F382C_PREFIX_2, | |
740 | MOD_VEX_0F382D_PREFIX_2, | |
741 | MOD_VEX_0F382E_PREFIX_2, | |
6c30d220 L |
742 | MOD_VEX_0F382F_PREFIX_2, |
743 | MOD_VEX_0F385A_PREFIX_2, | |
744 | MOD_VEX_0F388C_PREFIX_2, | |
745 | MOD_VEX_0F388E_PREFIX_2, | |
51e7da1b | 746 | }; |
1ceb70f8 | 747 | |
51e7da1b L |
748 | enum |
749 | { | |
42164a71 L |
750 | RM_C6_REG_7 = 0, |
751 | RM_C7_REG_7, | |
752 | RM_0F01_REG_0, | |
3873ba12 L |
753 | RM_0F01_REG_1, |
754 | RM_0F01_REG_2, | |
755 | RM_0F01_REG_3, | |
756 | RM_0F01_REG_7, | |
757 | RM_0FAE_REG_5, | |
758 | RM_0FAE_REG_6, | |
759 | RM_0FAE_REG_7 | |
51e7da1b | 760 | }; |
1ceb70f8 | 761 | |
51e7da1b L |
762 | enum |
763 | { | |
764 | PREFIX_90 = 0, | |
3873ba12 L |
765 | PREFIX_0F10, |
766 | PREFIX_0F11, | |
767 | PREFIX_0F12, | |
768 | PREFIX_0F16, | |
769 | PREFIX_0F2A, | |
770 | PREFIX_0F2B, | |
771 | PREFIX_0F2C, | |
772 | PREFIX_0F2D, | |
773 | PREFIX_0F2E, | |
774 | PREFIX_0F2F, | |
775 | PREFIX_0F51, | |
776 | PREFIX_0F52, | |
777 | PREFIX_0F53, | |
778 | PREFIX_0F58, | |
779 | PREFIX_0F59, | |
780 | PREFIX_0F5A, | |
781 | PREFIX_0F5B, | |
782 | PREFIX_0F5C, | |
783 | PREFIX_0F5D, | |
784 | PREFIX_0F5E, | |
785 | PREFIX_0F5F, | |
786 | PREFIX_0F60, | |
787 | PREFIX_0F61, | |
788 | PREFIX_0F62, | |
789 | PREFIX_0F6C, | |
790 | PREFIX_0F6D, | |
791 | PREFIX_0F6F, | |
792 | PREFIX_0F70, | |
793 | PREFIX_0F73_REG_3, | |
794 | PREFIX_0F73_REG_7, | |
795 | PREFIX_0F78, | |
796 | PREFIX_0F79, | |
797 | PREFIX_0F7C, | |
798 | PREFIX_0F7D, | |
799 | PREFIX_0F7E, | |
800 | PREFIX_0F7F, | |
c7b8aa3a L |
801 | PREFIX_0FAE_REG_0, |
802 | PREFIX_0FAE_REG_1, | |
803 | PREFIX_0FAE_REG_2, | |
804 | PREFIX_0FAE_REG_3, | |
3873ba12 | 805 | PREFIX_0FB8, |
f12dc422 | 806 | PREFIX_0FBC, |
3873ba12 L |
807 | PREFIX_0FBD, |
808 | PREFIX_0FC2, | |
809 | PREFIX_0FC3, | |
810 | PREFIX_0FC7_REG_6, | |
811 | PREFIX_0FD0, | |
812 | PREFIX_0FD6, | |
813 | PREFIX_0FE6, | |
814 | PREFIX_0FE7, | |
815 | PREFIX_0FF0, | |
816 | PREFIX_0FF7, | |
817 | PREFIX_0F3810, | |
818 | PREFIX_0F3814, | |
819 | PREFIX_0F3815, | |
820 | PREFIX_0F3817, | |
821 | PREFIX_0F3820, | |
822 | PREFIX_0F3821, | |
823 | PREFIX_0F3822, | |
824 | PREFIX_0F3823, | |
825 | PREFIX_0F3824, | |
826 | PREFIX_0F3825, | |
827 | PREFIX_0F3828, | |
828 | PREFIX_0F3829, | |
829 | PREFIX_0F382A, | |
830 | PREFIX_0F382B, | |
831 | PREFIX_0F3830, | |
832 | PREFIX_0F3831, | |
833 | PREFIX_0F3832, | |
834 | PREFIX_0F3833, | |
835 | PREFIX_0F3834, | |
836 | PREFIX_0F3835, | |
837 | PREFIX_0F3837, | |
838 | PREFIX_0F3838, | |
839 | PREFIX_0F3839, | |
840 | PREFIX_0F383A, | |
841 | PREFIX_0F383B, | |
842 | PREFIX_0F383C, | |
843 | PREFIX_0F383D, | |
844 | PREFIX_0F383E, | |
845 | PREFIX_0F383F, | |
846 | PREFIX_0F3840, | |
847 | PREFIX_0F3841, | |
848 | PREFIX_0F3880, | |
849 | PREFIX_0F3881, | |
6c30d220 | 850 | PREFIX_0F3882, |
3873ba12 L |
851 | PREFIX_0F38DB, |
852 | PREFIX_0F38DC, | |
853 | PREFIX_0F38DD, | |
854 | PREFIX_0F38DE, | |
855 | PREFIX_0F38DF, | |
856 | PREFIX_0F38F0, | |
857 | PREFIX_0F38F1, | |
e2e1fcde | 858 | PREFIX_0F38F6, |
3873ba12 L |
859 | PREFIX_0F3A08, |
860 | PREFIX_0F3A09, | |
861 | PREFIX_0F3A0A, | |
862 | PREFIX_0F3A0B, | |
863 | PREFIX_0F3A0C, | |
864 | PREFIX_0F3A0D, | |
865 | PREFIX_0F3A0E, | |
866 | PREFIX_0F3A14, | |
867 | PREFIX_0F3A15, | |
868 | PREFIX_0F3A16, | |
869 | PREFIX_0F3A17, | |
870 | PREFIX_0F3A20, | |
871 | PREFIX_0F3A21, | |
872 | PREFIX_0F3A22, | |
873 | PREFIX_0F3A40, | |
874 | PREFIX_0F3A41, | |
875 | PREFIX_0F3A42, | |
876 | PREFIX_0F3A44, | |
877 | PREFIX_0F3A60, | |
878 | PREFIX_0F3A61, | |
879 | PREFIX_0F3A62, | |
880 | PREFIX_0F3A63, | |
881 | PREFIX_0F3ADF, | |
592a252b L |
882 | PREFIX_VEX_0F10, |
883 | PREFIX_VEX_0F11, | |
884 | PREFIX_VEX_0F12, | |
885 | PREFIX_VEX_0F16, | |
886 | PREFIX_VEX_0F2A, | |
887 | PREFIX_VEX_0F2C, | |
888 | PREFIX_VEX_0F2D, | |
889 | PREFIX_VEX_0F2E, | |
890 | PREFIX_VEX_0F2F, | |
891 | PREFIX_VEX_0F51, | |
892 | PREFIX_VEX_0F52, | |
893 | PREFIX_VEX_0F53, | |
894 | PREFIX_VEX_0F58, | |
895 | PREFIX_VEX_0F59, | |
896 | PREFIX_VEX_0F5A, | |
897 | PREFIX_VEX_0F5B, | |
898 | PREFIX_VEX_0F5C, | |
899 | PREFIX_VEX_0F5D, | |
900 | PREFIX_VEX_0F5E, | |
901 | PREFIX_VEX_0F5F, | |
902 | PREFIX_VEX_0F60, | |
903 | PREFIX_VEX_0F61, | |
904 | PREFIX_VEX_0F62, | |
905 | PREFIX_VEX_0F63, | |
906 | PREFIX_VEX_0F64, | |
907 | PREFIX_VEX_0F65, | |
908 | PREFIX_VEX_0F66, | |
909 | PREFIX_VEX_0F67, | |
910 | PREFIX_VEX_0F68, | |
911 | PREFIX_VEX_0F69, | |
912 | PREFIX_VEX_0F6A, | |
913 | PREFIX_VEX_0F6B, | |
914 | PREFIX_VEX_0F6C, | |
915 | PREFIX_VEX_0F6D, | |
916 | PREFIX_VEX_0F6E, | |
917 | PREFIX_VEX_0F6F, | |
918 | PREFIX_VEX_0F70, | |
919 | PREFIX_VEX_0F71_REG_2, | |
920 | PREFIX_VEX_0F71_REG_4, | |
921 | PREFIX_VEX_0F71_REG_6, | |
922 | PREFIX_VEX_0F72_REG_2, | |
923 | PREFIX_VEX_0F72_REG_4, | |
924 | PREFIX_VEX_0F72_REG_6, | |
925 | PREFIX_VEX_0F73_REG_2, | |
926 | PREFIX_VEX_0F73_REG_3, | |
927 | PREFIX_VEX_0F73_REG_6, | |
928 | PREFIX_VEX_0F73_REG_7, | |
929 | PREFIX_VEX_0F74, | |
930 | PREFIX_VEX_0F75, | |
931 | PREFIX_VEX_0F76, | |
932 | PREFIX_VEX_0F77, | |
933 | PREFIX_VEX_0F7C, | |
934 | PREFIX_VEX_0F7D, | |
935 | PREFIX_VEX_0F7E, | |
936 | PREFIX_VEX_0F7F, | |
937 | PREFIX_VEX_0FC2, | |
938 | PREFIX_VEX_0FC4, | |
939 | PREFIX_VEX_0FC5, | |
940 | PREFIX_VEX_0FD0, | |
941 | PREFIX_VEX_0FD1, | |
942 | PREFIX_VEX_0FD2, | |
943 | PREFIX_VEX_0FD3, | |
944 | PREFIX_VEX_0FD4, | |
945 | PREFIX_VEX_0FD5, | |
946 | PREFIX_VEX_0FD6, | |
947 | PREFIX_VEX_0FD7, | |
948 | PREFIX_VEX_0FD8, | |
949 | PREFIX_VEX_0FD9, | |
950 | PREFIX_VEX_0FDA, | |
951 | PREFIX_VEX_0FDB, | |
952 | PREFIX_VEX_0FDC, | |
953 | PREFIX_VEX_0FDD, | |
954 | PREFIX_VEX_0FDE, | |
955 | PREFIX_VEX_0FDF, | |
956 | PREFIX_VEX_0FE0, | |
957 | PREFIX_VEX_0FE1, | |
958 | PREFIX_VEX_0FE2, | |
959 | PREFIX_VEX_0FE3, | |
960 | PREFIX_VEX_0FE4, | |
961 | PREFIX_VEX_0FE5, | |
962 | PREFIX_VEX_0FE6, | |
963 | PREFIX_VEX_0FE7, | |
964 | PREFIX_VEX_0FE8, | |
965 | PREFIX_VEX_0FE9, | |
966 | PREFIX_VEX_0FEA, | |
967 | PREFIX_VEX_0FEB, | |
968 | PREFIX_VEX_0FEC, | |
969 | PREFIX_VEX_0FED, | |
970 | PREFIX_VEX_0FEE, | |
971 | PREFIX_VEX_0FEF, | |
972 | PREFIX_VEX_0FF0, | |
973 | PREFIX_VEX_0FF1, | |
974 | PREFIX_VEX_0FF2, | |
975 | PREFIX_VEX_0FF3, | |
976 | PREFIX_VEX_0FF4, | |
977 | PREFIX_VEX_0FF5, | |
978 | PREFIX_VEX_0FF6, | |
979 | PREFIX_VEX_0FF7, | |
980 | PREFIX_VEX_0FF8, | |
981 | PREFIX_VEX_0FF9, | |
982 | PREFIX_VEX_0FFA, | |
983 | PREFIX_VEX_0FFB, | |
984 | PREFIX_VEX_0FFC, | |
985 | PREFIX_VEX_0FFD, | |
986 | PREFIX_VEX_0FFE, | |
987 | PREFIX_VEX_0F3800, | |
988 | PREFIX_VEX_0F3801, | |
989 | PREFIX_VEX_0F3802, | |
990 | PREFIX_VEX_0F3803, | |
991 | PREFIX_VEX_0F3804, | |
992 | PREFIX_VEX_0F3805, | |
993 | PREFIX_VEX_0F3806, | |
994 | PREFIX_VEX_0F3807, | |
995 | PREFIX_VEX_0F3808, | |
996 | PREFIX_VEX_0F3809, | |
997 | PREFIX_VEX_0F380A, | |
998 | PREFIX_VEX_0F380B, | |
999 | PREFIX_VEX_0F380C, | |
1000 | PREFIX_VEX_0F380D, | |
1001 | PREFIX_VEX_0F380E, | |
1002 | PREFIX_VEX_0F380F, | |
1003 | PREFIX_VEX_0F3813, | |
6c30d220 | 1004 | PREFIX_VEX_0F3816, |
592a252b L |
1005 | PREFIX_VEX_0F3817, |
1006 | PREFIX_VEX_0F3818, | |
1007 | PREFIX_VEX_0F3819, | |
1008 | PREFIX_VEX_0F381A, | |
1009 | PREFIX_VEX_0F381C, | |
1010 | PREFIX_VEX_0F381D, | |
1011 | PREFIX_VEX_0F381E, | |
1012 | PREFIX_VEX_0F3820, | |
1013 | PREFIX_VEX_0F3821, | |
1014 | PREFIX_VEX_0F3822, | |
1015 | PREFIX_VEX_0F3823, | |
1016 | PREFIX_VEX_0F3824, | |
1017 | PREFIX_VEX_0F3825, | |
1018 | PREFIX_VEX_0F3828, | |
1019 | PREFIX_VEX_0F3829, | |
1020 | PREFIX_VEX_0F382A, | |
1021 | PREFIX_VEX_0F382B, | |
1022 | PREFIX_VEX_0F382C, | |
1023 | PREFIX_VEX_0F382D, | |
1024 | PREFIX_VEX_0F382E, | |
1025 | PREFIX_VEX_0F382F, | |
1026 | PREFIX_VEX_0F3830, | |
1027 | PREFIX_VEX_0F3831, | |
1028 | PREFIX_VEX_0F3832, | |
1029 | PREFIX_VEX_0F3833, | |
1030 | PREFIX_VEX_0F3834, | |
1031 | PREFIX_VEX_0F3835, | |
6c30d220 | 1032 | PREFIX_VEX_0F3836, |
592a252b L |
1033 | PREFIX_VEX_0F3837, |
1034 | PREFIX_VEX_0F3838, | |
1035 | PREFIX_VEX_0F3839, | |
1036 | PREFIX_VEX_0F383A, | |
1037 | PREFIX_VEX_0F383B, | |
1038 | PREFIX_VEX_0F383C, | |
1039 | PREFIX_VEX_0F383D, | |
1040 | PREFIX_VEX_0F383E, | |
1041 | PREFIX_VEX_0F383F, | |
1042 | PREFIX_VEX_0F3840, | |
1043 | PREFIX_VEX_0F3841, | |
6c30d220 L |
1044 | PREFIX_VEX_0F3845, |
1045 | PREFIX_VEX_0F3846, | |
1046 | PREFIX_VEX_0F3847, | |
1047 | PREFIX_VEX_0F3858, | |
1048 | PREFIX_VEX_0F3859, | |
1049 | PREFIX_VEX_0F385A, | |
1050 | PREFIX_VEX_0F3878, | |
1051 | PREFIX_VEX_0F3879, | |
1052 | PREFIX_VEX_0F388C, | |
1053 | PREFIX_VEX_0F388E, | |
1054 | PREFIX_VEX_0F3890, | |
1055 | PREFIX_VEX_0F3891, | |
1056 | PREFIX_VEX_0F3892, | |
1057 | PREFIX_VEX_0F3893, | |
592a252b L |
1058 | PREFIX_VEX_0F3896, |
1059 | PREFIX_VEX_0F3897, | |
1060 | PREFIX_VEX_0F3898, | |
1061 | PREFIX_VEX_0F3899, | |
1062 | PREFIX_VEX_0F389A, | |
1063 | PREFIX_VEX_0F389B, | |
1064 | PREFIX_VEX_0F389C, | |
1065 | PREFIX_VEX_0F389D, | |
1066 | PREFIX_VEX_0F389E, | |
1067 | PREFIX_VEX_0F389F, | |
1068 | PREFIX_VEX_0F38A6, | |
1069 | PREFIX_VEX_0F38A7, | |
1070 | PREFIX_VEX_0F38A8, | |
1071 | PREFIX_VEX_0F38A9, | |
1072 | PREFIX_VEX_0F38AA, | |
1073 | PREFIX_VEX_0F38AB, | |
1074 | PREFIX_VEX_0F38AC, | |
1075 | PREFIX_VEX_0F38AD, | |
1076 | PREFIX_VEX_0F38AE, | |
1077 | PREFIX_VEX_0F38AF, | |
1078 | PREFIX_VEX_0F38B6, | |
1079 | PREFIX_VEX_0F38B7, | |
1080 | PREFIX_VEX_0F38B8, | |
1081 | PREFIX_VEX_0F38B9, | |
1082 | PREFIX_VEX_0F38BA, | |
1083 | PREFIX_VEX_0F38BB, | |
1084 | PREFIX_VEX_0F38BC, | |
1085 | PREFIX_VEX_0F38BD, | |
1086 | PREFIX_VEX_0F38BE, | |
1087 | PREFIX_VEX_0F38BF, | |
1088 | PREFIX_VEX_0F38DB, | |
1089 | PREFIX_VEX_0F38DC, | |
1090 | PREFIX_VEX_0F38DD, | |
1091 | PREFIX_VEX_0F38DE, | |
1092 | PREFIX_VEX_0F38DF, | |
f12dc422 L |
1093 | PREFIX_VEX_0F38F2, |
1094 | PREFIX_VEX_0F38F3_REG_1, | |
1095 | PREFIX_VEX_0F38F3_REG_2, | |
1096 | PREFIX_VEX_0F38F3_REG_3, | |
6c30d220 L |
1097 | PREFIX_VEX_0F38F5, |
1098 | PREFIX_VEX_0F38F6, | |
f12dc422 | 1099 | PREFIX_VEX_0F38F7, |
6c30d220 L |
1100 | PREFIX_VEX_0F3A00, |
1101 | PREFIX_VEX_0F3A01, | |
1102 | PREFIX_VEX_0F3A02, | |
592a252b L |
1103 | PREFIX_VEX_0F3A04, |
1104 | PREFIX_VEX_0F3A05, | |
1105 | PREFIX_VEX_0F3A06, | |
1106 | PREFIX_VEX_0F3A08, | |
1107 | PREFIX_VEX_0F3A09, | |
1108 | PREFIX_VEX_0F3A0A, | |
1109 | PREFIX_VEX_0F3A0B, | |
1110 | PREFIX_VEX_0F3A0C, | |
1111 | PREFIX_VEX_0F3A0D, | |
1112 | PREFIX_VEX_0F3A0E, | |
1113 | PREFIX_VEX_0F3A0F, | |
1114 | PREFIX_VEX_0F3A14, | |
1115 | PREFIX_VEX_0F3A15, | |
1116 | PREFIX_VEX_0F3A16, | |
1117 | PREFIX_VEX_0F3A17, | |
1118 | PREFIX_VEX_0F3A18, | |
1119 | PREFIX_VEX_0F3A19, | |
1120 | PREFIX_VEX_0F3A1D, | |
1121 | PREFIX_VEX_0F3A20, | |
1122 | PREFIX_VEX_0F3A21, | |
1123 | PREFIX_VEX_0F3A22, | |
6c30d220 L |
1124 | PREFIX_VEX_0F3A38, |
1125 | PREFIX_VEX_0F3A39, | |
592a252b L |
1126 | PREFIX_VEX_0F3A40, |
1127 | PREFIX_VEX_0F3A41, | |
1128 | PREFIX_VEX_0F3A42, | |
1129 | PREFIX_VEX_0F3A44, | |
6c30d220 | 1130 | PREFIX_VEX_0F3A46, |
592a252b L |
1131 | PREFIX_VEX_0F3A48, |
1132 | PREFIX_VEX_0F3A49, | |
1133 | PREFIX_VEX_0F3A4A, | |
1134 | PREFIX_VEX_0F3A4B, | |
1135 | PREFIX_VEX_0F3A4C, | |
1136 | PREFIX_VEX_0F3A5C, | |
1137 | PREFIX_VEX_0F3A5D, | |
1138 | PREFIX_VEX_0F3A5E, | |
1139 | PREFIX_VEX_0F3A5F, | |
1140 | PREFIX_VEX_0F3A60, | |
1141 | PREFIX_VEX_0F3A61, | |
1142 | PREFIX_VEX_0F3A62, | |
1143 | PREFIX_VEX_0F3A63, | |
1144 | PREFIX_VEX_0F3A68, | |
1145 | PREFIX_VEX_0F3A69, | |
1146 | PREFIX_VEX_0F3A6A, | |
1147 | PREFIX_VEX_0F3A6B, | |
1148 | PREFIX_VEX_0F3A6C, | |
1149 | PREFIX_VEX_0F3A6D, | |
1150 | PREFIX_VEX_0F3A6E, | |
1151 | PREFIX_VEX_0F3A6F, | |
1152 | PREFIX_VEX_0F3A78, | |
1153 | PREFIX_VEX_0F3A79, | |
1154 | PREFIX_VEX_0F3A7A, | |
1155 | PREFIX_VEX_0F3A7B, | |
1156 | PREFIX_VEX_0F3A7C, | |
1157 | PREFIX_VEX_0F3A7D, | |
1158 | PREFIX_VEX_0F3A7E, | |
1159 | PREFIX_VEX_0F3A7F, | |
6c30d220 L |
1160 | PREFIX_VEX_0F3ADF, |
1161 | PREFIX_VEX_0F3AF0 | |
51e7da1b | 1162 | }; |
4e7d34a6 | 1163 | |
51e7da1b L |
1164 | enum |
1165 | { | |
1166 | X86_64_06 = 0, | |
3873ba12 L |
1167 | X86_64_07, |
1168 | X86_64_0D, | |
1169 | X86_64_16, | |
1170 | X86_64_17, | |
1171 | X86_64_1E, | |
1172 | X86_64_1F, | |
1173 | X86_64_27, | |
1174 | X86_64_2F, | |
1175 | X86_64_37, | |
1176 | X86_64_3F, | |
1177 | X86_64_60, | |
1178 | X86_64_61, | |
1179 | X86_64_62, | |
1180 | X86_64_63, | |
1181 | X86_64_6D, | |
1182 | X86_64_6F, | |
1183 | X86_64_9A, | |
1184 | X86_64_C4, | |
1185 | X86_64_C5, | |
1186 | X86_64_CE, | |
1187 | X86_64_D4, | |
1188 | X86_64_D5, | |
1189 | X86_64_EA, | |
1190 | X86_64_0F01_REG_0, | |
1191 | X86_64_0F01_REG_1, | |
1192 | X86_64_0F01_REG_2, | |
1193 | X86_64_0F01_REG_3 | |
51e7da1b | 1194 | }; |
4e7d34a6 | 1195 | |
51e7da1b L |
1196 | enum |
1197 | { | |
1198 | THREE_BYTE_0F38 = 0, | |
3873ba12 L |
1199 | THREE_BYTE_0F3A, |
1200 | THREE_BYTE_0F7A | |
51e7da1b | 1201 | }; |
4e7d34a6 | 1202 | |
f88c9eb0 SP |
1203 | enum |
1204 | { | |
5dd85c99 SP |
1205 | XOP_08 = 0, |
1206 | XOP_09, | |
f88c9eb0 SP |
1207 | XOP_0A |
1208 | }; | |
1209 | ||
51e7da1b L |
1210 | enum |
1211 | { | |
1212 | VEX_0F = 0, | |
3873ba12 L |
1213 | VEX_0F38, |
1214 | VEX_0F3A | |
51e7da1b | 1215 | }; |
c0f3af97 | 1216 | |
51e7da1b L |
1217 | enum |
1218 | { | |
592a252b L |
1219 | VEX_LEN_0F10_P_1 = 0, |
1220 | VEX_LEN_0F10_P_3, | |
1221 | VEX_LEN_0F11_P_1, | |
1222 | VEX_LEN_0F11_P_3, | |
1223 | VEX_LEN_0F12_P_0_M_0, | |
1224 | VEX_LEN_0F12_P_0_M_1, | |
1225 | VEX_LEN_0F12_P_2, | |
1226 | VEX_LEN_0F13_M_0, | |
1227 | VEX_LEN_0F16_P_0_M_0, | |
1228 | VEX_LEN_0F16_P_0_M_1, | |
1229 | VEX_LEN_0F16_P_2, | |
1230 | VEX_LEN_0F17_M_0, | |
1231 | VEX_LEN_0F2A_P_1, | |
1232 | VEX_LEN_0F2A_P_3, | |
1233 | VEX_LEN_0F2C_P_1, | |
1234 | VEX_LEN_0F2C_P_3, | |
1235 | VEX_LEN_0F2D_P_1, | |
1236 | VEX_LEN_0F2D_P_3, | |
1237 | VEX_LEN_0F2E_P_0, | |
1238 | VEX_LEN_0F2E_P_2, | |
1239 | VEX_LEN_0F2F_P_0, | |
1240 | VEX_LEN_0F2F_P_2, | |
1241 | VEX_LEN_0F51_P_1, | |
1242 | VEX_LEN_0F51_P_3, | |
1243 | VEX_LEN_0F52_P_1, | |
1244 | VEX_LEN_0F53_P_1, | |
1245 | VEX_LEN_0F58_P_1, | |
1246 | VEX_LEN_0F58_P_3, | |
1247 | VEX_LEN_0F59_P_1, | |
1248 | VEX_LEN_0F59_P_3, | |
1249 | VEX_LEN_0F5A_P_1, | |
1250 | VEX_LEN_0F5A_P_3, | |
1251 | VEX_LEN_0F5C_P_1, | |
1252 | VEX_LEN_0F5C_P_3, | |
1253 | VEX_LEN_0F5D_P_1, | |
1254 | VEX_LEN_0F5D_P_3, | |
1255 | VEX_LEN_0F5E_P_1, | |
1256 | VEX_LEN_0F5E_P_3, | |
1257 | VEX_LEN_0F5F_P_1, | |
1258 | VEX_LEN_0F5F_P_3, | |
592a252b | 1259 | VEX_LEN_0F6E_P_2, |
592a252b L |
1260 | VEX_LEN_0F7E_P_1, |
1261 | VEX_LEN_0F7E_P_2, | |
1262 | VEX_LEN_0FAE_R_2_M_0, | |
1263 | VEX_LEN_0FAE_R_3_M_0, | |
1264 | VEX_LEN_0FC2_P_1, | |
1265 | VEX_LEN_0FC2_P_3, | |
1266 | VEX_LEN_0FC4_P_2, | |
1267 | VEX_LEN_0FC5_P_2, | |
592a252b | 1268 | VEX_LEN_0FD6_P_2, |
592a252b | 1269 | VEX_LEN_0FF7_P_2, |
6c30d220 L |
1270 | VEX_LEN_0F3816_P_2, |
1271 | VEX_LEN_0F3819_P_2, | |
592a252b | 1272 | VEX_LEN_0F381A_P_2_M_0, |
6c30d220 | 1273 | VEX_LEN_0F3836_P_2, |
592a252b | 1274 | VEX_LEN_0F3841_P_2, |
6c30d220 | 1275 | VEX_LEN_0F385A_P_2_M_0, |
592a252b L |
1276 | VEX_LEN_0F38DB_P_2, |
1277 | VEX_LEN_0F38DC_P_2, | |
1278 | VEX_LEN_0F38DD_P_2, | |
1279 | VEX_LEN_0F38DE_P_2, | |
1280 | VEX_LEN_0F38DF_P_2, | |
f12dc422 L |
1281 | VEX_LEN_0F38F2_P_0, |
1282 | VEX_LEN_0F38F3_R_1_P_0, | |
1283 | VEX_LEN_0F38F3_R_2_P_0, | |
1284 | VEX_LEN_0F38F3_R_3_P_0, | |
6c30d220 L |
1285 | VEX_LEN_0F38F5_P_0, |
1286 | VEX_LEN_0F38F5_P_1, | |
1287 | VEX_LEN_0F38F5_P_3, | |
1288 | VEX_LEN_0F38F6_P_3, | |
f12dc422 | 1289 | VEX_LEN_0F38F7_P_0, |
6c30d220 L |
1290 | VEX_LEN_0F38F7_P_1, |
1291 | VEX_LEN_0F38F7_P_2, | |
1292 | VEX_LEN_0F38F7_P_3, | |
1293 | VEX_LEN_0F3A00_P_2, | |
1294 | VEX_LEN_0F3A01_P_2, | |
592a252b L |
1295 | VEX_LEN_0F3A06_P_2, |
1296 | VEX_LEN_0F3A0A_P_2, | |
1297 | VEX_LEN_0F3A0B_P_2, | |
592a252b L |
1298 | VEX_LEN_0F3A14_P_2, |
1299 | VEX_LEN_0F3A15_P_2, | |
1300 | VEX_LEN_0F3A16_P_2, | |
1301 | VEX_LEN_0F3A17_P_2, | |
1302 | VEX_LEN_0F3A18_P_2, | |
1303 | VEX_LEN_0F3A19_P_2, | |
1304 | VEX_LEN_0F3A20_P_2, | |
1305 | VEX_LEN_0F3A21_P_2, | |
1306 | VEX_LEN_0F3A22_P_2, | |
6c30d220 L |
1307 | VEX_LEN_0F3A38_P_2, |
1308 | VEX_LEN_0F3A39_P_2, | |
592a252b | 1309 | VEX_LEN_0F3A41_P_2, |
592a252b | 1310 | VEX_LEN_0F3A44_P_2, |
6c30d220 | 1311 | VEX_LEN_0F3A46_P_2, |
592a252b L |
1312 | VEX_LEN_0F3A60_P_2, |
1313 | VEX_LEN_0F3A61_P_2, | |
1314 | VEX_LEN_0F3A62_P_2, | |
1315 | VEX_LEN_0F3A63_P_2, | |
1316 | VEX_LEN_0F3A6A_P_2, | |
1317 | VEX_LEN_0F3A6B_P_2, | |
1318 | VEX_LEN_0F3A6E_P_2, | |
1319 | VEX_LEN_0F3A6F_P_2, | |
1320 | VEX_LEN_0F3A7A_P_2, | |
1321 | VEX_LEN_0F3A7B_P_2, | |
1322 | VEX_LEN_0F3A7E_P_2, | |
1323 | VEX_LEN_0F3A7F_P_2, | |
1324 | VEX_LEN_0F3ADF_P_2, | |
6c30d220 | 1325 | VEX_LEN_0F3AF0_P_3, |
ff688e1f L |
1326 | VEX_LEN_0FXOP_08_CC, |
1327 | VEX_LEN_0FXOP_08_CD, | |
1328 | VEX_LEN_0FXOP_08_CE, | |
1329 | VEX_LEN_0FXOP_08_CF, | |
1330 | VEX_LEN_0FXOP_08_EC, | |
1331 | VEX_LEN_0FXOP_08_ED, | |
1332 | VEX_LEN_0FXOP_08_EE, | |
1333 | VEX_LEN_0FXOP_08_EF, | |
592a252b L |
1334 | VEX_LEN_0FXOP_09_80, |
1335 | VEX_LEN_0FXOP_09_81 | |
51e7da1b | 1336 | }; |
c0f3af97 | 1337 | |
9e30b8e0 L |
1338 | enum |
1339 | { | |
592a252b L |
1340 | VEX_W_0F10_P_0 = 0, |
1341 | VEX_W_0F10_P_1, | |
1342 | VEX_W_0F10_P_2, | |
1343 | VEX_W_0F10_P_3, | |
1344 | VEX_W_0F11_P_0, | |
1345 | VEX_W_0F11_P_1, | |
1346 | VEX_W_0F11_P_2, | |
1347 | VEX_W_0F11_P_3, | |
1348 | VEX_W_0F12_P_0_M_0, | |
1349 | VEX_W_0F12_P_0_M_1, | |
1350 | VEX_W_0F12_P_1, | |
1351 | VEX_W_0F12_P_2, | |
1352 | VEX_W_0F12_P_3, | |
1353 | VEX_W_0F13_M_0, | |
1354 | VEX_W_0F14, | |
1355 | VEX_W_0F15, | |
1356 | VEX_W_0F16_P_0_M_0, | |
1357 | VEX_W_0F16_P_0_M_1, | |
1358 | VEX_W_0F16_P_1, | |
1359 | VEX_W_0F16_P_2, | |
1360 | VEX_W_0F17_M_0, | |
1361 | VEX_W_0F28, | |
1362 | VEX_W_0F29, | |
1363 | VEX_W_0F2B_M_0, | |
1364 | VEX_W_0F2E_P_0, | |
1365 | VEX_W_0F2E_P_2, | |
1366 | VEX_W_0F2F_P_0, | |
1367 | VEX_W_0F2F_P_2, | |
1368 | VEX_W_0F50_M_0, | |
1369 | VEX_W_0F51_P_0, | |
1370 | VEX_W_0F51_P_1, | |
1371 | VEX_W_0F51_P_2, | |
1372 | VEX_W_0F51_P_3, | |
1373 | VEX_W_0F52_P_0, | |
1374 | VEX_W_0F52_P_1, | |
1375 | VEX_W_0F53_P_0, | |
1376 | VEX_W_0F53_P_1, | |
1377 | VEX_W_0F58_P_0, | |
1378 | VEX_W_0F58_P_1, | |
1379 | VEX_W_0F58_P_2, | |
1380 | VEX_W_0F58_P_3, | |
1381 | VEX_W_0F59_P_0, | |
1382 | VEX_W_0F59_P_1, | |
1383 | VEX_W_0F59_P_2, | |
1384 | VEX_W_0F59_P_3, | |
1385 | VEX_W_0F5A_P_0, | |
1386 | VEX_W_0F5A_P_1, | |
1387 | VEX_W_0F5A_P_3, | |
1388 | VEX_W_0F5B_P_0, | |
1389 | VEX_W_0F5B_P_1, | |
1390 | VEX_W_0F5B_P_2, | |
1391 | VEX_W_0F5C_P_0, | |
1392 | VEX_W_0F5C_P_1, | |
1393 | VEX_W_0F5C_P_2, | |
1394 | VEX_W_0F5C_P_3, | |
1395 | VEX_W_0F5D_P_0, | |
1396 | VEX_W_0F5D_P_1, | |
1397 | VEX_W_0F5D_P_2, | |
1398 | VEX_W_0F5D_P_3, | |
1399 | VEX_W_0F5E_P_0, | |
1400 | VEX_W_0F5E_P_1, | |
1401 | VEX_W_0F5E_P_2, | |
1402 | VEX_W_0F5E_P_3, | |
1403 | VEX_W_0F5F_P_0, | |
1404 | VEX_W_0F5F_P_1, | |
1405 | VEX_W_0F5F_P_2, | |
1406 | VEX_W_0F5F_P_3, | |
1407 | VEX_W_0F60_P_2, | |
1408 | VEX_W_0F61_P_2, | |
1409 | VEX_W_0F62_P_2, | |
1410 | VEX_W_0F63_P_2, | |
1411 | VEX_W_0F64_P_2, | |
1412 | VEX_W_0F65_P_2, | |
1413 | VEX_W_0F66_P_2, | |
1414 | VEX_W_0F67_P_2, | |
1415 | VEX_W_0F68_P_2, | |
1416 | VEX_W_0F69_P_2, | |
1417 | VEX_W_0F6A_P_2, | |
1418 | VEX_W_0F6B_P_2, | |
1419 | VEX_W_0F6C_P_2, | |
1420 | VEX_W_0F6D_P_2, | |
1421 | VEX_W_0F6F_P_1, | |
1422 | VEX_W_0F6F_P_2, | |
1423 | VEX_W_0F70_P_1, | |
1424 | VEX_W_0F70_P_2, | |
1425 | VEX_W_0F70_P_3, | |
1426 | VEX_W_0F71_R_2_P_2, | |
1427 | VEX_W_0F71_R_4_P_2, | |
1428 | VEX_W_0F71_R_6_P_2, | |
1429 | VEX_W_0F72_R_2_P_2, | |
1430 | VEX_W_0F72_R_4_P_2, | |
1431 | VEX_W_0F72_R_6_P_2, | |
1432 | VEX_W_0F73_R_2_P_2, | |
1433 | VEX_W_0F73_R_3_P_2, | |
1434 | VEX_W_0F73_R_6_P_2, | |
1435 | VEX_W_0F73_R_7_P_2, | |
1436 | VEX_W_0F74_P_2, | |
1437 | VEX_W_0F75_P_2, | |
1438 | VEX_W_0F76_P_2, | |
1439 | VEX_W_0F77_P_0, | |
1440 | VEX_W_0F7C_P_2, | |
1441 | VEX_W_0F7C_P_3, | |
1442 | VEX_W_0F7D_P_2, | |
1443 | VEX_W_0F7D_P_3, | |
1444 | VEX_W_0F7E_P_1, | |
1445 | VEX_W_0F7F_P_1, | |
1446 | VEX_W_0F7F_P_2, | |
1447 | VEX_W_0FAE_R_2_M_0, | |
1448 | VEX_W_0FAE_R_3_M_0, | |
1449 | VEX_W_0FC2_P_0, | |
1450 | VEX_W_0FC2_P_1, | |
1451 | VEX_W_0FC2_P_2, | |
1452 | VEX_W_0FC2_P_3, | |
1453 | VEX_W_0FC4_P_2, | |
1454 | VEX_W_0FC5_P_2, | |
1455 | VEX_W_0FD0_P_2, | |
1456 | VEX_W_0FD0_P_3, | |
1457 | VEX_W_0FD1_P_2, | |
1458 | VEX_W_0FD2_P_2, | |
1459 | VEX_W_0FD3_P_2, | |
1460 | VEX_W_0FD4_P_2, | |
1461 | VEX_W_0FD5_P_2, | |
1462 | VEX_W_0FD6_P_2, | |
1463 | VEX_W_0FD7_P_2_M_1, | |
1464 | VEX_W_0FD8_P_2, | |
1465 | VEX_W_0FD9_P_2, | |
1466 | VEX_W_0FDA_P_2, | |
1467 | VEX_W_0FDB_P_2, | |
1468 | VEX_W_0FDC_P_2, | |
1469 | VEX_W_0FDD_P_2, | |
1470 | VEX_W_0FDE_P_2, | |
1471 | VEX_W_0FDF_P_2, | |
1472 | VEX_W_0FE0_P_2, | |
1473 | VEX_W_0FE1_P_2, | |
1474 | VEX_W_0FE2_P_2, | |
1475 | VEX_W_0FE3_P_2, | |
1476 | VEX_W_0FE4_P_2, | |
1477 | VEX_W_0FE5_P_2, | |
1478 | VEX_W_0FE6_P_1, | |
1479 | VEX_W_0FE6_P_2, | |
1480 | VEX_W_0FE6_P_3, | |
1481 | VEX_W_0FE7_P_2_M_0, | |
1482 | VEX_W_0FE8_P_2, | |
1483 | VEX_W_0FE9_P_2, | |
1484 | VEX_W_0FEA_P_2, | |
1485 | VEX_W_0FEB_P_2, | |
1486 | VEX_W_0FEC_P_2, | |
1487 | VEX_W_0FED_P_2, | |
1488 | VEX_W_0FEE_P_2, | |
1489 | VEX_W_0FEF_P_2, | |
1490 | VEX_W_0FF0_P_3_M_0, | |
1491 | VEX_W_0FF1_P_2, | |
1492 | VEX_W_0FF2_P_2, | |
1493 | VEX_W_0FF3_P_2, | |
1494 | VEX_W_0FF4_P_2, | |
1495 | VEX_W_0FF5_P_2, | |
1496 | VEX_W_0FF6_P_2, | |
1497 | VEX_W_0FF7_P_2, | |
1498 | VEX_W_0FF8_P_2, | |
1499 | VEX_W_0FF9_P_2, | |
1500 | VEX_W_0FFA_P_2, | |
1501 | VEX_W_0FFB_P_2, | |
1502 | VEX_W_0FFC_P_2, | |
1503 | VEX_W_0FFD_P_2, | |
1504 | VEX_W_0FFE_P_2, | |
1505 | VEX_W_0F3800_P_2, | |
1506 | VEX_W_0F3801_P_2, | |
1507 | VEX_W_0F3802_P_2, | |
1508 | VEX_W_0F3803_P_2, | |
1509 | VEX_W_0F3804_P_2, | |
1510 | VEX_W_0F3805_P_2, | |
1511 | VEX_W_0F3806_P_2, | |
1512 | VEX_W_0F3807_P_2, | |
1513 | VEX_W_0F3808_P_2, | |
1514 | VEX_W_0F3809_P_2, | |
1515 | VEX_W_0F380A_P_2, | |
1516 | VEX_W_0F380B_P_2, | |
1517 | VEX_W_0F380C_P_2, | |
1518 | VEX_W_0F380D_P_2, | |
1519 | VEX_W_0F380E_P_2, | |
1520 | VEX_W_0F380F_P_2, | |
6c30d220 | 1521 | VEX_W_0F3816_P_2, |
592a252b | 1522 | VEX_W_0F3817_P_2, |
6c30d220 L |
1523 | VEX_W_0F3818_P_2, |
1524 | VEX_W_0F3819_P_2, | |
592a252b L |
1525 | VEX_W_0F381A_P_2_M_0, |
1526 | VEX_W_0F381C_P_2, | |
1527 | VEX_W_0F381D_P_2, | |
1528 | VEX_W_0F381E_P_2, | |
1529 | VEX_W_0F3820_P_2, | |
1530 | VEX_W_0F3821_P_2, | |
1531 | VEX_W_0F3822_P_2, | |
1532 | VEX_W_0F3823_P_2, | |
1533 | VEX_W_0F3824_P_2, | |
1534 | VEX_W_0F3825_P_2, | |
1535 | VEX_W_0F3828_P_2, | |
1536 | VEX_W_0F3829_P_2, | |
1537 | VEX_W_0F382A_P_2_M_0, | |
1538 | VEX_W_0F382B_P_2, | |
1539 | VEX_W_0F382C_P_2_M_0, | |
1540 | VEX_W_0F382D_P_2_M_0, | |
1541 | VEX_W_0F382E_P_2_M_0, | |
1542 | VEX_W_0F382F_P_2_M_0, | |
1543 | VEX_W_0F3830_P_2, | |
1544 | VEX_W_0F3831_P_2, | |
1545 | VEX_W_0F3832_P_2, | |
1546 | VEX_W_0F3833_P_2, | |
1547 | VEX_W_0F3834_P_2, | |
1548 | VEX_W_0F3835_P_2, | |
6c30d220 | 1549 | VEX_W_0F3836_P_2, |
592a252b L |
1550 | VEX_W_0F3837_P_2, |
1551 | VEX_W_0F3838_P_2, | |
1552 | VEX_W_0F3839_P_2, | |
1553 | VEX_W_0F383A_P_2, | |
1554 | VEX_W_0F383B_P_2, | |
1555 | VEX_W_0F383C_P_2, | |
1556 | VEX_W_0F383D_P_2, | |
1557 | VEX_W_0F383E_P_2, | |
1558 | VEX_W_0F383F_P_2, | |
1559 | VEX_W_0F3840_P_2, | |
1560 | VEX_W_0F3841_P_2, | |
6c30d220 L |
1561 | VEX_W_0F3846_P_2, |
1562 | VEX_W_0F3858_P_2, | |
1563 | VEX_W_0F3859_P_2, | |
1564 | VEX_W_0F385A_P_2_M_0, | |
1565 | VEX_W_0F3878_P_2, | |
1566 | VEX_W_0F3879_P_2, | |
592a252b L |
1567 | VEX_W_0F38DB_P_2, |
1568 | VEX_W_0F38DC_P_2, | |
1569 | VEX_W_0F38DD_P_2, | |
1570 | VEX_W_0F38DE_P_2, | |
1571 | VEX_W_0F38DF_P_2, | |
6c30d220 L |
1572 | VEX_W_0F3A00_P_2, |
1573 | VEX_W_0F3A01_P_2, | |
1574 | VEX_W_0F3A02_P_2, | |
592a252b L |
1575 | VEX_W_0F3A04_P_2, |
1576 | VEX_W_0F3A05_P_2, | |
1577 | VEX_W_0F3A06_P_2, | |
1578 | VEX_W_0F3A08_P_2, | |
1579 | VEX_W_0F3A09_P_2, | |
1580 | VEX_W_0F3A0A_P_2, | |
1581 | VEX_W_0F3A0B_P_2, | |
1582 | VEX_W_0F3A0C_P_2, | |
1583 | VEX_W_0F3A0D_P_2, | |
1584 | VEX_W_0F3A0E_P_2, | |
1585 | VEX_W_0F3A0F_P_2, | |
1586 | VEX_W_0F3A14_P_2, | |
1587 | VEX_W_0F3A15_P_2, | |
1588 | VEX_W_0F3A18_P_2, | |
1589 | VEX_W_0F3A19_P_2, | |
1590 | VEX_W_0F3A20_P_2, | |
1591 | VEX_W_0F3A21_P_2, | |
6c30d220 L |
1592 | VEX_W_0F3A38_P_2, |
1593 | VEX_W_0F3A39_P_2, | |
592a252b L |
1594 | VEX_W_0F3A40_P_2, |
1595 | VEX_W_0F3A41_P_2, | |
1596 | VEX_W_0F3A42_P_2, | |
1597 | VEX_W_0F3A44_P_2, | |
6c30d220 | 1598 | VEX_W_0F3A46_P_2, |
592a252b L |
1599 | VEX_W_0F3A48_P_2, |
1600 | VEX_W_0F3A49_P_2, | |
1601 | VEX_W_0F3A4A_P_2, | |
1602 | VEX_W_0F3A4B_P_2, | |
1603 | VEX_W_0F3A4C_P_2, | |
1604 | VEX_W_0F3A60_P_2, | |
1605 | VEX_W_0F3A61_P_2, | |
1606 | VEX_W_0F3A62_P_2, | |
1607 | VEX_W_0F3A63_P_2, | |
1608 | VEX_W_0F3ADF_P_2 | |
9e30b8e0 L |
1609 | }; |
1610 | ||
26ca5450 | 1611 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
1612 | |
1613 | struct dis386 { | |
2da11e11 | 1614 | const char *name; |
ce518a5f L |
1615 | struct |
1616 | { | |
1617 | op_rtn rtn; | |
1618 | int bytemode; | |
1619 | } op[MAX_OPERANDS]; | |
252b5132 RH |
1620 | }; |
1621 | ||
1622 | /* Upper case letters in the instruction names here are macros. | |
1623 | 'A' => print 'b' if no register operands or suffix_always is true | |
1624 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 1625 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 1626 | size prefix |
ed7841b3 | 1627 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 1628 | suffix_always is true |
252b5132 | 1629 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 1630 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 1631 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 1632 | 'H' => print ",pt" or ",pn" branch hint |
9306ca4a | 1633 | 'I' => honor following macro letter even in Intel mode (implemented only |
98b528ac | 1634 | for some of the macro letters) |
9306ca4a | 1635 | 'J' => print 'l' |
42903f7f | 1636 | 'K' => print 'd' or 'q' if rex prefix is present. |
252b5132 | 1637 | 'L' => print 'l' if suffix_always is true |
9d141669 | 1638 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 1639 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 1640 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
52b15da3 | 1641 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
98b528ac L |
1642 | or suffix_always is true. print 'q' if rex prefix is present. |
1643 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always | |
1644 | is true | |
a35ca55a | 1645 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 1646 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
6439fc28 AM |
1647 | 'T' => print 'q' in 64bit mode and behave as 'P' otherwise |
1648 | 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise | |
1a114b12 | 1649 | 'V' => print 'q' in 64bit mode and behave as 'S' otherwise |
a35ca55a | 1650 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 1651 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
8a72226a L |
1652 | 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and |
1653 | suffix_always is true. | |
6dd5059a | 1654 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
9d141669 | 1655 | '!' => change condition from true to false or from false to true. |
98b528ac L |
1656 | '%' => add 1 upper case letter to the macro. |
1657 | ||
1658 | 2 upper case letter macros: | |
c0f3af97 L |
1659 | "XY" => print 'x' or 'y' if no register operands or suffix_always |
1660 | is true. | |
4b06377f L |
1661 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
1662 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand | |
98b528ac | 1663 | or suffix_always is true |
4b06377f L |
1664 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
1665 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise | |
1666 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise | |
6c30d220 | 1667 | "LW" => print 'd', 'q' depending on the VEX.W bit |
52b15da3 | 1668 | |
6439fc28 AM |
1669 | Many of the above letters print nothing in Intel mode. See "putop" |
1670 | for the details. | |
52b15da3 | 1671 | |
6439fc28 | 1672 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 1673 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 1674 | |
6439fc28 | 1675 | static const struct dis386 dis386[] = { |
252b5132 | 1676 | /* 00 */ |
42164a71 L |
1677 | { "addB", { Ebh1, Gb } }, |
1678 | { "addS", { Evh1, Gv } }, | |
c7532693 L |
1679 | { "addB", { Gb, EbS } }, |
1680 | { "addS", { Gv, EvS } }, | |
ce518a5f L |
1681 | { "addB", { AL, Ib } }, |
1682 | { "addS", { eAX, Iv } }, | |
4e7d34a6 L |
1683 | { X86_64_TABLE (X86_64_06) }, |
1684 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 1685 | /* 08 */ |
42164a71 L |
1686 | { "orB", { Ebh1, Gb } }, |
1687 | { "orS", { Evh1, Gv } }, | |
c7532693 L |
1688 | { "orB", { Gb, EbS } }, |
1689 | { "orS", { Gv, EvS } }, | |
ce518a5f L |
1690 | { "orB", { AL, Ib } }, |
1691 | { "orS", { eAX, Iv } }, | |
4e7d34a6 | 1692 | { X86_64_TABLE (X86_64_0D) }, |
592d1631 | 1693 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
252b5132 | 1694 | /* 10 */ |
42164a71 L |
1695 | { "adcB", { Ebh1, Gb } }, |
1696 | { "adcS", { Evh1, Gv } }, | |
c7532693 L |
1697 | { "adcB", { Gb, EbS } }, |
1698 | { "adcS", { Gv, EvS } }, | |
ce518a5f L |
1699 | { "adcB", { AL, Ib } }, |
1700 | { "adcS", { eAX, Iv } }, | |
4e7d34a6 L |
1701 | { X86_64_TABLE (X86_64_16) }, |
1702 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 1703 | /* 18 */ |
42164a71 L |
1704 | { "sbbB", { Ebh1, Gb } }, |
1705 | { "sbbS", { Evh1, Gv } }, | |
c7532693 L |
1706 | { "sbbB", { Gb, EbS } }, |
1707 | { "sbbS", { Gv, EvS } }, | |
ce518a5f L |
1708 | { "sbbB", { AL, Ib } }, |
1709 | { "sbbS", { eAX, Iv } }, | |
4e7d34a6 L |
1710 | { X86_64_TABLE (X86_64_1E) }, |
1711 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 1712 | /* 20 */ |
42164a71 L |
1713 | { "andB", { Ebh1, Gb } }, |
1714 | { "andS", { Evh1, Gv } }, | |
c7532693 L |
1715 | { "andB", { Gb, EbS } }, |
1716 | { "andS", { Gv, EvS } }, | |
ce518a5f L |
1717 | { "andB", { AL, Ib } }, |
1718 | { "andS", { eAX, Iv } }, | |
592d1631 | 1719 | { Bad_Opcode }, /* SEG ES prefix */ |
4e7d34a6 | 1720 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 1721 | /* 28 */ |
42164a71 L |
1722 | { "subB", { Ebh1, Gb } }, |
1723 | { "subS", { Evh1, Gv } }, | |
c7532693 L |
1724 | { "subB", { Gb, EbS } }, |
1725 | { "subS", { Gv, EvS } }, | |
ce518a5f L |
1726 | { "subB", { AL, Ib } }, |
1727 | { "subS", { eAX, Iv } }, | |
592d1631 | 1728 | { Bad_Opcode }, /* SEG CS prefix */ |
4e7d34a6 | 1729 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 1730 | /* 30 */ |
42164a71 L |
1731 | { "xorB", { Ebh1, Gb } }, |
1732 | { "xorS", { Evh1, Gv } }, | |
c7532693 L |
1733 | { "xorB", { Gb, EbS } }, |
1734 | { "xorS", { Gv, EvS } }, | |
ce518a5f L |
1735 | { "xorB", { AL, Ib } }, |
1736 | { "xorS", { eAX, Iv } }, | |
592d1631 | 1737 | { Bad_Opcode }, /* SEG SS prefix */ |
4e7d34a6 | 1738 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 1739 | /* 38 */ |
ce518a5f L |
1740 | { "cmpB", { Eb, Gb } }, |
1741 | { "cmpS", { Ev, Gv } }, | |
c7532693 L |
1742 | { "cmpB", { Gb, EbS } }, |
1743 | { "cmpS", { Gv, EvS } }, | |
ce518a5f L |
1744 | { "cmpB", { AL, Ib } }, |
1745 | { "cmpS", { eAX, Iv } }, | |
592d1631 | 1746 | { Bad_Opcode }, /* SEG DS prefix */ |
4e7d34a6 | 1747 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 1748 | /* 40 */ |
ce518a5f L |
1749 | { "inc{S|}", { RMeAX } }, |
1750 | { "inc{S|}", { RMeCX } }, | |
1751 | { "inc{S|}", { RMeDX } }, | |
1752 | { "inc{S|}", { RMeBX } }, | |
1753 | { "inc{S|}", { RMeSP } }, | |
1754 | { "inc{S|}", { RMeBP } }, | |
1755 | { "inc{S|}", { RMeSI } }, | |
1756 | { "inc{S|}", { RMeDI } }, | |
252b5132 | 1757 | /* 48 */ |
ce518a5f L |
1758 | { "dec{S|}", { RMeAX } }, |
1759 | { "dec{S|}", { RMeCX } }, | |
1760 | { "dec{S|}", { RMeDX } }, | |
1761 | { "dec{S|}", { RMeBX } }, | |
1762 | { "dec{S|}", { RMeSP } }, | |
1763 | { "dec{S|}", { RMeBP } }, | |
1764 | { "dec{S|}", { RMeSI } }, | |
1765 | { "dec{S|}", { RMeDI } }, | |
252b5132 | 1766 | /* 50 */ |
ce518a5f L |
1767 | { "pushV", { RMrAX } }, |
1768 | { "pushV", { RMrCX } }, | |
1769 | { "pushV", { RMrDX } }, | |
1770 | { "pushV", { RMrBX } }, | |
1771 | { "pushV", { RMrSP } }, | |
1772 | { "pushV", { RMrBP } }, | |
1773 | { "pushV", { RMrSI } }, | |
1774 | { "pushV", { RMrDI } }, | |
252b5132 | 1775 | /* 58 */ |
ce518a5f L |
1776 | { "popV", { RMrAX } }, |
1777 | { "popV", { RMrCX } }, | |
1778 | { "popV", { RMrDX } }, | |
1779 | { "popV", { RMrBX } }, | |
1780 | { "popV", { RMrSP } }, | |
1781 | { "popV", { RMrBP } }, | |
1782 | { "popV", { RMrSI } }, | |
1783 | { "popV", { RMrDI } }, | |
252b5132 | 1784 | /* 60 */ |
4e7d34a6 L |
1785 | { X86_64_TABLE (X86_64_60) }, |
1786 | { X86_64_TABLE (X86_64_61) }, | |
1787 | { X86_64_TABLE (X86_64_62) }, | |
1788 | { X86_64_TABLE (X86_64_63) }, | |
592d1631 L |
1789 | { Bad_Opcode }, /* seg fs */ |
1790 | { Bad_Opcode }, /* seg gs */ | |
1791 | { Bad_Opcode }, /* op size prefix */ | |
1792 | { Bad_Opcode }, /* adr size prefix */ | |
252b5132 | 1793 | /* 68 */ |
d9e3625e | 1794 | { "pushT", { sIv } }, |
ce518a5f | 1795 | { "imulS", { Gv, Ev, Iv } }, |
e3949f17 | 1796 | { "pushT", { sIbT } }, |
ce518a5f | 1797 | { "imulS", { Gv, Ev, sIb } }, |
7c52e0e8 | 1798 | { "ins{b|}", { Ybr, indirDX } }, |
4e7d34a6 | 1799 | { X86_64_TABLE (X86_64_6D) }, |
7c52e0e8 | 1800 | { "outs{b|}", { indirDXr, Xb } }, |
4e7d34a6 | 1801 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 1802 | /* 70 */ |
ce518a5f L |
1803 | { "joH", { Jb, XX, cond_jump_flag } }, |
1804 | { "jnoH", { Jb, XX, cond_jump_flag } }, | |
1805 | { "jbH", { Jb, XX, cond_jump_flag } }, | |
1806 | { "jaeH", { Jb, XX, cond_jump_flag } }, | |
1807 | { "jeH", { Jb, XX, cond_jump_flag } }, | |
1808 | { "jneH", { Jb, XX, cond_jump_flag } }, | |
1809 | { "jbeH", { Jb, XX, cond_jump_flag } }, | |
1810 | { "jaH", { Jb, XX, cond_jump_flag } }, | |
252b5132 | 1811 | /* 78 */ |
ce518a5f L |
1812 | { "jsH", { Jb, XX, cond_jump_flag } }, |
1813 | { "jnsH", { Jb, XX, cond_jump_flag } }, | |
1814 | { "jpH", { Jb, XX, cond_jump_flag } }, | |
1815 | { "jnpH", { Jb, XX, cond_jump_flag } }, | |
1816 | { "jlH", { Jb, XX, cond_jump_flag } }, | |
1817 | { "jgeH", { Jb, XX, cond_jump_flag } }, | |
1818 | { "jleH", { Jb, XX, cond_jump_flag } }, | |
1819 | { "jgH", { Jb, XX, cond_jump_flag } }, | |
252b5132 | 1820 | /* 80 */ |
1ceb70f8 L |
1821 | { REG_TABLE (REG_80) }, |
1822 | { REG_TABLE (REG_81) }, | |
592d1631 | 1823 | { Bad_Opcode }, |
1ceb70f8 | 1824 | { REG_TABLE (REG_82) }, |
ce518a5f L |
1825 | { "testB", { Eb, Gb } }, |
1826 | { "testS", { Ev, Gv } }, | |
42164a71 L |
1827 | { "xchgB", { Ebh2, Gb } }, |
1828 | { "xchgS", { Evh2, Gv } }, | |
252b5132 | 1829 | /* 88 */ |
42164a71 L |
1830 | { "movB", { Ebh3, Gb } }, |
1831 | { "movS", { Evh3, Gv } }, | |
b6169b20 L |
1832 | { "movB", { Gb, EbS } }, |
1833 | { "movS", { Gv, EvS } }, | |
ce518a5f | 1834 | { "movD", { Sv, Sw } }, |
1ceb70f8 | 1835 | { MOD_TABLE (MOD_8D) }, |
ce518a5f | 1836 | { "movD", { Sw, Sv } }, |
1ceb70f8 | 1837 | { REG_TABLE (REG_8F) }, |
252b5132 | 1838 | /* 90 */ |
1ceb70f8 | 1839 | { PREFIX_TABLE (PREFIX_90) }, |
ce518a5f L |
1840 | { "xchgS", { RMeCX, eAX } }, |
1841 | { "xchgS", { RMeDX, eAX } }, | |
1842 | { "xchgS", { RMeBX, eAX } }, | |
1843 | { "xchgS", { RMeSP, eAX } }, | |
1844 | { "xchgS", { RMeBP, eAX } }, | |
1845 | { "xchgS", { RMeSI, eAX } }, | |
1846 | { "xchgS", { RMeDI, eAX } }, | |
252b5132 | 1847 | /* 98 */ |
7c52e0e8 L |
1848 | { "cW{t|}R", { XX } }, |
1849 | { "cR{t|}O", { XX } }, | |
4e7d34a6 | 1850 | { X86_64_TABLE (X86_64_9A) }, |
592d1631 | 1851 | { Bad_Opcode }, /* fwait */ |
ce518a5f L |
1852 | { "pushfT", { XX } }, |
1853 | { "popfT", { XX } }, | |
7c52e0e8 L |
1854 | { "sahf", { XX } }, |
1855 | { "lahf", { XX } }, | |
252b5132 | 1856 | /* a0 */ |
4b06377f L |
1857 | { "mov%LB", { AL, Ob } }, |
1858 | { "mov%LS", { eAX, Ov } }, | |
1859 | { "mov%LB", { Ob, AL } }, | |
1860 | { "mov%LS", { Ov, eAX } }, | |
7c52e0e8 L |
1861 | { "movs{b|}", { Ybr, Xb } }, |
1862 | { "movs{R|}", { Yvr, Xv } }, | |
1863 | { "cmps{b|}", { Xb, Yb } }, | |
1864 | { "cmps{R|}", { Xv, Yv } }, | |
252b5132 | 1865 | /* a8 */ |
ce518a5f L |
1866 | { "testB", { AL, Ib } }, |
1867 | { "testS", { eAX, Iv } }, | |
1868 | { "stosB", { Ybr, AL } }, | |
1869 | { "stosS", { Yvr, eAX } }, | |
1870 | { "lodsB", { ALr, Xb } }, | |
1871 | { "lodsS", { eAXr, Xv } }, | |
1872 | { "scasB", { AL, Yb } }, | |
1873 | { "scasS", { eAX, Yv } }, | |
252b5132 | 1874 | /* b0 */ |
ce518a5f L |
1875 | { "movB", { RMAL, Ib } }, |
1876 | { "movB", { RMCL, Ib } }, | |
1877 | { "movB", { RMDL, Ib } }, | |
1878 | { "movB", { RMBL, Ib } }, | |
1879 | { "movB", { RMAH, Ib } }, | |
1880 | { "movB", { RMCH, Ib } }, | |
1881 | { "movB", { RMDH, Ib } }, | |
1882 | { "movB", { RMBH, Ib } }, | |
252b5132 | 1883 | /* b8 */ |
4b06377f L |
1884 | { "mov%LV", { RMeAX, Iv64 } }, |
1885 | { "mov%LV", { RMeCX, Iv64 } }, | |
1886 | { "mov%LV", { RMeDX, Iv64 } }, | |
1887 | { "mov%LV", { RMeBX, Iv64 } }, | |
1888 | { "mov%LV", { RMeSP, Iv64 } }, | |
1889 | { "mov%LV", { RMeBP, Iv64 } }, | |
1890 | { "mov%LV", { RMeSI, Iv64 } }, | |
1891 | { "mov%LV", { RMeDI, Iv64 } }, | |
252b5132 | 1892 | /* c0 */ |
1ceb70f8 L |
1893 | { REG_TABLE (REG_C0) }, |
1894 | { REG_TABLE (REG_C1) }, | |
ce518a5f L |
1895 | { "retT", { Iw } }, |
1896 | { "retT", { XX } }, | |
4e7d34a6 L |
1897 | { X86_64_TABLE (X86_64_C4) }, |
1898 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
1899 | { REG_TABLE (REG_C6) }, |
1900 | { REG_TABLE (REG_C7) }, | |
252b5132 | 1901 | /* c8 */ |
ce518a5f L |
1902 | { "enterT", { Iw, Ib } }, |
1903 | { "leaveT", { XX } }, | |
ddab3d59 JB |
1904 | { "Jret{|f}P", { Iw } }, |
1905 | { "Jret{|f}P", { XX } }, | |
ce518a5f L |
1906 | { "int3", { XX } }, |
1907 | { "int", { Ib } }, | |
4e7d34a6 | 1908 | { X86_64_TABLE (X86_64_CE) }, |
ce518a5f | 1909 | { "iretP", { XX } }, |
252b5132 | 1910 | /* d0 */ |
1ceb70f8 L |
1911 | { REG_TABLE (REG_D0) }, |
1912 | { REG_TABLE (REG_D1) }, | |
1913 | { REG_TABLE (REG_D2) }, | |
1914 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
1915 | { X86_64_TABLE (X86_64_D4) }, |
1916 | { X86_64_TABLE (X86_64_D5) }, | |
592d1631 | 1917 | { Bad_Opcode }, |
ce518a5f | 1918 | { "xlat", { DSBX } }, |
252b5132 RH |
1919 | /* d8 */ |
1920 | { FLOAT }, | |
1921 | { FLOAT }, | |
1922 | { FLOAT }, | |
1923 | { FLOAT }, | |
1924 | { FLOAT }, | |
1925 | { FLOAT }, | |
1926 | { FLOAT }, | |
1927 | { FLOAT }, | |
1928 | /* e0 */ | |
ce518a5f L |
1929 | { "loopneFH", { Jb, XX, loop_jcxz_flag } }, |
1930 | { "loopeFH", { Jb, XX, loop_jcxz_flag } }, | |
1931 | { "loopFH", { Jb, XX, loop_jcxz_flag } }, | |
1932 | { "jEcxzH", { Jb, XX, loop_jcxz_flag } }, | |
1933 | { "inB", { AL, Ib } }, | |
1934 | { "inG", { zAX, Ib } }, | |
1935 | { "outB", { Ib, AL } }, | |
1936 | { "outG", { Ib, zAX } }, | |
252b5132 | 1937 | /* e8 */ |
ce518a5f L |
1938 | { "callT", { Jv } }, |
1939 | { "jmpT", { Jv } }, | |
4e7d34a6 | 1940 | { X86_64_TABLE (X86_64_EA) }, |
ce518a5f L |
1941 | { "jmp", { Jb } }, |
1942 | { "inB", { AL, indirDX } }, | |
1943 | { "inG", { zAX, indirDX } }, | |
1944 | { "outB", { indirDX, AL } }, | |
1945 | { "outG", { indirDX, zAX } }, | |
252b5132 | 1946 | /* f0 */ |
592d1631 | 1947 | { Bad_Opcode }, /* lock prefix */ |
ce518a5f | 1948 | { "icebp", { XX } }, |
592d1631 L |
1949 | { Bad_Opcode }, /* repne */ |
1950 | { Bad_Opcode }, /* repz */ | |
ce518a5f L |
1951 | { "hlt", { XX } }, |
1952 | { "cmc", { XX } }, | |
1ceb70f8 L |
1953 | { REG_TABLE (REG_F6) }, |
1954 | { REG_TABLE (REG_F7) }, | |
252b5132 | 1955 | /* f8 */ |
ce518a5f L |
1956 | { "clc", { XX } }, |
1957 | { "stc", { XX } }, | |
1958 | { "cli", { XX } }, | |
1959 | { "sti", { XX } }, | |
1960 | { "cld", { XX } }, | |
1961 | { "std", { XX } }, | |
1ceb70f8 L |
1962 | { REG_TABLE (REG_FE) }, |
1963 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
1964 | }; |
1965 | ||
6439fc28 | 1966 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 1967 | /* 00 */ |
1ceb70f8 L |
1968 | { REG_TABLE (REG_0F00 ) }, |
1969 | { REG_TABLE (REG_0F01 ) }, | |
ce518a5f L |
1970 | { "larS", { Gv, Ew } }, |
1971 | { "lslS", { Gv, Ew } }, | |
592d1631 | 1972 | { Bad_Opcode }, |
ce518a5f L |
1973 | { "syscall", { XX } }, |
1974 | { "clts", { XX } }, | |
1975 | { "sysretP", { XX } }, | |
252b5132 | 1976 | /* 08 */ |
ce518a5f L |
1977 | { "invd", { XX } }, |
1978 | { "wbinvd", { XX } }, | |
592d1631 | 1979 | { Bad_Opcode }, |
b414985b | 1980 | { "ud2", { XX } }, |
592d1631 | 1981 | { Bad_Opcode }, |
b5b1fc4f | 1982 | { REG_TABLE (REG_0F0D) }, |
ce518a5f L |
1983 | { "femms", { XX } }, |
1984 | { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */ | |
252b5132 | 1985 | /* 10 */ |
1ceb70f8 L |
1986 | { PREFIX_TABLE (PREFIX_0F10) }, |
1987 | { PREFIX_TABLE (PREFIX_0F11) }, | |
1988 | { PREFIX_TABLE (PREFIX_0F12) }, | |
1989 | { MOD_TABLE (MOD_0F13) }, | |
f2a421c4 L |
1990 | { "unpcklpX", { XM, EXx } }, |
1991 | { "unpckhpX", { XM, EXx } }, | |
1ceb70f8 L |
1992 | { PREFIX_TABLE (PREFIX_0F16) }, |
1993 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 1994 | /* 18 */ |
1ceb70f8 | 1995 | { REG_TABLE (REG_0F18) }, |
b5b1fc4f L |
1996 | { "nopQ", { Ev } }, |
1997 | { "nopQ", { Ev } }, | |
1998 | { "nopQ", { Ev } }, | |
1999 | { "nopQ", { Ev } }, | |
2000 | { "nopQ", { Ev } }, | |
2001 | { "nopQ", { Ev } }, | |
ce518a5f | 2002 | { "nopQ", { Ev } }, |
252b5132 | 2003 | /* 20 */ |
1ceb70f8 L |
2004 | { MOD_TABLE (MOD_0F20) }, |
2005 | { MOD_TABLE (MOD_0F21) }, | |
2006 | { MOD_TABLE (MOD_0F22) }, | |
2007 | { MOD_TABLE (MOD_0F23) }, | |
2008 | { MOD_TABLE (MOD_0F24) }, | |
592d1631 | 2009 | { Bad_Opcode }, |
1ceb70f8 | 2010 | { MOD_TABLE (MOD_0F26) }, |
592d1631 | 2011 | { Bad_Opcode }, |
252b5132 | 2012 | /* 28 */ |
09a2c6cf | 2013 | { "movapX", { XM, EXx } }, |
b6169b20 | 2014 | { "movapX", { EXxS, XM } }, |
1ceb70f8 L |
2015 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2016 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
2017 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
2018 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
2019 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
2020 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 2021 | /* 30 */ |
ce518a5f L |
2022 | { "wrmsr", { XX } }, |
2023 | { "rdtsc", { XX } }, | |
2024 | { "rdmsr", { XX } }, | |
2025 | { "rdpmc", { XX } }, | |
2026 | { "sysenter", { XX } }, | |
2027 | { "sysexit", { XX } }, | |
592d1631 | 2028 | { Bad_Opcode }, |
47dd174c | 2029 | { "getsec", { XX } }, |
252b5132 | 2030 | /* 38 */ |
4e7d34a6 | 2031 | { THREE_BYTE_TABLE (THREE_BYTE_0F38) }, |
592d1631 | 2032 | { Bad_Opcode }, |
4e7d34a6 | 2033 | { THREE_BYTE_TABLE (THREE_BYTE_0F3A) }, |
592d1631 L |
2034 | { Bad_Opcode }, |
2035 | { Bad_Opcode }, | |
2036 | { Bad_Opcode }, | |
2037 | { Bad_Opcode }, | |
2038 | { Bad_Opcode }, | |
252b5132 | 2039 | /* 40 */ |
b19d5385 JB |
2040 | { "cmovoS", { Gv, Ev } }, |
2041 | { "cmovnoS", { Gv, Ev } }, | |
2042 | { "cmovbS", { Gv, Ev } }, | |
2043 | { "cmovaeS", { Gv, Ev } }, | |
2044 | { "cmoveS", { Gv, Ev } }, | |
2045 | { "cmovneS", { Gv, Ev } }, | |
2046 | { "cmovbeS", { Gv, Ev } }, | |
2047 | { "cmovaS", { Gv, Ev } }, | |
252b5132 | 2048 | /* 48 */ |
b19d5385 JB |
2049 | { "cmovsS", { Gv, Ev } }, |
2050 | { "cmovnsS", { Gv, Ev } }, | |
2051 | { "cmovpS", { Gv, Ev } }, | |
2052 | { "cmovnpS", { Gv, Ev } }, | |
2053 | { "cmovlS", { Gv, Ev } }, | |
2054 | { "cmovgeS", { Gv, Ev } }, | |
2055 | { "cmovleS", { Gv, Ev } }, | |
2056 | { "cmovgS", { Gv, Ev } }, | |
252b5132 | 2057 | /* 50 */ |
75c135a8 | 2058 | { MOD_TABLE (MOD_0F51) }, |
1ceb70f8 L |
2059 | { PREFIX_TABLE (PREFIX_0F51) }, |
2060 | { PREFIX_TABLE (PREFIX_0F52) }, | |
2061 | { PREFIX_TABLE (PREFIX_0F53) }, | |
09a2c6cf L |
2062 | { "andpX", { XM, EXx } }, |
2063 | { "andnpX", { XM, EXx } }, | |
2064 | { "orpX", { XM, EXx } }, | |
2065 | { "xorpX", { XM, EXx } }, | |
252b5132 | 2066 | /* 58 */ |
1ceb70f8 L |
2067 | { PREFIX_TABLE (PREFIX_0F58) }, |
2068 | { PREFIX_TABLE (PREFIX_0F59) }, | |
2069 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
2070 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
2071 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
2072 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
2073 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
2074 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 2075 | /* 60 */ |
1ceb70f8 L |
2076 | { PREFIX_TABLE (PREFIX_0F60) }, |
2077 | { PREFIX_TABLE (PREFIX_0F61) }, | |
2078 | { PREFIX_TABLE (PREFIX_0F62) }, | |
ce518a5f L |
2079 | { "packsswb", { MX, EM } }, |
2080 | { "pcmpgtb", { MX, EM } }, | |
2081 | { "pcmpgtw", { MX, EM } }, | |
2082 | { "pcmpgtd", { MX, EM } }, | |
2083 | { "packuswb", { MX, EM } }, | |
252b5132 | 2084 | /* 68 */ |
ce518a5f L |
2085 | { "punpckhbw", { MX, EM } }, |
2086 | { "punpckhwd", { MX, EM } }, | |
2087 | { "punpckhdq", { MX, EM } }, | |
2088 | { "packssdw", { MX, EM } }, | |
1ceb70f8 L |
2089 | { PREFIX_TABLE (PREFIX_0F6C) }, |
2090 | { PREFIX_TABLE (PREFIX_0F6D) }, | |
231af070 | 2091 | { "movK", { MX, Edq } }, |
1ceb70f8 | 2092 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 2093 | /* 70 */ |
1ceb70f8 L |
2094 | { PREFIX_TABLE (PREFIX_0F70) }, |
2095 | { REG_TABLE (REG_0F71) }, | |
2096 | { REG_TABLE (REG_0F72) }, | |
2097 | { REG_TABLE (REG_0F73) }, | |
ce518a5f L |
2098 | { "pcmpeqb", { MX, EM } }, |
2099 | { "pcmpeqw", { MX, EM } }, | |
2100 | { "pcmpeqd", { MX, EM } }, | |
2101 | { "emms", { XX } }, | |
252b5132 | 2102 | /* 78 */ |
1ceb70f8 L |
2103 | { PREFIX_TABLE (PREFIX_0F78) }, |
2104 | { PREFIX_TABLE (PREFIX_0F79) }, | |
4e7d34a6 | 2105 | { THREE_BYTE_TABLE (THREE_BYTE_0F7A) }, |
592d1631 | 2106 | { Bad_Opcode }, |
1ceb70f8 L |
2107 | { PREFIX_TABLE (PREFIX_0F7C) }, |
2108 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
2109 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
2110 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 2111 | /* 80 */ |
ce518a5f L |
2112 | { "joH", { Jv, XX, cond_jump_flag } }, |
2113 | { "jnoH", { Jv, XX, cond_jump_flag } }, | |
2114 | { "jbH", { Jv, XX, cond_jump_flag } }, | |
2115 | { "jaeH", { Jv, XX, cond_jump_flag } }, | |
2116 | { "jeH", { Jv, XX, cond_jump_flag } }, | |
2117 | { "jneH", { Jv, XX, cond_jump_flag } }, | |
2118 | { "jbeH", { Jv, XX, cond_jump_flag } }, | |
2119 | { "jaH", { Jv, XX, cond_jump_flag } }, | |
252b5132 | 2120 | /* 88 */ |
ce518a5f L |
2121 | { "jsH", { Jv, XX, cond_jump_flag } }, |
2122 | { "jnsH", { Jv, XX, cond_jump_flag } }, | |
2123 | { "jpH", { Jv, XX, cond_jump_flag } }, | |
2124 | { "jnpH", { Jv, XX, cond_jump_flag } }, | |
2125 | { "jlH", { Jv, XX, cond_jump_flag } }, | |
2126 | { "jgeH", { Jv, XX, cond_jump_flag } }, | |
2127 | { "jleH", { Jv, XX, cond_jump_flag } }, | |
2128 | { "jgH", { Jv, XX, cond_jump_flag } }, | |
252b5132 | 2129 | /* 90 */ |
ce518a5f L |
2130 | { "seto", { Eb } }, |
2131 | { "setno", { Eb } }, | |
2132 | { "setb", { Eb } }, | |
2133 | { "setae", { Eb } }, | |
2134 | { "sete", { Eb } }, | |
2135 | { "setne", { Eb } }, | |
2136 | { "setbe", { Eb } }, | |
2137 | { "seta", { Eb } }, | |
252b5132 | 2138 | /* 98 */ |
ce518a5f L |
2139 | { "sets", { Eb } }, |
2140 | { "setns", { Eb } }, | |
2141 | { "setp", { Eb } }, | |
2142 | { "setnp", { Eb } }, | |
2143 | { "setl", { Eb } }, | |
2144 | { "setge", { Eb } }, | |
2145 | { "setle", { Eb } }, | |
2146 | { "setg", { Eb } }, | |
252b5132 | 2147 | /* a0 */ |
ce518a5f L |
2148 | { "pushT", { fs } }, |
2149 | { "popT", { fs } }, | |
2150 | { "cpuid", { XX } }, | |
2151 | { "btS", { Ev, Gv } }, | |
2152 | { "shldS", { Ev, Gv, Ib } }, | |
2153 | { "shldS", { Ev, Gv, CL } }, | |
1ceb70f8 L |
2154 | { REG_TABLE (REG_0FA6) }, |
2155 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 2156 | /* a8 */ |
ce518a5f L |
2157 | { "pushT", { gs } }, |
2158 | { "popT", { gs } }, | |
2159 | { "rsm", { XX } }, | |
42164a71 | 2160 | { "btsS", { Evh1, Gv } }, |
ce518a5f L |
2161 | { "shrdS", { Ev, Gv, Ib } }, |
2162 | { "shrdS", { Ev, Gv, CL } }, | |
1ceb70f8 | 2163 | { REG_TABLE (REG_0FAE) }, |
ce518a5f | 2164 | { "imulS", { Gv, Ev } }, |
252b5132 | 2165 | /* b0 */ |
42164a71 L |
2166 | { "cmpxchgB", { Ebh1, Gb } }, |
2167 | { "cmpxchgS", { Evh1, Gv } }, | |
1ceb70f8 | 2168 | { MOD_TABLE (MOD_0FB2) }, |
42164a71 | 2169 | { "btrS", { Evh1, Gv } }, |
1ceb70f8 L |
2170 | { MOD_TABLE (MOD_0FB4) }, |
2171 | { MOD_TABLE (MOD_0FB5) }, | |
7c52e0e8 L |
2172 | { "movz{bR|x}", { Gv, Eb } }, |
2173 | { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */ | |
252b5132 | 2174 | /* b8 */ |
1ceb70f8 | 2175 | { PREFIX_TABLE (PREFIX_0FB8) }, |
b414985b | 2176 | { "ud1", { XX } }, |
1ceb70f8 | 2177 | { REG_TABLE (REG_0FBA) }, |
42164a71 | 2178 | { "btcS", { Evh1, Gv } }, |
f12dc422 | 2179 | { PREFIX_TABLE (PREFIX_0FBC) }, |
1ceb70f8 | 2180 | { PREFIX_TABLE (PREFIX_0FBD) }, |
7c52e0e8 L |
2181 | { "movs{bR|x}", { Gv, Eb } }, |
2182 | { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */ | |
252b5132 | 2183 | /* c0 */ |
42164a71 L |
2184 | { "xaddB", { Ebh1, Gb } }, |
2185 | { "xaddS", { Evh1, Gv } }, | |
1ceb70f8 | 2186 | { PREFIX_TABLE (PREFIX_0FC2) }, |
4ee52178 | 2187 | { PREFIX_TABLE (PREFIX_0FC3) }, |
ce518a5f L |
2188 | { "pinsrw", { MX, Edqw, Ib } }, |
2189 | { "pextrw", { Gdq, MS, Ib } }, | |
09a2c6cf | 2190 | { "shufpX", { XM, EXx, Ib } }, |
1ceb70f8 | 2191 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 2192 | /* c8 */ |
ce518a5f L |
2193 | { "bswap", { RMeAX } }, |
2194 | { "bswap", { RMeCX } }, | |
2195 | { "bswap", { RMeDX } }, | |
2196 | { "bswap", { RMeBX } }, | |
2197 | { "bswap", { RMeSP } }, | |
2198 | { "bswap", { RMeBP } }, | |
2199 | { "bswap", { RMeSI } }, | |
2200 | { "bswap", { RMeDI } }, | |
252b5132 | 2201 | /* d0 */ |
1ceb70f8 | 2202 | { PREFIX_TABLE (PREFIX_0FD0) }, |
ce518a5f L |
2203 | { "psrlw", { MX, EM } }, |
2204 | { "psrld", { MX, EM } }, | |
2205 | { "psrlq", { MX, EM } }, | |
2206 | { "paddq", { MX, EM } }, | |
2207 | { "pmullw", { MX, EM } }, | |
1ceb70f8 | 2208 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 2209 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 2210 | /* d8 */ |
ce518a5f L |
2211 | { "psubusb", { MX, EM } }, |
2212 | { "psubusw", { MX, EM } }, | |
2213 | { "pminub", { MX, EM } }, | |
2214 | { "pand", { MX, EM } }, | |
2215 | { "paddusb", { MX, EM } }, | |
2216 | { "paddusw", { MX, EM } }, | |
2217 | { "pmaxub", { MX, EM } }, | |
2218 | { "pandn", { MX, EM } }, | |
252b5132 | 2219 | /* e0 */ |
ce518a5f L |
2220 | { "pavgb", { MX, EM } }, |
2221 | { "psraw", { MX, EM } }, | |
2222 | { "psrad", { MX, EM } }, | |
2223 | { "pavgw", { MX, EM } }, | |
2224 | { "pmulhuw", { MX, EM } }, | |
2225 | { "pmulhw", { MX, EM } }, | |
1ceb70f8 L |
2226 | { PREFIX_TABLE (PREFIX_0FE6) }, |
2227 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 2228 | /* e8 */ |
ce518a5f L |
2229 | { "psubsb", { MX, EM } }, |
2230 | { "psubsw", { MX, EM } }, | |
2231 | { "pminsw", { MX, EM } }, | |
2232 | { "por", { MX, EM } }, | |
2233 | { "paddsb", { MX, EM } }, | |
2234 | { "paddsw", { MX, EM } }, | |
2235 | { "pmaxsw", { MX, EM } }, | |
2236 | { "pxor", { MX, EM } }, | |
252b5132 | 2237 | /* f0 */ |
1ceb70f8 | 2238 | { PREFIX_TABLE (PREFIX_0FF0) }, |
ce518a5f L |
2239 | { "psllw", { MX, EM } }, |
2240 | { "pslld", { MX, EM } }, | |
2241 | { "psllq", { MX, EM } }, | |
2242 | { "pmuludq", { MX, EM } }, | |
2243 | { "pmaddwd", { MX, EM } }, | |
2244 | { "psadbw", { MX, EM } }, | |
1ceb70f8 | 2245 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 2246 | /* f8 */ |
ce518a5f L |
2247 | { "psubb", { MX, EM } }, |
2248 | { "psubw", { MX, EM } }, | |
2249 | { "psubd", { MX, EM } }, | |
2250 | { "psubq", { MX, EM } }, | |
2251 | { "paddb", { MX, EM } }, | |
2252 | { "paddw", { MX, EM } }, | |
2253 | { "paddd", { MX, EM } }, | |
592d1631 | 2254 | { Bad_Opcode }, |
252b5132 RH |
2255 | }; |
2256 | ||
2257 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
2258 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2259 | /* ------------------------------- */ | |
2260 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
2261 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
2262 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
2263 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
2264 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
2265 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
2266 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
2267 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
2268 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
2269 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
2270 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
2271 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
2272 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
2273 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
2274 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
2275 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
2276 | /* ------------------------------- */ | |
2277 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
2278 | }; |
2279 | ||
2280 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
2281 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2282 | /* ------------------------------- */ | |
252b5132 | 2283 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 2284 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 2285 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 2286 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 2287 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
2288 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
2289 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 2290 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
2291 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
2292 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 2293 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
050dfa73 | 2294 | /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ |
252b5132 | 2295 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 2296 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 2297 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
ca164297 | 2298 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ |
c608c12e AM |
2299 | /* ------------------------------- */ |
2300 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
2301 | }; | |
2302 | ||
252b5132 RH |
2303 | static char obuf[100]; |
2304 | static char *obufp; | |
ea397f5b | 2305 | static char *mnemonicendp; |
252b5132 RH |
2306 | static char scratchbuf[100]; |
2307 | static unsigned char *start_codep; | |
2308 | static unsigned char *insn_codep; | |
2309 | static unsigned char *codep; | |
f16cd0d5 L |
2310 | static int last_lock_prefix; |
2311 | static int last_repz_prefix; | |
2312 | static int last_repnz_prefix; | |
2313 | static int last_data_prefix; | |
2314 | static int last_addr_prefix; | |
2315 | static int last_rex_prefix; | |
2316 | static int last_seg_prefix; | |
2317 | #define MAX_CODE_LENGTH 15 | |
2318 | /* We can up to 14 prefixes since the maximum instruction length is | |
2319 | 15bytes. */ | |
2320 | static int all_prefixes[MAX_CODE_LENGTH - 1]; | |
252b5132 | 2321 | static disassemble_info *the_info; |
7967e09e L |
2322 | static struct |
2323 | { | |
2324 | int mod; | |
7967e09e | 2325 | int reg; |
484c222e | 2326 | int rm; |
7967e09e L |
2327 | } |
2328 | modrm; | |
4bba6815 | 2329 | static unsigned char need_modrm; |
dfc8cf43 L |
2330 | static struct |
2331 | { | |
2332 | int scale; | |
2333 | int index; | |
2334 | int base; | |
2335 | } | |
2336 | sib; | |
c0f3af97 L |
2337 | static struct |
2338 | { | |
2339 | int register_specifier; | |
2340 | int length; | |
2341 | int prefix; | |
2342 | int w; | |
2343 | } | |
2344 | vex; | |
2345 | static unsigned char need_vex; | |
2346 | static unsigned char need_vex_reg; | |
dae39acc | 2347 | static unsigned char vex_w_done; |
252b5132 | 2348 | |
ea397f5b L |
2349 | struct op |
2350 | { | |
2351 | const char *name; | |
2352 | unsigned int len; | |
2353 | }; | |
2354 | ||
4bba6815 AM |
2355 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
2356 | values are stale. Hitting this abort likely indicates that you | |
2357 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
2358 | #define MODRM_CHECK if (!need_modrm) abort () | |
2359 | ||
d708bcba AM |
2360 | static const char **names64; |
2361 | static const char **names32; | |
2362 | static const char **names16; | |
2363 | static const char **names8; | |
2364 | static const char **names8rex; | |
2365 | static const char **names_seg; | |
db51cc60 L |
2366 | static const char *index64; |
2367 | static const char *index32; | |
d708bcba AM |
2368 | static const char **index16; |
2369 | ||
2370 | static const char *intel_names64[] = { | |
2371 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
2372 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
2373 | }; | |
2374 | static const char *intel_names32[] = { | |
2375 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
2376 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
2377 | }; | |
2378 | static const char *intel_names16[] = { | |
2379 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
2380 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
2381 | }; | |
2382 | static const char *intel_names8[] = { | |
2383 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
2384 | }; | |
2385 | static const char *intel_names8rex[] = { | |
2386 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
2387 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
2388 | }; | |
2389 | static const char *intel_names_seg[] = { | |
2390 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
2391 | }; | |
db51cc60 L |
2392 | static const char *intel_index64 = "riz"; |
2393 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
2394 | static const char *intel_index16[] = { |
2395 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
2396 | }; | |
2397 | ||
2398 | static const char *att_names64[] = { | |
2399 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
2400 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
2401 | }; | |
d708bcba AM |
2402 | static const char *att_names32[] = { |
2403 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 2404 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 2405 | }; |
d708bcba AM |
2406 | static const char *att_names16[] = { |
2407 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 2408 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 2409 | }; |
d708bcba AM |
2410 | static const char *att_names8[] = { |
2411 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 2412 | }; |
d708bcba AM |
2413 | static const char *att_names8rex[] = { |
2414 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
2415 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
2416 | }; | |
d708bcba AM |
2417 | static const char *att_names_seg[] = { |
2418 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 2419 | }; |
db51cc60 L |
2420 | static const char *att_index64 = "%riz"; |
2421 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
2422 | static const char *att_index16[] = { |
2423 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
2424 | }; |
2425 | ||
b9733481 L |
2426 | static const char **names_mm; |
2427 | static const char *intel_names_mm[] = { | |
2428 | "mm0", "mm1", "mm2", "mm3", | |
2429 | "mm4", "mm5", "mm6", "mm7" | |
2430 | }; | |
2431 | static const char *att_names_mm[] = { | |
2432 | "%mm0", "%mm1", "%mm2", "%mm3", | |
2433 | "%mm4", "%mm5", "%mm6", "%mm7" | |
2434 | }; | |
2435 | ||
2436 | static const char **names_xmm; | |
2437 | static const char *intel_names_xmm[] = { | |
2438 | "xmm0", "xmm1", "xmm2", "xmm3", | |
2439 | "xmm4", "xmm5", "xmm6", "xmm7", | |
2440 | "xmm8", "xmm9", "xmm10", "xmm11", | |
2441 | "xmm12", "xmm13", "xmm14", "xmm15" | |
2442 | }; | |
2443 | static const char *att_names_xmm[] = { | |
2444 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", | |
2445 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", | |
2446 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", | |
2447 | "%xmm12", "%xmm13", "%xmm14", "%xmm15" | |
2448 | }; | |
2449 | ||
2450 | static const char **names_ymm; | |
2451 | static const char *intel_names_ymm[] = { | |
2452 | "ymm0", "ymm1", "ymm2", "ymm3", | |
2453 | "ymm4", "ymm5", "ymm6", "ymm7", | |
2454 | "ymm8", "ymm9", "ymm10", "ymm11", | |
2455 | "ymm12", "ymm13", "ymm14", "ymm15" | |
2456 | }; | |
2457 | static const char *att_names_ymm[] = { | |
2458 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", | |
2459 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", | |
2460 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", | |
2461 | "%ymm12", "%ymm13", "%ymm14", "%ymm15" | |
2462 | }; | |
2463 | ||
1ceb70f8 L |
2464 | static const struct dis386 reg_table[][8] = { |
2465 | /* REG_80 */ | |
252b5132 | 2466 | { |
42164a71 L |
2467 | { "addA", { Ebh1, Ib } }, |
2468 | { "orA", { Ebh1, Ib } }, | |
2469 | { "adcA", { Ebh1, Ib } }, | |
2470 | { "sbbA", { Ebh1, Ib } }, | |
2471 | { "andA", { Ebh1, Ib } }, | |
2472 | { "subA", { Ebh1, Ib } }, | |
2473 | { "xorA", { Ebh1, Ib } }, | |
ce518a5f | 2474 | { "cmpA", { Eb, Ib } }, |
252b5132 | 2475 | }, |
1ceb70f8 | 2476 | /* REG_81 */ |
252b5132 | 2477 | { |
42164a71 L |
2478 | { "addQ", { Evh1, Iv } }, |
2479 | { "orQ", { Evh1, Iv } }, | |
2480 | { "adcQ", { Evh1, Iv } }, | |
2481 | { "sbbQ", { Evh1, Iv } }, | |
2482 | { "andQ", { Evh1, Iv } }, | |
2483 | { "subQ", { Evh1, Iv } }, | |
2484 | { "xorQ", { Evh1, Iv } }, | |
ce518a5f | 2485 | { "cmpQ", { Ev, Iv } }, |
252b5132 | 2486 | }, |
1ceb70f8 | 2487 | /* REG_82 */ |
252b5132 | 2488 | { |
42164a71 L |
2489 | { "addQ", { Evh1, sIb } }, |
2490 | { "orQ", { Evh1, sIb } }, | |
2491 | { "adcQ", { Evh1, sIb } }, | |
2492 | { "sbbQ", { Evh1, sIb } }, | |
2493 | { "andQ", { Evh1, sIb } }, | |
2494 | { "subQ", { Evh1, sIb } }, | |
2495 | { "xorQ", { Evh1, sIb } }, | |
ce518a5f | 2496 | { "cmpQ", { Ev, sIb } }, |
252b5132 | 2497 | }, |
1ceb70f8 | 2498 | /* REG_8F */ |
4e7d34a6 L |
2499 | { |
2500 | { "popU", { stackEv } }, | |
c48244a5 | 2501 | { XOP_8F_TABLE (XOP_09) }, |
592d1631 L |
2502 | { Bad_Opcode }, |
2503 | { Bad_Opcode }, | |
2504 | { Bad_Opcode }, | |
f88c9eb0 | 2505 | { XOP_8F_TABLE (XOP_09) }, |
4e7d34a6 | 2506 | }, |
1ceb70f8 | 2507 | /* REG_C0 */ |
252b5132 | 2508 | { |
ce518a5f L |
2509 | { "rolA", { Eb, Ib } }, |
2510 | { "rorA", { Eb, Ib } }, | |
2511 | { "rclA", { Eb, Ib } }, | |
2512 | { "rcrA", { Eb, Ib } }, | |
2513 | { "shlA", { Eb, Ib } }, | |
2514 | { "shrA", { Eb, Ib } }, | |
592d1631 | 2515 | { Bad_Opcode }, |
ce518a5f | 2516 | { "sarA", { Eb, Ib } }, |
252b5132 | 2517 | }, |
1ceb70f8 | 2518 | /* REG_C1 */ |
252b5132 | 2519 | { |
ce518a5f L |
2520 | { "rolQ", { Ev, Ib } }, |
2521 | { "rorQ", { Ev, Ib } }, | |
2522 | { "rclQ", { Ev, Ib } }, | |
2523 | { "rcrQ", { Ev, Ib } }, | |
2524 | { "shlQ", { Ev, Ib } }, | |
2525 | { "shrQ", { Ev, Ib } }, | |
592d1631 | 2526 | { Bad_Opcode }, |
ce518a5f | 2527 | { "sarQ", { Ev, Ib } }, |
252b5132 | 2528 | }, |
1ceb70f8 | 2529 | /* REG_C6 */ |
4e7d34a6 | 2530 | { |
42164a71 L |
2531 | { "movA", { Ebh3, Ib } }, |
2532 | { Bad_Opcode }, | |
2533 | { Bad_Opcode }, | |
2534 | { Bad_Opcode }, | |
2535 | { Bad_Opcode }, | |
2536 | { Bad_Opcode }, | |
2537 | { Bad_Opcode }, | |
2538 | { MOD_TABLE (MOD_C6_REG_7) }, | |
4e7d34a6 | 2539 | }, |
1ceb70f8 | 2540 | /* REG_C7 */ |
4e7d34a6 | 2541 | { |
42164a71 L |
2542 | { "movQ", { Evh3, Iv } }, |
2543 | { Bad_Opcode }, | |
2544 | { Bad_Opcode }, | |
2545 | { Bad_Opcode }, | |
2546 | { Bad_Opcode }, | |
2547 | { Bad_Opcode }, | |
2548 | { Bad_Opcode }, | |
2549 | { MOD_TABLE (MOD_C7_REG_7) }, | |
4e7d34a6 | 2550 | }, |
1ceb70f8 | 2551 | /* REG_D0 */ |
252b5132 | 2552 | { |
ce518a5f L |
2553 | { "rolA", { Eb, I1 } }, |
2554 | { "rorA", { Eb, I1 } }, | |
2555 | { "rclA", { Eb, I1 } }, | |
2556 | { "rcrA", { Eb, I1 } }, | |
2557 | { "shlA", { Eb, I1 } }, | |
2558 | { "shrA", { Eb, I1 } }, | |
592d1631 | 2559 | { Bad_Opcode }, |
ce518a5f | 2560 | { "sarA", { Eb, I1 } }, |
252b5132 | 2561 | }, |
1ceb70f8 | 2562 | /* REG_D1 */ |
252b5132 | 2563 | { |
ce518a5f L |
2564 | { "rolQ", { Ev, I1 } }, |
2565 | { "rorQ", { Ev, I1 } }, | |
2566 | { "rclQ", { Ev, I1 } }, | |
2567 | { "rcrQ", { Ev, I1 } }, | |
2568 | { "shlQ", { Ev, I1 } }, | |
2569 | { "shrQ", { Ev, I1 } }, | |
592d1631 | 2570 | { Bad_Opcode }, |
ce518a5f | 2571 | { "sarQ", { Ev, I1 } }, |
252b5132 | 2572 | }, |
1ceb70f8 | 2573 | /* REG_D2 */ |
252b5132 | 2574 | { |
ce518a5f L |
2575 | { "rolA", { Eb, CL } }, |
2576 | { "rorA", { Eb, CL } }, | |
2577 | { "rclA", { Eb, CL } }, | |
2578 | { "rcrA", { Eb, CL } }, | |
2579 | { "shlA", { Eb, CL } }, | |
2580 | { "shrA", { Eb, CL } }, | |
592d1631 | 2581 | { Bad_Opcode }, |
ce518a5f | 2582 | { "sarA", { Eb, CL } }, |
252b5132 | 2583 | }, |
1ceb70f8 | 2584 | /* REG_D3 */ |
252b5132 | 2585 | { |
ce518a5f L |
2586 | { "rolQ", { Ev, CL } }, |
2587 | { "rorQ", { Ev, CL } }, | |
2588 | { "rclQ", { Ev, CL } }, | |
2589 | { "rcrQ", { Ev, CL } }, | |
2590 | { "shlQ", { Ev, CL } }, | |
2591 | { "shrQ", { Ev, CL } }, | |
592d1631 | 2592 | { Bad_Opcode }, |
ce518a5f | 2593 | { "sarQ", { Ev, CL } }, |
252b5132 | 2594 | }, |
1ceb70f8 | 2595 | /* REG_F6 */ |
252b5132 | 2596 | { |
ce518a5f | 2597 | { "testA", { Eb, Ib } }, |
592d1631 | 2598 | { Bad_Opcode }, |
42164a71 L |
2599 | { "notA", { Ebh1 } }, |
2600 | { "negA", { Ebh1 } }, | |
ce518a5f L |
2601 | { "mulA", { Eb } }, /* Don't print the implicit %al register, */ |
2602 | { "imulA", { Eb } }, /* to distinguish these opcodes from other */ | |
2603 | { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */ | |
2604 | { "idivA", { Eb } }, /* and idiv for consistency. */ | |
252b5132 | 2605 | }, |
1ceb70f8 | 2606 | /* REG_F7 */ |
252b5132 | 2607 | { |
ce518a5f | 2608 | { "testQ", { Ev, Iv } }, |
592d1631 | 2609 | { Bad_Opcode }, |
42164a71 L |
2610 | { "notQ", { Evh1 } }, |
2611 | { "negQ", { Evh1 } }, | |
ce518a5f L |
2612 | { "mulQ", { Ev } }, /* Don't print the implicit register. */ |
2613 | { "imulQ", { Ev } }, | |
2614 | { "divQ", { Ev } }, | |
2615 | { "idivQ", { Ev } }, | |
252b5132 | 2616 | }, |
1ceb70f8 | 2617 | /* REG_FE */ |
252b5132 | 2618 | { |
42164a71 L |
2619 | { "incA", { Ebh1 } }, |
2620 | { "decA", { Ebh1 } }, | |
252b5132 | 2621 | }, |
1ceb70f8 | 2622 | /* REG_FF */ |
252b5132 | 2623 | { |
42164a71 L |
2624 | { "incQ", { Evh1 } }, |
2625 | { "decQ", { Evh1 } }, | |
d9e3625e L |
2626 | { "call{T|}", { indirEv } }, |
2627 | { "Jcall{T|}", { indirEp } }, | |
2628 | { "jmp{T|}", { indirEv } }, | |
2629 | { "Jjmp{T|}", { indirEp } }, | |
ce518a5f | 2630 | { "pushU", { stackEv } }, |
592d1631 | 2631 | { Bad_Opcode }, |
252b5132 | 2632 | }, |
1ceb70f8 | 2633 | /* REG_0F00 */ |
252b5132 | 2634 | { |
ce518a5f L |
2635 | { "sldtD", { Sv } }, |
2636 | { "strD", { Sv } }, | |
2637 | { "lldt", { Ew } }, | |
2638 | { "ltr", { Ew } }, | |
2639 | { "verr", { Ew } }, | |
2640 | { "verw", { Ew } }, | |
592d1631 L |
2641 | { Bad_Opcode }, |
2642 | { Bad_Opcode }, | |
252b5132 | 2643 | }, |
1ceb70f8 | 2644 | /* REG_0F01 */ |
252b5132 | 2645 | { |
1ceb70f8 L |
2646 | { MOD_TABLE (MOD_0F01_REG_0) }, |
2647 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
2648 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
2649 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
ce518a5f | 2650 | { "smswD", { Sv } }, |
592d1631 | 2651 | { Bad_Opcode }, |
ce518a5f | 2652 | { "lmsw", { Ew } }, |
1ceb70f8 | 2653 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 2654 | }, |
b5b1fc4f | 2655 | /* REG_0F0D */ |
252b5132 | 2656 | { |
1ab03f4b L |
2657 | { "prefetch", { Mb } }, |
2658 | { "prefetchw", { Mb } }, | |
d7189fa5 RM |
2659 | { "prefetch", { Mb } }, |
2660 | { "prefetch", { Mb } }, | |
2661 | { "prefetch", { Mb } }, | |
2662 | { "prefetch", { Mb } }, | |
2663 | { "prefetch", { Mb } }, | |
2664 | { "prefetch", { Mb } }, | |
252b5132 | 2665 | }, |
1ceb70f8 | 2666 | /* REG_0F18 */ |
252b5132 | 2667 | { |
1ceb70f8 L |
2668 | { MOD_TABLE (MOD_0F18_REG_0) }, |
2669 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
2670 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
2671 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
d7189fa5 RM |
2672 | { MOD_TABLE (MOD_0F18_REG_4) }, |
2673 | { MOD_TABLE (MOD_0F18_REG_5) }, | |
2674 | { MOD_TABLE (MOD_0F18_REG_6) }, | |
2675 | { MOD_TABLE (MOD_0F18_REG_7) }, | |
252b5132 | 2676 | }, |
1ceb70f8 | 2677 | /* REG_0F71 */ |
a6bd098c | 2678 | { |
592d1631 L |
2679 | { Bad_Opcode }, |
2680 | { Bad_Opcode }, | |
1ceb70f8 | 2681 | { MOD_TABLE (MOD_0F71_REG_2) }, |
592d1631 | 2682 | { Bad_Opcode }, |
1ceb70f8 | 2683 | { MOD_TABLE (MOD_0F71_REG_4) }, |
592d1631 | 2684 | { Bad_Opcode }, |
1ceb70f8 | 2685 | { MOD_TABLE (MOD_0F71_REG_6) }, |
a6bd098c | 2686 | }, |
1ceb70f8 | 2687 | /* REG_0F72 */ |
a6bd098c | 2688 | { |
592d1631 L |
2689 | { Bad_Opcode }, |
2690 | { Bad_Opcode }, | |
1ceb70f8 | 2691 | { MOD_TABLE (MOD_0F72_REG_2) }, |
592d1631 | 2692 | { Bad_Opcode }, |
1ceb70f8 | 2693 | { MOD_TABLE (MOD_0F72_REG_4) }, |
592d1631 | 2694 | { Bad_Opcode }, |
1ceb70f8 | 2695 | { MOD_TABLE (MOD_0F72_REG_6) }, |
a6bd098c | 2696 | }, |
1ceb70f8 | 2697 | /* REG_0F73 */ |
252b5132 | 2698 | { |
592d1631 L |
2699 | { Bad_Opcode }, |
2700 | { Bad_Opcode }, | |
1ceb70f8 L |
2701 | { MOD_TABLE (MOD_0F73_REG_2) }, |
2702 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
592d1631 L |
2703 | { Bad_Opcode }, |
2704 | { Bad_Opcode }, | |
1ceb70f8 L |
2705 | { MOD_TABLE (MOD_0F73_REG_6) }, |
2706 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 2707 | }, |
1ceb70f8 | 2708 | /* REG_0FA6 */ |
252b5132 | 2709 | { |
4e7d34a6 L |
2710 | { "montmul", { { OP_0f07, 0 } } }, |
2711 | { "xsha1", { { OP_0f07, 0 } } }, | |
2712 | { "xsha256", { { OP_0f07, 0 } } }, | |
4e7d34a6 | 2713 | }, |
1ceb70f8 | 2714 | /* REG_0FA7 */ |
4e7d34a6 L |
2715 | { |
2716 | { "xstore-rng", { { OP_0f07, 0 } } }, | |
2717 | { "xcrypt-ecb", { { OP_0f07, 0 } } }, | |
2718 | { "xcrypt-cbc", { { OP_0f07, 0 } } }, | |
2719 | { "xcrypt-ctr", { { OP_0f07, 0 } } }, | |
2720 | { "xcrypt-cfb", { { OP_0f07, 0 } } }, | |
2721 | { "xcrypt-ofb", { { OP_0f07, 0 } } }, | |
4e7d34a6 | 2722 | }, |
1ceb70f8 | 2723 | /* REG_0FAE */ |
4e7d34a6 | 2724 | { |
1ceb70f8 L |
2725 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
2726 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
2727 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
2728 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 2729 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
2730 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
2731 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
2732 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 2733 | }, |
1ceb70f8 | 2734 | /* REG_0FBA */ |
252b5132 | 2735 | { |
592d1631 L |
2736 | { Bad_Opcode }, |
2737 | { Bad_Opcode }, | |
2738 | { Bad_Opcode }, | |
2739 | { Bad_Opcode }, | |
4e7d34a6 | 2740 | { "btQ", { Ev, Ib } }, |
42164a71 L |
2741 | { "btsQ", { Evh1, Ib } }, |
2742 | { "btrQ", { Evh1, Ib } }, | |
2743 | { "btcQ", { Evh1, Ib } }, | |
c608c12e | 2744 | }, |
1ceb70f8 | 2745 | /* REG_0FC7 */ |
c608c12e | 2746 | { |
592d1631 | 2747 | { Bad_Opcode }, |
4e7d34a6 | 2748 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } }, |
592d1631 L |
2749 | { Bad_Opcode }, |
2750 | { Bad_Opcode }, | |
2751 | { Bad_Opcode }, | |
2752 | { Bad_Opcode }, | |
1ceb70f8 L |
2753 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
2754 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 2755 | }, |
592a252b | 2756 | /* REG_VEX_0F71 */ |
c0f3af97 | 2757 | { |
592d1631 L |
2758 | { Bad_Opcode }, |
2759 | { Bad_Opcode }, | |
592a252b | 2760 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
592d1631 | 2761 | { Bad_Opcode }, |
592a252b | 2762 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
592d1631 | 2763 | { Bad_Opcode }, |
592a252b | 2764 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
c0f3af97 | 2765 | }, |
592a252b | 2766 | /* REG_VEX_0F72 */ |
c0f3af97 | 2767 | { |
592d1631 L |
2768 | { Bad_Opcode }, |
2769 | { Bad_Opcode }, | |
592a252b | 2770 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
592d1631 | 2771 | { Bad_Opcode }, |
592a252b | 2772 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
592d1631 | 2773 | { Bad_Opcode }, |
592a252b | 2774 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
c0f3af97 | 2775 | }, |
592a252b | 2776 | /* REG_VEX_0F73 */ |
c0f3af97 | 2777 | { |
592d1631 L |
2778 | { Bad_Opcode }, |
2779 | { Bad_Opcode }, | |
592a252b L |
2780 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
2781 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, | |
592d1631 L |
2782 | { Bad_Opcode }, |
2783 | { Bad_Opcode }, | |
592a252b L |
2784 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
2785 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, | |
c0f3af97 | 2786 | }, |
592a252b | 2787 | /* REG_VEX_0FAE */ |
c0f3af97 | 2788 | { |
592d1631 L |
2789 | { Bad_Opcode }, |
2790 | { Bad_Opcode }, | |
592a252b L |
2791 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
2792 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, | |
c0f3af97 | 2793 | }, |
f12dc422 L |
2794 | /* REG_VEX_0F38F3 */ |
2795 | { | |
2796 | { Bad_Opcode }, | |
2797 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, | |
2798 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, | |
2799 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, | |
2800 | }, | |
f88c9eb0 SP |
2801 | /* REG_XOP_LWPCB */ |
2802 | { | |
2803 | { "llwpcb", { { OP_LWPCB_E, 0 } } }, | |
2804 | { "slwpcb", { { OP_LWPCB_E, 0 } } }, | |
f88c9eb0 SP |
2805 | }, |
2806 | /* REG_XOP_LWP */ | |
2807 | { | |
ce7d077e SP |
2808 | { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } }, |
2809 | { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } }, | |
f88c9eb0 | 2810 | }, |
2a2a0f38 QN |
2811 | /* REG_XOP_TBM_01 */ |
2812 | { | |
2813 | { Bad_Opcode }, | |
2814 | { "blcfill", { { OP_LWP_E, 0 }, Ev } }, | |
2815 | { "blsfill", { { OP_LWP_E, 0 }, Ev } }, | |
2816 | { "blcs", { { OP_LWP_E, 0 }, Ev } }, | |
2817 | { "tzmsk", { { OP_LWP_E, 0 }, Ev } }, | |
2818 | { "blcic", { { OP_LWP_E, 0 }, Ev } }, | |
2819 | { "blsic", { { OP_LWP_E, 0 }, Ev } }, | |
2820 | { "t1mskc", { { OP_LWP_E, 0 }, Ev } }, | |
2821 | }, | |
2822 | /* REG_XOP_TBM_02 */ | |
2823 | { | |
2824 | { Bad_Opcode }, | |
2825 | { "blcmsk", { { OP_LWP_E, 0 }, Ev } }, | |
2826 | { Bad_Opcode }, | |
2827 | { Bad_Opcode }, | |
2828 | { Bad_Opcode }, | |
2829 | { Bad_Opcode }, | |
2830 | { "blci", { { OP_LWP_E, 0 }, Ev } }, | |
2831 | }, | |
4e7d34a6 L |
2832 | }; |
2833 | ||
1ceb70f8 L |
2834 | static const struct dis386 prefix_table[][4] = { |
2835 | /* PREFIX_90 */ | |
252b5132 | 2836 | { |
4e7d34a6 L |
2837 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, |
2838 | { "pause", { XX } }, | |
2839 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, | |
0f10071e | 2840 | }, |
4e7d34a6 | 2841 | |
1ceb70f8 | 2842 | /* PREFIX_0F10 */ |
cc0ec051 | 2843 | { |
4e7d34a6 L |
2844 | { "movups", { XM, EXx } }, |
2845 | { "movss", { XM, EXd } }, | |
2846 | { "movupd", { XM, EXx } }, | |
2847 | { "movsd", { XM, EXq } }, | |
30d1c836 | 2848 | }, |
4e7d34a6 | 2849 | |
1ceb70f8 | 2850 | /* PREFIX_0F11 */ |
30d1c836 | 2851 | { |
b6169b20 | 2852 | { "movups", { EXxS, XM } }, |
fa99fab2 | 2853 | { "movss", { EXdS, XM } }, |
b6169b20 | 2854 | { "movupd", { EXxS, XM } }, |
fa99fab2 | 2855 | { "movsd", { EXqS, XM } }, |
4e7d34a6 | 2856 | }, |
252b5132 | 2857 | |
1ceb70f8 | 2858 | /* PREFIX_0F12 */ |
c608c12e | 2859 | { |
1ceb70f8 | 2860 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
4e7d34a6 L |
2861 | { "movsldup", { XM, EXx } }, |
2862 | { "movlpd", { XM, EXq } }, | |
2863 | { "movddup", { XM, EXq } }, | |
c608c12e | 2864 | }, |
4e7d34a6 | 2865 | |
1ceb70f8 | 2866 | /* PREFIX_0F16 */ |
c608c12e | 2867 | { |
1ceb70f8 | 2868 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
4e7d34a6 L |
2869 | { "movshdup", { XM, EXx } }, |
2870 | { "movhpd", { XM, EXq } }, | |
c608c12e | 2871 | }, |
4e7d34a6 | 2872 | |
1ceb70f8 | 2873 | /* PREFIX_0F2A */ |
c608c12e | 2874 | { |
09335d05 | 2875 | { "cvtpi2ps", { XM, EMCq } }, |
98b528ac | 2876 | { "cvtsi2ss%LQ", { XM, Ev } }, |
09335d05 | 2877 | { "cvtpi2pd", { XM, EMCq } }, |
98b528ac | 2878 | { "cvtsi2sd%LQ", { XM, Ev } }, |
c608c12e | 2879 | }, |
4e7d34a6 | 2880 | |
1ceb70f8 | 2881 | /* PREFIX_0F2B */ |
c608c12e | 2882 | { |
75c135a8 L |
2883 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
2884 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
2885 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
2886 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 2887 | }, |
4e7d34a6 | 2888 | |
1ceb70f8 | 2889 | /* PREFIX_0F2C */ |
c608c12e | 2890 | { |
09335d05 L |
2891 | { "cvttps2pi", { MXC, EXq } }, |
2892 | { "cvttss2siY", { Gv, EXd } }, | |
09a2c6cf | 2893 | { "cvttpd2pi", { MXC, EXx } }, |
09335d05 | 2894 | { "cvttsd2siY", { Gv, EXq } }, |
c608c12e | 2895 | }, |
4e7d34a6 | 2896 | |
1ceb70f8 | 2897 | /* PREFIX_0F2D */ |
c608c12e | 2898 | { |
4e7d34a6 L |
2899 | { "cvtps2pi", { MXC, EXq } }, |
2900 | { "cvtss2siY", { Gv, EXd } }, | |
2901 | { "cvtpd2pi", { MXC, EXx } }, | |
2902 | { "cvtsd2siY", { Gv, EXq } }, | |
c608c12e | 2903 | }, |
4e7d34a6 | 2904 | |
1ceb70f8 | 2905 | /* PREFIX_0F2E */ |
c608c12e | 2906 | { |
7bb15c6f | 2907 | { "ucomiss",{ XM, EXd } }, |
592d1631 | 2908 | { Bad_Opcode }, |
7bb15c6f | 2909 | { "ucomisd",{ XM, EXq } }, |
c608c12e | 2910 | }, |
4e7d34a6 | 2911 | |
1ceb70f8 | 2912 | /* PREFIX_0F2F */ |
c608c12e | 2913 | { |
4e7d34a6 | 2914 | { "comiss", { XM, EXd } }, |
592d1631 | 2915 | { Bad_Opcode }, |
4e7d34a6 | 2916 | { "comisd", { XM, EXq } }, |
c608c12e | 2917 | }, |
4e7d34a6 | 2918 | |
1ceb70f8 | 2919 | /* PREFIX_0F51 */ |
c608c12e | 2920 | { |
4e7d34a6 L |
2921 | { "sqrtps", { XM, EXx } }, |
2922 | { "sqrtss", { XM, EXd } }, | |
2923 | { "sqrtpd", { XM, EXx } }, | |
2924 | { "sqrtsd", { XM, EXq } }, | |
c608c12e | 2925 | }, |
4e7d34a6 | 2926 | |
1ceb70f8 | 2927 | /* PREFIX_0F52 */ |
c608c12e | 2928 | { |
4e7d34a6 L |
2929 | { "rsqrtps",{ XM, EXx } }, |
2930 | { "rsqrtss",{ XM, EXd } }, | |
c608c12e | 2931 | }, |
4e7d34a6 | 2932 | |
1ceb70f8 | 2933 | /* PREFIX_0F53 */ |
c608c12e | 2934 | { |
4e7d34a6 L |
2935 | { "rcpps", { XM, EXx } }, |
2936 | { "rcpss", { XM, EXd } }, | |
c608c12e | 2937 | }, |
4e7d34a6 | 2938 | |
1ceb70f8 | 2939 | /* PREFIX_0F58 */ |
c608c12e | 2940 | { |
4e7d34a6 L |
2941 | { "addps", { XM, EXx } }, |
2942 | { "addss", { XM, EXd } }, | |
2943 | { "addpd", { XM, EXx } }, | |
2944 | { "addsd", { XM, EXq } }, | |
c608c12e | 2945 | }, |
4e7d34a6 | 2946 | |
1ceb70f8 | 2947 | /* PREFIX_0F59 */ |
c608c12e | 2948 | { |
4e7d34a6 L |
2949 | { "mulps", { XM, EXx } }, |
2950 | { "mulss", { XM, EXd } }, | |
2951 | { "mulpd", { XM, EXx } }, | |
2952 | { "mulsd", { XM, EXq } }, | |
041bd2e0 | 2953 | }, |
4e7d34a6 | 2954 | |
1ceb70f8 | 2955 | /* PREFIX_0F5A */ |
041bd2e0 | 2956 | { |
4e7d34a6 L |
2957 | { "cvtps2pd", { XM, EXq } }, |
2958 | { "cvtss2sd", { XM, EXd } }, | |
2959 | { "cvtpd2ps", { XM, EXx } }, | |
2960 | { "cvtsd2ss", { XM, EXq } }, | |
041bd2e0 | 2961 | }, |
4e7d34a6 | 2962 | |
1ceb70f8 | 2963 | /* PREFIX_0F5B */ |
041bd2e0 | 2964 | { |
09a2c6cf L |
2965 | { "cvtdq2ps", { XM, EXx } }, |
2966 | { "cvttps2dq", { XM, EXx } }, | |
2967 | { "cvtps2dq", { XM, EXx } }, | |
041bd2e0 | 2968 | }, |
4e7d34a6 | 2969 | |
1ceb70f8 | 2970 | /* PREFIX_0F5C */ |
041bd2e0 | 2971 | { |
4e7d34a6 L |
2972 | { "subps", { XM, EXx } }, |
2973 | { "subss", { XM, EXd } }, | |
2974 | { "subpd", { XM, EXx } }, | |
2975 | { "subsd", { XM, EXq } }, | |
041bd2e0 | 2976 | }, |
4e7d34a6 | 2977 | |
1ceb70f8 | 2978 | /* PREFIX_0F5D */ |
041bd2e0 | 2979 | { |
4e7d34a6 L |
2980 | { "minps", { XM, EXx } }, |
2981 | { "minss", { XM, EXd } }, | |
2982 | { "minpd", { XM, EXx } }, | |
2983 | { "minsd", { XM, EXq } }, | |
041bd2e0 | 2984 | }, |
4e7d34a6 | 2985 | |
1ceb70f8 | 2986 | /* PREFIX_0F5E */ |
041bd2e0 | 2987 | { |
4e7d34a6 L |
2988 | { "divps", { XM, EXx } }, |
2989 | { "divss", { XM, EXd } }, | |
2990 | { "divpd", { XM, EXx } }, | |
2991 | { "divsd", { XM, EXq } }, | |
041bd2e0 | 2992 | }, |
4e7d34a6 | 2993 | |
1ceb70f8 | 2994 | /* PREFIX_0F5F */ |
041bd2e0 | 2995 | { |
4e7d34a6 L |
2996 | { "maxps", { XM, EXx } }, |
2997 | { "maxss", { XM, EXd } }, | |
2998 | { "maxpd", { XM, EXx } }, | |
2999 | { "maxsd", { XM, EXq } }, | |
041bd2e0 | 3000 | }, |
4e7d34a6 | 3001 | |
1ceb70f8 | 3002 | /* PREFIX_0F60 */ |
041bd2e0 | 3003 | { |
4e7d34a6 | 3004 | { "punpcklbw",{ MX, EMd } }, |
592d1631 | 3005 | { Bad_Opcode }, |
4e7d34a6 | 3006 | { "punpcklbw",{ MX, EMx } }, |
041bd2e0 | 3007 | }, |
4e7d34a6 | 3008 | |
1ceb70f8 | 3009 | /* PREFIX_0F61 */ |
041bd2e0 | 3010 | { |
4e7d34a6 | 3011 | { "punpcklwd",{ MX, EMd } }, |
592d1631 | 3012 | { Bad_Opcode }, |
4e7d34a6 | 3013 | { "punpcklwd",{ MX, EMx } }, |
041bd2e0 | 3014 | }, |
4e7d34a6 | 3015 | |
1ceb70f8 | 3016 | /* PREFIX_0F62 */ |
041bd2e0 | 3017 | { |
4e7d34a6 | 3018 | { "punpckldq",{ MX, EMd } }, |
592d1631 | 3019 | { Bad_Opcode }, |
4e7d34a6 | 3020 | { "punpckldq",{ MX, EMx } }, |
041bd2e0 | 3021 | }, |
4e7d34a6 | 3022 | |
1ceb70f8 | 3023 | /* PREFIX_0F6C */ |
041bd2e0 | 3024 | { |
592d1631 L |
3025 | { Bad_Opcode }, |
3026 | { Bad_Opcode }, | |
4e7d34a6 | 3027 | { "punpcklqdq", { XM, EXx } }, |
0f17484f | 3028 | }, |
4e7d34a6 | 3029 | |
1ceb70f8 | 3030 | /* PREFIX_0F6D */ |
0f17484f | 3031 | { |
592d1631 L |
3032 | { Bad_Opcode }, |
3033 | { Bad_Opcode }, | |
4e7d34a6 | 3034 | { "punpckhqdq", { XM, EXx } }, |
041bd2e0 | 3035 | }, |
4e7d34a6 | 3036 | |
1ceb70f8 | 3037 | /* PREFIX_0F6F */ |
ca164297 | 3038 | { |
4e7d34a6 L |
3039 | { "movq", { MX, EM } }, |
3040 | { "movdqu", { XM, EXx } }, | |
3041 | { "movdqa", { XM, EXx } }, | |
ca164297 | 3042 | }, |
4e7d34a6 | 3043 | |
1ceb70f8 | 3044 | /* PREFIX_0F70 */ |
4e7d34a6 L |
3045 | { |
3046 | { "pshufw", { MX, EM, Ib } }, | |
3047 | { "pshufhw",{ XM, EXx, Ib } }, | |
3048 | { "pshufd", { XM, EXx, Ib } }, | |
3049 | { "pshuflw",{ XM, EXx, Ib } }, | |
3050 | }, | |
3051 | ||
92fddf8e L |
3052 | /* PREFIX_0F73_REG_3 */ |
3053 | { | |
592d1631 L |
3054 | { Bad_Opcode }, |
3055 | { Bad_Opcode }, | |
92fddf8e | 3056 | { "psrldq", { XS, Ib } }, |
92fddf8e L |
3057 | }, |
3058 | ||
3059 | /* PREFIX_0F73_REG_7 */ | |
3060 | { | |
592d1631 L |
3061 | { Bad_Opcode }, |
3062 | { Bad_Opcode }, | |
92fddf8e | 3063 | { "pslldq", { XS, Ib } }, |
92fddf8e L |
3064 | }, |
3065 | ||
1ceb70f8 | 3066 | /* PREFIX_0F78 */ |
4e7d34a6 L |
3067 | { |
3068 | {"vmread", { Em, Gm } }, | |
592d1631 | 3069 | { Bad_Opcode }, |
4e7d34a6 L |
3070 | {"extrq", { XS, Ib, Ib } }, |
3071 | {"insertq", { XM, XS, Ib, Ib } }, | |
3072 | }, | |
3073 | ||
1ceb70f8 | 3074 | /* PREFIX_0F79 */ |
4e7d34a6 L |
3075 | { |
3076 | {"vmwrite", { Gm, Em } }, | |
592d1631 | 3077 | { Bad_Opcode }, |
4e7d34a6 L |
3078 | {"extrq", { XM, XS } }, |
3079 | {"insertq", { XM, XS } }, | |
3080 | }, | |
3081 | ||
1ceb70f8 | 3082 | /* PREFIX_0F7C */ |
ca164297 | 3083 | { |
592d1631 L |
3084 | { Bad_Opcode }, |
3085 | { Bad_Opcode }, | |
09a2c6cf L |
3086 | { "haddpd", { XM, EXx } }, |
3087 | { "haddps", { XM, EXx } }, | |
ca164297 | 3088 | }, |
4e7d34a6 | 3089 | |
1ceb70f8 | 3090 | /* PREFIX_0F7D */ |
ca164297 | 3091 | { |
592d1631 L |
3092 | { Bad_Opcode }, |
3093 | { Bad_Opcode }, | |
09a2c6cf L |
3094 | { "hsubpd", { XM, EXx } }, |
3095 | { "hsubps", { XM, EXx } }, | |
ca164297 | 3096 | }, |
4e7d34a6 | 3097 | |
1ceb70f8 | 3098 | /* PREFIX_0F7E */ |
ca164297 | 3099 | { |
4e7d34a6 L |
3100 | { "movK", { Edq, MX } }, |
3101 | { "movq", { XM, EXq } }, | |
3102 | { "movK", { Edq, XM } }, | |
ca164297 | 3103 | }, |
4e7d34a6 | 3104 | |
1ceb70f8 | 3105 | /* PREFIX_0F7F */ |
ca164297 | 3106 | { |
b6169b20 L |
3107 | { "movq", { EMS, MX } }, |
3108 | { "movdqu", { EXxS, XM } }, | |
3109 | { "movdqa", { EXxS, XM } }, | |
ca164297 | 3110 | }, |
4e7d34a6 | 3111 | |
c7b8aa3a L |
3112 | /* PREFIX_0FAE_REG_0 */ |
3113 | { | |
3114 | { Bad_Opcode }, | |
3115 | { "rdfsbase", { Ev } }, | |
3116 | }, | |
3117 | ||
3118 | /* PREFIX_0FAE_REG_1 */ | |
3119 | { | |
3120 | { Bad_Opcode }, | |
3121 | { "rdgsbase", { Ev } }, | |
3122 | }, | |
3123 | ||
3124 | /* PREFIX_0FAE_REG_2 */ | |
3125 | { | |
3126 | { Bad_Opcode }, | |
3127 | { "wrfsbase", { Ev } }, | |
3128 | }, | |
3129 | ||
3130 | /* PREFIX_0FAE_REG_3 */ | |
3131 | { | |
3132 | { Bad_Opcode }, | |
3133 | { "wrgsbase", { Ev } }, | |
3134 | }, | |
3135 | ||
1ceb70f8 | 3136 | /* PREFIX_0FB8 */ |
ca164297 | 3137 | { |
592d1631 | 3138 | { Bad_Opcode }, |
4e7d34a6 | 3139 | { "popcntS", { Gv, Ev } }, |
ca164297 | 3140 | }, |
4e7d34a6 | 3141 | |
f12dc422 L |
3142 | /* PREFIX_0FBC */ |
3143 | { | |
3144 | { "bsfS", { Gv, Ev } }, | |
3145 | { "tzcntS", { Gv, Ev } }, | |
3146 | { "bsfS", { Gv, Ev } }, | |
3147 | }, | |
3148 | ||
1ceb70f8 | 3149 | /* PREFIX_0FBD */ |
050dfa73 | 3150 | { |
4e7d34a6 L |
3151 | { "bsrS", { Gv, Ev } }, |
3152 | { "lzcntS", { Gv, Ev } }, | |
3153 | { "bsrS", { Gv, Ev } }, | |
050dfa73 MM |
3154 | }, |
3155 | ||
1ceb70f8 | 3156 | /* PREFIX_0FC2 */ |
050dfa73 | 3157 | { |
ad19981d L |
3158 | { "cmpps", { XM, EXx, CMP } }, |
3159 | { "cmpss", { XM, EXd, CMP } }, | |
3160 | { "cmppd", { XM, EXx, CMP } }, | |
3161 | { "cmpsd", { XM, EXq, CMP } }, | |
050dfa73 | 3162 | }, |
246c51aa | 3163 | |
4ee52178 L |
3164 | /* PREFIX_0FC3 */ |
3165 | { | |
3166 | { "movntiS", { Ma, Gv } }, | |
4ee52178 L |
3167 | }, |
3168 | ||
92fddf8e L |
3169 | /* PREFIX_0FC7_REG_6 */ |
3170 | { | |
3171 | { "vmptrld",{ Mq } }, | |
3172 | { "vmxon", { Mq } }, | |
3173 | { "vmclear",{ Mq } }, | |
92fddf8e L |
3174 | }, |
3175 | ||
1ceb70f8 | 3176 | /* PREFIX_0FD0 */ |
050dfa73 | 3177 | { |
592d1631 L |
3178 | { Bad_Opcode }, |
3179 | { Bad_Opcode }, | |
4e7d34a6 L |
3180 | { "addsubpd", { XM, EXx } }, |
3181 | { "addsubps", { XM, EXx } }, | |
246c51aa | 3182 | }, |
050dfa73 | 3183 | |
1ceb70f8 | 3184 | /* PREFIX_0FD6 */ |
050dfa73 | 3185 | { |
592d1631 | 3186 | { Bad_Opcode }, |
4e7d34a6 | 3187 | { "movq2dq",{ XM, MS } }, |
b6169b20 | 3188 | { "movq", { EXqS, XM } }, |
4e7d34a6 | 3189 | { "movdq2q",{ MX, XS } }, |
050dfa73 MM |
3190 | }, |
3191 | ||
1ceb70f8 | 3192 | /* PREFIX_0FE6 */ |
7918206c | 3193 | { |
592d1631 | 3194 | { Bad_Opcode }, |
4e7d34a6 L |
3195 | { "cvtdq2pd", { XM, EXq } }, |
3196 | { "cvttpd2dq", { XM, EXx } }, | |
3197 | { "cvtpd2dq", { XM, EXx } }, | |
7918206c | 3198 | }, |
8b38ad71 | 3199 | |
1ceb70f8 | 3200 | /* PREFIX_0FE7 */ |
8b38ad71 | 3201 | { |
4ee52178 | 3202 | { "movntq", { Mq, MX } }, |
592d1631 | 3203 | { Bad_Opcode }, |
75c135a8 | 3204 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
4e7d34a6 L |
3205 | }, |
3206 | ||
1ceb70f8 | 3207 | /* PREFIX_0FF0 */ |
4e7d34a6 | 3208 | { |
592d1631 L |
3209 | { Bad_Opcode }, |
3210 | { Bad_Opcode }, | |
3211 | { Bad_Opcode }, | |
1ceb70f8 | 3212 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
3213 | }, |
3214 | ||
1ceb70f8 | 3215 | /* PREFIX_0FF7 */ |
4e7d34a6 L |
3216 | { |
3217 | { "maskmovq", { MX, MS } }, | |
592d1631 | 3218 | { Bad_Opcode }, |
4e7d34a6 | 3219 | { "maskmovdqu", { XM, XS } }, |
8b38ad71 | 3220 | }, |
42903f7f | 3221 | |
1ceb70f8 | 3222 | /* PREFIX_0F3810 */ |
42903f7f | 3223 | { |
592d1631 L |
3224 | { Bad_Opcode }, |
3225 | { Bad_Opcode }, | |
88a94849 | 3226 | { "pblendvb", { XM, EXx, XMM0 } }, |
42903f7f L |
3227 | }, |
3228 | ||
1ceb70f8 | 3229 | /* PREFIX_0F3814 */ |
42903f7f | 3230 | { |
592d1631 L |
3231 | { Bad_Opcode }, |
3232 | { Bad_Opcode }, | |
88a94849 | 3233 | { "blendvps", { XM, EXx, XMM0 } }, |
42903f7f L |
3234 | }, |
3235 | ||
1ceb70f8 | 3236 | /* PREFIX_0F3815 */ |
42903f7f | 3237 | { |
592d1631 L |
3238 | { Bad_Opcode }, |
3239 | { Bad_Opcode }, | |
09a2c6cf | 3240 | { "blendvpd", { XM, EXx, XMM0 } }, |
42903f7f L |
3241 | }, |
3242 | ||
1ceb70f8 | 3243 | /* PREFIX_0F3817 */ |
42903f7f | 3244 | { |
592d1631 L |
3245 | { Bad_Opcode }, |
3246 | { Bad_Opcode }, | |
09a2c6cf | 3247 | { "ptest", { XM, EXx } }, |
42903f7f L |
3248 | }, |
3249 | ||
1ceb70f8 | 3250 | /* PREFIX_0F3820 */ |
42903f7f | 3251 | { |
592d1631 L |
3252 | { Bad_Opcode }, |
3253 | { Bad_Opcode }, | |
8976381e | 3254 | { "pmovsxbw", { XM, EXq } }, |
42903f7f L |
3255 | }, |
3256 | ||
1ceb70f8 | 3257 | /* PREFIX_0F3821 */ |
42903f7f | 3258 | { |
592d1631 L |
3259 | { Bad_Opcode }, |
3260 | { Bad_Opcode }, | |
8976381e | 3261 | { "pmovsxbd", { XM, EXd } }, |
42903f7f L |
3262 | }, |
3263 | ||
1ceb70f8 | 3264 | /* PREFIX_0F3822 */ |
42903f7f | 3265 | { |
592d1631 L |
3266 | { Bad_Opcode }, |
3267 | { Bad_Opcode }, | |
8976381e | 3268 | { "pmovsxbq", { XM, EXw } }, |
42903f7f L |
3269 | }, |
3270 | ||
1ceb70f8 | 3271 | /* PREFIX_0F3823 */ |
42903f7f | 3272 | { |
592d1631 L |
3273 | { Bad_Opcode }, |
3274 | { Bad_Opcode }, | |
8976381e | 3275 | { "pmovsxwd", { XM, EXq } }, |
42903f7f L |
3276 | }, |
3277 | ||
1ceb70f8 | 3278 | /* PREFIX_0F3824 */ |
42903f7f | 3279 | { |
592d1631 L |
3280 | { Bad_Opcode }, |
3281 | { Bad_Opcode }, | |
8976381e | 3282 | { "pmovsxwq", { XM, EXd } }, |
42903f7f L |
3283 | }, |
3284 | ||
1ceb70f8 | 3285 | /* PREFIX_0F3825 */ |
42903f7f | 3286 | { |
592d1631 L |
3287 | { Bad_Opcode }, |
3288 | { Bad_Opcode }, | |
8976381e | 3289 | { "pmovsxdq", { XM, EXq } }, |
42903f7f L |
3290 | }, |
3291 | ||
1ceb70f8 | 3292 | /* PREFIX_0F3828 */ |
42903f7f | 3293 | { |
592d1631 L |
3294 | { Bad_Opcode }, |
3295 | { Bad_Opcode }, | |
09a2c6cf | 3296 | { "pmuldq", { XM, EXx } }, |
42903f7f L |
3297 | }, |
3298 | ||
1ceb70f8 | 3299 | /* PREFIX_0F3829 */ |
42903f7f | 3300 | { |
592d1631 L |
3301 | { Bad_Opcode }, |
3302 | { Bad_Opcode }, | |
09a2c6cf | 3303 | { "pcmpeqq", { XM, EXx } }, |
42903f7f L |
3304 | }, |
3305 | ||
1ceb70f8 | 3306 | /* PREFIX_0F382A */ |
42903f7f | 3307 | { |
592d1631 L |
3308 | { Bad_Opcode }, |
3309 | { Bad_Opcode }, | |
75c135a8 | 3310 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
42903f7f L |
3311 | }, |
3312 | ||
1ceb70f8 | 3313 | /* PREFIX_0F382B */ |
42903f7f | 3314 | { |
592d1631 L |
3315 | { Bad_Opcode }, |
3316 | { Bad_Opcode }, | |
09a2c6cf | 3317 | { "packusdw", { XM, EXx } }, |
42903f7f L |
3318 | }, |
3319 | ||
1ceb70f8 | 3320 | /* PREFIX_0F3830 */ |
42903f7f | 3321 | { |
592d1631 L |
3322 | { Bad_Opcode }, |
3323 | { Bad_Opcode }, | |
8976381e | 3324 | { "pmovzxbw", { XM, EXq } }, |
42903f7f L |
3325 | }, |
3326 | ||
1ceb70f8 | 3327 | /* PREFIX_0F3831 */ |
42903f7f | 3328 | { |
592d1631 L |
3329 | { Bad_Opcode }, |
3330 | { Bad_Opcode }, | |
8976381e | 3331 | { "pmovzxbd", { XM, EXd } }, |
42903f7f L |
3332 | }, |
3333 | ||
1ceb70f8 | 3334 | /* PREFIX_0F3832 */ |
42903f7f | 3335 | { |
592d1631 L |
3336 | { Bad_Opcode }, |
3337 | { Bad_Opcode }, | |
8976381e | 3338 | { "pmovzxbq", { XM, EXw } }, |
42903f7f L |
3339 | }, |
3340 | ||
1ceb70f8 | 3341 | /* PREFIX_0F3833 */ |
42903f7f | 3342 | { |
592d1631 L |
3343 | { Bad_Opcode }, |
3344 | { Bad_Opcode }, | |
8976381e | 3345 | { "pmovzxwd", { XM, EXq } }, |
42903f7f L |
3346 | }, |
3347 | ||
1ceb70f8 | 3348 | /* PREFIX_0F3834 */ |
42903f7f | 3349 | { |
592d1631 L |
3350 | { Bad_Opcode }, |
3351 | { Bad_Opcode }, | |
8976381e | 3352 | { "pmovzxwq", { XM, EXd } }, |
42903f7f L |
3353 | }, |
3354 | ||
1ceb70f8 | 3355 | /* PREFIX_0F3835 */ |
42903f7f | 3356 | { |
592d1631 L |
3357 | { Bad_Opcode }, |
3358 | { Bad_Opcode }, | |
8976381e | 3359 | { "pmovzxdq", { XM, EXq } }, |
42903f7f L |
3360 | }, |
3361 | ||
1ceb70f8 | 3362 | /* PREFIX_0F3837 */ |
4e7d34a6 | 3363 | { |
592d1631 L |
3364 | { Bad_Opcode }, |
3365 | { Bad_Opcode }, | |
4e7d34a6 | 3366 | { "pcmpgtq", { XM, EXx } }, |
4e7d34a6 L |
3367 | }, |
3368 | ||
1ceb70f8 | 3369 | /* PREFIX_0F3838 */ |
42903f7f | 3370 | { |
592d1631 L |
3371 | { Bad_Opcode }, |
3372 | { Bad_Opcode }, | |
09a2c6cf | 3373 | { "pminsb", { XM, EXx } }, |
42903f7f L |
3374 | }, |
3375 | ||
1ceb70f8 | 3376 | /* PREFIX_0F3839 */ |
42903f7f | 3377 | { |
592d1631 L |
3378 | { Bad_Opcode }, |
3379 | { Bad_Opcode }, | |
09a2c6cf | 3380 | { "pminsd", { XM, EXx } }, |
42903f7f L |
3381 | }, |
3382 | ||
1ceb70f8 | 3383 | /* PREFIX_0F383A */ |
42903f7f | 3384 | { |
592d1631 L |
3385 | { Bad_Opcode }, |
3386 | { Bad_Opcode }, | |
09a2c6cf | 3387 | { "pminuw", { XM, EXx } }, |
42903f7f L |
3388 | }, |
3389 | ||
1ceb70f8 | 3390 | /* PREFIX_0F383B */ |
42903f7f | 3391 | { |
592d1631 L |
3392 | { Bad_Opcode }, |
3393 | { Bad_Opcode }, | |
09a2c6cf | 3394 | { "pminud", { XM, EXx } }, |
42903f7f L |
3395 | }, |
3396 | ||
1ceb70f8 | 3397 | /* PREFIX_0F383C */ |
42903f7f | 3398 | { |
592d1631 L |
3399 | { Bad_Opcode }, |
3400 | { Bad_Opcode }, | |
09a2c6cf | 3401 | { "pmaxsb", { XM, EXx } }, |
42903f7f L |
3402 | }, |
3403 | ||
1ceb70f8 | 3404 | /* PREFIX_0F383D */ |
42903f7f | 3405 | { |
592d1631 L |
3406 | { Bad_Opcode }, |
3407 | { Bad_Opcode }, | |
09a2c6cf | 3408 | { "pmaxsd", { XM, EXx } }, |
42903f7f L |
3409 | }, |
3410 | ||
1ceb70f8 | 3411 | /* PREFIX_0F383E */ |
42903f7f | 3412 | { |
592d1631 L |
3413 | { Bad_Opcode }, |
3414 | { Bad_Opcode }, | |
09a2c6cf | 3415 | { "pmaxuw", { XM, EXx } }, |
42903f7f L |
3416 | }, |
3417 | ||
1ceb70f8 | 3418 | /* PREFIX_0F383F */ |
42903f7f | 3419 | { |
592d1631 L |
3420 | { Bad_Opcode }, |
3421 | { Bad_Opcode }, | |
09a2c6cf | 3422 | { "pmaxud", { XM, EXx } }, |
42903f7f L |
3423 | }, |
3424 | ||
1ceb70f8 | 3425 | /* PREFIX_0F3840 */ |
42903f7f | 3426 | { |
592d1631 L |
3427 | { Bad_Opcode }, |
3428 | { Bad_Opcode }, | |
09a2c6cf | 3429 | { "pmulld", { XM, EXx } }, |
42903f7f L |
3430 | }, |
3431 | ||
1ceb70f8 | 3432 | /* PREFIX_0F3841 */ |
42903f7f | 3433 | { |
592d1631 L |
3434 | { Bad_Opcode }, |
3435 | { Bad_Opcode }, | |
09a2c6cf | 3436 | { "phminposuw", { XM, EXx } }, |
42903f7f L |
3437 | }, |
3438 | ||
f1f8f695 L |
3439 | /* PREFIX_0F3880 */ |
3440 | { | |
592d1631 L |
3441 | { Bad_Opcode }, |
3442 | { Bad_Opcode }, | |
f1f8f695 | 3443 | { "invept", { Gm, Mo } }, |
f1f8f695 L |
3444 | }, |
3445 | ||
3446 | /* PREFIX_0F3881 */ | |
3447 | { | |
592d1631 L |
3448 | { Bad_Opcode }, |
3449 | { Bad_Opcode }, | |
f1f8f695 | 3450 | { "invvpid", { Gm, Mo } }, |
f1f8f695 L |
3451 | }, |
3452 | ||
6c30d220 L |
3453 | /* PREFIX_0F3882 */ |
3454 | { | |
3455 | { Bad_Opcode }, | |
3456 | { Bad_Opcode }, | |
3457 | { "invpcid", { Gm, M } }, | |
3458 | }, | |
3459 | ||
c0f3af97 L |
3460 | /* PREFIX_0F38DB */ |
3461 | { | |
592d1631 L |
3462 | { Bad_Opcode }, |
3463 | { Bad_Opcode }, | |
c0f3af97 | 3464 | { "aesimc", { XM, EXx } }, |
c0f3af97 L |
3465 | }, |
3466 | ||
3467 | /* PREFIX_0F38DC */ | |
3468 | { | |
592d1631 L |
3469 | { Bad_Opcode }, |
3470 | { Bad_Opcode }, | |
c0f3af97 | 3471 | { "aesenc", { XM, EXx } }, |
c0f3af97 L |
3472 | }, |
3473 | ||
3474 | /* PREFIX_0F38DD */ | |
3475 | { | |
592d1631 L |
3476 | { Bad_Opcode }, |
3477 | { Bad_Opcode }, | |
c0f3af97 | 3478 | { "aesenclast", { XM, EXx } }, |
c0f3af97 L |
3479 | }, |
3480 | ||
3481 | /* PREFIX_0F38DE */ | |
3482 | { | |
592d1631 L |
3483 | { Bad_Opcode }, |
3484 | { Bad_Opcode }, | |
c0f3af97 | 3485 | { "aesdec", { XM, EXx } }, |
c0f3af97 L |
3486 | }, |
3487 | ||
3488 | /* PREFIX_0F38DF */ | |
3489 | { | |
592d1631 L |
3490 | { Bad_Opcode }, |
3491 | { Bad_Opcode }, | |
c0f3af97 | 3492 | { "aesdeclast", { XM, EXx } }, |
c0f3af97 L |
3493 | }, |
3494 | ||
1ceb70f8 | 3495 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 3496 | { |
f1f8f695 | 3497 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } }, |
592d1631 | 3498 | { Bad_Opcode }, |
f1f8f695 | 3499 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } }, |
7bb15c6f | 3500 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } } }, |
4e7d34a6 L |
3501 | }, |
3502 | ||
1ceb70f8 | 3503 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 3504 | { |
f1f8f695 | 3505 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } }, |
592d1631 | 3506 | { Bad_Opcode }, |
f1f8f695 | 3507 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } }, |
7bb15c6f | 3508 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } } }, |
4e7d34a6 L |
3509 | }, |
3510 | ||
e2e1fcde L |
3511 | /* PREFIX_0F38F6 */ |
3512 | { | |
3513 | { Bad_Opcode }, | |
3514 | { "adoxS", { Gdq, Edq} }, | |
3515 | { "adcxS", { Gdq, Edq} }, | |
3516 | { Bad_Opcode }, | |
3517 | }, | |
3518 | ||
1ceb70f8 | 3519 | /* PREFIX_0F3A08 */ |
42903f7f | 3520 | { |
592d1631 L |
3521 | { Bad_Opcode }, |
3522 | { Bad_Opcode }, | |
09a2c6cf | 3523 | { "roundps", { XM, EXx, Ib } }, |
42903f7f L |
3524 | }, |
3525 | ||
1ceb70f8 | 3526 | /* PREFIX_0F3A09 */ |
42903f7f | 3527 | { |
592d1631 L |
3528 | { Bad_Opcode }, |
3529 | { Bad_Opcode }, | |
09a2c6cf | 3530 | { "roundpd", { XM, EXx, Ib } }, |
42903f7f L |
3531 | }, |
3532 | ||
1ceb70f8 | 3533 | /* PREFIX_0F3A0A */ |
42903f7f | 3534 | { |
592d1631 L |
3535 | { Bad_Opcode }, |
3536 | { Bad_Opcode }, | |
09335d05 | 3537 | { "roundss", { XM, EXd, Ib } }, |
42903f7f L |
3538 | }, |
3539 | ||
1ceb70f8 | 3540 | /* PREFIX_0F3A0B */ |
42903f7f | 3541 | { |
592d1631 L |
3542 | { Bad_Opcode }, |
3543 | { Bad_Opcode }, | |
09335d05 | 3544 | { "roundsd", { XM, EXq, Ib } }, |
42903f7f L |
3545 | }, |
3546 | ||
1ceb70f8 | 3547 | /* PREFIX_0F3A0C */ |
42903f7f | 3548 | { |
592d1631 L |
3549 | { Bad_Opcode }, |
3550 | { Bad_Opcode }, | |
09a2c6cf | 3551 | { "blendps", { XM, EXx, Ib } }, |
42903f7f L |
3552 | }, |
3553 | ||
1ceb70f8 | 3554 | /* PREFIX_0F3A0D */ |
42903f7f | 3555 | { |
592d1631 L |
3556 | { Bad_Opcode }, |
3557 | { Bad_Opcode }, | |
09a2c6cf | 3558 | { "blendpd", { XM, EXx, Ib } }, |
42903f7f L |
3559 | }, |
3560 | ||
1ceb70f8 | 3561 | /* PREFIX_0F3A0E */ |
42903f7f | 3562 | { |
592d1631 L |
3563 | { Bad_Opcode }, |
3564 | { Bad_Opcode }, | |
09a2c6cf | 3565 | { "pblendw", { XM, EXx, Ib } }, |
42903f7f L |
3566 | }, |
3567 | ||
1ceb70f8 | 3568 | /* PREFIX_0F3A14 */ |
42903f7f | 3569 | { |
592d1631 L |
3570 | { Bad_Opcode }, |
3571 | { Bad_Opcode }, | |
42903f7f | 3572 | { "pextrb", { Edqb, XM, Ib } }, |
42903f7f L |
3573 | }, |
3574 | ||
1ceb70f8 | 3575 | /* PREFIX_0F3A15 */ |
42903f7f | 3576 | { |
592d1631 L |
3577 | { Bad_Opcode }, |
3578 | { Bad_Opcode }, | |
42903f7f | 3579 | { "pextrw", { Edqw, XM, Ib } }, |
42903f7f L |
3580 | }, |
3581 | ||
1ceb70f8 | 3582 | /* PREFIX_0F3A16 */ |
42903f7f | 3583 | { |
592d1631 L |
3584 | { Bad_Opcode }, |
3585 | { Bad_Opcode }, | |
42903f7f | 3586 | { "pextrK", { Edq, XM, Ib } }, |
42903f7f L |
3587 | }, |
3588 | ||
1ceb70f8 | 3589 | /* PREFIX_0F3A17 */ |
42903f7f | 3590 | { |
592d1631 L |
3591 | { Bad_Opcode }, |
3592 | { Bad_Opcode }, | |
42903f7f | 3593 | { "extractps", { Edqd, XM, Ib } }, |
42903f7f L |
3594 | }, |
3595 | ||
1ceb70f8 | 3596 | /* PREFIX_0F3A20 */ |
42903f7f | 3597 | { |
592d1631 L |
3598 | { Bad_Opcode }, |
3599 | { Bad_Opcode }, | |
42903f7f | 3600 | { "pinsrb", { XM, Edqb, Ib } }, |
42903f7f L |
3601 | }, |
3602 | ||
1ceb70f8 | 3603 | /* PREFIX_0F3A21 */ |
42903f7f | 3604 | { |
592d1631 L |
3605 | { Bad_Opcode }, |
3606 | { Bad_Opcode }, | |
8976381e | 3607 | { "insertps", { XM, EXd, Ib } }, |
42903f7f L |
3608 | }, |
3609 | ||
1ceb70f8 | 3610 | /* PREFIX_0F3A22 */ |
42903f7f | 3611 | { |
592d1631 L |
3612 | { Bad_Opcode }, |
3613 | { Bad_Opcode }, | |
42903f7f | 3614 | { "pinsrK", { XM, Edq, Ib } }, |
42903f7f L |
3615 | }, |
3616 | ||
1ceb70f8 | 3617 | /* PREFIX_0F3A40 */ |
42903f7f | 3618 | { |
592d1631 L |
3619 | { Bad_Opcode }, |
3620 | { Bad_Opcode }, | |
09a2c6cf | 3621 | { "dpps", { XM, EXx, Ib } }, |
42903f7f L |
3622 | }, |
3623 | ||
1ceb70f8 | 3624 | /* PREFIX_0F3A41 */ |
42903f7f | 3625 | { |
592d1631 L |
3626 | { Bad_Opcode }, |
3627 | { Bad_Opcode }, | |
09a2c6cf | 3628 | { "dppd", { XM, EXx, Ib } }, |
42903f7f L |
3629 | }, |
3630 | ||
1ceb70f8 | 3631 | /* PREFIX_0F3A42 */ |
42903f7f | 3632 | { |
592d1631 L |
3633 | { Bad_Opcode }, |
3634 | { Bad_Opcode }, | |
09a2c6cf | 3635 | { "mpsadbw", { XM, EXx, Ib } }, |
42903f7f | 3636 | }, |
381d071f | 3637 | |
c0f3af97 L |
3638 | /* PREFIX_0F3A44 */ |
3639 | { | |
592d1631 L |
3640 | { Bad_Opcode }, |
3641 | { Bad_Opcode }, | |
c0f3af97 | 3642 | { "pclmulqdq", { XM, EXx, PCLMUL } }, |
c0f3af97 L |
3643 | }, |
3644 | ||
1ceb70f8 | 3645 | /* PREFIX_0F3A60 */ |
381d071f | 3646 | { |
592d1631 L |
3647 | { Bad_Opcode }, |
3648 | { Bad_Opcode }, | |
4e7d34a6 | 3649 | { "pcmpestrm", { XM, EXx, Ib } }, |
381d071f L |
3650 | }, |
3651 | ||
1ceb70f8 | 3652 | /* PREFIX_0F3A61 */ |
381d071f | 3653 | { |
592d1631 L |
3654 | { Bad_Opcode }, |
3655 | { Bad_Opcode }, | |
4e7d34a6 | 3656 | { "pcmpestri", { XM, EXx, Ib } }, |
381d071f L |
3657 | }, |
3658 | ||
1ceb70f8 | 3659 | /* PREFIX_0F3A62 */ |
381d071f | 3660 | { |
592d1631 L |
3661 | { Bad_Opcode }, |
3662 | { Bad_Opcode }, | |
4e7d34a6 | 3663 | { "pcmpistrm", { XM, EXx, Ib } }, |
381d071f L |
3664 | }, |
3665 | ||
1ceb70f8 | 3666 | /* PREFIX_0F3A63 */ |
381d071f | 3667 | { |
592d1631 L |
3668 | { Bad_Opcode }, |
3669 | { Bad_Opcode }, | |
4e7d34a6 | 3670 | { "pcmpistri", { XM, EXx, Ib } }, |
381d071f | 3671 | }, |
09a2c6cf | 3672 | |
c0f3af97 | 3673 | /* PREFIX_0F3ADF */ |
09a2c6cf | 3674 | { |
592d1631 L |
3675 | { Bad_Opcode }, |
3676 | { Bad_Opcode }, | |
c0f3af97 | 3677 | { "aeskeygenassist", { XM, EXx, Ib } }, |
09a2c6cf L |
3678 | }, |
3679 | ||
592a252b | 3680 | /* PREFIX_VEX_0F10 */ |
09a2c6cf | 3681 | { |
592a252b L |
3682 | { VEX_W_TABLE (VEX_W_0F10_P_0) }, |
3683 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) }, | |
3684 | { VEX_W_TABLE (VEX_W_0F10_P_2) }, | |
3685 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) }, | |
09a2c6cf L |
3686 | }, |
3687 | ||
592a252b | 3688 | /* PREFIX_VEX_0F11 */ |
09a2c6cf | 3689 | { |
592a252b L |
3690 | { VEX_W_TABLE (VEX_W_0F11_P_0) }, |
3691 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) }, | |
3692 | { VEX_W_TABLE (VEX_W_0F11_P_2) }, | |
3693 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) }, | |
09a2c6cf L |
3694 | }, |
3695 | ||
592a252b | 3696 | /* PREFIX_VEX_0F12 */ |
09a2c6cf | 3697 | { |
592a252b L |
3698 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
3699 | { VEX_W_TABLE (VEX_W_0F12_P_1) }, | |
3700 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) }, | |
3701 | { VEX_W_TABLE (VEX_W_0F12_P_3) }, | |
09a2c6cf L |
3702 | }, |
3703 | ||
592a252b | 3704 | /* PREFIX_VEX_0F16 */ |
09a2c6cf | 3705 | { |
592a252b L |
3706 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
3707 | { VEX_W_TABLE (VEX_W_0F16_P_1) }, | |
3708 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) }, | |
5f754f58 | 3709 | }, |
7c52e0e8 | 3710 | |
592a252b | 3711 | /* PREFIX_VEX_0F2A */ |
5f754f58 | 3712 | { |
592d1631 | 3713 | { Bad_Opcode }, |
592a252b | 3714 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) }, |
592d1631 | 3715 | { Bad_Opcode }, |
592a252b | 3716 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) }, |
5f754f58 | 3717 | }, |
7c52e0e8 | 3718 | |
592a252b | 3719 | /* PREFIX_VEX_0F2C */ |
5f754f58 | 3720 | { |
592d1631 | 3721 | { Bad_Opcode }, |
592a252b | 3722 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) }, |
592d1631 | 3723 | { Bad_Opcode }, |
592a252b | 3724 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) }, |
5f754f58 | 3725 | }, |
7c52e0e8 | 3726 | |
592a252b | 3727 | /* PREFIX_VEX_0F2D */ |
7c52e0e8 | 3728 | { |
592d1631 | 3729 | { Bad_Opcode }, |
592a252b | 3730 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) }, |
592d1631 | 3731 | { Bad_Opcode }, |
592a252b | 3732 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) }, |
7c52e0e8 L |
3733 | }, |
3734 | ||
592a252b | 3735 | /* PREFIX_VEX_0F2E */ |
7c52e0e8 | 3736 | { |
592a252b | 3737 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) }, |
592d1631 | 3738 | { Bad_Opcode }, |
592a252b | 3739 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) }, |
7c52e0e8 L |
3740 | }, |
3741 | ||
592a252b | 3742 | /* PREFIX_VEX_0F2F */ |
7c52e0e8 | 3743 | { |
592a252b | 3744 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) }, |
592d1631 | 3745 | { Bad_Opcode }, |
592a252b | 3746 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) }, |
7c52e0e8 L |
3747 | }, |
3748 | ||
592a252b | 3749 | /* PREFIX_VEX_0F51 */ |
7c52e0e8 | 3750 | { |
592a252b L |
3751 | { VEX_W_TABLE (VEX_W_0F51_P_0) }, |
3752 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) }, | |
3753 | { VEX_W_TABLE (VEX_W_0F51_P_2) }, | |
3754 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) }, | |
7c52e0e8 L |
3755 | }, |
3756 | ||
592a252b | 3757 | /* PREFIX_VEX_0F52 */ |
7c52e0e8 | 3758 | { |
592a252b L |
3759 | { VEX_W_TABLE (VEX_W_0F52_P_0) }, |
3760 | { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) }, | |
7c52e0e8 L |
3761 | }, |
3762 | ||
592a252b | 3763 | /* PREFIX_VEX_0F53 */ |
7c52e0e8 | 3764 | { |
592a252b L |
3765 | { VEX_W_TABLE (VEX_W_0F53_P_0) }, |
3766 | { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) }, | |
7c52e0e8 L |
3767 | }, |
3768 | ||
592a252b | 3769 | /* PREFIX_VEX_0F58 */ |
7c52e0e8 | 3770 | { |
592a252b L |
3771 | { VEX_W_TABLE (VEX_W_0F58_P_0) }, |
3772 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) }, | |
3773 | { VEX_W_TABLE (VEX_W_0F58_P_2) }, | |
3774 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) }, | |
7c52e0e8 L |
3775 | }, |
3776 | ||
592a252b | 3777 | /* PREFIX_VEX_0F59 */ |
7c52e0e8 | 3778 | { |
592a252b L |
3779 | { VEX_W_TABLE (VEX_W_0F59_P_0) }, |
3780 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) }, | |
3781 | { VEX_W_TABLE (VEX_W_0F59_P_2) }, | |
3782 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) }, | |
7c52e0e8 L |
3783 | }, |
3784 | ||
592a252b | 3785 | /* PREFIX_VEX_0F5A */ |
7c52e0e8 | 3786 | { |
592a252b L |
3787 | { VEX_W_TABLE (VEX_W_0F5A_P_0) }, |
3788 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) }, | |
c0f3af97 | 3789 | { "vcvtpd2ps%XY", { XMM, EXx } }, |
592a252b | 3790 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) }, |
7c52e0e8 L |
3791 | }, |
3792 | ||
592a252b | 3793 | /* PREFIX_VEX_0F5B */ |
7c52e0e8 | 3794 | { |
592a252b L |
3795 | { VEX_W_TABLE (VEX_W_0F5B_P_0) }, |
3796 | { VEX_W_TABLE (VEX_W_0F5B_P_1) }, | |
3797 | { VEX_W_TABLE (VEX_W_0F5B_P_2) }, | |
7c52e0e8 L |
3798 | }, |
3799 | ||
592a252b | 3800 | /* PREFIX_VEX_0F5C */ |
7c52e0e8 | 3801 | { |
592a252b L |
3802 | { VEX_W_TABLE (VEX_W_0F5C_P_0) }, |
3803 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) }, | |
3804 | { VEX_W_TABLE (VEX_W_0F5C_P_2) }, | |
3805 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) }, | |
7c52e0e8 L |
3806 | }, |
3807 | ||
592a252b | 3808 | /* PREFIX_VEX_0F5D */ |
7c52e0e8 | 3809 | { |
592a252b L |
3810 | { VEX_W_TABLE (VEX_W_0F5D_P_0) }, |
3811 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) }, | |
3812 | { VEX_W_TABLE (VEX_W_0F5D_P_2) }, | |
3813 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) }, | |
7c52e0e8 L |
3814 | }, |
3815 | ||
592a252b | 3816 | /* PREFIX_VEX_0F5E */ |
7c52e0e8 | 3817 | { |
592a252b L |
3818 | { VEX_W_TABLE (VEX_W_0F5E_P_0) }, |
3819 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) }, | |
3820 | { VEX_W_TABLE (VEX_W_0F5E_P_2) }, | |
3821 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) }, | |
7c52e0e8 L |
3822 | }, |
3823 | ||
592a252b | 3824 | /* PREFIX_VEX_0F5F */ |
7c52e0e8 | 3825 | { |
592a252b L |
3826 | { VEX_W_TABLE (VEX_W_0F5F_P_0) }, |
3827 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) }, | |
3828 | { VEX_W_TABLE (VEX_W_0F5F_P_2) }, | |
3829 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) }, | |
7c52e0e8 L |
3830 | }, |
3831 | ||
592a252b | 3832 | /* PREFIX_VEX_0F60 */ |
7c52e0e8 | 3833 | { |
592d1631 L |
3834 | { Bad_Opcode }, |
3835 | { Bad_Opcode }, | |
6c30d220 | 3836 | { VEX_W_TABLE (VEX_W_0F60_P_2) }, |
7c52e0e8 L |
3837 | }, |
3838 | ||
592a252b | 3839 | /* PREFIX_VEX_0F61 */ |
7c52e0e8 | 3840 | { |
592d1631 L |
3841 | { Bad_Opcode }, |
3842 | { Bad_Opcode }, | |
6c30d220 | 3843 | { VEX_W_TABLE (VEX_W_0F61_P_2) }, |
7c52e0e8 L |
3844 | }, |
3845 | ||
592a252b | 3846 | /* PREFIX_VEX_0F62 */ |
7c52e0e8 | 3847 | { |
592d1631 L |
3848 | { Bad_Opcode }, |
3849 | { Bad_Opcode }, | |
6c30d220 | 3850 | { VEX_W_TABLE (VEX_W_0F62_P_2) }, |
7c52e0e8 L |
3851 | }, |
3852 | ||
592a252b | 3853 | /* PREFIX_VEX_0F63 */ |
7c52e0e8 | 3854 | { |
592d1631 L |
3855 | { Bad_Opcode }, |
3856 | { Bad_Opcode }, | |
6c30d220 | 3857 | { VEX_W_TABLE (VEX_W_0F63_P_2) }, |
7c52e0e8 L |
3858 | }, |
3859 | ||
592a252b | 3860 | /* PREFIX_VEX_0F64 */ |
7c52e0e8 | 3861 | { |
592d1631 L |
3862 | { Bad_Opcode }, |
3863 | { Bad_Opcode }, | |
6c30d220 | 3864 | { VEX_W_TABLE (VEX_W_0F64_P_2) }, |
7c52e0e8 L |
3865 | }, |
3866 | ||
592a252b | 3867 | /* PREFIX_VEX_0F65 */ |
7c52e0e8 | 3868 | { |
592d1631 L |
3869 | { Bad_Opcode }, |
3870 | { Bad_Opcode }, | |
6c30d220 | 3871 | { VEX_W_TABLE (VEX_W_0F65_P_2) }, |
7c52e0e8 L |
3872 | }, |
3873 | ||
592a252b | 3874 | /* PREFIX_VEX_0F66 */ |
7c52e0e8 | 3875 | { |
592d1631 L |
3876 | { Bad_Opcode }, |
3877 | { Bad_Opcode }, | |
6c30d220 | 3878 | { VEX_W_TABLE (VEX_W_0F66_P_2) }, |
7c52e0e8 | 3879 | }, |
6439fc28 | 3880 | |
592a252b | 3881 | /* PREFIX_VEX_0F67 */ |
331d2d0d | 3882 | { |
592d1631 L |
3883 | { Bad_Opcode }, |
3884 | { Bad_Opcode }, | |
6c30d220 | 3885 | { VEX_W_TABLE (VEX_W_0F67_P_2) }, |
c0f3af97 L |
3886 | }, |
3887 | ||
592a252b | 3888 | /* PREFIX_VEX_0F68 */ |
c0f3af97 | 3889 | { |
592d1631 L |
3890 | { Bad_Opcode }, |
3891 | { Bad_Opcode }, | |
6c30d220 | 3892 | { VEX_W_TABLE (VEX_W_0F68_P_2) }, |
c0f3af97 L |
3893 | }, |
3894 | ||
592a252b | 3895 | /* PREFIX_VEX_0F69 */ |
c0f3af97 | 3896 | { |
592d1631 L |
3897 | { Bad_Opcode }, |
3898 | { Bad_Opcode }, | |
6c30d220 | 3899 | { VEX_W_TABLE (VEX_W_0F69_P_2) }, |
c0f3af97 L |
3900 | }, |
3901 | ||
592a252b | 3902 | /* PREFIX_VEX_0F6A */ |
c0f3af97 | 3903 | { |
592d1631 L |
3904 | { Bad_Opcode }, |
3905 | { Bad_Opcode }, | |
6c30d220 | 3906 | { VEX_W_TABLE (VEX_W_0F6A_P_2) }, |
c0f3af97 L |
3907 | }, |
3908 | ||
592a252b | 3909 | /* PREFIX_VEX_0F6B */ |
c0f3af97 | 3910 | { |
592d1631 L |
3911 | { Bad_Opcode }, |
3912 | { Bad_Opcode }, | |
6c30d220 | 3913 | { VEX_W_TABLE (VEX_W_0F6B_P_2) }, |
c0f3af97 L |
3914 | }, |
3915 | ||
592a252b | 3916 | /* PREFIX_VEX_0F6C */ |
c0f3af97 | 3917 | { |
592d1631 L |
3918 | { Bad_Opcode }, |
3919 | { Bad_Opcode }, | |
6c30d220 | 3920 | { VEX_W_TABLE (VEX_W_0F6C_P_2) }, |
c0f3af97 L |
3921 | }, |
3922 | ||
592a252b | 3923 | /* PREFIX_VEX_0F6D */ |
c0f3af97 | 3924 | { |
592d1631 L |
3925 | { Bad_Opcode }, |
3926 | { Bad_Opcode }, | |
6c30d220 | 3927 | { VEX_W_TABLE (VEX_W_0F6D_P_2) }, |
c0f3af97 L |
3928 | }, |
3929 | ||
592a252b | 3930 | /* PREFIX_VEX_0F6E */ |
c0f3af97 | 3931 | { |
592d1631 L |
3932 | { Bad_Opcode }, |
3933 | { Bad_Opcode }, | |
592a252b | 3934 | { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, |
c0f3af97 L |
3935 | }, |
3936 | ||
592a252b | 3937 | /* PREFIX_VEX_0F6F */ |
c0f3af97 | 3938 | { |
592d1631 | 3939 | { Bad_Opcode }, |
592a252b L |
3940 | { VEX_W_TABLE (VEX_W_0F6F_P_1) }, |
3941 | { VEX_W_TABLE (VEX_W_0F6F_P_2) }, | |
c0f3af97 L |
3942 | }, |
3943 | ||
592a252b | 3944 | /* PREFIX_VEX_0F70 */ |
c0f3af97 | 3945 | { |
592d1631 | 3946 | { Bad_Opcode }, |
6c30d220 L |
3947 | { VEX_W_TABLE (VEX_W_0F70_P_1) }, |
3948 | { VEX_W_TABLE (VEX_W_0F70_P_2) }, | |
3949 | { VEX_W_TABLE (VEX_W_0F70_P_3) }, | |
c0f3af97 L |
3950 | }, |
3951 | ||
592a252b | 3952 | /* PREFIX_VEX_0F71_REG_2 */ |
c0f3af97 | 3953 | { |
592d1631 L |
3954 | { Bad_Opcode }, |
3955 | { Bad_Opcode }, | |
6c30d220 | 3956 | { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) }, |
c0f3af97 L |
3957 | }, |
3958 | ||
592a252b | 3959 | /* PREFIX_VEX_0F71_REG_4 */ |
c0f3af97 | 3960 | { |
592d1631 L |
3961 | { Bad_Opcode }, |
3962 | { Bad_Opcode }, | |
6c30d220 | 3963 | { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) }, |
c0f3af97 L |
3964 | }, |
3965 | ||
592a252b | 3966 | /* PREFIX_VEX_0F71_REG_6 */ |
c0f3af97 | 3967 | { |
592d1631 L |
3968 | { Bad_Opcode }, |
3969 | { Bad_Opcode }, | |
6c30d220 | 3970 | { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) }, |
c0f3af97 L |
3971 | }, |
3972 | ||
592a252b | 3973 | /* PREFIX_VEX_0F72_REG_2 */ |
c0f3af97 | 3974 | { |
592d1631 L |
3975 | { Bad_Opcode }, |
3976 | { Bad_Opcode }, | |
6c30d220 | 3977 | { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) }, |
c0f3af97 L |
3978 | }, |
3979 | ||
592a252b | 3980 | /* PREFIX_VEX_0F72_REG_4 */ |
c0f3af97 | 3981 | { |
592d1631 L |
3982 | { Bad_Opcode }, |
3983 | { Bad_Opcode }, | |
6c30d220 | 3984 | { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) }, |
c0f3af97 L |
3985 | }, |
3986 | ||
592a252b | 3987 | /* PREFIX_VEX_0F72_REG_6 */ |
c0f3af97 | 3988 | { |
592d1631 L |
3989 | { Bad_Opcode }, |
3990 | { Bad_Opcode }, | |
6c30d220 | 3991 | { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) }, |
c0f3af97 L |
3992 | }, |
3993 | ||
592a252b | 3994 | /* PREFIX_VEX_0F73_REG_2 */ |
c0f3af97 | 3995 | { |
592d1631 L |
3996 | { Bad_Opcode }, |
3997 | { Bad_Opcode }, | |
6c30d220 | 3998 | { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) }, |
c0f3af97 L |
3999 | }, |
4000 | ||
592a252b | 4001 | /* PREFIX_VEX_0F73_REG_3 */ |
c0f3af97 | 4002 | { |
592d1631 L |
4003 | { Bad_Opcode }, |
4004 | { Bad_Opcode }, | |
6c30d220 | 4005 | { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) }, |
c0f3af97 L |
4006 | }, |
4007 | ||
592a252b | 4008 | /* PREFIX_VEX_0F73_REG_6 */ |
c0f3af97 | 4009 | { |
592d1631 L |
4010 | { Bad_Opcode }, |
4011 | { Bad_Opcode }, | |
6c30d220 | 4012 | { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) }, |
c0f3af97 L |
4013 | }, |
4014 | ||
592a252b | 4015 | /* PREFIX_VEX_0F73_REG_7 */ |
c0f3af97 | 4016 | { |
592d1631 L |
4017 | { Bad_Opcode }, |
4018 | { Bad_Opcode }, | |
6c30d220 | 4019 | { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) }, |
c0f3af97 L |
4020 | }, |
4021 | ||
592a252b | 4022 | /* PREFIX_VEX_0F74 */ |
c0f3af97 | 4023 | { |
592d1631 L |
4024 | { Bad_Opcode }, |
4025 | { Bad_Opcode }, | |
6c30d220 | 4026 | { VEX_W_TABLE (VEX_W_0F74_P_2) }, |
c0f3af97 L |
4027 | }, |
4028 | ||
592a252b | 4029 | /* PREFIX_VEX_0F75 */ |
c0f3af97 | 4030 | { |
592d1631 L |
4031 | { Bad_Opcode }, |
4032 | { Bad_Opcode }, | |
6c30d220 | 4033 | { VEX_W_TABLE (VEX_W_0F75_P_2) }, |
c0f3af97 L |
4034 | }, |
4035 | ||
592a252b | 4036 | /* PREFIX_VEX_0F76 */ |
c0f3af97 | 4037 | { |
592d1631 L |
4038 | { Bad_Opcode }, |
4039 | { Bad_Opcode }, | |
6c30d220 | 4040 | { VEX_W_TABLE (VEX_W_0F76_P_2) }, |
c0f3af97 L |
4041 | }, |
4042 | ||
592a252b | 4043 | /* PREFIX_VEX_0F77 */ |
c0f3af97 | 4044 | { |
592a252b | 4045 | { VEX_W_TABLE (VEX_W_0F77_P_0) }, |
c0f3af97 L |
4046 | }, |
4047 | ||
592a252b | 4048 | /* PREFIX_VEX_0F7C */ |
c0f3af97 | 4049 | { |
592d1631 L |
4050 | { Bad_Opcode }, |
4051 | { Bad_Opcode }, | |
592a252b L |
4052 | { VEX_W_TABLE (VEX_W_0F7C_P_2) }, |
4053 | { VEX_W_TABLE (VEX_W_0F7C_P_3) }, | |
c0f3af97 L |
4054 | }, |
4055 | ||
592a252b | 4056 | /* PREFIX_VEX_0F7D */ |
c0f3af97 | 4057 | { |
592d1631 L |
4058 | { Bad_Opcode }, |
4059 | { Bad_Opcode }, | |
592a252b L |
4060 | { VEX_W_TABLE (VEX_W_0F7D_P_2) }, |
4061 | { VEX_W_TABLE (VEX_W_0F7D_P_3) }, | |
c0f3af97 L |
4062 | }, |
4063 | ||
592a252b | 4064 | /* PREFIX_VEX_0F7E */ |
c0f3af97 | 4065 | { |
592d1631 | 4066 | { Bad_Opcode }, |
592a252b L |
4067 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
4068 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, | |
c0f3af97 L |
4069 | }, |
4070 | ||
592a252b | 4071 | /* PREFIX_VEX_0F7F */ |
c0f3af97 | 4072 | { |
592d1631 | 4073 | { Bad_Opcode }, |
592a252b L |
4074 | { VEX_W_TABLE (VEX_W_0F7F_P_1) }, |
4075 | { VEX_W_TABLE (VEX_W_0F7F_P_2) }, | |
c0f3af97 L |
4076 | }, |
4077 | ||
592a252b | 4078 | /* PREFIX_VEX_0FC2 */ |
c0f3af97 | 4079 | { |
592a252b L |
4080 | { VEX_W_TABLE (VEX_W_0FC2_P_0) }, |
4081 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) }, | |
4082 | { VEX_W_TABLE (VEX_W_0FC2_P_2) }, | |
4083 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) }, | |
c0f3af97 L |
4084 | }, |
4085 | ||
592a252b | 4086 | /* PREFIX_VEX_0FC4 */ |
c0f3af97 | 4087 | { |
592d1631 L |
4088 | { Bad_Opcode }, |
4089 | { Bad_Opcode }, | |
592a252b | 4090 | { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, |
c0f3af97 L |
4091 | }, |
4092 | ||
592a252b | 4093 | /* PREFIX_VEX_0FC5 */ |
c0f3af97 | 4094 | { |
592d1631 L |
4095 | { Bad_Opcode }, |
4096 | { Bad_Opcode }, | |
592a252b | 4097 | { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, |
c0f3af97 L |
4098 | }, |
4099 | ||
592a252b | 4100 | /* PREFIX_VEX_0FD0 */ |
c0f3af97 | 4101 | { |
592d1631 L |
4102 | { Bad_Opcode }, |
4103 | { Bad_Opcode }, | |
592a252b L |
4104 | { VEX_W_TABLE (VEX_W_0FD0_P_2) }, |
4105 | { VEX_W_TABLE (VEX_W_0FD0_P_3) }, | |
c0f3af97 L |
4106 | }, |
4107 | ||
592a252b | 4108 | /* PREFIX_VEX_0FD1 */ |
c0f3af97 | 4109 | { |
592d1631 L |
4110 | { Bad_Opcode }, |
4111 | { Bad_Opcode }, | |
6c30d220 | 4112 | { VEX_W_TABLE (VEX_W_0FD1_P_2) }, |
c0f3af97 L |
4113 | }, |
4114 | ||
592a252b | 4115 | /* PREFIX_VEX_0FD2 */ |
c0f3af97 | 4116 | { |
592d1631 L |
4117 | { Bad_Opcode }, |
4118 | { Bad_Opcode }, | |
6c30d220 | 4119 | { VEX_W_TABLE (VEX_W_0FD2_P_2) }, |
c0f3af97 L |
4120 | }, |
4121 | ||
592a252b | 4122 | /* PREFIX_VEX_0FD3 */ |
c0f3af97 | 4123 | { |
592d1631 L |
4124 | { Bad_Opcode }, |
4125 | { Bad_Opcode }, | |
6c30d220 | 4126 | { VEX_W_TABLE (VEX_W_0FD3_P_2) }, |
c0f3af97 L |
4127 | }, |
4128 | ||
592a252b | 4129 | /* PREFIX_VEX_0FD4 */ |
c0f3af97 | 4130 | { |
592d1631 L |
4131 | { Bad_Opcode }, |
4132 | { Bad_Opcode }, | |
6c30d220 | 4133 | { VEX_W_TABLE (VEX_W_0FD4_P_2) }, |
c0f3af97 L |
4134 | }, |
4135 | ||
592a252b | 4136 | /* PREFIX_VEX_0FD5 */ |
c0f3af97 | 4137 | { |
592d1631 L |
4138 | { Bad_Opcode }, |
4139 | { Bad_Opcode }, | |
6c30d220 | 4140 | { VEX_W_TABLE (VEX_W_0FD5_P_2) }, |
c0f3af97 L |
4141 | }, |
4142 | ||
592a252b | 4143 | /* PREFIX_VEX_0FD6 */ |
c0f3af97 | 4144 | { |
592d1631 L |
4145 | { Bad_Opcode }, |
4146 | { Bad_Opcode }, | |
592a252b | 4147 | { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, |
c0f3af97 L |
4148 | }, |
4149 | ||
592a252b | 4150 | /* PREFIX_VEX_0FD7 */ |
c0f3af97 | 4151 | { |
592d1631 L |
4152 | { Bad_Opcode }, |
4153 | { Bad_Opcode }, | |
592a252b | 4154 | { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, |
c0f3af97 L |
4155 | }, |
4156 | ||
592a252b | 4157 | /* PREFIX_VEX_0FD8 */ |
c0f3af97 | 4158 | { |
592d1631 L |
4159 | { Bad_Opcode }, |
4160 | { Bad_Opcode }, | |
6c30d220 | 4161 | { VEX_W_TABLE (VEX_W_0FD8_P_2) }, |
c0f3af97 L |
4162 | }, |
4163 | ||
592a252b | 4164 | /* PREFIX_VEX_0FD9 */ |
c0f3af97 | 4165 | { |
592d1631 L |
4166 | { Bad_Opcode }, |
4167 | { Bad_Opcode }, | |
6c30d220 | 4168 | { VEX_W_TABLE (VEX_W_0FD9_P_2) }, |
c0f3af97 L |
4169 | }, |
4170 | ||
592a252b | 4171 | /* PREFIX_VEX_0FDA */ |
c0f3af97 | 4172 | { |
592d1631 L |
4173 | { Bad_Opcode }, |
4174 | { Bad_Opcode }, | |
6c30d220 | 4175 | { VEX_W_TABLE (VEX_W_0FDA_P_2) }, |
c0f3af97 L |
4176 | }, |
4177 | ||
592a252b | 4178 | /* PREFIX_VEX_0FDB */ |
c0f3af97 | 4179 | { |
592d1631 L |
4180 | { Bad_Opcode }, |
4181 | { Bad_Opcode }, | |
6c30d220 | 4182 | { VEX_W_TABLE (VEX_W_0FDB_P_2) }, |
c0f3af97 L |
4183 | }, |
4184 | ||
592a252b | 4185 | /* PREFIX_VEX_0FDC */ |
c0f3af97 | 4186 | { |
592d1631 L |
4187 | { Bad_Opcode }, |
4188 | { Bad_Opcode }, | |
6c30d220 | 4189 | { VEX_W_TABLE (VEX_W_0FDC_P_2) }, |
c0f3af97 L |
4190 | }, |
4191 | ||
592a252b | 4192 | /* PREFIX_VEX_0FDD */ |
c0f3af97 | 4193 | { |
592d1631 L |
4194 | { Bad_Opcode }, |
4195 | { Bad_Opcode }, | |
6c30d220 | 4196 | { VEX_W_TABLE (VEX_W_0FDD_P_2) }, |
c0f3af97 L |
4197 | }, |
4198 | ||
592a252b | 4199 | /* PREFIX_VEX_0FDE */ |
c0f3af97 | 4200 | { |
592d1631 L |
4201 | { Bad_Opcode }, |
4202 | { Bad_Opcode }, | |
6c30d220 | 4203 | { VEX_W_TABLE (VEX_W_0FDE_P_2) }, |
c0f3af97 L |
4204 | }, |
4205 | ||
592a252b | 4206 | /* PREFIX_VEX_0FDF */ |
c0f3af97 | 4207 | { |
592d1631 L |
4208 | { Bad_Opcode }, |
4209 | { Bad_Opcode }, | |
6c30d220 | 4210 | { VEX_W_TABLE (VEX_W_0FDF_P_2) }, |
c0f3af97 L |
4211 | }, |
4212 | ||
592a252b | 4213 | /* PREFIX_VEX_0FE0 */ |
c0f3af97 | 4214 | { |
592d1631 L |
4215 | { Bad_Opcode }, |
4216 | { Bad_Opcode }, | |
6c30d220 | 4217 | { VEX_W_TABLE (VEX_W_0FE0_P_2) }, |
c0f3af97 L |
4218 | }, |
4219 | ||
592a252b | 4220 | /* PREFIX_VEX_0FE1 */ |
c0f3af97 | 4221 | { |
592d1631 L |
4222 | { Bad_Opcode }, |
4223 | { Bad_Opcode }, | |
6c30d220 | 4224 | { VEX_W_TABLE (VEX_W_0FE1_P_2) }, |
c0f3af97 L |
4225 | }, |
4226 | ||
592a252b | 4227 | /* PREFIX_VEX_0FE2 */ |
c0f3af97 | 4228 | { |
592d1631 L |
4229 | { Bad_Opcode }, |
4230 | { Bad_Opcode }, | |
6c30d220 | 4231 | { VEX_W_TABLE (VEX_W_0FE2_P_2) }, |
c0f3af97 L |
4232 | }, |
4233 | ||
592a252b | 4234 | /* PREFIX_VEX_0FE3 */ |
c0f3af97 | 4235 | { |
592d1631 L |
4236 | { Bad_Opcode }, |
4237 | { Bad_Opcode }, | |
6c30d220 | 4238 | { VEX_W_TABLE (VEX_W_0FE3_P_2) }, |
c0f3af97 L |
4239 | }, |
4240 | ||
592a252b | 4241 | /* PREFIX_VEX_0FE4 */ |
c0f3af97 | 4242 | { |
592d1631 L |
4243 | { Bad_Opcode }, |
4244 | { Bad_Opcode }, | |
6c30d220 | 4245 | { VEX_W_TABLE (VEX_W_0FE4_P_2) }, |
c0f3af97 L |
4246 | }, |
4247 | ||
592a252b | 4248 | /* PREFIX_VEX_0FE5 */ |
c0f3af97 | 4249 | { |
592d1631 L |
4250 | { Bad_Opcode }, |
4251 | { Bad_Opcode }, | |
6c30d220 | 4252 | { VEX_W_TABLE (VEX_W_0FE5_P_2) }, |
c0f3af97 L |
4253 | }, |
4254 | ||
592a252b | 4255 | /* PREFIX_VEX_0FE6 */ |
c0f3af97 | 4256 | { |
592d1631 | 4257 | { Bad_Opcode }, |
592a252b L |
4258 | { VEX_W_TABLE (VEX_W_0FE6_P_1) }, |
4259 | { VEX_W_TABLE (VEX_W_0FE6_P_2) }, | |
4260 | { VEX_W_TABLE (VEX_W_0FE6_P_3) }, | |
c0f3af97 L |
4261 | }, |
4262 | ||
592a252b | 4263 | /* PREFIX_VEX_0FE7 */ |
c0f3af97 | 4264 | { |
592d1631 L |
4265 | { Bad_Opcode }, |
4266 | { Bad_Opcode }, | |
592a252b | 4267 | { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, |
c0f3af97 L |
4268 | }, |
4269 | ||
592a252b | 4270 | /* PREFIX_VEX_0FE8 */ |
c0f3af97 | 4271 | { |
592d1631 L |
4272 | { Bad_Opcode }, |
4273 | { Bad_Opcode }, | |
6c30d220 | 4274 | { VEX_W_TABLE (VEX_W_0FE8_P_2) }, |
c0f3af97 L |
4275 | }, |
4276 | ||
592a252b | 4277 | /* PREFIX_VEX_0FE9 */ |
c0f3af97 | 4278 | { |
592d1631 L |
4279 | { Bad_Opcode }, |
4280 | { Bad_Opcode }, | |
6c30d220 | 4281 | { VEX_W_TABLE (VEX_W_0FE9_P_2) }, |
c0f3af97 L |
4282 | }, |
4283 | ||
592a252b | 4284 | /* PREFIX_VEX_0FEA */ |
c0f3af97 | 4285 | { |
592d1631 L |
4286 | { Bad_Opcode }, |
4287 | { Bad_Opcode }, | |
6c30d220 | 4288 | { VEX_W_TABLE (VEX_W_0FEA_P_2) }, |
c0f3af97 L |
4289 | }, |
4290 | ||
592a252b | 4291 | /* PREFIX_VEX_0FEB */ |
c0f3af97 | 4292 | { |
592d1631 L |
4293 | { Bad_Opcode }, |
4294 | { Bad_Opcode }, | |
6c30d220 | 4295 | { VEX_W_TABLE (VEX_W_0FEB_P_2) }, |
c0f3af97 L |
4296 | }, |
4297 | ||
592a252b | 4298 | /* PREFIX_VEX_0FEC */ |
c0f3af97 | 4299 | { |
592d1631 L |
4300 | { Bad_Opcode }, |
4301 | { Bad_Opcode }, | |
6c30d220 | 4302 | { VEX_W_TABLE (VEX_W_0FEC_P_2) }, |
c0f3af97 L |
4303 | }, |
4304 | ||
592a252b | 4305 | /* PREFIX_VEX_0FED */ |
c0f3af97 | 4306 | { |
592d1631 L |
4307 | { Bad_Opcode }, |
4308 | { Bad_Opcode }, | |
6c30d220 | 4309 | { VEX_W_TABLE (VEX_W_0FED_P_2) }, |
c0f3af97 L |
4310 | }, |
4311 | ||
592a252b | 4312 | /* PREFIX_VEX_0FEE */ |
c0f3af97 | 4313 | { |
592d1631 L |
4314 | { Bad_Opcode }, |
4315 | { Bad_Opcode }, | |
6c30d220 | 4316 | { VEX_W_TABLE (VEX_W_0FEE_P_2) }, |
c0f3af97 L |
4317 | }, |
4318 | ||
592a252b | 4319 | /* PREFIX_VEX_0FEF */ |
c0f3af97 | 4320 | { |
592d1631 L |
4321 | { Bad_Opcode }, |
4322 | { Bad_Opcode }, | |
6c30d220 | 4323 | { VEX_W_TABLE (VEX_W_0FEF_P_2) }, |
c0f3af97 L |
4324 | }, |
4325 | ||
592a252b | 4326 | /* PREFIX_VEX_0FF0 */ |
c0f3af97 | 4327 | { |
592d1631 L |
4328 | { Bad_Opcode }, |
4329 | { Bad_Opcode }, | |
4330 | { Bad_Opcode }, | |
592a252b | 4331 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, |
c0f3af97 L |
4332 | }, |
4333 | ||
592a252b | 4334 | /* PREFIX_VEX_0FF1 */ |
c0f3af97 | 4335 | { |
592d1631 L |
4336 | { Bad_Opcode }, |
4337 | { Bad_Opcode }, | |
6c30d220 | 4338 | { VEX_W_TABLE (VEX_W_0FF1_P_2) }, |
c0f3af97 L |
4339 | }, |
4340 | ||
592a252b | 4341 | /* PREFIX_VEX_0FF2 */ |
c0f3af97 | 4342 | { |
592d1631 L |
4343 | { Bad_Opcode }, |
4344 | { Bad_Opcode }, | |
6c30d220 | 4345 | { VEX_W_TABLE (VEX_W_0FF2_P_2) }, |
c0f3af97 L |
4346 | }, |
4347 | ||
592a252b | 4348 | /* PREFIX_VEX_0FF3 */ |
c0f3af97 | 4349 | { |
592d1631 L |
4350 | { Bad_Opcode }, |
4351 | { Bad_Opcode }, | |
6c30d220 | 4352 | { VEX_W_TABLE (VEX_W_0FF3_P_2) }, |
c0f3af97 L |
4353 | }, |
4354 | ||
592a252b | 4355 | /* PREFIX_VEX_0FF4 */ |
c0f3af97 | 4356 | { |
592d1631 L |
4357 | { Bad_Opcode }, |
4358 | { Bad_Opcode }, | |
6c30d220 | 4359 | { VEX_W_TABLE (VEX_W_0FF4_P_2) }, |
c0f3af97 L |
4360 | }, |
4361 | ||
592a252b | 4362 | /* PREFIX_VEX_0FF5 */ |
c0f3af97 | 4363 | { |
592d1631 L |
4364 | { Bad_Opcode }, |
4365 | { Bad_Opcode }, | |
6c30d220 | 4366 | { VEX_W_TABLE (VEX_W_0FF5_P_2) }, |
c0f3af97 L |
4367 | }, |
4368 | ||
592a252b | 4369 | /* PREFIX_VEX_0FF6 */ |
c0f3af97 | 4370 | { |
592d1631 L |
4371 | { Bad_Opcode }, |
4372 | { Bad_Opcode }, | |
6c30d220 | 4373 | { VEX_W_TABLE (VEX_W_0FF6_P_2) }, |
c0f3af97 L |
4374 | }, |
4375 | ||
592a252b | 4376 | /* PREFIX_VEX_0FF7 */ |
c0f3af97 | 4377 | { |
592d1631 L |
4378 | { Bad_Opcode }, |
4379 | { Bad_Opcode }, | |
592a252b | 4380 | { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, |
c0f3af97 L |
4381 | }, |
4382 | ||
592a252b | 4383 | /* PREFIX_VEX_0FF8 */ |
c0f3af97 | 4384 | { |
592d1631 L |
4385 | { Bad_Opcode }, |
4386 | { Bad_Opcode }, | |
6c30d220 | 4387 | { VEX_W_TABLE (VEX_W_0FF8_P_2) }, |
c0f3af97 L |
4388 | }, |
4389 | ||
592a252b | 4390 | /* PREFIX_VEX_0FF9 */ |
c0f3af97 | 4391 | { |
592d1631 L |
4392 | { Bad_Opcode }, |
4393 | { Bad_Opcode }, | |
6c30d220 | 4394 | { VEX_W_TABLE (VEX_W_0FF9_P_2) }, |
c0f3af97 L |
4395 | }, |
4396 | ||
592a252b | 4397 | /* PREFIX_VEX_0FFA */ |
c0f3af97 | 4398 | { |
592d1631 L |
4399 | { Bad_Opcode }, |
4400 | { Bad_Opcode }, | |
6c30d220 | 4401 | { VEX_W_TABLE (VEX_W_0FFA_P_2) }, |
c0f3af97 L |
4402 | }, |
4403 | ||
592a252b | 4404 | /* PREFIX_VEX_0FFB */ |
c0f3af97 | 4405 | { |
592d1631 L |
4406 | { Bad_Opcode }, |
4407 | { Bad_Opcode }, | |
6c30d220 | 4408 | { VEX_W_TABLE (VEX_W_0FFB_P_2) }, |
c0f3af97 L |
4409 | }, |
4410 | ||
592a252b | 4411 | /* PREFIX_VEX_0FFC */ |
c0f3af97 | 4412 | { |
592d1631 L |
4413 | { Bad_Opcode }, |
4414 | { Bad_Opcode }, | |
6c30d220 | 4415 | { VEX_W_TABLE (VEX_W_0FFC_P_2) }, |
c0f3af97 L |
4416 | }, |
4417 | ||
592a252b | 4418 | /* PREFIX_VEX_0FFD */ |
c0f3af97 | 4419 | { |
592d1631 L |
4420 | { Bad_Opcode }, |
4421 | { Bad_Opcode }, | |
6c30d220 | 4422 | { VEX_W_TABLE (VEX_W_0FFD_P_2) }, |
c0f3af97 L |
4423 | }, |
4424 | ||
592a252b | 4425 | /* PREFIX_VEX_0FFE */ |
c0f3af97 | 4426 | { |
592d1631 L |
4427 | { Bad_Opcode }, |
4428 | { Bad_Opcode }, | |
6c30d220 | 4429 | { VEX_W_TABLE (VEX_W_0FFE_P_2) }, |
c0f3af97 L |
4430 | }, |
4431 | ||
592a252b | 4432 | /* PREFIX_VEX_0F3800 */ |
c0f3af97 | 4433 | { |
592d1631 L |
4434 | { Bad_Opcode }, |
4435 | { Bad_Opcode }, | |
6c30d220 | 4436 | { VEX_W_TABLE (VEX_W_0F3800_P_2) }, |
c0f3af97 L |
4437 | }, |
4438 | ||
592a252b | 4439 | /* PREFIX_VEX_0F3801 */ |
c0f3af97 | 4440 | { |
592d1631 L |
4441 | { Bad_Opcode }, |
4442 | { Bad_Opcode }, | |
6c30d220 | 4443 | { VEX_W_TABLE (VEX_W_0F3801_P_2) }, |
c0f3af97 L |
4444 | }, |
4445 | ||
592a252b | 4446 | /* PREFIX_VEX_0F3802 */ |
c0f3af97 | 4447 | { |
592d1631 L |
4448 | { Bad_Opcode }, |
4449 | { Bad_Opcode }, | |
6c30d220 | 4450 | { VEX_W_TABLE (VEX_W_0F3802_P_2) }, |
c0f3af97 L |
4451 | }, |
4452 | ||
592a252b | 4453 | /* PREFIX_VEX_0F3803 */ |
c0f3af97 | 4454 | { |
592d1631 L |
4455 | { Bad_Opcode }, |
4456 | { Bad_Opcode }, | |
6c30d220 | 4457 | { VEX_W_TABLE (VEX_W_0F3803_P_2) }, |
c0f3af97 L |
4458 | }, |
4459 | ||
592a252b | 4460 | /* PREFIX_VEX_0F3804 */ |
c0f3af97 | 4461 | { |
592d1631 L |
4462 | { Bad_Opcode }, |
4463 | { Bad_Opcode }, | |
6c30d220 | 4464 | { VEX_W_TABLE (VEX_W_0F3804_P_2) }, |
c0f3af97 L |
4465 | }, |
4466 | ||
592a252b | 4467 | /* PREFIX_VEX_0F3805 */ |
c0f3af97 | 4468 | { |
592d1631 L |
4469 | { Bad_Opcode }, |
4470 | { Bad_Opcode }, | |
6c30d220 | 4471 | { VEX_W_TABLE (VEX_W_0F3805_P_2) }, |
c0f3af97 L |
4472 | }, |
4473 | ||
592a252b | 4474 | /* PREFIX_VEX_0F3806 */ |
c0f3af97 | 4475 | { |
592d1631 L |
4476 | { Bad_Opcode }, |
4477 | { Bad_Opcode }, | |
6c30d220 | 4478 | { VEX_W_TABLE (VEX_W_0F3806_P_2) }, |
c0f3af97 L |
4479 | }, |
4480 | ||
592a252b | 4481 | /* PREFIX_VEX_0F3807 */ |
c0f3af97 | 4482 | { |
592d1631 L |
4483 | { Bad_Opcode }, |
4484 | { Bad_Opcode }, | |
6c30d220 | 4485 | { VEX_W_TABLE (VEX_W_0F3807_P_2) }, |
c0f3af97 L |
4486 | }, |
4487 | ||
592a252b | 4488 | /* PREFIX_VEX_0F3808 */ |
c0f3af97 | 4489 | { |
592d1631 L |
4490 | { Bad_Opcode }, |
4491 | { Bad_Opcode }, | |
6c30d220 | 4492 | { VEX_W_TABLE (VEX_W_0F3808_P_2) }, |
c0f3af97 L |
4493 | }, |
4494 | ||
592a252b | 4495 | /* PREFIX_VEX_0F3809 */ |
c0f3af97 | 4496 | { |
592d1631 L |
4497 | { Bad_Opcode }, |
4498 | { Bad_Opcode }, | |
6c30d220 | 4499 | { VEX_W_TABLE (VEX_W_0F3809_P_2) }, |
c0f3af97 L |
4500 | }, |
4501 | ||
592a252b | 4502 | /* PREFIX_VEX_0F380A */ |
c0f3af97 | 4503 | { |
592d1631 L |
4504 | { Bad_Opcode }, |
4505 | { Bad_Opcode }, | |
6c30d220 | 4506 | { VEX_W_TABLE (VEX_W_0F380A_P_2) }, |
c0f3af97 L |
4507 | }, |
4508 | ||
592a252b | 4509 | /* PREFIX_VEX_0F380B */ |
c0f3af97 | 4510 | { |
592d1631 L |
4511 | { Bad_Opcode }, |
4512 | { Bad_Opcode }, | |
6c30d220 | 4513 | { VEX_W_TABLE (VEX_W_0F380B_P_2) }, |
c0f3af97 L |
4514 | }, |
4515 | ||
592a252b | 4516 | /* PREFIX_VEX_0F380C */ |
c0f3af97 | 4517 | { |
592d1631 L |
4518 | { Bad_Opcode }, |
4519 | { Bad_Opcode }, | |
592a252b | 4520 | { VEX_W_TABLE (VEX_W_0F380C_P_2) }, |
c0f3af97 L |
4521 | }, |
4522 | ||
592a252b | 4523 | /* PREFIX_VEX_0F380D */ |
c0f3af97 | 4524 | { |
592d1631 L |
4525 | { Bad_Opcode }, |
4526 | { Bad_Opcode }, | |
592a252b | 4527 | { VEX_W_TABLE (VEX_W_0F380D_P_2) }, |
c0f3af97 L |
4528 | }, |
4529 | ||
592a252b | 4530 | /* PREFIX_VEX_0F380E */ |
c0f3af97 | 4531 | { |
592d1631 L |
4532 | { Bad_Opcode }, |
4533 | { Bad_Opcode }, | |
592a252b | 4534 | { VEX_W_TABLE (VEX_W_0F380E_P_2) }, |
c0f3af97 L |
4535 | }, |
4536 | ||
592a252b | 4537 | /* PREFIX_VEX_0F380F */ |
c0f3af97 | 4538 | { |
592d1631 L |
4539 | { Bad_Opcode }, |
4540 | { Bad_Opcode }, | |
592a252b | 4541 | { VEX_W_TABLE (VEX_W_0F380F_P_2) }, |
c0f3af97 L |
4542 | }, |
4543 | ||
592a252b | 4544 | /* PREFIX_VEX_0F3813 */ |
c7b8aa3a L |
4545 | { |
4546 | { Bad_Opcode }, | |
4547 | { Bad_Opcode }, | |
4548 | { "vcvtph2ps", { XM, EXxmmq } }, | |
4549 | }, | |
4550 | ||
6c30d220 L |
4551 | /* PREFIX_VEX_0F3816 */ |
4552 | { | |
4553 | { Bad_Opcode }, | |
4554 | { Bad_Opcode }, | |
4555 | { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) }, | |
4556 | }, | |
4557 | ||
592a252b | 4558 | /* PREFIX_VEX_0F3817 */ |
c0f3af97 | 4559 | { |
592d1631 L |
4560 | { Bad_Opcode }, |
4561 | { Bad_Opcode }, | |
592a252b | 4562 | { VEX_W_TABLE (VEX_W_0F3817_P_2) }, |
c0f3af97 L |
4563 | }, |
4564 | ||
592a252b | 4565 | /* PREFIX_VEX_0F3818 */ |
c0f3af97 | 4566 | { |
592d1631 L |
4567 | { Bad_Opcode }, |
4568 | { Bad_Opcode }, | |
6c30d220 | 4569 | { VEX_W_TABLE (VEX_W_0F3818_P_2) }, |
c0f3af97 L |
4570 | }, |
4571 | ||
592a252b | 4572 | /* PREFIX_VEX_0F3819 */ |
c0f3af97 | 4573 | { |
592d1631 L |
4574 | { Bad_Opcode }, |
4575 | { Bad_Opcode }, | |
6c30d220 | 4576 | { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) }, |
c0f3af97 L |
4577 | }, |
4578 | ||
592a252b | 4579 | /* PREFIX_VEX_0F381A */ |
c0f3af97 | 4580 | { |
592d1631 L |
4581 | { Bad_Opcode }, |
4582 | { Bad_Opcode }, | |
592a252b | 4583 | { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, |
c0f3af97 L |
4584 | }, |
4585 | ||
592a252b | 4586 | /* PREFIX_VEX_0F381C */ |
c0f3af97 | 4587 | { |
592d1631 L |
4588 | { Bad_Opcode }, |
4589 | { Bad_Opcode }, | |
6c30d220 | 4590 | { VEX_W_TABLE (VEX_W_0F381C_P_2) }, |
c0f3af97 L |
4591 | }, |
4592 | ||
592a252b | 4593 | /* PREFIX_VEX_0F381D */ |
c0f3af97 | 4594 | { |
592d1631 L |
4595 | { Bad_Opcode }, |
4596 | { Bad_Opcode }, | |
6c30d220 | 4597 | { VEX_W_TABLE (VEX_W_0F381D_P_2) }, |
c0f3af97 L |
4598 | }, |
4599 | ||
592a252b | 4600 | /* PREFIX_VEX_0F381E */ |
c0f3af97 | 4601 | { |
592d1631 L |
4602 | { Bad_Opcode }, |
4603 | { Bad_Opcode }, | |
6c30d220 | 4604 | { VEX_W_TABLE (VEX_W_0F381E_P_2) }, |
c0f3af97 L |
4605 | }, |
4606 | ||
592a252b | 4607 | /* PREFIX_VEX_0F3820 */ |
c0f3af97 | 4608 | { |
592d1631 L |
4609 | { Bad_Opcode }, |
4610 | { Bad_Opcode }, | |
6c30d220 | 4611 | { VEX_W_TABLE (VEX_W_0F3820_P_2) }, |
c0f3af97 L |
4612 | }, |
4613 | ||
592a252b | 4614 | /* PREFIX_VEX_0F3821 */ |
c0f3af97 | 4615 | { |
592d1631 L |
4616 | { Bad_Opcode }, |
4617 | { Bad_Opcode }, | |
6c30d220 | 4618 | { VEX_W_TABLE (VEX_W_0F3821_P_2) }, |
c0f3af97 L |
4619 | }, |
4620 | ||
592a252b | 4621 | /* PREFIX_VEX_0F3822 */ |
c0f3af97 | 4622 | { |
592d1631 L |
4623 | { Bad_Opcode }, |
4624 | { Bad_Opcode }, | |
6c30d220 | 4625 | { VEX_W_TABLE (VEX_W_0F3822_P_2) }, |
c0f3af97 L |
4626 | }, |
4627 | ||
592a252b | 4628 | /* PREFIX_VEX_0F3823 */ |
c0f3af97 | 4629 | { |
592d1631 L |
4630 | { Bad_Opcode }, |
4631 | { Bad_Opcode }, | |
6c30d220 | 4632 | { VEX_W_TABLE (VEX_W_0F3823_P_2) }, |
c0f3af97 L |
4633 | }, |
4634 | ||
592a252b | 4635 | /* PREFIX_VEX_0F3824 */ |
c0f3af97 | 4636 | { |
592d1631 L |
4637 | { Bad_Opcode }, |
4638 | { Bad_Opcode }, | |
6c30d220 | 4639 | { VEX_W_TABLE (VEX_W_0F3824_P_2) }, |
c0f3af97 L |
4640 | }, |
4641 | ||
592a252b | 4642 | /* PREFIX_VEX_0F3825 */ |
c0f3af97 | 4643 | { |
592d1631 L |
4644 | { Bad_Opcode }, |
4645 | { Bad_Opcode }, | |
6c30d220 | 4646 | { VEX_W_TABLE (VEX_W_0F3825_P_2) }, |
c0f3af97 L |
4647 | }, |
4648 | ||
592a252b | 4649 | /* PREFIX_VEX_0F3828 */ |
c0f3af97 | 4650 | { |
592d1631 L |
4651 | { Bad_Opcode }, |
4652 | { Bad_Opcode }, | |
6c30d220 | 4653 | { VEX_W_TABLE (VEX_W_0F3828_P_2) }, |
c0f3af97 L |
4654 | }, |
4655 | ||
592a252b | 4656 | /* PREFIX_VEX_0F3829 */ |
c0f3af97 | 4657 | { |
592d1631 L |
4658 | { Bad_Opcode }, |
4659 | { Bad_Opcode }, | |
6c30d220 | 4660 | { VEX_W_TABLE (VEX_W_0F3829_P_2) }, |
c0f3af97 L |
4661 | }, |
4662 | ||
592a252b | 4663 | /* PREFIX_VEX_0F382A */ |
c0f3af97 | 4664 | { |
592d1631 L |
4665 | { Bad_Opcode }, |
4666 | { Bad_Opcode }, | |
592a252b | 4667 | { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, |
c0f3af97 L |
4668 | }, |
4669 | ||
592a252b | 4670 | /* PREFIX_VEX_0F382B */ |
c0f3af97 | 4671 | { |
592d1631 L |
4672 | { Bad_Opcode }, |
4673 | { Bad_Opcode }, | |
6c30d220 | 4674 | { VEX_W_TABLE (VEX_W_0F382B_P_2) }, |
c0f3af97 L |
4675 | }, |
4676 | ||
592a252b | 4677 | /* PREFIX_VEX_0F382C */ |
c0f3af97 | 4678 | { |
592d1631 L |
4679 | { Bad_Opcode }, |
4680 | { Bad_Opcode }, | |
592a252b | 4681 | { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, |
c0f3af97 L |
4682 | }, |
4683 | ||
592a252b | 4684 | /* PREFIX_VEX_0F382D */ |
c0f3af97 | 4685 | { |
592d1631 L |
4686 | { Bad_Opcode }, |
4687 | { Bad_Opcode }, | |
592a252b | 4688 | { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, |
c0f3af97 L |
4689 | }, |
4690 | ||
592a252b | 4691 | /* PREFIX_VEX_0F382E */ |
c0f3af97 | 4692 | { |
592d1631 L |
4693 | { Bad_Opcode }, |
4694 | { Bad_Opcode }, | |
592a252b | 4695 | { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, |
c0f3af97 L |
4696 | }, |
4697 | ||
592a252b | 4698 | /* PREFIX_VEX_0F382F */ |
c0f3af97 | 4699 | { |
592d1631 L |
4700 | { Bad_Opcode }, |
4701 | { Bad_Opcode }, | |
592a252b | 4702 | { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, |
c0f3af97 L |
4703 | }, |
4704 | ||
592a252b | 4705 | /* PREFIX_VEX_0F3830 */ |
c0f3af97 | 4706 | { |
592d1631 L |
4707 | { Bad_Opcode }, |
4708 | { Bad_Opcode }, | |
6c30d220 | 4709 | { VEX_W_TABLE (VEX_W_0F3830_P_2) }, |
c0f3af97 L |
4710 | }, |
4711 | ||
592a252b | 4712 | /* PREFIX_VEX_0F3831 */ |
c0f3af97 | 4713 | { |
592d1631 L |
4714 | { Bad_Opcode }, |
4715 | { Bad_Opcode }, | |
6c30d220 | 4716 | { VEX_W_TABLE (VEX_W_0F3831_P_2) }, |
c0f3af97 L |
4717 | }, |
4718 | ||
592a252b | 4719 | /* PREFIX_VEX_0F3832 */ |
c0f3af97 | 4720 | { |
592d1631 L |
4721 | { Bad_Opcode }, |
4722 | { Bad_Opcode }, | |
6c30d220 | 4723 | { VEX_W_TABLE (VEX_W_0F3832_P_2) }, |
c0f3af97 L |
4724 | }, |
4725 | ||
592a252b | 4726 | /* PREFIX_VEX_0F3833 */ |
c0f3af97 | 4727 | { |
592d1631 L |
4728 | { Bad_Opcode }, |
4729 | { Bad_Opcode }, | |
6c30d220 | 4730 | { VEX_W_TABLE (VEX_W_0F3833_P_2) }, |
c0f3af97 L |
4731 | }, |
4732 | ||
592a252b | 4733 | /* PREFIX_VEX_0F3834 */ |
c0f3af97 | 4734 | { |
592d1631 L |
4735 | { Bad_Opcode }, |
4736 | { Bad_Opcode }, | |
6c30d220 | 4737 | { VEX_W_TABLE (VEX_W_0F3834_P_2) }, |
c0f3af97 L |
4738 | }, |
4739 | ||
592a252b | 4740 | /* PREFIX_VEX_0F3835 */ |
c0f3af97 | 4741 | { |
592d1631 L |
4742 | { Bad_Opcode }, |
4743 | { Bad_Opcode }, | |
6c30d220 L |
4744 | { VEX_W_TABLE (VEX_W_0F3835_P_2) }, |
4745 | }, | |
4746 | ||
4747 | /* PREFIX_VEX_0F3836 */ | |
4748 | { | |
4749 | { Bad_Opcode }, | |
4750 | { Bad_Opcode }, | |
4751 | { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) }, | |
c0f3af97 L |
4752 | }, |
4753 | ||
592a252b | 4754 | /* PREFIX_VEX_0F3837 */ |
c0f3af97 | 4755 | { |
592d1631 L |
4756 | { Bad_Opcode }, |
4757 | { Bad_Opcode }, | |
6c30d220 | 4758 | { VEX_W_TABLE (VEX_W_0F3837_P_2) }, |
c0f3af97 L |
4759 | }, |
4760 | ||
592a252b | 4761 | /* PREFIX_VEX_0F3838 */ |
c0f3af97 | 4762 | { |
592d1631 L |
4763 | { Bad_Opcode }, |
4764 | { Bad_Opcode }, | |
6c30d220 | 4765 | { VEX_W_TABLE (VEX_W_0F3838_P_2) }, |
c0f3af97 L |
4766 | }, |
4767 | ||
592a252b | 4768 | /* PREFIX_VEX_0F3839 */ |
c0f3af97 | 4769 | { |
592d1631 L |
4770 | { Bad_Opcode }, |
4771 | { Bad_Opcode }, | |
6c30d220 | 4772 | { VEX_W_TABLE (VEX_W_0F3839_P_2) }, |
c0f3af97 L |
4773 | }, |
4774 | ||
592a252b | 4775 | /* PREFIX_VEX_0F383A */ |
c0f3af97 | 4776 | { |
592d1631 L |
4777 | { Bad_Opcode }, |
4778 | { Bad_Opcode }, | |
6c30d220 | 4779 | { VEX_W_TABLE (VEX_W_0F383A_P_2) }, |
c0f3af97 L |
4780 | }, |
4781 | ||
592a252b | 4782 | /* PREFIX_VEX_0F383B */ |
c0f3af97 | 4783 | { |
592d1631 L |
4784 | { Bad_Opcode }, |
4785 | { Bad_Opcode }, | |
6c30d220 | 4786 | { VEX_W_TABLE (VEX_W_0F383B_P_2) }, |
c0f3af97 L |
4787 | }, |
4788 | ||
592a252b | 4789 | /* PREFIX_VEX_0F383C */ |
c0f3af97 | 4790 | { |
592d1631 L |
4791 | { Bad_Opcode }, |
4792 | { Bad_Opcode }, | |
6c30d220 | 4793 | { VEX_W_TABLE (VEX_W_0F383C_P_2) }, |
c0f3af97 L |
4794 | }, |
4795 | ||
592a252b | 4796 | /* PREFIX_VEX_0F383D */ |
c0f3af97 | 4797 | { |
592d1631 L |
4798 | { Bad_Opcode }, |
4799 | { Bad_Opcode }, | |
6c30d220 | 4800 | { VEX_W_TABLE (VEX_W_0F383D_P_2) }, |
c0f3af97 L |
4801 | }, |
4802 | ||
592a252b | 4803 | /* PREFIX_VEX_0F383E */ |
c0f3af97 | 4804 | { |
592d1631 L |
4805 | { Bad_Opcode }, |
4806 | { Bad_Opcode }, | |
6c30d220 | 4807 | { VEX_W_TABLE (VEX_W_0F383E_P_2) }, |
c0f3af97 L |
4808 | }, |
4809 | ||
592a252b | 4810 | /* PREFIX_VEX_0F383F */ |
c0f3af97 | 4811 | { |
592d1631 L |
4812 | { Bad_Opcode }, |
4813 | { Bad_Opcode }, | |
6c30d220 | 4814 | { VEX_W_TABLE (VEX_W_0F383F_P_2) }, |
c0f3af97 L |
4815 | }, |
4816 | ||
592a252b | 4817 | /* PREFIX_VEX_0F3840 */ |
c0f3af97 | 4818 | { |
592d1631 L |
4819 | { Bad_Opcode }, |
4820 | { Bad_Opcode }, | |
6c30d220 | 4821 | { VEX_W_TABLE (VEX_W_0F3840_P_2) }, |
c0f3af97 L |
4822 | }, |
4823 | ||
592a252b | 4824 | /* PREFIX_VEX_0F3841 */ |
c0f3af97 | 4825 | { |
592d1631 L |
4826 | { Bad_Opcode }, |
4827 | { Bad_Opcode }, | |
592a252b | 4828 | { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, |
c0f3af97 L |
4829 | }, |
4830 | ||
6c30d220 L |
4831 | /* PREFIX_VEX_0F3845 */ |
4832 | { | |
4833 | { Bad_Opcode }, | |
4834 | { Bad_Opcode }, | |
4835 | { "vpsrlv%LW", { XM, Vex, EXx } }, | |
4836 | }, | |
4837 | ||
4838 | /* PREFIX_VEX_0F3846 */ | |
4839 | { | |
4840 | { Bad_Opcode }, | |
4841 | { Bad_Opcode }, | |
4842 | { VEX_W_TABLE (VEX_W_0F3846_P_2) }, | |
4843 | }, | |
4844 | ||
4845 | /* PREFIX_VEX_0F3847 */ | |
4846 | { | |
4847 | { Bad_Opcode }, | |
4848 | { Bad_Opcode }, | |
4849 | { "vpsllv%LW", { XM, Vex, EXx } }, | |
4850 | }, | |
4851 | ||
4852 | /* PREFIX_VEX_0F3858 */ | |
4853 | { | |
4854 | { Bad_Opcode }, | |
4855 | { Bad_Opcode }, | |
4856 | { VEX_W_TABLE (VEX_W_0F3858_P_2) }, | |
4857 | }, | |
4858 | ||
4859 | /* PREFIX_VEX_0F3859 */ | |
4860 | { | |
4861 | { Bad_Opcode }, | |
4862 | { Bad_Opcode }, | |
4863 | { VEX_W_TABLE (VEX_W_0F3859_P_2) }, | |
4864 | }, | |
4865 | ||
4866 | /* PREFIX_VEX_0F385A */ | |
4867 | { | |
4868 | { Bad_Opcode }, | |
4869 | { Bad_Opcode }, | |
4870 | { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) }, | |
4871 | }, | |
4872 | ||
4873 | /* PREFIX_VEX_0F3878 */ | |
4874 | { | |
4875 | { Bad_Opcode }, | |
4876 | { Bad_Opcode }, | |
4877 | { VEX_W_TABLE (VEX_W_0F3878_P_2) }, | |
4878 | }, | |
4879 | ||
4880 | /* PREFIX_VEX_0F3879 */ | |
4881 | { | |
4882 | { Bad_Opcode }, | |
4883 | { Bad_Opcode }, | |
4884 | { VEX_W_TABLE (VEX_W_0F3879_P_2) }, | |
4885 | }, | |
4886 | ||
4887 | /* PREFIX_VEX_0F388C */ | |
4888 | { | |
4889 | { Bad_Opcode }, | |
4890 | { Bad_Opcode }, | |
f7002f42 | 4891 | { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) }, |
6c30d220 L |
4892 | }, |
4893 | ||
4894 | /* PREFIX_VEX_0F388E */ | |
4895 | { | |
4896 | { Bad_Opcode }, | |
4897 | { Bad_Opcode }, | |
f7002f42 | 4898 | { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) }, |
6c30d220 L |
4899 | }, |
4900 | ||
4901 | /* PREFIX_VEX_0F3890 */ | |
4902 | { | |
4903 | { Bad_Opcode }, | |
4904 | { Bad_Opcode }, | |
4905 | { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } }, | |
4906 | }, | |
4907 | ||
4908 | /* PREFIX_VEX_0F3891 */ | |
4909 | { | |
4910 | { Bad_Opcode }, | |
4911 | { Bad_Opcode }, | |
4912 | { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } }, | |
4913 | }, | |
4914 | ||
4915 | /* PREFIX_VEX_0F3892 */ | |
4916 | { | |
4917 | { Bad_Opcode }, | |
4918 | { Bad_Opcode }, | |
4919 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } }, | |
4920 | }, | |
4921 | ||
4922 | /* PREFIX_VEX_0F3893 */ | |
4923 | { | |
4924 | { Bad_Opcode }, | |
4925 | { Bad_Opcode }, | |
4926 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } }, | |
4927 | }, | |
4928 | ||
592a252b | 4929 | /* PREFIX_VEX_0F3896 */ |
a5ff0eb2 | 4930 | { |
592d1631 L |
4931 | { Bad_Opcode }, |
4932 | { Bad_Opcode }, | |
0bfee649 | 4933 | { "vfmaddsub132p%XW", { XM, Vex, EXx } }, |
a5ff0eb2 L |
4934 | }, |
4935 | ||
592a252b | 4936 | /* PREFIX_VEX_0F3897 */ |
a5ff0eb2 | 4937 | { |
592d1631 L |
4938 | { Bad_Opcode }, |
4939 | { Bad_Opcode }, | |
0bfee649 | 4940 | { "vfmsubadd132p%XW", { XM, Vex, EXx } }, |
a5ff0eb2 L |
4941 | }, |
4942 | ||
592a252b | 4943 | /* PREFIX_VEX_0F3898 */ |
a5ff0eb2 | 4944 | { |
592d1631 L |
4945 | { Bad_Opcode }, |
4946 | { Bad_Opcode }, | |
0bfee649 | 4947 | { "vfmadd132p%XW", { XM, Vex, EXx } }, |
a5ff0eb2 L |
4948 | }, |
4949 | ||
592a252b | 4950 | /* PREFIX_VEX_0F3899 */ |
a5ff0eb2 | 4951 | { |
592d1631 L |
4952 | { Bad_Opcode }, |
4953 | { Bad_Opcode }, | |
1c480963 | 4954 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
a5ff0eb2 L |
4955 | }, |
4956 | ||
592a252b | 4957 | /* PREFIX_VEX_0F389A */ |
a5ff0eb2 | 4958 | { |
592d1631 L |
4959 | { Bad_Opcode }, |
4960 | { Bad_Opcode }, | |
0bfee649 | 4961 | { "vfmsub132p%XW", { XM, Vex, EXx } }, |
a5ff0eb2 L |
4962 | }, |
4963 | ||
592a252b | 4964 | /* PREFIX_VEX_0F389B */ |
c0f3af97 | 4965 | { |
592d1631 L |
4966 | { Bad_Opcode }, |
4967 | { Bad_Opcode }, | |
1c480963 | 4968 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
4969 | }, |
4970 | ||
592a252b | 4971 | /* PREFIX_VEX_0F389C */ |
c0f3af97 | 4972 | { |
592d1631 L |
4973 | { Bad_Opcode }, |
4974 | { Bad_Opcode }, | |
0bfee649 | 4975 | { "vfnmadd132p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4976 | }, |
4977 | ||
592a252b | 4978 | /* PREFIX_VEX_0F389D */ |
c0f3af97 | 4979 | { |
592d1631 L |
4980 | { Bad_Opcode }, |
4981 | { Bad_Opcode }, | |
1c480963 | 4982 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
4983 | }, |
4984 | ||
592a252b | 4985 | /* PREFIX_VEX_0F389E */ |
c0f3af97 | 4986 | { |
592d1631 L |
4987 | { Bad_Opcode }, |
4988 | { Bad_Opcode }, | |
0bfee649 | 4989 | { "vfnmsub132p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
4990 | }, |
4991 | ||
592a252b | 4992 | /* PREFIX_VEX_0F389F */ |
c0f3af97 | 4993 | { |
592d1631 L |
4994 | { Bad_Opcode }, |
4995 | { Bad_Opcode }, | |
1c480963 | 4996 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
4997 | }, |
4998 | ||
592a252b | 4999 | /* PREFIX_VEX_0F38A6 */ |
c0f3af97 | 5000 | { |
592d1631 L |
5001 | { Bad_Opcode }, |
5002 | { Bad_Opcode }, | |
0bfee649 | 5003 | { "vfmaddsub213p%XW", { XM, Vex, EXx } }, |
592d1631 | 5004 | { Bad_Opcode }, |
c0f3af97 L |
5005 | }, |
5006 | ||
592a252b | 5007 | /* PREFIX_VEX_0F38A7 */ |
c0f3af97 | 5008 | { |
592d1631 L |
5009 | { Bad_Opcode }, |
5010 | { Bad_Opcode }, | |
0bfee649 | 5011 | { "vfmsubadd213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5012 | }, |
5013 | ||
592a252b | 5014 | /* PREFIX_VEX_0F38A8 */ |
c0f3af97 | 5015 | { |
592d1631 L |
5016 | { Bad_Opcode }, |
5017 | { Bad_Opcode }, | |
0bfee649 | 5018 | { "vfmadd213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5019 | }, |
5020 | ||
592a252b | 5021 | /* PREFIX_VEX_0F38A9 */ |
c0f3af97 | 5022 | { |
592d1631 L |
5023 | { Bad_Opcode }, |
5024 | { Bad_Opcode }, | |
1c480963 | 5025 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5026 | }, |
5027 | ||
592a252b | 5028 | /* PREFIX_VEX_0F38AA */ |
c0f3af97 | 5029 | { |
592d1631 L |
5030 | { Bad_Opcode }, |
5031 | { Bad_Opcode }, | |
0bfee649 | 5032 | { "vfmsub213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5033 | }, |
5034 | ||
592a252b | 5035 | /* PREFIX_VEX_0F38AB */ |
c0f3af97 | 5036 | { |
592d1631 L |
5037 | { Bad_Opcode }, |
5038 | { Bad_Opcode }, | |
1c480963 | 5039 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5040 | }, |
5041 | ||
592a252b | 5042 | /* PREFIX_VEX_0F38AC */ |
c0f3af97 | 5043 | { |
592d1631 L |
5044 | { Bad_Opcode }, |
5045 | { Bad_Opcode }, | |
0bfee649 | 5046 | { "vfnmadd213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5047 | }, |
5048 | ||
592a252b | 5049 | /* PREFIX_VEX_0F38AD */ |
c0f3af97 | 5050 | { |
592d1631 L |
5051 | { Bad_Opcode }, |
5052 | { Bad_Opcode }, | |
1c480963 | 5053 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5054 | }, |
5055 | ||
592a252b | 5056 | /* PREFIX_VEX_0F38AE */ |
c0f3af97 | 5057 | { |
592d1631 L |
5058 | { Bad_Opcode }, |
5059 | { Bad_Opcode }, | |
0bfee649 | 5060 | { "vfnmsub213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5061 | }, |
5062 | ||
592a252b | 5063 | /* PREFIX_VEX_0F38AF */ |
c0f3af97 | 5064 | { |
592d1631 L |
5065 | { Bad_Opcode }, |
5066 | { Bad_Opcode }, | |
1c480963 | 5067 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5068 | }, |
5069 | ||
592a252b | 5070 | /* PREFIX_VEX_0F38B6 */ |
c0f3af97 | 5071 | { |
592d1631 L |
5072 | { Bad_Opcode }, |
5073 | { Bad_Opcode }, | |
0bfee649 | 5074 | { "vfmaddsub231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5075 | }, |
5076 | ||
592a252b | 5077 | /* PREFIX_VEX_0F38B7 */ |
c0f3af97 | 5078 | { |
592d1631 L |
5079 | { Bad_Opcode }, |
5080 | { Bad_Opcode }, | |
0bfee649 | 5081 | { "vfmsubadd231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5082 | }, |
5083 | ||
592a252b | 5084 | /* PREFIX_VEX_0F38B8 */ |
c0f3af97 | 5085 | { |
592d1631 L |
5086 | { Bad_Opcode }, |
5087 | { Bad_Opcode }, | |
0bfee649 | 5088 | { "vfmadd231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5089 | }, |
5090 | ||
592a252b | 5091 | /* PREFIX_VEX_0F38B9 */ |
c0f3af97 | 5092 | { |
592d1631 L |
5093 | { Bad_Opcode }, |
5094 | { Bad_Opcode }, | |
1c480963 | 5095 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5096 | }, |
5097 | ||
592a252b | 5098 | /* PREFIX_VEX_0F38BA */ |
c0f3af97 | 5099 | { |
592d1631 L |
5100 | { Bad_Opcode }, |
5101 | { Bad_Opcode }, | |
0bfee649 | 5102 | { "vfmsub231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5103 | }, |
5104 | ||
592a252b | 5105 | /* PREFIX_VEX_0F38BB */ |
c0f3af97 | 5106 | { |
592d1631 L |
5107 | { Bad_Opcode }, |
5108 | { Bad_Opcode }, | |
1c480963 | 5109 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5110 | }, |
5111 | ||
592a252b | 5112 | /* PREFIX_VEX_0F38BC */ |
c0f3af97 | 5113 | { |
592d1631 L |
5114 | { Bad_Opcode }, |
5115 | { Bad_Opcode }, | |
0bfee649 | 5116 | { "vfnmadd231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5117 | }, |
5118 | ||
592a252b | 5119 | /* PREFIX_VEX_0F38BD */ |
c0f3af97 | 5120 | { |
592d1631 L |
5121 | { Bad_Opcode }, |
5122 | { Bad_Opcode }, | |
1c480963 | 5123 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5124 | }, |
5125 | ||
592a252b | 5126 | /* PREFIX_VEX_0F38BE */ |
c0f3af97 | 5127 | { |
592d1631 L |
5128 | { Bad_Opcode }, |
5129 | { Bad_Opcode }, | |
0bfee649 | 5130 | { "vfnmsub231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5131 | }, |
5132 | ||
592a252b | 5133 | /* PREFIX_VEX_0F38BF */ |
c0f3af97 | 5134 | { |
592d1631 L |
5135 | { Bad_Opcode }, |
5136 | { Bad_Opcode }, | |
1c480963 | 5137 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5138 | }, |
5139 | ||
592a252b | 5140 | /* PREFIX_VEX_0F38DB */ |
c0f3af97 | 5141 | { |
592d1631 L |
5142 | { Bad_Opcode }, |
5143 | { Bad_Opcode }, | |
592a252b | 5144 | { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, |
c0f3af97 L |
5145 | }, |
5146 | ||
592a252b | 5147 | /* PREFIX_VEX_0F38DC */ |
c0f3af97 | 5148 | { |
592d1631 L |
5149 | { Bad_Opcode }, |
5150 | { Bad_Opcode }, | |
592a252b | 5151 | { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) }, |
c0f3af97 L |
5152 | }, |
5153 | ||
592a252b | 5154 | /* PREFIX_VEX_0F38DD */ |
c0f3af97 | 5155 | { |
592d1631 L |
5156 | { Bad_Opcode }, |
5157 | { Bad_Opcode }, | |
592a252b | 5158 | { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) }, |
c0f3af97 L |
5159 | }, |
5160 | ||
592a252b | 5161 | /* PREFIX_VEX_0F38DE */ |
c0f3af97 | 5162 | { |
592d1631 L |
5163 | { Bad_Opcode }, |
5164 | { Bad_Opcode }, | |
592a252b | 5165 | { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) }, |
c0f3af97 L |
5166 | }, |
5167 | ||
592a252b | 5168 | /* PREFIX_VEX_0F38DF */ |
c0f3af97 | 5169 | { |
592d1631 L |
5170 | { Bad_Opcode }, |
5171 | { Bad_Opcode }, | |
592a252b | 5172 | { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) }, |
c0f3af97 L |
5173 | }, |
5174 | ||
f12dc422 L |
5175 | /* PREFIX_VEX_0F38F2 */ |
5176 | { | |
5177 | { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, | |
5178 | }, | |
5179 | ||
5180 | /* PREFIX_VEX_0F38F3_REG_1 */ | |
5181 | { | |
5182 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, | |
5183 | }, | |
5184 | ||
5185 | /* PREFIX_VEX_0F38F3_REG_2 */ | |
5186 | { | |
5187 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, | |
5188 | }, | |
5189 | ||
5190 | /* PREFIX_VEX_0F38F3_REG_3 */ | |
5191 | { | |
5192 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, | |
5193 | }, | |
5194 | ||
6c30d220 L |
5195 | /* PREFIX_VEX_0F38F5 */ |
5196 | { | |
5197 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, | |
5198 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, | |
5199 | { Bad_Opcode }, | |
5200 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, | |
5201 | }, | |
5202 | ||
5203 | /* PREFIX_VEX_0F38F6 */ | |
5204 | { | |
5205 | { Bad_Opcode }, | |
5206 | { Bad_Opcode }, | |
5207 | { Bad_Opcode }, | |
5208 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, | |
5209 | }, | |
5210 | ||
f12dc422 L |
5211 | /* PREFIX_VEX_0F38F7 */ |
5212 | { | |
5213 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, | |
6c30d220 L |
5214 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, |
5215 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, | |
5216 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, | |
5217 | }, | |
5218 | ||
5219 | /* PREFIX_VEX_0F3A00 */ | |
5220 | { | |
5221 | { Bad_Opcode }, | |
5222 | { Bad_Opcode }, | |
5223 | { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) }, | |
5224 | }, | |
5225 | ||
5226 | /* PREFIX_VEX_0F3A01 */ | |
5227 | { | |
5228 | { Bad_Opcode }, | |
5229 | { Bad_Opcode }, | |
5230 | { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) }, | |
5231 | }, | |
5232 | ||
5233 | /* PREFIX_VEX_0F3A02 */ | |
5234 | { | |
5235 | { Bad_Opcode }, | |
5236 | { Bad_Opcode }, | |
5237 | { VEX_W_TABLE (VEX_W_0F3A02_P_2) }, | |
f12dc422 L |
5238 | }, |
5239 | ||
592a252b | 5240 | /* PREFIX_VEX_0F3A04 */ |
c0f3af97 | 5241 | { |
592d1631 L |
5242 | { Bad_Opcode }, |
5243 | { Bad_Opcode }, | |
592a252b | 5244 | { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, |
c0f3af97 L |
5245 | }, |
5246 | ||
592a252b | 5247 | /* PREFIX_VEX_0F3A05 */ |
c0f3af97 | 5248 | { |
592d1631 L |
5249 | { Bad_Opcode }, |
5250 | { Bad_Opcode }, | |
592a252b | 5251 | { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, |
c0f3af97 L |
5252 | }, |
5253 | ||
592a252b | 5254 | /* PREFIX_VEX_0F3A06 */ |
c0f3af97 | 5255 | { |
592d1631 L |
5256 | { Bad_Opcode }, |
5257 | { Bad_Opcode }, | |
592a252b | 5258 | { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, |
c0f3af97 L |
5259 | }, |
5260 | ||
592a252b | 5261 | /* PREFIX_VEX_0F3A08 */ |
c0f3af97 | 5262 | { |
592d1631 L |
5263 | { Bad_Opcode }, |
5264 | { Bad_Opcode }, | |
592a252b | 5265 | { VEX_W_TABLE (VEX_W_0F3A08_P_2) }, |
c0f3af97 L |
5266 | }, |
5267 | ||
592a252b | 5268 | /* PREFIX_VEX_0F3A09 */ |
c0f3af97 | 5269 | { |
592d1631 L |
5270 | { Bad_Opcode }, |
5271 | { Bad_Opcode }, | |
592a252b | 5272 | { VEX_W_TABLE (VEX_W_0F3A09_P_2) }, |
c0f3af97 L |
5273 | }, |
5274 | ||
592a252b | 5275 | /* PREFIX_VEX_0F3A0A */ |
c0f3af97 | 5276 | { |
592d1631 L |
5277 | { Bad_Opcode }, |
5278 | { Bad_Opcode }, | |
592a252b | 5279 | { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) }, |
0bfee649 L |
5280 | }, |
5281 | ||
592a252b | 5282 | /* PREFIX_VEX_0F3A0B */ |
0bfee649 | 5283 | { |
592d1631 L |
5284 | { Bad_Opcode }, |
5285 | { Bad_Opcode }, | |
592a252b | 5286 | { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) }, |
0bfee649 L |
5287 | }, |
5288 | ||
592a252b | 5289 | /* PREFIX_VEX_0F3A0C */ |
0bfee649 | 5290 | { |
592d1631 L |
5291 | { Bad_Opcode }, |
5292 | { Bad_Opcode }, | |
592a252b | 5293 | { VEX_W_TABLE (VEX_W_0F3A0C_P_2) }, |
0bfee649 L |
5294 | }, |
5295 | ||
592a252b | 5296 | /* PREFIX_VEX_0F3A0D */ |
0bfee649 | 5297 | { |
592d1631 L |
5298 | { Bad_Opcode }, |
5299 | { Bad_Opcode }, | |
592a252b | 5300 | { VEX_W_TABLE (VEX_W_0F3A0D_P_2) }, |
c0f3af97 L |
5301 | }, |
5302 | ||
592a252b | 5303 | /* PREFIX_VEX_0F3A0E */ |
0bfee649 | 5304 | { |
592d1631 L |
5305 | { Bad_Opcode }, |
5306 | { Bad_Opcode }, | |
6c30d220 | 5307 | { VEX_W_TABLE (VEX_W_0F3A0E_P_2) }, |
0bfee649 L |
5308 | }, |
5309 | ||
592a252b | 5310 | /* PREFIX_VEX_0F3A0F */ |
0bfee649 | 5311 | { |
592d1631 L |
5312 | { Bad_Opcode }, |
5313 | { Bad_Opcode }, | |
6c30d220 | 5314 | { VEX_W_TABLE (VEX_W_0F3A0F_P_2) }, |
0bfee649 L |
5315 | }, |
5316 | ||
592a252b | 5317 | /* PREFIX_VEX_0F3A14 */ |
0bfee649 | 5318 | { |
592d1631 L |
5319 | { Bad_Opcode }, |
5320 | { Bad_Opcode }, | |
592a252b | 5321 | { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, |
0bfee649 L |
5322 | }, |
5323 | ||
592a252b | 5324 | /* PREFIX_VEX_0F3A15 */ |
0bfee649 | 5325 | { |
592d1631 L |
5326 | { Bad_Opcode }, |
5327 | { Bad_Opcode }, | |
592a252b | 5328 | { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, |
0bfee649 L |
5329 | }, |
5330 | ||
592a252b | 5331 | /* PREFIX_VEX_0F3A16 */ |
c0f3af97 | 5332 | { |
592d1631 L |
5333 | { Bad_Opcode }, |
5334 | { Bad_Opcode }, | |
592a252b | 5335 | { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, |
c0f3af97 L |
5336 | }, |
5337 | ||
592a252b | 5338 | /* PREFIX_VEX_0F3A17 */ |
c0f3af97 | 5339 | { |
592d1631 L |
5340 | { Bad_Opcode }, |
5341 | { Bad_Opcode }, | |
592a252b | 5342 | { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, |
c0f3af97 L |
5343 | }, |
5344 | ||
592a252b | 5345 | /* PREFIX_VEX_0F3A18 */ |
c0f3af97 | 5346 | { |
592d1631 L |
5347 | { Bad_Opcode }, |
5348 | { Bad_Opcode }, | |
592a252b | 5349 | { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, |
c0f3af97 L |
5350 | }, |
5351 | ||
592a252b | 5352 | /* PREFIX_VEX_0F3A19 */ |
c0f3af97 | 5353 | { |
592d1631 L |
5354 | { Bad_Opcode }, |
5355 | { Bad_Opcode }, | |
592a252b | 5356 | { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, |
c0f3af97 L |
5357 | }, |
5358 | ||
592a252b | 5359 | /* PREFIX_VEX_0F3A1D */ |
c7b8aa3a L |
5360 | { |
5361 | { Bad_Opcode }, | |
5362 | { Bad_Opcode }, | |
5363 | { "vcvtps2ph", { EXxmmq, XM, Ib } }, | |
5364 | }, | |
5365 | ||
592a252b | 5366 | /* PREFIX_VEX_0F3A20 */ |
c0f3af97 | 5367 | { |
592d1631 L |
5368 | { Bad_Opcode }, |
5369 | { Bad_Opcode }, | |
592a252b | 5370 | { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, |
c0f3af97 L |
5371 | }, |
5372 | ||
592a252b | 5373 | /* PREFIX_VEX_0F3A21 */ |
c0f3af97 | 5374 | { |
592d1631 L |
5375 | { Bad_Opcode }, |
5376 | { Bad_Opcode }, | |
592a252b | 5377 | { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, |
c0f3af97 L |
5378 | }, |
5379 | ||
592a252b | 5380 | /* PREFIX_VEX_0F3A22 */ |
0bfee649 | 5381 | { |
592d1631 L |
5382 | { Bad_Opcode }, |
5383 | { Bad_Opcode }, | |
592a252b | 5384 | { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, |
0bfee649 L |
5385 | }, |
5386 | ||
6c30d220 L |
5387 | /* PREFIX_VEX_0F3A38 */ |
5388 | { | |
5389 | { Bad_Opcode }, | |
5390 | { Bad_Opcode }, | |
5391 | { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) }, | |
5392 | }, | |
5393 | ||
5394 | /* PREFIX_VEX_0F3A39 */ | |
5395 | { | |
5396 | { Bad_Opcode }, | |
5397 | { Bad_Opcode }, | |
5398 | { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) }, | |
5399 | }, | |
5400 | ||
592a252b | 5401 | /* PREFIX_VEX_0F3A40 */ |
c0f3af97 | 5402 | { |
592d1631 L |
5403 | { Bad_Opcode }, |
5404 | { Bad_Opcode }, | |
592a252b | 5405 | { VEX_W_TABLE (VEX_W_0F3A40_P_2) }, |
c0f3af97 L |
5406 | }, |
5407 | ||
592a252b | 5408 | /* PREFIX_VEX_0F3A41 */ |
c0f3af97 | 5409 | { |
592d1631 L |
5410 | { Bad_Opcode }, |
5411 | { Bad_Opcode }, | |
592a252b | 5412 | { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, |
c0f3af97 L |
5413 | }, |
5414 | ||
592a252b | 5415 | /* PREFIX_VEX_0F3A42 */ |
c0f3af97 | 5416 | { |
592d1631 L |
5417 | { Bad_Opcode }, |
5418 | { Bad_Opcode }, | |
6c30d220 | 5419 | { VEX_W_TABLE (VEX_W_0F3A42_P_2) }, |
c0f3af97 L |
5420 | }, |
5421 | ||
592a252b | 5422 | /* PREFIX_VEX_0F3A44 */ |
ce2f5b3c | 5423 | { |
592d1631 L |
5424 | { Bad_Opcode }, |
5425 | { Bad_Opcode }, | |
592a252b | 5426 | { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) }, |
ce2f5b3c L |
5427 | }, |
5428 | ||
6c30d220 L |
5429 | /* PREFIX_VEX_0F3A46 */ |
5430 | { | |
5431 | { Bad_Opcode }, | |
5432 | { Bad_Opcode }, | |
5433 | { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) }, | |
5434 | }, | |
5435 | ||
592a252b | 5436 | /* PREFIX_VEX_0F3A48 */ |
a683cc34 SP |
5437 | { |
5438 | { Bad_Opcode }, | |
5439 | { Bad_Opcode }, | |
592a252b | 5440 | { VEX_W_TABLE (VEX_W_0F3A48_P_2) }, |
a683cc34 SP |
5441 | }, |
5442 | ||
592a252b | 5443 | /* PREFIX_VEX_0F3A49 */ |
a683cc34 SP |
5444 | { |
5445 | { Bad_Opcode }, | |
5446 | { Bad_Opcode }, | |
592a252b | 5447 | { VEX_W_TABLE (VEX_W_0F3A49_P_2) }, |
a683cc34 SP |
5448 | }, |
5449 | ||
592a252b | 5450 | /* PREFIX_VEX_0F3A4A */ |
c0f3af97 | 5451 | { |
592d1631 L |
5452 | { Bad_Opcode }, |
5453 | { Bad_Opcode }, | |
592a252b | 5454 | { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, |
c0f3af97 L |
5455 | }, |
5456 | ||
592a252b | 5457 | /* PREFIX_VEX_0F3A4B */ |
c0f3af97 | 5458 | { |
592d1631 L |
5459 | { Bad_Opcode }, |
5460 | { Bad_Opcode }, | |
592a252b | 5461 | { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, |
c0f3af97 L |
5462 | }, |
5463 | ||
592a252b | 5464 | /* PREFIX_VEX_0F3A4C */ |
c0f3af97 | 5465 | { |
592d1631 L |
5466 | { Bad_Opcode }, |
5467 | { Bad_Opcode }, | |
6c30d220 | 5468 | { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, |
c0f3af97 L |
5469 | }, |
5470 | ||
592a252b | 5471 | /* PREFIX_VEX_0F3A5C */ |
922d8de8 | 5472 | { |
592d1631 L |
5473 | { Bad_Opcode }, |
5474 | { Bad_Opcode }, | |
206c2556 | 5475 | { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
5476 | }, |
5477 | ||
592a252b | 5478 | /* PREFIX_VEX_0F3A5D */ |
922d8de8 | 5479 | { |
592d1631 L |
5480 | { Bad_Opcode }, |
5481 | { Bad_Opcode }, | |
206c2556 | 5482 | { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
5483 | }, |
5484 | ||
592a252b | 5485 | /* PREFIX_VEX_0F3A5E */ |
922d8de8 | 5486 | { |
592d1631 L |
5487 | { Bad_Opcode }, |
5488 | { Bad_Opcode }, | |
206c2556 | 5489 | { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
5490 | }, |
5491 | ||
592a252b | 5492 | /* PREFIX_VEX_0F3A5F */ |
922d8de8 | 5493 | { |
592d1631 L |
5494 | { Bad_Opcode }, |
5495 | { Bad_Opcode }, | |
206c2556 | 5496 | { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
5497 | }, |
5498 | ||
592a252b | 5499 | /* PREFIX_VEX_0F3A60 */ |
c0f3af97 | 5500 | { |
592d1631 L |
5501 | { Bad_Opcode }, |
5502 | { Bad_Opcode }, | |
592a252b | 5503 | { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, |
592d1631 | 5504 | { Bad_Opcode }, |
c0f3af97 L |
5505 | }, |
5506 | ||
592a252b | 5507 | /* PREFIX_VEX_0F3A61 */ |
c0f3af97 | 5508 | { |
592d1631 L |
5509 | { Bad_Opcode }, |
5510 | { Bad_Opcode }, | |
592a252b | 5511 | { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, |
c0f3af97 L |
5512 | }, |
5513 | ||
592a252b | 5514 | /* PREFIX_VEX_0F3A62 */ |
c0f3af97 | 5515 | { |
592d1631 L |
5516 | { Bad_Opcode }, |
5517 | { Bad_Opcode }, | |
592a252b | 5518 | { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, |
c0f3af97 L |
5519 | }, |
5520 | ||
592a252b | 5521 | /* PREFIX_VEX_0F3A63 */ |
c0f3af97 | 5522 | { |
592d1631 L |
5523 | { Bad_Opcode }, |
5524 | { Bad_Opcode }, | |
592a252b | 5525 | { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, |
c0f3af97 | 5526 | }, |
a5ff0eb2 | 5527 | |
592a252b | 5528 | /* PREFIX_VEX_0F3A68 */ |
922d8de8 | 5529 | { |
592d1631 L |
5530 | { Bad_Opcode }, |
5531 | { Bad_Opcode }, | |
206c2556 | 5532 | { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
5533 | }, |
5534 | ||
592a252b | 5535 | /* PREFIX_VEX_0F3A69 */ |
922d8de8 | 5536 | { |
592d1631 L |
5537 | { Bad_Opcode }, |
5538 | { Bad_Opcode }, | |
206c2556 | 5539 | { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
5540 | }, |
5541 | ||
592a252b | 5542 | /* PREFIX_VEX_0F3A6A */ |
922d8de8 | 5543 | { |
592d1631 L |
5544 | { Bad_Opcode }, |
5545 | { Bad_Opcode }, | |
592a252b | 5546 | { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) }, |
922d8de8 DR |
5547 | }, |
5548 | ||
592a252b | 5549 | /* PREFIX_VEX_0F3A6B */ |
922d8de8 | 5550 | { |
592d1631 L |
5551 | { Bad_Opcode }, |
5552 | { Bad_Opcode }, | |
592a252b | 5553 | { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) }, |
922d8de8 DR |
5554 | }, |
5555 | ||
592a252b | 5556 | /* PREFIX_VEX_0F3A6C */ |
922d8de8 | 5557 | { |
592d1631 L |
5558 | { Bad_Opcode }, |
5559 | { Bad_Opcode }, | |
206c2556 | 5560 | { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
5561 | }, |
5562 | ||
592a252b | 5563 | /* PREFIX_VEX_0F3A6D */ |
922d8de8 | 5564 | { |
592d1631 L |
5565 | { Bad_Opcode }, |
5566 | { Bad_Opcode }, | |
206c2556 | 5567 | { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
5568 | }, |
5569 | ||
592a252b | 5570 | /* PREFIX_VEX_0F3A6E */ |
922d8de8 | 5571 | { |
592d1631 L |
5572 | { Bad_Opcode }, |
5573 | { Bad_Opcode }, | |
592a252b | 5574 | { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) }, |
922d8de8 DR |
5575 | }, |
5576 | ||
592a252b | 5577 | /* PREFIX_VEX_0F3A6F */ |
922d8de8 | 5578 | { |
592d1631 L |
5579 | { Bad_Opcode }, |
5580 | { Bad_Opcode }, | |
592a252b | 5581 | { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) }, |
922d8de8 DR |
5582 | }, |
5583 | ||
592a252b | 5584 | /* PREFIX_VEX_0F3A78 */ |
922d8de8 | 5585 | { |
592d1631 L |
5586 | { Bad_Opcode }, |
5587 | { Bad_Opcode }, | |
206c2556 | 5588 | { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
5589 | }, |
5590 | ||
592a252b | 5591 | /* PREFIX_VEX_0F3A79 */ |
922d8de8 | 5592 | { |
592d1631 L |
5593 | { Bad_Opcode }, |
5594 | { Bad_Opcode }, | |
206c2556 | 5595 | { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
5596 | }, |
5597 | ||
592a252b | 5598 | /* PREFIX_VEX_0F3A7A */ |
922d8de8 | 5599 | { |
592d1631 L |
5600 | { Bad_Opcode }, |
5601 | { Bad_Opcode }, | |
592a252b | 5602 | { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) }, |
922d8de8 DR |
5603 | }, |
5604 | ||
592a252b | 5605 | /* PREFIX_VEX_0F3A7B */ |
922d8de8 | 5606 | { |
592d1631 L |
5607 | { Bad_Opcode }, |
5608 | { Bad_Opcode }, | |
592a252b | 5609 | { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) }, |
922d8de8 DR |
5610 | }, |
5611 | ||
592a252b | 5612 | /* PREFIX_VEX_0F3A7C */ |
922d8de8 | 5613 | { |
592d1631 L |
5614 | { Bad_Opcode }, |
5615 | { Bad_Opcode }, | |
206c2556 | 5616 | { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
592d1631 | 5617 | { Bad_Opcode }, |
922d8de8 DR |
5618 | }, |
5619 | ||
592a252b | 5620 | /* PREFIX_VEX_0F3A7D */ |
922d8de8 | 5621 | { |
592d1631 L |
5622 | { Bad_Opcode }, |
5623 | { Bad_Opcode }, | |
206c2556 | 5624 | { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
5625 | }, |
5626 | ||
592a252b | 5627 | /* PREFIX_VEX_0F3A7E */ |
922d8de8 | 5628 | { |
592d1631 L |
5629 | { Bad_Opcode }, |
5630 | { Bad_Opcode }, | |
592a252b | 5631 | { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) }, |
922d8de8 DR |
5632 | }, |
5633 | ||
592a252b | 5634 | /* PREFIX_VEX_0F3A7F */ |
922d8de8 | 5635 | { |
592d1631 L |
5636 | { Bad_Opcode }, |
5637 | { Bad_Opcode }, | |
592a252b | 5638 | { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) }, |
922d8de8 DR |
5639 | }, |
5640 | ||
592a252b | 5641 | /* PREFIX_VEX_0F3ADF */ |
a5ff0eb2 | 5642 | { |
592d1631 L |
5643 | { Bad_Opcode }, |
5644 | { Bad_Opcode }, | |
592a252b | 5645 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, |
a5ff0eb2 | 5646 | }, |
6c30d220 L |
5647 | |
5648 | /* PREFIX_VEX_0F3AF0 */ | |
5649 | { | |
5650 | { Bad_Opcode }, | |
5651 | { Bad_Opcode }, | |
5652 | { Bad_Opcode }, | |
5653 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, | |
5654 | }, | |
c0f3af97 L |
5655 | }; |
5656 | ||
5657 | static const struct dis386 x86_64_table[][2] = { | |
5658 | /* X86_64_06 */ | |
5659 | { | |
d9e3625e | 5660 | { "pushP", { es } }, |
c0f3af97 L |
5661 | }, |
5662 | ||
5663 | /* X86_64_07 */ | |
5664 | { | |
d9e3625e | 5665 | { "popP", { es } }, |
c0f3af97 L |
5666 | }, |
5667 | ||
5668 | /* X86_64_0D */ | |
5669 | { | |
d9e3625e | 5670 | { "pushP", { cs } }, |
c0f3af97 L |
5671 | }, |
5672 | ||
5673 | /* X86_64_16 */ | |
5674 | { | |
d9e3625e | 5675 | { "pushP", { ss } }, |
c0f3af97 L |
5676 | }, |
5677 | ||
5678 | /* X86_64_17 */ | |
5679 | { | |
d9e3625e | 5680 | { "popP", { ss } }, |
c0f3af97 L |
5681 | }, |
5682 | ||
5683 | /* X86_64_1E */ | |
5684 | { | |
d9e3625e | 5685 | { "pushP", { ds } }, |
c0f3af97 L |
5686 | }, |
5687 | ||
5688 | /* X86_64_1F */ | |
5689 | { | |
d9e3625e | 5690 | { "popP", { ds } }, |
c0f3af97 L |
5691 | }, |
5692 | ||
5693 | /* X86_64_27 */ | |
5694 | { | |
5695 | { "daa", { XX } }, | |
c0f3af97 L |
5696 | }, |
5697 | ||
5698 | /* X86_64_2F */ | |
5699 | { | |
5700 | { "das", { XX } }, | |
c0f3af97 L |
5701 | }, |
5702 | ||
5703 | /* X86_64_37 */ | |
5704 | { | |
5705 | { "aaa", { XX } }, | |
c0f3af97 L |
5706 | }, |
5707 | ||
5708 | /* X86_64_3F */ | |
5709 | { | |
5710 | { "aas", { XX } }, | |
c0f3af97 L |
5711 | }, |
5712 | ||
5713 | /* X86_64_60 */ | |
5714 | { | |
d9e3625e | 5715 | { "pushaP", { XX } }, |
c0f3af97 L |
5716 | }, |
5717 | ||
5718 | /* X86_64_61 */ | |
5719 | { | |
d9e3625e | 5720 | { "popaP", { XX } }, |
c0f3af97 L |
5721 | }, |
5722 | ||
5723 | /* X86_64_62 */ | |
5724 | { | |
5725 | { MOD_TABLE (MOD_62_32BIT) }, | |
c0f3af97 L |
5726 | }, |
5727 | ||
5728 | /* X86_64_63 */ | |
5729 | { | |
5730 | { "arpl", { Ew, Gw } }, | |
5731 | { "movs{lq|xd}", { Gv, Ed } }, | |
5732 | }, | |
5733 | ||
5734 | /* X86_64_6D */ | |
5735 | { | |
5736 | { "ins{R|}", { Yzr, indirDX } }, | |
5737 | { "ins{G|}", { Yzr, indirDX } }, | |
5738 | }, | |
5739 | ||
5740 | /* X86_64_6F */ | |
5741 | { | |
5742 | { "outs{R|}", { indirDXr, Xz } }, | |
5743 | { "outs{G|}", { indirDXr, Xz } }, | |
5744 | }, | |
5745 | ||
5746 | /* X86_64_9A */ | |
5747 | { | |
5748 | { "Jcall{T|}", { Ap } }, | |
c0f3af97 L |
5749 | }, |
5750 | ||
5751 | /* X86_64_C4 */ | |
5752 | { | |
5753 | { MOD_TABLE (MOD_C4_32BIT) }, | |
5754 | { VEX_C4_TABLE (VEX_0F) }, | |
5755 | }, | |
5756 | ||
5757 | /* X86_64_C5 */ | |
5758 | { | |
5759 | { MOD_TABLE (MOD_C5_32BIT) }, | |
5760 | { VEX_C5_TABLE (VEX_0F) }, | |
5761 | }, | |
5762 | ||
5763 | /* X86_64_CE */ | |
5764 | { | |
5765 | { "into", { XX } }, | |
c0f3af97 L |
5766 | }, |
5767 | ||
5768 | /* X86_64_D4 */ | |
5769 | { | |
e3949f17 | 5770 | { "aam", { Ib } }, |
c0f3af97 L |
5771 | }, |
5772 | ||
5773 | /* X86_64_D5 */ | |
5774 | { | |
e3949f17 | 5775 | { "aad", { Ib } }, |
c0f3af97 L |
5776 | }, |
5777 | ||
5778 | /* X86_64_EA */ | |
5779 | { | |
5780 | { "Jjmp{T|}", { Ap } }, | |
c0f3af97 L |
5781 | }, |
5782 | ||
5783 | /* X86_64_0F01_REG_0 */ | |
5784 | { | |
5785 | { "sgdt{Q|IQ}", { M } }, | |
5786 | { "sgdt", { M } }, | |
5787 | }, | |
5788 | ||
5789 | /* X86_64_0F01_REG_1 */ | |
5790 | { | |
5791 | { "sidt{Q|IQ}", { M } }, | |
5792 | { "sidt", { M } }, | |
5793 | }, | |
5794 | ||
5795 | /* X86_64_0F01_REG_2 */ | |
5796 | { | |
5797 | { "lgdt{Q|Q}", { M } }, | |
5798 | { "lgdt", { M } }, | |
5799 | }, | |
5800 | ||
5801 | /* X86_64_0F01_REG_3 */ | |
5802 | { | |
5803 | { "lidt{Q|Q}", { M } }, | |
5804 | { "lidt", { M } }, | |
5805 | }, | |
5806 | }; | |
5807 | ||
5808 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
5809 | |
5810 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
5811 | { |
5812 | /* 00 */ | |
c1e679ec DR |
5813 | { "pshufb", { MX, EM } }, |
5814 | { "phaddw", { MX, EM } }, | |
5815 | { "phaddd", { MX, EM } }, | |
5816 | { "phaddsw", { MX, EM } }, | |
5817 | { "pmaddubsw", { MX, EM } }, | |
5818 | { "phsubw", { MX, EM } }, | |
5819 | { "phsubd", { MX, EM } }, | |
5820 | { "phsubsw", { MX, EM } }, | |
c0f3af97 | 5821 | /* 08 */ |
c1e679ec DR |
5822 | { "psignb", { MX, EM } }, |
5823 | { "psignw", { MX, EM } }, | |
5824 | { "psignd", { MX, EM } }, | |
5825 | { "pmulhrsw", { MX, EM } }, | |
592d1631 L |
5826 | { Bad_Opcode }, |
5827 | { Bad_Opcode }, | |
5828 | { Bad_Opcode }, | |
5829 | { Bad_Opcode }, | |
f88c9eb0 SP |
5830 | /* 10 */ |
5831 | { PREFIX_TABLE (PREFIX_0F3810) }, | |
592d1631 L |
5832 | { Bad_Opcode }, |
5833 | { Bad_Opcode }, | |
5834 | { Bad_Opcode }, | |
f88c9eb0 SP |
5835 | { PREFIX_TABLE (PREFIX_0F3814) }, |
5836 | { PREFIX_TABLE (PREFIX_0F3815) }, | |
592d1631 | 5837 | { Bad_Opcode }, |
f88c9eb0 SP |
5838 | { PREFIX_TABLE (PREFIX_0F3817) }, |
5839 | /* 18 */ | |
592d1631 L |
5840 | { Bad_Opcode }, |
5841 | { Bad_Opcode }, | |
5842 | { Bad_Opcode }, | |
5843 | { Bad_Opcode }, | |
f88c9eb0 SP |
5844 | { "pabsb", { MX, EM } }, |
5845 | { "pabsw", { MX, EM } }, | |
5846 | { "pabsd", { MX, EM } }, | |
592d1631 | 5847 | { Bad_Opcode }, |
f88c9eb0 SP |
5848 | /* 20 */ |
5849 | { PREFIX_TABLE (PREFIX_0F3820) }, | |
5850 | { PREFIX_TABLE (PREFIX_0F3821) }, | |
5851 | { PREFIX_TABLE (PREFIX_0F3822) }, | |
5852 | { PREFIX_TABLE (PREFIX_0F3823) }, | |
5853 | { PREFIX_TABLE (PREFIX_0F3824) }, | |
5854 | { PREFIX_TABLE (PREFIX_0F3825) }, | |
592d1631 L |
5855 | { Bad_Opcode }, |
5856 | { Bad_Opcode }, | |
f88c9eb0 SP |
5857 | /* 28 */ |
5858 | { PREFIX_TABLE (PREFIX_0F3828) }, | |
5859 | { PREFIX_TABLE (PREFIX_0F3829) }, | |
5860 | { PREFIX_TABLE (PREFIX_0F382A) }, | |
5861 | { PREFIX_TABLE (PREFIX_0F382B) }, | |
592d1631 L |
5862 | { Bad_Opcode }, |
5863 | { Bad_Opcode }, | |
5864 | { Bad_Opcode }, | |
5865 | { Bad_Opcode }, | |
f88c9eb0 SP |
5866 | /* 30 */ |
5867 | { PREFIX_TABLE (PREFIX_0F3830) }, | |
5868 | { PREFIX_TABLE (PREFIX_0F3831) }, | |
5869 | { PREFIX_TABLE (PREFIX_0F3832) }, | |
5870 | { PREFIX_TABLE (PREFIX_0F3833) }, | |
5871 | { PREFIX_TABLE (PREFIX_0F3834) }, | |
5872 | { PREFIX_TABLE (PREFIX_0F3835) }, | |
592d1631 | 5873 | { Bad_Opcode }, |
f88c9eb0 SP |
5874 | { PREFIX_TABLE (PREFIX_0F3837) }, |
5875 | /* 38 */ | |
5876 | { PREFIX_TABLE (PREFIX_0F3838) }, | |
5877 | { PREFIX_TABLE (PREFIX_0F3839) }, | |
5878 | { PREFIX_TABLE (PREFIX_0F383A) }, | |
5879 | { PREFIX_TABLE (PREFIX_0F383B) }, | |
5880 | { PREFIX_TABLE (PREFIX_0F383C) }, | |
5881 | { PREFIX_TABLE (PREFIX_0F383D) }, | |
5882 | { PREFIX_TABLE (PREFIX_0F383E) }, | |
5883 | { PREFIX_TABLE (PREFIX_0F383F) }, | |
5884 | /* 40 */ | |
5885 | { PREFIX_TABLE (PREFIX_0F3840) }, | |
5886 | { PREFIX_TABLE (PREFIX_0F3841) }, | |
592d1631 L |
5887 | { Bad_Opcode }, |
5888 | { Bad_Opcode }, | |
5889 | { Bad_Opcode }, | |
5890 | { Bad_Opcode }, | |
5891 | { Bad_Opcode }, | |
5892 | { Bad_Opcode }, | |
f88c9eb0 | 5893 | /* 48 */ |
592d1631 L |
5894 | { Bad_Opcode }, |
5895 | { Bad_Opcode }, | |
5896 | { Bad_Opcode }, | |
5897 | { Bad_Opcode }, | |
5898 | { Bad_Opcode }, | |
5899 | { Bad_Opcode }, | |
5900 | { Bad_Opcode }, | |
5901 | { Bad_Opcode }, | |
f88c9eb0 | 5902 | /* 50 */ |
592d1631 L |
5903 | { Bad_Opcode }, |
5904 | { Bad_Opcode }, | |
5905 | { Bad_Opcode }, | |
5906 | { Bad_Opcode }, | |
5907 | { Bad_Opcode }, | |
5908 | { Bad_Opcode }, | |
5909 | { Bad_Opcode }, | |
5910 | { Bad_Opcode }, | |
f88c9eb0 | 5911 | /* 58 */ |
592d1631 L |
5912 | { Bad_Opcode }, |
5913 | { Bad_Opcode }, | |
5914 | { Bad_Opcode }, | |
5915 | { Bad_Opcode }, | |
5916 | { Bad_Opcode }, | |
5917 | { Bad_Opcode }, | |
5918 | { Bad_Opcode }, | |
5919 | { Bad_Opcode }, | |
f88c9eb0 | 5920 | /* 60 */ |
592d1631 L |
5921 | { Bad_Opcode }, |
5922 | { Bad_Opcode }, | |
5923 | { Bad_Opcode }, | |
5924 | { Bad_Opcode }, | |
5925 | { Bad_Opcode }, | |
5926 | { Bad_Opcode }, | |
5927 | { Bad_Opcode }, | |
5928 | { Bad_Opcode }, | |
f88c9eb0 | 5929 | /* 68 */ |
592d1631 L |
5930 | { Bad_Opcode }, |
5931 | { Bad_Opcode }, | |
5932 | { Bad_Opcode }, | |
5933 | { Bad_Opcode }, | |
5934 | { Bad_Opcode }, | |
5935 | { Bad_Opcode }, | |
5936 | { Bad_Opcode }, | |
5937 | { Bad_Opcode }, | |
f88c9eb0 | 5938 | /* 70 */ |
592d1631 L |
5939 | { Bad_Opcode }, |
5940 | { Bad_Opcode }, | |
5941 | { Bad_Opcode }, | |
5942 | { Bad_Opcode }, | |
5943 | { Bad_Opcode }, | |
5944 | { Bad_Opcode }, | |
5945 | { Bad_Opcode }, | |
5946 | { Bad_Opcode }, | |
f88c9eb0 | 5947 | /* 78 */ |
592d1631 L |
5948 | { Bad_Opcode }, |
5949 | { Bad_Opcode }, | |
5950 | { Bad_Opcode }, | |
5951 | { Bad_Opcode }, | |
5952 | { Bad_Opcode }, | |
5953 | { Bad_Opcode }, | |
5954 | { Bad_Opcode }, | |
5955 | { Bad_Opcode }, | |
f88c9eb0 SP |
5956 | /* 80 */ |
5957 | { PREFIX_TABLE (PREFIX_0F3880) }, | |
5958 | { PREFIX_TABLE (PREFIX_0F3881) }, | |
6c30d220 | 5959 | { PREFIX_TABLE (PREFIX_0F3882) }, |
592d1631 L |
5960 | { Bad_Opcode }, |
5961 | { Bad_Opcode }, | |
5962 | { Bad_Opcode }, | |
5963 | { Bad_Opcode }, | |
5964 | { Bad_Opcode }, | |
f88c9eb0 | 5965 | /* 88 */ |
592d1631 L |
5966 | { Bad_Opcode }, |
5967 | { Bad_Opcode }, | |
5968 | { Bad_Opcode }, | |
5969 | { Bad_Opcode }, | |
5970 | { Bad_Opcode }, | |
5971 | { Bad_Opcode }, | |
5972 | { Bad_Opcode }, | |
5973 | { Bad_Opcode }, | |
f88c9eb0 | 5974 | /* 90 */ |
592d1631 L |
5975 | { Bad_Opcode }, |
5976 | { Bad_Opcode }, | |
5977 | { Bad_Opcode }, | |
5978 | { Bad_Opcode }, | |
5979 | { Bad_Opcode }, | |
5980 | { Bad_Opcode }, | |
5981 | { Bad_Opcode }, | |
5982 | { Bad_Opcode }, | |
f88c9eb0 | 5983 | /* 98 */ |
592d1631 L |
5984 | { Bad_Opcode }, |
5985 | { Bad_Opcode }, | |
5986 | { Bad_Opcode }, | |
5987 | { Bad_Opcode }, | |
5988 | { Bad_Opcode }, | |
5989 | { Bad_Opcode }, | |
5990 | { Bad_Opcode }, | |
5991 | { Bad_Opcode }, | |
f88c9eb0 | 5992 | /* a0 */ |
592d1631 L |
5993 | { Bad_Opcode }, |
5994 | { Bad_Opcode }, | |
5995 | { Bad_Opcode }, | |
5996 | { Bad_Opcode }, | |
5997 | { Bad_Opcode }, | |
5998 | { Bad_Opcode }, | |
5999 | { Bad_Opcode }, | |
6000 | { Bad_Opcode }, | |
f88c9eb0 | 6001 | /* a8 */ |
592d1631 L |
6002 | { Bad_Opcode }, |
6003 | { Bad_Opcode }, | |
6004 | { Bad_Opcode }, | |
6005 | { Bad_Opcode }, | |
6006 | { Bad_Opcode }, | |
6007 | { Bad_Opcode }, | |
6008 | { Bad_Opcode }, | |
6009 | { Bad_Opcode }, | |
f88c9eb0 | 6010 | /* b0 */ |
592d1631 L |
6011 | { Bad_Opcode }, |
6012 | { Bad_Opcode }, | |
6013 | { Bad_Opcode }, | |
6014 | { Bad_Opcode }, | |
6015 | { Bad_Opcode }, | |
6016 | { Bad_Opcode }, | |
6017 | { Bad_Opcode }, | |
6018 | { Bad_Opcode }, | |
f88c9eb0 | 6019 | /* b8 */ |
592d1631 L |
6020 | { Bad_Opcode }, |
6021 | { Bad_Opcode }, | |
6022 | { Bad_Opcode }, | |
6023 | { Bad_Opcode }, | |
6024 | { Bad_Opcode }, | |
6025 | { Bad_Opcode }, | |
6026 | { Bad_Opcode }, | |
6027 | { Bad_Opcode }, | |
f88c9eb0 | 6028 | /* c0 */ |
592d1631 L |
6029 | { Bad_Opcode }, |
6030 | { Bad_Opcode }, | |
6031 | { Bad_Opcode }, | |
6032 | { Bad_Opcode }, | |
6033 | { Bad_Opcode }, | |
6034 | { Bad_Opcode }, | |
6035 | { Bad_Opcode }, | |
6036 | { Bad_Opcode }, | |
f88c9eb0 | 6037 | /* c8 */ |
592d1631 L |
6038 | { Bad_Opcode }, |
6039 | { Bad_Opcode }, | |
6040 | { Bad_Opcode }, | |
6041 | { Bad_Opcode }, | |
6042 | { Bad_Opcode }, | |
6043 | { Bad_Opcode }, | |
6044 | { Bad_Opcode }, | |
6045 | { Bad_Opcode }, | |
f88c9eb0 | 6046 | /* d0 */ |
592d1631 L |
6047 | { Bad_Opcode }, |
6048 | { Bad_Opcode }, | |
6049 | { Bad_Opcode }, | |
6050 | { Bad_Opcode }, | |
6051 | { Bad_Opcode }, | |
6052 | { Bad_Opcode }, | |
6053 | { Bad_Opcode }, | |
6054 | { Bad_Opcode }, | |
f88c9eb0 | 6055 | /* d8 */ |
592d1631 L |
6056 | { Bad_Opcode }, |
6057 | { Bad_Opcode }, | |
6058 | { Bad_Opcode }, | |
f88c9eb0 SP |
6059 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
6060 | { PREFIX_TABLE (PREFIX_0F38DC) }, | |
6061 | { PREFIX_TABLE (PREFIX_0F38DD) }, | |
6062 | { PREFIX_TABLE (PREFIX_0F38DE) }, | |
6063 | { PREFIX_TABLE (PREFIX_0F38DF) }, | |
6064 | /* e0 */ | |
592d1631 L |
6065 | { Bad_Opcode }, |
6066 | { Bad_Opcode }, | |
6067 | { Bad_Opcode }, | |
6068 | { Bad_Opcode }, | |
6069 | { Bad_Opcode }, | |
6070 | { Bad_Opcode }, | |
6071 | { Bad_Opcode }, | |
6072 | { Bad_Opcode }, | |
f88c9eb0 | 6073 | /* e8 */ |
592d1631 L |
6074 | { Bad_Opcode }, |
6075 | { Bad_Opcode }, | |
6076 | { Bad_Opcode }, | |
6077 | { Bad_Opcode }, | |
6078 | { Bad_Opcode }, | |
6079 | { Bad_Opcode }, | |
6080 | { Bad_Opcode }, | |
6081 | { Bad_Opcode }, | |
f88c9eb0 SP |
6082 | /* f0 */ |
6083 | { PREFIX_TABLE (PREFIX_0F38F0) }, | |
6084 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
592d1631 L |
6085 | { Bad_Opcode }, |
6086 | { Bad_Opcode }, | |
6087 | { Bad_Opcode }, | |
6088 | { Bad_Opcode }, | |
e2e1fcde | 6089 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
592d1631 | 6090 | { Bad_Opcode }, |
f88c9eb0 | 6091 | /* f8 */ |
592d1631 L |
6092 | { Bad_Opcode }, |
6093 | { Bad_Opcode }, | |
6094 | { Bad_Opcode }, | |
6095 | { Bad_Opcode }, | |
6096 | { Bad_Opcode }, | |
6097 | { Bad_Opcode }, | |
6098 | { Bad_Opcode }, | |
6099 | { Bad_Opcode }, | |
f88c9eb0 SP |
6100 | }, |
6101 | /* THREE_BYTE_0F3A */ | |
6102 | { | |
6103 | /* 00 */ | |
592d1631 L |
6104 | { Bad_Opcode }, |
6105 | { Bad_Opcode }, | |
6106 | { Bad_Opcode }, | |
6107 | { Bad_Opcode }, | |
6108 | { Bad_Opcode }, | |
6109 | { Bad_Opcode }, | |
6110 | { Bad_Opcode }, | |
6111 | { Bad_Opcode }, | |
f88c9eb0 SP |
6112 | /* 08 */ |
6113 | { PREFIX_TABLE (PREFIX_0F3A08) }, | |
6114 | { PREFIX_TABLE (PREFIX_0F3A09) }, | |
6115 | { PREFIX_TABLE (PREFIX_0F3A0A) }, | |
6116 | { PREFIX_TABLE (PREFIX_0F3A0B) }, | |
6117 | { PREFIX_TABLE (PREFIX_0F3A0C) }, | |
6118 | { PREFIX_TABLE (PREFIX_0F3A0D) }, | |
6119 | { PREFIX_TABLE (PREFIX_0F3A0E) }, | |
6120 | { "palignr", { MX, EM, Ib } }, | |
6121 | /* 10 */ | |
592d1631 L |
6122 | { Bad_Opcode }, |
6123 | { Bad_Opcode }, | |
6124 | { Bad_Opcode }, | |
6125 | { Bad_Opcode }, | |
f88c9eb0 SP |
6126 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
6127 | { PREFIX_TABLE (PREFIX_0F3A15) }, | |
6128 | { PREFIX_TABLE (PREFIX_0F3A16) }, | |
6129 | { PREFIX_TABLE (PREFIX_0F3A17) }, | |
6130 | /* 18 */ | |
592d1631 L |
6131 | { Bad_Opcode }, |
6132 | { Bad_Opcode }, | |
6133 | { Bad_Opcode }, | |
6134 | { Bad_Opcode }, | |
6135 | { Bad_Opcode }, | |
6136 | { Bad_Opcode }, | |
6137 | { Bad_Opcode }, | |
6138 | { Bad_Opcode }, | |
f88c9eb0 SP |
6139 | /* 20 */ |
6140 | { PREFIX_TABLE (PREFIX_0F3A20) }, | |
6141 | { PREFIX_TABLE (PREFIX_0F3A21) }, | |
6142 | { PREFIX_TABLE (PREFIX_0F3A22) }, | |
592d1631 L |
6143 | { Bad_Opcode }, |
6144 | { Bad_Opcode }, | |
6145 | { Bad_Opcode }, | |
6146 | { Bad_Opcode }, | |
6147 | { Bad_Opcode }, | |
f88c9eb0 | 6148 | /* 28 */ |
592d1631 L |
6149 | { Bad_Opcode }, |
6150 | { Bad_Opcode }, | |
6151 | { Bad_Opcode }, | |
6152 | { Bad_Opcode }, | |
6153 | { Bad_Opcode }, | |
6154 | { Bad_Opcode }, | |
6155 | { Bad_Opcode }, | |
6156 | { Bad_Opcode }, | |
f88c9eb0 | 6157 | /* 30 */ |
592d1631 L |
6158 | { Bad_Opcode }, |
6159 | { Bad_Opcode }, | |
6160 | { Bad_Opcode }, | |
6161 | { Bad_Opcode }, | |
6162 | { Bad_Opcode }, | |
6163 | { Bad_Opcode }, | |
6164 | { Bad_Opcode }, | |
6165 | { Bad_Opcode }, | |
f88c9eb0 | 6166 | /* 38 */ |
592d1631 L |
6167 | { Bad_Opcode }, |
6168 | { Bad_Opcode }, | |
6169 | { Bad_Opcode }, | |
6170 | { Bad_Opcode }, | |
6171 | { Bad_Opcode }, | |
6172 | { Bad_Opcode }, | |
6173 | { Bad_Opcode }, | |
6174 | { Bad_Opcode }, | |
f88c9eb0 SP |
6175 | /* 40 */ |
6176 | { PREFIX_TABLE (PREFIX_0F3A40) }, | |
6177 | { PREFIX_TABLE (PREFIX_0F3A41) }, | |
6178 | { PREFIX_TABLE (PREFIX_0F3A42) }, | |
592d1631 | 6179 | { Bad_Opcode }, |
f88c9eb0 | 6180 | { PREFIX_TABLE (PREFIX_0F3A44) }, |
592d1631 L |
6181 | { Bad_Opcode }, |
6182 | { Bad_Opcode }, | |
6183 | { Bad_Opcode }, | |
f88c9eb0 | 6184 | /* 48 */ |
592d1631 L |
6185 | { Bad_Opcode }, |
6186 | { Bad_Opcode }, | |
6187 | { Bad_Opcode }, | |
6188 | { Bad_Opcode }, | |
6189 | { Bad_Opcode }, | |
6190 | { Bad_Opcode }, | |
6191 | { Bad_Opcode }, | |
6192 | { Bad_Opcode }, | |
f88c9eb0 | 6193 | /* 50 */ |
592d1631 L |
6194 | { Bad_Opcode }, |
6195 | { Bad_Opcode }, | |
6196 | { Bad_Opcode }, | |
6197 | { Bad_Opcode }, | |
6198 | { Bad_Opcode }, | |
6199 | { Bad_Opcode }, | |
6200 | { Bad_Opcode }, | |
6201 | { Bad_Opcode }, | |
f88c9eb0 | 6202 | /* 58 */ |
592d1631 L |
6203 | { Bad_Opcode }, |
6204 | { Bad_Opcode }, | |
6205 | { Bad_Opcode }, | |
6206 | { Bad_Opcode }, | |
6207 | { Bad_Opcode }, | |
6208 | { Bad_Opcode }, | |
6209 | { Bad_Opcode }, | |
6210 | { Bad_Opcode }, | |
f88c9eb0 SP |
6211 | /* 60 */ |
6212 | { PREFIX_TABLE (PREFIX_0F3A60) }, | |
6213 | { PREFIX_TABLE (PREFIX_0F3A61) }, | |
6214 | { PREFIX_TABLE (PREFIX_0F3A62) }, | |
6215 | { PREFIX_TABLE (PREFIX_0F3A63) }, | |
592d1631 L |
6216 | { Bad_Opcode }, |
6217 | { Bad_Opcode }, | |
6218 | { Bad_Opcode }, | |
6219 | { Bad_Opcode }, | |
f88c9eb0 | 6220 | /* 68 */ |
592d1631 L |
6221 | { Bad_Opcode }, |
6222 | { Bad_Opcode }, | |
6223 | { Bad_Opcode }, | |
6224 | { Bad_Opcode }, | |
6225 | { Bad_Opcode }, | |
6226 | { Bad_Opcode }, | |
6227 | { Bad_Opcode }, | |
6228 | { Bad_Opcode }, | |
f88c9eb0 | 6229 | /* 70 */ |
592d1631 L |
6230 | { Bad_Opcode }, |
6231 | { Bad_Opcode }, | |
6232 | { Bad_Opcode }, | |
6233 | { Bad_Opcode }, | |
6234 | { Bad_Opcode }, | |
6235 | { Bad_Opcode }, | |
6236 | { Bad_Opcode }, | |
6237 | { Bad_Opcode }, | |
f88c9eb0 | 6238 | /* 78 */ |
592d1631 L |
6239 | { Bad_Opcode }, |
6240 | { Bad_Opcode }, | |
6241 | { Bad_Opcode }, | |
6242 | { Bad_Opcode }, | |
6243 | { Bad_Opcode }, | |
6244 | { Bad_Opcode }, | |
6245 | { Bad_Opcode }, | |
6246 | { Bad_Opcode }, | |
f88c9eb0 | 6247 | /* 80 */ |
592d1631 L |
6248 | { Bad_Opcode }, |
6249 | { Bad_Opcode }, | |
6250 | { Bad_Opcode }, | |
6251 | { Bad_Opcode }, | |
6252 | { Bad_Opcode }, | |
6253 | { Bad_Opcode }, | |
6254 | { Bad_Opcode }, | |
6255 | { Bad_Opcode }, | |
f88c9eb0 | 6256 | /* 88 */ |
592d1631 L |
6257 | { Bad_Opcode }, |
6258 | { Bad_Opcode }, | |
6259 | { Bad_Opcode }, | |
6260 | { Bad_Opcode }, | |
6261 | { Bad_Opcode }, | |
6262 | { Bad_Opcode }, | |
6263 | { Bad_Opcode }, | |
6264 | { Bad_Opcode }, | |
f88c9eb0 | 6265 | /* 90 */ |
592d1631 L |
6266 | { Bad_Opcode }, |
6267 | { Bad_Opcode }, | |
6268 | { Bad_Opcode }, | |
6269 | { Bad_Opcode }, | |
6270 | { Bad_Opcode }, | |
6271 | { Bad_Opcode }, | |
6272 | { Bad_Opcode }, | |
6273 | { Bad_Opcode }, | |
f88c9eb0 | 6274 | /* 98 */ |
592d1631 L |
6275 | { Bad_Opcode }, |
6276 | { Bad_Opcode }, | |
6277 | { Bad_Opcode }, | |
6278 | { Bad_Opcode }, | |
6279 | { Bad_Opcode }, | |
6280 | { Bad_Opcode }, | |
6281 | { Bad_Opcode }, | |
6282 | { Bad_Opcode }, | |
f88c9eb0 | 6283 | /* a0 */ |
592d1631 L |
6284 | { Bad_Opcode }, |
6285 | { Bad_Opcode }, | |
6286 | { Bad_Opcode }, | |
6287 | { Bad_Opcode }, | |
6288 | { Bad_Opcode }, | |
6289 | { Bad_Opcode }, | |
6290 | { Bad_Opcode }, | |
6291 | { Bad_Opcode }, | |
f88c9eb0 | 6292 | /* a8 */ |
592d1631 L |
6293 | { Bad_Opcode }, |
6294 | { Bad_Opcode }, | |
6295 | { Bad_Opcode }, | |
6296 | { Bad_Opcode }, | |
6297 | { Bad_Opcode }, | |
6298 | { Bad_Opcode }, | |
6299 | { Bad_Opcode }, | |
6300 | { Bad_Opcode }, | |
f88c9eb0 | 6301 | /* b0 */ |
592d1631 L |
6302 | { Bad_Opcode }, |
6303 | { Bad_Opcode }, | |
6304 | { Bad_Opcode }, | |
6305 | { Bad_Opcode }, | |
6306 | { Bad_Opcode }, | |
6307 | { Bad_Opcode }, | |
6308 | { Bad_Opcode }, | |
6309 | { Bad_Opcode }, | |
f88c9eb0 | 6310 | /* b8 */ |
592d1631 L |
6311 | { Bad_Opcode }, |
6312 | { Bad_Opcode }, | |
6313 | { Bad_Opcode }, | |
6314 | { Bad_Opcode }, | |
6315 | { Bad_Opcode }, | |
6316 | { Bad_Opcode }, | |
6317 | { Bad_Opcode }, | |
6318 | { Bad_Opcode }, | |
f88c9eb0 | 6319 | /* c0 */ |
592d1631 L |
6320 | { Bad_Opcode }, |
6321 | { Bad_Opcode }, | |
6322 | { Bad_Opcode }, | |
6323 | { Bad_Opcode }, | |
6324 | { Bad_Opcode }, | |
6325 | { Bad_Opcode }, | |
6326 | { Bad_Opcode }, | |
6327 | { Bad_Opcode }, | |
f88c9eb0 | 6328 | /* c8 */ |
592d1631 L |
6329 | { Bad_Opcode }, |
6330 | { Bad_Opcode }, | |
6331 | { Bad_Opcode }, | |
6332 | { Bad_Opcode }, | |
6333 | { Bad_Opcode }, | |
6334 | { Bad_Opcode }, | |
6335 | { Bad_Opcode }, | |
6336 | { Bad_Opcode }, | |
f88c9eb0 | 6337 | /* d0 */ |
592d1631 L |
6338 | { Bad_Opcode }, |
6339 | { Bad_Opcode }, | |
6340 | { Bad_Opcode }, | |
6341 | { Bad_Opcode }, | |
6342 | { Bad_Opcode }, | |
6343 | { Bad_Opcode }, | |
6344 | { Bad_Opcode }, | |
6345 | { Bad_Opcode }, | |
f88c9eb0 | 6346 | /* d8 */ |
592d1631 L |
6347 | { Bad_Opcode }, |
6348 | { Bad_Opcode }, | |
6349 | { Bad_Opcode }, | |
6350 | { Bad_Opcode }, | |
6351 | { Bad_Opcode }, | |
6352 | { Bad_Opcode }, | |
6353 | { Bad_Opcode }, | |
f88c9eb0 SP |
6354 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
6355 | /* e0 */ | |
592d1631 L |
6356 | { Bad_Opcode }, |
6357 | { Bad_Opcode }, | |
6358 | { Bad_Opcode }, | |
6359 | { Bad_Opcode }, | |
6360 | { Bad_Opcode }, | |
6361 | { Bad_Opcode }, | |
6362 | { Bad_Opcode }, | |
6363 | { Bad_Opcode }, | |
f88c9eb0 | 6364 | /* e8 */ |
592d1631 L |
6365 | { Bad_Opcode }, |
6366 | { Bad_Opcode }, | |
6367 | { Bad_Opcode }, | |
6368 | { Bad_Opcode }, | |
6369 | { Bad_Opcode }, | |
6370 | { Bad_Opcode }, | |
6371 | { Bad_Opcode }, | |
6372 | { Bad_Opcode }, | |
f88c9eb0 | 6373 | /* f0 */ |
592d1631 L |
6374 | { Bad_Opcode }, |
6375 | { Bad_Opcode }, | |
6376 | { Bad_Opcode }, | |
6377 | { Bad_Opcode }, | |
6378 | { Bad_Opcode }, | |
6379 | { Bad_Opcode }, | |
6380 | { Bad_Opcode }, | |
6381 | { Bad_Opcode }, | |
f88c9eb0 | 6382 | /* f8 */ |
592d1631 L |
6383 | { Bad_Opcode }, |
6384 | { Bad_Opcode }, | |
6385 | { Bad_Opcode }, | |
6386 | { Bad_Opcode }, | |
6387 | { Bad_Opcode }, | |
6388 | { Bad_Opcode }, | |
6389 | { Bad_Opcode }, | |
6390 | { Bad_Opcode }, | |
f88c9eb0 SP |
6391 | }, |
6392 | ||
6393 | /* THREE_BYTE_0F7A */ | |
6394 | { | |
6395 | /* 00 */ | |
592d1631 L |
6396 | { Bad_Opcode }, |
6397 | { Bad_Opcode }, | |
6398 | { Bad_Opcode }, | |
6399 | { Bad_Opcode }, | |
6400 | { Bad_Opcode }, | |
6401 | { Bad_Opcode }, | |
6402 | { Bad_Opcode }, | |
6403 | { Bad_Opcode }, | |
f88c9eb0 | 6404 | /* 08 */ |
592d1631 L |
6405 | { Bad_Opcode }, |
6406 | { Bad_Opcode }, | |
6407 | { Bad_Opcode }, | |
6408 | { Bad_Opcode }, | |
6409 | { Bad_Opcode }, | |
6410 | { Bad_Opcode }, | |
6411 | { Bad_Opcode }, | |
6412 | { Bad_Opcode }, | |
f88c9eb0 | 6413 | /* 10 */ |
592d1631 L |
6414 | { Bad_Opcode }, |
6415 | { Bad_Opcode }, | |
6416 | { Bad_Opcode }, | |
6417 | { Bad_Opcode }, | |
6418 | { Bad_Opcode }, | |
6419 | { Bad_Opcode }, | |
6420 | { Bad_Opcode }, | |
6421 | { Bad_Opcode }, | |
f88c9eb0 | 6422 | /* 18 */ |
592d1631 L |
6423 | { Bad_Opcode }, |
6424 | { Bad_Opcode }, | |
6425 | { Bad_Opcode }, | |
6426 | { Bad_Opcode }, | |
6427 | { Bad_Opcode }, | |
6428 | { Bad_Opcode }, | |
6429 | { Bad_Opcode }, | |
6430 | { Bad_Opcode }, | |
f88c9eb0 SP |
6431 | /* 20 */ |
6432 | { "ptest", { XX } }, | |
592d1631 L |
6433 | { Bad_Opcode }, |
6434 | { Bad_Opcode }, | |
6435 | { Bad_Opcode }, | |
6436 | { Bad_Opcode }, | |
6437 | { Bad_Opcode }, | |
6438 | { Bad_Opcode }, | |
6439 | { Bad_Opcode }, | |
f88c9eb0 | 6440 | /* 28 */ |
592d1631 L |
6441 | { Bad_Opcode }, |
6442 | { Bad_Opcode }, | |
6443 | { Bad_Opcode }, | |
6444 | { Bad_Opcode }, | |
6445 | { Bad_Opcode }, | |
6446 | { Bad_Opcode }, | |
6447 | { Bad_Opcode }, | |
6448 | { Bad_Opcode }, | |
f88c9eb0 | 6449 | /* 30 */ |
592d1631 L |
6450 | { Bad_Opcode }, |
6451 | { Bad_Opcode }, | |
6452 | { Bad_Opcode }, | |
6453 | { Bad_Opcode }, | |
6454 | { Bad_Opcode }, | |
6455 | { Bad_Opcode }, | |
6456 | { Bad_Opcode }, | |
6457 | { Bad_Opcode }, | |
f88c9eb0 | 6458 | /* 38 */ |
592d1631 L |
6459 | { Bad_Opcode }, |
6460 | { Bad_Opcode }, | |
6461 | { Bad_Opcode }, | |
6462 | { Bad_Opcode }, | |
6463 | { Bad_Opcode }, | |
6464 | { Bad_Opcode }, | |
6465 | { Bad_Opcode }, | |
6466 | { Bad_Opcode }, | |
f88c9eb0 | 6467 | /* 40 */ |
592d1631 | 6468 | { Bad_Opcode }, |
f88c9eb0 SP |
6469 | { "phaddbw", { XM, EXq } }, |
6470 | { "phaddbd", { XM, EXq } }, | |
6471 | { "phaddbq", { XM, EXq } }, | |
592d1631 L |
6472 | { Bad_Opcode }, |
6473 | { Bad_Opcode }, | |
f88c9eb0 SP |
6474 | { "phaddwd", { XM, EXq } }, |
6475 | { "phaddwq", { XM, EXq } }, | |
6476 | /* 48 */ | |
592d1631 L |
6477 | { Bad_Opcode }, |
6478 | { Bad_Opcode }, | |
6479 | { Bad_Opcode }, | |
f88c9eb0 | 6480 | { "phadddq", { XM, EXq } }, |
592d1631 L |
6481 | { Bad_Opcode }, |
6482 | { Bad_Opcode }, | |
6483 | { Bad_Opcode }, | |
6484 | { Bad_Opcode }, | |
f88c9eb0 | 6485 | /* 50 */ |
592d1631 | 6486 | { Bad_Opcode }, |
f88c9eb0 SP |
6487 | { "phaddubw", { XM, EXq } }, |
6488 | { "phaddubd", { XM, EXq } }, | |
6489 | { "phaddubq", { XM, EXq } }, | |
592d1631 L |
6490 | { Bad_Opcode }, |
6491 | { Bad_Opcode }, | |
f88c9eb0 SP |
6492 | { "phadduwd", { XM, EXq } }, |
6493 | { "phadduwq", { XM, EXq } }, | |
6494 | /* 58 */ | |
592d1631 L |
6495 | { Bad_Opcode }, |
6496 | { Bad_Opcode }, | |
6497 | { Bad_Opcode }, | |
f88c9eb0 | 6498 | { "phaddudq", { XM, EXq } }, |
592d1631 L |
6499 | { Bad_Opcode }, |
6500 | { Bad_Opcode }, | |
6501 | { Bad_Opcode }, | |
6502 | { Bad_Opcode }, | |
f88c9eb0 | 6503 | /* 60 */ |
592d1631 | 6504 | { Bad_Opcode }, |
f88c9eb0 SP |
6505 | { "phsubbw", { XM, EXq } }, |
6506 | { "phsubbd", { XM, EXq } }, | |
6507 | { "phsubbq", { XM, EXq } }, | |
592d1631 L |
6508 | { Bad_Opcode }, |
6509 | { Bad_Opcode }, | |
6510 | { Bad_Opcode }, | |
6511 | { Bad_Opcode }, | |
4e7d34a6 | 6512 | /* 68 */ |
592d1631 L |
6513 | { Bad_Opcode }, |
6514 | { Bad_Opcode }, | |
6515 | { Bad_Opcode }, | |
6516 | { Bad_Opcode }, | |
6517 | { Bad_Opcode }, | |
6518 | { Bad_Opcode }, | |
6519 | { Bad_Opcode }, | |
6520 | { Bad_Opcode }, | |
85f10a01 | 6521 | /* 70 */ |
592d1631 L |
6522 | { Bad_Opcode }, |
6523 | { Bad_Opcode }, | |
6524 | { Bad_Opcode }, | |
6525 | { Bad_Opcode }, | |
6526 | { Bad_Opcode }, | |
6527 | { Bad_Opcode }, | |
6528 | { Bad_Opcode }, | |
6529 | { Bad_Opcode }, | |
85f10a01 | 6530 | /* 78 */ |
592d1631 L |
6531 | { Bad_Opcode }, |
6532 | { Bad_Opcode }, | |
6533 | { Bad_Opcode }, | |
6534 | { Bad_Opcode }, | |
6535 | { Bad_Opcode }, | |
6536 | { Bad_Opcode }, | |
6537 | { Bad_Opcode }, | |
6538 | { Bad_Opcode }, | |
85f10a01 | 6539 | /* 80 */ |
592d1631 L |
6540 | { Bad_Opcode }, |
6541 | { Bad_Opcode }, | |
6542 | { Bad_Opcode }, | |
6543 | { Bad_Opcode }, | |
6544 | { Bad_Opcode }, | |
6545 | { Bad_Opcode }, | |
6546 | { Bad_Opcode }, | |
6547 | { Bad_Opcode }, | |
85f10a01 | 6548 | /* 88 */ |
592d1631 L |
6549 | { Bad_Opcode }, |
6550 | { Bad_Opcode }, | |
6551 | { Bad_Opcode }, | |
6552 | { Bad_Opcode }, | |
6553 | { Bad_Opcode }, | |
6554 | { Bad_Opcode }, | |
6555 | { Bad_Opcode }, | |
6556 | { Bad_Opcode }, | |
85f10a01 | 6557 | /* 90 */ |
592d1631 L |
6558 | { Bad_Opcode }, |
6559 | { Bad_Opcode }, | |
6560 | { Bad_Opcode }, | |
6561 | { Bad_Opcode }, | |
6562 | { Bad_Opcode }, | |
6563 | { Bad_Opcode }, | |
6564 | { Bad_Opcode }, | |
6565 | { Bad_Opcode }, | |
85f10a01 | 6566 | /* 98 */ |
592d1631 L |
6567 | { Bad_Opcode }, |
6568 | { Bad_Opcode }, | |
6569 | { Bad_Opcode }, | |
6570 | { Bad_Opcode }, | |
6571 | { Bad_Opcode }, | |
6572 | { Bad_Opcode }, | |
6573 | { Bad_Opcode }, | |
6574 | { Bad_Opcode }, | |
85f10a01 | 6575 | /* a0 */ |
592d1631 L |
6576 | { Bad_Opcode }, |
6577 | { Bad_Opcode }, | |
6578 | { Bad_Opcode }, | |
6579 | { Bad_Opcode }, | |
6580 | { Bad_Opcode }, | |
6581 | { Bad_Opcode }, | |
6582 | { Bad_Opcode }, | |
6583 | { Bad_Opcode }, | |
85f10a01 | 6584 | /* a8 */ |
592d1631 L |
6585 | { Bad_Opcode }, |
6586 | { Bad_Opcode }, | |
6587 | { Bad_Opcode }, | |
6588 | { Bad_Opcode }, | |
6589 | { Bad_Opcode }, | |
6590 | { Bad_Opcode }, | |
6591 | { Bad_Opcode }, | |
6592 | { Bad_Opcode }, | |
85f10a01 | 6593 | /* b0 */ |
592d1631 L |
6594 | { Bad_Opcode }, |
6595 | { Bad_Opcode }, | |
6596 | { Bad_Opcode }, | |
6597 | { Bad_Opcode }, | |
6598 | { Bad_Opcode }, | |
6599 | { Bad_Opcode }, | |
6600 | { Bad_Opcode }, | |
6601 | { Bad_Opcode }, | |
85f10a01 | 6602 | /* b8 */ |
592d1631 L |
6603 | { Bad_Opcode }, |
6604 | { Bad_Opcode }, | |
6605 | { Bad_Opcode }, | |
6606 | { Bad_Opcode }, | |
6607 | { Bad_Opcode }, | |
6608 | { Bad_Opcode }, | |
6609 | { Bad_Opcode }, | |
6610 | { Bad_Opcode }, | |
85f10a01 | 6611 | /* c0 */ |
592d1631 L |
6612 | { Bad_Opcode }, |
6613 | { Bad_Opcode }, | |
6614 | { Bad_Opcode }, | |
6615 | { Bad_Opcode }, | |
6616 | { Bad_Opcode }, | |
6617 | { Bad_Opcode }, | |
6618 | { Bad_Opcode }, | |
6619 | { Bad_Opcode }, | |
85f10a01 | 6620 | /* c8 */ |
592d1631 L |
6621 | { Bad_Opcode }, |
6622 | { Bad_Opcode }, | |
6623 | { Bad_Opcode }, | |
6624 | { Bad_Opcode }, | |
6625 | { Bad_Opcode }, | |
6626 | { Bad_Opcode }, | |
6627 | { Bad_Opcode }, | |
6628 | { Bad_Opcode }, | |
85f10a01 | 6629 | /* d0 */ |
592d1631 L |
6630 | { Bad_Opcode }, |
6631 | { Bad_Opcode }, | |
6632 | { Bad_Opcode }, | |
6633 | { Bad_Opcode }, | |
6634 | { Bad_Opcode }, | |
6635 | { Bad_Opcode }, | |
6636 | { Bad_Opcode }, | |
6637 | { Bad_Opcode }, | |
85f10a01 | 6638 | /* d8 */ |
592d1631 L |
6639 | { Bad_Opcode }, |
6640 | { Bad_Opcode }, | |
6641 | { Bad_Opcode }, | |
6642 | { Bad_Opcode }, | |
6643 | { Bad_Opcode }, | |
6644 | { Bad_Opcode }, | |
6645 | { Bad_Opcode }, | |
6646 | { Bad_Opcode }, | |
85f10a01 | 6647 | /* e0 */ |
592d1631 L |
6648 | { Bad_Opcode }, |
6649 | { Bad_Opcode }, | |
6650 | { Bad_Opcode }, | |
6651 | { Bad_Opcode }, | |
6652 | { Bad_Opcode }, | |
6653 | { Bad_Opcode }, | |
6654 | { Bad_Opcode }, | |
6655 | { Bad_Opcode }, | |
85f10a01 | 6656 | /* e8 */ |
592d1631 L |
6657 | { Bad_Opcode }, |
6658 | { Bad_Opcode }, | |
6659 | { Bad_Opcode }, | |
6660 | { Bad_Opcode }, | |
6661 | { Bad_Opcode }, | |
6662 | { Bad_Opcode }, | |
6663 | { Bad_Opcode }, | |
6664 | { Bad_Opcode }, | |
85f10a01 | 6665 | /* f0 */ |
592d1631 L |
6666 | { Bad_Opcode }, |
6667 | { Bad_Opcode }, | |
6668 | { Bad_Opcode }, | |
6669 | { Bad_Opcode }, | |
6670 | { Bad_Opcode }, | |
6671 | { Bad_Opcode }, | |
6672 | { Bad_Opcode }, | |
6673 | { Bad_Opcode }, | |
85f10a01 | 6674 | /* f8 */ |
592d1631 L |
6675 | { Bad_Opcode }, |
6676 | { Bad_Opcode }, | |
6677 | { Bad_Opcode }, | |
6678 | { Bad_Opcode }, | |
6679 | { Bad_Opcode }, | |
6680 | { Bad_Opcode }, | |
6681 | { Bad_Opcode }, | |
6682 | { Bad_Opcode }, | |
85f10a01 | 6683 | }, |
f88c9eb0 SP |
6684 | }; |
6685 | ||
6686 | static const struct dis386 xop_table[][256] = { | |
5dd85c99 | 6687 | /* XOP_08 */ |
85f10a01 MM |
6688 | { |
6689 | /* 00 */ | |
592d1631 L |
6690 | { Bad_Opcode }, |
6691 | { Bad_Opcode }, | |
6692 | { Bad_Opcode }, | |
6693 | { Bad_Opcode }, | |
6694 | { Bad_Opcode }, | |
6695 | { Bad_Opcode }, | |
6696 | { Bad_Opcode }, | |
6697 | { Bad_Opcode }, | |
85f10a01 | 6698 | /* 08 */ |
592d1631 L |
6699 | { Bad_Opcode }, |
6700 | { Bad_Opcode }, | |
6701 | { Bad_Opcode }, | |
6702 | { Bad_Opcode }, | |
6703 | { Bad_Opcode }, | |
6704 | { Bad_Opcode }, | |
6705 | { Bad_Opcode }, | |
6706 | { Bad_Opcode }, | |
85f10a01 | 6707 | /* 10 */ |
3929df09 | 6708 | { Bad_Opcode }, |
592d1631 L |
6709 | { Bad_Opcode }, |
6710 | { Bad_Opcode }, | |
6711 | { Bad_Opcode }, | |
6712 | { Bad_Opcode }, | |
6713 | { Bad_Opcode }, | |
6714 | { Bad_Opcode }, | |
6715 | { Bad_Opcode }, | |
85f10a01 | 6716 | /* 18 */ |
592d1631 L |
6717 | { Bad_Opcode }, |
6718 | { Bad_Opcode }, | |
6719 | { Bad_Opcode }, | |
6720 | { Bad_Opcode }, | |
6721 | { Bad_Opcode }, | |
6722 | { Bad_Opcode }, | |
6723 | { Bad_Opcode }, | |
6724 | { Bad_Opcode }, | |
85f10a01 | 6725 | /* 20 */ |
592d1631 L |
6726 | { Bad_Opcode }, |
6727 | { Bad_Opcode }, | |
6728 | { Bad_Opcode }, | |
6729 | { Bad_Opcode }, | |
6730 | { Bad_Opcode }, | |
6731 | { Bad_Opcode }, | |
6732 | { Bad_Opcode }, | |
6733 | { Bad_Opcode }, | |
85f10a01 | 6734 | /* 28 */ |
592d1631 L |
6735 | { Bad_Opcode }, |
6736 | { Bad_Opcode }, | |
6737 | { Bad_Opcode }, | |
6738 | { Bad_Opcode }, | |
6739 | { Bad_Opcode }, | |
6740 | { Bad_Opcode }, | |
6741 | { Bad_Opcode }, | |
6742 | { Bad_Opcode }, | |
c0f3af97 | 6743 | /* 30 */ |
592d1631 L |
6744 | { Bad_Opcode }, |
6745 | { Bad_Opcode }, | |
6746 | { Bad_Opcode }, | |
6747 | { Bad_Opcode }, | |
6748 | { Bad_Opcode }, | |
6749 | { Bad_Opcode }, | |
6750 | { Bad_Opcode }, | |
6751 | { Bad_Opcode }, | |
c0f3af97 | 6752 | /* 38 */ |
592d1631 L |
6753 | { Bad_Opcode }, |
6754 | { Bad_Opcode }, | |
6755 | { Bad_Opcode }, | |
6756 | { Bad_Opcode }, | |
6757 | { Bad_Opcode }, | |
6758 | { Bad_Opcode }, | |
6759 | { Bad_Opcode }, | |
6760 | { Bad_Opcode }, | |
c0f3af97 | 6761 | /* 40 */ |
592d1631 L |
6762 | { Bad_Opcode }, |
6763 | { Bad_Opcode }, | |
6764 | { Bad_Opcode }, | |
6765 | { Bad_Opcode }, | |
6766 | { Bad_Opcode }, | |
6767 | { Bad_Opcode }, | |
6768 | { Bad_Opcode }, | |
6769 | { Bad_Opcode }, | |
85f10a01 | 6770 | /* 48 */ |
592d1631 L |
6771 | { Bad_Opcode }, |
6772 | { Bad_Opcode }, | |
6773 | { Bad_Opcode }, | |
6774 | { Bad_Opcode }, | |
6775 | { Bad_Opcode }, | |
6776 | { Bad_Opcode }, | |
6777 | { Bad_Opcode }, | |
6778 | { Bad_Opcode }, | |
c0f3af97 | 6779 | /* 50 */ |
592d1631 L |
6780 | { Bad_Opcode }, |
6781 | { Bad_Opcode }, | |
6782 | { Bad_Opcode }, | |
6783 | { Bad_Opcode }, | |
6784 | { Bad_Opcode }, | |
6785 | { Bad_Opcode }, | |
6786 | { Bad_Opcode }, | |
6787 | { Bad_Opcode }, | |
85f10a01 | 6788 | /* 58 */ |
592d1631 L |
6789 | { Bad_Opcode }, |
6790 | { Bad_Opcode }, | |
6791 | { Bad_Opcode }, | |
6792 | { Bad_Opcode }, | |
6793 | { Bad_Opcode }, | |
6794 | { Bad_Opcode }, | |
6795 | { Bad_Opcode }, | |
6796 | { Bad_Opcode }, | |
c1e679ec | 6797 | /* 60 */ |
592d1631 L |
6798 | { Bad_Opcode }, |
6799 | { Bad_Opcode }, | |
6800 | { Bad_Opcode }, | |
6801 | { Bad_Opcode }, | |
6802 | { Bad_Opcode }, | |
6803 | { Bad_Opcode }, | |
6804 | { Bad_Opcode }, | |
6805 | { Bad_Opcode }, | |
c0f3af97 | 6806 | /* 68 */ |
592d1631 L |
6807 | { Bad_Opcode }, |
6808 | { Bad_Opcode }, | |
6809 | { Bad_Opcode }, | |
6810 | { Bad_Opcode }, | |
6811 | { Bad_Opcode }, | |
6812 | { Bad_Opcode }, | |
6813 | { Bad_Opcode }, | |
6814 | { Bad_Opcode }, | |
85f10a01 | 6815 | /* 70 */ |
592d1631 L |
6816 | { Bad_Opcode }, |
6817 | { Bad_Opcode }, | |
6818 | { Bad_Opcode }, | |
6819 | { Bad_Opcode }, | |
6820 | { Bad_Opcode }, | |
6821 | { Bad_Opcode }, | |
6822 | { Bad_Opcode }, | |
6823 | { Bad_Opcode }, | |
85f10a01 | 6824 | /* 78 */ |
592d1631 L |
6825 | { Bad_Opcode }, |
6826 | { Bad_Opcode }, | |
6827 | { Bad_Opcode }, | |
6828 | { Bad_Opcode }, | |
6829 | { Bad_Opcode }, | |
6830 | { Bad_Opcode }, | |
6831 | { Bad_Opcode }, | |
6832 | { Bad_Opcode }, | |
85f10a01 | 6833 | /* 80 */ |
592d1631 L |
6834 | { Bad_Opcode }, |
6835 | { Bad_Opcode }, | |
6836 | { Bad_Opcode }, | |
6837 | { Bad_Opcode }, | |
6838 | { Bad_Opcode }, | |
5dd85c99 SP |
6839 | { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6840 | { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
6841 | { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
6842 | /* 88 */ | |
592d1631 L |
6843 | { Bad_Opcode }, |
6844 | { Bad_Opcode }, | |
6845 | { Bad_Opcode }, | |
6846 | { Bad_Opcode }, | |
6847 | { Bad_Opcode }, | |
6848 | { Bad_Opcode }, | |
5dd85c99 SP |
6849 | { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6850 | { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
6851 | /* 90 */ | |
592d1631 L |
6852 | { Bad_Opcode }, |
6853 | { Bad_Opcode }, | |
6854 | { Bad_Opcode }, | |
6855 | { Bad_Opcode }, | |
6856 | { Bad_Opcode }, | |
5dd85c99 SP |
6857 | { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6858 | { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
6859 | { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
6860 | /* 98 */ | |
592d1631 L |
6861 | { Bad_Opcode }, |
6862 | { Bad_Opcode }, | |
6863 | { Bad_Opcode }, | |
6864 | { Bad_Opcode }, | |
6865 | { Bad_Opcode }, | |
6866 | { Bad_Opcode }, | |
5dd85c99 SP |
6867 | { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6868 | { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
6869 | /* a0 */ | |
592d1631 L |
6870 | { Bad_Opcode }, |
6871 | { Bad_Opcode }, | |
5dd85c99 SP |
6872 | { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
6873 | { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
592d1631 L |
6874 | { Bad_Opcode }, |
6875 | { Bad_Opcode }, | |
5dd85c99 | 6876 | { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
592d1631 | 6877 | { Bad_Opcode }, |
5dd85c99 | 6878 | /* a8 */ |
592d1631 L |
6879 | { Bad_Opcode }, |
6880 | { Bad_Opcode }, | |
6881 | { Bad_Opcode }, | |
6882 | { Bad_Opcode }, | |
6883 | { Bad_Opcode }, | |
6884 | { Bad_Opcode }, | |
6885 | { Bad_Opcode }, | |
6886 | { Bad_Opcode }, | |
5dd85c99 | 6887 | /* b0 */ |
592d1631 L |
6888 | { Bad_Opcode }, |
6889 | { Bad_Opcode }, | |
6890 | { Bad_Opcode }, | |
6891 | { Bad_Opcode }, | |
6892 | { Bad_Opcode }, | |
6893 | { Bad_Opcode }, | |
5dd85c99 | 6894 | { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
592d1631 | 6895 | { Bad_Opcode }, |
5dd85c99 | 6896 | /* b8 */ |
592d1631 L |
6897 | { Bad_Opcode }, |
6898 | { Bad_Opcode }, | |
6899 | { Bad_Opcode }, | |
6900 | { Bad_Opcode }, | |
6901 | { Bad_Opcode }, | |
6902 | { Bad_Opcode }, | |
6903 | { Bad_Opcode }, | |
6904 | { Bad_Opcode }, | |
5dd85c99 SP |
6905 | /* c0 */ |
6906 | { "vprotb", { XM, Vex_2src_1, Ib } }, | |
6907 | { "vprotw", { XM, Vex_2src_1, Ib } }, | |
6908 | { "vprotd", { XM, Vex_2src_1, Ib } }, | |
6909 | { "vprotq", { XM, Vex_2src_1, Ib } }, | |
592d1631 L |
6910 | { Bad_Opcode }, |
6911 | { Bad_Opcode }, | |
6912 | { Bad_Opcode }, | |
6913 | { Bad_Opcode }, | |
5dd85c99 | 6914 | /* c8 */ |
592d1631 L |
6915 | { Bad_Opcode }, |
6916 | { Bad_Opcode }, | |
6917 | { Bad_Opcode }, | |
6918 | { Bad_Opcode }, | |
ff688e1f L |
6919 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, |
6920 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, | |
6921 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, | |
6922 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, | |
5dd85c99 | 6923 | /* d0 */ |
592d1631 L |
6924 | { Bad_Opcode }, |
6925 | { Bad_Opcode }, | |
6926 | { Bad_Opcode }, | |
6927 | { Bad_Opcode }, | |
6928 | { Bad_Opcode }, | |
6929 | { Bad_Opcode }, | |
6930 | { Bad_Opcode }, | |
6931 | { Bad_Opcode }, | |
5dd85c99 | 6932 | /* d8 */ |
592d1631 L |
6933 | { Bad_Opcode }, |
6934 | { Bad_Opcode }, | |
6935 | { Bad_Opcode }, | |
6936 | { Bad_Opcode }, | |
6937 | { Bad_Opcode }, | |
6938 | { Bad_Opcode }, | |
6939 | { Bad_Opcode }, | |
6940 | { Bad_Opcode }, | |
5dd85c99 | 6941 | /* e0 */ |
592d1631 L |
6942 | { Bad_Opcode }, |
6943 | { Bad_Opcode }, | |
6944 | { Bad_Opcode }, | |
6945 | { Bad_Opcode }, | |
6946 | { Bad_Opcode }, | |
6947 | { Bad_Opcode }, | |
6948 | { Bad_Opcode }, | |
6949 | { Bad_Opcode }, | |
5dd85c99 | 6950 | /* e8 */ |
592d1631 L |
6951 | { Bad_Opcode }, |
6952 | { Bad_Opcode }, | |
6953 | { Bad_Opcode }, | |
6954 | { Bad_Opcode }, | |
ff688e1f L |
6955 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, |
6956 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, | |
6957 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, | |
6958 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, | |
5dd85c99 | 6959 | /* f0 */ |
592d1631 L |
6960 | { Bad_Opcode }, |
6961 | { Bad_Opcode }, | |
6962 | { Bad_Opcode }, | |
6963 | { Bad_Opcode }, | |
6964 | { Bad_Opcode }, | |
6965 | { Bad_Opcode }, | |
6966 | { Bad_Opcode }, | |
6967 | { Bad_Opcode }, | |
5dd85c99 | 6968 | /* f8 */ |
592d1631 L |
6969 | { Bad_Opcode }, |
6970 | { Bad_Opcode }, | |
6971 | { Bad_Opcode }, | |
6972 | { Bad_Opcode }, | |
6973 | { Bad_Opcode }, | |
6974 | { Bad_Opcode }, | |
6975 | { Bad_Opcode }, | |
6976 | { Bad_Opcode }, | |
5dd85c99 SP |
6977 | }, |
6978 | /* XOP_09 */ | |
6979 | { | |
6980 | /* 00 */ | |
592d1631 | 6981 | { Bad_Opcode }, |
2a2a0f38 QN |
6982 | { REG_TABLE (REG_XOP_TBM_01) }, |
6983 | { REG_TABLE (REG_XOP_TBM_02) }, | |
592d1631 L |
6984 | { Bad_Opcode }, |
6985 | { Bad_Opcode }, | |
6986 | { Bad_Opcode }, | |
6987 | { Bad_Opcode }, | |
6988 | { Bad_Opcode }, | |
5dd85c99 | 6989 | /* 08 */ |
592d1631 L |
6990 | { Bad_Opcode }, |
6991 | { Bad_Opcode }, | |
6992 | { Bad_Opcode }, | |
6993 | { Bad_Opcode }, | |
6994 | { Bad_Opcode }, | |
6995 | { Bad_Opcode }, | |
6996 | { Bad_Opcode }, | |
6997 | { Bad_Opcode }, | |
5dd85c99 | 6998 | /* 10 */ |
592d1631 L |
6999 | { Bad_Opcode }, |
7000 | { Bad_Opcode }, | |
5dd85c99 | 7001 | { REG_TABLE (REG_XOP_LWPCB) }, |
592d1631 L |
7002 | { Bad_Opcode }, |
7003 | { Bad_Opcode }, | |
7004 | { Bad_Opcode }, | |
7005 | { Bad_Opcode }, | |
7006 | { Bad_Opcode }, | |
5dd85c99 | 7007 | /* 18 */ |
592d1631 L |
7008 | { Bad_Opcode }, |
7009 | { Bad_Opcode }, | |
7010 | { Bad_Opcode }, | |
7011 | { Bad_Opcode }, | |
7012 | { Bad_Opcode }, | |
7013 | { Bad_Opcode }, | |
7014 | { Bad_Opcode }, | |
7015 | { Bad_Opcode }, | |
5dd85c99 | 7016 | /* 20 */ |
592d1631 L |
7017 | { Bad_Opcode }, |
7018 | { Bad_Opcode }, | |
7019 | { Bad_Opcode }, | |
7020 | { Bad_Opcode }, | |
7021 | { Bad_Opcode }, | |
7022 | { Bad_Opcode }, | |
7023 | { Bad_Opcode }, | |
7024 | { Bad_Opcode }, | |
5dd85c99 | 7025 | /* 28 */ |
592d1631 L |
7026 | { Bad_Opcode }, |
7027 | { Bad_Opcode }, | |
7028 | { Bad_Opcode }, | |
7029 | { Bad_Opcode }, | |
7030 | { Bad_Opcode }, | |
7031 | { Bad_Opcode }, | |
7032 | { Bad_Opcode }, | |
7033 | { Bad_Opcode }, | |
5dd85c99 | 7034 | /* 30 */ |
592d1631 L |
7035 | { Bad_Opcode }, |
7036 | { Bad_Opcode }, | |
7037 | { Bad_Opcode }, | |
7038 | { Bad_Opcode }, | |
7039 | { Bad_Opcode }, | |
7040 | { Bad_Opcode }, | |
7041 | { Bad_Opcode }, | |
7042 | { Bad_Opcode }, | |
5dd85c99 | 7043 | /* 38 */ |
592d1631 L |
7044 | { Bad_Opcode }, |
7045 | { Bad_Opcode }, | |
7046 | { Bad_Opcode }, | |
7047 | { Bad_Opcode }, | |
7048 | { Bad_Opcode }, | |
7049 | { Bad_Opcode }, | |
7050 | { Bad_Opcode }, | |
7051 | { Bad_Opcode }, | |
5dd85c99 | 7052 | /* 40 */ |
592d1631 L |
7053 | { Bad_Opcode }, |
7054 | { Bad_Opcode }, | |
7055 | { Bad_Opcode }, | |
7056 | { Bad_Opcode }, | |
7057 | { Bad_Opcode }, | |
7058 | { Bad_Opcode }, | |
7059 | { Bad_Opcode }, | |
7060 | { Bad_Opcode }, | |
5dd85c99 | 7061 | /* 48 */ |
592d1631 L |
7062 | { Bad_Opcode }, |
7063 | { Bad_Opcode }, | |
7064 | { Bad_Opcode }, | |
7065 | { Bad_Opcode }, | |
7066 | { Bad_Opcode }, | |
7067 | { Bad_Opcode }, | |
7068 | { Bad_Opcode }, | |
7069 | { Bad_Opcode }, | |
5dd85c99 | 7070 | /* 50 */ |
592d1631 L |
7071 | { Bad_Opcode }, |
7072 | { Bad_Opcode }, | |
7073 | { Bad_Opcode }, | |
7074 | { Bad_Opcode }, | |
7075 | { Bad_Opcode }, | |
7076 | { Bad_Opcode }, | |
7077 | { Bad_Opcode }, | |
7078 | { Bad_Opcode }, | |
5dd85c99 | 7079 | /* 58 */ |
592d1631 L |
7080 | { Bad_Opcode }, |
7081 | { Bad_Opcode }, | |
7082 | { Bad_Opcode }, | |
7083 | { Bad_Opcode }, | |
7084 | { Bad_Opcode }, | |
7085 | { Bad_Opcode }, | |
7086 | { Bad_Opcode }, | |
7087 | { Bad_Opcode }, | |
5dd85c99 | 7088 | /* 60 */ |
592d1631 L |
7089 | { Bad_Opcode }, |
7090 | { Bad_Opcode }, | |
7091 | { Bad_Opcode }, | |
7092 | { Bad_Opcode }, | |
7093 | { Bad_Opcode }, | |
7094 | { Bad_Opcode }, | |
7095 | { Bad_Opcode }, | |
7096 | { Bad_Opcode }, | |
5dd85c99 | 7097 | /* 68 */ |
592d1631 L |
7098 | { Bad_Opcode }, |
7099 | { Bad_Opcode }, | |
7100 | { Bad_Opcode }, | |
7101 | { Bad_Opcode }, | |
7102 | { Bad_Opcode }, | |
7103 | { Bad_Opcode }, | |
7104 | { Bad_Opcode }, | |
7105 | { Bad_Opcode }, | |
5dd85c99 | 7106 | /* 70 */ |
592d1631 L |
7107 | { Bad_Opcode }, |
7108 | { Bad_Opcode }, | |
7109 | { Bad_Opcode }, | |
7110 | { Bad_Opcode }, | |
7111 | { Bad_Opcode }, | |
7112 | { Bad_Opcode }, | |
7113 | { Bad_Opcode }, | |
7114 | { Bad_Opcode }, | |
5dd85c99 | 7115 | /* 78 */ |
592d1631 L |
7116 | { Bad_Opcode }, |
7117 | { Bad_Opcode }, | |
7118 | { Bad_Opcode }, | |
7119 | { Bad_Opcode }, | |
7120 | { Bad_Opcode }, | |
7121 | { Bad_Opcode }, | |
7122 | { Bad_Opcode }, | |
7123 | { Bad_Opcode }, | |
5dd85c99 | 7124 | /* 80 */ |
592a252b L |
7125 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, |
7126 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, | |
5dd85c99 SP |
7127 | { "vfrczss", { XM, EXd } }, |
7128 | { "vfrczsd", { XM, EXq } }, | |
592d1631 L |
7129 | { Bad_Opcode }, |
7130 | { Bad_Opcode }, | |
7131 | { Bad_Opcode }, | |
7132 | { Bad_Opcode }, | |
5dd85c99 | 7133 | /* 88 */ |
592d1631 L |
7134 | { Bad_Opcode }, |
7135 | { Bad_Opcode }, | |
7136 | { Bad_Opcode }, | |
7137 | { Bad_Opcode }, | |
7138 | { Bad_Opcode }, | |
7139 | { Bad_Opcode }, | |
7140 | { Bad_Opcode }, | |
7141 | { Bad_Opcode }, | |
5dd85c99 SP |
7142 | /* 90 */ |
7143 | { "vprotb", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7144 | { "vprotw", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7145 | { "vprotd", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7146 | { "vprotq", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7147 | { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7148 | { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7149 | { "vpshld", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7150 | { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7151 | /* 98 */ | |
7152 | { "vpshab", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7153 | { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7154 | { "vpshad", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7155 | { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 } }, | |
592d1631 L |
7156 | { Bad_Opcode }, |
7157 | { Bad_Opcode }, | |
7158 | { Bad_Opcode }, | |
7159 | { Bad_Opcode }, | |
5dd85c99 | 7160 | /* a0 */ |
592d1631 L |
7161 | { Bad_Opcode }, |
7162 | { Bad_Opcode }, | |
7163 | { Bad_Opcode }, | |
7164 | { Bad_Opcode }, | |
7165 | { Bad_Opcode }, | |
7166 | { Bad_Opcode }, | |
7167 | { Bad_Opcode }, | |
7168 | { Bad_Opcode }, | |
5dd85c99 | 7169 | /* a8 */ |
592d1631 L |
7170 | { Bad_Opcode }, |
7171 | { Bad_Opcode }, | |
7172 | { Bad_Opcode }, | |
7173 | { Bad_Opcode }, | |
7174 | { Bad_Opcode }, | |
7175 | { Bad_Opcode }, | |
7176 | { Bad_Opcode }, | |
7177 | { Bad_Opcode }, | |
5dd85c99 | 7178 | /* b0 */ |
592d1631 L |
7179 | { Bad_Opcode }, |
7180 | { Bad_Opcode }, | |
7181 | { Bad_Opcode }, | |
7182 | { Bad_Opcode }, | |
7183 | { Bad_Opcode }, | |
7184 | { Bad_Opcode }, | |
7185 | { Bad_Opcode }, | |
7186 | { Bad_Opcode }, | |
5dd85c99 | 7187 | /* b8 */ |
592d1631 L |
7188 | { Bad_Opcode }, |
7189 | { Bad_Opcode }, | |
7190 | { Bad_Opcode }, | |
7191 | { Bad_Opcode }, | |
7192 | { Bad_Opcode }, | |
7193 | { Bad_Opcode }, | |
7194 | { Bad_Opcode }, | |
7195 | { Bad_Opcode }, | |
5dd85c99 | 7196 | /* c0 */ |
592d1631 | 7197 | { Bad_Opcode }, |
5dd85c99 SP |
7198 | { "vphaddbw", { XM, EXxmm } }, |
7199 | { "vphaddbd", { XM, EXxmm } }, | |
7200 | { "vphaddbq", { XM, EXxmm } }, | |
592d1631 L |
7201 | { Bad_Opcode }, |
7202 | { Bad_Opcode }, | |
5dd85c99 SP |
7203 | { "vphaddwd", { XM, EXxmm } }, |
7204 | { "vphaddwq", { XM, EXxmm } }, | |
7205 | /* c8 */ | |
592d1631 L |
7206 | { Bad_Opcode }, |
7207 | { Bad_Opcode }, | |
7208 | { Bad_Opcode }, | |
5dd85c99 | 7209 | { "vphadddq", { XM, EXxmm } }, |
592d1631 L |
7210 | { Bad_Opcode }, |
7211 | { Bad_Opcode }, | |
7212 | { Bad_Opcode }, | |
7213 | { Bad_Opcode }, | |
5dd85c99 | 7214 | /* d0 */ |
592d1631 | 7215 | { Bad_Opcode }, |
5dd85c99 SP |
7216 | { "vphaddubw", { XM, EXxmm } }, |
7217 | { "vphaddubd", { XM, EXxmm } }, | |
7218 | { "vphaddubq", { XM, EXxmm } }, | |
592d1631 L |
7219 | { Bad_Opcode }, |
7220 | { Bad_Opcode }, | |
5dd85c99 SP |
7221 | { "vphadduwd", { XM, EXxmm } }, |
7222 | { "vphadduwq", { XM, EXxmm } }, | |
7223 | /* d8 */ | |
592d1631 L |
7224 | { Bad_Opcode }, |
7225 | { Bad_Opcode }, | |
7226 | { Bad_Opcode }, | |
5dd85c99 | 7227 | { "vphaddudq", { XM, EXxmm } }, |
592d1631 L |
7228 | { Bad_Opcode }, |
7229 | { Bad_Opcode }, | |
7230 | { Bad_Opcode }, | |
7231 | { Bad_Opcode }, | |
5dd85c99 | 7232 | /* e0 */ |
592d1631 | 7233 | { Bad_Opcode }, |
5dd85c99 SP |
7234 | { "vphsubbw", { XM, EXxmm } }, |
7235 | { "vphsubwd", { XM, EXxmm } }, | |
7236 | { "vphsubdq", { XM, EXxmm } }, | |
592d1631 L |
7237 | { Bad_Opcode }, |
7238 | { Bad_Opcode }, | |
7239 | { Bad_Opcode }, | |
7240 | { Bad_Opcode }, | |
4e7d34a6 | 7241 | /* e8 */ |
592d1631 L |
7242 | { Bad_Opcode }, |
7243 | { Bad_Opcode }, | |
7244 | { Bad_Opcode }, | |
7245 | { Bad_Opcode }, | |
7246 | { Bad_Opcode }, | |
7247 | { Bad_Opcode }, | |
7248 | { Bad_Opcode }, | |
7249 | { Bad_Opcode }, | |
4e7d34a6 | 7250 | /* f0 */ |
592d1631 L |
7251 | { Bad_Opcode }, |
7252 | { Bad_Opcode }, | |
7253 | { Bad_Opcode }, | |
7254 | { Bad_Opcode }, | |
7255 | { Bad_Opcode }, | |
7256 | { Bad_Opcode }, | |
7257 | { Bad_Opcode }, | |
7258 | { Bad_Opcode }, | |
4e7d34a6 | 7259 | /* f8 */ |
592d1631 L |
7260 | { Bad_Opcode }, |
7261 | { Bad_Opcode }, | |
7262 | { Bad_Opcode }, | |
7263 | { Bad_Opcode }, | |
7264 | { Bad_Opcode }, | |
7265 | { Bad_Opcode }, | |
7266 | { Bad_Opcode }, | |
7267 | { Bad_Opcode }, | |
4e7d34a6 | 7268 | }, |
f88c9eb0 | 7269 | /* XOP_0A */ |
4e7d34a6 L |
7270 | { |
7271 | /* 00 */ | |
592d1631 L |
7272 | { Bad_Opcode }, |
7273 | { Bad_Opcode }, | |
7274 | { Bad_Opcode }, | |
7275 | { Bad_Opcode }, | |
7276 | { Bad_Opcode }, | |
7277 | { Bad_Opcode }, | |
7278 | { Bad_Opcode }, | |
7279 | { Bad_Opcode }, | |
4e7d34a6 | 7280 | /* 08 */ |
592d1631 L |
7281 | { Bad_Opcode }, |
7282 | { Bad_Opcode }, | |
7283 | { Bad_Opcode }, | |
7284 | { Bad_Opcode }, | |
7285 | { Bad_Opcode }, | |
7286 | { Bad_Opcode }, | |
7287 | { Bad_Opcode }, | |
7288 | { Bad_Opcode }, | |
4e7d34a6 | 7289 | /* 10 */ |
2a2a0f38 | 7290 | { "bextr", { Gv, Ev, Iq } }, |
592d1631 | 7291 | { Bad_Opcode }, |
f88c9eb0 | 7292 | { REG_TABLE (REG_XOP_LWP) }, |
592d1631 L |
7293 | { Bad_Opcode }, |
7294 | { Bad_Opcode }, | |
7295 | { Bad_Opcode }, | |
7296 | { Bad_Opcode }, | |
7297 | { Bad_Opcode }, | |
4e7d34a6 | 7298 | /* 18 */ |
592d1631 L |
7299 | { Bad_Opcode }, |
7300 | { Bad_Opcode }, | |
7301 | { Bad_Opcode }, | |
7302 | { Bad_Opcode }, | |
7303 | { Bad_Opcode }, | |
7304 | { Bad_Opcode }, | |
7305 | { Bad_Opcode }, | |
7306 | { Bad_Opcode }, | |
4e7d34a6 | 7307 | /* 20 */ |
592d1631 L |
7308 | { Bad_Opcode }, |
7309 | { Bad_Opcode }, | |
7310 | { Bad_Opcode }, | |
7311 | { Bad_Opcode }, | |
7312 | { Bad_Opcode }, | |
7313 | { Bad_Opcode }, | |
7314 | { Bad_Opcode }, | |
7315 | { Bad_Opcode }, | |
4e7d34a6 | 7316 | /* 28 */ |
592d1631 L |
7317 | { Bad_Opcode }, |
7318 | { Bad_Opcode }, | |
7319 | { Bad_Opcode }, | |
7320 | { Bad_Opcode }, | |
7321 | { Bad_Opcode }, | |
7322 | { Bad_Opcode }, | |
7323 | { Bad_Opcode }, | |
7324 | { Bad_Opcode }, | |
4e7d34a6 | 7325 | /* 30 */ |
592d1631 L |
7326 | { Bad_Opcode }, |
7327 | { Bad_Opcode }, | |
7328 | { Bad_Opcode }, | |
7329 | { Bad_Opcode }, | |
7330 | { Bad_Opcode }, | |
7331 | { Bad_Opcode }, | |
7332 | { Bad_Opcode }, | |
7333 | { Bad_Opcode }, | |
c0f3af97 | 7334 | /* 38 */ |
592d1631 L |
7335 | { Bad_Opcode }, |
7336 | { Bad_Opcode }, | |
7337 | { Bad_Opcode }, | |
7338 | { Bad_Opcode }, | |
7339 | { Bad_Opcode }, | |
7340 | { Bad_Opcode }, | |
7341 | { Bad_Opcode }, | |
7342 | { Bad_Opcode }, | |
c0f3af97 | 7343 | /* 40 */ |
592d1631 L |
7344 | { Bad_Opcode }, |
7345 | { Bad_Opcode }, | |
7346 | { Bad_Opcode }, | |
7347 | { Bad_Opcode }, | |
7348 | { Bad_Opcode }, | |
7349 | { Bad_Opcode }, | |
7350 | { Bad_Opcode }, | |
7351 | { Bad_Opcode }, | |
c1e679ec | 7352 | /* 48 */ |
592d1631 L |
7353 | { Bad_Opcode }, |
7354 | { Bad_Opcode }, | |
7355 | { Bad_Opcode }, | |
7356 | { Bad_Opcode }, | |
7357 | { Bad_Opcode }, | |
7358 | { Bad_Opcode }, | |
7359 | { Bad_Opcode }, | |
7360 | { Bad_Opcode }, | |
c1e679ec | 7361 | /* 50 */ |
592d1631 L |
7362 | { Bad_Opcode }, |
7363 | { Bad_Opcode }, | |
7364 | { Bad_Opcode }, | |
7365 | { Bad_Opcode }, | |
7366 | { Bad_Opcode }, | |
7367 | { Bad_Opcode }, | |
7368 | { Bad_Opcode }, | |
7369 | { Bad_Opcode }, | |
4e7d34a6 | 7370 | /* 58 */ |
592d1631 L |
7371 | { Bad_Opcode }, |
7372 | { Bad_Opcode }, | |
7373 | { Bad_Opcode }, | |
7374 | { Bad_Opcode }, | |
7375 | { Bad_Opcode }, | |
7376 | { Bad_Opcode }, | |
7377 | { Bad_Opcode }, | |
7378 | { Bad_Opcode }, | |
4e7d34a6 | 7379 | /* 60 */ |
592d1631 L |
7380 | { Bad_Opcode }, |
7381 | { Bad_Opcode }, | |
7382 | { Bad_Opcode }, | |
7383 | { Bad_Opcode }, | |
7384 | { Bad_Opcode }, | |
7385 | { Bad_Opcode }, | |
7386 | { Bad_Opcode }, | |
7387 | { Bad_Opcode }, | |
4e7d34a6 | 7388 | /* 68 */ |
592d1631 L |
7389 | { Bad_Opcode }, |
7390 | { Bad_Opcode }, | |
7391 | { Bad_Opcode }, | |
7392 | { Bad_Opcode }, | |
7393 | { Bad_Opcode }, | |
7394 | { Bad_Opcode }, | |
7395 | { Bad_Opcode }, | |
7396 | { Bad_Opcode }, | |
4e7d34a6 | 7397 | /* 70 */ |
592d1631 L |
7398 | { Bad_Opcode }, |
7399 | { Bad_Opcode }, | |
7400 | { Bad_Opcode }, | |
7401 | { Bad_Opcode }, | |
7402 | { Bad_Opcode }, | |
7403 | { Bad_Opcode }, | |
7404 | { Bad_Opcode }, | |
7405 | { Bad_Opcode }, | |
4e7d34a6 | 7406 | /* 78 */ |
592d1631 L |
7407 | { Bad_Opcode }, |
7408 | { Bad_Opcode }, | |
7409 | { Bad_Opcode }, | |
7410 | { Bad_Opcode }, | |
7411 | { Bad_Opcode }, | |
7412 | { Bad_Opcode }, | |
7413 | { Bad_Opcode }, | |
7414 | { Bad_Opcode }, | |
4e7d34a6 | 7415 | /* 80 */ |
592d1631 L |
7416 | { Bad_Opcode }, |
7417 | { Bad_Opcode }, | |
7418 | { Bad_Opcode }, | |
7419 | { Bad_Opcode }, | |
7420 | { Bad_Opcode }, | |
7421 | { Bad_Opcode }, | |
7422 | { Bad_Opcode }, | |
7423 | { Bad_Opcode }, | |
4e7d34a6 | 7424 | /* 88 */ |
592d1631 L |
7425 | { Bad_Opcode }, |
7426 | { Bad_Opcode }, | |
7427 | { Bad_Opcode }, | |
7428 | { Bad_Opcode }, | |
7429 | { Bad_Opcode }, | |
7430 | { Bad_Opcode }, | |
7431 | { Bad_Opcode }, | |
7432 | { Bad_Opcode }, | |
4e7d34a6 | 7433 | /* 90 */ |
592d1631 L |
7434 | { Bad_Opcode }, |
7435 | { Bad_Opcode }, | |
7436 | { Bad_Opcode }, | |
7437 | { Bad_Opcode }, | |
7438 | { Bad_Opcode }, | |
7439 | { Bad_Opcode }, | |
7440 | { Bad_Opcode }, | |
7441 | { Bad_Opcode }, | |
4e7d34a6 | 7442 | /* 98 */ |
592d1631 L |
7443 | { Bad_Opcode }, |
7444 | { Bad_Opcode }, | |
7445 | { Bad_Opcode }, | |
7446 | { Bad_Opcode }, | |
7447 | { Bad_Opcode }, | |
7448 | { Bad_Opcode }, | |
7449 | { Bad_Opcode }, | |
7450 | { Bad_Opcode }, | |
4e7d34a6 | 7451 | /* a0 */ |
592d1631 L |
7452 | { Bad_Opcode }, |
7453 | { Bad_Opcode }, | |
7454 | { Bad_Opcode }, | |
7455 | { Bad_Opcode }, | |
7456 | { Bad_Opcode }, | |
7457 | { Bad_Opcode }, | |
7458 | { Bad_Opcode }, | |
7459 | { Bad_Opcode }, | |
4e7d34a6 | 7460 | /* a8 */ |
592d1631 L |
7461 | { Bad_Opcode }, |
7462 | { Bad_Opcode }, | |
7463 | { Bad_Opcode }, | |
7464 | { Bad_Opcode }, | |
7465 | { Bad_Opcode }, | |
7466 | { Bad_Opcode }, | |
7467 | { Bad_Opcode }, | |
7468 | { Bad_Opcode }, | |
d5d7db8e | 7469 | /* b0 */ |
592d1631 L |
7470 | { Bad_Opcode }, |
7471 | { Bad_Opcode }, | |
7472 | { Bad_Opcode }, | |
7473 | { Bad_Opcode }, | |
7474 | { Bad_Opcode }, | |
7475 | { Bad_Opcode }, | |
7476 | { Bad_Opcode }, | |
7477 | { Bad_Opcode }, | |
85f10a01 | 7478 | /* b8 */ |
592d1631 L |
7479 | { Bad_Opcode }, |
7480 | { Bad_Opcode }, | |
7481 | { Bad_Opcode }, | |
7482 | { Bad_Opcode }, | |
7483 | { Bad_Opcode }, | |
7484 | { Bad_Opcode }, | |
7485 | { Bad_Opcode }, | |
7486 | { Bad_Opcode }, | |
85f10a01 | 7487 | /* c0 */ |
592d1631 L |
7488 | { Bad_Opcode }, |
7489 | { Bad_Opcode }, | |
7490 | { Bad_Opcode }, | |
7491 | { Bad_Opcode }, | |
7492 | { Bad_Opcode }, | |
7493 | { Bad_Opcode }, | |
7494 | { Bad_Opcode }, | |
7495 | { Bad_Opcode }, | |
85f10a01 | 7496 | /* c8 */ |
592d1631 L |
7497 | { Bad_Opcode }, |
7498 | { Bad_Opcode }, | |
7499 | { Bad_Opcode }, | |
7500 | { Bad_Opcode }, | |
7501 | { Bad_Opcode }, | |
7502 | { Bad_Opcode }, | |
7503 | { Bad_Opcode }, | |
7504 | { Bad_Opcode }, | |
85f10a01 | 7505 | /* d0 */ |
592d1631 L |
7506 | { Bad_Opcode }, |
7507 | { Bad_Opcode }, | |
7508 | { Bad_Opcode }, | |
7509 | { Bad_Opcode }, | |
7510 | { Bad_Opcode }, | |
7511 | { Bad_Opcode }, | |
7512 | { Bad_Opcode }, | |
7513 | { Bad_Opcode }, | |
85f10a01 | 7514 | /* d8 */ |
592d1631 L |
7515 | { Bad_Opcode }, |
7516 | { Bad_Opcode }, | |
7517 | { Bad_Opcode }, | |
7518 | { Bad_Opcode }, | |
7519 | { Bad_Opcode }, | |
7520 | { Bad_Opcode }, | |
7521 | { Bad_Opcode }, | |
7522 | { Bad_Opcode }, | |
85f10a01 | 7523 | /* e0 */ |
592d1631 L |
7524 | { Bad_Opcode }, |
7525 | { Bad_Opcode }, | |
7526 | { Bad_Opcode }, | |
7527 | { Bad_Opcode }, | |
7528 | { Bad_Opcode }, | |
7529 | { Bad_Opcode }, | |
7530 | { Bad_Opcode }, | |
7531 | { Bad_Opcode }, | |
85f10a01 | 7532 | /* e8 */ |
592d1631 L |
7533 | { Bad_Opcode }, |
7534 | { Bad_Opcode }, | |
7535 | { Bad_Opcode }, | |
7536 | { Bad_Opcode }, | |
7537 | { Bad_Opcode }, | |
7538 | { Bad_Opcode }, | |
7539 | { Bad_Opcode }, | |
7540 | { Bad_Opcode }, | |
85f10a01 | 7541 | /* f0 */ |
592d1631 L |
7542 | { Bad_Opcode }, |
7543 | { Bad_Opcode }, | |
7544 | { Bad_Opcode }, | |
7545 | { Bad_Opcode }, | |
7546 | { Bad_Opcode }, | |
7547 | { Bad_Opcode }, | |
7548 | { Bad_Opcode }, | |
7549 | { Bad_Opcode }, | |
85f10a01 | 7550 | /* f8 */ |
592d1631 L |
7551 | { Bad_Opcode }, |
7552 | { Bad_Opcode }, | |
7553 | { Bad_Opcode }, | |
7554 | { Bad_Opcode }, | |
7555 | { Bad_Opcode }, | |
7556 | { Bad_Opcode }, | |
7557 | { Bad_Opcode }, | |
7558 | { Bad_Opcode }, | |
85f10a01 | 7559 | }, |
c0f3af97 L |
7560 | }; |
7561 | ||
7562 | static const struct dis386 vex_table[][256] = { | |
7563 | /* VEX_0F */ | |
85f10a01 MM |
7564 | { |
7565 | /* 00 */ | |
592d1631 L |
7566 | { Bad_Opcode }, |
7567 | { Bad_Opcode }, | |
7568 | { Bad_Opcode }, | |
7569 | { Bad_Opcode }, | |
7570 | { Bad_Opcode }, | |
7571 | { Bad_Opcode }, | |
7572 | { Bad_Opcode }, | |
7573 | { Bad_Opcode }, | |
85f10a01 | 7574 | /* 08 */ |
592d1631 L |
7575 | { Bad_Opcode }, |
7576 | { Bad_Opcode }, | |
7577 | { Bad_Opcode }, | |
7578 | { Bad_Opcode }, | |
7579 | { Bad_Opcode }, | |
7580 | { Bad_Opcode }, | |
7581 | { Bad_Opcode }, | |
7582 | { Bad_Opcode }, | |
c0f3af97 | 7583 | /* 10 */ |
592a252b L |
7584 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
7585 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, | |
7586 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, | |
7587 | { MOD_TABLE (MOD_VEX_0F13) }, | |
7588 | { VEX_W_TABLE (VEX_W_0F14) }, | |
7589 | { VEX_W_TABLE (VEX_W_0F15) }, | |
7590 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, | |
7591 | { MOD_TABLE (MOD_VEX_0F17) }, | |
c0f3af97 | 7592 | /* 18 */ |
592d1631 L |
7593 | { Bad_Opcode }, |
7594 | { Bad_Opcode }, | |
7595 | { Bad_Opcode }, | |
7596 | { Bad_Opcode }, | |
7597 | { Bad_Opcode }, | |
7598 | { Bad_Opcode }, | |
7599 | { Bad_Opcode }, | |
7600 | { Bad_Opcode }, | |
c0f3af97 | 7601 | /* 20 */ |
592d1631 L |
7602 | { Bad_Opcode }, |
7603 | { Bad_Opcode }, | |
7604 | { Bad_Opcode }, | |
7605 | { Bad_Opcode }, | |
7606 | { Bad_Opcode }, | |
7607 | { Bad_Opcode }, | |
7608 | { Bad_Opcode }, | |
7609 | { Bad_Opcode }, | |
c0f3af97 | 7610 | /* 28 */ |
592a252b L |
7611 | { VEX_W_TABLE (VEX_W_0F28) }, |
7612 | { VEX_W_TABLE (VEX_W_0F29) }, | |
7613 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, | |
7614 | { MOD_TABLE (MOD_VEX_0F2B) }, | |
7615 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, | |
7616 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, | |
7617 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, | |
7618 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, | |
85f10a01 | 7619 | /* 30 */ |
592d1631 L |
7620 | { Bad_Opcode }, |
7621 | { Bad_Opcode }, | |
7622 | { Bad_Opcode }, | |
7623 | { Bad_Opcode }, | |
7624 | { Bad_Opcode }, | |
7625 | { Bad_Opcode }, | |
7626 | { Bad_Opcode }, | |
7627 | { Bad_Opcode }, | |
4e7d34a6 | 7628 | /* 38 */ |
592d1631 L |
7629 | { Bad_Opcode }, |
7630 | { Bad_Opcode }, | |
7631 | { Bad_Opcode }, | |
7632 | { Bad_Opcode }, | |
7633 | { Bad_Opcode }, | |
7634 | { Bad_Opcode }, | |
7635 | { Bad_Opcode }, | |
7636 | { Bad_Opcode }, | |
d5d7db8e | 7637 | /* 40 */ |
592d1631 L |
7638 | { Bad_Opcode }, |
7639 | { Bad_Opcode }, | |
7640 | { Bad_Opcode }, | |
7641 | { Bad_Opcode }, | |
7642 | { Bad_Opcode }, | |
7643 | { Bad_Opcode }, | |
7644 | { Bad_Opcode }, | |
7645 | { Bad_Opcode }, | |
85f10a01 | 7646 | /* 48 */ |
592d1631 L |
7647 | { Bad_Opcode }, |
7648 | { Bad_Opcode }, | |
7649 | { Bad_Opcode }, | |
7650 | { Bad_Opcode }, | |
7651 | { Bad_Opcode }, | |
7652 | { Bad_Opcode }, | |
7653 | { Bad_Opcode }, | |
7654 | { Bad_Opcode }, | |
d5d7db8e | 7655 | /* 50 */ |
592a252b L |
7656 | { MOD_TABLE (MOD_VEX_0F50) }, |
7657 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, | |
7658 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, | |
7659 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, | |
c0f3af97 L |
7660 | { "vandpX", { XM, Vex, EXx } }, |
7661 | { "vandnpX", { XM, Vex, EXx } }, | |
7662 | { "vorpX", { XM, Vex, EXx } }, | |
7663 | { "vxorpX", { XM, Vex, EXx } }, | |
7664 | /* 58 */ | |
592a252b L |
7665 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
7666 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, | |
7667 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, | |
7668 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, | |
7669 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, | |
7670 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, | |
7671 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, | |
7672 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, | |
c0f3af97 | 7673 | /* 60 */ |
592a252b L |
7674 | { PREFIX_TABLE (PREFIX_VEX_0F60) }, |
7675 | { PREFIX_TABLE (PREFIX_VEX_0F61) }, | |
7676 | { PREFIX_TABLE (PREFIX_VEX_0F62) }, | |
7677 | { PREFIX_TABLE (PREFIX_VEX_0F63) }, | |
7678 | { PREFIX_TABLE (PREFIX_VEX_0F64) }, | |
7679 | { PREFIX_TABLE (PREFIX_VEX_0F65) }, | |
7680 | { PREFIX_TABLE (PREFIX_VEX_0F66) }, | |
7681 | { PREFIX_TABLE (PREFIX_VEX_0F67) }, | |
c0f3af97 | 7682 | /* 68 */ |
592a252b L |
7683 | { PREFIX_TABLE (PREFIX_VEX_0F68) }, |
7684 | { PREFIX_TABLE (PREFIX_VEX_0F69) }, | |
7685 | { PREFIX_TABLE (PREFIX_VEX_0F6A) }, | |
7686 | { PREFIX_TABLE (PREFIX_VEX_0F6B) }, | |
7687 | { PREFIX_TABLE (PREFIX_VEX_0F6C) }, | |
7688 | { PREFIX_TABLE (PREFIX_VEX_0F6D) }, | |
7689 | { PREFIX_TABLE (PREFIX_VEX_0F6E) }, | |
7690 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, | |
c0f3af97 | 7691 | /* 70 */ |
592a252b L |
7692 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
7693 | { REG_TABLE (REG_VEX_0F71) }, | |
7694 | { REG_TABLE (REG_VEX_0F72) }, | |
7695 | { REG_TABLE (REG_VEX_0F73) }, | |
7696 | { PREFIX_TABLE (PREFIX_VEX_0F74) }, | |
7697 | { PREFIX_TABLE (PREFIX_VEX_0F75) }, | |
7698 | { PREFIX_TABLE (PREFIX_VEX_0F76) }, | |
7699 | { PREFIX_TABLE (PREFIX_VEX_0F77) }, | |
c0f3af97 | 7700 | /* 78 */ |
592d1631 L |
7701 | { Bad_Opcode }, |
7702 | { Bad_Opcode }, | |
7703 | { Bad_Opcode }, | |
7704 | { Bad_Opcode }, | |
592a252b L |
7705 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
7706 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, | |
7707 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, | |
7708 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, | |
c0f3af97 | 7709 | /* 80 */ |
592d1631 L |
7710 | { Bad_Opcode }, |
7711 | { Bad_Opcode }, | |
7712 | { Bad_Opcode }, | |
7713 | { Bad_Opcode }, | |
7714 | { Bad_Opcode }, | |
7715 | { Bad_Opcode }, | |
7716 | { Bad_Opcode }, | |
7717 | { Bad_Opcode }, | |
c0f3af97 | 7718 | /* 88 */ |
592d1631 L |
7719 | { Bad_Opcode }, |
7720 | { Bad_Opcode }, | |
7721 | { Bad_Opcode }, | |
7722 | { Bad_Opcode }, | |
7723 | { Bad_Opcode }, | |
7724 | { Bad_Opcode }, | |
7725 | { Bad_Opcode }, | |
7726 | { Bad_Opcode }, | |
c0f3af97 | 7727 | /* 90 */ |
592d1631 L |
7728 | { Bad_Opcode }, |
7729 | { Bad_Opcode }, | |
7730 | { Bad_Opcode }, | |
7731 | { Bad_Opcode }, | |
7732 | { Bad_Opcode }, | |
7733 | { Bad_Opcode }, | |
7734 | { Bad_Opcode }, | |
7735 | { Bad_Opcode }, | |
c0f3af97 | 7736 | /* 98 */ |
592d1631 L |
7737 | { Bad_Opcode }, |
7738 | { Bad_Opcode }, | |
7739 | { Bad_Opcode }, | |
7740 | { Bad_Opcode }, | |
7741 | { Bad_Opcode }, | |
7742 | { Bad_Opcode }, | |
7743 | { Bad_Opcode }, | |
7744 | { Bad_Opcode }, | |
c0f3af97 | 7745 | /* a0 */ |
592d1631 L |
7746 | { Bad_Opcode }, |
7747 | { Bad_Opcode }, | |
7748 | { Bad_Opcode }, | |
7749 | { Bad_Opcode }, | |
7750 | { Bad_Opcode }, | |
7751 | { Bad_Opcode }, | |
7752 | { Bad_Opcode }, | |
7753 | { Bad_Opcode }, | |
c0f3af97 | 7754 | /* a8 */ |
592d1631 L |
7755 | { Bad_Opcode }, |
7756 | { Bad_Opcode }, | |
7757 | { Bad_Opcode }, | |
7758 | { Bad_Opcode }, | |
7759 | { Bad_Opcode }, | |
7760 | { Bad_Opcode }, | |
592a252b | 7761 | { REG_TABLE (REG_VEX_0FAE) }, |
592d1631 | 7762 | { Bad_Opcode }, |
c0f3af97 | 7763 | /* b0 */ |
592d1631 L |
7764 | { Bad_Opcode }, |
7765 | { Bad_Opcode }, | |
7766 | { Bad_Opcode }, | |
7767 | { Bad_Opcode }, | |
7768 | { Bad_Opcode }, | |
7769 | { Bad_Opcode }, | |
7770 | { Bad_Opcode }, | |
7771 | { Bad_Opcode }, | |
c0f3af97 | 7772 | /* b8 */ |
592d1631 L |
7773 | { Bad_Opcode }, |
7774 | { Bad_Opcode }, | |
7775 | { Bad_Opcode }, | |
7776 | { Bad_Opcode }, | |
7777 | { Bad_Opcode }, | |
7778 | { Bad_Opcode }, | |
7779 | { Bad_Opcode }, | |
7780 | { Bad_Opcode }, | |
c0f3af97 | 7781 | /* c0 */ |
592d1631 L |
7782 | { Bad_Opcode }, |
7783 | { Bad_Opcode }, | |
592a252b | 7784 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
592d1631 | 7785 | { Bad_Opcode }, |
592a252b L |
7786 | { PREFIX_TABLE (PREFIX_VEX_0FC4) }, |
7787 | { PREFIX_TABLE (PREFIX_VEX_0FC5) }, | |
c0f3af97 | 7788 | { "vshufpX", { XM, Vex, EXx, Ib } }, |
592d1631 | 7789 | { Bad_Opcode }, |
c0f3af97 | 7790 | /* c8 */ |
592d1631 L |
7791 | { Bad_Opcode }, |
7792 | { Bad_Opcode }, | |
7793 | { Bad_Opcode }, | |
7794 | { Bad_Opcode }, | |
7795 | { Bad_Opcode }, | |
7796 | { Bad_Opcode }, | |
7797 | { Bad_Opcode }, | |
7798 | { Bad_Opcode }, | |
c0f3af97 | 7799 | /* d0 */ |
592a252b L |
7800 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
7801 | { PREFIX_TABLE (PREFIX_VEX_0FD1) }, | |
7802 | { PREFIX_TABLE (PREFIX_VEX_0FD2) }, | |
7803 | { PREFIX_TABLE (PREFIX_VEX_0FD3) }, | |
7804 | { PREFIX_TABLE (PREFIX_VEX_0FD4) }, | |
7805 | { PREFIX_TABLE (PREFIX_VEX_0FD5) }, | |
7806 | { PREFIX_TABLE (PREFIX_VEX_0FD6) }, | |
7807 | { PREFIX_TABLE (PREFIX_VEX_0FD7) }, | |
c0f3af97 | 7808 | /* d8 */ |
592a252b L |
7809 | { PREFIX_TABLE (PREFIX_VEX_0FD8) }, |
7810 | { PREFIX_TABLE (PREFIX_VEX_0FD9) }, | |
7811 | { PREFIX_TABLE (PREFIX_VEX_0FDA) }, | |
7812 | { PREFIX_TABLE (PREFIX_VEX_0FDB) }, | |
7813 | { PREFIX_TABLE (PREFIX_VEX_0FDC) }, | |
7814 | { PREFIX_TABLE (PREFIX_VEX_0FDD) }, | |
7815 | { PREFIX_TABLE (PREFIX_VEX_0FDE) }, | |
7816 | { PREFIX_TABLE (PREFIX_VEX_0FDF) }, | |
c0f3af97 | 7817 | /* e0 */ |
592a252b L |
7818 | { PREFIX_TABLE (PREFIX_VEX_0FE0) }, |
7819 | { PREFIX_TABLE (PREFIX_VEX_0FE1) }, | |
7820 | { PREFIX_TABLE (PREFIX_VEX_0FE2) }, | |
7821 | { PREFIX_TABLE (PREFIX_VEX_0FE3) }, | |
7822 | { PREFIX_TABLE (PREFIX_VEX_0FE4) }, | |
7823 | { PREFIX_TABLE (PREFIX_VEX_0FE5) }, | |
7824 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, | |
7825 | { PREFIX_TABLE (PREFIX_VEX_0FE7) }, | |
c0f3af97 | 7826 | /* e8 */ |
592a252b L |
7827 | { PREFIX_TABLE (PREFIX_VEX_0FE8) }, |
7828 | { PREFIX_TABLE (PREFIX_VEX_0FE9) }, | |
7829 | { PREFIX_TABLE (PREFIX_VEX_0FEA) }, | |
7830 | { PREFIX_TABLE (PREFIX_VEX_0FEB) }, | |
7831 | { PREFIX_TABLE (PREFIX_VEX_0FEC) }, | |
7832 | { PREFIX_TABLE (PREFIX_VEX_0FED) }, | |
7833 | { PREFIX_TABLE (PREFIX_VEX_0FEE) }, | |
7834 | { PREFIX_TABLE (PREFIX_VEX_0FEF) }, | |
c0f3af97 | 7835 | /* f0 */ |
592a252b L |
7836 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
7837 | { PREFIX_TABLE (PREFIX_VEX_0FF1) }, | |
7838 | { PREFIX_TABLE (PREFIX_VEX_0FF2) }, | |
7839 | { PREFIX_TABLE (PREFIX_VEX_0FF3) }, | |
7840 | { PREFIX_TABLE (PREFIX_VEX_0FF4) }, | |
7841 | { PREFIX_TABLE (PREFIX_VEX_0FF5) }, | |
7842 | { PREFIX_TABLE (PREFIX_VEX_0FF6) }, | |
7843 | { PREFIX_TABLE (PREFIX_VEX_0FF7) }, | |
c0f3af97 | 7844 | /* f8 */ |
592a252b L |
7845 | { PREFIX_TABLE (PREFIX_VEX_0FF8) }, |
7846 | { PREFIX_TABLE (PREFIX_VEX_0FF9) }, | |
7847 | { PREFIX_TABLE (PREFIX_VEX_0FFA) }, | |
7848 | { PREFIX_TABLE (PREFIX_VEX_0FFB) }, | |
7849 | { PREFIX_TABLE (PREFIX_VEX_0FFC) }, | |
7850 | { PREFIX_TABLE (PREFIX_VEX_0FFD) }, | |
7851 | { PREFIX_TABLE (PREFIX_VEX_0FFE) }, | |
592d1631 | 7852 | { Bad_Opcode }, |
c0f3af97 L |
7853 | }, |
7854 | /* VEX_0F38 */ | |
7855 | { | |
7856 | /* 00 */ | |
592a252b L |
7857 | { PREFIX_TABLE (PREFIX_VEX_0F3800) }, |
7858 | { PREFIX_TABLE (PREFIX_VEX_0F3801) }, | |
7859 | { PREFIX_TABLE (PREFIX_VEX_0F3802) }, | |
7860 | { PREFIX_TABLE (PREFIX_VEX_0F3803) }, | |
7861 | { PREFIX_TABLE (PREFIX_VEX_0F3804) }, | |
7862 | { PREFIX_TABLE (PREFIX_VEX_0F3805) }, | |
7863 | { PREFIX_TABLE (PREFIX_VEX_0F3806) }, | |
7864 | { PREFIX_TABLE (PREFIX_VEX_0F3807) }, | |
c0f3af97 | 7865 | /* 08 */ |
592a252b L |
7866 | { PREFIX_TABLE (PREFIX_VEX_0F3808) }, |
7867 | { PREFIX_TABLE (PREFIX_VEX_0F3809) }, | |
7868 | { PREFIX_TABLE (PREFIX_VEX_0F380A) }, | |
7869 | { PREFIX_TABLE (PREFIX_VEX_0F380B) }, | |
7870 | { PREFIX_TABLE (PREFIX_VEX_0F380C) }, | |
7871 | { PREFIX_TABLE (PREFIX_VEX_0F380D) }, | |
7872 | { PREFIX_TABLE (PREFIX_VEX_0F380E) }, | |
7873 | { PREFIX_TABLE (PREFIX_VEX_0F380F) }, | |
c0f3af97 | 7874 | /* 10 */ |
592d1631 L |
7875 | { Bad_Opcode }, |
7876 | { Bad_Opcode }, | |
7877 | { Bad_Opcode }, | |
592a252b | 7878 | { PREFIX_TABLE (PREFIX_VEX_0F3813) }, |
592d1631 L |
7879 | { Bad_Opcode }, |
7880 | { Bad_Opcode }, | |
6c30d220 | 7881 | { PREFIX_TABLE (PREFIX_VEX_0F3816) }, |
592a252b | 7882 | { PREFIX_TABLE (PREFIX_VEX_0F3817) }, |
c0f3af97 | 7883 | /* 18 */ |
592a252b L |
7884 | { PREFIX_TABLE (PREFIX_VEX_0F3818) }, |
7885 | { PREFIX_TABLE (PREFIX_VEX_0F3819) }, | |
7886 | { PREFIX_TABLE (PREFIX_VEX_0F381A) }, | |
592d1631 | 7887 | { Bad_Opcode }, |
592a252b L |
7888 | { PREFIX_TABLE (PREFIX_VEX_0F381C) }, |
7889 | { PREFIX_TABLE (PREFIX_VEX_0F381D) }, | |
7890 | { PREFIX_TABLE (PREFIX_VEX_0F381E) }, | |
592d1631 | 7891 | { Bad_Opcode }, |
c0f3af97 | 7892 | /* 20 */ |
592a252b L |
7893 | { PREFIX_TABLE (PREFIX_VEX_0F3820) }, |
7894 | { PREFIX_TABLE (PREFIX_VEX_0F3821) }, | |
7895 | { PREFIX_TABLE (PREFIX_VEX_0F3822) }, | |
7896 | { PREFIX_TABLE (PREFIX_VEX_0F3823) }, | |
7897 | { PREFIX_TABLE (PREFIX_VEX_0F3824) }, | |
7898 | { PREFIX_TABLE (PREFIX_VEX_0F3825) }, | |
592d1631 L |
7899 | { Bad_Opcode }, |
7900 | { Bad_Opcode }, | |
c0f3af97 | 7901 | /* 28 */ |
592a252b L |
7902 | { PREFIX_TABLE (PREFIX_VEX_0F3828) }, |
7903 | { PREFIX_TABLE (PREFIX_VEX_0F3829) }, | |
7904 | { PREFIX_TABLE (PREFIX_VEX_0F382A) }, | |
7905 | { PREFIX_TABLE (PREFIX_VEX_0F382B) }, | |
7906 | { PREFIX_TABLE (PREFIX_VEX_0F382C) }, | |
7907 | { PREFIX_TABLE (PREFIX_VEX_0F382D) }, | |
7908 | { PREFIX_TABLE (PREFIX_VEX_0F382E) }, | |
7909 | { PREFIX_TABLE (PREFIX_VEX_0F382F) }, | |
c0f3af97 | 7910 | /* 30 */ |
592a252b L |
7911 | { PREFIX_TABLE (PREFIX_VEX_0F3830) }, |
7912 | { PREFIX_TABLE (PREFIX_VEX_0F3831) }, | |
7913 | { PREFIX_TABLE (PREFIX_VEX_0F3832) }, | |
7914 | { PREFIX_TABLE (PREFIX_VEX_0F3833) }, | |
7915 | { PREFIX_TABLE (PREFIX_VEX_0F3834) }, | |
7916 | { PREFIX_TABLE (PREFIX_VEX_0F3835) }, | |
6c30d220 | 7917 | { PREFIX_TABLE (PREFIX_VEX_0F3836) }, |
592a252b | 7918 | { PREFIX_TABLE (PREFIX_VEX_0F3837) }, |
c0f3af97 | 7919 | /* 38 */ |
592a252b L |
7920 | { PREFIX_TABLE (PREFIX_VEX_0F3838) }, |
7921 | { PREFIX_TABLE (PREFIX_VEX_0F3839) }, | |
7922 | { PREFIX_TABLE (PREFIX_VEX_0F383A) }, | |
7923 | { PREFIX_TABLE (PREFIX_VEX_0F383B) }, | |
7924 | { PREFIX_TABLE (PREFIX_VEX_0F383C) }, | |
7925 | { PREFIX_TABLE (PREFIX_VEX_0F383D) }, | |
7926 | { PREFIX_TABLE (PREFIX_VEX_0F383E) }, | |
7927 | { PREFIX_TABLE (PREFIX_VEX_0F383F) }, | |
c0f3af97 | 7928 | /* 40 */ |
592a252b L |
7929 | { PREFIX_TABLE (PREFIX_VEX_0F3840) }, |
7930 | { PREFIX_TABLE (PREFIX_VEX_0F3841) }, | |
592d1631 L |
7931 | { Bad_Opcode }, |
7932 | { Bad_Opcode }, | |
7933 | { Bad_Opcode }, | |
6c30d220 L |
7934 | { PREFIX_TABLE (PREFIX_VEX_0F3845) }, |
7935 | { PREFIX_TABLE (PREFIX_VEX_0F3846) }, | |
7936 | { PREFIX_TABLE (PREFIX_VEX_0F3847) }, | |
c0f3af97 | 7937 | /* 48 */ |
592d1631 L |
7938 | { Bad_Opcode }, |
7939 | { Bad_Opcode }, | |
7940 | { Bad_Opcode }, | |
7941 | { Bad_Opcode }, | |
7942 | { Bad_Opcode }, | |
7943 | { Bad_Opcode }, | |
7944 | { Bad_Opcode }, | |
7945 | { Bad_Opcode }, | |
c0f3af97 | 7946 | /* 50 */ |
592d1631 L |
7947 | { Bad_Opcode }, |
7948 | { Bad_Opcode }, | |
7949 | { Bad_Opcode }, | |
7950 | { Bad_Opcode }, | |
7951 | { Bad_Opcode }, | |
7952 | { Bad_Opcode }, | |
7953 | { Bad_Opcode }, | |
7954 | { Bad_Opcode }, | |
c0f3af97 | 7955 | /* 58 */ |
6c30d220 L |
7956 | { PREFIX_TABLE (PREFIX_VEX_0F3858) }, |
7957 | { PREFIX_TABLE (PREFIX_VEX_0F3859) }, | |
7958 | { PREFIX_TABLE (PREFIX_VEX_0F385A) }, | |
592d1631 L |
7959 | { Bad_Opcode }, |
7960 | { Bad_Opcode }, | |
7961 | { Bad_Opcode }, | |
7962 | { Bad_Opcode }, | |
7963 | { Bad_Opcode }, | |
c0f3af97 | 7964 | /* 60 */ |
592d1631 L |
7965 | { Bad_Opcode }, |
7966 | { Bad_Opcode }, | |
7967 | { Bad_Opcode }, | |
7968 | { Bad_Opcode }, | |
7969 | { Bad_Opcode }, | |
7970 | { Bad_Opcode }, | |
7971 | { Bad_Opcode }, | |
7972 | { Bad_Opcode }, | |
c0f3af97 | 7973 | /* 68 */ |
592d1631 L |
7974 | { Bad_Opcode }, |
7975 | { Bad_Opcode }, | |
7976 | { Bad_Opcode }, | |
7977 | { Bad_Opcode }, | |
7978 | { Bad_Opcode }, | |
7979 | { Bad_Opcode }, | |
7980 | { Bad_Opcode }, | |
7981 | { Bad_Opcode }, | |
c0f3af97 | 7982 | /* 70 */ |
592d1631 L |
7983 | { Bad_Opcode }, |
7984 | { Bad_Opcode }, | |
7985 | { Bad_Opcode }, | |
7986 | { Bad_Opcode }, | |
7987 | { Bad_Opcode }, | |
7988 | { Bad_Opcode }, | |
7989 | { Bad_Opcode }, | |
7990 | { Bad_Opcode }, | |
c0f3af97 | 7991 | /* 78 */ |
6c30d220 L |
7992 | { PREFIX_TABLE (PREFIX_VEX_0F3878) }, |
7993 | { PREFIX_TABLE (PREFIX_VEX_0F3879) }, | |
592d1631 L |
7994 | { Bad_Opcode }, |
7995 | { Bad_Opcode }, | |
7996 | { Bad_Opcode }, | |
7997 | { Bad_Opcode }, | |
7998 | { Bad_Opcode }, | |
7999 | { Bad_Opcode }, | |
c0f3af97 | 8000 | /* 80 */ |
592d1631 L |
8001 | { Bad_Opcode }, |
8002 | { Bad_Opcode }, | |
8003 | { Bad_Opcode }, | |
8004 | { Bad_Opcode }, | |
8005 | { Bad_Opcode }, | |
8006 | { Bad_Opcode }, | |
8007 | { Bad_Opcode }, | |
8008 | { Bad_Opcode }, | |
c0f3af97 | 8009 | /* 88 */ |
592d1631 L |
8010 | { Bad_Opcode }, |
8011 | { Bad_Opcode }, | |
8012 | { Bad_Opcode }, | |
8013 | { Bad_Opcode }, | |
6c30d220 | 8014 | { PREFIX_TABLE (PREFIX_VEX_0F388C) }, |
592d1631 | 8015 | { Bad_Opcode }, |
6c30d220 | 8016 | { PREFIX_TABLE (PREFIX_VEX_0F388E) }, |
592d1631 | 8017 | { Bad_Opcode }, |
c0f3af97 | 8018 | /* 90 */ |
6c30d220 L |
8019 | { PREFIX_TABLE (PREFIX_VEX_0F3890) }, |
8020 | { PREFIX_TABLE (PREFIX_VEX_0F3891) }, | |
8021 | { PREFIX_TABLE (PREFIX_VEX_0F3892) }, | |
8022 | { PREFIX_TABLE (PREFIX_VEX_0F3893) }, | |
592d1631 L |
8023 | { Bad_Opcode }, |
8024 | { Bad_Opcode }, | |
592a252b L |
8025 | { PREFIX_TABLE (PREFIX_VEX_0F3896) }, |
8026 | { PREFIX_TABLE (PREFIX_VEX_0F3897) }, | |
c0f3af97 | 8027 | /* 98 */ |
592a252b L |
8028 | { PREFIX_TABLE (PREFIX_VEX_0F3898) }, |
8029 | { PREFIX_TABLE (PREFIX_VEX_0F3899) }, | |
8030 | { PREFIX_TABLE (PREFIX_VEX_0F389A) }, | |
8031 | { PREFIX_TABLE (PREFIX_VEX_0F389B) }, | |
8032 | { PREFIX_TABLE (PREFIX_VEX_0F389C) }, | |
8033 | { PREFIX_TABLE (PREFIX_VEX_0F389D) }, | |
8034 | { PREFIX_TABLE (PREFIX_VEX_0F389E) }, | |
8035 | { PREFIX_TABLE (PREFIX_VEX_0F389F) }, | |
c0f3af97 | 8036 | /* a0 */ |
592d1631 L |
8037 | { Bad_Opcode }, |
8038 | { Bad_Opcode }, | |
8039 | { Bad_Opcode }, | |
8040 | { Bad_Opcode }, | |
8041 | { Bad_Opcode }, | |
8042 | { Bad_Opcode }, | |
592a252b L |
8043 | { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, |
8044 | { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, | |
c0f3af97 | 8045 | /* a8 */ |
592a252b L |
8046 | { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, |
8047 | { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, | |
8048 | { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, | |
8049 | { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, | |
8050 | { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, | |
8051 | { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, | |
8052 | { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, | |
8053 | { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, | |
c0f3af97 | 8054 | /* b0 */ |
592d1631 L |
8055 | { Bad_Opcode }, |
8056 | { Bad_Opcode }, | |
8057 | { Bad_Opcode }, | |
8058 | { Bad_Opcode }, | |
8059 | { Bad_Opcode }, | |
8060 | { Bad_Opcode }, | |
592a252b L |
8061 | { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, |
8062 | { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, | |
c0f3af97 | 8063 | /* b8 */ |
592a252b L |
8064 | { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, |
8065 | { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, | |
8066 | { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, | |
8067 | { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, | |
8068 | { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, | |
8069 | { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, | |
8070 | { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, | |
8071 | { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, | |
c0f3af97 | 8072 | /* c0 */ |
592d1631 L |
8073 | { Bad_Opcode }, |
8074 | { Bad_Opcode }, | |
8075 | { Bad_Opcode }, | |
8076 | { Bad_Opcode }, | |
8077 | { Bad_Opcode }, | |
8078 | { Bad_Opcode }, | |
8079 | { Bad_Opcode }, | |
8080 | { Bad_Opcode }, | |
c0f3af97 | 8081 | /* c8 */ |
592d1631 L |
8082 | { Bad_Opcode }, |
8083 | { Bad_Opcode }, | |
8084 | { Bad_Opcode }, | |
8085 | { Bad_Opcode }, | |
8086 | { Bad_Opcode }, | |
8087 | { Bad_Opcode }, | |
8088 | { Bad_Opcode }, | |
8089 | { Bad_Opcode }, | |
c0f3af97 | 8090 | /* d0 */ |
592d1631 L |
8091 | { Bad_Opcode }, |
8092 | { Bad_Opcode }, | |
8093 | { Bad_Opcode }, | |
8094 | { Bad_Opcode }, | |
8095 | { Bad_Opcode }, | |
8096 | { Bad_Opcode }, | |
8097 | { Bad_Opcode }, | |
8098 | { Bad_Opcode }, | |
c0f3af97 | 8099 | /* d8 */ |
592d1631 L |
8100 | { Bad_Opcode }, |
8101 | { Bad_Opcode }, | |
8102 | { Bad_Opcode }, | |
592a252b L |
8103 | { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, |
8104 | { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, | |
8105 | { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, | |
8106 | { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, | |
8107 | { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, | |
c0f3af97 | 8108 | /* e0 */ |
592d1631 L |
8109 | { Bad_Opcode }, |
8110 | { Bad_Opcode }, | |
8111 | { Bad_Opcode }, | |
8112 | { Bad_Opcode }, | |
8113 | { Bad_Opcode }, | |
8114 | { Bad_Opcode }, | |
8115 | { Bad_Opcode }, | |
8116 | { Bad_Opcode }, | |
c0f3af97 | 8117 | /* e8 */ |
592d1631 L |
8118 | { Bad_Opcode }, |
8119 | { Bad_Opcode }, | |
8120 | { Bad_Opcode }, | |
8121 | { Bad_Opcode }, | |
8122 | { Bad_Opcode }, | |
8123 | { Bad_Opcode }, | |
8124 | { Bad_Opcode }, | |
8125 | { Bad_Opcode }, | |
c0f3af97 | 8126 | /* f0 */ |
592d1631 L |
8127 | { Bad_Opcode }, |
8128 | { Bad_Opcode }, | |
f12dc422 L |
8129 | { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, |
8130 | { REG_TABLE (REG_VEX_0F38F3) }, | |
592d1631 | 8131 | { Bad_Opcode }, |
6c30d220 L |
8132 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
8133 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, | |
f12dc422 | 8134 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
c0f3af97 | 8135 | /* f8 */ |
592d1631 L |
8136 | { Bad_Opcode }, |
8137 | { Bad_Opcode }, | |
8138 | { Bad_Opcode }, | |
8139 | { Bad_Opcode }, | |
8140 | { Bad_Opcode }, | |
8141 | { Bad_Opcode }, | |
8142 | { Bad_Opcode }, | |
8143 | { Bad_Opcode }, | |
c0f3af97 L |
8144 | }, |
8145 | /* VEX_0F3A */ | |
8146 | { | |
8147 | /* 00 */ | |
6c30d220 L |
8148 | { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, |
8149 | { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, | |
8150 | { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, | |
592d1631 | 8151 | { Bad_Opcode }, |
592a252b L |
8152 | { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, |
8153 | { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, | |
8154 | { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, | |
592d1631 | 8155 | { Bad_Opcode }, |
c0f3af97 | 8156 | /* 08 */ |
592a252b L |
8157 | { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, |
8158 | { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, | |
8159 | { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, | |
8160 | { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, | |
8161 | { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, | |
8162 | { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, | |
8163 | { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, | |
8164 | { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, | |
c0f3af97 | 8165 | /* 10 */ |
592d1631 L |
8166 | { Bad_Opcode }, |
8167 | { Bad_Opcode }, | |
8168 | { Bad_Opcode }, | |
8169 | { Bad_Opcode }, | |
592a252b L |
8170 | { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, |
8171 | { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, | |
8172 | { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, | |
8173 | { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, | |
c0f3af97 | 8174 | /* 18 */ |
592a252b L |
8175 | { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, |
8176 | { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, | |
592d1631 L |
8177 | { Bad_Opcode }, |
8178 | { Bad_Opcode }, | |
8179 | { Bad_Opcode }, | |
592a252b | 8180 | { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, |
592d1631 L |
8181 | { Bad_Opcode }, |
8182 | { Bad_Opcode }, | |
c0f3af97 | 8183 | /* 20 */ |
592a252b L |
8184 | { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, |
8185 | { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, | |
8186 | { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, | |
592d1631 L |
8187 | { Bad_Opcode }, |
8188 | { Bad_Opcode }, | |
8189 | { Bad_Opcode }, | |
8190 | { Bad_Opcode }, | |
8191 | { Bad_Opcode }, | |
c0f3af97 | 8192 | /* 28 */ |
592d1631 L |
8193 | { Bad_Opcode }, |
8194 | { Bad_Opcode }, | |
8195 | { Bad_Opcode }, | |
8196 | { Bad_Opcode }, | |
8197 | { Bad_Opcode }, | |
8198 | { Bad_Opcode }, | |
8199 | { Bad_Opcode }, | |
8200 | { Bad_Opcode }, | |
c0f3af97 | 8201 | /* 30 */ |
592d1631 L |
8202 | { Bad_Opcode }, |
8203 | { Bad_Opcode }, | |
8204 | { Bad_Opcode }, | |
8205 | { Bad_Opcode }, | |
8206 | { Bad_Opcode }, | |
8207 | { Bad_Opcode }, | |
8208 | { Bad_Opcode }, | |
8209 | { Bad_Opcode }, | |
c0f3af97 | 8210 | /* 38 */ |
6c30d220 L |
8211 | { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, |
8212 | { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, | |
592d1631 L |
8213 | { Bad_Opcode }, |
8214 | { Bad_Opcode }, | |
8215 | { Bad_Opcode }, | |
8216 | { Bad_Opcode }, | |
8217 | { Bad_Opcode }, | |
8218 | { Bad_Opcode }, | |
c0f3af97 | 8219 | /* 40 */ |
592a252b L |
8220 | { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, |
8221 | { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, | |
8222 | { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, | |
592d1631 | 8223 | { Bad_Opcode }, |
592a252b | 8224 | { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, |
592d1631 | 8225 | { Bad_Opcode }, |
6c30d220 | 8226 | { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, |
592d1631 | 8227 | { Bad_Opcode }, |
c0f3af97 | 8228 | /* 48 */ |
592a252b L |
8229 | { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, |
8230 | { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, | |
8231 | { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, | |
8232 | { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, | |
8233 | { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, | |
592d1631 L |
8234 | { Bad_Opcode }, |
8235 | { Bad_Opcode }, | |
8236 | { Bad_Opcode }, | |
c0f3af97 | 8237 | /* 50 */ |
592d1631 L |
8238 | { Bad_Opcode }, |
8239 | { Bad_Opcode }, | |
8240 | { Bad_Opcode }, | |
8241 | { Bad_Opcode }, | |
8242 | { Bad_Opcode }, | |
8243 | { Bad_Opcode }, | |
8244 | { Bad_Opcode }, | |
8245 | { Bad_Opcode }, | |
c0f3af97 | 8246 | /* 58 */ |
592d1631 L |
8247 | { Bad_Opcode }, |
8248 | { Bad_Opcode }, | |
8249 | { Bad_Opcode }, | |
8250 | { Bad_Opcode }, | |
592a252b L |
8251 | { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, |
8252 | { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, | |
8253 | { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, | |
8254 | { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, | |
c0f3af97 | 8255 | /* 60 */ |
592a252b L |
8256 | { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, |
8257 | { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, | |
8258 | { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, | |
8259 | { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, | |
592d1631 L |
8260 | { Bad_Opcode }, |
8261 | { Bad_Opcode }, | |
8262 | { Bad_Opcode }, | |
8263 | { Bad_Opcode }, | |
c0f3af97 | 8264 | /* 68 */ |
592a252b L |
8265 | { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, |
8266 | { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, | |
8267 | { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, | |
8268 | { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, | |
8269 | { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, | |
8270 | { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, | |
8271 | { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, | |
8272 | { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, | |
c0f3af97 | 8273 | /* 70 */ |
592d1631 L |
8274 | { Bad_Opcode }, |
8275 | { Bad_Opcode }, | |
8276 | { Bad_Opcode }, | |
8277 | { Bad_Opcode }, | |
8278 | { Bad_Opcode }, | |
8279 | { Bad_Opcode }, | |
8280 | { Bad_Opcode }, | |
8281 | { Bad_Opcode }, | |
c0f3af97 | 8282 | /* 78 */ |
592a252b L |
8283 | { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, |
8284 | { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, | |
8285 | { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, | |
8286 | { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, | |
8287 | { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, | |
8288 | { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, | |
8289 | { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, | |
8290 | { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, | |
c0f3af97 | 8291 | /* 80 */ |
592d1631 L |
8292 | { Bad_Opcode }, |
8293 | { Bad_Opcode }, | |
8294 | { Bad_Opcode }, | |
8295 | { Bad_Opcode }, | |
8296 | { Bad_Opcode }, | |
8297 | { Bad_Opcode }, | |
8298 | { Bad_Opcode }, | |
8299 | { Bad_Opcode }, | |
c0f3af97 | 8300 | /* 88 */ |
592d1631 L |
8301 | { Bad_Opcode }, |
8302 | { Bad_Opcode }, | |
8303 | { Bad_Opcode }, | |
8304 | { Bad_Opcode }, | |
8305 | { Bad_Opcode }, | |
8306 | { Bad_Opcode }, | |
8307 | { Bad_Opcode }, | |
8308 | { Bad_Opcode }, | |
c0f3af97 | 8309 | /* 90 */ |
592d1631 L |
8310 | { Bad_Opcode }, |
8311 | { Bad_Opcode }, | |
8312 | { Bad_Opcode }, | |
8313 | { Bad_Opcode }, | |
8314 | { Bad_Opcode }, | |
8315 | { Bad_Opcode }, | |
8316 | { Bad_Opcode }, | |
8317 | { Bad_Opcode }, | |
c0f3af97 | 8318 | /* 98 */ |
592d1631 L |
8319 | { Bad_Opcode }, |
8320 | { Bad_Opcode }, | |
8321 | { Bad_Opcode }, | |
8322 | { Bad_Opcode }, | |
8323 | { Bad_Opcode }, | |
8324 | { Bad_Opcode }, | |
8325 | { Bad_Opcode }, | |
8326 | { Bad_Opcode }, | |
c0f3af97 | 8327 | /* a0 */ |
592d1631 L |
8328 | { Bad_Opcode }, |
8329 | { Bad_Opcode }, | |
8330 | { Bad_Opcode }, | |
8331 | { Bad_Opcode }, | |
8332 | { Bad_Opcode }, | |
8333 | { Bad_Opcode }, | |
8334 | { Bad_Opcode }, | |
8335 | { Bad_Opcode }, | |
c0f3af97 | 8336 | /* a8 */ |
592d1631 L |
8337 | { Bad_Opcode }, |
8338 | { Bad_Opcode }, | |
8339 | { Bad_Opcode }, | |
8340 | { Bad_Opcode }, | |
8341 | { Bad_Opcode }, | |
8342 | { Bad_Opcode }, | |
8343 | { Bad_Opcode }, | |
8344 | { Bad_Opcode }, | |
c0f3af97 | 8345 | /* b0 */ |
592d1631 L |
8346 | { Bad_Opcode }, |
8347 | { Bad_Opcode }, | |
8348 | { Bad_Opcode }, | |
8349 | { Bad_Opcode }, | |
8350 | { Bad_Opcode }, | |
8351 | { Bad_Opcode }, | |
8352 | { Bad_Opcode }, | |
8353 | { Bad_Opcode }, | |
c0f3af97 | 8354 | /* b8 */ |
592d1631 L |
8355 | { Bad_Opcode }, |
8356 | { Bad_Opcode }, | |
8357 | { Bad_Opcode }, | |
8358 | { Bad_Opcode }, | |
8359 | { Bad_Opcode }, | |
8360 | { Bad_Opcode }, | |
8361 | { Bad_Opcode }, | |
8362 | { Bad_Opcode }, | |
c0f3af97 | 8363 | /* c0 */ |
592d1631 L |
8364 | { Bad_Opcode }, |
8365 | { Bad_Opcode }, | |
8366 | { Bad_Opcode }, | |
8367 | { Bad_Opcode }, | |
8368 | { Bad_Opcode }, | |
8369 | { Bad_Opcode }, | |
8370 | { Bad_Opcode }, | |
8371 | { Bad_Opcode }, | |
c0f3af97 | 8372 | /* c8 */ |
592d1631 L |
8373 | { Bad_Opcode }, |
8374 | { Bad_Opcode }, | |
8375 | { Bad_Opcode }, | |
8376 | { Bad_Opcode }, | |
8377 | { Bad_Opcode }, | |
8378 | { Bad_Opcode }, | |
8379 | { Bad_Opcode }, | |
8380 | { Bad_Opcode }, | |
c0f3af97 | 8381 | /* d0 */ |
592d1631 L |
8382 | { Bad_Opcode }, |
8383 | { Bad_Opcode }, | |
8384 | { Bad_Opcode }, | |
8385 | { Bad_Opcode }, | |
8386 | { Bad_Opcode }, | |
8387 | { Bad_Opcode }, | |
8388 | { Bad_Opcode }, | |
8389 | { Bad_Opcode }, | |
c0f3af97 | 8390 | /* d8 */ |
592d1631 L |
8391 | { Bad_Opcode }, |
8392 | { Bad_Opcode }, | |
8393 | { Bad_Opcode }, | |
8394 | { Bad_Opcode }, | |
8395 | { Bad_Opcode }, | |
8396 | { Bad_Opcode }, | |
8397 | { Bad_Opcode }, | |
592a252b | 8398 | { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, |
c0f3af97 | 8399 | /* e0 */ |
592d1631 L |
8400 | { Bad_Opcode }, |
8401 | { Bad_Opcode }, | |
8402 | { Bad_Opcode }, | |
8403 | { Bad_Opcode }, | |
8404 | { Bad_Opcode }, | |
8405 | { Bad_Opcode }, | |
8406 | { Bad_Opcode }, | |
8407 | { Bad_Opcode }, | |
c0f3af97 | 8408 | /* e8 */ |
592d1631 L |
8409 | { Bad_Opcode }, |
8410 | { Bad_Opcode }, | |
8411 | { Bad_Opcode }, | |
8412 | { Bad_Opcode }, | |
8413 | { Bad_Opcode }, | |
8414 | { Bad_Opcode }, | |
8415 | { Bad_Opcode }, | |
8416 | { Bad_Opcode }, | |
c0f3af97 | 8417 | /* f0 */ |
6c30d220 | 8418 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
592d1631 L |
8419 | { Bad_Opcode }, |
8420 | { Bad_Opcode }, | |
8421 | { Bad_Opcode }, | |
8422 | { Bad_Opcode }, | |
8423 | { Bad_Opcode }, | |
8424 | { Bad_Opcode }, | |
8425 | { Bad_Opcode }, | |
c0f3af97 | 8426 | /* f8 */ |
592d1631 L |
8427 | { Bad_Opcode }, |
8428 | { Bad_Opcode }, | |
8429 | { Bad_Opcode }, | |
8430 | { Bad_Opcode }, | |
8431 | { Bad_Opcode }, | |
8432 | { Bad_Opcode }, | |
8433 | { Bad_Opcode }, | |
8434 | { Bad_Opcode }, | |
c0f3af97 L |
8435 | }, |
8436 | }; | |
8437 | ||
8438 | static const struct dis386 vex_len_table[][2] = { | |
592a252b | 8439 | /* VEX_LEN_0F10_P_1 */ |
c0f3af97 | 8440 | { |
592a252b L |
8441 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, |
8442 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, | |
c0f3af97 L |
8443 | }, |
8444 | ||
592a252b | 8445 | /* VEX_LEN_0F10_P_3 */ |
c0f3af97 | 8446 | { |
592a252b L |
8447 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, |
8448 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, | |
c0f3af97 L |
8449 | }, |
8450 | ||
592a252b | 8451 | /* VEX_LEN_0F11_P_1 */ |
c0f3af97 | 8452 | { |
592a252b L |
8453 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, |
8454 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, | |
c0f3af97 L |
8455 | }, |
8456 | ||
592a252b | 8457 | /* VEX_LEN_0F11_P_3 */ |
c0f3af97 | 8458 | { |
592a252b L |
8459 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, |
8460 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, | |
c0f3af97 L |
8461 | }, |
8462 | ||
592a252b | 8463 | /* VEX_LEN_0F12_P_0_M_0 */ |
c0f3af97 | 8464 | { |
592a252b | 8465 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) }, |
c0f3af97 L |
8466 | }, |
8467 | ||
592a252b | 8468 | /* VEX_LEN_0F12_P_0_M_1 */ |
c0f3af97 | 8469 | { |
592a252b | 8470 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) }, |
c0f3af97 L |
8471 | }, |
8472 | ||
592a252b | 8473 | /* VEX_LEN_0F12_P_2 */ |
c0f3af97 | 8474 | { |
592a252b | 8475 | { VEX_W_TABLE (VEX_W_0F12_P_2) }, |
c0f3af97 L |
8476 | }, |
8477 | ||
592a252b | 8478 | /* VEX_LEN_0F13_M_0 */ |
c0f3af97 | 8479 | { |
592a252b | 8480 | { VEX_W_TABLE (VEX_W_0F13_M_0) }, |
c0f3af97 L |
8481 | }, |
8482 | ||
592a252b | 8483 | /* VEX_LEN_0F16_P_0_M_0 */ |
c0f3af97 | 8484 | { |
592a252b | 8485 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) }, |
c0f3af97 L |
8486 | }, |
8487 | ||
592a252b | 8488 | /* VEX_LEN_0F16_P_0_M_1 */ |
c0f3af97 | 8489 | { |
592a252b | 8490 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) }, |
c0f3af97 L |
8491 | }, |
8492 | ||
592a252b | 8493 | /* VEX_LEN_0F16_P_2 */ |
c0f3af97 | 8494 | { |
592a252b | 8495 | { VEX_W_TABLE (VEX_W_0F16_P_2) }, |
c0f3af97 L |
8496 | }, |
8497 | ||
592a252b | 8498 | /* VEX_LEN_0F17_M_0 */ |
c0f3af97 | 8499 | { |
592a252b | 8500 | { VEX_W_TABLE (VEX_W_0F17_M_0) }, |
c0f3af97 L |
8501 | }, |
8502 | ||
592a252b | 8503 | /* VEX_LEN_0F2A_P_1 */ |
c0f3af97 | 8504 | { |
539f890d L |
8505 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } }, |
8506 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } }, | |
c0f3af97 L |
8507 | }, |
8508 | ||
592a252b | 8509 | /* VEX_LEN_0F2A_P_3 */ |
c0f3af97 | 8510 | { |
539f890d L |
8511 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } }, |
8512 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } }, | |
c0f3af97 L |
8513 | }, |
8514 | ||
592a252b | 8515 | /* VEX_LEN_0F2C_P_1 */ |
c0f3af97 | 8516 | { |
539f890d L |
8517 | { "vcvttss2siY", { Gv, EXdScalar } }, |
8518 | { "vcvttss2siY", { Gv, EXdScalar } }, | |
c0f3af97 L |
8519 | }, |
8520 | ||
592a252b | 8521 | /* VEX_LEN_0F2C_P_3 */ |
c0f3af97 | 8522 | { |
539f890d L |
8523 | { "vcvttsd2siY", { Gv, EXqScalar } }, |
8524 | { "vcvttsd2siY", { Gv, EXqScalar } }, | |
c0f3af97 L |
8525 | }, |
8526 | ||
592a252b | 8527 | /* VEX_LEN_0F2D_P_1 */ |
c0f3af97 | 8528 | { |
539f890d L |
8529 | { "vcvtss2siY", { Gv, EXdScalar } }, |
8530 | { "vcvtss2siY", { Gv, EXdScalar } }, | |
c0f3af97 L |
8531 | }, |
8532 | ||
592a252b | 8533 | /* VEX_LEN_0F2D_P_3 */ |
c0f3af97 | 8534 | { |
539f890d L |
8535 | { "vcvtsd2siY", { Gv, EXqScalar } }, |
8536 | { "vcvtsd2siY", { Gv, EXqScalar } }, | |
c0f3af97 L |
8537 | }, |
8538 | ||
592a252b | 8539 | /* VEX_LEN_0F2E_P_0 */ |
c0f3af97 | 8540 | { |
592a252b L |
8541 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, |
8542 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, | |
c0f3af97 L |
8543 | }, |
8544 | ||
592a252b | 8545 | /* VEX_LEN_0F2E_P_2 */ |
c0f3af97 | 8546 | { |
592a252b L |
8547 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, |
8548 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, | |
c0f3af97 L |
8549 | }, |
8550 | ||
592a252b | 8551 | /* VEX_LEN_0F2F_P_0 */ |
c0f3af97 | 8552 | { |
592a252b L |
8553 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, |
8554 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, | |
c0f3af97 L |
8555 | }, |
8556 | ||
592a252b | 8557 | /* VEX_LEN_0F2F_P_2 */ |
c0f3af97 | 8558 | { |
592a252b L |
8559 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, |
8560 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, | |
c0f3af97 L |
8561 | }, |
8562 | ||
592a252b | 8563 | /* VEX_LEN_0F51_P_1 */ |
c0f3af97 | 8564 | { |
592a252b L |
8565 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, |
8566 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, | |
c0f3af97 L |
8567 | }, |
8568 | ||
592a252b | 8569 | /* VEX_LEN_0F51_P_3 */ |
c0f3af97 | 8570 | { |
592a252b L |
8571 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, |
8572 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, | |
c0f3af97 L |
8573 | }, |
8574 | ||
592a252b | 8575 | /* VEX_LEN_0F52_P_1 */ |
c0f3af97 | 8576 | { |
592a252b L |
8577 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, |
8578 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, | |
c0f3af97 L |
8579 | }, |
8580 | ||
592a252b | 8581 | /* VEX_LEN_0F53_P_1 */ |
c0f3af97 | 8582 | { |
592a252b L |
8583 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, |
8584 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, | |
c0f3af97 L |
8585 | }, |
8586 | ||
592a252b | 8587 | /* VEX_LEN_0F58_P_1 */ |
c0f3af97 | 8588 | { |
592a252b L |
8589 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, |
8590 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, | |
c0f3af97 L |
8591 | }, |
8592 | ||
592a252b | 8593 | /* VEX_LEN_0F58_P_3 */ |
c0f3af97 | 8594 | { |
592a252b L |
8595 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, |
8596 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, | |
c0f3af97 L |
8597 | }, |
8598 | ||
592a252b | 8599 | /* VEX_LEN_0F59_P_1 */ |
c0f3af97 | 8600 | { |
592a252b L |
8601 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, |
8602 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, | |
c0f3af97 L |
8603 | }, |
8604 | ||
592a252b | 8605 | /* VEX_LEN_0F59_P_3 */ |
c0f3af97 | 8606 | { |
592a252b L |
8607 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, |
8608 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, | |
c0f3af97 L |
8609 | }, |
8610 | ||
592a252b | 8611 | /* VEX_LEN_0F5A_P_1 */ |
c0f3af97 | 8612 | { |
592a252b L |
8613 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, |
8614 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, | |
c0f3af97 L |
8615 | }, |
8616 | ||
592a252b | 8617 | /* VEX_LEN_0F5A_P_3 */ |
c0f3af97 | 8618 | { |
592a252b L |
8619 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, |
8620 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, | |
c0f3af97 L |
8621 | }, |
8622 | ||
592a252b | 8623 | /* VEX_LEN_0F5C_P_1 */ |
c0f3af97 | 8624 | { |
592a252b L |
8625 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, |
8626 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, | |
c0f3af97 L |
8627 | }, |
8628 | ||
592a252b | 8629 | /* VEX_LEN_0F5C_P_3 */ |
c0f3af97 | 8630 | { |
592a252b L |
8631 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, |
8632 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, | |
c0f3af97 L |
8633 | }, |
8634 | ||
592a252b | 8635 | /* VEX_LEN_0F5D_P_1 */ |
c0f3af97 | 8636 | { |
592a252b L |
8637 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, |
8638 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, | |
c0f3af97 L |
8639 | }, |
8640 | ||
592a252b | 8641 | /* VEX_LEN_0F5D_P_3 */ |
c0f3af97 | 8642 | { |
592a252b L |
8643 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, |
8644 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, | |
c0f3af97 L |
8645 | }, |
8646 | ||
592a252b | 8647 | /* VEX_LEN_0F5E_P_1 */ |
c0f3af97 | 8648 | { |
592a252b L |
8649 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, |
8650 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, | |
c0f3af97 L |
8651 | }, |
8652 | ||
592a252b | 8653 | /* VEX_LEN_0F5E_P_3 */ |
c0f3af97 | 8654 | { |
592a252b L |
8655 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, |
8656 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, | |
c0f3af97 L |
8657 | }, |
8658 | ||
592a252b | 8659 | /* VEX_LEN_0F5F_P_1 */ |
c0f3af97 | 8660 | { |
592a252b L |
8661 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, |
8662 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, | |
c0f3af97 L |
8663 | }, |
8664 | ||
592a252b | 8665 | /* VEX_LEN_0F5F_P_3 */ |
c0f3af97 | 8666 | { |
592a252b L |
8667 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, |
8668 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, | |
c0f3af97 L |
8669 | }, |
8670 | ||
592a252b | 8671 | /* VEX_LEN_0F6E_P_2 */ |
c0f3af97 | 8672 | { |
539f890d L |
8673 | { "vmovK", { XMScalar, Edq } }, |
8674 | { "vmovK", { XMScalar, Edq } }, | |
c0f3af97 L |
8675 | }, |
8676 | ||
592a252b | 8677 | /* VEX_LEN_0F7E_P_1 */ |
c0f3af97 | 8678 | { |
592a252b L |
8679 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, |
8680 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, | |
c0f3af97 L |
8681 | }, |
8682 | ||
592a252b | 8683 | /* VEX_LEN_0F7E_P_2 */ |
c0f3af97 | 8684 | { |
539f890d | 8685 | { "vmovK", { Edq, XMScalar } }, |
6c30d220 | 8686 | { "vmovK", { Edq, XMScalar } }, |
c0f3af97 L |
8687 | }, |
8688 | ||
6c30d220 | 8689 | /* VEX_LEN_0FAE_R_2_M_0 */ |
c0f3af97 | 8690 | { |
6c30d220 | 8691 | { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) }, |
c0f3af97 L |
8692 | }, |
8693 | ||
6c30d220 | 8694 | /* VEX_LEN_0FAE_R_3_M_0 */ |
c0f3af97 | 8695 | { |
6c30d220 | 8696 | { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) }, |
c0f3af97 L |
8697 | }, |
8698 | ||
6c30d220 | 8699 | /* VEX_LEN_0FC2_P_1 */ |
c0f3af97 | 8700 | { |
6c30d220 L |
8701 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, |
8702 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, | |
c0f3af97 L |
8703 | }, |
8704 | ||
6c30d220 | 8705 | /* VEX_LEN_0FC2_P_3 */ |
c0f3af97 | 8706 | { |
6c30d220 L |
8707 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, |
8708 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, | |
c0f3af97 L |
8709 | }, |
8710 | ||
6c30d220 | 8711 | /* VEX_LEN_0FC4_P_2 */ |
c0f3af97 | 8712 | { |
6c30d220 | 8713 | { VEX_W_TABLE (VEX_W_0FC4_P_2) }, |
c0f3af97 L |
8714 | }, |
8715 | ||
6c30d220 | 8716 | /* VEX_LEN_0FC5_P_2 */ |
c0f3af97 | 8717 | { |
6c30d220 | 8718 | { VEX_W_TABLE (VEX_W_0FC5_P_2) }, |
c0f3af97 L |
8719 | }, |
8720 | ||
6c30d220 | 8721 | /* VEX_LEN_0FD6_P_2 */ |
c0f3af97 | 8722 | { |
6c30d220 L |
8723 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, |
8724 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, | |
c0f3af97 L |
8725 | }, |
8726 | ||
6c30d220 | 8727 | /* VEX_LEN_0FF7_P_2 */ |
c0f3af97 | 8728 | { |
6c30d220 | 8729 | { VEX_W_TABLE (VEX_W_0FF7_P_2) }, |
c0f3af97 L |
8730 | }, |
8731 | ||
6c30d220 | 8732 | /* VEX_LEN_0F3816_P_2 */ |
c0f3af97 | 8733 | { |
6c30d220 L |
8734 | { Bad_Opcode }, |
8735 | { VEX_W_TABLE (VEX_W_0F3816_P_2) }, | |
c0f3af97 L |
8736 | }, |
8737 | ||
6c30d220 | 8738 | /* VEX_LEN_0F3819_P_2 */ |
c0f3af97 | 8739 | { |
6c30d220 L |
8740 | { Bad_Opcode }, |
8741 | { VEX_W_TABLE (VEX_W_0F3819_P_2) }, | |
c0f3af97 L |
8742 | }, |
8743 | ||
6c30d220 | 8744 | /* VEX_LEN_0F381A_P_2_M_0 */ |
c0f3af97 | 8745 | { |
6c30d220 L |
8746 | { Bad_Opcode }, |
8747 | { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, | |
c0f3af97 L |
8748 | }, |
8749 | ||
6c30d220 | 8750 | /* VEX_LEN_0F3836_P_2 */ |
c0f3af97 | 8751 | { |
6c30d220 L |
8752 | { Bad_Opcode }, |
8753 | { VEX_W_TABLE (VEX_W_0F3836_P_2) }, | |
c0f3af97 L |
8754 | }, |
8755 | ||
592a252b | 8756 | /* VEX_LEN_0F3841_P_2 */ |
c0f3af97 | 8757 | { |
592a252b | 8758 | { VEX_W_TABLE (VEX_W_0F3841_P_2) }, |
c0f3af97 L |
8759 | }, |
8760 | ||
6c30d220 L |
8761 | /* VEX_LEN_0F385A_P_2_M_0 */ |
8762 | { | |
8763 | { Bad_Opcode }, | |
8764 | { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) }, | |
8765 | }, | |
8766 | ||
592a252b | 8767 | /* VEX_LEN_0F38DB_P_2 */ |
a5ff0eb2 | 8768 | { |
592a252b | 8769 | { VEX_W_TABLE (VEX_W_0F38DB_P_2) }, |
a5ff0eb2 L |
8770 | }, |
8771 | ||
592a252b | 8772 | /* VEX_LEN_0F38DC_P_2 */ |
a5ff0eb2 | 8773 | { |
592a252b | 8774 | { VEX_W_TABLE (VEX_W_0F38DC_P_2) }, |
a5ff0eb2 L |
8775 | }, |
8776 | ||
592a252b | 8777 | /* VEX_LEN_0F38DD_P_2 */ |
a5ff0eb2 | 8778 | { |
592a252b | 8779 | { VEX_W_TABLE (VEX_W_0F38DD_P_2) }, |
a5ff0eb2 L |
8780 | }, |
8781 | ||
592a252b | 8782 | /* VEX_LEN_0F38DE_P_2 */ |
a5ff0eb2 | 8783 | { |
592a252b | 8784 | { VEX_W_TABLE (VEX_W_0F38DE_P_2) }, |
a5ff0eb2 L |
8785 | }, |
8786 | ||
592a252b | 8787 | /* VEX_LEN_0F38DF_P_2 */ |
a5ff0eb2 | 8788 | { |
592a252b | 8789 | { VEX_W_TABLE (VEX_W_0F38DF_P_2) }, |
a5ff0eb2 L |
8790 | }, |
8791 | ||
f12dc422 L |
8792 | /* VEX_LEN_0F38F2_P_0 */ |
8793 | { | |
8794 | { "andnS", { Gdq, VexGdq, Edq } }, | |
8795 | }, | |
8796 | ||
8797 | /* VEX_LEN_0F38F3_R_1_P_0 */ | |
8798 | { | |
8799 | { "blsrS", { VexGdq, Edq } }, | |
8800 | }, | |
8801 | ||
8802 | /* VEX_LEN_0F38F3_R_2_P_0 */ | |
8803 | { | |
8804 | { "blsmskS", { VexGdq, Edq } }, | |
8805 | }, | |
8806 | ||
8807 | /* VEX_LEN_0F38F3_R_3_P_0 */ | |
8808 | { | |
8809 | { "blsiS", { VexGdq, Edq } }, | |
8810 | }, | |
8811 | ||
6c30d220 L |
8812 | /* VEX_LEN_0F38F5_P_0 */ |
8813 | { | |
8814 | { "bzhiS", { Gdq, Edq, VexGdq } }, | |
8815 | }, | |
8816 | ||
8817 | /* VEX_LEN_0F38F5_P_1 */ | |
8818 | { | |
8819 | { "pextS", { Gdq, VexGdq, Edq } }, | |
8820 | }, | |
8821 | ||
8822 | /* VEX_LEN_0F38F5_P_3 */ | |
8823 | { | |
8824 | { "pdepS", { Gdq, VexGdq, Edq } }, | |
8825 | }, | |
8826 | ||
8827 | /* VEX_LEN_0F38F6_P_3 */ | |
8828 | { | |
8829 | { "mulxS", { Gdq, VexGdq, Edq } }, | |
8830 | }, | |
8831 | ||
f12dc422 L |
8832 | /* VEX_LEN_0F38F7_P_0 */ |
8833 | { | |
8834 | { "bextrS", { Gdq, Edq, VexGdq } }, | |
8835 | }, | |
8836 | ||
6c30d220 L |
8837 | /* VEX_LEN_0F38F7_P_1 */ |
8838 | { | |
8839 | { "sarxS", { Gdq, Edq, VexGdq } }, | |
8840 | }, | |
8841 | ||
8842 | /* VEX_LEN_0F38F7_P_2 */ | |
8843 | { | |
8844 | { "shlxS", { Gdq, Edq, VexGdq } }, | |
8845 | }, | |
8846 | ||
8847 | /* VEX_LEN_0F38F7_P_3 */ | |
8848 | { | |
8849 | { "shrxS", { Gdq, Edq, VexGdq } }, | |
8850 | }, | |
8851 | ||
8852 | /* VEX_LEN_0F3A00_P_2 */ | |
8853 | { | |
8854 | { Bad_Opcode }, | |
8855 | { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, | |
8856 | }, | |
8857 | ||
8858 | /* VEX_LEN_0F3A01_P_2 */ | |
8859 | { | |
8860 | { Bad_Opcode }, | |
8861 | { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, | |
8862 | }, | |
8863 | ||
592a252b | 8864 | /* VEX_LEN_0F3A06_P_2 */ |
c0f3af97 | 8865 | { |
592d1631 | 8866 | { Bad_Opcode }, |
592a252b | 8867 | { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, |
c0f3af97 L |
8868 | }, |
8869 | ||
592a252b | 8870 | /* VEX_LEN_0F3A0A_P_2 */ |
c0f3af97 | 8871 | { |
592a252b L |
8872 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, |
8873 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, | |
c0f3af97 L |
8874 | }, |
8875 | ||
592a252b | 8876 | /* VEX_LEN_0F3A0B_P_2 */ |
c0f3af97 | 8877 | { |
592a252b L |
8878 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, |
8879 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, | |
c0f3af97 L |
8880 | }, |
8881 | ||
592a252b | 8882 | /* VEX_LEN_0F3A14_P_2 */ |
c0f3af97 | 8883 | { |
592a252b | 8884 | { VEX_W_TABLE (VEX_W_0F3A14_P_2) }, |
c0f3af97 L |
8885 | }, |
8886 | ||
592a252b | 8887 | /* VEX_LEN_0F3A15_P_2 */ |
c0f3af97 | 8888 | { |
592a252b | 8889 | { VEX_W_TABLE (VEX_W_0F3A15_P_2) }, |
c0f3af97 L |
8890 | }, |
8891 | ||
592a252b | 8892 | /* VEX_LEN_0F3A16_P_2 */ |
c0f3af97 L |
8893 | { |
8894 | { "vpextrK", { Edq, XM, Ib } }, | |
c0f3af97 L |
8895 | }, |
8896 | ||
592a252b | 8897 | /* VEX_LEN_0F3A17_P_2 */ |
c0f3af97 L |
8898 | { |
8899 | { "vextractps", { Edqd, XM, Ib } }, | |
c0f3af97 L |
8900 | }, |
8901 | ||
592a252b | 8902 | /* VEX_LEN_0F3A18_P_2 */ |
c0f3af97 | 8903 | { |
592d1631 | 8904 | { Bad_Opcode }, |
592a252b | 8905 | { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, |
c0f3af97 L |
8906 | }, |
8907 | ||
592a252b | 8908 | /* VEX_LEN_0F3A19_P_2 */ |
c0f3af97 | 8909 | { |
592d1631 | 8910 | { Bad_Opcode }, |
592a252b | 8911 | { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, |
c0f3af97 L |
8912 | }, |
8913 | ||
592a252b | 8914 | /* VEX_LEN_0F3A20_P_2 */ |
c0f3af97 | 8915 | { |
592a252b | 8916 | { VEX_W_TABLE (VEX_W_0F3A20_P_2) }, |
c0f3af97 L |
8917 | }, |
8918 | ||
592a252b | 8919 | /* VEX_LEN_0F3A21_P_2 */ |
c0f3af97 | 8920 | { |
592a252b | 8921 | { VEX_W_TABLE (VEX_W_0F3A21_P_2) }, |
c0f3af97 L |
8922 | }, |
8923 | ||
592a252b | 8924 | /* VEX_LEN_0F3A22_P_2 */ |
c0f3af97 L |
8925 | { |
8926 | { "vpinsrK", { XM, Vex128, Edq, Ib } }, | |
c0f3af97 L |
8927 | }, |
8928 | ||
6c30d220 | 8929 | /* VEX_LEN_0F3A38_P_2 */ |
c0f3af97 | 8930 | { |
6c30d220 L |
8931 | { Bad_Opcode }, |
8932 | { VEX_W_TABLE (VEX_W_0F3A38_P_2) }, | |
c0f3af97 L |
8933 | }, |
8934 | ||
6c30d220 | 8935 | /* VEX_LEN_0F3A39_P_2 */ |
c0f3af97 | 8936 | { |
6c30d220 L |
8937 | { Bad_Opcode }, |
8938 | { VEX_W_TABLE (VEX_W_0F3A39_P_2) }, | |
8939 | }, | |
8940 | ||
8941 | /* VEX_LEN_0F3A41_P_2 */ | |
8942 | { | |
8943 | { VEX_W_TABLE (VEX_W_0F3A41_P_2) }, | |
c0f3af97 L |
8944 | }, |
8945 | ||
592a252b | 8946 | /* VEX_LEN_0F3A44_P_2 */ |
ce2f5b3c | 8947 | { |
592a252b | 8948 | { VEX_W_TABLE (VEX_W_0F3A44_P_2) }, |
ce2f5b3c L |
8949 | }, |
8950 | ||
6c30d220 | 8951 | /* VEX_LEN_0F3A46_P_2 */ |
c0f3af97 | 8952 | { |
6c30d220 L |
8953 | { Bad_Opcode }, |
8954 | { VEX_W_TABLE (VEX_W_0F3A46_P_2) }, | |
c0f3af97 L |
8955 | }, |
8956 | ||
592a252b | 8957 | /* VEX_LEN_0F3A60_P_2 */ |
c0f3af97 | 8958 | { |
592a252b | 8959 | { VEX_W_TABLE (VEX_W_0F3A60_P_2) }, |
c0f3af97 L |
8960 | }, |
8961 | ||
592a252b | 8962 | /* VEX_LEN_0F3A61_P_2 */ |
c0f3af97 | 8963 | { |
592a252b | 8964 | { VEX_W_TABLE (VEX_W_0F3A61_P_2) }, |
c0f3af97 L |
8965 | }, |
8966 | ||
592a252b | 8967 | /* VEX_LEN_0F3A62_P_2 */ |
c0f3af97 | 8968 | { |
592a252b | 8969 | { VEX_W_TABLE (VEX_W_0F3A62_P_2) }, |
c0f3af97 L |
8970 | }, |
8971 | ||
592a252b | 8972 | /* VEX_LEN_0F3A63_P_2 */ |
c0f3af97 | 8973 | { |
592a252b | 8974 | { VEX_W_TABLE (VEX_W_0F3A63_P_2) }, |
c0f3af97 L |
8975 | }, |
8976 | ||
592a252b | 8977 | /* VEX_LEN_0F3A6A_P_2 */ |
922d8de8 | 8978 | { |
206c2556 | 8979 | { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
922d8de8 DR |
8980 | }, |
8981 | ||
592a252b | 8982 | /* VEX_LEN_0F3A6B_P_2 */ |
922d8de8 | 8983 | { |
206c2556 | 8984 | { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
922d8de8 DR |
8985 | }, |
8986 | ||
592a252b | 8987 | /* VEX_LEN_0F3A6E_P_2 */ |
922d8de8 | 8988 | { |
206c2556 | 8989 | { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
922d8de8 DR |
8990 | }, |
8991 | ||
592a252b | 8992 | /* VEX_LEN_0F3A6F_P_2 */ |
922d8de8 | 8993 | { |
206c2556 | 8994 | { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
922d8de8 DR |
8995 | }, |
8996 | ||
592a252b | 8997 | /* VEX_LEN_0F3A7A_P_2 */ |
922d8de8 | 8998 | { |
206c2556 | 8999 | { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
922d8de8 DR |
9000 | }, |
9001 | ||
592a252b | 9002 | /* VEX_LEN_0F3A7B_P_2 */ |
922d8de8 | 9003 | { |
206c2556 | 9004 | { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
922d8de8 DR |
9005 | }, |
9006 | ||
592a252b | 9007 | /* VEX_LEN_0F3A7E_P_2 */ |
922d8de8 | 9008 | { |
206c2556 | 9009 | { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
922d8de8 DR |
9010 | }, |
9011 | ||
592a252b | 9012 | /* VEX_LEN_0F3A7F_P_2 */ |
922d8de8 | 9013 | { |
206c2556 | 9014 | { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
922d8de8 DR |
9015 | }, |
9016 | ||
592a252b | 9017 | /* VEX_LEN_0F3ADF_P_2 */ |
a5ff0eb2 | 9018 | { |
592a252b | 9019 | { VEX_W_TABLE (VEX_W_0F3ADF_P_2) }, |
a5ff0eb2 | 9020 | }, |
4c807e72 | 9021 | |
6c30d220 L |
9022 | /* VEX_LEN_0F3AF0_P_3 */ |
9023 | { | |
182ae480 | 9024 | { "rorxS", { Gdq, Edq, Ib } }, |
6c30d220 L |
9025 | }, |
9026 | ||
ff688e1f L |
9027 | /* VEX_LEN_0FXOP_08_CC */ |
9028 | { | |
9029 | { "vpcomb", { XM, Vex128, EXx, Ib } }, | |
9030 | }, | |
9031 | ||
9032 | /* VEX_LEN_0FXOP_08_CD */ | |
9033 | { | |
9034 | { "vpcomw", { XM, Vex128, EXx, Ib } }, | |
9035 | }, | |
9036 | ||
9037 | /* VEX_LEN_0FXOP_08_CE */ | |
9038 | { | |
9039 | { "vpcomd", { XM, Vex128, EXx, Ib } }, | |
9040 | }, | |
9041 | ||
9042 | /* VEX_LEN_0FXOP_08_CF */ | |
9043 | { | |
9044 | { "vpcomq", { XM, Vex128, EXx, Ib } }, | |
9045 | }, | |
9046 | ||
9047 | /* VEX_LEN_0FXOP_08_EC */ | |
9048 | { | |
9049 | { "vpcomub", { XM, Vex128, EXx, Ib } }, | |
9050 | }, | |
9051 | ||
9052 | /* VEX_LEN_0FXOP_08_ED */ | |
9053 | { | |
9054 | { "vpcomuw", { XM, Vex128, EXx, Ib } }, | |
9055 | }, | |
9056 | ||
9057 | /* VEX_LEN_0FXOP_08_EE */ | |
9058 | { | |
9059 | { "vpcomud", { XM, Vex128, EXx, Ib } }, | |
9060 | }, | |
9061 | ||
9062 | /* VEX_LEN_0FXOP_08_EF */ | |
9063 | { | |
9064 | { "vpcomuq", { XM, Vex128, EXx, Ib } }, | |
9065 | }, | |
9066 | ||
592a252b | 9067 | /* VEX_LEN_0FXOP_09_80 */ |
5dd85c99 | 9068 | { |
4c807e72 L |
9069 | { "vfrczps", { XM, EXxmm } }, |
9070 | { "vfrczps", { XM, EXymmq } }, | |
5dd85c99 | 9071 | }, |
4c807e72 | 9072 | |
592a252b | 9073 | /* VEX_LEN_0FXOP_09_81 */ |
5dd85c99 | 9074 | { |
4c807e72 L |
9075 | { "vfrczpd", { XM, EXxmm } }, |
9076 | { "vfrczpd", { XM, EXymmq } }, | |
5dd85c99 | 9077 | }, |
331d2d0d L |
9078 | }; |
9079 | ||
9e30b8e0 | 9080 | static const struct dis386 vex_w_table[][2] = { |
b844680a | 9081 | { |
592a252b | 9082 | /* VEX_W_0F10_P_0 */ |
9e30b8e0 | 9083 | { "vmovups", { XM, EXx } }, |
d8faab4e L |
9084 | }, |
9085 | { | |
592a252b | 9086 | /* VEX_W_0F10_P_1 */ |
539f890d | 9087 | { "vmovss", { XMVexScalar, VexScalar, EXdScalar } }, |
d8faab4e L |
9088 | }, |
9089 | { | |
592a252b | 9090 | /* VEX_W_0F10_P_2 */ |
9e30b8e0 | 9091 | { "vmovupd", { XM, EXx } }, |
d8faab4e L |
9092 | }, |
9093 | { | |
592a252b | 9094 | /* VEX_W_0F10_P_3 */ |
539f890d | 9095 | { "vmovsd", { XMVexScalar, VexScalar, EXqScalar } }, |
d8faab4e L |
9096 | }, |
9097 | { | |
592a252b | 9098 | /* VEX_W_0F11_P_0 */ |
9e30b8e0 | 9099 | { "vmovups", { EXxS, XM } }, |
d8faab4e L |
9100 | }, |
9101 | { | |
592a252b | 9102 | /* VEX_W_0F11_P_1 */ |
539f890d | 9103 | { "vmovss", { EXdVexScalarS, VexScalar, XMScalar } }, |
b844680a L |
9104 | }, |
9105 | { | |
592a252b | 9106 | /* VEX_W_0F11_P_2 */ |
9e30b8e0 | 9107 | { "vmovupd", { EXxS, XM } }, |
b844680a L |
9108 | }, |
9109 | { | |
592a252b | 9110 | /* VEX_W_0F11_P_3 */ |
539f890d | 9111 | { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar } }, |
d8faab4e L |
9112 | }, |
9113 | { | |
592a252b | 9114 | /* VEX_W_0F12_P_0_M_0 */ |
9e30b8e0 | 9115 | { "vmovlps", { XM, Vex128, EXq } }, |
b844680a L |
9116 | }, |
9117 | { | |
592a252b | 9118 | /* VEX_W_0F12_P_0_M_1 */ |
9e30b8e0 | 9119 | { "vmovhlps", { XM, Vex128, EXq } }, |
b844680a L |
9120 | }, |
9121 | { | |
592a252b | 9122 | /* VEX_W_0F12_P_1 */ |
9e30b8e0 | 9123 | { "vmovsldup", { XM, EXx } }, |
b844680a L |
9124 | }, |
9125 | { | |
592a252b | 9126 | /* VEX_W_0F12_P_2 */ |
9e30b8e0 | 9127 | { "vmovlpd", { XM, Vex128, EXq } }, |
b844680a L |
9128 | }, |
9129 | { | |
592a252b | 9130 | /* VEX_W_0F12_P_3 */ |
9e30b8e0 | 9131 | { "vmovddup", { XM, EXymmq } }, |
b844680a L |
9132 | }, |
9133 | { | |
592a252b | 9134 | /* VEX_W_0F13_M_0 */ |
9e30b8e0 | 9135 | { "vmovlpX", { EXq, XM } }, |
b844680a L |
9136 | }, |
9137 | { | |
592a252b | 9138 | /* VEX_W_0F14 */ |
9e30b8e0 | 9139 | { "vunpcklpX", { XM, Vex, EXx } }, |
b844680a L |
9140 | }, |
9141 | { | |
592a252b | 9142 | /* VEX_W_0F15 */ |
9e30b8e0 | 9143 | { "vunpckhpX", { XM, Vex, EXx } }, |
b844680a L |
9144 | }, |
9145 | { | |
592a252b | 9146 | /* VEX_W_0F16_P_0_M_0 */ |
9e30b8e0 | 9147 | { "vmovhps", { XM, Vex128, EXq } }, |
9e30b8e0 L |
9148 | }, |
9149 | { | |
592a252b | 9150 | /* VEX_W_0F16_P_0_M_1 */ |
9e30b8e0 | 9151 | { "vmovlhps", { XM, Vex128, EXq } }, |
9e30b8e0 L |
9152 | }, |
9153 | { | |
592a252b | 9154 | /* VEX_W_0F16_P_1 */ |
9e30b8e0 | 9155 | { "vmovshdup", { XM, EXx } }, |
9e30b8e0 L |
9156 | }, |
9157 | { | |
592a252b | 9158 | /* VEX_W_0F16_P_2 */ |
9e30b8e0 | 9159 | { "vmovhpd", { XM, Vex128, EXq } }, |
9e30b8e0 L |
9160 | }, |
9161 | { | |
592a252b | 9162 | /* VEX_W_0F17_M_0 */ |
9e30b8e0 | 9163 | { "vmovhpX", { EXq, XM } }, |
9e30b8e0 L |
9164 | }, |
9165 | { | |
592a252b | 9166 | /* VEX_W_0F28 */ |
9e30b8e0 | 9167 | { "vmovapX", { XM, EXx } }, |
9e30b8e0 L |
9168 | }, |
9169 | { | |
592a252b | 9170 | /* VEX_W_0F29 */ |
9e30b8e0 | 9171 | { "vmovapX", { EXxS, XM } }, |
9e30b8e0 L |
9172 | }, |
9173 | { | |
592a252b | 9174 | /* VEX_W_0F2B_M_0 */ |
9e30b8e0 | 9175 | { "vmovntpX", { Mx, XM } }, |
9e30b8e0 L |
9176 | }, |
9177 | { | |
592a252b | 9178 | /* VEX_W_0F2E_P_0 */ |
7bb15c6f | 9179 | { "vucomiss", { XMScalar, EXdScalar } }, |
9e30b8e0 L |
9180 | }, |
9181 | { | |
592a252b | 9182 | /* VEX_W_0F2E_P_2 */ |
7bb15c6f | 9183 | { "vucomisd", { XMScalar, EXqScalar } }, |
9e30b8e0 L |
9184 | }, |
9185 | { | |
592a252b | 9186 | /* VEX_W_0F2F_P_0 */ |
539f890d | 9187 | { "vcomiss", { XMScalar, EXdScalar } }, |
9e30b8e0 L |
9188 | }, |
9189 | { | |
592a252b | 9190 | /* VEX_W_0F2F_P_2 */ |
539f890d | 9191 | { "vcomisd", { XMScalar, EXqScalar } }, |
9e30b8e0 L |
9192 | }, |
9193 | { | |
592a252b | 9194 | /* VEX_W_0F50_M_0 */ |
9e30b8e0 | 9195 | { "vmovmskpX", { Gdq, XS } }, |
9e30b8e0 L |
9196 | }, |
9197 | { | |
592a252b | 9198 | /* VEX_W_0F51_P_0 */ |
9e30b8e0 | 9199 | { "vsqrtps", { XM, EXx } }, |
9e30b8e0 L |
9200 | }, |
9201 | { | |
592a252b | 9202 | /* VEX_W_0F51_P_1 */ |
539f890d | 9203 | { "vsqrtss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
9204 | }, |
9205 | { | |
592a252b | 9206 | /* VEX_W_0F51_P_2 */ |
9e30b8e0 | 9207 | { "vsqrtpd", { XM, EXx } }, |
9e30b8e0 L |
9208 | }, |
9209 | { | |
592a252b | 9210 | /* VEX_W_0F51_P_3 */ |
539f890d | 9211 | { "vsqrtsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
9212 | }, |
9213 | { | |
592a252b | 9214 | /* VEX_W_0F52_P_0 */ |
9e30b8e0 | 9215 | { "vrsqrtps", { XM, EXx } }, |
9e30b8e0 L |
9216 | }, |
9217 | { | |
592a252b | 9218 | /* VEX_W_0F52_P_1 */ |
539f890d | 9219 | { "vrsqrtss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
9220 | }, |
9221 | { | |
592a252b | 9222 | /* VEX_W_0F53_P_0 */ |
9e30b8e0 | 9223 | { "vrcpps", { XM, EXx } }, |
9e30b8e0 L |
9224 | }, |
9225 | { | |
592a252b | 9226 | /* VEX_W_0F53_P_1 */ |
539f890d | 9227 | { "vrcpss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
9228 | }, |
9229 | { | |
592a252b | 9230 | /* VEX_W_0F58_P_0 */ |
9e30b8e0 | 9231 | { "vaddps", { XM, Vex, EXx } }, |
9e30b8e0 L |
9232 | }, |
9233 | { | |
592a252b | 9234 | /* VEX_W_0F58_P_1 */ |
539f890d | 9235 | { "vaddss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
9236 | }, |
9237 | { | |
592a252b | 9238 | /* VEX_W_0F58_P_2 */ |
9e30b8e0 | 9239 | { "vaddpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9240 | }, |
9241 | { | |
592a252b | 9242 | /* VEX_W_0F58_P_3 */ |
539f890d | 9243 | { "vaddsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
9244 | }, |
9245 | { | |
592a252b | 9246 | /* VEX_W_0F59_P_0 */ |
9e30b8e0 | 9247 | { "vmulps", { XM, Vex, EXx } }, |
9e30b8e0 L |
9248 | }, |
9249 | { | |
592a252b | 9250 | /* VEX_W_0F59_P_1 */ |
539f890d | 9251 | { "vmulss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
9252 | }, |
9253 | { | |
592a252b | 9254 | /* VEX_W_0F59_P_2 */ |
9e30b8e0 | 9255 | { "vmulpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9256 | }, |
9257 | { | |
592a252b | 9258 | /* VEX_W_0F59_P_3 */ |
539f890d | 9259 | { "vmulsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
9260 | }, |
9261 | { | |
592a252b | 9262 | /* VEX_W_0F5A_P_0 */ |
9e30b8e0 | 9263 | { "vcvtps2pd", { XM, EXxmmq } }, |
9e30b8e0 L |
9264 | }, |
9265 | { | |
592a252b | 9266 | /* VEX_W_0F5A_P_1 */ |
539f890d | 9267 | { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
9268 | }, |
9269 | { | |
592a252b | 9270 | /* VEX_W_0F5A_P_3 */ |
539f890d | 9271 | { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
9272 | }, |
9273 | { | |
592a252b | 9274 | /* VEX_W_0F5B_P_0 */ |
9e30b8e0 | 9275 | { "vcvtdq2ps", { XM, EXx } }, |
9e30b8e0 L |
9276 | }, |
9277 | { | |
592a252b | 9278 | /* VEX_W_0F5B_P_1 */ |
9e30b8e0 | 9279 | { "vcvttps2dq", { XM, EXx } }, |
9e30b8e0 L |
9280 | }, |
9281 | { | |
592a252b | 9282 | /* VEX_W_0F5B_P_2 */ |
9e30b8e0 | 9283 | { "vcvtps2dq", { XM, EXx } }, |
9e30b8e0 L |
9284 | }, |
9285 | { | |
592a252b | 9286 | /* VEX_W_0F5C_P_0 */ |
9e30b8e0 | 9287 | { "vsubps", { XM, Vex, EXx } }, |
9e30b8e0 L |
9288 | }, |
9289 | { | |
592a252b | 9290 | /* VEX_W_0F5C_P_1 */ |
539f890d | 9291 | { "vsubss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
9292 | }, |
9293 | { | |
592a252b | 9294 | /* VEX_W_0F5C_P_2 */ |
9e30b8e0 | 9295 | { "vsubpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9296 | }, |
9297 | { | |
592a252b | 9298 | /* VEX_W_0F5C_P_3 */ |
539f890d | 9299 | { "vsubsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
9300 | }, |
9301 | { | |
592a252b | 9302 | /* VEX_W_0F5D_P_0 */ |
9e30b8e0 | 9303 | { "vminps", { XM, Vex, EXx } }, |
9e30b8e0 L |
9304 | }, |
9305 | { | |
592a252b | 9306 | /* VEX_W_0F5D_P_1 */ |
539f890d | 9307 | { "vminss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
9308 | }, |
9309 | { | |
592a252b | 9310 | /* VEX_W_0F5D_P_2 */ |
9e30b8e0 | 9311 | { "vminpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9312 | }, |
9313 | { | |
592a252b | 9314 | /* VEX_W_0F5D_P_3 */ |
539f890d | 9315 | { "vminsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
9316 | }, |
9317 | { | |
592a252b | 9318 | /* VEX_W_0F5E_P_0 */ |
9e30b8e0 | 9319 | { "vdivps", { XM, Vex, EXx } }, |
9e30b8e0 L |
9320 | }, |
9321 | { | |
592a252b | 9322 | /* VEX_W_0F5E_P_1 */ |
539f890d | 9323 | { "vdivss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
9324 | }, |
9325 | { | |
592a252b | 9326 | /* VEX_W_0F5E_P_2 */ |
9e30b8e0 | 9327 | { "vdivpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9328 | }, |
9329 | { | |
592a252b | 9330 | /* VEX_W_0F5E_P_3 */ |
539f890d | 9331 | { "vdivsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
9332 | }, |
9333 | { | |
592a252b | 9334 | /* VEX_W_0F5F_P_0 */ |
9e30b8e0 | 9335 | { "vmaxps", { XM, Vex, EXx } }, |
9e30b8e0 L |
9336 | }, |
9337 | { | |
592a252b | 9338 | /* VEX_W_0F5F_P_1 */ |
539f890d | 9339 | { "vmaxss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
9340 | }, |
9341 | { | |
592a252b | 9342 | /* VEX_W_0F5F_P_2 */ |
9e30b8e0 | 9343 | { "vmaxpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9344 | }, |
9345 | { | |
592a252b | 9346 | /* VEX_W_0F5F_P_3 */ |
539f890d | 9347 | { "vmaxsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
9348 | }, |
9349 | { | |
592a252b | 9350 | /* VEX_W_0F60_P_2 */ |
6c30d220 | 9351 | { "vpunpcklbw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9352 | }, |
9353 | { | |
592a252b | 9354 | /* VEX_W_0F61_P_2 */ |
6c30d220 | 9355 | { "vpunpcklwd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9356 | }, |
9357 | { | |
592a252b | 9358 | /* VEX_W_0F62_P_2 */ |
6c30d220 | 9359 | { "vpunpckldq", { XM, Vex, EXx } }, |
9e30b8e0 L |
9360 | }, |
9361 | { | |
592a252b | 9362 | /* VEX_W_0F63_P_2 */ |
6c30d220 | 9363 | { "vpacksswb", { XM, Vex, EXx } }, |
9e30b8e0 L |
9364 | }, |
9365 | { | |
592a252b | 9366 | /* VEX_W_0F64_P_2 */ |
6c30d220 | 9367 | { "vpcmpgtb", { XM, Vex, EXx } }, |
9e30b8e0 L |
9368 | }, |
9369 | { | |
592a252b | 9370 | /* VEX_W_0F65_P_2 */ |
6c30d220 | 9371 | { "vpcmpgtw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9372 | }, |
9373 | { | |
592a252b | 9374 | /* VEX_W_0F66_P_2 */ |
6c30d220 | 9375 | { "vpcmpgtd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9376 | }, |
9377 | { | |
592a252b | 9378 | /* VEX_W_0F67_P_2 */ |
6c30d220 | 9379 | { "vpackuswb", { XM, Vex, EXx } }, |
9e30b8e0 L |
9380 | }, |
9381 | { | |
592a252b | 9382 | /* VEX_W_0F68_P_2 */ |
6c30d220 | 9383 | { "vpunpckhbw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9384 | }, |
9385 | { | |
592a252b | 9386 | /* VEX_W_0F69_P_2 */ |
6c30d220 | 9387 | { "vpunpckhwd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9388 | }, |
9389 | { | |
592a252b | 9390 | /* VEX_W_0F6A_P_2 */ |
6c30d220 | 9391 | { "vpunpckhdq", { XM, Vex, EXx } }, |
9e30b8e0 L |
9392 | }, |
9393 | { | |
592a252b | 9394 | /* VEX_W_0F6B_P_2 */ |
6c30d220 | 9395 | { "vpackssdw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9396 | }, |
9397 | { | |
592a252b | 9398 | /* VEX_W_0F6C_P_2 */ |
6c30d220 | 9399 | { "vpunpcklqdq", { XM, Vex, EXx } }, |
9e30b8e0 L |
9400 | }, |
9401 | { | |
592a252b | 9402 | /* VEX_W_0F6D_P_2 */ |
6c30d220 | 9403 | { "vpunpckhqdq", { XM, Vex, EXx } }, |
9e30b8e0 L |
9404 | }, |
9405 | { | |
592a252b | 9406 | /* VEX_W_0F6F_P_1 */ |
efdb52b7 | 9407 | { "vmovdqu", { XM, EXx } }, |
9e30b8e0 L |
9408 | }, |
9409 | { | |
592a252b | 9410 | /* VEX_W_0F6F_P_2 */ |
efdb52b7 | 9411 | { "vmovdqa", { XM, EXx } }, |
9e30b8e0 L |
9412 | }, |
9413 | { | |
592a252b | 9414 | /* VEX_W_0F70_P_1 */ |
9e30b8e0 | 9415 | { "vpshufhw", { XM, EXx, Ib } }, |
9e30b8e0 L |
9416 | }, |
9417 | { | |
592a252b | 9418 | /* VEX_W_0F70_P_2 */ |
9e30b8e0 | 9419 | { "vpshufd", { XM, EXx, Ib } }, |
9e30b8e0 L |
9420 | }, |
9421 | { | |
592a252b | 9422 | /* VEX_W_0F70_P_3 */ |
9e30b8e0 | 9423 | { "vpshuflw", { XM, EXx, Ib } }, |
9e30b8e0 L |
9424 | }, |
9425 | { | |
592a252b | 9426 | /* VEX_W_0F71_R_2_P_2 */ |
6c30d220 | 9427 | { "vpsrlw", { Vex, XS, Ib } }, |
9e30b8e0 L |
9428 | }, |
9429 | { | |
592a252b | 9430 | /* VEX_W_0F71_R_4_P_2 */ |
6c30d220 | 9431 | { "vpsraw", { Vex, XS, Ib } }, |
9e30b8e0 L |
9432 | }, |
9433 | { | |
592a252b | 9434 | /* VEX_W_0F71_R_6_P_2 */ |
6c30d220 | 9435 | { "vpsllw", { Vex, XS, Ib } }, |
9e30b8e0 L |
9436 | }, |
9437 | { | |
592a252b | 9438 | /* VEX_W_0F72_R_2_P_2 */ |
6c30d220 | 9439 | { "vpsrld", { Vex, XS, Ib } }, |
9e30b8e0 L |
9440 | }, |
9441 | { | |
592a252b | 9442 | /* VEX_W_0F72_R_4_P_2 */ |
6c30d220 | 9443 | { "vpsrad", { Vex, XS, Ib } }, |
9e30b8e0 L |
9444 | }, |
9445 | { | |
592a252b | 9446 | /* VEX_W_0F72_R_6_P_2 */ |
6c30d220 | 9447 | { "vpslld", { Vex, XS, Ib } }, |
9e30b8e0 L |
9448 | }, |
9449 | { | |
592a252b | 9450 | /* VEX_W_0F73_R_2_P_2 */ |
6c30d220 | 9451 | { "vpsrlq", { Vex, XS, Ib } }, |
9e30b8e0 L |
9452 | }, |
9453 | { | |
592a252b | 9454 | /* VEX_W_0F73_R_3_P_2 */ |
6c30d220 | 9455 | { "vpsrldq", { Vex, XS, Ib } }, |
9e30b8e0 L |
9456 | }, |
9457 | { | |
592a252b | 9458 | /* VEX_W_0F73_R_6_P_2 */ |
6c30d220 | 9459 | { "vpsllq", { Vex, XS, Ib } }, |
9e30b8e0 L |
9460 | }, |
9461 | { | |
592a252b | 9462 | /* VEX_W_0F73_R_7_P_2 */ |
6c30d220 | 9463 | { "vpslldq", { Vex, XS, Ib } }, |
9e30b8e0 L |
9464 | }, |
9465 | { | |
592a252b | 9466 | /* VEX_W_0F74_P_2 */ |
6c30d220 | 9467 | { "vpcmpeqb", { XM, Vex, EXx } }, |
9e30b8e0 L |
9468 | }, |
9469 | { | |
592a252b | 9470 | /* VEX_W_0F75_P_2 */ |
6c30d220 | 9471 | { "vpcmpeqw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9472 | }, |
9473 | { | |
592a252b | 9474 | /* VEX_W_0F76_P_2 */ |
6c30d220 | 9475 | { "vpcmpeqd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9476 | }, |
9477 | { | |
592a252b | 9478 | /* VEX_W_0F77_P_0 */ |
9e30b8e0 | 9479 | { "", { VZERO } }, |
9e30b8e0 L |
9480 | }, |
9481 | { | |
592a252b | 9482 | /* VEX_W_0F7C_P_2 */ |
9e30b8e0 | 9483 | { "vhaddpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9484 | }, |
9485 | { | |
592a252b | 9486 | /* VEX_W_0F7C_P_3 */ |
9e30b8e0 | 9487 | { "vhaddps", { XM, Vex, EXx } }, |
9e30b8e0 L |
9488 | }, |
9489 | { | |
592a252b | 9490 | /* VEX_W_0F7D_P_2 */ |
9e30b8e0 | 9491 | { "vhsubpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9492 | }, |
9493 | { | |
592a252b | 9494 | /* VEX_W_0F7D_P_3 */ |
9e30b8e0 | 9495 | { "vhsubps", { XM, Vex, EXx } }, |
9e30b8e0 L |
9496 | }, |
9497 | { | |
592a252b | 9498 | /* VEX_W_0F7E_P_1 */ |
539f890d | 9499 | { "vmovq", { XMScalar, EXqScalar } }, |
9e30b8e0 L |
9500 | }, |
9501 | { | |
592a252b | 9502 | /* VEX_W_0F7F_P_1 */ |
9e30b8e0 | 9503 | { "vmovdqu", { EXxS, XM } }, |
9e30b8e0 L |
9504 | }, |
9505 | { | |
592a252b | 9506 | /* VEX_W_0F7F_P_2 */ |
9e30b8e0 | 9507 | { "vmovdqa", { EXxS, XM } }, |
9e30b8e0 L |
9508 | }, |
9509 | { | |
592a252b | 9510 | /* VEX_W_0FAE_R_2_M_0 */ |
9e30b8e0 | 9511 | { "vldmxcsr", { Md } }, |
9e30b8e0 L |
9512 | }, |
9513 | { | |
592a252b | 9514 | /* VEX_W_0FAE_R_3_M_0 */ |
9e30b8e0 | 9515 | { "vstmxcsr", { Md } }, |
9e30b8e0 L |
9516 | }, |
9517 | { | |
592a252b | 9518 | /* VEX_W_0FC2_P_0 */ |
9e30b8e0 | 9519 | { "vcmpps", { XM, Vex, EXx, VCMP } }, |
9e30b8e0 L |
9520 | }, |
9521 | { | |
592a252b | 9522 | /* VEX_W_0FC2_P_1 */ |
539f890d | 9523 | { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP } }, |
9e30b8e0 L |
9524 | }, |
9525 | { | |
592a252b | 9526 | /* VEX_W_0FC2_P_2 */ |
9e30b8e0 | 9527 | { "vcmppd", { XM, Vex, EXx, VCMP } }, |
9e30b8e0 L |
9528 | }, |
9529 | { | |
592a252b | 9530 | /* VEX_W_0FC2_P_3 */ |
539f890d | 9531 | { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP } }, |
9e30b8e0 L |
9532 | }, |
9533 | { | |
592a252b | 9534 | /* VEX_W_0FC4_P_2 */ |
9e30b8e0 | 9535 | { "vpinsrw", { XM, Vex128, Edqw, Ib } }, |
9e30b8e0 L |
9536 | }, |
9537 | { | |
592a252b | 9538 | /* VEX_W_0FC5_P_2 */ |
9e30b8e0 | 9539 | { "vpextrw", { Gdq, XS, Ib } }, |
9e30b8e0 L |
9540 | }, |
9541 | { | |
592a252b | 9542 | /* VEX_W_0FD0_P_2 */ |
9e30b8e0 | 9543 | { "vaddsubpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9544 | }, |
9545 | { | |
592a252b | 9546 | /* VEX_W_0FD0_P_3 */ |
9e30b8e0 | 9547 | { "vaddsubps", { XM, Vex, EXx } }, |
9e30b8e0 L |
9548 | }, |
9549 | { | |
592a252b | 9550 | /* VEX_W_0FD1_P_2 */ |
6c30d220 | 9551 | { "vpsrlw", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
9552 | }, |
9553 | { | |
592a252b | 9554 | /* VEX_W_0FD2_P_2 */ |
6c30d220 | 9555 | { "vpsrld", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
9556 | }, |
9557 | { | |
592a252b | 9558 | /* VEX_W_0FD3_P_2 */ |
6c30d220 | 9559 | { "vpsrlq", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
9560 | }, |
9561 | { | |
592a252b | 9562 | /* VEX_W_0FD4_P_2 */ |
6c30d220 | 9563 | { "vpaddq", { XM, Vex, EXx } }, |
9e30b8e0 L |
9564 | }, |
9565 | { | |
592a252b | 9566 | /* VEX_W_0FD5_P_2 */ |
6c30d220 | 9567 | { "vpmullw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9568 | }, |
9569 | { | |
592a252b | 9570 | /* VEX_W_0FD6_P_2 */ |
539f890d | 9571 | { "vmovq", { EXqScalarS, XMScalar } }, |
9e30b8e0 L |
9572 | }, |
9573 | { | |
592a252b | 9574 | /* VEX_W_0FD7_P_2_M_1 */ |
9e30b8e0 | 9575 | { "vpmovmskb", { Gdq, XS } }, |
9e30b8e0 L |
9576 | }, |
9577 | { | |
592a252b | 9578 | /* VEX_W_0FD8_P_2 */ |
6c30d220 | 9579 | { "vpsubusb", { XM, Vex, EXx } }, |
9e30b8e0 L |
9580 | }, |
9581 | { | |
592a252b | 9582 | /* VEX_W_0FD9_P_2 */ |
6c30d220 | 9583 | { "vpsubusw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9584 | }, |
9585 | { | |
592a252b | 9586 | /* VEX_W_0FDA_P_2 */ |
6c30d220 | 9587 | { "vpminub", { XM, Vex, EXx } }, |
9e30b8e0 L |
9588 | }, |
9589 | { | |
592a252b | 9590 | /* VEX_W_0FDB_P_2 */ |
6c30d220 | 9591 | { "vpand", { XM, Vex, EXx } }, |
9e30b8e0 L |
9592 | }, |
9593 | { | |
592a252b | 9594 | /* VEX_W_0FDC_P_2 */ |
6c30d220 | 9595 | { "vpaddusb", { XM, Vex, EXx } }, |
9e30b8e0 L |
9596 | }, |
9597 | { | |
592a252b | 9598 | /* VEX_W_0FDD_P_2 */ |
6c30d220 | 9599 | { "vpaddusw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9600 | }, |
9601 | { | |
592a252b | 9602 | /* VEX_W_0FDE_P_2 */ |
6c30d220 | 9603 | { "vpmaxub", { XM, Vex, EXx } }, |
9e30b8e0 L |
9604 | }, |
9605 | { | |
592a252b | 9606 | /* VEX_W_0FDF_P_2 */ |
6c30d220 | 9607 | { "vpandn", { XM, Vex, EXx } }, |
9e30b8e0 L |
9608 | }, |
9609 | { | |
592a252b | 9610 | /* VEX_W_0FE0_P_2 */ |
6c30d220 | 9611 | { "vpavgb", { XM, Vex, EXx } }, |
9e30b8e0 L |
9612 | }, |
9613 | { | |
592a252b | 9614 | /* VEX_W_0FE1_P_2 */ |
6c30d220 | 9615 | { "vpsraw", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
9616 | }, |
9617 | { | |
592a252b | 9618 | /* VEX_W_0FE2_P_2 */ |
6c30d220 | 9619 | { "vpsrad", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
9620 | }, |
9621 | { | |
592a252b | 9622 | /* VEX_W_0FE3_P_2 */ |
6c30d220 | 9623 | { "vpavgw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9624 | }, |
9625 | { | |
592a252b | 9626 | /* VEX_W_0FE4_P_2 */ |
6c30d220 | 9627 | { "vpmulhuw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9628 | }, |
9629 | { | |
592a252b | 9630 | /* VEX_W_0FE5_P_2 */ |
6c30d220 | 9631 | { "vpmulhw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9632 | }, |
9633 | { | |
592a252b | 9634 | /* VEX_W_0FE6_P_1 */ |
efdb52b7 | 9635 | { "vcvtdq2pd", { XM, EXxmmq } }, |
9e30b8e0 L |
9636 | }, |
9637 | { | |
592a252b | 9638 | /* VEX_W_0FE6_P_2 */ |
a179a9fd | 9639 | { "vcvttpd2dq%XY", { XMM, EXx } }, |
9e30b8e0 L |
9640 | }, |
9641 | { | |
592a252b | 9642 | /* VEX_W_0FE6_P_3 */ |
a179a9fd | 9643 | { "vcvtpd2dq%XY", { XMM, EXx } }, |
9e30b8e0 L |
9644 | }, |
9645 | { | |
592a252b | 9646 | /* VEX_W_0FE7_P_2_M_0 */ |
9e30b8e0 | 9647 | { "vmovntdq", { Mx, XM } }, |
9e30b8e0 L |
9648 | }, |
9649 | { | |
592a252b | 9650 | /* VEX_W_0FE8_P_2 */ |
6c30d220 | 9651 | { "vpsubsb", { XM, Vex, EXx } }, |
9e30b8e0 L |
9652 | }, |
9653 | { | |
592a252b | 9654 | /* VEX_W_0FE9_P_2 */ |
6c30d220 | 9655 | { "vpsubsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9656 | }, |
9657 | { | |
592a252b | 9658 | /* VEX_W_0FEA_P_2 */ |
6c30d220 | 9659 | { "vpminsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9660 | }, |
9661 | { | |
592a252b | 9662 | /* VEX_W_0FEB_P_2 */ |
6c30d220 | 9663 | { "vpor", { XM, Vex, EXx } }, |
9e30b8e0 L |
9664 | }, |
9665 | { | |
592a252b | 9666 | /* VEX_W_0FEC_P_2 */ |
6c30d220 | 9667 | { "vpaddsb", { XM, Vex, EXx } }, |
9e30b8e0 L |
9668 | }, |
9669 | { | |
592a252b | 9670 | /* VEX_W_0FED_P_2 */ |
6c30d220 | 9671 | { "vpaddsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9672 | }, |
9673 | { | |
592a252b | 9674 | /* VEX_W_0FEE_P_2 */ |
6c30d220 | 9675 | { "vpmaxsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9676 | }, |
9677 | { | |
592a252b | 9678 | /* VEX_W_0FEF_P_2 */ |
6c30d220 | 9679 | { "vpxor", { XM, Vex, EXx } }, |
9e30b8e0 L |
9680 | }, |
9681 | { | |
592a252b | 9682 | /* VEX_W_0FF0_P_3_M_0 */ |
9e30b8e0 | 9683 | { "vlddqu", { XM, M } }, |
9e30b8e0 L |
9684 | }, |
9685 | { | |
592a252b | 9686 | /* VEX_W_0FF1_P_2 */ |
6c30d220 | 9687 | { "vpsllw", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
9688 | }, |
9689 | { | |
592a252b | 9690 | /* VEX_W_0FF2_P_2 */ |
6c30d220 | 9691 | { "vpslld", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
9692 | }, |
9693 | { | |
592a252b | 9694 | /* VEX_W_0FF3_P_2 */ |
6c30d220 | 9695 | { "vpsllq", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
9696 | }, |
9697 | { | |
592a252b | 9698 | /* VEX_W_0FF4_P_2 */ |
6c30d220 | 9699 | { "vpmuludq", { XM, Vex, EXx } }, |
9e30b8e0 L |
9700 | }, |
9701 | { | |
592a252b | 9702 | /* VEX_W_0FF5_P_2 */ |
6c30d220 | 9703 | { "vpmaddwd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9704 | }, |
9705 | { | |
592a252b | 9706 | /* VEX_W_0FF6_P_2 */ |
6c30d220 | 9707 | { "vpsadbw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9708 | }, |
9709 | { | |
592a252b | 9710 | /* VEX_W_0FF7_P_2 */ |
9e30b8e0 | 9711 | { "vmaskmovdqu", { XM, XS } }, |
9e30b8e0 L |
9712 | }, |
9713 | { | |
592a252b | 9714 | /* VEX_W_0FF8_P_2 */ |
6c30d220 | 9715 | { "vpsubb", { XM, Vex, EXx } }, |
9e30b8e0 L |
9716 | }, |
9717 | { | |
592a252b | 9718 | /* VEX_W_0FF9_P_2 */ |
6c30d220 | 9719 | { "vpsubw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9720 | }, |
9721 | { | |
592a252b | 9722 | /* VEX_W_0FFA_P_2 */ |
6c30d220 | 9723 | { "vpsubd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9724 | }, |
9725 | { | |
592a252b | 9726 | /* VEX_W_0FFB_P_2 */ |
6c30d220 | 9727 | { "vpsubq", { XM, Vex, EXx } }, |
9e30b8e0 L |
9728 | }, |
9729 | { | |
592a252b | 9730 | /* VEX_W_0FFC_P_2 */ |
6c30d220 | 9731 | { "vpaddb", { XM, Vex, EXx } }, |
9e30b8e0 L |
9732 | }, |
9733 | { | |
592a252b | 9734 | /* VEX_W_0FFD_P_2 */ |
6c30d220 | 9735 | { "vpaddw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9736 | }, |
9737 | { | |
592a252b | 9738 | /* VEX_W_0FFE_P_2 */ |
6c30d220 | 9739 | { "vpaddd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9740 | }, |
9741 | { | |
592a252b | 9742 | /* VEX_W_0F3800_P_2 */ |
6c30d220 | 9743 | { "vpshufb", { XM, Vex, EXx } }, |
9e30b8e0 L |
9744 | }, |
9745 | { | |
592a252b | 9746 | /* VEX_W_0F3801_P_2 */ |
6c30d220 | 9747 | { "vphaddw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9748 | }, |
9749 | { | |
592a252b | 9750 | /* VEX_W_0F3802_P_2 */ |
6c30d220 | 9751 | { "vphaddd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9752 | }, |
9753 | { | |
592a252b | 9754 | /* VEX_W_0F3803_P_2 */ |
6c30d220 | 9755 | { "vphaddsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9756 | }, |
9757 | { | |
592a252b | 9758 | /* VEX_W_0F3804_P_2 */ |
6c30d220 | 9759 | { "vpmaddubsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9760 | }, |
9761 | { | |
592a252b | 9762 | /* VEX_W_0F3805_P_2 */ |
6c30d220 | 9763 | { "vphsubw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9764 | }, |
9765 | { | |
592a252b | 9766 | /* VEX_W_0F3806_P_2 */ |
6c30d220 | 9767 | { "vphsubd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9768 | }, |
9769 | { | |
592a252b | 9770 | /* VEX_W_0F3807_P_2 */ |
6c30d220 | 9771 | { "vphsubsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9772 | }, |
9773 | { | |
592a252b | 9774 | /* VEX_W_0F3808_P_2 */ |
6c30d220 | 9775 | { "vpsignb", { XM, Vex, EXx } }, |
9e30b8e0 L |
9776 | }, |
9777 | { | |
592a252b | 9778 | /* VEX_W_0F3809_P_2 */ |
6c30d220 | 9779 | { "vpsignw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9780 | }, |
9781 | { | |
592a252b | 9782 | /* VEX_W_0F380A_P_2 */ |
6c30d220 | 9783 | { "vpsignd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9784 | }, |
9785 | { | |
592a252b | 9786 | /* VEX_W_0F380B_P_2 */ |
6c30d220 | 9787 | { "vpmulhrsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9788 | }, |
9789 | { | |
592a252b | 9790 | /* VEX_W_0F380C_P_2 */ |
9e30b8e0 | 9791 | { "vpermilps", { XM, Vex, EXx } }, |
9e30b8e0 L |
9792 | }, |
9793 | { | |
592a252b | 9794 | /* VEX_W_0F380D_P_2 */ |
9e30b8e0 | 9795 | { "vpermilpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9796 | }, |
9797 | { | |
592a252b | 9798 | /* VEX_W_0F380E_P_2 */ |
9e30b8e0 | 9799 | { "vtestps", { XM, EXx } }, |
9e30b8e0 L |
9800 | }, |
9801 | { | |
592a252b | 9802 | /* VEX_W_0F380F_P_2 */ |
9e30b8e0 | 9803 | { "vtestpd", { XM, EXx } }, |
9e30b8e0 | 9804 | }, |
6c30d220 L |
9805 | { |
9806 | /* VEX_W_0F3816_P_2 */ | |
9807 | { "vpermps", { XM, Vex, EXx } }, | |
9808 | }, | |
9e30b8e0 | 9809 | { |
592a252b | 9810 | /* VEX_W_0F3817_P_2 */ |
9e30b8e0 | 9811 | { "vptest", { XM, EXx } }, |
9e30b8e0 | 9812 | }, |
bcf2684f | 9813 | { |
6c30d220 L |
9814 | /* VEX_W_0F3818_P_2 */ |
9815 | { "vbroadcastss", { XM, EXxmm_md } }, | |
bcf2684f | 9816 | }, |
9e30b8e0 | 9817 | { |
6c30d220 L |
9818 | /* VEX_W_0F3819_P_2 */ |
9819 | { "vbroadcastsd", { XM, EXxmm_mq } }, | |
9e30b8e0 L |
9820 | }, |
9821 | { | |
592a252b | 9822 | /* VEX_W_0F381A_P_2_M_0 */ |
9e30b8e0 | 9823 | { "vbroadcastf128", { XM, Mxmm } }, |
9e30b8e0 L |
9824 | }, |
9825 | { | |
592a252b | 9826 | /* VEX_W_0F381C_P_2 */ |
9e30b8e0 | 9827 | { "vpabsb", { XM, EXx } }, |
9e30b8e0 L |
9828 | }, |
9829 | { | |
592a252b | 9830 | /* VEX_W_0F381D_P_2 */ |
9e30b8e0 | 9831 | { "vpabsw", { XM, EXx } }, |
9e30b8e0 L |
9832 | }, |
9833 | { | |
592a252b | 9834 | /* VEX_W_0F381E_P_2 */ |
9e30b8e0 | 9835 | { "vpabsd", { XM, EXx } }, |
9e30b8e0 L |
9836 | }, |
9837 | { | |
592a252b | 9838 | /* VEX_W_0F3820_P_2 */ |
6c30d220 | 9839 | { "vpmovsxbw", { XM, EXxmmq } }, |
9e30b8e0 L |
9840 | }, |
9841 | { | |
592a252b | 9842 | /* VEX_W_0F3821_P_2 */ |
6c30d220 | 9843 | { "vpmovsxbd", { XM, EXxmmqd } }, |
9e30b8e0 L |
9844 | }, |
9845 | { | |
592a252b | 9846 | /* VEX_W_0F3822_P_2 */ |
6c30d220 | 9847 | { "vpmovsxbq", { XM, EXxmmdw } }, |
9e30b8e0 L |
9848 | }, |
9849 | { | |
592a252b | 9850 | /* VEX_W_0F3823_P_2 */ |
6c30d220 | 9851 | { "vpmovsxwd", { XM, EXxmmq } }, |
9e30b8e0 L |
9852 | }, |
9853 | { | |
592a252b | 9854 | /* VEX_W_0F3824_P_2 */ |
6c30d220 | 9855 | { "vpmovsxwq", { XM, EXxmmqd } }, |
9e30b8e0 L |
9856 | }, |
9857 | { | |
592a252b | 9858 | /* VEX_W_0F3825_P_2 */ |
6c30d220 | 9859 | { "vpmovsxdq", { XM, EXxmmq } }, |
9e30b8e0 L |
9860 | }, |
9861 | { | |
592a252b | 9862 | /* VEX_W_0F3828_P_2 */ |
6c30d220 | 9863 | { "vpmuldq", { XM, Vex, EXx } }, |
9e30b8e0 L |
9864 | }, |
9865 | { | |
592a252b | 9866 | /* VEX_W_0F3829_P_2 */ |
6c30d220 | 9867 | { "vpcmpeqq", { XM, Vex, EXx } }, |
9e30b8e0 L |
9868 | }, |
9869 | { | |
592a252b | 9870 | /* VEX_W_0F382A_P_2_M_0 */ |
9e30b8e0 | 9871 | { "vmovntdqa", { XM, Mx } }, |
9e30b8e0 L |
9872 | }, |
9873 | { | |
592a252b | 9874 | /* VEX_W_0F382B_P_2 */ |
6c30d220 | 9875 | { "vpackusdw", { XM, Vex, EXx } }, |
9e30b8e0 | 9876 | }, |
53aa04a0 | 9877 | { |
592a252b | 9878 | /* VEX_W_0F382C_P_2_M_0 */ |
53aa04a0 | 9879 | { "vmaskmovps", { XM, Vex, Mx } }, |
53aa04a0 L |
9880 | }, |
9881 | { | |
592a252b | 9882 | /* VEX_W_0F382D_P_2_M_0 */ |
53aa04a0 | 9883 | { "vmaskmovpd", { XM, Vex, Mx } }, |
53aa04a0 L |
9884 | }, |
9885 | { | |
592a252b | 9886 | /* VEX_W_0F382E_P_2_M_0 */ |
53aa04a0 | 9887 | { "vmaskmovps", { Mx, Vex, XM } }, |
53aa04a0 L |
9888 | }, |
9889 | { | |
592a252b | 9890 | /* VEX_W_0F382F_P_2_M_0 */ |
53aa04a0 | 9891 | { "vmaskmovpd", { Mx, Vex, XM } }, |
53aa04a0 | 9892 | }, |
9e30b8e0 | 9893 | { |
592a252b | 9894 | /* VEX_W_0F3830_P_2 */ |
6c30d220 | 9895 | { "vpmovzxbw", { XM, EXxmmq } }, |
9e30b8e0 L |
9896 | }, |
9897 | { | |
592a252b | 9898 | /* VEX_W_0F3831_P_2 */ |
6c30d220 | 9899 | { "vpmovzxbd", { XM, EXxmmqd } }, |
9e30b8e0 L |
9900 | }, |
9901 | { | |
592a252b | 9902 | /* VEX_W_0F3832_P_2 */ |
6c30d220 | 9903 | { "vpmovzxbq", { XM, EXxmmdw } }, |
9e30b8e0 L |
9904 | }, |
9905 | { | |
592a252b | 9906 | /* VEX_W_0F3833_P_2 */ |
6c30d220 | 9907 | { "vpmovzxwd", { XM, EXxmmq } }, |
9e30b8e0 L |
9908 | }, |
9909 | { | |
592a252b | 9910 | /* VEX_W_0F3834_P_2 */ |
6c30d220 | 9911 | { "vpmovzxwq", { XM, EXxmmqd } }, |
9e30b8e0 L |
9912 | }, |
9913 | { | |
592a252b | 9914 | /* VEX_W_0F3835_P_2 */ |
6c30d220 L |
9915 | { "vpmovzxdq", { XM, EXxmmq } }, |
9916 | }, | |
9917 | { | |
9918 | /* VEX_W_0F3836_P_2 */ | |
9919 | { "vpermd", { XM, Vex, EXx } }, | |
9e30b8e0 L |
9920 | }, |
9921 | { | |
592a252b | 9922 | /* VEX_W_0F3837_P_2 */ |
6c30d220 | 9923 | { "vpcmpgtq", { XM, Vex, EXx } }, |
9e30b8e0 L |
9924 | }, |
9925 | { | |
592a252b | 9926 | /* VEX_W_0F3838_P_2 */ |
6c30d220 | 9927 | { "vpminsb", { XM, Vex, EXx } }, |
9e30b8e0 L |
9928 | }, |
9929 | { | |
592a252b | 9930 | /* VEX_W_0F3839_P_2 */ |
6c30d220 | 9931 | { "vpminsd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9932 | }, |
9933 | { | |
592a252b | 9934 | /* VEX_W_0F383A_P_2 */ |
6c30d220 | 9935 | { "vpminuw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9936 | }, |
9937 | { | |
592a252b | 9938 | /* VEX_W_0F383B_P_2 */ |
6c30d220 | 9939 | { "vpminud", { XM, Vex, EXx } }, |
9e30b8e0 L |
9940 | }, |
9941 | { | |
592a252b | 9942 | /* VEX_W_0F383C_P_2 */ |
6c30d220 | 9943 | { "vpmaxsb", { XM, Vex, EXx } }, |
9e30b8e0 L |
9944 | }, |
9945 | { | |
592a252b | 9946 | /* VEX_W_0F383D_P_2 */ |
6c30d220 | 9947 | { "vpmaxsd", { XM, Vex, EXx } }, |
9e30b8e0 L |
9948 | }, |
9949 | { | |
592a252b | 9950 | /* VEX_W_0F383E_P_2 */ |
6c30d220 | 9951 | { "vpmaxuw", { XM, Vex, EXx } }, |
9e30b8e0 L |
9952 | }, |
9953 | { | |
592a252b | 9954 | /* VEX_W_0F383F_P_2 */ |
6c30d220 | 9955 | { "vpmaxud", { XM, Vex, EXx } }, |
9e30b8e0 L |
9956 | }, |
9957 | { | |
592a252b | 9958 | /* VEX_W_0F3840_P_2 */ |
6c30d220 | 9959 | { "vpmulld", { XM, Vex, EXx } }, |
9e30b8e0 L |
9960 | }, |
9961 | { | |
592a252b | 9962 | /* VEX_W_0F3841_P_2 */ |
9e30b8e0 | 9963 | { "vphminposuw", { XM, EXx } }, |
9e30b8e0 | 9964 | }, |
6c30d220 L |
9965 | { |
9966 | /* VEX_W_0F3846_P_2 */ | |
9967 | { "vpsravd", { XM, Vex, EXx } }, | |
9968 | }, | |
9969 | { | |
9970 | /* VEX_W_0F3858_P_2 */ | |
9971 | { "vpbroadcastd", { XM, EXxmm_md } }, | |
9972 | }, | |
9973 | { | |
9974 | /* VEX_W_0F3859_P_2 */ | |
9975 | { "vpbroadcastq", { XM, EXxmm_mq } }, | |
9976 | }, | |
9977 | { | |
9978 | /* VEX_W_0F385A_P_2_M_0 */ | |
9979 | { "vbroadcasti128", { XM, Mxmm } }, | |
9980 | }, | |
9981 | { | |
9982 | /* VEX_W_0F3878_P_2 */ | |
9983 | { "vpbroadcastb", { XM, EXxmm_mb } }, | |
9984 | }, | |
9985 | { | |
9986 | /* VEX_W_0F3879_P_2 */ | |
9987 | { "vpbroadcastw", { XM, EXxmm_mw } }, | |
9988 | }, | |
9e30b8e0 | 9989 | { |
592a252b | 9990 | /* VEX_W_0F38DB_P_2 */ |
9e30b8e0 | 9991 | { "vaesimc", { XM, EXx } }, |
9e30b8e0 L |
9992 | }, |
9993 | { | |
592a252b | 9994 | /* VEX_W_0F38DC_P_2 */ |
9e30b8e0 | 9995 | { "vaesenc", { XM, Vex128, EXx } }, |
9e30b8e0 L |
9996 | }, |
9997 | { | |
592a252b | 9998 | /* VEX_W_0F38DD_P_2 */ |
9e30b8e0 | 9999 | { "vaesenclast", { XM, Vex128, EXx } }, |
9e30b8e0 L |
10000 | }, |
10001 | { | |
592a252b | 10002 | /* VEX_W_0F38DE_P_2 */ |
9e30b8e0 | 10003 | { "vaesdec", { XM, Vex128, EXx } }, |
9e30b8e0 L |
10004 | }, |
10005 | { | |
592a252b | 10006 | /* VEX_W_0F38DF_P_2 */ |
9e30b8e0 | 10007 | { "vaesdeclast", { XM, Vex128, EXx } }, |
9e30b8e0 | 10008 | }, |
6c30d220 L |
10009 | { |
10010 | /* VEX_W_0F3A00_P_2 */ | |
10011 | { Bad_Opcode }, | |
10012 | { "vpermq", { XM, EXx, Ib } }, | |
10013 | }, | |
10014 | { | |
10015 | /* VEX_W_0F3A01_P_2 */ | |
10016 | { Bad_Opcode }, | |
10017 | { "vpermpd", { XM, EXx, Ib } }, | |
10018 | }, | |
10019 | { | |
10020 | /* VEX_W_0F3A02_P_2 */ | |
10021 | { "vpblendd", { XM, Vex, EXx, Ib } }, | |
10022 | }, | |
9e30b8e0 | 10023 | { |
592a252b | 10024 | /* VEX_W_0F3A04_P_2 */ |
9e30b8e0 | 10025 | { "vpermilps", { XM, EXx, Ib } }, |
9e30b8e0 L |
10026 | }, |
10027 | { | |
592a252b | 10028 | /* VEX_W_0F3A05_P_2 */ |
9e30b8e0 | 10029 | { "vpermilpd", { XM, EXx, Ib } }, |
9e30b8e0 L |
10030 | }, |
10031 | { | |
592a252b | 10032 | /* VEX_W_0F3A06_P_2 */ |
9e30b8e0 | 10033 | { "vperm2f128", { XM, Vex256, EXx, Ib } }, |
9e30b8e0 L |
10034 | }, |
10035 | { | |
592a252b | 10036 | /* VEX_W_0F3A08_P_2 */ |
9e30b8e0 | 10037 | { "vroundps", { XM, EXx, Ib } }, |
9e30b8e0 L |
10038 | }, |
10039 | { | |
592a252b | 10040 | /* VEX_W_0F3A09_P_2 */ |
9e30b8e0 | 10041 | { "vroundpd", { XM, EXx, Ib } }, |
9e30b8e0 L |
10042 | }, |
10043 | { | |
592a252b | 10044 | /* VEX_W_0F3A0A_P_2 */ |
539f890d | 10045 | { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib } }, |
9e30b8e0 L |
10046 | }, |
10047 | { | |
592a252b | 10048 | /* VEX_W_0F3A0B_P_2 */ |
539f890d | 10049 | { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib } }, |
9e30b8e0 L |
10050 | }, |
10051 | { | |
592a252b | 10052 | /* VEX_W_0F3A0C_P_2 */ |
9e30b8e0 | 10053 | { "vblendps", { XM, Vex, EXx, Ib } }, |
9e30b8e0 L |
10054 | }, |
10055 | { | |
592a252b | 10056 | /* VEX_W_0F3A0D_P_2 */ |
9e30b8e0 | 10057 | { "vblendpd", { XM, Vex, EXx, Ib } }, |
9e30b8e0 L |
10058 | }, |
10059 | { | |
592a252b | 10060 | /* VEX_W_0F3A0E_P_2 */ |
6c30d220 | 10061 | { "vpblendw", { XM, Vex, EXx, Ib } }, |
9e30b8e0 L |
10062 | }, |
10063 | { | |
592a252b | 10064 | /* VEX_W_0F3A0F_P_2 */ |
6c30d220 | 10065 | { "vpalignr", { XM, Vex, EXx, Ib } }, |
9e30b8e0 L |
10066 | }, |
10067 | { | |
592a252b | 10068 | /* VEX_W_0F3A14_P_2 */ |
9e30b8e0 | 10069 | { "vpextrb", { Edqb, XM, Ib } }, |
9e30b8e0 L |
10070 | }, |
10071 | { | |
592a252b | 10072 | /* VEX_W_0F3A15_P_2 */ |
9e30b8e0 | 10073 | { "vpextrw", { Edqw, XM, Ib } }, |
9e30b8e0 L |
10074 | }, |
10075 | { | |
592a252b | 10076 | /* VEX_W_0F3A18_P_2 */ |
9e30b8e0 | 10077 | { "vinsertf128", { XM, Vex256, EXxmm, Ib } }, |
9e30b8e0 L |
10078 | }, |
10079 | { | |
592a252b | 10080 | /* VEX_W_0F3A19_P_2 */ |
9e30b8e0 | 10081 | { "vextractf128", { EXxmm, XM, Ib } }, |
9e30b8e0 L |
10082 | }, |
10083 | { | |
592a252b | 10084 | /* VEX_W_0F3A20_P_2 */ |
9e30b8e0 | 10085 | { "vpinsrb", { XM, Vex128, Edqb, Ib } }, |
9e30b8e0 L |
10086 | }, |
10087 | { | |
592a252b | 10088 | /* VEX_W_0F3A21_P_2 */ |
9e30b8e0 | 10089 | { "vinsertps", { XM, Vex128, EXd, Ib } }, |
9e30b8e0 | 10090 | }, |
6c30d220 L |
10091 | { |
10092 | /* VEX_W_0F3A38_P_2 */ | |
10093 | { "vinserti128", { XM, Vex256, EXxmm, Ib } }, | |
10094 | }, | |
10095 | { | |
10096 | /* VEX_W_0F3A39_P_2 */ | |
10097 | { "vextracti128", { EXxmm, XM, Ib } }, | |
10098 | }, | |
9e30b8e0 | 10099 | { |
592a252b | 10100 | /* VEX_W_0F3A40_P_2 */ |
9e30b8e0 | 10101 | { "vdpps", { XM, Vex, EXx, Ib } }, |
9e30b8e0 L |
10102 | }, |
10103 | { | |
592a252b | 10104 | /* VEX_W_0F3A41_P_2 */ |
9e30b8e0 | 10105 | { "vdppd", { XM, Vex128, EXx, Ib } }, |
9e30b8e0 L |
10106 | }, |
10107 | { | |
592a252b | 10108 | /* VEX_W_0F3A42_P_2 */ |
6c30d220 | 10109 | { "vmpsadbw", { XM, Vex, EXx, Ib } }, |
9e30b8e0 L |
10110 | }, |
10111 | { | |
592a252b | 10112 | /* VEX_W_0F3A44_P_2 */ |
9e30b8e0 | 10113 | { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } }, |
9e30b8e0 | 10114 | }, |
6c30d220 L |
10115 | { |
10116 | /* VEX_W_0F3A46_P_2 */ | |
10117 | { "vperm2i128", { XM, Vex256, EXx, Ib } }, | |
10118 | }, | |
a683cc34 | 10119 | { |
592a252b | 10120 | /* VEX_W_0F3A48_P_2 */ |
a683cc34 SP |
10121 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, |
10122 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, | |
10123 | }, | |
10124 | { | |
592a252b | 10125 | /* VEX_W_0F3A49_P_2 */ |
a683cc34 SP |
10126 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, |
10127 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, | |
10128 | }, | |
9e30b8e0 | 10129 | { |
592a252b | 10130 | /* VEX_W_0F3A4A_P_2 */ |
9e30b8e0 | 10131 | { "vblendvps", { XM, Vex, EXx, XMVexI4 } }, |
9e30b8e0 L |
10132 | }, |
10133 | { | |
592a252b | 10134 | /* VEX_W_0F3A4B_P_2 */ |
9e30b8e0 | 10135 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 } }, |
9e30b8e0 L |
10136 | }, |
10137 | { | |
592a252b | 10138 | /* VEX_W_0F3A4C_P_2 */ |
6c30d220 | 10139 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 } }, |
9e30b8e0 L |
10140 | }, |
10141 | { | |
592a252b | 10142 | /* VEX_W_0F3A60_P_2 */ |
9e30b8e0 | 10143 | { "vpcmpestrm", { XM, EXx, Ib } }, |
9e30b8e0 L |
10144 | }, |
10145 | { | |
592a252b | 10146 | /* VEX_W_0F3A61_P_2 */ |
9e30b8e0 | 10147 | { "vpcmpestri", { XM, EXx, Ib } }, |
9e30b8e0 L |
10148 | }, |
10149 | { | |
592a252b | 10150 | /* VEX_W_0F3A62_P_2 */ |
9e30b8e0 | 10151 | { "vpcmpistrm", { XM, EXx, Ib } }, |
9e30b8e0 L |
10152 | }, |
10153 | { | |
592a252b | 10154 | /* VEX_W_0F3A63_P_2 */ |
9e30b8e0 | 10155 | { "vpcmpistri", { XM, EXx, Ib } }, |
9e30b8e0 L |
10156 | }, |
10157 | { | |
592a252b | 10158 | /* VEX_W_0F3ADF_P_2 */ |
9e30b8e0 | 10159 | { "vaeskeygenassist", { XM, EXx, Ib } }, |
9e30b8e0 L |
10160 | }, |
10161 | }; | |
10162 | ||
10163 | static const struct dis386 mod_table[][2] = { | |
10164 | { | |
10165 | /* MOD_8D */ | |
10166 | { "leaS", { Gv, M } }, | |
9e30b8e0 | 10167 | }, |
42164a71 L |
10168 | { |
10169 | /* MOD_C6_REG_7 */ | |
10170 | { Bad_Opcode }, | |
10171 | { RM_TABLE (RM_C6_REG_7) }, | |
10172 | }, | |
10173 | { | |
10174 | /* MOD_C7_REG_7 */ | |
10175 | { Bad_Opcode }, | |
10176 | { RM_TABLE (RM_C7_REG_7) }, | |
10177 | }, | |
9e30b8e0 L |
10178 | { |
10179 | /* MOD_0F01_REG_0 */ | |
10180 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
10181 | { RM_TABLE (RM_0F01_REG_0) }, | |
10182 | }, | |
10183 | { | |
10184 | /* MOD_0F01_REG_1 */ | |
10185 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
10186 | { RM_TABLE (RM_0F01_REG_1) }, | |
10187 | }, | |
10188 | { | |
10189 | /* MOD_0F01_REG_2 */ | |
10190 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
10191 | { RM_TABLE (RM_0F01_REG_2) }, | |
10192 | }, | |
10193 | { | |
10194 | /* MOD_0F01_REG_3 */ | |
10195 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
10196 | { RM_TABLE (RM_0F01_REG_3) }, | |
10197 | }, | |
10198 | { | |
10199 | /* MOD_0F01_REG_7 */ | |
10200 | { "invlpg", { Mb } }, | |
10201 | { RM_TABLE (RM_0F01_REG_7) }, | |
10202 | }, | |
10203 | { | |
10204 | /* MOD_0F12_PREFIX_0 */ | |
10205 | { "movlps", { XM, EXq } }, | |
10206 | { "movhlps", { XM, EXq } }, | |
10207 | }, | |
10208 | { | |
10209 | /* MOD_0F13 */ | |
10210 | { "movlpX", { EXq, XM } }, | |
9e30b8e0 L |
10211 | }, |
10212 | { | |
10213 | /* MOD_0F16_PREFIX_0 */ | |
10214 | { "movhps", { XM, EXq } }, | |
10215 | { "movlhps", { XM, EXq } }, | |
10216 | }, | |
10217 | { | |
10218 | /* MOD_0F17 */ | |
10219 | { "movhpX", { EXq, XM } }, | |
9e30b8e0 L |
10220 | }, |
10221 | { | |
10222 | /* MOD_0F18_REG_0 */ | |
10223 | { "prefetchnta", { Mb } }, | |
9e30b8e0 L |
10224 | }, |
10225 | { | |
10226 | /* MOD_0F18_REG_1 */ | |
10227 | { "prefetcht0", { Mb } }, | |
9e30b8e0 L |
10228 | }, |
10229 | { | |
10230 | /* MOD_0F18_REG_2 */ | |
10231 | { "prefetcht1", { Mb } }, | |
9e30b8e0 L |
10232 | }, |
10233 | { | |
10234 | /* MOD_0F18_REG_3 */ | |
10235 | { "prefetcht2", { Mb } }, | |
9e30b8e0 | 10236 | }, |
d7189fa5 RM |
10237 | { |
10238 | /* MOD_0F18_REG_4 */ | |
10239 | { "nop/reserved", { Mb } }, | |
10240 | }, | |
10241 | { | |
10242 | /* MOD_0F18_REG_5 */ | |
10243 | { "nop/reserved", { Mb } }, | |
10244 | }, | |
10245 | { | |
10246 | /* MOD_0F18_REG_6 */ | |
10247 | { "nop/reserved", { Mb } }, | |
10248 | }, | |
10249 | { | |
10250 | /* MOD_0F18_REG_7 */ | |
10251 | { "nop/reserved", { Mb } }, | |
10252 | }, | |
9e30b8e0 L |
10253 | { |
10254 | /* MOD_0F20 */ | |
592d1631 | 10255 | { Bad_Opcode }, |
9e30b8e0 L |
10256 | { "movZ", { Rm, Cm } }, |
10257 | }, | |
10258 | { | |
10259 | /* MOD_0F21 */ | |
592d1631 | 10260 | { Bad_Opcode }, |
9e30b8e0 L |
10261 | { "movZ", { Rm, Dm } }, |
10262 | }, | |
10263 | { | |
10264 | /* MOD_0F22 */ | |
592d1631 | 10265 | { Bad_Opcode }, |
9e30b8e0 | 10266 | { "movZ", { Cm, Rm } }, |
b844680a L |
10267 | }, |
10268 | { | |
92fddf8e | 10269 | /* MOD_0F23 */ |
592d1631 | 10270 | { Bad_Opcode }, |
92fddf8e | 10271 | { "movZ", { Dm, Rm } }, |
b844680a L |
10272 | }, |
10273 | { | |
92fddf8e | 10274 | /* MOD_0F24 */ |
7bb15c6f | 10275 | { Bad_Opcode }, |
92fddf8e | 10276 | { "movL", { Rd, Td } }, |
b844680a L |
10277 | }, |
10278 | { | |
92fddf8e | 10279 | /* MOD_0F26 */ |
592d1631 | 10280 | { Bad_Opcode }, |
92fddf8e | 10281 | { "movL", { Td, Rd } }, |
b844680a | 10282 | }, |
75c135a8 L |
10283 | { |
10284 | /* MOD_0F2B_PREFIX_0 */ | |
4ee52178 | 10285 | {"movntps", { Mx, XM } }, |
75c135a8 L |
10286 | }, |
10287 | { | |
10288 | /* MOD_0F2B_PREFIX_1 */ | |
4ee52178 | 10289 | {"movntss", { Md, XM } }, |
75c135a8 L |
10290 | }, |
10291 | { | |
10292 | /* MOD_0F2B_PREFIX_2 */ | |
4ee52178 | 10293 | {"movntpd", { Mx, XM } }, |
75c135a8 L |
10294 | }, |
10295 | { | |
10296 | /* MOD_0F2B_PREFIX_3 */ | |
4ee52178 | 10297 | {"movntsd", { Mq, XM } }, |
75c135a8 L |
10298 | }, |
10299 | { | |
10300 | /* MOD_0F51 */ | |
592d1631 | 10301 | { Bad_Opcode }, |
75c135a8 L |
10302 | { "movmskpX", { Gdq, XS } }, |
10303 | }, | |
b844680a | 10304 | { |
1ceb70f8 | 10305 | /* MOD_0F71_REG_2 */ |
592d1631 | 10306 | { Bad_Opcode }, |
4e7d34a6 | 10307 | { "psrlw", { MS, Ib } }, |
b844680a L |
10308 | }, |
10309 | { | |
1ceb70f8 | 10310 | /* MOD_0F71_REG_4 */ |
592d1631 | 10311 | { Bad_Opcode }, |
4e7d34a6 | 10312 | { "psraw", { MS, Ib } }, |
b844680a L |
10313 | }, |
10314 | { | |
1ceb70f8 | 10315 | /* MOD_0F71_REG_6 */ |
592d1631 | 10316 | { Bad_Opcode }, |
4e7d34a6 | 10317 | { "psllw", { MS, Ib } }, |
b844680a L |
10318 | }, |
10319 | { | |
1ceb70f8 | 10320 | /* MOD_0F72_REG_2 */ |
592d1631 | 10321 | { Bad_Opcode }, |
4e7d34a6 | 10322 | { "psrld", { MS, Ib } }, |
b844680a L |
10323 | }, |
10324 | { | |
1ceb70f8 | 10325 | /* MOD_0F72_REG_4 */ |
592d1631 | 10326 | { Bad_Opcode }, |
4e7d34a6 | 10327 | { "psrad", { MS, Ib } }, |
b844680a L |
10328 | }, |
10329 | { | |
1ceb70f8 | 10330 | /* MOD_0F72_REG_6 */ |
592d1631 | 10331 | { Bad_Opcode }, |
4e7d34a6 | 10332 | { "pslld", { MS, Ib } }, |
b844680a L |
10333 | }, |
10334 | { | |
1ceb70f8 | 10335 | /* MOD_0F73_REG_2 */ |
592d1631 | 10336 | { Bad_Opcode }, |
4e7d34a6 | 10337 | { "psrlq", { MS, Ib } }, |
b844680a L |
10338 | }, |
10339 | { | |
1ceb70f8 | 10340 | /* MOD_0F73_REG_3 */ |
592d1631 | 10341 | { Bad_Opcode }, |
c0f3af97 L |
10342 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
10343 | }, | |
10344 | { | |
10345 | /* MOD_0F73_REG_6 */ | |
592d1631 | 10346 | { Bad_Opcode }, |
c0f3af97 L |
10347 | { "psllq", { MS, Ib } }, |
10348 | }, | |
10349 | { | |
10350 | /* MOD_0F73_REG_7 */ | |
592d1631 | 10351 | { Bad_Opcode }, |
c0f3af97 L |
10352 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
10353 | }, | |
10354 | { | |
10355 | /* MOD_0FAE_REG_0 */ | |
eacc9c89 | 10356 | { "fxsave", { FXSAVE } }, |
c7b8aa3a | 10357 | { PREFIX_TABLE (PREFIX_0FAE_REG_0) }, |
c0f3af97 L |
10358 | }, |
10359 | { | |
10360 | /* MOD_0FAE_REG_1 */ | |
eacc9c89 | 10361 | { "fxrstor", { FXSAVE } }, |
c7b8aa3a | 10362 | { PREFIX_TABLE (PREFIX_0FAE_REG_1) }, |
c0f3af97 L |
10363 | }, |
10364 | { | |
10365 | /* MOD_0FAE_REG_2 */ | |
10366 | { "ldmxcsr", { Md } }, | |
c7b8aa3a | 10367 | { PREFIX_TABLE (PREFIX_0FAE_REG_2) }, |
c0f3af97 L |
10368 | }, |
10369 | { | |
10370 | /* MOD_0FAE_REG_3 */ | |
10371 | { "stmxcsr", { Md } }, | |
c7b8aa3a | 10372 | { PREFIX_TABLE (PREFIX_0FAE_REG_3) }, |
c0f3af97 L |
10373 | }, |
10374 | { | |
10375 | /* MOD_0FAE_REG_4 */ | |
73bb6729 | 10376 | { "xsave", { FXSAVE } }, |
c0f3af97 L |
10377 | }, |
10378 | { | |
10379 | /* MOD_0FAE_REG_5 */ | |
73bb6729 | 10380 | { "xrstor", { FXSAVE } }, |
c0f3af97 L |
10381 | { RM_TABLE (RM_0FAE_REG_5) }, |
10382 | }, | |
10383 | { | |
10384 | /* MOD_0FAE_REG_6 */ | |
c7b8aa3a | 10385 | { "xsaveopt", { FXSAVE } }, |
c0f3af97 L |
10386 | { RM_TABLE (RM_0FAE_REG_6) }, |
10387 | }, | |
10388 | { | |
10389 | /* MOD_0FAE_REG_7 */ | |
10390 | { "clflush", { Mb } }, | |
10391 | { RM_TABLE (RM_0FAE_REG_7) }, | |
10392 | }, | |
10393 | { | |
10394 | /* MOD_0FB2 */ | |
10395 | { "lssS", { Gv, Mp } }, | |
c0f3af97 L |
10396 | }, |
10397 | { | |
10398 | /* MOD_0FB4 */ | |
10399 | { "lfsS", { Gv, Mp } }, | |
c0f3af97 L |
10400 | }, |
10401 | { | |
10402 | /* MOD_0FB5 */ | |
10403 | { "lgsS", { Gv, Mp } }, | |
c0f3af97 L |
10404 | }, |
10405 | { | |
10406 | /* MOD_0FC7_REG_6 */ | |
10407 | { PREFIX_TABLE (PREFIX_0FC7_REG_6) }, | |
d7d9a9f8 | 10408 | { "rdrand", { Ev } }, |
c0f3af97 L |
10409 | }, |
10410 | { | |
10411 | /* MOD_0FC7_REG_7 */ | |
10412 | { "vmptrst", { Mq } }, | |
e2e1fcde | 10413 | { "rdseed", { Ev } }, |
c0f3af97 L |
10414 | }, |
10415 | { | |
10416 | /* MOD_0FD7 */ | |
592d1631 | 10417 | { Bad_Opcode }, |
c0f3af97 L |
10418 | { "pmovmskb", { Gdq, MS } }, |
10419 | }, | |
10420 | { | |
10421 | /* MOD_0FE7_PREFIX_2 */ | |
10422 | { "movntdq", { Mx, XM } }, | |
c0f3af97 L |
10423 | }, |
10424 | { | |
10425 | /* MOD_0FF0_PREFIX_3 */ | |
10426 | { "lddqu", { XM, M } }, | |
c0f3af97 L |
10427 | }, |
10428 | { | |
10429 | /* MOD_0F382A_PREFIX_2 */ | |
10430 | { "movntdqa", { XM, Mx } }, | |
c0f3af97 L |
10431 | }, |
10432 | { | |
10433 | /* MOD_62_32BIT */ | |
10434 | { "bound{S|}", { Gv, Ma } }, | |
c0f3af97 L |
10435 | }, |
10436 | { | |
10437 | /* MOD_C4_32BIT */ | |
10438 | { "lesS", { Gv, Mp } }, | |
10439 | { VEX_C4_TABLE (VEX_0F) }, | |
10440 | }, | |
10441 | { | |
10442 | /* MOD_C5_32BIT */ | |
10443 | { "ldsS", { Gv, Mp } }, | |
10444 | { VEX_C5_TABLE (VEX_0F) }, | |
10445 | }, | |
10446 | { | |
592a252b L |
10447 | /* MOD_VEX_0F12_PREFIX_0 */ |
10448 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, | |
10449 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, | |
c0f3af97 L |
10450 | }, |
10451 | { | |
592a252b L |
10452 | /* MOD_VEX_0F13 */ |
10453 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, | |
c0f3af97 L |
10454 | }, |
10455 | { | |
592a252b L |
10456 | /* MOD_VEX_0F16_PREFIX_0 */ |
10457 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, | |
10458 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, | |
c0f3af97 L |
10459 | }, |
10460 | { | |
592a252b L |
10461 | /* MOD_VEX_0F17 */ |
10462 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, | |
c0f3af97 L |
10463 | }, |
10464 | { | |
592a252b L |
10465 | /* MOD_VEX_0F2B */ |
10466 | { VEX_W_TABLE (VEX_W_0F2B_M_0) }, | |
c0f3af97 L |
10467 | }, |
10468 | { | |
592a252b | 10469 | /* MOD_VEX_0F50 */ |
592d1631 | 10470 | { Bad_Opcode }, |
592a252b | 10471 | { VEX_W_TABLE (VEX_W_0F50_M_0) }, |
c0f3af97 L |
10472 | }, |
10473 | { | |
592a252b | 10474 | /* MOD_VEX_0F71_REG_2 */ |
592d1631 | 10475 | { Bad_Opcode }, |
592a252b | 10476 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, |
b844680a L |
10477 | }, |
10478 | { | |
592a252b | 10479 | /* MOD_VEX_0F71_REG_4 */ |
592d1631 | 10480 | { Bad_Opcode }, |
592a252b | 10481 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, |
b844680a L |
10482 | }, |
10483 | { | |
592a252b | 10484 | /* MOD_VEX_0F71_REG_6 */ |
592d1631 | 10485 | { Bad_Opcode }, |
592a252b | 10486 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, |
b844680a L |
10487 | }, |
10488 | { | |
592a252b | 10489 | /* MOD_VEX_0F72_REG_2 */ |
592d1631 | 10490 | { Bad_Opcode }, |
592a252b | 10491 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, |
b844680a | 10492 | }, |
d8faab4e | 10493 | { |
592a252b | 10494 | /* MOD_VEX_0F72_REG_4 */ |
592d1631 | 10495 | { Bad_Opcode }, |
592a252b | 10496 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, |
d8faab4e L |
10497 | }, |
10498 | { | |
592a252b | 10499 | /* MOD_VEX_0F72_REG_6 */ |
592d1631 | 10500 | { Bad_Opcode }, |
592a252b | 10501 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, |
d8faab4e | 10502 | }, |
876d4bfa | 10503 | { |
592a252b | 10504 | /* MOD_VEX_0F73_REG_2 */ |
592d1631 | 10505 | { Bad_Opcode }, |
592a252b | 10506 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, |
876d4bfa L |
10507 | }, |
10508 | { | |
592a252b | 10509 | /* MOD_VEX_0F73_REG_3 */ |
592d1631 | 10510 | { Bad_Opcode }, |
592a252b | 10511 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, |
475a2301 L |
10512 | }, |
10513 | { | |
592a252b | 10514 | /* MOD_VEX_0F73_REG_6 */ |
592d1631 | 10515 | { Bad_Opcode }, |
592a252b | 10516 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, |
876d4bfa L |
10517 | }, |
10518 | { | |
592a252b | 10519 | /* MOD_VEX_0F73_REG_7 */ |
592d1631 | 10520 | { Bad_Opcode }, |
592a252b | 10521 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, |
876d4bfa L |
10522 | }, |
10523 | { | |
592a252b L |
10524 | /* MOD_VEX_0FAE_REG_2 */ |
10525 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, | |
876d4bfa | 10526 | }, |
bbedc832 | 10527 | { |
592a252b L |
10528 | /* MOD_VEX_0FAE_REG_3 */ |
10529 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, | |
bbedc832 | 10530 | }, |
144c41d9 | 10531 | { |
592a252b | 10532 | /* MOD_VEX_0FD7_PREFIX_2 */ |
592d1631 | 10533 | { Bad_Opcode }, |
6c30d220 | 10534 | { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) }, |
144c41d9 | 10535 | }, |
1afd85e3 | 10536 | { |
592a252b L |
10537 | /* MOD_VEX_0FE7_PREFIX_2 */ |
10538 | { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) }, | |
1afd85e3 L |
10539 | }, |
10540 | { | |
592a252b L |
10541 | /* MOD_VEX_0FF0_PREFIX_3 */ |
10542 | { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) }, | |
92fddf8e | 10543 | }, |
75c135a8 | 10544 | { |
592a252b L |
10545 | /* MOD_VEX_0F381A_PREFIX_2 */ |
10546 | { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, | |
75c135a8 | 10547 | }, |
1afd85e3 | 10548 | { |
592a252b | 10549 | /* MOD_VEX_0F382A_PREFIX_2 */ |
6c30d220 | 10550 | { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) }, |
1afd85e3 | 10551 | }, |
75c135a8 | 10552 | { |
592a252b L |
10553 | /* MOD_VEX_0F382C_PREFIX_2 */ |
10554 | { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, | |
75c135a8 | 10555 | }, |
1afd85e3 | 10556 | { |
592a252b L |
10557 | /* MOD_VEX_0F382D_PREFIX_2 */ |
10558 | { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, | |
1afd85e3 L |
10559 | }, |
10560 | { | |
592a252b L |
10561 | /* MOD_VEX_0F382E_PREFIX_2 */ |
10562 | { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, | |
1afd85e3 L |
10563 | }, |
10564 | { | |
592a252b L |
10565 | /* MOD_VEX_0F382F_PREFIX_2 */ |
10566 | { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, | |
1afd85e3 | 10567 | }, |
6c30d220 L |
10568 | { |
10569 | /* MOD_VEX_0F385A_PREFIX_2 */ | |
10570 | { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, | |
10571 | }, | |
10572 | { | |
10573 | /* MOD_VEX_0F388C_PREFIX_2 */ | |
10574 | { "vpmaskmov%LW", { XM, Vex, Mx } }, | |
10575 | }, | |
10576 | { | |
10577 | /* MOD_VEX_0F388E_PREFIX_2 */ | |
10578 | { "vpmaskmov%LW", { Mx, Vex, XM } }, | |
10579 | }, | |
b844680a L |
10580 | }; |
10581 | ||
1ceb70f8 | 10582 | static const struct dis386 rm_table[][8] = { |
42164a71 L |
10583 | { |
10584 | /* RM_C6_REG_7 */ | |
10585 | { "xabort", { Skip_MODRM, Ib } }, | |
10586 | }, | |
10587 | { | |
10588 | /* RM_C7_REG_7 */ | |
10589 | { "xbeginT", { Skip_MODRM, Jv } }, | |
10590 | }, | |
b844680a | 10591 | { |
1ceb70f8 | 10592 | /* RM_0F01_REG_0 */ |
592d1631 | 10593 | { Bad_Opcode }, |
b844680a L |
10594 | { "vmcall", { Skip_MODRM } }, |
10595 | { "vmlaunch", { Skip_MODRM } }, | |
10596 | { "vmresume", { Skip_MODRM } }, | |
10597 | { "vmxoff", { Skip_MODRM } }, | |
b844680a L |
10598 | }, |
10599 | { | |
1ceb70f8 | 10600 | /* RM_0F01_REG_1 */ |
b844680a L |
10601 | { "monitor", { { OP_Monitor, 0 } } }, |
10602 | { "mwait", { { OP_Mwait, 0 } } }, | |
b844680a | 10603 | }, |
475a2301 L |
10604 | { |
10605 | /* RM_0F01_REG_2 */ | |
10606 | { "xgetbv", { Skip_MODRM } }, | |
10607 | { "xsetbv", { Skip_MODRM } }, | |
8729a6f6 L |
10608 | { Bad_Opcode }, |
10609 | { Bad_Opcode }, | |
10610 | { "vmfunc", { Skip_MODRM } }, | |
42164a71 L |
10611 | { "xend", { Skip_MODRM } }, |
10612 | { "xtest", { Skip_MODRM } }, | |
10613 | { Bad_Opcode }, | |
475a2301 | 10614 | }, |
b844680a | 10615 | { |
1ceb70f8 | 10616 | /* RM_0F01_REG_3 */ |
4e7d34a6 L |
10617 | { "vmrun", { Skip_MODRM } }, |
10618 | { "vmmcall", { Skip_MODRM } }, | |
10619 | { "vmload", { Skip_MODRM } }, | |
10620 | { "vmsave", { Skip_MODRM } }, | |
10621 | { "stgi", { Skip_MODRM } }, | |
10622 | { "clgi", { Skip_MODRM } }, | |
10623 | { "skinit", { Skip_MODRM } }, | |
10624 | { "invlpga", { Skip_MODRM } }, | |
10625 | }, | |
10626 | { | |
1ceb70f8 | 10627 | /* RM_0F01_REG_7 */ |
4e7d34a6 L |
10628 | { "swapgs", { Skip_MODRM } }, |
10629 | { "rdtscp", { Skip_MODRM } }, | |
b844680a L |
10630 | }, |
10631 | { | |
1ceb70f8 | 10632 | /* RM_0FAE_REG_5 */ |
4e7d34a6 | 10633 | { "lfence", { Skip_MODRM } }, |
b844680a L |
10634 | }, |
10635 | { | |
1ceb70f8 | 10636 | /* RM_0FAE_REG_6 */ |
4e7d34a6 | 10637 | { "mfence", { Skip_MODRM } }, |
b844680a | 10638 | }, |
bbedc832 | 10639 | { |
1ceb70f8 | 10640 | /* RM_0FAE_REG_7 */ |
4e7d34a6 | 10641 | { "sfence", { Skip_MODRM } }, |
144c41d9 | 10642 | }, |
b844680a L |
10643 | }; |
10644 | ||
c608c12e AM |
10645 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
10646 | ||
f16cd0d5 L |
10647 | /* We use the high bit to indicate different name for the same |
10648 | prefix. */ | |
10649 | #define ADDR16_PREFIX (0x67 | 0x100) | |
10650 | #define ADDR32_PREFIX (0x67 | 0x200) | |
10651 | #define DATA16_PREFIX (0x66 | 0x100) | |
10652 | #define DATA32_PREFIX (0x66 | 0x200) | |
10653 | #define REP_PREFIX (0xf3 | 0x100) | |
42164a71 L |
10654 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
10655 | #define XRELEASE_PREFIX (0xf3 | 0x400) | |
f16cd0d5 L |
10656 | |
10657 | static int | |
26ca5450 | 10658 | ckprefix (void) |
252b5132 | 10659 | { |
f16cd0d5 | 10660 | int newrex, i, length; |
52b15da3 | 10661 | rex = 0; |
c0f3af97 | 10662 | rex_ignored = 0; |
252b5132 | 10663 | prefixes = 0; |
7d421014 | 10664 | used_prefixes = 0; |
52b15da3 | 10665 | rex_used = 0; |
f16cd0d5 L |
10666 | last_lock_prefix = -1; |
10667 | last_repz_prefix = -1; | |
10668 | last_repnz_prefix = -1; | |
10669 | last_data_prefix = -1; | |
10670 | last_addr_prefix = -1; | |
10671 | last_rex_prefix = -1; | |
10672 | last_seg_prefix = -1; | |
f310f33d L |
10673 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
10674 | all_prefixes[i] = 0; | |
10675 | i = 0; | |
f16cd0d5 L |
10676 | length = 0; |
10677 | /* The maximum instruction length is 15bytes. */ | |
10678 | while (length < MAX_CODE_LENGTH - 1) | |
252b5132 RH |
10679 | { |
10680 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 10681 | newrex = 0; |
252b5132 RH |
10682 | switch (*codep) |
10683 | { | |
52b15da3 JH |
10684 | /* REX prefixes family. */ |
10685 | case 0x40: | |
10686 | case 0x41: | |
10687 | case 0x42: | |
10688 | case 0x43: | |
10689 | case 0x44: | |
10690 | case 0x45: | |
10691 | case 0x46: | |
10692 | case 0x47: | |
10693 | case 0x48: | |
10694 | case 0x49: | |
10695 | case 0x4a: | |
10696 | case 0x4b: | |
10697 | case 0x4c: | |
10698 | case 0x4d: | |
10699 | case 0x4e: | |
10700 | case 0x4f: | |
f16cd0d5 L |
10701 | if (address_mode == mode_64bit) |
10702 | newrex = *codep; | |
10703 | else | |
10704 | return 1; | |
10705 | last_rex_prefix = i; | |
52b15da3 | 10706 | break; |
252b5132 RH |
10707 | case 0xf3: |
10708 | prefixes |= PREFIX_REPZ; | |
f16cd0d5 | 10709 | last_repz_prefix = i; |
252b5132 RH |
10710 | break; |
10711 | case 0xf2: | |
10712 | prefixes |= PREFIX_REPNZ; | |
f16cd0d5 | 10713 | last_repnz_prefix = i; |
252b5132 RH |
10714 | break; |
10715 | case 0xf0: | |
10716 | prefixes |= PREFIX_LOCK; | |
f16cd0d5 | 10717 | last_lock_prefix = i; |
252b5132 RH |
10718 | break; |
10719 | case 0x2e: | |
10720 | prefixes |= PREFIX_CS; | |
f16cd0d5 | 10721 | last_seg_prefix = i; |
252b5132 RH |
10722 | break; |
10723 | case 0x36: | |
10724 | prefixes |= PREFIX_SS; | |
f16cd0d5 | 10725 | last_seg_prefix = i; |
252b5132 RH |
10726 | break; |
10727 | case 0x3e: | |
10728 | prefixes |= PREFIX_DS; | |
f16cd0d5 | 10729 | last_seg_prefix = i; |
252b5132 RH |
10730 | break; |
10731 | case 0x26: | |
10732 | prefixes |= PREFIX_ES; | |
f16cd0d5 | 10733 | last_seg_prefix = i; |
252b5132 RH |
10734 | break; |
10735 | case 0x64: | |
10736 | prefixes |= PREFIX_FS; | |
f16cd0d5 | 10737 | last_seg_prefix = i; |
252b5132 RH |
10738 | break; |
10739 | case 0x65: | |
10740 | prefixes |= PREFIX_GS; | |
f16cd0d5 | 10741 | last_seg_prefix = i; |
252b5132 RH |
10742 | break; |
10743 | case 0x66: | |
10744 | prefixes |= PREFIX_DATA; | |
f16cd0d5 | 10745 | last_data_prefix = i; |
252b5132 RH |
10746 | break; |
10747 | case 0x67: | |
10748 | prefixes |= PREFIX_ADDR; | |
f16cd0d5 | 10749 | last_addr_prefix = i; |
252b5132 | 10750 | break; |
5076851f | 10751 | case FWAIT_OPCODE: |
252b5132 RH |
10752 | /* fwait is really an instruction. If there are prefixes |
10753 | before the fwait, they belong to the fwait, *not* to the | |
10754 | following instruction. */ | |
3e7d61b2 | 10755 | if (prefixes || rex) |
252b5132 RH |
10756 | { |
10757 | prefixes |= PREFIX_FWAIT; | |
10758 | codep++; | |
f16cd0d5 | 10759 | return 1; |
252b5132 RH |
10760 | } |
10761 | prefixes = PREFIX_FWAIT; | |
10762 | break; | |
10763 | default: | |
f16cd0d5 | 10764 | return 1; |
252b5132 | 10765 | } |
52b15da3 JH |
10766 | /* Rex is ignored when followed by another prefix. */ |
10767 | if (rex) | |
10768 | { | |
3e7d61b2 | 10769 | rex_used = rex; |
f16cd0d5 | 10770 | return 1; |
52b15da3 | 10771 | } |
f16cd0d5 L |
10772 | if (*codep != FWAIT_OPCODE) |
10773 | all_prefixes[i++] = *codep; | |
52b15da3 | 10774 | rex = newrex; |
252b5132 | 10775 | codep++; |
f16cd0d5 L |
10776 | length++; |
10777 | } | |
10778 | return 0; | |
10779 | } | |
10780 | ||
10781 | static int | |
10782 | seg_prefix (int pref) | |
10783 | { | |
10784 | switch (pref) | |
10785 | { | |
10786 | case 0x2e: | |
10787 | return PREFIX_CS; | |
10788 | case 0x36: | |
10789 | return PREFIX_SS; | |
10790 | case 0x3e: | |
10791 | return PREFIX_DS; | |
10792 | case 0x26: | |
10793 | return PREFIX_ES; | |
10794 | case 0x64: | |
10795 | return PREFIX_FS; | |
10796 | case 0x65: | |
10797 | return PREFIX_GS; | |
10798 | default: | |
10799 | return 0; | |
252b5132 RH |
10800 | } |
10801 | } | |
10802 | ||
7d421014 ILT |
10803 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
10804 | prefix byte. */ | |
10805 | ||
10806 | static const char * | |
26ca5450 | 10807 | prefix_name (int pref, int sizeflag) |
7d421014 | 10808 | { |
0003779b L |
10809 | static const char *rexes [16] = |
10810 | { | |
10811 | "rex", /* 0x40 */ | |
10812 | "rex.B", /* 0x41 */ | |
10813 | "rex.X", /* 0x42 */ | |
10814 | "rex.XB", /* 0x43 */ | |
10815 | "rex.R", /* 0x44 */ | |
10816 | "rex.RB", /* 0x45 */ | |
10817 | "rex.RX", /* 0x46 */ | |
10818 | "rex.RXB", /* 0x47 */ | |
10819 | "rex.W", /* 0x48 */ | |
10820 | "rex.WB", /* 0x49 */ | |
10821 | "rex.WX", /* 0x4a */ | |
10822 | "rex.WXB", /* 0x4b */ | |
10823 | "rex.WR", /* 0x4c */ | |
10824 | "rex.WRB", /* 0x4d */ | |
10825 | "rex.WRX", /* 0x4e */ | |
10826 | "rex.WRXB", /* 0x4f */ | |
10827 | }; | |
10828 | ||
7d421014 ILT |
10829 | switch (pref) |
10830 | { | |
52b15da3 JH |
10831 | /* REX prefixes family. */ |
10832 | case 0x40: | |
52b15da3 | 10833 | case 0x41: |
52b15da3 | 10834 | case 0x42: |
52b15da3 | 10835 | case 0x43: |
52b15da3 | 10836 | case 0x44: |
52b15da3 | 10837 | case 0x45: |
52b15da3 | 10838 | case 0x46: |
52b15da3 | 10839 | case 0x47: |
52b15da3 | 10840 | case 0x48: |
52b15da3 | 10841 | case 0x49: |
52b15da3 | 10842 | case 0x4a: |
52b15da3 | 10843 | case 0x4b: |
52b15da3 | 10844 | case 0x4c: |
52b15da3 | 10845 | case 0x4d: |
52b15da3 | 10846 | case 0x4e: |
52b15da3 | 10847 | case 0x4f: |
0003779b | 10848 | return rexes [pref - 0x40]; |
7d421014 ILT |
10849 | case 0xf3: |
10850 | return "repz"; | |
10851 | case 0xf2: | |
10852 | return "repnz"; | |
10853 | case 0xf0: | |
10854 | return "lock"; | |
10855 | case 0x2e: | |
10856 | return "cs"; | |
10857 | case 0x36: | |
10858 | return "ss"; | |
10859 | case 0x3e: | |
10860 | return "ds"; | |
10861 | case 0x26: | |
10862 | return "es"; | |
10863 | case 0x64: | |
10864 | return "fs"; | |
10865 | case 0x65: | |
10866 | return "gs"; | |
10867 | case 0x66: | |
10868 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
10869 | case 0x67: | |
cb712a9e | 10870 | if (address_mode == mode_64bit) |
db6eb5be | 10871 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 10872 | else |
2888cb7a | 10873 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
10874 | case FWAIT_OPCODE: |
10875 | return "fwait"; | |
f16cd0d5 L |
10876 | case ADDR16_PREFIX: |
10877 | return "addr16"; | |
10878 | case ADDR32_PREFIX: | |
10879 | return "addr32"; | |
10880 | case DATA16_PREFIX: | |
10881 | return "data16"; | |
10882 | case DATA32_PREFIX: | |
10883 | return "data32"; | |
10884 | case REP_PREFIX: | |
10885 | return "rep"; | |
42164a71 L |
10886 | case XACQUIRE_PREFIX: |
10887 | return "xacquire"; | |
10888 | case XRELEASE_PREFIX: | |
10889 | return "xrelease"; | |
7d421014 ILT |
10890 | default: |
10891 | return NULL; | |
10892 | } | |
10893 | } | |
10894 | ||
ce518a5f L |
10895 | static char op_out[MAX_OPERANDS][100]; |
10896 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 10897 | static int two_source_ops; |
ce518a5f L |
10898 | static bfd_vma op_address[MAX_OPERANDS]; |
10899 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 10900 | static bfd_vma start_pc; |
ce518a5f | 10901 | |
252b5132 RH |
10902 | /* |
10903 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
10904 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
10905 | * section of the "Virtual 8086 Mode" chapter.) | |
10906 | * 'pc' should be the address of this instruction, it will | |
10907 | * be used to print the target address if this is a relative jump or call | |
10908 | * The function returns the length of this instruction in bytes. | |
10909 | */ | |
10910 | ||
252b5132 | 10911 | static char intel_syntax; |
9d141669 | 10912 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
10913 | static char open_char; |
10914 | static char close_char; | |
10915 | static char separator_char; | |
10916 | static char scale_char; | |
10917 | ||
e396998b AM |
10918 | /* Here for backwards compatibility. When gdb stops using |
10919 | print_insn_i386_att and print_insn_i386_intel these functions can | |
10920 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 10921 | int |
26ca5450 | 10922 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
10923 | { |
10924 | intel_syntax = 0; | |
e396998b AM |
10925 | |
10926 | return print_insn (pc, info); | |
252b5132 RH |
10927 | } |
10928 | ||
10929 | int | |
26ca5450 | 10930 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
10931 | { |
10932 | intel_syntax = 1; | |
e396998b AM |
10933 | |
10934 | return print_insn (pc, info); | |
252b5132 RH |
10935 | } |
10936 | ||
e396998b | 10937 | int |
26ca5450 | 10938 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
10939 | { |
10940 | intel_syntax = -1; | |
10941 | ||
10942 | return print_insn (pc, info); | |
10943 | } | |
10944 | ||
f59a29b9 L |
10945 | void |
10946 | print_i386_disassembler_options (FILE *stream) | |
10947 | { | |
10948 | fprintf (stream, _("\n\ | |
10949 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
10950 | with the -M switch (multiple options should be separated by commas):\n")); | |
10951 | ||
10952 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
10953 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
10954 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
10955 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
10956 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
10957 | fprintf (stream, _(" att-mnemonic\n" |
10958 | " Display instruction in AT&T mnemonic\n")); | |
10959 | fprintf (stream, _(" intel-mnemonic\n" | |
10960 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
10961 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
10962 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
10963 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
10964 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
10965 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
10966 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
10967 | } | |
10968 | ||
592d1631 L |
10969 | /* Bad opcode. */ |
10970 | static const struct dis386 bad_opcode = { "(bad)", { XX } }; | |
10971 | ||
b844680a L |
10972 | /* Get a pointer to struct dis386 with a valid name. */ |
10973 | ||
10974 | static const struct dis386 * | |
8bb15339 | 10975 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a | 10976 | { |
91d6fa6a | 10977 | int vindex, vex_table_index; |
b844680a L |
10978 | |
10979 | if (dp->name != NULL) | |
10980 | return dp; | |
10981 | ||
10982 | switch (dp->op[0].bytemode) | |
10983 | { | |
1ceb70f8 L |
10984 | case USE_REG_TABLE: |
10985 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
10986 | break; | |
10987 | ||
10988 | case USE_MOD_TABLE: | |
91d6fa6a NC |
10989 | vindex = modrm.mod == 0x3 ? 1 : 0; |
10990 | dp = &mod_table[dp->op[1].bytemode][vindex]; | |
1ceb70f8 L |
10991 | break; |
10992 | ||
10993 | case USE_RM_TABLE: | |
10994 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
10995 | break; |
10996 | ||
4e7d34a6 | 10997 | case USE_PREFIX_TABLE: |
c0f3af97 | 10998 | if (need_vex) |
b844680a | 10999 | { |
c0f3af97 L |
11000 | /* The prefix in VEX is implicit. */ |
11001 | switch (vex.prefix) | |
11002 | { | |
11003 | case 0: | |
91d6fa6a | 11004 | vindex = 0; |
c0f3af97 L |
11005 | break; |
11006 | case REPE_PREFIX_OPCODE: | |
91d6fa6a | 11007 | vindex = 1; |
c0f3af97 L |
11008 | break; |
11009 | case DATA_PREFIX_OPCODE: | |
91d6fa6a | 11010 | vindex = 2; |
c0f3af97 L |
11011 | break; |
11012 | case REPNE_PREFIX_OPCODE: | |
91d6fa6a | 11013 | vindex = 3; |
c0f3af97 L |
11014 | break; |
11015 | default: | |
11016 | abort (); | |
11017 | break; | |
11018 | } | |
b844680a | 11019 | } |
7bb15c6f | 11020 | else |
b844680a | 11021 | { |
91d6fa6a | 11022 | vindex = 0; |
c0f3af97 L |
11023 | used_prefixes |= (prefixes & PREFIX_REPZ); |
11024 | if (prefixes & PREFIX_REPZ) | |
b844680a | 11025 | { |
91d6fa6a | 11026 | vindex = 1; |
f16cd0d5 | 11027 | all_prefixes[last_repz_prefix] = 0; |
b844680a L |
11028 | } |
11029 | else | |
11030 | { | |
c0f3af97 L |
11031 | /* We should check PREFIX_REPNZ and PREFIX_REPZ before |
11032 | PREFIX_DATA. */ | |
11033 | used_prefixes |= (prefixes & PREFIX_REPNZ); | |
11034 | if (prefixes & PREFIX_REPNZ) | |
11035 | { | |
91d6fa6a | 11036 | vindex = 3; |
f16cd0d5 | 11037 | all_prefixes[last_repnz_prefix] = 0; |
c0f3af97 L |
11038 | } |
11039 | else | |
b844680a | 11040 | { |
c0f3af97 L |
11041 | used_prefixes |= (prefixes & PREFIX_DATA); |
11042 | if (prefixes & PREFIX_DATA) | |
11043 | { | |
91d6fa6a | 11044 | vindex = 2; |
f16cd0d5 | 11045 | all_prefixes[last_data_prefix] = 0; |
c0f3af97 | 11046 | } |
b844680a L |
11047 | } |
11048 | } | |
11049 | } | |
91d6fa6a | 11050 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
b844680a L |
11051 | break; |
11052 | ||
4e7d34a6 | 11053 | case USE_X86_64_TABLE: |
91d6fa6a NC |
11054 | vindex = address_mode == mode_64bit ? 1 : 0; |
11055 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; | |
b844680a L |
11056 | break; |
11057 | ||
4e7d34a6 | 11058 | case USE_3BYTE_TABLE: |
8bb15339 | 11059 | FETCH_DATA (info, codep + 2); |
91d6fa6a NC |
11060 | vindex = *codep++; |
11061 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; | |
8bb15339 L |
11062 | modrm.mod = (*codep >> 6) & 3; |
11063 | modrm.reg = (*codep >> 3) & 7; | |
11064 | modrm.rm = *codep & 7; | |
11065 | break; | |
11066 | ||
c0f3af97 L |
11067 | case USE_VEX_LEN_TABLE: |
11068 | if (!need_vex) | |
11069 | abort (); | |
11070 | ||
11071 | switch (vex.length) | |
11072 | { | |
11073 | case 128: | |
91d6fa6a | 11074 | vindex = 0; |
c0f3af97 L |
11075 | break; |
11076 | case 256: | |
91d6fa6a | 11077 | vindex = 1; |
c0f3af97 L |
11078 | break; |
11079 | default: | |
11080 | abort (); | |
11081 | break; | |
11082 | } | |
11083 | ||
91d6fa6a | 11084 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
c0f3af97 L |
11085 | break; |
11086 | ||
f88c9eb0 SP |
11087 | case USE_XOP_8F_TABLE: |
11088 | FETCH_DATA (info, codep + 3); | |
11089 | /* All bits in the REX prefix are ignored. */ | |
11090 | rex_ignored = rex; | |
11091 | rex = ~(*codep >> 5) & 0x7; | |
11092 | ||
11093 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ | |
11094 | switch ((*codep & 0x1f)) | |
11095 | { | |
11096 | default: | |
f07af43e L |
11097 | dp = &bad_opcode; |
11098 | return dp; | |
5dd85c99 SP |
11099 | case 0x8: |
11100 | vex_table_index = XOP_08; | |
11101 | break; | |
f88c9eb0 SP |
11102 | case 0x9: |
11103 | vex_table_index = XOP_09; | |
11104 | break; | |
11105 | case 0xa: | |
11106 | vex_table_index = XOP_0A; | |
11107 | break; | |
11108 | } | |
11109 | codep++; | |
11110 | vex.w = *codep & 0x80; | |
11111 | if (vex.w && address_mode == mode_64bit) | |
11112 | rex |= REX_W; | |
11113 | ||
11114 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
11115 | if (address_mode != mode_64bit | |
11116 | && vex.register_specifier > 0x7) | |
f07af43e L |
11117 | { |
11118 | dp = &bad_opcode; | |
11119 | return dp; | |
11120 | } | |
f88c9eb0 SP |
11121 | |
11122 | vex.length = (*codep & 0x4) ? 256 : 128; | |
11123 | switch ((*codep & 0x3)) | |
11124 | { | |
11125 | case 0: | |
11126 | vex.prefix = 0; | |
11127 | break; | |
11128 | case 1: | |
11129 | vex.prefix = DATA_PREFIX_OPCODE; | |
11130 | break; | |
11131 | case 2: | |
11132 | vex.prefix = REPE_PREFIX_OPCODE; | |
11133 | break; | |
11134 | case 3: | |
11135 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11136 | break; | |
11137 | } | |
11138 | need_vex = 1; | |
11139 | need_vex_reg = 1; | |
11140 | codep++; | |
91d6fa6a NC |
11141 | vindex = *codep++; |
11142 | dp = &xop_table[vex_table_index][vindex]; | |
c48244a5 SP |
11143 | |
11144 | FETCH_DATA (info, codep + 1); | |
11145 | modrm.mod = (*codep >> 6) & 3; | |
11146 | modrm.reg = (*codep >> 3) & 7; | |
11147 | modrm.rm = *codep & 7; | |
f88c9eb0 SP |
11148 | break; |
11149 | ||
c0f3af97 L |
11150 | case USE_VEX_C4_TABLE: |
11151 | FETCH_DATA (info, codep + 3); | |
11152 | /* All bits in the REX prefix are ignored. */ | |
11153 | rex_ignored = rex; | |
11154 | rex = ~(*codep >> 5) & 0x7; | |
11155 | switch ((*codep & 0x1f)) | |
11156 | { | |
11157 | default: | |
f07af43e L |
11158 | dp = &bad_opcode; |
11159 | return dp; | |
c0f3af97 | 11160 | case 0x1: |
f88c9eb0 | 11161 | vex_table_index = VEX_0F; |
c0f3af97 L |
11162 | break; |
11163 | case 0x2: | |
f88c9eb0 | 11164 | vex_table_index = VEX_0F38; |
c0f3af97 L |
11165 | break; |
11166 | case 0x3: | |
f88c9eb0 | 11167 | vex_table_index = VEX_0F3A; |
c0f3af97 L |
11168 | break; |
11169 | } | |
11170 | codep++; | |
11171 | vex.w = *codep & 0x80; | |
11172 | if (vex.w && address_mode == mode_64bit) | |
11173 | rex |= REX_W; | |
11174 | ||
11175 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
11176 | if (address_mode != mode_64bit | |
11177 | && vex.register_specifier > 0x7) | |
f07af43e L |
11178 | { |
11179 | dp = &bad_opcode; | |
11180 | return dp; | |
11181 | } | |
c0f3af97 L |
11182 | |
11183 | vex.length = (*codep & 0x4) ? 256 : 128; | |
11184 | switch ((*codep & 0x3)) | |
11185 | { | |
11186 | case 0: | |
11187 | vex.prefix = 0; | |
11188 | break; | |
11189 | case 1: | |
11190 | vex.prefix = DATA_PREFIX_OPCODE; | |
11191 | break; | |
11192 | case 2: | |
11193 | vex.prefix = REPE_PREFIX_OPCODE; | |
11194 | break; | |
11195 | case 3: | |
11196 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11197 | break; | |
11198 | } | |
11199 | need_vex = 1; | |
11200 | need_vex_reg = 1; | |
11201 | codep++; | |
91d6fa6a NC |
11202 | vindex = *codep++; |
11203 | dp = &vex_table[vex_table_index][vindex]; | |
c0f3af97 | 11204 | /* There is no MODRM byte for VEX [82|77]. */ |
91d6fa6a | 11205 | if (vindex != 0x77 && vindex != 0x82) |
c0f3af97 L |
11206 | { |
11207 | FETCH_DATA (info, codep + 1); | |
11208 | modrm.mod = (*codep >> 6) & 3; | |
11209 | modrm.reg = (*codep >> 3) & 7; | |
11210 | modrm.rm = *codep & 7; | |
11211 | } | |
11212 | break; | |
11213 | ||
11214 | case USE_VEX_C5_TABLE: | |
11215 | FETCH_DATA (info, codep + 2); | |
11216 | /* All bits in the REX prefix are ignored. */ | |
11217 | rex_ignored = rex; | |
11218 | rex = (*codep & 0x80) ? 0 : REX_R; | |
11219 | ||
11220 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
11221 | if (address_mode != mode_64bit | |
11222 | && vex.register_specifier > 0x7) | |
f07af43e L |
11223 | { |
11224 | dp = &bad_opcode; | |
11225 | return dp; | |
11226 | } | |
c0f3af97 | 11227 | |
759a05ce L |
11228 | vex.w = 0; |
11229 | ||
c0f3af97 L |
11230 | vex.length = (*codep & 0x4) ? 256 : 128; |
11231 | switch ((*codep & 0x3)) | |
11232 | { | |
11233 | case 0: | |
11234 | vex.prefix = 0; | |
11235 | break; | |
11236 | case 1: | |
11237 | vex.prefix = DATA_PREFIX_OPCODE; | |
11238 | break; | |
11239 | case 2: | |
11240 | vex.prefix = REPE_PREFIX_OPCODE; | |
11241 | break; | |
11242 | case 3: | |
11243 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11244 | break; | |
11245 | } | |
11246 | need_vex = 1; | |
11247 | need_vex_reg = 1; | |
11248 | codep++; | |
91d6fa6a NC |
11249 | vindex = *codep++; |
11250 | dp = &vex_table[dp->op[1].bytemode][vindex]; | |
c0f3af97 | 11251 | /* There is no MODRM byte for VEX [82|77]. */ |
91d6fa6a | 11252 | if (vindex != 0x77 && vindex != 0x82) |
c0f3af97 L |
11253 | { |
11254 | FETCH_DATA (info, codep + 1); | |
11255 | modrm.mod = (*codep >> 6) & 3; | |
11256 | modrm.reg = (*codep >> 3) & 7; | |
11257 | modrm.rm = *codep & 7; | |
11258 | } | |
11259 | break; | |
11260 | ||
9e30b8e0 L |
11261 | case USE_VEX_W_TABLE: |
11262 | if (!need_vex) | |
11263 | abort (); | |
11264 | ||
11265 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; | |
11266 | break; | |
11267 | ||
592d1631 L |
11268 | case 0: |
11269 | dp = &bad_opcode; | |
11270 | break; | |
11271 | ||
b844680a | 11272 | default: |
d34b5006 | 11273 | abort (); |
b844680a L |
11274 | } |
11275 | ||
11276 | if (dp->name != NULL) | |
11277 | return dp; | |
11278 | else | |
8bb15339 | 11279 | return get_valid_dis386 (dp, info); |
b844680a L |
11280 | } |
11281 | ||
dfc8cf43 L |
11282 | static void |
11283 | get_sib (disassemble_info *info) | |
11284 | { | |
11285 | /* If modrm.mod == 3, operand must be register. */ | |
11286 | if (need_modrm | |
11287 | && address_mode != mode_16bit | |
11288 | && modrm.mod != 3 | |
11289 | && modrm.rm == 4) | |
11290 | { | |
11291 | FETCH_DATA (info, codep + 2); | |
11292 | sib.index = (codep [1] >> 3) & 7; | |
11293 | sib.scale = (codep [1] >> 6) & 3; | |
11294 | sib.base = codep [1] & 7; | |
11295 | } | |
11296 | } | |
11297 | ||
e396998b | 11298 | static int |
26ca5450 | 11299 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 11300 | { |
2da11e11 | 11301 | const struct dis386 *dp; |
252b5132 | 11302 | int i; |
ce518a5f | 11303 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 11304 | int needcomma; |
e396998b AM |
11305 | int sizeflag; |
11306 | const char *p; | |
252b5132 | 11307 | struct dis_private priv; |
f16cd0d5 L |
11308 | int prefix_length; |
11309 | int default_prefixes; | |
252b5132 | 11310 | |
d7921315 L |
11311 | priv.orig_sizeflag = AFLAG | DFLAG; |
11312 | if ((info->mach & bfd_mach_i386_i386) != 0) | |
cb712a9e | 11313 | address_mode = mode_32bit; |
2da11e11 | 11314 | else if (info->mach == bfd_mach_i386_i8086) |
d7921315 L |
11315 | { |
11316 | address_mode = mode_16bit; | |
11317 | priv.orig_sizeflag = 0; | |
11318 | } | |
2da11e11 | 11319 | else |
d7921315 L |
11320 | address_mode = mode_64bit; |
11321 | ||
11322 | if (intel_syntax == (char) -1) | |
11323 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; | |
e396998b AM |
11324 | |
11325 | for (p = info->disassembler_options; p != NULL; ) | |
11326 | { | |
0112cd26 | 11327 | if (CONST_STRNEQ (p, "x86-64")) |
e396998b | 11328 | { |
cb712a9e | 11329 | address_mode = mode_64bit; |
e396998b AM |
11330 | priv.orig_sizeflag = AFLAG | DFLAG; |
11331 | } | |
0112cd26 | 11332 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 11333 | { |
cb712a9e | 11334 | address_mode = mode_32bit; |
e396998b AM |
11335 | priv.orig_sizeflag = AFLAG | DFLAG; |
11336 | } | |
0112cd26 | 11337 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 11338 | { |
cb712a9e | 11339 | address_mode = mode_16bit; |
e396998b AM |
11340 | priv.orig_sizeflag = 0; |
11341 | } | |
0112cd26 | 11342 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
11343 | { |
11344 | intel_syntax = 1; | |
9d141669 L |
11345 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
11346 | intel_mnemonic = 1; | |
e396998b | 11347 | } |
0112cd26 | 11348 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
11349 | { |
11350 | intel_syntax = 0; | |
9d141669 L |
11351 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
11352 | intel_mnemonic = 0; | |
e396998b | 11353 | } |
0112cd26 | 11354 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 11355 | { |
f59a29b9 L |
11356 | if (address_mode == mode_64bit) |
11357 | { | |
11358 | if (p[4] == '3' && p[5] == '2') | |
11359 | priv.orig_sizeflag &= ~AFLAG; | |
11360 | else if (p[4] == '6' && p[5] == '4') | |
11361 | priv.orig_sizeflag |= AFLAG; | |
11362 | } | |
11363 | else | |
11364 | { | |
11365 | if (p[4] == '1' && p[5] == '6') | |
11366 | priv.orig_sizeflag &= ~AFLAG; | |
11367 | else if (p[4] == '3' && p[5] == '2') | |
11368 | priv.orig_sizeflag |= AFLAG; | |
11369 | } | |
e396998b | 11370 | } |
0112cd26 | 11371 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
11372 | { |
11373 | if (p[4] == '1' && p[5] == '6') | |
11374 | priv.orig_sizeflag &= ~DFLAG; | |
11375 | else if (p[4] == '3' && p[5] == '2') | |
11376 | priv.orig_sizeflag |= DFLAG; | |
11377 | } | |
0112cd26 | 11378 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
11379 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
11380 | ||
11381 | p = strchr (p, ','); | |
11382 | if (p != NULL) | |
11383 | p++; | |
11384 | } | |
11385 | ||
11386 | if (intel_syntax) | |
11387 | { | |
11388 | names64 = intel_names64; | |
11389 | names32 = intel_names32; | |
11390 | names16 = intel_names16; | |
11391 | names8 = intel_names8; | |
11392 | names8rex = intel_names8rex; | |
11393 | names_seg = intel_names_seg; | |
b9733481 L |
11394 | names_mm = intel_names_mm; |
11395 | names_xmm = intel_names_xmm; | |
11396 | names_ymm = intel_names_ymm; | |
db51cc60 L |
11397 | index64 = intel_index64; |
11398 | index32 = intel_index32; | |
e396998b AM |
11399 | index16 = intel_index16; |
11400 | open_char = '['; | |
11401 | close_char = ']'; | |
11402 | separator_char = '+'; | |
11403 | scale_char = '*'; | |
11404 | } | |
11405 | else | |
11406 | { | |
11407 | names64 = att_names64; | |
11408 | names32 = att_names32; | |
11409 | names16 = att_names16; | |
11410 | names8 = att_names8; | |
11411 | names8rex = att_names8rex; | |
11412 | names_seg = att_names_seg; | |
b9733481 L |
11413 | names_mm = att_names_mm; |
11414 | names_xmm = att_names_xmm; | |
11415 | names_ymm = att_names_ymm; | |
db51cc60 L |
11416 | index64 = att_index64; |
11417 | index32 = att_index32; | |
e396998b AM |
11418 | index16 = att_index16; |
11419 | open_char = '('; | |
11420 | close_char = ')'; | |
11421 | separator_char = ','; | |
11422 | scale_char = ','; | |
11423 | } | |
2da11e11 | 11424 | |
4fe53c98 | 11425 | /* The output looks better if we put 7 bytes on a line, since that |
8a9036a4 L |
11426 | puts most long word instructions on a single line. Use 8 bytes |
11427 | for Intel L1OM. */ | |
d7921315 | 11428 | if ((info->mach & bfd_mach_l1om) != 0) |
8a9036a4 L |
11429 | info->bytes_per_line = 8; |
11430 | else | |
11431 | info->bytes_per_line = 7; | |
252b5132 | 11432 | |
26ca5450 | 11433 | info->private_data = &priv; |
252b5132 RH |
11434 | priv.max_fetched = priv.the_buffer; |
11435 | priv.insn_start = pc; | |
252b5132 RH |
11436 | |
11437 | obuf[0] = 0; | |
ce518a5f L |
11438 | for (i = 0; i < MAX_OPERANDS; ++i) |
11439 | { | |
11440 | op_out[i][0] = 0; | |
11441 | op_index[i] = -1; | |
11442 | } | |
252b5132 RH |
11443 | |
11444 | the_info = info; | |
11445 | start_pc = pc; | |
e396998b AM |
11446 | start_codep = priv.the_buffer; |
11447 | codep = priv.the_buffer; | |
252b5132 | 11448 | |
5076851f ILT |
11449 | if (setjmp (priv.bailout) != 0) |
11450 | { | |
7d421014 ILT |
11451 | const char *name; |
11452 | ||
5076851f | 11453 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
11454 | means we have an incomplete instruction of some sort. Just |
11455 | print the first byte as a prefix or a .byte pseudo-op. */ | |
11456 | if (codep > priv.the_buffer) | |
5076851f | 11457 | { |
e396998b | 11458 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
11459 | if (name != NULL) |
11460 | (*info->fprintf_func) (info->stream, "%s", name); | |
11461 | else | |
5076851f | 11462 | { |
7d421014 ILT |
11463 | /* Just print the first byte as a .byte instruction. */ |
11464 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 11465 | (unsigned int) priv.the_buffer[0]); |
5076851f | 11466 | } |
5076851f | 11467 | |
7d421014 | 11468 | return 1; |
5076851f ILT |
11469 | } |
11470 | ||
11471 | return -1; | |
11472 | } | |
11473 | ||
52b15da3 | 11474 | obufp = obuf; |
f16cd0d5 L |
11475 | sizeflag = priv.orig_sizeflag; |
11476 | ||
11477 | if (!ckprefix () || rex_used) | |
11478 | { | |
11479 | /* Too many prefixes or unused REX prefixes. */ | |
11480 | for (i = 0; | |
f6dd4781 | 11481 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
f16cd0d5 | 11482 | i++) |
de882298 RM |
11483 | (*info->fprintf_func) (info->stream, "%s%s", |
11484 | i == 0 ? "" : " ", | |
f16cd0d5 | 11485 | prefix_name (all_prefixes[i], sizeflag)); |
de882298 | 11486 | return i; |
f16cd0d5 | 11487 | } |
252b5132 RH |
11488 | |
11489 | insn_codep = codep; | |
11490 | ||
11491 | FETCH_DATA (info, codep + 1); | |
11492 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
11493 | ||
3e7d61b2 | 11494 | if (((prefixes & PREFIX_FWAIT) |
f16cd0d5 | 11495 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
252b5132 | 11496 | { |
f16cd0d5 | 11497 | (*info->fprintf_func) (info->stream, "fwait"); |
7d421014 | 11498 | return 1; |
252b5132 RH |
11499 | } |
11500 | ||
252b5132 RH |
11501 | if (*codep == 0x0f) |
11502 | { | |
eec0f4ca | 11503 | unsigned char threebyte; |
252b5132 | 11504 | FETCH_DATA (info, codep + 2); |
eec0f4ca L |
11505 | threebyte = *++codep; |
11506 | dp = &dis386_twobyte[threebyte]; | |
252b5132 | 11507 | need_modrm = twobyte_has_modrm[*codep]; |
eec0f4ca | 11508 | codep++; |
252b5132 RH |
11509 | } |
11510 | else | |
11511 | { | |
6439fc28 | 11512 | dp = &dis386[*codep]; |
252b5132 | 11513 | need_modrm = onebyte_has_modrm[*codep]; |
eec0f4ca | 11514 | codep++; |
252b5132 | 11515 | } |
246c51aa | 11516 | |
b844680a | 11517 | if ((prefixes & PREFIX_REPZ)) |
f16cd0d5 | 11518 | used_prefixes |= PREFIX_REPZ; |
b844680a | 11519 | if ((prefixes & PREFIX_REPNZ)) |
f16cd0d5 | 11520 | used_prefixes |= PREFIX_REPNZ; |
b844680a | 11521 | if ((prefixes & PREFIX_LOCK)) |
f16cd0d5 | 11522 | used_prefixes |= PREFIX_LOCK; |
c608c12e | 11523 | |
f16cd0d5 | 11524 | default_prefixes = 0; |
c608c12e AM |
11525 | if (prefixes & PREFIX_ADDR) |
11526 | { | |
11527 | sizeflag ^= AFLAG; | |
ce518a5f | 11528 | if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax) |
3ffd33cf | 11529 | { |
cb712a9e | 11530 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
f16cd0d5 | 11531 | all_prefixes[last_addr_prefix] = ADDR32_PREFIX; |
3ffd33cf | 11532 | else |
f16cd0d5 L |
11533 | all_prefixes[last_addr_prefix] = ADDR16_PREFIX; |
11534 | default_prefixes |= PREFIX_ADDR; | |
3ffd33cf AM |
11535 | } |
11536 | } | |
11537 | ||
b844680a | 11538 | if ((prefixes & PREFIX_DATA)) |
3ffd33cf AM |
11539 | { |
11540 | sizeflag ^= DFLAG; | |
ce518a5f L |
11541 | if (dp->op[2].bytemode == cond_jump_mode |
11542 | && dp->op[0].bytemode == v_mode | |
6439fc28 | 11543 | && !intel_syntax) |
3ffd33cf AM |
11544 | { |
11545 | if (sizeflag & DFLAG) | |
f16cd0d5 | 11546 | all_prefixes[last_data_prefix] = DATA32_PREFIX; |
3ffd33cf | 11547 | else |
f16cd0d5 L |
11548 | all_prefixes[last_data_prefix] = DATA16_PREFIX; |
11549 | default_prefixes |= PREFIX_DATA; | |
11550 | } | |
11551 | else if (rex & REX_W) | |
11552 | { | |
11553 | /* REX_W will override PREFIX_DATA. */ | |
11554 | default_prefixes |= PREFIX_DATA; | |
3ffd33cf AM |
11555 | } |
11556 | } | |
11557 | ||
8bb15339 | 11558 | if (need_modrm) |
252b5132 RH |
11559 | { |
11560 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
11561 | modrm.mod = (*codep >> 6) & 3; |
11562 | modrm.reg = (*codep >> 3) & 7; | |
11563 | modrm.rm = *codep & 7; | |
252b5132 RH |
11564 | } |
11565 | ||
42d5f9c6 MS |
11566 | need_vex = 0; |
11567 | need_vex_reg = 0; | |
11568 | vex_w_done = 0; | |
55b126d4 | 11569 | |
ce518a5f | 11570 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 | 11571 | { |
dfc8cf43 | 11572 | get_sib (info); |
252b5132 RH |
11573 | dofloat (sizeflag); |
11574 | } | |
11575 | else | |
11576 | { | |
8bb15339 | 11577 | dp = get_valid_dis386 (dp, info); |
b844680a | 11578 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
ce518a5f | 11579 | { |
dfc8cf43 | 11580 | get_sib (info); |
ce518a5f L |
11581 | for (i = 0; i < MAX_OPERANDS; ++i) |
11582 | { | |
246c51aa | 11583 | obufp = op_out[i]; |
ce518a5f L |
11584 | op_ad = MAX_OPERANDS - 1 - i; |
11585 | if (dp->op[i].rtn) | |
11586 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
11587 | } | |
6439fc28 | 11588 | } |
252b5132 RH |
11589 | } |
11590 | ||
7d421014 ILT |
11591 | /* See if any prefixes were not used. If so, print the first one |
11592 | separately. If we don't do this, we'll wind up printing an | |
11593 | instruction stream which does not precisely correspond to the | |
11594 | bytes we are disassembling. */ | |
f16cd0d5 | 11595 | if ((prefixes & ~(used_prefixes | default_prefixes)) != 0) |
7d421014 | 11596 | { |
f16cd0d5 L |
11597 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
11598 | if (all_prefixes[i]) | |
11599 | { | |
11600 | const char *name; | |
11601 | name = prefix_name (all_prefixes[i], priv.orig_sizeflag); | |
11602 | if (name == NULL) | |
11603 | name = INTERNAL_DISASSEMBLER_ERROR; | |
11604 | (*info->fprintf_func) (info->stream, "%s", name); | |
11605 | return 1; | |
11606 | } | |
52b15da3 | 11607 | } |
7d421014 | 11608 | |
d869730d | 11609 | /* Check if the REX prefix is used. */ |
2a70cca4 | 11610 | if (rex_ignored == 0 && (rex ^ rex_used) == 0) |
f16cd0d5 L |
11611 | all_prefixes[last_rex_prefix] = 0; |
11612 | ||
5e6718e4 | 11613 | /* Check if the SEG prefix is used. */ |
f16cd0d5 L |
11614 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
11615 | | PREFIX_FS | PREFIX_GS)) != 0 | |
11616 | && (used_prefixes | |
11617 | & seg_prefix (all_prefixes[last_seg_prefix])) != 0) | |
11618 | all_prefixes[last_seg_prefix] = 0; | |
11619 | ||
5e6718e4 | 11620 | /* Check if the ADDR prefix is used. */ |
f16cd0d5 L |
11621 | if ((prefixes & PREFIX_ADDR) != 0 |
11622 | && (used_prefixes & PREFIX_ADDR) != 0) | |
11623 | all_prefixes[last_addr_prefix] = 0; | |
11624 | ||
5e6718e4 | 11625 | /* Check if the DATA prefix is used. */ |
f16cd0d5 L |
11626 | if ((prefixes & PREFIX_DATA) != 0 |
11627 | && (used_prefixes & PREFIX_DATA) != 0) | |
11628 | all_prefixes[last_data_prefix] = 0; | |
11629 | ||
11630 | prefix_length = 0; | |
f310f33d | 11631 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
f16cd0d5 L |
11632 | if (all_prefixes[i]) |
11633 | { | |
11634 | const char *name; | |
11635 | name = prefix_name (all_prefixes[i], sizeflag); | |
11636 | if (name == NULL) | |
11637 | abort (); | |
11638 | prefix_length += strlen (name) + 1; | |
11639 | (*info->fprintf_func) (info->stream, "%s ", name); | |
11640 | } | |
b844680a | 11641 | |
f16cd0d5 L |
11642 | /* Check maximum code length. */ |
11643 | if ((codep - start_codep) > MAX_CODE_LENGTH) | |
11644 | { | |
11645 | (*info->fprintf_func) (info->stream, "(bad)"); | |
11646 | return MAX_CODE_LENGTH; | |
11647 | } | |
b844680a | 11648 | |
ea397f5b | 11649 | obufp = mnemonicendp; |
f16cd0d5 | 11650 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
252b5132 RH |
11651 | oappend (" "); |
11652 | oappend (" "); | |
11653 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
11654 | ||
11655 | /* The enter and bound instructions are printed with operands in the same | |
11656 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 11657 | if (intel_syntax || two_source_ops) |
252b5132 | 11658 | { |
185b1163 L |
11659 | bfd_vma riprel; |
11660 | ||
ce518a5f L |
11661 | for (i = 0; i < MAX_OPERANDS; ++i) |
11662 | op_txt[i] = op_out[i]; | |
246c51aa | 11663 | |
ce518a5f L |
11664 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
11665 | { | |
11666 | op_ad = op_index[i]; | |
11667 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
11668 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
11669 | riprel = op_riprel[i]; |
11670 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
11671 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 11672 | } |
252b5132 RH |
11673 | } |
11674 | else | |
11675 | { | |
ce518a5f L |
11676 | for (i = 0; i < MAX_OPERANDS; ++i) |
11677 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; | |
050dfa73 MM |
11678 | } |
11679 | ||
ce518a5f L |
11680 | needcomma = 0; |
11681 | for (i = 0; i < MAX_OPERANDS; ++i) | |
11682 | if (*op_txt[i]) | |
11683 | { | |
11684 | if (needcomma) | |
11685 | (*info->fprintf_func) (info->stream, ","); | |
11686 | if (op_index[i] != -1 && !op_riprel[i]) | |
11687 | (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info); | |
11688 | else | |
11689 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
11690 | needcomma = 1; | |
11691 | } | |
050dfa73 | 11692 | |
ce518a5f | 11693 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
11694 | if (op_index[i] != -1 && op_riprel[i]) |
11695 | { | |
11696 | (*info->fprintf_func) (info->stream, " # "); | |
11697 | (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep | |
11698 | + op_address[op_index[i]]), info); | |
185b1163 | 11699 | break; |
52b15da3 | 11700 | } |
e396998b | 11701 | return codep - priv.the_buffer; |
252b5132 RH |
11702 | } |
11703 | ||
6439fc28 | 11704 | static const char *float_mem[] = { |
252b5132 | 11705 | /* d8 */ |
7c52e0e8 L |
11706 | "fadd{s|}", |
11707 | "fmul{s|}", | |
11708 | "fcom{s|}", | |
11709 | "fcomp{s|}", | |
11710 | "fsub{s|}", | |
11711 | "fsubr{s|}", | |
11712 | "fdiv{s|}", | |
11713 | "fdivr{s|}", | |
db6eb5be | 11714 | /* d9 */ |
7c52e0e8 | 11715 | "fld{s|}", |
252b5132 | 11716 | "(bad)", |
7c52e0e8 L |
11717 | "fst{s|}", |
11718 | "fstp{s|}", | |
9306ca4a | 11719 | "fldenvIC", |
252b5132 | 11720 | "fldcw", |
9306ca4a | 11721 | "fNstenvIC", |
252b5132 RH |
11722 | "fNstcw", |
11723 | /* da */ | |
7c52e0e8 L |
11724 | "fiadd{l|}", |
11725 | "fimul{l|}", | |
11726 | "ficom{l|}", | |
11727 | "ficomp{l|}", | |
11728 | "fisub{l|}", | |
11729 | "fisubr{l|}", | |
11730 | "fidiv{l|}", | |
11731 | "fidivr{l|}", | |
252b5132 | 11732 | /* db */ |
7c52e0e8 L |
11733 | "fild{l|}", |
11734 | "fisttp{l|}", | |
11735 | "fist{l|}", | |
11736 | "fistp{l|}", | |
252b5132 | 11737 | "(bad)", |
6439fc28 | 11738 | "fld{t||t|}", |
252b5132 | 11739 | "(bad)", |
6439fc28 | 11740 | "fstp{t||t|}", |
252b5132 | 11741 | /* dc */ |
7c52e0e8 L |
11742 | "fadd{l|}", |
11743 | "fmul{l|}", | |
11744 | "fcom{l|}", | |
11745 | "fcomp{l|}", | |
11746 | "fsub{l|}", | |
11747 | "fsubr{l|}", | |
11748 | "fdiv{l|}", | |
11749 | "fdivr{l|}", | |
252b5132 | 11750 | /* dd */ |
7c52e0e8 L |
11751 | "fld{l|}", |
11752 | "fisttp{ll|}", | |
11753 | "fst{l||}", | |
11754 | "fstp{l|}", | |
9306ca4a | 11755 | "frstorIC", |
252b5132 | 11756 | "(bad)", |
9306ca4a | 11757 | "fNsaveIC", |
252b5132 RH |
11758 | "fNstsw", |
11759 | /* de */ | |
11760 | "fiadd", | |
11761 | "fimul", | |
11762 | "ficom", | |
11763 | "ficomp", | |
11764 | "fisub", | |
11765 | "fisubr", | |
11766 | "fidiv", | |
11767 | "fidivr", | |
11768 | /* df */ | |
11769 | "fild", | |
ca164297 | 11770 | "fisttp", |
252b5132 RH |
11771 | "fist", |
11772 | "fistp", | |
11773 | "fbld", | |
7c52e0e8 | 11774 | "fild{ll|}", |
252b5132 | 11775 | "fbstp", |
7c52e0e8 | 11776 | "fistp{ll|}", |
1d9f512f AM |
11777 | }; |
11778 | ||
11779 | static const unsigned char float_mem_mode[] = { | |
11780 | /* d8 */ | |
11781 | d_mode, | |
11782 | d_mode, | |
11783 | d_mode, | |
11784 | d_mode, | |
11785 | d_mode, | |
11786 | d_mode, | |
11787 | d_mode, | |
11788 | d_mode, | |
11789 | /* d9 */ | |
11790 | d_mode, | |
11791 | 0, | |
11792 | d_mode, | |
11793 | d_mode, | |
11794 | 0, | |
11795 | w_mode, | |
11796 | 0, | |
11797 | w_mode, | |
11798 | /* da */ | |
11799 | d_mode, | |
11800 | d_mode, | |
11801 | d_mode, | |
11802 | d_mode, | |
11803 | d_mode, | |
11804 | d_mode, | |
11805 | d_mode, | |
11806 | d_mode, | |
11807 | /* db */ | |
11808 | d_mode, | |
11809 | d_mode, | |
11810 | d_mode, | |
11811 | d_mode, | |
11812 | 0, | |
9306ca4a | 11813 | t_mode, |
1d9f512f | 11814 | 0, |
9306ca4a | 11815 | t_mode, |
1d9f512f AM |
11816 | /* dc */ |
11817 | q_mode, | |
11818 | q_mode, | |
11819 | q_mode, | |
11820 | q_mode, | |
11821 | q_mode, | |
11822 | q_mode, | |
11823 | q_mode, | |
11824 | q_mode, | |
11825 | /* dd */ | |
11826 | q_mode, | |
11827 | q_mode, | |
11828 | q_mode, | |
11829 | q_mode, | |
11830 | 0, | |
11831 | 0, | |
11832 | 0, | |
11833 | w_mode, | |
11834 | /* de */ | |
11835 | w_mode, | |
11836 | w_mode, | |
11837 | w_mode, | |
11838 | w_mode, | |
11839 | w_mode, | |
11840 | w_mode, | |
11841 | w_mode, | |
11842 | w_mode, | |
11843 | /* df */ | |
11844 | w_mode, | |
11845 | w_mode, | |
11846 | w_mode, | |
11847 | w_mode, | |
9306ca4a | 11848 | t_mode, |
1d9f512f | 11849 | q_mode, |
9306ca4a | 11850 | t_mode, |
1d9f512f | 11851 | q_mode |
252b5132 RH |
11852 | }; |
11853 | ||
ce518a5f L |
11854 | #define ST { OP_ST, 0 } |
11855 | #define STi { OP_STi, 0 } | |
252b5132 | 11856 | |
4efba78c L |
11857 | #define FGRPd9_2 NULL, { { NULL, 0 } } |
11858 | #define FGRPd9_4 NULL, { { NULL, 1 } } | |
11859 | #define FGRPd9_5 NULL, { { NULL, 2 } } | |
11860 | #define FGRPd9_6 NULL, { { NULL, 3 } } | |
11861 | #define FGRPd9_7 NULL, { { NULL, 4 } } | |
11862 | #define FGRPda_5 NULL, { { NULL, 5 } } | |
11863 | #define FGRPdb_4 NULL, { { NULL, 6 } } | |
11864 | #define FGRPde_3 NULL, { { NULL, 7 } } | |
11865 | #define FGRPdf_4 NULL, { { NULL, 8 } } | |
252b5132 | 11866 | |
2da11e11 | 11867 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
11868 | /* d8 */ |
11869 | { | |
ce518a5f L |
11870 | { "fadd", { ST, STi } }, |
11871 | { "fmul", { ST, STi } }, | |
11872 | { "fcom", { STi } }, | |
11873 | { "fcomp", { STi } }, | |
11874 | { "fsub", { ST, STi } }, | |
11875 | { "fsubr", { ST, STi } }, | |
11876 | { "fdiv", { ST, STi } }, | |
11877 | { "fdivr", { ST, STi } }, | |
252b5132 RH |
11878 | }, |
11879 | /* d9 */ | |
11880 | { | |
ce518a5f L |
11881 | { "fld", { STi } }, |
11882 | { "fxch", { STi } }, | |
252b5132 | 11883 | { FGRPd9_2 }, |
592d1631 | 11884 | { Bad_Opcode }, |
252b5132 RH |
11885 | { FGRPd9_4 }, |
11886 | { FGRPd9_5 }, | |
11887 | { FGRPd9_6 }, | |
11888 | { FGRPd9_7 }, | |
11889 | }, | |
11890 | /* da */ | |
11891 | { | |
ce518a5f L |
11892 | { "fcmovb", { ST, STi } }, |
11893 | { "fcmove", { ST, STi } }, | |
11894 | { "fcmovbe",{ ST, STi } }, | |
11895 | { "fcmovu", { ST, STi } }, | |
592d1631 | 11896 | { Bad_Opcode }, |
252b5132 | 11897 | { FGRPda_5 }, |
592d1631 L |
11898 | { Bad_Opcode }, |
11899 | { Bad_Opcode }, | |
252b5132 RH |
11900 | }, |
11901 | /* db */ | |
11902 | { | |
ce518a5f L |
11903 | { "fcmovnb",{ ST, STi } }, |
11904 | { "fcmovne",{ ST, STi } }, | |
11905 | { "fcmovnbe",{ ST, STi } }, | |
11906 | { "fcmovnu",{ ST, STi } }, | |
252b5132 | 11907 | { FGRPdb_4 }, |
ce518a5f L |
11908 | { "fucomi", { ST, STi } }, |
11909 | { "fcomi", { ST, STi } }, | |
592d1631 | 11910 | { Bad_Opcode }, |
252b5132 RH |
11911 | }, |
11912 | /* dc */ | |
11913 | { | |
ce518a5f L |
11914 | { "fadd", { STi, ST } }, |
11915 | { "fmul", { STi, ST } }, | |
592d1631 L |
11916 | { Bad_Opcode }, |
11917 | { Bad_Opcode }, | |
9d141669 L |
11918 | { "fsub!M", { STi, ST } }, |
11919 | { "fsubM", { STi, ST } }, | |
11920 | { "fdiv!M", { STi, ST } }, | |
11921 | { "fdivM", { STi, ST } }, | |
252b5132 RH |
11922 | }, |
11923 | /* dd */ | |
11924 | { | |
ce518a5f | 11925 | { "ffree", { STi } }, |
592d1631 | 11926 | { Bad_Opcode }, |
ce518a5f L |
11927 | { "fst", { STi } }, |
11928 | { "fstp", { STi } }, | |
11929 | { "fucom", { STi } }, | |
11930 | { "fucomp", { STi } }, | |
592d1631 L |
11931 | { Bad_Opcode }, |
11932 | { Bad_Opcode }, | |
252b5132 RH |
11933 | }, |
11934 | /* de */ | |
11935 | { | |
ce518a5f L |
11936 | { "faddp", { STi, ST } }, |
11937 | { "fmulp", { STi, ST } }, | |
592d1631 | 11938 | { Bad_Opcode }, |
252b5132 | 11939 | { FGRPde_3 }, |
9d141669 L |
11940 | { "fsub!Mp", { STi, ST } }, |
11941 | { "fsubMp", { STi, ST } }, | |
11942 | { "fdiv!Mp", { STi, ST } }, | |
11943 | { "fdivMp", { STi, ST } }, | |
252b5132 RH |
11944 | }, |
11945 | /* df */ | |
11946 | { | |
ce518a5f | 11947 | { "ffreep", { STi } }, |
592d1631 L |
11948 | { Bad_Opcode }, |
11949 | { Bad_Opcode }, | |
11950 | { Bad_Opcode }, | |
252b5132 | 11951 | { FGRPdf_4 }, |
ce518a5f L |
11952 | { "fucomip", { ST, STi } }, |
11953 | { "fcomip", { ST, STi } }, | |
592d1631 | 11954 | { Bad_Opcode }, |
252b5132 RH |
11955 | }, |
11956 | }; | |
11957 | ||
252b5132 RH |
11958 | static char *fgrps[][8] = { |
11959 | /* d9_2 0 */ | |
11960 | { | |
11961 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
11962 | }, | |
11963 | ||
11964 | /* d9_4 1 */ | |
11965 | { | |
11966 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
11967 | }, | |
11968 | ||
11969 | /* d9_5 2 */ | |
11970 | { | |
11971 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
11972 | }, | |
11973 | ||
11974 | /* d9_6 3 */ | |
11975 | { | |
11976 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
11977 | }, | |
11978 | ||
11979 | /* d9_7 4 */ | |
11980 | { | |
11981 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
11982 | }, | |
11983 | ||
11984 | /* da_5 5 */ | |
11985 | { | |
11986 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
11987 | }, | |
11988 | ||
11989 | /* db_4 6 */ | |
11990 | { | |
309d3373 JB |
11991 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
11992 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", | |
252b5132 RH |
11993 | }, |
11994 | ||
11995 | /* de_3 7 */ | |
11996 | { | |
11997 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
11998 | }, | |
11999 | ||
12000 | /* df_4 8 */ | |
12001 | { | |
12002 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12003 | }, | |
12004 | }; | |
12005 | ||
b6169b20 L |
12006 | static void |
12007 | swap_operand (void) | |
12008 | { | |
12009 | mnemonicendp[0] = '.'; | |
12010 | mnemonicendp[1] = 's'; | |
12011 | mnemonicendp += 2; | |
12012 | } | |
12013 | ||
b844680a L |
12014 | static void |
12015 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
12016 | int sizeflag ATTRIBUTE_UNUSED) | |
12017 | { | |
12018 | /* Skip mod/rm byte. */ | |
12019 | MODRM_CHECK; | |
12020 | codep++; | |
12021 | } | |
12022 | ||
252b5132 | 12023 | static void |
26ca5450 | 12024 | dofloat (int sizeflag) |
252b5132 | 12025 | { |
2da11e11 | 12026 | const struct dis386 *dp; |
252b5132 RH |
12027 | unsigned char floatop; |
12028 | ||
12029 | floatop = codep[-1]; | |
12030 | ||
7967e09e | 12031 | if (modrm.mod != 3) |
252b5132 | 12032 | { |
7967e09e | 12033 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
12034 | |
12035 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 12036 | obufp = op_out[0]; |
6e50d963 | 12037 | op_ad = 2; |
1d9f512f | 12038 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
12039 | return; |
12040 | } | |
6608db57 | 12041 | /* Skip mod/rm byte. */ |
4bba6815 | 12042 | MODRM_CHECK; |
252b5132 RH |
12043 | codep++; |
12044 | ||
7967e09e | 12045 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
12046 | if (dp->name == NULL) |
12047 | { | |
7967e09e | 12048 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 12049 | |
6608db57 | 12050 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 12051 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 12052 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
12053 | } |
12054 | else | |
12055 | { | |
12056 | putop (dp->name, sizeflag); | |
12057 | ||
ce518a5f | 12058 | obufp = op_out[0]; |
6e50d963 | 12059 | op_ad = 2; |
ce518a5f L |
12060 | if (dp->op[0].rtn) |
12061 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 12062 | |
ce518a5f | 12063 | obufp = op_out[1]; |
6e50d963 | 12064 | op_ad = 1; |
ce518a5f L |
12065 | if (dp->op[1].rtn) |
12066 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
12067 | } |
12068 | } | |
12069 | ||
252b5132 | 12070 | static void |
26ca5450 | 12071 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 12072 | { |
422673a9 | 12073 | oappend ("%st" + intel_syntax); |
252b5132 RH |
12074 | } |
12075 | ||
252b5132 | 12076 | static void |
26ca5450 | 12077 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 12078 | { |
7967e09e | 12079 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
d708bcba | 12080 | oappend (scratchbuf + intel_syntax); |
252b5132 RH |
12081 | } |
12082 | ||
6608db57 | 12083 | /* Capital letters in template are macros. */ |
6439fc28 | 12084 | static int |
d3ce72d0 | 12085 | putop (const char *in_template, int sizeflag) |
252b5132 | 12086 | { |
2da11e11 | 12087 | const char *p; |
9306ca4a | 12088 | int alt = 0; |
9d141669 | 12089 | int cond = 1; |
98b528ac L |
12090 | unsigned int l = 0, len = 1; |
12091 | char last[4]; | |
12092 | ||
12093 | #define SAVE_LAST(c) \ | |
12094 | if (l < len && l < sizeof (last)) \ | |
12095 | last[l++] = c; \ | |
12096 | else \ | |
12097 | abort (); | |
252b5132 | 12098 | |
d3ce72d0 | 12099 | for (p = in_template; *p; p++) |
252b5132 RH |
12100 | { |
12101 | switch (*p) | |
12102 | { | |
12103 | default: | |
12104 | *obufp++ = *p; | |
12105 | break; | |
98b528ac L |
12106 | case '%': |
12107 | len++; | |
12108 | break; | |
9d141669 L |
12109 | case '!': |
12110 | cond = 0; | |
12111 | break; | |
6439fc28 AM |
12112 | case '{': |
12113 | alt = 0; | |
12114 | if (intel_syntax) | |
6439fc28 AM |
12115 | { |
12116 | while (*++p != '|') | |
7c52e0e8 L |
12117 | if (*p == '}' || *p == '\0') |
12118 | abort (); | |
6439fc28 | 12119 | } |
9306ca4a JB |
12120 | /* Fall through. */ |
12121 | case 'I': | |
12122 | alt = 1; | |
12123 | continue; | |
6439fc28 AM |
12124 | case '|': |
12125 | while (*++p != '}') | |
12126 | { | |
12127 | if (*p == '\0') | |
12128 | abort (); | |
12129 | } | |
12130 | break; | |
12131 | case '}': | |
12132 | break; | |
252b5132 | 12133 | case 'A': |
db6eb5be AM |
12134 | if (intel_syntax) |
12135 | break; | |
7967e09e | 12136 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 RH |
12137 | *obufp++ = 'b'; |
12138 | break; | |
12139 | case 'B': | |
4b06377f L |
12140 | if (l == 0 && len == 1) |
12141 | { | |
12142 | case_B: | |
12143 | if (intel_syntax) | |
12144 | break; | |
12145 | if (sizeflag & SUFFIX_ALWAYS) | |
12146 | *obufp++ = 'b'; | |
12147 | } | |
12148 | else | |
12149 | { | |
12150 | if (l != 1 | |
12151 | || len != 2 | |
12152 | || last[0] != 'L') | |
12153 | { | |
12154 | SAVE_LAST (*p); | |
12155 | break; | |
12156 | } | |
12157 | ||
12158 | if (address_mode == mode_64bit | |
12159 | && !(prefixes & PREFIX_ADDR)) | |
12160 | { | |
12161 | *obufp++ = 'a'; | |
12162 | *obufp++ = 'b'; | |
12163 | *obufp++ = 's'; | |
12164 | } | |
12165 | ||
12166 | goto case_B; | |
12167 | } | |
252b5132 | 12168 | break; |
9306ca4a JB |
12169 | case 'C': |
12170 | if (intel_syntax && !alt) | |
12171 | break; | |
12172 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
12173 | { | |
12174 | if (sizeflag & DFLAG) | |
12175 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12176 | else | |
12177 | *obufp++ = intel_syntax ? 'w' : 's'; | |
12178 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12179 | } | |
12180 | break; | |
ed7841b3 JB |
12181 | case 'D': |
12182 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
12183 | break; | |
161a04f6 | 12184 | USED_REX (REX_W); |
7967e09e | 12185 | if (modrm.mod == 3) |
ed7841b3 | 12186 | { |
161a04f6 | 12187 | if (rex & REX_W) |
ed7841b3 | 12188 | *obufp++ = 'q'; |
ed7841b3 | 12189 | else |
f16cd0d5 L |
12190 | { |
12191 | if (sizeflag & DFLAG) | |
12192 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12193 | else | |
12194 | *obufp++ = 'w'; | |
12195 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12196 | } | |
ed7841b3 JB |
12197 | } |
12198 | else | |
12199 | *obufp++ = 'w'; | |
12200 | break; | |
252b5132 | 12201 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 12202 | if (address_mode == mode_64bit) |
c1a64871 JH |
12203 | { |
12204 | if (sizeflag & AFLAG) | |
12205 | *obufp++ = 'r'; | |
12206 | else | |
12207 | *obufp++ = 'e'; | |
12208 | } | |
12209 | else | |
12210 | if (sizeflag & AFLAG) | |
12211 | *obufp++ = 'e'; | |
3ffd33cf AM |
12212 | used_prefixes |= (prefixes & PREFIX_ADDR); |
12213 | break; | |
12214 | case 'F': | |
db6eb5be AM |
12215 | if (intel_syntax) |
12216 | break; | |
e396998b | 12217 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
12218 | { |
12219 | if (sizeflag & AFLAG) | |
cb712a9e | 12220 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 12221 | else |
cb712a9e | 12222 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
12223 | used_prefixes |= (prefixes & PREFIX_ADDR); |
12224 | } | |
252b5132 | 12225 | break; |
52fd6d94 JB |
12226 | case 'G': |
12227 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
12228 | break; | |
161a04f6 | 12229 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
12230 | *obufp++ = 'l'; |
12231 | else | |
12232 | *obufp++ = 'w'; | |
161a04f6 | 12233 | if (!(rex & REX_W)) |
52fd6d94 JB |
12234 | used_prefixes |= (prefixes & PREFIX_DATA); |
12235 | break; | |
5dd0794d | 12236 | case 'H': |
db6eb5be AM |
12237 | if (intel_syntax) |
12238 | break; | |
5dd0794d AM |
12239 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
12240 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
12241 | { | |
12242 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
12243 | *obufp++ = ','; | |
12244 | *obufp++ = 'p'; | |
12245 | if (prefixes & PREFIX_DS) | |
12246 | *obufp++ = 't'; | |
12247 | else | |
12248 | *obufp++ = 'n'; | |
12249 | } | |
12250 | break; | |
9306ca4a JB |
12251 | case 'J': |
12252 | if (intel_syntax) | |
12253 | break; | |
12254 | *obufp++ = 'l'; | |
12255 | break; | |
42903f7f L |
12256 | case 'K': |
12257 | USED_REX (REX_W); | |
12258 | if (rex & REX_W) | |
12259 | *obufp++ = 'q'; | |
12260 | else | |
12261 | *obufp++ = 'd'; | |
12262 | break; | |
6dd5059a L |
12263 | case 'Z': |
12264 | if (intel_syntax) | |
12265 | break; | |
12266 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) | |
12267 | { | |
12268 | *obufp++ = 'q'; | |
12269 | break; | |
12270 | } | |
12271 | /* Fall through. */ | |
98b528ac | 12272 | goto case_L; |
252b5132 | 12273 | case 'L': |
98b528ac L |
12274 | if (l != 0 || len != 1) |
12275 | { | |
12276 | SAVE_LAST (*p); | |
12277 | break; | |
12278 | } | |
12279 | case_L: | |
db6eb5be AM |
12280 | if (intel_syntax) |
12281 | break; | |
252b5132 RH |
12282 | if (sizeflag & SUFFIX_ALWAYS) |
12283 | *obufp++ = 'l'; | |
252b5132 | 12284 | break; |
9d141669 L |
12285 | case 'M': |
12286 | if (intel_mnemonic != cond) | |
12287 | *obufp++ = 'r'; | |
12288 | break; | |
252b5132 RH |
12289 | case 'N': |
12290 | if ((prefixes & PREFIX_FWAIT) == 0) | |
12291 | *obufp++ = 'n'; | |
7d421014 ILT |
12292 | else |
12293 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 12294 | break; |
52b15da3 | 12295 | case 'O': |
161a04f6 L |
12296 | USED_REX (REX_W); |
12297 | if (rex & REX_W) | |
6439fc28 | 12298 | *obufp++ = 'o'; |
a35ca55a JB |
12299 | else if (intel_syntax && (sizeflag & DFLAG)) |
12300 | *obufp++ = 'q'; | |
52b15da3 JH |
12301 | else |
12302 | *obufp++ = 'd'; | |
161a04f6 | 12303 | if (!(rex & REX_W)) |
a35ca55a | 12304 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 12305 | break; |
6439fc28 | 12306 | case 'T': |
d9e3625e L |
12307 | if (!intel_syntax |
12308 | && address_mode == mode_64bit | |
7bb15c6f | 12309 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
12310 | { |
12311 | *obufp++ = 'q'; | |
12312 | break; | |
12313 | } | |
6608db57 | 12314 | /* Fall through. */ |
252b5132 | 12315 | case 'P': |
db6eb5be | 12316 | if (intel_syntax) |
d9e3625e L |
12317 | { |
12318 | if ((rex & REX_W) == 0 | |
12319 | && (prefixes & PREFIX_DATA)) | |
12320 | { | |
12321 | if ((sizeflag & DFLAG) == 0) | |
12322 | *obufp++ = 'w'; | |
12323 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12324 | } | |
12325 | break; | |
12326 | } | |
252b5132 | 12327 | if ((prefixes & PREFIX_DATA) |
161a04f6 | 12328 | || (rex & REX_W) |
e396998b | 12329 | || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 | 12330 | { |
161a04f6 L |
12331 | USED_REX (REX_W); |
12332 | if (rex & REX_W) | |
52b15da3 | 12333 | *obufp++ = 'q'; |
c2419411 | 12334 | else |
52b15da3 JH |
12335 | { |
12336 | if (sizeflag & DFLAG) | |
12337 | *obufp++ = 'l'; | |
12338 | else | |
12339 | *obufp++ = 'w'; | |
f16cd0d5 | 12340 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 12341 | } |
252b5132 RH |
12342 | } |
12343 | break; | |
6439fc28 | 12344 | case 'U': |
db6eb5be AM |
12345 | if (intel_syntax) |
12346 | break; | |
7bb15c6f RM |
12347 | if (address_mode == mode_64bit |
12348 | && ((sizeflag & DFLAG) || (rex & REX_W))) | |
6439fc28 | 12349 | { |
7967e09e | 12350 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
1a114b12 | 12351 | *obufp++ = 'q'; |
6439fc28 AM |
12352 | break; |
12353 | } | |
6608db57 | 12354 | /* Fall through. */ |
98b528ac | 12355 | goto case_Q; |
252b5132 | 12356 | case 'Q': |
98b528ac | 12357 | if (l == 0 && len == 1) |
252b5132 | 12358 | { |
98b528ac L |
12359 | case_Q: |
12360 | if (intel_syntax && !alt) | |
12361 | break; | |
12362 | USED_REX (REX_W); | |
12363 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 12364 | { |
98b528ac L |
12365 | if (rex & REX_W) |
12366 | *obufp++ = 'q'; | |
52b15da3 | 12367 | else |
98b528ac L |
12368 | { |
12369 | if (sizeflag & DFLAG) | |
12370 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12371 | else | |
12372 | *obufp++ = 'w'; | |
f16cd0d5 | 12373 | used_prefixes |= (prefixes & PREFIX_DATA); |
98b528ac | 12374 | } |
52b15da3 | 12375 | } |
98b528ac L |
12376 | } |
12377 | else | |
12378 | { | |
12379 | if (l != 1 || len != 2 || last[0] != 'L') | |
12380 | { | |
12381 | SAVE_LAST (*p); | |
12382 | break; | |
12383 | } | |
12384 | if (intel_syntax | |
12385 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) | |
12386 | break; | |
12387 | if ((rex & REX_W)) | |
12388 | { | |
12389 | USED_REX (REX_W); | |
12390 | *obufp++ = 'q'; | |
12391 | } | |
12392 | else | |
12393 | *obufp++ = 'l'; | |
252b5132 RH |
12394 | } |
12395 | break; | |
12396 | case 'R': | |
161a04f6 L |
12397 | USED_REX (REX_W); |
12398 | if (rex & REX_W) | |
a35ca55a JB |
12399 | *obufp++ = 'q'; |
12400 | else if (sizeflag & DFLAG) | |
c608c12e | 12401 | { |
a35ca55a | 12402 | if (intel_syntax) |
c608c12e | 12403 | *obufp++ = 'd'; |
c608c12e | 12404 | else |
a35ca55a | 12405 | *obufp++ = 'l'; |
c608c12e | 12406 | } |
252b5132 | 12407 | else |
a35ca55a JB |
12408 | *obufp++ = 'w'; |
12409 | if (intel_syntax && !p[1] | |
161a04f6 | 12410 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 12411 | *obufp++ = 'e'; |
161a04f6 | 12412 | if (!(rex & REX_W)) |
52b15da3 | 12413 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 12414 | break; |
1a114b12 | 12415 | case 'V': |
4b06377f | 12416 | if (l == 0 && len == 1) |
1a114b12 | 12417 | { |
4b06377f L |
12418 | if (intel_syntax) |
12419 | break; | |
7bb15c6f RM |
12420 | if (address_mode == mode_64bit |
12421 | && ((sizeflag & DFLAG) || (rex & REX_W))) | |
4b06377f L |
12422 | { |
12423 | if (sizeflag & SUFFIX_ALWAYS) | |
12424 | *obufp++ = 'q'; | |
12425 | break; | |
12426 | } | |
12427 | } | |
12428 | else | |
12429 | { | |
12430 | if (l != 1 | |
12431 | || len != 2 | |
12432 | || last[0] != 'L') | |
12433 | { | |
12434 | SAVE_LAST (*p); | |
12435 | break; | |
12436 | } | |
12437 | ||
12438 | if (rex & REX_W) | |
12439 | { | |
12440 | *obufp++ = 'a'; | |
12441 | *obufp++ = 'b'; | |
12442 | *obufp++ = 's'; | |
12443 | } | |
1a114b12 JB |
12444 | } |
12445 | /* Fall through. */ | |
4b06377f | 12446 | goto case_S; |
252b5132 | 12447 | case 'S': |
4b06377f | 12448 | if (l == 0 && len == 1) |
252b5132 | 12449 | { |
4b06377f L |
12450 | case_S: |
12451 | if (intel_syntax) | |
12452 | break; | |
12453 | if (sizeflag & SUFFIX_ALWAYS) | |
52b15da3 | 12454 | { |
4b06377f L |
12455 | if (rex & REX_W) |
12456 | *obufp++ = 'q'; | |
52b15da3 | 12457 | else |
4b06377f L |
12458 | { |
12459 | if (sizeflag & DFLAG) | |
12460 | *obufp++ = 'l'; | |
12461 | else | |
12462 | *obufp++ = 'w'; | |
12463 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12464 | } | |
12465 | } | |
12466 | } | |
12467 | else | |
12468 | { | |
12469 | if (l != 1 | |
12470 | || len != 2 | |
12471 | || last[0] != 'L') | |
12472 | { | |
12473 | SAVE_LAST (*p); | |
12474 | break; | |
52b15da3 | 12475 | } |
4b06377f L |
12476 | |
12477 | if (address_mode == mode_64bit | |
12478 | && !(prefixes & PREFIX_ADDR)) | |
12479 | { | |
12480 | *obufp++ = 'a'; | |
12481 | *obufp++ = 'b'; | |
12482 | *obufp++ = 's'; | |
12483 | } | |
12484 | ||
12485 | goto case_S; | |
252b5132 | 12486 | } |
252b5132 | 12487 | break; |
041bd2e0 | 12488 | case 'X': |
c0f3af97 L |
12489 | if (l != 0 || len != 1) |
12490 | { | |
12491 | SAVE_LAST (*p); | |
12492 | break; | |
12493 | } | |
12494 | if (need_vex && vex.prefix) | |
12495 | { | |
12496 | if (vex.prefix == DATA_PREFIX_OPCODE) | |
12497 | *obufp++ = 'd'; | |
12498 | else | |
12499 | *obufp++ = 's'; | |
12500 | } | |
041bd2e0 | 12501 | else |
f16cd0d5 L |
12502 | { |
12503 | if (prefixes & PREFIX_DATA) | |
12504 | *obufp++ = 'd'; | |
12505 | else | |
12506 | *obufp++ = 's'; | |
12507 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12508 | } | |
041bd2e0 | 12509 | break; |
76f227a5 | 12510 | case 'Y': |
c0f3af97 | 12511 | if (l == 0 && len == 1) |
76f227a5 | 12512 | { |
c0f3af97 L |
12513 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) |
12514 | break; | |
12515 | if (rex & REX_W) | |
12516 | { | |
12517 | USED_REX (REX_W); | |
12518 | *obufp++ = 'q'; | |
12519 | } | |
12520 | break; | |
12521 | } | |
12522 | else | |
12523 | { | |
12524 | if (l != 1 || len != 2 || last[0] != 'X') | |
12525 | { | |
12526 | SAVE_LAST (*p); | |
12527 | break; | |
12528 | } | |
12529 | if (!need_vex) | |
12530 | abort (); | |
12531 | if (intel_syntax | |
12532 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) | |
12533 | break; | |
12534 | switch (vex.length) | |
12535 | { | |
12536 | case 128: | |
12537 | *obufp++ = 'x'; | |
12538 | break; | |
12539 | case 256: | |
12540 | *obufp++ = 'y'; | |
12541 | break; | |
12542 | default: | |
12543 | abort (); | |
12544 | } | |
76f227a5 JH |
12545 | } |
12546 | break; | |
252b5132 | 12547 | case 'W': |
0bfee649 | 12548 | if (l == 0 && len == 1) |
a35ca55a | 12549 | { |
0bfee649 L |
12550 | /* operand size flag for cwtl, cbtw */ |
12551 | USED_REX (REX_W); | |
12552 | if (rex & REX_W) | |
12553 | { | |
12554 | if (intel_syntax) | |
12555 | *obufp++ = 'd'; | |
12556 | else | |
12557 | *obufp++ = 'l'; | |
12558 | } | |
12559 | else if (sizeflag & DFLAG) | |
12560 | *obufp++ = 'w'; | |
a35ca55a | 12561 | else |
0bfee649 L |
12562 | *obufp++ = 'b'; |
12563 | if (!(rex & REX_W)) | |
12564 | used_prefixes |= (prefixes & PREFIX_DATA); | |
a35ca55a | 12565 | } |
252b5132 | 12566 | else |
0bfee649 | 12567 | { |
6c30d220 L |
12568 | if (l != 1 |
12569 | || len != 2 | |
12570 | || (last[0] != 'X' | |
12571 | && last[0] != 'L')) | |
0bfee649 L |
12572 | { |
12573 | SAVE_LAST (*p); | |
12574 | break; | |
12575 | } | |
12576 | if (!need_vex) | |
12577 | abort (); | |
6c30d220 L |
12578 | if (last[0] == 'X') |
12579 | *obufp++ = vex.w ? 'd': 's'; | |
12580 | else | |
12581 | *obufp++ = vex.w ? 'q': 'd'; | |
0bfee649 | 12582 | } |
252b5132 RH |
12583 | break; |
12584 | } | |
9306ca4a | 12585 | alt = 0; |
252b5132 RH |
12586 | } |
12587 | *obufp = 0; | |
ea397f5b | 12588 | mnemonicendp = obufp; |
6439fc28 | 12589 | return 0; |
252b5132 RH |
12590 | } |
12591 | ||
12592 | static void | |
26ca5450 | 12593 | oappend (const char *s) |
252b5132 | 12594 | { |
ea397f5b | 12595 | obufp = stpcpy (obufp, s); |
252b5132 RH |
12596 | } |
12597 | ||
12598 | static void | |
26ca5450 | 12599 | append_seg (void) |
252b5132 RH |
12600 | { |
12601 | if (prefixes & PREFIX_CS) | |
7d421014 | 12602 | { |
7d421014 | 12603 | used_prefixes |= PREFIX_CS; |
d708bcba | 12604 | oappend ("%cs:" + intel_syntax); |
7d421014 | 12605 | } |
252b5132 | 12606 | if (prefixes & PREFIX_DS) |
7d421014 | 12607 | { |
7d421014 | 12608 | used_prefixes |= PREFIX_DS; |
d708bcba | 12609 | oappend ("%ds:" + intel_syntax); |
7d421014 | 12610 | } |
252b5132 | 12611 | if (prefixes & PREFIX_SS) |
7d421014 | 12612 | { |
7d421014 | 12613 | used_prefixes |= PREFIX_SS; |
d708bcba | 12614 | oappend ("%ss:" + intel_syntax); |
7d421014 | 12615 | } |
252b5132 | 12616 | if (prefixes & PREFIX_ES) |
7d421014 | 12617 | { |
7d421014 | 12618 | used_prefixes |= PREFIX_ES; |
d708bcba | 12619 | oappend ("%es:" + intel_syntax); |
7d421014 | 12620 | } |
252b5132 | 12621 | if (prefixes & PREFIX_FS) |
7d421014 | 12622 | { |
7d421014 | 12623 | used_prefixes |= PREFIX_FS; |
d708bcba | 12624 | oappend ("%fs:" + intel_syntax); |
7d421014 | 12625 | } |
252b5132 | 12626 | if (prefixes & PREFIX_GS) |
7d421014 | 12627 | { |
7d421014 | 12628 | used_prefixes |= PREFIX_GS; |
d708bcba | 12629 | oappend ("%gs:" + intel_syntax); |
7d421014 | 12630 | } |
252b5132 RH |
12631 | } |
12632 | ||
12633 | static void | |
26ca5450 | 12634 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
12635 | { |
12636 | if (!intel_syntax) | |
12637 | oappend ("*"); | |
12638 | OP_E (bytemode, sizeflag); | |
12639 | } | |
12640 | ||
52b15da3 | 12641 | static void |
26ca5450 | 12642 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 12643 | { |
cb712a9e | 12644 | if (address_mode == mode_64bit) |
52b15da3 JH |
12645 | { |
12646 | if (hex) | |
12647 | { | |
12648 | char tmp[30]; | |
12649 | int i; | |
12650 | buf[0] = '0'; | |
12651 | buf[1] = 'x'; | |
12652 | sprintf_vma (tmp, disp); | |
6608db57 | 12653 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
12654 | strcpy (buf + 2, tmp + i); |
12655 | } | |
12656 | else | |
12657 | { | |
12658 | bfd_signed_vma v = disp; | |
12659 | char tmp[30]; | |
12660 | int i; | |
12661 | if (v < 0) | |
12662 | { | |
12663 | *(buf++) = '-'; | |
12664 | v = -disp; | |
6608db57 | 12665 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
12666 | if (v < 0) |
12667 | { | |
12668 | strcpy (buf, "9223372036854775808"); | |
12669 | return; | |
12670 | } | |
12671 | } | |
12672 | if (!v) | |
12673 | { | |
12674 | strcpy (buf, "0"); | |
12675 | return; | |
12676 | } | |
12677 | ||
12678 | i = 0; | |
12679 | tmp[29] = 0; | |
12680 | while (v) | |
12681 | { | |
6608db57 | 12682 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
12683 | v /= 10; |
12684 | i++; | |
12685 | } | |
12686 | strcpy (buf, tmp + 29 - i); | |
12687 | } | |
12688 | } | |
12689 | else | |
12690 | { | |
12691 | if (hex) | |
12692 | sprintf (buf, "0x%x", (unsigned int) disp); | |
12693 | else | |
12694 | sprintf (buf, "%d", (int) disp); | |
12695 | } | |
12696 | } | |
12697 | ||
5d669648 L |
12698 | /* Put DISP in BUF as signed hex number. */ |
12699 | ||
12700 | static void | |
12701 | print_displacement (char *buf, bfd_vma disp) | |
12702 | { | |
12703 | bfd_signed_vma val = disp; | |
12704 | char tmp[30]; | |
12705 | int i, j = 0; | |
12706 | ||
12707 | if (val < 0) | |
12708 | { | |
12709 | buf[j++] = '-'; | |
12710 | val = -disp; | |
12711 | ||
12712 | /* Check for possible overflow. */ | |
12713 | if (val < 0) | |
12714 | { | |
12715 | switch (address_mode) | |
12716 | { | |
12717 | case mode_64bit: | |
12718 | strcpy (buf + j, "0x8000000000000000"); | |
12719 | break; | |
12720 | case mode_32bit: | |
12721 | strcpy (buf + j, "0x80000000"); | |
12722 | break; | |
12723 | case mode_16bit: | |
12724 | strcpy (buf + j, "0x8000"); | |
12725 | break; | |
12726 | } | |
12727 | return; | |
12728 | } | |
12729 | } | |
12730 | ||
12731 | buf[j++] = '0'; | |
12732 | buf[j++] = 'x'; | |
12733 | ||
0af1713e | 12734 | sprintf_vma (tmp, (bfd_vma) val); |
5d669648 L |
12735 | for (i = 0; tmp[i] == '0'; i++) |
12736 | continue; | |
12737 | if (tmp[i] == '\0') | |
12738 | i--; | |
12739 | strcpy (buf + j, tmp + i); | |
12740 | } | |
12741 | ||
3f31e633 JB |
12742 | static void |
12743 | intel_operand_size (int bytemode, int sizeflag) | |
12744 | { | |
12745 | switch (bytemode) | |
12746 | { | |
12747 | case b_mode: | |
b6169b20 | 12748 | case b_swap_mode: |
42903f7f | 12749 | case dqb_mode: |
3f31e633 JB |
12750 | oappend ("BYTE PTR "); |
12751 | break; | |
12752 | case w_mode: | |
12753 | case dqw_mode: | |
12754 | oappend ("WORD PTR "); | |
12755 | break; | |
1a114b12 | 12756 | case stack_v_mode: |
7bb15c6f | 12757 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
3f31e633 JB |
12758 | { |
12759 | oappend ("QWORD PTR "); | |
3f31e633 JB |
12760 | break; |
12761 | } | |
12762 | /* FALLTHRU */ | |
12763 | case v_mode: | |
b6169b20 | 12764 | case v_swap_mode: |
3f31e633 | 12765 | case dq_mode: |
161a04f6 L |
12766 | USED_REX (REX_W); |
12767 | if (rex & REX_W) | |
3f31e633 | 12768 | oappend ("QWORD PTR "); |
3f31e633 | 12769 | else |
f16cd0d5 L |
12770 | { |
12771 | if ((sizeflag & DFLAG) || bytemode == dq_mode) | |
12772 | oappend ("DWORD PTR "); | |
12773 | else | |
12774 | oappend ("WORD PTR "); | |
12775 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12776 | } | |
3f31e633 | 12777 | break; |
52fd6d94 | 12778 | case z_mode: |
161a04f6 | 12779 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
12780 | *obufp++ = 'D'; |
12781 | oappend ("WORD PTR "); | |
161a04f6 | 12782 | if (!(rex & REX_W)) |
52fd6d94 JB |
12783 | used_prefixes |= (prefixes & PREFIX_DATA); |
12784 | break; | |
34b772a6 JB |
12785 | case a_mode: |
12786 | if (sizeflag & DFLAG) | |
12787 | oappend ("QWORD PTR "); | |
12788 | else | |
12789 | oappend ("DWORD PTR "); | |
12790 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12791 | break; | |
3f31e633 | 12792 | case d_mode: |
539f890d L |
12793 | case d_scalar_mode: |
12794 | case d_scalar_swap_mode: | |
fa99fab2 | 12795 | case d_swap_mode: |
42903f7f | 12796 | case dqd_mode: |
3f31e633 JB |
12797 | oappend ("DWORD PTR "); |
12798 | break; | |
12799 | case q_mode: | |
539f890d L |
12800 | case q_scalar_mode: |
12801 | case q_scalar_swap_mode: | |
b6169b20 | 12802 | case q_swap_mode: |
3f31e633 JB |
12803 | oappend ("QWORD PTR "); |
12804 | break; | |
12805 | case m_mode: | |
cb712a9e | 12806 | if (address_mode == mode_64bit) |
3f31e633 JB |
12807 | oappend ("QWORD PTR "); |
12808 | else | |
12809 | oappend ("DWORD PTR "); | |
12810 | break; | |
12811 | case f_mode: | |
12812 | if (sizeflag & DFLAG) | |
12813 | oappend ("FWORD PTR "); | |
12814 | else | |
12815 | oappend ("DWORD PTR "); | |
12816 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12817 | break; | |
12818 | case t_mode: | |
12819 | oappend ("TBYTE PTR "); | |
12820 | break; | |
12821 | case x_mode: | |
b6169b20 | 12822 | case x_swap_mode: |
c0f3af97 L |
12823 | if (need_vex) |
12824 | { | |
12825 | switch (vex.length) | |
12826 | { | |
12827 | case 128: | |
12828 | oappend ("XMMWORD PTR "); | |
12829 | break; | |
12830 | case 256: | |
12831 | oappend ("YMMWORD PTR "); | |
12832 | break; | |
12833 | default: | |
12834 | abort (); | |
12835 | } | |
12836 | } | |
12837 | else | |
12838 | oappend ("XMMWORD PTR "); | |
12839 | break; | |
12840 | case xmm_mode: | |
3f31e633 JB |
12841 | oappend ("XMMWORD PTR "); |
12842 | break; | |
c0f3af97 L |
12843 | case xmmq_mode: |
12844 | if (!need_vex) | |
12845 | abort (); | |
12846 | ||
12847 | switch (vex.length) | |
12848 | { | |
12849 | case 128: | |
12850 | oappend ("QWORD PTR "); | |
12851 | break; | |
12852 | case 256: | |
12853 | oappend ("XMMWORD PTR "); | |
12854 | break; | |
12855 | default: | |
12856 | abort (); | |
12857 | } | |
12858 | break; | |
6c30d220 L |
12859 | case xmm_mb_mode: |
12860 | if (!need_vex) | |
12861 | abort (); | |
12862 | ||
12863 | switch (vex.length) | |
12864 | { | |
12865 | case 128: | |
12866 | case 256: | |
12867 | oappend ("BYTE PTR "); | |
12868 | break; | |
12869 | default: | |
12870 | abort (); | |
12871 | } | |
12872 | break; | |
12873 | case xmm_mw_mode: | |
12874 | if (!need_vex) | |
12875 | abort (); | |
12876 | ||
12877 | switch (vex.length) | |
12878 | { | |
12879 | case 128: | |
12880 | case 256: | |
12881 | oappend ("WORD PTR "); | |
12882 | break; | |
12883 | default: | |
12884 | abort (); | |
12885 | } | |
12886 | break; | |
12887 | case xmm_md_mode: | |
12888 | if (!need_vex) | |
12889 | abort (); | |
12890 | ||
12891 | switch (vex.length) | |
12892 | { | |
12893 | case 128: | |
12894 | case 256: | |
12895 | oappend ("DWORD PTR "); | |
12896 | break; | |
12897 | default: | |
12898 | abort (); | |
12899 | } | |
12900 | break; | |
12901 | case xmm_mq_mode: | |
12902 | if (!need_vex) | |
12903 | abort (); | |
12904 | ||
12905 | switch (vex.length) | |
12906 | { | |
12907 | case 128: | |
12908 | case 256: | |
12909 | oappend ("QWORD PTR "); | |
12910 | break; | |
12911 | default: | |
12912 | abort (); | |
12913 | } | |
12914 | break; | |
12915 | case xmmdw_mode: | |
12916 | if (!need_vex) | |
12917 | abort (); | |
12918 | ||
12919 | switch (vex.length) | |
12920 | { | |
12921 | case 128: | |
12922 | oappend ("WORD PTR "); | |
12923 | break; | |
12924 | case 256: | |
12925 | oappend ("DWORD PTR "); | |
12926 | break; | |
12927 | default: | |
12928 | abort (); | |
12929 | } | |
12930 | break; | |
12931 | case xmmqd_mode: | |
12932 | if (!need_vex) | |
12933 | abort (); | |
12934 | ||
12935 | switch (vex.length) | |
12936 | { | |
12937 | case 128: | |
12938 | oappend ("DWORD PTR "); | |
12939 | break; | |
12940 | case 256: | |
12941 | oappend ("QWORD PTR "); | |
12942 | break; | |
12943 | default: | |
12944 | abort (); | |
12945 | } | |
12946 | break; | |
c0f3af97 L |
12947 | case ymmq_mode: |
12948 | if (!need_vex) | |
12949 | abort (); | |
12950 | ||
12951 | switch (vex.length) | |
12952 | { | |
12953 | case 128: | |
12954 | oappend ("QWORD PTR "); | |
12955 | break; | |
12956 | case 256: | |
12957 | oappend ("YMMWORD PTR "); | |
12958 | break; | |
12959 | default: | |
12960 | abort (); | |
12961 | } | |
12962 | break; | |
6c30d220 L |
12963 | case ymmxmm_mode: |
12964 | if (!need_vex) | |
12965 | abort (); | |
12966 | ||
12967 | switch (vex.length) | |
12968 | { | |
12969 | case 128: | |
12970 | case 256: | |
12971 | oappend ("XMMWORD PTR "); | |
12972 | break; | |
12973 | default: | |
12974 | abort (); | |
12975 | } | |
12976 | break; | |
fb9c77c7 L |
12977 | case o_mode: |
12978 | oappend ("OWORD PTR "); | |
12979 | break; | |
0bfee649 | 12980 | case vex_w_dq_mode: |
1c480963 | 12981 | case vex_scalar_w_dq_mode: |
6c30d220 L |
12982 | case vex_vsib_d_w_dq_mode: |
12983 | case vex_vsib_q_w_dq_mode: | |
0bfee649 L |
12984 | if (!need_vex) |
12985 | abort (); | |
12986 | ||
12987 | if (vex.w) | |
12988 | oappend ("QWORD PTR "); | |
12989 | else | |
12990 | oappend ("DWORD PTR "); | |
12991 | break; | |
3f31e633 JB |
12992 | default: |
12993 | break; | |
12994 | } | |
12995 | } | |
12996 | ||
252b5132 | 12997 | static void |
c0f3af97 | 12998 | OP_E_register (int bytemode, int sizeflag) |
252b5132 | 12999 | { |
c0f3af97 L |
13000 | int reg = modrm.rm; |
13001 | const char **names; | |
252b5132 | 13002 | |
c0f3af97 L |
13003 | USED_REX (REX_B); |
13004 | if ((rex & REX_B)) | |
13005 | reg += 8; | |
252b5132 | 13006 | |
b6169b20 L |
13007 | if ((sizeflag & SUFFIX_ALWAYS) |
13008 | && (bytemode == b_swap_mode || bytemode == v_swap_mode)) | |
13009 | swap_operand (); | |
13010 | ||
c0f3af97 | 13011 | switch (bytemode) |
252b5132 | 13012 | { |
c0f3af97 | 13013 | case b_mode: |
b6169b20 | 13014 | case b_swap_mode: |
c0f3af97 L |
13015 | USED_REX (0); |
13016 | if (rex) | |
13017 | names = names8rex; | |
13018 | else | |
13019 | names = names8; | |
13020 | break; | |
13021 | case w_mode: | |
13022 | names = names16; | |
13023 | break; | |
13024 | case d_mode: | |
13025 | names = names32; | |
13026 | break; | |
13027 | case q_mode: | |
13028 | names = names64; | |
13029 | break; | |
13030 | case m_mode: | |
13031 | names = address_mode == mode_64bit ? names64 : names32; | |
13032 | break; | |
13033 | case stack_v_mode: | |
7bb15c6f | 13034 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
252b5132 | 13035 | { |
c0f3af97 | 13036 | names = names64; |
252b5132 | 13037 | break; |
252b5132 | 13038 | } |
c0f3af97 L |
13039 | bytemode = v_mode; |
13040 | /* FALLTHRU */ | |
13041 | case v_mode: | |
b6169b20 | 13042 | case v_swap_mode: |
c0f3af97 L |
13043 | case dq_mode: |
13044 | case dqb_mode: | |
13045 | case dqd_mode: | |
13046 | case dqw_mode: | |
13047 | USED_REX (REX_W); | |
13048 | if (rex & REX_W) | |
13049 | names = names64; | |
c0f3af97 | 13050 | else |
f16cd0d5 | 13051 | { |
7bb15c6f | 13052 | if ((sizeflag & DFLAG) |
f16cd0d5 L |
13053 | || (bytemode != v_mode |
13054 | && bytemode != v_swap_mode)) | |
13055 | names = names32; | |
13056 | else | |
13057 | names = names16; | |
13058 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13059 | } | |
c0f3af97 L |
13060 | break; |
13061 | case 0: | |
13062 | return; | |
13063 | default: | |
13064 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
252b5132 RH |
13065 | return; |
13066 | } | |
c0f3af97 L |
13067 | oappend (names[reg]); |
13068 | } | |
13069 | ||
13070 | static void | |
c1e679ec | 13071 | OP_E_memory (int bytemode, int sizeflag) |
c0f3af97 L |
13072 | { |
13073 | bfd_vma disp = 0; | |
13074 | int add = (rex & REX_B) ? 8 : 0; | |
13075 | int riprel = 0; | |
252b5132 | 13076 | |
c0f3af97 | 13077 | USED_REX (REX_B); |
3f31e633 JB |
13078 | if (intel_syntax) |
13079 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
13080 | append_seg (); |
13081 | ||
5d669648 | 13082 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 13083 | { |
5d669648 L |
13084 | /* 32/64 bit address mode */ |
13085 | int havedisp; | |
252b5132 RH |
13086 | int havesib; |
13087 | int havebase; | |
0f7da397 | 13088 | int haveindex; |
20afcfb7 | 13089 | int needindex; |
82c18208 | 13090 | int base, rbase; |
91d6fa6a | 13091 | int vindex = 0; |
252b5132 | 13092 | int scale = 0; |
6c30d220 L |
13093 | const char **indexes64 = names64; |
13094 | const char **indexes32 = names32; | |
252b5132 RH |
13095 | |
13096 | havesib = 0; | |
13097 | havebase = 1; | |
0f7da397 | 13098 | haveindex = 0; |
7967e09e | 13099 | base = modrm.rm; |
252b5132 RH |
13100 | |
13101 | if (base == 4) | |
13102 | { | |
13103 | havesib = 1; | |
dfc8cf43 | 13104 | vindex = sib.index; |
161a04f6 L |
13105 | USED_REX (REX_X); |
13106 | if (rex & REX_X) | |
91d6fa6a | 13107 | vindex += 8; |
6c30d220 L |
13108 | switch (bytemode) |
13109 | { | |
13110 | case vex_vsib_d_w_dq_mode: | |
13111 | case vex_vsib_q_w_dq_mode: | |
13112 | if (!need_vex) | |
13113 | abort (); | |
13114 | ||
13115 | haveindex = 1; | |
13116 | switch (vex.length) | |
13117 | { | |
13118 | case 128: | |
7bb15c6f | 13119 | indexes64 = indexes32 = names_xmm; |
6c30d220 L |
13120 | break; |
13121 | case 256: | |
13122 | if (!vex.w || bytemode == vex_vsib_q_w_dq_mode) | |
7bb15c6f | 13123 | indexes64 = indexes32 = names_ymm; |
6c30d220 | 13124 | else |
7bb15c6f | 13125 | indexes64 = indexes32 = names_xmm; |
6c30d220 L |
13126 | break; |
13127 | default: | |
13128 | abort (); | |
13129 | } | |
13130 | break; | |
13131 | default: | |
13132 | haveindex = vindex != 4; | |
13133 | break; | |
13134 | } | |
13135 | scale = sib.scale; | |
13136 | base = sib.base; | |
252b5132 RH |
13137 | codep++; |
13138 | } | |
82c18208 | 13139 | rbase = base + add; |
252b5132 | 13140 | |
7967e09e | 13141 | switch (modrm.mod) |
252b5132 RH |
13142 | { |
13143 | case 0: | |
82c18208 | 13144 | if (base == 5) |
252b5132 RH |
13145 | { |
13146 | havebase = 0; | |
cb712a9e | 13147 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
13148 | riprel = 1; |
13149 | disp = get32s (); | |
252b5132 RH |
13150 | } |
13151 | break; | |
13152 | case 1: | |
13153 | FETCH_DATA (the_info, codep + 1); | |
13154 | disp = *codep++; | |
13155 | if ((disp & 0x80) != 0) | |
13156 | disp -= 0x100; | |
13157 | break; | |
13158 | case 2: | |
52b15da3 | 13159 | disp = get32s (); |
252b5132 RH |
13160 | break; |
13161 | } | |
13162 | ||
20afcfb7 L |
13163 | /* In 32bit mode, we need index register to tell [offset] from |
13164 | [eiz*1 + offset]. */ | |
13165 | needindex = (havesib | |
13166 | && !havebase | |
13167 | && !haveindex | |
13168 | && address_mode == mode_32bit); | |
13169 | havedisp = (havebase | |
13170 | || needindex | |
13171 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 13172 | |
252b5132 | 13173 | if (!intel_syntax) |
82c18208 | 13174 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 13175 | { |
5d669648 L |
13176 | if (havedisp || riprel) |
13177 | print_displacement (scratchbuf, disp); | |
13178 | else | |
13179 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 13180 | oappend (scratchbuf); |
52b15da3 JH |
13181 | if (riprel) |
13182 | { | |
13183 | set_op (disp, 1); | |
87767711 | 13184 | oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)"); |
52b15da3 | 13185 | } |
db6eb5be | 13186 | } |
2da11e11 | 13187 | |
87767711 JB |
13188 | if (havebase || haveindex || riprel) |
13189 | used_prefixes |= PREFIX_ADDR; | |
13190 | ||
5d669648 | 13191 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 13192 | { |
252b5132 | 13193 | *obufp++ = open_char; |
52b15da3 | 13194 | if (intel_syntax && riprel) |
185b1163 L |
13195 | { |
13196 | set_op (disp, 1); | |
87767711 | 13197 | oappend (sizeflag & AFLAG ? "rip" : "eip"); |
185b1163 | 13198 | } |
db6eb5be | 13199 | *obufp = '\0'; |
252b5132 | 13200 | if (havebase) |
cb712a9e | 13201 | oappend (address_mode == mode_64bit && (sizeflag & AFLAG) |
82c18208 | 13202 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
13203 | if (havesib) |
13204 | { | |
db51cc60 L |
13205 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
13206 | print index to tell base + index from base. */ | |
13207 | if (scale != 0 | |
20afcfb7 | 13208 | || needindex |
db51cc60 L |
13209 | || haveindex |
13210 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 13211 | { |
9306ca4a | 13212 | if (!intel_syntax || havebase) |
db6eb5be | 13213 | { |
9306ca4a JB |
13214 | *obufp++ = separator_char; |
13215 | *obufp = '\0'; | |
db6eb5be | 13216 | } |
db51cc60 | 13217 | if (haveindex) |
7bb15c6f | 13218 | oappend (address_mode == mode_64bit |
db51cc60 | 13219 | && (sizeflag & AFLAG) |
6c30d220 | 13220 | ? indexes64[vindex] : indexes32[vindex]); |
db51cc60 | 13221 | else |
7bb15c6f | 13222 | oappend (address_mode == mode_64bit |
db51cc60 L |
13223 | && (sizeflag & AFLAG) |
13224 | ? index64 : index32); | |
13225 | ||
db6eb5be AM |
13226 | *obufp++ = scale_char; |
13227 | *obufp = '\0'; | |
13228 | sprintf (scratchbuf, "%d", 1 << scale); | |
13229 | oappend (scratchbuf); | |
13230 | } | |
252b5132 | 13231 | } |
185b1163 | 13232 | if (intel_syntax |
82c18208 | 13233 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 13234 | { |
db51cc60 | 13235 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
13236 | { |
13237 | *obufp++ = '+'; | |
13238 | *obufp = '\0'; | |
13239 | } | |
05203043 | 13240 | else if (modrm.mod != 1 && disp != -disp) |
3d456fa1 JB |
13241 | { |
13242 | *obufp++ = '-'; | |
13243 | *obufp = '\0'; | |
13244 | disp = - (bfd_signed_vma) disp; | |
13245 | } | |
13246 | ||
db51cc60 L |
13247 | if (havedisp) |
13248 | print_displacement (scratchbuf, disp); | |
13249 | else | |
13250 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
13251 | oappend (scratchbuf); |
13252 | } | |
252b5132 RH |
13253 | |
13254 | *obufp++ = close_char; | |
db6eb5be | 13255 | *obufp = '\0'; |
252b5132 RH |
13256 | } |
13257 | else if (intel_syntax) | |
db6eb5be | 13258 | { |
82c18208 | 13259 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 13260 | { |
252b5132 RH |
13261 | if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS |
13262 | | PREFIX_ES | PREFIX_FS | PREFIX_GS)) | |
13263 | ; | |
13264 | else | |
13265 | { | |
d708bcba | 13266 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
13267 | oappend (":"); |
13268 | } | |
52b15da3 | 13269 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
13270 | oappend (scratchbuf); |
13271 | } | |
13272 | } | |
252b5132 RH |
13273 | } |
13274 | else | |
f16cd0d5 L |
13275 | { |
13276 | /* 16 bit address mode */ | |
13277 | used_prefixes |= prefixes & PREFIX_ADDR; | |
7967e09e | 13278 | switch (modrm.mod) |
252b5132 RH |
13279 | { |
13280 | case 0: | |
7967e09e | 13281 | if (modrm.rm == 6) |
252b5132 RH |
13282 | { |
13283 | disp = get16 (); | |
13284 | if ((disp & 0x8000) != 0) | |
13285 | disp -= 0x10000; | |
13286 | } | |
13287 | break; | |
13288 | case 1: | |
13289 | FETCH_DATA (the_info, codep + 1); | |
13290 | disp = *codep++; | |
13291 | if ((disp & 0x80) != 0) | |
13292 | disp -= 0x100; | |
13293 | break; | |
13294 | case 2: | |
13295 | disp = get16 (); | |
13296 | if ((disp & 0x8000) != 0) | |
13297 | disp -= 0x10000; | |
13298 | break; | |
13299 | } | |
13300 | ||
13301 | if (!intel_syntax) | |
7967e09e | 13302 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 13303 | { |
5d669648 | 13304 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
13305 | oappend (scratchbuf); |
13306 | } | |
252b5132 | 13307 | |
7967e09e | 13308 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
13309 | { |
13310 | *obufp++ = open_char; | |
db6eb5be | 13311 | *obufp = '\0'; |
7967e09e | 13312 | oappend (index16[modrm.rm]); |
5d669648 L |
13313 | if (intel_syntax |
13314 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 13315 | { |
5d669648 | 13316 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
13317 | { |
13318 | *obufp++ = '+'; | |
13319 | *obufp = '\0'; | |
13320 | } | |
7967e09e | 13321 | else if (modrm.mod != 1) |
3d456fa1 JB |
13322 | { |
13323 | *obufp++ = '-'; | |
13324 | *obufp = '\0'; | |
13325 | disp = - (bfd_signed_vma) disp; | |
13326 | } | |
13327 | ||
5d669648 | 13328 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
13329 | oappend (scratchbuf); |
13330 | } | |
13331 | ||
db6eb5be AM |
13332 | *obufp++ = close_char; |
13333 | *obufp = '\0'; | |
252b5132 | 13334 | } |
3d456fa1 JB |
13335 | else if (intel_syntax) |
13336 | { | |
13337 | if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | |
13338 | | PREFIX_ES | PREFIX_FS | PREFIX_GS)) | |
13339 | ; | |
13340 | else | |
13341 | { | |
13342 | oappend (names_seg[ds_reg - es_reg]); | |
13343 | oappend (":"); | |
13344 | } | |
13345 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
13346 | oappend (scratchbuf); | |
13347 | } | |
252b5132 RH |
13348 | } |
13349 | } | |
13350 | ||
c0f3af97 | 13351 | static void |
8b3f93e7 | 13352 | OP_E (int bytemode, int sizeflag) |
c0f3af97 L |
13353 | { |
13354 | /* Skip mod/rm byte. */ | |
13355 | MODRM_CHECK; | |
13356 | codep++; | |
13357 | ||
13358 | if (modrm.mod == 3) | |
13359 | OP_E_register (bytemode, sizeflag); | |
13360 | else | |
c1e679ec | 13361 | OP_E_memory (bytemode, sizeflag); |
c0f3af97 L |
13362 | } |
13363 | ||
252b5132 | 13364 | static void |
26ca5450 | 13365 | OP_G (int bytemode, int sizeflag) |
252b5132 | 13366 | { |
52b15da3 | 13367 | int add = 0; |
161a04f6 L |
13368 | USED_REX (REX_R); |
13369 | if (rex & REX_R) | |
52b15da3 | 13370 | add += 8; |
252b5132 RH |
13371 | switch (bytemode) |
13372 | { | |
13373 | case b_mode: | |
52b15da3 JH |
13374 | USED_REX (0); |
13375 | if (rex) | |
7967e09e | 13376 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 13377 | else |
7967e09e | 13378 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
13379 | break; |
13380 | case w_mode: | |
7967e09e | 13381 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
13382 | break; |
13383 | case d_mode: | |
7967e09e | 13384 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
13385 | break; |
13386 | case q_mode: | |
7967e09e | 13387 | oappend (names64[modrm.reg + add]); |
252b5132 RH |
13388 | break; |
13389 | case v_mode: | |
9306ca4a | 13390 | case dq_mode: |
42903f7f L |
13391 | case dqb_mode: |
13392 | case dqd_mode: | |
9306ca4a | 13393 | case dqw_mode: |
161a04f6 L |
13394 | USED_REX (REX_W); |
13395 | if (rex & REX_W) | |
7967e09e | 13396 | oappend (names64[modrm.reg + add]); |
252b5132 | 13397 | else |
f16cd0d5 L |
13398 | { |
13399 | if ((sizeflag & DFLAG) || bytemode != v_mode) | |
13400 | oappend (names32[modrm.reg + add]); | |
13401 | else | |
13402 | oappend (names16[modrm.reg + add]); | |
13403 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13404 | } | |
252b5132 | 13405 | break; |
90700ea2 | 13406 | case m_mode: |
cb712a9e | 13407 | if (address_mode == mode_64bit) |
7967e09e | 13408 | oappend (names64[modrm.reg + add]); |
90700ea2 | 13409 | else |
7967e09e | 13410 | oappend (names32[modrm.reg + add]); |
90700ea2 | 13411 | break; |
252b5132 RH |
13412 | default: |
13413 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
13414 | break; | |
13415 | } | |
13416 | } | |
13417 | ||
52b15da3 | 13418 | static bfd_vma |
26ca5450 | 13419 | get64 (void) |
52b15da3 | 13420 | { |
5dd0794d | 13421 | bfd_vma x; |
52b15da3 | 13422 | #ifdef BFD64 |
5dd0794d AM |
13423 | unsigned int a; |
13424 | unsigned int b; | |
13425 | ||
52b15da3 JH |
13426 | FETCH_DATA (the_info, codep + 8); |
13427 | a = *codep++ & 0xff; | |
13428 | a |= (*codep++ & 0xff) << 8; | |
13429 | a |= (*codep++ & 0xff) << 16; | |
13430 | a |= (*codep++ & 0xff) << 24; | |
5dd0794d | 13431 | b = *codep++ & 0xff; |
52b15da3 JH |
13432 | b |= (*codep++ & 0xff) << 8; |
13433 | b |= (*codep++ & 0xff) << 16; | |
13434 | b |= (*codep++ & 0xff) << 24; | |
13435 | x = a + ((bfd_vma) b << 32); | |
13436 | #else | |
6608db57 | 13437 | abort (); |
5dd0794d | 13438 | x = 0; |
52b15da3 JH |
13439 | #endif |
13440 | return x; | |
13441 | } | |
13442 | ||
13443 | static bfd_signed_vma | |
26ca5450 | 13444 | get32 (void) |
252b5132 | 13445 | { |
52b15da3 | 13446 | bfd_signed_vma x = 0; |
252b5132 RH |
13447 | |
13448 | FETCH_DATA (the_info, codep + 4); | |
52b15da3 JH |
13449 | x = *codep++ & (bfd_signed_vma) 0xff; |
13450 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
13451 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
13452 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
13453 | return x; | |
13454 | } | |
13455 | ||
13456 | static bfd_signed_vma | |
26ca5450 | 13457 | get32s (void) |
52b15da3 JH |
13458 | { |
13459 | bfd_signed_vma x = 0; | |
13460 | ||
13461 | FETCH_DATA (the_info, codep + 4); | |
13462 | x = *codep++ & (bfd_signed_vma) 0xff; | |
13463 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
13464 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
13465 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
13466 | ||
13467 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); | |
13468 | ||
252b5132 RH |
13469 | return x; |
13470 | } | |
13471 | ||
13472 | static int | |
26ca5450 | 13473 | get16 (void) |
252b5132 RH |
13474 | { |
13475 | int x = 0; | |
13476 | ||
13477 | FETCH_DATA (the_info, codep + 2); | |
13478 | x = *codep++ & 0xff; | |
13479 | x |= (*codep++ & 0xff) << 8; | |
13480 | return x; | |
13481 | } | |
13482 | ||
13483 | static void | |
26ca5450 | 13484 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
13485 | { |
13486 | op_index[op_ad] = op_ad; | |
cb712a9e | 13487 | if (address_mode == mode_64bit) |
7081ff04 AJ |
13488 | { |
13489 | op_address[op_ad] = op; | |
13490 | op_riprel[op_ad] = riprel; | |
13491 | } | |
13492 | else | |
13493 | { | |
13494 | /* Mask to get a 32-bit address. */ | |
13495 | op_address[op_ad] = op & 0xffffffff; | |
13496 | op_riprel[op_ad] = riprel & 0xffffffff; | |
13497 | } | |
252b5132 RH |
13498 | } |
13499 | ||
13500 | static void | |
26ca5450 | 13501 | OP_REG (int code, int sizeflag) |
252b5132 | 13502 | { |
2da11e11 | 13503 | const char *s; |
9b60702d | 13504 | int add; |
de882298 RM |
13505 | |
13506 | switch (code) | |
13507 | { | |
13508 | case es_reg: case ss_reg: case cs_reg: | |
13509 | case ds_reg: case fs_reg: case gs_reg: | |
13510 | oappend (names_seg[code - es_reg]); | |
13511 | return; | |
13512 | } | |
13513 | ||
161a04f6 L |
13514 | USED_REX (REX_B); |
13515 | if (rex & REX_B) | |
52b15da3 | 13516 | add = 8; |
9b60702d L |
13517 | else |
13518 | add = 0; | |
52b15da3 JH |
13519 | |
13520 | switch (code) | |
13521 | { | |
52b15da3 JH |
13522 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
13523 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
13524 | s = names16[code - ax_reg + add]; | |
13525 | break; | |
52b15da3 JH |
13526 | case al_reg: case ah_reg: case cl_reg: case ch_reg: |
13527 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
13528 | USED_REX (0); | |
13529 | if (rex) | |
13530 | s = names8rex[code - al_reg + add]; | |
13531 | else | |
13532 | s = names8[code - al_reg]; | |
13533 | break; | |
6439fc28 AM |
13534 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
13535 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
7bb15c6f RM |
13536 | if (address_mode == mode_64bit |
13537 | && ((sizeflag & DFLAG) || (rex & REX_W))) | |
6439fc28 AM |
13538 | { |
13539 | s = names64[code - rAX_reg + add]; | |
13540 | break; | |
13541 | } | |
13542 | code += eAX_reg - rAX_reg; | |
6608db57 | 13543 | /* Fall through. */ |
52b15da3 JH |
13544 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
13545 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
13546 | USED_REX (REX_W); |
13547 | if (rex & REX_W) | |
52b15da3 | 13548 | s = names64[code - eAX_reg + add]; |
52b15da3 | 13549 | else |
f16cd0d5 L |
13550 | { |
13551 | if (sizeflag & DFLAG) | |
13552 | s = names32[code - eAX_reg + add]; | |
13553 | else | |
13554 | s = names16[code - eAX_reg + add]; | |
13555 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13556 | } | |
52b15da3 | 13557 | break; |
52b15da3 JH |
13558 | default: |
13559 | s = INTERNAL_DISASSEMBLER_ERROR; | |
13560 | break; | |
13561 | } | |
13562 | oappend (s); | |
13563 | } | |
13564 | ||
13565 | static void | |
26ca5450 | 13566 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
13567 | { |
13568 | const char *s; | |
252b5132 RH |
13569 | |
13570 | switch (code) | |
13571 | { | |
13572 | case indir_dx_reg: | |
d708bcba | 13573 | if (intel_syntax) |
52fd6d94 | 13574 | s = "dx"; |
d708bcba | 13575 | else |
db6eb5be | 13576 | s = "(%dx)"; |
252b5132 RH |
13577 | break; |
13578 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: | |
13579 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
13580 | s = names16[code - ax_reg]; | |
13581 | break; | |
13582 | case es_reg: case ss_reg: case cs_reg: | |
13583 | case ds_reg: case fs_reg: case gs_reg: | |
13584 | s = names_seg[code - es_reg]; | |
13585 | break; | |
13586 | case al_reg: case ah_reg: case cl_reg: case ch_reg: | |
13587 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
52b15da3 JH |
13588 | USED_REX (0); |
13589 | if (rex) | |
13590 | s = names8rex[code - al_reg]; | |
13591 | else | |
13592 | s = names8[code - al_reg]; | |
252b5132 RH |
13593 | break; |
13594 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: | |
13595 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
13596 | USED_REX (REX_W); |
13597 | if (rex & REX_W) | |
52b15da3 | 13598 | s = names64[code - eAX_reg]; |
252b5132 | 13599 | else |
f16cd0d5 L |
13600 | { |
13601 | if (sizeflag & DFLAG) | |
13602 | s = names32[code - eAX_reg]; | |
13603 | else | |
13604 | s = names16[code - eAX_reg]; | |
13605 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13606 | } | |
252b5132 | 13607 | break; |
52fd6d94 | 13608 | case z_mode_ax_reg: |
161a04f6 | 13609 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
13610 | s = *names32; |
13611 | else | |
13612 | s = *names16; | |
161a04f6 | 13613 | if (!(rex & REX_W)) |
52fd6d94 JB |
13614 | used_prefixes |= (prefixes & PREFIX_DATA); |
13615 | break; | |
252b5132 RH |
13616 | default: |
13617 | s = INTERNAL_DISASSEMBLER_ERROR; | |
13618 | break; | |
13619 | } | |
13620 | oappend (s); | |
13621 | } | |
13622 | ||
13623 | static void | |
26ca5450 | 13624 | OP_I (int bytemode, int sizeflag) |
252b5132 | 13625 | { |
52b15da3 JH |
13626 | bfd_signed_vma op; |
13627 | bfd_signed_vma mask = -1; | |
252b5132 RH |
13628 | |
13629 | switch (bytemode) | |
13630 | { | |
13631 | case b_mode: | |
13632 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
13633 | op = *codep++; |
13634 | mask = 0xff; | |
13635 | break; | |
13636 | case q_mode: | |
cb712a9e | 13637 | if (address_mode == mode_64bit) |
6439fc28 AM |
13638 | { |
13639 | op = get32s (); | |
13640 | break; | |
13641 | } | |
6608db57 | 13642 | /* Fall through. */ |
252b5132 | 13643 | case v_mode: |
161a04f6 L |
13644 | USED_REX (REX_W); |
13645 | if (rex & REX_W) | |
52b15da3 | 13646 | op = get32s (); |
252b5132 | 13647 | else |
52b15da3 | 13648 | { |
f16cd0d5 L |
13649 | if (sizeflag & DFLAG) |
13650 | { | |
13651 | op = get32 (); | |
13652 | mask = 0xffffffff; | |
13653 | } | |
13654 | else | |
13655 | { | |
13656 | op = get16 (); | |
13657 | mask = 0xfffff; | |
13658 | } | |
13659 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 13660 | } |
252b5132 RH |
13661 | break; |
13662 | case w_mode: | |
52b15da3 | 13663 | mask = 0xfffff; |
252b5132 RH |
13664 | op = get16 (); |
13665 | break; | |
9306ca4a JB |
13666 | case const_1_mode: |
13667 | if (intel_syntax) | |
13668 | oappend ("1"); | |
13669 | return; | |
252b5132 RH |
13670 | default: |
13671 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
13672 | return; | |
13673 | } | |
13674 | ||
52b15da3 JH |
13675 | op &= mask; |
13676 | scratchbuf[0] = '$'; | |
d708bcba AM |
13677 | print_operand_value (scratchbuf + 1, 1, op); |
13678 | oappend (scratchbuf + intel_syntax); | |
52b15da3 JH |
13679 | scratchbuf[0] = '\0'; |
13680 | } | |
13681 | ||
13682 | static void | |
26ca5450 | 13683 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 JH |
13684 | { |
13685 | bfd_signed_vma op; | |
13686 | bfd_signed_vma mask = -1; | |
13687 | ||
cb712a9e | 13688 | if (address_mode != mode_64bit) |
6439fc28 AM |
13689 | { |
13690 | OP_I (bytemode, sizeflag); | |
13691 | return; | |
13692 | } | |
13693 | ||
52b15da3 JH |
13694 | switch (bytemode) |
13695 | { | |
13696 | case b_mode: | |
13697 | FETCH_DATA (the_info, codep + 1); | |
13698 | op = *codep++; | |
13699 | mask = 0xff; | |
13700 | break; | |
13701 | case v_mode: | |
161a04f6 L |
13702 | USED_REX (REX_W); |
13703 | if (rex & REX_W) | |
52b15da3 | 13704 | op = get64 (); |
52b15da3 JH |
13705 | else |
13706 | { | |
f16cd0d5 L |
13707 | if (sizeflag & DFLAG) |
13708 | { | |
13709 | op = get32 (); | |
13710 | mask = 0xffffffff; | |
13711 | } | |
13712 | else | |
13713 | { | |
13714 | op = get16 (); | |
13715 | mask = 0xfffff; | |
13716 | } | |
13717 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 13718 | } |
52b15da3 JH |
13719 | break; |
13720 | case w_mode: | |
13721 | mask = 0xfffff; | |
13722 | op = get16 (); | |
13723 | break; | |
13724 | default: | |
13725 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
13726 | return; | |
13727 | } | |
13728 | ||
13729 | op &= mask; | |
13730 | scratchbuf[0] = '$'; | |
d708bcba AM |
13731 | print_operand_value (scratchbuf + 1, 1, op); |
13732 | oappend (scratchbuf + intel_syntax); | |
252b5132 RH |
13733 | scratchbuf[0] = '\0'; |
13734 | } | |
13735 | ||
13736 | static void | |
26ca5450 | 13737 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 13738 | { |
52b15da3 | 13739 | bfd_signed_vma op; |
252b5132 RH |
13740 | |
13741 | switch (bytemode) | |
13742 | { | |
13743 | case b_mode: | |
e3949f17 | 13744 | case b_T_mode: |
252b5132 RH |
13745 | FETCH_DATA (the_info, codep + 1); |
13746 | op = *codep++; | |
13747 | if ((op & 0x80) != 0) | |
13748 | op -= 0x100; | |
e3949f17 L |
13749 | if (bytemode == b_T_mode) |
13750 | { | |
13751 | if (address_mode != mode_64bit | |
7bb15c6f | 13752 | || !((sizeflag & DFLAG) || (rex & REX_W))) |
e3949f17 | 13753 | { |
7bb15c6f RM |
13754 | /* The operand-size prefix is overridden by a REX prefix. */ |
13755 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
e3949f17 L |
13756 | op &= 0xffffffff; |
13757 | else | |
13758 | op &= 0xffff; | |
13759 | } | |
13760 | } | |
13761 | else | |
13762 | { | |
13763 | if (!(rex & REX_W)) | |
13764 | { | |
13765 | if (sizeflag & DFLAG) | |
13766 | op &= 0xffffffff; | |
13767 | else | |
13768 | op &= 0xffff; | |
13769 | } | |
13770 | } | |
252b5132 RH |
13771 | break; |
13772 | case v_mode: | |
7bb15c6f RM |
13773 | /* The operand-size prefix is overridden by a REX prefix. */ |
13774 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
52b15da3 | 13775 | op = get32s (); |
252b5132 | 13776 | else |
d9e3625e | 13777 | op = get16 (); |
252b5132 RH |
13778 | break; |
13779 | default: | |
13780 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
13781 | return; | |
13782 | } | |
52b15da3 JH |
13783 | |
13784 | scratchbuf[0] = '$'; | |
13785 | print_operand_value (scratchbuf + 1, 1, op); | |
d708bcba | 13786 | oappend (scratchbuf + intel_syntax); |
252b5132 RH |
13787 | } |
13788 | ||
13789 | static void | |
26ca5450 | 13790 | OP_J (int bytemode, int sizeflag) |
252b5132 | 13791 | { |
52b15da3 | 13792 | bfd_vma disp; |
7081ff04 | 13793 | bfd_vma mask = -1; |
65ca155d | 13794 | bfd_vma segment = 0; |
252b5132 RH |
13795 | |
13796 | switch (bytemode) | |
13797 | { | |
13798 | case b_mode: | |
13799 | FETCH_DATA (the_info, codep + 1); | |
13800 | disp = *codep++; | |
13801 | if ((disp & 0x80) != 0) | |
13802 | disp -= 0x100; | |
13803 | break; | |
13804 | case v_mode: | |
f16cd0d5 | 13805 | USED_REX (REX_W); |
161a04f6 | 13806 | if ((sizeflag & DFLAG) || (rex & REX_W)) |
52b15da3 | 13807 | disp = get32s (); |
252b5132 RH |
13808 | else |
13809 | { | |
13810 | disp = get16 (); | |
206717e8 L |
13811 | if ((disp & 0x8000) != 0) |
13812 | disp -= 0x10000; | |
65ca155d L |
13813 | /* In 16bit mode, address is wrapped around at 64k within |
13814 | the same segment. Otherwise, a data16 prefix on a jump | |
13815 | instruction means that the pc is masked to 16 bits after | |
13816 | the displacement is added! */ | |
13817 | mask = 0xffff; | |
13818 | if ((prefixes & PREFIX_DATA) == 0) | |
13819 | segment = ((start_pc + codep - start_codep) | |
13820 | & ~((bfd_vma) 0xffff)); | |
252b5132 | 13821 | } |
f16cd0d5 L |
13822 | if (!(rex & REX_W)) |
13823 | used_prefixes |= (prefixes & PREFIX_DATA); | |
252b5132 RH |
13824 | break; |
13825 | default: | |
13826 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
13827 | return; | |
13828 | } | |
42d5f9c6 | 13829 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
52b15da3 JH |
13830 | set_op (disp, 0); |
13831 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
13832 | oappend (scratchbuf); |
13833 | } | |
13834 | ||
252b5132 | 13835 | static void |
ed7841b3 | 13836 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 13837 | { |
ed7841b3 | 13838 | if (bytemode == w_mode) |
7967e09e | 13839 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 13840 | else |
7967e09e | 13841 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
13842 | } |
13843 | ||
13844 | static void | |
26ca5450 | 13845 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
13846 | { |
13847 | int seg, offset; | |
13848 | ||
c608c12e | 13849 | if (sizeflag & DFLAG) |
252b5132 | 13850 | { |
c608c12e AM |
13851 | offset = get32 (); |
13852 | seg = get16 (); | |
252b5132 | 13853 | } |
c608c12e AM |
13854 | else |
13855 | { | |
13856 | offset = get16 (); | |
13857 | seg = get16 (); | |
13858 | } | |
7d421014 | 13859 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 13860 | if (intel_syntax) |
3f31e633 | 13861 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
13862 | else |
13863 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 13864 | oappend (scratchbuf); |
252b5132 RH |
13865 | } |
13866 | ||
252b5132 | 13867 | static void |
3f31e633 | 13868 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 13869 | { |
52b15da3 | 13870 | bfd_vma off; |
252b5132 | 13871 | |
3f31e633 JB |
13872 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
13873 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
13874 | append_seg (); |
13875 | ||
cb712a9e | 13876 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
13877 | off = get32 (); |
13878 | else | |
13879 | off = get16 (); | |
13880 | ||
13881 | if (intel_syntax) | |
13882 | { | |
13883 | if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | |
db6eb5be | 13884 | | PREFIX_ES | PREFIX_FS | PREFIX_GS))) |
252b5132 | 13885 | { |
d708bcba | 13886 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
13887 | oappend (":"); |
13888 | } | |
13889 | } | |
52b15da3 JH |
13890 | print_operand_value (scratchbuf, 1, off); |
13891 | oappend (scratchbuf); | |
13892 | } | |
6439fc28 | 13893 | |
52b15da3 | 13894 | static void |
3f31e633 | 13895 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
13896 | { |
13897 | bfd_vma off; | |
13898 | ||
539e75ad L |
13899 | if (address_mode != mode_64bit |
13900 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
13901 | { |
13902 | OP_OFF (bytemode, sizeflag); | |
13903 | return; | |
13904 | } | |
13905 | ||
3f31e633 JB |
13906 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
13907 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
13908 | append_seg (); |
13909 | ||
6608db57 | 13910 | off = get64 (); |
52b15da3 JH |
13911 | |
13912 | if (intel_syntax) | |
13913 | { | |
13914 | if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | |
db6eb5be | 13915 | | PREFIX_ES | PREFIX_FS | PREFIX_GS))) |
52b15da3 | 13916 | { |
d708bcba | 13917 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
13918 | oappend (":"); |
13919 | } | |
13920 | } | |
13921 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
13922 | oappend (scratchbuf); |
13923 | } | |
13924 | ||
13925 | static void | |
26ca5450 | 13926 | ptr_reg (int code, int sizeflag) |
252b5132 | 13927 | { |
2da11e11 | 13928 | const char *s; |
d708bcba | 13929 | |
1d9f512f | 13930 | *obufp++ = open_char; |
20f0a1fc | 13931 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 13932 | if (address_mode == mode_64bit) |
c1a64871 JH |
13933 | { |
13934 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 13935 | s = names32[code - eAX_reg]; |
c1a64871 | 13936 | else |
db6eb5be | 13937 | s = names64[code - eAX_reg]; |
c1a64871 | 13938 | } |
52b15da3 | 13939 | else if (sizeflag & AFLAG) |
252b5132 RH |
13940 | s = names32[code - eAX_reg]; |
13941 | else | |
13942 | s = names16[code - eAX_reg]; | |
13943 | oappend (s); | |
1d9f512f AM |
13944 | *obufp++ = close_char; |
13945 | *obufp = 0; | |
252b5132 RH |
13946 | } |
13947 | ||
13948 | static void | |
26ca5450 | 13949 | OP_ESreg (int code, int sizeflag) |
252b5132 | 13950 | { |
9306ca4a | 13951 | if (intel_syntax) |
52fd6d94 JB |
13952 | { |
13953 | switch (codep[-1]) | |
13954 | { | |
13955 | case 0x6d: /* insw/insl */ | |
13956 | intel_operand_size (z_mode, sizeflag); | |
13957 | break; | |
13958 | case 0xa5: /* movsw/movsl/movsq */ | |
13959 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
13960 | case 0xab: /* stosw/stosl */ | |
13961 | case 0xaf: /* scasw/scasl */ | |
13962 | intel_operand_size (v_mode, sizeflag); | |
13963 | break; | |
13964 | default: | |
13965 | intel_operand_size (b_mode, sizeflag); | |
13966 | } | |
13967 | } | |
d708bcba | 13968 | oappend ("%es:" + intel_syntax); |
252b5132 RH |
13969 | ptr_reg (code, sizeflag); |
13970 | } | |
13971 | ||
13972 | static void | |
26ca5450 | 13973 | OP_DSreg (int code, int sizeflag) |
252b5132 | 13974 | { |
9306ca4a | 13975 | if (intel_syntax) |
52fd6d94 JB |
13976 | { |
13977 | switch (codep[-1]) | |
13978 | { | |
13979 | case 0x6f: /* outsw/outsl */ | |
13980 | intel_operand_size (z_mode, sizeflag); | |
13981 | break; | |
13982 | case 0xa5: /* movsw/movsl/movsq */ | |
13983 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
13984 | case 0xad: /* lodsw/lodsl/lodsq */ | |
13985 | intel_operand_size (v_mode, sizeflag); | |
13986 | break; | |
13987 | default: | |
13988 | intel_operand_size (b_mode, sizeflag); | |
13989 | } | |
13990 | } | |
252b5132 RH |
13991 | if ((prefixes |
13992 | & (PREFIX_CS | |
13993 | | PREFIX_DS | |
13994 | | PREFIX_SS | |
13995 | | PREFIX_ES | |
13996 | | PREFIX_FS | |
13997 | | PREFIX_GS)) == 0) | |
13998 | prefixes |= PREFIX_DS; | |
6608db57 | 13999 | append_seg (); |
252b5132 RH |
14000 | ptr_reg (code, sizeflag); |
14001 | } | |
14002 | ||
252b5132 | 14003 | static void |
26ca5450 | 14004 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 14005 | { |
9b60702d | 14006 | int add; |
161a04f6 | 14007 | if (rex & REX_R) |
c4a530c5 | 14008 | { |
161a04f6 | 14009 | USED_REX (REX_R); |
c4a530c5 JB |
14010 | add = 8; |
14011 | } | |
cb712a9e | 14012 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 14013 | { |
f16cd0d5 | 14014 | all_prefixes[last_lock_prefix] = 0; |
c4a530c5 JB |
14015 | used_prefixes |= PREFIX_LOCK; |
14016 | add = 8; | |
14017 | } | |
9b60702d L |
14018 | else |
14019 | add = 0; | |
7967e09e | 14020 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
d708bcba | 14021 | oappend (scratchbuf + intel_syntax); |
252b5132 RH |
14022 | } |
14023 | ||
252b5132 | 14024 | static void |
26ca5450 | 14025 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 14026 | { |
9b60702d | 14027 | int add; |
161a04f6 L |
14028 | USED_REX (REX_R); |
14029 | if (rex & REX_R) | |
52b15da3 | 14030 | add = 8; |
9b60702d L |
14031 | else |
14032 | add = 0; | |
d708bcba | 14033 | if (intel_syntax) |
7967e09e | 14034 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
d708bcba | 14035 | else |
7967e09e | 14036 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
14037 | oappend (scratchbuf); |
14038 | } | |
14039 | ||
252b5132 | 14040 | static void |
26ca5450 | 14041 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 14042 | { |
7967e09e | 14043 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
d708bcba | 14044 | oappend (scratchbuf + intel_syntax); |
252b5132 RH |
14045 | } |
14046 | ||
14047 | static void | |
6f74c397 | 14048 | OP_R (int bytemode, int sizeflag) |
252b5132 | 14049 | { |
7967e09e | 14050 | if (modrm.mod == 3) |
2da11e11 AM |
14051 | OP_E (bytemode, sizeflag); |
14052 | else | |
6608db57 | 14053 | BadOp (); |
252b5132 RH |
14054 | } |
14055 | ||
14056 | static void | |
26ca5450 | 14057 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 14058 | { |
b9733481 L |
14059 | int reg = modrm.reg; |
14060 | const char **names; | |
14061 | ||
041bd2e0 JH |
14062 | used_prefixes |= (prefixes & PREFIX_DATA); |
14063 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 14064 | { |
b9733481 | 14065 | names = names_xmm; |
161a04f6 L |
14066 | USED_REX (REX_R); |
14067 | if (rex & REX_R) | |
b9733481 | 14068 | reg += 8; |
20f0a1fc | 14069 | } |
041bd2e0 | 14070 | else |
b9733481 L |
14071 | names = names_mm; |
14072 | oappend (names[reg]); | |
252b5132 RH |
14073 | } |
14074 | ||
c608c12e | 14075 | static void |
c0f3af97 | 14076 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 14077 | { |
b9733481 L |
14078 | int reg = modrm.reg; |
14079 | const char **names; | |
14080 | ||
161a04f6 L |
14081 | USED_REX (REX_R); |
14082 | if (rex & REX_R) | |
b9733481 | 14083 | reg += 8; |
539f890d L |
14084 | if (need_vex |
14085 | && bytemode != xmm_mode | |
14086 | && bytemode != scalar_mode) | |
c0f3af97 L |
14087 | { |
14088 | switch (vex.length) | |
14089 | { | |
14090 | case 128: | |
b9733481 | 14091 | names = names_xmm; |
c0f3af97 L |
14092 | break; |
14093 | case 256: | |
6c30d220 L |
14094 | if (vex.w || bytemode != vex_vsib_q_w_dq_mode) |
14095 | names = names_ymm; | |
14096 | else | |
14097 | names = names_xmm; | |
c0f3af97 L |
14098 | break; |
14099 | default: | |
14100 | abort (); | |
14101 | } | |
14102 | } | |
14103 | else | |
b9733481 L |
14104 | names = names_xmm; |
14105 | oappend (names[reg]); | |
c608c12e AM |
14106 | } |
14107 | ||
252b5132 | 14108 | static void |
26ca5450 | 14109 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 14110 | { |
b9733481 L |
14111 | int reg; |
14112 | const char **names; | |
14113 | ||
7967e09e | 14114 | if (modrm.mod != 3) |
252b5132 | 14115 | { |
b6169b20 L |
14116 | if (intel_syntax |
14117 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
9306ca4a JB |
14118 | { |
14119 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
14120 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14121 | } | |
252b5132 RH |
14122 | OP_E (bytemode, sizeflag); |
14123 | return; | |
14124 | } | |
14125 | ||
b6169b20 L |
14126 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
14127 | swap_operand (); | |
14128 | ||
6608db57 | 14129 | /* Skip mod/rm byte. */ |
4bba6815 | 14130 | MODRM_CHECK; |
252b5132 | 14131 | codep++; |
041bd2e0 | 14132 | used_prefixes |= (prefixes & PREFIX_DATA); |
b9733481 | 14133 | reg = modrm.rm; |
041bd2e0 | 14134 | if (prefixes & PREFIX_DATA) |
20f0a1fc | 14135 | { |
b9733481 | 14136 | names = names_xmm; |
161a04f6 L |
14137 | USED_REX (REX_B); |
14138 | if (rex & REX_B) | |
b9733481 | 14139 | reg += 8; |
20f0a1fc | 14140 | } |
041bd2e0 | 14141 | else |
b9733481 L |
14142 | names = names_mm; |
14143 | oappend (names[reg]); | |
252b5132 RH |
14144 | } |
14145 | ||
246c51aa L |
14146 | /* cvt* are the only instructions in sse2 which have |
14147 | both SSE and MMX operands and also have 0x66 prefix | |
14148 | in their opcode. 0x66 was originally used to differentiate | |
14149 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
14150 | cvt* separately using OP_EMC and OP_MXC */ |
14151 | static void | |
14152 | OP_EMC (int bytemode, int sizeflag) | |
14153 | { | |
7967e09e | 14154 | if (modrm.mod != 3) |
4d9567e0 MM |
14155 | { |
14156 | if (intel_syntax && bytemode == v_mode) | |
14157 | { | |
14158 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
14159 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14160 | } | |
14161 | OP_E (bytemode, sizeflag); | |
14162 | return; | |
14163 | } | |
246c51aa | 14164 | |
4d9567e0 MM |
14165 | /* Skip mod/rm byte. */ |
14166 | MODRM_CHECK; | |
14167 | codep++; | |
14168 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 14169 | oappend (names_mm[modrm.rm]); |
4d9567e0 MM |
14170 | } |
14171 | ||
14172 | static void | |
14173 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
14174 | { | |
14175 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 14176 | oappend (names_mm[modrm.reg]); |
4d9567e0 MM |
14177 | } |
14178 | ||
c608c12e | 14179 | static void |
26ca5450 | 14180 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 14181 | { |
b9733481 L |
14182 | int reg; |
14183 | const char **names; | |
d6f574e0 L |
14184 | |
14185 | /* Skip mod/rm byte. */ | |
14186 | MODRM_CHECK; | |
14187 | codep++; | |
14188 | ||
7967e09e | 14189 | if (modrm.mod != 3) |
c608c12e | 14190 | { |
c1e679ec | 14191 | OP_E_memory (bytemode, sizeflag); |
c608c12e AM |
14192 | return; |
14193 | } | |
d6f574e0 | 14194 | |
b9733481 | 14195 | reg = modrm.rm; |
161a04f6 L |
14196 | USED_REX (REX_B); |
14197 | if (rex & REX_B) | |
b9733481 | 14198 | reg += 8; |
c608c12e | 14199 | |
b6169b20 | 14200 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 L |
14201 | && (bytemode == x_swap_mode |
14202 | || bytemode == d_swap_mode | |
7bb15c6f | 14203 | || bytemode == d_scalar_swap_mode |
539f890d L |
14204 | || bytemode == q_swap_mode |
14205 | || bytemode == q_scalar_swap_mode)) | |
b6169b20 L |
14206 | swap_operand (); |
14207 | ||
c0f3af97 L |
14208 | if (need_vex |
14209 | && bytemode != xmm_mode | |
6c30d220 L |
14210 | && bytemode != xmmdw_mode |
14211 | && bytemode != xmmqd_mode | |
14212 | && bytemode != xmm_mb_mode | |
14213 | && bytemode != xmm_mw_mode | |
14214 | && bytemode != xmm_md_mode | |
14215 | && bytemode != xmm_mq_mode | |
539f890d L |
14216 | && bytemode != xmmq_mode |
14217 | && bytemode != d_scalar_mode | |
7bb15c6f | 14218 | && bytemode != d_scalar_swap_mode |
539f890d | 14219 | && bytemode != q_scalar_mode |
1c480963 L |
14220 | && bytemode != q_scalar_swap_mode |
14221 | && bytemode != vex_scalar_w_dq_mode) | |
c0f3af97 L |
14222 | { |
14223 | switch (vex.length) | |
14224 | { | |
14225 | case 128: | |
b9733481 | 14226 | names = names_xmm; |
c0f3af97 L |
14227 | break; |
14228 | case 256: | |
b9733481 | 14229 | names = names_ymm; |
c0f3af97 L |
14230 | break; |
14231 | default: | |
14232 | abort (); | |
14233 | } | |
14234 | } | |
14235 | else | |
b9733481 L |
14236 | names = names_xmm; |
14237 | oappend (names[reg]); | |
c608c12e AM |
14238 | } |
14239 | ||
252b5132 | 14240 | static void |
26ca5450 | 14241 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 14242 | { |
7967e09e | 14243 | if (modrm.mod == 3) |
2da11e11 AM |
14244 | OP_EM (bytemode, sizeflag); |
14245 | else | |
6608db57 | 14246 | BadOp (); |
252b5132 RH |
14247 | } |
14248 | ||
992aaec9 | 14249 | static void |
26ca5450 | 14250 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 14251 | { |
7967e09e | 14252 | if (modrm.mod == 3) |
992aaec9 AM |
14253 | OP_EX (bytemode, sizeflag); |
14254 | else | |
6608db57 | 14255 | BadOp (); |
992aaec9 AM |
14256 | } |
14257 | ||
cc0ec051 AM |
14258 | static void |
14259 | OP_M (int bytemode, int sizeflag) | |
14260 | { | |
7967e09e | 14261 | if (modrm.mod == 3) |
75413a22 L |
14262 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
14263 | BadOp (); | |
cc0ec051 AM |
14264 | else |
14265 | OP_E (bytemode, sizeflag); | |
14266 | } | |
14267 | ||
14268 | static void | |
14269 | OP_0f07 (int bytemode, int sizeflag) | |
14270 | { | |
7967e09e | 14271 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
14272 | BadOp (); |
14273 | else | |
14274 | OP_E (bytemode, sizeflag); | |
14275 | } | |
14276 | ||
46e883c5 | 14277 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 14278 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 14279 | |
cc0ec051 | 14280 | static void |
46e883c5 | 14281 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 14282 | { |
8b38ad71 L |
14283 | if ((prefixes & PREFIX_DATA) != 0 |
14284 | || (rex != 0 | |
14285 | && rex != 0x48 | |
14286 | && address_mode == mode_64bit)) | |
46e883c5 L |
14287 | OP_REG (bytemode, sizeflag); |
14288 | else | |
14289 | strcpy (obuf, "nop"); | |
14290 | } | |
14291 | ||
14292 | static void | |
14293 | NOP_Fixup2 (int bytemode, int sizeflag) | |
14294 | { | |
8b38ad71 L |
14295 | if ((prefixes & PREFIX_DATA) != 0 |
14296 | || (rex != 0 | |
14297 | && rex != 0x48 | |
14298 | && address_mode == mode_64bit)) | |
46e883c5 | 14299 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
14300 | } |
14301 | ||
84037f8c | 14302 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
14303 | /* 00 */ NULL, NULL, NULL, NULL, |
14304 | /* 04 */ NULL, NULL, NULL, NULL, | |
14305 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 14306 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
14307 | /* 10 */ NULL, NULL, NULL, NULL, |
14308 | /* 14 */ NULL, NULL, NULL, NULL, | |
14309 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 14310 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
14311 | /* 20 */ NULL, NULL, NULL, NULL, |
14312 | /* 24 */ NULL, NULL, NULL, NULL, | |
14313 | /* 28 */ NULL, NULL, NULL, NULL, | |
14314 | /* 2C */ NULL, NULL, NULL, NULL, | |
14315 | /* 30 */ NULL, NULL, NULL, NULL, | |
14316 | /* 34 */ NULL, NULL, NULL, NULL, | |
14317 | /* 38 */ NULL, NULL, NULL, NULL, | |
14318 | /* 3C */ NULL, NULL, NULL, NULL, | |
14319 | /* 40 */ NULL, NULL, NULL, NULL, | |
14320 | /* 44 */ NULL, NULL, NULL, NULL, | |
14321 | /* 48 */ NULL, NULL, NULL, NULL, | |
14322 | /* 4C */ NULL, NULL, NULL, NULL, | |
14323 | /* 50 */ NULL, NULL, NULL, NULL, | |
14324 | /* 54 */ NULL, NULL, NULL, NULL, | |
14325 | /* 58 */ NULL, NULL, NULL, NULL, | |
14326 | /* 5C */ NULL, NULL, NULL, NULL, | |
14327 | /* 60 */ NULL, NULL, NULL, NULL, | |
14328 | /* 64 */ NULL, NULL, NULL, NULL, | |
14329 | /* 68 */ NULL, NULL, NULL, NULL, | |
14330 | /* 6C */ NULL, NULL, NULL, NULL, | |
14331 | /* 70 */ NULL, NULL, NULL, NULL, | |
14332 | /* 74 */ NULL, NULL, NULL, NULL, | |
14333 | /* 78 */ NULL, NULL, NULL, NULL, | |
14334 | /* 7C */ NULL, NULL, NULL, NULL, | |
14335 | /* 80 */ NULL, NULL, NULL, NULL, | |
14336 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
14337 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
14338 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
14339 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
14340 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
14341 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
14342 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
14343 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
14344 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
14345 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
14346 | /* AC */ NULL, NULL, "pfacc", NULL, | |
14347 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 14348 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 14349 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
14350 | /* BC */ NULL, NULL, NULL, "pavgusb", |
14351 | /* C0 */ NULL, NULL, NULL, NULL, | |
14352 | /* C4 */ NULL, NULL, NULL, NULL, | |
14353 | /* C8 */ NULL, NULL, NULL, NULL, | |
14354 | /* CC */ NULL, NULL, NULL, NULL, | |
14355 | /* D0 */ NULL, NULL, NULL, NULL, | |
14356 | /* D4 */ NULL, NULL, NULL, NULL, | |
14357 | /* D8 */ NULL, NULL, NULL, NULL, | |
14358 | /* DC */ NULL, NULL, NULL, NULL, | |
14359 | /* E0 */ NULL, NULL, NULL, NULL, | |
14360 | /* E4 */ NULL, NULL, NULL, NULL, | |
14361 | /* E8 */ NULL, NULL, NULL, NULL, | |
14362 | /* EC */ NULL, NULL, NULL, NULL, | |
14363 | /* F0 */ NULL, NULL, NULL, NULL, | |
14364 | /* F4 */ NULL, NULL, NULL, NULL, | |
14365 | /* F8 */ NULL, NULL, NULL, NULL, | |
14366 | /* FC */ NULL, NULL, NULL, NULL, | |
14367 | }; | |
14368 | ||
14369 | static void | |
26ca5450 | 14370 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
14371 | { |
14372 | const char *mnemonic; | |
14373 | ||
14374 | FETCH_DATA (the_info, codep + 1); | |
14375 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
14376 | place where an 8-bit immediate would normally go. ie. the last | |
14377 | byte of the instruction. */ | |
ea397f5b | 14378 | obufp = mnemonicendp; |
c608c12e | 14379 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 14380 | if (mnemonic) |
2da11e11 | 14381 | oappend (mnemonic); |
252b5132 RH |
14382 | else |
14383 | { | |
14384 | /* Since a variable sized modrm/sib chunk is between the start | |
14385 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
14386 | all the modrm processing first, and don't know until now that | |
14387 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
14388 | op_out[0][0] = '\0'; |
14389 | op_out[1][0] = '\0'; | |
6608db57 | 14390 | BadOp (); |
252b5132 | 14391 | } |
ea397f5b | 14392 | mnemonicendp = obufp; |
252b5132 | 14393 | } |
c608c12e | 14394 | |
ea397f5b L |
14395 | static struct op simd_cmp_op[] = |
14396 | { | |
14397 | { STRING_COMMA_LEN ("eq") }, | |
14398 | { STRING_COMMA_LEN ("lt") }, | |
14399 | { STRING_COMMA_LEN ("le") }, | |
14400 | { STRING_COMMA_LEN ("unord") }, | |
14401 | { STRING_COMMA_LEN ("neq") }, | |
14402 | { STRING_COMMA_LEN ("nlt") }, | |
14403 | { STRING_COMMA_LEN ("nle") }, | |
14404 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
14405 | }; |
14406 | ||
14407 | static void | |
ad19981d | 14408 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
14409 | { |
14410 | unsigned int cmp_type; | |
14411 | ||
14412 | FETCH_DATA (the_info, codep + 1); | |
14413 | cmp_type = *codep++ & 0xff; | |
c0f3af97 | 14414 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 14415 | { |
ad19981d | 14416 | char suffix [3]; |
ea397f5b | 14417 | char *p = mnemonicendp - 2; |
ad19981d L |
14418 | suffix[0] = p[0]; |
14419 | suffix[1] = p[1]; | |
14420 | suffix[2] = '\0'; | |
ea397f5b L |
14421 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
14422 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
c608c12e AM |
14423 | } |
14424 | else | |
14425 | { | |
ad19981d L |
14426 | /* We have a reserved extension byte. Output it directly. */ |
14427 | scratchbuf[0] = '$'; | |
14428 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
14429 | oappend (scratchbuf + intel_syntax); | |
14430 | scratchbuf[0] = '\0'; | |
c608c12e AM |
14431 | } |
14432 | } | |
14433 | ||
ca164297 | 14434 | static void |
b844680a L |
14435 | OP_Mwait (int bytemode ATTRIBUTE_UNUSED, |
14436 | int sizeflag ATTRIBUTE_UNUSED) | |
14437 | { | |
14438 | /* mwait %eax,%ecx */ | |
14439 | if (!intel_syntax) | |
14440 | { | |
14441 | const char **names = (address_mode == mode_64bit | |
14442 | ? names64 : names32); | |
14443 | strcpy (op_out[0], names[0]); | |
14444 | strcpy (op_out[1], names[1]); | |
14445 | two_source_ops = 1; | |
14446 | } | |
14447 | /* Skip mod/rm byte. */ | |
14448 | MODRM_CHECK; | |
14449 | codep++; | |
14450 | } | |
14451 | ||
14452 | static void | |
14453 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
14454 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 14455 | { |
b844680a L |
14456 | /* monitor %eax,%ecx,%edx" */ |
14457 | if (!intel_syntax) | |
ca164297 | 14458 | { |
b844680a | 14459 | const char **op1_names; |
cb712a9e L |
14460 | const char **names = (address_mode == mode_64bit |
14461 | ? names64 : names32); | |
1d9f512f | 14462 | |
b844680a L |
14463 | if (!(prefixes & PREFIX_ADDR)) |
14464 | op1_names = (address_mode == mode_16bit | |
14465 | ? names16 : names); | |
ca164297 L |
14466 | else |
14467 | { | |
b844680a | 14468 | /* Remove "addr16/addr32". */ |
f16cd0d5 | 14469 | all_prefixes[last_addr_prefix] = 0; |
b844680a L |
14470 | op1_names = (address_mode != mode_32bit |
14471 | ? names32 : names16); | |
14472 | used_prefixes |= PREFIX_ADDR; | |
ca164297 | 14473 | } |
b844680a L |
14474 | strcpy (op_out[0], op1_names[0]); |
14475 | strcpy (op_out[1], names[1]); | |
14476 | strcpy (op_out[2], names[2]); | |
14477 | two_source_ops = 1; | |
ca164297 | 14478 | } |
b844680a L |
14479 | /* Skip mod/rm byte. */ |
14480 | MODRM_CHECK; | |
14481 | codep++; | |
30123838 JB |
14482 | } |
14483 | ||
6608db57 KH |
14484 | static void |
14485 | BadOp (void) | |
2da11e11 | 14486 | { |
6608db57 KH |
14487 | /* Throw away prefixes and 1st. opcode byte. */ |
14488 | codep = insn_codep + 1; | |
2da11e11 AM |
14489 | oappend ("(bad)"); |
14490 | } | |
4cc91dba | 14491 | |
35c52694 L |
14492 | static void |
14493 | REP_Fixup (int bytemode, int sizeflag) | |
14494 | { | |
14495 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
14496 | lods and stos. */ | |
35c52694 | 14497 | if (prefixes & PREFIX_REPZ) |
f16cd0d5 | 14498 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
35c52694 L |
14499 | |
14500 | switch (bytemode) | |
14501 | { | |
14502 | case al_reg: | |
14503 | case eAX_reg: | |
14504 | case indir_dx_reg: | |
14505 | OP_IMREG (bytemode, sizeflag); | |
14506 | break; | |
14507 | case eDI_reg: | |
14508 | OP_ESreg (bytemode, sizeflag); | |
14509 | break; | |
14510 | case eSI_reg: | |
14511 | OP_DSreg (bytemode, sizeflag); | |
14512 | break; | |
14513 | default: | |
14514 | abort (); | |
14515 | break; | |
14516 | } | |
14517 | } | |
f5804c90 | 14518 | |
42164a71 L |
14519 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
14520 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. | |
14521 | */ | |
14522 | ||
14523 | static void | |
14524 | HLE_Fixup1 (int bytemode, int sizeflag) | |
14525 | { | |
14526 | if (modrm.mod != 3 | |
14527 | && (prefixes & PREFIX_LOCK) != 0) | |
14528 | { | |
14529 | if (prefixes & PREFIX_REPZ) | |
14530 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
14531 | if (prefixes & PREFIX_REPNZ) | |
14532 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
14533 | } | |
14534 | ||
14535 | OP_E (bytemode, sizeflag); | |
14536 | } | |
14537 | ||
14538 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as | |
14539 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. | |
14540 | */ | |
14541 | ||
14542 | static void | |
14543 | HLE_Fixup2 (int bytemode, int sizeflag) | |
14544 | { | |
14545 | if (modrm.mod != 3) | |
14546 | { | |
14547 | if (prefixes & PREFIX_REPZ) | |
14548 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
14549 | if (prefixes & PREFIX_REPNZ) | |
14550 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
14551 | } | |
14552 | ||
14553 | OP_E (bytemode, sizeflag); | |
14554 | } | |
14555 | ||
14556 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as | |
14557 | "xrelease" for memory operand. No check for LOCK prefix. */ | |
14558 | ||
14559 | static void | |
14560 | HLE_Fixup3 (int bytemode, int sizeflag) | |
14561 | { | |
14562 | if (modrm.mod != 3 | |
14563 | && last_repz_prefix > last_repnz_prefix | |
14564 | && (prefixes & PREFIX_REPZ) != 0) | |
14565 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
14566 | ||
14567 | OP_E (bytemode, sizeflag); | |
14568 | } | |
14569 | ||
f5804c90 L |
14570 | static void |
14571 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
14572 | { | |
161a04f6 L |
14573 | USED_REX (REX_W); |
14574 | if (rex & REX_W) | |
f5804c90 L |
14575 | { |
14576 | /* Change cmpxchg8b to cmpxchg16b. */ | |
ea397f5b L |
14577 | char *p = mnemonicendp - 2; |
14578 | mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 14579 | bytemode = o_mode; |
f5804c90 | 14580 | } |
42164a71 L |
14581 | else if ((prefixes & PREFIX_LOCK) != 0) |
14582 | { | |
14583 | if (prefixes & PREFIX_REPZ) | |
14584 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
14585 | if (prefixes & PREFIX_REPNZ) | |
14586 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
14587 | } | |
14588 | ||
f5804c90 L |
14589 | OP_M (bytemode, sizeflag); |
14590 | } | |
42903f7f L |
14591 | |
14592 | static void | |
14593 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
14594 | { | |
b9733481 L |
14595 | const char **names; |
14596 | ||
c0f3af97 L |
14597 | if (need_vex) |
14598 | { | |
14599 | switch (vex.length) | |
14600 | { | |
14601 | case 128: | |
b9733481 | 14602 | names = names_xmm; |
c0f3af97 L |
14603 | break; |
14604 | case 256: | |
b9733481 | 14605 | names = names_ymm; |
c0f3af97 L |
14606 | break; |
14607 | default: | |
14608 | abort (); | |
14609 | } | |
14610 | } | |
14611 | else | |
b9733481 L |
14612 | names = names_xmm; |
14613 | oappend (names[reg]); | |
42903f7f | 14614 | } |
381d071f L |
14615 | |
14616 | static void | |
14617 | CRC32_Fixup (int bytemode, int sizeflag) | |
14618 | { | |
14619 | /* Add proper suffix to "crc32". */ | |
ea397f5b | 14620 | char *p = mnemonicendp; |
381d071f L |
14621 | |
14622 | switch (bytemode) | |
14623 | { | |
14624 | case b_mode: | |
20592a94 | 14625 | if (intel_syntax) |
ea397f5b | 14626 | goto skip; |
20592a94 | 14627 | |
381d071f L |
14628 | *p++ = 'b'; |
14629 | break; | |
14630 | case v_mode: | |
20592a94 | 14631 | if (intel_syntax) |
ea397f5b | 14632 | goto skip; |
20592a94 | 14633 | |
381d071f L |
14634 | USED_REX (REX_W); |
14635 | if (rex & REX_W) | |
14636 | *p++ = 'q'; | |
7bb15c6f | 14637 | else |
f16cd0d5 L |
14638 | { |
14639 | if (sizeflag & DFLAG) | |
14640 | *p++ = 'l'; | |
14641 | else | |
14642 | *p++ = 'w'; | |
14643 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14644 | } | |
381d071f L |
14645 | break; |
14646 | default: | |
14647 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14648 | break; | |
14649 | } | |
ea397f5b | 14650 | mnemonicendp = p; |
381d071f L |
14651 | *p = '\0'; |
14652 | ||
ea397f5b | 14653 | skip: |
381d071f L |
14654 | if (modrm.mod == 3) |
14655 | { | |
14656 | int add; | |
14657 | ||
14658 | /* Skip mod/rm byte. */ | |
14659 | MODRM_CHECK; | |
14660 | codep++; | |
14661 | ||
14662 | USED_REX (REX_B); | |
14663 | add = (rex & REX_B) ? 8 : 0; | |
14664 | if (bytemode == b_mode) | |
14665 | { | |
14666 | USED_REX (0); | |
14667 | if (rex) | |
14668 | oappend (names8rex[modrm.rm + add]); | |
14669 | else | |
14670 | oappend (names8[modrm.rm + add]); | |
14671 | } | |
14672 | else | |
14673 | { | |
14674 | USED_REX (REX_W); | |
14675 | if (rex & REX_W) | |
14676 | oappend (names64[modrm.rm + add]); | |
14677 | else if ((prefixes & PREFIX_DATA)) | |
14678 | oappend (names16[modrm.rm + add]); | |
14679 | else | |
14680 | oappend (names32[modrm.rm + add]); | |
14681 | } | |
14682 | } | |
14683 | else | |
9344ff29 | 14684 | OP_E (bytemode, sizeflag); |
381d071f | 14685 | } |
85f10a01 | 14686 | |
eacc9c89 L |
14687 | static void |
14688 | FXSAVE_Fixup (int bytemode, int sizeflag) | |
14689 | { | |
14690 | /* Add proper suffix to "fxsave" and "fxrstor". */ | |
14691 | USED_REX (REX_W); | |
14692 | if (rex & REX_W) | |
14693 | { | |
14694 | char *p = mnemonicendp; | |
14695 | *p++ = '6'; | |
14696 | *p++ = '4'; | |
14697 | *p = '\0'; | |
14698 | mnemonicendp = p; | |
14699 | } | |
14700 | OP_M (bytemode, sizeflag); | |
14701 | } | |
14702 | ||
c0f3af97 L |
14703 | /* Display the destination register operand for instructions with |
14704 | VEX. */ | |
14705 | ||
14706 | static void | |
14707 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
14708 | { | |
539f890d | 14709 | int reg; |
b9733481 L |
14710 | const char **names; |
14711 | ||
c0f3af97 L |
14712 | if (!need_vex) |
14713 | abort (); | |
14714 | ||
14715 | if (!need_vex_reg) | |
14716 | return; | |
14717 | ||
539f890d L |
14718 | reg = vex.register_specifier; |
14719 | if (bytemode == vex_scalar_mode) | |
14720 | { | |
14721 | oappend (names_xmm[reg]); | |
14722 | return; | |
14723 | } | |
14724 | ||
c0f3af97 L |
14725 | switch (vex.length) |
14726 | { | |
14727 | case 128: | |
14728 | switch (bytemode) | |
14729 | { | |
14730 | case vex_mode: | |
14731 | case vex128_mode: | |
6c30d220 | 14732 | case vex_vsib_q_w_dq_mode: |
cb21baef L |
14733 | names = names_xmm; |
14734 | break; | |
14735 | case dq_mode: | |
14736 | if (vex.w) | |
14737 | names = names64; | |
14738 | else | |
14739 | names = names32; | |
c0f3af97 L |
14740 | break; |
14741 | default: | |
14742 | abort (); | |
14743 | return; | |
14744 | } | |
c0f3af97 L |
14745 | break; |
14746 | case 256: | |
14747 | switch (bytemode) | |
14748 | { | |
14749 | case vex_mode: | |
14750 | case vex256_mode: | |
6c30d220 L |
14751 | names = names_ymm; |
14752 | break; | |
14753 | case vex_vsib_q_w_dq_mode: | |
14754 | names = vex.w ? names_ymm : names_xmm; | |
c0f3af97 L |
14755 | break; |
14756 | default: | |
14757 | abort (); | |
14758 | return; | |
14759 | } | |
c0f3af97 L |
14760 | break; |
14761 | default: | |
14762 | abort (); | |
14763 | break; | |
14764 | } | |
539f890d | 14765 | oappend (names[reg]); |
c0f3af97 L |
14766 | } |
14767 | ||
922d8de8 DR |
14768 | /* Get the VEX immediate byte without moving codep. */ |
14769 | ||
14770 | static unsigned char | |
ccc5981b | 14771 | get_vex_imm8 (int sizeflag, int opnum) |
922d8de8 DR |
14772 | { |
14773 | int bytes_before_imm = 0; | |
14774 | ||
922d8de8 DR |
14775 | if (modrm.mod != 3) |
14776 | { | |
14777 | /* There are SIB/displacement bytes. */ | |
14778 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) | |
02e647f9 | 14779 | { |
922d8de8 | 14780 | /* 32/64 bit address mode */ |
02e647f9 | 14781 | int base = modrm.rm; |
922d8de8 DR |
14782 | |
14783 | /* Check SIB byte. */ | |
02e647f9 SP |
14784 | if (base == 4) |
14785 | { | |
14786 | FETCH_DATA (the_info, codep + 1); | |
14787 | base = *codep & 7; | |
14788 | /* When decoding the third source, don't increase | |
14789 | bytes_before_imm as this has already been incremented | |
14790 | by one in OP_E_memory while decoding the second | |
14791 | source operand. */ | |
ccc5981b SP |
14792 | if (opnum == 0) |
14793 | bytes_before_imm++; | |
02e647f9 SP |
14794 | } |
14795 | ||
14796 | /* Don't increase bytes_before_imm when decoding the third source, | |
14797 | it has already been incremented by OP_E_memory while decoding | |
14798 | the second source operand. */ | |
14799 | if (opnum == 0) | |
14800 | { | |
14801 | switch (modrm.mod) | |
14802 | { | |
14803 | case 0: | |
14804 | /* When modrm.rm == 5 or modrm.rm == 4 and base in | |
14805 | SIB == 5, there is a 4 byte displacement. */ | |
14806 | if (base != 5) | |
14807 | /* No displacement. */ | |
14808 | break; | |
14809 | case 2: | |
14810 | /* 4 byte displacement. */ | |
14811 | bytes_before_imm += 4; | |
14812 | break; | |
14813 | case 1: | |
14814 | /* 1 byte displacement. */ | |
14815 | bytes_before_imm++; | |
14816 | break; | |
14817 | } | |
14818 | } | |
14819 | } | |
922d8de8 | 14820 | else |
02e647f9 SP |
14821 | { |
14822 | /* 16 bit address mode */ | |
14823 | /* Don't increase bytes_before_imm when decoding the third source, | |
14824 | it has already been incremented by OP_E_memory while decoding | |
14825 | the second source operand. */ | |
14826 | if (opnum == 0) | |
14827 | { | |
14828 | switch (modrm.mod) | |
14829 | { | |
14830 | case 0: | |
14831 | /* When modrm.rm == 6, there is a 2 byte displacement. */ | |
14832 | if (modrm.rm != 6) | |
14833 | /* No displacement. */ | |
14834 | break; | |
14835 | case 2: | |
14836 | /* 2 byte displacement. */ | |
14837 | bytes_before_imm += 2; | |
14838 | break; | |
14839 | case 1: | |
14840 | /* 1 byte displacement: when decoding the third source, | |
14841 | don't increase bytes_before_imm as this has already | |
14842 | been incremented by one in OP_E_memory while decoding | |
14843 | the second source operand. */ | |
14844 | if (opnum == 0) | |
14845 | bytes_before_imm++; | |
ccc5981b | 14846 | |
02e647f9 SP |
14847 | break; |
14848 | } | |
922d8de8 DR |
14849 | } |
14850 | } | |
14851 | } | |
14852 | ||
14853 | FETCH_DATA (the_info, codep + bytes_before_imm + 1); | |
14854 | return codep [bytes_before_imm]; | |
14855 | } | |
14856 | ||
14857 | static void | |
14858 | OP_EX_VexReg (int bytemode, int sizeflag, int reg) | |
14859 | { | |
b9733481 L |
14860 | const char **names; |
14861 | ||
922d8de8 DR |
14862 | if (reg == -1 && modrm.mod != 3) |
14863 | { | |
14864 | OP_E_memory (bytemode, sizeflag); | |
14865 | return; | |
14866 | } | |
14867 | else | |
14868 | { | |
14869 | if (reg == -1) | |
14870 | { | |
14871 | reg = modrm.rm; | |
14872 | USED_REX (REX_B); | |
14873 | if (rex & REX_B) | |
14874 | reg += 8; | |
14875 | } | |
14876 | else if (reg > 7 && address_mode != mode_64bit) | |
14877 | BadOp (); | |
14878 | } | |
14879 | ||
14880 | switch (vex.length) | |
14881 | { | |
14882 | case 128: | |
b9733481 | 14883 | names = names_xmm; |
922d8de8 DR |
14884 | break; |
14885 | case 256: | |
b9733481 | 14886 | names = names_ymm; |
922d8de8 DR |
14887 | break; |
14888 | default: | |
14889 | abort (); | |
14890 | } | |
b9733481 | 14891 | oappend (names[reg]); |
922d8de8 DR |
14892 | } |
14893 | ||
a683cc34 SP |
14894 | static void |
14895 | OP_EX_VexImmW (int bytemode, int sizeflag) | |
14896 | { | |
14897 | int reg = -1; | |
14898 | static unsigned char vex_imm8; | |
14899 | ||
14900 | if (vex_w_done == 0) | |
14901 | { | |
14902 | vex_w_done = 1; | |
14903 | ||
14904 | /* Skip mod/rm byte. */ | |
14905 | MODRM_CHECK; | |
14906 | codep++; | |
14907 | ||
14908 | vex_imm8 = get_vex_imm8 (sizeflag, 0); | |
14909 | ||
14910 | if (vex.w) | |
14911 | reg = vex_imm8 >> 4; | |
14912 | ||
14913 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
14914 | } | |
14915 | else if (vex_w_done == 1) | |
14916 | { | |
14917 | vex_w_done = 2; | |
14918 | ||
14919 | if (!vex.w) | |
14920 | reg = vex_imm8 >> 4; | |
14921 | ||
14922 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
14923 | } | |
14924 | else | |
14925 | { | |
14926 | /* Output the imm8 directly. */ | |
14927 | scratchbuf[0] = '$'; | |
14928 | print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf); | |
14929 | oappend (scratchbuf + intel_syntax); | |
14930 | scratchbuf[0] = '\0'; | |
14931 | codep++; | |
14932 | } | |
14933 | } | |
14934 | ||
5dd85c99 SP |
14935 | static void |
14936 | OP_Vex_2src (int bytemode, int sizeflag) | |
14937 | { | |
14938 | if (modrm.mod == 3) | |
14939 | { | |
b9733481 | 14940 | int reg = modrm.rm; |
5dd85c99 | 14941 | USED_REX (REX_B); |
b9733481 L |
14942 | if (rex & REX_B) |
14943 | reg += 8; | |
14944 | oappend (names_xmm[reg]); | |
5dd85c99 SP |
14945 | } |
14946 | else | |
14947 | { | |
14948 | if (intel_syntax | |
14949 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
14950 | { | |
14951 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
14952 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14953 | } | |
14954 | OP_E (bytemode, sizeflag); | |
14955 | } | |
14956 | } | |
14957 | ||
14958 | static void | |
14959 | OP_Vex_2src_1 (int bytemode, int sizeflag) | |
14960 | { | |
14961 | if (modrm.mod == 3) | |
14962 | { | |
14963 | /* Skip mod/rm byte. */ | |
14964 | MODRM_CHECK; | |
14965 | codep++; | |
14966 | } | |
14967 | ||
14968 | if (vex.w) | |
b9733481 | 14969 | oappend (names_xmm[vex.register_specifier]); |
5dd85c99 SP |
14970 | else |
14971 | OP_Vex_2src (bytemode, sizeflag); | |
14972 | } | |
14973 | ||
14974 | static void | |
14975 | OP_Vex_2src_2 (int bytemode, int sizeflag) | |
14976 | { | |
14977 | if (vex.w) | |
14978 | OP_Vex_2src (bytemode, sizeflag); | |
14979 | else | |
b9733481 | 14980 | oappend (names_xmm[vex.register_specifier]); |
5dd85c99 SP |
14981 | } |
14982 | ||
922d8de8 DR |
14983 | static void |
14984 | OP_EX_VexW (int bytemode, int sizeflag) | |
14985 | { | |
14986 | int reg = -1; | |
14987 | ||
14988 | if (!vex_w_done) | |
14989 | { | |
14990 | vex_w_done = 1; | |
41effecb SP |
14991 | |
14992 | /* Skip mod/rm byte. */ | |
14993 | MODRM_CHECK; | |
14994 | codep++; | |
14995 | ||
922d8de8 | 14996 | if (vex.w) |
ccc5981b | 14997 | reg = get_vex_imm8 (sizeflag, 0) >> 4; |
922d8de8 DR |
14998 | } |
14999 | else | |
15000 | { | |
15001 | if (!vex.w) | |
ccc5981b | 15002 | reg = get_vex_imm8 (sizeflag, 1) >> 4; |
922d8de8 DR |
15003 | } |
15004 | ||
15005 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
15006 | } | |
15007 | ||
922d8de8 DR |
15008 | static void |
15009 | VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
15010 | int sizeflag ATTRIBUTE_UNUSED) | |
15011 | { | |
15012 | /* Skip the immediate byte and check for invalid bits. */ | |
15013 | FETCH_DATA (the_info, codep + 1); | |
15014 | if (*codep++ & 0xf) | |
15015 | BadOp (); | |
15016 | } | |
15017 | ||
c0f3af97 L |
15018 | static void |
15019 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
15020 | { | |
15021 | int reg; | |
b9733481 L |
15022 | const char **names; |
15023 | ||
c0f3af97 L |
15024 | FETCH_DATA (the_info, codep + 1); |
15025 | reg = *codep++; | |
15026 | ||
15027 | if (bytemode != x_mode) | |
15028 | abort (); | |
15029 | ||
15030 | if (reg & 0xf) | |
15031 | BadOp (); | |
15032 | ||
15033 | reg >>= 4; | |
dae39acc L |
15034 | if (reg > 7 && address_mode != mode_64bit) |
15035 | BadOp (); | |
15036 | ||
c0f3af97 L |
15037 | switch (vex.length) |
15038 | { | |
15039 | case 128: | |
b9733481 | 15040 | names = names_xmm; |
c0f3af97 L |
15041 | break; |
15042 | case 256: | |
b9733481 | 15043 | names = names_ymm; |
c0f3af97 L |
15044 | break; |
15045 | default: | |
15046 | abort (); | |
15047 | } | |
b9733481 | 15048 | oappend (names[reg]); |
c0f3af97 L |
15049 | } |
15050 | ||
922d8de8 DR |
15051 | static void |
15052 | OP_XMM_VexW (int bytemode, int sizeflag) | |
15053 | { | |
15054 | /* Turn off the REX.W bit since it is used for swapping operands | |
15055 | now. */ | |
15056 | rex &= ~REX_W; | |
15057 | OP_XMM (bytemode, sizeflag); | |
15058 | } | |
15059 | ||
c0f3af97 L |
15060 | static void |
15061 | OP_EX_Vex (int bytemode, int sizeflag) | |
15062 | { | |
15063 | if (modrm.mod != 3) | |
15064 | { | |
15065 | if (vex.register_specifier != 0) | |
15066 | BadOp (); | |
15067 | need_vex_reg = 0; | |
15068 | } | |
15069 | OP_EX (bytemode, sizeflag); | |
15070 | } | |
15071 | ||
15072 | static void | |
15073 | OP_XMM_Vex (int bytemode, int sizeflag) | |
15074 | { | |
15075 | if (modrm.mod != 3) | |
15076 | { | |
15077 | if (vex.register_specifier != 0) | |
15078 | BadOp (); | |
15079 | need_vex_reg = 0; | |
15080 | } | |
15081 | OP_XMM (bytemode, sizeflag); | |
15082 | } | |
15083 | ||
15084 | static void | |
15085 | VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15086 | { | |
15087 | switch (vex.length) | |
15088 | { | |
15089 | case 128: | |
ea397f5b | 15090 | mnemonicendp = stpcpy (obuf, "vzeroupper"); |
c0f3af97 L |
15091 | break; |
15092 | case 256: | |
ea397f5b | 15093 | mnemonicendp = stpcpy (obuf, "vzeroall"); |
c0f3af97 L |
15094 | break; |
15095 | default: | |
15096 | abort (); | |
15097 | } | |
15098 | } | |
15099 | ||
ea397f5b L |
15100 | static struct op vex_cmp_op[] = |
15101 | { | |
15102 | { STRING_COMMA_LEN ("eq") }, | |
15103 | { STRING_COMMA_LEN ("lt") }, | |
15104 | { STRING_COMMA_LEN ("le") }, | |
15105 | { STRING_COMMA_LEN ("unord") }, | |
15106 | { STRING_COMMA_LEN ("neq") }, | |
15107 | { STRING_COMMA_LEN ("nlt") }, | |
15108 | { STRING_COMMA_LEN ("nle") }, | |
15109 | { STRING_COMMA_LEN ("ord") }, | |
15110 | { STRING_COMMA_LEN ("eq_uq") }, | |
15111 | { STRING_COMMA_LEN ("nge") }, | |
15112 | { STRING_COMMA_LEN ("ngt") }, | |
15113 | { STRING_COMMA_LEN ("false") }, | |
15114 | { STRING_COMMA_LEN ("neq_oq") }, | |
15115 | { STRING_COMMA_LEN ("ge") }, | |
15116 | { STRING_COMMA_LEN ("gt") }, | |
15117 | { STRING_COMMA_LEN ("true") }, | |
15118 | { STRING_COMMA_LEN ("eq_os") }, | |
15119 | { STRING_COMMA_LEN ("lt_oq") }, | |
15120 | { STRING_COMMA_LEN ("le_oq") }, | |
15121 | { STRING_COMMA_LEN ("unord_s") }, | |
15122 | { STRING_COMMA_LEN ("neq_us") }, | |
15123 | { STRING_COMMA_LEN ("nlt_uq") }, | |
15124 | { STRING_COMMA_LEN ("nle_uq") }, | |
15125 | { STRING_COMMA_LEN ("ord_s") }, | |
15126 | { STRING_COMMA_LEN ("eq_us") }, | |
15127 | { STRING_COMMA_LEN ("nge_uq") }, | |
15128 | { STRING_COMMA_LEN ("ngt_uq") }, | |
15129 | { STRING_COMMA_LEN ("false_os") }, | |
15130 | { STRING_COMMA_LEN ("neq_os") }, | |
15131 | { STRING_COMMA_LEN ("ge_oq") }, | |
15132 | { STRING_COMMA_LEN ("gt_oq") }, | |
15133 | { STRING_COMMA_LEN ("true_us") }, | |
c0f3af97 L |
15134 | }; |
15135 | ||
15136 | static void | |
15137 | VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15138 | { | |
15139 | unsigned int cmp_type; | |
15140 | ||
15141 | FETCH_DATA (the_info, codep + 1); | |
15142 | cmp_type = *codep++ & 0xff; | |
15143 | if (cmp_type < ARRAY_SIZE (vex_cmp_op)) | |
15144 | { | |
15145 | char suffix [3]; | |
ea397f5b | 15146 | char *p = mnemonicendp - 2; |
c0f3af97 L |
15147 | suffix[0] = p[0]; |
15148 | suffix[1] = p[1]; | |
15149 | suffix[2] = '\0'; | |
ea397f5b L |
15150 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); |
15151 | mnemonicendp += vex_cmp_op[cmp_type].len; | |
c0f3af97 L |
15152 | } |
15153 | else | |
15154 | { | |
15155 | /* We have a reserved extension byte. Output it directly. */ | |
15156 | scratchbuf[0] = '$'; | |
15157 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
15158 | oappend (scratchbuf + intel_syntax); | |
15159 | scratchbuf[0] = '\0'; | |
15160 | } | |
15161 | } | |
15162 | ||
ea397f5b L |
15163 | static const struct op pclmul_op[] = |
15164 | { | |
15165 | { STRING_COMMA_LEN ("lql") }, | |
15166 | { STRING_COMMA_LEN ("hql") }, | |
15167 | { STRING_COMMA_LEN ("lqh") }, | |
15168 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
15169 | }; |
15170 | ||
15171 | static void | |
15172 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
15173 | int sizeflag ATTRIBUTE_UNUSED) | |
15174 | { | |
15175 | unsigned int pclmul_type; | |
15176 | ||
15177 | FETCH_DATA (the_info, codep + 1); | |
15178 | pclmul_type = *codep++ & 0xff; | |
15179 | switch (pclmul_type) | |
15180 | { | |
15181 | case 0x10: | |
15182 | pclmul_type = 2; | |
15183 | break; | |
15184 | case 0x11: | |
15185 | pclmul_type = 3; | |
15186 | break; | |
15187 | default: | |
15188 | break; | |
7bb15c6f | 15189 | } |
c0f3af97 L |
15190 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
15191 | { | |
15192 | char suffix [4]; | |
ea397f5b | 15193 | char *p = mnemonicendp - 3; |
c0f3af97 L |
15194 | suffix[0] = p[0]; |
15195 | suffix[1] = p[1]; | |
15196 | suffix[2] = p[2]; | |
15197 | suffix[3] = '\0'; | |
ea397f5b L |
15198 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
15199 | mnemonicendp += pclmul_op[pclmul_type].len; | |
c0f3af97 L |
15200 | } |
15201 | else | |
15202 | { | |
15203 | /* We have a reserved extension byte. Output it directly. */ | |
15204 | scratchbuf[0] = '$'; | |
15205 | print_operand_value (scratchbuf + 1, 1, pclmul_type); | |
15206 | oappend (scratchbuf + intel_syntax); | |
15207 | scratchbuf[0] = '\0'; | |
15208 | } | |
15209 | } | |
15210 | ||
f1f8f695 L |
15211 | static void |
15212 | MOVBE_Fixup (int bytemode, int sizeflag) | |
15213 | { | |
15214 | /* Add proper suffix to "movbe". */ | |
ea397f5b | 15215 | char *p = mnemonicendp; |
f1f8f695 L |
15216 | |
15217 | switch (bytemode) | |
15218 | { | |
15219 | case v_mode: | |
15220 | if (intel_syntax) | |
ea397f5b | 15221 | goto skip; |
f1f8f695 L |
15222 | |
15223 | USED_REX (REX_W); | |
15224 | if (sizeflag & SUFFIX_ALWAYS) | |
15225 | { | |
15226 | if (rex & REX_W) | |
15227 | *p++ = 'q'; | |
f1f8f695 | 15228 | else |
f16cd0d5 L |
15229 | { |
15230 | if (sizeflag & DFLAG) | |
15231 | *p++ = 'l'; | |
15232 | else | |
15233 | *p++ = 'w'; | |
15234 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15235 | } | |
f1f8f695 | 15236 | } |
f1f8f695 L |
15237 | break; |
15238 | default: | |
15239 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15240 | break; | |
15241 | } | |
ea397f5b | 15242 | mnemonicendp = p; |
f1f8f695 L |
15243 | *p = '\0'; |
15244 | ||
ea397f5b | 15245 | skip: |
f1f8f695 L |
15246 | OP_M (bytemode, sizeflag); |
15247 | } | |
f88c9eb0 SP |
15248 | |
15249 | static void | |
15250 | OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15251 | { | |
15252 | int reg; | |
15253 | const char **names; | |
15254 | ||
15255 | /* Skip mod/rm byte. */ | |
15256 | MODRM_CHECK; | |
15257 | codep++; | |
15258 | ||
15259 | if (vex.w) | |
15260 | names = names64; | |
f88c9eb0 | 15261 | else |
ce7d077e | 15262 | names = names32; |
f88c9eb0 SP |
15263 | |
15264 | reg = modrm.rm; | |
15265 | USED_REX (REX_B); | |
15266 | if (rex & REX_B) | |
15267 | reg += 8; | |
15268 | ||
15269 | oappend (names[reg]); | |
15270 | } | |
15271 | ||
15272 | static void | |
15273 | OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15274 | { | |
15275 | const char **names; | |
15276 | ||
15277 | if (vex.w) | |
15278 | names = names64; | |
f88c9eb0 | 15279 | else |
ce7d077e | 15280 | names = names32; |
f88c9eb0 SP |
15281 | |
15282 | oappend (names[vex.register_specifier]); | |
15283 | } |