Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
060d22b0 | 2 | Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
9ce09ba2 | 3 | 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013 |
0af1713e | 4 | Free Software Foundation, Inc. |
252b5132 | 5 | |
9b201bb5 | 6 | This file is part of the GNU opcodes library. |
20f0a1fc | 7 | |
9b201bb5 | 8 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 9 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
10 | the Free Software Foundation; either version 3, or (at your option) |
11 | any later version. | |
20f0a1fc | 12 | |
9b201bb5 NC |
13 | It is distributed in the hope that it will be useful, but WITHOUT |
14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | License for more details. | |
20f0a1fc NC |
17 | |
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
20 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
21 | MA 02110-1301, USA. */ | |
22 | ||
20f0a1fc NC |
23 | |
24 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
25 | July 1988 | |
26 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
27 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
28 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
29 | ||
30 | /* The main tables describing the instructions is essentially a copy | |
31 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
32 | Programmers Manual. Usually, there is a capital letter, followed | |
33 | by a small letter. The capital letter tell the addressing mode, | |
34 | and the small letter tells about the operand size. Refer to | |
35 | the Intel manual for details. */ | |
252b5132 | 36 | |
252b5132 | 37 | #include "sysdep.h" |
dabbade6 | 38 | #include "dis-asm.h" |
252b5132 | 39 | #include "opintl.h" |
0b1cf022 | 40 | #include "opcode/i386.h" |
85f10a01 | 41 | #include "libiberty.h" |
252b5132 RH |
42 | |
43 | #include <setjmp.h> | |
44 | ||
26ca5450 AJ |
45 | static int print_insn (bfd_vma, disassemble_info *); |
46 | static void dofloat (int); | |
47 | static void OP_ST (int, int); | |
48 | static void OP_STi (int, int); | |
49 | static int putop (const char *, int); | |
50 | static void oappend (const char *); | |
51 | static void append_seg (void); | |
52 | static void OP_indirE (int, int); | |
53 | static void print_operand_value (char *, int, bfd_vma); | |
c0f3af97 | 54 | static void OP_E_register (int, int); |
c1e679ec | 55 | static void OP_E_memory (int, int); |
5d669648 | 56 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
57 | static void OP_E (int, int); |
58 | static void OP_G (int, int); | |
59 | static bfd_vma get64 (void); | |
60 | static bfd_signed_vma get32 (void); | |
61 | static bfd_signed_vma get32s (void); | |
62 | static int get16 (void); | |
63 | static void set_op (bfd_vma, int); | |
b844680a | 64 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
65 | static void OP_REG (int, int); |
66 | static void OP_IMREG (int, int); | |
67 | static void OP_I (int, int); | |
68 | static void OP_I64 (int, int); | |
69 | static void OP_sI (int, int); | |
70 | static void OP_J (int, int); | |
71 | static void OP_SEG (int, int); | |
72 | static void OP_DIR (int, int); | |
73 | static void OP_OFF (int, int); | |
74 | static void OP_OFF64 (int, int); | |
75 | static void ptr_reg (int, int); | |
76 | static void OP_ESreg (int, int); | |
77 | static void OP_DSreg (int, int); | |
78 | static void OP_C (int, int); | |
79 | static void OP_D (int, int); | |
80 | static void OP_T (int, int); | |
6f74c397 | 81 | static void OP_R (int, int); |
26ca5450 AJ |
82 | static void OP_MMX (int, int); |
83 | static void OP_XMM (int, int); | |
84 | static void OP_EM (int, int); | |
85 | static void OP_EX (int, int); | |
4d9567e0 MM |
86 | static void OP_EMC (int,int); |
87 | static void OP_MXC (int,int); | |
26ca5450 AJ |
88 | static void OP_MS (int, int); |
89 | static void OP_XS (int, int); | |
cc0ec051 | 90 | static void OP_M (int, int); |
c0f3af97 L |
91 | static void OP_VEX (int, int); |
92 | static void OP_EX_Vex (int, int); | |
922d8de8 | 93 | static void OP_EX_VexW (int, int); |
a683cc34 | 94 | static void OP_EX_VexImmW (int, int); |
c0f3af97 | 95 | static void OP_XMM_Vex (int, int); |
922d8de8 | 96 | static void OP_XMM_VexW (int, int); |
43234a1e | 97 | static void OP_Rounding (int, int); |
c0f3af97 L |
98 | static void OP_REG_VexI4 (int, int); |
99 | static void PCLMUL_Fixup (int, int); | |
922d8de8 | 100 | static void VEXI4_Fixup (int, int); |
c0f3af97 L |
101 | static void VZERO_Fixup (int, int); |
102 | static void VCMP_Fixup (int, int); | |
43234a1e | 103 | static void VPCMP_Fixup (int, int); |
cc0ec051 | 104 | static void OP_0f07 (int, int); |
b844680a L |
105 | static void OP_Monitor (int, int); |
106 | static void OP_Mwait (int, int); | |
46e883c5 L |
107 | static void NOP_Fixup1 (int, int); |
108 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 109 | static void OP_3DNowSuffix (int, int); |
ad19981d | 110 | static void CMP_Fixup (int, int); |
26ca5450 | 111 | static void BadOp (void); |
35c52694 | 112 | static void REP_Fixup (int, int); |
7e8b059b | 113 | static void BND_Fixup (int, int); |
42164a71 L |
114 | static void HLE_Fixup1 (int, int); |
115 | static void HLE_Fixup2 (int, int); | |
116 | static void HLE_Fixup3 (int, int); | |
f5804c90 | 117 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 118 | static void XMM_Fixup (int, int); |
381d071f | 119 | static void CRC32_Fixup (int, int); |
eacc9c89 | 120 | static void FXSAVE_Fixup (int, int); |
f88c9eb0 SP |
121 | static void OP_LWPCB_E (int, int); |
122 | static void OP_LWP_E (int, int); | |
5dd85c99 SP |
123 | static void OP_Vex_2src_1 (int, int); |
124 | static void OP_Vex_2src_2 (int, int); | |
c1e679ec | 125 | |
f1f8f695 | 126 | static void MOVBE_Fixup (int, int); |
252b5132 | 127 | |
43234a1e L |
128 | static void OP_Mask (int, int); |
129 | ||
6608db57 | 130 | struct dis_private { |
252b5132 RH |
131 | /* Points to first byte not fetched. */ |
132 | bfd_byte *max_fetched; | |
0b1cf022 | 133 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 134 | bfd_vma insn_start; |
e396998b | 135 | int orig_sizeflag; |
252b5132 RH |
136 | jmp_buf bailout; |
137 | }; | |
138 | ||
cb712a9e L |
139 | enum address_mode |
140 | { | |
141 | mode_16bit, | |
142 | mode_32bit, | |
143 | mode_64bit | |
144 | }; | |
145 | ||
146 | enum address_mode address_mode; | |
52b15da3 | 147 | |
5076851f ILT |
148 | /* Flags for the prefixes for the current instruction. See below. */ |
149 | static int prefixes; | |
150 | ||
52b15da3 JH |
151 | /* REX prefix the current instruction. See below. */ |
152 | static int rex; | |
153 | /* Bits of REX we've already used. */ | |
154 | static int rex_used; | |
d869730d | 155 | /* REX bits in original REX prefix ignored. */ |
c0f3af97 | 156 | static int rex_ignored; |
52b15da3 JH |
157 | /* Mark parts used in the REX prefix. When we are testing for |
158 | empty prefix (for 8bit register REX extension), just mask it | |
159 | out. Otherwise test for REX bit is excuse for existence of REX | |
160 | only in case value is nonzero. */ | |
161 | #define USED_REX(value) \ | |
162 | { \ | |
163 | if (value) \ | |
161a04f6 L |
164 | { \ |
165 | if ((rex & value)) \ | |
166 | rex_used |= (value) | REX_OPCODE; \ | |
167 | } \ | |
52b15da3 | 168 | else \ |
161a04f6 | 169 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
170 | } |
171 | ||
7d421014 ILT |
172 | /* Flags for prefixes which we somehow handled when printing the |
173 | current instruction. */ | |
174 | static int used_prefixes; | |
175 | ||
5076851f ILT |
176 | /* Flags stored in PREFIXES. */ |
177 | #define PREFIX_REPZ 1 | |
178 | #define PREFIX_REPNZ 2 | |
179 | #define PREFIX_LOCK 4 | |
180 | #define PREFIX_CS 8 | |
181 | #define PREFIX_SS 0x10 | |
182 | #define PREFIX_DS 0x20 | |
183 | #define PREFIX_ES 0x40 | |
184 | #define PREFIX_FS 0x80 | |
185 | #define PREFIX_GS 0x100 | |
186 | #define PREFIX_DATA 0x200 | |
187 | #define PREFIX_ADDR 0x400 | |
188 | #define PREFIX_FWAIT 0x800 | |
189 | ||
252b5132 RH |
190 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
191 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
192 | on error. */ | |
193 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 194 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
195 | ? 1 : fetch_data ((info), (addr))) |
196 | ||
197 | static int | |
26ca5450 | 198 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
199 | { |
200 | int status; | |
6608db57 | 201 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
202 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
203 | ||
0b1cf022 | 204 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
205 | status = (*info->read_memory_func) (start, |
206 | priv->max_fetched, | |
207 | addr - priv->max_fetched, | |
208 | info); | |
209 | else | |
210 | status = -1; | |
252b5132 RH |
211 | if (status != 0) |
212 | { | |
7d421014 | 213 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
214 | print_insn_i386 will do something sensible. Otherwise, print |
215 | an error. We do that here because this is where we know | |
216 | STATUS. */ | |
7d421014 | 217 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 218 | (*info->memory_error_func) (status, start, info); |
252b5132 RH |
219 | longjmp (priv->bailout, 1); |
220 | } | |
221 | else | |
222 | priv->max_fetched = addr; | |
223 | return 1; | |
224 | } | |
225 | ||
ce518a5f | 226 | #define XX { NULL, 0 } |
592d1631 | 227 | #define Bad_Opcode NULL, { { NULL, 0 } } |
ce518a5f L |
228 | |
229 | #define Eb { OP_E, b_mode } | |
7e8b059b | 230 | #define Ebnd { OP_E, bnd_mode } |
b6169b20 | 231 | #define EbS { OP_E, b_swap_mode } |
ce518a5f | 232 | #define Ev { OP_E, v_mode } |
7e8b059b | 233 | #define Ev_bnd { OP_E, v_bnd_mode } |
b6169b20 | 234 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
235 | #define Ed { OP_E, d_mode } |
236 | #define Edq { OP_E, dq_mode } | |
237 | #define Edqw { OP_E, dqw_mode } | |
42903f7f L |
238 | #define Edqb { OP_E, dqb_mode } |
239 | #define Edqd { OP_E, dqd_mode } | |
09335d05 | 240 | #define Eq { OP_E, q_mode } |
ce518a5f L |
241 | #define indirEv { OP_indirE, stack_v_mode } |
242 | #define indirEp { OP_indirE, f_mode } | |
243 | #define stackEv { OP_E, stack_v_mode } | |
244 | #define Em { OP_E, m_mode } | |
245 | #define Ew { OP_E, w_mode } | |
246 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 247 | #define Ma { OP_M, a_mode } |
b844680a | 248 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 249 | #define Md { OP_M, d_mode } |
f1f8f695 | 250 | #define Mo { OP_M, o_mode } |
ce518a5f L |
251 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
252 | #define Mq { OP_M, q_mode } | |
4ee52178 | 253 | #define Mx { OP_M, x_mode } |
c0f3af97 | 254 | #define Mxmm { OP_M, xmm_mode } |
ce518a5f | 255 | #define Gb { OP_G, b_mode } |
7e8b059b | 256 | #define Gbnd { OP_G, bnd_mode } |
ce518a5f L |
257 | #define Gv { OP_G, v_mode } |
258 | #define Gd { OP_G, d_mode } | |
259 | #define Gdq { OP_G, dq_mode } | |
260 | #define Gm { OP_G, m_mode } | |
261 | #define Gw { OP_G, w_mode } | |
6f74c397 | 262 | #define Rd { OP_R, d_mode } |
43234a1e | 263 | #define Rdq { OP_R, dq_mode } |
6f74c397 | 264 | #define Rm { OP_R, m_mode } |
ce518a5f L |
265 | #define Ib { OP_I, b_mode } |
266 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
e3949f17 | 267 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
ce518a5f | 268 | #define Iv { OP_I, v_mode } |
7bb15c6f | 269 | #define sIv { OP_sI, v_mode } |
ce518a5f L |
270 | #define Iq { OP_I, q_mode } |
271 | #define Iv64 { OP_I64, v_mode } | |
272 | #define Iw { OP_I, w_mode } | |
273 | #define I1 { OP_I, const_1_mode } | |
274 | #define Jb { OP_J, b_mode } | |
275 | #define Jv { OP_J, v_mode } | |
276 | #define Cm { OP_C, m_mode } | |
277 | #define Dm { OP_D, m_mode } | |
278 | #define Td { OP_T, d_mode } | |
b844680a | 279 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
280 | |
281 | #define RMeAX { OP_REG, eAX_reg } | |
282 | #define RMeBX { OP_REG, eBX_reg } | |
283 | #define RMeCX { OP_REG, eCX_reg } | |
284 | #define RMeDX { OP_REG, eDX_reg } | |
285 | #define RMeSP { OP_REG, eSP_reg } | |
286 | #define RMeBP { OP_REG, eBP_reg } | |
287 | #define RMeSI { OP_REG, eSI_reg } | |
288 | #define RMeDI { OP_REG, eDI_reg } | |
289 | #define RMrAX { OP_REG, rAX_reg } | |
290 | #define RMrBX { OP_REG, rBX_reg } | |
291 | #define RMrCX { OP_REG, rCX_reg } | |
292 | #define RMrDX { OP_REG, rDX_reg } | |
293 | #define RMrSP { OP_REG, rSP_reg } | |
294 | #define RMrBP { OP_REG, rBP_reg } | |
295 | #define RMrSI { OP_REG, rSI_reg } | |
296 | #define RMrDI { OP_REG, rDI_reg } | |
297 | #define RMAL { OP_REG, al_reg } | |
ce518a5f L |
298 | #define RMCL { OP_REG, cl_reg } |
299 | #define RMDL { OP_REG, dl_reg } | |
300 | #define RMBL { OP_REG, bl_reg } | |
301 | #define RMAH { OP_REG, ah_reg } | |
302 | #define RMCH { OP_REG, ch_reg } | |
303 | #define RMDH { OP_REG, dh_reg } | |
304 | #define RMBH { OP_REG, bh_reg } | |
305 | #define RMAX { OP_REG, ax_reg } | |
306 | #define RMDX { OP_REG, dx_reg } | |
307 | ||
308 | #define eAX { OP_IMREG, eAX_reg } | |
309 | #define eBX { OP_IMREG, eBX_reg } | |
310 | #define eCX { OP_IMREG, eCX_reg } | |
311 | #define eDX { OP_IMREG, eDX_reg } | |
312 | #define eSP { OP_IMREG, eSP_reg } | |
313 | #define eBP { OP_IMREG, eBP_reg } | |
314 | #define eSI { OP_IMREG, eSI_reg } | |
315 | #define eDI { OP_IMREG, eDI_reg } | |
316 | #define AL { OP_IMREG, al_reg } | |
317 | #define CL { OP_IMREG, cl_reg } | |
318 | #define DL { OP_IMREG, dl_reg } | |
319 | #define BL { OP_IMREG, bl_reg } | |
320 | #define AH { OP_IMREG, ah_reg } | |
321 | #define CH { OP_IMREG, ch_reg } | |
322 | #define DH { OP_IMREG, dh_reg } | |
323 | #define BH { OP_IMREG, bh_reg } | |
324 | #define AX { OP_IMREG, ax_reg } | |
325 | #define DX { OP_IMREG, dx_reg } | |
326 | #define zAX { OP_IMREG, z_mode_ax_reg } | |
327 | #define indirDX { OP_IMREG, indir_dx_reg } | |
328 | ||
329 | #define Sw { OP_SEG, w_mode } | |
330 | #define Sv { OP_SEG, v_mode } | |
331 | #define Ap { OP_DIR, 0 } | |
332 | #define Ob { OP_OFF64, b_mode } | |
333 | #define Ov { OP_OFF64, v_mode } | |
334 | #define Xb { OP_DSreg, eSI_reg } | |
335 | #define Xv { OP_DSreg, eSI_reg } | |
336 | #define Xz { OP_DSreg, eSI_reg } | |
337 | #define Yb { OP_ESreg, eDI_reg } | |
338 | #define Yv { OP_ESreg, eDI_reg } | |
339 | #define DSBX { OP_DSreg, eBX_reg } | |
340 | ||
341 | #define es { OP_REG, es_reg } | |
342 | #define ss { OP_REG, ss_reg } | |
343 | #define cs { OP_REG, cs_reg } | |
344 | #define ds { OP_REG, ds_reg } | |
345 | #define fs { OP_REG, fs_reg } | |
346 | #define gs { OP_REG, gs_reg } | |
347 | ||
348 | #define MX { OP_MMX, 0 } | |
349 | #define XM { OP_XMM, 0 } | |
539f890d | 350 | #define XMScalar { OP_XMM, scalar_mode } |
6c30d220 | 351 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
c0f3af97 | 352 | #define XMM { OP_XMM, xmm_mode } |
43234a1e | 353 | #define XMxmmq { OP_XMM, xmmq_mode } |
ce518a5f | 354 | #define EM { OP_EM, v_mode } |
b6169b20 | 355 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 356 | #define EMd { OP_EM, d_mode } |
14051056 | 357 | #define EMx { OP_EM, x_mode } |
8976381e | 358 | #define EXw { OP_EX, w_mode } |
09a2c6cf | 359 | #define EXd { OP_EX, d_mode } |
539f890d | 360 | #define EXdScalar { OP_EX, d_scalar_mode } |
fa99fab2 | 361 | #define EXdS { OP_EX, d_swap_mode } |
43234a1e | 362 | #define EXdScalarS { OP_EX, d_scalar_swap_mode } |
09a2c6cf | 363 | #define EXq { OP_EX, q_mode } |
539f890d L |
364 | #define EXqScalar { OP_EX, q_scalar_mode } |
365 | #define EXqScalarS { OP_EX, q_scalar_swap_mode } | |
b6169b20 | 366 | #define EXqS { OP_EX, q_swap_mode } |
09a2c6cf | 367 | #define EXx { OP_EX, x_mode } |
b6169b20 | 368 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 | 369 | #define EXxmm { OP_EX, xmm_mode } |
43234a1e | 370 | #define EXymm { OP_EX, ymm_mode } |
c0f3af97 | 371 | #define EXxmmq { OP_EX, xmmq_mode } |
43234a1e | 372 | #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } |
6c30d220 L |
373 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
374 | #define EXxmm_mw { OP_EX, xmm_mw_mode } | |
375 | #define EXxmm_md { OP_EX, xmm_md_mode } | |
376 | #define EXxmm_mq { OP_EX, xmm_mq_mode } | |
43234a1e | 377 | #define EXxmm_mdq { OP_EX, xmm_mdq_mode } |
6c30d220 L |
378 | #define EXxmmdw { OP_EX, xmmdw_mode } |
379 | #define EXxmmqd { OP_EX, xmmqd_mode } | |
c0f3af97 | 380 | #define EXymmq { OP_EX, ymmq_mode } |
0bfee649 | 381 | #define EXVexWdq { OP_EX, vex_w_dq_mode } |
1c480963 | 382 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
43234a1e L |
383 | #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } |
384 | #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } | |
ce518a5f L |
385 | #define MS { OP_MS, v_mode } |
386 | #define XS { OP_XS, v_mode } | |
09335d05 | 387 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 388 | #define MXC { OP_MXC, 0 } |
ce518a5f | 389 | #define OPSUF { OP_3DNowSuffix, 0 } |
ad19981d | 390 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 391 | #define XMM0 { XMM_Fixup, 0 } |
eacc9c89 | 392 | #define FXSAVE { FXSAVE_Fixup, 0 } |
5dd85c99 SP |
393 | #define Vex_2src_1 { OP_Vex_2src_1, 0 } |
394 | #define Vex_2src_2 { OP_Vex_2src_2, 0 } | |
252b5132 | 395 | |
c0f3af97 | 396 | #define Vex { OP_VEX, vex_mode } |
539f890d | 397 | #define VexScalar { OP_VEX, vex_scalar_mode } |
6c30d220 | 398 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
c0f3af97 L |
399 | #define Vex128 { OP_VEX, vex128_mode } |
400 | #define Vex256 { OP_VEX, vex256_mode } | |
cb21baef | 401 | #define VexGdq { OP_VEX, dq_mode } |
922d8de8 | 402 | #define VexI4 { VEXI4_Fixup, 0} |
c0f3af97 | 403 | #define EXdVex { OP_EX_Vex, d_mode } |
fa99fab2 | 404 | #define EXdVexS { OP_EX_Vex, d_swap_mode } |
539f890d | 405 | #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } |
c0f3af97 | 406 | #define EXqVex { OP_EX_Vex, q_mode } |
fa99fab2 | 407 | #define EXqVexS { OP_EX_Vex, q_swap_mode } |
539f890d | 408 | #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } |
922d8de8 DR |
409 | #define EXVexW { OP_EX_VexW, x_mode } |
410 | #define EXdVexW { OP_EX_VexW, d_mode } | |
411 | #define EXqVexW { OP_EX_VexW, q_mode } | |
a683cc34 | 412 | #define EXVexImmW { OP_EX_VexImmW, x_mode } |
c0f3af97 | 413 | #define XMVex { OP_XMM_Vex, 0 } |
539f890d | 414 | #define XMVexScalar { OP_XMM_Vex, scalar_mode } |
922d8de8 | 415 | #define XMVexW { OP_XMM_VexW, 0 } |
c0f3af97 L |
416 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
417 | #define PCLMUL { PCLMUL_Fixup, 0 } | |
418 | #define VZERO { VZERO_Fixup, 0 } | |
419 | #define VCMP { VCMP_Fixup, 0 } | |
43234a1e L |
420 | #define VPCMP { VPCMP_Fixup, 0 } |
421 | ||
422 | #define EXxEVexR { OP_Rounding, evex_rounding_mode } | |
423 | #define EXxEVexS { OP_Rounding, evex_sae_mode } | |
424 | ||
425 | #define XMask { OP_Mask, mask_mode } | |
426 | #define MaskG { OP_G, mask_mode } | |
427 | #define MaskE { OP_E, mask_mode } | |
428 | #define MaskR { OP_R, mask_mode } | |
429 | #define MaskVex { OP_VEX, mask_mode } | |
c0f3af97 | 430 | |
6c30d220 L |
431 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
432 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } | |
433 | ||
35c52694 | 434 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
435 | #define Xbr { REP_Fixup, eSI_reg } |
436 | #define Xvr { REP_Fixup, eSI_reg } | |
437 | #define Ybr { REP_Fixup, eDI_reg } | |
438 | #define Yvr { REP_Fixup, eDI_reg } | |
439 | #define Yzr { REP_Fixup, eDI_reg } | |
440 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
441 | #define ALr { REP_Fixup, al_reg } | |
442 | #define eAXr { REP_Fixup, eAX_reg } | |
443 | ||
42164a71 L |
444 | /* Used handle HLE prefix for lockable instructions. */ |
445 | #define Ebh1 { HLE_Fixup1, b_mode } | |
446 | #define Evh1 { HLE_Fixup1, v_mode } | |
447 | #define Ebh2 { HLE_Fixup2, b_mode } | |
448 | #define Evh2 { HLE_Fixup2, v_mode } | |
449 | #define Ebh3 { HLE_Fixup3, b_mode } | |
450 | #define Evh3 { HLE_Fixup3, v_mode } | |
451 | ||
7e8b059b L |
452 | #define BND { BND_Fixup, 0 } |
453 | ||
ce518a5f L |
454 | #define cond_jump_flag { NULL, cond_jump_mode } |
455 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 456 | |
252b5132 | 457 | /* bits in sizeflag */ |
252b5132 | 458 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
459 | #define AFLAG 2 |
460 | #define DFLAG 1 | |
461 | ||
51e7da1b L |
462 | enum |
463 | { | |
464 | /* byte operand */ | |
465 | b_mode = 1, | |
466 | /* byte operand with operand swapped */ | |
3873ba12 | 467 | b_swap_mode, |
e3949f17 L |
468 | /* byte operand, sign extend like 'T' suffix */ |
469 | b_T_mode, | |
51e7da1b | 470 | /* operand size depends on prefixes */ |
3873ba12 | 471 | v_mode, |
51e7da1b | 472 | /* operand size depends on prefixes with operand swapped */ |
3873ba12 | 473 | v_swap_mode, |
51e7da1b | 474 | /* word operand */ |
3873ba12 | 475 | w_mode, |
51e7da1b | 476 | /* double word operand */ |
3873ba12 | 477 | d_mode, |
51e7da1b | 478 | /* double word operand with operand swapped */ |
3873ba12 | 479 | d_swap_mode, |
51e7da1b | 480 | /* quad word operand */ |
3873ba12 | 481 | q_mode, |
51e7da1b | 482 | /* quad word operand with operand swapped */ |
3873ba12 | 483 | q_swap_mode, |
51e7da1b | 484 | /* ten-byte operand */ |
3873ba12 | 485 | t_mode, |
43234a1e L |
486 | /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
487 | broadcast enabled. */ | |
3873ba12 | 488 | x_mode, |
43234a1e L |
489 | /* Similar to x_mode, but with different EVEX mem shifts. */ |
490 | evex_x_gscat_mode, | |
491 | /* Similar to x_mode, but with disabled broadcast. */ | |
492 | evex_x_nobcst_mode, | |
493 | /* Similar to x_mode, but with operands swapped and disabled broadcast | |
494 | in EVEX. */ | |
3873ba12 | 495 | x_swap_mode, |
51e7da1b | 496 | /* 16-byte XMM operand */ |
3873ba12 | 497 | xmm_mode, |
43234a1e L |
498 | /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
499 | memory operand (depending on vector length). Broadcast isn't | |
500 | allowed. */ | |
3873ba12 | 501 | xmmq_mode, |
43234a1e L |
502 | /* Same as xmmq_mode, but broadcast is allowed. */ |
503 | evex_half_bcst_xmmq_mode, | |
6c30d220 L |
504 | /* XMM register or byte memory operand */ |
505 | xmm_mb_mode, | |
506 | /* XMM register or word memory operand */ | |
507 | xmm_mw_mode, | |
508 | /* XMM register or double word memory operand */ | |
509 | xmm_md_mode, | |
510 | /* XMM register or quad word memory operand */ | |
511 | xmm_mq_mode, | |
43234a1e L |
512 | /* XMM register or double/quad word memory operand, depending on |
513 | VEX.W. */ | |
514 | xmm_mdq_mode, | |
515 | /* 16-byte XMM, word, double word or quad word operand. */ | |
6c30d220 | 516 | xmmdw_mode, |
43234a1e | 517 | /* 16-byte XMM, double word, quad word operand or xmm word operand. */ |
6c30d220 | 518 | xmmqd_mode, |
43234a1e L |
519 | /* 32-byte YMM operand */ |
520 | ymm_mode, | |
521 | /* quad word, ymmword or zmmword memory operand. */ | |
3873ba12 | 522 | ymmq_mode, |
6c30d220 L |
523 | /* 32-byte YMM or 16-byte word operand */ |
524 | ymmxmm_mode, | |
51e7da1b | 525 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
3873ba12 | 526 | m_mode, |
51e7da1b | 527 | /* pair of v_mode operands */ |
3873ba12 L |
528 | a_mode, |
529 | cond_jump_mode, | |
530 | loop_jcxz_mode, | |
7e8b059b | 531 | v_bnd_mode, |
51e7da1b | 532 | /* operand size depends on REX prefixes. */ |
3873ba12 | 533 | dq_mode, |
51e7da1b | 534 | /* registers like dq_mode, memory like w_mode. */ |
3873ba12 | 535 | dqw_mode, |
7e8b059b | 536 | bnd_mode, |
51e7da1b | 537 | /* 4- or 6-byte pointer operand */ |
3873ba12 L |
538 | f_mode, |
539 | const_1_mode, | |
51e7da1b | 540 | /* v_mode for stack-related opcodes. */ |
3873ba12 | 541 | stack_v_mode, |
51e7da1b | 542 | /* non-quad operand size depends on prefixes */ |
3873ba12 | 543 | z_mode, |
51e7da1b | 544 | /* 16-byte operand */ |
3873ba12 | 545 | o_mode, |
51e7da1b | 546 | /* registers like dq_mode, memory like b_mode. */ |
3873ba12 | 547 | dqb_mode, |
51e7da1b | 548 | /* registers like dq_mode, memory like d_mode. */ |
3873ba12 | 549 | dqd_mode, |
51e7da1b | 550 | /* normal vex mode */ |
3873ba12 | 551 | vex_mode, |
51e7da1b | 552 | /* 128bit vex mode */ |
3873ba12 | 553 | vex128_mode, |
51e7da1b | 554 | /* 256bit vex mode */ |
3873ba12 | 555 | vex256_mode, |
51e7da1b | 556 | /* operand size depends on the VEX.W bit. */ |
3873ba12 | 557 | vex_w_dq_mode, |
d55ee72f | 558 | |
6c30d220 L |
559 | /* Similar to vex_w_dq_mode, with VSIB dword indices. */ |
560 | vex_vsib_d_w_dq_mode, | |
561 | /* Similar to vex_w_dq_mode, with VSIB qword indices. */ | |
562 | vex_vsib_q_w_dq_mode, | |
563 | ||
539f890d L |
564 | /* scalar, ignore vector length. */ |
565 | scalar_mode, | |
566 | /* like d_mode, ignore vector length. */ | |
567 | d_scalar_mode, | |
568 | /* like d_swap_mode, ignore vector length. */ | |
569 | d_scalar_swap_mode, | |
570 | /* like q_mode, ignore vector length. */ | |
571 | q_scalar_mode, | |
572 | /* like q_swap_mode, ignore vector length. */ | |
573 | q_scalar_swap_mode, | |
574 | /* like vex_mode, ignore vector length. */ | |
575 | vex_scalar_mode, | |
1c480963 L |
576 | /* like vex_w_dq_mode, ignore vector length. */ |
577 | vex_scalar_w_dq_mode, | |
539f890d | 578 | |
43234a1e L |
579 | /* Static rounding. */ |
580 | evex_rounding_mode, | |
581 | /* Supress all exceptions. */ | |
582 | evex_sae_mode, | |
583 | ||
584 | /* Mask register operand. */ | |
585 | mask_mode, | |
586 | ||
3873ba12 L |
587 | es_reg, |
588 | cs_reg, | |
589 | ss_reg, | |
590 | ds_reg, | |
591 | fs_reg, | |
592 | gs_reg, | |
d55ee72f | 593 | |
3873ba12 L |
594 | eAX_reg, |
595 | eCX_reg, | |
596 | eDX_reg, | |
597 | eBX_reg, | |
598 | eSP_reg, | |
599 | eBP_reg, | |
600 | eSI_reg, | |
601 | eDI_reg, | |
d55ee72f | 602 | |
3873ba12 L |
603 | al_reg, |
604 | cl_reg, | |
605 | dl_reg, | |
606 | bl_reg, | |
607 | ah_reg, | |
608 | ch_reg, | |
609 | dh_reg, | |
610 | bh_reg, | |
d55ee72f | 611 | |
3873ba12 L |
612 | ax_reg, |
613 | cx_reg, | |
614 | dx_reg, | |
615 | bx_reg, | |
616 | sp_reg, | |
617 | bp_reg, | |
618 | si_reg, | |
619 | di_reg, | |
d55ee72f | 620 | |
3873ba12 L |
621 | rAX_reg, |
622 | rCX_reg, | |
623 | rDX_reg, | |
624 | rBX_reg, | |
625 | rSP_reg, | |
626 | rBP_reg, | |
627 | rSI_reg, | |
628 | rDI_reg, | |
d55ee72f | 629 | |
3873ba12 L |
630 | z_mode_ax_reg, |
631 | indir_dx_reg | |
51e7da1b | 632 | }; |
252b5132 | 633 | |
51e7da1b L |
634 | enum |
635 | { | |
636 | FLOATCODE = 1, | |
3873ba12 L |
637 | USE_REG_TABLE, |
638 | USE_MOD_TABLE, | |
639 | USE_RM_TABLE, | |
640 | USE_PREFIX_TABLE, | |
641 | USE_X86_64_TABLE, | |
642 | USE_3BYTE_TABLE, | |
f88c9eb0 | 643 | USE_XOP_8F_TABLE, |
3873ba12 L |
644 | USE_VEX_C4_TABLE, |
645 | USE_VEX_C5_TABLE, | |
9e30b8e0 | 646 | USE_VEX_LEN_TABLE, |
43234a1e L |
647 | USE_VEX_W_TABLE, |
648 | USE_EVEX_TABLE | |
51e7da1b | 649 | }; |
6439fc28 | 650 | |
1ceb70f8 | 651 | #define FLOAT NULL, { { NULL, FLOATCODE } } |
4efba78c | 652 | |
4e7d34a6 | 653 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } } |
1ceb70f8 L |
654 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
655 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
656 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
657 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
658 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
659 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
f88c9eb0 | 660 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
c0f3af97 L |
661 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
662 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) | |
663 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) | |
9e30b8e0 | 664 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
43234a1e | 665 | #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) |
1ceb70f8 | 666 | |
51e7da1b L |
667 | enum |
668 | { | |
669 | REG_80 = 0, | |
3873ba12 L |
670 | REG_81, |
671 | REG_82, | |
672 | REG_8F, | |
673 | REG_C0, | |
674 | REG_C1, | |
675 | REG_C6, | |
676 | REG_C7, | |
677 | REG_D0, | |
678 | REG_D1, | |
679 | REG_D2, | |
680 | REG_D3, | |
681 | REG_F6, | |
682 | REG_F7, | |
683 | REG_FE, | |
684 | REG_FF, | |
685 | REG_0F00, | |
686 | REG_0F01, | |
687 | REG_0F0D, | |
688 | REG_0F18, | |
689 | REG_0F71, | |
690 | REG_0F72, | |
691 | REG_0F73, | |
692 | REG_0FA6, | |
693 | REG_0FA7, | |
694 | REG_0FAE, | |
695 | REG_0FBA, | |
696 | REG_0FC7, | |
592a252b L |
697 | REG_VEX_0F71, |
698 | REG_VEX_0F72, | |
699 | REG_VEX_0F73, | |
700 | REG_VEX_0FAE, | |
f12dc422 | 701 | REG_VEX_0F38F3, |
f88c9eb0 | 702 | REG_XOP_LWPCB, |
2a2a0f38 QN |
703 | REG_XOP_LWP, |
704 | REG_XOP_TBM_01, | |
43234a1e L |
705 | REG_XOP_TBM_02, |
706 | ||
707 | REG_EVEX_0F72, | |
708 | REG_EVEX_0F73, | |
709 | REG_EVEX_0F38C6, | |
710 | REG_EVEX_0F38C7 | |
51e7da1b | 711 | }; |
1ceb70f8 | 712 | |
51e7da1b L |
713 | enum |
714 | { | |
715 | MOD_8D = 0, | |
42164a71 L |
716 | MOD_C6_REG_7, |
717 | MOD_C7_REG_7, | |
4a357820 MZ |
718 | MOD_FF_REG_3, |
719 | MOD_FF_REG_5, | |
3873ba12 L |
720 | MOD_0F01_REG_0, |
721 | MOD_0F01_REG_1, | |
722 | MOD_0F01_REG_2, | |
723 | MOD_0F01_REG_3, | |
724 | MOD_0F01_REG_7, | |
725 | MOD_0F12_PREFIX_0, | |
726 | MOD_0F13, | |
727 | MOD_0F16_PREFIX_0, | |
728 | MOD_0F17, | |
729 | MOD_0F18_REG_0, | |
730 | MOD_0F18_REG_1, | |
731 | MOD_0F18_REG_2, | |
732 | MOD_0F18_REG_3, | |
d7189fa5 RM |
733 | MOD_0F18_REG_4, |
734 | MOD_0F18_REG_5, | |
735 | MOD_0F18_REG_6, | |
736 | MOD_0F18_REG_7, | |
7e8b059b L |
737 | MOD_0F1A_PREFIX_0, |
738 | MOD_0F1B_PREFIX_0, | |
739 | MOD_0F1B_PREFIX_1, | |
3873ba12 L |
740 | MOD_0F20, |
741 | MOD_0F21, | |
742 | MOD_0F22, | |
743 | MOD_0F23, | |
744 | MOD_0F24, | |
745 | MOD_0F26, | |
746 | MOD_0F2B_PREFIX_0, | |
747 | MOD_0F2B_PREFIX_1, | |
748 | MOD_0F2B_PREFIX_2, | |
749 | MOD_0F2B_PREFIX_3, | |
750 | MOD_0F51, | |
751 | MOD_0F71_REG_2, | |
752 | MOD_0F71_REG_4, | |
753 | MOD_0F71_REG_6, | |
754 | MOD_0F72_REG_2, | |
755 | MOD_0F72_REG_4, | |
756 | MOD_0F72_REG_6, | |
757 | MOD_0F73_REG_2, | |
758 | MOD_0F73_REG_3, | |
759 | MOD_0F73_REG_6, | |
760 | MOD_0F73_REG_7, | |
761 | MOD_0FAE_REG_0, | |
762 | MOD_0FAE_REG_1, | |
763 | MOD_0FAE_REG_2, | |
764 | MOD_0FAE_REG_3, | |
765 | MOD_0FAE_REG_4, | |
766 | MOD_0FAE_REG_5, | |
767 | MOD_0FAE_REG_6, | |
768 | MOD_0FAE_REG_7, | |
769 | MOD_0FB2, | |
770 | MOD_0FB4, | |
771 | MOD_0FB5, | |
772 | MOD_0FC7_REG_6, | |
773 | MOD_0FC7_REG_7, | |
774 | MOD_0FD7, | |
775 | MOD_0FE7_PREFIX_2, | |
776 | MOD_0FF0_PREFIX_3, | |
777 | MOD_0F382A_PREFIX_2, | |
778 | MOD_62_32BIT, | |
779 | MOD_C4_32BIT, | |
780 | MOD_C5_32BIT, | |
592a252b L |
781 | MOD_VEX_0F12_PREFIX_0, |
782 | MOD_VEX_0F13, | |
783 | MOD_VEX_0F16_PREFIX_0, | |
784 | MOD_VEX_0F17, | |
785 | MOD_VEX_0F2B, | |
786 | MOD_VEX_0F50, | |
787 | MOD_VEX_0F71_REG_2, | |
788 | MOD_VEX_0F71_REG_4, | |
789 | MOD_VEX_0F71_REG_6, | |
790 | MOD_VEX_0F72_REG_2, | |
791 | MOD_VEX_0F72_REG_4, | |
792 | MOD_VEX_0F72_REG_6, | |
793 | MOD_VEX_0F73_REG_2, | |
794 | MOD_VEX_0F73_REG_3, | |
795 | MOD_VEX_0F73_REG_6, | |
796 | MOD_VEX_0F73_REG_7, | |
797 | MOD_VEX_0FAE_REG_2, | |
798 | MOD_VEX_0FAE_REG_3, | |
799 | MOD_VEX_0FD7_PREFIX_2, | |
800 | MOD_VEX_0FE7_PREFIX_2, | |
801 | MOD_VEX_0FF0_PREFIX_3, | |
592a252b L |
802 | MOD_VEX_0F381A_PREFIX_2, |
803 | MOD_VEX_0F382A_PREFIX_2, | |
804 | MOD_VEX_0F382C_PREFIX_2, | |
805 | MOD_VEX_0F382D_PREFIX_2, | |
806 | MOD_VEX_0F382E_PREFIX_2, | |
6c30d220 L |
807 | MOD_VEX_0F382F_PREFIX_2, |
808 | MOD_VEX_0F385A_PREFIX_2, | |
809 | MOD_VEX_0F388C_PREFIX_2, | |
810 | MOD_VEX_0F388E_PREFIX_2, | |
43234a1e L |
811 | |
812 | MOD_EVEX_0F10_PREFIX_1, | |
813 | MOD_EVEX_0F10_PREFIX_3, | |
814 | MOD_EVEX_0F11_PREFIX_1, | |
815 | MOD_EVEX_0F11_PREFIX_3, | |
816 | MOD_EVEX_0F12_PREFIX_0, | |
817 | MOD_EVEX_0F16_PREFIX_0, | |
818 | MOD_EVEX_0F38C6_REG_1, | |
819 | MOD_EVEX_0F38C6_REG_2, | |
820 | MOD_EVEX_0F38C6_REG_5, | |
821 | MOD_EVEX_0F38C6_REG_6, | |
822 | MOD_EVEX_0F38C7_REG_1, | |
823 | MOD_EVEX_0F38C7_REG_2, | |
824 | MOD_EVEX_0F38C7_REG_5, | |
825 | MOD_EVEX_0F38C7_REG_6 | |
51e7da1b | 826 | }; |
1ceb70f8 | 827 | |
51e7da1b L |
828 | enum |
829 | { | |
42164a71 L |
830 | RM_C6_REG_7 = 0, |
831 | RM_C7_REG_7, | |
832 | RM_0F01_REG_0, | |
3873ba12 L |
833 | RM_0F01_REG_1, |
834 | RM_0F01_REG_2, | |
835 | RM_0F01_REG_3, | |
836 | RM_0F01_REG_7, | |
837 | RM_0FAE_REG_5, | |
838 | RM_0FAE_REG_6, | |
839 | RM_0FAE_REG_7 | |
51e7da1b | 840 | }; |
1ceb70f8 | 841 | |
51e7da1b L |
842 | enum |
843 | { | |
844 | PREFIX_90 = 0, | |
3873ba12 L |
845 | PREFIX_0F10, |
846 | PREFIX_0F11, | |
847 | PREFIX_0F12, | |
848 | PREFIX_0F16, | |
7e8b059b L |
849 | PREFIX_0F1A, |
850 | PREFIX_0F1B, | |
3873ba12 L |
851 | PREFIX_0F2A, |
852 | PREFIX_0F2B, | |
853 | PREFIX_0F2C, | |
854 | PREFIX_0F2D, | |
855 | PREFIX_0F2E, | |
856 | PREFIX_0F2F, | |
857 | PREFIX_0F51, | |
858 | PREFIX_0F52, | |
859 | PREFIX_0F53, | |
860 | PREFIX_0F58, | |
861 | PREFIX_0F59, | |
862 | PREFIX_0F5A, | |
863 | PREFIX_0F5B, | |
864 | PREFIX_0F5C, | |
865 | PREFIX_0F5D, | |
866 | PREFIX_0F5E, | |
867 | PREFIX_0F5F, | |
868 | PREFIX_0F60, | |
869 | PREFIX_0F61, | |
870 | PREFIX_0F62, | |
871 | PREFIX_0F6C, | |
872 | PREFIX_0F6D, | |
873 | PREFIX_0F6F, | |
874 | PREFIX_0F70, | |
875 | PREFIX_0F73_REG_3, | |
876 | PREFIX_0F73_REG_7, | |
877 | PREFIX_0F78, | |
878 | PREFIX_0F79, | |
879 | PREFIX_0F7C, | |
880 | PREFIX_0F7D, | |
881 | PREFIX_0F7E, | |
882 | PREFIX_0F7F, | |
c7b8aa3a L |
883 | PREFIX_0FAE_REG_0, |
884 | PREFIX_0FAE_REG_1, | |
885 | PREFIX_0FAE_REG_2, | |
886 | PREFIX_0FAE_REG_3, | |
3873ba12 | 887 | PREFIX_0FB8, |
f12dc422 | 888 | PREFIX_0FBC, |
3873ba12 L |
889 | PREFIX_0FBD, |
890 | PREFIX_0FC2, | |
891 | PREFIX_0FC3, | |
892 | PREFIX_0FC7_REG_6, | |
893 | PREFIX_0FD0, | |
894 | PREFIX_0FD6, | |
895 | PREFIX_0FE6, | |
896 | PREFIX_0FE7, | |
897 | PREFIX_0FF0, | |
898 | PREFIX_0FF7, | |
899 | PREFIX_0F3810, | |
900 | PREFIX_0F3814, | |
901 | PREFIX_0F3815, | |
902 | PREFIX_0F3817, | |
903 | PREFIX_0F3820, | |
904 | PREFIX_0F3821, | |
905 | PREFIX_0F3822, | |
906 | PREFIX_0F3823, | |
907 | PREFIX_0F3824, | |
908 | PREFIX_0F3825, | |
909 | PREFIX_0F3828, | |
910 | PREFIX_0F3829, | |
911 | PREFIX_0F382A, | |
912 | PREFIX_0F382B, | |
913 | PREFIX_0F3830, | |
914 | PREFIX_0F3831, | |
915 | PREFIX_0F3832, | |
916 | PREFIX_0F3833, | |
917 | PREFIX_0F3834, | |
918 | PREFIX_0F3835, | |
919 | PREFIX_0F3837, | |
920 | PREFIX_0F3838, | |
921 | PREFIX_0F3839, | |
922 | PREFIX_0F383A, | |
923 | PREFIX_0F383B, | |
924 | PREFIX_0F383C, | |
925 | PREFIX_0F383D, | |
926 | PREFIX_0F383E, | |
927 | PREFIX_0F383F, | |
928 | PREFIX_0F3840, | |
929 | PREFIX_0F3841, | |
930 | PREFIX_0F3880, | |
931 | PREFIX_0F3881, | |
6c30d220 | 932 | PREFIX_0F3882, |
a0046408 L |
933 | PREFIX_0F38C8, |
934 | PREFIX_0F38C9, | |
935 | PREFIX_0F38CA, | |
936 | PREFIX_0F38CB, | |
937 | PREFIX_0F38CC, | |
938 | PREFIX_0F38CD, | |
3873ba12 L |
939 | PREFIX_0F38DB, |
940 | PREFIX_0F38DC, | |
941 | PREFIX_0F38DD, | |
942 | PREFIX_0F38DE, | |
943 | PREFIX_0F38DF, | |
944 | PREFIX_0F38F0, | |
945 | PREFIX_0F38F1, | |
e2e1fcde | 946 | PREFIX_0F38F6, |
3873ba12 L |
947 | PREFIX_0F3A08, |
948 | PREFIX_0F3A09, | |
949 | PREFIX_0F3A0A, | |
950 | PREFIX_0F3A0B, | |
951 | PREFIX_0F3A0C, | |
952 | PREFIX_0F3A0D, | |
953 | PREFIX_0F3A0E, | |
954 | PREFIX_0F3A14, | |
955 | PREFIX_0F3A15, | |
956 | PREFIX_0F3A16, | |
957 | PREFIX_0F3A17, | |
958 | PREFIX_0F3A20, | |
959 | PREFIX_0F3A21, | |
960 | PREFIX_0F3A22, | |
961 | PREFIX_0F3A40, | |
962 | PREFIX_0F3A41, | |
963 | PREFIX_0F3A42, | |
964 | PREFIX_0F3A44, | |
965 | PREFIX_0F3A60, | |
966 | PREFIX_0F3A61, | |
967 | PREFIX_0F3A62, | |
968 | PREFIX_0F3A63, | |
a0046408 | 969 | PREFIX_0F3ACC, |
3873ba12 | 970 | PREFIX_0F3ADF, |
592a252b L |
971 | PREFIX_VEX_0F10, |
972 | PREFIX_VEX_0F11, | |
973 | PREFIX_VEX_0F12, | |
974 | PREFIX_VEX_0F16, | |
975 | PREFIX_VEX_0F2A, | |
976 | PREFIX_VEX_0F2C, | |
977 | PREFIX_VEX_0F2D, | |
978 | PREFIX_VEX_0F2E, | |
979 | PREFIX_VEX_0F2F, | |
43234a1e L |
980 | PREFIX_VEX_0F41, |
981 | PREFIX_VEX_0F42, | |
982 | PREFIX_VEX_0F44, | |
983 | PREFIX_VEX_0F45, | |
984 | PREFIX_VEX_0F46, | |
985 | PREFIX_VEX_0F47, | |
986 | PREFIX_VEX_0F4B, | |
592a252b L |
987 | PREFIX_VEX_0F51, |
988 | PREFIX_VEX_0F52, | |
989 | PREFIX_VEX_0F53, | |
990 | PREFIX_VEX_0F58, | |
991 | PREFIX_VEX_0F59, | |
992 | PREFIX_VEX_0F5A, | |
993 | PREFIX_VEX_0F5B, | |
994 | PREFIX_VEX_0F5C, | |
995 | PREFIX_VEX_0F5D, | |
996 | PREFIX_VEX_0F5E, | |
997 | PREFIX_VEX_0F5F, | |
998 | PREFIX_VEX_0F60, | |
999 | PREFIX_VEX_0F61, | |
1000 | PREFIX_VEX_0F62, | |
1001 | PREFIX_VEX_0F63, | |
1002 | PREFIX_VEX_0F64, | |
1003 | PREFIX_VEX_0F65, | |
1004 | PREFIX_VEX_0F66, | |
1005 | PREFIX_VEX_0F67, | |
1006 | PREFIX_VEX_0F68, | |
1007 | PREFIX_VEX_0F69, | |
1008 | PREFIX_VEX_0F6A, | |
1009 | PREFIX_VEX_0F6B, | |
1010 | PREFIX_VEX_0F6C, | |
1011 | PREFIX_VEX_0F6D, | |
1012 | PREFIX_VEX_0F6E, | |
1013 | PREFIX_VEX_0F6F, | |
1014 | PREFIX_VEX_0F70, | |
1015 | PREFIX_VEX_0F71_REG_2, | |
1016 | PREFIX_VEX_0F71_REG_4, | |
1017 | PREFIX_VEX_0F71_REG_6, | |
1018 | PREFIX_VEX_0F72_REG_2, | |
1019 | PREFIX_VEX_0F72_REG_4, | |
1020 | PREFIX_VEX_0F72_REG_6, | |
1021 | PREFIX_VEX_0F73_REG_2, | |
1022 | PREFIX_VEX_0F73_REG_3, | |
1023 | PREFIX_VEX_0F73_REG_6, | |
1024 | PREFIX_VEX_0F73_REG_7, | |
1025 | PREFIX_VEX_0F74, | |
1026 | PREFIX_VEX_0F75, | |
1027 | PREFIX_VEX_0F76, | |
1028 | PREFIX_VEX_0F77, | |
1029 | PREFIX_VEX_0F7C, | |
1030 | PREFIX_VEX_0F7D, | |
1031 | PREFIX_VEX_0F7E, | |
1032 | PREFIX_VEX_0F7F, | |
43234a1e L |
1033 | PREFIX_VEX_0F90, |
1034 | PREFIX_VEX_0F91, | |
1035 | PREFIX_VEX_0F92, | |
1036 | PREFIX_VEX_0F93, | |
1037 | PREFIX_VEX_0F98, | |
592a252b L |
1038 | PREFIX_VEX_0FC2, |
1039 | PREFIX_VEX_0FC4, | |
1040 | PREFIX_VEX_0FC5, | |
1041 | PREFIX_VEX_0FD0, | |
1042 | PREFIX_VEX_0FD1, | |
1043 | PREFIX_VEX_0FD2, | |
1044 | PREFIX_VEX_0FD3, | |
1045 | PREFIX_VEX_0FD4, | |
1046 | PREFIX_VEX_0FD5, | |
1047 | PREFIX_VEX_0FD6, | |
1048 | PREFIX_VEX_0FD7, | |
1049 | PREFIX_VEX_0FD8, | |
1050 | PREFIX_VEX_0FD9, | |
1051 | PREFIX_VEX_0FDA, | |
1052 | PREFIX_VEX_0FDB, | |
1053 | PREFIX_VEX_0FDC, | |
1054 | PREFIX_VEX_0FDD, | |
1055 | PREFIX_VEX_0FDE, | |
1056 | PREFIX_VEX_0FDF, | |
1057 | PREFIX_VEX_0FE0, | |
1058 | PREFIX_VEX_0FE1, | |
1059 | PREFIX_VEX_0FE2, | |
1060 | PREFIX_VEX_0FE3, | |
1061 | PREFIX_VEX_0FE4, | |
1062 | PREFIX_VEX_0FE5, | |
1063 | PREFIX_VEX_0FE6, | |
1064 | PREFIX_VEX_0FE7, | |
1065 | PREFIX_VEX_0FE8, | |
1066 | PREFIX_VEX_0FE9, | |
1067 | PREFIX_VEX_0FEA, | |
1068 | PREFIX_VEX_0FEB, | |
1069 | PREFIX_VEX_0FEC, | |
1070 | PREFIX_VEX_0FED, | |
1071 | PREFIX_VEX_0FEE, | |
1072 | PREFIX_VEX_0FEF, | |
1073 | PREFIX_VEX_0FF0, | |
1074 | PREFIX_VEX_0FF1, | |
1075 | PREFIX_VEX_0FF2, | |
1076 | PREFIX_VEX_0FF3, | |
1077 | PREFIX_VEX_0FF4, | |
1078 | PREFIX_VEX_0FF5, | |
1079 | PREFIX_VEX_0FF6, | |
1080 | PREFIX_VEX_0FF7, | |
1081 | PREFIX_VEX_0FF8, | |
1082 | PREFIX_VEX_0FF9, | |
1083 | PREFIX_VEX_0FFA, | |
1084 | PREFIX_VEX_0FFB, | |
1085 | PREFIX_VEX_0FFC, | |
1086 | PREFIX_VEX_0FFD, | |
1087 | PREFIX_VEX_0FFE, | |
1088 | PREFIX_VEX_0F3800, | |
1089 | PREFIX_VEX_0F3801, | |
1090 | PREFIX_VEX_0F3802, | |
1091 | PREFIX_VEX_0F3803, | |
1092 | PREFIX_VEX_0F3804, | |
1093 | PREFIX_VEX_0F3805, | |
1094 | PREFIX_VEX_0F3806, | |
1095 | PREFIX_VEX_0F3807, | |
1096 | PREFIX_VEX_0F3808, | |
1097 | PREFIX_VEX_0F3809, | |
1098 | PREFIX_VEX_0F380A, | |
1099 | PREFIX_VEX_0F380B, | |
1100 | PREFIX_VEX_0F380C, | |
1101 | PREFIX_VEX_0F380D, | |
1102 | PREFIX_VEX_0F380E, | |
1103 | PREFIX_VEX_0F380F, | |
1104 | PREFIX_VEX_0F3813, | |
6c30d220 | 1105 | PREFIX_VEX_0F3816, |
592a252b L |
1106 | PREFIX_VEX_0F3817, |
1107 | PREFIX_VEX_0F3818, | |
1108 | PREFIX_VEX_0F3819, | |
1109 | PREFIX_VEX_0F381A, | |
1110 | PREFIX_VEX_0F381C, | |
1111 | PREFIX_VEX_0F381D, | |
1112 | PREFIX_VEX_0F381E, | |
1113 | PREFIX_VEX_0F3820, | |
1114 | PREFIX_VEX_0F3821, | |
1115 | PREFIX_VEX_0F3822, | |
1116 | PREFIX_VEX_0F3823, | |
1117 | PREFIX_VEX_0F3824, | |
1118 | PREFIX_VEX_0F3825, | |
1119 | PREFIX_VEX_0F3828, | |
1120 | PREFIX_VEX_0F3829, | |
1121 | PREFIX_VEX_0F382A, | |
1122 | PREFIX_VEX_0F382B, | |
1123 | PREFIX_VEX_0F382C, | |
1124 | PREFIX_VEX_0F382D, | |
1125 | PREFIX_VEX_0F382E, | |
1126 | PREFIX_VEX_0F382F, | |
1127 | PREFIX_VEX_0F3830, | |
1128 | PREFIX_VEX_0F3831, | |
1129 | PREFIX_VEX_0F3832, | |
1130 | PREFIX_VEX_0F3833, | |
1131 | PREFIX_VEX_0F3834, | |
1132 | PREFIX_VEX_0F3835, | |
6c30d220 | 1133 | PREFIX_VEX_0F3836, |
592a252b L |
1134 | PREFIX_VEX_0F3837, |
1135 | PREFIX_VEX_0F3838, | |
1136 | PREFIX_VEX_0F3839, | |
1137 | PREFIX_VEX_0F383A, | |
1138 | PREFIX_VEX_0F383B, | |
1139 | PREFIX_VEX_0F383C, | |
1140 | PREFIX_VEX_0F383D, | |
1141 | PREFIX_VEX_0F383E, | |
1142 | PREFIX_VEX_0F383F, | |
1143 | PREFIX_VEX_0F3840, | |
1144 | PREFIX_VEX_0F3841, | |
6c30d220 L |
1145 | PREFIX_VEX_0F3845, |
1146 | PREFIX_VEX_0F3846, | |
1147 | PREFIX_VEX_0F3847, | |
1148 | PREFIX_VEX_0F3858, | |
1149 | PREFIX_VEX_0F3859, | |
1150 | PREFIX_VEX_0F385A, | |
1151 | PREFIX_VEX_0F3878, | |
1152 | PREFIX_VEX_0F3879, | |
1153 | PREFIX_VEX_0F388C, | |
1154 | PREFIX_VEX_0F388E, | |
1155 | PREFIX_VEX_0F3890, | |
1156 | PREFIX_VEX_0F3891, | |
1157 | PREFIX_VEX_0F3892, | |
1158 | PREFIX_VEX_0F3893, | |
592a252b L |
1159 | PREFIX_VEX_0F3896, |
1160 | PREFIX_VEX_0F3897, | |
1161 | PREFIX_VEX_0F3898, | |
1162 | PREFIX_VEX_0F3899, | |
1163 | PREFIX_VEX_0F389A, | |
1164 | PREFIX_VEX_0F389B, | |
1165 | PREFIX_VEX_0F389C, | |
1166 | PREFIX_VEX_0F389D, | |
1167 | PREFIX_VEX_0F389E, | |
1168 | PREFIX_VEX_0F389F, | |
1169 | PREFIX_VEX_0F38A6, | |
1170 | PREFIX_VEX_0F38A7, | |
1171 | PREFIX_VEX_0F38A8, | |
1172 | PREFIX_VEX_0F38A9, | |
1173 | PREFIX_VEX_0F38AA, | |
1174 | PREFIX_VEX_0F38AB, | |
1175 | PREFIX_VEX_0F38AC, | |
1176 | PREFIX_VEX_0F38AD, | |
1177 | PREFIX_VEX_0F38AE, | |
1178 | PREFIX_VEX_0F38AF, | |
1179 | PREFIX_VEX_0F38B6, | |
1180 | PREFIX_VEX_0F38B7, | |
1181 | PREFIX_VEX_0F38B8, | |
1182 | PREFIX_VEX_0F38B9, | |
1183 | PREFIX_VEX_0F38BA, | |
1184 | PREFIX_VEX_0F38BB, | |
1185 | PREFIX_VEX_0F38BC, | |
1186 | PREFIX_VEX_0F38BD, | |
1187 | PREFIX_VEX_0F38BE, | |
1188 | PREFIX_VEX_0F38BF, | |
1189 | PREFIX_VEX_0F38DB, | |
1190 | PREFIX_VEX_0F38DC, | |
1191 | PREFIX_VEX_0F38DD, | |
1192 | PREFIX_VEX_0F38DE, | |
1193 | PREFIX_VEX_0F38DF, | |
f12dc422 L |
1194 | PREFIX_VEX_0F38F2, |
1195 | PREFIX_VEX_0F38F3_REG_1, | |
1196 | PREFIX_VEX_0F38F3_REG_2, | |
1197 | PREFIX_VEX_0F38F3_REG_3, | |
6c30d220 L |
1198 | PREFIX_VEX_0F38F5, |
1199 | PREFIX_VEX_0F38F6, | |
f12dc422 | 1200 | PREFIX_VEX_0F38F7, |
6c30d220 L |
1201 | PREFIX_VEX_0F3A00, |
1202 | PREFIX_VEX_0F3A01, | |
1203 | PREFIX_VEX_0F3A02, | |
592a252b L |
1204 | PREFIX_VEX_0F3A04, |
1205 | PREFIX_VEX_0F3A05, | |
1206 | PREFIX_VEX_0F3A06, | |
1207 | PREFIX_VEX_0F3A08, | |
1208 | PREFIX_VEX_0F3A09, | |
1209 | PREFIX_VEX_0F3A0A, | |
1210 | PREFIX_VEX_0F3A0B, | |
1211 | PREFIX_VEX_0F3A0C, | |
1212 | PREFIX_VEX_0F3A0D, | |
1213 | PREFIX_VEX_0F3A0E, | |
1214 | PREFIX_VEX_0F3A0F, | |
1215 | PREFIX_VEX_0F3A14, | |
1216 | PREFIX_VEX_0F3A15, | |
1217 | PREFIX_VEX_0F3A16, | |
1218 | PREFIX_VEX_0F3A17, | |
1219 | PREFIX_VEX_0F3A18, | |
1220 | PREFIX_VEX_0F3A19, | |
1221 | PREFIX_VEX_0F3A1D, | |
1222 | PREFIX_VEX_0F3A20, | |
1223 | PREFIX_VEX_0F3A21, | |
1224 | PREFIX_VEX_0F3A22, | |
43234a1e L |
1225 | PREFIX_VEX_0F3A30, |
1226 | PREFIX_VEX_0F3A32, | |
6c30d220 L |
1227 | PREFIX_VEX_0F3A38, |
1228 | PREFIX_VEX_0F3A39, | |
592a252b L |
1229 | PREFIX_VEX_0F3A40, |
1230 | PREFIX_VEX_0F3A41, | |
1231 | PREFIX_VEX_0F3A42, | |
1232 | PREFIX_VEX_0F3A44, | |
6c30d220 | 1233 | PREFIX_VEX_0F3A46, |
592a252b L |
1234 | PREFIX_VEX_0F3A48, |
1235 | PREFIX_VEX_0F3A49, | |
1236 | PREFIX_VEX_0F3A4A, | |
1237 | PREFIX_VEX_0F3A4B, | |
1238 | PREFIX_VEX_0F3A4C, | |
1239 | PREFIX_VEX_0F3A5C, | |
1240 | PREFIX_VEX_0F3A5D, | |
1241 | PREFIX_VEX_0F3A5E, | |
1242 | PREFIX_VEX_0F3A5F, | |
1243 | PREFIX_VEX_0F3A60, | |
1244 | PREFIX_VEX_0F3A61, | |
1245 | PREFIX_VEX_0F3A62, | |
1246 | PREFIX_VEX_0F3A63, | |
1247 | PREFIX_VEX_0F3A68, | |
1248 | PREFIX_VEX_0F3A69, | |
1249 | PREFIX_VEX_0F3A6A, | |
1250 | PREFIX_VEX_0F3A6B, | |
1251 | PREFIX_VEX_0F3A6C, | |
1252 | PREFIX_VEX_0F3A6D, | |
1253 | PREFIX_VEX_0F3A6E, | |
1254 | PREFIX_VEX_0F3A6F, | |
1255 | PREFIX_VEX_0F3A78, | |
1256 | PREFIX_VEX_0F3A79, | |
1257 | PREFIX_VEX_0F3A7A, | |
1258 | PREFIX_VEX_0F3A7B, | |
1259 | PREFIX_VEX_0F3A7C, | |
1260 | PREFIX_VEX_0F3A7D, | |
1261 | PREFIX_VEX_0F3A7E, | |
1262 | PREFIX_VEX_0F3A7F, | |
6c30d220 | 1263 | PREFIX_VEX_0F3ADF, |
43234a1e L |
1264 | PREFIX_VEX_0F3AF0, |
1265 | ||
1266 | PREFIX_EVEX_0F10, | |
1267 | PREFIX_EVEX_0F11, | |
1268 | PREFIX_EVEX_0F12, | |
1269 | PREFIX_EVEX_0F13, | |
1270 | PREFIX_EVEX_0F14, | |
1271 | PREFIX_EVEX_0F15, | |
1272 | PREFIX_EVEX_0F16, | |
1273 | PREFIX_EVEX_0F17, | |
1274 | PREFIX_EVEX_0F28, | |
1275 | PREFIX_EVEX_0F29, | |
1276 | PREFIX_EVEX_0F2A, | |
1277 | PREFIX_EVEX_0F2B, | |
1278 | PREFIX_EVEX_0F2C, | |
1279 | PREFIX_EVEX_0F2D, | |
1280 | PREFIX_EVEX_0F2E, | |
1281 | PREFIX_EVEX_0F2F, | |
1282 | PREFIX_EVEX_0F51, | |
1283 | PREFIX_EVEX_0F58, | |
1284 | PREFIX_EVEX_0F59, | |
1285 | PREFIX_EVEX_0F5A, | |
1286 | PREFIX_EVEX_0F5B, | |
1287 | PREFIX_EVEX_0F5C, | |
1288 | PREFIX_EVEX_0F5D, | |
1289 | PREFIX_EVEX_0F5E, | |
1290 | PREFIX_EVEX_0F5F, | |
1291 | PREFIX_EVEX_0F62, | |
1292 | PREFIX_EVEX_0F66, | |
1293 | PREFIX_EVEX_0F6A, | |
1294 | PREFIX_EVEX_0F6C, | |
1295 | PREFIX_EVEX_0F6D, | |
1296 | PREFIX_EVEX_0F6E, | |
1297 | PREFIX_EVEX_0F6F, | |
1298 | PREFIX_EVEX_0F70, | |
1299 | PREFIX_EVEX_0F72_REG_0, | |
1300 | PREFIX_EVEX_0F72_REG_1, | |
1301 | PREFIX_EVEX_0F72_REG_2, | |
1302 | PREFIX_EVEX_0F72_REG_4, | |
1303 | PREFIX_EVEX_0F72_REG_6, | |
1304 | PREFIX_EVEX_0F73_REG_2, | |
1305 | PREFIX_EVEX_0F73_REG_6, | |
1306 | PREFIX_EVEX_0F76, | |
1307 | PREFIX_EVEX_0F78, | |
1308 | PREFIX_EVEX_0F79, | |
1309 | PREFIX_EVEX_0F7A, | |
1310 | PREFIX_EVEX_0F7B, | |
1311 | PREFIX_EVEX_0F7E, | |
1312 | PREFIX_EVEX_0F7F, | |
1313 | PREFIX_EVEX_0FC2, | |
1314 | PREFIX_EVEX_0FC6, | |
1315 | PREFIX_EVEX_0FD2, | |
1316 | PREFIX_EVEX_0FD3, | |
1317 | PREFIX_EVEX_0FD4, | |
1318 | PREFIX_EVEX_0FD6, | |
1319 | PREFIX_EVEX_0FDB, | |
1320 | PREFIX_EVEX_0FDF, | |
1321 | PREFIX_EVEX_0FE2, | |
1322 | PREFIX_EVEX_0FE6, | |
1323 | PREFIX_EVEX_0FE7, | |
1324 | PREFIX_EVEX_0FEB, | |
1325 | PREFIX_EVEX_0FEF, | |
1326 | PREFIX_EVEX_0FF2, | |
1327 | PREFIX_EVEX_0FF3, | |
1328 | PREFIX_EVEX_0FF4, | |
1329 | PREFIX_EVEX_0FFA, | |
1330 | PREFIX_EVEX_0FFB, | |
1331 | PREFIX_EVEX_0FFE, | |
1332 | PREFIX_EVEX_0F380C, | |
1333 | PREFIX_EVEX_0F380D, | |
1334 | PREFIX_EVEX_0F3811, | |
1335 | PREFIX_EVEX_0F3812, | |
1336 | PREFIX_EVEX_0F3813, | |
1337 | PREFIX_EVEX_0F3814, | |
1338 | PREFIX_EVEX_0F3815, | |
1339 | PREFIX_EVEX_0F3816, | |
1340 | PREFIX_EVEX_0F3818, | |
1341 | PREFIX_EVEX_0F3819, | |
1342 | PREFIX_EVEX_0F381A, | |
1343 | PREFIX_EVEX_0F381B, | |
1344 | PREFIX_EVEX_0F381E, | |
1345 | PREFIX_EVEX_0F381F, | |
1346 | PREFIX_EVEX_0F3821, | |
1347 | PREFIX_EVEX_0F3822, | |
1348 | PREFIX_EVEX_0F3823, | |
1349 | PREFIX_EVEX_0F3824, | |
1350 | PREFIX_EVEX_0F3825, | |
1351 | PREFIX_EVEX_0F3827, | |
1352 | PREFIX_EVEX_0F3828, | |
1353 | PREFIX_EVEX_0F3829, | |
1354 | PREFIX_EVEX_0F382A, | |
1355 | PREFIX_EVEX_0F382C, | |
1356 | PREFIX_EVEX_0F382D, | |
1357 | PREFIX_EVEX_0F3831, | |
1358 | PREFIX_EVEX_0F3832, | |
1359 | PREFIX_EVEX_0F3833, | |
1360 | PREFIX_EVEX_0F3834, | |
1361 | PREFIX_EVEX_0F3835, | |
1362 | PREFIX_EVEX_0F3836, | |
1363 | PREFIX_EVEX_0F3837, | |
1364 | PREFIX_EVEX_0F3839, | |
1365 | PREFIX_EVEX_0F383A, | |
1366 | PREFIX_EVEX_0F383B, | |
1367 | PREFIX_EVEX_0F383D, | |
1368 | PREFIX_EVEX_0F383F, | |
1369 | PREFIX_EVEX_0F3840, | |
1370 | PREFIX_EVEX_0F3842, | |
1371 | PREFIX_EVEX_0F3843, | |
1372 | PREFIX_EVEX_0F3844, | |
1373 | PREFIX_EVEX_0F3845, | |
1374 | PREFIX_EVEX_0F3846, | |
1375 | PREFIX_EVEX_0F3847, | |
1376 | PREFIX_EVEX_0F384C, | |
1377 | PREFIX_EVEX_0F384D, | |
1378 | PREFIX_EVEX_0F384E, | |
1379 | PREFIX_EVEX_0F384F, | |
1380 | PREFIX_EVEX_0F3858, | |
1381 | PREFIX_EVEX_0F3859, | |
1382 | PREFIX_EVEX_0F385A, | |
1383 | PREFIX_EVEX_0F385B, | |
1384 | PREFIX_EVEX_0F3864, | |
1385 | PREFIX_EVEX_0F3865, | |
1386 | PREFIX_EVEX_0F3876, | |
1387 | PREFIX_EVEX_0F3877, | |
1388 | PREFIX_EVEX_0F387C, | |
1389 | PREFIX_EVEX_0F387E, | |
1390 | PREFIX_EVEX_0F387F, | |
1391 | PREFIX_EVEX_0F3888, | |
1392 | PREFIX_EVEX_0F3889, | |
1393 | PREFIX_EVEX_0F388A, | |
1394 | PREFIX_EVEX_0F388B, | |
1395 | PREFIX_EVEX_0F3890, | |
1396 | PREFIX_EVEX_0F3891, | |
1397 | PREFIX_EVEX_0F3892, | |
1398 | PREFIX_EVEX_0F3893, | |
1399 | PREFIX_EVEX_0F3896, | |
1400 | PREFIX_EVEX_0F3897, | |
1401 | PREFIX_EVEX_0F3898, | |
1402 | PREFIX_EVEX_0F3899, | |
1403 | PREFIX_EVEX_0F389A, | |
1404 | PREFIX_EVEX_0F389B, | |
1405 | PREFIX_EVEX_0F389C, | |
1406 | PREFIX_EVEX_0F389D, | |
1407 | PREFIX_EVEX_0F389E, | |
1408 | PREFIX_EVEX_0F389F, | |
1409 | PREFIX_EVEX_0F38A0, | |
1410 | PREFIX_EVEX_0F38A1, | |
1411 | PREFIX_EVEX_0F38A2, | |
1412 | PREFIX_EVEX_0F38A3, | |
1413 | PREFIX_EVEX_0F38A6, | |
1414 | PREFIX_EVEX_0F38A7, | |
1415 | PREFIX_EVEX_0F38A8, | |
1416 | PREFIX_EVEX_0F38A9, | |
1417 | PREFIX_EVEX_0F38AA, | |
1418 | PREFIX_EVEX_0F38AB, | |
1419 | PREFIX_EVEX_0F38AC, | |
1420 | PREFIX_EVEX_0F38AD, | |
1421 | PREFIX_EVEX_0F38AE, | |
1422 | PREFIX_EVEX_0F38AF, | |
1423 | PREFIX_EVEX_0F38B6, | |
1424 | PREFIX_EVEX_0F38B7, | |
1425 | PREFIX_EVEX_0F38B8, | |
1426 | PREFIX_EVEX_0F38B9, | |
1427 | PREFIX_EVEX_0F38BA, | |
1428 | PREFIX_EVEX_0F38BB, | |
1429 | PREFIX_EVEX_0F38BC, | |
1430 | PREFIX_EVEX_0F38BD, | |
1431 | PREFIX_EVEX_0F38BE, | |
1432 | PREFIX_EVEX_0F38BF, | |
1433 | PREFIX_EVEX_0F38C4, | |
1434 | PREFIX_EVEX_0F38C6_REG_1, | |
1435 | PREFIX_EVEX_0F38C6_REG_2, | |
1436 | PREFIX_EVEX_0F38C6_REG_5, | |
1437 | PREFIX_EVEX_0F38C6_REG_6, | |
1438 | PREFIX_EVEX_0F38C7_REG_1, | |
1439 | PREFIX_EVEX_0F38C7_REG_2, | |
1440 | PREFIX_EVEX_0F38C7_REG_5, | |
1441 | PREFIX_EVEX_0F38C7_REG_6, | |
1442 | PREFIX_EVEX_0F38C8, | |
1443 | PREFIX_EVEX_0F38CA, | |
1444 | PREFIX_EVEX_0F38CB, | |
1445 | PREFIX_EVEX_0F38CC, | |
1446 | PREFIX_EVEX_0F38CD, | |
1447 | ||
1448 | PREFIX_EVEX_0F3A00, | |
1449 | PREFIX_EVEX_0F3A01, | |
1450 | PREFIX_EVEX_0F3A03, | |
1451 | PREFIX_EVEX_0F3A04, | |
1452 | PREFIX_EVEX_0F3A05, | |
1453 | PREFIX_EVEX_0F3A08, | |
1454 | PREFIX_EVEX_0F3A09, | |
1455 | PREFIX_EVEX_0F3A0A, | |
1456 | PREFIX_EVEX_0F3A0B, | |
1457 | PREFIX_EVEX_0F3A17, | |
1458 | PREFIX_EVEX_0F3A18, | |
1459 | PREFIX_EVEX_0F3A19, | |
1460 | PREFIX_EVEX_0F3A1A, | |
1461 | PREFIX_EVEX_0F3A1B, | |
1462 | PREFIX_EVEX_0F3A1D, | |
1463 | PREFIX_EVEX_0F3A1E, | |
1464 | PREFIX_EVEX_0F3A1F, | |
1465 | PREFIX_EVEX_0F3A21, | |
1466 | PREFIX_EVEX_0F3A23, | |
1467 | PREFIX_EVEX_0F3A25, | |
1468 | PREFIX_EVEX_0F3A26, | |
1469 | PREFIX_EVEX_0F3A27, | |
1470 | PREFIX_EVEX_0F3A38, | |
1471 | PREFIX_EVEX_0F3A39, | |
1472 | PREFIX_EVEX_0F3A3A, | |
1473 | PREFIX_EVEX_0F3A3B, | |
43234a1e L |
1474 | PREFIX_EVEX_0F3A43, |
1475 | PREFIX_EVEX_0F3A54, | |
1476 | PREFIX_EVEX_0F3A55, | |
51e7da1b | 1477 | }; |
4e7d34a6 | 1478 | |
51e7da1b L |
1479 | enum |
1480 | { | |
1481 | X86_64_06 = 0, | |
3873ba12 L |
1482 | X86_64_07, |
1483 | X86_64_0D, | |
1484 | X86_64_16, | |
1485 | X86_64_17, | |
1486 | X86_64_1E, | |
1487 | X86_64_1F, | |
1488 | X86_64_27, | |
1489 | X86_64_2F, | |
1490 | X86_64_37, | |
1491 | X86_64_3F, | |
1492 | X86_64_60, | |
1493 | X86_64_61, | |
1494 | X86_64_62, | |
1495 | X86_64_63, | |
1496 | X86_64_6D, | |
1497 | X86_64_6F, | |
1498 | X86_64_9A, | |
1499 | X86_64_C4, | |
1500 | X86_64_C5, | |
1501 | X86_64_CE, | |
1502 | X86_64_D4, | |
1503 | X86_64_D5, | |
1504 | X86_64_EA, | |
1505 | X86_64_0F01_REG_0, | |
1506 | X86_64_0F01_REG_1, | |
1507 | X86_64_0F01_REG_2, | |
1508 | X86_64_0F01_REG_3 | |
51e7da1b | 1509 | }; |
4e7d34a6 | 1510 | |
51e7da1b L |
1511 | enum |
1512 | { | |
1513 | THREE_BYTE_0F38 = 0, | |
3873ba12 L |
1514 | THREE_BYTE_0F3A, |
1515 | THREE_BYTE_0F7A | |
51e7da1b | 1516 | }; |
4e7d34a6 | 1517 | |
f88c9eb0 SP |
1518 | enum |
1519 | { | |
5dd85c99 SP |
1520 | XOP_08 = 0, |
1521 | XOP_09, | |
f88c9eb0 SP |
1522 | XOP_0A |
1523 | }; | |
1524 | ||
51e7da1b L |
1525 | enum |
1526 | { | |
1527 | VEX_0F = 0, | |
3873ba12 L |
1528 | VEX_0F38, |
1529 | VEX_0F3A | |
51e7da1b | 1530 | }; |
c0f3af97 | 1531 | |
43234a1e L |
1532 | enum |
1533 | { | |
1534 | EVEX_0F = 0, | |
1535 | EVEX_0F38, | |
1536 | EVEX_0F3A | |
1537 | }; | |
1538 | ||
51e7da1b L |
1539 | enum |
1540 | { | |
592a252b L |
1541 | VEX_LEN_0F10_P_1 = 0, |
1542 | VEX_LEN_0F10_P_3, | |
1543 | VEX_LEN_0F11_P_1, | |
1544 | VEX_LEN_0F11_P_3, | |
1545 | VEX_LEN_0F12_P_0_M_0, | |
1546 | VEX_LEN_0F12_P_0_M_1, | |
1547 | VEX_LEN_0F12_P_2, | |
1548 | VEX_LEN_0F13_M_0, | |
1549 | VEX_LEN_0F16_P_0_M_0, | |
1550 | VEX_LEN_0F16_P_0_M_1, | |
1551 | VEX_LEN_0F16_P_2, | |
1552 | VEX_LEN_0F17_M_0, | |
1553 | VEX_LEN_0F2A_P_1, | |
1554 | VEX_LEN_0F2A_P_3, | |
1555 | VEX_LEN_0F2C_P_1, | |
1556 | VEX_LEN_0F2C_P_3, | |
1557 | VEX_LEN_0F2D_P_1, | |
1558 | VEX_LEN_0F2D_P_3, | |
1559 | VEX_LEN_0F2E_P_0, | |
1560 | VEX_LEN_0F2E_P_2, | |
1561 | VEX_LEN_0F2F_P_0, | |
1562 | VEX_LEN_0F2F_P_2, | |
43234a1e L |
1563 | VEX_LEN_0F41_P_0, |
1564 | VEX_LEN_0F42_P_0, | |
1565 | VEX_LEN_0F44_P_0, | |
1566 | VEX_LEN_0F45_P_0, | |
1567 | VEX_LEN_0F46_P_0, | |
1568 | VEX_LEN_0F47_P_0, | |
1569 | VEX_LEN_0F4B_P_2, | |
592a252b L |
1570 | VEX_LEN_0F51_P_1, |
1571 | VEX_LEN_0F51_P_3, | |
1572 | VEX_LEN_0F52_P_1, | |
1573 | VEX_LEN_0F53_P_1, | |
1574 | VEX_LEN_0F58_P_1, | |
1575 | VEX_LEN_0F58_P_3, | |
1576 | VEX_LEN_0F59_P_1, | |
1577 | VEX_LEN_0F59_P_3, | |
1578 | VEX_LEN_0F5A_P_1, | |
1579 | VEX_LEN_0F5A_P_3, | |
1580 | VEX_LEN_0F5C_P_1, | |
1581 | VEX_LEN_0F5C_P_3, | |
1582 | VEX_LEN_0F5D_P_1, | |
1583 | VEX_LEN_0F5D_P_3, | |
1584 | VEX_LEN_0F5E_P_1, | |
1585 | VEX_LEN_0F5E_P_3, | |
1586 | VEX_LEN_0F5F_P_1, | |
1587 | VEX_LEN_0F5F_P_3, | |
592a252b | 1588 | VEX_LEN_0F6E_P_2, |
592a252b L |
1589 | VEX_LEN_0F7E_P_1, |
1590 | VEX_LEN_0F7E_P_2, | |
43234a1e L |
1591 | VEX_LEN_0F90_P_0, |
1592 | VEX_LEN_0F91_P_0, | |
1593 | VEX_LEN_0F92_P_0, | |
1594 | VEX_LEN_0F93_P_0, | |
1595 | VEX_LEN_0F98_P_0, | |
592a252b L |
1596 | VEX_LEN_0FAE_R_2_M_0, |
1597 | VEX_LEN_0FAE_R_3_M_0, | |
1598 | VEX_LEN_0FC2_P_1, | |
1599 | VEX_LEN_0FC2_P_3, | |
1600 | VEX_LEN_0FC4_P_2, | |
1601 | VEX_LEN_0FC5_P_2, | |
592a252b | 1602 | VEX_LEN_0FD6_P_2, |
592a252b | 1603 | VEX_LEN_0FF7_P_2, |
6c30d220 L |
1604 | VEX_LEN_0F3816_P_2, |
1605 | VEX_LEN_0F3819_P_2, | |
592a252b | 1606 | VEX_LEN_0F381A_P_2_M_0, |
6c30d220 | 1607 | VEX_LEN_0F3836_P_2, |
592a252b | 1608 | VEX_LEN_0F3841_P_2, |
6c30d220 | 1609 | VEX_LEN_0F385A_P_2_M_0, |
592a252b L |
1610 | VEX_LEN_0F38DB_P_2, |
1611 | VEX_LEN_0F38DC_P_2, | |
1612 | VEX_LEN_0F38DD_P_2, | |
1613 | VEX_LEN_0F38DE_P_2, | |
1614 | VEX_LEN_0F38DF_P_2, | |
f12dc422 L |
1615 | VEX_LEN_0F38F2_P_0, |
1616 | VEX_LEN_0F38F3_R_1_P_0, | |
1617 | VEX_LEN_0F38F3_R_2_P_0, | |
1618 | VEX_LEN_0F38F3_R_3_P_0, | |
6c30d220 L |
1619 | VEX_LEN_0F38F5_P_0, |
1620 | VEX_LEN_0F38F5_P_1, | |
1621 | VEX_LEN_0F38F5_P_3, | |
1622 | VEX_LEN_0F38F6_P_3, | |
f12dc422 | 1623 | VEX_LEN_0F38F7_P_0, |
6c30d220 L |
1624 | VEX_LEN_0F38F7_P_1, |
1625 | VEX_LEN_0F38F7_P_2, | |
1626 | VEX_LEN_0F38F7_P_3, | |
1627 | VEX_LEN_0F3A00_P_2, | |
1628 | VEX_LEN_0F3A01_P_2, | |
592a252b L |
1629 | VEX_LEN_0F3A06_P_2, |
1630 | VEX_LEN_0F3A0A_P_2, | |
1631 | VEX_LEN_0F3A0B_P_2, | |
592a252b L |
1632 | VEX_LEN_0F3A14_P_2, |
1633 | VEX_LEN_0F3A15_P_2, | |
1634 | VEX_LEN_0F3A16_P_2, | |
1635 | VEX_LEN_0F3A17_P_2, | |
1636 | VEX_LEN_0F3A18_P_2, | |
1637 | VEX_LEN_0F3A19_P_2, | |
1638 | VEX_LEN_0F3A20_P_2, | |
1639 | VEX_LEN_0F3A21_P_2, | |
1640 | VEX_LEN_0F3A22_P_2, | |
43234a1e L |
1641 | VEX_LEN_0F3A30_P_2, |
1642 | VEX_LEN_0F3A32_P_2, | |
6c30d220 L |
1643 | VEX_LEN_0F3A38_P_2, |
1644 | VEX_LEN_0F3A39_P_2, | |
592a252b | 1645 | VEX_LEN_0F3A41_P_2, |
592a252b | 1646 | VEX_LEN_0F3A44_P_2, |
6c30d220 | 1647 | VEX_LEN_0F3A46_P_2, |
592a252b L |
1648 | VEX_LEN_0F3A60_P_2, |
1649 | VEX_LEN_0F3A61_P_2, | |
1650 | VEX_LEN_0F3A62_P_2, | |
1651 | VEX_LEN_0F3A63_P_2, | |
1652 | VEX_LEN_0F3A6A_P_2, | |
1653 | VEX_LEN_0F3A6B_P_2, | |
1654 | VEX_LEN_0F3A6E_P_2, | |
1655 | VEX_LEN_0F3A6F_P_2, | |
1656 | VEX_LEN_0F3A7A_P_2, | |
1657 | VEX_LEN_0F3A7B_P_2, | |
1658 | VEX_LEN_0F3A7E_P_2, | |
1659 | VEX_LEN_0F3A7F_P_2, | |
1660 | VEX_LEN_0F3ADF_P_2, | |
6c30d220 | 1661 | VEX_LEN_0F3AF0_P_3, |
ff688e1f L |
1662 | VEX_LEN_0FXOP_08_CC, |
1663 | VEX_LEN_0FXOP_08_CD, | |
1664 | VEX_LEN_0FXOP_08_CE, | |
1665 | VEX_LEN_0FXOP_08_CF, | |
1666 | VEX_LEN_0FXOP_08_EC, | |
1667 | VEX_LEN_0FXOP_08_ED, | |
1668 | VEX_LEN_0FXOP_08_EE, | |
1669 | VEX_LEN_0FXOP_08_EF, | |
592a252b L |
1670 | VEX_LEN_0FXOP_09_80, |
1671 | VEX_LEN_0FXOP_09_81 | |
51e7da1b | 1672 | }; |
c0f3af97 | 1673 | |
9e30b8e0 L |
1674 | enum |
1675 | { | |
592a252b L |
1676 | VEX_W_0F10_P_0 = 0, |
1677 | VEX_W_0F10_P_1, | |
1678 | VEX_W_0F10_P_2, | |
1679 | VEX_W_0F10_P_3, | |
1680 | VEX_W_0F11_P_0, | |
1681 | VEX_W_0F11_P_1, | |
1682 | VEX_W_0F11_P_2, | |
1683 | VEX_W_0F11_P_3, | |
1684 | VEX_W_0F12_P_0_M_0, | |
1685 | VEX_W_0F12_P_0_M_1, | |
1686 | VEX_W_0F12_P_1, | |
1687 | VEX_W_0F12_P_2, | |
1688 | VEX_W_0F12_P_3, | |
1689 | VEX_W_0F13_M_0, | |
1690 | VEX_W_0F14, | |
1691 | VEX_W_0F15, | |
1692 | VEX_W_0F16_P_0_M_0, | |
1693 | VEX_W_0F16_P_0_M_1, | |
1694 | VEX_W_0F16_P_1, | |
1695 | VEX_W_0F16_P_2, | |
1696 | VEX_W_0F17_M_0, | |
1697 | VEX_W_0F28, | |
1698 | VEX_W_0F29, | |
1699 | VEX_W_0F2B_M_0, | |
1700 | VEX_W_0F2E_P_0, | |
1701 | VEX_W_0F2E_P_2, | |
1702 | VEX_W_0F2F_P_0, | |
1703 | VEX_W_0F2F_P_2, | |
43234a1e L |
1704 | VEX_W_0F41_P_0_LEN_1, |
1705 | VEX_W_0F42_P_0_LEN_1, | |
1706 | VEX_W_0F44_P_0_LEN_0, | |
1707 | VEX_W_0F45_P_0_LEN_1, | |
1708 | VEX_W_0F46_P_0_LEN_1, | |
1709 | VEX_W_0F47_P_0_LEN_1, | |
1710 | VEX_W_0F4B_P_2_LEN_1, | |
592a252b L |
1711 | VEX_W_0F50_M_0, |
1712 | VEX_W_0F51_P_0, | |
1713 | VEX_W_0F51_P_1, | |
1714 | VEX_W_0F51_P_2, | |
1715 | VEX_W_0F51_P_3, | |
1716 | VEX_W_0F52_P_0, | |
1717 | VEX_W_0F52_P_1, | |
1718 | VEX_W_0F53_P_0, | |
1719 | VEX_W_0F53_P_1, | |
1720 | VEX_W_0F58_P_0, | |
1721 | VEX_W_0F58_P_1, | |
1722 | VEX_W_0F58_P_2, | |
1723 | VEX_W_0F58_P_3, | |
1724 | VEX_W_0F59_P_0, | |
1725 | VEX_W_0F59_P_1, | |
1726 | VEX_W_0F59_P_2, | |
1727 | VEX_W_0F59_P_3, | |
1728 | VEX_W_0F5A_P_0, | |
1729 | VEX_W_0F5A_P_1, | |
1730 | VEX_W_0F5A_P_3, | |
1731 | VEX_W_0F5B_P_0, | |
1732 | VEX_W_0F5B_P_1, | |
1733 | VEX_W_0F5B_P_2, | |
1734 | VEX_W_0F5C_P_0, | |
1735 | VEX_W_0F5C_P_1, | |
1736 | VEX_W_0F5C_P_2, | |
1737 | VEX_W_0F5C_P_3, | |
1738 | VEX_W_0F5D_P_0, | |
1739 | VEX_W_0F5D_P_1, | |
1740 | VEX_W_0F5D_P_2, | |
1741 | VEX_W_0F5D_P_3, | |
1742 | VEX_W_0F5E_P_0, | |
1743 | VEX_W_0F5E_P_1, | |
1744 | VEX_W_0F5E_P_2, | |
1745 | VEX_W_0F5E_P_3, | |
1746 | VEX_W_0F5F_P_0, | |
1747 | VEX_W_0F5F_P_1, | |
1748 | VEX_W_0F5F_P_2, | |
1749 | VEX_W_0F5F_P_3, | |
1750 | VEX_W_0F60_P_2, | |
1751 | VEX_W_0F61_P_2, | |
1752 | VEX_W_0F62_P_2, | |
1753 | VEX_W_0F63_P_2, | |
1754 | VEX_W_0F64_P_2, | |
1755 | VEX_W_0F65_P_2, | |
1756 | VEX_W_0F66_P_2, | |
1757 | VEX_W_0F67_P_2, | |
1758 | VEX_W_0F68_P_2, | |
1759 | VEX_W_0F69_P_2, | |
1760 | VEX_W_0F6A_P_2, | |
1761 | VEX_W_0F6B_P_2, | |
1762 | VEX_W_0F6C_P_2, | |
1763 | VEX_W_0F6D_P_2, | |
1764 | VEX_W_0F6F_P_1, | |
1765 | VEX_W_0F6F_P_2, | |
1766 | VEX_W_0F70_P_1, | |
1767 | VEX_W_0F70_P_2, | |
1768 | VEX_W_0F70_P_3, | |
1769 | VEX_W_0F71_R_2_P_2, | |
1770 | VEX_W_0F71_R_4_P_2, | |
1771 | VEX_W_0F71_R_6_P_2, | |
1772 | VEX_W_0F72_R_2_P_2, | |
1773 | VEX_W_0F72_R_4_P_2, | |
1774 | VEX_W_0F72_R_6_P_2, | |
1775 | VEX_W_0F73_R_2_P_2, | |
1776 | VEX_W_0F73_R_3_P_2, | |
1777 | VEX_W_0F73_R_6_P_2, | |
1778 | VEX_W_0F73_R_7_P_2, | |
1779 | VEX_W_0F74_P_2, | |
1780 | VEX_W_0F75_P_2, | |
1781 | VEX_W_0F76_P_2, | |
1782 | VEX_W_0F77_P_0, | |
1783 | VEX_W_0F7C_P_2, | |
1784 | VEX_W_0F7C_P_3, | |
1785 | VEX_W_0F7D_P_2, | |
1786 | VEX_W_0F7D_P_3, | |
1787 | VEX_W_0F7E_P_1, | |
1788 | VEX_W_0F7F_P_1, | |
1789 | VEX_W_0F7F_P_2, | |
43234a1e L |
1790 | VEX_W_0F90_P_0_LEN_0, |
1791 | VEX_W_0F91_P_0_LEN_0, | |
1792 | VEX_W_0F92_P_0_LEN_0, | |
1793 | VEX_W_0F93_P_0_LEN_0, | |
1794 | VEX_W_0F98_P_0_LEN_0, | |
592a252b L |
1795 | VEX_W_0FAE_R_2_M_0, |
1796 | VEX_W_0FAE_R_3_M_0, | |
1797 | VEX_W_0FC2_P_0, | |
1798 | VEX_W_0FC2_P_1, | |
1799 | VEX_W_0FC2_P_2, | |
1800 | VEX_W_0FC2_P_3, | |
1801 | VEX_W_0FC4_P_2, | |
1802 | VEX_W_0FC5_P_2, | |
1803 | VEX_W_0FD0_P_2, | |
1804 | VEX_W_0FD0_P_3, | |
1805 | VEX_W_0FD1_P_2, | |
1806 | VEX_W_0FD2_P_2, | |
1807 | VEX_W_0FD3_P_2, | |
1808 | VEX_W_0FD4_P_2, | |
1809 | VEX_W_0FD5_P_2, | |
1810 | VEX_W_0FD6_P_2, | |
1811 | VEX_W_0FD7_P_2_M_1, | |
1812 | VEX_W_0FD8_P_2, | |
1813 | VEX_W_0FD9_P_2, | |
1814 | VEX_W_0FDA_P_2, | |
1815 | VEX_W_0FDB_P_2, | |
1816 | VEX_W_0FDC_P_2, | |
1817 | VEX_W_0FDD_P_2, | |
1818 | VEX_W_0FDE_P_2, | |
1819 | VEX_W_0FDF_P_2, | |
1820 | VEX_W_0FE0_P_2, | |
1821 | VEX_W_0FE1_P_2, | |
1822 | VEX_W_0FE2_P_2, | |
1823 | VEX_W_0FE3_P_2, | |
1824 | VEX_W_0FE4_P_2, | |
1825 | VEX_W_0FE5_P_2, | |
1826 | VEX_W_0FE6_P_1, | |
1827 | VEX_W_0FE6_P_2, | |
1828 | VEX_W_0FE6_P_3, | |
1829 | VEX_W_0FE7_P_2_M_0, | |
1830 | VEX_W_0FE8_P_2, | |
1831 | VEX_W_0FE9_P_2, | |
1832 | VEX_W_0FEA_P_2, | |
1833 | VEX_W_0FEB_P_2, | |
1834 | VEX_W_0FEC_P_2, | |
1835 | VEX_W_0FED_P_2, | |
1836 | VEX_W_0FEE_P_2, | |
1837 | VEX_W_0FEF_P_2, | |
1838 | VEX_W_0FF0_P_3_M_0, | |
1839 | VEX_W_0FF1_P_2, | |
1840 | VEX_W_0FF2_P_2, | |
1841 | VEX_W_0FF3_P_2, | |
1842 | VEX_W_0FF4_P_2, | |
1843 | VEX_W_0FF5_P_2, | |
1844 | VEX_W_0FF6_P_2, | |
1845 | VEX_W_0FF7_P_2, | |
1846 | VEX_W_0FF8_P_2, | |
1847 | VEX_W_0FF9_P_2, | |
1848 | VEX_W_0FFA_P_2, | |
1849 | VEX_W_0FFB_P_2, | |
1850 | VEX_W_0FFC_P_2, | |
1851 | VEX_W_0FFD_P_2, | |
1852 | VEX_W_0FFE_P_2, | |
1853 | VEX_W_0F3800_P_2, | |
1854 | VEX_W_0F3801_P_2, | |
1855 | VEX_W_0F3802_P_2, | |
1856 | VEX_W_0F3803_P_2, | |
1857 | VEX_W_0F3804_P_2, | |
1858 | VEX_W_0F3805_P_2, | |
1859 | VEX_W_0F3806_P_2, | |
1860 | VEX_W_0F3807_P_2, | |
1861 | VEX_W_0F3808_P_2, | |
1862 | VEX_W_0F3809_P_2, | |
1863 | VEX_W_0F380A_P_2, | |
1864 | VEX_W_0F380B_P_2, | |
1865 | VEX_W_0F380C_P_2, | |
1866 | VEX_W_0F380D_P_2, | |
1867 | VEX_W_0F380E_P_2, | |
1868 | VEX_W_0F380F_P_2, | |
6c30d220 | 1869 | VEX_W_0F3816_P_2, |
592a252b | 1870 | VEX_W_0F3817_P_2, |
6c30d220 L |
1871 | VEX_W_0F3818_P_2, |
1872 | VEX_W_0F3819_P_2, | |
592a252b L |
1873 | VEX_W_0F381A_P_2_M_0, |
1874 | VEX_W_0F381C_P_2, | |
1875 | VEX_W_0F381D_P_2, | |
1876 | VEX_W_0F381E_P_2, | |
1877 | VEX_W_0F3820_P_2, | |
1878 | VEX_W_0F3821_P_2, | |
1879 | VEX_W_0F3822_P_2, | |
1880 | VEX_W_0F3823_P_2, | |
1881 | VEX_W_0F3824_P_2, | |
1882 | VEX_W_0F3825_P_2, | |
1883 | VEX_W_0F3828_P_2, | |
1884 | VEX_W_0F3829_P_2, | |
1885 | VEX_W_0F382A_P_2_M_0, | |
1886 | VEX_W_0F382B_P_2, | |
1887 | VEX_W_0F382C_P_2_M_0, | |
1888 | VEX_W_0F382D_P_2_M_0, | |
1889 | VEX_W_0F382E_P_2_M_0, | |
1890 | VEX_W_0F382F_P_2_M_0, | |
1891 | VEX_W_0F3830_P_2, | |
1892 | VEX_W_0F3831_P_2, | |
1893 | VEX_W_0F3832_P_2, | |
1894 | VEX_W_0F3833_P_2, | |
1895 | VEX_W_0F3834_P_2, | |
1896 | VEX_W_0F3835_P_2, | |
6c30d220 | 1897 | VEX_W_0F3836_P_2, |
592a252b L |
1898 | VEX_W_0F3837_P_2, |
1899 | VEX_W_0F3838_P_2, | |
1900 | VEX_W_0F3839_P_2, | |
1901 | VEX_W_0F383A_P_2, | |
1902 | VEX_W_0F383B_P_2, | |
1903 | VEX_W_0F383C_P_2, | |
1904 | VEX_W_0F383D_P_2, | |
1905 | VEX_W_0F383E_P_2, | |
1906 | VEX_W_0F383F_P_2, | |
1907 | VEX_W_0F3840_P_2, | |
1908 | VEX_W_0F3841_P_2, | |
6c30d220 L |
1909 | VEX_W_0F3846_P_2, |
1910 | VEX_W_0F3858_P_2, | |
1911 | VEX_W_0F3859_P_2, | |
1912 | VEX_W_0F385A_P_2_M_0, | |
1913 | VEX_W_0F3878_P_2, | |
1914 | VEX_W_0F3879_P_2, | |
592a252b L |
1915 | VEX_W_0F38DB_P_2, |
1916 | VEX_W_0F38DC_P_2, | |
1917 | VEX_W_0F38DD_P_2, | |
1918 | VEX_W_0F38DE_P_2, | |
1919 | VEX_W_0F38DF_P_2, | |
6c30d220 L |
1920 | VEX_W_0F3A00_P_2, |
1921 | VEX_W_0F3A01_P_2, | |
1922 | VEX_W_0F3A02_P_2, | |
592a252b L |
1923 | VEX_W_0F3A04_P_2, |
1924 | VEX_W_0F3A05_P_2, | |
1925 | VEX_W_0F3A06_P_2, | |
1926 | VEX_W_0F3A08_P_2, | |
1927 | VEX_W_0F3A09_P_2, | |
1928 | VEX_W_0F3A0A_P_2, | |
1929 | VEX_W_0F3A0B_P_2, | |
1930 | VEX_W_0F3A0C_P_2, | |
1931 | VEX_W_0F3A0D_P_2, | |
1932 | VEX_W_0F3A0E_P_2, | |
1933 | VEX_W_0F3A0F_P_2, | |
1934 | VEX_W_0F3A14_P_2, | |
1935 | VEX_W_0F3A15_P_2, | |
1936 | VEX_W_0F3A18_P_2, | |
1937 | VEX_W_0F3A19_P_2, | |
1938 | VEX_W_0F3A20_P_2, | |
1939 | VEX_W_0F3A21_P_2, | |
43234a1e L |
1940 | VEX_W_0F3A30_P_2_LEN_0, |
1941 | VEX_W_0F3A32_P_2_LEN_0, | |
6c30d220 L |
1942 | VEX_W_0F3A38_P_2, |
1943 | VEX_W_0F3A39_P_2, | |
592a252b L |
1944 | VEX_W_0F3A40_P_2, |
1945 | VEX_W_0F3A41_P_2, | |
1946 | VEX_W_0F3A42_P_2, | |
1947 | VEX_W_0F3A44_P_2, | |
6c30d220 | 1948 | VEX_W_0F3A46_P_2, |
592a252b L |
1949 | VEX_W_0F3A48_P_2, |
1950 | VEX_W_0F3A49_P_2, | |
1951 | VEX_W_0F3A4A_P_2, | |
1952 | VEX_W_0F3A4B_P_2, | |
1953 | VEX_W_0F3A4C_P_2, | |
1954 | VEX_W_0F3A60_P_2, | |
1955 | VEX_W_0F3A61_P_2, | |
1956 | VEX_W_0F3A62_P_2, | |
1957 | VEX_W_0F3A63_P_2, | |
43234a1e L |
1958 | VEX_W_0F3ADF_P_2, |
1959 | ||
1960 | EVEX_W_0F10_P_0, | |
1961 | EVEX_W_0F10_P_1_M_0, | |
1962 | EVEX_W_0F10_P_1_M_1, | |
1963 | EVEX_W_0F10_P_2, | |
1964 | EVEX_W_0F10_P_3_M_0, | |
1965 | EVEX_W_0F10_P_3_M_1, | |
1966 | EVEX_W_0F11_P_0, | |
1967 | EVEX_W_0F11_P_1_M_0, | |
1968 | EVEX_W_0F11_P_1_M_1, | |
1969 | EVEX_W_0F11_P_2, | |
1970 | EVEX_W_0F11_P_3_M_0, | |
1971 | EVEX_W_0F11_P_3_M_1, | |
1972 | EVEX_W_0F12_P_0_M_0, | |
1973 | EVEX_W_0F12_P_0_M_1, | |
1974 | EVEX_W_0F12_P_1, | |
1975 | EVEX_W_0F12_P_2, | |
1976 | EVEX_W_0F12_P_3, | |
1977 | EVEX_W_0F13_P_0, | |
1978 | EVEX_W_0F13_P_2, | |
1979 | EVEX_W_0F14_P_0, | |
1980 | EVEX_W_0F14_P_2, | |
1981 | EVEX_W_0F15_P_0, | |
1982 | EVEX_W_0F15_P_2, | |
1983 | EVEX_W_0F16_P_0_M_0, | |
1984 | EVEX_W_0F16_P_0_M_1, | |
1985 | EVEX_W_0F16_P_1, | |
1986 | EVEX_W_0F16_P_2, | |
1987 | EVEX_W_0F17_P_0, | |
1988 | EVEX_W_0F17_P_2, | |
1989 | EVEX_W_0F28_P_0, | |
1990 | EVEX_W_0F28_P_2, | |
1991 | EVEX_W_0F29_P_0, | |
1992 | EVEX_W_0F29_P_2, | |
1993 | EVEX_W_0F2A_P_1, | |
1994 | EVEX_W_0F2A_P_3, | |
1995 | EVEX_W_0F2B_P_0, | |
1996 | EVEX_W_0F2B_P_2, | |
1997 | EVEX_W_0F2E_P_0, | |
1998 | EVEX_W_0F2E_P_2, | |
1999 | EVEX_W_0F2F_P_0, | |
2000 | EVEX_W_0F2F_P_2, | |
2001 | EVEX_W_0F51_P_0, | |
2002 | EVEX_W_0F51_P_1, | |
2003 | EVEX_W_0F51_P_2, | |
2004 | EVEX_W_0F51_P_3, | |
2005 | EVEX_W_0F58_P_0, | |
2006 | EVEX_W_0F58_P_1, | |
2007 | EVEX_W_0F58_P_2, | |
2008 | EVEX_W_0F58_P_3, | |
2009 | EVEX_W_0F59_P_0, | |
2010 | EVEX_W_0F59_P_1, | |
2011 | EVEX_W_0F59_P_2, | |
2012 | EVEX_W_0F59_P_3, | |
2013 | EVEX_W_0F5A_P_0, | |
2014 | EVEX_W_0F5A_P_1, | |
2015 | EVEX_W_0F5A_P_2, | |
2016 | EVEX_W_0F5A_P_3, | |
2017 | EVEX_W_0F5B_P_0, | |
2018 | EVEX_W_0F5B_P_1, | |
2019 | EVEX_W_0F5B_P_2, | |
2020 | EVEX_W_0F5C_P_0, | |
2021 | EVEX_W_0F5C_P_1, | |
2022 | EVEX_W_0F5C_P_2, | |
2023 | EVEX_W_0F5C_P_3, | |
2024 | EVEX_W_0F5D_P_0, | |
2025 | EVEX_W_0F5D_P_1, | |
2026 | EVEX_W_0F5D_P_2, | |
2027 | EVEX_W_0F5D_P_3, | |
2028 | EVEX_W_0F5E_P_0, | |
2029 | EVEX_W_0F5E_P_1, | |
2030 | EVEX_W_0F5E_P_2, | |
2031 | EVEX_W_0F5E_P_3, | |
2032 | EVEX_W_0F5F_P_0, | |
2033 | EVEX_W_0F5F_P_1, | |
2034 | EVEX_W_0F5F_P_2, | |
2035 | EVEX_W_0F5F_P_3, | |
2036 | EVEX_W_0F62_P_2, | |
2037 | EVEX_W_0F66_P_2, | |
2038 | EVEX_W_0F6A_P_2, | |
2039 | EVEX_W_0F6C_P_2, | |
2040 | EVEX_W_0F6D_P_2, | |
2041 | EVEX_W_0F6E_P_2, | |
2042 | EVEX_W_0F6F_P_1, | |
2043 | EVEX_W_0F6F_P_2, | |
2044 | EVEX_W_0F70_P_2, | |
2045 | EVEX_W_0F72_R_2_P_2, | |
2046 | EVEX_W_0F72_R_6_P_2, | |
2047 | EVEX_W_0F73_R_2_P_2, | |
2048 | EVEX_W_0F73_R_6_P_2, | |
2049 | EVEX_W_0F76_P_2, | |
2050 | EVEX_W_0F78_P_0, | |
2051 | EVEX_W_0F79_P_0, | |
2052 | EVEX_W_0F7A_P_1, | |
2053 | EVEX_W_0F7A_P_3, | |
2054 | EVEX_W_0F7B_P_1, | |
2055 | EVEX_W_0F7B_P_3, | |
2056 | EVEX_W_0F7E_P_1, | |
2057 | EVEX_W_0F7E_P_2, | |
2058 | EVEX_W_0F7F_P_1, | |
2059 | EVEX_W_0F7F_P_2, | |
2060 | EVEX_W_0FC2_P_0, | |
2061 | EVEX_W_0FC2_P_1, | |
2062 | EVEX_W_0FC2_P_2, | |
2063 | EVEX_W_0FC2_P_3, | |
2064 | EVEX_W_0FC6_P_0, | |
2065 | EVEX_W_0FC6_P_2, | |
2066 | EVEX_W_0FD2_P_2, | |
2067 | EVEX_W_0FD3_P_2, | |
2068 | EVEX_W_0FD4_P_2, | |
2069 | EVEX_W_0FD6_P_2, | |
2070 | EVEX_W_0FE6_P_1, | |
2071 | EVEX_W_0FE6_P_2, | |
2072 | EVEX_W_0FE6_P_3, | |
2073 | EVEX_W_0FE7_P_2, | |
2074 | EVEX_W_0FF2_P_2, | |
2075 | EVEX_W_0FF3_P_2, | |
2076 | EVEX_W_0FF4_P_2, | |
2077 | EVEX_W_0FFA_P_2, | |
2078 | EVEX_W_0FFB_P_2, | |
2079 | EVEX_W_0FFE_P_2, | |
2080 | EVEX_W_0F380C_P_2, | |
2081 | EVEX_W_0F380D_P_2, | |
2082 | EVEX_W_0F3811_P_1, | |
2083 | EVEX_W_0F3812_P_1, | |
2084 | EVEX_W_0F3813_P_1, | |
2085 | EVEX_W_0F3813_P_2, | |
2086 | EVEX_W_0F3814_P_1, | |
2087 | EVEX_W_0F3815_P_1, | |
2088 | EVEX_W_0F3818_P_2, | |
2089 | EVEX_W_0F3819_P_2, | |
2090 | EVEX_W_0F381A_P_2, | |
2091 | EVEX_W_0F381B_P_2, | |
2092 | EVEX_W_0F381E_P_2, | |
2093 | EVEX_W_0F381F_P_2, | |
2094 | EVEX_W_0F3821_P_1, | |
2095 | EVEX_W_0F3822_P_1, | |
2096 | EVEX_W_0F3823_P_1, | |
2097 | EVEX_W_0F3824_P_1, | |
2098 | EVEX_W_0F3825_P_1, | |
2099 | EVEX_W_0F3825_P_2, | |
2100 | EVEX_W_0F3828_P_2, | |
2101 | EVEX_W_0F3829_P_2, | |
2102 | EVEX_W_0F382A_P_1, | |
2103 | EVEX_W_0F382A_P_2, | |
2104 | EVEX_W_0F3831_P_1, | |
2105 | EVEX_W_0F3832_P_1, | |
2106 | EVEX_W_0F3833_P_1, | |
2107 | EVEX_W_0F3834_P_1, | |
2108 | EVEX_W_0F3835_P_1, | |
2109 | EVEX_W_0F3835_P_2, | |
2110 | EVEX_W_0F3837_P_2, | |
2111 | EVEX_W_0F383A_P_1, | |
2112 | EVEX_W_0F3840_P_2, | |
2113 | EVEX_W_0F3858_P_2, | |
2114 | EVEX_W_0F3859_P_2, | |
2115 | EVEX_W_0F385A_P_2, | |
2116 | EVEX_W_0F385B_P_2, | |
2117 | EVEX_W_0F3891_P_2, | |
2118 | EVEX_W_0F3893_P_2, | |
2119 | EVEX_W_0F38A1_P_2, | |
2120 | EVEX_W_0F38A3_P_2, | |
2121 | EVEX_W_0F38C7_R_1_P_2, | |
2122 | EVEX_W_0F38C7_R_2_P_2, | |
2123 | EVEX_W_0F38C7_R_5_P_2, | |
2124 | EVEX_W_0F38C7_R_6_P_2, | |
2125 | ||
2126 | EVEX_W_0F3A00_P_2, | |
2127 | EVEX_W_0F3A01_P_2, | |
2128 | EVEX_W_0F3A04_P_2, | |
2129 | EVEX_W_0F3A05_P_2, | |
2130 | EVEX_W_0F3A08_P_2, | |
2131 | EVEX_W_0F3A09_P_2, | |
2132 | EVEX_W_0F3A0A_P_2, | |
2133 | EVEX_W_0F3A0B_P_2, | |
2134 | EVEX_W_0F3A18_P_2, | |
2135 | EVEX_W_0F3A19_P_2, | |
2136 | EVEX_W_0F3A1A_P_2, | |
2137 | EVEX_W_0F3A1B_P_2, | |
2138 | EVEX_W_0F3A1D_P_2, | |
2139 | EVEX_W_0F3A21_P_2, | |
2140 | EVEX_W_0F3A23_P_2, | |
2141 | EVEX_W_0F3A38_P_2, | |
2142 | EVEX_W_0F3A39_P_2, | |
2143 | EVEX_W_0F3A3A_P_2, | |
2144 | EVEX_W_0F3A3B_P_2, | |
2145 | EVEX_W_0F3A43_P_2, | |
9e30b8e0 L |
2146 | }; |
2147 | ||
26ca5450 | 2148 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
2149 | |
2150 | struct dis386 { | |
2da11e11 | 2151 | const char *name; |
ce518a5f L |
2152 | struct |
2153 | { | |
2154 | op_rtn rtn; | |
2155 | int bytemode; | |
2156 | } op[MAX_OPERANDS]; | |
252b5132 RH |
2157 | }; |
2158 | ||
2159 | /* Upper case letters in the instruction names here are macros. | |
2160 | 'A' => print 'b' if no register operands or suffix_always is true | |
2161 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 2162 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 2163 | size prefix |
ed7841b3 | 2164 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 2165 | suffix_always is true |
252b5132 | 2166 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 2167 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 2168 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 2169 | 'H' => print ",pt" or ",pn" branch hint |
9306ca4a | 2170 | 'I' => honor following macro letter even in Intel mode (implemented only |
98b528ac | 2171 | for some of the macro letters) |
9306ca4a | 2172 | 'J' => print 'l' |
42903f7f | 2173 | 'K' => print 'd' or 'q' if rex prefix is present. |
252b5132 | 2174 | 'L' => print 'l' if suffix_always is true |
9d141669 | 2175 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 2176 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 2177 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
52b15da3 | 2178 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
98b528ac L |
2179 | or suffix_always is true. print 'q' if rex prefix is present. |
2180 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always | |
2181 | is true | |
a35ca55a | 2182 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 2183 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
6439fc28 AM |
2184 | 'T' => print 'q' in 64bit mode and behave as 'P' otherwise |
2185 | 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise | |
1a114b12 | 2186 | 'V' => print 'q' in 64bit mode and behave as 'S' otherwise |
a35ca55a | 2187 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 2188 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
8a72226a L |
2189 | 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and |
2190 | suffix_always is true. | |
6dd5059a | 2191 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
9d141669 | 2192 | '!' => change condition from true to false or from false to true. |
98b528ac L |
2193 | '%' => add 1 upper case letter to the macro. |
2194 | ||
2195 | 2 upper case letter macros: | |
c0f3af97 L |
2196 | "XY" => print 'x' or 'y' if no register operands or suffix_always |
2197 | is true. | |
4b06377f L |
2198 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
2199 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand | |
98b528ac | 2200 | or suffix_always is true |
4b06377f L |
2201 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
2202 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise | |
2203 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise | |
6c30d220 | 2204 | "LW" => print 'd', 'q' depending on the VEX.W bit |
52b15da3 | 2205 | |
6439fc28 AM |
2206 | Many of the above letters print nothing in Intel mode. See "putop" |
2207 | for the details. | |
52b15da3 | 2208 | |
6439fc28 | 2209 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 2210 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 2211 | |
6439fc28 | 2212 | static const struct dis386 dis386[] = { |
252b5132 | 2213 | /* 00 */ |
42164a71 L |
2214 | { "addB", { Ebh1, Gb } }, |
2215 | { "addS", { Evh1, Gv } }, | |
c7532693 L |
2216 | { "addB", { Gb, EbS } }, |
2217 | { "addS", { Gv, EvS } }, | |
ce518a5f L |
2218 | { "addB", { AL, Ib } }, |
2219 | { "addS", { eAX, Iv } }, | |
4e7d34a6 L |
2220 | { X86_64_TABLE (X86_64_06) }, |
2221 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 2222 | /* 08 */ |
42164a71 L |
2223 | { "orB", { Ebh1, Gb } }, |
2224 | { "orS", { Evh1, Gv } }, | |
c7532693 L |
2225 | { "orB", { Gb, EbS } }, |
2226 | { "orS", { Gv, EvS } }, | |
ce518a5f L |
2227 | { "orB", { AL, Ib } }, |
2228 | { "orS", { eAX, Iv } }, | |
4e7d34a6 | 2229 | { X86_64_TABLE (X86_64_0D) }, |
592d1631 | 2230 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
252b5132 | 2231 | /* 10 */ |
42164a71 L |
2232 | { "adcB", { Ebh1, Gb } }, |
2233 | { "adcS", { Evh1, Gv } }, | |
c7532693 L |
2234 | { "adcB", { Gb, EbS } }, |
2235 | { "adcS", { Gv, EvS } }, | |
ce518a5f L |
2236 | { "adcB", { AL, Ib } }, |
2237 | { "adcS", { eAX, Iv } }, | |
4e7d34a6 L |
2238 | { X86_64_TABLE (X86_64_16) }, |
2239 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 2240 | /* 18 */ |
42164a71 L |
2241 | { "sbbB", { Ebh1, Gb } }, |
2242 | { "sbbS", { Evh1, Gv } }, | |
c7532693 L |
2243 | { "sbbB", { Gb, EbS } }, |
2244 | { "sbbS", { Gv, EvS } }, | |
ce518a5f L |
2245 | { "sbbB", { AL, Ib } }, |
2246 | { "sbbS", { eAX, Iv } }, | |
4e7d34a6 L |
2247 | { X86_64_TABLE (X86_64_1E) }, |
2248 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 2249 | /* 20 */ |
42164a71 L |
2250 | { "andB", { Ebh1, Gb } }, |
2251 | { "andS", { Evh1, Gv } }, | |
c7532693 L |
2252 | { "andB", { Gb, EbS } }, |
2253 | { "andS", { Gv, EvS } }, | |
ce518a5f L |
2254 | { "andB", { AL, Ib } }, |
2255 | { "andS", { eAX, Iv } }, | |
592d1631 | 2256 | { Bad_Opcode }, /* SEG ES prefix */ |
4e7d34a6 | 2257 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 2258 | /* 28 */ |
42164a71 L |
2259 | { "subB", { Ebh1, Gb } }, |
2260 | { "subS", { Evh1, Gv } }, | |
c7532693 L |
2261 | { "subB", { Gb, EbS } }, |
2262 | { "subS", { Gv, EvS } }, | |
ce518a5f L |
2263 | { "subB", { AL, Ib } }, |
2264 | { "subS", { eAX, Iv } }, | |
592d1631 | 2265 | { Bad_Opcode }, /* SEG CS prefix */ |
4e7d34a6 | 2266 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 2267 | /* 30 */ |
42164a71 L |
2268 | { "xorB", { Ebh1, Gb } }, |
2269 | { "xorS", { Evh1, Gv } }, | |
c7532693 L |
2270 | { "xorB", { Gb, EbS } }, |
2271 | { "xorS", { Gv, EvS } }, | |
ce518a5f L |
2272 | { "xorB", { AL, Ib } }, |
2273 | { "xorS", { eAX, Iv } }, | |
592d1631 | 2274 | { Bad_Opcode }, /* SEG SS prefix */ |
4e7d34a6 | 2275 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 2276 | /* 38 */ |
ce518a5f L |
2277 | { "cmpB", { Eb, Gb } }, |
2278 | { "cmpS", { Ev, Gv } }, | |
c7532693 L |
2279 | { "cmpB", { Gb, EbS } }, |
2280 | { "cmpS", { Gv, EvS } }, | |
ce518a5f L |
2281 | { "cmpB", { AL, Ib } }, |
2282 | { "cmpS", { eAX, Iv } }, | |
592d1631 | 2283 | { Bad_Opcode }, /* SEG DS prefix */ |
4e7d34a6 | 2284 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 2285 | /* 40 */ |
ce518a5f L |
2286 | { "inc{S|}", { RMeAX } }, |
2287 | { "inc{S|}", { RMeCX } }, | |
2288 | { "inc{S|}", { RMeDX } }, | |
2289 | { "inc{S|}", { RMeBX } }, | |
2290 | { "inc{S|}", { RMeSP } }, | |
2291 | { "inc{S|}", { RMeBP } }, | |
2292 | { "inc{S|}", { RMeSI } }, | |
2293 | { "inc{S|}", { RMeDI } }, | |
252b5132 | 2294 | /* 48 */ |
ce518a5f L |
2295 | { "dec{S|}", { RMeAX } }, |
2296 | { "dec{S|}", { RMeCX } }, | |
2297 | { "dec{S|}", { RMeDX } }, | |
2298 | { "dec{S|}", { RMeBX } }, | |
2299 | { "dec{S|}", { RMeSP } }, | |
2300 | { "dec{S|}", { RMeBP } }, | |
2301 | { "dec{S|}", { RMeSI } }, | |
2302 | { "dec{S|}", { RMeDI } }, | |
252b5132 | 2303 | /* 50 */ |
ce518a5f L |
2304 | { "pushV", { RMrAX } }, |
2305 | { "pushV", { RMrCX } }, | |
2306 | { "pushV", { RMrDX } }, | |
2307 | { "pushV", { RMrBX } }, | |
2308 | { "pushV", { RMrSP } }, | |
2309 | { "pushV", { RMrBP } }, | |
2310 | { "pushV", { RMrSI } }, | |
2311 | { "pushV", { RMrDI } }, | |
252b5132 | 2312 | /* 58 */ |
ce518a5f L |
2313 | { "popV", { RMrAX } }, |
2314 | { "popV", { RMrCX } }, | |
2315 | { "popV", { RMrDX } }, | |
2316 | { "popV", { RMrBX } }, | |
2317 | { "popV", { RMrSP } }, | |
2318 | { "popV", { RMrBP } }, | |
2319 | { "popV", { RMrSI } }, | |
2320 | { "popV", { RMrDI } }, | |
252b5132 | 2321 | /* 60 */ |
4e7d34a6 L |
2322 | { X86_64_TABLE (X86_64_60) }, |
2323 | { X86_64_TABLE (X86_64_61) }, | |
2324 | { X86_64_TABLE (X86_64_62) }, | |
2325 | { X86_64_TABLE (X86_64_63) }, | |
592d1631 L |
2326 | { Bad_Opcode }, /* seg fs */ |
2327 | { Bad_Opcode }, /* seg gs */ | |
2328 | { Bad_Opcode }, /* op size prefix */ | |
2329 | { Bad_Opcode }, /* adr size prefix */ | |
252b5132 | 2330 | /* 68 */ |
d9e3625e | 2331 | { "pushT", { sIv } }, |
ce518a5f | 2332 | { "imulS", { Gv, Ev, Iv } }, |
e3949f17 | 2333 | { "pushT", { sIbT } }, |
ce518a5f | 2334 | { "imulS", { Gv, Ev, sIb } }, |
7c52e0e8 | 2335 | { "ins{b|}", { Ybr, indirDX } }, |
4e7d34a6 | 2336 | { X86_64_TABLE (X86_64_6D) }, |
7c52e0e8 | 2337 | { "outs{b|}", { indirDXr, Xb } }, |
4e7d34a6 | 2338 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 2339 | /* 70 */ |
7e8b059b L |
2340 | { "joH", { Jb, BND, cond_jump_flag } }, |
2341 | { "jnoH", { Jb, BND, cond_jump_flag } }, | |
2342 | { "jbH", { Jb, BND, cond_jump_flag } }, | |
2343 | { "jaeH", { Jb, BND, cond_jump_flag } }, | |
2344 | { "jeH", { Jb, BND, cond_jump_flag } }, | |
2345 | { "jneH", { Jb, BND, cond_jump_flag } }, | |
2346 | { "jbeH", { Jb, BND, cond_jump_flag } }, | |
2347 | { "jaH", { Jb, BND, cond_jump_flag } }, | |
252b5132 | 2348 | /* 78 */ |
7e8b059b L |
2349 | { "jsH", { Jb, BND, cond_jump_flag } }, |
2350 | { "jnsH", { Jb, BND, cond_jump_flag } }, | |
2351 | { "jpH", { Jb, BND, cond_jump_flag } }, | |
2352 | { "jnpH", { Jb, BND, cond_jump_flag } }, | |
2353 | { "jlH", { Jb, BND, cond_jump_flag } }, | |
2354 | { "jgeH", { Jb, BND, cond_jump_flag } }, | |
2355 | { "jleH", { Jb, BND, cond_jump_flag } }, | |
2356 | { "jgH", { Jb, BND, cond_jump_flag } }, | |
252b5132 | 2357 | /* 80 */ |
1ceb70f8 L |
2358 | { REG_TABLE (REG_80) }, |
2359 | { REG_TABLE (REG_81) }, | |
592d1631 | 2360 | { Bad_Opcode }, |
1ceb70f8 | 2361 | { REG_TABLE (REG_82) }, |
ce518a5f L |
2362 | { "testB", { Eb, Gb } }, |
2363 | { "testS", { Ev, Gv } }, | |
42164a71 L |
2364 | { "xchgB", { Ebh2, Gb } }, |
2365 | { "xchgS", { Evh2, Gv } }, | |
252b5132 | 2366 | /* 88 */ |
42164a71 L |
2367 | { "movB", { Ebh3, Gb } }, |
2368 | { "movS", { Evh3, Gv } }, | |
b6169b20 L |
2369 | { "movB", { Gb, EbS } }, |
2370 | { "movS", { Gv, EvS } }, | |
ce518a5f | 2371 | { "movD", { Sv, Sw } }, |
1ceb70f8 | 2372 | { MOD_TABLE (MOD_8D) }, |
ce518a5f | 2373 | { "movD", { Sw, Sv } }, |
1ceb70f8 | 2374 | { REG_TABLE (REG_8F) }, |
252b5132 | 2375 | /* 90 */ |
1ceb70f8 | 2376 | { PREFIX_TABLE (PREFIX_90) }, |
ce518a5f L |
2377 | { "xchgS", { RMeCX, eAX } }, |
2378 | { "xchgS", { RMeDX, eAX } }, | |
2379 | { "xchgS", { RMeBX, eAX } }, | |
2380 | { "xchgS", { RMeSP, eAX } }, | |
2381 | { "xchgS", { RMeBP, eAX } }, | |
2382 | { "xchgS", { RMeSI, eAX } }, | |
2383 | { "xchgS", { RMeDI, eAX } }, | |
252b5132 | 2384 | /* 98 */ |
7c52e0e8 L |
2385 | { "cW{t|}R", { XX } }, |
2386 | { "cR{t|}O", { XX } }, | |
4e7d34a6 | 2387 | { X86_64_TABLE (X86_64_9A) }, |
592d1631 | 2388 | { Bad_Opcode }, /* fwait */ |
ce518a5f L |
2389 | { "pushfT", { XX } }, |
2390 | { "popfT", { XX } }, | |
7c52e0e8 L |
2391 | { "sahf", { XX } }, |
2392 | { "lahf", { XX } }, | |
252b5132 | 2393 | /* a0 */ |
4b06377f L |
2394 | { "mov%LB", { AL, Ob } }, |
2395 | { "mov%LS", { eAX, Ov } }, | |
2396 | { "mov%LB", { Ob, AL } }, | |
2397 | { "mov%LS", { Ov, eAX } }, | |
7c52e0e8 L |
2398 | { "movs{b|}", { Ybr, Xb } }, |
2399 | { "movs{R|}", { Yvr, Xv } }, | |
2400 | { "cmps{b|}", { Xb, Yb } }, | |
2401 | { "cmps{R|}", { Xv, Yv } }, | |
252b5132 | 2402 | /* a8 */ |
ce518a5f L |
2403 | { "testB", { AL, Ib } }, |
2404 | { "testS", { eAX, Iv } }, | |
2405 | { "stosB", { Ybr, AL } }, | |
2406 | { "stosS", { Yvr, eAX } }, | |
2407 | { "lodsB", { ALr, Xb } }, | |
2408 | { "lodsS", { eAXr, Xv } }, | |
2409 | { "scasB", { AL, Yb } }, | |
2410 | { "scasS", { eAX, Yv } }, | |
252b5132 | 2411 | /* b0 */ |
ce518a5f L |
2412 | { "movB", { RMAL, Ib } }, |
2413 | { "movB", { RMCL, Ib } }, | |
2414 | { "movB", { RMDL, Ib } }, | |
2415 | { "movB", { RMBL, Ib } }, | |
2416 | { "movB", { RMAH, Ib } }, | |
2417 | { "movB", { RMCH, Ib } }, | |
2418 | { "movB", { RMDH, Ib } }, | |
2419 | { "movB", { RMBH, Ib } }, | |
252b5132 | 2420 | /* b8 */ |
4b06377f L |
2421 | { "mov%LV", { RMeAX, Iv64 } }, |
2422 | { "mov%LV", { RMeCX, Iv64 } }, | |
2423 | { "mov%LV", { RMeDX, Iv64 } }, | |
2424 | { "mov%LV", { RMeBX, Iv64 } }, | |
2425 | { "mov%LV", { RMeSP, Iv64 } }, | |
2426 | { "mov%LV", { RMeBP, Iv64 } }, | |
2427 | { "mov%LV", { RMeSI, Iv64 } }, | |
2428 | { "mov%LV", { RMeDI, Iv64 } }, | |
252b5132 | 2429 | /* c0 */ |
1ceb70f8 L |
2430 | { REG_TABLE (REG_C0) }, |
2431 | { REG_TABLE (REG_C1) }, | |
7e8b059b L |
2432 | { "retT", { Iw, BND } }, |
2433 | { "retT", { BND } }, | |
4e7d34a6 L |
2434 | { X86_64_TABLE (X86_64_C4) }, |
2435 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
2436 | { REG_TABLE (REG_C6) }, |
2437 | { REG_TABLE (REG_C7) }, | |
252b5132 | 2438 | /* c8 */ |
ce518a5f L |
2439 | { "enterT", { Iw, Ib } }, |
2440 | { "leaveT", { XX } }, | |
ddab3d59 JB |
2441 | { "Jret{|f}P", { Iw } }, |
2442 | { "Jret{|f}P", { XX } }, | |
ce518a5f L |
2443 | { "int3", { XX } }, |
2444 | { "int", { Ib } }, | |
4e7d34a6 | 2445 | { X86_64_TABLE (X86_64_CE) }, |
ce518a5f | 2446 | { "iretP", { XX } }, |
252b5132 | 2447 | /* d0 */ |
1ceb70f8 L |
2448 | { REG_TABLE (REG_D0) }, |
2449 | { REG_TABLE (REG_D1) }, | |
2450 | { REG_TABLE (REG_D2) }, | |
2451 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
2452 | { X86_64_TABLE (X86_64_D4) }, |
2453 | { X86_64_TABLE (X86_64_D5) }, | |
592d1631 | 2454 | { Bad_Opcode }, |
ce518a5f | 2455 | { "xlat", { DSBX } }, |
252b5132 RH |
2456 | /* d8 */ |
2457 | { FLOAT }, | |
2458 | { FLOAT }, | |
2459 | { FLOAT }, | |
2460 | { FLOAT }, | |
2461 | { FLOAT }, | |
2462 | { FLOAT }, | |
2463 | { FLOAT }, | |
2464 | { FLOAT }, | |
2465 | /* e0 */ | |
ce518a5f L |
2466 | { "loopneFH", { Jb, XX, loop_jcxz_flag } }, |
2467 | { "loopeFH", { Jb, XX, loop_jcxz_flag } }, | |
2468 | { "loopFH", { Jb, XX, loop_jcxz_flag } }, | |
2469 | { "jEcxzH", { Jb, XX, loop_jcxz_flag } }, | |
2470 | { "inB", { AL, Ib } }, | |
2471 | { "inG", { zAX, Ib } }, | |
2472 | { "outB", { Ib, AL } }, | |
2473 | { "outG", { Ib, zAX } }, | |
252b5132 | 2474 | /* e8 */ |
7e8b059b L |
2475 | { "callT", { Jv, BND } }, |
2476 | { "jmpT", { Jv, BND } }, | |
4e7d34a6 | 2477 | { X86_64_TABLE (X86_64_EA) }, |
7e8b059b | 2478 | { "jmp", { Jb, BND } }, |
ce518a5f L |
2479 | { "inB", { AL, indirDX } }, |
2480 | { "inG", { zAX, indirDX } }, | |
2481 | { "outB", { indirDX, AL } }, | |
2482 | { "outG", { indirDX, zAX } }, | |
252b5132 | 2483 | /* f0 */ |
592d1631 | 2484 | { Bad_Opcode }, /* lock prefix */ |
ce518a5f | 2485 | { "icebp", { XX } }, |
592d1631 L |
2486 | { Bad_Opcode }, /* repne */ |
2487 | { Bad_Opcode }, /* repz */ | |
ce518a5f L |
2488 | { "hlt", { XX } }, |
2489 | { "cmc", { XX } }, | |
1ceb70f8 L |
2490 | { REG_TABLE (REG_F6) }, |
2491 | { REG_TABLE (REG_F7) }, | |
252b5132 | 2492 | /* f8 */ |
ce518a5f L |
2493 | { "clc", { XX } }, |
2494 | { "stc", { XX } }, | |
2495 | { "cli", { XX } }, | |
2496 | { "sti", { XX } }, | |
2497 | { "cld", { XX } }, | |
2498 | { "std", { XX } }, | |
1ceb70f8 L |
2499 | { REG_TABLE (REG_FE) }, |
2500 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
2501 | }; |
2502 | ||
6439fc28 | 2503 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 2504 | /* 00 */ |
1ceb70f8 L |
2505 | { REG_TABLE (REG_0F00 ) }, |
2506 | { REG_TABLE (REG_0F01 ) }, | |
ce518a5f L |
2507 | { "larS", { Gv, Ew } }, |
2508 | { "lslS", { Gv, Ew } }, | |
592d1631 | 2509 | { Bad_Opcode }, |
ce518a5f L |
2510 | { "syscall", { XX } }, |
2511 | { "clts", { XX } }, | |
2512 | { "sysretP", { XX } }, | |
252b5132 | 2513 | /* 08 */ |
ce518a5f L |
2514 | { "invd", { XX } }, |
2515 | { "wbinvd", { XX } }, | |
592d1631 | 2516 | { Bad_Opcode }, |
b414985b | 2517 | { "ud2", { XX } }, |
592d1631 | 2518 | { Bad_Opcode }, |
b5b1fc4f | 2519 | { REG_TABLE (REG_0F0D) }, |
ce518a5f L |
2520 | { "femms", { XX } }, |
2521 | { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */ | |
252b5132 | 2522 | /* 10 */ |
1ceb70f8 L |
2523 | { PREFIX_TABLE (PREFIX_0F10) }, |
2524 | { PREFIX_TABLE (PREFIX_0F11) }, | |
2525 | { PREFIX_TABLE (PREFIX_0F12) }, | |
2526 | { MOD_TABLE (MOD_0F13) }, | |
f2a421c4 L |
2527 | { "unpcklpX", { XM, EXx } }, |
2528 | { "unpckhpX", { XM, EXx } }, | |
1ceb70f8 L |
2529 | { PREFIX_TABLE (PREFIX_0F16) }, |
2530 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 2531 | /* 18 */ |
1ceb70f8 | 2532 | { REG_TABLE (REG_0F18) }, |
b5b1fc4f | 2533 | { "nopQ", { Ev } }, |
7e8b059b L |
2534 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2535 | { PREFIX_TABLE (PREFIX_0F1B) }, | |
b5b1fc4f L |
2536 | { "nopQ", { Ev } }, |
2537 | { "nopQ", { Ev } }, | |
2538 | { "nopQ", { Ev } }, | |
ce518a5f | 2539 | { "nopQ", { Ev } }, |
252b5132 | 2540 | /* 20 */ |
1ceb70f8 L |
2541 | { MOD_TABLE (MOD_0F20) }, |
2542 | { MOD_TABLE (MOD_0F21) }, | |
2543 | { MOD_TABLE (MOD_0F22) }, | |
2544 | { MOD_TABLE (MOD_0F23) }, | |
2545 | { MOD_TABLE (MOD_0F24) }, | |
592d1631 | 2546 | { Bad_Opcode }, |
1ceb70f8 | 2547 | { MOD_TABLE (MOD_0F26) }, |
592d1631 | 2548 | { Bad_Opcode }, |
252b5132 | 2549 | /* 28 */ |
09a2c6cf | 2550 | { "movapX", { XM, EXx } }, |
b6169b20 | 2551 | { "movapX", { EXxS, XM } }, |
1ceb70f8 L |
2552 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2553 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
2554 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
2555 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
2556 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
2557 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 2558 | /* 30 */ |
ce518a5f L |
2559 | { "wrmsr", { XX } }, |
2560 | { "rdtsc", { XX } }, | |
2561 | { "rdmsr", { XX } }, | |
2562 | { "rdpmc", { XX } }, | |
2563 | { "sysenter", { XX } }, | |
2564 | { "sysexit", { XX } }, | |
592d1631 | 2565 | { Bad_Opcode }, |
47dd174c | 2566 | { "getsec", { XX } }, |
252b5132 | 2567 | /* 38 */ |
4e7d34a6 | 2568 | { THREE_BYTE_TABLE (THREE_BYTE_0F38) }, |
592d1631 | 2569 | { Bad_Opcode }, |
4e7d34a6 | 2570 | { THREE_BYTE_TABLE (THREE_BYTE_0F3A) }, |
592d1631 L |
2571 | { Bad_Opcode }, |
2572 | { Bad_Opcode }, | |
2573 | { Bad_Opcode }, | |
2574 | { Bad_Opcode }, | |
2575 | { Bad_Opcode }, | |
252b5132 | 2576 | /* 40 */ |
b19d5385 JB |
2577 | { "cmovoS", { Gv, Ev } }, |
2578 | { "cmovnoS", { Gv, Ev } }, | |
2579 | { "cmovbS", { Gv, Ev } }, | |
2580 | { "cmovaeS", { Gv, Ev } }, | |
2581 | { "cmoveS", { Gv, Ev } }, | |
2582 | { "cmovneS", { Gv, Ev } }, | |
2583 | { "cmovbeS", { Gv, Ev } }, | |
2584 | { "cmovaS", { Gv, Ev } }, | |
252b5132 | 2585 | /* 48 */ |
b19d5385 JB |
2586 | { "cmovsS", { Gv, Ev } }, |
2587 | { "cmovnsS", { Gv, Ev } }, | |
2588 | { "cmovpS", { Gv, Ev } }, | |
2589 | { "cmovnpS", { Gv, Ev } }, | |
2590 | { "cmovlS", { Gv, Ev } }, | |
2591 | { "cmovgeS", { Gv, Ev } }, | |
2592 | { "cmovleS", { Gv, Ev } }, | |
2593 | { "cmovgS", { Gv, Ev } }, | |
252b5132 | 2594 | /* 50 */ |
75c135a8 | 2595 | { MOD_TABLE (MOD_0F51) }, |
1ceb70f8 L |
2596 | { PREFIX_TABLE (PREFIX_0F51) }, |
2597 | { PREFIX_TABLE (PREFIX_0F52) }, | |
2598 | { PREFIX_TABLE (PREFIX_0F53) }, | |
09a2c6cf L |
2599 | { "andpX", { XM, EXx } }, |
2600 | { "andnpX", { XM, EXx } }, | |
2601 | { "orpX", { XM, EXx } }, | |
2602 | { "xorpX", { XM, EXx } }, | |
252b5132 | 2603 | /* 58 */ |
1ceb70f8 L |
2604 | { PREFIX_TABLE (PREFIX_0F58) }, |
2605 | { PREFIX_TABLE (PREFIX_0F59) }, | |
2606 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
2607 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
2608 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
2609 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
2610 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
2611 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 2612 | /* 60 */ |
1ceb70f8 L |
2613 | { PREFIX_TABLE (PREFIX_0F60) }, |
2614 | { PREFIX_TABLE (PREFIX_0F61) }, | |
2615 | { PREFIX_TABLE (PREFIX_0F62) }, | |
ce518a5f L |
2616 | { "packsswb", { MX, EM } }, |
2617 | { "pcmpgtb", { MX, EM } }, | |
2618 | { "pcmpgtw", { MX, EM } }, | |
2619 | { "pcmpgtd", { MX, EM } }, | |
2620 | { "packuswb", { MX, EM } }, | |
252b5132 | 2621 | /* 68 */ |
ce518a5f L |
2622 | { "punpckhbw", { MX, EM } }, |
2623 | { "punpckhwd", { MX, EM } }, | |
2624 | { "punpckhdq", { MX, EM } }, | |
2625 | { "packssdw", { MX, EM } }, | |
1ceb70f8 L |
2626 | { PREFIX_TABLE (PREFIX_0F6C) }, |
2627 | { PREFIX_TABLE (PREFIX_0F6D) }, | |
231af070 | 2628 | { "movK", { MX, Edq } }, |
1ceb70f8 | 2629 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 2630 | /* 70 */ |
1ceb70f8 L |
2631 | { PREFIX_TABLE (PREFIX_0F70) }, |
2632 | { REG_TABLE (REG_0F71) }, | |
2633 | { REG_TABLE (REG_0F72) }, | |
2634 | { REG_TABLE (REG_0F73) }, | |
ce518a5f L |
2635 | { "pcmpeqb", { MX, EM } }, |
2636 | { "pcmpeqw", { MX, EM } }, | |
2637 | { "pcmpeqd", { MX, EM } }, | |
2638 | { "emms", { XX } }, | |
252b5132 | 2639 | /* 78 */ |
1ceb70f8 L |
2640 | { PREFIX_TABLE (PREFIX_0F78) }, |
2641 | { PREFIX_TABLE (PREFIX_0F79) }, | |
4e7d34a6 | 2642 | { THREE_BYTE_TABLE (THREE_BYTE_0F7A) }, |
592d1631 | 2643 | { Bad_Opcode }, |
1ceb70f8 L |
2644 | { PREFIX_TABLE (PREFIX_0F7C) }, |
2645 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
2646 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
2647 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 2648 | /* 80 */ |
7e8b059b L |
2649 | { "joH", { Jv, BND, cond_jump_flag } }, |
2650 | { "jnoH", { Jv, BND, cond_jump_flag } }, | |
2651 | { "jbH", { Jv, BND, cond_jump_flag } }, | |
2652 | { "jaeH", { Jv, BND, cond_jump_flag } }, | |
2653 | { "jeH", { Jv, BND, cond_jump_flag } }, | |
2654 | { "jneH", { Jv, BND, cond_jump_flag } }, | |
2655 | { "jbeH", { Jv, BND, cond_jump_flag } }, | |
2656 | { "jaH", { Jv, BND, cond_jump_flag } }, | |
252b5132 | 2657 | /* 88 */ |
7e8b059b L |
2658 | { "jsH", { Jv, BND, cond_jump_flag } }, |
2659 | { "jnsH", { Jv, BND, cond_jump_flag } }, | |
2660 | { "jpH", { Jv, BND, cond_jump_flag } }, | |
2661 | { "jnpH", { Jv, BND, cond_jump_flag } }, | |
2662 | { "jlH", { Jv, BND, cond_jump_flag } }, | |
2663 | { "jgeH", { Jv, BND, cond_jump_flag } }, | |
2664 | { "jleH", { Jv, BND, cond_jump_flag } }, | |
2665 | { "jgH", { Jv, BND, cond_jump_flag } }, | |
252b5132 | 2666 | /* 90 */ |
ce518a5f L |
2667 | { "seto", { Eb } }, |
2668 | { "setno", { Eb } }, | |
2669 | { "setb", { Eb } }, | |
2670 | { "setae", { Eb } }, | |
2671 | { "sete", { Eb } }, | |
2672 | { "setne", { Eb } }, | |
2673 | { "setbe", { Eb } }, | |
2674 | { "seta", { Eb } }, | |
252b5132 | 2675 | /* 98 */ |
ce518a5f L |
2676 | { "sets", { Eb } }, |
2677 | { "setns", { Eb } }, | |
2678 | { "setp", { Eb } }, | |
2679 | { "setnp", { Eb } }, | |
2680 | { "setl", { Eb } }, | |
2681 | { "setge", { Eb } }, | |
2682 | { "setle", { Eb } }, | |
2683 | { "setg", { Eb } }, | |
252b5132 | 2684 | /* a0 */ |
ce518a5f L |
2685 | { "pushT", { fs } }, |
2686 | { "popT", { fs } }, | |
2687 | { "cpuid", { XX } }, | |
2688 | { "btS", { Ev, Gv } }, | |
2689 | { "shldS", { Ev, Gv, Ib } }, | |
2690 | { "shldS", { Ev, Gv, CL } }, | |
1ceb70f8 L |
2691 | { REG_TABLE (REG_0FA6) }, |
2692 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 2693 | /* a8 */ |
ce518a5f L |
2694 | { "pushT", { gs } }, |
2695 | { "popT", { gs } }, | |
2696 | { "rsm", { XX } }, | |
42164a71 | 2697 | { "btsS", { Evh1, Gv } }, |
ce518a5f L |
2698 | { "shrdS", { Ev, Gv, Ib } }, |
2699 | { "shrdS", { Ev, Gv, CL } }, | |
1ceb70f8 | 2700 | { REG_TABLE (REG_0FAE) }, |
ce518a5f | 2701 | { "imulS", { Gv, Ev } }, |
252b5132 | 2702 | /* b0 */ |
42164a71 L |
2703 | { "cmpxchgB", { Ebh1, Gb } }, |
2704 | { "cmpxchgS", { Evh1, Gv } }, | |
1ceb70f8 | 2705 | { MOD_TABLE (MOD_0FB2) }, |
42164a71 | 2706 | { "btrS", { Evh1, Gv } }, |
1ceb70f8 L |
2707 | { MOD_TABLE (MOD_0FB4) }, |
2708 | { MOD_TABLE (MOD_0FB5) }, | |
7c52e0e8 L |
2709 | { "movz{bR|x}", { Gv, Eb } }, |
2710 | { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */ | |
252b5132 | 2711 | /* b8 */ |
1ceb70f8 | 2712 | { PREFIX_TABLE (PREFIX_0FB8) }, |
b414985b | 2713 | { "ud1", { XX } }, |
1ceb70f8 | 2714 | { REG_TABLE (REG_0FBA) }, |
42164a71 | 2715 | { "btcS", { Evh1, Gv } }, |
f12dc422 | 2716 | { PREFIX_TABLE (PREFIX_0FBC) }, |
1ceb70f8 | 2717 | { PREFIX_TABLE (PREFIX_0FBD) }, |
7c52e0e8 L |
2718 | { "movs{bR|x}", { Gv, Eb } }, |
2719 | { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */ | |
252b5132 | 2720 | /* c0 */ |
42164a71 L |
2721 | { "xaddB", { Ebh1, Gb } }, |
2722 | { "xaddS", { Evh1, Gv } }, | |
1ceb70f8 | 2723 | { PREFIX_TABLE (PREFIX_0FC2) }, |
4ee52178 | 2724 | { PREFIX_TABLE (PREFIX_0FC3) }, |
ce518a5f L |
2725 | { "pinsrw", { MX, Edqw, Ib } }, |
2726 | { "pextrw", { Gdq, MS, Ib } }, | |
09a2c6cf | 2727 | { "shufpX", { XM, EXx, Ib } }, |
1ceb70f8 | 2728 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 2729 | /* c8 */ |
ce518a5f L |
2730 | { "bswap", { RMeAX } }, |
2731 | { "bswap", { RMeCX } }, | |
2732 | { "bswap", { RMeDX } }, | |
2733 | { "bswap", { RMeBX } }, | |
2734 | { "bswap", { RMeSP } }, | |
2735 | { "bswap", { RMeBP } }, | |
2736 | { "bswap", { RMeSI } }, | |
2737 | { "bswap", { RMeDI } }, | |
252b5132 | 2738 | /* d0 */ |
1ceb70f8 | 2739 | { PREFIX_TABLE (PREFIX_0FD0) }, |
ce518a5f L |
2740 | { "psrlw", { MX, EM } }, |
2741 | { "psrld", { MX, EM } }, | |
2742 | { "psrlq", { MX, EM } }, | |
2743 | { "paddq", { MX, EM } }, | |
2744 | { "pmullw", { MX, EM } }, | |
1ceb70f8 | 2745 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 2746 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 2747 | /* d8 */ |
ce518a5f L |
2748 | { "psubusb", { MX, EM } }, |
2749 | { "psubusw", { MX, EM } }, | |
2750 | { "pminub", { MX, EM } }, | |
2751 | { "pand", { MX, EM } }, | |
2752 | { "paddusb", { MX, EM } }, | |
2753 | { "paddusw", { MX, EM } }, | |
2754 | { "pmaxub", { MX, EM } }, | |
2755 | { "pandn", { MX, EM } }, | |
252b5132 | 2756 | /* e0 */ |
ce518a5f L |
2757 | { "pavgb", { MX, EM } }, |
2758 | { "psraw", { MX, EM } }, | |
2759 | { "psrad", { MX, EM } }, | |
2760 | { "pavgw", { MX, EM } }, | |
2761 | { "pmulhuw", { MX, EM } }, | |
2762 | { "pmulhw", { MX, EM } }, | |
1ceb70f8 L |
2763 | { PREFIX_TABLE (PREFIX_0FE6) }, |
2764 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 2765 | /* e8 */ |
ce518a5f L |
2766 | { "psubsb", { MX, EM } }, |
2767 | { "psubsw", { MX, EM } }, | |
2768 | { "pminsw", { MX, EM } }, | |
2769 | { "por", { MX, EM } }, | |
2770 | { "paddsb", { MX, EM } }, | |
2771 | { "paddsw", { MX, EM } }, | |
2772 | { "pmaxsw", { MX, EM } }, | |
2773 | { "pxor", { MX, EM } }, | |
252b5132 | 2774 | /* f0 */ |
1ceb70f8 | 2775 | { PREFIX_TABLE (PREFIX_0FF0) }, |
ce518a5f L |
2776 | { "psllw", { MX, EM } }, |
2777 | { "pslld", { MX, EM } }, | |
2778 | { "psllq", { MX, EM } }, | |
2779 | { "pmuludq", { MX, EM } }, | |
2780 | { "pmaddwd", { MX, EM } }, | |
2781 | { "psadbw", { MX, EM } }, | |
1ceb70f8 | 2782 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 2783 | /* f8 */ |
ce518a5f L |
2784 | { "psubb", { MX, EM } }, |
2785 | { "psubw", { MX, EM } }, | |
2786 | { "psubd", { MX, EM } }, | |
2787 | { "psubq", { MX, EM } }, | |
2788 | { "paddb", { MX, EM } }, | |
2789 | { "paddw", { MX, EM } }, | |
2790 | { "paddd", { MX, EM } }, | |
592d1631 | 2791 | { Bad_Opcode }, |
252b5132 RH |
2792 | }; |
2793 | ||
2794 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
2795 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2796 | /* ------------------------------- */ | |
2797 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
2798 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
2799 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
2800 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
2801 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
2802 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
2803 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
2804 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
2805 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
2806 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
2807 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
2808 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
2809 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
2810 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
2811 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
2812 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
2813 | /* ------------------------------- */ | |
2814 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
2815 | }; |
2816 | ||
2817 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
2818 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2819 | /* ------------------------------- */ | |
252b5132 | 2820 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 2821 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 2822 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 2823 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 2824 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
2825 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
2826 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 2827 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
2828 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
2829 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 2830 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
050dfa73 | 2831 | /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ |
252b5132 | 2832 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 2833 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 2834 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
ca164297 | 2835 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ |
c608c12e AM |
2836 | /* ------------------------------- */ |
2837 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
2838 | }; | |
2839 | ||
252b5132 RH |
2840 | static char obuf[100]; |
2841 | static char *obufp; | |
ea397f5b | 2842 | static char *mnemonicendp; |
252b5132 RH |
2843 | static char scratchbuf[100]; |
2844 | static unsigned char *start_codep; | |
2845 | static unsigned char *insn_codep; | |
2846 | static unsigned char *codep; | |
f16cd0d5 L |
2847 | static int last_lock_prefix; |
2848 | static int last_repz_prefix; | |
2849 | static int last_repnz_prefix; | |
2850 | static int last_data_prefix; | |
2851 | static int last_addr_prefix; | |
2852 | static int last_rex_prefix; | |
2853 | static int last_seg_prefix; | |
2854 | #define MAX_CODE_LENGTH 15 | |
2855 | /* We can up to 14 prefixes since the maximum instruction length is | |
2856 | 15bytes. */ | |
2857 | static int all_prefixes[MAX_CODE_LENGTH - 1]; | |
252b5132 | 2858 | static disassemble_info *the_info; |
7967e09e L |
2859 | static struct |
2860 | { | |
2861 | int mod; | |
7967e09e | 2862 | int reg; |
484c222e | 2863 | int rm; |
7967e09e L |
2864 | } |
2865 | modrm; | |
4bba6815 | 2866 | static unsigned char need_modrm; |
dfc8cf43 L |
2867 | static struct |
2868 | { | |
2869 | int scale; | |
2870 | int index; | |
2871 | int base; | |
2872 | } | |
2873 | sib; | |
c0f3af97 L |
2874 | static struct |
2875 | { | |
2876 | int register_specifier; | |
2877 | int length; | |
2878 | int prefix; | |
2879 | int w; | |
43234a1e L |
2880 | int evex; |
2881 | int r; | |
2882 | int v; | |
2883 | int mask_register_specifier; | |
2884 | int zeroing; | |
2885 | int ll; | |
2886 | int b; | |
c0f3af97 L |
2887 | } |
2888 | vex; | |
2889 | static unsigned char need_vex; | |
2890 | static unsigned char need_vex_reg; | |
dae39acc | 2891 | static unsigned char vex_w_done; |
252b5132 | 2892 | |
ea397f5b L |
2893 | struct op |
2894 | { | |
2895 | const char *name; | |
2896 | unsigned int len; | |
2897 | }; | |
2898 | ||
4bba6815 AM |
2899 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
2900 | values are stale. Hitting this abort likely indicates that you | |
2901 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
2902 | #define MODRM_CHECK if (!need_modrm) abort () | |
2903 | ||
d708bcba AM |
2904 | static const char **names64; |
2905 | static const char **names32; | |
2906 | static const char **names16; | |
2907 | static const char **names8; | |
2908 | static const char **names8rex; | |
2909 | static const char **names_seg; | |
db51cc60 L |
2910 | static const char *index64; |
2911 | static const char *index32; | |
d708bcba | 2912 | static const char **index16; |
7e8b059b | 2913 | static const char **names_bnd; |
d708bcba AM |
2914 | |
2915 | static const char *intel_names64[] = { | |
2916 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
2917 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
2918 | }; | |
2919 | static const char *intel_names32[] = { | |
2920 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
2921 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
2922 | }; | |
2923 | static const char *intel_names16[] = { | |
2924 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
2925 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
2926 | }; | |
2927 | static const char *intel_names8[] = { | |
2928 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
2929 | }; | |
2930 | static const char *intel_names8rex[] = { | |
2931 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
2932 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
2933 | }; | |
2934 | static const char *intel_names_seg[] = { | |
2935 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
2936 | }; | |
db51cc60 L |
2937 | static const char *intel_index64 = "riz"; |
2938 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
2939 | static const char *intel_index16[] = { |
2940 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
2941 | }; | |
2942 | ||
2943 | static const char *att_names64[] = { | |
2944 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
2945 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
2946 | }; | |
d708bcba AM |
2947 | static const char *att_names32[] = { |
2948 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 2949 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 2950 | }; |
d708bcba AM |
2951 | static const char *att_names16[] = { |
2952 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 2953 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 2954 | }; |
d708bcba AM |
2955 | static const char *att_names8[] = { |
2956 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 2957 | }; |
d708bcba AM |
2958 | static const char *att_names8rex[] = { |
2959 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
2960 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
2961 | }; | |
d708bcba AM |
2962 | static const char *att_names_seg[] = { |
2963 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 2964 | }; |
db51cc60 L |
2965 | static const char *att_index64 = "%riz"; |
2966 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
2967 | static const char *att_index16[] = { |
2968 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
2969 | }; |
2970 | ||
b9733481 L |
2971 | static const char **names_mm; |
2972 | static const char *intel_names_mm[] = { | |
2973 | "mm0", "mm1", "mm2", "mm3", | |
2974 | "mm4", "mm5", "mm6", "mm7" | |
2975 | }; | |
2976 | static const char *att_names_mm[] = { | |
2977 | "%mm0", "%mm1", "%mm2", "%mm3", | |
2978 | "%mm4", "%mm5", "%mm6", "%mm7" | |
2979 | }; | |
2980 | ||
7e8b059b L |
2981 | static const char *intel_names_bnd[] = { |
2982 | "bnd0", "bnd1", "bnd2", "bnd3" | |
2983 | }; | |
2984 | ||
2985 | static const char *att_names_bnd[] = { | |
2986 | "%bnd0", "%bnd1", "%bnd2", "%bnd3" | |
2987 | }; | |
2988 | ||
b9733481 L |
2989 | static const char **names_xmm; |
2990 | static const char *intel_names_xmm[] = { | |
2991 | "xmm0", "xmm1", "xmm2", "xmm3", | |
2992 | "xmm4", "xmm5", "xmm6", "xmm7", | |
2993 | "xmm8", "xmm9", "xmm10", "xmm11", | |
43234a1e L |
2994 | "xmm12", "xmm13", "xmm14", "xmm15", |
2995 | "xmm16", "xmm17", "xmm18", "xmm19", | |
2996 | "xmm20", "xmm21", "xmm22", "xmm23", | |
2997 | "xmm24", "xmm25", "xmm26", "xmm27", | |
2998 | "xmm28", "xmm29", "xmm30", "xmm31" | |
b9733481 L |
2999 | }; |
3000 | static const char *att_names_xmm[] = { | |
3001 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", | |
3002 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", | |
3003 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", | |
43234a1e L |
3004 | "%xmm12", "%xmm13", "%xmm14", "%xmm15", |
3005 | "%xmm16", "%xmm17", "%xmm18", "%xmm19", | |
3006 | "%xmm20", "%xmm21", "%xmm22", "%xmm23", | |
3007 | "%xmm24", "%xmm25", "%xmm26", "%xmm27", | |
3008 | "%xmm28", "%xmm29", "%xmm30", "%xmm31" | |
b9733481 L |
3009 | }; |
3010 | ||
3011 | static const char **names_ymm; | |
3012 | static const char *intel_names_ymm[] = { | |
3013 | "ymm0", "ymm1", "ymm2", "ymm3", | |
3014 | "ymm4", "ymm5", "ymm6", "ymm7", | |
3015 | "ymm8", "ymm9", "ymm10", "ymm11", | |
43234a1e L |
3016 | "ymm12", "ymm13", "ymm14", "ymm15", |
3017 | "ymm16", "ymm17", "ymm18", "ymm19", | |
3018 | "ymm20", "ymm21", "ymm22", "ymm23", | |
3019 | "ymm24", "ymm25", "ymm26", "ymm27", | |
3020 | "ymm28", "ymm29", "ymm30", "ymm31" | |
b9733481 L |
3021 | }; |
3022 | static const char *att_names_ymm[] = { | |
3023 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", | |
3024 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", | |
3025 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", | |
43234a1e L |
3026 | "%ymm12", "%ymm13", "%ymm14", "%ymm15", |
3027 | "%ymm16", "%ymm17", "%ymm18", "%ymm19", | |
3028 | "%ymm20", "%ymm21", "%ymm22", "%ymm23", | |
3029 | "%ymm24", "%ymm25", "%ymm26", "%ymm27", | |
3030 | "%ymm28", "%ymm29", "%ymm30", "%ymm31" | |
3031 | }; | |
3032 | ||
3033 | static const char **names_zmm; | |
3034 | static const char *intel_names_zmm[] = { | |
3035 | "zmm0", "zmm1", "zmm2", "zmm3", | |
3036 | "zmm4", "zmm5", "zmm6", "zmm7", | |
3037 | "zmm8", "zmm9", "zmm10", "zmm11", | |
3038 | "zmm12", "zmm13", "zmm14", "zmm15", | |
3039 | "zmm16", "zmm17", "zmm18", "zmm19", | |
3040 | "zmm20", "zmm21", "zmm22", "zmm23", | |
3041 | "zmm24", "zmm25", "zmm26", "zmm27", | |
3042 | "zmm28", "zmm29", "zmm30", "zmm31" | |
3043 | }; | |
3044 | static const char *att_names_zmm[] = { | |
3045 | "%zmm0", "%zmm1", "%zmm2", "%zmm3", | |
3046 | "%zmm4", "%zmm5", "%zmm6", "%zmm7", | |
3047 | "%zmm8", "%zmm9", "%zmm10", "%zmm11", | |
3048 | "%zmm12", "%zmm13", "%zmm14", "%zmm15", | |
3049 | "%zmm16", "%zmm17", "%zmm18", "%zmm19", | |
3050 | "%zmm20", "%zmm21", "%zmm22", "%zmm23", | |
3051 | "%zmm24", "%zmm25", "%zmm26", "%zmm27", | |
3052 | "%zmm28", "%zmm29", "%zmm30", "%zmm31" | |
3053 | }; | |
3054 | ||
3055 | static const char **names_mask; | |
3056 | static const char *intel_names_mask[] = { | |
3057 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" | |
3058 | }; | |
3059 | static const char *att_names_mask[] = { | |
3060 | "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" | |
3061 | }; | |
3062 | ||
3063 | static const char *names_rounding[] = | |
3064 | { | |
3065 | "{rn-sae}", | |
3066 | "{rd-sae}", | |
3067 | "{ru-sae}", | |
3068 | "{rz-sae}" | |
b9733481 L |
3069 | }; |
3070 | ||
1ceb70f8 L |
3071 | static const struct dis386 reg_table[][8] = { |
3072 | /* REG_80 */ | |
252b5132 | 3073 | { |
42164a71 L |
3074 | { "addA", { Ebh1, Ib } }, |
3075 | { "orA", { Ebh1, Ib } }, | |
3076 | { "adcA", { Ebh1, Ib } }, | |
3077 | { "sbbA", { Ebh1, Ib } }, | |
3078 | { "andA", { Ebh1, Ib } }, | |
3079 | { "subA", { Ebh1, Ib } }, | |
3080 | { "xorA", { Ebh1, Ib } }, | |
ce518a5f | 3081 | { "cmpA", { Eb, Ib } }, |
252b5132 | 3082 | }, |
1ceb70f8 | 3083 | /* REG_81 */ |
252b5132 | 3084 | { |
42164a71 L |
3085 | { "addQ", { Evh1, Iv } }, |
3086 | { "orQ", { Evh1, Iv } }, | |
3087 | { "adcQ", { Evh1, Iv } }, | |
3088 | { "sbbQ", { Evh1, Iv } }, | |
3089 | { "andQ", { Evh1, Iv } }, | |
3090 | { "subQ", { Evh1, Iv } }, | |
3091 | { "xorQ", { Evh1, Iv } }, | |
ce518a5f | 3092 | { "cmpQ", { Ev, Iv } }, |
252b5132 | 3093 | }, |
1ceb70f8 | 3094 | /* REG_82 */ |
252b5132 | 3095 | { |
42164a71 L |
3096 | { "addQ", { Evh1, sIb } }, |
3097 | { "orQ", { Evh1, sIb } }, | |
3098 | { "adcQ", { Evh1, sIb } }, | |
3099 | { "sbbQ", { Evh1, sIb } }, | |
3100 | { "andQ", { Evh1, sIb } }, | |
3101 | { "subQ", { Evh1, sIb } }, | |
3102 | { "xorQ", { Evh1, sIb } }, | |
ce518a5f | 3103 | { "cmpQ", { Ev, sIb } }, |
252b5132 | 3104 | }, |
1ceb70f8 | 3105 | /* REG_8F */ |
4e7d34a6 L |
3106 | { |
3107 | { "popU", { stackEv } }, | |
c48244a5 | 3108 | { XOP_8F_TABLE (XOP_09) }, |
592d1631 L |
3109 | { Bad_Opcode }, |
3110 | { Bad_Opcode }, | |
3111 | { Bad_Opcode }, | |
f88c9eb0 | 3112 | { XOP_8F_TABLE (XOP_09) }, |
4e7d34a6 | 3113 | }, |
1ceb70f8 | 3114 | /* REG_C0 */ |
252b5132 | 3115 | { |
ce518a5f L |
3116 | { "rolA", { Eb, Ib } }, |
3117 | { "rorA", { Eb, Ib } }, | |
3118 | { "rclA", { Eb, Ib } }, | |
3119 | { "rcrA", { Eb, Ib } }, | |
3120 | { "shlA", { Eb, Ib } }, | |
3121 | { "shrA", { Eb, Ib } }, | |
592d1631 | 3122 | { Bad_Opcode }, |
ce518a5f | 3123 | { "sarA", { Eb, Ib } }, |
252b5132 | 3124 | }, |
1ceb70f8 | 3125 | /* REG_C1 */ |
252b5132 | 3126 | { |
ce518a5f L |
3127 | { "rolQ", { Ev, Ib } }, |
3128 | { "rorQ", { Ev, Ib } }, | |
3129 | { "rclQ", { Ev, Ib } }, | |
3130 | { "rcrQ", { Ev, Ib } }, | |
3131 | { "shlQ", { Ev, Ib } }, | |
3132 | { "shrQ", { Ev, Ib } }, | |
592d1631 | 3133 | { Bad_Opcode }, |
ce518a5f | 3134 | { "sarQ", { Ev, Ib } }, |
252b5132 | 3135 | }, |
1ceb70f8 | 3136 | /* REG_C6 */ |
4e7d34a6 | 3137 | { |
42164a71 L |
3138 | { "movA", { Ebh3, Ib } }, |
3139 | { Bad_Opcode }, | |
3140 | { Bad_Opcode }, | |
3141 | { Bad_Opcode }, | |
3142 | { Bad_Opcode }, | |
3143 | { Bad_Opcode }, | |
3144 | { Bad_Opcode }, | |
3145 | { MOD_TABLE (MOD_C6_REG_7) }, | |
4e7d34a6 | 3146 | }, |
1ceb70f8 | 3147 | /* REG_C7 */ |
4e7d34a6 | 3148 | { |
42164a71 L |
3149 | { "movQ", { Evh3, Iv } }, |
3150 | { Bad_Opcode }, | |
3151 | { Bad_Opcode }, | |
3152 | { Bad_Opcode }, | |
3153 | { Bad_Opcode }, | |
3154 | { Bad_Opcode }, | |
3155 | { Bad_Opcode }, | |
3156 | { MOD_TABLE (MOD_C7_REG_7) }, | |
4e7d34a6 | 3157 | }, |
1ceb70f8 | 3158 | /* REG_D0 */ |
252b5132 | 3159 | { |
ce518a5f L |
3160 | { "rolA", { Eb, I1 } }, |
3161 | { "rorA", { Eb, I1 } }, | |
3162 | { "rclA", { Eb, I1 } }, | |
3163 | { "rcrA", { Eb, I1 } }, | |
3164 | { "shlA", { Eb, I1 } }, | |
3165 | { "shrA", { Eb, I1 } }, | |
592d1631 | 3166 | { Bad_Opcode }, |
ce518a5f | 3167 | { "sarA", { Eb, I1 } }, |
252b5132 | 3168 | }, |
1ceb70f8 | 3169 | /* REG_D1 */ |
252b5132 | 3170 | { |
ce518a5f L |
3171 | { "rolQ", { Ev, I1 } }, |
3172 | { "rorQ", { Ev, I1 } }, | |
3173 | { "rclQ", { Ev, I1 } }, | |
3174 | { "rcrQ", { Ev, I1 } }, | |
3175 | { "shlQ", { Ev, I1 } }, | |
3176 | { "shrQ", { Ev, I1 } }, | |
592d1631 | 3177 | { Bad_Opcode }, |
ce518a5f | 3178 | { "sarQ", { Ev, I1 } }, |
252b5132 | 3179 | }, |
1ceb70f8 | 3180 | /* REG_D2 */ |
252b5132 | 3181 | { |
ce518a5f L |
3182 | { "rolA", { Eb, CL } }, |
3183 | { "rorA", { Eb, CL } }, | |
3184 | { "rclA", { Eb, CL } }, | |
3185 | { "rcrA", { Eb, CL } }, | |
3186 | { "shlA", { Eb, CL } }, | |
3187 | { "shrA", { Eb, CL } }, | |
592d1631 | 3188 | { Bad_Opcode }, |
ce518a5f | 3189 | { "sarA", { Eb, CL } }, |
252b5132 | 3190 | }, |
1ceb70f8 | 3191 | /* REG_D3 */ |
252b5132 | 3192 | { |
ce518a5f L |
3193 | { "rolQ", { Ev, CL } }, |
3194 | { "rorQ", { Ev, CL } }, | |
3195 | { "rclQ", { Ev, CL } }, | |
3196 | { "rcrQ", { Ev, CL } }, | |
3197 | { "shlQ", { Ev, CL } }, | |
3198 | { "shrQ", { Ev, CL } }, | |
592d1631 | 3199 | { Bad_Opcode }, |
ce518a5f | 3200 | { "sarQ", { Ev, CL } }, |
252b5132 | 3201 | }, |
1ceb70f8 | 3202 | /* REG_F6 */ |
252b5132 | 3203 | { |
ce518a5f | 3204 | { "testA", { Eb, Ib } }, |
592d1631 | 3205 | { Bad_Opcode }, |
42164a71 L |
3206 | { "notA", { Ebh1 } }, |
3207 | { "negA", { Ebh1 } }, | |
ce518a5f L |
3208 | { "mulA", { Eb } }, /* Don't print the implicit %al register, */ |
3209 | { "imulA", { Eb } }, /* to distinguish these opcodes from other */ | |
3210 | { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */ | |
3211 | { "idivA", { Eb } }, /* and idiv for consistency. */ | |
252b5132 | 3212 | }, |
1ceb70f8 | 3213 | /* REG_F7 */ |
252b5132 | 3214 | { |
ce518a5f | 3215 | { "testQ", { Ev, Iv } }, |
592d1631 | 3216 | { Bad_Opcode }, |
42164a71 L |
3217 | { "notQ", { Evh1 } }, |
3218 | { "negQ", { Evh1 } }, | |
ce518a5f L |
3219 | { "mulQ", { Ev } }, /* Don't print the implicit register. */ |
3220 | { "imulQ", { Ev } }, | |
3221 | { "divQ", { Ev } }, | |
3222 | { "idivQ", { Ev } }, | |
252b5132 | 3223 | }, |
1ceb70f8 | 3224 | /* REG_FE */ |
252b5132 | 3225 | { |
42164a71 L |
3226 | { "incA", { Ebh1 } }, |
3227 | { "decA", { Ebh1 } }, | |
252b5132 | 3228 | }, |
1ceb70f8 | 3229 | /* REG_FF */ |
252b5132 | 3230 | { |
42164a71 L |
3231 | { "incQ", { Evh1 } }, |
3232 | { "decQ", { Evh1 } }, | |
7e8b059b | 3233 | { "call{T|}", { indirEv, BND } }, |
4a357820 | 3234 | { MOD_TABLE (MOD_FF_REG_3) }, |
7e8b059b | 3235 | { "jmp{T|}", { indirEv, BND } }, |
4a357820 | 3236 | { MOD_TABLE (MOD_FF_REG_5) }, |
ce518a5f | 3237 | { "pushU", { stackEv } }, |
592d1631 | 3238 | { Bad_Opcode }, |
252b5132 | 3239 | }, |
1ceb70f8 | 3240 | /* REG_0F00 */ |
252b5132 | 3241 | { |
ce518a5f L |
3242 | { "sldtD", { Sv } }, |
3243 | { "strD", { Sv } }, | |
3244 | { "lldt", { Ew } }, | |
3245 | { "ltr", { Ew } }, | |
3246 | { "verr", { Ew } }, | |
3247 | { "verw", { Ew } }, | |
592d1631 L |
3248 | { Bad_Opcode }, |
3249 | { Bad_Opcode }, | |
252b5132 | 3250 | }, |
1ceb70f8 | 3251 | /* REG_0F01 */ |
252b5132 | 3252 | { |
1ceb70f8 L |
3253 | { MOD_TABLE (MOD_0F01_REG_0) }, |
3254 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
3255 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
3256 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
ce518a5f | 3257 | { "smswD", { Sv } }, |
592d1631 | 3258 | { Bad_Opcode }, |
ce518a5f | 3259 | { "lmsw", { Ew } }, |
1ceb70f8 | 3260 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 3261 | }, |
b5b1fc4f | 3262 | /* REG_0F0D */ |
252b5132 | 3263 | { |
1ab03f4b L |
3264 | { "prefetch", { Mb } }, |
3265 | { "prefetchw", { Mb } }, | |
43234a1e | 3266 | { "prefetchwt1", { Mb } }, |
d7189fa5 RM |
3267 | { "prefetch", { Mb } }, |
3268 | { "prefetch", { Mb } }, | |
3269 | { "prefetch", { Mb } }, | |
3270 | { "prefetch", { Mb } }, | |
3271 | { "prefetch", { Mb } }, | |
252b5132 | 3272 | }, |
1ceb70f8 | 3273 | /* REG_0F18 */ |
252b5132 | 3274 | { |
1ceb70f8 L |
3275 | { MOD_TABLE (MOD_0F18_REG_0) }, |
3276 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
3277 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
3278 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
d7189fa5 RM |
3279 | { MOD_TABLE (MOD_0F18_REG_4) }, |
3280 | { MOD_TABLE (MOD_0F18_REG_5) }, | |
3281 | { MOD_TABLE (MOD_0F18_REG_6) }, | |
3282 | { MOD_TABLE (MOD_0F18_REG_7) }, | |
252b5132 | 3283 | }, |
1ceb70f8 | 3284 | /* REG_0F71 */ |
a6bd098c | 3285 | { |
592d1631 L |
3286 | { Bad_Opcode }, |
3287 | { Bad_Opcode }, | |
1ceb70f8 | 3288 | { MOD_TABLE (MOD_0F71_REG_2) }, |
592d1631 | 3289 | { Bad_Opcode }, |
1ceb70f8 | 3290 | { MOD_TABLE (MOD_0F71_REG_4) }, |
592d1631 | 3291 | { Bad_Opcode }, |
1ceb70f8 | 3292 | { MOD_TABLE (MOD_0F71_REG_6) }, |
a6bd098c | 3293 | }, |
1ceb70f8 | 3294 | /* REG_0F72 */ |
a6bd098c | 3295 | { |
592d1631 L |
3296 | { Bad_Opcode }, |
3297 | { Bad_Opcode }, | |
1ceb70f8 | 3298 | { MOD_TABLE (MOD_0F72_REG_2) }, |
592d1631 | 3299 | { Bad_Opcode }, |
1ceb70f8 | 3300 | { MOD_TABLE (MOD_0F72_REG_4) }, |
592d1631 | 3301 | { Bad_Opcode }, |
1ceb70f8 | 3302 | { MOD_TABLE (MOD_0F72_REG_6) }, |
a6bd098c | 3303 | }, |
1ceb70f8 | 3304 | /* REG_0F73 */ |
252b5132 | 3305 | { |
592d1631 L |
3306 | { Bad_Opcode }, |
3307 | { Bad_Opcode }, | |
1ceb70f8 L |
3308 | { MOD_TABLE (MOD_0F73_REG_2) }, |
3309 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
592d1631 L |
3310 | { Bad_Opcode }, |
3311 | { Bad_Opcode }, | |
1ceb70f8 L |
3312 | { MOD_TABLE (MOD_0F73_REG_6) }, |
3313 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 3314 | }, |
1ceb70f8 | 3315 | /* REG_0FA6 */ |
252b5132 | 3316 | { |
4e7d34a6 L |
3317 | { "montmul", { { OP_0f07, 0 } } }, |
3318 | { "xsha1", { { OP_0f07, 0 } } }, | |
3319 | { "xsha256", { { OP_0f07, 0 } } }, | |
4e7d34a6 | 3320 | }, |
1ceb70f8 | 3321 | /* REG_0FA7 */ |
4e7d34a6 L |
3322 | { |
3323 | { "xstore-rng", { { OP_0f07, 0 } } }, | |
3324 | { "xcrypt-ecb", { { OP_0f07, 0 } } }, | |
3325 | { "xcrypt-cbc", { { OP_0f07, 0 } } }, | |
3326 | { "xcrypt-ctr", { { OP_0f07, 0 } } }, | |
3327 | { "xcrypt-cfb", { { OP_0f07, 0 } } }, | |
3328 | { "xcrypt-ofb", { { OP_0f07, 0 } } }, | |
4e7d34a6 | 3329 | }, |
1ceb70f8 | 3330 | /* REG_0FAE */ |
4e7d34a6 | 3331 | { |
1ceb70f8 L |
3332 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
3333 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
3334 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
3335 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 3336 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
3337 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
3338 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
3339 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 3340 | }, |
1ceb70f8 | 3341 | /* REG_0FBA */ |
252b5132 | 3342 | { |
592d1631 L |
3343 | { Bad_Opcode }, |
3344 | { Bad_Opcode }, | |
3345 | { Bad_Opcode }, | |
3346 | { Bad_Opcode }, | |
4e7d34a6 | 3347 | { "btQ", { Ev, Ib } }, |
42164a71 L |
3348 | { "btsQ", { Evh1, Ib } }, |
3349 | { "btrQ", { Evh1, Ib } }, | |
3350 | { "btcQ", { Evh1, Ib } }, | |
c608c12e | 3351 | }, |
1ceb70f8 | 3352 | /* REG_0FC7 */ |
c608c12e | 3353 | { |
592d1631 | 3354 | { Bad_Opcode }, |
4e7d34a6 | 3355 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } }, |
592d1631 L |
3356 | { Bad_Opcode }, |
3357 | { Bad_Opcode }, | |
3358 | { Bad_Opcode }, | |
3359 | { Bad_Opcode }, | |
1ceb70f8 L |
3360 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
3361 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 3362 | }, |
592a252b | 3363 | /* REG_VEX_0F71 */ |
c0f3af97 | 3364 | { |
592d1631 L |
3365 | { Bad_Opcode }, |
3366 | { Bad_Opcode }, | |
592a252b | 3367 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
592d1631 | 3368 | { Bad_Opcode }, |
592a252b | 3369 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
592d1631 | 3370 | { Bad_Opcode }, |
592a252b | 3371 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
c0f3af97 | 3372 | }, |
592a252b | 3373 | /* REG_VEX_0F72 */ |
c0f3af97 | 3374 | { |
592d1631 L |
3375 | { Bad_Opcode }, |
3376 | { Bad_Opcode }, | |
592a252b | 3377 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
592d1631 | 3378 | { Bad_Opcode }, |
592a252b | 3379 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
592d1631 | 3380 | { Bad_Opcode }, |
592a252b | 3381 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
c0f3af97 | 3382 | }, |
592a252b | 3383 | /* REG_VEX_0F73 */ |
c0f3af97 | 3384 | { |
592d1631 L |
3385 | { Bad_Opcode }, |
3386 | { Bad_Opcode }, | |
592a252b L |
3387 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
3388 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, | |
592d1631 L |
3389 | { Bad_Opcode }, |
3390 | { Bad_Opcode }, | |
592a252b L |
3391 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
3392 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, | |
c0f3af97 | 3393 | }, |
592a252b | 3394 | /* REG_VEX_0FAE */ |
c0f3af97 | 3395 | { |
592d1631 L |
3396 | { Bad_Opcode }, |
3397 | { Bad_Opcode }, | |
592a252b L |
3398 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
3399 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, | |
c0f3af97 | 3400 | }, |
f12dc422 L |
3401 | /* REG_VEX_0F38F3 */ |
3402 | { | |
3403 | { Bad_Opcode }, | |
3404 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, | |
3405 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, | |
3406 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, | |
3407 | }, | |
f88c9eb0 SP |
3408 | /* REG_XOP_LWPCB */ |
3409 | { | |
3410 | { "llwpcb", { { OP_LWPCB_E, 0 } } }, | |
3411 | { "slwpcb", { { OP_LWPCB_E, 0 } } }, | |
f88c9eb0 SP |
3412 | }, |
3413 | /* REG_XOP_LWP */ | |
3414 | { | |
ce7d077e SP |
3415 | { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } }, |
3416 | { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } }, | |
f88c9eb0 | 3417 | }, |
2a2a0f38 QN |
3418 | /* REG_XOP_TBM_01 */ |
3419 | { | |
3420 | { Bad_Opcode }, | |
3421 | { "blcfill", { { OP_LWP_E, 0 }, Ev } }, | |
3422 | { "blsfill", { { OP_LWP_E, 0 }, Ev } }, | |
3423 | { "blcs", { { OP_LWP_E, 0 }, Ev } }, | |
3424 | { "tzmsk", { { OP_LWP_E, 0 }, Ev } }, | |
3425 | { "blcic", { { OP_LWP_E, 0 }, Ev } }, | |
3426 | { "blsic", { { OP_LWP_E, 0 }, Ev } }, | |
3427 | { "t1mskc", { { OP_LWP_E, 0 }, Ev } }, | |
3428 | }, | |
3429 | /* REG_XOP_TBM_02 */ | |
3430 | { | |
3431 | { Bad_Opcode }, | |
3432 | { "blcmsk", { { OP_LWP_E, 0 }, Ev } }, | |
3433 | { Bad_Opcode }, | |
3434 | { Bad_Opcode }, | |
3435 | { Bad_Opcode }, | |
3436 | { Bad_Opcode }, | |
3437 | { "blci", { { OP_LWP_E, 0 }, Ev } }, | |
3438 | }, | |
43234a1e L |
3439 | #define NEED_REG_TABLE |
3440 | #include "i386-dis-evex.h" | |
3441 | #undef NEED_REG_TABLE | |
4e7d34a6 L |
3442 | }; |
3443 | ||
1ceb70f8 L |
3444 | static const struct dis386 prefix_table[][4] = { |
3445 | /* PREFIX_90 */ | |
252b5132 | 3446 | { |
4e7d34a6 L |
3447 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, |
3448 | { "pause", { XX } }, | |
3449 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, | |
0f10071e | 3450 | }, |
4e7d34a6 | 3451 | |
1ceb70f8 | 3452 | /* PREFIX_0F10 */ |
cc0ec051 | 3453 | { |
4e7d34a6 L |
3454 | { "movups", { XM, EXx } }, |
3455 | { "movss", { XM, EXd } }, | |
3456 | { "movupd", { XM, EXx } }, | |
3457 | { "movsd", { XM, EXq } }, | |
30d1c836 | 3458 | }, |
4e7d34a6 | 3459 | |
1ceb70f8 | 3460 | /* PREFIX_0F11 */ |
30d1c836 | 3461 | { |
b6169b20 | 3462 | { "movups", { EXxS, XM } }, |
fa99fab2 | 3463 | { "movss", { EXdS, XM } }, |
b6169b20 | 3464 | { "movupd", { EXxS, XM } }, |
fa99fab2 | 3465 | { "movsd", { EXqS, XM } }, |
4e7d34a6 | 3466 | }, |
252b5132 | 3467 | |
1ceb70f8 | 3468 | /* PREFIX_0F12 */ |
c608c12e | 3469 | { |
1ceb70f8 | 3470 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
4e7d34a6 L |
3471 | { "movsldup", { XM, EXx } }, |
3472 | { "movlpd", { XM, EXq } }, | |
3473 | { "movddup", { XM, EXq } }, | |
c608c12e | 3474 | }, |
4e7d34a6 | 3475 | |
1ceb70f8 | 3476 | /* PREFIX_0F16 */ |
c608c12e | 3477 | { |
1ceb70f8 | 3478 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
4e7d34a6 L |
3479 | { "movshdup", { XM, EXx } }, |
3480 | { "movhpd", { XM, EXq } }, | |
c608c12e | 3481 | }, |
4e7d34a6 | 3482 | |
7e8b059b L |
3483 | /* PREFIX_0F1A */ |
3484 | { | |
3485 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, | |
3486 | { "bndcl", { Gbnd, Ev_bnd } }, | |
3487 | { "bndmov", { Gbnd, Ebnd } }, | |
3488 | { "bndcu", { Gbnd, Ev_bnd } }, | |
3489 | }, | |
3490 | ||
3491 | /* PREFIX_0F1B */ | |
3492 | { | |
3493 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, | |
3494 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, | |
3495 | { "bndmov", { Ebnd, Gbnd } }, | |
3496 | { "bndcn", { Gbnd, Ev_bnd } }, | |
3497 | }, | |
3498 | ||
1ceb70f8 | 3499 | /* PREFIX_0F2A */ |
c608c12e | 3500 | { |
09335d05 | 3501 | { "cvtpi2ps", { XM, EMCq } }, |
98b528ac | 3502 | { "cvtsi2ss%LQ", { XM, Ev } }, |
09335d05 | 3503 | { "cvtpi2pd", { XM, EMCq } }, |
98b528ac | 3504 | { "cvtsi2sd%LQ", { XM, Ev } }, |
c608c12e | 3505 | }, |
4e7d34a6 | 3506 | |
1ceb70f8 | 3507 | /* PREFIX_0F2B */ |
c608c12e | 3508 | { |
75c135a8 L |
3509 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
3510 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
3511 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
3512 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 3513 | }, |
4e7d34a6 | 3514 | |
1ceb70f8 | 3515 | /* PREFIX_0F2C */ |
c608c12e | 3516 | { |
09335d05 L |
3517 | { "cvttps2pi", { MXC, EXq } }, |
3518 | { "cvttss2siY", { Gv, EXd } }, | |
09a2c6cf | 3519 | { "cvttpd2pi", { MXC, EXx } }, |
09335d05 | 3520 | { "cvttsd2siY", { Gv, EXq } }, |
c608c12e | 3521 | }, |
4e7d34a6 | 3522 | |
1ceb70f8 | 3523 | /* PREFIX_0F2D */ |
c608c12e | 3524 | { |
4e7d34a6 L |
3525 | { "cvtps2pi", { MXC, EXq } }, |
3526 | { "cvtss2siY", { Gv, EXd } }, | |
3527 | { "cvtpd2pi", { MXC, EXx } }, | |
3528 | { "cvtsd2siY", { Gv, EXq } }, | |
c608c12e | 3529 | }, |
4e7d34a6 | 3530 | |
1ceb70f8 | 3531 | /* PREFIX_0F2E */ |
c608c12e | 3532 | { |
7bb15c6f | 3533 | { "ucomiss",{ XM, EXd } }, |
592d1631 | 3534 | { Bad_Opcode }, |
7bb15c6f | 3535 | { "ucomisd",{ XM, EXq } }, |
c608c12e | 3536 | }, |
4e7d34a6 | 3537 | |
1ceb70f8 | 3538 | /* PREFIX_0F2F */ |
c608c12e | 3539 | { |
4e7d34a6 | 3540 | { "comiss", { XM, EXd } }, |
592d1631 | 3541 | { Bad_Opcode }, |
4e7d34a6 | 3542 | { "comisd", { XM, EXq } }, |
c608c12e | 3543 | }, |
4e7d34a6 | 3544 | |
1ceb70f8 | 3545 | /* PREFIX_0F51 */ |
c608c12e | 3546 | { |
4e7d34a6 L |
3547 | { "sqrtps", { XM, EXx } }, |
3548 | { "sqrtss", { XM, EXd } }, | |
3549 | { "sqrtpd", { XM, EXx } }, | |
3550 | { "sqrtsd", { XM, EXq } }, | |
c608c12e | 3551 | }, |
4e7d34a6 | 3552 | |
1ceb70f8 | 3553 | /* PREFIX_0F52 */ |
c608c12e | 3554 | { |
4e7d34a6 L |
3555 | { "rsqrtps",{ XM, EXx } }, |
3556 | { "rsqrtss",{ XM, EXd } }, | |
c608c12e | 3557 | }, |
4e7d34a6 | 3558 | |
1ceb70f8 | 3559 | /* PREFIX_0F53 */ |
c608c12e | 3560 | { |
4e7d34a6 L |
3561 | { "rcpps", { XM, EXx } }, |
3562 | { "rcpss", { XM, EXd } }, | |
c608c12e | 3563 | }, |
4e7d34a6 | 3564 | |
1ceb70f8 | 3565 | /* PREFIX_0F58 */ |
c608c12e | 3566 | { |
4e7d34a6 L |
3567 | { "addps", { XM, EXx } }, |
3568 | { "addss", { XM, EXd } }, | |
3569 | { "addpd", { XM, EXx } }, | |
3570 | { "addsd", { XM, EXq } }, | |
c608c12e | 3571 | }, |
4e7d34a6 | 3572 | |
1ceb70f8 | 3573 | /* PREFIX_0F59 */ |
c608c12e | 3574 | { |
4e7d34a6 L |
3575 | { "mulps", { XM, EXx } }, |
3576 | { "mulss", { XM, EXd } }, | |
3577 | { "mulpd", { XM, EXx } }, | |
3578 | { "mulsd", { XM, EXq } }, | |
041bd2e0 | 3579 | }, |
4e7d34a6 | 3580 | |
1ceb70f8 | 3581 | /* PREFIX_0F5A */ |
041bd2e0 | 3582 | { |
4e7d34a6 L |
3583 | { "cvtps2pd", { XM, EXq } }, |
3584 | { "cvtss2sd", { XM, EXd } }, | |
3585 | { "cvtpd2ps", { XM, EXx } }, | |
3586 | { "cvtsd2ss", { XM, EXq } }, | |
041bd2e0 | 3587 | }, |
4e7d34a6 | 3588 | |
1ceb70f8 | 3589 | /* PREFIX_0F5B */ |
041bd2e0 | 3590 | { |
09a2c6cf L |
3591 | { "cvtdq2ps", { XM, EXx } }, |
3592 | { "cvttps2dq", { XM, EXx } }, | |
3593 | { "cvtps2dq", { XM, EXx } }, | |
041bd2e0 | 3594 | }, |
4e7d34a6 | 3595 | |
1ceb70f8 | 3596 | /* PREFIX_0F5C */ |
041bd2e0 | 3597 | { |
4e7d34a6 L |
3598 | { "subps", { XM, EXx } }, |
3599 | { "subss", { XM, EXd } }, | |
3600 | { "subpd", { XM, EXx } }, | |
3601 | { "subsd", { XM, EXq } }, | |
041bd2e0 | 3602 | }, |
4e7d34a6 | 3603 | |
1ceb70f8 | 3604 | /* PREFIX_0F5D */ |
041bd2e0 | 3605 | { |
4e7d34a6 L |
3606 | { "minps", { XM, EXx } }, |
3607 | { "minss", { XM, EXd } }, | |
3608 | { "minpd", { XM, EXx } }, | |
3609 | { "minsd", { XM, EXq } }, | |
041bd2e0 | 3610 | }, |
4e7d34a6 | 3611 | |
1ceb70f8 | 3612 | /* PREFIX_0F5E */ |
041bd2e0 | 3613 | { |
4e7d34a6 L |
3614 | { "divps", { XM, EXx } }, |
3615 | { "divss", { XM, EXd } }, | |
3616 | { "divpd", { XM, EXx } }, | |
3617 | { "divsd", { XM, EXq } }, | |
041bd2e0 | 3618 | }, |
4e7d34a6 | 3619 | |
1ceb70f8 | 3620 | /* PREFIX_0F5F */ |
041bd2e0 | 3621 | { |
4e7d34a6 L |
3622 | { "maxps", { XM, EXx } }, |
3623 | { "maxss", { XM, EXd } }, | |
3624 | { "maxpd", { XM, EXx } }, | |
3625 | { "maxsd", { XM, EXq } }, | |
041bd2e0 | 3626 | }, |
4e7d34a6 | 3627 | |
1ceb70f8 | 3628 | /* PREFIX_0F60 */ |
041bd2e0 | 3629 | { |
4e7d34a6 | 3630 | { "punpcklbw",{ MX, EMd } }, |
592d1631 | 3631 | { Bad_Opcode }, |
4e7d34a6 | 3632 | { "punpcklbw",{ MX, EMx } }, |
041bd2e0 | 3633 | }, |
4e7d34a6 | 3634 | |
1ceb70f8 | 3635 | /* PREFIX_0F61 */ |
041bd2e0 | 3636 | { |
4e7d34a6 | 3637 | { "punpcklwd",{ MX, EMd } }, |
592d1631 | 3638 | { Bad_Opcode }, |
4e7d34a6 | 3639 | { "punpcklwd",{ MX, EMx } }, |
041bd2e0 | 3640 | }, |
4e7d34a6 | 3641 | |
1ceb70f8 | 3642 | /* PREFIX_0F62 */ |
041bd2e0 | 3643 | { |
4e7d34a6 | 3644 | { "punpckldq",{ MX, EMd } }, |
592d1631 | 3645 | { Bad_Opcode }, |
4e7d34a6 | 3646 | { "punpckldq",{ MX, EMx } }, |
041bd2e0 | 3647 | }, |
4e7d34a6 | 3648 | |
1ceb70f8 | 3649 | /* PREFIX_0F6C */ |
041bd2e0 | 3650 | { |
592d1631 L |
3651 | { Bad_Opcode }, |
3652 | { Bad_Opcode }, | |
4e7d34a6 | 3653 | { "punpcklqdq", { XM, EXx } }, |
0f17484f | 3654 | }, |
4e7d34a6 | 3655 | |
1ceb70f8 | 3656 | /* PREFIX_0F6D */ |
0f17484f | 3657 | { |
592d1631 L |
3658 | { Bad_Opcode }, |
3659 | { Bad_Opcode }, | |
4e7d34a6 | 3660 | { "punpckhqdq", { XM, EXx } }, |
041bd2e0 | 3661 | }, |
4e7d34a6 | 3662 | |
1ceb70f8 | 3663 | /* PREFIX_0F6F */ |
ca164297 | 3664 | { |
4e7d34a6 L |
3665 | { "movq", { MX, EM } }, |
3666 | { "movdqu", { XM, EXx } }, | |
3667 | { "movdqa", { XM, EXx } }, | |
ca164297 | 3668 | }, |
4e7d34a6 | 3669 | |
1ceb70f8 | 3670 | /* PREFIX_0F70 */ |
4e7d34a6 L |
3671 | { |
3672 | { "pshufw", { MX, EM, Ib } }, | |
3673 | { "pshufhw",{ XM, EXx, Ib } }, | |
3674 | { "pshufd", { XM, EXx, Ib } }, | |
3675 | { "pshuflw",{ XM, EXx, Ib } }, | |
3676 | }, | |
3677 | ||
92fddf8e L |
3678 | /* PREFIX_0F73_REG_3 */ |
3679 | { | |
592d1631 L |
3680 | { Bad_Opcode }, |
3681 | { Bad_Opcode }, | |
92fddf8e | 3682 | { "psrldq", { XS, Ib } }, |
92fddf8e L |
3683 | }, |
3684 | ||
3685 | /* PREFIX_0F73_REG_7 */ | |
3686 | { | |
592d1631 L |
3687 | { Bad_Opcode }, |
3688 | { Bad_Opcode }, | |
92fddf8e | 3689 | { "pslldq", { XS, Ib } }, |
92fddf8e L |
3690 | }, |
3691 | ||
1ceb70f8 | 3692 | /* PREFIX_0F78 */ |
4e7d34a6 L |
3693 | { |
3694 | {"vmread", { Em, Gm } }, | |
592d1631 | 3695 | { Bad_Opcode }, |
4e7d34a6 L |
3696 | {"extrq", { XS, Ib, Ib } }, |
3697 | {"insertq", { XM, XS, Ib, Ib } }, | |
3698 | }, | |
3699 | ||
1ceb70f8 | 3700 | /* PREFIX_0F79 */ |
4e7d34a6 L |
3701 | { |
3702 | {"vmwrite", { Gm, Em } }, | |
592d1631 | 3703 | { Bad_Opcode }, |
4e7d34a6 L |
3704 | {"extrq", { XM, XS } }, |
3705 | {"insertq", { XM, XS } }, | |
3706 | }, | |
3707 | ||
1ceb70f8 | 3708 | /* PREFIX_0F7C */ |
ca164297 | 3709 | { |
592d1631 L |
3710 | { Bad_Opcode }, |
3711 | { Bad_Opcode }, | |
09a2c6cf L |
3712 | { "haddpd", { XM, EXx } }, |
3713 | { "haddps", { XM, EXx } }, | |
ca164297 | 3714 | }, |
4e7d34a6 | 3715 | |
1ceb70f8 | 3716 | /* PREFIX_0F7D */ |
ca164297 | 3717 | { |
592d1631 L |
3718 | { Bad_Opcode }, |
3719 | { Bad_Opcode }, | |
09a2c6cf L |
3720 | { "hsubpd", { XM, EXx } }, |
3721 | { "hsubps", { XM, EXx } }, | |
ca164297 | 3722 | }, |
4e7d34a6 | 3723 | |
1ceb70f8 | 3724 | /* PREFIX_0F7E */ |
ca164297 | 3725 | { |
4e7d34a6 L |
3726 | { "movK", { Edq, MX } }, |
3727 | { "movq", { XM, EXq } }, | |
3728 | { "movK", { Edq, XM } }, | |
ca164297 | 3729 | }, |
4e7d34a6 | 3730 | |
1ceb70f8 | 3731 | /* PREFIX_0F7F */ |
ca164297 | 3732 | { |
b6169b20 L |
3733 | { "movq", { EMS, MX } }, |
3734 | { "movdqu", { EXxS, XM } }, | |
3735 | { "movdqa", { EXxS, XM } }, | |
ca164297 | 3736 | }, |
4e7d34a6 | 3737 | |
c7b8aa3a L |
3738 | /* PREFIX_0FAE_REG_0 */ |
3739 | { | |
3740 | { Bad_Opcode }, | |
3741 | { "rdfsbase", { Ev } }, | |
3742 | }, | |
3743 | ||
3744 | /* PREFIX_0FAE_REG_1 */ | |
3745 | { | |
3746 | { Bad_Opcode }, | |
3747 | { "rdgsbase", { Ev } }, | |
3748 | }, | |
3749 | ||
3750 | /* PREFIX_0FAE_REG_2 */ | |
3751 | { | |
3752 | { Bad_Opcode }, | |
3753 | { "wrfsbase", { Ev } }, | |
3754 | }, | |
3755 | ||
3756 | /* PREFIX_0FAE_REG_3 */ | |
3757 | { | |
3758 | { Bad_Opcode }, | |
3759 | { "wrgsbase", { Ev } }, | |
3760 | }, | |
3761 | ||
1ceb70f8 | 3762 | /* PREFIX_0FB8 */ |
ca164297 | 3763 | { |
592d1631 | 3764 | { Bad_Opcode }, |
4e7d34a6 | 3765 | { "popcntS", { Gv, Ev } }, |
ca164297 | 3766 | }, |
4e7d34a6 | 3767 | |
f12dc422 L |
3768 | /* PREFIX_0FBC */ |
3769 | { | |
3770 | { "bsfS", { Gv, Ev } }, | |
3771 | { "tzcntS", { Gv, Ev } }, | |
3772 | { "bsfS", { Gv, Ev } }, | |
3773 | }, | |
3774 | ||
1ceb70f8 | 3775 | /* PREFIX_0FBD */ |
050dfa73 | 3776 | { |
4e7d34a6 L |
3777 | { "bsrS", { Gv, Ev } }, |
3778 | { "lzcntS", { Gv, Ev } }, | |
3779 | { "bsrS", { Gv, Ev } }, | |
050dfa73 MM |
3780 | }, |
3781 | ||
1ceb70f8 | 3782 | /* PREFIX_0FC2 */ |
050dfa73 | 3783 | { |
ad19981d L |
3784 | { "cmpps", { XM, EXx, CMP } }, |
3785 | { "cmpss", { XM, EXd, CMP } }, | |
3786 | { "cmppd", { XM, EXx, CMP } }, | |
3787 | { "cmpsd", { XM, EXq, CMP } }, | |
050dfa73 | 3788 | }, |
246c51aa | 3789 | |
4ee52178 L |
3790 | /* PREFIX_0FC3 */ |
3791 | { | |
3792 | { "movntiS", { Ma, Gv } }, | |
4ee52178 L |
3793 | }, |
3794 | ||
92fddf8e L |
3795 | /* PREFIX_0FC7_REG_6 */ |
3796 | { | |
3797 | { "vmptrld",{ Mq } }, | |
3798 | { "vmxon", { Mq } }, | |
3799 | { "vmclear",{ Mq } }, | |
92fddf8e L |
3800 | }, |
3801 | ||
1ceb70f8 | 3802 | /* PREFIX_0FD0 */ |
050dfa73 | 3803 | { |
592d1631 L |
3804 | { Bad_Opcode }, |
3805 | { Bad_Opcode }, | |
4e7d34a6 L |
3806 | { "addsubpd", { XM, EXx } }, |
3807 | { "addsubps", { XM, EXx } }, | |
246c51aa | 3808 | }, |
050dfa73 | 3809 | |
1ceb70f8 | 3810 | /* PREFIX_0FD6 */ |
050dfa73 | 3811 | { |
592d1631 | 3812 | { Bad_Opcode }, |
4e7d34a6 | 3813 | { "movq2dq",{ XM, MS } }, |
b6169b20 | 3814 | { "movq", { EXqS, XM } }, |
4e7d34a6 | 3815 | { "movdq2q",{ MX, XS } }, |
050dfa73 MM |
3816 | }, |
3817 | ||
1ceb70f8 | 3818 | /* PREFIX_0FE6 */ |
7918206c | 3819 | { |
592d1631 | 3820 | { Bad_Opcode }, |
4e7d34a6 L |
3821 | { "cvtdq2pd", { XM, EXq } }, |
3822 | { "cvttpd2dq", { XM, EXx } }, | |
3823 | { "cvtpd2dq", { XM, EXx } }, | |
7918206c | 3824 | }, |
8b38ad71 | 3825 | |
1ceb70f8 | 3826 | /* PREFIX_0FE7 */ |
8b38ad71 | 3827 | { |
4ee52178 | 3828 | { "movntq", { Mq, MX } }, |
592d1631 | 3829 | { Bad_Opcode }, |
75c135a8 | 3830 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
4e7d34a6 L |
3831 | }, |
3832 | ||
1ceb70f8 | 3833 | /* PREFIX_0FF0 */ |
4e7d34a6 | 3834 | { |
592d1631 L |
3835 | { Bad_Opcode }, |
3836 | { Bad_Opcode }, | |
3837 | { Bad_Opcode }, | |
1ceb70f8 | 3838 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
3839 | }, |
3840 | ||
1ceb70f8 | 3841 | /* PREFIX_0FF7 */ |
4e7d34a6 L |
3842 | { |
3843 | { "maskmovq", { MX, MS } }, | |
592d1631 | 3844 | { Bad_Opcode }, |
4e7d34a6 | 3845 | { "maskmovdqu", { XM, XS } }, |
8b38ad71 | 3846 | }, |
42903f7f | 3847 | |
1ceb70f8 | 3848 | /* PREFIX_0F3810 */ |
42903f7f | 3849 | { |
592d1631 L |
3850 | { Bad_Opcode }, |
3851 | { Bad_Opcode }, | |
88a94849 | 3852 | { "pblendvb", { XM, EXx, XMM0 } }, |
42903f7f L |
3853 | }, |
3854 | ||
1ceb70f8 | 3855 | /* PREFIX_0F3814 */ |
42903f7f | 3856 | { |
592d1631 L |
3857 | { Bad_Opcode }, |
3858 | { Bad_Opcode }, | |
88a94849 | 3859 | { "blendvps", { XM, EXx, XMM0 } }, |
42903f7f L |
3860 | }, |
3861 | ||
1ceb70f8 | 3862 | /* PREFIX_0F3815 */ |
42903f7f | 3863 | { |
592d1631 L |
3864 | { Bad_Opcode }, |
3865 | { Bad_Opcode }, | |
09a2c6cf | 3866 | { "blendvpd", { XM, EXx, XMM0 } }, |
42903f7f L |
3867 | }, |
3868 | ||
1ceb70f8 | 3869 | /* PREFIX_0F3817 */ |
42903f7f | 3870 | { |
592d1631 L |
3871 | { Bad_Opcode }, |
3872 | { Bad_Opcode }, | |
09a2c6cf | 3873 | { "ptest", { XM, EXx } }, |
42903f7f L |
3874 | }, |
3875 | ||
1ceb70f8 | 3876 | /* PREFIX_0F3820 */ |
42903f7f | 3877 | { |
592d1631 L |
3878 | { Bad_Opcode }, |
3879 | { Bad_Opcode }, | |
8976381e | 3880 | { "pmovsxbw", { XM, EXq } }, |
42903f7f L |
3881 | }, |
3882 | ||
1ceb70f8 | 3883 | /* PREFIX_0F3821 */ |
42903f7f | 3884 | { |
592d1631 L |
3885 | { Bad_Opcode }, |
3886 | { Bad_Opcode }, | |
8976381e | 3887 | { "pmovsxbd", { XM, EXd } }, |
42903f7f L |
3888 | }, |
3889 | ||
1ceb70f8 | 3890 | /* PREFIX_0F3822 */ |
42903f7f | 3891 | { |
592d1631 L |
3892 | { Bad_Opcode }, |
3893 | { Bad_Opcode }, | |
8976381e | 3894 | { "pmovsxbq", { XM, EXw } }, |
42903f7f L |
3895 | }, |
3896 | ||
1ceb70f8 | 3897 | /* PREFIX_0F3823 */ |
42903f7f | 3898 | { |
592d1631 L |
3899 | { Bad_Opcode }, |
3900 | { Bad_Opcode }, | |
8976381e | 3901 | { "pmovsxwd", { XM, EXq } }, |
42903f7f L |
3902 | }, |
3903 | ||
1ceb70f8 | 3904 | /* PREFIX_0F3824 */ |
42903f7f | 3905 | { |
592d1631 L |
3906 | { Bad_Opcode }, |
3907 | { Bad_Opcode }, | |
8976381e | 3908 | { "pmovsxwq", { XM, EXd } }, |
42903f7f L |
3909 | }, |
3910 | ||
1ceb70f8 | 3911 | /* PREFIX_0F3825 */ |
42903f7f | 3912 | { |
592d1631 L |
3913 | { Bad_Opcode }, |
3914 | { Bad_Opcode }, | |
8976381e | 3915 | { "pmovsxdq", { XM, EXq } }, |
42903f7f L |
3916 | }, |
3917 | ||
1ceb70f8 | 3918 | /* PREFIX_0F3828 */ |
42903f7f | 3919 | { |
592d1631 L |
3920 | { Bad_Opcode }, |
3921 | { Bad_Opcode }, | |
09a2c6cf | 3922 | { "pmuldq", { XM, EXx } }, |
42903f7f L |
3923 | }, |
3924 | ||
1ceb70f8 | 3925 | /* PREFIX_0F3829 */ |
42903f7f | 3926 | { |
592d1631 L |
3927 | { Bad_Opcode }, |
3928 | { Bad_Opcode }, | |
09a2c6cf | 3929 | { "pcmpeqq", { XM, EXx } }, |
42903f7f L |
3930 | }, |
3931 | ||
1ceb70f8 | 3932 | /* PREFIX_0F382A */ |
42903f7f | 3933 | { |
592d1631 L |
3934 | { Bad_Opcode }, |
3935 | { Bad_Opcode }, | |
75c135a8 | 3936 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
42903f7f L |
3937 | }, |
3938 | ||
1ceb70f8 | 3939 | /* PREFIX_0F382B */ |
42903f7f | 3940 | { |
592d1631 L |
3941 | { Bad_Opcode }, |
3942 | { Bad_Opcode }, | |
09a2c6cf | 3943 | { "packusdw", { XM, EXx } }, |
42903f7f L |
3944 | }, |
3945 | ||
1ceb70f8 | 3946 | /* PREFIX_0F3830 */ |
42903f7f | 3947 | { |
592d1631 L |
3948 | { Bad_Opcode }, |
3949 | { Bad_Opcode }, | |
8976381e | 3950 | { "pmovzxbw", { XM, EXq } }, |
42903f7f L |
3951 | }, |
3952 | ||
1ceb70f8 | 3953 | /* PREFIX_0F3831 */ |
42903f7f | 3954 | { |
592d1631 L |
3955 | { Bad_Opcode }, |
3956 | { Bad_Opcode }, | |
8976381e | 3957 | { "pmovzxbd", { XM, EXd } }, |
42903f7f L |
3958 | }, |
3959 | ||
1ceb70f8 | 3960 | /* PREFIX_0F3832 */ |
42903f7f | 3961 | { |
592d1631 L |
3962 | { Bad_Opcode }, |
3963 | { Bad_Opcode }, | |
8976381e | 3964 | { "pmovzxbq", { XM, EXw } }, |
42903f7f L |
3965 | }, |
3966 | ||
1ceb70f8 | 3967 | /* PREFIX_0F3833 */ |
42903f7f | 3968 | { |
592d1631 L |
3969 | { Bad_Opcode }, |
3970 | { Bad_Opcode }, | |
8976381e | 3971 | { "pmovzxwd", { XM, EXq } }, |
42903f7f L |
3972 | }, |
3973 | ||
1ceb70f8 | 3974 | /* PREFIX_0F3834 */ |
42903f7f | 3975 | { |
592d1631 L |
3976 | { Bad_Opcode }, |
3977 | { Bad_Opcode }, | |
8976381e | 3978 | { "pmovzxwq", { XM, EXd } }, |
42903f7f L |
3979 | }, |
3980 | ||
1ceb70f8 | 3981 | /* PREFIX_0F3835 */ |
42903f7f | 3982 | { |
592d1631 L |
3983 | { Bad_Opcode }, |
3984 | { Bad_Opcode }, | |
8976381e | 3985 | { "pmovzxdq", { XM, EXq } }, |
42903f7f L |
3986 | }, |
3987 | ||
1ceb70f8 | 3988 | /* PREFIX_0F3837 */ |
4e7d34a6 | 3989 | { |
592d1631 L |
3990 | { Bad_Opcode }, |
3991 | { Bad_Opcode }, | |
4e7d34a6 | 3992 | { "pcmpgtq", { XM, EXx } }, |
4e7d34a6 L |
3993 | }, |
3994 | ||
1ceb70f8 | 3995 | /* PREFIX_0F3838 */ |
42903f7f | 3996 | { |
592d1631 L |
3997 | { Bad_Opcode }, |
3998 | { Bad_Opcode }, | |
09a2c6cf | 3999 | { "pminsb", { XM, EXx } }, |
42903f7f L |
4000 | }, |
4001 | ||
1ceb70f8 | 4002 | /* PREFIX_0F3839 */ |
42903f7f | 4003 | { |
592d1631 L |
4004 | { Bad_Opcode }, |
4005 | { Bad_Opcode }, | |
09a2c6cf | 4006 | { "pminsd", { XM, EXx } }, |
42903f7f L |
4007 | }, |
4008 | ||
1ceb70f8 | 4009 | /* PREFIX_0F383A */ |
42903f7f | 4010 | { |
592d1631 L |
4011 | { Bad_Opcode }, |
4012 | { Bad_Opcode }, | |
09a2c6cf | 4013 | { "pminuw", { XM, EXx } }, |
42903f7f L |
4014 | }, |
4015 | ||
1ceb70f8 | 4016 | /* PREFIX_0F383B */ |
42903f7f | 4017 | { |
592d1631 L |
4018 | { Bad_Opcode }, |
4019 | { Bad_Opcode }, | |
09a2c6cf | 4020 | { "pminud", { XM, EXx } }, |
42903f7f L |
4021 | }, |
4022 | ||
1ceb70f8 | 4023 | /* PREFIX_0F383C */ |
42903f7f | 4024 | { |
592d1631 L |
4025 | { Bad_Opcode }, |
4026 | { Bad_Opcode }, | |
09a2c6cf | 4027 | { "pmaxsb", { XM, EXx } }, |
42903f7f L |
4028 | }, |
4029 | ||
1ceb70f8 | 4030 | /* PREFIX_0F383D */ |
42903f7f | 4031 | { |
592d1631 L |
4032 | { Bad_Opcode }, |
4033 | { Bad_Opcode }, | |
09a2c6cf | 4034 | { "pmaxsd", { XM, EXx } }, |
42903f7f L |
4035 | }, |
4036 | ||
1ceb70f8 | 4037 | /* PREFIX_0F383E */ |
42903f7f | 4038 | { |
592d1631 L |
4039 | { Bad_Opcode }, |
4040 | { Bad_Opcode }, | |
09a2c6cf | 4041 | { "pmaxuw", { XM, EXx } }, |
42903f7f L |
4042 | }, |
4043 | ||
1ceb70f8 | 4044 | /* PREFIX_0F383F */ |
42903f7f | 4045 | { |
592d1631 L |
4046 | { Bad_Opcode }, |
4047 | { Bad_Opcode }, | |
09a2c6cf | 4048 | { "pmaxud", { XM, EXx } }, |
42903f7f L |
4049 | }, |
4050 | ||
1ceb70f8 | 4051 | /* PREFIX_0F3840 */ |
42903f7f | 4052 | { |
592d1631 L |
4053 | { Bad_Opcode }, |
4054 | { Bad_Opcode }, | |
09a2c6cf | 4055 | { "pmulld", { XM, EXx } }, |
42903f7f L |
4056 | }, |
4057 | ||
1ceb70f8 | 4058 | /* PREFIX_0F3841 */ |
42903f7f | 4059 | { |
592d1631 L |
4060 | { Bad_Opcode }, |
4061 | { Bad_Opcode }, | |
09a2c6cf | 4062 | { "phminposuw", { XM, EXx } }, |
42903f7f L |
4063 | }, |
4064 | ||
f1f8f695 L |
4065 | /* PREFIX_0F3880 */ |
4066 | { | |
592d1631 L |
4067 | { Bad_Opcode }, |
4068 | { Bad_Opcode }, | |
f1f8f695 | 4069 | { "invept", { Gm, Mo } }, |
f1f8f695 L |
4070 | }, |
4071 | ||
4072 | /* PREFIX_0F3881 */ | |
4073 | { | |
592d1631 L |
4074 | { Bad_Opcode }, |
4075 | { Bad_Opcode }, | |
f1f8f695 | 4076 | { "invvpid", { Gm, Mo } }, |
f1f8f695 L |
4077 | }, |
4078 | ||
6c30d220 L |
4079 | /* PREFIX_0F3882 */ |
4080 | { | |
4081 | { Bad_Opcode }, | |
4082 | { Bad_Opcode }, | |
4083 | { "invpcid", { Gm, M } }, | |
4084 | }, | |
4085 | ||
a0046408 L |
4086 | /* PREFIX_0F38C8 */ |
4087 | { | |
4088 | { "sha1nexte", { XM, EXxmm } }, | |
4089 | }, | |
4090 | ||
4091 | /* PREFIX_0F38C9 */ | |
4092 | { | |
4093 | { "sha1msg1", { XM, EXxmm } }, | |
4094 | }, | |
4095 | ||
4096 | /* PREFIX_0F38CA */ | |
4097 | { | |
4098 | { "sha1msg2", { XM, EXxmm } }, | |
4099 | }, | |
4100 | ||
4101 | /* PREFIX_0F38CB */ | |
4102 | { | |
4103 | { "sha256rnds2", { XM, EXxmm, XMM0 } }, | |
4104 | }, | |
4105 | ||
4106 | /* PREFIX_0F38CC */ | |
4107 | { | |
4108 | { "sha256msg1", { XM, EXxmm } }, | |
4109 | }, | |
4110 | ||
4111 | /* PREFIX_0F38CD */ | |
4112 | { | |
4113 | { "sha256msg2", { XM, EXxmm } }, | |
4114 | }, | |
4115 | ||
c0f3af97 L |
4116 | /* PREFIX_0F38DB */ |
4117 | { | |
592d1631 L |
4118 | { Bad_Opcode }, |
4119 | { Bad_Opcode }, | |
c0f3af97 | 4120 | { "aesimc", { XM, EXx } }, |
c0f3af97 L |
4121 | }, |
4122 | ||
4123 | /* PREFIX_0F38DC */ | |
4124 | { | |
592d1631 L |
4125 | { Bad_Opcode }, |
4126 | { Bad_Opcode }, | |
c0f3af97 | 4127 | { "aesenc", { XM, EXx } }, |
c0f3af97 L |
4128 | }, |
4129 | ||
4130 | /* PREFIX_0F38DD */ | |
4131 | { | |
592d1631 L |
4132 | { Bad_Opcode }, |
4133 | { Bad_Opcode }, | |
c0f3af97 | 4134 | { "aesenclast", { XM, EXx } }, |
c0f3af97 L |
4135 | }, |
4136 | ||
4137 | /* PREFIX_0F38DE */ | |
4138 | { | |
592d1631 L |
4139 | { Bad_Opcode }, |
4140 | { Bad_Opcode }, | |
c0f3af97 | 4141 | { "aesdec", { XM, EXx } }, |
c0f3af97 L |
4142 | }, |
4143 | ||
4144 | /* PREFIX_0F38DF */ | |
4145 | { | |
592d1631 L |
4146 | { Bad_Opcode }, |
4147 | { Bad_Opcode }, | |
c0f3af97 | 4148 | { "aesdeclast", { XM, EXx } }, |
c0f3af97 L |
4149 | }, |
4150 | ||
1ceb70f8 | 4151 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 4152 | { |
f1f8f695 | 4153 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } }, |
592d1631 | 4154 | { Bad_Opcode }, |
f1f8f695 | 4155 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } }, |
7bb15c6f | 4156 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } } }, |
4e7d34a6 L |
4157 | }, |
4158 | ||
1ceb70f8 | 4159 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 4160 | { |
f1f8f695 | 4161 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } }, |
592d1631 | 4162 | { Bad_Opcode }, |
f1f8f695 | 4163 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } }, |
7bb15c6f | 4164 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } } }, |
4e7d34a6 L |
4165 | }, |
4166 | ||
e2e1fcde L |
4167 | /* PREFIX_0F38F6 */ |
4168 | { | |
4169 | { Bad_Opcode }, | |
4170 | { "adoxS", { Gdq, Edq} }, | |
4171 | { "adcxS", { Gdq, Edq} }, | |
4172 | { Bad_Opcode }, | |
4173 | }, | |
4174 | ||
1ceb70f8 | 4175 | /* PREFIX_0F3A08 */ |
42903f7f | 4176 | { |
592d1631 L |
4177 | { Bad_Opcode }, |
4178 | { Bad_Opcode }, | |
09a2c6cf | 4179 | { "roundps", { XM, EXx, Ib } }, |
42903f7f L |
4180 | }, |
4181 | ||
1ceb70f8 | 4182 | /* PREFIX_0F3A09 */ |
42903f7f | 4183 | { |
592d1631 L |
4184 | { Bad_Opcode }, |
4185 | { Bad_Opcode }, | |
09a2c6cf | 4186 | { "roundpd", { XM, EXx, Ib } }, |
42903f7f L |
4187 | }, |
4188 | ||
1ceb70f8 | 4189 | /* PREFIX_0F3A0A */ |
42903f7f | 4190 | { |
592d1631 L |
4191 | { Bad_Opcode }, |
4192 | { Bad_Opcode }, | |
09335d05 | 4193 | { "roundss", { XM, EXd, Ib } }, |
42903f7f L |
4194 | }, |
4195 | ||
1ceb70f8 | 4196 | /* PREFIX_0F3A0B */ |
42903f7f | 4197 | { |
592d1631 L |
4198 | { Bad_Opcode }, |
4199 | { Bad_Opcode }, | |
09335d05 | 4200 | { "roundsd", { XM, EXq, Ib } }, |
42903f7f L |
4201 | }, |
4202 | ||
1ceb70f8 | 4203 | /* PREFIX_0F3A0C */ |
42903f7f | 4204 | { |
592d1631 L |
4205 | { Bad_Opcode }, |
4206 | { Bad_Opcode }, | |
09a2c6cf | 4207 | { "blendps", { XM, EXx, Ib } }, |
42903f7f L |
4208 | }, |
4209 | ||
1ceb70f8 | 4210 | /* PREFIX_0F3A0D */ |
42903f7f | 4211 | { |
592d1631 L |
4212 | { Bad_Opcode }, |
4213 | { Bad_Opcode }, | |
09a2c6cf | 4214 | { "blendpd", { XM, EXx, Ib } }, |
42903f7f L |
4215 | }, |
4216 | ||
1ceb70f8 | 4217 | /* PREFIX_0F3A0E */ |
42903f7f | 4218 | { |
592d1631 L |
4219 | { Bad_Opcode }, |
4220 | { Bad_Opcode }, | |
09a2c6cf | 4221 | { "pblendw", { XM, EXx, Ib } }, |
42903f7f L |
4222 | }, |
4223 | ||
1ceb70f8 | 4224 | /* PREFIX_0F3A14 */ |
42903f7f | 4225 | { |
592d1631 L |
4226 | { Bad_Opcode }, |
4227 | { Bad_Opcode }, | |
42903f7f | 4228 | { "pextrb", { Edqb, XM, Ib } }, |
42903f7f L |
4229 | }, |
4230 | ||
1ceb70f8 | 4231 | /* PREFIX_0F3A15 */ |
42903f7f | 4232 | { |
592d1631 L |
4233 | { Bad_Opcode }, |
4234 | { Bad_Opcode }, | |
42903f7f | 4235 | { "pextrw", { Edqw, XM, Ib } }, |
42903f7f L |
4236 | }, |
4237 | ||
1ceb70f8 | 4238 | /* PREFIX_0F3A16 */ |
42903f7f | 4239 | { |
592d1631 L |
4240 | { Bad_Opcode }, |
4241 | { Bad_Opcode }, | |
42903f7f | 4242 | { "pextrK", { Edq, XM, Ib } }, |
42903f7f L |
4243 | }, |
4244 | ||
1ceb70f8 | 4245 | /* PREFIX_0F3A17 */ |
42903f7f | 4246 | { |
592d1631 L |
4247 | { Bad_Opcode }, |
4248 | { Bad_Opcode }, | |
42903f7f | 4249 | { "extractps", { Edqd, XM, Ib } }, |
42903f7f L |
4250 | }, |
4251 | ||
1ceb70f8 | 4252 | /* PREFIX_0F3A20 */ |
42903f7f | 4253 | { |
592d1631 L |
4254 | { Bad_Opcode }, |
4255 | { Bad_Opcode }, | |
42903f7f | 4256 | { "pinsrb", { XM, Edqb, Ib } }, |
42903f7f L |
4257 | }, |
4258 | ||
1ceb70f8 | 4259 | /* PREFIX_0F3A21 */ |
42903f7f | 4260 | { |
592d1631 L |
4261 | { Bad_Opcode }, |
4262 | { Bad_Opcode }, | |
8976381e | 4263 | { "insertps", { XM, EXd, Ib } }, |
42903f7f L |
4264 | }, |
4265 | ||
1ceb70f8 | 4266 | /* PREFIX_0F3A22 */ |
42903f7f | 4267 | { |
592d1631 L |
4268 | { Bad_Opcode }, |
4269 | { Bad_Opcode }, | |
42903f7f | 4270 | { "pinsrK", { XM, Edq, Ib } }, |
42903f7f L |
4271 | }, |
4272 | ||
1ceb70f8 | 4273 | /* PREFIX_0F3A40 */ |
42903f7f | 4274 | { |
592d1631 L |
4275 | { Bad_Opcode }, |
4276 | { Bad_Opcode }, | |
09a2c6cf | 4277 | { "dpps", { XM, EXx, Ib } }, |
42903f7f L |
4278 | }, |
4279 | ||
1ceb70f8 | 4280 | /* PREFIX_0F3A41 */ |
42903f7f | 4281 | { |
592d1631 L |
4282 | { Bad_Opcode }, |
4283 | { Bad_Opcode }, | |
09a2c6cf | 4284 | { "dppd", { XM, EXx, Ib } }, |
42903f7f L |
4285 | }, |
4286 | ||
1ceb70f8 | 4287 | /* PREFIX_0F3A42 */ |
42903f7f | 4288 | { |
592d1631 L |
4289 | { Bad_Opcode }, |
4290 | { Bad_Opcode }, | |
09a2c6cf | 4291 | { "mpsadbw", { XM, EXx, Ib } }, |
42903f7f | 4292 | }, |
381d071f | 4293 | |
c0f3af97 L |
4294 | /* PREFIX_0F3A44 */ |
4295 | { | |
592d1631 L |
4296 | { Bad_Opcode }, |
4297 | { Bad_Opcode }, | |
c0f3af97 | 4298 | { "pclmulqdq", { XM, EXx, PCLMUL } }, |
c0f3af97 L |
4299 | }, |
4300 | ||
1ceb70f8 | 4301 | /* PREFIX_0F3A60 */ |
381d071f | 4302 | { |
592d1631 L |
4303 | { Bad_Opcode }, |
4304 | { Bad_Opcode }, | |
4e7d34a6 | 4305 | { "pcmpestrm", { XM, EXx, Ib } }, |
381d071f L |
4306 | }, |
4307 | ||
1ceb70f8 | 4308 | /* PREFIX_0F3A61 */ |
381d071f | 4309 | { |
592d1631 L |
4310 | { Bad_Opcode }, |
4311 | { Bad_Opcode }, | |
4e7d34a6 | 4312 | { "pcmpestri", { XM, EXx, Ib } }, |
381d071f L |
4313 | }, |
4314 | ||
1ceb70f8 | 4315 | /* PREFIX_0F3A62 */ |
381d071f | 4316 | { |
592d1631 L |
4317 | { Bad_Opcode }, |
4318 | { Bad_Opcode }, | |
4e7d34a6 | 4319 | { "pcmpistrm", { XM, EXx, Ib } }, |
381d071f L |
4320 | }, |
4321 | ||
1ceb70f8 | 4322 | /* PREFIX_0F3A63 */ |
381d071f | 4323 | { |
592d1631 L |
4324 | { Bad_Opcode }, |
4325 | { Bad_Opcode }, | |
4e7d34a6 | 4326 | { "pcmpistri", { XM, EXx, Ib } }, |
381d071f | 4327 | }, |
09a2c6cf | 4328 | |
a0046408 L |
4329 | /* PREFIX_0F3ACC */ |
4330 | { | |
4331 | { "sha1rnds4", { XM, EXxmm, Ib } }, | |
4332 | }, | |
4333 | ||
c0f3af97 | 4334 | /* PREFIX_0F3ADF */ |
09a2c6cf | 4335 | { |
592d1631 L |
4336 | { Bad_Opcode }, |
4337 | { Bad_Opcode }, | |
c0f3af97 | 4338 | { "aeskeygenassist", { XM, EXx, Ib } }, |
09a2c6cf L |
4339 | }, |
4340 | ||
592a252b | 4341 | /* PREFIX_VEX_0F10 */ |
09a2c6cf | 4342 | { |
592a252b L |
4343 | { VEX_W_TABLE (VEX_W_0F10_P_0) }, |
4344 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) }, | |
4345 | { VEX_W_TABLE (VEX_W_0F10_P_2) }, | |
4346 | { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) }, | |
09a2c6cf L |
4347 | }, |
4348 | ||
592a252b | 4349 | /* PREFIX_VEX_0F11 */ |
09a2c6cf | 4350 | { |
592a252b L |
4351 | { VEX_W_TABLE (VEX_W_0F11_P_0) }, |
4352 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) }, | |
4353 | { VEX_W_TABLE (VEX_W_0F11_P_2) }, | |
4354 | { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) }, | |
09a2c6cf L |
4355 | }, |
4356 | ||
592a252b | 4357 | /* PREFIX_VEX_0F12 */ |
09a2c6cf | 4358 | { |
592a252b L |
4359 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
4360 | { VEX_W_TABLE (VEX_W_0F12_P_1) }, | |
4361 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) }, | |
4362 | { VEX_W_TABLE (VEX_W_0F12_P_3) }, | |
09a2c6cf L |
4363 | }, |
4364 | ||
592a252b | 4365 | /* PREFIX_VEX_0F16 */ |
09a2c6cf | 4366 | { |
592a252b L |
4367 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
4368 | { VEX_W_TABLE (VEX_W_0F16_P_1) }, | |
4369 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) }, | |
5f754f58 | 4370 | }, |
7c52e0e8 | 4371 | |
592a252b | 4372 | /* PREFIX_VEX_0F2A */ |
5f754f58 | 4373 | { |
592d1631 | 4374 | { Bad_Opcode }, |
592a252b | 4375 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) }, |
592d1631 | 4376 | { Bad_Opcode }, |
592a252b | 4377 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) }, |
5f754f58 | 4378 | }, |
7c52e0e8 | 4379 | |
592a252b | 4380 | /* PREFIX_VEX_0F2C */ |
5f754f58 | 4381 | { |
592d1631 | 4382 | { Bad_Opcode }, |
592a252b | 4383 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) }, |
592d1631 | 4384 | { Bad_Opcode }, |
592a252b | 4385 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) }, |
5f754f58 | 4386 | }, |
7c52e0e8 | 4387 | |
592a252b | 4388 | /* PREFIX_VEX_0F2D */ |
7c52e0e8 | 4389 | { |
592d1631 | 4390 | { Bad_Opcode }, |
592a252b | 4391 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) }, |
592d1631 | 4392 | { Bad_Opcode }, |
592a252b | 4393 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) }, |
7c52e0e8 L |
4394 | }, |
4395 | ||
592a252b | 4396 | /* PREFIX_VEX_0F2E */ |
7c52e0e8 | 4397 | { |
592a252b | 4398 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) }, |
592d1631 | 4399 | { Bad_Opcode }, |
592a252b | 4400 | { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) }, |
7c52e0e8 L |
4401 | }, |
4402 | ||
592a252b | 4403 | /* PREFIX_VEX_0F2F */ |
7c52e0e8 | 4404 | { |
592a252b | 4405 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) }, |
592d1631 | 4406 | { Bad_Opcode }, |
592a252b | 4407 | { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) }, |
7c52e0e8 L |
4408 | }, |
4409 | ||
43234a1e L |
4410 | /* PREFIX_VEX_0F41 */ |
4411 | { | |
4412 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, | |
4413 | }, | |
4414 | ||
4415 | /* PREFIX_VEX_0F42 */ | |
4416 | { | |
4417 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, | |
4418 | }, | |
4419 | ||
4420 | /* PREFIX_VEX_0F44 */ | |
4421 | { | |
4422 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, | |
4423 | }, | |
4424 | ||
4425 | /* PREFIX_VEX_0F45 */ | |
4426 | { | |
4427 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, | |
4428 | }, | |
4429 | ||
4430 | /* PREFIX_VEX_0F46 */ | |
4431 | { | |
4432 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, | |
4433 | }, | |
4434 | ||
4435 | /* PREFIX_VEX_0F47 */ | |
4436 | { | |
4437 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, | |
4438 | }, | |
4439 | ||
4440 | /* PREFIX_VEX_0F4B */ | |
4441 | { | |
4442 | { Bad_Opcode }, | |
4443 | { Bad_Opcode }, | |
4444 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, | |
4445 | }, | |
4446 | ||
592a252b | 4447 | /* PREFIX_VEX_0F51 */ |
7c52e0e8 | 4448 | { |
592a252b L |
4449 | { VEX_W_TABLE (VEX_W_0F51_P_0) }, |
4450 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) }, | |
4451 | { VEX_W_TABLE (VEX_W_0F51_P_2) }, | |
4452 | { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) }, | |
7c52e0e8 L |
4453 | }, |
4454 | ||
592a252b | 4455 | /* PREFIX_VEX_0F52 */ |
7c52e0e8 | 4456 | { |
592a252b L |
4457 | { VEX_W_TABLE (VEX_W_0F52_P_0) }, |
4458 | { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) }, | |
7c52e0e8 L |
4459 | }, |
4460 | ||
592a252b | 4461 | /* PREFIX_VEX_0F53 */ |
7c52e0e8 | 4462 | { |
592a252b L |
4463 | { VEX_W_TABLE (VEX_W_0F53_P_0) }, |
4464 | { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) }, | |
7c52e0e8 L |
4465 | }, |
4466 | ||
592a252b | 4467 | /* PREFIX_VEX_0F58 */ |
7c52e0e8 | 4468 | { |
592a252b L |
4469 | { VEX_W_TABLE (VEX_W_0F58_P_0) }, |
4470 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) }, | |
4471 | { VEX_W_TABLE (VEX_W_0F58_P_2) }, | |
4472 | { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) }, | |
7c52e0e8 L |
4473 | }, |
4474 | ||
592a252b | 4475 | /* PREFIX_VEX_0F59 */ |
7c52e0e8 | 4476 | { |
592a252b L |
4477 | { VEX_W_TABLE (VEX_W_0F59_P_0) }, |
4478 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) }, | |
4479 | { VEX_W_TABLE (VEX_W_0F59_P_2) }, | |
4480 | { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) }, | |
7c52e0e8 L |
4481 | }, |
4482 | ||
592a252b | 4483 | /* PREFIX_VEX_0F5A */ |
7c52e0e8 | 4484 | { |
592a252b L |
4485 | { VEX_W_TABLE (VEX_W_0F5A_P_0) }, |
4486 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) }, | |
c0f3af97 | 4487 | { "vcvtpd2ps%XY", { XMM, EXx } }, |
592a252b | 4488 | { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) }, |
7c52e0e8 L |
4489 | }, |
4490 | ||
592a252b | 4491 | /* PREFIX_VEX_0F5B */ |
7c52e0e8 | 4492 | { |
592a252b L |
4493 | { VEX_W_TABLE (VEX_W_0F5B_P_0) }, |
4494 | { VEX_W_TABLE (VEX_W_0F5B_P_1) }, | |
4495 | { VEX_W_TABLE (VEX_W_0F5B_P_2) }, | |
7c52e0e8 L |
4496 | }, |
4497 | ||
592a252b | 4498 | /* PREFIX_VEX_0F5C */ |
7c52e0e8 | 4499 | { |
592a252b L |
4500 | { VEX_W_TABLE (VEX_W_0F5C_P_0) }, |
4501 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) }, | |
4502 | { VEX_W_TABLE (VEX_W_0F5C_P_2) }, | |
4503 | { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) }, | |
7c52e0e8 L |
4504 | }, |
4505 | ||
592a252b | 4506 | /* PREFIX_VEX_0F5D */ |
7c52e0e8 | 4507 | { |
592a252b L |
4508 | { VEX_W_TABLE (VEX_W_0F5D_P_0) }, |
4509 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) }, | |
4510 | { VEX_W_TABLE (VEX_W_0F5D_P_2) }, | |
4511 | { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) }, | |
7c52e0e8 L |
4512 | }, |
4513 | ||
592a252b | 4514 | /* PREFIX_VEX_0F5E */ |
7c52e0e8 | 4515 | { |
592a252b L |
4516 | { VEX_W_TABLE (VEX_W_0F5E_P_0) }, |
4517 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) }, | |
4518 | { VEX_W_TABLE (VEX_W_0F5E_P_2) }, | |
4519 | { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) }, | |
7c52e0e8 L |
4520 | }, |
4521 | ||
592a252b | 4522 | /* PREFIX_VEX_0F5F */ |
7c52e0e8 | 4523 | { |
592a252b L |
4524 | { VEX_W_TABLE (VEX_W_0F5F_P_0) }, |
4525 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) }, | |
4526 | { VEX_W_TABLE (VEX_W_0F5F_P_2) }, | |
4527 | { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) }, | |
7c52e0e8 L |
4528 | }, |
4529 | ||
592a252b | 4530 | /* PREFIX_VEX_0F60 */ |
7c52e0e8 | 4531 | { |
592d1631 L |
4532 | { Bad_Opcode }, |
4533 | { Bad_Opcode }, | |
6c30d220 | 4534 | { VEX_W_TABLE (VEX_W_0F60_P_2) }, |
7c52e0e8 L |
4535 | }, |
4536 | ||
592a252b | 4537 | /* PREFIX_VEX_0F61 */ |
7c52e0e8 | 4538 | { |
592d1631 L |
4539 | { Bad_Opcode }, |
4540 | { Bad_Opcode }, | |
6c30d220 | 4541 | { VEX_W_TABLE (VEX_W_0F61_P_2) }, |
7c52e0e8 L |
4542 | }, |
4543 | ||
592a252b | 4544 | /* PREFIX_VEX_0F62 */ |
7c52e0e8 | 4545 | { |
592d1631 L |
4546 | { Bad_Opcode }, |
4547 | { Bad_Opcode }, | |
6c30d220 | 4548 | { VEX_W_TABLE (VEX_W_0F62_P_2) }, |
7c52e0e8 L |
4549 | }, |
4550 | ||
592a252b | 4551 | /* PREFIX_VEX_0F63 */ |
7c52e0e8 | 4552 | { |
592d1631 L |
4553 | { Bad_Opcode }, |
4554 | { Bad_Opcode }, | |
6c30d220 | 4555 | { VEX_W_TABLE (VEX_W_0F63_P_2) }, |
7c52e0e8 L |
4556 | }, |
4557 | ||
592a252b | 4558 | /* PREFIX_VEX_0F64 */ |
7c52e0e8 | 4559 | { |
592d1631 L |
4560 | { Bad_Opcode }, |
4561 | { Bad_Opcode }, | |
6c30d220 | 4562 | { VEX_W_TABLE (VEX_W_0F64_P_2) }, |
7c52e0e8 L |
4563 | }, |
4564 | ||
592a252b | 4565 | /* PREFIX_VEX_0F65 */ |
7c52e0e8 | 4566 | { |
592d1631 L |
4567 | { Bad_Opcode }, |
4568 | { Bad_Opcode }, | |
6c30d220 | 4569 | { VEX_W_TABLE (VEX_W_0F65_P_2) }, |
7c52e0e8 L |
4570 | }, |
4571 | ||
592a252b | 4572 | /* PREFIX_VEX_0F66 */ |
7c52e0e8 | 4573 | { |
592d1631 L |
4574 | { Bad_Opcode }, |
4575 | { Bad_Opcode }, | |
6c30d220 | 4576 | { VEX_W_TABLE (VEX_W_0F66_P_2) }, |
7c52e0e8 | 4577 | }, |
6439fc28 | 4578 | |
592a252b | 4579 | /* PREFIX_VEX_0F67 */ |
331d2d0d | 4580 | { |
592d1631 L |
4581 | { Bad_Opcode }, |
4582 | { Bad_Opcode }, | |
6c30d220 | 4583 | { VEX_W_TABLE (VEX_W_0F67_P_2) }, |
c0f3af97 L |
4584 | }, |
4585 | ||
592a252b | 4586 | /* PREFIX_VEX_0F68 */ |
c0f3af97 | 4587 | { |
592d1631 L |
4588 | { Bad_Opcode }, |
4589 | { Bad_Opcode }, | |
6c30d220 | 4590 | { VEX_W_TABLE (VEX_W_0F68_P_2) }, |
c0f3af97 L |
4591 | }, |
4592 | ||
592a252b | 4593 | /* PREFIX_VEX_0F69 */ |
c0f3af97 | 4594 | { |
592d1631 L |
4595 | { Bad_Opcode }, |
4596 | { Bad_Opcode }, | |
6c30d220 | 4597 | { VEX_W_TABLE (VEX_W_0F69_P_2) }, |
c0f3af97 L |
4598 | }, |
4599 | ||
592a252b | 4600 | /* PREFIX_VEX_0F6A */ |
c0f3af97 | 4601 | { |
592d1631 L |
4602 | { Bad_Opcode }, |
4603 | { Bad_Opcode }, | |
6c30d220 | 4604 | { VEX_W_TABLE (VEX_W_0F6A_P_2) }, |
c0f3af97 L |
4605 | }, |
4606 | ||
592a252b | 4607 | /* PREFIX_VEX_0F6B */ |
c0f3af97 | 4608 | { |
592d1631 L |
4609 | { Bad_Opcode }, |
4610 | { Bad_Opcode }, | |
6c30d220 | 4611 | { VEX_W_TABLE (VEX_W_0F6B_P_2) }, |
c0f3af97 L |
4612 | }, |
4613 | ||
592a252b | 4614 | /* PREFIX_VEX_0F6C */ |
c0f3af97 | 4615 | { |
592d1631 L |
4616 | { Bad_Opcode }, |
4617 | { Bad_Opcode }, | |
6c30d220 | 4618 | { VEX_W_TABLE (VEX_W_0F6C_P_2) }, |
c0f3af97 L |
4619 | }, |
4620 | ||
592a252b | 4621 | /* PREFIX_VEX_0F6D */ |
c0f3af97 | 4622 | { |
592d1631 L |
4623 | { Bad_Opcode }, |
4624 | { Bad_Opcode }, | |
6c30d220 | 4625 | { VEX_W_TABLE (VEX_W_0F6D_P_2) }, |
c0f3af97 L |
4626 | }, |
4627 | ||
592a252b | 4628 | /* PREFIX_VEX_0F6E */ |
c0f3af97 | 4629 | { |
592d1631 L |
4630 | { Bad_Opcode }, |
4631 | { Bad_Opcode }, | |
592a252b | 4632 | { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, |
c0f3af97 L |
4633 | }, |
4634 | ||
592a252b | 4635 | /* PREFIX_VEX_0F6F */ |
c0f3af97 | 4636 | { |
592d1631 | 4637 | { Bad_Opcode }, |
592a252b L |
4638 | { VEX_W_TABLE (VEX_W_0F6F_P_1) }, |
4639 | { VEX_W_TABLE (VEX_W_0F6F_P_2) }, | |
c0f3af97 L |
4640 | }, |
4641 | ||
592a252b | 4642 | /* PREFIX_VEX_0F70 */ |
c0f3af97 | 4643 | { |
592d1631 | 4644 | { Bad_Opcode }, |
6c30d220 L |
4645 | { VEX_W_TABLE (VEX_W_0F70_P_1) }, |
4646 | { VEX_W_TABLE (VEX_W_0F70_P_2) }, | |
4647 | { VEX_W_TABLE (VEX_W_0F70_P_3) }, | |
c0f3af97 L |
4648 | }, |
4649 | ||
592a252b | 4650 | /* PREFIX_VEX_0F71_REG_2 */ |
c0f3af97 | 4651 | { |
592d1631 L |
4652 | { Bad_Opcode }, |
4653 | { Bad_Opcode }, | |
6c30d220 | 4654 | { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) }, |
c0f3af97 L |
4655 | }, |
4656 | ||
592a252b | 4657 | /* PREFIX_VEX_0F71_REG_4 */ |
c0f3af97 | 4658 | { |
592d1631 L |
4659 | { Bad_Opcode }, |
4660 | { Bad_Opcode }, | |
6c30d220 | 4661 | { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) }, |
c0f3af97 L |
4662 | }, |
4663 | ||
592a252b | 4664 | /* PREFIX_VEX_0F71_REG_6 */ |
c0f3af97 | 4665 | { |
592d1631 L |
4666 | { Bad_Opcode }, |
4667 | { Bad_Opcode }, | |
6c30d220 | 4668 | { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) }, |
c0f3af97 L |
4669 | }, |
4670 | ||
592a252b | 4671 | /* PREFIX_VEX_0F72_REG_2 */ |
c0f3af97 | 4672 | { |
592d1631 L |
4673 | { Bad_Opcode }, |
4674 | { Bad_Opcode }, | |
6c30d220 | 4675 | { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) }, |
c0f3af97 L |
4676 | }, |
4677 | ||
592a252b | 4678 | /* PREFIX_VEX_0F72_REG_4 */ |
c0f3af97 | 4679 | { |
592d1631 L |
4680 | { Bad_Opcode }, |
4681 | { Bad_Opcode }, | |
6c30d220 | 4682 | { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) }, |
c0f3af97 L |
4683 | }, |
4684 | ||
592a252b | 4685 | /* PREFIX_VEX_0F72_REG_6 */ |
c0f3af97 | 4686 | { |
592d1631 L |
4687 | { Bad_Opcode }, |
4688 | { Bad_Opcode }, | |
6c30d220 | 4689 | { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) }, |
c0f3af97 L |
4690 | }, |
4691 | ||
592a252b | 4692 | /* PREFIX_VEX_0F73_REG_2 */ |
c0f3af97 | 4693 | { |
592d1631 L |
4694 | { Bad_Opcode }, |
4695 | { Bad_Opcode }, | |
6c30d220 | 4696 | { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) }, |
c0f3af97 L |
4697 | }, |
4698 | ||
592a252b | 4699 | /* PREFIX_VEX_0F73_REG_3 */ |
c0f3af97 | 4700 | { |
592d1631 L |
4701 | { Bad_Opcode }, |
4702 | { Bad_Opcode }, | |
6c30d220 | 4703 | { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) }, |
c0f3af97 L |
4704 | }, |
4705 | ||
592a252b | 4706 | /* PREFIX_VEX_0F73_REG_6 */ |
c0f3af97 | 4707 | { |
592d1631 L |
4708 | { Bad_Opcode }, |
4709 | { Bad_Opcode }, | |
6c30d220 | 4710 | { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) }, |
c0f3af97 L |
4711 | }, |
4712 | ||
592a252b | 4713 | /* PREFIX_VEX_0F73_REG_7 */ |
c0f3af97 | 4714 | { |
592d1631 L |
4715 | { Bad_Opcode }, |
4716 | { Bad_Opcode }, | |
6c30d220 | 4717 | { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) }, |
c0f3af97 L |
4718 | }, |
4719 | ||
592a252b | 4720 | /* PREFIX_VEX_0F74 */ |
c0f3af97 | 4721 | { |
592d1631 L |
4722 | { Bad_Opcode }, |
4723 | { Bad_Opcode }, | |
6c30d220 | 4724 | { VEX_W_TABLE (VEX_W_0F74_P_2) }, |
c0f3af97 L |
4725 | }, |
4726 | ||
592a252b | 4727 | /* PREFIX_VEX_0F75 */ |
c0f3af97 | 4728 | { |
592d1631 L |
4729 | { Bad_Opcode }, |
4730 | { Bad_Opcode }, | |
6c30d220 | 4731 | { VEX_W_TABLE (VEX_W_0F75_P_2) }, |
c0f3af97 L |
4732 | }, |
4733 | ||
592a252b | 4734 | /* PREFIX_VEX_0F76 */ |
c0f3af97 | 4735 | { |
592d1631 L |
4736 | { Bad_Opcode }, |
4737 | { Bad_Opcode }, | |
6c30d220 | 4738 | { VEX_W_TABLE (VEX_W_0F76_P_2) }, |
c0f3af97 L |
4739 | }, |
4740 | ||
592a252b | 4741 | /* PREFIX_VEX_0F77 */ |
c0f3af97 | 4742 | { |
592a252b | 4743 | { VEX_W_TABLE (VEX_W_0F77_P_0) }, |
c0f3af97 L |
4744 | }, |
4745 | ||
592a252b | 4746 | /* PREFIX_VEX_0F7C */ |
c0f3af97 | 4747 | { |
592d1631 L |
4748 | { Bad_Opcode }, |
4749 | { Bad_Opcode }, | |
592a252b L |
4750 | { VEX_W_TABLE (VEX_W_0F7C_P_2) }, |
4751 | { VEX_W_TABLE (VEX_W_0F7C_P_3) }, | |
c0f3af97 L |
4752 | }, |
4753 | ||
592a252b | 4754 | /* PREFIX_VEX_0F7D */ |
c0f3af97 | 4755 | { |
592d1631 L |
4756 | { Bad_Opcode }, |
4757 | { Bad_Opcode }, | |
592a252b L |
4758 | { VEX_W_TABLE (VEX_W_0F7D_P_2) }, |
4759 | { VEX_W_TABLE (VEX_W_0F7D_P_3) }, | |
c0f3af97 L |
4760 | }, |
4761 | ||
592a252b | 4762 | /* PREFIX_VEX_0F7E */ |
c0f3af97 | 4763 | { |
592d1631 | 4764 | { Bad_Opcode }, |
592a252b L |
4765 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
4766 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, | |
c0f3af97 L |
4767 | }, |
4768 | ||
592a252b | 4769 | /* PREFIX_VEX_0F7F */ |
c0f3af97 | 4770 | { |
592d1631 | 4771 | { Bad_Opcode }, |
592a252b L |
4772 | { VEX_W_TABLE (VEX_W_0F7F_P_1) }, |
4773 | { VEX_W_TABLE (VEX_W_0F7F_P_2) }, | |
c0f3af97 L |
4774 | }, |
4775 | ||
43234a1e L |
4776 | /* PREFIX_VEX_0F90 */ |
4777 | { | |
4778 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, | |
4779 | }, | |
4780 | ||
4781 | /* PREFIX_VEX_0F91 */ | |
4782 | { | |
4783 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, | |
4784 | }, | |
4785 | ||
4786 | /* PREFIX_VEX_0F92 */ | |
4787 | { | |
4788 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, | |
4789 | }, | |
4790 | ||
4791 | /* PREFIX_VEX_0F93 */ | |
4792 | { | |
4793 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, | |
4794 | }, | |
4795 | ||
4796 | /* PREFIX_VEX_0F98 */ | |
4797 | { | |
4798 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, | |
4799 | }, | |
4800 | ||
592a252b | 4801 | /* PREFIX_VEX_0FC2 */ |
c0f3af97 | 4802 | { |
592a252b L |
4803 | { VEX_W_TABLE (VEX_W_0FC2_P_0) }, |
4804 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) }, | |
4805 | { VEX_W_TABLE (VEX_W_0FC2_P_2) }, | |
4806 | { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) }, | |
c0f3af97 L |
4807 | }, |
4808 | ||
592a252b | 4809 | /* PREFIX_VEX_0FC4 */ |
c0f3af97 | 4810 | { |
592d1631 L |
4811 | { Bad_Opcode }, |
4812 | { Bad_Opcode }, | |
592a252b | 4813 | { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, |
c0f3af97 L |
4814 | }, |
4815 | ||
592a252b | 4816 | /* PREFIX_VEX_0FC5 */ |
c0f3af97 | 4817 | { |
592d1631 L |
4818 | { Bad_Opcode }, |
4819 | { Bad_Opcode }, | |
592a252b | 4820 | { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, |
c0f3af97 L |
4821 | }, |
4822 | ||
592a252b | 4823 | /* PREFIX_VEX_0FD0 */ |
c0f3af97 | 4824 | { |
592d1631 L |
4825 | { Bad_Opcode }, |
4826 | { Bad_Opcode }, | |
592a252b L |
4827 | { VEX_W_TABLE (VEX_W_0FD0_P_2) }, |
4828 | { VEX_W_TABLE (VEX_W_0FD0_P_3) }, | |
c0f3af97 L |
4829 | }, |
4830 | ||
592a252b | 4831 | /* PREFIX_VEX_0FD1 */ |
c0f3af97 | 4832 | { |
592d1631 L |
4833 | { Bad_Opcode }, |
4834 | { Bad_Opcode }, | |
6c30d220 | 4835 | { VEX_W_TABLE (VEX_W_0FD1_P_2) }, |
c0f3af97 L |
4836 | }, |
4837 | ||
592a252b | 4838 | /* PREFIX_VEX_0FD2 */ |
c0f3af97 | 4839 | { |
592d1631 L |
4840 | { Bad_Opcode }, |
4841 | { Bad_Opcode }, | |
6c30d220 | 4842 | { VEX_W_TABLE (VEX_W_0FD2_P_2) }, |
c0f3af97 L |
4843 | }, |
4844 | ||
592a252b | 4845 | /* PREFIX_VEX_0FD3 */ |
c0f3af97 | 4846 | { |
592d1631 L |
4847 | { Bad_Opcode }, |
4848 | { Bad_Opcode }, | |
6c30d220 | 4849 | { VEX_W_TABLE (VEX_W_0FD3_P_2) }, |
c0f3af97 L |
4850 | }, |
4851 | ||
592a252b | 4852 | /* PREFIX_VEX_0FD4 */ |
c0f3af97 | 4853 | { |
592d1631 L |
4854 | { Bad_Opcode }, |
4855 | { Bad_Opcode }, | |
6c30d220 | 4856 | { VEX_W_TABLE (VEX_W_0FD4_P_2) }, |
c0f3af97 L |
4857 | }, |
4858 | ||
592a252b | 4859 | /* PREFIX_VEX_0FD5 */ |
c0f3af97 | 4860 | { |
592d1631 L |
4861 | { Bad_Opcode }, |
4862 | { Bad_Opcode }, | |
6c30d220 | 4863 | { VEX_W_TABLE (VEX_W_0FD5_P_2) }, |
c0f3af97 L |
4864 | }, |
4865 | ||
592a252b | 4866 | /* PREFIX_VEX_0FD6 */ |
c0f3af97 | 4867 | { |
592d1631 L |
4868 | { Bad_Opcode }, |
4869 | { Bad_Opcode }, | |
592a252b | 4870 | { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, |
c0f3af97 L |
4871 | }, |
4872 | ||
592a252b | 4873 | /* PREFIX_VEX_0FD7 */ |
c0f3af97 | 4874 | { |
592d1631 L |
4875 | { Bad_Opcode }, |
4876 | { Bad_Opcode }, | |
592a252b | 4877 | { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, |
c0f3af97 L |
4878 | }, |
4879 | ||
592a252b | 4880 | /* PREFIX_VEX_0FD8 */ |
c0f3af97 | 4881 | { |
592d1631 L |
4882 | { Bad_Opcode }, |
4883 | { Bad_Opcode }, | |
6c30d220 | 4884 | { VEX_W_TABLE (VEX_W_0FD8_P_2) }, |
c0f3af97 L |
4885 | }, |
4886 | ||
592a252b | 4887 | /* PREFIX_VEX_0FD9 */ |
c0f3af97 | 4888 | { |
592d1631 L |
4889 | { Bad_Opcode }, |
4890 | { Bad_Opcode }, | |
6c30d220 | 4891 | { VEX_W_TABLE (VEX_W_0FD9_P_2) }, |
c0f3af97 L |
4892 | }, |
4893 | ||
592a252b | 4894 | /* PREFIX_VEX_0FDA */ |
c0f3af97 | 4895 | { |
592d1631 L |
4896 | { Bad_Opcode }, |
4897 | { Bad_Opcode }, | |
6c30d220 | 4898 | { VEX_W_TABLE (VEX_W_0FDA_P_2) }, |
c0f3af97 L |
4899 | }, |
4900 | ||
592a252b | 4901 | /* PREFIX_VEX_0FDB */ |
c0f3af97 | 4902 | { |
592d1631 L |
4903 | { Bad_Opcode }, |
4904 | { Bad_Opcode }, | |
6c30d220 | 4905 | { VEX_W_TABLE (VEX_W_0FDB_P_2) }, |
c0f3af97 L |
4906 | }, |
4907 | ||
592a252b | 4908 | /* PREFIX_VEX_0FDC */ |
c0f3af97 | 4909 | { |
592d1631 L |
4910 | { Bad_Opcode }, |
4911 | { Bad_Opcode }, | |
6c30d220 | 4912 | { VEX_W_TABLE (VEX_W_0FDC_P_2) }, |
c0f3af97 L |
4913 | }, |
4914 | ||
592a252b | 4915 | /* PREFIX_VEX_0FDD */ |
c0f3af97 | 4916 | { |
592d1631 L |
4917 | { Bad_Opcode }, |
4918 | { Bad_Opcode }, | |
6c30d220 | 4919 | { VEX_W_TABLE (VEX_W_0FDD_P_2) }, |
c0f3af97 L |
4920 | }, |
4921 | ||
592a252b | 4922 | /* PREFIX_VEX_0FDE */ |
c0f3af97 | 4923 | { |
592d1631 L |
4924 | { Bad_Opcode }, |
4925 | { Bad_Opcode }, | |
6c30d220 | 4926 | { VEX_W_TABLE (VEX_W_0FDE_P_2) }, |
c0f3af97 L |
4927 | }, |
4928 | ||
592a252b | 4929 | /* PREFIX_VEX_0FDF */ |
c0f3af97 | 4930 | { |
592d1631 L |
4931 | { Bad_Opcode }, |
4932 | { Bad_Opcode }, | |
6c30d220 | 4933 | { VEX_W_TABLE (VEX_W_0FDF_P_2) }, |
c0f3af97 L |
4934 | }, |
4935 | ||
592a252b | 4936 | /* PREFIX_VEX_0FE0 */ |
c0f3af97 | 4937 | { |
592d1631 L |
4938 | { Bad_Opcode }, |
4939 | { Bad_Opcode }, | |
6c30d220 | 4940 | { VEX_W_TABLE (VEX_W_0FE0_P_2) }, |
c0f3af97 L |
4941 | }, |
4942 | ||
592a252b | 4943 | /* PREFIX_VEX_0FE1 */ |
c0f3af97 | 4944 | { |
592d1631 L |
4945 | { Bad_Opcode }, |
4946 | { Bad_Opcode }, | |
6c30d220 | 4947 | { VEX_W_TABLE (VEX_W_0FE1_P_2) }, |
c0f3af97 L |
4948 | }, |
4949 | ||
592a252b | 4950 | /* PREFIX_VEX_0FE2 */ |
c0f3af97 | 4951 | { |
592d1631 L |
4952 | { Bad_Opcode }, |
4953 | { Bad_Opcode }, | |
6c30d220 | 4954 | { VEX_W_TABLE (VEX_W_0FE2_P_2) }, |
c0f3af97 L |
4955 | }, |
4956 | ||
592a252b | 4957 | /* PREFIX_VEX_0FE3 */ |
c0f3af97 | 4958 | { |
592d1631 L |
4959 | { Bad_Opcode }, |
4960 | { Bad_Opcode }, | |
6c30d220 | 4961 | { VEX_W_TABLE (VEX_W_0FE3_P_2) }, |
c0f3af97 L |
4962 | }, |
4963 | ||
592a252b | 4964 | /* PREFIX_VEX_0FE4 */ |
c0f3af97 | 4965 | { |
592d1631 L |
4966 | { Bad_Opcode }, |
4967 | { Bad_Opcode }, | |
6c30d220 | 4968 | { VEX_W_TABLE (VEX_W_0FE4_P_2) }, |
c0f3af97 L |
4969 | }, |
4970 | ||
592a252b | 4971 | /* PREFIX_VEX_0FE5 */ |
c0f3af97 | 4972 | { |
592d1631 L |
4973 | { Bad_Opcode }, |
4974 | { Bad_Opcode }, | |
6c30d220 | 4975 | { VEX_W_TABLE (VEX_W_0FE5_P_2) }, |
c0f3af97 L |
4976 | }, |
4977 | ||
592a252b | 4978 | /* PREFIX_VEX_0FE6 */ |
c0f3af97 | 4979 | { |
592d1631 | 4980 | { Bad_Opcode }, |
592a252b L |
4981 | { VEX_W_TABLE (VEX_W_0FE6_P_1) }, |
4982 | { VEX_W_TABLE (VEX_W_0FE6_P_2) }, | |
4983 | { VEX_W_TABLE (VEX_W_0FE6_P_3) }, | |
c0f3af97 L |
4984 | }, |
4985 | ||
592a252b | 4986 | /* PREFIX_VEX_0FE7 */ |
c0f3af97 | 4987 | { |
592d1631 L |
4988 | { Bad_Opcode }, |
4989 | { Bad_Opcode }, | |
592a252b | 4990 | { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, |
c0f3af97 L |
4991 | }, |
4992 | ||
592a252b | 4993 | /* PREFIX_VEX_0FE8 */ |
c0f3af97 | 4994 | { |
592d1631 L |
4995 | { Bad_Opcode }, |
4996 | { Bad_Opcode }, | |
6c30d220 | 4997 | { VEX_W_TABLE (VEX_W_0FE8_P_2) }, |
c0f3af97 L |
4998 | }, |
4999 | ||
592a252b | 5000 | /* PREFIX_VEX_0FE9 */ |
c0f3af97 | 5001 | { |
592d1631 L |
5002 | { Bad_Opcode }, |
5003 | { Bad_Opcode }, | |
6c30d220 | 5004 | { VEX_W_TABLE (VEX_W_0FE9_P_2) }, |
c0f3af97 L |
5005 | }, |
5006 | ||
592a252b | 5007 | /* PREFIX_VEX_0FEA */ |
c0f3af97 | 5008 | { |
592d1631 L |
5009 | { Bad_Opcode }, |
5010 | { Bad_Opcode }, | |
6c30d220 | 5011 | { VEX_W_TABLE (VEX_W_0FEA_P_2) }, |
c0f3af97 L |
5012 | }, |
5013 | ||
592a252b | 5014 | /* PREFIX_VEX_0FEB */ |
c0f3af97 | 5015 | { |
592d1631 L |
5016 | { Bad_Opcode }, |
5017 | { Bad_Opcode }, | |
6c30d220 | 5018 | { VEX_W_TABLE (VEX_W_0FEB_P_2) }, |
c0f3af97 L |
5019 | }, |
5020 | ||
592a252b | 5021 | /* PREFIX_VEX_0FEC */ |
c0f3af97 | 5022 | { |
592d1631 L |
5023 | { Bad_Opcode }, |
5024 | { Bad_Opcode }, | |
6c30d220 | 5025 | { VEX_W_TABLE (VEX_W_0FEC_P_2) }, |
c0f3af97 L |
5026 | }, |
5027 | ||
592a252b | 5028 | /* PREFIX_VEX_0FED */ |
c0f3af97 | 5029 | { |
592d1631 L |
5030 | { Bad_Opcode }, |
5031 | { Bad_Opcode }, | |
6c30d220 | 5032 | { VEX_W_TABLE (VEX_W_0FED_P_2) }, |
c0f3af97 L |
5033 | }, |
5034 | ||
592a252b | 5035 | /* PREFIX_VEX_0FEE */ |
c0f3af97 | 5036 | { |
592d1631 L |
5037 | { Bad_Opcode }, |
5038 | { Bad_Opcode }, | |
6c30d220 | 5039 | { VEX_W_TABLE (VEX_W_0FEE_P_2) }, |
c0f3af97 L |
5040 | }, |
5041 | ||
592a252b | 5042 | /* PREFIX_VEX_0FEF */ |
c0f3af97 | 5043 | { |
592d1631 L |
5044 | { Bad_Opcode }, |
5045 | { Bad_Opcode }, | |
6c30d220 | 5046 | { VEX_W_TABLE (VEX_W_0FEF_P_2) }, |
c0f3af97 L |
5047 | }, |
5048 | ||
592a252b | 5049 | /* PREFIX_VEX_0FF0 */ |
c0f3af97 | 5050 | { |
592d1631 L |
5051 | { Bad_Opcode }, |
5052 | { Bad_Opcode }, | |
5053 | { Bad_Opcode }, | |
592a252b | 5054 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, |
c0f3af97 L |
5055 | }, |
5056 | ||
592a252b | 5057 | /* PREFIX_VEX_0FF1 */ |
c0f3af97 | 5058 | { |
592d1631 L |
5059 | { Bad_Opcode }, |
5060 | { Bad_Opcode }, | |
6c30d220 | 5061 | { VEX_W_TABLE (VEX_W_0FF1_P_2) }, |
c0f3af97 L |
5062 | }, |
5063 | ||
592a252b | 5064 | /* PREFIX_VEX_0FF2 */ |
c0f3af97 | 5065 | { |
592d1631 L |
5066 | { Bad_Opcode }, |
5067 | { Bad_Opcode }, | |
6c30d220 | 5068 | { VEX_W_TABLE (VEX_W_0FF2_P_2) }, |
c0f3af97 L |
5069 | }, |
5070 | ||
592a252b | 5071 | /* PREFIX_VEX_0FF3 */ |
c0f3af97 | 5072 | { |
592d1631 L |
5073 | { Bad_Opcode }, |
5074 | { Bad_Opcode }, | |
6c30d220 | 5075 | { VEX_W_TABLE (VEX_W_0FF3_P_2) }, |
c0f3af97 L |
5076 | }, |
5077 | ||
592a252b | 5078 | /* PREFIX_VEX_0FF4 */ |
c0f3af97 | 5079 | { |
592d1631 L |
5080 | { Bad_Opcode }, |
5081 | { Bad_Opcode }, | |
6c30d220 | 5082 | { VEX_W_TABLE (VEX_W_0FF4_P_2) }, |
c0f3af97 L |
5083 | }, |
5084 | ||
592a252b | 5085 | /* PREFIX_VEX_0FF5 */ |
c0f3af97 | 5086 | { |
592d1631 L |
5087 | { Bad_Opcode }, |
5088 | { Bad_Opcode }, | |
6c30d220 | 5089 | { VEX_W_TABLE (VEX_W_0FF5_P_2) }, |
c0f3af97 L |
5090 | }, |
5091 | ||
592a252b | 5092 | /* PREFIX_VEX_0FF6 */ |
c0f3af97 | 5093 | { |
592d1631 L |
5094 | { Bad_Opcode }, |
5095 | { Bad_Opcode }, | |
6c30d220 | 5096 | { VEX_W_TABLE (VEX_W_0FF6_P_2) }, |
c0f3af97 L |
5097 | }, |
5098 | ||
592a252b | 5099 | /* PREFIX_VEX_0FF7 */ |
c0f3af97 | 5100 | { |
592d1631 L |
5101 | { Bad_Opcode }, |
5102 | { Bad_Opcode }, | |
592a252b | 5103 | { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, |
c0f3af97 L |
5104 | }, |
5105 | ||
592a252b | 5106 | /* PREFIX_VEX_0FF8 */ |
c0f3af97 | 5107 | { |
592d1631 L |
5108 | { Bad_Opcode }, |
5109 | { Bad_Opcode }, | |
6c30d220 | 5110 | { VEX_W_TABLE (VEX_W_0FF8_P_2) }, |
c0f3af97 L |
5111 | }, |
5112 | ||
592a252b | 5113 | /* PREFIX_VEX_0FF9 */ |
c0f3af97 | 5114 | { |
592d1631 L |
5115 | { Bad_Opcode }, |
5116 | { Bad_Opcode }, | |
6c30d220 | 5117 | { VEX_W_TABLE (VEX_W_0FF9_P_2) }, |
c0f3af97 L |
5118 | }, |
5119 | ||
592a252b | 5120 | /* PREFIX_VEX_0FFA */ |
c0f3af97 | 5121 | { |
592d1631 L |
5122 | { Bad_Opcode }, |
5123 | { Bad_Opcode }, | |
6c30d220 | 5124 | { VEX_W_TABLE (VEX_W_0FFA_P_2) }, |
c0f3af97 L |
5125 | }, |
5126 | ||
592a252b | 5127 | /* PREFIX_VEX_0FFB */ |
c0f3af97 | 5128 | { |
592d1631 L |
5129 | { Bad_Opcode }, |
5130 | { Bad_Opcode }, | |
6c30d220 | 5131 | { VEX_W_TABLE (VEX_W_0FFB_P_2) }, |
c0f3af97 L |
5132 | }, |
5133 | ||
592a252b | 5134 | /* PREFIX_VEX_0FFC */ |
c0f3af97 | 5135 | { |
592d1631 L |
5136 | { Bad_Opcode }, |
5137 | { Bad_Opcode }, | |
6c30d220 | 5138 | { VEX_W_TABLE (VEX_W_0FFC_P_2) }, |
c0f3af97 L |
5139 | }, |
5140 | ||
592a252b | 5141 | /* PREFIX_VEX_0FFD */ |
c0f3af97 | 5142 | { |
592d1631 L |
5143 | { Bad_Opcode }, |
5144 | { Bad_Opcode }, | |
6c30d220 | 5145 | { VEX_W_TABLE (VEX_W_0FFD_P_2) }, |
c0f3af97 L |
5146 | }, |
5147 | ||
592a252b | 5148 | /* PREFIX_VEX_0FFE */ |
c0f3af97 | 5149 | { |
592d1631 L |
5150 | { Bad_Opcode }, |
5151 | { Bad_Opcode }, | |
6c30d220 | 5152 | { VEX_W_TABLE (VEX_W_0FFE_P_2) }, |
c0f3af97 L |
5153 | }, |
5154 | ||
592a252b | 5155 | /* PREFIX_VEX_0F3800 */ |
c0f3af97 | 5156 | { |
592d1631 L |
5157 | { Bad_Opcode }, |
5158 | { Bad_Opcode }, | |
6c30d220 | 5159 | { VEX_W_TABLE (VEX_W_0F3800_P_2) }, |
c0f3af97 L |
5160 | }, |
5161 | ||
592a252b | 5162 | /* PREFIX_VEX_0F3801 */ |
c0f3af97 | 5163 | { |
592d1631 L |
5164 | { Bad_Opcode }, |
5165 | { Bad_Opcode }, | |
6c30d220 | 5166 | { VEX_W_TABLE (VEX_W_0F3801_P_2) }, |
c0f3af97 L |
5167 | }, |
5168 | ||
592a252b | 5169 | /* PREFIX_VEX_0F3802 */ |
c0f3af97 | 5170 | { |
592d1631 L |
5171 | { Bad_Opcode }, |
5172 | { Bad_Opcode }, | |
6c30d220 | 5173 | { VEX_W_TABLE (VEX_W_0F3802_P_2) }, |
c0f3af97 L |
5174 | }, |
5175 | ||
592a252b | 5176 | /* PREFIX_VEX_0F3803 */ |
c0f3af97 | 5177 | { |
592d1631 L |
5178 | { Bad_Opcode }, |
5179 | { Bad_Opcode }, | |
6c30d220 | 5180 | { VEX_W_TABLE (VEX_W_0F3803_P_2) }, |
c0f3af97 L |
5181 | }, |
5182 | ||
592a252b | 5183 | /* PREFIX_VEX_0F3804 */ |
c0f3af97 | 5184 | { |
592d1631 L |
5185 | { Bad_Opcode }, |
5186 | { Bad_Opcode }, | |
6c30d220 | 5187 | { VEX_W_TABLE (VEX_W_0F3804_P_2) }, |
c0f3af97 L |
5188 | }, |
5189 | ||
592a252b | 5190 | /* PREFIX_VEX_0F3805 */ |
c0f3af97 | 5191 | { |
592d1631 L |
5192 | { Bad_Opcode }, |
5193 | { Bad_Opcode }, | |
6c30d220 | 5194 | { VEX_W_TABLE (VEX_W_0F3805_P_2) }, |
c0f3af97 L |
5195 | }, |
5196 | ||
592a252b | 5197 | /* PREFIX_VEX_0F3806 */ |
c0f3af97 | 5198 | { |
592d1631 L |
5199 | { Bad_Opcode }, |
5200 | { Bad_Opcode }, | |
6c30d220 | 5201 | { VEX_W_TABLE (VEX_W_0F3806_P_2) }, |
c0f3af97 L |
5202 | }, |
5203 | ||
592a252b | 5204 | /* PREFIX_VEX_0F3807 */ |
c0f3af97 | 5205 | { |
592d1631 L |
5206 | { Bad_Opcode }, |
5207 | { Bad_Opcode }, | |
6c30d220 | 5208 | { VEX_W_TABLE (VEX_W_0F3807_P_2) }, |
c0f3af97 L |
5209 | }, |
5210 | ||
592a252b | 5211 | /* PREFIX_VEX_0F3808 */ |
c0f3af97 | 5212 | { |
592d1631 L |
5213 | { Bad_Opcode }, |
5214 | { Bad_Opcode }, | |
6c30d220 | 5215 | { VEX_W_TABLE (VEX_W_0F3808_P_2) }, |
c0f3af97 L |
5216 | }, |
5217 | ||
592a252b | 5218 | /* PREFIX_VEX_0F3809 */ |
c0f3af97 | 5219 | { |
592d1631 L |
5220 | { Bad_Opcode }, |
5221 | { Bad_Opcode }, | |
6c30d220 | 5222 | { VEX_W_TABLE (VEX_W_0F3809_P_2) }, |
c0f3af97 L |
5223 | }, |
5224 | ||
592a252b | 5225 | /* PREFIX_VEX_0F380A */ |
c0f3af97 | 5226 | { |
592d1631 L |
5227 | { Bad_Opcode }, |
5228 | { Bad_Opcode }, | |
6c30d220 | 5229 | { VEX_W_TABLE (VEX_W_0F380A_P_2) }, |
c0f3af97 L |
5230 | }, |
5231 | ||
592a252b | 5232 | /* PREFIX_VEX_0F380B */ |
c0f3af97 | 5233 | { |
592d1631 L |
5234 | { Bad_Opcode }, |
5235 | { Bad_Opcode }, | |
6c30d220 | 5236 | { VEX_W_TABLE (VEX_W_0F380B_P_2) }, |
c0f3af97 L |
5237 | }, |
5238 | ||
592a252b | 5239 | /* PREFIX_VEX_0F380C */ |
c0f3af97 | 5240 | { |
592d1631 L |
5241 | { Bad_Opcode }, |
5242 | { Bad_Opcode }, | |
592a252b | 5243 | { VEX_W_TABLE (VEX_W_0F380C_P_2) }, |
c0f3af97 L |
5244 | }, |
5245 | ||
592a252b | 5246 | /* PREFIX_VEX_0F380D */ |
c0f3af97 | 5247 | { |
592d1631 L |
5248 | { Bad_Opcode }, |
5249 | { Bad_Opcode }, | |
592a252b | 5250 | { VEX_W_TABLE (VEX_W_0F380D_P_2) }, |
c0f3af97 L |
5251 | }, |
5252 | ||
592a252b | 5253 | /* PREFIX_VEX_0F380E */ |
c0f3af97 | 5254 | { |
592d1631 L |
5255 | { Bad_Opcode }, |
5256 | { Bad_Opcode }, | |
592a252b | 5257 | { VEX_W_TABLE (VEX_W_0F380E_P_2) }, |
c0f3af97 L |
5258 | }, |
5259 | ||
592a252b | 5260 | /* PREFIX_VEX_0F380F */ |
c0f3af97 | 5261 | { |
592d1631 L |
5262 | { Bad_Opcode }, |
5263 | { Bad_Opcode }, | |
592a252b | 5264 | { VEX_W_TABLE (VEX_W_0F380F_P_2) }, |
c0f3af97 L |
5265 | }, |
5266 | ||
592a252b | 5267 | /* PREFIX_VEX_0F3813 */ |
c7b8aa3a L |
5268 | { |
5269 | { Bad_Opcode }, | |
5270 | { Bad_Opcode }, | |
5271 | { "vcvtph2ps", { XM, EXxmmq } }, | |
5272 | }, | |
5273 | ||
6c30d220 L |
5274 | /* PREFIX_VEX_0F3816 */ |
5275 | { | |
5276 | { Bad_Opcode }, | |
5277 | { Bad_Opcode }, | |
5278 | { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) }, | |
5279 | }, | |
5280 | ||
592a252b | 5281 | /* PREFIX_VEX_0F3817 */ |
c0f3af97 | 5282 | { |
592d1631 L |
5283 | { Bad_Opcode }, |
5284 | { Bad_Opcode }, | |
592a252b | 5285 | { VEX_W_TABLE (VEX_W_0F3817_P_2) }, |
c0f3af97 L |
5286 | }, |
5287 | ||
592a252b | 5288 | /* PREFIX_VEX_0F3818 */ |
c0f3af97 | 5289 | { |
592d1631 L |
5290 | { Bad_Opcode }, |
5291 | { Bad_Opcode }, | |
6c30d220 | 5292 | { VEX_W_TABLE (VEX_W_0F3818_P_2) }, |
c0f3af97 L |
5293 | }, |
5294 | ||
592a252b | 5295 | /* PREFIX_VEX_0F3819 */ |
c0f3af97 | 5296 | { |
592d1631 L |
5297 | { Bad_Opcode }, |
5298 | { Bad_Opcode }, | |
6c30d220 | 5299 | { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) }, |
c0f3af97 L |
5300 | }, |
5301 | ||
592a252b | 5302 | /* PREFIX_VEX_0F381A */ |
c0f3af97 | 5303 | { |
592d1631 L |
5304 | { Bad_Opcode }, |
5305 | { Bad_Opcode }, | |
592a252b | 5306 | { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, |
c0f3af97 L |
5307 | }, |
5308 | ||
592a252b | 5309 | /* PREFIX_VEX_0F381C */ |
c0f3af97 | 5310 | { |
592d1631 L |
5311 | { Bad_Opcode }, |
5312 | { Bad_Opcode }, | |
6c30d220 | 5313 | { VEX_W_TABLE (VEX_W_0F381C_P_2) }, |
c0f3af97 L |
5314 | }, |
5315 | ||
592a252b | 5316 | /* PREFIX_VEX_0F381D */ |
c0f3af97 | 5317 | { |
592d1631 L |
5318 | { Bad_Opcode }, |
5319 | { Bad_Opcode }, | |
6c30d220 | 5320 | { VEX_W_TABLE (VEX_W_0F381D_P_2) }, |
c0f3af97 L |
5321 | }, |
5322 | ||
592a252b | 5323 | /* PREFIX_VEX_0F381E */ |
c0f3af97 | 5324 | { |
592d1631 L |
5325 | { Bad_Opcode }, |
5326 | { Bad_Opcode }, | |
6c30d220 | 5327 | { VEX_W_TABLE (VEX_W_0F381E_P_2) }, |
c0f3af97 L |
5328 | }, |
5329 | ||
592a252b | 5330 | /* PREFIX_VEX_0F3820 */ |
c0f3af97 | 5331 | { |
592d1631 L |
5332 | { Bad_Opcode }, |
5333 | { Bad_Opcode }, | |
6c30d220 | 5334 | { VEX_W_TABLE (VEX_W_0F3820_P_2) }, |
c0f3af97 L |
5335 | }, |
5336 | ||
592a252b | 5337 | /* PREFIX_VEX_0F3821 */ |
c0f3af97 | 5338 | { |
592d1631 L |
5339 | { Bad_Opcode }, |
5340 | { Bad_Opcode }, | |
6c30d220 | 5341 | { VEX_W_TABLE (VEX_W_0F3821_P_2) }, |
c0f3af97 L |
5342 | }, |
5343 | ||
592a252b | 5344 | /* PREFIX_VEX_0F3822 */ |
c0f3af97 | 5345 | { |
592d1631 L |
5346 | { Bad_Opcode }, |
5347 | { Bad_Opcode }, | |
6c30d220 | 5348 | { VEX_W_TABLE (VEX_W_0F3822_P_2) }, |
c0f3af97 L |
5349 | }, |
5350 | ||
592a252b | 5351 | /* PREFIX_VEX_0F3823 */ |
c0f3af97 | 5352 | { |
592d1631 L |
5353 | { Bad_Opcode }, |
5354 | { Bad_Opcode }, | |
6c30d220 | 5355 | { VEX_W_TABLE (VEX_W_0F3823_P_2) }, |
c0f3af97 L |
5356 | }, |
5357 | ||
592a252b | 5358 | /* PREFIX_VEX_0F3824 */ |
c0f3af97 | 5359 | { |
592d1631 L |
5360 | { Bad_Opcode }, |
5361 | { Bad_Opcode }, | |
6c30d220 | 5362 | { VEX_W_TABLE (VEX_W_0F3824_P_2) }, |
c0f3af97 L |
5363 | }, |
5364 | ||
592a252b | 5365 | /* PREFIX_VEX_0F3825 */ |
c0f3af97 | 5366 | { |
592d1631 L |
5367 | { Bad_Opcode }, |
5368 | { Bad_Opcode }, | |
6c30d220 | 5369 | { VEX_W_TABLE (VEX_W_0F3825_P_2) }, |
c0f3af97 L |
5370 | }, |
5371 | ||
592a252b | 5372 | /* PREFIX_VEX_0F3828 */ |
c0f3af97 | 5373 | { |
592d1631 L |
5374 | { Bad_Opcode }, |
5375 | { Bad_Opcode }, | |
6c30d220 | 5376 | { VEX_W_TABLE (VEX_W_0F3828_P_2) }, |
c0f3af97 L |
5377 | }, |
5378 | ||
592a252b | 5379 | /* PREFIX_VEX_0F3829 */ |
c0f3af97 | 5380 | { |
592d1631 L |
5381 | { Bad_Opcode }, |
5382 | { Bad_Opcode }, | |
6c30d220 | 5383 | { VEX_W_TABLE (VEX_W_0F3829_P_2) }, |
c0f3af97 L |
5384 | }, |
5385 | ||
592a252b | 5386 | /* PREFIX_VEX_0F382A */ |
c0f3af97 | 5387 | { |
592d1631 L |
5388 | { Bad_Opcode }, |
5389 | { Bad_Opcode }, | |
592a252b | 5390 | { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, |
c0f3af97 L |
5391 | }, |
5392 | ||
592a252b | 5393 | /* PREFIX_VEX_0F382B */ |
c0f3af97 | 5394 | { |
592d1631 L |
5395 | { Bad_Opcode }, |
5396 | { Bad_Opcode }, | |
6c30d220 | 5397 | { VEX_W_TABLE (VEX_W_0F382B_P_2) }, |
c0f3af97 L |
5398 | }, |
5399 | ||
592a252b | 5400 | /* PREFIX_VEX_0F382C */ |
c0f3af97 | 5401 | { |
592d1631 L |
5402 | { Bad_Opcode }, |
5403 | { Bad_Opcode }, | |
592a252b | 5404 | { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, |
c0f3af97 L |
5405 | }, |
5406 | ||
592a252b | 5407 | /* PREFIX_VEX_0F382D */ |
c0f3af97 | 5408 | { |
592d1631 L |
5409 | { Bad_Opcode }, |
5410 | { Bad_Opcode }, | |
592a252b | 5411 | { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, |
c0f3af97 L |
5412 | }, |
5413 | ||
592a252b | 5414 | /* PREFIX_VEX_0F382E */ |
c0f3af97 | 5415 | { |
592d1631 L |
5416 | { Bad_Opcode }, |
5417 | { Bad_Opcode }, | |
592a252b | 5418 | { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, |
c0f3af97 L |
5419 | }, |
5420 | ||
592a252b | 5421 | /* PREFIX_VEX_0F382F */ |
c0f3af97 | 5422 | { |
592d1631 L |
5423 | { Bad_Opcode }, |
5424 | { Bad_Opcode }, | |
592a252b | 5425 | { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, |
c0f3af97 L |
5426 | }, |
5427 | ||
592a252b | 5428 | /* PREFIX_VEX_0F3830 */ |
c0f3af97 | 5429 | { |
592d1631 L |
5430 | { Bad_Opcode }, |
5431 | { Bad_Opcode }, | |
6c30d220 | 5432 | { VEX_W_TABLE (VEX_W_0F3830_P_2) }, |
c0f3af97 L |
5433 | }, |
5434 | ||
592a252b | 5435 | /* PREFIX_VEX_0F3831 */ |
c0f3af97 | 5436 | { |
592d1631 L |
5437 | { Bad_Opcode }, |
5438 | { Bad_Opcode }, | |
6c30d220 | 5439 | { VEX_W_TABLE (VEX_W_0F3831_P_2) }, |
c0f3af97 L |
5440 | }, |
5441 | ||
592a252b | 5442 | /* PREFIX_VEX_0F3832 */ |
c0f3af97 | 5443 | { |
592d1631 L |
5444 | { Bad_Opcode }, |
5445 | { Bad_Opcode }, | |
6c30d220 | 5446 | { VEX_W_TABLE (VEX_W_0F3832_P_2) }, |
c0f3af97 L |
5447 | }, |
5448 | ||
592a252b | 5449 | /* PREFIX_VEX_0F3833 */ |
c0f3af97 | 5450 | { |
592d1631 L |
5451 | { Bad_Opcode }, |
5452 | { Bad_Opcode }, | |
6c30d220 | 5453 | { VEX_W_TABLE (VEX_W_0F3833_P_2) }, |
c0f3af97 L |
5454 | }, |
5455 | ||
592a252b | 5456 | /* PREFIX_VEX_0F3834 */ |
c0f3af97 | 5457 | { |
592d1631 L |
5458 | { Bad_Opcode }, |
5459 | { Bad_Opcode }, | |
6c30d220 | 5460 | { VEX_W_TABLE (VEX_W_0F3834_P_2) }, |
c0f3af97 L |
5461 | }, |
5462 | ||
592a252b | 5463 | /* PREFIX_VEX_0F3835 */ |
c0f3af97 | 5464 | { |
592d1631 L |
5465 | { Bad_Opcode }, |
5466 | { Bad_Opcode }, | |
6c30d220 L |
5467 | { VEX_W_TABLE (VEX_W_0F3835_P_2) }, |
5468 | }, | |
5469 | ||
5470 | /* PREFIX_VEX_0F3836 */ | |
5471 | { | |
5472 | { Bad_Opcode }, | |
5473 | { Bad_Opcode }, | |
5474 | { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) }, | |
c0f3af97 L |
5475 | }, |
5476 | ||
592a252b | 5477 | /* PREFIX_VEX_0F3837 */ |
c0f3af97 | 5478 | { |
592d1631 L |
5479 | { Bad_Opcode }, |
5480 | { Bad_Opcode }, | |
6c30d220 | 5481 | { VEX_W_TABLE (VEX_W_0F3837_P_2) }, |
c0f3af97 L |
5482 | }, |
5483 | ||
592a252b | 5484 | /* PREFIX_VEX_0F3838 */ |
c0f3af97 | 5485 | { |
592d1631 L |
5486 | { Bad_Opcode }, |
5487 | { Bad_Opcode }, | |
6c30d220 | 5488 | { VEX_W_TABLE (VEX_W_0F3838_P_2) }, |
c0f3af97 L |
5489 | }, |
5490 | ||
592a252b | 5491 | /* PREFIX_VEX_0F3839 */ |
c0f3af97 | 5492 | { |
592d1631 L |
5493 | { Bad_Opcode }, |
5494 | { Bad_Opcode }, | |
6c30d220 | 5495 | { VEX_W_TABLE (VEX_W_0F3839_P_2) }, |
c0f3af97 L |
5496 | }, |
5497 | ||
592a252b | 5498 | /* PREFIX_VEX_0F383A */ |
c0f3af97 | 5499 | { |
592d1631 L |
5500 | { Bad_Opcode }, |
5501 | { Bad_Opcode }, | |
6c30d220 | 5502 | { VEX_W_TABLE (VEX_W_0F383A_P_2) }, |
c0f3af97 L |
5503 | }, |
5504 | ||
592a252b | 5505 | /* PREFIX_VEX_0F383B */ |
c0f3af97 | 5506 | { |
592d1631 L |
5507 | { Bad_Opcode }, |
5508 | { Bad_Opcode }, | |
6c30d220 | 5509 | { VEX_W_TABLE (VEX_W_0F383B_P_2) }, |
c0f3af97 L |
5510 | }, |
5511 | ||
592a252b | 5512 | /* PREFIX_VEX_0F383C */ |
c0f3af97 | 5513 | { |
592d1631 L |
5514 | { Bad_Opcode }, |
5515 | { Bad_Opcode }, | |
6c30d220 | 5516 | { VEX_W_TABLE (VEX_W_0F383C_P_2) }, |
c0f3af97 L |
5517 | }, |
5518 | ||
592a252b | 5519 | /* PREFIX_VEX_0F383D */ |
c0f3af97 | 5520 | { |
592d1631 L |
5521 | { Bad_Opcode }, |
5522 | { Bad_Opcode }, | |
6c30d220 | 5523 | { VEX_W_TABLE (VEX_W_0F383D_P_2) }, |
c0f3af97 L |
5524 | }, |
5525 | ||
592a252b | 5526 | /* PREFIX_VEX_0F383E */ |
c0f3af97 | 5527 | { |
592d1631 L |
5528 | { Bad_Opcode }, |
5529 | { Bad_Opcode }, | |
6c30d220 | 5530 | { VEX_W_TABLE (VEX_W_0F383E_P_2) }, |
c0f3af97 L |
5531 | }, |
5532 | ||
592a252b | 5533 | /* PREFIX_VEX_0F383F */ |
c0f3af97 | 5534 | { |
592d1631 L |
5535 | { Bad_Opcode }, |
5536 | { Bad_Opcode }, | |
6c30d220 | 5537 | { VEX_W_TABLE (VEX_W_0F383F_P_2) }, |
c0f3af97 L |
5538 | }, |
5539 | ||
592a252b | 5540 | /* PREFIX_VEX_0F3840 */ |
c0f3af97 | 5541 | { |
592d1631 L |
5542 | { Bad_Opcode }, |
5543 | { Bad_Opcode }, | |
6c30d220 | 5544 | { VEX_W_TABLE (VEX_W_0F3840_P_2) }, |
c0f3af97 L |
5545 | }, |
5546 | ||
592a252b | 5547 | /* PREFIX_VEX_0F3841 */ |
c0f3af97 | 5548 | { |
592d1631 L |
5549 | { Bad_Opcode }, |
5550 | { Bad_Opcode }, | |
592a252b | 5551 | { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, |
c0f3af97 L |
5552 | }, |
5553 | ||
6c30d220 L |
5554 | /* PREFIX_VEX_0F3845 */ |
5555 | { | |
5556 | { Bad_Opcode }, | |
5557 | { Bad_Opcode }, | |
5558 | { "vpsrlv%LW", { XM, Vex, EXx } }, | |
5559 | }, | |
5560 | ||
5561 | /* PREFIX_VEX_0F3846 */ | |
5562 | { | |
5563 | { Bad_Opcode }, | |
5564 | { Bad_Opcode }, | |
5565 | { VEX_W_TABLE (VEX_W_0F3846_P_2) }, | |
5566 | }, | |
5567 | ||
5568 | /* PREFIX_VEX_0F3847 */ | |
5569 | { | |
5570 | { Bad_Opcode }, | |
5571 | { Bad_Opcode }, | |
5572 | { "vpsllv%LW", { XM, Vex, EXx } }, | |
5573 | }, | |
5574 | ||
5575 | /* PREFIX_VEX_0F3858 */ | |
5576 | { | |
5577 | { Bad_Opcode }, | |
5578 | { Bad_Opcode }, | |
5579 | { VEX_W_TABLE (VEX_W_0F3858_P_2) }, | |
5580 | }, | |
5581 | ||
5582 | /* PREFIX_VEX_0F3859 */ | |
5583 | { | |
5584 | { Bad_Opcode }, | |
5585 | { Bad_Opcode }, | |
5586 | { VEX_W_TABLE (VEX_W_0F3859_P_2) }, | |
5587 | }, | |
5588 | ||
5589 | /* PREFIX_VEX_0F385A */ | |
5590 | { | |
5591 | { Bad_Opcode }, | |
5592 | { Bad_Opcode }, | |
5593 | { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) }, | |
5594 | }, | |
5595 | ||
5596 | /* PREFIX_VEX_0F3878 */ | |
5597 | { | |
5598 | { Bad_Opcode }, | |
5599 | { Bad_Opcode }, | |
5600 | { VEX_W_TABLE (VEX_W_0F3878_P_2) }, | |
5601 | }, | |
5602 | ||
5603 | /* PREFIX_VEX_0F3879 */ | |
5604 | { | |
5605 | { Bad_Opcode }, | |
5606 | { Bad_Opcode }, | |
5607 | { VEX_W_TABLE (VEX_W_0F3879_P_2) }, | |
5608 | }, | |
5609 | ||
5610 | /* PREFIX_VEX_0F388C */ | |
5611 | { | |
5612 | { Bad_Opcode }, | |
5613 | { Bad_Opcode }, | |
f7002f42 | 5614 | { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) }, |
6c30d220 L |
5615 | }, |
5616 | ||
5617 | /* PREFIX_VEX_0F388E */ | |
5618 | { | |
5619 | { Bad_Opcode }, | |
5620 | { Bad_Opcode }, | |
f7002f42 | 5621 | { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) }, |
6c30d220 L |
5622 | }, |
5623 | ||
5624 | /* PREFIX_VEX_0F3890 */ | |
5625 | { | |
5626 | { Bad_Opcode }, | |
5627 | { Bad_Opcode }, | |
5628 | { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } }, | |
5629 | }, | |
5630 | ||
5631 | /* PREFIX_VEX_0F3891 */ | |
5632 | { | |
5633 | { Bad_Opcode }, | |
5634 | { Bad_Opcode }, | |
5635 | { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } }, | |
5636 | }, | |
5637 | ||
5638 | /* PREFIX_VEX_0F3892 */ | |
5639 | { | |
5640 | { Bad_Opcode }, | |
5641 | { Bad_Opcode }, | |
5642 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } }, | |
5643 | }, | |
5644 | ||
5645 | /* PREFIX_VEX_0F3893 */ | |
5646 | { | |
5647 | { Bad_Opcode }, | |
5648 | { Bad_Opcode }, | |
5649 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } }, | |
5650 | }, | |
5651 | ||
592a252b | 5652 | /* PREFIX_VEX_0F3896 */ |
a5ff0eb2 | 5653 | { |
592d1631 L |
5654 | { Bad_Opcode }, |
5655 | { Bad_Opcode }, | |
0bfee649 | 5656 | { "vfmaddsub132p%XW", { XM, Vex, EXx } }, |
a5ff0eb2 L |
5657 | }, |
5658 | ||
592a252b | 5659 | /* PREFIX_VEX_0F3897 */ |
a5ff0eb2 | 5660 | { |
592d1631 L |
5661 | { Bad_Opcode }, |
5662 | { Bad_Opcode }, | |
0bfee649 | 5663 | { "vfmsubadd132p%XW", { XM, Vex, EXx } }, |
a5ff0eb2 L |
5664 | }, |
5665 | ||
592a252b | 5666 | /* PREFIX_VEX_0F3898 */ |
a5ff0eb2 | 5667 | { |
592d1631 L |
5668 | { Bad_Opcode }, |
5669 | { Bad_Opcode }, | |
0bfee649 | 5670 | { "vfmadd132p%XW", { XM, Vex, EXx } }, |
a5ff0eb2 L |
5671 | }, |
5672 | ||
592a252b | 5673 | /* PREFIX_VEX_0F3899 */ |
a5ff0eb2 | 5674 | { |
592d1631 L |
5675 | { Bad_Opcode }, |
5676 | { Bad_Opcode }, | |
1c480963 | 5677 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
a5ff0eb2 L |
5678 | }, |
5679 | ||
592a252b | 5680 | /* PREFIX_VEX_0F389A */ |
a5ff0eb2 | 5681 | { |
592d1631 L |
5682 | { Bad_Opcode }, |
5683 | { Bad_Opcode }, | |
0bfee649 | 5684 | { "vfmsub132p%XW", { XM, Vex, EXx } }, |
a5ff0eb2 L |
5685 | }, |
5686 | ||
592a252b | 5687 | /* PREFIX_VEX_0F389B */ |
c0f3af97 | 5688 | { |
592d1631 L |
5689 | { Bad_Opcode }, |
5690 | { Bad_Opcode }, | |
1c480963 | 5691 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5692 | }, |
5693 | ||
592a252b | 5694 | /* PREFIX_VEX_0F389C */ |
c0f3af97 | 5695 | { |
592d1631 L |
5696 | { Bad_Opcode }, |
5697 | { Bad_Opcode }, | |
0bfee649 | 5698 | { "vfnmadd132p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5699 | }, |
5700 | ||
592a252b | 5701 | /* PREFIX_VEX_0F389D */ |
c0f3af97 | 5702 | { |
592d1631 L |
5703 | { Bad_Opcode }, |
5704 | { Bad_Opcode }, | |
1c480963 | 5705 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5706 | }, |
5707 | ||
592a252b | 5708 | /* PREFIX_VEX_0F389E */ |
c0f3af97 | 5709 | { |
592d1631 L |
5710 | { Bad_Opcode }, |
5711 | { Bad_Opcode }, | |
0bfee649 | 5712 | { "vfnmsub132p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5713 | }, |
5714 | ||
592a252b | 5715 | /* PREFIX_VEX_0F389F */ |
c0f3af97 | 5716 | { |
592d1631 L |
5717 | { Bad_Opcode }, |
5718 | { Bad_Opcode }, | |
1c480963 | 5719 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5720 | }, |
5721 | ||
592a252b | 5722 | /* PREFIX_VEX_0F38A6 */ |
c0f3af97 | 5723 | { |
592d1631 L |
5724 | { Bad_Opcode }, |
5725 | { Bad_Opcode }, | |
0bfee649 | 5726 | { "vfmaddsub213p%XW", { XM, Vex, EXx } }, |
592d1631 | 5727 | { Bad_Opcode }, |
c0f3af97 L |
5728 | }, |
5729 | ||
592a252b | 5730 | /* PREFIX_VEX_0F38A7 */ |
c0f3af97 | 5731 | { |
592d1631 L |
5732 | { Bad_Opcode }, |
5733 | { Bad_Opcode }, | |
0bfee649 | 5734 | { "vfmsubadd213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5735 | }, |
5736 | ||
592a252b | 5737 | /* PREFIX_VEX_0F38A8 */ |
c0f3af97 | 5738 | { |
592d1631 L |
5739 | { Bad_Opcode }, |
5740 | { Bad_Opcode }, | |
0bfee649 | 5741 | { "vfmadd213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5742 | }, |
5743 | ||
592a252b | 5744 | /* PREFIX_VEX_0F38A9 */ |
c0f3af97 | 5745 | { |
592d1631 L |
5746 | { Bad_Opcode }, |
5747 | { Bad_Opcode }, | |
1c480963 | 5748 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5749 | }, |
5750 | ||
592a252b | 5751 | /* PREFIX_VEX_0F38AA */ |
c0f3af97 | 5752 | { |
592d1631 L |
5753 | { Bad_Opcode }, |
5754 | { Bad_Opcode }, | |
0bfee649 | 5755 | { "vfmsub213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5756 | }, |
5757 | ||
592a252b | 5758 | /* PREFIX_VEX_0F38AB */ |
c0f3af97 | 5759 | { |
592d1631 L |
5760 | { Bad_Opcode }, |
5761 | { Bad_Opcode }, | |
1c480963 | 5762 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5763 | }, |
5764 | ||
592a252b | 5765 | /* PREFIX_VEX_0F38AC */ |
c0f3af97 | 5766 | { |
592d1631 L |
5767 | { Bad_Opcode }, |
5768 | { Bad_Opcode }, | |
0bfee649 | 5769 | { "vfnmadd213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5770 | }, |
5771 | ||
592a252b | 5772 | /* PREFIX_VEX_0F38AD */ |
c0f3af97 | 5773 | { |
592d1631 L |
5774 | { Bad_Opcode }, |
5775 | { Bad_Opcode }, | |
1c480963 | 5776 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5777 | }, |
5778 | ||
592a252b | 5779 | /* PREFIX_VEX_0F38AE */ |
c0f3af97 | 5780 | { |
592d1631 L |
5781 | { Bad_Opcode }, |
5782 | { Bad_Opcode }, | |
0bfee649 | 5783 | { "vfnmsub213p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5784 | }, |
5785 | ||
592a252b | 5786 | /* PREFIX_VEX_0F38AF */ |
c0f3af97 | 5787 | { |
592d1631 L |
5788 | { Bad_Opcode }, |
5789 | { Bad_Opcode }, | |
1c480963 | 5790 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5791 | }, |
5792 | ||
592a252b | 5793 | /* PREFIX_VEX_0F38B6 */ |
c0f3af97 | 5794 | { |
592d1631 L |
5795 | { Bad_Opcode }, |
5796 | { Bad_Opcode }, | |
0bfee649 | 5797 | { "vfmaddsub231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5798 | }, |
5799 | ||
592a252b | 5800 | /* PREFIX_VEX_0F38B7 */ |
c0f3af97 | 5801 | { |
592d1631 L |
5802 | { Bad_Opcode }, |
5803 | { Bad_Opcode }, | |
0bfee649 | 5804 | { "vfmsubadd231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5805 | }, |
5806 | ||
592a252b | 5807 | /* PREFIX_VEX_0F38B8 */ |
c0f3af97 | 5808 | { |
592d1631 L |
5809 | { Bad_Opcode }, |
5810 | { Bad_Opcode }, | |
0bfee649 | 5811 | { "vfmadd231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5812 | }, |
5813 | ||
592a252b | 5814 | /* PREFIX_VEX_0F38B9 */ |
c0f3af97 | 5815 | { |
592d1631 L |
5816 | { Bad_Opcode }, |
5817 | { Bad_Opcode }, | |
1c480963 | 5818 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5819 | }, |
5820 | ||
592a252b | 5821 | /* PREFIX_VEX_0F38BA */ |
c0f3af97 | 5822 | { |
592d1631 L |
5823 | { Bad_Opcode }, |
5824 | { Bad_Opcode }, | |
0bfee649 | 5825 | { "vfmsub231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5826 | }, |
5827 | ||
592a252b | 5828 | /* PREFIX_VEX_0F38BB */ |
c0f3af97 | 5829 | { |
592d1631 L |
5830 | { Bad_Opcode }, |
5831 | { Bad_Opcode }, | |
1c480963 | 5832 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5833 | }, |
5834 | ||
592a252b | 5835 | /* PREFIX_VEX_0F38BC */ |
c0f3af97 | 5836 | { |
592d1631 L |
5837 | { Bad_Opcode }, |
5838 | { Bad_Opcode }, | |
0bfee649 | 5839 | { "vfnmadd231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5840 | }, |
5841 | ||
592a252b | 5842 | /* PREFIX_VEX_0F38BD */ |
c0f3af97 | 5843 | { |
592d1631 L |
5844 | { Bad_Opcode }, |
5845 | { Bad_Opcode }, | |
1c480963 | 5846 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5847 | }, |
5848 | ||
592a252b | 5849 | /* PREFIX_VEX_0F38BE */ |
c0f3af97 | 5850 | { |
592d1631 L |
5851 | { Bad_Opcode }, |
5852 | { Bad_Opcode }, | |
0bfee649 | 5853 | { "vfnmsub231p%XW", { XM, Vex, EXx } }, |
c0f3af97 L |
5854 | }, |
5855 | ||
592a252b | 5856 | /* PREFIX_VEX_0F38BF */ |
c0f3af97 | 5857 | { |
592d1631 L |
5858 | { Bad_Opcode }, |
5859 | { Bad_Opcode }, | |
1c480963 | 5860 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, |
c0f3af97 L |
5861 | }, |
5862 | ||
592a252b | 5863 | /* PREFIX_VEX_0F38DB */ |
c0f3af97 | 5864 | { |
592d1631 L |
5865 | { Bad_Opcode }, |
5866 | { Bad_Opcode }, | |
592a252b | 5867 | { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, |
c0f3af97 L |
5868 | }, |
5869 | ||
592a252b | 5870 | /* PREFIX_VEX_0F38DC */ |
c0f3af97 | 5871 | { |
592d1631 L |
5872 | { Bad_Opcode }, |
5873 | { Bad_Opcode }, | |
592a252b | 5874 | { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) }, |
c0f3af97 L |
5875 | }, |
5876 | ||
592a252b | 5877 | /* PREFIX_VEX_0F38DD */ |
c0f3af97 | 5878 | { |
592d1631 L |
5879 | { Bad_Opcode }, |
5880 | { Bad_Opcode }, | |
592a252b | 5881 | { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) }, |
c0f3af97 L |
5882 | }, |
5883 | ||
592a252b | 5884 | /* PREFIX_VEX_0F38DE */ |
c0f3af97 | 5885 | { |
592d1631 L |
5886 | { Bad_Opcode }, |
5887 | { Bad_Opcode }, | |
592a252b | 5888 | { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) }, |
c0f3af97 L |
5889 | }, |
5890 | ||
592a252b | 5891 | /* PREFIX_VEX_0F38DF */ |
c0f3af97 | 5892 | { |
592d1631 L |
5893 | { Bad_Opcode }, |
5894 | { Bad_Opcode }, | |
592a252b | 5895 | { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) }, |
c0f3af97 L |
5896 | }, |
5897 | ||
f12dc422 L |
5898 | /* PREFIX_VEX_0F38F2 */ |
5899 | { | |
5900 | { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, | |
5901 | }, | |
5902 | ||
5903 | /* PREFIX_VEX_0F38F3_REG_1 */ | |
5904 | { | |
5905 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, | |
5906 | }, | |
5907 | ||
5908 | /* PREFIX_VEX_0F38F3_REG_2 */ | |
5909 | { | |
5910 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, | |
5911 | }, | |
5912 | ||
5913 | /* PREFIX_VEX_0F38F3_REG_3 */ | |
5914 | { | |
5915 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, | |
5916 | }, | |
5917 | ||
6c30d220 L |
5918 | /* PREFIX_VEX_0F38F5 */ |
5919 | { | |
5920 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, | |
5921 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, | |
5922 | { Bad_Opcode }, | |
5923 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, | |
5924 | }, | |
5925 | ||
5926 | /* PREFIX_VEX_0F38F6 */ | |
5927 | { | |
5928 | { Bad_Opcode }, | |
5929 | { Bad_Opcode }, | |
5930 | { Bad_Opcode }, | |
5931 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, | |
5932 | }, | |
5933 | ||
f12dc422 L |
5934 | /* PREFIX_VEX_0F38F7 */ |
5935 | { | |
5936 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, | |
6c30d220 L |
5937 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, |
5938 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, | |
5939 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, | |
5940 | }, | |
5941 | ||
5942 | /* PREFIX_VEX_0F3A00 */ | |
5943 | { | |
5944 | { Bad_Opcode }, | |
5945 | { Bad_Opcode }, | |
5946 | { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) }, | |
5947 | }, | |
5948 | ||
5949 | /* PREFIX_VEX_0F3A01 */ | |
5950 | { | |
5951 | { Bad_Opcode }, | |
5952 | { Bad_Opcode }, | |
5953 | { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) }, | |
5954 | }, | |
5955 | ||
5956 | /* PREFIX_VEX_0F3A02 */ | |
5957 | { | |
5958 | { Bad_Opcode }, | |
5959 | { Bad_Opcode }, | |
5960 | { VEX_W_TABLE (VEX_W_0F3A02_P_2) }, | |
f12dc422 L |
5961 | }, |
5962 | ||
592a252b | 5963 | /* PREFIX_VEX_0F3A04 */ |
c0f3af97 | 5964 | { |
592d1631 L |
5965 | { Bad_Opcode }, |
5966 | { Bad_Opcode }, | |
592a252b | 5967 | { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, |
c0f3af97 L |
5968 | }, |
5969 | ||
592a252b | 5970 | /* PREFIX_VEX_0F3A05 */ |
c0f3af97 | 5971 | { |
592d1631 L |
5972 | { Bad_Opcode }, |
5973 | { Bad_Opcode }, | |
592a252b | 5974 | { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, |
c0f3af97 L |
5975 | }, |
5976 | ||
592a252b | 5977 | /* PREFIX_VEX_0F3A06 */ |
c0f3af97 | 5978 | { |
592d1631 L |
5979 | { Bad_Opcode }, |
5980 | { Bad_Opcode }, | |
592a252b | 5981 | { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, |
c0f3af97 L |
5982 | }, |
5983 | ||
592a252b | 5984 | /* PREFIX_VEX_0F3A08 */ |
c0f3af97 | 5985 | { |
592d1631 L |
5986 | { Bad_Opcode }, |
5987 | { Bad_Opcode }, | |
592a252b | 5988 | { VEX_W_TABLE (VEX_W_0F3A08_P_2) }, |
c0f3af97 L |
5989 | }, |
5990 | ||
592a252b | 5991 | /* PREFIX_VEX_0F3A09 */ |
c0f3af97 | 5992 | { |
592d1631 L |
5993 | { Bad_Opcode }, |
5994 | { Bad_Opcode }, | |
592a252b | 5995 | { VEX_W_TABLE (VEX_W_0F3A09_P_2) }, |
c0f3af97 L |
5996 | }, |
5997 | ||
592a252b | 5998 | /* PREFIX_VEX_0F3A0A */ |
c0f3af97 | 5999 | { |
592d1631 L |
6000 | { Bad_Opcode }, |
6001 | { Bad_Opcode }, | |
592a252b | 6002 | { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) }, |
0bfee649 L |
6003 | }, |
6004 | ||
592a252b | 6005 | /* PREFIX_VEX_0F3A0B */ |
0bfee649 | 6006 | { |
592d1631 L |
6007 | { Bad_Opcode }, |
6008 | { Bad_Opcode }, | |
592a252b | 6009 | { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) }, |
0bfee649 L |
6010 | }, |
6011 | ||
592a252b | 6012 | /* PREFIX_VEX_0F3A0C */ |
0bfee649 | 6013 | { |
592d1631 L |
6014 | { Bad_Opcode }, |
6015 | { Bad_Opcode }, | |
592a252b | 6016 | { VEX_W_TABLE (VEX_W_0F3A0C_P_2) }, |
0bfee649 L |
6017 | }, |
6018 | ||
592a252b | 6019 | /* PREFIX_VEX_0F3A0D */ |
0bfee649 | 6020 | { |
592d1631 L |
6021 | { Bad_Opcode }, |
6022 | { Bad_Opcode }, | |
592a252b | 6023 | { VEX_W_TABLE (VEX_W_0F3A0D_P_2) }, |
c0f3af97 L |
6024 | }, |
6025 | ||
592a252b | 6026 | /* PREFIX_VEX_0F3A0E */ |
0bfee649 | 6027 | { |
592d1631 L |
6028 | { Bad_Opcode }, |
6029 | { Bad_Opcode }, | |
6c30d220 | 6030 | { VEX_W_TABLE (VEX_W_0F3A0E_P_2) }, |
0bfee649 L |
6031 | }, |
6032 | ||
592a252b | 6033 | /* PREFIX_VEX_0F3A0F */ |
0bfee649 | 6034 | { |
592d1631 L |
6035 | { Bad_Opcode }, |
6036 | { Bad_Opcode }, | |
6c30d220 | 6037 | { VEX_W_TABLE (VEX_W_0F3A0F_P_2) }, |
0bfee649 L |
6038 | }, |
6039 | ||
592a252b | 6040 | /* PREFIX_VEX_0F3A14 */ |
0bfee649 | 6041 | { |
592d1631 L |
6042 | { Bad_Opcode }, |
6043 | { Bad_Opcode }, | |
592a252b | 6044 | { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, |
0bfee649 L |
6045 | }, |
6046 | ||
592a252b | 6047 | /* PREFIX_VEX_0F3A15 */ |
0bfee649 | 6048 | { |
592d1631 L |
6049 | { Bad_Opcode }, |
6050 | { Bad_Opcode }, | |
592a252b | 6051 | { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, |
0bfee649 L |
6052 | }, |
6053 | ||
592a252b | 6054 | /* PREFIX_VEX_0F3A16 */ |
c0f3af97 | 6055 | { |
592d1631 L |
6056 | { Bad_Opcode }, |
6057 | { Bad_Opcode }, | |
592a252b | 6058 | { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, |
c0f3af97 L |
6059 | }, |
6060 | ||
592a252b | 6061 | /* PREFIX_VEX_0F3A17 */ |
c0f3af97 | 6062 | { |
592d1631 L |
6063 | { Bad_Opcode }, |
6064 | { Bad_Opcode }, | |
592a252b | 6065 | { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, |
c0f3af97 L |
6066 | }, |
6067 | ||
592a252b | 6068 | /* PREFIX_VEX_0F3A18 */ |
c0f3af97 | 6069 | { |
592d1631 L |
6070 | { Bad_Opcode }, |
6071 | { Bad_Opcode }, | |
592a252b | 6072 | { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, |
c0f3af97 L |
6073 | }, |
6074 | ||
592a252b | 6075 | /* PREFIX_VEX_0F3A19 */ |
c0f3af97 | 6076 | { |
592d1631 L |
6077 | { Bad_Opcode }, |
6078 | { Bad_Opcode }, | |
592a252b | 6079 | { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, |
c0f3af97 L |
6080 | }, |
6081 | ||
592a252b | 6082 | /* PREFIX_VEX_0F3A1D */ |
c7b8aa3a L |
6083 | { |
6084 | { Bad_Opcode }, | |
6085 | { Bad_Opcode }, | |
6086 | { "vcvtps2ph", { EXxmmq, XM, Ib } }, | |
6087 | }, | |
6088 | ||
592a252b | 6089 | /* PREFIX_VEX_0F3A20 */ |
c0f3af97 | 6090 | { |
592d1631 L |
6091 | { Bad_Opcode }, |
6092 | { Bad_Opcode }, | |
592a252b | 6093 | { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, |
c0f3af97 L |
6094 | }, |
6095 | ||
592a252b | 6096 | /* PREFIX_VEX_0F3A21 */ |
c0f3af97 | 6097 | { |
592d1631 L |
6098 | { Bad_Opcode }, |
6099 | { Bad_Opcode }, | |
592a252b | 6100 | { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, |
c0f3af97 L |
6101 | }, |
6102 | ||
592a252b | 6103 | /* PREFIX_VEX_0F3A22 */ |
0bfee649 | 6104 | { |
592d1631 L |
6105 | { Bad_Opcode }, |
6106 | { Bad_Opcode }, | |
592a252b | 6107 | { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, |
0bfee649 L |
6108 | }, |
6109 | ||
43234a1e L |
6110 | /* PREFIX_VEX_0F3A30 */ |
6111 | { | |
6112 | { Bad_Opcode }, | |
6113 | { Bad_Opcode }, | |
6114 | { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) }, | |
6115 | }, | |
6116 | ||
6117 | /* PREFIX_VEX_0F3A32 */ | |
6118 | { | |
6119 | { Bad_Opcode }, | |
6120 | { Bad_Opcode }, | |
6121 | { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) }, | |
6122 | }, | |
6123 | ||
6c30d220 L |
6124 | /* PREFIX_VEX_0F3A38 */ |
6125 | { | |
6126 | { Bad_Opcode }, | |
6127 | { Bad_Opcode }, | |
6128 | { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) }, | |
6129 | }, | |
6130 | ||
6131 | /* PREFIX_VEX_0F3A39 */ | |
6132 | { | |
6133 | { Bad_Opcode }, | |
6134 | { Bad_Opcode }, | |
6135 | { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) }, | |
6136 | }, | |
6137 | ||
592a252b | 6138 | /* PREFIX_VEX_0F3A40 */ |
c0f3af97 | 6139 | { |
592d1631 L |
6140 | { Bad_Opcode }, |
6141 | { Bad_Opcode }, | |
592a252b | 6142 | { VEX_W_TABLE (VEX_W_0F3A40_P_2) }, |
c0f3af97 L |
6143 | }, |
6144 | ||
592a252b | 6145 | /* PREFIX_VEX_0F3A41 */ |
c0f3af97 | 6146 | { |
592d1631 L |
6147 | { Bad_Opcode }, |
6148 | { Bad_Opcode }, | |
592a252b | 6149 | { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, |
c0f3af97 L |
6150 | }, |
6151 | ||
592a252b | 6152 | /* PREFIX_VEX_0F3A42 */ |
c0f3af97 | 6153 | { |
592d1631 L |
6154 | { Bad_Opcode }, |
6155 | { Bad_Opcode }, | |
6c30d220 | 6156 | { VEX_W_TABLE (VEX_W_0F3A42_P_2) }, |
c0f3af97 L |
6157 | }, |
6158 | ||
592a252b | 6159 | /* PREFIX_VEX_0F3A44 */ |
ce2f5b3c | 6160 | { |
592d1631 L |
6161 | { Bad_Opcode }, |
6162 | { Bad_Opcode }, | |
592a252b | 6163 | { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) }, |
ce2f5b3c L |
6164 | }, |
6165 | ||
6c30d220 L |
6166 | /* PREFIX_VEX_0F3A46 */ |
6167 | { | |
6168 | { Bad_Opcode }, | |
6169 | { Bad_Opcode }, | |
6170 | { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) }, | |
6171 | }, | |
6172 | ||
592a252b | 6173 | /* PREFIX_VEX_0F3A48 */ |
a683cc34 SP |
6174 | { |
6175 | { Bad_Opcode }, | |
6176 | { Bad_Opcode }, | |
592a252b | 6177 | { VEX_W_TABLE (VEX_W_0F3A48_P_2) }, |
a683cc34 SP |
6178 | }, |
6179 | ||
592a252b | 6180 | /* PREFIX_VEX_0F3A49 */ |
a683cc34 SP |
6181 | { |
6182 | { Bad_Opcode }, | |
6183 | { Bad_Opcode }, | |
592a252b | 6184 | { VEX_W_TABLE (VEX_W_0F3A49_P_2) }, |
a683cc34 SP |
6185 | }, |
6186 | ||
592a252b | 6187 | /* PREFIX_VEX_0F3A4A */ |
c0f3af97 | 6188 | { |
592d1631 L |
6189 | { Bad_Opcode }, |
6190 | { Bad_Opcode }, | |
592a252b | 6191 | { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, |
c0f3af97 L |
6192 | }, |
6193 | ||
592a252b | 6194 | /* PREFIX_VEX_0F3A4B */ |
c0f3af97 | 6195 | { |
592d1631 L |
6196 | { Bad_Opcode }, |
6197 | { Bad_Opcode }, | |
592a252b | 6198 | { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, |
c0f3af97 L |
6199 | }, |
6200 | ||
592a252b | 6201 | /* PREFIX_VEX_0F3A4C */ |
c0f3af97 | 6202 | { |
592d1631 L |
6203 | { Bad_Opcode }, |
6204 | { Bad_Opcode }, | |
6c30d220 | 6205 | { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, |
c0f3af97 L |
6206 | }, |
6207 | ||
592a252b | 6208 | /* PREFIX_VEX_0F3A5C */ |
922d8de8 | 6209 | { |
592d1631 L |
6210 | { Bad_Opcode }, |
6211 | { Bad_Opcode }, | |
206c2556 | 6212 | { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
6213 | }, |
6214 | ||
592a252b | 6215 | /* PREFIX_VEX_0F3A5D */ |
922d8de8 | 6216 | { |
592d1631 L |
6217 | { Bad_Opcode }, |
6218 | { Bad_Opcode }, | |
206c2556 | 6219 | { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
6220 | }, |
6221 | ||
592a252b | 6222 | /* PREFIX_VEX_0F3A5E */ |
922d8de8 | 6223 | { |
592d1631 L |
6224 | { Bad_Opcode }, |
6225 | { Bad_Opcode }, | |
206c2556 | 6226 | { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
6227 | }, |
6228 | ||
592a252b | 6229 | /* PREFIX_VEX_0F3A5F */ |
922d8de8 | 6230 | { |
592d1631 L |
6231 | { Bad_Opcode }, |
6232 | { Bad_Opcode }, | |
206c2556 | 6233 | { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
6234 | }, |
6235 | ||
592a252b | 6236 | /* PREFIX_VEX_0F3A60 */ |
c0f3af97 | 6237 | { |
592d1631 L |
6238 | { Bad_Opcode }, |
6239 | { Bad_Opcode }, | |
592a252b | 6240 | { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, |
592d1631 | 6241 | { Bad_Opcode }, |
c0f3af97 L |
6242 | }, |
6243 | ||
592a252b | 6244 | /* PREFIX_VEX_0F3A61 */ |
c0f3af97 | 6245 | { |
592d1631 L |
6246 | { Bad_Opcode }, |
6247 | { Bad_Opcode }, | |
592a252b | 6248 | { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, |
c0f3af97 L |
6249 | }, |
6250 | ||
592a252b | 6251 | /* PREFIX_VEX_0F3A62 */ |
c0f3af97 | 6252 | { |
592d1631 L |
6253 | { Bad_Opcode }, |
6254 | { Bad_Opcode }, | |
592a252b | 6255 | { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, |
c0f3af97 L |
6256 | }, |
6257 | ||
592a252b | 6258 | /* PREFIX_VEX_0F3A63 */ |
c0f3af97 | 6259 | { |
592d1631 L |
6260 | { Bad_Opcode }, |
6261 | { Bad_Opcode }, | |
592a252b | 6262 | { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, |
c0f3af97 | 6263 | }, |
a5ff0eb2 | 6264 | |
592a252b | 6265 | /* PREFIX_VEX_0F3A68 */ |
922d8de8 | 6266 | { |
592d1631 L |
6267 | { Bad_Opcode }, |
6268 | { Bad_Opcode }, | |
206c2556 | 6269 | { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
6270 | }, |
6271 | ||
592a252b | 6272 | /* PREFIX_VEX_0F3A69 */ |
922d8de8 | 6273 | { |
592d1631 L |
6274 | { Bad_Opcode }, |
6275 | { Bad_Opcode }, | |
206c2556 | 6276 | { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
6277 | }, |
6278 | ||
592a252b | 6279 | /* PREFIX_VEX_0F3A6A */ |
922d8de8 | 6280 | { |
592d1631 L |
6281 | { Bad_Opcode }, |
6282 | { Bad_Opcode }, | |
592a252b | 6283 | { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) }, |
922d8de8 DR |
6284 | }, |
6285 | ||
592a252b | 6286 | /* PREFIX_VEX_0F3A6B */ |
922d8de8 | 6287 | { |
592d1631 L |
6288 | { Bad_Opcode }, |
6289 | { Bad_Opcode }, | |
592a252b | 6290 | { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) }, |
922d8de8 DR |
6291 | }, |
6292 | ||
592a252b | 6293 | /* PREFIX_VEX_0F3A6C */ |
922d8de8 | 6294 | { |
592d1631 L |
6295 | { Bad_Opcode }, |
6296 | { Bad_Opcode }, | |
206c2556 | 6297 | { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
6298 | }, |
6299 | ||
592a252b | 6300 | /* PREFIX_VEX_0F3A6D */ |
922d8de8 | 6301 | { |
592d1631 L |
6302 | { Bad_Opcode }, |
6303 | { Bad_Opcode }, | |
206c2556 | 6304 | { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
6305 | }, |
6306 | ||
592a252b | 6307 | /* PREFIX_VEX_0F3A6E */ |
922d8de8 | 6308 | { |
592d1631 L |
6309 | { Bad_Opcode }, |
6310 | { Bad_Opcode }, | |
592a252b | 6311 | { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) }, |
922d8de8 DR |
6312 | }, |
6313 | ||
592a252b | 6314 | /* PREFIX_VEX_0F3A6F */ |
922d8de8 | 6315 | { |
592d1631 L |
6316 | { Bad_Opcode }, |
6317 | { Bad_Opcode }, | |
592a252b | 6318 | { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) }, |
922d8de8 DR |
6319 | }, |
6320 | ||
592a252b | 6321 | /* PREFIX_VEX_0F3A78 */ |
922d8de8 | 6322 | { |
592d1631 L |
6323 | { Bad_Opcode }, |
6324 | { Bad_Opcode }, | |
206c2556 | 6325 | { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
6326 | }, |
6327 | ||
592a252b | 6328 | /* PREFIX_VEX_0F3A79 */ |
922d8de8 | 6329 | { |
592d1631 L |
6330 | { Bad_Opcode }, |
6331 | { Bad_Opcode }, | |
206c2556 | 6332 | { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
6333 | }, |
6334 | ||
592a252b | 6335 | /* PREFIX_VEX_0F3A7A */ |
922d8de8 | 6336 | { |
592d1631 L |
6337 | { Bad_Opcode }, |
6338 | { Bad_Opcode }, | |
592a252b | 6339 | { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) }, |
922d8de8 DR |
6340 | }, |
6341 | ||
592a252b | 6342 | /* PREFIX_VEX_0F3A7B */ |
922d8de8 | 6343 | { |
592d1631 L |
6344 | { Bad_Opcode }, |
6345 | { Bad_Opcode }, | |
592a252b | 6346 | { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) }, |
922d8de8 DR |
6347 | }, |
6348 | ||
592a252b | 6349 | /* PREFIX_VEX_0F3A7C */ |
922d8de8 | 6350 | { |
592d1631 L |
6351 | { Bad_Opcode }, |
6352 | { Bad_Opcode }, | |
206c2556 | 6353 | { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
592d1631 | 6354 | { Bad_Opcode }, |
922d8de8 DR |
6355 | }, |
6356 | ||
592a252b | 6357 | /* PREFIX_VEX_0F3A7D */ |
922d8de8 | 6358 | { |
592d1631 L |
6359 | { Bad_Opcode }, |
6360 | { Bad_Opcode }, | |
206c2556 | 6361 | { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
922d8de8 DR |
6362 | }, |
6363 | ||
592a252b | 6364 | /* PREFIX_VEX_0F3A7E */ |
922d8de8 | 6365 | { |
592d1631 L |
6366 | { Bad_Opcode }, |
6367 | { Bad_Opcode }, | |
592a252b | 6368 | { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) }, |
922d8de8 DR |
6369 | }, |
6370 | ||
592a252b | 6371 | /* PREFIX_VEX_0F3A7F */ |
922d8de8 | 6372 | { |
592d1631 L |
6373 | { Bad_Opcode }, |
6374 | { Bad_Opcode }, | |
592a252b | 6375 | { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) }, |
922d8de8 DR |
6376 | }, |
6377 | ||
592a252b | 6378 | /* PREFIX_VEX_0F3ADF */ |
a5ff0eb2 | 6379 | { |
592d1631 L |
6380 | { Bad_Opcode }, |
6381 | { Bad_Opcode }, | |
592a252b | 6382 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, |
a5ff0eb2 | 6383 | }, |
6c30d220 L |
6384 | |
6385 | /* PREFIX_VEX_0F3AF0 */ | |
6386 | { | |
6387 | { Bad_Opcode }, | |
6388 | { Bad_Opcode }, | |
6389 | { Bad_Opcode }, | |
6390 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, | |
6391 | }, | |
43234a1e L |
6392 | |
6393 | #define NEED_PREFIX_TABLE | |
6394 | #include "i386-dis-evex.h" | |
6395 | #undef NEED_PREFIX_TABLE | |
c0f3af97 L |
6396 | }; |
6397 | ||
6398 | static const struct dis386 x86_64_table[][2] = { | |
6399 | /* X86_64_06 */ | |
6400 | { | |
d9e3625e | 6401 | { "pushP", { es } }, |
c0f3af97 L |
6402 | }, |
6403 | ||
6404 | /* X86_64_07 */ | |
6405 | { | |
d9e3625e | 6406 | { "popP", { es } }, |
c0f3af97 L |
6407 | }, |
6408 | ||
6409 | /* X86_64_0D */ | |
6410 | { | |
d9e3625e | 6411 | { "pushP", { cs } }, |
c0f3af97 L |
6412 | }, |
6413 | ||
6414 | /* X86_64_16 */ | |
6415 | { | |
d9e3625e | 6416 | { "pushP", { ss } }, |
c0f3af97 L |
6417 | }, |
6418 | ||
6419 | /* X86_64_17 */ | |
6420 | { | |
d9e3625e | 6421 | { "popP", { ss } }, |
c0f3af97 L |
6422 | }, |
6423 | ||
6424 | /* X86_64_1E */ | |
6425 | { | |
d9e3625e | 6426 | { "pushP", { ds } }, |
c0f3af97 L |
6427 | }, |
6428 | ||
6429 | /* X86_64_1F */ | |
6430 | { | |
d9e3625e | 6431 | { "popP", { ds } }, |
c0f3af97 L |
6432 | }, |
6433 | ||
6434 | /* X86_64_27 */ | |
6435 | { | |
6436 | { "daa", { XX } }, | |
c0f3af97 L |
6437 | }, |
6438 | ||
6439 | /* X86_64_2F */ | |
6440 | { | |
6441 | { "das", { XX } }, | |
c0f3af97 L |
6442 | }, |
6443 | ||
6444 | /* X86_64_37 */ | |
6445 | { | |
6446 | { "aaa", { XX } }, | |
c0f3af97 L |
6447 | }, |
6448 | ||
6449 | /* X86_64_3F */ | |
6450 | { | |
6451 | { "aas", { XX } }, | |
c0f3af97 L |
6452 | }, |
6453 | ||
6454 | /* X86_64_60 */ | |
6455 | { | |
d9e3625e | 6456 | { "pushaP", { XX } }, |
c0f3af97 L |
6457 | }, |
6458 | ||
6459 | /* X86_64_61 */ | |
6460 | { | |
d9e3625e | 6461 | { "popaP", { XX } }, |
c0f3af97 L |
6462 | }, |
6463 | ||
6464 | /* X86_64_62 */ | |
6465 | { | |
6466 | { MOD_TABLE (MOD_62_32BIT) }, | |
43234a1e | 6467 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
6468 | }, |
6469 | ||
6470 | /* X86_64_63 */ | |
6471 | { | |
6472 | { "arpl", { Ew, Gw } }, | |
6473 | { "movs{lq|xd}", { Gv, Ed } }, | |
6474 | }, | |
6475 | ||
6476 | /* X86_64_6D */ | |
6477 | { | |
6478 | { "ins{R|}", { Yzr, indirDX } }, | |
6479 | { "ins{G|}", { Yzr, indirDX } }, | |
6480 | }, | |
6481 | ||
6482 | /* X86_64_6F */ | |
6483 | { | |
6484 | { "outs{R|}", { indirDXr, Xz } }, | |
6485 | { "outs{G|}", { indirDXr, Xz } }, | |
6486 | }, | |
6487 | ||
6488 | /* X86_64_9A */ | |
6489 | { | |
6490 | { "Jcall{T|}", { Ap } }, | |
c0f3af97 L |
6491 | }, |
6492 | ||
6493 | /* X86_64_C4 */ | |
6494 | { | |
6495 | { MOD_TABLE (MOD_C4_32BIT) }, | |
6496 | { VEX_C4_TABLE (VEX_0F) }, | |
6497 | }, | |
6498 | ||
6499 | /* X86_64_C5 */ | |
6500 | { | |
6501 | { MOD_TABLE (MOD_C5_32BIT) }, | |
6502 | { VEX_C5_TABLE (VEX_0F) }, | |
6503 | }, | |
6504 | ||
6505 | /* X86_64_CE */ | |
6506 | { | |
6507 | { "into", { XX } }, | |
c0f3af97 L |
6508 | }, |
6509 | ||
6510 | /* X86_64_D4 */ | |
6511 | { | |
e3949f17 | 6512 | { "aam", { Ib } }, |
c0f3af97 L |
6513 | }, |
6514 | ||
6515 | /* X86_64_D5 */ | |
6516 | { | |
e3949f17 | 6517 | { "aad", { Ib } }, |
c0f3af97 L |
6518 | }, |
6519 | ||
6520 | /* X86_64_EA */ | |
6521 | { | |
6522 | { "Jjmp{T|}", { Ap } }, | |
c0f3af97 L |
6523 | }, |
6524 | ||
6525 | /* X86_64_0F01_REG_0 */ | |
6526 | { | |
6527 | { "sgdt{Q|IQ}", { M } }, | |
6528 | { "sgdt", { M } }, | |
6529 | }, | |
6530 | ||
6531 | /* X86_64_0F01_REG_1 */ | |
6532 | { | |
6533 | { "sidt{Q|IQ}", { M } }, | |
6534 | { "sidt", { M } }, | |
6535 | }, | |
6536 | ||
6537 | /* X86_64_0F01_REG_2 */ | |
6538 | { | |
6539 | { "lgdt{Q|Q}", { M } }, | |
6540 | { "lgdt", { M } }, | |
6541 | }, | |
6542 | ||
6543 | /* X86_64_0F01_REG_3 */ | |
6544 | { | |
6545 | { "lidt{Q|Q}", { M } }, | |
6546 | { "lidt", { M } }, | |
6547 | }, | |
6548 | }; | |
6549 | ||
6550 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
6551 | |
6552 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
6553 | { |
6554 | /* 00 */ | |
c1e679ec DR |
6555 | { "pshufb", { MX, EM } }, |
6556 | { "phaddw", { MX, EM } }, | |
6557 | { "phaddd", { MX, EM } }, | |
6558 | { "phaddsw", { MX, EM } }, | |
6559 | { "pmaddubsw", { MX, EM } }, | |
6560 | { "phsubw", { MX, EM } }, | |
6561 | { "phsubd", { MX, EM } }, | |
6562 | { "phsubsw", { MX, EM } }, | |
c0f3af97 | 6563 | /* 08 */ |
c1e679ec DR |
6564 | { "psignb", { MX, EM } }, |
6565 | { "psignw", { MX, EM } }, | |
6566 | { "psignd", { MX, EM } }, | |
6567 | { "pmulhrsw", { MX, EM } }, | |
592d1631 L |
6568 | { Bad_Opcode }, |
6569 | { Bad_Opcode }, | |
6570 | { Bad_Opcode }, | |
6571 | { Bad_Opcode }, | |
f88c9eb0 SP |
6572 | /* 10 */ |
6573 | { PREFIX_TABLE (PREFIX_0F3810) }, | |
592d1631 L |
6574 | { Bad_Opcode }, |
6575 | { Bad_Opcode }, | |
6576 | { Bad_Opcode }, | |
f88c9eb0 SP |
6577 | { PREFIX_TABLE (PREFIX_0F3814) }, |
6578 | { PREFIX_TABLE (PREFIX_0F3815) }, | |
592d1631 | 6579 | { Bad_Opcode }, |
f88c9eb0 SP |
6580 | { PREFIX_TABLE (PREFIX_0F3817) }, |
6581 | /* 18 */ | |
592d1631 L |
6582 | { Bad_Opcode }, |
6583 | { Bad_Opcode }, | |
6584 | { Bad_Opcode }, | |
6585 | { Bad_Opcode }, | |
f88c9eb0 SP |
6586 | { "pabsb", { MX, EM } }, |
6587 | { "pabsw", { MX, EM } }, | |
6588 | { "pabsd", { MX, EM } }, | |
592d1631 | 6589 | { Bad_Opcode }, |
f88c9eb0 SP |
6590 | /* 20 */ |
6591 | { PREFIX_TABLE (PREFIX_0F3820) }, | |
6592 | { PREFIX_TABLE (PREFIX_0F3821) }, | |
6593 | { PREFIX_TABLE (PREFIX_0F3822) }, | |
6594 | { PREFIX_TABLE (PREFIX_0F3823) }, | |
6595 | { PREFIX_TABLE (PREFIX_0F3824) }, | |
6596 | { PREFIX_TABLE (PREFIX_0F3825) }, | |
592d1631 L |
6597 | { Bad_Opcode }, |
6598 | { Bad_Opcode }, | |
f88c9eb0 SP |
6599 | /* 28 */ |
6600 | { PREFIX_TABLE (PREFIX_0F3828) }, | |
6601 | { PREFIX_TABLE (PREFIX_0F3829) }, | |
6602 | { PREFIX_TABLE (PREFIX_0F382A) }, | |
6603 | { PREFIX_TABLE (PREFIX_0F382B) }, | |
592d1631 L |
6604 | { Bad_Opcode }, |
6605 | { Bad_Opcode }, | |
6606 | { Bad_Opcode }, | |
6607 | { Bad_Opcode }, | |
f88c9eb0 SP |
6608 | /* 30 */ |
6609 | { PREFIX_TABLE (PREFIX_0F3830) }, | |
6610 | { PREFIX_TABLE (PREFIX_0F3831) }, | |
6611 | { PREFIX_TABLE (PREFIX_0F3832) }, | |
6612 | { PREFIX_TABLE (PREFIX_0F3833) }, | |
6613 | { PREFIX_TABLE (PREFIX_0F3834) }, | |
6614 | { PREFIX_TABLE (PREFIX_0F3835) }, | |
592d1631 | 6615 | { Bad_Opcode }, |
f88c9eb0 SP |
6616 | { PREFIX_TABLE (PREFIX_0F3837) }, |
6617 | /* 38 */ | |
6618 | { PREFIX_TABLE (PREFIX_0F3838) }, | |
6619 | { PREFIX_TABLE (PREFIX_0F3839) }, | |
6620 | { PREFIX_TABLE (PREFIX_0F383A) }, | |
6621 | { PREFIX_TABLE (PREFIX_0F383B) }, | |
6622 | { PREFIX_TABLE (PREFIX_0F383C) }, | |
6623 | { PREFIX_TABLE (PREFIX_0F383D) }, | |
6624 | { PREFIX_TABLE (PREFIX_0F383E) }, | |
6625 | { PREFIX_TABLE (PREFIX_0F383F) }, | |
6626 | /* 40 */ | |
6627 | { PREFIX_TABLE (PREFIX_0F3840) }, | |
6628 | { PREFIX_TABLE (PREFIX_0F3841) }, | |
592d1631 L |
6629 | { Bad_Opcode }, |
6630 | { Bad_Opcode }, | |
6631 | { Bad_Opcode }, | |
6632 | { Bad_Opcode }, | |
6633 | { Bad_Opcode }, | |
6634 | { Bad_Opcode }, | |
f88c9eb0 | 6635 | /* 48 */ |
592d1631 L |
6636 | { Bad_Opcode }, |
6637 | { Bad_Opcode }, | |
6638 | { Bad_Opcode }, | |
6639 | { Bad_Opcode }, | |
6640 | { Bad_Opcode }, | |
6641 | { Bad_Opcode }, | |
6642 | { Bad_Opcode }, | |
6643 | { Bad_Opcode }, | |
f88c9eb0 | 6644 | /* 50 */ |
592d1631 L |
6645 | { Bad_Opcode }, |
6646 | { Bad_Opcode }, | |
6647 | { Bad_Opcode }, | |
6648 | { Bad_Opcode }, | |
6649 | { Bad_Opcode }, | |
6650 | { Bad_Opcode }, | |
6651 | { Bad_Opcode }, | |
6652 | { Bad_Opcode }, | |
f88c9eb0 | 6653 | /* 58 */ |
592d1631 L |
6654 | { Bad_Opcode }, |
6655 | { Bad_Opcode }, | |
6656 | { Bad_Opcode }, | |
6657 | { Bad_Opcode }, | |
6658 | { Bad_Opcode }, | |
6659 | { Bad_Opcode }, | |
6660 | { Bad_Opcode }, | |
6661 | { Bad_Opcode }, | |
f88c9eb0 | 6662 | /* 60 */ |
592d1631 L |
6663 | { Bad_Opcode }, |
6664 | { Bad_Opcode }, | |
6665 | { Bad_Opcode }, | |
6666 | { Bad_Opcode }, | |
6667 | { Bad_Opcode }, | |
6668 | { Bad_Opcode }, | |
6669 | { Bad_Opcode }, | |
6670 | { Bad_Opcode }, | |
f88c9eb0 | 6671 | /* 68 */ |
592d1631 L |
6672 | { Bad_Opcode }, |
6673 | { Bad_Opcode }, | |
6674 | { Bad_Opcode }, | |
6675 | { Bad_Opcode }, | |
6676 | { Bad_Opcode }, | |
6677 | { Bad_Opcode }, | |
6678 | { Bad_Opcode }, | |
6679 | { Bad_Opcode }, | |
f88c9eb0 | 6680 | /* 70 */ |
592d1631 L |
6681 | { Bad_Opcode }, |
6682 | { Bad_Opcode }, | |
6683 | { Bad_Opcode }, | |
6684 | { Bad_Opcode }, | |
6685 | { Bad_Opcode }, | |
6686 | { Bad_Opcode }, | |
6687 | { Bad_Opcode }, | |
6688 | { Bad_Opcode }, | |
f88c9eb0 | 6689 | /* 78 */ |
592d1631 L |
6690 | { Bad_Opcode }, |
6691 | { Bad_Opcode }, | |
6692 | { Bad_Opcode }, | |
6693 | { Bad_Opcode }, | |
6694 | { Bad_Opcode }, | |
6695 | { Bad_Opcode }, | |
6696 | { Bad_Opcode }, | |
6697 | { Bad_Opcode }, | |
f88c9eb0 SP |
6698 | /* 80 */ |
6699 | { PREFIX_TABLE (PREFIX_0F3880) }, | |
6700 | { PREFIX_TABLE (PREFIX_0F3881) }, | |
6c30d220 | 6701 | { PREFIX_TABLE (PREFIX_0F3882) }, |
592d1631 L |
6702 | { Bad_Opcode }, |
6703 | { Bad_Opcode }, | |
6704 | { Bad_Opcode }, | |
6705 | { Bad_Opcode }, | |
6706 | { Bad_Opcode }, | |
f88c9eb0 | 6707 | /* 88 */ |
592d1631 L |
6708 | { Bad_Opcode }, |
6709 | { Bad_Opcode }, | |
6710 | { Bad_Opcode }, | |
6711 | { Bad_Opcode }, | |
6712 | { Bad_Opcode }, | |
6713 | { Bad_Opcode }, | |
6714 | { Bad_Opcode }, | |
6715 | { Bad_Opcode }, | |
f88c9eb0 | 6716 | /* 90 */ |
592d1631 L |
6717 | { Bad_Opcode }, |
6718 | { Bad_Opcode }, | |
6719 | { Bad_Opcode }, | |
6720 | { Bad_Opcode }, | |
6721 | { Bad_Opcode }, | |
6722 | { Bad_Opcode }, | |
6723 | { Bad_Opcode }, | |
6724 | { Bad_Opcode }, | |
f88c9eb0 | 6725 | /* 98 */ |
592d1631 L |
6726 | { Bad_Opcode }, |
6727 | { Bad_Opcode }, | |
6728 | { Bad_Opcode }, | |
6729 | { Bad_Opcode }, | |
6730 | { Bad_Opcode }, | |
6731 | { Bad_Opcode }, | |
6732 | { Bad_Opcode }, | |
6733 | { Bad_Opcode }, | |
f88c9eb0 | 6734 | /* a0 */ |
592d1631 L |
6735 | { Bad_Opcode }, |
6736 | { Bad_Opcode }, | |
6737 | { Bad_Opcode }, | |
6738 | { Bad_Opcode }, | |
6739 | { Bad_Opcode }, | |
6740 | { Bad_Opcode }, | |
6741 | { Bad_Opcode }, | |
6742 | { Bad_Opcode }, | |
f88c9eb0 | 6743 | /* a8 */ |
592d1631 L |
6744 | { Bad_Opcode }, |
6745 | { Bad_Opcode }, | |
6746 | { Bad_Opcode }, | |
6747 | { Bad_Opcode }, | |
6748 | { Bad_Opcode }, | |
6749 | { Bad_Opcode }, | |
6750 | { Bad_Opcode }, | |
6751 | { Bad_Opcode }, | |
f88c9eb0 | 6752 | /* b0 */ |
592d1631 L |
6753 | { Bad_Opcode }, |
6754 | { Bad_Opcode }, | |
6755 | { Bad_Opcode }, | |
6756 | { Bad_Opcode }, | |
6757 | { Bad_Opcode }, | |
6758 | { Bad_Opcode }, | |
6759 | { Bad_Opcode }, | |
6760 | { Bad_Opcode }, | |
f88c9eb0 | 6761 | /* b8 */ |
592d1631 L |
6762 | { Bad_Opcode }, |
6763 | { Bad_Opcode }, | |
6764 | { Bad_Opcode }, | |
6765 | { Bad_Opcode }, | |
6766 | { Bad_Opcode }, | |
6767 | { Bad_Opcode }, | |
6768 | { Bad_Opcode }, | |
6769 | { Bad_Opcode }, | |
f88c9eb0 | 6770 | /* c0 */ |
592d1631 L |
6771 | { Bad_Opcode }, |
6772 | { Bad_Opcode }, | |
6773 | { Bad_Opcode }, | |
6774 | { Bad_Opcode }, | |
6775 | { Bad_Opcode }, | |
6776 | { Bad_Opcode }, | |
6777 | { Bad_Opcode }, | |
6778 | { Bad_Opcode }, | |
f88c9eb0 | 6779 | /* c8 */ |
a0046408 L |
6780 | { PREFIX_TABLE (PREFIX_0F38C8) }, |
6781 | { PREFIX_TABLE (PREFIX_0F38C9) }, | |
6782 | { PREFIX_TABLE (PREFIX_0F38CA) }, | |
6783 | { PREFIX_TABLE (PREFIX_0F38CB) }, | |
6784 | { PREFIX_TABLE (PREFIX_0F38CC) }, | |
6785 | { PREFIX_TABLE (PREFIX_0F38CD) }, | |
592d1631 L |
6786 | { Bad_Opcode }, |
6787 | { Bad_Opcode }, | |
f88c9eb0 | 6788 | /* d0 */ |
592d1631 L |
6789 | { Bad_Opcode }, |
6790 | { Bad_Opcode }, | |
6791 | { Bad_Opcode }, | |
6792 | { Bad_Opcode }, | |
6793 | { Bad_Opcode }, | |
6794 | { Bad_Opcode }, | |
6795 | { Bad_Opcode }, | |
6796 | { Bad_Opcode }, | |
f88c9eb0 | 6797 | /* d8 */ |
592d1631 L |
6798 | { Bad_Opcode }, |
6799 | { Bad_Opcode }, | |
6800 | { Bad_Opcode }, | |
f88c9eb0 SP |
6801 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
6802 | { PREFIX_TABLE (PREFIX_0F38DC) }, | |
6803 | { PREFIX_TABLE (PREFIX_0F38DD) }, | |
6804 | { PREFIX_TABLE (PREFIX_0F38DE) }, | |
6805 | { PREFIX_TABLE (PREFIX_0F38DF) }, | |
6806 | /* e0 */ | |
592d1631 L |
6807 | { Bad_Opcode }, |
6808 | { Bad_Opcode }, | |
6809 | { Bad_Opcode }, | |
6810 | { Bad_Opcode }, | |
6811 | { Bad_Opcode }, | |
6812 | { Bad_Opcode }, | |
6813 | { Bad_Opcode }, | |
6814 | { Bad_Opcode }, | |
f88c9eb0 | 6815 | /* e8 */ |
592d1631 L |
6816 | { Bad_Opcode }, |
6817 | { Bad_Opcode }, | |
6818 | { Bad_Opcode }, | |
6819 | { Bad_Opcode }, | |
6820 | { Bad_Opcode }, | |
6821 | { Bad_Opcode }, | |
6822 | { Bad_Opcode }, | |
6823 | { Bad_Opcode }, | |
f88c9eb0 SP |
6824 | /* f0 */ |
6825 | { PREFIX_TABLE (PREFIX_0F38F0) }, | |
6826 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
592d1631 L |
6827 | { Bad_Opcode }, |
6828 | { Bad_Opcode }, | |
6829 | { Bad_Opcode }, | |
6830 | { Bad_Opcode }, | |
e2e1fcde | 6831 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
592d1631 | 6832 | { Bad_Opcode }, |
f88c9eb0 | 6833 | /* f8 */ |
592d1631 L |
6834 | { Bad_Opcode }, |
6835 | { Bad_Opcode }, | |
6836 | { Bad_Opcode }, | |
6837 | { Bad_Opcode }, | |
6838 | { Bad_Opcode }, | |
6839 | { Bad_Opcode }, | |
6840 | { Bad_Opcode }, | |
6841 | { Bad_Opcode }, | |
f88c9eb0 SP |
6842 | }, |
6843 | /* THREE_BYTE_0F3A */ | |
6844 | { | |
6845 | /* 00 */ | |
592d1631 L |
6846 | { Bad_Opcode }, |
6847 | { Bad_Opcode }, | |
6848 | { Bad_Opcode }, | |
6849 | { Bad_Opcode }, | |
6850 | { Bad_Opcode }, | |
6851 | { Bad_Opcode }, | |
6852 | { Bad_Opcode }, | |
6853 | { Bad_Opcode }, | |
f88c9eb0 SP |
6854 | /* 08 */ |
6855 | { PREFIX_TABLE (PREFIX_0F3A08) }, | |
6856 | { PREFIX_TABLE (PREFIX_0F3A09) }, | |
6857 | { PREFIX_TABLE (PREFIX_0F3A0A) }, | |
6858 | { PREFIX_TABLE (PREFIX_0F3A0B) }, | |
6859 | { PREFIX_TABLE (PREFIX_0F3A0C) }, | |
6860 | { PREFIX_TABLE (PREFIX_0F3A0D) }, | |
6861 | { PREFIX_TABLE (PREFIX_0F3A0E) }, | |
6862 | { "palignr", { MX, EM, Ib } }, | |
6863 | /* 10 */ | |
592d1631 L |
6864 | { Bad_Opcode }, |
6865 | { Bad_Opcode }, | |
6866 | { Bad_Opcode }, | |
6867 | { Bad_Opcode }, | |
f88c9eb0 SP |
6868 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
6869 | { PREFIX_TABLE (PREFIX_0F3A15) }, | |
6870 | { PREFIX_TABLE (PREFIX_0F3A16) }, | |
6871 | { PREFIX_TABLE (PREFIX_0F3A17) }, | |
6872 | /* 18 */ | |
592d1631 L |
6873 | { Bad_Opcode }, |
6874 | { Bad_Opcode }, | |
6875 | { Bad_Opcode }, | |
6876 | { Bad_Opcode }, | |
6877 | { Bad_Opcode }, | |
6878 | { Bad_Opcode }, | |
6879 | { Bad_Opcode }, | |
6880 | { Bad_Opcode }, | |
f88c9eb0 SP |
6881 | /* 20 */ |
6882 | { PREFIX_TABLE (PREFIX_0F3A20) }, | |
6883 | { PREFIX_TABLE (PREFIX_0F3A21) }, | |
6884 | { PREFIX_TABLE (PREFIX_0F3A22) }, | |
592d1631 L |
6885 | { Bad_Opcode }, |
6886 | { Bad_Opcode }, | |
6887 | { Bad_Opcode }, | |
6888 | { Bad_Opcode }, | |
6889 | { Bad_Opcode }, | |
f88c9eb0 | 6890 | /* 28 */ |
592d1631 L |
6891 | { Bad_Opcode }, |
6892 | { Bad_Opcode }, | |
6893 | { Bad_Opcode }, | |
6894 | { Bad_Opcode }, | |
6895 | { Bad_Opcode }, | |
6896 | { Bad_Opcode }, | |
6897 | { Bad_Opcode }, | |
6898 | { Bad_Opcode }, | |
f88c9eb0 | 6899 | /* 30 */ |
592d1631 L |
6900 | { Bad_Opcode }, |
6901 | { Bad_Opcode }, | |
6902 | { Bad_Opcode }, | |
6903 | { Bad_Opcode }, | |
6904 | { Bad_Opcode }, | |
6905 | { Bad_Opcode }, | |
6906 | { Bad_Opcode }, | |
6907 | { Bad_Opcode }, | |
f88c9eb0 | 6908 | /* 38 */ |
592d1631 L |
6909 | { Bad_Opcode }, |
6910 | { Bad_Opcode }, | |
6911 | { Bad_Opcode }, | |
6912 | { Bad_Opcode }, | |
6913 | { Bad_Opcode }, | |
6914 | { Bad_Opcode }, | |
6915 | { Bad_Opcode }, | |
6916 | { Bad_Opcode }, | |
f88c9eb0 SP |
6917 | /* 40 */ |
6918 | { PREFIX_TABLE (PREFIX_0F3A40) }, | |
6919 | { PREFIX_TABLE (PREFIX_0F3A41) }, | |
6920 | { PREFIX_TABLE (PREFIX_0F3A42) }, | |
592d1631 | 6921 | { Bad_Opcode }, |
f88c9eb0 | 6922 | { PREFIX_TABLE (PREFIX_0F3A44) }, |
592d1631 L |
6923 | { Bad_Opcode }, |
6924 | { Bad_Opcode }, | |
6925 | { Bad_Opcode }, | |
f88c9eb0 | 6926 | /* 48 */ |
592d1631 L |
6927 | { Bad_Opcode }, |
6928 | { Bad_Opcode }, | |
6929 | { Bad_Opcode }, | |
6930 | { Bad_Opcode }, | |
6931 | { Bad_Opcode }, | |
6932 | { Bad_Opcode }, | |
6933 | { Bad_Opcode }, | |
6934 | { Bad_Opcode }, | |
f88c9eb0 | 6935 | /* 50 */ |
592d1631 L |
6936 | { Bad_Opcode }, |
6937 | { Bad_Opcode }, | |
6938 | { Bad_Opcode }, | |
6939 | { Bad_Opcode }, | |
6940 | { Bad_Opcode }, | |
6941 | { Bad_Opcode }, | |
6942 | { Bad_Opcode }, | |
6943 | { Bad_Opcode }, | |
f88c9eb0 | 6944 | /* 58 */ |
592d1631 L |
6945 | { Bad_Opcode }, |
6946 | { Bad_Opcode }, | |
6947 | { Bad_Opcode }, | |
6948 | { Bad_Opcode }, | |
6949 | { Bad_Opcode }, | |
6950 | { Bad_Opcode }, | |
6951 | { Bad_Opcode }, | |
6952 | { Bad_Opcode }, | |
f88c9eb0 SP |
6953 | /* 60 */ |
6954 | { PREFIX_TABLE (PREFIX_0F3A60) }, | |
6955 | { PREFIX_TABLE (PREFIX_0F3A61) }, | |
6956 | { PREFIX_TABLE (PREFIX_0F3A62) }, | |
6957 | { PREFIX_TABLE (PREFIX_0F3A63) }, | |
592d1631 L |
6958 | { Bad_Opcode }, |
6959 | { Bad_Opcode }, | |
6960 | { Bad_Opcode }, | |
6961 | { Bad_Opcode }, | |
f88c9eb0 | 6962 | /* 68 */ |
592d1631 L |
6963 | { Bad_Opcode }, |
6964 | { Bad_Opcode }, | |
6965 | { Bad_Opcode }, | |
6966 | { Bad_Opcode }, | |
6967 | { Bad_Opcode }, | |
6968 | { Bad_Opcode }, | |
6969 | { Bad_Opcode }, | |
6970 | { Bad_Opcode }, | |
f88c9eb0 | 6971 | /* 70 */ |
592d1631 L |
6972 | { Bad_Opcode }, |
6973 | { Bad_Opcode }, | |
6974 | { Bad_Opcode }, | |
6975 | { Bad_Opcode }, | |
6976 | { Bad_Opcode }, | |
6977 | { Bad_Opcode }, | |
6978 | { Bad_Opcode }, | |
6979 | { Bad_Opcode }, | |
f88c9eb0 | 6980 | /* 78 */ |
592d1631 L |
6981 | { Bad_Opcode }, |
6982 | { Bad_Opcode }, | |
6983 | { Bad_Opcode }, | |
6984 | { Bad_Opcode }, | |
6985 | { Bad_Opcode }, | |
6986 | { Bad_Opcode }, | |
6987 | { Bad_Opcode }, | |
6988 | { Bad_Opcode }, | |
f88c9eb0 | 6989 | /* 80 */ |
592d1631 L |
6990 | { Bad_Opcode }, |
6991 | { Bad_Opcode }, | |
6992 | { Bad_Opcode }, | |
6993 | { Bad_Opcode }, | |
6994 | { Bad_Opcode }, | |
6995 | { Bad_Opcode }, | |
6996 | { Bad_Opcode }, | |
6997 | { Bad_Opcode }, | |
f88c9eb0 | 6998 | /* 88 */ |
592d1631 L |
6999 | { Bad_Opcode }, |
7000 | { Bad_Opcode }, | |
7001 | { Bad_Opcode }, | |
7002 | { Bad_Opcode }, | |
7003 | { Bad_Opcode }, | |
7004 | { Bad_Opcode }, | |
7005 | { Bad_Opcode }, | |
7006 | { Bad_Opcode }, | |
f88c9eb0 | 7007 | /* 90 */ |
592d1631 L |
7008 | { Bad_Opcode }, |
7009 | { Bad_Opcode }, | |
7010 | { Bad_Opcode }, | |
7011 | { Bad_Opcode }, | |
7012 | { Bad_Opcode }, | |
7013 | { Bad_Opcode }, | |
7014 | { Bad_Opcode }, | |
7015 | { Bad_Opcode }, | |
f88c9eb0 | 7016 | /* 98 */ |
592d1631 L |
7017 | { Bad_Opcode }, |
7018 | { Bad_Opcode }, | |
7019 | { Bad_Opcode }, | |
7020 | { Bad_Opcode }, | |
7021 | { Bad_Opcode }, | |
7022 | { Bad_Opcode }, | |
7023 | { Bad_Opcode }, | |
7024 | { Bad_Opcode }, | |
f88c9eb0 | 7025 | /* a0 */ |
592d1631 L |
7026 | { Bad_Opcode }, |
7027 | { Bad_Opcode }, | |
7028 | { Bad_Opcode }, | |
7029 | { Bad_Opcode }, | |
7030 | { Bad_Opcode }, | |
7031 | { Bad_Opcode }, | |
7032 | { Bad_Opcode }, | |
7033 | { Bad_Opcode }, | |
f88c9eb0 | 7034 | /* a8 */ |
592d1631 L |
7035 | { Bad_Opcode }, |
7036 | { Bad_Opcode }, | |
7037 | { Bad_Opcode }, | |
7038 | { Bad_Opcode }, | |
7039 | { Bad_Opcode }, | |
7040 | { Bad_Opcode }, | |
7041 | { Bad_Opcode }, | |
7042 | { Bad_Opcode }, | |
f88c9eb0 | 7043 | /* b0 */ |
592d1631 L |
7044 | { Bad_Opcode }, |
7045 | { Bad_Opcode }, | |
7046 | { Bad_Opcode }, | |
7047 | { Bad_Opcode }, | |
7048 | { Bad_Opcode }, | |
7049 | { Bad_Opcode }, | |
7050 | { Bad_Opcode }, | |
7051 | { Bad_Opcode }, | |
f88c9eb0 | 7052 | /* b8 */ |
592d1631 L |
7053 | { Bad_Opcode }, |
7054 | { Bad_Opcode }, | |
7055 | { Bad_Opcode }, | |
7056 | { Bad_Opcode }, | |
7057 | { Bad_Opcode }, | |
7058 | { Bad_Opcode }, | |
7059 | { Bad_Opcode }, | |
7060 | { Bad_Opcode }, | |
f88c9eb0 | 7061 | /* c0 */ |
592d1631 L |
7062 | { Bad_Opcode }, |
7063 | { Bad_Opcode }, | |
7064 | { Bad_Opcode }, | |
7065 | { Bad_Opcode }, | |
7066 | { Bad_Opcode }, | |
7067 | { Bad_Opcode }, | |
7068 | { Bad_Opcode }, | |
7069 | { Bad_Opcode }, | |
f88c9eb0 | 7070 | /* c8 */ |
592d1631 L |
7071 | { Bad_Opcode }, |
7072 | { Bad_Opcode }, | |
7073 | { Bad_Opcode }, | |
7074 | { Bad_Opcode }, | |
a0046408 | 7075 | { PREFIX_TABLE (PREFIX_0F3ACC) }, |
592d1631 L |
7076 | { Bad_Opcode }, |
7077 | { Bad_Opcode }, | |
7078 | { Bad_Opcode }, | |
f88c9eb0 | 7079 | /* d0 */ |
592d1631 L |
7080 | { Bad_Opcode }, |
7081 | { Bad_Opcode }, | |
7082 | { Bad_Opcode }, | |
7083 | { Bad_Opcode }, | |
7084 | { Bad_Opcode }, | |
7085 | { Bad_Opcode }, | |
7086 | { Bad_Opcode }, | |
7087 | { Bad_Opcode }, | |
f88c9eb0 | 7088 | /* d8 */ |
592d1631 L |
7089 | { Bad_Opcode }, |
7090 | { Bad_Opcode }, | |
7091 | { Bad_Opcode }, | |
7092 | { Bad_Opcode }, | |
7093 | { Bad_Opcode }, | |
7094 | { Bad_Opcode }, | |
7095 | { Bad_Opcode }, | |
f88c9eb0 SP |
7096 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
7097 | /* e0 */ | |
592d1631 L |
7098 | { Bad_Opcode }, |
7099 | { Bad_Opcode }, | |
7100 | { Bad_Opcode }, | |
7101 | { Bad_Opcode }, | |
7102 | { Bad_Opcode }, | |
7103 | { Bad_Opcode }, | |
7104 | { Bad_Opcode }, | |
7105 | { Bad_Opcode }, | |
f88c9eb0 | 7106 | /* e8 */ |
592d1631 L |
7107 | { Bad_Opcode }, |
7108 | { Bad_Opcode }, | |
7109 | { Bad_Opcode }, | |
7110 | { Bad_Opcode }, | |
7111 | { Bad_Opcode }, | |
7112 | { Bad_Opcode }, | |
7113 | { Bad_Opcode }, | |
7114 | { Bad_Opcode }, | |
f88c9eb0 | 7115 | /* f0 */ |
592d1631 L |
7116 | { Bad_Opcode }, |
7117 | { Bad_Opcode }, | |
7118 | { Bad_Opcode }, | |
7119 | { Bad_Opcode }, | |
7120 | { Bad_Opcode }, | |
7121 | { Bad_Opcode }, | |
7122 | { Bad_Opcode }, | |
7123 | { Bad_Opcode }, | |
f88c9eb0 | 7124 | /* f8 */ |
592d1631 L |
7125 | { Bad_Opcode }, |
7126 | { Bad_Opcode }, | |
7127 | { Bad_Opcode }, | |
7128 | { Bad_Opcode }, | |
7129 | { Bad_Opcode }, | |
7130 | { Bad_Opcode }, | |
7131 | { Bad_Opcode }, | |
7132 | { Bad_Opcode }, | |
f88c9eb0 SP |
7133 | }, |
7134 | ||
7135 | /* THREE_BYTE_0F7A */ | |
7136 | { | |
7137 | /* 00 */ | |
592d1631 L |
7138 | { Bad_Opcode }, |
7139 | { Bad_Opcode }, | |
7140 | { Bad_Opcode }, | |
7141 | { Bad_Opcode }, | |
7142 | { Bad_Opcode }, | |
7143 | { Bad_Opcode }, | |
7144 | { Bad_Opcode }, | |
7145 | { Bad_Opcode }, | |
f88c9eb0 | 7146 | /* 08 */ |
592d1631 L |
7147 | { Bad_Opcode }, |
7148 | { Bad_Opcode }, | |
7149 | { Bad_Opcode }, | |
7150 | { Bad_Opcode }, | |
7151 | { Bad_Opcode }, | |
7152 | { Bad_Opcode }, | |
7153 | { Bad_Opcode }, | |
7154 | { Bad_Opcode }, | |
f88c9eb0 | 7155 | /* 10 */ |
592d1631 L |
7156 | { Bad_Opcode }, |
7157 | { Bad_Opcode }, | |
7158 | { Bad_Opcode }, | |
7159 | { Bad_Opcode }, | |
7160 | { Bad_Opcode }, | |
7161 | { Bad_Opcode }, | |
7162 | { Bad_Opcode }, | |
7163 | { Bad_Opcode }, | |
f88c9eb0 | 7164 | /* 18 */ |
592d1631 L |
7165 | { Bad_Opcode }, |
7166 | { Bad_Opcode }, | |
7167 | { Bad_Opcode }, | |
7168 | { Bad_Opcode }, | |
7169 | { Bad_Opcode }, | |
7170 | { Bad_Opcode }, | |
7171 | { Bad_Opcode }, | |
7172 | { Bad_Opcode }, | |
f88c9eb0 SP |
7173 | /* 20 */ |
7174 | { "ptest", { XX } }, | |
592d1631 L |
7175 | { Bad_Opcode }, |
7176 | { Bad_Opcode }, | |
7177 | { Bad_Opcode }, | |
7178 | { Bad_Opcode }, | |
7179 | { Bad_Opcode }, | |
7180 | { Bad_Opcode }, | |
7181 | { Bad_Opcode }, | |
f88c9eb0 | 7182 | /* 28 */ |
592d1631 L |
7183 | { Bad_Opcode }, |
7184 | { Bad_Opcode }, | |
7185 | { Bad_Opcode }, | |
7186 | { Bad_Opcode }, | |
7187 | { Bad_Opcode }, | |
7188 | { Bad_Opcode }, | |
7189 | { Bad_Opcode }, | |
7190 | { Bad_Opcode }, | |
f88c9eb0 | 7191 | /* 30 */ |
592d1631 L |
7192 | { Bad_Opcode }, |
7193 | { Bad_Opcode }, | |
7194 | { Bad_Opcode }, | |
7195 | { Bad_Opcode }, | |
7196 | { Bad_Opcode }, | |
7197 | { Bad_Opcode }, | |
7198 | { Bad_Opcode }, | |
7199 | { Bad_Opcode }, | |
f88c9eb0 | 7200 | /* 38 */ |
592d1631 L |
7201 | { Bad_Opcode }, |
7202 | { Bad_Opcode }, | |
7203 | { Bad_Opcode }, | |
7204 | { Bad_Opcode }, | |
7205 | { Bad_Opcode }, | |
7206 | { Bad_Opcode }, | |
7207 | { Bad_Opcode }, | |
7208 | { Bad_Opcode }, | |
f88c9eb0 | 7209 | /* 40 */ |
592d1631 | 7210 | { Bad_Opcode }, |
f88c9eb0 SP |
7211 | { "phaddbw", { XM, EXq } }, |
7212 | { "phaddbd", { XM, EXq } }, | |
7213 | { "phaddbq", { XM, EXq } }, | |
592d1631 L |
7214 | { Bad_Opcode }, |
7215 | { Bad_Opcode }, | |
f88c9eb0 SP |
7216 | { "phaddwd", { XM, EXq } }, |
7217 | { "phaddwq", { XM, EXq } }, | |
7218 | /* 48 */ | |
592d1631 L |
7219 | { Bad_Opcode }, |
7220 | { Bad_Opcode }, | |
7221 | { Bad_Opcode }, | |
f88c9eb0 | 7222 | { "phadddq", { XM, EXq } }, |
592d1631 L |
7223 | { Bad_Opcode }, |
7224 | { Bad_Opcode }, | |
7225 | { Bad_Opcode }, | |
7226 | { Bad_Opcode }, | |
f88c9eb0 | 7227 | /* 50 */ |
592d1631 | 7228 | { Bad_Opcode }, |
f88c9eb0 SP |
7229 | { "phaddubw", { XM, EXq } }, |
7230 | { "phaddubd", { XM, EXq } }, | |
7231 | { "phaddubq", { XM, EXq } }, | |
592d1631 L |
7232 | { Bad_Opcode }, |
7233 | { Bad_Opcode }, | |
f88c9eb0 SP |
7234 | { "phadduwd", { XM, EXq } }, |
7235 | { "phadduwq", { XM, EXq } }, | |
7236 | /* 58 */ | |
592d1631 L |
7237 | { Bad_Opcode }, |
7238 | { Bad_Opcode }, | |
7239 | { Bad_Opcode }, | |
f88c9eb0 | 7240 | { "phaddudq", { XM, EXq } }, |
592d1631 L |
7241 | { Bad_Opcode }, |
7242 | { Bad_Opcode }, | |
7243 | { Bad_Opcode }, | |
7244 | { Bad_Opcode }, | |
f88c9eb0 | 7245 | /* 60 */ |
592d1631 | 7246 | { Bad_Opcode }, |
f88c9eb0 SP |
7247 | { "phsubbw", { XM, EXq } }, |
7248 | { "phsubbd", { XM, EXq } }, | |
7249 | { "phsubbq", { XM, EXq } }, | |
592d1631 L |
7250 | { Bad_Opcode }, |
7251 | { Bad_Opcode }, | |
7252 | { Bad_Opcode }, | |
7253 | { Bad_Opcode }, | |
4e7d34a6 | 7254 | /* 68 */ |
592d1631 L |
7255 | { Bad_Opcode }, |
7256 | { Bad_Opcode }, | |
7257 | { Bad_Opcode }, | |
7258 | { Bad_Opcode }, | |
7259 | { Bad_Opcode }, | |
7260 | { Bad_Opcode }, | |
7261 | { Bad_Opcode }, | |
7262 | { Bad_Opcode }, | |
85f10a01 | 7263 | /* 70 */ |
592d1631 L |
7264 | { Bad_Opcode }, |
7265 | { Bad_Opcode }, | |
7266 | { Bad_Opcode }, | |
7267 | { Bad_Opcode }, | |
7268 | { Bad_Opcode }, | |
7269 | { Bad_Opcode }, | |
7270 | { Bad_Opcode }, | |
7271 | { Bad_Opcode }, | |
85f10a01 | 7272 | /* 78 */ |
592d1631 L |
7273 | { Bad_Opcode }, |
7274 | { Bad_Opcode }, | |
7275 | { Bad_Opcode }, | |
7276 | { Bad_Opcode }, | |
7277 | { Bad_Opcode }, | |
7278 | { Bad_Opcode }, | |
7279 | { Bad_Opcode }, | |
7280 | { Bad_Opcode }, | |
85f10a01 | 7281 | /* 80 */ |
592d1631 L |
7282 | { Bad_Opcode }, |
7283 | { Bad_Opcode }, | |
7284 | { Bad_Opcode }, | |
7285 | { Bad_Opcode }, | |
7286 | { Bad_Opcode }, | |
7287 | { Bad_Opcode }, | |
7288 | { Bad_Opcode }, | |
7289 | { Bad_Opcode }, | |
85f10a01 | 7290 | /* 88 */ |
592d1631 L |
7291 | { Bad_Opcode }, |
7292 | { Bad_Opcode }, | |
7293 | { Bad_Opcode }, | |
7294 | { Bad_Opcode }, | |
7295 | { Bad_Opcode }, | |
7296 | { Bad_Opcode }, | |
7297 | { Bad_Opcode }, | |
7298 | { Bad_Opcode }, | |
85f10a01 | 7299 | /* 90 */ |
592d1631 L |
7300 | { Bad_Opcode }, |
7301 | { Bad_Opcode }, | |
7302 | { Bad_Opcode }, | |
7303 | { Bad_Opcode }, | |
7304 | { Bad_Opcode }, | |
7305 | { Bad_Opcode }, | |
7306 | { Bad_Opcode }, | |
7307 | { Bad_Opcode }, | |
85f10a01 | 7308 | /* 98 */ |
592d1631 L |
7309 | { Bad_Opcode }, |
7310 | { Bad_Opcode }, | |
7311 | { Bad_Opcode }, | |
7312 | { Bad_Opcode }, | |
7313 | { Bad_Opcode }, | |
7314 | { Bad_Opcode }, | |
7315 | { Bad_Opcode }, | |
7316 | { Bad_Opcode }, | |
85f10a01 | 7317 | /* a0 */ |
592d1631 L |
7318 | { Bad_Opcode }, |
7319 | { Bad_Opcode }, | |
7320 | { Bad_Opcode }, | |
7321 | { Bad_Opcode }, | |
7322 | { Bad_Opcode }, | |
7323 | { Bad_Opcode }, | |
7324 | { Bad_Opcode }, | |
7325 | { Bad_Opcode }, | |
85f10a01 | 7326 | /* a8 */ |
592d1631 L |
7327 | { Bad_Opcode }, |
7328 | { Bad_Opcode }, | |
7329 | { Bad_Opcode }, | |
7330 | { Bad_Opcode }, | |
7331 | { Bad_Opcode }, | |
7332 | { Bad_Opcode }, | |
7333 | { Bad_Opcode }, | |
7334 | { Bad_Opcode }, | |
85f10a01 | 7335 | /* b0 */ |
592d1631 L |
7336 | { Bad_Opcode }, |
7337 | { Bad_Opcode }, | |
7338 | { Bad_Opcode }, | |
7339 | { Bad_Opcode }, | |
7340 | { Bad_Opcode }, | |
7341 | { Bad_Opcode }, | |
7342 | { Bad_Opcode }, | |
7343 | { Bad_Opcode }, | |
85f10a01 | 7344 | /* b8 */ |
592d1631 L |
7345 | { Bad_Opcode }, |
7346 | { Bad_Opcode }, | |
7347 | { Bad_Opcode }, | |
7348 | { Bad_Opcode }, | |
7349 | { Bad_Opcode }, | |
7350 | { Bad_Opcode }, | |
7351 | { Bad_Opcode }, | |
7352 | { Bad_Opcode }, | |
85f10a01 | 7353 | /* c0 */ |
592d1631 L |
7354 | { Bad_Opcode }, |
7355 | { Bad_Opcode }, | |
7356 | { Bad_Opcode }, | |
7357 | { Bad_Opcode }, | |
7358 | { Bad_Opcode }, | |
7359 | { Bad_Opcode }, | |
7360 | { Bad_Opcode }, | |
7361 | { Bad_Opcode }, | |
85f10a01 | 7362 | /* c8 */ |
592d1631 L |
7363 | { Bad_Opcode }, |
7364 | { Bad_Opcode }, | |
7365 | { Bad_Opcode }, | |
7366 | { Bad_Opcode }, | |
7367 | { Bad_Opcode }, | |
7368 | { Bad_Opcode }, | |
7369 | { Bad_Opcode }, | |
7370 | { Bad_Opcode }, | |
85f10a01 | 7371 | /* d0 */ |
592d1631 L |
7372 | { Bad_Opcode }, |
7373 | { Bad_Opcode }, | |
7374 | { Bad_Opcode }, | |
7375 | { Bad_Opcode }, | |
7376 | { Bad_Opcode }, | |
7377 | { Bad_Opcode }, | |
7378 | { Bad_Opcode }, | |
7379 | { Bad_Opcode }, | |
85f10a01 | 7380 | /* d8 */ |
592d1631 L |
7381 | { Bad_Opcode }, |
7382 | { Bad_Opcode }, | |
7383 | { Bad_Opcode }, | |
7384 | { Bad_Opcode }, | |
7385 | { Bad_Opcode }, | |
7386 | { Bad_Opcode }, | |
7387 | { Bad_Opcode }, | |
7388 | { Bad_Opcode }, | |
85f10a01 | 7389 | /* e0 */ |
592d1631 L |
7390 | { Bad_Opcode }, |
7391 | { Bad_Opcode }, | |
7392 | { Bad_Opcode }, | |
7393 | { Bad_Opcode }, | |
7394 | { Bad_Opcode }, | |
7395 | { Bad_Opcode }, | |
7396 | { Bad_Opcode }, | |
7397 | { Bad_Opcode }, | |
85f10a01 | 7398 | /* e8 */ |
592d1631 L |
7399 | { Bad_Opcode }, |
7400 | { Bad_Opcode }, | |
7401 | { Bad_Opcode }, | |
7402 | { Bad_Opcode }, | |
7403 | { Bad_Opcode }, | |
7404 | { Bad_Opcode }, | |
7405 | { Bad_Opcode }, | |
7406 | { Bad_Opcode }, | |
85f10a01 | 7407 | /* f0 */ |
592d1631 L |
7408 | { Bad_Opcode }, |
7409 | { Bad_Opcode }, | |
7410 | { Bad_Opcode }, | |
7411 | { Bad_Opcode }, | |
7412 | { Bad_Opcode }, | |
7413 | { Bad_Opcode }, | |
7414 | { Bad_Opcode }, | |
7415 | { Bad_Opcode }, | |
85f10a01 | 7416 | /* f8 */ |
592d1631 L |
7417 | { Bad_Opcode }, |
7418 | { Bad_Opcode }, | |
7419 | { Bad_Opcode }, | |
7420 | { Bad_Opcode }, | |
7421 | { Bad_Opcode }, | |
7422 | { Bad_Opcode }, | |
7423 | { Bad_Opcode }, | |
7424 | { Bad_Opcode }, | |
85f10a01 | 7425 | }, |
f88c9eb0 SP |
7426 | }; |
7427 | ||
7428 | static const struct dis386 xop_table[][256] = { | |
5dd85c99 | 7429 | /* XOP_08 */ |
85f10a01 MM |
7430 | { |
7431 | /* 00 */ | |
592d1631 L |
7432 | { Bad_Opcode }, |
7433 | { Bad_Opcode }, | |
7434 | { Bad_Opcode }, | |
7435 | { Bad_Opcode }, | |
7436 | { Bad_Opcode }, | |
7437 | { Bad_Opcode }, | |
7438 | { Bad_Opcode }, | |
7439 | { Bad_Opcode }, | |
85f10a01 | 7440 | /* 08 */ |
592d1631 L |
7441 | { Bad_Opcode }, |
7442 | { Bad_Opcode }, | |
7443 | { Bad_Opcode }, | |
7444 | { Bad_Opcode }, | |
7445 | { Bad_Opcode }, | |
7446 | { Bad_Opcode }, | |
7447 | { Bad_Opcode }, | |
7448 | { Bad_Opcode }, | |
85f10a01 | 7449 | /* 10 */ |
3929df09 | 7450 | { Bad_Opcode }, |
592d1631 L |
7451 | { Bad_Opcode }, |
7452 | { Bad_Opcode }, | |
7453 | { Bad_Opcode }, | |
7454 | { Bad_Opcode }, | |
7455 | { Bad_Opcode }, | |
7456 | { Bad_Opcode }, | |
7457 | { Bad_Opcode }, | |
85f10a01 | 7458 | /* 18 */ |
592d1631 L |
7459 | { Bad_Opcode }, |
7460 | { Bad_Opcode }, | |
7461 | { Bad_Opcode }, | |
7462 | { Bad_Opcode }, | |
7463 | { Bad_Opcode }, | |
7464 | { Bad_Opcode }, | |
7465 | { Bad_Opcode }, | |
7466 | { Bad_Opcode }, | |
85f10a01 | 7467 | /* 20 */ |
592d1631 L |
7468 | { Bad_Opcode }, |
7469 | { Bad_Opcode }, | |
7470 | { Bad_Opcode }, | |
7471 | { Bad_Opcode }, | |
7472 | { Bad_Opcode }, | |
7473 | { Bad_Opcode }, | |
7474 | { Bad_Opcode }, | |
7475 | { Bad_Opcode }, | |
85f10a01 | 7476 | /* 28 */ |
592d1631 L |
7477 | { Bad_Opcode }, |
7478 | { Bad_Opcode }, | |
7479 | { Bad_Opcode }, | |
7480 | { Bad_Opcode }, | |
7481 | { Bad_Opcode }, | |
7482 | { Bad_Opcode }, | |
7483 | { Bad_Opcode }, | |
7484 | { Bad_Opcode }, | |
c0f3af97 | 7485 | /* 30 */ |
592d1631 L |
7486 | { Bad_Opcode }, |
7487 | { Bad_Opcode }, | |
7488 | { Bad_Opcode }, | |
7489 | { Bad_Opcode }, | |
7490 | { Bad_Opcode }, | |
7491 | { Bad_Opcode }, | |
7492 | { Bad_Opcode }, | |
7493 | { Bad_Opcode }, | |
c0f3af97 | 7494 | /* 38 */ |
592d1631 L |
7495 | { Bad_Opcode }, |
7496 | { Bad_Opcode }, | |
7497 | { Bad_Opcode }, | |
7498 | { Bad_Opcode }, | |
7499 | { Bad_Opcode }, | |
7500 | { Bad_Opcode }, | |
7501 | { Bad_Opcode }, | |
7502 | { Bad_Opcode }, | |
c0f3af97 | 7503 | /* 40 */ |
592d1631 L |
7504 | { Bad_Opcode }, |
7505 | { Bad_Opcode }, | |
7506 | { Bad_Opcode }, | |
7507 | { Bad_Opcode }, | |
7508 | { Bad_Opcode }, | |
7509 | { Bad_Opcode }, | |
7510 | { Bad_Opcode }, | |
7511 | { Bad_Opcode }, | |
85f10a01 | 7512 | /* 48 */ |
592d1631 L |
7513 | { Bad_Opcode }, |
7514 | { Bad_Opcode }, | |
7515 | { Bad_Opcode }, | |
7516 | { Bad_Opcode }, | |
7517 | { Bad_Opcode }, | |
7518 | { Bad_Opcode }, | |
7519 | { Bad_Opcode }, | |
7520 | { Bad_Opcode }, | |
c0f3af97 | 7521 | /* 50 */ |
592d1631 L |
7522 | { Bad_Opcode }, |
7523 | { Bad_Opcode }, | |
7524 | { Bad_Opcode }, | |
7525 | { Bad_Opcode }, | |
7526 | { Bad_Opcode }, | |
7527 | { Bad_Opcode }, | |
7528 | { Bad_Opcode }, | |
7529 | { Bad_Opcode }, | |
85f10a01 | 7530 | /* 58 */ |
592d1631 L |
7531 | { Bad_Opcode }, |
7532 | { Bad_Opcode }, | |
7533 | { Bad_Opcode }, | |
7534 | { Bad_Opcode }, | |
7535 | { Bad_Opcode }, | |
7536 | { Bad_Opcode }, | |
7537 | { Bad_Opcode }, | |
7538 | { Bad_Opcode }, | |
c1e679ec | 7539 | /* 60 */ |
592d1631 L |
7540 | { Bad_Opcode }, |
7541 | { Bad_Opcode }, | |
7542 | { Bad_Opcode }, | |
7543 | { Bad_Opcode }, | |
7544 | { Bad_Opcode }, | |
7545 | { Bad_Opcode }, | |
7546 | { Bad_Opcode }, | |
7547 | { Bad_Opcode }, | |
c0f3af97 | 7548 | /* 68 */ |
592d1631 L |
7549 | { Bad_Opcode }, |
7550 | { Bad_Opcode }, | |
7551 | { Bad_Opcode }, | |
7552 | { Bad_Opcode }, | |
7553 | { Bad_Opcode }, | |
7554 | { Bad_Opcode }, | |
7555 | { Bad_Opcode }, | |
7556 | { Bad_Opcode }, | |
85f10a01 | 7557 | /* 70 */ |
592d1631 L |
7558 | { Bad_Opcode }, |
7559 | { Bad_Opcode }, | |
7560 | { Bad_Opcode }, | |
7561 | { Bad_Opcode }, | |
7562 | { Bad_Opcode }, | |
7563 | { Bad_Opcode }, | |
7564 | { Bad_Opcode }, | |
7565 | { Bad_Opcode }, | |
85f10a01 | 7566 | /* 78 */ |
592d1631 L |
7567 | { Bad_Opcode }, |
7568 | { Bad_Opcode }, | |
7569 | { Bad_Opcode }, | |
7570 | { Bad_Opcode }, | |
7571 | { Bad_Opcode }, | |
7572 | { Bad_Opcode }, | |
7573 | { Bad_Opcode }, | |
7574 | { Bad_Opcode }, | |
85f10a01 | 7575 | /* 80 */ |
592d1631 L |
7576 | { Bad_Opcode }, |
7577 | { Bad_Opcode }, | |
7578 | { Bad_Opcode }, | |
7579 | { Bad_Opcode }, | |
7580 | { Bad_Opcode }, | |
5dd85c99 SP |
7581 | { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
7582 | { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
7583 | { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
7584 | /* 88 */ | |
592d1631 L |
7585 | { Bad_Opcode }, |
7586 | { Bad_Opcode }, | |
7587 | { Bad_Opcode }, | |
7588 | { Bad_Opcode }, | |
7589 | { Bad_Opcode }, | |
7590 | { Bad_Opcode }, | |
5dd85c99 SP |
7591 | { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
7592 | { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
7593 | /* 90 */ | |
592d1631 L |
7594 | { Bad_Opcode }, |
7595 | { Bad_Opcode }, | |
7596 | { Bad_Opcode }, | |
7597 | { Bad_Opcode }, | |
7598 | { Bad_Opcode }, | |
5dd85c99 SP |
7599 | { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
7600 | { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
7601 | { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
7602 | /* 98 */ | |
592d1631 L |
7603 | { Bad_Opcode }, |
7604 | { Bad_Opcode }, | |
7605 | { Bad_Opcode }, | |
7606 | { Bad_Opcode }, | |
7607 | { Bad_Opcode }, | |
7608 | { Bad_Opcode }, | |
5dd85c99 SP |
7609 | { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
7610 | { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
7611 | /* a0 */ | |
592d1631 L |
7612 | { Bad_Opcode }, |
7613 | { Bad_Opcode }, | |
5dd85c99 SP |
7614 | { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
7615 | { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, | |
592d1631 L |
7616 | { Bad_Opcode }, |
7617 | { Bad_Opcode }, | |
5dd85c99 | 7618 | { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
592d1631 | 7619 | { Bad_Opcode }, |
5dd85c99 | 7620 | /* a8 */ |
592d1631 L |
7621 | { Bad_Opcode }, |
7622 | { Bad_Opcode }, | |
7623 | { Bad_Opcode }, | |
7624 | { Bad_Opcode }, | |
7625 | { Bad_Opcode }, | |
7626 | { Bad_Opcode }, | |
7627 | { Bad_Opcode }, | |
7628 | { Bad_Opcode }, | |
5dd85c99 | 7629 | /* b0 */ |
592d1631 L |
7630 | { Bad_Opcode }, |
7631 | { Bad_Opcode }, | |
7632 | { Bad_Opcode }, | |
7633 | { Bad_Opcode }, | |
7634 | { Bad_Opcode }, | |
7635 | { Bad_Opcode }, | |
5dd85c99 | 7636 | { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, |
592d1631 | 7637 | { Bad_Opcode }, |
5dd85c99 | 7638 | /* b8 */ |
592d1631 L |
7639 | { Bad_Opcode }, |
7640 | { Bad_Opcode }, | |
7641 | { Bad_Opcode }, | |
7642 | { Bad_Opcode }, | |
7643 | { Bad_Opcode }, | |
7644 | { Bad_Opcode }, | |
7645 | { Bad_Opcode }, | |
7646 | { Bad_Opcode }, | |
5dd85c99 SP |
7647 | /* c0 */ |
7648 | { "vprotb", { XM, Vex_2src_1, Ib } }, | |
7649 | { "vprotw", { XM, Vex_2src_1, Ib } }, | |
7650 | { "vprotd", { XM, Vex_2src_1, Ib } }, | |
7651 | { "vprotq", { XM, Vex_2src_1, Ib } }, | |
592d1631 L |
7652 | { Bad_Opcode }, |
7653 | { Bad_Opcode }, | |
7654 | { Bad_Opcode }, | |
7655 | { Bad_Opcode }, | |
5dd85c99 | 7656 | /* c8 */ |
592d1631 L |
7657 | { Bad_Opcode }, |
7658 | { Bad_Opcode }, | |
7659 | { Bad_Opcode }, | |
7660 | { Bad_Opcode }, | |
ff688e1f L |
7661 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, |
7662 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, | |
7663 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, | |
7664 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, | |
5dd85c99 | 7665 | /* d0 */ |
592d1631 L |
7666 | { Bad_Opcode }, |
7667 | { Bad_Opcode }, | |
7668 | { Bad_Opcode }, | |
7669 | { Bad_Opcode }, | |
7670 | { Bad_Opcode }, | |
7671 | { Bad_Opcode }, | |
7672 | { Bad_Opcode }, | |
7673 | { Bad_Opcode }, | |
5dd85c99 | 7674 | /* d8 */ |
592d1631 L |
7675 | { Bad_Opcode }, |
7676 | { Bad_Opcode }, | |
7677 | { Bad_Opcode }, | |
7678 | { Bad_Opcode }, | |
7679 | { Bad_Opcode }, | |
7680 | { Bad_Opcode }, | |
7681 | { Bad_Opcode }, | |
7682 | { Bad_Opcode }, | |
5dd85c99 | 7683 | /* e0 */ |
592d1631 L |
7684 | { Bad_Opcode }, |
7685 | { Bad_Opcode }, | |
7686 | { Bad_Opcode }, | |
7687 | { Bad_Opcode }, | |
7688 | { Bad_Opcode }, | |
7689 | { Bad_Opcode }, | |
7690 | { Bad_Opcode }, | |
7691 | { Bad_Opcode }, | |
5dd85c99 | 7692 | /* e8 */ |
592d1631 L |
7693 | { Bad_Opcode }, |
7694 | { Bad_Opcode }, | |
7695 | { Bad_Opcode }, | |
7696 | { Bad_Opcode }, | |
ff688e1f L |
7697 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, |
7698 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, | |
7699 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, | |
7700 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, | |
5dd85c99 | 7701 | /* f0 */ |
592d1631 L |
7702 | { Bad_Opcode }, |
7703 | { Bad_Opcode }, | |
7704 | { Bad_Opcode }, | |
7705 | { Bad_Opcode }, | |
7706 | { Bad_Opcode }, | |
7707 | { Bad_Opcode }, | |
7708 | { Bad_Opcode }, | |
7709 | { Bad_Opcode }, | |
5dd85c99 | 7710 | /* f8 */ |
592d1631 L |
7711 | { Bad_Opcode }, |
7712 | { Bad_Opcode }, | |
7713 | { Bad_Opcode }, | |
7714 | { Bad_Opcode }, | |
7715 | { Bad_Opcode }, | |
7716 | { Bad_Opcode }, | |
7717 | { Bad_Opcode }, | |
7718 | { Bad_Opcode }, | |
5dd85c99 SP |
7719 | }, |
7720 | /* XOP_09 */ | |
7721 | { | |
7722 | /* 00 */ | |
592d1631 | 7723 | { Bad_Opcode }, |
2a2a0f38 QN |
7724 | { REG_TABLE (REG_XOP_TBM_01) }, |
7725 | { REG_TABLE (REG_XOP_TBM_02) }, | |
592d1631 L |
7726 | { Bad_Opcode }, |
7727 | { Bad_Opcode }, | |
7728 | { Bad_Opcode }, | |
7729 | { Bad_Opcode }, | |
7730 | { Bad_Opcode }, | |
5dd85c99 | 7731 | /* 08 */ |
592d1631 L |
7732 | { Bad_Opcode }, |
7733 | { Bad_Opcode }, | |
7734 | { Bad_Opcode }, | |
7735 | { Bad_Opcode }, | |
7736 | { Bad_Opcode }, | |
7737 | { Bad_Opcode }, | |
7738 | { Bad_Opcode }, | |
7739 | { Bad_Opcode }, | |
5dd85c99 | 7740 | /* 10 */ |
592d1631 L |
7741 | { Bad_Opcode }, |
7742 | { Bad_Opcode }, | |
5dd85c99 | 7743 | { REG_TABLE (REG_XOP_LWPCB) }, |
592d1631 L |
7744 | { Bad_Opcode }, |
7745 | { Bad_Opcode }, | |
7746 | { Bad_Opcode }, | |
7747 | { Bad_Opcode }, | |
7748 | { Bad_Opcode }, | |
5dd85c99 | 7749 | /* 18 */ |
592d1631 L |
7750 | { Bad_Opcode }, |
7751 | { Bad_Opcode }, | |
7752 | { Bad_Opcode }, | |
7753 | { Bad_Opcode }, | |
7754 | { Bad_Opcode }, | |
7755 | { Bad_Opcode }, | |
7756 | { Bad_Opcode }, | |
7757 | { Bad_Opcode }, | |
5dd85c99 | 7758 | /* 20 */ |
592d1631 L |
7759 | { Bad_Opcode }, |
7760 | { Bad_Opcode }, | |
7761 | { Bad_Opcode }, | |
7762 | { Bad_Opcode }, | |
7763 | { Bad_Opcode }, | |
7764 | { Bad_Opcode }, | |
7765 | { Bad_Opcode }, | |
7766 | { Bad_Opcode }, | |
5dd85c99 | 7767 | /* 28 */ |
592d1631 L |
7768 | { Bad_Opcode }, |
7769 | { Bad_Opcode }, | |
7770 | { Bad_Opcode }, | |
7771 | { Bad_Opcode }, | |
7772 | { Bad_Opcode }, | |
7773 | { Bad_Opcode }, | |
7774 | { Bad_Opcode }, | |
7775 | { Bad_Opcode }, | |
5dd85c99 | 7776 | /* 30 */ |
592d1631 L |
7777 | { Bad_Opcode }, |
7778 | { Bad_Opcode }, | |
7779 | { Bad_Opcode }, | |
7780 | { Bad_Opcode }, | |
7781 | { Bad_Opcode }, | |
7782 | { Bad_Opcode }, | |
7783 | { Bad_Opcode }, | |
7784 | { Bad_Opcode }, | |
5dd85c99 | 7785 | /* 38 */ |
592d1631 L |
7786 | { Bad_Opcode }, |
7787 | { Bad_Opcode }, | |
7788 | { Bad_Opcode }, | |
7789 | { Bad_Opcode }, | |
7790 | { Bad_Opcode }, | |
7791 | { Bad_Opcode }, | |
7792 | { Bad_Opcode }, | |
7793 | { Bad_Opcode }, | |
5dd85c99 | 7794 | /* 40 */ |
592d1631 L |
7795 | { Bad_Opcode }, |
7796 | { Bad_Opcode }, | |
7797 | { Bad_Opcode }, | |
7798 | { Bad_Opcode }, | |
7799 | { Bad_Opcode }, | |
7800 | { Bad_Opcode }, | |
7801 | { Bad_Opcode }, | |
7802 | { Bad_Opcode }, | |
5dd85c99 | 7803 | /* 48 */ |
592d1631 L |
7804 | { Bad_Opcode }, |
7805 | { Bad_Opcode }, | |
7806 | { Bad_Opcode }, | |
7807 | { Bad_Opcode }, | |
7808 | { Bad_Opcode }, | |
7809 | { Bad_Opcode }, | |
7810 | { Bad_Opcode }, | |
7811 | { Bad_Opcode }, | |
5dd85c99 | 7812 | /* 50 */ |
592d1631 L |
7813 | { Bad_Opcode }, |
7814 | { Bad_Opcode }, | |
7815 | { Bad_Opcode }, | |
7816 | { Bad_Opcode }, | |
7817 | { Bad_Opcode }, | |
7818 | { Bad_Opcode }, | |
7819 | { Bad_Opcode }, | |
7820 | { Bad_Opcode }, | |
5dd85c99 | 7821 | /* 58 */ |
592d1631 L |
7822 | { Bad_Opcode }, |
7823 | { Bad_Opcode }, | |
7824 | { Bad_Opcode }, | |
7825 | { Bad_Opcode }, | |
7826 | { Bad_Opcode }, | |
7827 | { Bad_Opcode }, | |
7828 | { Bad_Opcode }, | |
7829 | { Bad_Opcode }, | |
5dd85c99 | 7830 | /* 60 */ |
592d1631 L |
7831 | { Bad_Opcode }, |
7832 | { Bad_Opcode }, | |
7833 | { Bad_Opcode }, | |
7834 | { Bad_Opcode }, | |
7835 | { Bad_Opcode }, | |
7836 | { Bad_Opcode }, | |
7837 | { Bad_Opcode }, | |
7838 | { Bad_Opcode }, | |
5dd85c99 | 7839 | /* 68 */ |
592d1631 L |
7840 | { Bad_Opcode }, |
7841 | { Bad_Opcode }, | |
7842 | { Bad_Opcode }, | |
7843 | { Bad_Opcode }, | |
7844 | { Bad_Opcode }, | |
7845 | { Bad_Opcode }, | |
7846 | { Bad_Opcode }, | |
7847 | { Bad_Opcode }, | |
5dd85c99 | 7848 | /* 70 */ |
592d1631 L |
7849 | { Bad_Opcode }, |
7850 | { Bad_Opcode }, | |
7851 | { Bad_Opcode }, | |
7852 | { Bad_Opcode }, | |
7853 | { Bad_Opcode }, | |
7854 | { Bad_Opcode }, | |
7855 | { Bad_Opcode }, | |
7856 | { Bad_Opcode }, | |
5dd85c99 | 7857 | /* 78 */ |
592d1631 L |
7858 | { Bad_Opcode }, |
7859 | { Bad_Opcode }, | |
7860 | { Bad_Opcode }, | |
7861 | { Bad_Opcode }, | |
7862 | { Bad_Opcode }, | |
7863 | { Bad_Opcode }, | |
7864 | { Bad_Opcode }, | |
7865 | { Bad_Opcode }, | |
5dd85c99 | 7866 | /* 80 */ |
592a252b L |
7867 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, |
7868 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, | |
5dd85c99 SP |
7869 | { "vfrczss", { XM, EXd } }, |
7870 | { "vfrczsd", { XM, EXq } }, | |
592d1631 L |
7871 | { Bad_Opcode }, |
7872 | { Bad_Opcode }, | |
7873 | { Bad_Opcode }, | |
7874 | { Bad_Opcode }, | |
5dd85c99 | 7875 | /* 88 */ |
592d1631 L |
7876 | { Bad_Opcode }, |
7877 | { Bad_Opcode }, | |
7878 | { Bad_Opcode }, | |
7879 | { Bad_Opcode }, | |
7880 | { Bad_Opcode }, | |
7881 | { Bad_Opcode }, | |
7882 | { Bad_Opcode }, | |
7883 | { Bad_Opcode }, | |
5dd85c99 SP |
7884 | /* 90 */ |
7885 | { "vprotb", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7886 | { "vprotw", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7887 | { "vprotd", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7888 | { "vprotq", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7889 | { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7890 | { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7891 | { "vpshld", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7892 | { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7893 | /* 98 */ | |
7894 | { "vpshab", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7895 | { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7896 | { "vpshad", { XM, Vex_2src_1, Vex_2src_2 } }, | |
7897 | { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 } }, | |
592d1631 L |
7898 | { Bad_Opcode }, |
7899 | { Bad_Opcode }, | |
7900 | { Bad_Opcode }, | |
7901 | { Bad_Opcode }, | |
5dd85c99 | 7902 | /* a0 */ |
592d1631 L |
7903 | { Bad_Opcode }, |
7904 | { Bad_Opcode }, | |
7905 | { Bad_Opcode }, | |
7906 | { Bad_Opcode }, | |
7907 | { Bad_Opcode }, | |
7908 | { Bad_Opcode }, | |
7909 | { Bad_Opcode }, | |
7910 | { Bad_Opcode }, | |
5dd85c99 | 7911 | /* a8 */ |
592d1631 L |
7912 | { Bad_Opcode }, |
7913 | { Bad_Opcode }, | |
7914 | { Bad_Opcode }, | |
7915 | { Bad_Opcode }, | |
7916 | { Bad_Opcode }, | |
7917 | { Bad_Opcode }, | |
7918 | { Bad_Opcode }, | |
7919 | { Bad_Opcode }, | |
5dd85c99 | 7920 | /* b0 */ |
592d1631 L |
7921 | { Bad_Opcode }, |
7922 | { Bad_Opcode }, | |
7923 | { Bad_Opcode }, | |
7924 | { Bad_Opcode }, | |
7925 | { Bad_Opcode }, | |
7926 | { Bad_Opcode }, | |
7927 | { Bad_Opcode }, | |
7928 | { Bad_Opcode }, | |
5dd85c99 | 7929 | /* b8 */ |
592d1631 L |
7930 | { Bad_Opcode }, |
7931 | { Bad_Opcode }, | |
7932 | { Bad_Opcode }, | |
7933 | { Bad_Opcode }, | |
7934 | { Bad_Opcode }, | |
7935 | { Bad_Opcode }, | |
7936 | { Bad_Opcode }, | |
7937 | { Bad_Opcode }, | |
5dd85c99 | 7938 | /* c0 */ |
592d1631 | 7939 | { Bad_Opcode }, |
5dd85c99 SP |
7940 | { "vphaddbw", { XM, EXxmm } }, |
7941 | { "vphaddbd", { XM, EXxmm } }, | |
7942 | { "vphaddbq", { XM, EXxmm } }, | |
592d1631 L |
7943 | { Bad_Opcode }, |
7944 | { Bad_Opcode }, | |
5dd85c99 SP |
7945 | { "vphaddwd", { XM, EXxmm } }, |
7946 | { "vphaddwq", { XM, EXxmm } }, | |
7947 | /* c8 */ | |
592d1631 L |
7948 | { Bad_Opcode }, |
7949 | { Bad_Opcode }, | |
7950 | { Bad_Opcode }, | |
5dd85c99 | 7951 | { "vphadddq", { XM, EXxmm } }, |
592d1631 L |
7952 | { Bad_Opcode }, |
7953 | { Bad_Opcode }, | |
7954 | { Bad_Opcode }, | |
7955 | { Bad_Opcode }, | |
5dd85c99 | 7956 | /* d0 */ |
592d1631 | 7957 | { Bad_Opcode }, |
5dd85c99 SP |
7958 | { "vphaddubw", { XM, EXxmm } }, |
7959 | { "vphaddubd", { XM, EXxmm } }, | |
7960 | { "vphaddubq", { XM, EXxmm } }, | |
592d1631 L |
7961 | { Bad_Opcode }, |
7962 | { Bad_Opcode }, | |
5dd85c99 SP |
7963 | { "vphadduwd", { XM, EXxmm } }, |
7964 | { "vphadduwq", { XM, EXxmm } }, | |
7965 | /* d8 */ | |
592d1631 L |
7966 | { Bad_Opcode }, |
7967 | { Bad_Opcode }, | |
7968 | { Bad_Opcode }, | |
5dd85c99 | 7969 | { "vphaddudq", { XM, EXxmm } }, |
592d1631 L |
7970 | { Bad_Opcode }, |
7971 | { Bad_Opcode }, | |
7972 | { Bad_Opcode }, | |
7973 | { Bad_Opcode }, | |
5dd85c99 | 7974 | /* e0 */ |
592d1631 | 7975 | { Bad_Opcode }, |
5dd85c99 SP |
7976 | { "vphsubbw", { XM, EXxmm } }, |
7977 | { "vphsubwd", { XM, EXxmm } }, | |
7978 | { "vphsubdq", { XM, EXxmm } }, | |
592d1631 L |
7979 | { Bad_Opcode }, |
7980 | { Bad_Opcode }, | |
7981 | { Bad_Opcode }, | |
7982 | { Bad_Opcode }, | |
4e7d34a6 | 7983 | /* e8 */ |
592d1631 L |
7984 | { Bad_Opcode }, |
7985 | { Bad_Opcode }, | |
7986 | { Bad_Opcode }, | |
7987 | { Bad_Opcode }, | |
7988 | { Bad_Opcode }, | |
7989 | { Bad_Opcode }, | |
7990 | { Bad_Opcode }, | |
7991 | { Bad_Opcode }, | |
4e7d34a6 | 7992 | /* f0 */ |
592d1631 L |
7993 | { Bad_Opcode }, |
7994 | { Bad_Opcode }, | |
7995 | { Bad_Opcode }, | |
7996 | { Bad_Opcode }, | |
7997 | { Bad_Opcode }, | |
7998 | { Bad_Opcode }, | |
7999 | { Bad_Opcode }, | |
8000 | { Bad_Opcode }, | |
4e7d34a6 | 8001 | /* f8 */ |
592d1631 L |
8002 | { Bad_Opcode }, |
8003 | { Bad_Opcode }, | |
8004 | { Bad_Opcode }, | |
8005 | { Bad_Opcode }, | |
8006 | { Bad_Opcode }, | |
8007 | { Bad_Opcode }, | |
8008 | { Bad_Opcode }, | |
8009 | { Bad_Opcode }, | |
4e7d34a6 | 8010 | }, |
f88c9eb0 | 8011 | /* XOP_0A */ |
4e7d34a6 L |
8012 | { |
8013 | /* 00 */ | |
592d1631 L |
8014 | { Bad_Opcode }, |
8015 | { Bad_Opcode }, | |
8016 | { Bad_Opcode }, | |
8017 | { Bad_Opcode }, | |
8018 | { Bad_Opcode }, | |
8019 | { Bad_Opcode }, | |
8020 | { Bad_Opcode }, | |
8021 | { Bad_Opcode }, | |
4e7d34a6 | 8022 | /* 08 */ |
592d1631 L |
8023 | { Bad_Opcode }, |
8024 | { Bad_Opcode }, | |
8025 | { Bad_Opcode }, | |
8026 | { Bad_Opcode }, | |
8027 | { Bad_Opcode }, | |
8028 | { Bad_Opcode }, | |
8029 | { Bad_Opcode }, | |
8030 | { Bad_Opcode }, | |
4e7d34a6 | 8031 | /* 10 */ |
2a2a0f38 | 8032 | { "bextr", { Gv, Ev, Iq } }, |
592d1631 | 8033 | { Bad_Opcode }, |
f88c9eb0 | 8034 | { REG_TABLE (REG_XOP_LWP) }, |
592d1631 L |
8035 | { Bad_Opcode }, |
8036 | { Bad_Opcode }, | |
8037 | { Bad_Opcode }, | |
8038 | { Bad_Opcode }, | |
8039 | { Bad_Opcode }, | |
4e7d34a6 | 8040 | /* 18 */ |
592d1631 L |
8041 | { Bad_Opcode }, |
8042 | { Bad_Opcode }, | |
8043 | { Bad_Opcode }, | |
8044 | { Bad_Opcode }, | |
8045 | { Bad_Opcode }, | |
8046 | { Bad_Opcode }, | |
8047 | { Bad_Opcode }, | |
8048 | { Bad_Opcode }, | |
4e7d34a6 | 8049 | /* 20 */ |
592d1631 L |
8050 | { Bad_Opcode }, |
8051 | { Bad_Opcode }, | |
8052 | { Bad_Opcode }, | |
8053 | { Bad_Opcode }, | |
8054 | { Bad_Opcode }, | |
8055 | { Bad_Opcode }, | |
8056 | { Bad_Opcode }, | |
8057 | { Bad_Opcode }, | |
4e7d34a6 | 8058 | /* 28 */ |
592d1631 L |
8059 | { Bad_Opcode }, |
8060 | { Bad_Opcode }, | |
8061 | { Bad_Opcode }, | |
8062 | { Bad_Opcode }, | |
8063 | { Bad_Opcode }, | |
8064 | { Bad_Opcode }, | |
8065 | { Bad_Opcode }, | |
8066 | { Bad_Opcode }, | |
4e7d34a6 | 8067 | /* 30 */ |
592d1631 L |
8068 | { Bad_Opcode }, |
8069 | { Bad_Opcode }, | |
8070 | { Bad_Opcode }, | |
8071 | { Bad_Opcode }, | |
8072 | { Bad_Opcode }, | |
8073 | { Bad_Opcode }, | |
8074 | { Bad_Opcode }, | |
8075 | { Bad_Opcode }, | |
c0f3af97 | 8076 | /* 38 */ |
592d1631 L |
8077 | { Bad_Opcode }, |
8078 | { Bad_Opcode }, | |
8079 | { Bad_Opcode }, | |
8080 | { Bad_Opcode }, | |
8081 | { Bad_Opcode }, | |
8082 | { Bad_Opcode }, | |
8083 | { Bad_Opcode }, | |
8084 | { Bad_Opcode }, | |
c0f3af97 | 8085 | /* 40 */ |
592d1631 L |
8086 | { Bad_Opcode }, |
8087 | { Bad_Opcode }, | |
8088 | { Bad_Opcode }, | |
8089 | { Bad_Opcode }, | |
8090 | { Bad_Opcode }, | |
8091 | { Bad_Opcode }, | |
8092 | { Bad_Opcode }, | |
8093 | { Bad_Opcode }, | |
c1e679ec | 8094 | /* 48 */ |
592d1631 L |
8095 | { Bad_Opcode }, |
8096 | { Bad_Opcode }, | |
8097 | { Bad_Opcode }, | |
8098 | { Bad_Opcode }, | |
8099 | { Bad_Opcode }, | |
8100 | { Bad_Opcode }, | |
8101 | { Bad_Opcode }, | |
8102 | { Bad_Opcode }, | |
c1e679ec | 8103 | /* 50 */ |
592d1631 L |
8104 | { Bad_Opcode }, |
8105 | { Bad_Opcode }, | |
8106 | { Bad_Opcode }, | |
8107 | { Bad_Opcode }, | |
8108 | { Bad_Opcode }, | |
8109 | { Bad_Opcode }, | |
8110 | { Bad_Opcode }, | |
8111 | { Bad_Opcode }, | |
4e7d34a6 | 8112 | /* 58 */ |
592d1631 L |
8113 | { Bad_Opcode }, |
8114 | { Bad_Opcode }, | |
8115 | { Bad_Opcode }, | |
8116 | { Bad_Opcode }, | |
8117 | { Bad_Opcode }, | |
8118 | { Bad_Opcode }, | |
8119 | { Bad_Opcode }, | |
8120 | { Bad_Opcode }, | |
4e7d34a6 | 8121 | /* 60 */ |
592d1631 L |
8122 | { Bad_Opcode }, |
8123 | { Bad_Opcode }, | |
8124 | { Bad_Opcode }, | |
8125 | { Bad_Opcode }, | |
8126 | { Bad_Opcode }, | |
8127 | { Bad_Opcode }, | |
8128 | { Bad_Opcode }, | |
8129 | { Bad_Opcode }, | |
4e7d34a6 | 8130 | /* 68 */ |
592d1631 L |
8131 | { Bad_Opcode }, |
8132 | { Bad_Opcode }, | |
8133 | { Bad_Opcode }, | |
8134 | { Bad_Opcode }, | |
8135 | { Bad_Opcode }, | |
8136 | { Bad_Opcode }, | |
8137 | { Bad_Opcode }, | |
8138 | { Bad_Opcode }, | |
4e7d34a6 | 8139 | /* 70 */ |
592d1631 L |
8140 | { Bad_Opcode }, |
8141 | { Bad_Opcode }, | |
8142 | { Bad_Opcode }, | |
8143 | { Bad_Opcode }, | |
8144 | { Bad_Opcode }, | |
8145 | { Bad_Opcode }, | |
8146 | { Bad_Opcode }, | |
8147 | { Bad_Opcode }, | |
4e7d34a6 | 8148 | /* 78 */ |
592d1631 L |
8149 | { Bad_Opcode }, |
8150 | { Bad_Opcode }, | |
8151 | { Bad_Opcode }, | |
8152 | { Bad_Opcode }, | |
8153 | { Bad_Opcode }, | |
8154 | { Bad_Opcode }, | |
8155 | { Bad_Opcode }, | |
8156 | { Bad_Opcode }, | |
4e7d34a6 | 8157 | /* 80 */ |
592d1631 L |
8158 | { Bad_Opcode }, |
8159 | { Bad_Opcode }, | |
8160 | { Bad_Opcode }, | |
8161 | { Bad_Opcode }, | |
8162 | { Bad_Opcode }, | |
8163 | { Bad_Opcode }, | |
8164 | { Bad_Opcode }, | |
8165 | { Bad_Opcode }, | |
4e7d34a6 | 8166 | /* 88 */ |
592d1631 L |
8167 | { Bad_Opcode }, |
8168 | { Bad_Opcode }, | |
8169 | { Bad_Opcode }, | |
8170 | { Bad_Opcode }, | |
8171 | { Bad_Opcode }, | |
8172 | { Bad_Opcode }, | |
8173 | { Bad_Opcode }, | |
8174 | { Bad_Opcode }, | |
4e7d34a6 | 8175 | /* 90 */ |
592d1631 L |
8176 | { Bad_Opcode }, |
8177 | { Bad_Opcode }, | |
8178 | { Bad_Opcode }, | |
8179 | { Bad_Opcode }, | |
8180 | { Bad_Opcode }, | |
8181 | { Bad_Opcode }, | |
8182 | { Bad_Opcode }, | |
8183 | { Bad_Opcode }, | |
4e7d34a6 | 8184 | /* 98 */ |
592d1631 L |
8185 | { Bad_Opcode }, |
8186 | { Bad_Opcode }, | |
8187 | { Bad_Opcode }, | |
8188 | { Bad_Opcode }, | |
8189 | { Bad_Opcode }, | |
8190 | { Bad_Opcode }, | |
8191 | { Bad_Opcode }, | |
8192 | { Bad_Opcode }, | |
4e7d34a6 | 8193 | /* a0 */ |
592d1631 L |
8194 | { Bad_Opcode }, |
8195 | { Bad_Opcode }, | |
8196 | { Bad_Opcode }, | |
8197 | { Bad_Opcode }, | |
8198 | { Bad_Opcode }, | |
8199 | { Bad_Opcode }, | |
8200 | { Bad_Opcode }, | |
8201 | { Bad_Opcode }, | |
4e7d34a6 | 8202 | /* a8 */ |
592d1631 L |
8203 | { Bad_Opcode }, |
8204 | { Bad_Opcode }, | |
8205 | { Bad_Opcode }, | |
8206 | { Bad_Opcode }, | |
8207 | { Bad_Opcode }, | |
8208 | { Bad_Opcode }, | |
8209 | { Bad_Opcode }, | |
8210 | { Bad_Opcode }, | |
d5d7db8e | 8211 | /* b0 */ |
592d1631 L |
8212 | { Bad_Opcode }, |
8213 | { Bad_Opcode }, | |
8214 | { Bad_Opcode }, | |
8215 | { Bad_Opcode }, | |
8216 | { Bad_Opcode }, | |
8217 | { Bad_Opcode }, | |
8218 | { Bad_Opcode }, | |
8219 | { Bad_Opcode }, | |
85f10a01 | 8220 | /* b8 */ |
592d1631 L |
8221 | { Bad_Opcode }, |
8222 | { Bad_Opcode }, | |
8223 | { Bad_Opcode }, | |
8224 | { Bad_Opcode }, | |
8225 | { Bad_Opcode }, | |
8226 | { Bad_Opcode }, | |
8227 | { Bad_Opcode }, | |
8228 | { Bad_Opcode }, | |
85f10a01 | 8229 | /* c0 */ |
592d1631 L |
8230 | { Bad_Opcode }, |
8231 | { Bad_Opcode }, | |
8232 | { Bad_Opcode }, | |
8233 | { Bad_Opcode }, | |
8234 | { Bad_Opcode }, | |
8235 | { Bad_Opcode }, | |
8236 | { Bad_Opcode }, | |
8237 | { Bad_Opcode }, | |
85f10a01 | 8238 | /* c8 */ |
592d1631 L |
8239 | { Bad_Opcode }, |
8240 | { Bad_Opcode }, | |
8241 | { Bad_Opcode }, | |
8242 | { Bad_Opcode }, | |
8243 | { Bad_Opcode }, | |
8244 | { Bad_Opcode }, | |
8245 | { Bad_Opcode }, | |
8246 | { Bad_Opcode }, | |
85f10a01 | 8247 | /* d0 */ |
592d1631 L |
8248 | { Bad_Opcode }, |
8249 | { Bad_Opcode }, | |
8250 | { Bad_Opcode }, | |
8251 | { Bad_Opcode }, | |
8252 | { Bad_Opcode }, | |
8253 | { Bad_Opcode }, | |
8254 | { Bad_Opcode }, | |
8255 | { Bad_Opcode }, | |
85f10a01 | 8256 | /* d8 */ |
592d1631 L |
8257 | { Bad_Opcode }, |
8258 | { Bad_Opcode }, | |
8259 | { Bad_Opcode }, | |
8260 | { Bad_Opcode }, | |
8261 | { Bad_Opcode }, | |
8262 | { Bad_Opcode }, | |
8263 | { Bad_Opcode }, | |
8264 | { Bad_Opcode }, | |
85f10a01 | 8265 | /* e0 */ |
592d1631 L |
8266 | { Bad_Opcode }, |
8267 | { Bad_Opcode }, | |
8268 | { Bad_Opcode }, | |
8269 | { Bad_Opcode }, | |
8270 | { Bad_Opcode }, | |
8271 | { Bad_Opcode }, | |
8272 | { Bad_Opcode }, | |
8273 | { Bad_Opcode }, | |
85f10a01 | 8274 | /* e8 */ |
592d1631 L |
8275 | { Bad_Opcode }, |
8276 | { Bad_Opcode }, | |
8277 | { Bad_Opcode }, | |
8278 | { Bad_Opcode }, | |
8279 | { Bad_Opcode }, | |
8280 | { Bad_Opcode }, | |
8281 | { Bad_Opcode }, | |
8282 | { Bad_Opcode }, | |
85f10a01 | 8283 | /* f0 */ |
592d1631 L |
8284 | { Bad_Opcode }, |
8285 | { Bad_Opcode }, | |
8286 | { Bad_Opcode }, | |
8287 | { Bad_Opcode }, | |
8288 | { Bad_Opcode }, | |
8289 | { Bad_Opcode }, | |
8290 | { Bad_Opcode }, | |
8291 | { Bad_Opcode }, | |
85f10a01 | 8292 | /* f8 */ |
592d1631 L |
8293 | { Bad_Opcode }, |
8294 | { Bad_Opcode }, | |
8295 | { Bad_Opcode }, | |
8296 | { Bad_Opcode }, | |
8297 | { Bad_Opcode }, | |
8298 | { Bad_Opcode }, | |
8299 | { Bad_Opcode }, | |
8300 | { Bad_Opcode }, | |
85f10a01 | 8301 | }, |
c0f3af97 L |
8302 | }; |
8303 | ||
8304 | static const struct dis386 vex_table[][256] = { | |
8305 | /* VEX_0F */ | |
85f10a01 MM |
8306 | { |
8307 | /* 00 */ | |
592d1631 L |
8308 | { Bad_Opcode }, |
8309 | { Bad_Opcode }, | |
8310 | { Bad_Opcode }, | |
8311 | { Bad_Opcode }, | |
8312 | { Bad_Opcode }, | |
8313 | { Bad_Opcode }, | |
8314 | { Bad_Opcode }, | |
8315 | { Bad_Opcode }, | |
85f10a01 | 8316 | /* 08 */ |
592d1631 L |
8317 | { Bad_Opcode }, |
8318 | { Bad_Opcode }, | |
8319 | { Bad_Opcode }, | |
8320 | { Bad_Opcode }, | |
8321 | { Bad_Opcode }, | |
8322 | { Bad_Opcode }, | |
8323 | { Bad_Opcode }, | |
8324 | { Bad_Opcode }, | |
c0f3af97 | 8325 | /* 10 */ |
592a252b L |
8326 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
8327 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, | |
8328 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, | |
8329 | { MOD_TABLE (MOD_VEX_0F13) }, | |
8330 | { VEX_W_TABLE (VEX_W_0F14) }, | |
8331 | { VEX_W_TABLE (VEX_W_0F15) }, | |
8332 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, | |
8333 | { MOD_TABLE (MOD_VEX_0F17) }, | |
c0f3af97 | 8334 | /* 18 */ |
592d1631 L |
8335 | { Bad_Opcode }, |
8336 | { Bad_Opcode }, | |
8337 | { Bad_Opcode }, | |
8338 | { Bad_Opcode }, | |
8339 | { Bad_Opcode }, | |
8340 | { Bad_Opcode }, | |
8341 | { Bad_Opcode }, | |
8342 | { Bad_Opcode }, | |
c0f3af97 | 8343 | /* 20 */ |
592d1631 L |
8344 | { Bad_Opcode }, |
8345 | { Bad_Opcode }, | |
8346 | { Bad_Opcode }, | |
8347 | { Bad_Opcode }, | |
8348 | { Bad_Opcode }, | |
8349 | { Bad_Opcode }, | |
8350 | { Bad_Opcode }, | |
8351 | { Bad_Opcode }, | |
c0f3af97 | 8352 | /* 28 */ |
592a252b L |
8353 | { VEX_W_TABLE (VEX_W_0F28) }, |
8354 | { VEX_W_TABLE (VEX_W_0F29) }, | |
8355 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, | |
8356 | { MOD_TABLE (MOD_VEX_0F2B) }, | |
8357 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, | |
8358 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, | |
8359 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, | |
8360 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, | |
85f10a01 | 8361 | /* 30 */ |
592d1631 L |
8362 | { Bad_Opcode }, |
8363 | { Bad_Opcode }, | |
8364 | { Bad_Opcode }, | |
8365 | { Bad_Opcode }, | |
8366 | { Bad_Opcode }, | |
8367 | { Bad_Opcode }, | |
8368 | { Bad_Opcode }, | |
8369 | { Bad_Opcode }, | |
4e7d34a6 | 8370 | /* 38 */ |
592d1631 L |
8371 | { Bad_Opcode }, |
8372 | { Bad_Opcode }, | |
8373 | { Bad_Opcode }, | |
8374 | { Bad_Opcode }, | |
8375 | { Bad_Opcode }, | |
8376 | { Bad_Opcode }, | |
8377 | { Bad_Opcode }, | |
8378 | { Bad_Opcode }, | |
d5d7db8e | 8379 | /* 40 */ |
592d1631 | 8380 | { Bad_Opcode }, |
43234a1e L |
8381 | { PREFIX_TABLE (PREFIX_VEX_0F41) }, |
8382 | { PREFIX_TABLE (PREFIX_VEX_0F42) }, | |
592d1631 | 8383 | { Bad_Opcode }, |
43234a1e L |
8384 | { PREFIX_TABLE (PREFIX_VEX_0F44) }, |
8385 | { PREFIX_TABLE (PREFIX_VEX_0F45) }, | |
8386 | { PREFIX_TABLE (PREFIX_VEX_0F46) }, | |
8387 | { PREFIX_TABLE (PREFIX_VEX_0F47) }, | |
85f10a01 | 8388 | /* 48 */ |
592d1631 L |
8389 | { Bad_Opcode }, |
8390 | { Bad_Opcode }, | |
8391 | { Bad_Opcode }, | |
43234a1e | 8392 | { PREFIX_TABLE (PREFIX_VEX_0F4B) }, |
592d1631 L |
8393 | { Bad_Opcode }, |
8394 | { Bad_Opcode }, | |
8395 | { Bad_Opcode }, | |
8396 | { Bad_Opcode }, | |
d5d7db8e | 8397 | /* 50 */ |
592a252b L |
8398 | { MOD_TABLE (MOD_VEX_0F50) }, |
8399 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, | |
8400 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, | |
8401 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, | |
c0f3af97 L |
8402 | { "vandpX", { XM, Vex, EXx } }, |
8403 | { "vandnpX", { XM, Vex, EXx } }, | |
8404 | { "vorpX", { XM, Vex, EXx } }, | |
8405 | { "vxorpX", { XM, Vex, EXx } }, | |
8406 | /* 58 */ | |
592a252b L |
8407 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
8408 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, | |
8409 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, | |
8410 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, | |
8411 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, | |
8412 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, | |
8413 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, | |
8414 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, | |
c0f3af97 | 8415 | /* 60 */ |
592a252b L |
8416 | { PREFIX_TABLE (PREFIX_VEX_0F60) }, |
8417 | { PREFIX_TABLE (PREFIX_VEX_0F61) }, | |
8418 | { PREFIX_TABLE (PREFIX_VEX_0F62) }, | |
8419 | { PREFIX_TABLE (PREFIX_VEX_0F63) }, | |
8420 | { PREFIX_TABLE (PREFIX_VEX_0F64) }, | |
8421 | { PREFIX_TABLE (PREFIX_VEX_0F65) }, | |
8422 | { PREFIX_TABLE (PREFIX_VEX_0F66) }, | |
8423 | { PREFIX_TABLE (PREFIX_VEX_0F67) }, | |
c0f3af97 | 8424 | /* 68 */ |
592a252b L |
8425 | { PREFIX_TABLE (PREFIX_VEX_0F68) }, |
8426 | { PREFIX_TABLE (PREFIX_VEX_0F69) }, | |
8427 | { PREFIX_TABLE (PREFIX_VEX_0F6A) }, | |
8428 | { PREFIX_TABLE (PREFIX_VEX_0F6B) }, | |
8429 | { PREFIX_TABLE (PREFIX_VEX_0F6C) }, | |
8430 | { PREFIX_TABLE (PREFIX_VEX_0F6D) }, | |
8431 | { PREFIX_TABLE (PREFIX_VEX_0F6E) }, | |
8432 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, | |
c0f3af97 | 8433 | /* 70 */ |
592a252b L |
8434 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
8435 | { REG_TABLE (REG_VEX_0F71) }, | |
8436 | { REG_TABLE (REG_VEX_0F72) }, | |
8437 | { REG_TABLE (REG_VEX_0F73) }, | |
8438 | { PREFIX_TABLE (PREFIX_VEX_0F74) }, | |
8439 | { PREFIX_TABLE (PREFIX_VEX_0F75) }, | |
8440 | { PREFIX_TABLE (PREFIX_VEX_0F76) }, | |
8441 | { PREFIX_TABLE (PREFIX_VEX_0F77) }, | |
c0f3af97 | 8442 | /* 78 */ |
592d1631 L |
8443 | { Bad_Opcode }, |
8444 | { Bad_Opcode }, | |
8445 | { Bad_Opcode }, | |
8446 | { Bad_Opcode }, | |
592a252b L |
8447 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
8448 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, | |
8449 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, | |
8450 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, | |
c0f3af97 | 8451 | /* 80 */ |
592d1631 L |
8452 | { Bad_Opcode }, |
8453 | { Bad_Opcode }, | |
8454 | { Bad_Opcode }, | |
8455 | { Bad_Opcode }, | |
8456 | { Bad_Opcode }, | |
8457 | { Bad_Opcode }, | |
8458 | { Bad_Opcode }, | |
8459 | { Bad_Opcode }, | |
c0f3af97 | 8460 | /* 88 */ |
592d1631 L |
8461 | { Bad_Opcode }, |
8462 | { Bad_Opcode }, | |
8463 | { Bad_Opcode }, | |
8464 | { Bad_Opcode }, | |
8465 | { Bad_Opcode }, | |
8466 | { Bad_Opcode }, | |
8467 | { Bad_Opcode }, | |
8468 | { Bad_Opcode }, | |
c0f3af97 | 8469 | /* 90 */ |
43234a1e L |
8470 | { PREFIX_TABLE (PREFIX_VEX_0F90) }, |
8471 | { PREFIX_TABLE (PREFIX_VEX_0F91) }, | |
8472 | { PREFIX_TABLE (PREFIX_VEX_0F92) }, | |
8473 | { PREFIX_TABLE (PREFIX_VEX_0F93) }, | |
592d1631 L |
8474 | { Bad_Opcode }, |
8475 | { Bad_Opcode }, | |
8476 | { Bad_Opcode }, | |
8477 | { Bad_Opcode }, | |
c0f3af97 | 8478 | /* 98 */ |
43234a1e | 8479 | { PREFIX_TABLE (PREFIX_VEX_0F98) }, |
592d1631 L |
8480 | { Bad_Opcode }, |
8481 | { Bad_Opcode }, | |
8482 | { Bad_Opcode }, | |
8483 | { Bad_Opcode }, | |
8484 | { Bad_Opcode }, | |
8485 | { Bad_Opcode }, | |
8486 | { Bad_Opcode }, | |
c0f3af97 | 8487 | /* a0 */ |
592d1631 L |
8488 | { Bad_Opcode }, |
8489 | { Bad_Opcode }, | |
8490 | { Bad_Opcode }, | |
8491 | { Bad_Opcode }, | |
8492 | { Bad_Opcode }, | |
8493 | { Bad_Opcode }, | |
8494 | { Bad_Opcode }, | |
8495 | { Bad_Opcode }, | |
c0f3af97 | 8496 | /* a8 */ |
592d1631 L |
8497 | { Bad_Opcode }, |
8498 | { Bad_Opcode }, | |
8499 | { Bad_Opcode }, | |
8500 | { Bad_Opcode }, | |
8501 | { Bad_Opcode }, | |
8502 | { Bad_Opcode }, | |
592a252b | 8503 | { REG_TABLE (REG_VEX_0FAE) }, |
592d1631 | 8504 | { Bad_Opcode }, |
c0f3af97 | 8505 | /* b0 */ |
592d1631 L |
8506 | { Bad_Opcode }, |
8507 | { Bad_Opcode }, | |
8508 | { Bad_Opcode }, | |
8509 | { Bad_Opcode }, | |
8510 | { Bad_Opcode }, | |
8511 | { Bad_Opcode }, | |
8512 | { Bad_Opcode }, | |
8513 | { Bad_Opcode }, | |
c0f3af97 | 8514 | /* b8 */ |
592d1631 L |
8515 | { Bad_Opcode }, |
8516 | { Bad_Opcode }, | |
8517 | { Bad_Opcode }, | |
8518 | { Bad_Opcode }, | |
8519 | { Bad_Opcode }, | |
8520 | { Bad_Opcode }, | |
8521 | { Bad_Opcode }, | |
8522 | { Bad_Opcode }, | |
c0f3af97 | 8523 | /* c0 */ |
592d1631 L |
8524 | { Bad_Opcode }, |
8525 | { Bad_Opcode }, | |
592a252b | 8526 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
592d1631 | 8527 | { Bad_Opcode }, |
592a252b L |
8528 | { PREFIX_TABLE (PREFIX_VEX_0FC4) }, |
8529 | { PREFIX_TABLE (PREFIX_VEX_0FC5) }, | |
c0f3af97 | 8530 | { "vshufpX", { XM, Vex, EXx, Ib } }, |
592d1631 | 8531 | { Bad_Opcode }, |
c0f3af97 | 8532 | /* c8 */ |
592d1631 L |
8533 | { Bad_Opcode }, |
8534 | { Bad_Opcode }, | |
8535 | { Bad_Opcode }, | |
8536 | { Bad_Opcode }, | |
8537 | { Bad_Opcode }, | |
8538 | { Bad_Opcode }, | |
8539 | { Bad_Opcode }, | |
8540 | { Bad_Opcode }, | |
c0f3af97 | 8541 | /* d0 */ |
592a252b L |
8542 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
8543 | { PREFIX_TABLE (PREFIX_VEX_0FD1) }, | |
8544 | { PREFIX_TABLE (PREFIX_VEX_0FD2) }, | |
8545 | { PREFIX_TABLE (PREFIX_VEX_0FD3) }, | |
8546 | { PREFIX_TABLE (PREFIX_VEX_0FD4) }, | |
8547 | { PREFIX_TABLE (PREFIX_VEX_0FD5) }, | |
8548 | { PREFIX_TABLE (PREFIX_VEX_0FD6) }, | |
8549 | { PREFIX_TABLE (PREFIX_VEX_0FD7) }, | |
c0f3af97 | 8550 | /* d8 */ |
592a252b L |
8551 | { PREFIX_TABLE (PREFIX_VEX_0FD8) }, |
8552 | { PREFIX_TABLE (PREFIX_VEX_0FD9) }, | |
8553 | { PREFIX_TABLE (PREFIX_VEX_0FDA) }, | |
8554 | { PREFIX_TABLE (PREFIX_VEX_0FDB) }, | |
8555 | { PREFIX_TABLE (PREFIX_VEX_0FDC) }, | |
8556 | { PREFIX_TABLE (PREFIX_VEX_0FDD) }, | |
8557 | { PREFIX_TABLE (PREFIX_VEX_0FDE) }, | |
8558 | { PREFIX_TABLE (PREFIX_VEX_0FDF) }, | |
c0f3af97 | 8559 | /* e0 */ |
592a252b L |
8560 | { PREFIX_TABLE (PREFIX_VEX_0FE0) }, |
8561 | { PREFIX_TABLE (PREFIX_VEX_0FE1) }, | |
8562 | { PREFIX_TABLE (PREFIX_VEX_0FE2) }, | |
8563 | { PREFIX_TABLE (PREFIX_VEX_0FE3) }, | |
8564 | { PREFIX_TABLE (PREFIX_VEX_0FE4) }, | |
8565 | { PREFIX_TABLE (PREFIX_VEX_0FE5) }, | |
8566 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, | |
8567 | { PREFIX_TABLE (PREFIX_VEX_0FE7) }, | |
c0f3af97 | 8568 | /* e8 */ |
592a252b L |
8569 | { PREFIX_TABLE (PREFIX_VEX_0FE8) }, |
8570 | { PREFIX_TABLE (PREFIX_VEX_0FE9) }, | |
8571 | { PREFIX_TABLE (PREFIX_VEX_0FEA) }, | |
8572 | { PREFIX_TABLE (PREFIX_VEX_0FEB) }, | |
8573 | { PREFIX_TABLE (PREFIX_VEX_0FEC) }, | |
8574 | { PREFIX_TABLE (PREFIX_VEX_0FED) }, | |
8575 | { PREFIX_TABLE (PREFIX_VEX_0FEE) }, | |
8576 | { PREFIX_TABLE (PREFIX_VEX_0FEF) }, | |
c0f3af97 | 8577 | /* f0 */ |
592a252b L |
8578 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
8579 | { PREFIX_TABLE (PREFIX_VEX_0FF1) }, | |
8580 | { PREFIX_TABLE (PREFIX_VEX_0FF2) }, | |
8581 | { PREFIX_TABLE (PREFIX_VEX_0FF3) }, | |
8582 | { PREFIX_TABLE (PREFIX_VEX_0FF4) }, | |
8583 | { PREFIX_TABLE (PREFIX_VEX_0FF5) }, | |
8584 | { PREFIX_TABLE (PREFIX_VEX_0FF6) }, | |
8585 | { PREFIX_TABLE (PREFIX_VEX_0FF7) }, | |
c0f3af97 | 8586 | /* f8 */ |
592a252b L |
8587 | { PREFIX_TABLE (PREFIX_VEX_0FF8) }, |
8588 | { PREFIX_TABLE (PREFIX_VEX_0FF9) }, | |
8589 | { PREFIX_TABLE (PREFIX_VEX_0FFA) }, | |
8590 | { PREFIX_TABLE (PREFIX_VEX_0FFB) }, | |
8591 | { PREFIX_TABLE (PREFIX_VEX_0FFC) }, | |
8592 | { PREFIX_TABLE (PREFIX_VEX_0FFD) }, | |
8593 | { PREFIX_TABLE (PREFIX_VEX_0FFE) }, | |
592d1631 | 8594 | { Bad_Opcode }, |
c0f3af97 L |
8595 | }, |
8596 | /* VEX_0F38 */ | |
8597 | { | |
8598 | /* 00 */ | |
592a252b L |
8599 | { PREFIX_TABLE (PREFIX_VEX_0F3800) }, |
8600 | { PREFIX_TABLE (PREFIX_VEX_0F3801) }, | |
8601 | { PREFIX_TABLE (PREFIX_VEX_0F3802) }, | |
8602 | { PREFIX_TABLE (PREFIX_VEX_0F3803) }, | |
8603 | { PREFIX_TABLE (PREFIX_VEX_0F3804) }, | |
8604 | { PREFIX_TABLE (PREFIX_VEX_0F3805) }, | |
8605 | { PREFIX_TABLE (PREFIX_VEX_0F3806) }, | |
8606 | { PREFIX_TABLE (PREFIX_VEX_0F3807) }, | |
c0f3af97 | 8607 | /* 08 */ |
592a252b L |
8608 | { PREFIX_TABLE (PREFIX_VEX_0F3808) }, |
8609 | { PREFIX_TABLE (PREFIX_VEX_0F3809) }, | |
8610 | { PREFIX_TABLE (PREFIX_VEX_0F380A) }, | |
8611 | { PREFIX_TABLE (PREFIX_VEX_0F380B) }, | |
8612 | { PREFIX_TABLE (PREFIX_VEX_0F380C) }, | |
8613 | { PREFIX_TABLE (PREFIX_VEX_0F380D) }, | |
8614 | { PREFIX_TABLE (PREFIX_VEX_0F380E) }, | |
8615 | { PREFIX_TABLE (PREFIX_VEX_0F380F) }, | |
c0f3af97 | 8616 | /* 10 */ |
592d1631 L |
8617 | { Bad_Opcode }, |
8618 | { Bad_Opcode }, | |
8619 | { Bad_Opcode }, | |
592a252b | 8620 | { PREFIX_TABLE (PREFIX_VEX_0F3813) }, |
592d1631 L |
8621 | { Bad_Opcode }, |
8622 | { Bad_Opcode }, | |
6c30d220 | 8623 | { PREFIX_TABLE (PREFIX_VEX_0F3816) }, |
592a252b | 8624 | { PREFIX_TABLE (PREFIX_VEX_0F3817) }, |
c0f3af97 | 8625 | /* 18 */ |
592a252b L |
8626 | { PREFIX_TABLE (PREFIX_VEX_0F3818) }, |
8627 | { PREFIX_TABLE (PREFIX_VEX_0F3819) }, | |
8628 | { PREFIX_TABLE (PREFIX_VEX_0F381A) }, | |
592d1631 | 8629 | { Bad_Opcode }, |
592a252b L |
8630 | { PREFIX_TABLE (PREFIX_VEX_0F381C) }, |
8631 | { PREFIX_TABLE (PREFIX_VEX_0F381D) }, | |
8632 | { PREFIX_TABLE (PREFIX_VEX_0F381E) }, | |
592d1631 | 8633 | { Bad_Opcode }, |
c0f3af97 | 8634 | /* 20 */ |
592a252b L |
8635 | { PREFIX_TABLE (PREFIX_VEX_0F3820) }, |
8636 | { PREFIX_TABLE (PREFIX_VEX_0F3821) }, | |
8637 | { PREFIX_TABLE (PREFIX_VEX_0F3822) }, | |
8638 | { PREFIX_TABLE (PREFIX_VEX_0F3823) }, | |
8639 | { PREFIX_TABLE (PREFIX_VEX_0F3824) }, | |
8640 | { PREFIX_TABLE (PREFIX_VEX_0F3825) }, | |
592d1631 L |
8641 | { Bad_Opcode }, |
8642 | { Bad_Opcode }, | |
c0f3af97 | 8643 | /* 28 */ |
592a252b L |
8644 | { PREFIX_TABLE (PREFIX_VEX_0F3828) }, |
8645 | { PREFIX_TABLE (PREFIX_VEX_0F3829) }, | |
8646 | { PREFIX_TABLE (PREFIX_VEX_0F382A) }, | |
8647 | { PREFIX_TABLE (PREFIX_VEX_0F382B) }, | |
8648 | { PREFIX_TABLE (PREFIX_VEX_0F382C) }, | |
8649 | { PREFIX_TABLE (PREFIX_VEX_0F382D) }, | |
8650 | { PREFIX_TABLE (PREFIX_VEX_0F382E) }, | |
8651 | { PREFIX_TABLE (PREFIX_VEX_0F382F) }, | |
c0f3af97 | 8652 | /* 30 */ |
592a252b L |
8653 | { PREFIX_TABLE (PREFIX_VEX_0F3830) }, |
8654 | { PREFIX_TABLE (PREFIX_VEX_0F3831) }, | |
8655 | { PREFIX_TABLE (PREFIX_VEX_0F3832) }, | |
8656 | { PREFIX_TABLE (PREFIX_VEX_0F3833) }, | |
8657 | { PREFIX_TABLE (PREFIX_VEX_0F3834) }, | |
8658 | { PREFIX_TABLE (PREFIX_VEX_0F3835) }, | |
6c30d220 | 8659 | { PREFIX_TABLE (PREFIX_VEX_0F3836) }, |
592a252b | 8660 | { PREFIX_TABLE (PREFIX_VEX_0F3837) }, |
c0f3af97 | 8661 | /* 38 */ |
592a252b L |
8662 | { PREFIX_TABLE (PREFIX_VEX_0F3838) }, |
8663 | { PREFIX_TABLE (PREFIX_VEX_0F3839) }, | |
8664 | { PREFIX_TABLE (PREFIX_VEX_0F383A) }, | |
8665 | { PREFIX_TABLE (PREFIX_VEX_0F383B) }, | |
8666 | { PREFIX_TABLE (PREFIX_VEX_0F383C) }, | |
8667 | { PREFIX_TABLE (PREFIX_VEX_0F383D) }, | |
8668 | { PREFIX_TABLE (PREFIX_VEX_0F383E) }, | |
8669 | { PREFIX_TABLE (PREFIX_VEX_0F383F) }, | |
c0f3af97 | 8670 | /* 40 */ |
592a252b L |
8671 | { PREFIX_TABLE (PREFIX_VEX_0F3840) }, |
8672 | { PREFIX_TABLE (PREFIX_VEX_0F3841) }, | |
592d1631 L |
8673 | { Bad_Opcode }, |
8674 | { Bad_Opcode }, | |
8675 | { Bad_Opcode }, | |
6c30d220 L |
8676 | { PREFIX_TABLE (PREFIX_VEX_0F3845) }, |
8677 | { PREFIX_TABLE (PREFIX_VEX_0F3846) }, | |
8678 | { PREFIX_TABLE (PREFIX_VEX_0F3847) }, | |
c0f3af97 | 8679 | /* 48 */ |
592d1631 L |
8680 | { Bad_Opcode }, |
8681 | { Bad_Opcode }, | |
8682 | { Bad_Opcode }, | |
8683 | { Bad_Opcode }, | |
8684 | { Bad_Opcode }, | |
8685 | { Bad_Opcode }, | |
8686 | { Bad_Opcode }, | |
8687 | { Bad_Opcode }, | |
c0f3af97 | 8688 | /* 50 */ |
592d1631 L |
8689 | { Bad_Opcode }, |
8690 | { Bad_Opcode }, | |
8691 | { Bad_Opcode }, | |
8692 | { Bad_Opcode }, | |
8693 | { Bad_Opcode }, | |
8694 | { Bad_Opcode }, | |
8695 | { Bad_Opcode }, | |
8696 | { Bad_Opcode }, | |
c0f3af97 | 8697 | /* 58 */ |
6c30d220 L |
8698 | { PREFIX_TABLE (PREFIX_VEX_0F3858) }, |
8699 | { PREFIX_TABLE (PREFIX_VEX_0F3859) }, | |
8700 | { PREFIX_TABLE (PREFIX_VEX_0F385A) }, | |
592d1631 L |
8701 | { Bad_Opcode }, |
8702 | { Bad_Opcode }, | |
8703 | { Bad_Opcode }, | |
8704 | { Bad_Opcode }, | |
8705 | { Bad_Opcode }, | |
c0f3af97 | 8706 | /* 60 */ |
592d1631 L |
8707 | { Bad_Opcode }, |
8708 | { Bad_Opcode }, | |
8709 | { Bad_Opcode }, | |
8710 | { Bad_Opcode }, | |
8711 | { Bad_Opcode }, | |
8712 | { Bad_Opcode }, | |
8713 | { Bad_Opcode }, | |
8714 | { Bad_Opcode }, | |
c0f3af97 | 8715 | /* 68 */ |
592d1631 L |
8716 | { Bad_Opcode }, |
8717 | { Bad_Opcode }, | |
8718 | { Bad_Opcode }, | |
8719 | { Bad_Opcode }, | |
8720 | { Bad_Opcode }, | |
8721 | { Bad_Opcode }, | |
8722 | { Bad_Opcode }, | |
8723 | { Bad_Opcode }, | |
c0f3af97 | 8724 | /* 70 */ |
592d1631 L |
8725 | { Bad_Opcode }, |
8726 | { Bad_Opcode }, | |
8727 | { Bad_Opcode }, | |
8728 | { Bad_Opcode }, | |
8729 | { Bad_Opcode }, | |
8730 | { Bad_Opcode }, | |
8731 | { Bad_Opcode }, | |
8732 | { Bad_Opcode }, | |
c0f3af97 | 8733 | /* 78 */ |
6c30d220 L |
8734 | { PREFIX_TABLE (PREFIX_VEX_0F3878) }, |
8735 | { PREFIX_TABLE (PREFIX_VEX_0F3879) }, | |
592d1631 L |
8736 | { Bad_Opcode }, |
8737 | { Bad_Opcode }, | |
8738 | { Bad_Opcode }, | |
8739 | { Bad_Opcode }, | |
8740 | { Bad_Opcode }, | |
8741 | { Bad_Opcode }, | |
c0f3af97 | 8742 | /* 80 */ |
592d1631 L |
8743 | { Bad_Opcode }, |
8744 | { Bad_Opcode }, | |
8745 | { Bad_Opcode }, | |
8746 | { Bad_Opcode }, | |
8747 | { Bad_Opcode }, | |
8748 | { Bad_Opcode }, | |
8749 | { Bad_Opcode }, | |
8750 | { Bad_Opcode }, | |
c0f3af97 | 8751 | /* 88 */ |
592d1631 L |
8752 | { Bad_Opcode }, |
8753 | { Bad_Opcode }, | |
8754 | { Bad_Opcode }, | |
8755 | { Bad_Opcode }, | |
6c30d220 | 8756 | { PREFIX_TABLE (PREFIX_VEX_0F388C) }, |
592d1631 | 8757 | { Bad_Opcode }, |
6c30d220 | 8758 | { PREFIX_TABLE (PREFIX_VEX_0F388E) }, |
592d1631 | 8759 | { Bad_Opcode }, |
c0f3af97 | 8760 | /* 90 */ |
6c30d220 L |
8761 | { PREFIX_TABLE (PREFIX_VEX_0F3890) }, |
8762 | { PREFIX_TABLE (PREFIX_VEX_0F3891) }, | |
8763 | { PREFIX_TABLE (PREFIX_VEX_0F3892) }, | |
8764 | { PREFIX_TABLE (PREFIX_VEX_0F3893) }, | |
592d1631 L |
8765 | { Bad_Opcode }, |
8766 | { Bad_Opcode }, | |
592a252b L |
8767 | { PREFIX_TABLE (PREFIX_VEX_0F3896) }, |
8768 | { PREFIX_TABLE (PREFIX_VEX_0F3897) }, | |
c0f3af97 | 8769 | /* 98 */ |
592a252b L |
8770 | { PREFIX_TABLE (PREFIX_VEX_0F3898) }, |
8771 | { PREFIX_TABLE (PREFIX_VEX_0F3899) }, | |
8772 | { PREFIX_TABLE (PREFIX_VEX_0F389A) }, | |
8773 | { PREFIX_TABLE (PREFIX_VEX_0F389B) }, | |
8774 | { PREFIX_TABLE (PREFIX_VEX_0F389C) }, | |
8775 | { PREFIX_TABLE (PREFIX_VEX_0F389D) }, | |
8776 | { PREFIX_TABLE (PREFIX_VEX_0F389E) }, | |
8777 | { PREFIX_TABLE (PREFIX_VEX_0F389F) }, | |
c0f3af97 | 8778 | /* a0 */ |
592d1631 L |
8779 | { Bad_Opcode }, |
8780 | { Bad_Opcode }, | |
8781 | { Bad_Opcode }, | |
8782 | { Bad_Opcode }, | |
8783 | { Bad_Opcode }, | |
8784 | { Bad_Opcode }, | |
592a252b L |
8785 | { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, |
8786 | { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, | |
c0f3af97 | 8787 | /* a8 */ |
592a252b L |
8788 | { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, |
8789 | { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, | |
8790 | { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, | |
8791 | { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, | |
8792 | { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, | |
8793 | { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, | |
8794 | { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, | |
8795 | { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, | |
c0f3af97 | 8796 | /* b0 */ |
592d1631 L |
8797 | { Bad_Opcode }, |
8798 | { Bad_Opcode }, | |
8799 | { Bad_Opcode }, | |
8800 | { Bad_Opcode }, | |
8801 | { Bad_Opcode }, | |
8802 | { Bad_Opcode }, | |
592a252b L |
8803 | { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, |
8804 | { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, | |
c0f3af97 | 8805 | /* b8 */ |
592a252b L |
8806 | { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, |
8807 | { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, | |
8808 | { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, | |
8809 | { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, | |
8810 | { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, | |
8811 | { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, | |
8812 | { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, | |
8813 | { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, | |
c0f3af97 | 8814 | /* c0 */ |
592d1631 L |
8815 | { Bad_Opcode }, |
8816 | { Bad_Opcode }, | |
8817 | { Bad_Opcode }, | |
8818 | { Bad_Opcode }, | |
8819 | { Bad_Opcode }, | |
8820 | { Bad_Opcode }, | |
8821 | { Bad_Opcode }, | |
8822 | { Bad_Opcode }, | |
c0f3af97 | 8823 | /* c8 */ |
592d1631 L |
8824 | { Bad_Opcode }, |
8825 | { Bad_Opcode }, | |
8826 | { Bad_Opcode }, | |
8827 | { Bad_Opcode }, | |
8828 | { Bad_Opcode }, | |
8829 | { Bad_Opcode }, | |
8830 | { Bad_Opcode }, | |
8831 | { Bad_Opcode }, | |
c0f3af97 | 8832 | /* d0 */ |
592d1631 L |
8833 | { Bad_Opcode }, |
8834 | { Bad_Opcode }, | |
8835 | { Bad_Opcode }, | |
8836 | { Bad_Opcode }, | |
8837 | { Bad_Opcode }, | |
8838 | { Bad_Opcode }, | |
8839 | { Bad_Opcode }, | |
8840 | { Bad_Opcode }, | |
c0f3af97 | 8841 | /* d8 */ |
592d1631 L |
8842 | { Bad_Opcode }, |
8843 | { Bad_Opcode }, | |
8844 | { Bad_Opcode }, | |
592a252b L |
8845 | { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, |
8846 | { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, | |
8847 | { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, | |
8848 | { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, | |
8849 | { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, | |
c0f3af97 | 8850 | /* e0 */ |
592d1631 L |
8851 | { Bad_Opcode }, |
8852 | { Bad_Opcode }, | |
8853 | { Bad_Opcode }, | |
8854 | { Bad_Opcode }, | |
8855 | { Bad_Opcode }, | |
8856 | { Bad_Opcode }, | |
8857 | { Bad_Opcode }, | |
8858 | { Bad_Opcode }, | |
c0f3af97 | 8859 | /* e8 */ |
592d1631 L |
8860 | { Bad_Opcode }, |
8861 | { Bad_Opcode }, | |
8862 | { Bad_Opcode }, | |
8863 | { Bad_Opcode }, | |
8864 | { Bad_Opcode }, | |
8865 | { Bad_Opcode }, | |
8866 | { Bad_Opcode }, | |
8867 | { Bad_Opcode }, | |
c0f3af97 | 8868 | /* f0 */ |
592d1631 L |
8869 | { Bad_Opcode }, |
8870 | { Bad_Opcode }, | |
f12dc422 L |
8871 | { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, |
8872 | { REG_TABLE (REG_VEX_0F38F3) }, | |
592d1631 | 8873 | { Bad_Opcode }, |
6c30d220 L |
8874 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
8875 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, | |
f12dc422 | 8876 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
c0f3af97 | 8877 | /* f8 */ |
592d1631 L |
8878 | { Bad_Opcode }, |
8879 | { Bad_Opcode }, | |
8880 | { Bad_Opcode }, | |
8881 | { Bad_Opcode }, | |
8882 | { Bad_Opcode }, | |
8883 | { Bad_Opcode }, | |
8884 | { Bad_Opcode }, | |
8885 | { Bad_Opcode }, | |
c0f3af97 L |
8886 | }, |
8887 | /* VEX_0F3A */ | |
8888 | { | |
8889 | /* 00 */ | |
6c30d220 L |
8890 | { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, |
8891 | { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, | |
8892 | { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, | |
592d1631 | 8893 | { Bad_Opcode }, |
592a252b L |
8894 | { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, |
8895 | { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, | |
8896 | { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, | |
592d1631 | 8897 | { Bad_Opcode }, |
c0f3af97 | 8898 | /* 08 */ |
592a252b L |
8899 | { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, |
8900 | { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, | |
8901 | { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, | |
8902 | { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, | |
8903 | { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, | |
8904 | { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, | |
8905 | { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, | |
8906 | { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, | |
c0f3af97 | 8907 | /* 10 */ |
592d1631 L |
8908 | { Bad_Opcode }, |
8909 | { Bad_Opcode }, | |
8910 | { Bad_Opcode }, | |
8911 | { Bad_Opcode }, | |
592a252b L |
8912 | { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, |
8913 | { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, | |
8914 | { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, | |
8915 | { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, | |
c0f3af97 | 8916 | /* 18 */ |
592a252b L |
8917 | { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, |
8918 | { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, | |
592d1631 L |
8919 | { Bad_Opcode }, |
8920 | { Bad_Opcode }, | |
8921 | { Bad_Opcode }, | |
592a252b | 8922 | { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, |
592d1631 L |
8923 | { Bad_Opcode }, |
8924 | { Bad_Opcode }, | |
c0f3af97 | 8925 | /* 20 */ |
592a252b L |
8926 | { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, |
8927 | { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, | |
8928 | { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, | |
592d1631 L |
8929 | { Bad_Opcode }, |
8930 | { Bad_Opcode }, | |
8931 | { Bad_Opcode }, | |
8932 | { Bad_Opcode }, | |
8933 | { Bad_Opcode }, | |
c0f3af97 | 8934 | /* 28 */ |
592d1631 L |
8935 | { Bad_Opcode }, |
8936 | { Bad_Opcode }, | |
8937 | { Bad_Opcode }, | |
8938 | { Bad_Opcode }, | |
8939 | { Bad_Opcode }, | |
8940 | { Bad_Opcode }, | |
8941 | { Bad_Opcode }, | |
8942 | { Bad_Opcode }, | |
c0f3af97 | 8943 | /* 30 */ |
43234a1e | 8944 | { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, |
592d1631 | 8945 | { Bad_Opcode }, |
43234a1e | 8946 | { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, |
592d1631 L |
8947 | { Bad_Opcode }, |
8948 | { Bad_Opcode }, | |
8949 | { Bad_Opcode }, | |
8950 | { Bad_Opcode }, | |
8951 | { Bad_Opcode }, | |
c0f3af97 | 8952 | /* 38 */ |
6c30d220 L |
8953 | { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, |
8954 | { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, | |
592d1631 L |
8955 | { Bad_Opcode }, |
8956 | { Bad_Opcode }, | |
8957 | { Bad_Opcode }, | |
8958 | { Bad_Opcode }, | |
8959 | { Bad_Opcode }, | |
8960 | { Bad_Opcode }, | |
c0f3af97 | 8961 | /* 40 */ |
592a252b L |
8962 | { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, |
8963 | { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, | |
8964 | { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, | |
592d1631 | 8965 | { Bad_Opcode }, |
592a252b | 8966 | { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, |
592d1631 | 8967 | { Bad_Opcode }, |
6c30d220 | 8968 | { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, |
592d1631 | 8969 | { Bad_Opcode }, |
c0f3af97 | 8970 | /* 48 */ |
592a252b L |
8971 | { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, |
8972 | { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, | |
8973 | { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, | |
8974 | { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, | |
8975 | { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, | |
592d1631 L |
8976 | { Bad_Opcode }, |
8977 | { Bad_Opcode }, | |
8978 | { Bad_Opcode }, | |
c0f3af97 | 8979 | /* 50 */ |
592d1631 L |
8980 | { Bad_Opcode }, |
8981 | { Bad_Opcode }, | |
8982 | { Bad_Opcode }, | |
8983 | { Bad_Opcode }, | |
8984 | { Bad_Opcode }, | |
8985 | { Bad_Opcode }, | |
8986 | { Bad_Opcode }, | |
8987 | { Bad_Opcode }, | |
c0f3af97 | 8988 | /* 58 */ |
592d1631 L |
8989 | { Bad_Opcode }, |
8990 | { Bad_Opcode }, | |
8991 | { Bad_Opcode }, | |
8992 | { Bad_Opcode }, | |
592a252b L |
8993 | { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, |
8994 | { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, | |
8995 | { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, | |
8996 | { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, | |
c0f3af97 | 8997 | /* 60 */ |
592a252b L |
8998 | { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, |
8999 | { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, | |
9000 | { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, | |
9001 | { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, | |
592d1631 L |
9002 | { Bad_Opcode }, |
9003 | { Bad_Opcode }, | |
9004 | { Bad_Opcode }, | |
9005 | { Bad_Opcode }, | |
c0f3af97 | 9006 | /* 68 */ |
592a252b L |
9007 | { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, |
9008 | { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, | |
9009 | { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, | |
9010 | { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, | |
9011 | { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, | |
9012 | { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, | |
9013 | { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, | |
9014 | { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, | |
c0f3af97 | 9015 | /* 70 */ |
592d1631 L |
9016 | { Bad_Opcode }, |
9017 | { Bad_Opcode }, | |
9018 | { Bad_Opcode }, | |
9019 | { Bad_Opcode }, | |
9020 | { Bad_Opcode }, | |
9021 | { Bad_Opcode }, | |
9022 | { Bad_Opcode }, | |
9023 | { Bad_Opcode }, | |
c0f3af97 | 9024 | /* 78 */ |
592a252b L |
9025 | { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, |
9026 | { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, | |
9027 | { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, | |
9028 | { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, | |
9029 | { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, | |
9030 | { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, | |
9031 | { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, | |
9032 | { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, | |
c0f3af97 | 9033 | /* 80 */ |
592d1631 L |
9034 | { Bad_Opcode }, |
9035 | { Bad_Opcode }, | |
9036 | { Bad_Opcode }, | |
9037 | { Bad_Opcode }, | |
9038 | { Bad_Opcode }, | |
9039 | { Bad_Opcode }, | |
9040 | { Bad_Opcode }, | |
9041 | { Bad_Opcode }, | |
c0f3af97 | 9042 | /* 88 */ |
592d1631 L |
9043 | { Bad_Opcode }, |
9044 | { Bad_Opcode }, | |
9045 | { Bad_Opcode }, | |
9046 | { Bad_Opcode }, | |
9047 | { Bad_Opcode }, | |
9048 | { Bad_Opcode }, | |
9049 | { Bad_Opcode }, | |
9050 | { Bad_Opcode }, | |
c0f3af97 | 9051 | /* 90 */ |
592d1631 L |
9052 | { Bad_Opcode }, |
9053 | { Bad_Opcode }, | |
9054 | { Bad_Opcode }, | |
9055 | { Bad_Opcode }, | |
9056 | { Bad_Opcode }, | |
9057 | { Bad_Opcode }, | |
9058 | { Bad_Opcode }, | |
9059 | { Bad_Opcode }, | |
c0f3af97 | 9060 | /* 98 */ |
592d1631 L |
9061 | { Bad_Opcode }, |
9062 | { Bad_Opcode }, | |
9063 | { Bad_Opcode }, | |
9064 | { Bad_Opcode }, | |
9065 | { Bad_Opcode }, | |
9066 | { Bad_Opcode }, | |
9067 | { Bad_Opcode }, | |
9068 | { Bad_Opcode }, | |
c0f3af97 | 9069 | /* a0 */ |
592d1631 L |
9070 | { Bad_Opcode }, |
9071 | { Bad_Opcode }, | |
9072 | { Bad_Opcode }, | |
9073 | { Bad_Opcode }, | |
9074 | { Bad_Opcode }, | |
9075 | { Bad_Opcode }, | |
9076 | { Bad_Opcode }, | |
9077 | { Bad_Opcode }, | |
c0f3af97 | 9078 | /* a8 */ |
592d1631 L |
9079 | { Bad_Opcode }, |
9080 | { Bad_Opcode }, | |
9081 | { Bad_Opcode }, | |
9082 | { Bad_Opcode }, | |
9083 | { Bad_Opcode }, | |
9084 | { Bad_Opcode }, | |
9085 | { Bad_Opcode }, | |
9086 | { Bad_Opcode }, | |
c0f3af97 | 9087 | /* b0 */ |
592d1631 L |
9088 | { Bad_Opcode }, |
9089 | { Bad_Opcode }, | |
9090 | { Bad_Opcode }, | |
9091 | { Bad_Opcode }, | |
9092 | { Bad_Opcode }, | |
9093 | { Bad_Opcode }, | |
9094 | { Bad_Opcode }, | |
9095 | { Bad_Opcode }, | |
c0f3af97 | 9096 | /* b8 */ |
592d1631 L |
9097 | { Bad_Opcode }, |
9098 | { Bad_Opcode }, | |
9099 | { Bad_Opcode }, | |
9100 | { Bad_Opcode }, | |
9101 | { Bad_Opcode }, | |
9102 | { Bad_Opcode }, | |
9103 | { Bad_Opcode }, | |
9104 | { Bad_Opcode }, | |
c0f3af97 | 9105 | /* c0 */ |
592d1631 L |
9106 | { Bad_Opcode }, |
9107 | { Bad_Opcode }, | |
9108 | { Bad_Opcode }, | |
9109 | { Bad_Opcode }, | |
9110 | { Bad_Opcode }, | |
9111 | { Bad_Opcode }, | |
9112 | { Bad_Opcode }, | |
9113 | { Bad_Opcode }, | |
c0f3af97 | 9114 | /* c8 */ |
592d1631 L |
9115 | { Bad_Opcode }, |
9116 | { Bad_Opcode }, | |
9117 | { Bad_Opcode }, | |
9118 | { Bad_Opcode }, | |
9119 | { Bad_Opcode }, | |
9120 | { Bad_Opcode }, | |
9121 | { Bad_Opcode }, | |
9122 | { Bad_Opcode }, | |
c0f3af97 | 9123 | /* d0 */ |
592d1631 L |
9124 | { Bad_Opcode }, |
9125 | { Bad_Opcode }, | |
9126 | { Bad_Opcode }, | |
9127 | { Bad_Opcode }, | |
9128 | { Bad_Opcode }, | |
9129 | { Bad_Opcode }, | |
9130 | { Bad_Opcode }, | |
9131 | { Bad_Opcode }, | |
c0f3af97 | 9132 | /* d8 */ |
592d1631 L |
9133 | { Bad_Opcode }, |
9134 | { Bad_Opcode }, | |
9135 | { Bad_Opcode }, | |
9136 | { Bad_Opcode }, | |
9137 | { Bad_Opcode }, | |
9138 | { Bad_Opcode }, | |
9139 | { Bad_Opcode }, | |
592a252b | 9140 | { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, |
c0f3af97 | 9141 | /* e0 */ |
592d1631 L |
9142 | { Bad_Opcode }, |
9143 | { Bad_Opcode }, | |
9144 | { Bad_Opcode }, | |
9145 | { Bad_Opcode }, | |
9146 | { Bad_Opcode }, | |
9147 | { Bad_Opcode }, | |
9148 | { Bad_Opcode }, | |
9149 | { Bad_Opcode }, | |
c0f3af97 | 9150 | /* e8 */ |
592d1631 L |
9151 | { Bad_Opcode }, |
9152 | { Bad_Opcode }, | |
9153 | { Bad_Opcode }, | |
9154 | { Bad_Opcode }, | |
9155 | { Bad_Opcode }, | |
9156 | { Bad_Opcode }, | |
9157 | { Bad_Opcode }, | |
9158 | { Bad_Opcode }, | |
c0f3af97 | 9159 | /* f0 */ |
6c30d220 | 9160 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
592d1631 L |
9161 | { Bad_Opcode }, |
9162 | { Bad_Opcode }, | |
9163 | { Bad_Opcode }, | |
9164 | { Bad_Opcode }, | |
9165 | { Bad_Opcode }, | |
9166 | { Bad_Opcode }, | |
9167 | { Bad_Opcode }, | |
c0f3af97 | 9168 | /* f8 */ |
592d1631 L |
9169 | { Bad_Opcode }, |
9170 | { Bad_Opcode }, | |
9171 | { Bad_Opcode }, | |
9172 | { Bad_Opcode }, | |
9173 | { Bad_Opcode }, | |
9174 | { Bad_Opcode }, | |
9175 | { Bad_Opcode }, | |
9176 | { Bad_Opcode }, | |
c0f3af97 L |
9177 | }, |
9178 | }; | |
9179 | ||
43234a1e L |
9180 | #define NEED_OPCODE_TABLE |
9181 | #include "i386-dis-evex.h" | |
9182 | #undef NEED_OPCODE_TABLE | |
c0f3af97 | 9183 | static const struct dis386 vex_len_table[][2] = { |
592a252b | 9184 | /* VEX_LEN_0F10_P_1 */ |
c0f3af97 | 9185 | { |
592a252b L |
9186 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, |
9187 | { VEX_W_TABLE (VEX_W_0F10_P_1) }, | |
c0f3af97 L |
9188 | }, |
9189 | ||
592a252b | 9190 | /* VEX_LEN_0F10_P_3 */ |
c0f3af97 | 9191 | { |
592a252b L |
9192 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, |
9193 | { VEX_W_TABLE (VEX_W_0F10_P_3) }, | |
c0f3af97 L |
9194 | }, |
9195 | ||
592a252b | 9196 | /* VEX_LEN_0F11_P_1 */ |
c0f3af97 | 9197 | { |
592a252b L |
9198 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, |
9199 | { VEX_W_TABLE (VEX_W_0F11_P_1) }, | |
c0f3af97 L |
9200 | }, |
9201 | ||
592a252b | 9202 | /* VEX_LEN_0F11_P_3 */ |
c0f3af97 | 9203 | { |
592a252b L |
9204 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, |
9205 | { VEX_W_TABLE (VEX_W_0F11_P_3) }, | |
c0f3af97 L |
9206 | }, |
9207 | ||
592a252b | 9208 | /* VEX_LEN_0F12_P_0_M_0 */ |
c0f3af97 | 9209 | { |
592a252b | 9210 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) }, |
c0f3af97 L |
9211 | }, |
9212 | ||
592a252b | 9213 | /* VEX_LEN_0F12_P_0_M_1 */ |
c0f3af97 | 9214 | { |
592a252b | 9215 | { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) }, |
c0f3af97 L |
9216 | }, |
9217 | ||
592a252b | 9218 | /* VEX_LEN_0F12_P_2 */ |
c0f3af97 | 9219 | { |
592a252b | 9220 | { VEX_W_TABLE (VEX_W_0F12_P_2) }, |
c0f3af97 L |
9221 | }, |
9222 | ||
592a252b | 9223 | /* VEX_LEN_0F13_M_0 */ |
c0f3af97 | 9224 | { |
592a252b | 9225 | { VEX_W_TABLE (VEX_W_0F13_M_0) }, |
c0f3af97 L |
9226 | }, |
9227 | ||
592a252b | 9228 | /* VEX_LEN_0F16_P_0_M_0 */ |
c0f3af97 | 9229 | { |
592a252b | 9230 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) }, |
c0f3af97 L |
9231 | }, |
9232 | ||
592a252b | 9233 | /* VEX_LEN_0F16_P_0_M_1 */ |
c0f3af97 | 9234 | { |
592a252b | 9235 | { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) }, |
c0f3af97 L |
9236 | }, |
9237 | ||
592a252b | 9238 | /* VEX_LEN_0F16_P_2 */ |
c0f3af97 | 9239 | { |
592a252b | 9240 | { VEX_W_TABLE (VEX_W_0F16_P_2) }, |
c0f3af97 L |
9241 | }, |
9242 | ||
592a252b | 9243 | /* VEX_LEN_0F17_M_0 */ |
c0f3af97 | 9244 | { |
592a252b | 9245 | { VEX_W_TABLE (VEX_W_0F17_M_0) }, |
c0f3af97 L |
9246 | }, |
9247 | ||
592a252b | 9248 | /* VEX_LEN_0F2A_P_1 */ |
c0f3af97 | 9249 | { |
539f890d L |
9250 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } }, |
9251 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } }, | |
c0f3af97 L |
9252 | }, |
9253 | ||
592a252b | 9254 | /* VEX_LEN_0F2A_P_3 */ |
c0f3af97 | 9255 | { |
539f890d L |
9256 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } }, |
9257 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } }, | |
c0f3af97 L |
9258 | }, |
9259 | ||
592a252b | 9260 | /* VEX_LEN_0F2C_P_1 */ |
c0f3af97 | 9261 | { |
539f890d L |
9262 | { "vcvttss2siY", { Gv, EXdScalar } }, |
9263 | { "vcvttss2siY", { Gv, EXdScalar } }, | |
c0f3af97 L |
9264 | }, |
9265 | ||
592a252b | 9266 | /* VEX_LEN_0F2C_P_3 */ |
c0f3af97 | 9267 | { |
539f890d L |
9268 | { "vcvttsd2siY", { Gv, EXqScalar } }, |
9269 | { "vcvttsd2siY", { Gv, EXqScalar } }, | |
c0f3af97 L |
9270 | }, |
9271 | ||
592a252b | 9272 | /* VEX_LEN_0F2D_P_1 */ |
c0f3af97 | 9273 | { |
539f890d L |
9274 | { "vcvtss2siY", { Gv, EXdScalar } }, |
9275 | { "vcvtss2siY", { Gv, EXdScalar } }, | |
c0f3af97 L |
9276 | }, |
9277 | ||
592a252b | 9278 | /* VEX_LEN_0F2D_P_3 */ |
c0f3af97 | 9279 | { |
539f890d L |
9280 | { "vcvtsd2siY", { Gv, EXqScalar } }, |
9281 | { "vcvtsd2siY", { Gv, EXqScalar } }, | |
c0f3af97 L |
9282 | }, |
9283 | ||
592a252b | 9284 | /* VEX_LEN_0F2E_P_0 */ |
c0f3af97 | 9285 | { |
592a252b L |
9286 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, |
9287 | { VEX_W_TABLE (VEX_W_0F2E_P_0) }, | |
c0f3af97 L |
9288 | }, |
9289 | ||
592a252b | 9290 | /* VEX_LEN_0F2E_P_2 */ |
c0f3af97 | 9291 | { |
592a252b L |
9292 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, |
9293 | { VEX_W_TABLE (VEX_W_0F2E_P_2) }, | |
c0f3af97 L |
9294 | }, |
9295 | ||
592a252b | 9296 | /* VEX_LEN_0F2F_P_0 */ |
c0f3af97 | 9297 | { |
592a252b L |
9298 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, |
9299 | { VEX_W_TABLE (VEX_W_0F2F_P_0) }, | |
c0f3af97 L |
9300 | }, |
9301 | ||
592a252b | 9302 | /* VEX_LEN_0F2F_P_2 */ |
c0f3af97 | 9303 | { |
592a252b L |
9304 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, |
9305 | { VEX_W_TABLE (VEX_W_0F2F_P_2) }, | |
c0f3af97 L |
9306 | }, |
9307 | ||
43234a1e L |
9308 | /* VEX_LEN_0F41_P_0 */ |
9309 | { | |
9310 | { Bad_Opcode }, | |
9311 | { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, | |
9312 | }, | |
9313 | /* VEX_LEN_0F42_P_0 */ | |
9314 | { | |
9315 | { Bad_Opcode }, | |
9316 | { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, | |
9317 | }, | |
9318 | /* VEX_LEN_0F44_P_0 */ | |
9319 | { | |
9320 | { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, | |
9321 | }, | |
9322 | /* VEX_LEN_0F45_P_0 */ | |
9323 | { | |
9324 | { Bad_Opcode }, | |
9325 | { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, | |
9326 | }, | |
9327 | /* VEX_LEN_0F46_P_0 */ | |
9328 | { | |
9329 | { Bad_Opcode }, | |
9330 | { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, | |
9331 | }, | |
9332 | /* VEX_LEN_0F47_P_0 */ | |
9333 | { | |
9334 | { Bad_Opcode }, | |
9335 | { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, | |
9336 | }, | |
9337 | /* VEX_LEN_0F4B_P_2 */ | |
9338 | { | |
9339 | { Bad_Opcode }, | |
9340 | { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, | |
9341 | }, | |
9342 | ||
592a252b | 9343 | /* VEX_LEN_0F51_P_1 */ |
c0f3af97 | 9344 | { |
592a252b L |
9345 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, |
9346 | { VEX_W_TABLE (VEX_W_0F51_P_1) }, | |
c0f3af97 L |
9347 | }, |
9348 | ||
592a252b | 9349 | /* VEX_LEN_0F51_P_3 */ |
c0f3af97 | 9350 | { |
592a252b L |
9351 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, |
9352 | { VEX_W_TABLE (VEX_W_0F51_P_3) }, | |
c0f3af97 L |
9353 | }, |
9354 | ||
592a252b | 9355 | /* VEX_LEN_0F52_P_1 */ |
c0f3af97 | 9356 | { |
592a252b L |
9357 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, |
9358 | { VEX_W_TABLE (VEX_W_0F52_P_1) }, | |
c0f3af97 L |
9359 | }, |
9360 | ||
592a252b | 9361 | /* VEX_LEN_0F53_P_1 */ |
c0f3af97 | 9362 | { |
592a252b L |
9363 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, |
9364 | { VEX_W_TABLE (VEX_W_0F53_P_1) }, | |
c0f3af97 L |
9365 | }, |
9366 | ||
592a252b | 9367 | /* VEX_LEN_0F58_P_1 */ |
c0f3af97 | 9368 | { |
592a252b L |
9369 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, |
9370 | { VEX_W_TABLE (VEX_W_0F58_P_1) }, | |
c0f3af97 L |
9371 | }, |
9372 | ||
592a252b | 9373 | /* VEX_LEN_0F58_P_3 */ |
c0f3af97 | 9374 | { |
592a252b L |
9375 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, |
9376 | { VEX_W_TABLE (VEX_W_0F58_P_3) }, | |
c0f3af97 L |
9377 | }, |
9378 | ||
592a252b | 9379 | /* VEX_LEN_0F59_P_1 */ |
c0f3af97 | 9380 | { |
592a252b L |
9381 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, |
9382 | { VEX_W_TABLE (VEX_W_0F59_P_1) }, | |
c0f3af97 L |
9383 | }, |
9384 | ||
592a252b | 9385 | /* VEX_LEN_0F59_P_3 */ |
c0f3af97 | 9386 | { |
592a252b L |
9387 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, |
9388 | { VEX_W_TABLE (VEX_W_0F59_P_3) }, | |
c0f3af97 L |
9389 | }, |
9390 | ||
592a252b | 9391 | /* VEX_LEN_0F5A_P_1 */ |
c0f3af97 | 9392 | { |
592a252b L |
9393 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, |
9394 | { VEX_W_TABLE (VEX_W_0F5A_P_1) }, | |
c0f3af97 L |
9395 | }, |
9396 | ||
592a252b | 9397 | /* VEX_LEN_0F5A_P_3 */ |
c0f3af97 | 9398 | { |
592a252b L |
9399 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, |
9400 | { VEX_W_TABLE (VEX_W_0F5A_P_3) }, | |
c0f3af97 L |
9401 | }, |
9402 | ||
592a252b | 9403 | /* VEX_LEN_0F5C_P_1 */ |
c0f3af97 | 9404 | { |
592a252b L |
9405 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, |
9406 | { VEX_W_TABLE (VEX_W_0F5C_P_1) }, | |
c0f3af97 L |
9407 | }, |
9408 | ||
592a252b | 9409 | /* VEX_LEN_0F5C_P_3 */ |
c0f3af97 | 9410 | { |
592a252b L |
9411 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, |
9412 | { VEX_W_TABLE (VEX_W_0F5C_P_3) }, | |
c0f3af97 L |
9413 | }, |
9414 | ||
592a252b | 9415 | /* VEX_LEN_0F5D_P_1 */ |
c0f3af97 | 9416 | { |
592a252b L |
9417 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, |
9418 | { VEX_W_TABLE (VEX_W_0F5D_P_1) }, | |
c0f3af97 L |
9419 | }, |
9420 | ||
592a252b | 9421 | /* VEX_LEN_0F5D_P_3 */ |
c0f3af97 | 9422 | { |
592a252b L |
9423 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, |
9424 | { VEX_W_TABLE (VEX_W_0F5D_P_3) }, | |
c0f3af97 L |
9425 | }, |
9426 | ||
592a252b | 9427 | /* VEX_LEN_0F5E_P_1 */ |
c0f3af97 | 9428 | { |
592a252b L |
9429 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, |
9430 | { VEX_W_TABLE (VEX_W_0F5E_P_1) }, | |
c0f3af97 L |
9431 | }, |
9432 | ||
592a252b | 9433 | /* VEX_LEN_0F5E_P_3 */ |
c0f3af97 | 9434 | { |
592a252b L |
9435 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, |
9436 | { VEX_W_TABLE (VEX_W_0F5E_P_3) }, | |
c0f3af97 L |
9437 | }, |
9438 | ||
592a252b | 9439 | /* VEX_LEN_0F5F_P_1 */ |
c0f3af97 | 9440 | { |
592a252b L |
9441 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, |
9442 | { VEX_W_TABLE (VEX_W_0F5F_P_1) }, | |
c0f3af97 L |
9443 | }, |
9444 | ||
592a252b | 9445 | /* VEX_LEN_0F5F_P_3 */ |
c0f3af97 | 9446 | { |
592a252b L |
9447 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, |
9448 | { VEX_W_TABLE (VEX_W_0F5F_P_3) }, | |
c0f3af97 L |
9449 | }, |
9450 | ||
592a252b | 9451 | /* VEX_LEN_0F6E_P_2 */ |
c0f3af97 | 9452 | { |
539f890d L |
9453 | { "vmovK", { XMScalar, Edq } }, |
9454 | { "vmovK", { XMScalar, Edq } }, | |
c0f3af97 L |
9455 | }, |
9456 | ||
592a252b | 9457 | /* VEX_LEN_0F7E_P_1 */ |
c0f3af97 | 9458 | { |
592a252b L |
9459 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, |
9460 | { VEX_W_TABLE (VEX_W_0F7E_P_1) }, | |
c0f3af97 L |
9461 | }, |
9462 | ||
592a252b | 9463 | /* VEX_LEN_0F7E_P_2 */ |
c0f3af97 | 9464 | { |
539f890d | 9465 | { "vmovK", { Edq, XMScalar } }, |
6c30d220 | 9466 | { "vmovK", { Edq, XMScalar } }, |
c0f3af97 L |
9467 | }, |
9468 | ||
43234a1e L |
9469 | /* VEX_LEN_0F90_P_0 */ |
9470 | { | |
9471 | { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, | |
9472 | }, | |
9473 | ||
9474 | /* VEX_LEN_0F91_P_0 */ | |
9475 | { | |
9476 | { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, | |
9477 | }, | |
9478 | ||
9479 | /* VEX_LEN_0F92_P_0 */ | |
9480 | { | |
9481 | { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, | |
9482 | }, | |
9483 | ||
9484 | /* VEX_LEN_0F93_P_0 */ | |
9485 | { | |
9486 | { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, | |
9487 | }, | |
9488 | ||
9489 | /* VEX_LEN_0F98_P_0 */ | |
9490 | { | |
9491 | { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, | |
9492 | }, | |
9493 | ||
6c30d220 | 9494 | /* VEX_LEN_0FAE_R_2_M_0 */ |
c0f3af97 | 9495 | { |
6c30d220 | 9496 | { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) }, |
c0f3af97 L |
9497 | }, |
9498 | ||
6c30d220 | 9499 | /* VEX_LEN_0FAE_R_3_M_0 */ |
c0f3af97 | 9500 | { |
6c30d220 | 9501 | { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) }, |
c0f3af97 L |
9502 | }, |
9503 | ||
6c30d220 | 9504 | /* VEX_LEN_0FC2_P_1 */ |
c0f3af97 | 9505 | { |
6c30d220 L |
9506 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, |
9507 | { VEX_W_TABLE (VEX_W_0FC2_P_1) }, | |
c0f3af97 L |
9508 | }, |
9509 | ||
6c30d220 | 9510 | /* VEX_LEN_0FC2_P_3 */ |
c0f3af97 | 9511 | { |
6c30d220 L |
9512 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, |
9513 | { VEX_W_TABLE (VEX_W_0FC2_P_3) }, | |
c0f3af97 L |
9514 | }, |
9515 | ||
6c30d220 | 9516 | /* VEX_LEN_0FC4_P_2 */ |
c0f3af97 | 9517 | { |
6c30d220 | 9518 | { VEX_W_TABLE (VEX_W_0FC4_P_2) }, |
c0f3af97 L |
9519 | }, |
9520 | ||
6c30d220 | 9521 | /* VEX_LEN_0FC5_P_2 */ |
c0f3af97 | 9522 | { |
6c30d220 | 9523 | { VEX_W_TABLE (VEX_W_0FC5_P_2) }, |
c0f3af97 L |
9524 | }, |
9525 | ||
6c30d220 | 9526 | /* VEX_LEN_0FD6_P_2 */ |
c0f3af97 | 9527 | { |
6c30d220 L |
9528 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, |
9529 | { VEX_W_TABLE (VEX_W_0FD6_P_2) }, | |
c0f3af97 L |
9530 | }, |
9531 | ||
6c30d220 | 9532 | /* VEX_LEN_0FF7_P_2 */ |
c0f3af97 | 9533 | { |
6c30d220 | 9534 | { VEX_W_TABLE (VEX_W_0FF7_P_2) }, |
c0f3af97 L |
9535 | }, |
9536 | ||
6c30d220 | 9537 | /* VEX_LEN_0F3816_P_2 */ |
c0f3af97 | 9538 | { |
6c30d220 L |
9539 | { Bad_Opcode }, |
9540 | { VEX_W_TABLE (VEX_W_0F3816_P_2) }, | |
c0f3af97 L |
9541 | }, |
9542 | ||
6c30d220 | 9543 | /* VEX_LEN_0F3819_P_2 */ |
c0f3af97 | 9544 | { |
6c30d220 L |
9545 | { Bad_Opcode }, |
9546 | { VEX_W_TABLE (VEX_W_0F3819_P_2) }, | |
c0f3af97 L |
9547 | }, |
9548 | ||
6c30d220 | 9549 | /* VEX_LEN_0F381A_P_2_M_0 */ |
c0f3af97 | 9550 | { |
6c30d220 L |
9551 | { Bad_Opcode }, |
9552 | { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, | |
c0f3af97 L |
9553 | }, |
9554 | ||
6c30d220 | 9555 | /* VEX_LEN_0F3836_P_2 */ |
c0f3af97 | 9556 | { |
6c30d220 L |
9557 | { Bad_Opcode }, |
9558 | { VEX_W_TABLE (VEX_W_0F3836_P_2) }, | |
c0f3af97 L |
9559 | }, |
9560 | ||
592a252b | 9561 | /* VEX_LEN_0F3841_P_2 */ |
c0f3af97 | 9562 | { |
592a252b | 9563 | { VEX_W_TABLE (VEX_W_0F3841_P_2) }, |
c0f3af97 L |
9564 | }, |
9565 | ||
6c30d220 L |
9566 | /* VEX_LEN_0F385A_P_2_M_0 */ |
9567 | { | |
9568 | { Bad_Opcode }, | |
9569 | { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) }, | |
9570 | }, | |
9571 | ||
592a252b | 9572 | /* VEX_LEN_0F38DB_P_2 */ |
a5ff0eb2 | 9573 | { |
592a252b | 9574 | { VEX_W_TABLE (VEX_W_0F38DB_P_2) }, |
a5ff0eb2 L |
9575 | }, |
9576 | ||
592a252b | 9577 | /* VEX_LEN_0F38DC_P_2 */ |
a5ff0eb2 | 9578 | { |
592a252b | 9579 | { VEX_W_TABLE (VEX_W_0F38DC_P_2) }, |
a5ff0eb2 L |
9580 | }, |
9581 | ||
592a252b | 9582 | /* VEX_LEN_0F38DD_P_2 */ |
a5ff0eb2 | 9583 | { |
592a252b | 9584 | { VEX_W_TABLE (VEX_W_0F38DD_P_2) }, |
a5ff0eb2 L |
9585 | }, |
9586 | ||
592a252b | 9587 | /* VEX_LEN_0F38DE_P_2 */ |
a5ff0eb2 | 9588 | { |
592a252b | 9589 | { VEX_W_TABLE (VEX_W_0F38DE_P_2) }, |
a5ff0eb2 L |
9590 | }, |
9591 | ||
592a252b | 9592 | /* VEX_LEN_0F38DF_P_2 */ |
a5ff0eb2 | 9593 | { |
592a252b | 9594 | { VEX_W_TABLE (VEX_W_0F38DF_P_2) }, |
a5ff0eb2 L |
9595 | }, |
9596 | ||
f12dc422 L |
9597 | /* VEX_LEN_0F38F2_P_0 */ |
9598 | { | |
9599 | { "andnS", { Gdq, VexGdq, Edq } }, | |
9600 | }, | |
9601 | ||
9602 | /* VEX_LEN_0F38F3_R_1_P_0 */ | |
9603 | { | |
9604 | { "blsrS", { VexGdq, Edq } }, | |
9605 | }, | |
9606 | ||
9607 | /* VEX_LEN_0F38F3_R_2_P_0 */ | |
9608 | { | |
9609 | { "blsmskS", { VexGdq, Edq } }, | |
9610 | }, | |
9611 | ||
9612 | /* VEX_LEN_0F38F3_R_3_P_0 */ | |
9613 | { | |
9614 | { "blsiS", { VexGdq, Edq } }, | |
9615 | }, | |
9616 | ||
6c30d220 L |
9617 | /* VEX_LEN_0F38F5_P_0 */ |
9618 | { | |
9619 | { "bzhiS", { Gdq, Edq, VexGdq } }, | |
9620 | }, | |
9621 | ||
9622 | /* VEX_LEN_0F38F5_P_1 */ | |
9623 | { | |
9624 | { "pextS", { Gdq, VexGdq, Edq } }, | |
9625 | }, | |
9626 | ||
9627 | /* VEX_LEN_0F38F5_P_3 */ | |
9628 | { | |
9629 | { "pdepS", { Gdq, VexGdq, Edq } }, | |
9630 | }, | |
9631 | ||
9632 | /* VEX_LEN_0F38F6_P_3 */ | |
9633 | { | |
9634 | { "mulxS", { Gdq, VexGdq, Edq } }, | |
9635 | }, | |
9636 | ||
f12dc422 L |
9637 | /* VEX_LEN_0F38F7_P_0 */ |
9638 | { | |
9639 | { "bextrS", { Gdq, Edq, VexGdq } }, | |
9640 | }, | |
9641 | ||
6c30d220 L |
9642 | /* VEX_LEN_0F38F7_P_1 */ |
9643 | { | |
9644 | { "sarxS", { Gdq, Edq, VexGdq } }, | |
9645 | }, | |
9646 | ||
9647 | /* VEX_LEN_0F38F7_P_2 */ | |
9648 | { | |
9649 | { "shlxS", { Gdq, Edq, VexGdq } }, | |
9650 | }, | |
9651 | ||
9652 | /* VEX_LEN_0F38F7_P_3 */ | |
9653 | { | |
9654 | { "shrxS", { Gdq, Edq, VexGdq } }, | |
9655 | }, | |
9656 | ||
9657 | /* VEX_LEN_0F3A00_P_2 */ | |
9658 | { | |
9659 | { Bad_Opcode }, | |
9660 | { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, | |
9661 | }, | |
9662 | ||
9663 | /* VEX_LEN_0F3A01_P_2 */ | |
9664 | { | |
9665 | { Bad_Opcode }, | |
9666 | { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, | |
9667 | }, | |
9668 | ||
592a252b | 9669 | /* VEX_LEN_0F3A06_P_2 */ |
c0f3af97 | 9670 | { |
592d1631 | 9671 | { Bad_Opcode }, |
592a252b | 9672 | { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, |
c0f3af97 L |
9673 | }, |
9674 | ||
592a252b | 9675 | /* VEX_LEN_0F3A0A_P_2 */ |
c0f3af97 | 9676 | { |
592a252b L |
9677 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, |
9678 | { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, | |
c0f3af97 L |
9679 | }, |
9680 | ||
592a252b | 9681 | /* VEX_LEN_0F3A0B_P_2 */ |
c0f3af97 | 9682 | { |
592a252b L |
9683 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, |
9684 | { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, | |
c0f3af97 L |
9685 | }, |
9686 | ||
592a252b | 9687 | /* VEX_LEN_0F3A14_P_2 */ |
c0f3af97 | 9688 | { |
592a252b | 9689 | { VEX_W_TABLE (VEX_W_0F3A14_P_2) }, |
c0f3af97 L |
9690 | }, |
9691 | ||
592a252b | 9692 | /* VEX_LEN_0F3A15_P_2 */ |
c0f3af97 | 9693 | { |
592a252b | 9694 | { VEX_W_TABLE (VEX_W_0F3A15_P_2) }, |
c0f3af97 L |
9695 | }, |
9696 | ||
592a252b | 9697 | /* VEX_LEN_0F3A16_P_2 */ |
c0f3af97 L |
9698 | { |
9699 | { "vpextrK", { Edq, XM, Ib } }, | |
c0f3af97 L |
9700 | }, |
9701 | ||
592a252b | 9702 | /* VEX_LEN_0F3A17_P_2 */ |
c0f3af97 L |
9703 | { |
9704 | { "vextractps", { Edqd, XM, Ib } }, | |
c0f3af97 L |
9705 | }, |
9706 | ||
592a252b | 9707 | /* VEX_LEN_0F3A18_P_2 */ |
c0f3af97 | 9708 | { |
592d1631 | 9709 | { Bad_Opcode }, |
592a252b | 9710 | { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, |
c0f3af97 L |
9711 | }, |
9712 | ||
592a252b | 9713 | /* VEX_LEN_0F3A19_P_2 */ |
c0f3af97 | 9714 | { |
592d1631 | 9715 | { Bad_Opcode }, |
592a252b | 9716 | { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, |
c0f3af97 L |
9717 | }, |
9718 | ||
592a252b | 9719 | /* VEX_LEN_0F3A20_P_2 */ |
c0f3af97 | 9720 | { |
592a252b | 9721 | { VEX_W_TABLE (VEX_W_0F3A20_P_2) }, |
c0f3af97 L |
9722 | }, |
9723 | ||
592a252b | 9724 | /* VEX_LEN_0F3A21_P_2 */ |
c0f3af97 | 9725 | { |
592a252b | 9726 | { VEX_W_TABLE (VEX_W_0F3A21_P_2) }, |
c0f3af97 L |
9727 | }, |
9728 | ||
592a252b | 9729 | /* VEX_LEN_0F3A22_P_2 */ |
c0f3af97 L |
9730 | { |
9731 | { "vpinsrK", { XM, Vex128, Edq, Ib } }, | |
c0f3af97 L |
9732 | }, |
9733 | ||
43234a1e L |
9734 | /* VEX_LEN_0F3A30_P_2 */ |
9735 | { | |
9736 | { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, | |
9737 | }, | |
9738 | ||
9739 | /* VEX_LEN_0F3A32_P_2 */ | |
9740 | { | |
9741 | { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, | |
9742 | }, | |
9743 | ||
6c30d220 | 9744 | /* VEX_LEN_0F3A38_P_2 */ |
c0f3af97 | 9745 | { |
6c30d220 L |
9746 | { Bad_Opcode }, |
9747 | { VEX_W_TABLE (VEX_W_0F3A38_P_2) }, | |
c0f3af97 L |
9748 | }, |
9749 | ||
6c30d220 | 9750 | /* VEX_LEN_0F3A39_P_2 */ |
c0f3af97 | 9751 | { |
6c30d220 L |
9752 | { Bad_Opcode }, |
9753 | { VEX_W_TABLE (VEX_W_0F3A39_P_2) }, | |
9754 | }, | |
9755 | ||
9756 | /* VEX_LEN_0F3A41_P_2 */ | |
9757 | { | |
9758 | { VEX_W_TABLE (VEX_W_0F3A41_P_2) }, | |
c0f3af97 L |
9759 | }, |
9760 | ||
592a252b | 9761 | /* VEX_LEN_0F3A44_P_2 */ |
ce2f5b3c | 9762 | { |
592a252b | 9763 | { VEX_W_TABLE (VEX_W_0F3A44_P_2) }, |
ce2f5b3c L |
9764 | }, |
9765 | ||
6c30d220 | 9766 | /* VEX_LEN_0F3A46_P_2 */ |
c0f3af97 | 9767 | { |
6c30d220 L |
9768 | { Bad_Opcode }, |
9769 | { VEX_W_TABLE (VEX_W_0F3A46_P_2) }, | |
c0f3af97 L |
9770 | }, |
9771 | ||
592a252b | 9772 | /* VEX_LEN_0F3A60_P_2 */ |
c0f3af97 | 9773 | { |
592a252b | 9774 | { VEX_W_TABLE (VEX_W_0F3A60_P_2) }, |
c0f3af97 L |
9775 | }, |
9776 | ||
592a252b | 9777 | /* VEX_LEN_0F3A61_P_2 */ |
c0f3af97 | 9778 | { |
592a252b | 9779 | { VEX_W_TABLE (VEX_W_0F3A61_P_2) }, |
c0f3af97 L |
9780 | }, |
9781 | ||
592a252b | 9782 | /* VEX_LEN_0F3A62_P_2 */ |
c0f3af97 | 9783 | { |
592a252b | 9784 | { VEX_W_TABLE (VEX_W_0F3A62_P_2) }, |
c0f3af97 L |
9785 | }, |
9786 | ||
592a252b | 9787 | /* VEX_LEN_0F3A63_P_2 */ |
c0f3af97 | 9788 | { |
592a252b | 9789 | { VEX_W_TABLE (VEX_W_0F3A63_P_2) }, |
c0f3af97 L |
9790 | }, |
9791 | ||
592a252b | 9792 | /* VEX_LEN_0F3A6A_P_2 */ |
922d8de8 | 9793 | { |
206c2556 | 9794 | { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
922d8de8 DR |
9795 | }, |
9796 | ||
592a252b | 9797 | /* VEX_LEN_0F3A6B_P_2 */ |
922d8de8 | 9798 | { |
206c2556 | 9799 | { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
922d8de8 DR |
9800 | }, |
9801 | ||
592a252b | 9802 | /* VEX_LEN_0F3A6E_P_2 */ |
922d8de8 | 9803 | { |
206c2556 | 9804 | { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
922d8de8 DR |
9805 | }, |
9806 | ||
592a252b | 9807 | /* VEX_LEN_0F3A6F_P_2 */ |
922d8de8 | 9808 | { |
206c2556 | 9809 | { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
922d8de8 DR |
9810 | }, |
9811 | ||
592a252b | 9812 | /* VEX_LEN_0F3A7A_P_2 */ |
922d8de8 | 9813 | { |
206c2556 | 9814 | { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
922d8de8 DR |
9815 | }, |
9816 | ||
592a252b | 9817 | /* VEX_LEN_0F3A7B_P_2 */ |
922d8de8 | 9818 | { |
206c2556 | 9819 | { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
922d8de8 DR |
9820 | }, |
9821 | ||
592a252b | 9822 | /* VEX_LEN_0F3A7E_P_2 */ |
922d8de8 | 9823 | { |
206c2556 | 9824 | { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, |
922d8de8 DR |
9825 | }, |
9826 | ||
592a252b | 9827 | /* VEX_LEN_0F3A7F_P_2 */ |
922d8de8 | 9828 | { |
206c2556 | 9829 | { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, |
922d8de8 DR |
9830 | }, |
9831 | ||
592a252b | 9832 | /* VEX_LEN_0F3ADF_P_2 */ |
a5ff0eb2 | 9833 | { |
592a252b | 9834 | { VEX_W_TABLE (VEX_W_0F3ADF_P_2) }, |
a5ff0eb2 | 9835 | }, |
4c807e72 | 9836 | |
6c30d220 L |
9837 | /* VEX_LEN_0F3AF0_P_3 */ |
9838 | { | |
182ae480 | 9839 | { "rorxS", { Gdq, Edq, Ib } }, |
6c30d220 L |
9840 | }, |
9841 | ||
ff688e1f L |
9842 | /* VEX_LEN_0FXOP_08_CC */ |
9843 | { | |
9844 | { "vpcomb", { XM, Vex128, EXx, Ib } }, | |
9845 | }, | |
9846 | ||
9847 | /* VEX_LEN_0FXOP_08_CD */ | |
9848 | { | |
9849 | { "vpcomw", { XM, Vex128, EXx, Ib } }, | |
9850 | }, | |
9851 | ||
9852 | /* VEX_LEN_0FXOP_08_CE */ | |
9853 | { | |
9854 | { "vpcomd", { XM, Vex128, EXx, Ib } }, | |
9855 | }, | |
9856 | ||
9857 | /* VEX_LEN_0FXOP_08_CF */ | |
9858 | { | |
9859 | { "vpcomq", { XM, Vex128, EXx, Ib } }, | |
9860 | }, | |
9861 | ||
9862 | /* VEX_LEN_0FXOP_08_EC */ | |
9863 | { | |
9864 | { "vpcomub", { XM, Vex128, EXx, Ib } }, | |
9865 | }, | |
9866 | ||
9867 | /* VEX_LEN_0FXOP_08_ED */ | |
9868 | { | |
9869 | { "vpcomuw", { XM, Vex128, EXx, Ib } }, | |
9870 | }, | |
9871 | ||
9872 | /* VEX_LEN_0FXOP_08_EE */ | |
9873 | { | |
9874 | { "vpcomud", { XM, Vex128, EXx, Ib } }, | |
9875 | }, | |
9876 | ||
9877 | /* VEX_LEN_0FXOP_08_EF */ | |
9878 | { | |
9879 | { "vpcomuq", { XM, Vex128, EXx, Ib } }, | |
9880 | }, | |
9881 | ||
592a252b | 9882 | /* VEX_LEN_0FXOP_09_80 */ |
5dd85c99 | 9883 | { |
4c807e72 L |
9884 | { "vfrczps", { XM, EXxmm } }, |
9885 | { "vfrczps", { XM, EXymmq } }, | |
5dd85c99 | 9886 | }, |
4c807e72 | 9887 | |
592a252b | 9888 | /* VEX_LEN_0FXOP_09_81 */ |
5dd85c99 | 9889 | { |
4c807e72 L |
9890 | { "vfrczpd", { XM, EXxmm } }, |
9891 | { "vfrczpd", { XM, EXymmq } }, | |
5dd85c99 | 9892 | }, |
331d2d0d L |
9893 | }; |
9894 | ||
9e30b8e0 | 9895 | static const struct dis386 vex_w_table[][2] = { |
b844680a | 9896 | { |
592a252b | 9897 | /* VEX_W_0F10_P_0 */ |
9e30b8e0 | 9898 | { "vmovups", { XM, EXx } }, |
d8faab4e L |
9899 | }, |
9900 | { | |
592a252b | 9901 | /* VEX_W_0F10_P_1 */ |
539f890d | 9902 | { "vmovss", { XMVexScalar, VexScalar, EXdScalar } }, |
d8faab4e L |
9903 | }, |
9904 | { | |
592a252b | 9905 | /* VEX_W_0F10_P_2 */ |
9e30b8e0 | 9906 | { "vmovupd", { XM, EXx } }, |
d8faab4e L |
9907 | }, |
9908 | { | |
592a252b | 9909 | /* VEX_W_0F10_P_3 */ |
539f890d | 9910 | { "vmovsd", { XMVexScalar, VexScalar, EXqScalar } }, |
d8faab4e L |
9911 | }, |
9912 | { | |
592a252b | 9913 | /* VEX_W_0F11_P_0 */ |
9e30b8e0 | 9914 | { "vmovups", { EXxS, XM } }, |
d8faab4e L |
9915 | }, |
9916 | { | |
592a252b | 9917 | /* VEX_W_0F11_P_1 */ |
539f890d | 9918 | { "vmovss", { EXdVexScalarS, VexScalar, XMScalar } }, |
b844680a L |
9919 | }, |
9920 | { | |
592a252b | 9921 | /* VEX_W_0F11_P_2 */ |
9e30b8e0 | 9922 | { "vmovupd", { EXxS, XM } }, |
b844680a L |
9923 | }, |
9924 | { | |
592a252b | 9925 | /* VEX_W_0F11_P_3 */ |
539f890d | 9926 | { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar } }, |
d8faab4e L |
9927 | }, |
9928 | { | |
592a252b | 9929 | /* VEX_W_0F12_P_0_M_0 */ |
9e30b8e0 | 9930 | { "vmovlps", { XM, Vex128, EXq } }, |
b844680a L |
9931 | }, |
9932 | { | |
592a252b | 9933 | /* VEX_W_0F12_P_0_M_1 */ |
9e30b8e0 | 9934 | { "vmovhlps", { XM, Vex128, EXq } }, |
b844680a L |
9935 | }, |
9936 | { | |
592a252b | 9937 | /* VEX_W_0F12_P_1 */ |
9e30b8e0 | 9938 | { "vmovsldup", { XM, EXx } }, |
b844680a L |
9939 | }, |
9940 | { | |
592a252b | 9941 | /* VEX_W_0F12_P_2 */ |
9e30b8e0 | 9942 | { "vmovlpd", { XM, Vex128, EXq } }, |
b844680a L |
9943 | }, |
9944 | { | |
592a252b | 9945 | /* VEX_W_0F12_P_3 */ |
9e30b8e0 | 9946 | { "vmovddup", { XM, EXymmq } }, |
b844680a L |
9947 | }, |
9948 | { | |
592a252b | 9949 | /* VEX_W_0F13_M_0 */ |
9e30b8e0 | 9950 | { "vmovlpX", { EXq, XM } }, |
b844680a L |
9951 | }, |
9952 | { | |
592a252b | 9953 | /* VEX_W_0F14 */ |
9e30b8e0 | 9954 | { "vunpcklpX", { XM, Vex, EXx } }, |
b844680a L |
9955 | }, |
9956 | { | |
592a252b | 9957 | /* VEX_W_0F15 */ |
9e30b8e0 | 9958 | { "vunpckhpX", { XM, Vex, EXx } }, |
b844680a L |
9959 | }, |
9960 | { | |
592a252b | 9961 | /* VEX_W_0F16_P_0_M_0 */ |
9e30b8e0 | 9962 | { "vmovhps", { XM, Vex128, EXq } }, |
9e30b8e0 L |
9963 | }, |
9964 | { | |
592a252b | 9965 | /* VEX_W_0F16_P_0_M_1 */ |
9e30b8e0 | 9966 | { "vmovlhps", { XM, Vex128, EXq } }, |
9e30b8e0 L |
9967 | }, |
9968 | { | |
592a252b | 9969 | /* VEX_W_0F16_P_1 */ |
9e30b8e0 | 9970 | { "vmovshdup", { XM, EXx } }, |
9e30b8e0 L |
9971 | }, |
9972 | { | |
592a252b | 9973 | /* VEX_W_0F16_P_2 */ |
9e30b8e0 | 9974 | { "vmovhpd", { XM, Vex128, EXq } }, |
9e30b8e0 L |
9975 | }, |
9976 | { | |
592a252b | 9977 | /* VEX_W_0F17_M_0 */ |
9e30b8e0 | 9978 | { "vmovhpX", { EXq, XM } }, |
9e30b8e0 L |
9979 | }, |
9980 | { | |
592a252b | 9981 | /* VEX_W_0F28 */ |
9e30b8e0 | 9982 | { "vmovapX", { XM, EXx } }, |
9e30b8e0 L |
9983 | }, |
9984 | { | |
592a252b | 9985 | /* VEX_W_0F29 */ |
9e30b8e0 | 9986 | { "vmovapX", { EXxS, XM } }, |
9e30b8e0 L |
9987 | }, |
9988 | { | |
592a252b | 9989 | /* VEX_W_0F2B_M_0 */ |
9e30b8e0 | 9990 | { "vmovntpX", { Mx, XM } }, |
9e30b8e0 L |
9991 | }, |
9992 | { | |
592a252b | 9993 | /* VEX_W_0F2E_P_0 */ |
7bb15c6f | 9994 | { "vucomiss", { XMScalar, EXdScalar } }, |
9e30b8e0 L |
9995 | }, |
9996 | { | |
592a252b | 9997 | /* VEX_W_0F2E_P_2 */ |
7bb15c6f | 9998 | { "vucomisd", { XMScalar, EXqScalar } }, |
9e30b8e0 L |
9999 | }, |
10000 | { | |
592a252b | 10001 | /* VEX_W_0F2F_P_0 */ |
539f890d | 10002 | { "vcomiss", { XMScalar, EXdScalar } }, |
9e30b8e0 L |
10003 | }, |
10004 | { | |
592a252b | 10005 | /* VEX_W_0F2F_P_2 */ |
539f890d | 10006 | { "vcomisd", { XMScalar, EXqScalar } }, |
9e30b8e0 | 10007 | }, |
43234a1e L |
10008 | { |
10009 | /* VEX_W_0F41_P_0_LEN_1 */ | |
10010 | { "kandw", { MaskG, MaskVex, MaskR } }, | |
10011 | }, | |
10012 | { | |
10013 | /* VEX_W_0F42_P_0_LEN_1 */ | |
10014 | { "kandnw", { MaskG, MaskVex, MaskR } }, | |
10015 | }, | |
10016 | { | |
10017 | /* VEX_W_0F44_P_0_LEN_0 */ | |
10018 | { "knotw", { MaskG, MaskR } }, | |
10019 | }, | |
10020 | { | |
10021 | /* VEX_W_0F45_P_0_LEN_1 */ | |
10022 | { "korw", { MaskG, MaskVex, MaskR } }, | |
10023 | }, | |
10024 | { | |
10025 | /* VEX_W_0F46_P_0_LEN_1 */ | |
10026 | { "kxnorw", { MaskG, MaskVex, MaskR } }, | |
10027 | }, | |
10028 | { | |
10029 | /* VEX_W_0F47_P_0_LEN_1 */ | |
10030 | { "kxorw", { MaskG, MaskVex, MaskR } }, | |
10031 | }, | |
10032 | { | |
10033 | /* VEX_W_0F4B_P_2_LEN_1 */ | |
10034 | { "kunpckbw", { MaskG, MaskVex, MaskR } }, | |
10035 | }, | |
9e30b8e0 | 10036 | { |
592a252b | 10037 | /* VEX_W_0F50_M_0 */ |
9e30b8e0 | 10038 | { "vmovmskpX", { Gdq, XS } }, |
9e30b8e0 L |
10039 | }, |
10040 | { | |
592a252b | 10041 | /* VEX_W_0F51_P_0 */ |
9e30b8e0 | 10042 | { "vsqrtps", { XM, EXx } }, |
9e30b8e0 L |
10043 | }, |
10044 | { | |
592a252b | 10045 | /* VEX_W_0F51_P_1 */ |
539f890d | 10046 | { "vsqrtss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
10047 | }, |
10048 | { | |
592a252b | 10049 | /* VEX_W_0F51_P_2 */ |
9e30b8e0 | 10050 | { "vsqrtpd", { XM, EXx } }, |
9e30b8e0 L |
10051 | }, |
10052 | { | |
592a252b | 10053 | /* VEX_W_0F51_P_3 */ |
539f890d | 10054 | { "vsqrtsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
10055 | }, |
10056 | { | |
592a252b | 10057 | /* VEX_W_0F52_P_0 */ |
9e30b8e0 | 10058 | { "vrsqrtps", { XM, EXx } }, |
9e30b8e0 L |
10059 | }, |
10060 | { | |
592a252b | 10061 | /* VEX_W_0F52_P_1 */ |
539f890d | 10062 | { "vrsqrtss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
10063 | }, |
10064 | { | |
592a252b | 10065 | /* VEX_W_0F53_P_0 */ |
9e30b8e0 | 10066 | { "vrcpps", { XM, EXx } }, |
9e30b8e0 L |
10067 | }, |
10068 | { | |
592a252b | 10069 | /* VEX_W_0F53_P_1 */ |
539f890d | 10070 | { "vrcpss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
10071 | }, |
10072 | { | |
592a252b | 10073 | /* VEX_W_0F58_P_0 */ |
9e30b8e0 | 10074 | { "vaddps", { XM, Vex, EXx } }, |
9e30b8e0 L |
10075 | }, |
10076 | { | |
592a252b | 10077 | /* VEX_W_0F58_P_1 */ |
539f890d | 10078 | { "vaddss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
10079 | }, |
10080 | { | |
592a252b | 10081 | /* VEX_W_0F58_P_2 */ |
9e30b8e0 | 10082 | { "vaddpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10083 | }, |
10084 | { | |
592a252b | 10085 | /* VEX_W_0F58_P_3 */ |
539f890d | 10086 | { "vaddsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
10087 | }, |
10088 | { | |
592a252b | 10089 | /* VEX_W_0F59_P_0 */ |
9e30b8e0 | 10090 | { "vmulps", { XM, Vex, EXx } }, |
9e30b8e0 L |
10091 | }, |
10092 | { | |
592a252b | 10093 | /* VEX_W_0F59_P_1 */ |
539f890d | 10094 | { "vmulss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
10095 | }, |
10096 | { | |
592a252b | 10097 | /* VEX_W_0F59_P_2 */ |
9e30b8e0 | 10098 | { "vmulpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10099 | }, |
10100 | { | |
592a252b | 10101 | /* VEX_W_0F59_P_3 */ |
539f890d | 10102 | { "vmulsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
10103 | }, |
10104 | { | |
592a252b | 10105 | /* VEX_W_0F5A_P_0 */ |
9e30b8e0 | 10106 | { "vcvtps2pd", { XM, EXxmmq } }, |
9e30b8e0 L |
10107 | }, |
10108 | { | |
592a252b | 10109 | /* VEX_W_0F5A_P_1 */ |
539f890d | 10110 | { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
10111 | }, |
10112 | { | |
592a252b | 10113 | /* VEX_W_0F5A_P_3 */ |
539f890d | 10114 | { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
10115 | }, |
10116 | { | |
592a252b | 10117 | /* VEX_W_0F5B_P_0 */ |
9e30b8e0 | 10118 | { "vcvtdq2ps", { XM, EXx } }, |
9e30b8e0 L |
10119 | }, |
10120 | { | |
592a252b | 10121 | /* VEX_W_0F5B_P_1 */ |
9e30b8e0 | 10122 | { "vcvttps2dq", { XM, EXx } }, |
9e30b8e0 L |
10123 | }, |
10124 | { | |
592a252b | 10125 | /* VEX_W_0F5B_P_2 */ |
9e30b8e0 | 10126 | { "vcvtps2dq", { XM, EXx } }, |
9e30b8e0 L |
10127 | }, |
10128 | { | |
592a252b | 10129 | /* VEX_W_0F5C_P_0 */ |
9e30b8e0 | 10130 | { "vsubps", { XM, Vex, EXx } }, |
9e30b8e0 L |
10131 | }, |
10132 | { | |
592a252b | 10133 | /* VEX_W_0F5C_P_1 */ |
539f890d | 10134 | { "vsubss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
10135 | }, |
10136 | { | |
592a252b | 10137 | /* VEX_W_0F5C_P_2 */ |
9e30b8e0 | 10138 | { "vsubpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10139 | }, |
10140 | { | |
592a252b | 10141 | /* VEX_W_0F5C_P_3 */ |
539f890d | 10142 | { "vsubsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
10143 | }, |
10144 | { | |
592a252b | 10145 | /* VEX_W_0F5D_P_0 */ |
9e30b8e0 | 10146 | { "vminps", { XM, Vex, EXx } }, |
9e30b8e0 L |
10147 | }, |
10148 | { | |
592a252b | 10149 | /* VEX_W_0F5D_P_1 */ |
539f890d | 10150 | { "vminss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
10151 | }, |
10152 | { | |
592a252b | 10153 | /* VEX_W_0F5D_P_2 */ |
9e30b8e0 | 10154 | { "vminpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10155 | }, |
10156 | { | |
592a252b | 10157 | /* VEX_W_0F5D_P_3 */ |
539f890d | 10158 | { "vminsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
10159 | }, |
10160 | { | |
592a252b | 10161 | /* VEX_W_0F5E_P_0 */ |
9e30b8e0 | 10162 | { "vdivps", { XM, Vex, EXx } }, |
9e30b8e0 L |
10163 | }, |
10164 | { | |
592a252b | 10165 | /* VEX_W_0F5E_P_1 */ |
539f890d | 10166 | { "vdivss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
10167 | }, |
10168 | { | |
592a252b | 10169 | /* VEX_W_0F5E_P_2 */ |
9e30b8e0 | 10170 | { "vdivpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10171 | }, |
10172 | { | |
592a252b | 10173 | /* VEX_W_0F5E_P_3 */ |
539f890d | 10174 | { "vdivsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
10175 | }, |
10176 | { | |
592a252b | 10177 | /* VEX_W_0F5F_P_0 */ |
9e30b8e0 | 10178 | { "vmaxps", { XM, Vex, EXx } }, |
9e30b8e0 L |
10179 | }, |
10180 | { | |
592a252b | 10181 | /* VEX_W_0F5F_P_1 */ |
539f890d | 10182 | { "vmaxss", { XMScalar, VexScalar, EXdScalar } }, |
9e30b8e0 L |
10183 | }, |
10184 | { | |
592a252b | 10185 | /* VEX_W_0F5F_P_2 */ |
9e30b8e0 | 10186 | { "vmaxpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10187 | }, |
10188 | { | |
592a252b | 10189 | /* VEX_W_0F5F_P_3 */ |
539f890d | 10190 | { "vmaxsd", { XMScalar, VexScalar, EXqScalar } }, |
9e30b8e0 L |
10191 | }, |
10192 | { | |
592a252b | 10193 | /* VEX_W_0F60_P_2 */ |
6c30d220 | 10194 | { "vpunpcklbw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10195 | }, |
10196 | { | |
592a252b | 10197 | /* VEX_W_0F61_P_2 */ |
6c30d220 | 10198 | { "vpunpcklwd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10199 | }, |
10200 | { | |
592a252b | 10201 | /* VEX_W_0F62_P_2 */ |
6c30d220 | 10202 | { "vpunpckldq", { XM, Vex, EXx } }, |
9e30b8e0 L |
10203 | }, |
10204 | { | |
592a252b | 10205 | /* VEX_W_0F63_P_2 */ |
6c30d220 | 10206 | { "vpacksswb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10207 | }, |
10208 | { | |
592a252b | 10209 | /* VEX_W_0F64_P_2 */ |
6c30d220 | 10210 | { "vpcmpgtb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10211 | }, |
10212 | { | |
592a252b | 10213 | /* VEX_W_0F65_P_2 */ |
6c30d220 | 10214 | { "vpcmpgtw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10215 | }, |
10216 | { | |
592a252b | 10217 | /* VEX_W_0F66_P_2 */ |
6c30d220 | 10218 | { "vpcmpgtd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10219 | }, |
10220 | { | |
592a252b | 10221 | /* VEX_W_0F67_P_2 */ |
6c30d220 | 10222 | { "vpackuswb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10223 | }, |
10224 | { | |
592a252b | 10225 | /* VEX_W_0F68_P_2 */ |
6c30d220 | 10226 | { "vpunpckhbw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10227 | }, |
10228 | { | |
592a252b | 10229 | /* VEX_W_0F69_P_2 */ |
6c30d220 | 10230 | { "vpunpckhwd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10231 | }, |
10232 | { | |
592a252b | 10233 | /* VEX_W_0F6A_P_2 */ |
6c30d220 | 10234 | { "vpunpckhdq", { XM, Vex, EXx } }, |
9e30b8e0 L |
10235 | }, |
10236 | { | |
592a252b | 10237 | /* VEX_W_0F6B_P_2 */ |
6c30d220 | 10238 | { "vpackssdw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10239 | }, |
10240 | { | |
592a252b | 10241 | /* VEX_W_0F6C_P_2 */ |
6c30d220 | 10242 | { "vpunpcklqdq", { XM, Vex, EXx } }, |
9e30b8e0 L |
10243 | }, |
10244 | { | |
592a252b | 10245 | /* VEX_W_0F6D_P_2 */ |
6c30d220 | 10246 | { "vpunpckhqdq", { XM, Vex, EXx } }, |
9e30b8e0 L |
10247 | }, |
10248 | { | |
592a252b | 10249 | /* VEX_W_0F6F_P_1 */ |
efdb52b7 | 10250 | { "vmovdqu", { XM, EXx } }, |
9e30b8e0 L |
10251 | }, |
10252 | { | |
592a252b | 10253 | /* VEX_W_0F6F_P_2 */ |
efdb52b7 | 10254 | { "vmovdqa", { XM, EXx } }, |
9e30b8e0 L |
10255 | }, |
10256 | { | |
592a252b | 10257 | /* VEX_W_0F70_P_1 */ |
9e30b8e0 | 10258 | { "vpshufhw", { XM, EXx, Ib } }, |
9e30b8e0 L |
10259 | }, |
10260 | { | |
592a252b | 10261 | /* VEX_W_0F70_P_2 */ |
9e30b8e0 | 10262 | { "vpshufd", { XM, EXx, Ib } }, |
9e30b8e0 L |
10263 | }, |
10264 | { | |
592a252b | 10265 | /* VEX_W_0F70_P_3 */ |
9e30b8e0 | 10266 | { "vpshuflw", { XM, EXx, Ib } }, |
9e30b8e0 L |
10267 | }, |
10268 | { | |
592a252b | 10269 | /* VEX_W_0F71_R_2_P_2 */ |
6c30d220 | 10270 | { "vpsrlw", { Vex, XS, Ib } }, |
9e30b8e0 L |
10271 | }, |
10272 | { | |
592a252b | 10273 | /* VEX_W_0F71_R_4_P_2 */ |
6c30d220 | 10274 | { "vpsraw", { Vex, XS, Ib } }, |
9e30b8e0 L |
10275 | }, |
10276 | { | |
592a252b | 10277 | /* VEX_W_0F71_R_6_P_2 */ |
6c30d220 | 10278 | { "vpsllw", { Vex, XS, Ib } }, |
9e30b8e0 L |
10279 | }, |
10280 | { | |
592a252b | 10281 | /* VEX_W_0F72_R_2_P_2 */ |
6c30d220 | 10282 | { "vpsrld", { Vex, XS, Ib } }, |
9e30b8e0 L |
10283 | }, |
10284 | { | |
592a252b | 10285 | /* VEX_W_0F72_R_4_P_2 */ |
6c30d220 | 10286 | { "vpsrad", { Vex, XS, Ib } }, |
9e30b8e0 L |
10287 | }, |
10288 | { | |
592a252b | 10289 | /* VEX_W_0F72_R_6_P_2 */ |
6c30d220 | 10290 | { "vpslld", { Vex, XS, Ib } }, |
9e30b8e0 L |
10291 | }, |
10292 | { | |
592a252b | 10293 | /* VEX_W_0F73_R_2_P_2 */ |
6c30d220 | 10294 | { "vpsrlq", { Vex, XS, Ib } }, |
9e30b8e0 L |
10295 | }, |
10296 | { | |
592a252b | 10297 | /* VEX_W_0F73_R_3_P_2 */ |
6c30d220 | 10298 | { "vpsrldq", { Vex, XS, Ib } }, |
9e30b8e0 L |
10299 | }, |
10300 | { | |
592a252b | 10301 | /* VEX_W_0F73_R_6_P_2 */ |
6c30d220 | 10302 | { "vpsllq", { Vex, XS, Ib } }, |
9e30b8e0 L |
10303 | }, |
10304 | { | |
592a252b | 10305 | /* VEX_W_0F73_R_7_P_2 */ |
6c30d220 | 10306 | { "vpslldq", { Vex, XS, Ib } }, |
9e30b8e0 L |
10307 | }, |
10308 | { | |
592a252b | 10309 | /* VEX_W_0F74_P_2 */ |
6c30d220 | 10310 | { "vpcmpeqb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10311 | }, |
10312 | { | |
592a252b | 10313 | /* VEX_W_0F75_P_2 */ |
6c30d220 | 10314 | { "vpcmpeqw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10315 | }, |
10316 | { | |
592a252b | 10317 | /* VEX_W_0F76_P_2 */ |
6c30d220 | 10318 | { "vpcmpeqd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10319 | }, |
10320 | { | |
592a252b | 10321 | /* VEX_W_0F77_P_0 */ |
9e30b8e0 | 10322 | { "", { VZERO } }, |
9e30b8e0 L |
10323 | }, |
10324 | { | |
592a252b | 10325 | /* VEX_W_0F7C_P_2 */ |
9e30b8e0 | 10326 | { "vhaddpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10327 | }, |
10328 | { | |
592a252b | 10329 | /* VEX_W_0F7C_P_3 */ |
9e30b8e0 | 10330 | { "vhaddps", { XM, Vex, EXx } }, |
9e30b8e0 L |
10331 | }, |
10332 | { | |
592a252b | 10333 | /* VEX_W_0F7D_P_2 */ |
9e30b8e0 | 10334 | { "vhsubpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10335 | }, |
10336 | { | |
592a252b | 10337 | /* VEX_W_0F7D_P_3 */ |
9e30b8e0 | 10338 | { "vhsubps", { XM, Vex, EXx } }, |
9e30b8e0 L |
10339 | }, |
10340 | { | |
592a252b | 10341 | /* VEX_W_0F7E_P_1 */ |
539f890d | 10342 | { "vmovq", { XMScalar, EXqScalar } }, |
9e30b8e0 L |
10343 | }, |
10344 | { | |
592a252b | 10345 | /* VEX_W_0F7F_P_1 */ |
9e30b8e0 | 10346 | { "vmovdqu", { EXxS, XM } }, |
9e30b8e0 L |
10347 | }, |
10348 | { | |
592a252b | 10349 | /* VEX_W_0F7F_P_2 */ |
9e30b8e0 | 10350 | { "vmovdqa", { EXxS, XM } }, |
9e30b8e0 | 10351 | }, |
43234a1e L |
10352 | { |
10353 | /* VEX_W_0F90_P_0_LEN_0 */ | |
10354 | { "kmovw", { MaskG, MaskE } }, | |
10355 | }, | |
10356 | { | |
10357 | /* VEX_W_0F91_P_0_LEN_0 */ | |
10358 | { "kmovw", { Ew, MaskG } }, | |
10359 | }, | |
10360 | { | |
10361 | /* VEX_W_0F92_P_0_LEN_0 */ | |
10362 | { "kmovw", { MaskG, Rdq } }, | |
10363 | }, | |
10364 | { | |
10365 | /* VEX_W_0F93_P_0_LEN_0 */ | |
10366 | { "kmovw", { Gdq, MaskR } }, | |
10367 | }, | |
10368 | { | |
10369 | /* VEX_W_0F98_P_0_LEN_0 */ | |
10370 | { "kortestw", { MaskG, MaskR } }, | |
10371 | }, | |
9e30b8e0 | 10372 | { |
592a252b | 10373 | /* VEX_W_0FAE_R_2_M_0 */ |
9e30b8e0 | 10374 | { "vldmxcsr", { Md } }, |
9e30b8e0 L |
10375 | }, |
10376 | { | |
592a252b | 10377 | /* VEX_W_0FAE_R_3_M_0 */ |
9e30b8e0 | 10378 | { "vstmxcsr", { Md } }, |
9e30b8e0 L |
10379 | }, |
10380 | { | |
592a252b | 10381 | /* VEX_W_0FC2_P_0 */ |
9e30b8e0 | 10382 | { "vcmpps", { XM, Vex, EXx, VCMP } }, |
9e30b8e0 L |
10383 | }, |
10384 | { | |
592a252b | 10385 | /* VEX_W_0FC2_P_1 */ |
539f890d | 10386 | { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP } }, |
9e30b8e0 L |
10387 | }, |
10388 | { | |
592a252b | 10389 | /* VEX_W_0FC2_P_2 */ |
9e30b8e0 | 10390 | { "vcmppd", { XM, Vex, EXx, VCMP } }, |
9e30b8e0 L |
10391 | }, |
10392 | { | |
592a252b | 10393 | /* VEX_W_0FC2_P_3 */ |
539f890d | 10394 | { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP } }, |
9e30b8e0 L |
10395 | }, |
10396 | { | |
592a252b | 10397 | /* VEX_W_0FC4_P_2 */ |
9e30b8e0 | 10398 | { "vpinsrw", { XM, Vex128, Edqw, Ib } }, |
9e30b8e0 L |
10399 | }, |
10400 | { | |
592a252b | 10401 | /* VEX_W_0FC5_P_2 */ |
9e30b8e0 | 10402 | { "vpextrw", { Gdq, XS, Ib } }, |
9e30b8e0 L |
10403 | }, |
10404 | { | |
592a252b | 10405 | /* VEX_W_0FD0_P_2 */ |
9e30b8e0 | 10406 | { "vaddsubpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10407 | }, |
10408 | { | |
592a252b | 10409 | /* VEX_W_0FD0_P_3 */ |
9e30b8e0 | 10410 | { "vaddsubps", { XM, Vex, EXx } }, |
9e30b8e0 L |
10411 | }, |
10412 | { | |
592a252b | 10413 | /* VEX_W_0FD1_P_2 */ |
6c30d220 | 10414 | { "vpsrlw", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
10415 | }, |
10416 | { | |
592a252b | 10417 | /* VEX_W_0FD2_P_2 */ |
6c30d220 | 10418 | { "vpsrld", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
10419 | }, |
10420 | { | |
592a252b | 10421 | /* VEX_W_0FD3_P_2 */ |
6c30d220 | 10422 | { "vpsrlq", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
10423 | }, |
10424 | { | |
592a252b | 10425 | /* VEX_W_0FD4_P_2 */ |
6c30d220 | 10426 | { "vpaddq", { XM, Vex, EXx } }, |
9e30b8e0 L |
10427 | }, |
10428 | { | |
592a252b | 10429 | /* VEX_W_0FD5_P_2 */ |
6c30d220 | 10430 | { "vpmullw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10431 | }, |
10432 | { | |
592a252b | 10433 | /* VEX_W_0FD6_P_2 */ |
539f890d | 10434 | { "vmovq", { EXqScalarS, XMScalar } }, |
9e30b8e0 L |
10435 | }, |
10436 | { | |
592a252b | 10437 | /* VEX_W_0FD7_P_2_M_1 */ |
9e30b8e0 | 10438 | { "vpmovmskb", { Gdq, XS } }, |
9e30b8e0 L |
10439 | }, |
10440 | { | |
592a252b | 10441 | /* VEX_W_0FD8_P_2 */ |
6c30d220 | 10442 | { "vpsubusb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10443 | }, |
10444 | { | |
592a252b | 10445 | /* VEX_W_0FD9_P_2 */ |
6c30d220 | 10446 | { "vpsubusw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10447 | }, |
10448 | { | |
592a252b | 10449 | /* VEX_W_0FDA_P_2 */ |
6c30d220 | 10450 | { "vpminub", { XM, Vex, EXx } }, |
9e30b8e0 L |
10451 | }, |
10452 | { | |
592a252b | 10453 | /* VEX_W_0FDB_P_2 */ |
6c30d220 | 10454 | { "vpand", { XM, Vex, EXx } }, |
9e30b8e0 L |
10455 | }, |
10456 | { | |
592a252b | 10457 | /* VEX_W_0FDC_P_2 */ |
6c30d220 | 10458 | { "vpaddusb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10459 | }, |
10460 | { | |
592a252b | 10461 | /* VEX_W_0FDD_P_2 */ |
6c30d220 | 10462 | { "vpaddusw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10463 | }, |
10464 | { | |
592a252b | 10465 | /* VEX_W_0FDE_P_2 */ |
6c30d220 | 10466 | { "vpmaxub", { XM, Vex, EXx } }, |
9e30b8e0 L |
10467 | }, |
10468 | { | |
592a252b | 10469 | /* VEX_W_0FDF_P_2 */ |
6c30d220 | 10470 | { "vpandn", { XM, Vex, EXx } }, |
9e30b8e0 L |
10471 | }, |
10472 | { | |
592a252b | 10473 | /* VEX_W_0FE0_P_2 */ |
6c30d220 | 10474 | { "vpavgb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10475 | }, |
10476 | { | |
592a252b | 10477 | /* VEX_W_0FE1_P_2 */ |
6c30d220 | 10478 | { "vpsraw", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
10479 | }, |
10480 | { | |
592a252b | 10481 | /* VEX_W_0FE2_P_2 */ |
6c30d220 | 10482 | { "vpsrad", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
10483 | }, |
10484 | { | |
592a252b | 10485 | /* VEX_W_0FE3_P_2 */ |
6c30d220 | 10486 | { "vpavgw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10487 | }, |
10488 | { | |
592a252b | 10489 | /* VEX_W_0FE4_P_2 */ |
6c30d220 | 10490 | { "vpmulhuw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10491 | }, |
10492 | { | |
592a252b | 10493 | /* VEX_W_0FE5_P_2 */ |
6c30d220 | 10494 | { "vpmulhw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10495 | }, |
10496 | { | |
592a252b | 10497 | /* VEX_W_0FE6_P_1 */ |
efdb52b7 | 10498 | { "vcvtdq2pd", { XM, EXxmmq } }, |
9e30b8e0 L |
10499 | }, |
10500 | { | |
592a252b | 10501 | /* VEX_W_0FE6_P_2 */ |
a179a9fd | 10502 | { "vcvttpd2dq%XY", { XMM, EXx } }, |
9e30b8e0 L |
10503 | }, |
10504 | { | |
592a252b | 10505 | /* VEX_W_0FE6_P_3 */ |
a179a9fd | 10506 | { "vcvtpd2dq%XY", { XMM, EXx } }, |
9e30b8e0 L |
10507 | }, |
10508 | { | |
592a252b | 10509 | /* VEX_W_0FE7_P_2_M_0 */ |
9e30b8e0 | 10510 | { "vmovntdq", { Mx, XM } }, |
9e30b8e0 L |
10511 | }, |
10512 | { | |
592a252b | 10513 | /* VEX_W_0FE8_P_2 */ |
6c30d220 | 10514 | { "vpsubsb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10515 | }, |
10516 | { | |
592a252b | 10517 | /* VEX_W_0FE9_P_2 */ |
6c30d220 | 10518 | { "vpsubsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10519 | }, |
10520 | { | |
592a252b | 10521 | /* VEX_W_0FEA_P_2 */ |
6c30d220 | 10522 | { "vpminsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10523 | }, |
10524 | { | |
592a252b | 10525 | /* VEX_W_0FEB_P_2 */ |
6c30d220 | 10526 | { "vpor", { XM, Vex, EXx } }, |
9e30b8e0 L |
10527 | }, |
10528 | { | |
592a252b | 10529 | /* VEX_W_0FEC_P_2 */ |
6c30d220 | 10530 | { "vpaddsb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10531 | }, |
10532 | { | |
592a252b | 10533 | /* VEX_W_0FED_P_2 */ |
6c30d220 | 10534 | { "vpaddsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10535 | }, |
10536 | { | |
592a252b | 10537 | /* VEX_W_0FEE_P_2 */ |
6c30d220 | 10538 | { "vpmaxsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10539 | }, |
10540 | { | |
592a252b | 10541 | /* VEX_W_0FEF_P_2 */ |
6c30d220 | 10542 | { "vpxor", { XM, Vex, EXx } }, |
9e30b8e0 L |
10543 | }, |
10544 | { | |
592a252b | 10545 | /* VEX_W_0FF0_P_3_M_0 */ |
9e30b8e0 | 10546 | { "vlddqu", { XM, M } }, |
9e30b8e0 L |
10547 | }, |
10548 | { | |
592a252b | 10549 | /* VEX_W_0FF1_P_2 */ |
6c30d220 | 10550 | { "vpsllw", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
10551 | }, |
10552 | { | |
592a252b | 10553 | /* VEX_W_0FF2_P_2 */ |
6c30d220 | 10554 | { "vpslld", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
10555 | }, |
10556 | { | |
592a252b | 10557 | /* VEX_W_0FF3_P_2 */ |
6c30d220 | 10558 | { "vpsllq", { XM, Vex, EXxmm } }, |
9e30b8e0 L |
10559 | }, |
10560 | { | |
592a252b | 10561 | /* VEX_W_0FF4_P_2 */ |
6c30d220 | 10562 | { "vpmuludq", { XM, Vex, EXx } }, |
9e30b8e0 L |
10563 | }, |
10564 | { | |
592a252b | 10565 | /* VEX_W_0FF5_P_2 */ |
6c30d220 | 10566 | { "vpmaddwd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10567 | }, |
10568 | { | |
592a252b | 10569 | /* VEX_W_0FF6_P_2 */ |
6c30d220 | 10570 | { "vpsadbw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10571 | }, |
10572 | { | |
592a252b | 10573 | /* VEX_W_0FF7_P_2 */ |
9e30b8e0 | 10574 | { "vmaskmovdqu", { XM, XS } }, |
9e30b8e0 L |
10575 | }, |
10576 | { | |
592a252b | 10577 | /* VEX_W_0FF8_P_2 */ |
6c30d220 | 10578 | { "vpsubb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10579 | }, |
10580 | { | |
592a252b | 10581 | /* VEX_W_0FF9_P_2 */ |
6c30d220 | 10582 | { "vpsubw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10583 | }, |
10584 | { | |
592a252b | 10585 | /* VEX_W_0FFA_P_2 */ |
6c30d220 | 10586 | { "vpsubd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10587 | }, |
10588 | { | |
592a252b | 10589 | /* VEX_W_0FFB_P_2 */ |
6c30d220 | 10590 | { "vpsubq", { XM, Vex, EXx } }, |
9e30b8e0 L |
10591 | }, |
10592 | { | |
592a252b | 10593 | /* VEX_W_0FFC_P_2 */ |
6c30d220 | 10594 | { "vpaddb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10595 | }, |
10596 | { | |
592a252b | 10597 | /* VEX_W_0FFD_P_2 */ |
6c30d220 | 10598 | { "vpaddw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10599 | }, |
10600 | { | |
592a252b | 10601 | /* VEX_W_0FFE_P_2 */ |
6c30d220 | 10602 | { "vpaddd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10603 | }, |
10604 | { | |
592a252b | 10605 | /* VEX_W_0F3800_P_2 */ |
6c30d220 | 10606 | { "vpshufb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10607 | }, |
10608 | { | |
592a252b | 10609 | /* VEX_W_0F3801_P_2 */ |
6c30d220 | 10610 | { "vphaddw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10611 | }, |
10612 | { | |
592a252b | 10613 | /* VEX_W_0F3802_P_2 */ |
6c30d220 | 10614 | { "vphaddd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10615 | }, |
10616 | { | |
592a252b | 10617 | /* VEX_W_0F3803_P_2 */ |
6c30d220 | 10618 | { "vphaddsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10619 | }, |
10620 | { | |
592a252b | 10621 | /* VEX_W_0F3804_P_2 */ |
6c30d220 | 10622 | { "vpmaddubsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10623 | }, |
10624 | { | |
592a252b | 10625 | /* VEX_W_0F3805_P_2 */ |
6c30d220 | 10626 | { "vphsubw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10627 | }, |
10628 | { | |
592a252b | 10629 | /* VEX_W_0F3806_P_2 */ |
6c30d220 | 10630 | { "vphsubd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10631 | }, |
10632 | { | |
592a252b | 10633 | /* VEX_W_0F3807_P_2 */ |
6c30d220 | 10634 | { "vphsubsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10635 | }, |
10636 | { | |
592a252b | 10637 | /* VEX_W_0F3808_P_2 */ |
6c30d220 | 10638 | { "vpsignb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10639 | }, |
10640 | { | |
592a252b | 10641 | /* VEX_W_0F3809_P_2 */ |
6c30d220 | 10642 | { "vpsignw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10643 | }, |
10644 | { | |
592a252b | 10645 | /* VEX_W_0F380A_P_2 */ |
6c30d220 | 10646 | { "vpsignd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10647 | }, |
10648 | { | |
592a252b | 10649 | /* VEX_W_0F380B_P_2 */ |
6c30d220 | 10650 | { "vpmulhrsw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10651 | }, |
10652 | { | |
592a252b | 10653 | /* VEX_W_0F380C_P_2 */ |
9e30b8e0 | 10654 | { "vpermilps", { XM, Vex, EXx } }, |
9e30b8e0 L |
10655 | }, |
10656 | { | |
592a252b | 10657 | /* VEX_W_0F380D_P_2 */ |
9e30b8e0 | 10658 | { "vpermilpd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10659 | }, |
10660 | { | |
592a252b | 10661 | /* VEX_W_0F380E_P_2 */ |
9e30b8e0 | 10662 | { "vtestps", { XM, EXx } }, |
9e30b8e0 L |
10663 | }, |
10664 | { | |
592a252b | 10665 | /* VEX_W_0F380F_P_2 */ |
9e30b8e0 | 10666 | { "vtestpd", { XM, EXx } }, |
9e30b8e0 | 10667 | }, |
6c30d220 L |
10668 | { |
10669 | /* VEX_W_0F3816_P_2 */ | |
10670 | { "vpermps", { XM, Vex, EXx } }, | |
10671 | }, | |
9e30b8e0 | 10672 | { |
592a252b | 10673 | /* VEX_W_0F3817_P_2 */ |
9e30b8e0 | 10674 | { "vptest", { XM, EXx } }, |
9e30b8e0 | 10675 | }, |
bcf2684f | 10676 | { |
6c30d220 L |
10677 | /* VEX_W_0F3818_P_2 */ |
10678 | { "vbroadcastss", { XM, EXxmm_md } }, | |
bcf2684f | 10679 | }, |
9e30b8e0 | 10680 | { |
6c30d220 L |
10681 | /* VEX_W_0F3819_P_2 */ |
10682 | { "vbroadcastsd", { XM, EXxmm_mq } }, | |
9e30b8e0 L |
10683 | }, |
10684 | { | |
592a252b | 10685 | /* VEX_W_0F381A_P_2_M_0 */ |
9e30b8e0 | 10686 | { "vbroadcastf128", { XM, Mxmm } }, |
9e30b8e0 L |
10687 | }, |
10688 | { | |
592a252b | 10689 | /* VEX_W_0F381C_P_2 */ |
9e30b8e0 | 10690 | { "vpabsb", { XM, EXx } }, |
9e30b8e0 L |
10691 | }, |
10692 | { | |
592a252b | 10693 | /* VEX_W_0F381D_P_2 */ |
9e30b8e0 | 10694 | { "vpabsw", { XM, EXx } }, |
9e30b8e0 L |
10695 | }, |
10696 | { | |
592a252b | 10697 | /* VEX_W_0F381E_P_2 */ |
9e30b8e0 | 10698 | { "vpabsd", { XM, EXx } }, |
9e30b8e0 L |
10699 | }, |
10700 | { | |
592a252b | 10701 | /* VEX_W_0F3820_P_2 */ |
6c30d220 | 10702 | { "vpmovsxbw", { XM, EXxmmq } }, |
9e30b8e0 L |
10703 | }, |
10704 | { | |
592a252b | 10705 | /* VEX_W_0F3821_P_2 */ |
6c30d220 | 10706 | { "vpmovsxbd", { XM, EXxmmqd } }, |
9e30b8e0 L |
10707 | }, |
10708 | { | |
592a252b | 10709 | /* VEX_W_0F3822_P_2 */ |
6c30d220 | 10710 | { "vpmovsxbq", { XM, EXxmmdw } }, |
9e30b8e0 L |
10711 | }, |
10712 | { | |
592a252b | 10713 | /* VEX_W_0F3823_P_2 */ |
6c30d220 | 10714 | { "vpmovsxwd", { XM, EXxmmq } }, |
9e30b8e0 L |
10715 | }, |
10716 | { | |
592a252b | 10717 | /* VEX_W_0F3824_P_2 */ |
6c30d220 | 10718 | { "vpmovsxwq", { XM, EXxmmqd } }, |
9e30b8e0 L |
10719 | }, |
10720 | { | |
592a252b | 10721 | /* VEX_W_0F3825_P_2 */ |
6c30d220 | 10722 | { "vpmovsxdq", { XM, EXxmmq } }, |
9e30b8e0 L |
10723 | }, |
10724 | { | |
592a252b | 10725 | /* VEX_W_0F3828_P_2 */ |
6c30d220 | 10726 | { "vpmuldq", { XM, Vex, EXx } }, |
9e30b8e0 L |
10727 | }, |
10728 | { | |
592a252b | 10729 | /* VEX_W_0F3829_P_2 */ |
6c30d220 | 10730 | { "vpcmpeqq", { XM, Vex, EXx } }, |
9e30b8e0 L |
10731 | }, |
10732 | { | |
592a252b | 10733 | /* VEX_W_0F382A_P_2_M_0 */ |
9e30b8e0 | 10734 | { "vmovntdqa", { XM, Mx } }, |
9e30b8e0 L |
10735 | }, |
10736 | { | |
592a252b | 10737 | /* VEX_W_0F382B_P_2 */ |
6c30d220 | 10738 | { "vpackusdw", { XM, Vex, EXx } }, |
9e30b8e0 | 10739 | }, |
53aa04a0 | 10740 | { |
592a252b | 10741 | /* VEX_W_0F382C_P_2_M_0 */ |
53aa04a0 | 10742 | { "vmaskmovps", { XM, Vex, Mx } }, |
53aa04a0 L |
10743 | }, |
10744 | { | |
592a252b | 10745 | /* VEX_W_0F382D_P_2_M_0 */ |
53aa04a0 | 10746 | { "vmaskmovpd", { XM, Vex, Mx } }, |
53aa04a0 L |
10747 | }, |
10748 | { | |
592a252b | 10749 | /* VEX_W_0F382E_P_2_M_0 */ |
53aa04a0 | 10750 | { "vmaskmovps", { Mx, Vex, XM } }, |
53aa04a0 L |
10751 | }, |
10752 | { | |
592a252b | 10753 | /* VEX_W_0F382F_P_2_M_0 */ |
53aa04a0 | 10754 | { "vmaskmovpd", { Mx, Vex, XM } }, |
53aa04a0 | 10755 | }, |
9e30b8e0 | 10756 | { |
592a252b | 10757 | /* VEX_W_0F3830_P_2 */ |
6c30d220 | 10758 | { "vpmovzxbw", { XM, EXxmmq } }, |
9e30b8e0 L |
10759 | }, |
10760 | { | |
592a252b | 10761 | /* VEX_W_0F3831_P_2 */ |
6c30d220 | 10762 | { "vpmovzxbd", { XM, EXxmmqd } }, |
9e30b8e0 L |
10763 | }, |
10764 | { | |
592a252b | 10765 | /* VEX_W_0F3832_P_2 */ |
6c30d220 | 10766 | { "vpmovzxbq", { XM, EXxmmdw } }, |
9e30b8e0 L |
10767 | }, |
10768 | { | |
592a252b | 10769 | /* VEX_W_0F3833_P_2 */ |
6c30d220 | 10770 | { "vpmovzxwd", { XM, EXxmmq } }, |
9e30b8e0 L |
10771 | }, |
10772 | { | |
592a252b | 10773 | /* VEX_W_0F3834_P_2 */ |
6c30d220 | 10774 | { "vpmovzxwq", { XM, EXxmmqd } }, |
9e30b8e0 L |
10775 | }, |
10776 | { | |
592a252b | 10777 | /* VEX_W_0F3835_P_2 */ |
6c30d220 L |
10778 | { "vpmovzxdq", { XM, EXxmmq } }, |
10779 | }, | |
10780 | { | |
10781 | /* VEX_W_0F3836_P_2 */ | |
10782 | { "vpermd", { XM, Vex, EXx } }, | |
9e30b8e0 L |
10783 | }, |
10784 | { | |
592a252b | 10785 | /* VEX_W_0F3837_P_2 */ |
6c30d220 | 10786 | { "vpcmpgtq", { XM, Vex, EXx } }, |
9e30b8e0 L |
10787 | }, |
10788 | { | |
592a252b | 10789 | /* VEX_W_0F3838_P_2 */ |
6c30d220 | 10790 | { "vpminsb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10791 | }, |
10792 | { | |
592a252b | 10793 | /* VEX_W_0F3839_P_2 */ |
6c30d220 | 10794 | { "vpminsd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10795 | }, |
10796 | { | |
592a252b | 10797 | /* VEX_W_0F383A_P_2 */ |
6c30d220 | 10798 | { "vpminuw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10799 | }, |
10800 | { | |
592a252b | 10801 | /* VEX_W_0F383B_P_2 */ |
6c30d220 | 10802 | { "vpminud", { XM, Vex, EXx } }, |
9e30b8e0 L |
10803 | }, |
10804 | { | |
592a252b | 10805 | /* VEX_W_0F383C_P_2 */ |
6c30d220 | 10806 | { "vpmaxsb", { XM, Vex, EXx } }, |
9e30b8e0 L |
10807 | }, |
10808 | { | |
592a252b | 10809 | /* VEX_W_0F383D_P_2 */ |
6c30d220 | 10810 | { "vpmaxsd", { XM, Vex, EXx } }, |
9e30b8e0 L |
10811 | }, |
10812 | { | |
592a252b | 10813 | /* VEX_W_0F383E_P_2 */ |
6c30d220 | 10814 | { "vpmaxuw", { XM, Vex, EXx } }, |
9e30b8e0 L |
10815 | }, |
10816 | { | |
592a252b | 10817 | /* VEX_W_0F383F_P_2 */ |
6c30d220 | 10818 | { "vpmaxud", { XM, Vex, EXx } }, |
9e30b8e0 L |
10819 | }, |
10820 | { | |
592a252b | 10821 | /* VEX_W_0F3840_P_2 */ |
6c30d220 | 10822 | { "vpmulld", { XM, Vex, EXx } }, |
9e30b8e0 L |
10823 | }, |
10824 | { | |
592a252b | 10825 | /* VEX_W_0F3841_P_2 */ |
9e30b8e0 | 10826 | { "vphminposuw", { XM, EXx } }, |
9e30b8e0 | 10827 | }, |
6c30d220 L |
10828 | { |
10829 | /* VEX_W_0F3846_P_2 */ | |
10830 | { "vpsravd", { XM, Vex, EXx } }, | |
10831 | }, | |
10832 | { | |
10833 | /* VEX_W_0F3858_P_2 */ | |
10834 | { "vpbroadcastd", { XM, EXxmm_md } }, | |
10835 | }, | |
10836 | { | |
10837 | /* VEX_W_0F3859_P_2 */ | |
10838 | { "vpbroadcastq", { XM, EXxmm_mq } }, | |
10839 | }, | |
10840 | { | |
10841 | /* VEX_W_0F385A_P_2_M_0 */ | |
10842 | { "vbroadcasti128", { XM, Mxmm } }, | |
10843 | }, | |
10844 | { | |
10845 | /* VEX_W_0F3878_P_2 */ | |
10846 | { "vpbroadcastb", { XM, EXxmm_mb } }, | |
10847 | }, | |
10848 | { | |
10849 | /* VEX_W_0F3879_P_2 */ | |
10850 | { "vpbroadcastw", { XM, EXxmm_mw } }, | |
10851 | }, | |
9e30b8e0 | 10852 | { |
592a252b | 10853 | /* VEX_W_0F38DB_P_2 */ |
9e30b8e0 | 10854 | { "vaesimc", { XM, EXx } }, |
9e30b8e0 L |
10855 | }, |
10856 | { | |
592a252b | 10857 | /* VEX_W_0F38DC_P_2 */ |
9e30b8e0 | 10858 | { "vaesenc", { XM, Vex128, EXx } }, |
9e30b8e0 L |
10859 | }, |
10860 | { | |
592a252b | 10861 | /* VEX_W_0F38DD_P_2 */ |
9e30b8e0 | 10862 | { "vaesenclast", { XM, Vex128, EXx } }, |
9e30b8e0 L |
10863 | }, |
10864 | { | |
592a252b | 10865 | /* VEX_W_0F38DE_P_2 */ |
9e30b8e0 | 10866 | { "vaesdec", { XM, Vex128, EXx } }, |
9e30b8e0 L |
10867 | }, |
10868 | { | |
592a252b | 10869 | /* VEX_W_0F38DF_P_2 */ |
9e30b8e0 | 10870 | { "vaesdeclast", { XM, Vex128, EXx } }, |
9e30b8e0 | 10871 | }, |
6c30d220 L |
10872 | { |
10873 | /* VEX_W_0F3A00_P_2 */ | |
10874 | { Bad_Opcode }, | |
10875 | { "vpermq", { XM, EXx, Ib } }, | |
10876 | }, | |
10877 | { | |
10878 | /* VEX_W_0F3A01_P_2 */ | |
10879 | { Bad_Opcode }, | |
10880 | { "vpermpd", { XM, EXx, Ib } }, | |
10881 | }, | |
10882 | { | |
10883 | /* VEX_W_0F3A02_P_2 */ | |
10884 | { "vpblendd", { XM, Vex, EXx, Ib } }, | |
10885 | }, | |
9e30b8e0 | 10886 | { |
592a252b | 10887 | /* VEX_W_0F3A04_P_2 */ |
9e30b8e0 | 10888 | { "vpermilps", { XM, EXx, Ib } }, |
9e30b8e0 L |
10889 | }, |
10890 | { | |
592a252b | 10891 | /* VEX_W_0F3A05_P_2 */ |
9e30b8e0 | 10892 | { "vpermilpd", { XM, EXx, Ib } }, |
9e30b8e0 L |
10893 | }, |
10894 | { | |
592a252b | 10895 | /* VEX_W_0F3A06_P_2 */ |
9e30b8e0 | 10896 | { "vperm2f128", { XM, Vex256, EXx, Ib } }, |
9e30b8e0 L |
10897 | }, |
10898 | { | |
592a252b | 10899 | /* VEX_W_0F3A08_P_2 */ |
9e30b8e0 | 10900 | { "vroundps", { XM, EXx, Ib } }, |
9e30b8e0 L |
10901 | }, |
10902 | { | |
592a252b | 10903 | /* VEX_W_0F3A09_P_2 */ |
9e30b8e0 | 10904 | { "vroundpd", { XM, EXx, Ib } }, |
9e30b8e0 L |
10905 | }, |
10906 | { | |
592a252b | 10907 | /* VEX_W_0F3A0A_P_2 */ |
539f890d | 10908 | { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib } }, |
9e30b8e0 L |
10909 | }, |
10910 | { | |
592a252b | 10911 | /* VEX_W_0F3A0B_P_2 */ |
539f890d | 10912 | { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib } }, |
9e30b8e0 L |
10913 | }, |
10914 | { | |
592a252b | 10915 | /* VEX_W_0F3A0C_P_2 */ |
9e30b8e0 | 10916 | { "vblendps", { XM, Vex, EXx, Ib } }, |
9e30b8e0 L |
10917 | }, |
10918 | { | |
592a252b | 10919 | /* VEX_W_0F3A0D_P_2 */ |
9e30b8e0 | 10920 | { "vblendpd", { XM, Vex, EXx, Ib } }, |
9e30b8e0 L |
10921 | }, |
10922 | { | |
592a252b | 10923 | /* VEX_W_0F3A0E_P_2 */ |
6c30d220 | 10924 | { "vpblendw", { XM, Vex, EXx, Ib } }, |
9e30b8e0 L |
10925 | }, |
10926 | { | |
592a252b | 10927 | /* VEX_W_0F3A0F_P_2 */ |
6c30d220 | 10928 | { "vpalignr", { XM, Vex, EXx, Ib } }, |
9e30b8e0 L |
10929 | }, |
10930 | { | |
592a252b | 10931 | /* VEX_W_0F3A14_P_2 */ |
9e30b8e0 | 10932 | { "vpextrb", { Edqb, XM, Ib } }, |
9e30b8e0 L |
10933 | }, |
10934 | { | |
592a252b | 10935 | /* VEX_W_0F3A15_P_2 */ |
9e30b8e0 | 10936 | { "vpextrw", { Edqw, XM, Ib } }, |
9e30b8e0 L |
10937 | }, |
10938 | { | |
592a252b | 10939 | /* VEX_W_0F3A18_P_2 */ |
9e30b8e0 | 10940 | { "vinsertf128", { XM, Vex256, EXxmm, Ib } }, |
9e30b8e0 L |
10941 | }, |
10942 | { | |
592a252b | 10943 | /* VEX_W_0F3A19_P_2 */ |
9e30b8e0 | 10944 | { "vextractf128", { EXxmm, XM, Ib } }, |
9e30b8e0 L |
10945 | }, |
10946 | { | |
592a252b | 10947 | /* VEX_W_0F3A20_P_2 */ |
9e30b8e0 | 10948 | { "vpinsrb", { XM, Vex128, Edqb, Ib } }, |
9e30b8e0 L |
10949 | }, |
10950 | { | |
592a252b | 10951 | /* VEX_W_0F3A21_P_2 */ |
9e30b8e0 | 10952 | { "vinsertps", { XM, Vex128, EXd, Ib } }, |
9e30b8e0 | 10953 | }, |
43234a1e L |
10954 | { |
10955 | /* VEX_W_0F3A30_P_2 */ | |
10956 | { Bad_Opcode }, | |
10957 | { "kshiftrw", { MaskG, MaskR, Ib } }, | |
10958 | }, | |
10959 | { | |
10960 | /* VEX_W_0F3A32_P_2 */ | |
10961 | { Bad_Opcode }, | |
10962 | { "kshiftlw", { MaskG, MaskR, Ib } }, | |
10963 | }, | |
6c30d220 L |
10964 | { |
10965 | /* VEX_W_0F3A38_P_2 */ | |
10966 | { "vinserti128", { XM, Vex256, EXxmm, Ib } }, | |
10967 | }, | |
10968 | { | |
10969 | /* VEX_W_0F3A39_P_2 */ | |
10970 | { "vextracti128", { EXxmm, XM, Ib } }, | |
10971 | }, | |
9e30b8e0 | 10972 | { |
592a252b | 10973 | /* VEX_W_0F3A40_P_2 */ |
9e30b8e0 | 10974 | { "vdpps", { XM, Vex, EXx, Ib } }, |
9e30b8e0 L |
10975 | }, |
10976 | { | |
592a252b | 10977 | /* VEX_W_0F3A41_P_2 */ |
9e30b8e0 | 10978 | { "vdppd", { XM, Vex128, EXx, Ib } }, |
9e30b8e0 L |
10979 | }, |
10980 | { | |
592a252b | 10981 | /* VEX_W_0F3A42_P_2 */ |
6c30d220 | 10982 | { "vmpsadbw", { XM, Vex, EXx, Ib } }, |
9e30b8e0 L |
10983 | }, |
10984 | { | |
592a252b | 10985 | /* VEX_W_0F3A44_P_2 */ |
9e30b8e0 | 10986 | { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } }, |
9e30b8e0 | 10987 | }, |
6c30d220 L |
10988 | { |
10989 | /* VEX_W_0F3A46_P_2 */ | |
10990 | { "vperm2i128", { XM, Vex256, EXx, Ib } }, | |
10991 | }, | |
a683cc34 | 10992 | { |
592a252b | 10993 | /* VEX_W_0F3A48_P_2 */ |
a683cc34 SP |
10994 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, |
10995 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, | |
10996 | }, | |
10997 | { | |
592a252b | 10998 | /* VEX_W_0F3A49_P_2 */ |
a683cc34 SP |
10999 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, |
11000 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, | |
11001 | }, | |
9e30b8e0 | 11002 | { |
592a252b | 11003 | /* VEX_W_0F3A4A_P_2 */ |
9e30b8e0 | 11004 | { "vblendvps", { XM, Vex, EXx, XMVexI4 } }, |
9e30b8e0 L |
11005 | }, |
11006 | { | |
592a252b | 11007 | /* VEX_W_0F3A4B_P_2 */ |
9e30b8e0 | 11008 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 } }, |
9e30b8e0 L |
11009 | }, |
11010 | { | |
592a252b | 11011 | /* VEX_W_0F3A4C_P_2 */ |
6c30d220 | 11012 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 } }, |
9e30b8e0 L |
11013 | }, |
11014 | { | |
592a252b | 11015 | /* VEX_W_0F3A60_P_2 */ |
9e30b8e0 | 11016 | { "vpcmpestrm", { XM, EXx, Ib } }, |
9e30b8e0 L |
11017 | }, |
11018 | { | |
592a252b | 11019 | /* VEX_W_0F3A61_P_2 */ |
9e30b8e0 | 11020 | { "vpcmpestri", { XM, EXx, Ib } }, |
9e30b8e0 L |
11021 | }, |
11022 | { | |
592a252b | 11023 | /* VEX_W_0F3A62_P_2 */ |
9e30b8e0 | 11024 | { "vpcmpistrm", { XM, EXx, Ib } }, |
9e30b8e0 L |
11025 | }, |
11026 | { | |
592a252b | 11027 | /* VEX_W_0F3A63_P_2 */ |
9e30b8e0 | 11028 | { "vpcmpistri", { XM, EXx, Ib } }, |
9e30b8e0 L |
11029 | }, |
11030 | { | |
592a252b | 11031 | /* VEX_W_0F3ADF_P_2 */ |
9e30b8e0 | 11032 | { "vaeskeygenassist", { XM, EXx, Ib } }, |
9e30b8e0 | 11033 | }, |
43234a1e L |
11034 | #define NEED_VEX_W_TABLE |
11035 | #include "i386-dis-evex.h" | |
11036 | #undef NEED_VEX_W_TABLE | |
9e30b8e0 L |
11037 | }; |
11038 | ||
11039 | static const struct dis386 mod_table[][2] = { | |
11040 | { | |
11041 | /* MOD_8D */ | |
11042 | { "leaS", { Gv, M } }, | |
9e30b8e0 | 11043 | }, |
42164a71 L |
11044 | { |
11045 | /* MOD_C6_REG_7 */ | |
11046 | { Bad_Opcode }, | |
11047 | { RM_TABLE (RM_C6_REG_7) }, | |
11048 | }, | |
11049 | { | |
11050 | /* MOD_C7_REG_7 */ | |
11051 | { Bad_Opcode }, | |
11052 | { RM_TABLE (RM_C7_REG_7) }, | |
11053 | }, | |
4a357820 MZ |
11054 | { |
11055 | /* MOD_FF_REG_3 */ | |
11056 | { "Jcall{T|}", { indirEp } }, | |
11057 | }, | |
11058 | { | |
11059 | /* MOD_FF_REG_5 */ | |
11060 | { "Jjmp{T|}", { indirEp } }, | |
11061 | }, | |
9e30b8e0 L |
11062 | { |
11063 | /* MOD_0F01_REG_0 */ | |
11064 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
11065 | { RM_TABLE (RM_0F01_REG_0) }, | |
11066 | }, | |
11067 | { | |
11068 | /* MOD_0F01_REG_1 */ | |
11069 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
11070 | { RM_TABLE (RM_0F01_REG_1) }, | |
11071 | }, | |
11072 | { | |
11073 | /* MOD_0F01_REG_2 */ | |
11074 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
11075 | { RM_TABLE (RM_0F01_REG_2) }, | |
11076 | }, | |
11077 | { | |
11078 | /* MOD_0F01_REG_3 */ | |
11079 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
11080 | { RM_TABLE (RM_0F01_REG_3) }, | |
11081 | }, | |
11082 | { | |
11083 | /* MOD_0F01_REG_7 */ | |
11084 | { "invlpg", { Mb } }, | |
11085 | { RM_TABLE (RM_0F01_REG_7) }, | |
11086 | }, | |
11087 | { | |
11088 | /* MOD_0F12_PREFIX_0 */ | |
11089 | { "movlps", { XM, EXq } }, | |
11090 | { "movhlps", { XM, EXq } }, | |
11091 | }, | |
11092 | { | |
11093 | /* MOD_0F13 */ | |
11094 | { "movlpX", { EXq, XM } }, | |
9e30b8e0 L |
11095 | }, |
11096 | { | |
11097 | /* MOD_0F16_PREFIX_0 */ | |
11098 | { "movhps", { XM, EXq } }, | |
11099 | { "movlhps", { XM, EXq } }, | |
11100 | }, | |
11101 | { | |
11102 | /* MOD_0F17 */ | |
11103 | { "movhpX", { EXq, XM } }, | |
9e30b8e0 L |
11104 | }, |
11105 | { | |
11106 | /* MOD_0F18_REG_0 */ | |
11107 | { "prefetchnta", { Mb } }, | |
9e30b8e0 L |
11108 | }, |
11109 | { | |
11110 | /* MOD_0F18_REG_1 */ | |
11111 | { "prefetcht0", { Mb } }, | |
9e30b8e0 L |
11112 | }, |
11113 | { | |
11114 | /* MOD_0F18_REG_2 */ | |
11115 | { "prefetcht1", { Mb } }, | |
9e30b8e0 L |
11116 | }, |
11117 | { | |
11118 | /* MOD_0F18_REG_3 */ | |
11119 | { "prefetcht2", { Mb } }, | |
9e30b8e0 | 11120 | }, |
d7189fa5 RM |
11121 | { |
11122 | /* MOD_0F18_REG_4 */ | |
11123 | { "nop/reserved", { Mb } }, | |
11124 | }, | |
11125 | { | |
11126 | /* MOD_0F18_REG_5 */ | |
11127 | { "nop/reserved", { Mb } }, | |
11128 | }, | |
11129 | { | |
11130 | /* MOD_0F18_REG_6 */ | |
11131 | { "nop/reserved", { Mb } }, | |
11132 | }, | |
11133 | { | |
11134 | /* MOD_0F18_REG_7 */ | |
11135 | { "nop/reserved", { Mb } }, | |
11136 | }, | |
7e8b059b L |
11137 | { |
11138 | /* MOD_0F1A_PREFIX_0 */ | |
11139 | { "bndldx", { Gbnd, Ev_bnd } }, | |
11140 | { "nopQ", { Ev } }, | |
11141 | }, | |
11142 | { | |
11143 | /* MOD_0F1B_PREFIX_0 */ | |
11144 | { "bndstx", { Ev_bnd, Gbnd } }, | |
11145 | { "nopQ", { Ev } }, | |
11146 | }, | |
11147 | { | |
11148 | /* MOD_0F1B_PREFIX_1 */ | |
11149 | { "bndmk", { Gbnd, Ev_bnd } }, | |
11150 | { "nopQ", { Ev } }, | |
11151 | }, | |
9e30b8e0 L |
11152 | { |
11153 | /* MOD_0F20 */ | |
592d1631 | 11154 | { Bad_Opcode }, |
9e30b8e0 L |
11155 | { "movZ", { Rm, Cm } }, |
11156 | }, | |
11157 | { | |
11158 | /* MOD_0F21 */ | |
592d1631 | 11159 | { Bad_Opcode }, |
9e30b8e0 L |
11160 | { "movZ", { Rm, Dm } }, |
11161 | }, | |
11162 | { | |
11163 | /* MOD_0F22 */ | |
592d1631 | 11164 | { Bad_Opcode }, |
9e30b8e0 | 11165 | { "movZ", { Cm, Rm } }, |
b844680a L |
11166 | }, |
11167 | { | |
92fddf8e | 11168 | /* MOD_0F23 */ |
592d1631 | 11169 | { Bad_Opcode }, |
92fddf8e | 11170 | { "movZ", { Dm, Rm } }, |
b844680a L |
11171 | }, |
11172 | { | |
92fddf8e | 11173 | /* MOD_0F24 */ |
7bb15c6f | 11174 | { Bad_Opcode }, |
92fddf8e | 11175 | { "movL", { Rd, Td } }, |
b844680a L |
11176 | }, |
11177 | { | |
92fddf8e | 11178 | /* MOD_0F26 */ |
592d1631 | 11179 | { Bad_Opcode }, |
92fddf8e | 11180 | { "movL", { Td, Rd } }, |
b844680a | 11181 | }, |
75c135a8 L |
11182 | { |
11183 | /* MOD_0F2B_PREFIX_0 */ | |
4ee52178 | 11184 | {"movntps", { Mx, XM } }, |
75c135a8 L |
11185 | }, |
11186 | { | |
11187 | /* MOD_0F2B_PREFIX_1 */ | |
4ee52178 | 11188 | {"movntss", { Md, XM } }, |
75c135a8 L |
11189 | }, |
11190 | { | |
11191 | /* MOD_0F2B_PREFIX_2 */ | |
4ee52178 | 11192 | {"movntpd", { Mx, XM } }, |
75c135a8 L |
11193 | }, |
11194 | { | |
11195 | /* MOD_0F2B_PREFIX_3 */ | |
4ee52178 | 11196 | {"movntsd", { Mq, XM } }, |
75c135a8 L |
11197 | }, |
11198 | { | |
11199 | /* MOD_0F51 */ | |
592d1631 | 11200 | { Bad_Opcode }, |
75c135a8 L |
11201 | { "movmskpX", { Gdq, XS } }, |
11202 | }, | |
b844680a | 11203 | { |
1ceb70f8 | 11204 | /* MOD_0F71_REG_2 */ |
592d1631 | 11205 | { Bad_Opcode }, |
4e7d34a6 | 11206 | { "psrlw", { MS, Ib } }, |
b844680a L |
11207 | }, |
11208 | { | |
1ceb70f8 | 11209 | /* MOD_0F71_REG_4 */ |
592d1631 | 11210 | { Bad_Opcode }, |
4e7d34a6 | 11211 | { "psraw", { MS, Ib } }, |
b844680a L |
11212 | }, |
11213 | { | |
1ceb70f8 | 11214 | /* MOD_0F71_REG_6 */ |
592d1631 | 11215 | { Bad_Opcode }, |
4e7d34a6 | 11216 | { "psllw", { MS, Ib } }, |
b844680a L |
11217 | }, |
11218 | { | |
1ceb70f8 | 11219 | /* MOD_0F72_REG_2 */ |
592d1631 | 11220 | { Bad_Opcode }, |
4e7d34a6 | 11221 | { "psrld", { MS, Ib } }, |
b844680a L |
11222 | }, |
11223 | { | |
1ceb70f8 | 11224 | /* MOD_0F72_REG_4 */ |
592d1631 | 11225 | { Bad_Opcode }, |
4e7d34a6 | 11226 | { "psrad", { MS, Ib } }, |
b844680a L |
11227 | }, |
11228 | { | |
1ceb70f8 | 11229 | /* MOD_0F72_REG_6 */ |
592d1631 | 11230 | { Bad_Opcode }, |
4e7d34a6 | 11231 | { "pslld", { MS, Ib } }, |
b844680a L |
11232 | }, |
11233 | { | |
1ceb70f8 | 11234 | /* MOD_0F73_REG_2 */ |
592d1631 | 11235 | { Bad_Opcode }, |
4e7d34a6 | 11236 | { "psrlq", { MS, Ib } }, |
b844680a L |
11237 | }, |
11238 | { | |
1ceb70f8 | 11239 | /* MOD_0F73_REG_3 */ |
592d1631 | 11240 | { Bad_Opcode }, |
c0f3af97 L |
11241 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
11242 | }, | |
11243 | { | |
11244 | /* MOD_0F73_REG_6 */ | |
592d1631 | 11245 | { Bad_Opcode }, |
c0f3af97 L |
11246 | { "psllq", { MS, Ib } }, |
11247 | }, | |
11248 | { | |
11249 | /* MOD_0F73_REG_7 */ | |
592d1631 | 11250 | { Bad_Opcode }, |
c0f3af97 L |
11251 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
11252 | }, | |
11253 | { | |
11254 | /* MOD_0FAE_REG_0 */ | |
eacc9c89 | 11255 | { "fxsave", { FXSAVE } }, |
c7b8aa3a | 11256 | { PREFIX_TABLE (PREFIX_0FAE_REG_0) }, |
c0f3af97 L |
11257 | }, |
11258 | { | |
11259 | /* MOD_0FAE_REG_1 */ | |
eacc9c89 | 11260 | { "fxrstor", { FXSAVE } }, |
c7b8aa3a | 11261 | { PREFIX_TABLE (PREFIX_0FAE_REG_1) }, |
c0f3af97 L |
11262 | }, |
11263 | { | |
11264 | /* MOD_0FAE_REG_2 */ | |
11265 | { "ldmxcsr", { Md } }, | |
c7b8aa3a | 11266 | { PREFIX_TABLE (PREFIX_0FAE_REG_2) }, |
c0f3af97 L |
11267 | }, |
11268 | { | |
11269 | /* MOD_0FAE_REG_3 */ | |
11270 | { "stmxcsr", { Md } }, | |
c7b8aa3a | 11271 | { PREFIX_TABLE (PREFIX_0FAE_REG_3) }, |
c0f3af97 L |
11272 | }, |
11273 | { | |
11274 | /* MOD_0FAE_REG_4 */ | |
73bb6729 | 11275 | { "xsave", { FXSAVE } }, |
c0f3af97 L |
11276 | }, |
11277 | { | |
11278 | /* MOD_0FAE_REG_5 */ | |
73bb6729 | 11279 | { "xrstor", { FXSAVE } }, |
c0f3af97 L |
11280 | { RM_TABLE (RM_0FAE_REG_5) }, |
11281 | }, | |
11282 | { | |
11283 | /* MOD_0FAE_REG_6 */ | |
c7b8aa3a | 11284 | { "xsaveopt", { FXSAVE } }, |
c0f3af97 L |
11285 | { RM_TABLE (RM_0FAE_REG_6) }, |
11286 | }, | |
11287 | { | |
11288 | /* MOD_0FAE_REG_7 */ | |
11289 | { "clflush", { Mb } }, | |
11290 | { RM_TABLE (RM_0FAE_REG_7) }, | |
11291 | }, | |
11292 | { | |
11293 | /* MOD_0FB2 */ | |
11294 | { "lssS", { Gv, Mp } }, | |
c0f3af97 L |
11295 | }, |
11296 | { | |
11297 | /* MOD_0FB4 */ | |
11298 | { "lfsS", { Gv, Mp } }, | |
c0f3af97 L |
11299 | }, |
11300 | { | |
11301 | /* MOD_0FB5 */ | |
11302 | { "lgsS", { Gv, Mp } }, | |
c0f3af97 L |
11303 | }, |
11304 | { | |
11305 | /* MOD_0FC7_REG_6 */ | |
11306 | { PREFIX_TABLE (PREFIX_0FC7_REG_6) }, | |
d7d9a9f8 | 11307 | { "rdrand", { Ev } }, |
c0f3af97 L |
11308 | }, |
11309 | { | |
11310 | /* MOD_0FC7_REG_7 */ | |
11311 | { "vmptrst", { Mq } }, | |
e2e1fcde | 11312 | { "rdseed", { Ev } }, |
c0f3af97 L |
11313 | }, |
11314 | { | |
11315 | /* MOD_0FD7 */ | |
592d1631 | 11316 | { Bad_Opcode }, |
c0f3af97 L |
11317 | { "pmovmskb", { Gdq, MS } }, |
11318 | }, | |
11319 | { | |
11320 | /* MOD_0FE7_PREFIX_2 */ | |
11321 | { "movntdq", { Mx, XM } }, | |
c0f3af97 L |
11322 | }, |
11323 | { | |
11324 | /* MOD_0FF0_PREFIX_3 */ | |
11325 | { "lddqu", { XM, M } }, | |
c0f3af97 L |
11326 | }, |
11327 | { | |
11328 | /* MOD_0F382A_PREFIX_2 */ | |
11329 | { "movntdqa", { XM, Mx } }, | |
c0f3af97 L |
11330 | }, |
11331 | { | |
11332 | /* MOD_62_32BIT */ | |
11333 | { "bound{S|}", { Gv, Ma } }, | |
43234a1e | 11334 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
11335 | }, |
11336 | { | |
11337 | /* MOD_C4_32BIT */ | |
11338 | { "lesS", { Gv, Mp } }, | |
11339 | { VEX_C4_TABLE (VEX_0F) }, | |
11340 | }, | |
11341 | { | |
11342 | /* MOD_C5_32BIT */ | |
11343 | { "ldsS", { Gv, Mp } }, | |
11344 | { VEX_C5_TABLE (VEX_0F) }, | |
11345 | }, | |
11346 | { | |
592a252b L |
11347 | /* MOD_VEX_0F12_PREFIX_0 */ |
11348 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, | |
11349 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, | |
c0f3af97 L |
11350 | }, |
11351 | { | |
592a252b L |
11352 | /* MOD_VEX_0F13 */ |
11353 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, | |
c0f3af97 L |
11354 | }, |
11355 | { | |
592a252b L |
11356 | /* MOD_VEX_0F16_PREFIX_0 */ |
11357 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, | |
11358 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, | |
c0f3af97 L |
11359 | }, |
11360 | { | |
592a252b L |
11361 | /* MOD_VEX_0F17 */ |
11362 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, | |
c0f3af97 L |
11363 | }, |
11364 | { | |
592a252b L |
11365 | /* MOD_VEX_0F2B */ |
11366 | { VEX_W_TABLE (VEX_W_0F2B_M_0) }, | |
c0f3af97 L |
11367 | }, |
11368 | { | |
592a252b | 11369 | /* MOD_VEX_0F50 */ |
592d1631 | 11370 | { Bad_Opcode }, |
592a252b | 11371 | { VEX_W_TABLE (VEX_W_0F50_M_0) }, |
c0f3af97 L |
11372 | }, |
11373 | { | |
592a252b | 11374 | /* MOD_VEX_0F71_REG_2 */ |
592d1631 | 11375 | { Bad_Opcode }, |
592a252b | 11376 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, |
b844680a L |
11377 | }, |
11378 | { | |
592a252b | 11379 | /* MOD_VEX_0F71_REG_4 */ |
592d1631 | 11380 | { Bad_Opcode }, |
592a252b | 11381 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, |
b844680a L |
11382 | }, |
11383 | { | |
592a252b | 11384 | /* MOD_VEX_0F71_REG_6 */ |
592d1631 | 11385 | { Bad_Opcode }, |
592a252b | 11386 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, |
b844680a L |
11387 | }, |
11388 | { | |
592a252b | 11389 | /* MOD_VEX_0F72_REG_2 */ |
592d1631 | 11390 | { Bad_Opcode }, |
592a252b | 11391 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, |
b844680a | 11392 | }, |
d8faab4e | 11393 | { |
592a252b | 11394 | /* MOD_VEX_0F72_REG_4 */ |
592d1631 | 11395 | { Bad_Opcode }, |
592a252b | 11396 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, |
d8faab4e L |
11397 | }, |
11398 | { | |
592a252b | 11399 | /* MOD_VEX_0F72_REG_6 */ |
592d1631 | 11400 | { Bad_Opcode }, |
592a252b | 11401 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, |
d8faab4e | 11402 | }, |
876d4bfa | 11403 | { |
592a252b | 11404 | /* MOD_VEX_0F73_REG_2 */ |
592d1631 | 11405 | { Bad_Opcode }, |
592a252b | 11406 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, |
876d4bfa L |
11407 | }, |
11408 | { | |
592a252b | 11409 | /* MOD_VEX_0F73_REG_3 */ |
592d1631 | 11410 | { Bad_Opcode }, |
592a252b | 11411 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, |
475a2301 L |
11412 | }, |
11413 | { | |
592a252b | 11414 | /* MOD_VEX_0F73_REG_6 */ |
592d1631 | 11415 | { Bad_Opcode }, |
592a252b | 11416 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, |
876d4bfa L |
11417 | }, |
11418 | { | |
592a252b | 11419 | /* MOD_VEX_0F73_REG_7 */ |
592d1631 | 11420 | { Bad_Opcode }, |
592a252b | 11421 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, |
876d4bfa L |
11422 | }, |
11423 | { | |
592a252b L |
11424 | /* MOD_VEX_0FAE_REG_2 */ |
11425 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, | |
876d4bfa | 11426 | }, |
bbedc832 | 11427 | { |
592a252b L |
11428 | /* MOD_VEX_0FAE_REG_3 */ |
11429 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, | |
bbedc832 | 11430 | }, |
144c41d9 | 11431 | { |
592a252b | 11432 | /* MOD_VEX_0FD7_PREFIX_2 */ |
592d1631 | 11433 | { Bad_Opcode }, |
6c30d220 | 11434 | { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) }, |
144c41d9 | 11435 | }, |
1afd85e3 | 11436 | { |
592a252b L |
11437 | /* MOD_VEX_0FE7_PREFIX_2 */ |
11438 | { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) }, | |
1afd85e3 L |
11439 | }, |
11440 | { | |
592a252b L |
11441 | /* MOD_VEX_0FF0_PREFIX_3 */ |
11442 | { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) }, | |
92fddf8e | 11443 | }, |
75c135a8 | 11444 | { |
592a252b L |
11445 | /* MOD_VEX_0F381A_PREFIX_2 */ |
11446 | { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, | |
75c135a8 | 11447 | }, |
1afd85e3 | 11448 | { |
592a252b | 11449 | /* MOD_VEX_0F382A_PREFIX_2 */ |
6c30d220 | 11450 | { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) }, |
1afd85e3 | 11451 | }, |
75c135a8 | 11452 | { |
592a252b L |
11453 | /* MOD_VEX_0F382C_PREFIX_2 */ |
11454 | { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, | |
75c135a8 | 11455 | }, |
1afd85e3 | 11456 | { |
592a252b L |
11457 | /* MOD_VEX_0F382D_PREFIX_2 */ |
11458 | { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, | |
1afd85e3 L |
11459 | }, |
11460 | { | |
592a252b L |
11461 | /* MOD_VEX_0F382E_PREFIX_2 */ |
11462 | { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, | |
1afd85e3 L |
11463 | }, |
11464 | { | |
592a252b L |
11465 | /* MOD_VEX_0F382F_PREFIX_2 */ |
11466 | { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, | |
1afd85e3 | 11467 | }, |
6c30d220 L |
11468 | { |
11469 | /* MOD_VEX_0F385A_PREFIX_2 */ | |
11470 | { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, | |
11471 | }, | |
11472 | { | |
11473 | /* MOD_VEX_0F388C_PREFIX_2 */ | |
11474 | { "vpmaskmov%LW", { XM, Vex, Mx } }, | |
11475 | }, | |
11476 | { | |
11477 | /* MOD_VEX_0F388E_PREFIX_2 */ | |
11478 | { "vpmaskmov%LW", { Mx, Vex, XM } }, | |
11479 | }, | |
43234a1e L |
11480 | #define NEED_MOD_TABLE |
11481 | #include "i386-dis-evex.h" | |
11482 | #undef NEED_MOD_TABLE | |
b844680a L |
11483 | }; |
11484 | ||
1ceb70f8 | 11485 | static const struct dis386 rm_table[][8] = { |
42164a71 L |
11486 | { |
11487 | /* RM_C6_REG_7 */ | |
11488 | { "xabort", { Skip_MODRM, Ib } }, | |
11489 | }, | |
11490 | { | |
11491 | /* RM_C7_REG_7 */ | |
11492 | { "xbeginT", { Skip_MODRM, Jv } }, | |
11493 | }, | |
b844680a | 11494 | { |
1ceb70f8 | 11495 | /* RM_0F01_REG_0 */ |
592d1631 | 11496 | { Bad_Opcode }, |
b844680a L |
11497 | { "vmcall", { Skip_MODRM } }, |
11498 | { "vmlaunch", { Skip_MODRM } }, | |
11499 | { "vmresume", { Skip_MODRM } }, | |
11500 | { "vmxoff", { Skip_MODRM } }, | |
b844680a L |
11501 | }, |
11502 | { | |
1ceb70f8 | 11503 | /* RM_0F01_REG_1 */ |
b844680a L |
11504 | { "monitor", { { OP_Monitor, 0 } } }, |
11505 | { "mwait", { { OP_Mwait, 0 } } }, | |
5c111e37 L |
11506 | { "clac", { Skip_MODRM } }, |
11507 | { "stac", { Skip_MODRM } }, | |
b844680a | 11508 | }, |
475a2301 L |
11509 | { |
11510 | /* RM_0F01_REG_2 */ | |
11511 | { "xgetbv", { Skip_MODRM } }, | |
11512 | { "xsetbv", { Skip_MODRM } }, | |
8729a6f6 L |
11513 | { Bad_Opcode }, |
11514 | { Bad_Opcode }, | |
11515 | { "vmfunc", { Skip_MODRM } }, | |
42164a71 L |
11516 | { "xend", { Skip_MODRM } }, |
11517 | { "xtest", { Skip_MODRM } }, | |
11518 | { Bad_Opcode }, | |
475a2301 | 11519 | }, |
b844680a | 11520 | { |
1ceb70f8 | 11521 | /* RM_0F01_REG_3 */ |
4e7d34a6 L |
11522 | { "vmrun", { Skip_MODRM } }, |
11523 | { "vmmcall", { Skip_MODRM } }, | |
11524 | { "vmload", { Skip_MODRM } }, | |
11525 | { "vmsave", { Skip_MODRM } }, | |
11526 | { "stgi", { Skip_MODRM } }, | |
11527 | { "clgi", { Skip_MODRM } }, | |
11528 | { "skinit", { Skip_MODRM } }, | |
11529 | { "invlpga", { Skip_MODRM } }, | |
11530 | }, | |
11531 | { | |
1ceb70f8 | 11532 | /* RM_0F01_REG_7 */ |
4e7d34a6 L |
11533 | { "swapgs", { Skip_MODRM } }, |
11534 | { "rdtscp", { Skip_MODRM } }, | |
b844680a L |
11535 | }, |
11536 | { | |
1ceb70f8 | 11537 | /* RM_0FAE_REG_5 */ |
4e7d34a6 | 11538 | { "lfence", { Skip_MODRM } }, |
b844680a L |
11539 | }, |
11540 | { | |
1ceb70f8 | 11541 | /* RM_0FAE_REG_6 */ |
4e7d34a6 | 11542 | { "mfence", { Skip_MODRM } }, |
b844680a | 11543 | }, |
bbedc832 | 11544 | { |
1ceb70f8 | 11545 | /* RM_0FAE_REG_7 */ |
4e7d34a6 | 11546 | { "sfence", { Skip_MODRM } }, |
144c41d9 | 11547 | }, |
b844680a L |
11548 | }; |
11549 | ||
c608c12e AM |
11550 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
11551 | ||
f16cd0d5 L |
11552 | /* We use the high bit to indicate different name for the same |
11553 | prefix. */ | |
11554 | #define ADDR16_PREFIX (0x67 | 0x100) | |
11555 | #define ADDR32_PREFIX (0x67 | 0x200) | |
11556 | #define DATA16_PREFIX (0x66 | 0x100) | |
11557 | #define DATA32_PREFIX (0x66 | 0x200) | |
11558 | #define REP_PREFIX (0xf3 | 0x100) | |
42164a71 L |
11559 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
11560 | #define XRELEASE_PREFIX (0xf3 | 0x400) | |
7e8b059b | 11561 | #define BND_PREFIX (0xf2 | 0x400) |
f16cd0d5 L |
11562 | |
11563 | static int | |
26ca5450 | 11564 | ckprefix (void) |
252b5132 | 11565 | { |
f16cd0d5 | 11566 | int newrex, i, length; |
52b15da3 | 11567 | rex = 0; |
c0f3af97 | 11568 | rex_ignored = 0; |
252b5132 | 11569 | prefixes = 0; |
7d421014 | 11570 | used_prefixes = 0; |
52b15da3 | 11571 | rex_used = 0; |
f16cd0d5 L |
11572 | last_lock_prefix = -1; |
11573 | last_repz_prefix = -1; | |
11574 | last_repnz_prefix = -1; | |
11575 | last_data_prefix = -1; | |
11576 | last_addr_prefix = -1; | |
11577 | last_rex_prefix = -1; | |
11578 | last_seg_prefix = -1; | |
f310f33d L |
11579 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
11580 | all_prefixes[i] = 0; | |
11581 | i = 0; | |
f16cd0d5 L |
11582 | length = 0; |
11583 | /* The maximum instruction length is 15bytes. */ | |
11584 | while (length < MAX_CODE_LENGTH - 1) | |
252b5132 RH |
11585 | { |
11586 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 11587 | newrex = 0; |
252b5132 RH |
11588 | switch (*codep) |
11589 | { | |
52b15da3 JH |
11590 | /* REX prefixes family. */ |
11591 | case 0x40: | |
11592 | case 0x41: | |
11593 | case 0x42: | |
11594 | case 0x43: | |
11595 | case 0x44: | |
11596 | case 0x45: | |
11597 | case 0x46: | |
11598 | case 0x47: | |
11599 | case 0x48: | |
11600 | case 0x49: | |
11601 | case 0x4a: | |
11602 | case 0x4b: | |
11603 | case 0x4c: | |
11604 | case 0x4d: | |
11605 | case 0x4e: | |
11606 | case 0x4f: | |
f16cd0d5 L |
11607 | if (address_mode == mode_64bit) |
11608 | newrex = *codep; | |
11609 | else | |
11610 | return 1; | |
11611 | last_rex_prefix = i; | |
52b15da3 | 11612 | break; |
252b5132 RH |
11613 | case 0xf3: |
11614 | prefixes |= PREFIX_REPZ; | |
f16cd0d5 | 11615 | last_repz_prefix = i; |
252b5132 RH |
11616 | break; |
11617 | case 0xf2: | |
11618 | prefixes |= PREFIX_REPNZ; | |
f16cd0d5 | 11619 | last_repnz_prefix = i; |
252b5132 RH |
11620 | break; |
11621 | case 0xf0: | |
11622 | prefixes |= PREFIX_LOCK; | |
f16cd0d5 | 11623 | last_lock_prefix = i; |
252b5132 RH |
11624 | break; |
11625 | case 0x2e: | |
11626 | prefixes |= PREFIX_CS; | |
f16cd0d5 | 11627 | last_seg_prefix = i; |
252b5132 RH |
11628 | break; |
11629 | case 0x36: | |
11630 | prefixes |= PREFIX_SS; | |
f16cd0d5 | 11631 | last_seg_prefix = i; |
252b5132 RH |
11632 | break; |
11633 | case 0x3e: | |
11634 | prefixes |= PREFIX_DS; | |
f16cd0d5 | 11635 | last_seg_prefix = i; |
252b5132 RH |
11636 | break; |
11637 | case 0x26: | |
11638 | prefixes |= PREFIX_ES; | |
f16cd0d5 | 11639 | last_seg_prefix = i; |
252b5132 RH |
11640 | break; |
11641 | case 0x64: | |
11642 | prefixes |= PREFIX_FS; | |
f16cd0d5 | 11643 | last_seg_prefix = i; |
252b5132 RH |
11644 | break; |
11645 | case 0x65: | |
11646 | prefixes |= PREFIX_GS; | |
f16cd0d5 | 11647 | last_seg_prefix = i; |
252b5132 RH |
11648 | break; |
11649 | case 0x66: | |
11650 | prefixes |= PREFIX_DATA; | |
f16cd0d5 | 11651 | last_data_prefix = i; |
252b5132 RH |
11652 | break; |
11653 | case 0x67: | |
11654 | prefixes |= PREFIX_ADDR; | |
f16cd0d5 | 11655 | last_addr_prefix = i; |
252b5132 | 11656 | break; |
5076851f | 11657 | case FWAIT_OPCODE: |
252b5132 RH |
11658 | /* fwait is really an instruction. If there are prefixes |
11659 | before the fwait, they belong to the fwait, *not* to the | |
11660 | following instruction. */ | |
3e7d61b2 | 11661 | if (prefixes || rex) |
252b5132 RH |
11662 | { |
11663 | prefixes |= PREFIX_FWAIT; | |
11664 | codep++; | |
6c067bbb RM |
11665 | /* This ensures that the previous REX prefixes are noticed |
11666 | as unused prefixes, as in the return case below. */ | |
11667 | rex_used = rex; | |
f16cd0d5 | 11668 | return 1; |
252b5132 RH |
11669 | } |
11670 | prefixes = PREFIX_FWAIT; | |
11671 | break; | |
11672 | default: | |
f16cd0d5 | 11673 | return 1; |
252b5132 | 11674 | } |
52b15da3 JH |
11675 | /* Rex is ignored when followed by another prefix. */ |
11676 | if (rex) | |
11677 | { | |
3e7d61b2 | 11678 | rex_used = rex; |
f16cd0d5 | 11679 | return 1; |
52b15da3 | 11680 | } |
f16cd0d5 L |
11681 | if (*codep != FWAIT_OPCODE) |
11682 | all_prefixes[i++] = *codep; | |
52b15da3 | 11683 | rex = newrex; |
252b5132 | 11684 | codep++; |
f16cd0d5 L |
11685 | length++; |
11686 | } | |
11687 | return 0; | |
11688 | } | |
11689 | ||
11690 | static int | |
11691 | seg_prefix (int pref) | |
11692 | { | |
11693 | switch (pref) | |
11694 | { | |
11695 | case 0x2e: | |
11696 | return PREFIX_CS; | |
11697 | case 0x36: | |
11698 | return PREFIX_SS; | |
11699 | case 0x3e: | |
11700 | return PREFIX_DS; | |
11701 | case 0x26: | |
11702 | return PREFIX_ES; | |
11703 | case 0x64: | |
11704 | return PREFIX_FS; | |
11705 | case 0x65: | |
11706 | return PREFIX_GS; | |
11707 | default: | |
11708 | return 0; | |
252b5132 RH |
11709 | } |
11710 | } | |
11711 | ||
7d421014 ILT |
11712 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
11713 | prefix byte. */ | |
11714 | ||
11715 | static const char * | |
26ca5450 | 11716 | prefix_name (int pref, int sizeflag) |
7d421014 | 11717 | { |
0003779b L |
11718 | static const char *rexes [16] = |
11719 | { | |
11720 | "rex", /* 0x40 */ | |
11721 | "rex.B", /* 0x41 */ | |
11722 | "rex.X", /* 0x42 */ | |
11723 | "rex.XB", /* 0x43 */ | |
11724 | "rex.R", /* 0x44 */ | |
11725 | "rex.RB", /* 0x45 */ | |
11726 | "rex.RX", /* 0x46 */ | |
11727 | "rex.RXB", /* 0x47 */ | |
11728 | "rex.W", /* 0x48 */ | |
11729 | "rex.WB", /* 0x49 */ | |
11730 | "rex.WX", /* 0x4a */ | |
11731 | "rex.WXB", /* 0x4b */ | |
11732 | "rex.WR", /* 0x4c */ | |
11733 | "rex.WRB", /* 0x4d */ | |
11734 | "rex.WRX", /* 0x4e */ | |
11735 | "rex.WRXB", /* 0x4f */ | |
11736 | }; | |
11737 | ||
7d421014 ILT |
11738 | switch (pref) |
11739 | { | |
52b15da3 JH |
11740 | /* REX prefixes family. */ |
11741 | case 0x40: | |
52b15da3 | 11742 | case 0x41: |
52b15da3 | 11743 | case 0x42: |
52b15da3 | 11744 | case 0x43: |
52b15da3 | 11745 | case 0x44: |
52b15da3 | 11746 | case 0x45: |
52b15da3 | 11747 | case 0x46: |
52b15da3 | 11748 | case 0x47: |
52b15da3 | 11749 | case 0x48: |
52b15da3 | 11750 | case 0x49: |
52b15da3 | 11751 | case 0x4a: |
52b15da3 | 11752 | case 0x4b: |
52b15da3 | 11753 | case 0x4c: |
52b15da3 | 11754 | case 0x4d: |
52b15da3 | 11755 | case 0x4e: |
52b15da3 | 11756 | case 0x4f: |
0003779b | 11757 | return rexes [pref - 0x40]; |
7d421014 ILT |
11758 | case 0xf3: |
11759 | return "repz"; | |
11760 | case 0xf2: | |
11761 | return "repnz"; | |
11762 | case 0xf0: | |
11763 | return "lock"; | |
11764 | case 0x2e: | |
11765 | return "cs"; | |
11766 | case 0x36: | |
11767 | return "ss"; | |
11768 | case 0x3e: | |
11769 | return "ds"; | |
11770 | case 0x26: | |
11771 | return "es"; | |
11772 | case 0x64: | |
11773 | return "fs"; | |
11774 | case 0x65: | |
11775 | return "gs"; | |
11776 | case 0x66: | |
11777 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
11778 | case 0x67: | |
cb712a9e | 11779 | if (address_mode == mode_64bit) |
db6eb5be | 11780 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 11781 | else |
2888cb7a | 11782 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
11783 | case FWAIT_OPCODE: |
11784 | return "fwait"; | |
f16cd0d5 L |
11785 | case ADDR16_PREFIX: |
11786 | return "addr16"; | |
11787 | case ADDR32_PREFIX: | |
11788 | return "addr32"; | |
11789 | case DATA16_PREFIX: | |
11790 | return "data16"; | |
11791 | case DATA32_PREFIX: | |
11792 | return "data32"; | |
11793 | case REP_PREFIX: | |
11794 | return "rep"; | |
42164a71 L |
11795 | case XACQUIRE_PREFIX: |
11796 | return "xacquire"; | |
11797 | case XRELEASE_PREFIX: | |
11798 | return "xrelease"; | |
7e8b059b L |
11799 | case BND_PREFIX: |
11800 | return "bnd"; | |
7d421014 ILT |
11801 | default: |
11802 | return NULL; | |
11803 | } | |
11804 | } | |
11805 | ||
ce518a5f L |
11806 | static char op_out[MAX_OPERANDS][100]; |
11807 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 11808 | static int two_source_ops; |
ce518a5f L |
11809 | static bfd_vma op_address[MAX_OPERANDS]; |
11810 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 11811 | static bfd_vma start_pc; |
ce518a5f | 11812 | |
252b5132 RH |
11813 | /* |
11814 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
11815 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
11816 | * section of the "Virtual 8086 Mode" chapter.) | |
11817 | * 'pc' should be the address of this instruction, it will | |
11818 | * be used to print the target address if this is a relative jump or call | |
11819 | * The function returns the length of this instruction in bytes. | |
11820 | */ | |
11821 | ||
252b5132 | 11822 | static char intel_syntax; |
9d141669 | 11823 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
11824 | static char open_char; |
11825 | static char close_char; | |
11826 | static char separator_char; | |
11827 | static char scale_char; | |
11828 | ||
e396998b AM |
11829 | /* Here for backwards compatibility. When gdb stops using |
11830 | print_insn_i386_att and print_insn_i386_intel these functions can | |
11831 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 11832 | int |
26ca5450 | 11833 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
11834 | { |
11835 | intel_syntax = 0; | |
e396998b AM |
11836 | |
11837 | return print_insn (pc, info); | |
252b5132 RH |
11838 | } |
11839 | ||
11840 | int | |
26ca5450 | 11841 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
11842 | { |
11843 | intel_syntax = 1; | |
e396998b AM |
11844 | |
11845 | return print_insn (pc, info); | |
252b5132 RH |
11846 | } |
11847 | ||
e396998b | 11848 | int |
26ca5450 | 11849 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
11850 | { |
11851 | intel_syntax = -1; | |
11852 | ||
11853 | return print_insn (pc, info); | |
11854 | } | |
11855 | ||
f59a29b9 L |
11856 | void |
11857 | print_i386_disassembler_options (FILE *stream) | |
11858 | { | |
11859 | fprintf (stream, _("\n\ | |
11860 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
11861 | with the -M switch (multiple options should be separated by commas):\n")); | |
11862 | ||
11863 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
11864 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
11865 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
11866 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
11867 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
11868 | fprintf (stream, _(" att-mnemonic\n" |
11869 | " Display instruction in AT&T mnemonic\n")); | |
11870 | fprintf (stream, _(" intel-mnemonic\n" | |
11871 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
11872 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
11873 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
11874 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
11875 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
11876 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
11877 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
11878 | } | |
11879 | ||
592d1631 L |
11880 | /* Bad opcode. */ |
11881 | static const struct dis386 bad_opcode = { "(bad)", { XX } }; | |
11882 | ||
b844680a L |
11883 | /* Get a pointer to struct dis386 with a valid name. */ |
11884 | ||
11885 | static const struct dis386 * | |
8bb15339 | 11886 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a | 11887 | { |
91d6fa6a | 11888 | int vindex, vex_table_index; |
b844680a L |
11889 | |
11890 | if (dp->name != NULL) | |
11891 | return dp; | |
11892 | ||
11893 | switch (dp->op[0].bytemode) | |
11894 | { | |
1ceb70f8 L |
11895 | case USE_REG_TABLE: |
11896 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
11897 | break; | |
11898 | ||
11899 | case USE_MOD_TABLE: | |
91d6fa6a NC |
11900 | vindex = modrm.mod == 0x3 ? 1 : 0; |
11901 | dp = &mod_table[dp->op[1].bytemode][vindex]; | |
1ceb70f8 L |
11902 | break; |
11903 | ||
11904 | case USE_RM_TABLE: | |
11905 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
11906 | break; |
11907 | ||
4e7d34a6 | 11908 | case USE_PREFIX_TABLE: |
c0f3af97 | 11909 | if (need_vex) |
b844680a | 11910 | { |
c0f3af97 L |
11911 | /* The prefix in VEX is implicit. */ |
11912 | switch (vex.prefix) | |
11913 | { | |
11914 | case 0: | |
91d6fa6a | 11915 | vindex = 0; |
c0f3af97 L |
11916 | break; |
11917 | case REPE_PREFIX_OPCODE: | |
91d6fa6a | 11918 | vindex = 1; |
c0f3af97 L |
11919 | break; |
11920 | case DATA_PREFIX_OPCODE: | |
91d6fa6a | 11921 | vindex = 2; |
c0f3af97 L |
11922 | break; |
11923 | case REPNE_PREFIX_OPCODE: | |
91d6fa6a | 11924 | vindex = 3; |
c0f3af97 L |
11925 | break; |
11926 | default: | |
11927 | abort (); | |
11928 | break; | |
11929 | } | |
b844680a | 11930 | } |
7bb15c6f | 11931 | else |
b844680a | 11932 | { |
91d6fa6a | 11933 | vindex = 0; |
c0f3af97 L |
11934 | used_prefixes |= (prefixes & PREFIX_REPZ); |
11935 | if (prefixes & PREFIX_REPZ) | |
b844680a | 11936 | { |
91d6fa6a | 11937 | vindex = 1; |
f16cd0d5 | 11938 | all_prefixes[last_repz_prefix] = 0; |
b844680a L |
11939 | } |
11940 | else | |
11941 | { | |
c0f3af97 L |
11942 | /* We should check PREFIX_REPNZ and PREFIX_REPZ before |
11943 | PREFIX_DATA. */ | |
11944 | used_prefixes |= (prefixes & PREFIX_REPNZ); | |
11945 | if (prefixes & PREFIX_REPNZ) | |
11946 | { | |
91d6fa6a | 11947 | vindex = 3; |
f16cd0d5 | 11948 | all_prefixes[last_repnz_prefix] = 0; |
c0f3af97 L |
11949 | } |
11950 | else | |
b844680a | 11951 | { |
c0f3af97 L |
11952 | used_prefixes |= (prefixes & PREFIX_DATA); |
11953 | if (prefixes & PREFIX_DATA) | |
11954 | { | |
91d6fa6a | 11955 | vindex = 2; |
f16cd0d5 | 11956 | all_prefixes[last_data_prefix] = 0; |
c0f3af97 | 11957 | } |
b844680a L |
11958 | } |
11959 | } | |
11960 | } | |
91d6fa6a | 11961 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
b844680a L |
11962 | break; |
11963 | ||
4e7d34a6 | 11964 | case USE_X86_64_TABLE: |
91d6fa6a NC |
11965 | vindex = address_mode == mode_64bit ? 1 : 0; |
11966 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; | |
b844680a L |
11967 | break; |
11968 | ||
4e7d34a6 | 11969 | case USE_3BYTE_TABLE: |
8bb15339 | 11970 | FETCH_DATA (info, codep + 2); |
91d6fa6a NC |
11971 | vindex = *codep++; |
11972 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; | |
8bb15339 L |
11973 | modrm.mod = (*codep >> 6) & 3; |
11974 | modrm.reg = (*codep >> 3) & 7; | |
11975 | modrm.rm = *codep & 7; | |
11976 | break; | |
11977 | ||
c0f3af97 L |
11978 | case USE_VEX_LEN_TABLE: |
11979 | if (!need_vex) | |
11980 | abort (); | |
11981 | ||
11982 | switch (vex.length) | |
11983 | { | |
11984 | case 128: | |
91d6fa6a | 11985 | vindex = 0; |
c0f3af97 L |
11986 | break; |
11987 | case 256: | |
91d6fa6a | 11988 | vindex = 1; |
c0f3af97 L |
11989 | break; |
11990 | default: | |
11991 | abort (); | |
11992 | break; | |
11993 | } | |
11994 | ||
91d6fa6a | 11995 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
c0f3af97 L |
11996 | break; |
11997 | ||
f88c9eb0 SP |
11998 | case USE_XOP_8F_TABLE: |
11999 | FETCH_DATA (info, codep + 3); | |
12000 | /* All bits in the REX prefix are ignored. */ | |
12001 | rex_ignored = rex; | |
12002 | rex = ~(*codep >> 5) & 0x7; | |
12003 | ||
12004 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ | |
12005 | switch ((*codep & 0x1f)) | |
12006 | { | |
12007 | default: | |
f07af43e L |
12008 | dp = &bad_opcode; |
12009 | return dp; | |
5dd85c99 SP |
12010 | case 0x8: |
12011 | vex_table_index = XOP_08; | |
12012 | break; | |
f88c9eb0 SP |
12013 | case 0x9: |
12014 | vex_table_index = XOP_09; | |
12015 | break; | |
12016 | case 0xa: | |
12017 | vex_table_index = XOP_0A; | |
12018 | break; | |
12019 | } | |
12020 | codep++; | |
12021 | vex.w = *codep & 0x80; | |
12022 | if (vex.w && address_mode == mode_64bit) | |
12023 | rex |= REX_W; | |
12024 | ||
12025 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
12026 | if (address_mode != mode_64bit | |
12027 | && vex.register_specifier > 0x7) | |
f07af43e L |
12028 | { |
12029 | dp = &bad_opcode; | |
12030 | return dp; | |
12031 | } | |
f88c9eb0 SP |
12032 | |
12033 | vex.length = (*codep & 0x4) ? 256 : 128; | |
12034 | switch ((*codep & 0x3)) | |
12035 | { | |
12036 | case 0: | |
12037 | vex.prefix = 0; | |
12038 | break; | |
12039 | case 1: | |
12040 | vex.prefix = DATA_PREFIX_OPCODE; | |
12041 | break; | |
12042 | case 2: | |
12043 | vex.prefix = REPE_PREFIX_OPCODE; | |
12044 | break; | |
12045 | case 3: | |
12046 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12047 | break; | |
12048 | } | |
12049 | need_vex = 1; | |
12050 | need_vex_reg = 1; | |
12051 | codep++; | |
91d6fa6a NC |
12052 | vindex = *codep++; |
12053 | dp = &xop_table[vex_table_index][vindex]; | |
c48244a5 SP |
12054 | |
12055 | FETCH_DATA (info, codep + 1); | |
12056 | modrm.mod = (*codep >> 6) & 3; | |
12057 | modrm.reg = (*codep >> 3) & 7; | |
12058 | modrm.rm = *codep & 7; | |
f88c9eb0 SP |
12059 | break; |
12060 | ||
c0f3af97 | 12061 | case USE_VEX_C4_TABLE: |
43234a1e | 12062 | /* VEX prefix. */ |
c0f3af97 L |
12063 | FETCH_DATA (info, codep + 3); |
12064 | /* All bits in the REX prefix are ignored. */ | |
12065 | rex_ignored = rex; | |
12066 | rex = ~(*codep >> 5) & 0x7; | |
12067 | switch ((*codep & 0x1f)) | |
12068 | { | |
12069 | default: | |
f07af43e L |
12070 | dp = &bad_opcode; |
12071 | return dp; | |
c0f3af97 | 12072 | case 0x1: |
f88c9eb0 | 12073 | vex_table_index = VEX_0F; |
c0f3af97 L |
12074 | break; |
12075 | case 0x2: | |
f88c9eb0 | 12076 | vex_table_index = VEX_0F38; |
c0f3af97 L |
12077 | break; |
12078 | case 0x3: | |
f88c9eb0 | 12079 | vex_table_index = VEX_0F3A; |
c0f3af97 L |
12080 | break; |
12081 | } | |
12082 | codep++; | |
12083 | vex.w = *codep & 0x80; | |
12084 | if (vex.w && address_mode == mode_64bit) | |
12085 | rex |= REX_W; | |
12086 | ||
12087 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
12088 | if (address_mode != mode_64bit | |
12089 | && vex.register_specifier > 0x7) | |
f07af43e L |
12090 | { |
12091 | dp = &bad_opcode; | |
12092 | return dp; | |
12093 | } | |
c0f3af97 L |
12094 | |
12095 | vex.length = (*codep & 0x4) ? 256 : 128; | |
12096 | switch ((*codep & 0x3)) | |
12097 | { | |
12098 | case 0: | |
12099 | vex.prefix = 0; | |
12100 | break; | |
12101 | case 1: | |
12102 | vex.prefix = DATA_PREFIX_OPCODE; | |
12103 | break; | |
12104 | case 2: | |
12105 | vex.prefix = REPE_PREFIX_OPCODE; | |
12106 | break; | |
12107 | case 3: | |
12108 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12109 | break; | |
12110 | } | |
12111 | need_vex = 1; | |
12112 | need_vex_reg = 1; | |
12113 | codep++; | |
91d6fa6a NC |
12114 | vindex = *codep++; |
12115 | dp = &vex_table[vex_table_index][vindex]; | |
c0f3af97 | 12116 | /* There is no MODRM byte for VEX [82|77]. */ |
91d6fa6a | 12117 | if (vindex != 0x77 && vindex != 0x82) |
c0f3af97 L |
12118 | { |
12119 | FETCH_DATA (info, codep + 1); | |
12120 | modrm.mod = (*codep >> 6) & 3; | |
12121 | modrm.reg = (*codep >> 3) & 7; | |
12122 | modrm.rm = *codep & 7; | |
12123 | } | |
12124 | break; | |
12125 | ||
12126 | case USE_VEX_C5_TABLE: | |
43234a1e | 12127 | /* VEX prefix. */ |
c0f3af97 L |
12128 | FETCH_DATA (info, codep + 2); |
12129 | /* All bits in the REX prefix are ignored. */ | |
12130 | rex_ignored = rex; | |
12131 | rex = (*codep & 0x80) ? 0 : REX_R; | |
12132 | ||
12133 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
12134 | if (address_mode != mode_64bit | |
12135 | && vex.register_specifier > 0x7) | |
f07af43e L |
12136 | { |
12137 | dp = &bad_opcode; | |
12138 | return dp; | |
12139 | } | |
c0f3af97 | 12140 | |
759a05ce L |
12141 | vex.w = 0; |
12142 | ||
c0f3af97 L |
12143 | vex.length = (*codep & 0x4) ? 256 : 128; |
12144 | switch ((*codep & 0x3)) | |
12145 | { | |
12146 | case 0: | |
12147 | vex.prefix = 0; | |
12148 | break; | |
12149 | case 1: | |
12150 | vex.prefix = DATA_PREFIX_OPCODE; | |
12151 | break; | |
12152 | case 2: | |
12153 | vex.prefix = REPE_PREFIX_OPCODE; | |
12154 | break; | |
12155 | case 3: | |
12156 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12157 | break; | |
12158 | } | |
12159 | need_vex = 1; | |
12160 | need_vex_reg = 1; | |
12161 | codep++; | |
91d6fa6a NC |
12162 | vindex = *codep++; |
12163 | dp = &vex_table[dp->op[1].bytemode][vindex]; | |
c0f3af97 | 12164 | /* There is no MODRM byte for VEX [82|77]. */ |
91d6fa6a | 12165 | if (vindex != 0x77 && vindex != 0x82) |
c0f3af97 L |
12166 | { |
12167 | FETCH_DATA (info, codep + 1); | |
12168 | modrm.mod = (*codep >> 6) & 3; | |
12169 | modrm.reg = (*codep >> 3) & 7; | |
12170 | modrm.rm = *codep & 7; | |
12171 | } | |
12172 | break; | |
12173 | ||
9e30b8e0 L |
12174 | case USE_VEX_W_TABLE: |
12175 | if (!need_vex) | |
12176 | abort (); | |
12177 | ||
12178 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; | |
12179 | break; | |
12180 | ||
43234a1e L |
12181 | case USE_EVEX_TABLE: |
12182 | two_source_ops = 0; | |
12183 | /* EVEX prefix. */ | |
12184 | vex.evex = 1; | |
12185 | FETCH_DATA (info, codep + 4); | |
12186 | /* All bits in the REX prefix are ignored. */ | |
12187 | rex_ignored = rex; | |
12188 | /* The first byte after 0x62. */ | |
12189 | rex = ~(*codep >> 5) & 0x7; | |
12190 | vex.r = *codep & 0x10; | |
12191 | switch ((*codep & 0xf)) | |
12192 | { | |
12193 | default: | |
12194 | return &bad_opcode; | |
12195 | case 0x1: | |
12196 | vex_table_index = EVEX_0F; | |
12197 | break; | |
12198 | case 0x2: | |
12199 | vex_table_index = EVEX_0F38; | |
12200 | break; | |
12201 | case 0x3: | |
12202 | vex_table_index = EVEX_0F3A; | |
12203 | break; | |
12204 | } | |
12205 | ||
12206 | /* The second byte after 0x62. */ | |
12207 | codep++; | |
12208 | vex.w = *codep & 0x80; | |
12209 | if (vex.w && address_mode == mode_64bit) | |
12210 | rex |= REX_W; | |
12211 | ||
12212 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
12213 | if (address_mode != mode_64bit) | |
12214 | { | |
12215 | /* In 16/32-bit mode silently ignore following bits. */ | |
12216 | rex &= ~REX_B; | |
12217 | vex.r = 1; | |
12218 | vex.v = 1; | |
12219 | vex.register_specifier &= 0x7; | |
12220 | } | |
12221 | ||
12222 | /* The U bit. */ | |
12223 | if (!(*codep & 0x4)) | |
12224 | return &bad_opcode; | |
12225 | ||
12226 | switch ((*codep & 0x3)) | |
12227 | { | |
12228 | case 0: | |
12229 | vex.prefix = 0; | |
12230 | break; | |
12231 | case 1: | |
12232 | vex.prefix = DATA_PREFIX_OPCODE; | |
12233 | break; | |
12234 | case 2: | |
12235 | vex.prefix = REPE_PREFIX_OPCODE; | |
12236 | break; | |
12237 | case 3: | |
12238 | vex.prefix = REPNE_PREFIX_OPCODE; | |
12239 | break; | |
12240 | } | |
12241 | ||
12242 | /* The third byte after 0x62. */ | |
12243 | codep++; | |
12244 | ||
12245 | /* Remember the static rounding bits. */ | |
12246 | vex.ll = (*codep >> 5) & 3; | |
12247 | vex.b = (*codep & 0x10) != 0; | |
12248 | ||
12249 | vex.v = *codep & 0x8; | |
12250 | vex.mask_register_specifier = *codep & 0x7; | |
12251 | vex.zeroing = *codep & 0x80; | |
12252 | ||
12253 | need_vex = 1; | |
12254 | need_vex_reg = 1; | |
12255 | codep++; | |
12256 | vindex = *codep++; | |
12257 | dp = &evex_table[vex_table_index][vindex]; | |
12258 | FETCH_DATA (info, codep + 1); | |
12259 | modrm.mod = (*codep >> 6) & 3; | |
12260 | modrm.reg = (*codep >> 3) & 7; | |
12261 | modrm.rm = *codep & 7; | |
12262 | ||
12263 | /* Set vector length. */ | |
12264 | if (modrm.mod == 3 && vex.b) | |
12265 | vex.length = 512; | |
12266 | else | |
12267 | { | |
12268 | switch (vex.ll) | |
12269 | { | |
12270 | case 0x0: | |
12271 | vex.length = 128; | |
12272 | break; | |
12273 | case 0x1: | |
12274 | vex.length = 256; | |
12275 | break; | |
12276 | case 0x2: | |
12277 | vex.length = 512; | |
12278 | break; | |
12279 | default: | |
12280 | return &bad_opcode; | |
12281 | } | |
12282 | } | |
12283 | break; | |
12284 | ||
592d1631 L |
12285 | case 0: |
12286 | dp = &bad_opcode; | |
12287 | break; | |
12288 | ||
b844680a | 12289 | default: |
d34b5006 | 12290 | abort (); |
b844680a L |
12291 | } |
12292 | ||
12293 | if (dp->name != NULL) | |
12294 | return dp; | |
12295 | else | |
8bb15339 | 12296 | return get_valid_dis386 (dp, info); |
b844680a L |
12297 | } |
12298 | ||
dfc8cf43 | 12299 | static void |
55cf16e1 | 12300 | get_sib (disassemble_info *info, int sizeflag) |
dfc8cf43 L |
12301 | { |
12302 | /* If modrm.mod == 3, operand must be register. */ | |
12303 | if (need_modrm | |
55cf16e1 | 12304 | && ((sizeflag & AFLAG) || address_mode == mode_64bit) |
dfc8cf43 L |
12305 | && modrm.mod != 3 |
12306 | && modrm.rm == 4) | |
12307 | { | |
12308 | FETCH_DATA (info, codep + 2); | |
12309 | sib.index = (codep [1] >> 3) & 7; | |
12310 | sib.scale = (codep [1] >> 6) & 3; | |
12311 | sib.base = codep [1] & 7; | |
12312 | } | |
12313 | } | |
12314 | ||
e396998b | 12315 | static int |
26ca5450 | 12316 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 12317 | { |
2da11e11 | 12318 | const struct dis386 *dp; |
252b5132 | 12319 | int i; |
ce518a5f | 12320 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 12321 | int needcomma; |
e396998b AM |
12322 | int sizeflag; |
12323 | const char *p; | |
252b5132 | 12324 | struct dis_private priv; |
f16cd0d5 L |
12325 | int prefix_length; |
12326 | int default_prefixes; | |
252b5132 | 12327 | |
d7921315 L |
12328 | priv.orig_sizeflag = AFLAG | DFLAG; |
12329 | if ((info->mach & bfd_mach_i386_i386) != 0) | |
cb712a9e | 12330 | address_mode = mode_32bit; |
2da11e11 | 12331 | else if (info->mach == bfd_mach_i386_i8086) |
d7921315 L |
12332 | { |
12333 | address_mode = mode_16bit; | |
12334 | priv.orig_sizeflag = 0; | |
12335 | } | |
2da11e11 | 12336 | else |
d7921315 L |
12337 | address_mode = mode_64bit; |
12338 | ||
12339 | if (intel_syntax == (char) -1) | |
12340 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; | |
e396998b AM |
12341 | |
12342 | for (p = info->disassembler_options; p != NULL; ) | |
12343 | { | |
0112cd26 | 12344 | if (CONST_STRNEQ (p, "x86-64")) |
e396998b | 12345 | { |
cb712a9e | 12346 | address_mode = mode_64bit; |
e396998b AM |
12347 | priv.orig_sizeflag = AFLAG | DFLAG; |
12348 | } | |
0112cd26 | 12349 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 12350 | { |
cb712a9e | 12351 | address_mode = mode_32bit; |
e396998b AM |
12352 | priv.orig_sizeflag = AFLAG | DFLAG; |
12353 | } | |
0112cd26 | 12354 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 12355 | { |
cb712a9e | 12356 | address_mode = mode_16bit; |
e396998b AM |
12357 | priv.orig_sizeflag = 0; |
12358 | } | |
0112cd26 | 12359 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
12360 | { |
12361 | intel_syntax = 1; | |
9d141669 L |
12362 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
12363 | intel_mnemonic = 1; | |
e396998b | 12364 | } |
0112cd26 | 12365 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
12366 | { |
12367 | intel_syntax = 0; | |
9d141669 L |
12368 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
12369 | intel_mnemonic = 0; | |
e396998b | 12370 | } |
0112cd26 | 12371 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 12372 | { |
f59a29b9 L |
12373 | if (address_mode == mode_64bit) |
12374 | { | |
12375 | if (p[4] == '3' && p[5] == '2') | |
12376 | priv.orig_sizeflag &= ~AFLAG; | |
12377 | else if (p[4] == '6' && p[5] == '4') | |
12378 | priv.orig_sizeflag |= AFLAG; | |
12379 | } | |
12380 | else | |
12381 | { | |
12382 | if (p[4] == '1' && p[5] == '6') | |
12383 | priv.orig_sizeflag &= ~AFLAG; | |
12384 | else if (p[4] == '3' && p[5] == '2') | |
12385 | priv.orig_sizeflag |= AFLAG; | |
12386 | } | |
e396998b | 12387 | } |
0112cd26 | 12388 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
12389 | { |
12390 | if (p[4] == '1' && p[5] == '6') | |
12391 | priv.orig_sizeflag &= ~DFLAG; | |
12392 | else if (p[4] == '3' && p[5] == '2') | |
12393 | priv.orig_sizeflag |= DFLAG; | |
12394 | } | |
0112cd26 | 12395 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
12396 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
12397 | ||
12398 | p = strchr (p, ','); | |
12399 | if (p != NULL) | |
12400 | p++; | |
12401 | } | |
12402 | ||
12403 | if (intel_syntax) | |
12404 | { | |
12405 | names64 = intel_names64; | |
12406 | names32 = intel_names32; | |
12407 | names16 = intel_names16; | |
12408 | names8 = intel_names8; | |
12409 | names8rex = intel_names8rex; | |
12410 | names_seg = intel_names_seg; | |
b9733481 | 12411 | names_mm = intel_names_mm; |
7e8b059b | 12412 | names_bnd = intel_names_bnd; |
b9733481 L |
12413 | names_xmm = intel_names_xmm; |
12414 | names_ymm = intel_names_ymm; | |
43234a1e | 12415 | names_zmm = intel_names_zmm; |
db51cc60 L |
12416 | index64 = intel_index64; |
12417 | index32 = intel_index32; | |
43234a1e | 12418 | names_mask = intel_names_mask; |
e396998b AM |
12419 | index16 = intel_index16; |
12420 | open_char = '['; | |
12421 | close_char = ']'; | |
12422 | separator_char = '+'; | |
12423 | scale_char = '*'; | |
12424 | } | |
12425 | else | |
12426 | { | |
12427 | names64 = att_names64; | |
12428 | names32 = att_names32; | |
12429 | names16 = att_names16; | |
12430 | names8 = att_names8; | |
12431 | names8rex = att_names8rex; | |
12432 | names_seg = att_names_seg; | |
b9733481 | 12433 | names_mm = att_names_mm; |
7e8b059b | 12434 | names_bnd = att_names_bnd; |
b9733481 L |
12435 | names_xmm = att_names_xmm; |
12436 | names_ymm = att_names_ymm; | |
43234a1e | 12437 | names_zmm = att_names_zmm; |
db51cc60 L |
12438 | index64 = att_index64; |
12439 | index32 = att_index32; | |
43234a1e | 12440 | names_mask = att_names_mask; |
e396998b AM |
12441 | index16 = att_index16; |
12442 | open_char = '('; | |
12443 | close_char = ')'; | |
12444 | separator_char = ','; | |
12445 | scale_char = ','; | |
12446 | } | |
2da11e11 | 12447 | |
4fe53c98 | 12448 | /* The output looks better if we put 7 bytes on a line, since that |
8a9036a4 L |
12449 | puts most long word instructions on a single line. Use 8 bytes |
12450 | for Intel L1OM. */ | |
d7921315 | 12451 | if ((info->mach & bfd_mach_l1om) != 0) |
8a9036a4 L |
12452 | info->bytes_per_line = 8; |
12453 | else | |
12454 | info->bytes_per_line = 7; | |
252b5132 | 12455 | |
26ca5450 | 12456 | info->private_data = &priv; |
252b5132 RH |
12457 | priv.max_fetched = priv.the_buffer; |
12458 | priv.insn_start = pc; | |
252b5132 RH |
12459 | |
12460 | obuf[0] = 0; | |
ce518a5f L |
12461 | for (i = 0; i < MAX_OPERANDS; ++i) |
12462 | { | |
12463 | op_out[i][0] = 0; | |
12464 | op_index[i] = -1; | |
12465 | } | |
252b5132 RH |
12466 | |
12467 | the_info = info; | |
12468 | start_pc = pc; | |
e396998b AM |
12469 | start_codep = priv.the_buffer; |
12470 | codep = priv.the_buffer; | |
252b5132 | 12471 | |
5076851f ILT |
12472 | if (setjmp (priv.bailout) != 0) |
12473 | { | |
7d421014 ILT |
12474 | const char *name; |
12475 | ||
5076851f | 12476 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
12477 | means we have an incomplete instruction of some sort. Just |
12478 | print the first byte as a prefix or a .byte pseudo-op. */ | |
12479 | if (codep > priv.the_buffer) | |
5076851f | 12480 | { |
e396998b | 12481 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
12482 | if (name != NULL) |
12483 | (*info->fprintf_func) (info->stream, "%s", name); | |
12484 | else | |
5076851f | 12485 | { |
7d421014 ILT |
12486 | /* Just print the first byte as a .byte instruction. */ |
12487 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 12488 | (unsigned int) priv.the_buffer[0]); |
5076851f | 12489 | } |
5076851f | 12490 | |
7d421014 | 12491 | return 1; |
5076851f ILT |
12492 | } |
12493 | ||
12494 | return -1; | |
12495 | } | |
12496 | ||
52b15da3 | 12497 | obufp = obuf; |
f16cd0d5 L |
12498 | sizeflag = priv.orig_sizeflag; |
12499 | ||
12500 | if (!ckprefix () || rex_used) | |
12501 | { | |
12502 | /* Too many prefixes or unused REX prefixes. */ | |
12503 | for (i = 0; | |
f6dd4781 | 12504 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
f16cd0d5 | 12505 | i++) |
de882298 | 12506 | (*info->fprintf_func) (info->stream, "%s%s", |
6c067bbb | 12507 | i == 0 ? "" : " ", |
f16cd0d5 | 12508 | prefix_name (all_prefixes[i], sizeflag)); |
de882298 | 12509 | return i; |
f16cd0d5 | 12510 | } |
252b5132 RH |
12511 | |
12512 | insn_codep = codep; | |
12513 | ||
12514 | FETCH_DATA (info, codep + 1); | |
12515 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
12516 | ||
3e7d61b2 | 12517 | if (((prefixes & PREFIX_FWAIT) |
f16cd0d5 | 12518 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
252b5132 | 12519 | { |
f16cd0d5 | 12520 | (*info->fprintf_func) (info->stream, "fwait"); |
7d421014 | 12521 | return 1; |
252b5132 RH |
12522 | } |
12523 | ||
252b5132 RH |
12524 | if (*codep == 0x0f) |
12525 | { | |
eec0f4ca | 12526 | unsigned char threebyte; |
252b5132 | 12527 | FETCH_DATA (info, codep + 2); |
eec0f4ca L |
12528 | threebyte = *++codep; |
12529 | dp = &dis386_twobyte[threebyte]; | |
252b5132 | 12530 | need_modrm = twobyte_has_modrm[*codep]; |
eec0f4ca | 12531 | codep++; |
252b5132 RH |
12532 | } |
12533 | else | |
12534 | { | |
6439fc28 | 12535 | dp = &dis386[*codep]; |
252b5132 | 12536 | need_modrm = onebyte_has_modrm[*codep]; |
eec0f4ca | 12537 | codep++; |
252b5132 | 12538 | } |
246c51aa | 12539 | |
b844680a | 12540 | if ((prefixes & PREFIX_REPZ)) |
f16cd0d5 | 12541 | used_prefixes |= PREFIX_REPZ; |
b844680a | 12542 | if ((prefixes & PREFIX_REPNZ)) |
f16cd0d5 | 12543 | used_prefixes |= PREFIX_REPNZ; |
b844680a | 12544 | if ((prefixes & PREFIX_LOCK)) |
f16cd0d5 | 12545 | used_prefixes |= PREFIX_LOCK; |
c608c12e | 12546 | |
f16cd0d5 | 12547 | default_prefixes = 0; |
c608c12e AM |
12548 | if (prefixes & PREFIX_ADDR) |
12549 | { | |
12550 | sizeflag ^= AFLAG; | |
ce518a5f | 12551 | if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax) |
3ffd33cf | 12552 | { |
cb712a9e | 12553 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
f16cd0d5 | 12554 | all_prefixes[last_addr_prefix] = ADDR32_PREFIX; |
3ffd33cf | 12555 | else |
f16cd0d5 L |
12556 | all_prefixes[last_addr_prefix] = ADDR16_PREFIX; |
12557 | default_prefixes |= PREFIX_ADDR; | |
3ffd33cf AM |
12558 | } |
12559 | } | |
12560 | ||
b844680a | 12561 | if ((prefixes & PREFIX_DATA)) |
3ffd33cf AM |
12562 | { |
12563 | sizeflag ^= DFLAG; | |
ce518a5f L |
12564 | if (dp->op[2].bytemode == cond_jump_mode |
12565 | && dp->op[0].bytemode == v_mode | |
6439fc28 | 12566 | && !intel_syntax) |
3ffd33cf AM |
12567 | { |
12568 | if (sizeflag & DFLAG) | |
f16cd0d5 | 12569 | all_prefixes[last_data_prefix] = DATA32_PREFIX; |
3ffd33cf | 12570 | else |
f16cd0d5 L |
12571 | all_prefixes[last_data_prefix] = DATA16_PREFIX; |
12572 | default_prefixes |= PREFIX_DATA; | |
12573 | } | |
12574 | else if (rex & REX_W) | |
12575 | { | |
12576 | /* REX_W will override PREFIX_DATA. */ | |
12577 | default_prefixes |= PREFIX_DATA; | |
3ffd33cf AM |
12578 | } |
12579 | } | |
12580 | ||
8bb15339 | 12581 | if (need_modrm) |
252b5132 RH |
12582 | { |
12583 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
12584 | modrm.mod = (*codep >> 6) & 3; |
12585 | modrm.reg = (*codep >> 3) & 7; | |
12586 | modrm.rm = *codep & 7; | |
252b5132 RH |
12587 | } |
12588 | ||
42d5f9c6 MS |
12589 | need_vex = 0; |
12590 | need_vex_reg = 0; | |
12591 | vex_w_done = 0; | |
43234a1e | 12592 | vex.evex = 0; |
55b126d4 | 12593 | |
ce518a5f | 12594 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 | 12595 | { |
55cf16e1 | 12596 | get_sib (info, sizeflag); |
252b5132 RH |
12597 | dofloat (sizeflag); |
12598 | } | |
12599 | else | |
12600 | { | |
8bb15339 | 12601 | dp = get_valid_dis386 (dp, info); |
b844680a | 12602 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
6c067bbb | 12603 | { |
55cf16e1 | 12604 | get_sib (info, sizeflag); |
ce518a5f L |
12605 | for (i = 0; i < MAX_OPERANDS; ++i) |
12606 | { | |
246c51aa | 12607 | obufp = op_out[i]; |
ce518a5f L |
12608 | op_ad = MAX_OPERANDS - 1 - i; |
12609 | if (dp->op[i].rtn) | |
12610 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
43234a1e L |
12611 | /* For EVEX instruction after the last operand masking |
12612 | should be printed. */ | |
12613 | if (i == 0 && vex.evex) | |
12614 | { | |
12615 | /* Don't print {%k0}. */ | |
12616 | if (vex.mask_register_specifier) | |
12617 | { | |
12618 | oappend ("{"); | |
12619 | oappend (names_mask[vex.mask_register_specifier]); | |
12620 | oappend ("}"); | |
12621 | } | |
12622 | if (vex.zeroing) | |
12623 | oappend ("{z}"); | |
12624 | } | |
ce518a5f | 12625 | } |
6439fc28 | 12626 | } |
252b5132 RH |
12627 | } |
12628 | ||
7d421014 ILT |
12629 | /* See if any prefixes were not used. If so, print the first one |
12630 | separately. If we don't do this, we'll wind up printing an | |
12631 | instruction stream which does not precisely correspond to the | |
12632 | bytes we are disassembling. */ | |
f16cd0d5 | 12633 | if ((prefixes & ~(used_prefixes | default_prefixes)) != 0) |
7d421014 | 12634 | { |
f16cd0d5 L |
12635 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
12636 | if (all_prefixes[i]) | |
12637 | { | |
12638 | const char *name; | |
12639 | name = prefix_name (all_prefixes[i], priv.orig_sizeflag); | |
12640 | if (name == NULL) | |
12641 | name = INTERNAL_DISASSEMBLER_ERROR; | |
12642 | (*info->fprintf_func) (info->stream, "%s", name); | |
12643 | return 1; | |
12644 | } | |
52b15da3 | 12645 | } |
7d421014 | 12646 | |
d869730d | 12647 | /* Check if the REX prefix is used. */ |
e2e6193d | 12648 | if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0) |
f16cd0d5 L |
12649 | all_prefixes[last_rex_prefix] = 0; |
12650 | ||
5e6718e4 | 12651 | /* Check if the SEG prefix is used. */ |
f16cd0d5 L |
12652 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
12653 | | PREFIX_FS | PREFIX_GS)) != 0 | |
12654 | && (used_prefixes | |
12655 | & seg_prefix (all_prefixes[last_seg_prefix])) != 0) | |
12656 | all_prefixes[last_seg_prefix] = 0; | |
12657 | ||
5e6718e4 | 12658 | /* Check if the ADDR prefix is used. */ |
f16cd0d5 L |
12659 | if ((prefixes & PREFIX_ADDR) != 0 |
12660 | && (used_prefixes & PREFIX_ADDR) != 0) | |
12661 | all_prefixes[last_addr_prefix] = 0; | |
12662 | ||
5e6718e4 | 12663 | /* Check if the DATA prefix is used. */ |
f16cd0d5 L |
12664 | if ((prefixes & PREFIX_DATA) != 0 |
12665 | && (used_prefixes & PREFIX_DATA) != 0) | |
12666 | all_prefixes[last_data_prefix] = 0; | |
12667 | ||
12668 | prefix_length = 0; | |
f310f33d | 12669 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
f16cd0d5 L |
12670 | if (all_prefixes[i]) |
12671 | { | |
12672 | const char *name; | |
12673 | name = prefix_name (all_prefixes[i], sizeflag); | |
12674 | if (name == NULL) | |
12675 | abort (); | |
12676 | prefix_length += strlen (name) + 1; | |
12677 | (*info->fprintf_func) (info->stream, "%s ", name); | |
12678 | } | |
b844680a | 12679 | |
f16cd0d5 L |
12680 | /* Check maximum code length. */ |
12681 | if ((codep - start_codep) > MAX_CODE_LENGTH) | |
12682 | { | |
12683 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12684 | return MAX_CODE_LENGTH; | |
12685 | } | |
b844680a | 12686 | |
ea397f5b | 12687 | obufp = mnemonicendp; |
f16cd0d5 | 12688 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
252b5132 RH |
12689 | oappend (" "); |
12690 | oappend (" "); | |
12691 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
12692 | ||
12693 | /* The enter and bound instructions are printed with operands in the same | |
12694 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 12695 | if (intel_syntax || two_source_ops) |
252b5132 | 12696 | { |
185b1163 L |
12697 | bfd_vma riprel; |
12698 | ||
ce518a5f | 12699 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 12700 | op_txt[i] = op_out[i]; |
246c51aa | 12701 | |
ce518a5f L |
12702 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
12703 | { | |
6c067bbb RM |
12704 | op_ad = op_index[i]; |
12705 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
12706 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
12707 | riprel = op_riprel[i]; |
12708 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
12709 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 12710 | } |
252b5132 RH |
12711 | } |
12712 | else | |
12713 | { | |
ce518a5f | 12714 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 12715 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; |
050dfa73 MM |
12716 | } |
12717 | ||
ce518a5f L |
12718 | needcomma = 0; |
12719 | for (i = 0; i < MAX_OPERANDS; ++i) | |
12720 | if (*op_txt[i]) | |
12721 | { | |
12722 | if (needcomma) | |
12723 | (*info->fprintf_func) (info->stream, ","); | |
12724 | if (op_index[i] != -1 && !op_riprel[i]) | |
12725 | (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info); | |
12726 | else | |
12727 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
12728 | needcomma = 1; | |
12729 | } | |
050dfa73 | 12730 | |
ce518a5f | 12731 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
12732 | if (op_index[i] != -1 && op_riprel[i]) |
12733 | { | |
12734 | (*info->fprintf_func) (info->stream, " # "); | |
12735 | (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep | |
12736 | + op_address[op_index[i]]), info); | |
185b1163 | 12737 | break; |
52b15da3 | 12738 | } |
e396998b | 12739 | return codep - priv.the_buffer; |
252b5132 RH |
12740 | } |
12741 | ||
6439fc28 | 12742 | static const char *float_mem[] = { |
252b5132 | 12743 | /* d8 */ |
7c52e0e8 L |
12744 | "fadd{s|}", |
12745 | "fmul{s|}", | |
12746 | "fcom{s|}", | |
12747 | "fcomp{s|}", | |
12748 | "fsub{s|}", | |
12749 | "fsubr{s|}", | |
12750 | "fdiv{s|}", | |
12751 | "fdivr{s|}", | |
db6eb5be | 12752 | /* d9 */ |
7c52e0e8 | 12753 | "fld{s|}", |
252b5132 | 12754 | "(bad)", |
7c52e0e8 L |
12755 | "fst{s|}", |
12756 | "fstp{s|}", | |
9306ca4a | 12757 | "fldenvIC", |
252b5132 | 12758 | "fldcw", |
9306ca4a | 12759 | "fNstenvIC", |
252b5132 RH |
12760 | "fNstcw", |
12761 | /* da */ | |
7c52e0e8 L |
12762 | "fiadd{l|}", |
12763 | "fimul{l|}", | |
12764 | "ficom{l|}", | |
12765 | "ficomp{l|}", | |
12766 | "fisub{l|}", | |
12767 | "fisubr{l|}", | |
12768 | "fidiv{l|}", | |
12769 | "fidivr{l|}", | |
252b5132 | 12770 | /* db */ |
7c52e0e8 L |
12771 | "fild{l|}", |
12772 | "fisttp{l|}", | |
12773 | "fist{l|}", | |
12774 | "fistp{l|}", | |
252b5132 | 12775 | "(bad)", |
6439fc28 | 12776 | "fld{t||t|}", |
252b5132 | 12777 | "(bad)", |
6439fc28 | 12778 | "fstp{t||t|}", |
252b5132 | 12779 | /* dc */ |
7c52e0e8 L |
12780 | "fadd{l|}", |
12781 | "fmul{l|}", | |
12782 | "fcom{l|}", | |
12783 | "fcomp{l|}", | |
12784 | "fsub{l|}", | |
12785 | "fsubr{l|}", | |
12786 | "fdiv{l|}", | |
12787 | "fdivr{l|}", | |
252b5132 | 12788 | /* dd */ |
7c52e0e8 L |
12789 | "fld{l|}", |
12790 | "fisttp{ll|}", | |
12791 | "fst{l||}", | |
12792 | "fstp{l|}", | |
9306ca4a | 12793 | "frstorIC", |
252b5132 | 12794 | "(bad)", |
9306ca4a | 12795 | "fNsaveIC", |
252b5132 RH |
12796 | "fNstsw", |
12797 | /* de */ | |
12798 | "fiadd", | |
12799 | "fimul", | |
12800 | "ficom", | |
12801 | "ficomp", | |
12802 | "fisub", | |
12803 | "fisubr", | |
12804 | "fidiv", | |
12805 | "fidivr", | |
12806 | /* df */ | |
12807 | "fild", | |
ca164297 | 12808 | "fisttp", |
252b5132 RH |
12809 | "fist", |
12810 | "fistp", | |
12811 | "fbld", | |
7c52e0e8 | 12812 | "fild{ll|}", |
252b5132 | 12813 | "fbstp", |
7c52e0e8 | 12814 | "fistp{ll|}", |
1d9f512f AM |
12815 | }; |
12816 | ||
12817 | static const unsigned char float_mem_mode[] = { | |
12818 | /* d8 */ | |
12819 | d_mode, | |
12820 | d_mode, | |
12821 | d_mode, | |
12822 | d_mode, | |
12823 | d_mode, | |
12824 | d_mode, | |
12825 | d_mode, | |
12826 | d_mode, | |
12827 | /* d9 */ | |
12828 | d_mode, | |
12829 | 0, | |
12830 | d_mode, | |
12831 | d_mode, | |
12832 | 0, | |
12833 | w_mode, | |
12834 | 0, | |
12835 | w_mode, | |
12836 | /* da */ | |
12837 | d_mode, | |
12838 | d_mode, | |
12839 | d_mode, | |
12840 | d_mode, | |
12841 | d_mode, | |
12842 | d_mode, | |
12843 | d_mode, | |
12844 | d_mode, | |
12845 | /* db */ | |
12846 | d_mode, | |
12847 | d_mode, | |
12848 | d_mode, | |
12849 | d_mode, | |
12850 | 0, | |
9306ca4a | 12851 | t_mode, |
1d9f512f | 12852 | 0, |
9306ca4a | 12853 | t_mode, |
1d9f512f AM |
12854 | /* dc */ |
12855 | q_mode, | |
12856 | q_mode, | |
12857 | q_mode, | |
12858 | q_mode, | |
12859 | q_mode, | |
12860 | q_mode, | |
12861 | q_mode, | |
12862 | q_mode, | |
12863 | /* dd */ | |
12864 | q_mode, | |
12865 | q_mode, | |
12866 | q_mode, | |
12867 | q_mode, | |
12868 | 0, | |
12869 | 0, | |
12870 | 0, | |
12871 | w_mode, | |
12872 | /* de */ | |
12873 | w_mode, | |
12874 | w_mode, | |
12875 | w_mode, | |
12876 | w_mode, | |
12877 | w_mode, | |
12878 | w_mode, | |
12879 | w_mode, | |
12880 | w_mode, | |
12881 | /* df */ | |
12882 | w_mode, | |
12883 | w_mode, | |
12884 | w_mode, | |
12885 | w_mode, | |
9306ca4a | 12886 | t_mode, |
1d9f512f | 12887 | q_mode, |
9306ca4a | 12888 | t_mode, |
1d9f512f | 12889 | q_mode |
252b5132 RH |
12890 | }; |
12891 | ||
ce518a5f L |
12892 | #define ST { OP_ST, 0 } |
12893 | #define STi { OP_STi, 0 } | |
252b5132 | 12894 | |
4efba78c L |
12895 | #define FGRPd9_2 NULL, { { NULL, 0 } } |
12896 | #define FGRPd9_4 NULL, { { NULL, 1 } } | |
12897 | #define FGRPd9_5 NULL, { { NULL, 2 } } | |
12898 | #define FGRPd9_6 NULL, { { NULL, 3 } } | |
12899 | #define FGRPd9_7 NULL, { { NULL, 4 } } | |
12900 | #define FGRPda_5 NULL, { { NULL, 5 } } | |
12901 | #define FGRPdb_4 NULL, { { NULL, 6 } } | |
12902 | #define FGRPde_3 NULL, { { NULL, 7 } } | |
12903 | #define FGRPdf_4 NULL, { { NULL, 8 } } | |
252b5132 | 12904 | |
2da11e11 | 12905 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
12906 | /* d8 */ |
12907 | { | |
ce518a5f L |
12908 | { "fadd", { ST, STi } }, |
12909 | { "fmul", { ST, STi } }, | |
12910 | { "fcom", { STi } }, | |
12911 | { "fcomp", { STi } }, | |
12912 | { "fsub", { ST, STi } }, | |
12913 | { "fsubr", { ST, STi } }, | |
12914 | { "fdiv", { ST, STi } }, | |
12915 | { "fdivr", { ST, STi } }, | |
252b5132 RH |
12916 | }, |
12917 | /* d9 */ | |
12918 | { | |
ce518a5f L |
12919 | { "fld", { STi } }, |
12920 | { "fxch", { STi } }, | |
252b5132 | 12921 | { FGRPd9_2 }, |
592d1631 | 12922 | { Bad_Opcode }, |
252b5132 RH |
12923 | { FGRPd9_4 }, |
12924 | { FGRPd9_5 }, | |
12925 | { FGRPd9_6 }, | |
12926 | { FGRPd9_7 }, | |
12927 | }, | |
12928 | /* da */ | |
12929 | { | |
ce518a5f L |
12930 | { "fcmovb", { ST, STi } }, |
12931 | { "fcmove", { ST, STi } }, | |
12932 | { "fcmovbe",{ ST, STi } }, | |
12933 | { "fcmovu", { ST, STi } }, | |
592d1631 | 12934 | { Bad_Opcode }, |
252b5132 | 12935 | { FGRPda_5 }, |
592d1631 L |
12936 | { Bad_Opcode }, |
12937 | { Bad_Opcode }, | |
252b5132 RH |
12938 | }, |
12939 | /* db */ | |
12940 | { | |
ce518a5f L |
12941 | { "fcmovnb",{ ST, STi } }, |
12942 | { "fcmovne",{ ST, STi } }, | |
12943 | { "fcmovnbe",{ ST, STi } }, | |
12944 | { "fcmovnu",{ ST, STi } }, | |
252b5132 | 12945 | { FGRPdb_4 }, |
ce518a5f L |
12946 | { "fucomi", { ST, STi } }, |
12947 | { "fcomi", { ST, STi } }, | |
592d1631 | 12948 | { Bad_Opcode }, |
252b5132 RH |
12949 | }, |
12950 | /* dc */ | |
12951 | { | |
ce518a5f L |
12952 | { "fadd", { STi, ST } }, |
12953 | { "fmul", { STi, ST } }, | |
592d1631 L |
12954 | { Bad_Opcode }, |
12955 | { Bad_Opcode }, | |
9d141669 L |
12956 | { "fsub!M", { STi, ST } }, |
12957 | { "fsubM", { STi, ST } }, | |
12958 | { "fdiv!M", { STi, ST } }, | |
12959 | { "fdivM", { STi, ST } }, | |
252b5132 RH |
12960 | }, |
12961 | /* dd */ | |
12962 | { | |
ce518a5f | 12963 | { "ffree", { STi } }, |
592d1631 | 12964 | { Bad_Opcode }, |
ce518a5f L |
12965 | { "fst", { STi } }, |
12966 | { "fstp", { STi } }, | |
12967 | { "fucom", { STi } }, | |
12968 | { "fucomp", { STi } }, | |
592d1631 L |
12969 | { Bad_Opcode }, |
12970 | { Bad_Opcode }, | |
252b5132 RH |
12971 | }, |
12972 | /* de */ | |
12973 | { | |
ce518a5f L |
12974 | { "faddp", { STi, ST } }, |
12975 | { "fmulp", { STi, ST } }, | |
592d1631 | 12976 | { Bad_Opcode }, |
252b5132 | 12977 | { FGRPde_3 }, |
9d141669 L |
12978 | { "fsub!Mp", { STi, ST } }, |
12979 | { "fsubMp", { STi, ST } }, | |
12980 | { "fdiv!Mp", { STi, ST } }, | |
12981 | { "fdivMp", { STi, ST } }, | |
252b5132 RH |
12982 | }, |
12983 | /* df */ | |
12984 | { | |
ce518a5f | 12985 | { "ffreep", { STi } }, |
592d1631 L |
12986 | { Bad_Opcode }, |
12987 | { Bad_Opcode }, | |
12988 | { Bad_Opcode }, | |
252b5132 | 12989 | { FGRPdf_4 }, |
ce518a5f L |
12990 | { "fucomip", { ST, STi } }, |
12991 | { "fcomip", { ST, STi } }, | |
592d1631 | 12992 | { Bad_Opcode }, |
252b5132 RH |
12993 | }, |
12994 | }; | |
12995 | ||
252b5132 RH |
12996 | static char *fgrps[][8] = { |
12997 | /* d9_2 0 */ | |
12998 | { | |
12999 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13000 | }, | |
13001 | ||
13002 | /* d9_4 1 */ | |
13003 | { | |
13004 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
13005 | }, | |
13006 | ||
13007 | /* d9_5 2 */ | |
13008 | { | |
13009 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
13010 | }, | |
13011 | ||
13012 | /* d9_6 3 */ | |
13013 | { | |
13014 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
13015 | }, | |
13016 | ||
13017 | /* d9_7 4 */ | |
13018 | { | |
13019 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
13020 | }, | |
13021 | ||
13022 | /* da_5 5 */ | |
13023 | { | |
13024 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13025 | }, | |
13026 | ||
13027 | /* db_4 6 */ | |
13028 | { | |
309d3373 JB |
13029 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
13030 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", | |
252b5132 RH |
13031 | }, |
13032 | ||
13033 | /* de_3 7 */ | |
13034 | { | |
13035 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13036 | }, | |
13037 | ||
13038 | /* df_4 8 */ | |
13039 | { | |
13040 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
13041 | }, | |
13042 | }; | |
13043 | ||
b6169b20 L |
13044 | static void |
13045 | swap_operand (void) | |
13046 | { | |
13047 | mnemonicendp[0] = '.'; | |
13048 | mnemonicendp[1] = 's'; | |
13049 | mnemonicendp += 2; | |
13050 | } | |
13051 | ||
b844680a L |
13052 | static void |
13053 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
13054 | int sizeflag ATTRIBUTE_UNUSED) | |
13055 | { | |
13056 | /* Skip mod/rm byte. */ | |
13057 | MODRM_CHECK; | |
13058 | codep++; | |
13059 | } | |
13060 | ||
252b5132 | 13061 | static void |
26ca5450 | 13062 | dofloat (int sizeflag) |
252b5132 | 13063 | { |
2da11e11 | 13064 | const struct dis386 *dp; |
252b5132 RH |
13065 | unsigned char floatop; |
13066 | ||
13067 | floatop = codep[-1]; | |
13068 | ||
7967e09e | 13069 | if (modrm.mod != 3) |
252b5132 | 13070 | { |
7967e09e | 13071 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
13072 | |
13073 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 13074 | obufp = op_out[0]; |
6e50d963 | 13075 | op_ad = 2; |
1d9f512f | 13076 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
13077 | return; |
13078 | } | |
6608db57 | 13079 | /* Skip mod/rm byte. */ |
4bba6815 | 13080 | MODRM_CHECK; |
252b5132 RH |
13081 | codep++; |
13082 | ||
7967e09e | 13083 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
13084 | if (dp->name == NULL) |
13085 | { | |
7967e09e | 13086 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 13087 | |
6608db57 | 13088 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 13089 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 13090 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
13091 | } |
13092 | else | |
13093 | { | |
13094 | putop (dp->name, sizeflag); | |
13095 | ||
ce518a5f | 13096 | obufp = op_out[0]; |
6e50d963 | 13097 | op_ad = 2; |
ce518a5f L |
13098 | if (dp->op[0].rtn) |
13099 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 13100 | |
ce518a5f | 13101 | obufp = op_out[1]; |
6e50d963 | 13102 | op_ad = 1; |
ce518a5f L |
13103 | if (dp->op[1].rtn) |
13104 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
13105 | } |
13106 | } | |
13107 | ||
9ce09ba2 RM |
13108 | /* Like oappend (below), but S is a string starting with '%'. |
13109 | In Intel syntax, the '%' is elided. */ | |
13110 | static void | |
13111 | oappend_maybe_intel (const char *s) | |
13112 | { | |
13113 | oappend (s + intel_syntax); | |
13114 | } | |
13115 | ||
252b5132 | 13116 | static void |
26ca5450 | 13117 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13118 | { |
9ce09ba2 | 13119 | oappend_maybe_intel ("%st"); |
252b5132 RH |
13120 | } |
13121 | ||
252b5132 | 13122 | static void |
26ca5450 | 13123 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13124 | { |
7967e09e | 13125 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
9ce09ba2 | 13126 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
13127 | } |
13128 | ||
6608db57 | 13129 | /* Capital letters in template are macros. */ |
6439fc28 | 13130 | static int |
d3ce72d0 | 13131 | putop (const char *in_template, int sizeflag) |
252b5132 | 13132 | { |
2da11e11 | 13133 | const char *p; |
9306ca4a | 13134 | int alt = 0; |
9d141669 | 13135 | int cond = 1; |
98b528ac L |
13136 | unsigned int l = 0, len = 1; |
13137 | char last[4]; | |
13138 | ||
13139 | #define SAVE_LAST(c) \ | |
13140 | if (l < len && l < sizeof (last)) \ | |
13141 | last[l++] = c; \ | |
13142 | else \ | |
13143 | abort (); | |
252b5132 | 13144 | |
d3ce72d0 | 13145 | for (p = in_template; *p; p++) |
252b5132 RH |
13146 | { |
13147 | switch (*p) | |
13148 | { | |
13149 | default: | |
13150 | *obufp++ = *p; | |
13151 | break; | |
98b528ac L |
13152 | case '%': |
13153 | len++; | |
13154 | break; | |
9d141669 L |
13155 | case '!': |
13156 | cond = 0; | |
13157 | break; | |
6439fc28 AM |
13158 | case '{': |
13159 | alt = 0; | |
13160 | if (intel_syntax) | |
6439fc28 AM |
13161 | { |
13162 | while (*++p != '|') | |
7c52e0e8 L |
13163 | if (*p == '}' || *p == '\0') |
13164 | abort (); | |
6439fc28 | 13165 | } |
9306ca4a JB |
13166 | /* Fall through. */ |
13167 | case 'I': | |
13168 | alt = 1; | |
13169 | continue; | |
6439fc28 AM |
13170 | case '|': |
13171 | while (*++p != '}') | |
13172 | { | |
13173 | if (*p == '\0') | |
13174 | abort (); | |
13175 | } | |
13176 | break; | |
13177 | case '}': | |
13178 | break; | |
252b5132 | 13179 | case 'A': |
db6eb5be AM |
13180 | if (intel_syntax) |
13181 | break; | |
7967e09e | 13182 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 RH |
13183 | *obufp++ = 'b'; |
13184 | break; | |
13185 | case 'B': | |
4b06377f L |
13186 | if (l == 0 && len == 1) |
13187 | { | |
13188 | case_B: | |
13189 | if (intel_syntax) | |
13190 | break; | |
13191 | if (sizeflag & SUFFIX_ALWAYS) | |
13192 | *obufp++ = 'b'; | |
13193 | } | |
13194 | else | |
13195 | { | |
13196 | if (l != 1 | |
13197 | || len != 2 | |
13198 | || last[0] != 'L') | |
13199 | { | |
13200 | SAVE_LAST (*p); | |
13201 | break; | |
13202 | } | |
13203 | ||
13204 | if (address_mode == mode_64bit | |
13205 | && !(prefixes & PREFIX_ADDR)) | |
13206 | { | |
13207 | *obufp++ = 'a'; | |
13208 | *obufp++ = 'b'; | |
13209 | *obufp++ = 's'; | |
13210 | } | |
13211 | ||
13212 | goto case_B; | |
13213 | } | |
252b5132 | 13214 | break; |
9306ca4a JB |
13215 | case 'C': |
13216 | if (intel_syntax && !alt) | |
13217 | break; | |
13218 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
13219 | { | |
13220 | if (sizeflag & DFLAG) | |
13221 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13222 | else | |
13223 | *obufp++ = intel_syntax ? 'w' : 's'; | |
13224 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13225 | } | |
13226 | break; | |
ed7841b3 JB |
13227 | case 'D': |
13228 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
13229 | break; | |
161a04f6 | 13230 | USED_REX (REX_W); |
7967e09e | 13231 | if (modrm.mod == 3) |
ed7841b3 | 13232 | { |
161a04f6 | 13233 | if (rex & REX_W) |
ed7841b3 | 13234 | *obufp++ = 'q'; |
ed7841b3 | 13235 | else |
f16cd0d5 L |
13236 | { |
13237 | if (sizeflag & DFLAG) | |
13238 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13239 | else | |
13240 | *obufp++ = 'w'; | |
13241 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13242 | } | |
ed7841b3 JB |
13243 | } |
13244 | else | |
13245 | *obufp++ = 'w'; | |
13246 | break; | |
252b5132 | 13247 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 13248 | if (address_mode == mode_64bit) |
c1a64871 JH |
13249 | { |
13250 | if (sizeflag & AFLAG) | |
13251 | *obufp++ = 'r'; | |
13252 | else | |
13253 | *obufp++ = 'e'; | |
13254 | } | |
13255 | else | |
13256 | if (sizeflag & AFLAG) | |
13257 | *obufp++ = 'e'; | |
3ffd33cf AM |
13258 | used_prefixes |= (prefixes & PREFIX_ADDR); |
13259 | break; | |
13260 | case 'F': | |
db6eb5be AM |
13261 | if (intel_syntax) |
13262 | break; | |
e396998b | 13263 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
13264 | { |
13265 | if (sizeflag & AFLAG) | |
cb712a9e | 13266 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 13267 | else |
cb712a9e | 13268 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
13269 | used_prefixes |= (prefixes & PREFIX_ADDR); |
13270 | } | |
252b5132 | 13271 | break; |
52fd6d94 JB |
13272 | case 'G': |
13273 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
13274 | break; | |
161a04f6 | 13275 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
13276 | *obufp++ = 'l'; |
13277 | else | |
13278 | *obufp++ = 'w'; | |
161a04f6 | 13279 | if (!(rex & REX_W)) |
52fd6d94 JB |
13280 | used_prefixes |= (prefixes & PREFIX_DATA); |
13281 | break; | |
5dd0794d | 13282 | case 'H': |
db6eb5be AM |
13283 | if (intel_syntax) |
13284 | break; | |
5dd0794d AM |
13285 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
13286 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
13287 | { | |
13288 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
13289 | *obufp++ = ','; | |
13290 | *obufp++ = 'p'; | |
13291 | if (prefixes & PREFIX_DS) | |
13292 | *obufp++ = 't'; | |
13293 | else | |
13294 | *obufp++ = 'n'; | |
13295 | } | |
13296 | break; | |
9306ca4a JB |
13297 | case 'J': |
13298 | if (intel_syntax) | |
13299 | break; | |
13300 | *obufp++ = 'l'; | |
13301 | break; | |
42903f7f L |
13302 | case 'K': |
13303 | USED_REX (REX_W); | |
13304 | if (rex & REX_W) | |
13305 | *obufp++ = 'q'; | |
13306 | else | |
13307 | *obufp++ = 'd'; | |
13308 | break; | |
6dd5059a L |
13309 | case 'Z': |
13310 | if (intel_syntax) | |
13311 | break; | |
13312 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) | |
13313 | { | |
13314 | *obufp++ = 'q'; | |
13315 | break; | |
13316 | } | |
13317 | /* Fall through. */ | |
98b528ac | 13318 | goto case_L; |
252b5132 | 13319 | case 'L': |
98b528ac L |
13320 | if (l != 0 || len != 1) |
13321 | { | |
13322 | SAVE_LAST (*p); | |
13323 | break; | |
13324 | } | |
13325 | case_L: | |
db6eb5be AM |
13326 | if (intel_syntax) |
13327 | break; | |
252b5132 RH |
13328 | if (sizeflag & SUFFIX_ALWAYS) |
13329 | *obufp++ = 'l'; | |
252b5132 | 13330 | break; |
9d141669 L |
13331 | case 'M': |
13332 | if (intel_mnemonic != cond) | |
13333 | *obufp++ = 'r'; | |
13334 | break; | |
252b5132 RH |
13335 | case 'N': |
13336 | if ((prefixes & PREFIX_FWAIT) == 0) | |
13337 | *obufp++ = 'n'; | |
7d421014 ILT |
13338 | else |
13339 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 13340 | break; |
52b15da3 | 13341 | case 'O': |
161a04f6 L |
13342 | USED_REX (REX_W); |
13343 | if (rex & REX_W) | |
6439fc28 | 13344 | *obufp++ = 'o'; |
a35ca55a JB |
13345 | else if (intel_syntax && (sizeflag & DFLAG)) |
13346 | *obufp++ = 'q'; | |
52b15da3 JH |
13347 | else |
13348 | *obufp++ = 'd'; | |
161a04f6 | 13349 | if (!(rex & REX_W)) |
a35ca55a | 13350 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 13351 | break; |
6439fc28 | 13352 | case 'T': |
d9e3625e L |
13353 | if (!intel_syntax |
13354 | && address_mode == mode_64bit | |
7bb15c6f | 13355 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
13356 | { |
13357 | *obufp++ = 'q'; | |
13358 | break; | |
13359 | } | |
6608db57 | 13360 | /* Fall through. */ |
252b5132 | 13361 | case 'P': |
db6eb5be | 13362 | if (intel_syntax) |
d9e3625e L |
13363 | { |
13364 | if ((rex & REX_W) == 0 | |
13365 | && (prefixes & PREFIX_DATA)) | |
13366 | { | |
13367 | if ((sizeflag & DFLAG) == 0) | |
13368 | *obufp++ = 'w'; | |
13369 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13370 | } | |
13371 | break; | |
13372 | } | |
252b5132 | 13373 | if ((prefixes & PREFIX_DATA) |
161a04f6 | 13374 | || (rex & REX_W) |
e396998b | 13375 | || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 | 13376 | { |
161a04f6 L |
13377 | USED_REX (REX_W); |
13378 | if (rex & REX_W) | |
52b15da3 | 13379 | *obufp++ = 'q'; |
c2419411 | 13380 | else |
52b15da3 JH |
13381 | { |
13382 | if (sizeflag & DFLAG) | |
13383 | *obufp++ = 'l'; | |
13384 | else | |
13385 | *obufp++ = 'w'; | |
f16cd0d5 | 13386 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 13387 | } |
252b5132 RH |
13388 | } |
13389 | break; | |
6439fc28 | 13390 | case 'U': |
db6eb5be AM |
13391 | if (intel_syntax) |
13392 | break; | |
7bb15c6f | 13393 | if (address_mode == mode_64bit |
6c067bbb | 13394 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 | 13395 | { |
7967e09e | 13396 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
1a114b12 | 13397 | *obufp++ = 'q'; |
6439fc28 AM |
13398 | break; |
13399 | } | |
6608db57 | 13400 | /* Fall through. */ |
98b528ac | 13401 | goto case_Q; |
252b5132 | 13402 | case 'Q': |
98b528ac | 13403 | if (l == 0 && len == 1) |
252b5132 | 13404 | { |
98b528ac L |
13405 | case_Q: |
13406 | if (intel_syntax && !alt) | |
13407 | break; | |
13408 | USED_REX (REX_W); | |
13409 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 13410 | { |
98b528ac L |
13411 | if (rex & REX_W) |
13412 | *obufp++ = 'q'; | |
52b15da3 | 13413 | else |
98b528ac L |
13414 | { |
13415 | if (sizeflag & DFLAG) | |
13416 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13417 | else | |
13418 | *obufp++ = 'w'; | |
f16cd0d5 | 13419 | used_prefixes |= (prefixes & PREFIX_DATA); |
98b528ac | 13420 | } |
52b15da3 | 13421 | } |
98b528ac L |
13422 | } |
13423 | else | |
13424 | { | |
13425 | if (l != 1 || len != 2 || last[0] != 'L') | |
13426 | { | |
13427 | SAVE_LAST (*p); | |
13428 | break; | |
13429 | } | |
13430 | if (intel_syntax | |
13431 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) | |
13432 | break; | |
13433 | if ((rex & REX_W)) | |
13434 | { | |
13435 | USED_REX (REX_W); | |
13436 | *obufp++ = 'q'; | |
13437 | } | |
13438 | else | |
13439 | *obufp++ = 'l'; | |
252b5132 RH |
13440 | } |
13441 | break; | |
13442 | case 'R': | |
161a04f6 L |
13443 | USED_REX (REX_W); |
13444 | if (rex & REX_W) | |
a35ca55a JB |
13445 | *obufp++ = 'q'; |
13446 | else if (sizeflag & DFLAG) | |
c608c12e | 13447 | { |
a35ca55a | 13448 | if (intel_syntax) |
c608c12e | 13449 | *obufp++ = 'd'; |
c608c12e | 13450 | else |
a35ca55a | 13451 | *obufp++ = 'l'; |
c608c12e | 13452 | } |
252b5132 | 13453 | else |
a35ca55a JB |
13454 | *obufp++ = 'w'; |
13455 | if (intel_syntax && !p[1] | |
161a04f6 | 13456 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 13457 | *obufp++ = 'e'; |
161a04f6 | 13458 | if (!(rex & REX_W)) |
52b15da3 | 13459 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 13460 | break; |
1a114b12 | 13461 | case 'V': |
4b06377f | 13462 | if (l == 0 && len == 1) |
1a114b12 | 13463 | { |
4b06377f L |
13464 | if (intel_syntax) |
13465 | break; | |
7bb15c6f | 13466 | if (address_mode == mode_64bit |
6c067bbb | 13467 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
4b06377f L |
13468 | { |
13469 | if (sizeflag & SUFFIX_ALWAYS) | |
13470 | *obufp++ = 'q'; | |
13471 | break; | |
13472 | } | |
13473 | } | |
13474 | else | |
13475 | { | |
13476 | if (l != 1 | |
13477 | || len != 2 | |
13478 | || last[0] != 'L') | |
13479 | { | |
13480 | SAVE_LAST (*p); | |
13481 | break; | |
13482 | } | |
13483 | ||
13484 | if (rex & REX_W) | |
13485 | { | |
13486 | *obufp++ = 'a'; | |
13487 | *obufp++ = 'b'; | |
13488 | *obufp++ = 's'; | |
13489 | } | |
1a114b12 JB |
13490 | } |
13491 | /* Fall through. */ | |
4b06377f | 13492 | goto case_S; |
252b5132 | 13493 | case 'S': |
4b06377f | 13494 | if (l == 0 && len == 1) |
252b5132 | 13495 | { |
4b06377f L |
13496 | case_S: |
13497 | if (intel_syntax) | |
13498 | break; | |
13499 | if (sizeflag & SUFFIX_ALWAYS) | |
52b15da3 | 13500 | { |
4b06377f L |
13501 | if (rex & REX_W) |
13502 | *obufp++ = 'q'; | |
52b15da3 | 13503 | else |
4b06377f L |
13504 | { |
13505 | if (sizeflag & DFLAG) | |
13506 | *obufp++ = 'l'; | |
13507 | else | |
13508 | *obufp++ = 'w'; | |
13509 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13510 | } | |
13511 | } | |
13512 | } | |
13513 | else | |
13514 | { | |
13515 | if (l != 1 | |
13516 | || len != 2 | |
13517 | || last[0] != 'L') | |
13518 | { | |
13519 | SAVE_LAST (*p); | |
13520 | break; | |
52b15da3 | 13521 | } |
4b06377f L |
13522 | |
13523 | if (address_mode == mode_64bit | |
13524 | && !(prefixes & PREFIX_ADDR)) | |
13525 | { | |
13526 | *obufp++ = 'a'; | |
13527 | *obufp++ = 'b'; | |
13528 | *obufp++ = 's'; | |
13529 | } | |
13530 | ||
13531 | goto case_S; | |
252b5132 | 13532 | } |
252b5132 | 13533 | break; |
041bd2e0 | 13534 | case 'X': |
c0f3af97 L |
13535 | if (l != 0 || len != 1) |
13536 | { | |
13537 | SAVE_LAST (*p); | |
13538 | break; | |
13539 | } | |
13540 | if (need_vex && vex.prefix) | |
13541 | { | |
13542 | if (vex.prefix == DATA_PREFIX_OPCODE) | |
13543 | *obufp++ = 'd'; | |
13544 | else | |
13545 | *obufp++ = 's'; | |
13546 | } | |
041bd2e0 | 13547 | else |
f16cd0d5 L |
13548 | { |
13549 | if (prefixes & PREFIX_DATA) | |
13550 | *obufp++ = 'd'; | |
13551 | else | |
13552 | *obufp++ = 's'; | |
13553 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13554 | } | |
041bd2e0 | 13555 | break; |
76f227a5 | 13556 | case 'Y': |
c0f3af97 | 13557 | if (l == 0 && len == 1) |
76f227a5 | 13558 | { |
c0f3af97 L |
13559 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) |
13560 | break; | |
13561 | if (rex & REX_W) | |
13562 | { | |
13563 | USED_REX (REX_W); | |
13564 | *obufp++ = 'q'; | |
13565 | } | |
13566 | break; | |
13567 | } | |
13568 | else | |
13569 | { | |
13570 | if (l != 1 || len != 2 || last[0] != 'X') | |
13571 | { | |
13572 | SAVE_LAST (*p); | |
13573 | break; | |
13574 | } | |
13575 | if (!need_vex) | |
13576 | abort (); | |
13577 | if (intel_syntax | |
13578 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) | |
13579 | break; | |
13580 | switch (vex.length) | |
13581 | { | |
13582 | case 128: | |
13583 | *obufp++ = 'x'; | |
13584 | break; | |
13585 | case 256: | |
13586 | *obufp++ = 'y'; | |
13587 | break; | |
13588 | default: | |
13589 | abort (); | |
13590 | } | |
76f227a5 JH |
13591 | } |
13592 | break; | |
252b5132 | 13593 | case 'W': |
0bfee649 | 13594 | if (l == 0 && len == 1) |
a35ca55a | 13595 | { |
0bfee649 L |
13596 | /* operand size flag for cwtl, cbtw */ |
13597 | USED_REX (REX_W); | |
13598 | if (rex & REX_W) | |
13599 | { | |
13600 | if (intel_syntax) | |
13601 | *obufp++ = 'd'; | |
13602 | else | |
13603 | *obufp++ = 'l'; | |
13604 | } | |
13605 | else if (sizeflag & DFLAG) | |
13606 | *obufp++ = 'w'; | |
a35ca55a | 13607 | else |
0bfee649 L |
13608 | *obufp++ = 'b'; |
13609 | if (!(rex & REX_W)) | |
13610 | used_prefixes |= (prefixes & PREFIX_DATA); | |
a35ca55a | 13611 | } |
252b5132 | 13612 | else |
0bfee649 | 13613 | { |
6c30d220 L |
13614 | if (l != 1 |
13615 | || len != 2 | |
13616 | || (last[0] != 'X' | |
13617 | && last[0] != 'L')) | |
0bfee649 L |
13618 | { |
13619 | SAVE_LAST (*p); | |
13620 | break; | |
13621 | } | |
13622 | if (!need_vex) | |
13623 | abort (); | |
6c30d220 L |
13624 | if (last[0] == 'X') |
13625 | *obufp++ = vex.w ? 'd': 's'; | |
13626 | else | |
13627 | *obufp++ = vex.w ? 'q': 'd'; | |
0bfee649 | 13628 | } |
252b5132 RH |
13629 | break; |
13630 | } | |
9306ca4a | 13631 | alt = 0; |
252b5132 RH |
13632 | } |
13633 | *obufp = 0; | |
ea397f5b | 13634 | mnemonicendp = obufp; |
6439fc28 | 13635 | return 0; |
252b5132 RH |
13636 | } |
13637 | ||
13638 | static void | |
26ca5450 | 13639 | oappend (const char *s) |
252b5132 | 13640 | { |
ea397f5b | 13641 | obufp = stpcpy (obufp, s); |
252b5132 RH |
13642 | } |
13643 | ||
13644 | static void | |
26ca5450 | 13645 | append_seg (void) |
252b5132 RH |
13646 | { |
13647 | if (prefixes & PREFIX_CS) | |
7d421014 | 13648 | { |
7d421014 | 13649 | used_prefixes |= PREFIX_CS; |
9ce09ba2 | 13650 | oappend_maybe_intel ("%cs:"); |
7d421014 | 13651 | } |
252b5132 | 13652 | if (prefixes & PREFIX_DS) |
7d421014 | 13653 | { |
7d421014 | 13654 | used_prefixes |= PREFIX_DS; |
9ce09ba2 | 13655 | oappend_maybe_intel ("%ds:"); |
7d421014 | 13656 | } |
252b5132 | 13657 | if (prefixes & PREFIX_SS) |
7d421014 | 13658 | { |
7d421014 | 13659 | used_prefixes |= PREFIX_SS; |
9ce09ba2 | 13660 | oappend_maybe_intel ("%ss:"); |
7d421014 | 13661 | } |
252b5132 | 13662 | if (prefixes & PREFIX_ES) |
7d421014 | 13663 | { |
7d421014 | 13664 | used_prefixes |= PREFIX_ES; |
9ce09ba2 | 13665 | oappend_maybe_intel ("%es:"); |
7d421014 | 13666 | } |
252b5132 | 13667 | if (prefixes & PREFIX_FS) |
7d421014 | 13668 | { |
7d421014 | 13669 | used_prefixes |= PREFIX_FS; |
9ce09ba2 | 13670 | oappend_maybe_intel ("%fs:"); |
7d421014 | 13671 | } |
252b5132 | 13672 | if (prefixes & PREFIX_GS) |
7d421014 | 13673 | { |
7d421014 | 13674 | used_prefixes |= PREFIX_GS; |
9ce09ba2 | 13675 | oappend_maybe_intel ("%gs:"); |
7d421014 | 13676 | } |
252b5132 RH |
13677 | } |
13678 | ||
13679 | static void | |
26ca5450 | 13680 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
13681 | { |
13682 | if (!intel_syntax) | |
13683 | oappend ("*"); | |
13684 | OP_E (bytemode, sizeflag); | |
13685 | } | |
13686 | ||
52b15da3 | 13687 | static void |
26ca5450 | 13688 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 13689 | { |
cb712a9e | 13690 | if (address_mode == mode_64bit) |
52b15da3 JH |
13691 | { |
13692 | if (hex) | |
13693 | { | |
13694 | char tmp[30]; | |
13695 | int i; | |
13696 | buf[0] = '0'; | |
13697 | buf[1] = 'x'; | |
13698 | sprintf_vma (tmp, disp); | |
6608db57 | 13699 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
13700 | strcpy (buf + 2, tmp + i); |
13701 | } | |
13702 | else | |
13703 | { | |
13704 | bfd_signed_vma v = disp; | |
13705 | char tmp[30]; | |
13706 | int i; | |
13707 | if (v < 0) | |
13708 | { | |
13709 | *(buf++) = '-'; | |
13710 | v = -disp; | |
6608db57 | 13711 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
13712 | if (v < 0) |
13713 | { | |
13714 | strcpy (buf, "9223372036854775808"); | |
13715 | return; | |
13716 | } | |
13717 | } | |
13718 | if (!v) | |
13719 | { | |
13720 | strcpy (buf, "0"); | |
13721 | return; | |
13722 | } | |
13723 | ||
13724 | i = 0; | |
13725 | tmp[29] = 0; | |
13726 | while (v) | |
13727 | { | |
6608db57 | 13728 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
13729 | v /= 10; |
13730 | i++; | |
13731 | } | |
13732 | strcpy (buf, tmp + 29 - i); | |
13733 | } | |
13734 | } | |
13735 | else | |
13736 | { | |
13737 | if (hex) | |
13738 | sprintf (buf, "0x%x", (unsigned int) disp); | |
13739 | else | |
13740 | sprintf (buf, "%d", (int) disp); | |
13741 | } | |
13742 | } | |
13743 | ||
5d669648 L |
13744 | /* Put DISP in BUF as signed hex number. */ |
13745 | ||
13746 | static void | |
13747 | print_displacement (char *buf, bfd_vma disp) | |
13748 | { | |
13749 | bfd_signed_vma val = disp; | |
13750 | char tmp[30]; | |
13751 | int i, j = 0; | |
13752 | ||
13753 | if (val < 0) | |
13754 | { | |
13755 | buf[j++] = '-'; | |
13756 | val = -disp; | |
13757 | ||
13758 | /* Check for possible overflow. */ | |
13759 | if (val < 0) | |
13760 | { | |
13761 | switch (address_mode) | |
13762 | { | |
13763 | case mode_64bit: | |
13764 | strcpy (buf + j, "0x8000000000000000"); | |
13765 | break; | |
13766 | case mode_32bit: | |
13767 | strcpy (buf + j, "0x80000000"); | |
13768 | break; | |
13769 | case mode_16bit: | |
13770 | strcpy (buf + j, "0x8000"); | |
13771 | break; | |
13772 | } | |
13773 | return; | |
13774 | } | |
13775 | } | |
13776 | ||
13777 | buf[j++] = '0'; | |
13778 | buf[j++] = 'x'; | |
13779 | ||
0af1713e | 13780 | sprintf_vma (tmp, (bfd_vma) val); |
5d669648 L |
13781 | for (i = 0; tmp[i] == '0'; i++) |
13782 | continue; | |
13783 | if (tmp[i] == '\0') | |
13784 | i--; | |
13785 | strcpy (buf + j, tmp + i); | |
13786 | } | |
13787 | ||
3f31e633 JB |
13788 | static void |
13789 | intel_operand_size (int bytemode, int sizeflag) | |
13790 | { | |
43234a1e L |
13791 | if (vex.evex |
13792 | && vex.b | |
13793 | && (bytemode == x_mode | |
13794 | || bytemode == evex_half_bcst_xmmq_mode)) | |
13795 | { | |
13796 | if (vex.w) | |
13797 | oappend ("QWORD PTR "); | |
13798 | else | |
13799 | oappend ("DWORD PTR "); | |
13800 | return; | |
13801 | } | |
3f31e633 JB |
13802 | switch (bytemode) |
13803 | { | |
13804 | case b_mode: | |
b6169b20 | 13805 | case b_swap_mode: |
42903f7f | 13806 | case dqb_mode: |
3f31e633 JB |
13807 | oappend ("BYTE PTR "); |
13808 | break; | |
13809 | case w_mode: | |
13810 | case dqw_mode: | |
13811 | oappend ("WORD PTR "); | |
13812 | break; | |
1a114b12 | 13813 | case stack_v_mode: |
7bb15c6f | 13814 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
3f31e633 JB |
13815 | { |
13816 | oappend ("QWORD PTR "); | |
3f31e633 JB |
13817 | break; |
13818 | } | |
13819 | /* FALLTHRU */ | |
13820 | case v_mode: | |
b6169b20 | 13821 | case v_swap_mode: |
3f31e633 | 13822 | case dq_mode: |
161a04f6 L |
13823 | USED_REX (REX_W); |
13824 | if (rex & REX_W) | |
3f31e633 | 13825 | oappend ("QWORD PTR "); |
3f31e633 | 13826 | else |
f16cd0d5 L |
13827 | { |
13828 | if ((sizeflag & DFLAG) || bytemode == dq_mode) | |
13829 | oappend ("DWORD PTR "); | |
13830 | else | |
13831 | oappend ("WORD PTR "); | |
13832 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13833 | } | |
3f31e633 | 13834 | break; |
52fd6d94 | 13835 | case z_mode: |
161a04f6 | 13836 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
13837 | *obufp++ = 'D'; |
13838 | oappend ("WORD PTR "); | |
161a04f6 | 13839 | if (!(rex & REX_W)) |
52fd6d94 JB |
13840 | used_prefixes |= (prefixes & PREFIX_DATA); |
13841 | break; | |
34b772a6 JB |
13842 | case a_mode: |
13843 | if (sizeflag & DFLAG) | |
13844 | oappend ("QWORD PTR "); | |
13845 | else | |
13846 | oappend ("DWORD PTR "); | |
13847 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13848 | break; | |
3f31e633 | 13849 | case d_mode: |
539f890d L |
13850 | case d_scalar_mode: |
13851 | case d_scalar_swap_mode: | |
fa99fab2 | 13852 | case d_swap_mode: |
42903f7f | 13853 | case dqd_mode: |
3f31e633 JB |
13854 | oappend ("DWORD PTR "); |
13855 | break; | |
13856 | case q_mode: | |
539f890d L |
13857 | case q_scalar_mode: |
13858 | case q_scalar_swap_mode: | |
b6169b20 | 13859 | case q_swap_mode: |
3f31e633 JB |
13860 | oappend ("QWORD PTR "); |
13861 | break; | |
13862 | case m_mode: | |
cb712a9e | 13863 | if (address_mode == mode_64bit) |
3f31e633 JB |
13864 | oappend ("QWORD PTR "); |
13865 | else | |
13866 | oappend ("DWORD PTR "); | |
13867 | break; | |
13868 | case f_mode: | |
13869 | if (sizeflag & DFLAG) | |
13870 | oappend ("FWORD PTR "); | |
13871 | else | |
13872 | oappend ("DWORD PTR "); | |
13873 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13874 | break; | |
13875 | case t_mode: | |
13876 | oappend ("TBYTE PTR "); | |
13877 | break; | |
13878 | case x_mode: | |
b6169b20 | 13879 | case x_swap_mode: |
43234a1e L |
13880 | case evex_x_gscat_mode: |
13881 | case evex_x_nobcst_mode: | |
c0f3af97 L |
13882 | if (need_vex) |
13883 | { | |
13884 | switch (vex.length) | |
13885 | { | |
13886 | case 128: | |
13887 | oappend ("XMMWORD PTR "); | |
13888 | break; | |
13889 | case 256: | |
13890 | oappend ("YMMWORD PTR "); | |
13891 | break; | |
43234a1e L |
13892 | case 512: |
13893 | oappend ("ZMMWORD PTR "); | |
13894 | break; | |
c0f3af97 L |
13895 | default: |
13896 | abort (); | |
13897 | } | |
13898 | } | |
13899 | else | |
13900 | oappend ("XMMWORD PTR "); | |
13901 | break; | |
13902 | case xmm_mode: | |
3f31e633 JB |
13903 | oappend ("XMMWORD PTR "); |
13904 | break; | |
43234a1e L |
13905 | case ymm_mode: |
13906 | oappend ("YMMWORD PTR "); | |
13907 | break; | |
c0f3af97 | 13908 | case xmmq_mode: |
43234a1e | 13909 | case evex_half_bcst_xmmq_mode: |
c0f3af97 L |
13910 | if (!need_vex) |
13911 | abort (); | |
13912 | ||
13913 | switch (vex.length) | |
13914 | { | |
13915 | case 128: | |
13916 | oappend ("QWORD PTR "); | |
13917 | break; | |
13918 | case 256: | |
13919 | oappend ("XMMWORD PTR "); | |
13920 | break; | |
43234a1e L |
13921 | case 512: |
13922 | oappend ("YMMWORD PTR "); | |
13923 | break; | |
c0f3af97 L |
13924 | default: |
13925 | abort (); | |
13926 | } | |
13927 | break; | |
6c30d220 L |
13928 | case xmm_mb_mode: |
13929 | if (!need_vex) | |
13930 | abort (); | |
13931 | ||
13932 | switch (vex.length) | |
13933 | { | |
13934 | case 128: | |
13935 | case 256: | |
43234a1e | 13936 | case 512: |
6c30d220 L |
13937 | oappend ("BYTE PTR "); |
13938 | break; | |
13939 | default: | |
13940 | abort (); | |
13941 | } | |
13942 | break; | |
13943 | case xmm_mw_mode: | |
13944 | if (!need_vex) | |
13945 | abort (); | |
13946 | ||
13947 | switch (vex.length) | |
13948 | { | |
13949 | case 128: | |
13950 | case 256: | |
43234a1e | 13951 | case 512: |
6c30d220 L |
13952 | oappend ("WORD PTR "); |
13953 | break; | |
13954 | default: | |
13955 | abort (); | |
13956 | } | |
13957 | break; | |
13958 | case xmm_md_mode: | |
13959 | if (!need_vex) | |
13960 | abort (); | |
13961 | ||
13962 | switch (vex.length) | |
13963 | { | |
13964 | case 128: | |
13965 | case 256: | |
43234a1e | 13966 | case 512: |
6c30d220 L |
13967 | oappend ("DWORD PTR "); |
13968 | break; | |
13969 | default: | |
13970 | abort (); | |
13971 | } | |
13972 | break; | |
13973 | case xmm_mq_mode: | |
13974 | if (!need_vex) | |
13975 | abort (); | |
13976 | ||
13977 | switch (vex.length) | |
13978 | { | |
13979 | case 128: | |
13980 | case 256: | |
43234a1e | 13981 | case 512: |
6c30d220 L |
13982 | oappend ("QWORD PTR "); |
13983 | break; | |
13984 | default: | |
13985 | abort (); | |
13986 | } | |
13987 | break; | |
13988 | case xmmdw_mode: | |
13989 | if (!need_vex) | |
13990 | abort (); | |
13991 | ||
13992 | switch (vex.length) | |
13993 | { | |
13994 | case 128: | |
13995 | oappend ("WORD PTR "); | |
13996 | break; | |
13997 | case 256: | |
13998 | oappend ("DWORD PTR "); | |
13999 | break; | |
43234a1e L |
14000 | case 512: |
14001 | oappend ("QWORD PTR "); | |
14002 | break; | |
6c30d220 L |
14003 | default: |
14004 | abort (); | |
14005 | } | |
14006 | break; | |
14007 | case xmmqd_mode: | |
14008 | if (!need_vex) | |
14009 | abort (); | |
14010 | ||
14011 | switch (vex.length) | |
14012 | { | |
14013 | case 128: | |
14014 | oappend ("DWORD PTR "); | |
14015 | break; | |
14016 | case 256: | |
14017 | oappend ("QWORD PTR "); | |
14018 | break; | |
43234a1e L |
14019 | case 512: |
14020 | oappend ("XMMWORD PTR "); | |
14021 | break; | |
6c30d220 L |
14022 | default: |
14023 | abort (); | |
14024 | } | |
14025 | break; | |
c0f3af97 L |
14026 | case ymmq_mode: |
14027 | if (!need_vex) | |
14028 | abort (); | |
14029 | ||
14030 | switch (vex.length) | |
14031 | { | |
14032 | case 128: | |
14033 | oappend ("QWORD PTR "); | |
14034 | break; | |
14035 | case 256: | |
14036 | oappend ("YMMWORD PTR "); | |
14037 | break; | |
43234a1e L |
14038 | case 512: |
14039 | oappend ("ZMMWORD PTR "); | |
14040 | break; | |
c0f3af97 L |
14041 | default: |
14042 | abort (); | |
14043 | } | |
14044 | break; | |
6c30d220 L |
14045 | case ymmxmm_mode: |
14046 | if (!need_vex) | |
14047 | abort (); | |
14048 | ||
14049 | switch (vex.length) | |
14050 | { | |
14051 | case 128: | |
14052 | case 256: | |
14053 | oappend ("XMMWORD PTR "); | |
14054 | break; | |
14055 | default: | |
14056 | abort (); | |
14057 | } | |
14058 | break; | |
fb9c77c7 L |
14059 | case o_mode: |
14060 | oappend ("OWORD PTR "); | |
14061 | break; | |
43234a1e | 14062 | case xmm_mdq_mode: |
0bfee649 | 14063 | case vex_w_dq_mode: |
1c480963 | 14064 | case vex_scalar_w_dq_mode: |
0bfee649 L |
14065 | if (!need_vex) |
14066 | abort (); | |
14067 | ||
14068 | if (vex.w) | |
14069 | oappend ("QWORD PTR "); | |
14070 | else | |
14071 | oappend ("DWORD PTR "); | |
14072 | break; | |
43234a1e L |
14073 | case vex_vsib_d_w_dq_mode: |
14074 | case vex_vsib_q_w_dq_mode: | |
14075 | if (!need_vex) | |
14076 | abort (); | |
14077 | ||
14078 | if (!vex.evex) | |
14079 | { | |
14080 | if (vex.w) | |
14081 | oappend ("QWORD PTR "); | |
14082 | else | |
14083 | oappend ("DWORD PTR "); | |
14084 | } | |
14085 | else | |
14086 | { | |
14087 | if (vex.length != 512) | |
14088 | abort (); | |
14089 | oappend ("ZMMWORD PTR "); | |
14090 | } | |
14091 | break; | |
14092 | case mask_mode: | |
14093 | if (!need_vex) | |
14094 | abort (); | |
14095 | /* Currently the only instructions, which allows either mask or | |
14096 | memory operand, are AVX512's KMOVW instructions. They need | |
14097 | Word-sized operand. */ | |
14098 | if (vex.w || vex.length != 128) | |
14099 | abort (); | |
14100 | oappend ("WORD PTR "); | |
14101 | break; | |
6c75cc62 | 14102 | case v_bnd_mode: |
3f31e633 JB |
14103 | default: |
14104 | break; | |
14105 | } | |
14106 | } | |
14107 | ||
252b5132 | 14108 | static void |
c0f3af97 | 14109 | OP_E_register (int bytemode, int sizeflag) |
252b5132 | 14110 | { |
c0f3af97 L |
14111 | int reg = modrm.rm; |
14112 | const char **names; | |
252b5132 | 14113 | |
c0f3af97 L |
14114 | USED_REX (REX_B); |
14115 | if ((rex & REX_B)) | |
14116 | reg += 8; | |
252b5132 | 14117 | |
b6169b20 L |
14118 | if ((sizeflag & SUFFIX_ALWAYS) |
14119 | && (bytemode == b_swap_mode || bytemode == v_swap_mode)) | |
14120 | swap_operand (); | |
14121 | ||
c0f3af97 | 14122 | switch (bytemode) |
252b5132 | 14123 | { |
c0f3af97 | 14124 | case b_mode: |
b6169b20 | 14125 | case b_swap_mode: |
c0f3af97 L |
14126 | USED_REX (0); |
14127 | if (rex) | |
14128 | names = names8rex; | |
14129 | else | |
14130 | names = names8; | |
14131 | break; | |
14132 | case w_mode: | |
14133 | names = names16; | |
14134 | break; | |
14135 | case d_mode: | |
14136 | names = names32; | |
14137 | break; | |
14138 | case q_mode: | |
14139 | names = names64; | |
14140 | break; | |
14141 | case m_mode: | |
6c75cc62 | 14142 | case v_bnd_mode: |
c0f3af97 L |
14143 | names = address_mode == mode_64bit ? names64 : names32; |
14144 | break; | |
7e8b059b L |
14145 | case bnd_mode: |
14146 | names = names_bnd; | |
14147 | break; | |
c0f3af97 | 14148 | case stack_v_mode: |
7bb15c6f | 14149 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
252b5132 | 14150 | { |
c0f3af97 | 14151 | names = names64; |
252b5132 | 14152 | break; |
252b5132 | 14153 | } |
c0f3af97 L |
14154 | bytemode = v_mode; |
14155 | /* FALLTHRU */ | |
14156 | case v_mode: | |
b6169b20 | 14157 | case v_swap_mode: |
c0f3af97 L |
14158 | case dq_mode: |
14159 | case dqb_mode: | |
14160 | case dqd_mode: | |
14161 | case dqw_mode: | |
14162 | USED_REX (REX_W); | |
14163 | if (rex & REX_W) | |
14164 | names = names64; | |
c0f3af97 | 14165 | else |
f16cd0d5 | 14166 | { |
7bb15c6f | 14167 | if ((sizeflag & DFLAG) |
f16cd0d5 L |
14168 | || (bytemode != v_mode |
14169 | && bytemode != v_swap_mode)) | |
14170 | names = names32; | |
14171 | else | |
14172 | names = names16; | |
14173 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14174 | } | |
c0f3af97 | 14175 | break; |
43234a1e L |
14176 | case mask_mode: |
14177 | names = names_mask; | |
14178 | break; | |
c0f3af97 L |
14179 | case 0: |
14180 | return; | |
14181 | default: | |
14182 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
252b5132 RH |
14183 | return; |
14184 | } | |
c0f3af97 L |
14185 | oappend (names[reg]); |
14186 | } | |
14187 | ||
14188 | static void | |
c1e679ec | 14189 | OP_E_memory (int bytemode, int sizeflag) |
c0f3af97 L |
14190 | { |
14191 | bfd_vma disp = 0; | |
14192 | int add = (rex & REX_B) ? 8 : 0; | |
14193 | int riprel = 0; | |
43234a1e L |
14194 | int shift; |
14195 | ||
14196 | if (vex.evex) | |
14197 | { | |
14198 | /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ | |
14199 | if (vex.b | |
14200 | && bytemode != x_mode | |
14201 | && bytemode != evex_half_bcst_xmmq_mode) | |
14202 | { | |
14203 | BadOp (); | |
14204 | return; | |
14205 | } | |
14206 | switch (bytemode) | |
14207 | { | |
14208 | case vex_vsib_d_w_dq_mode: | |
eaa9d1ad | 14209 | case vex_vsib_q_w_dq_mode: |
43234a1e L |
14210 | case evex_x_gscat_mode: |
14211 | case xmm_mdq_mode: | |
14212 | shift = vex.w ? 3 : 2; | |
14213 | break; | |
43234a1e L |
14214 | case x_mode: |
14215 | case evex_half_bcst_xmmq_mode: | |
14216 | if (vex.b) | |
14217 | { | |
14218 | shift = vex.w ? 3 : 2; | |
14219 | break; | |
14220 | } | |
14221 | /* Fall through if vex.b == 0. */ | |
14222 | case xmmqd_mode: | |
14223 | case xmmdw_mode: | |
14224 | case xmmq_mode: | |
14225 | case ymmq_mode: | |
14226 | case evex_x_nobcst_mode: | |
14227 | case x_swap_mode: | |
14228 | switch (vex.length) | |
14229 | { | |
14230 | case 128: | |
14231 | shift = 4; | |
14232 | break; | |
14233 | case 256: | |
14234 | shift = 5; | |
14235 | break; | |
14236 | case 512: | |
14237 | shift = 6; | |
14238 | break; | |
14239 | default: | |
14240 | abort (); | |
14241 | } | |
14242 | break; | |
14243 | case ymm_mode: | |
14244 | shift = 5; | |
14245 | break; | |
14246 | case xmm_mode: | |
14247 | shift = 4; | |
14248 | break; | |
14249 | case xmm_mq_mode: | |
14250 | case q_mode: | |
14251 | case q_scalar_mode: | |
14252 | case q_swap_mode: | |
14253 | case q_scalar_swap_mode: | |
14254 | shift = 3; | |
14255 | break; | |
14256 | case dqd_mode: | |
14257 | case xmm_md_mode: | |
14258 | case d_mode: | |
14259 | case d_scalar_mode: | |
14260 | case d_swap_mode: | |
14261 | case d_scalar_swap_mode: | |
14262 | shift = 2; | |
14263 | break; | |
14264 | case xmm_mw_mode: | |
14265 | shift = 1; | |
14266 | break; | |
14267 | case xmm_mb_mode: | |
14268 | shift = 0; | |
14269 | break; | |
14270 | default: | |
14271 | abort (); | |
14272 | } | |
14273 | /* Make necessary corrections to shift for modes that need it. | |
14274 | For these modes we currently have shift 4, 5 or 6 depending on | |
14275 | vex.length (it corresponds to xmmword, ymmword or zmmword | |
14276 | operand). We might want to make it 3, 4 or 5 (e.g. for | |
14277 | xmmq_mode). In case of broadcast enabled the corrections | |
14278 | aren't needed, as element size is always 32 or 64 bits. */ | |
14279 | if (bytemode == xmmq_mode | |
14280 | || (bytemode == evex_half_bcst_xmmq_mode | |
14281 | && !vex.b)) | |
14282 | shift -= 1; | |
14283 | else if (bytemode == xmmqd_mode) | |
14284 | shift -= 2; | |
14285 | else if (bytemode == xmmdw_mode) | |
14286 | shift -= 3; | |
14287 | } | |
14288 | else | |
14289 | shift = 0; | |
252b5132 | 14290 | |
c0f3af97 | 14291 | USED_REX (REX_B); |
3f31e633 JB |
14292 | if (intel_syntax) |
14293 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
14294 | append_seg (); |
14295 | ||
5d669648 | 14296 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 14297 | { |
5d669648 L |
14298 | /* 32/64 bit address mode */ |
14299 | int havedisp; | |
252b5132 RH |
14300 | int havesib; |
14301 | int havebase; | |
0f7da397 | 14302 | int haveindex; |
20afcfb7 | 14303 | int needindex; |
82c18208 | 14304 | int base, rbase; |
91d6fa6a | 14305 | int vindex = 0; |
252b5132 | 14306 | int scale = 0; |
7e8b059b L |
14307 | int addr32flag = !((sizeflag & AFLAG) |
14308 | || bytemode == v_bnd_mode | |
14309 | || bytemode == bnd_mode); | |
6c30d220 L |
14310 | const char **indexes64 = names64; |
14311 | const char **indexes32 = names32; | |
252b5132 RH |
14312 | |
14313 | havesib = 0; | |
14314 | havebase = 1; | |
0f7da397 | 14315 | haveindex = 0; |
7967e09e | 14316 | base = modrm.rm; |
252b5132 RH |
14317 | |
14318 | if (base == 4) | |
14319 | { | |
14320 | havesib = 1; | |
dfc8cf43 | 14321 | vindex = sib.index; |
161a04f6 L |
14322 | USED_REX (REX_X); |
14323 | if (rex & REX_X) | |
91d6fa6a | 14324 | vindex += 8; |
6c30d220 L |
14325 | switch (bytemode) |
14326 | { | |
14327 | case vex_vsib_d_w_dq_mode: | |
14328 | case vex_vsib_q_w_dq_mode: | |
14329 | if (!need_vex) | |
14330 | abort (); | |
43234a1e L |
14331 | if (vex.evex) |
14332 | { | |
14333 | if (!vex.v) | |
14334 | vindex += 16; | |
14335 | } | |
6c30d220 L |
14336 | |
14337 | haveindex = 1; | |
14338 | switch (vex.length) | |
14339 | { | |
14340 | case 128: | |
7bb15c6f | 14341 | indexes64 = indexes32 = names_xmm; |
6c30d220 L |
14342 | break; |
14343 | case 256: | |
14344 | if (!vex.w || bytemode == vex_vsib_q_w_dq_mode) | |
7bb15c6f | 14345 | indexes64 = indexes32 = names_ymm; |
6c30d220 | 14346 | else |
7bb15c6f | 14347 | indexes64 = indexes32 = names_xmm; |
6c30d220 | 14348 | break; |
43234a1e L |
14349 | case 512: |
14350 | if (!vex.w || bytemode == vex_vsib_q_w_dq_mode) | |
14351 | indexes64 = indexes32 = names_zmm; | |
14352 | else | |
14353 | indexes64 = indexes32 = names_ymm; | |
14354 | break; | |
6c30d220 L |
14355 | default: |
14356 | abort (); | |
14357 | } | |
14358 | break; | |
14359 | default: | |
14360 | haveindex = vindex != 4; | |
14361 | break; | |
14362 | } | |
14363 | scale = sib.scale; | |
14364 | base = sib.base; | |
252b5132 RH |
14365 | codep++; |
14366 | } | |
82c18208 | 14367 | rbase = base + add; |
252b5132 | 14368 | |
7967e09e | 14369 | switch (modrm.mod) |
252b5132 RH |
14370 | { |
14371 | case 0: | |
82c18208 | 14372 | if (base == 5) |
252b5132 RH |
14373 | { |
14374 | havebase = 0; | |
cb712a9e | 14375 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
14376 | riprel = 1; |
14377 | disp = get32s (); | |
252b5132 RH |
14378 | } |
14379 | break; | |
14380 | case 1: | |
14381 | FETCH_DATA (the_info, codep + 1); | |
14382 | disp = *codep++; | |
14383 | if ((disp & 0x80) != 0) | |
14384 | disp -= 0x100; | |
43234a1e L |
14385 | if (vex.evex && shift > 0) |
14386 | disp <<= shift; | |
252b5132 RH |
14387 | break; |
14388 | case 2: | |
52b15da3 | 14389 | disp = get32s (); |
252b5132 RH |
14390 | break; |
14391 | } | |
14392 | ||
20afcfb7 L |
14393 | /* In 32bit mode, we need index register to tell [offset] from |
14394 | [eiz*1 + offset]. */ | |
14395 | needindex = (havesib | |
14396 | && !havebase | |
14397 | && !haveindex | |
14398 | && address_mode == mode_32bit); | |
14399 | havedisp = (havebase | |
14400 | || needindex | |
14401 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 14402 | |
252b5132 | 14403 | if (!intel_syntax) |
82c18208 | 14404 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 14405 | { |
5d669648 L |
14406 | if (havedisp || riprel) |
14407 | print_displacement (scratchbuf, disp); | |
14408 | else | |
14409 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 14410 | oappend (scratchbuf); |
52b15da3 JH |
14411 | if (riprel) |
14412 | { | |
14413 | set_op (disp, 1); | |
87767711 | 14414 | oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)"); |
52b15da3 | 14415 | } |
db6eb5be | 14416 | } |
2da11e11 | 14417 | |
7e8b059b L |
14418 | if ((havebase || haveindex || riprel) |
14419 | && (bytemode != v_bnd_mode) | |
14420 | && (bytemode != bnd_mode)) | |
87767711 JB |
14421 | used_prefixes |= PREFIX_ADDR; |
14422 | ||
5d669648 | 14423 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 14424 | { |
252b5132 | 14425 | *obufp++ = open_char; |
52b15da3 | 14426 | if (intel_syntax && riprel) |
185b1163 L |
14427 | { |
14428 | set_op (disp, 1); | |
87767711 | 14429 | oappend (sizeflag & AFLAG ? "rip" : "eip"); |
185b1163 | 14430 | } |
db6eb5be | 14431 | *obufp = '\0'; |
252b5132 | 14432 | if (havebase) |
7e8b059b | 14433 | oappend (address_mode == mode_64bit && !addr32flag |
82c18208 | 14434 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
14435 | if (havesib) |
14436 | { | |
db51cc60 L |
14437 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
14438 | print index to tell base + index from base. */ | |
14439 | if (scale != 0 | |
20afcfb7 | 14440 | || needindex |
db51cc60 L |
14441 | || haveindex |
14442 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 14443 | { |
9306ca4a | 14444 | if (!intel_syntax || havebase) |
db6eb5be | 14445 | { |
9306ca4a JB |
14446 | *obufp++ = separator_char; |
14447 | *obufp = '\0'; | |
db6eb5be | 14448 | } |
db51cc60 | 14449 | if (haveindex) |
7e8b059b | 14450 | oappend (address_mode == mode_64bit && !addr32flag |
6c30d220 | 14451 | ? indexes64[vindex] : indexes32[vindex]); |
db51cc60 | 14452 | else |
7e8b059b | 14453 | oappend (address_mode == mode_64bit && !addr32flag |
db51cc60 L |
14454 | ? index64 : index32); |
14455 | ||
db6eb5be AM |
14456 | *obufp++ = scale_char; |
14457 | *obufp = '\0'; | |
14458 | sprintf (scratchbuf, "%d", 1 << scale); | |
14459 | oappend (scratchbuf); | |
14460 | } | |
252b5132 | 14461 | } |
185b1163 | 14462 | if (intel_syntax |
82c18208 | 14463 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 14464 | { |
db51cc60 | 14465 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
14466 | { |
14467 | *obufp++ = '+'; | |
14468 | *obufp = '\0'; | |
14469 | } | |
05203043 | 14470 | else if (modrm.mod != 1 && disp != -disp) |
3d456fa1 JB |
14471 | { |
14472 | *obufp++ = '-'; | |
14473 | *obufp = '\0'; | |
14474 | disp = - (bfd_signed_vma) disp; | |
14475 | } | |
14476 | ||
db51cc60 L |
14477 | if (havedisp) |
14478 | print_displacement (scratchbuf, disp); | |
14479 | else | |
14480 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
14481 | oappend (scratchbuf); |
14482 | } | |
252b5132 RH |
14483 | |
14484 | *obufp++ = close_char; | |
db6eb5be | 14485 | *obufp = '\0'; |
252b5132 RH |
14486 | } |
14487 | else if (intel_syntax) | |
db6eb5be | 14488 | { |
82c18208 | 14489 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 14490 | { |
252b5132 RH |
14491 | if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS |
14492 | | PREFIX_ES | PREFIX_FS | PREFIX_GS)) | |
14493 | ; | |
14494 | else | |
14495 | { | |
d708bcba | 14496 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
14497 | oappend (":"); |
14498 | } | |
52b15da3 | 14499 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
14500 | oappend (scratchbuf); |
14501 | } | |
14502 | } | |
252b5132 RH |
14503 | } |
14504 | else | |
f16cd0d5 L |
14505 | { |
14506 | /* 16 bit address mode */ | |
14507 | used_prefixes |= prefixes & PREFIX_ADDR; | |
7967e09e | 14508 | switch (modrm.mod) |
252b5132 RH |
14509 | { |
14510 | case 0: | |
7967e09e | 14511 | if (modrm.rm == 6) |
252b5132 RH |
14512 | { |
14513 | disp = get16 (); | |
14514 | if ((disp & 0x8000) != 0) | |
14515 | disp -= 0x10000; | |
14516 | } | |
14517 | break; | |
14518 | case 1: | |
14519 | FETCH_DATA (the_info, codep + 1); | |
14520 | disp = *codep++; | |
14521 | if ((disp & 0x80) != 0) | |
14522 | disp -= 0x100; | |
14523 | break; | |
14524 | case 2: | |
14525 | disp = get16 (); | |
14526 | if ((disp & 0x8000) != 0) | |
14527 | disp -= 0x10000; | |
14528 | break; | |
14529 | } | |
14530 | ||
14531 | if (!intel_syntax) | |
7967e09e | 14532 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 14533 | { |
5d669648 | 14534 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
14535 | oappend (scratchbuf); |
14536 | } | |
252b5132 | 14537 | |
7967e09e | 14538 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
14539 | { |
14540 | *obufp++ = open_char; | |
db6eb5be | 14541 | *obufp = '\0'; |
7967e09e | 14542 | oappend (index16[modrm.rm]); |
5d669648 L |
14543 | if (intel_syntax |
14544 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 14545 | { |
5d669648 | 14546 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
14547 | { |
14548 | *obufp++ = '+'; | |
14549 | *obufp = '\0'; | |
14550 | } | |
7967e09e | 14551 | else if (modrm.mod != 1) |
3d456fa1 JB |
14552 | { |
14553 | *obufp++ = '-'; | |
14554 | *obufp = '\0'; | |
14555 | disp = - (bfd_signed_vma) disp; | |
14556 | } | |
14557 | ||
5d669648 | 14558 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
14559 | oappend (scratchbuf); |
14560 | } | |
14561 | ||
db6eb5be AM |
14562 | *obufp++ = close_char; |
14563 | *obufp = '\0'; | |
252b5132 | 14564 | } |
3d456fa1 JB |
14565 | else if (intel_syntax) |
14566 | { | |
14567 | if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | |
14568 | | PREFIX_ES | PREFIX_FS | PREFIX_GS)) | |
14569 | ; | |
14570 | else | |
14571 | { | |
14572 | oappend (names_seg[ds_reg - es_reg]); | |
14573 | oappend (":"); | |
14574 | } | |
14575 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
14576 | oappend (scratchbuf); | |
14577 | } | |
252b5132 | 14578 | } |
43234a1e L |
14579 | if (vex.evex && vex.b |
14580 | && (bytemode == x_mode | |
14581 | || bytemode == evex_half_bcst_xmmq_mode)) | |
14582 | { | |
14583 | if (vex.w || bytemode == evex_half_bcst_xmmq_mode) | |
14584 | oappend ("{1to8}"); | |
14585 | else | |
14586 | oappend ("{1to16}"); | |
14587 | } | |
252b5132 RH |
14588 | } |
14589 | ||
c0f3af97 | 14590 | static void |
8b3f93e7 | 14591 | OP_E (int bytemode, int sizeflag) |
c0f3af97 L |
14592 | { |
14593 | /* Skip mod/rm byte. */ | |
14594 | MODRM_CHECK; | |
14595 | codep++; | |
14596 | ||
14597 | if (modrm.mod == 3) | |
14598 | OP_E_register (bytemode, sizeflag); | |
14599 | else | |
c1e679ec | 14600 | OP_E_memory (bytemode, sizeflag); |
c0f3af97 L |
14601 | } |
14602 | ||
252b5132 | 14603 | static void |
26ca5450 | 14604 | OP_G (int bytemode, int sizeflag) |
252b5132 | 14605 | { |
52b15da3 | 14606 | int add = 0; |
161a04f6 L |
14607 | USED_REX (REX_R); |
14608 | if (rex & REX_R) | |
52b15da3 | 14609 | add += 8; |
252b5132 RH |
14610 | switch (bytemode) |
14611 | { | |
14612 | case b_mode: | |
52b15da3 JH |
14613 | USED_REX (0); |
14614 | if (rex) | |
7967e09e | 14615 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 14616 | else |
7967e09e | 14617 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
14618 | break; |
14619 | case w_mode: | |
7967e09e | 14620 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
14621 | break; |
14622 | case d_mode: | |
7967e09e | 14623 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
14624 | break; |
14625 | case q_mode: | |
7967e09e | 14626 | oappend (names64[modrm.reg + add]); |
252b5132 | 14627 | break; |
7e8b059b L |
14628 | case bnd_mode: |
14629 | oappend (names_bnd[modrm.reg]); | |
14630 | break; | |
252b5132 | 14631 | case v_mode: |
9306ca4a | 14632 | case dq_mode: |
42903f7f L |
14633 | case dqb_mode: |
14634 | case dqd_mode: | |
9306ca4a | 14635 | case dqw_mode: |
161a04f6 L |
14636 | USED_REX (REX_W); |
14637 | if (rex & REX_W) | |
7967e09e | 14638 | oappend (names64[modrm.reg + add]); |
252b5132 | 14639 | else |
f16cd0d5 L |
14640 | { |
14641 | if ((sizeflag & DFLAG) || bytemode != v_mode) | |
14642 | oappend (names32[modrm.reg + add]); | |
14643 | else | |
14644 | oappend (names16[modrm.reg + add]); | |
14645 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14646 | } | |
252b5132 | 14647 | break; |
90700ea2 | 14648 | case m_mode: |
cb712a9e | 14649 | if (address_mode == mode_64bit) |
7967e09e | 14650 | oappend (names64[modrm.reg + add]); |
90700ea2 | 14651 | else |
7967e09e | 14652 | oappend (names32[modrm.reg + add]); |
90700ea2 | 14653 | break; |
43234a1e L |
14654 | case mask_mode: |
14655 | oappend (names_mask[modrm.reg + add]); | |
14656 | break; | |
252b5132 RH |
14657 | default: |
14658 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14659 | break; | |
14660 | } | |
14661 | } | |
14662 | ||
52b15da3 | 14663 | static bfd_vma |
26ca5450 | 14664 | get64 (void) |
52b15da3 | 14665 | { |
5dd0794d | 14666 | bfd_vma x; |
52b15da3 | 14667 | #ifdef BFD64 |
5dd0794d AM |
14668 | unsigned int a; |
14669 | unsigned int b; | |
14670 | ||
52b15da3 JH |
14671 | FETCH_DATA (the_info, codep + 8); |
14672 | a = *codep++ & 0xff; | |
14673 | a |= (*codep++ & 0xff) << 8; | |
14674 | a |= (*codep++ & 0xff) << 16; | |
14675 | a |= (*codep++ & 0xff) << 24; | |
5dd0794d | 14676 | b = *codep++ & 0xff; |
52b15da3 JH |
14677 | b |= (*codep++ & 0xff) << 8; |
14678 | b |= (*codep++ & 0xff) << 16; | |
14679 | b |= (*codep++ & 0xff) << 24; | |
14680 | x = a + ((bfd_vma) b << 32); | |
14681 | #else | |
6608db57 | 14682 | abort (); |
5dd0794d | 14683 | x = 0; |
52b15da3 JH |
14684 | #endif |
14685 | return x; | |
14686 | } | |
14687 | ||
14688 | static bfd_signed_vma | |
26ca5450 | 14689 | get32 (void) |
252b5132 | 14690 | { |
52b15da3 | 14691 | bfd_signed_vma x = 0; |
252b5132 RH |
14692 | |
14693 | FETCH_DATA (the_info, codep + 4); | |
52b15da3 JH |
14694 | x = *codep++ & (bfd_signed_vma) 0xff; |
14695 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
14696 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
14697 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
14698 | return x; | |
14699 | } | |
14700 | ||
14701 | static bfd_signed_vma | |
26ca5450 | 14702 | get32s (void) |
52b15da3 JH |
14703 | { |
14704 | bfd_signed_vma x = 0; | |
14705 | ||
14706 | FETCH_DATA (the_info, codep + 4); | |
14707 | x = *codep++ & (bfd_signed_vma) 0xff; | |
14708 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
14709 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
14710 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
14711 | ||
14712 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); | |
14713 | ||
252b5132 RH |
14714 | return x; |
14715 | } | |
14716 | ||
14717 | static int | |
26ca5450 | 14718 | get16 (void) |
252b5132 RH |
14719 | { |
14720 | int x = 0; | |
14721 | ||
14722 | FETCH_DATA (the_info, codep + 2); | |
14723 | x = *codep++ & 0xff; | |
14724 | x |= (*codep++ & 0xff) << 8; | |
14725 | return x; | |
14726 | } | |
14727 | ||
14728 | static void | |
26ca5450 | 14729 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
14730 | { |
14731 | op_index[op_ad] = op_ad; | |
cb712a9e | 14732 | if (address_mode == mode_64bit) |
7081ff04 AJ |
14733 | { |
14734 | op_address[op_ad] = op; | |
14735 | op_riprel[op_ad] = riprel; | |
14736 | } | |
14737 | else | |
14738 | { | |
14739 | /* Mask to get a 32-bit address. */ | |
14740 | op_address[op_ad] = op & 0xffffffff; | |
14741 | op_riprel[op_ad] = riprel & 0xffffffff; | |
14742 | } | |
252b5132 RH |
14743 | } |
14744 | ||
14745 | static void | |
26ca5450 | 14746 | OP_REG (int code, int sizeflag) |
252b5132 | 14747 | { |
2da11e11 | 14748 | const char *s; |
9b60702d | 14749 | int add; |
de882298 RM |
14750 | |
14751 | switch (code) | |
14752 | { | |
14753 | case es_reg: case ss_reg: case cs_reg: | |
14754 | case ds_reg: case fs_reg: case gs_reg: | |
14755 | oappend (names_seg[code - es_reg]); | |
14756 | return; | |
14757 | } | |
14758 | ||
161a04f6 L |
14759 | USED_REX (REX_B); |
14760 | if (rex & REX_B) | |
52b15da3 | 14761 | add = 8; |
9b60702d L |
14762 | else |
14763 | add = 0; | |
52b15da3 JH |
14764 | |
14765 | switch (code) | |
14766 | { | |
52b15da3 JH |
14767 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
14768 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
14769 | s = names16[code - ax_reg + add]; | |
14770 | break; | |
52b15da3 JH |
14771 | case al_reg: case ah_reg: case cl_reg: case ch_reg: |
14772 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
14773 | USED_REX (0); | |
14774 | if (rex) | |
14775 | s = names8rex[code - al_reg + add]; | |
14776 | else | |
14777 | s = names8[code - al_reg]; | |
14778 | break; | |
6439fc28 AM |
14779 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
14780 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
7bb15c6f | 14781 | if (address_mode == mode_64bit |
6c067bbb | 14782 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
14783 | { |
14784 | s = names64[code - rAX_reg + add]; | |
14785 | break; | |
14786 | } | |
14787 | code += eAX_reg - rAX_reg; | |
6608db57 | 14788 | /* Fall through. */ |
52b15da3 JH |
14789 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
14790 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
14791 | USED_REX (REX_W); |
14792 | if (rex & REX_W) | |
52b15da3 | 14793 | s = names64[code - eAX_reg + add]; |
52b15da3 | 14794 | else |
f16cd0d5 L |
14795 | { |
14796 | if (sizeflag & DFLAG) | |
14797 | s = names32[code - eAX_reg + add]; | |
14798 | else | |
14799 | s = names16[code - eAX_reg + add]; | |
14800 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14801 | } | |
52b15da3 | 14802 | break; |
52b15da3 JH |
14803 | default: |
14804 | s = INTERNAL_DISASSEMBLER_ERROR; | |
14805 | break; | |
14806 | } | |
14807 | oappend (s); | |
14808 | } | |
14809 | ||
14810 | static void | |
26ca5450 | 14811 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
14812 | { |
14813 | const char *s; | |
252b5132 RH |
14814 | |
14815 | switch (code) | |
14816 | { | |
14817 | case indir_dx_reg: | |
d708bcba | 14818 | if (intel_syntax) |
52fd6d94 | 14819 | s = "dx"; |
d708bcba | 14820 | else |
db6eb5be | 14821 | s = "(%dx)"; |
252b5132 RH |
14822 | break; |
14823 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: | |
14824 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
14825 | s = names16[code - ax_reg]; | |
14826 | break; | |
14827 | case es_reg: case ss_reg: case cs_reg: | |
14828 | case ds_reg: case fs_reg: case gs_reg: | |
14829 | s = names_seg[code - es_reg]; | |
14830 | break; | |
14831 | case al_reg: case ah_reg: case cl_reg: case ch_reg: | |
14832 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
52b15da3 JH |
14833 | USED_REX (0); |
14834 | if (rex) | |
14835 | s = names8rex[code - al_reg]; | |
14836 | else | |
14837 | s = names8[code - al_reg]; | |
252b5132 RH |
14838 | break; |
14839 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: | |
14840 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
14841 | USED_REX (REX_W); |
14842 | if (rex & REX_W) | |
52b15da3 | 14843 | s = names64[code - eAX_reg]; |
252b5132 | 14844 | else |
f16cd0d5 L |
14845 | { |
14846 | if (sizeflag & DFLAG) | |
14847 | s = names32[code - eAX_reg]; | |
14848 | else | |
14849 | s = names16[code - eAX_reg]; | |
14850 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14851 | } | |
252b5132 | 14852 | break; |
52fd6d94 | 14853 | case z_mode_ax_reg: |
161a04f6 | 14854 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
14855 | s = *names32; |
14856 | else | |
14857 | s = *names16; | |
161a04f6 | 14858 | if (!(rex & REX_W)) |
52fd6d94 JB |
14859 | used_prefixes |= (prefixes & PREFIX_DATA); |
14860 | break; | |
252b5132 RH |
14861 | default: |
14862 | s = INTERNAL_DISASSEMBLER_ERROR; | |
14863 | break; | |
14864 | } | |
14865 | oappend (s); | |
14866 | } | |
14867 | ||
14868 | static void | |
26ca5450 | 14869 | OP_I (int bytemode, int sizeflag) |
252b5132 | 14870 | { |
52b15da3 JH |
14871 | bfd_signed_vma op; |
14872 | bfd_signed_vma mask = -1; | |
252b5132 RH |
14873 | |
14874 | switch (bytemode) | |
14875 | { | |
14876 | case b_mode: | |
14877 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
14878 | op = *codep++; |
14879 | mask = 0xff; | |
14880 | break; | |
14881 | case q_mode: | |
cb712a9e | 14882 | if (address_mode == mode_64bit) |
6439fc28 AM |
14883 | { |
14884 | op = get32s (); | |
14885 | break; | |
14886 | } | |
6608db57 | 14887 | /* Fall through. */ |
252b5132 | 14888 | case v_mode: |
161a04f6 L |
14889 | USED_REX (REX_W); |
14890 | if (rex & REX_W) | |
52b15da3 | 14891 | op = get32s (); |
252b5132 | 14892 | else |
52b15da3 | 14893 | { |
f16cd0d5 L |
14894 | if (sizeflag & DFLAG) |
14895 | { | |
14896 | op = get32 (); | |
14897 | mask = 0xffffffff; | |
14898 | } | |
14899 | else | |
14900 | { | |
14901 | op = get16 (); | |
14902 | mask = 0xfffff; | |
14903 | } | |
14904 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 14905 | } |
252b5132 RH |
14906 | break; |
14907 | case w_mode: | |
52b15da3 | 14908 | mask = 0xfffff; |
252b5132 RH |
14909 | op = get16 (); |
14910 | break; | |
9306ca4a JB |
14911 | case const_1_mode: |
14912 | if (intel_syntax) | |
6c067bbb | 14913 | oappend ("1"); |
9306ca4a | 14914 | return; |
252b5132 RH |
14915 | default: |
14916 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14917 | return; | |
14918 | } | |
14919 | ||
52b15da3 JH |
14920 | op &= mask; |
14921 | scratchbuf[0] = '$'; | |
d708bcba | 14922 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 14923 | oappend_maybe_intel (scratchbuf); |
52b15da3 JH |
14924 | scratchbuf[0] = '\0'; |
14925 | } | |
14926 | ||
14927 | static void | |
26ca5450 | 14928 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 JH |
14929 | { |
14930 | bfd_signed_vma op; | |
14931 | bfd_signed_vma mask = -1; | |
14932 | ||
cb712a9e | 14933 | if (address_mode != mode_64bit) |
6439fc28 AM |
14934 | { |
14935 | OP_I (bytemode, sizeflag); | |
14936 | return; | |
14937 | } | |
14938 | ||
52b15da3 JH |
14939 | switch (bytemode) |
14940 | { | |
14941 | case b_mode: | |
14942 | FETCH_DATA (the_info, codep + 1); | |
14943 | op = *codep++; | |
14944 | mask = 0xff; | |
14945 | break; | |
14946 | case v_mode: | |
161a04f6 L |
14947 | USED_REX (REX_W); |
14948 | if (rex & REX_W) | |
52b15da3 | 14949 | op = get64 (); |
52b15da3 JH |
14950 | else |
14951 | { | |
f16cd0d5 L |
14952 | if (sizeflag & DFLAG) |
14953 | { | |
14954 | op = get32 (); | |
14955 | mask = 0xffffffff; | |
14956 | } | |
14957 | else | |
14958 | { | |
14959 | op = get16 (); | |
14960 | mask = 0xfffff; | |
14961 | } | |
14962 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 14963 | } |
52b15da3 JH |
14964 | break; |
14965 | case w_mode: | |
14966 | mask = 0xfffff; | |
14967 | op = get16 (); | |
14968 | break; | |
14969 | default: | |
14970 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14971 | return; | |
14972 | } | |
14973 | ||
14974 | op &= mask; | |
14975 | scratchbuf[0] = '$'; | |
d708bcba | 14976 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 14977 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
14978 | scratchbuf[0] = '\0'; |
14979 | } | |
14980 | ||
14981 | static void | |
26ca5450 | 14982 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 14983 | { |
52b15da3 | 14984 | bfd_signed_vma op; |
252b5132 RH |
14985 | |
14986 | switch (bytemode) | |
14987 | { | |
14988 | case b_mode: | |
e3949f17 | 14989 | case b_T_mode: |
252b5132 RH |
14990 | FETCH_DATA (the_info, codep + 1); |
14991 | op = *codep++; | |
14992 | if ((op & 0x80) != 0) | |
14993 | op -= 0x100; | |
e3949f17 L |
14994 | if (bytemode == b_T_mode) |
14995 | { | |
14996 | if (address_mode != mode_64bit | |
7bb15c6f | 14997 | || !((sizeflag & DFLAG) || (rex & REX_W))) |
e3949f17 | 14998 | { |
6c067bbb RM |
14999 | /* The operand-size prefix is overridden by a REX prefix. */ |
15000 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
e3949f17 L |
15001 | op &= 0xffffffff; |
15002 | else | |
15003 | op &= 0xffff; | |
15004 | } | |
15005 | } | |
15006 | else | |
15007 | { | |
15008 | if (!(rex & REX_W)) | |
15009 | { | |
15010 | if (sizeflag & DFLAG) | |
15011 | op &= 0xffffffff; | |
15012 | else | |
15013 | op &= 0xffff; | |
15014 | } | |
15015 | } | |
252b5132 RH |
15016 | break; |
15017 | case v_mode: | |
7bb15c6f RM |
15018 | /* The operand-size prefix is overridden by a REX prefix. */ |
15019 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
52b15da3 | 15020 | op = get32s (); |
252b5132 | 15021 | else |
d9e3625e | 15022 | op = get16 (); |
252b5132 RH |
15023 | break; |
15024 | default: | |
15025 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15026 | return; | |
15027 | } | |
52b15da3 JH |
15028 | |
15029 | scratchbuf[0] = '$'; | |
15030 | print_operand_value (scratchbuf + 1, 1, op); | |
9ce09ba2 | 15031 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15032 | } |
15033 | ||
15034 | static void | |
26ca5450 | 15035 | OP_J (int bytemode, int sizeflag) |
252b5132 | 15036 | { |
52b15da3 | 15037 | bfd_vma disp; |
7081ff04 | 15038 | bfd_vma mask = -1; |
65ca155d | 15039 | bfd_vma segment = 0; |
252b5132 RH |
15040 | |
15041 | switch (bytemode) | |
15042 | { | |
15043 | case b_mode: | |
15044 | FETCH_DATA (the_info, codep + 1); | |
15045 | disp = *codep++; | |
15046 | if ((disp & 0x80) != 0) | |
15047 | disp -= 0x100; | |
15048 | break; | |
15049 | case v_mode: | |
f16cd0d5 | 15050 | USED_REX (REX_W); |
161a04f6 | 15051 | if ((sizeflag & DFLAG) || (rex & REX_W)) |
52b15da3 | 15052 | disp = get32s (); |
252b5132 RH |
15053 | else |
15054 | { | |
15055 | disp = get16 (); | |
206717e8 L |
15056 | if ((disp & 0x8000) != 0) |
15057 | disp -= 0x10000; | |
65ca155d L |
15058 | /* In 16bit mode, address is wrapped around at 64k within |
15059 | the same segment. Otherwise, a data16 prefix on a jump | |
15060 | instruction means that the pc is masked to 16 bits after | |
15061 | the displacement is added! */ | |
15062 | mask = 0xffff; | |
15063 | if ((prefixes & PREFIX_DATA) == 0) | |
15064 | segment = ((start_pc + codep - start_codep) | |
15065 | & ~((bfd_vma) 0xffff)); | |
252b5132 | 15066 | } |
f16cd0d5 L |
15067 | if (!(rex & REX_W)) |
15068 | used_prefixes |= (prefixes & PREFIX_DATA); | |
252b5132 RH |
15069 | break; |
15070 | default: | |
15071 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15072 | return; | |
15073 | } | |
42d5f9c6 | 15074 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
52b15da3 JH |
15075 | set_op (disp, 0); |
15076 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
15077 | oappend (scratchbuf); |
15078 | } | |
15079 | ||
252b5132 | 15080 | static void |
ed7841b3 | 15081 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 15082 | { |
ed7841b3 | 15083 | if (bytemode == w_mode) |
7967e09e | 15084 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 15085 | else |
7967e09e | 15086 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
15087 | } |
15088 | ||
15089 | static void | |
26ca5450 | 15090 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
15091 | { |
15092 | int seg, offset; | |
15093 | ||
c608c12e | 15094 | if (sizeflag & DFLAG) |
252b5132 | 15095 | { |
c608c12e AM |
15096 | offset = get32 (); |
15097 | seg = get16 (); | |
252b5132 | 15098 | } |
c608c12e AM |
15099 | else |
15100 | { | |
15101 | offset = get16 (); | |
15102 | seg = get16 (); | |
15103 | } | |
7d421014 | 15104 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 15105 | if (intel_syntax) |
3f31e633 | 15106 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
15107 | else |
15108 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 15109 | oappend (scratchbuf); |
252b5132 RH |
15110 | } |
15111 | ||
252b5132 | 15112 | static void |
3f31e633 | 15113 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 15114 | { |
52b15da3 | 15115 | bfd_vma off; |
252b5132 | 15116 | |
3f31e633 JB |
15117 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
15118 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
15119 | append_seg (); |
15120 | ||
cb712a9e | 15121 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
15122 | off = get32 (); |
15123 | else | |
15124 | off = get16 (); | |
15125 | ||
15126 | if (intel_syntax) | |
15127 | { | |
15128 | if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | |
db6eb5be | 15129 | | PREFIX_ES | PREFIX_FS | PREFIX_GS))) |
252b5132 | 15130 | { |
d708bcba | 15131 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
15132 | oappend (":"); |
15133 | } | |
15134 | } | |
52b15da3 JH |
15135 | print_operand_value (scratchbuf, 1, off); |
15136 | oappend (scratchbuf); | |
15137 | } | |
6439fc28 | 15138 | |
52b15da3 | 15139 | static void |
3f31e633 | 15140 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
15141 | { |
15142 | bfd_vma off; | |
15143 | ||
539e75ad L |
15144 | if (address_mode != mode_64bit |
15145 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
15146 | { |
15147 | OP_OFF (bytemode, sizeflag); | |
15148 | return; | |
15149 | } | |
15150 | ||
3f31e633 JB |
15151 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
15152 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
15153 | append_seg (); |
15154 | ||
6608db57 | 15155 | off = get64 (); |
52b15da3 JH |
15156 | |
15157 | if (intel_syntax) | |
15158 | { | |
15159 | if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | |
db6eb5be | 15160 | | PREFIX_ES | PREFIX_FS | PREFIX_GS))) |
52b15da3 | 15161 | { |
d708bcba | 15162 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
15163 | oappend (":"); |
15164 | } | |
15165 | } | |
15166 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
15167 | oappend (scratchbuf); |
15168 | } | |
15169 | ||
15170 | static void | |
26ca5450 | 15171 | ptr_reg (int code, int sizeflag) |
252b5132 | 15172 | { |
2da11e11 | 15173 | const char *s; |
d708bcba | 15174 | |
1d9f512f | 15175 | *obufp++ = open_char; |
20f0a1fc | 15176 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 15177 | if (address_mode == mode_64bit) |
c1a64871 JH |
15178 | { |
15179 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 15180 | s = names32[code - eAX_reg]; |
c1a64871 | 15181 | else |
db6eb5be | 15182 | s = names64[code - eAX_reg]; |
c1a64871 | 15183 | } |
52b15da3 | 15184 | else if (sizeflag & AFLAG) |
252b5132 RH |
15185 | s = names32[code - eAX_reg]; |
15186 | else | |
15187 | s = names16[code - eAX_reg]; | |
15188 | oappend (s); | |
1d9f512f AM |
15189 | *obufp++ = close_char; |
15190 | *obufp = 0; | |
252b5132 RH |
15191 | } |
15192 | ||
15193 | static void | |
26ca5450 | 15194 | OP_ESreg (int code, int sizeflag) |
252b5132 | 15195 | { |
9306ca4a | 15196 | if (intel_syntax) |
52fd6d94 JB |
15197 | { |
15198 | switch (codep[-1]) | |
15199 | { | |
15200 | case 0x6d: /* insw/insl */ | |
15201 | intel_operand_size (z_mode, sizeflag); | |
15202 | break; | |
15203 | case 0xa5: /* movsw/movsl/movsq */ | |
15204 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
15205 | case 0xab: /* stosw/stosl */ | |
15206 | case 0xaf: /* scasw/scasl */ | |
15207 | intel_operand_size (v_mode, sizeflag); | |
15208 | break; | |
15209 | default: | |
15210 | intel_operand_size (b_mode, sizeflag); | |
15211 | } | |
15212 | } | |
9ce09ba2 | 15213 | oappend_maybe_intel ("%es:"); |
252b5132 RH |
15214 | ptr_reg (code, sizeflag); |
15215 | } | |
15216 | ||
15217 | static void | |
26ca5450 | 15218 | OP_DSreg (int code, int sizeflag) |
252b5132 | 15219 | { |
9306ca4a | 15220 | if (intel_syntax) |
52fd6d94 JB |
15221 | { |
15222 | switch (codep[-1]) | |
15223 | { | |
15224 | case 0x6f: /* outsw/outsl */ | |
15225 | intel_operand_size (z_mode, sizeflag); | |
15226 | break; | |
15227 | case 0xa5: /* movsw/movsl/movsq */ | |
15228 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
15229 | case 0xad: /* lodsw/lodsl/lodsq */ | |
15230 | intel_operand_size (v_mode, sizeflag); | |
15231 | break; | |
15232 | default: | |
15233 | intel_operand_size (b_mode, sizeflag); | |
15234 | } | |
15235 | } | |
252b5132 RH |
15236 | if ((prefixes |
15237 | & (PREFIX_CS | |
15238 | | PREFIX_DS | |
15239 | | PREFIX_SS | |
15240 | | PREFIX_ES | |
15241 | | PREFIX_FS | |
15242 | | PREFIX_GS)) == 0) | |
15243 | prefixes |= PREFIX_DS; | |
6608db57 | 15244 | append_seg (); |
252b5132 RH |
15245 | ptr_reg (code, sizeflag); |
15246 | } | |
15247 | ||
252b5132 | 15248 | static void |
26ca5450 | 15249 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15250 | { |
9b60702d | 15251 | int add; |
161a04f6 | 15252 | if (rex & REX_R) |
c4a530c5 | 15253 | { |
161a04f6 | 15254 | USED_REX (REX_R); |
c4a530c5 JB |
15255 | add = 8; |
15256 | } | |
cb712a9e | 15257 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 15258 | { |
f16cd0d5 | 15259 | all_prefixes[last_lock_prefix] = 0; |
c4a530c5 JB |
15260 | used_prefixes |= PREFIX_LOCK; |
15261 | add = 8; | |
15262 | } | |
9b60702d L |
15263 | else |
15264 | add = 0; | |
7967e09e | 15265 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
9ce09ba2 | 15266 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15267 | } |
15268 | ||
252b5132 | 15269 | static void |
26ca5450 | 15270 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15271 | { |
9b60702d | 15272 | int add; |
161a04f6 L |
15273 | USED_REX (REX_R); |
15274 | if (rex & REX_R) | |
52b15da3 | 15275 | add = 8; |
9b60702d L |
15276 | else |
15277 | add = 0; | |
d708bcba | 15278 | if (intel_syntax) |
7967e09e | 15279 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
d708bcba | 15280 | else |
7967e09e | 15281 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
15282 | oappend (scratchbuf); |
15283 | } | |
15284 | ||
252b5132 | 15285 | static void |
26ca5450 | 15286 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15287 | { |
7967e09e | 15288 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
9ce09ba2 | 15289 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15290 | } |
15291 | ||
15292 | static void | |
6f74c397 | 15293 | OP_R (int bytemode, int sizeflag) |
252b5132 | 15294 | { |
7967e09e | 15295 | if (modrm.mod == 3) |
2da11e11 AM |
15296 | OP_E (bytemode, sizeflag); |
15297 | else | |
6608db57 | 15298 | BadOp (); |
252b5132 RH |
15299 | } |
15300 | ||
15301 | static void | |
26ca5450 | 15302 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15303 | { |
b9733481 L |
15304 | int reg = modrm.reg; |
15305 | const char **names; | |
15306 | ||
041bd2e0 JH |
15307 | used_prefixes |= (prefixes & PREFIX_DATA); |
15308 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 15309 | { |
b9733481 | 15310 | names = names_xmm; |
161a04f6 L |
15311 | USED_REX (REX_R); |
15312 | if (rex & REX_R) | |
b9733481 | 15313 | reg += 8; |
20f0a1fc | 15314 | } |
041bd2e0 | 15315 | else |
b9733481 L |
15316 | names = names_mm; |
15317 | oappend (names[reg]); | |
252b5132 RH |
15318 | } |
15319 | ||
c608c12e | 15320 | static void |
c0f3af97 | 15321 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 15322 | { |
b9733481 L |
15323 | int reg = modrm.reg; |
15324 | const char **names; | |
15325 | ||
161a04f6 L |
15326 | USED_REX (REX_R); |
15327 | if (rex & REX_R) | |
b9733481 | 15328 | reg += 8; |
43234a1e L |
15329 | if (vex.evex) |
15330 | { | |
15331 | if (!vex.r) | |
15332 | reg += 16; | |
15333 | } | |
15334 | ||
539f890d L |
15335 | if (need_vex |
15336 | && bytemode != xmm_mode | |
43234a1e L |
15337 | && bytemode != xmmq_mode |
15338 | && bytemode != evex_half_bcst_xmmq_mode | |
15339 | && bytemode != ymm_mode | |
539f890d | 15340 | && bytemode != scalar_mode) |
c0f3af97 L |
15341 | { |
15342 | switch (vex.length) | |
15343 | { | |
15344 | case 128: | |
b9733481 | 15345 | names = names_xmm; |
c0f3af97 L |
15346 | break; |
15347 | case 256: | |
6c30d220 L |
15348 | if (vex.w || bytemode != vex_vsib_q_w_dq_mode) |
15349 | names = names_ymm; | |
15350 | else | |
15351 | names = names_xmm; | |
c0f3af97 | 15352 | break; |
43234a1e L |
15353 | case 512: |
15354 | names = names_zmm; | |
15355 | break; | |
c0f3af97 L |
15356 | default: |
15357 | abort (); | |
15358 | } | |
15359 | } | |
43234a1e L |
15360 | else if (bytemode == xmmq_mode |
15361 | || bytemode == evex_half_bcst_xmmq_mode) | |
15362 | { | |
15363 | switch (vex.length) | |
15364 | { | |
15365 | case 128: | |
15366 | case 256: | |
15367 | names = names_xmm; | |
15368 | break; | |
15369 | case 512: | |
15370 | names = names_ymm; | |
15371 | break; | |
15372 | default: | |
15373 | abort (); | |
15374 | } | |
15375 | } | |
15376 | else if (bytemode == ymm_mode) | |
15377 | names = names_ymm; | |
c0f3af97 | 15378 | else |
b9733481 L |
15379 | names = names_xmm; |
15380 | oappend (names[reg]); | |
c608c12e AM |
15381 | } |
15382 | ||
252b5132 | 15383 | static void |
26ca5450 | 15384 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 15385 | { |
b9733481 L |
15386 | int reg; |
15387 | const char **names; | |
15388 | ||
7967e09e | 15389 | if (modrm.mod != 3) |
252b5132 | 15390 | { |
b6169b20 L |
15391 | if (intel_syntax |
15392 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
9306ca4a JB |
15393 | { |
15394 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
15395 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 15396 | } |
252b5132 RH |
15397 | OP_E (bytemode, sizeflag); |
15398 | return; | |
15399 | } | |
15400 | ||
b6169b20 L |
15401 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
15402 | swap_operand (); | |
15403 | ||
6608db57 | 15404 | /* Skip mod/rm byte. */ |
4bba6815 | 15405 | MODRM_CHECK; |
252b5132 | 15406 | codep++; |
041bd2e0 | 15407 | used_prefixes |= (prefixes & PREFIX_DATA); |
b9733481 | 15408 | reg = modrm.rm; |
041bd2e0 | 15409 | if (prefixes & PREFIX_DATA) |
20f0a1fc | 15410 | { |
b9733481 | 15411 | names = names_xmm; |
161a04f6 L |
15412 | USED_REX (REX_B); |
15413 | if (rex & REX_B) | |
b9733481 | 15414 | reg += 8; |
20f0a1fc | 15415 | } |
041bd2e0 | 15416 | else |
b9733481 L |
15417 | names = names_mm; |
15418 | oappend (names[reg]); | |
252b5132 RH |
15419 | } |
15420 | ||
246c51aa L |
15421 | /* cvt* are the only instructions in sse2 which have |
15422 | both SSE and MMX operands and also have 0x66 prefix | |
15423 | in their opcode. 0x66 was originally used to differentiate | |
15424 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
15425 | cvt* separately using OP_EMC and OP_MXC */ |
15426 | static void | |
15427 | OP_EMC (int bytemode, int sizeflag) | |
15428 | { | |
7967e09e | 15429 | if (modrm.mod != 3) |
4d9567e0 MM |
15430 | { |
15431 | if (intel_syntax && bytemode == v_mode) | |
15432 | { | |
15433 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
15434 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 15435 | } |
4d9567e0 MM |
15436 | OP_E (bytemode, sizeflag); |
15437 | return; | |
15438 | } | |
246c51aa | 15439 | |
4d9567e0 MM |
15440 | /* Skip mod/rm byte. */ |
15441 | MODRM_CHECK; | |
15442 | codep++; | |
15443 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 15444 | oappend (names_mm[modrm.rm]); |
4d9567e0 MM |
15445 | } |
15446 | ||
15447 | static void | |
15448 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15449 | { | |
15450 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 15451 | oappend (names_mm[modrm.reg]); |
4d9567e0 MM |
15452 | } |
15453 | ||
c608c12e | 15454 | static void |
26ca5450 | 15455 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 15456 | { |
b9733481 L |
15457 | int reg; |
15458 | const char **names; | |
d6f574e0 L |
15459 | |
15460 | /* Skip mod/rm byte. */ | |
15461 | MODRM_CHECK; | |
15462 | codep++; | |
15463 | ||
7967e09e | 15464 | if (modrm.mod != 3) |
c608c12e | 15465 | { |
c1e679ec | 15466 | OP_E_memory (bytemode, sizeflag); |
c608c12e AM |
15467 | return; |
15468 | } | |
d6f574e0 | 15469 | |
b9733481 | 15470 | reg = modrm.rm; |
161a04f6 L |
15471 | USED_REX (REX_B); |
15472 | if (rex & REX_B) | |
b9733481 | 15473 | reg += 8; |
43234a1e L |
15474 | if (vex.evex) |
15475 | { | |
15476 | USED_REX (REX_X); | |
15477 | if ((rex & REX_X)) | |
15478 | reg += 16; | |
15479 | } | |
c608c12e | 15480 | |
b6169b20 | 15481 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 L |
15482 | && (bytemode == x_swap_mode |
15483 | || bytemode == d_swap_mode | |
7bb15c6f | 15484 | || bytemode == d_scalar_swap_mode |
539f890d L |
15485 | || bytemode == q_swap_mode |
15486 | || bytemode == q_scalar_swap_mode)) | |
b6169b20 L |
15487 | swap_operand (); |
15488 | ||
c0f3af97 L |
15489 | if (need_vex |
15490 | && bytemode != xmm_mode | |
6c30d220 L |
15491 | && bytemode != xmmdw_mode |
15492 | && bytemode != xmmqd_mode | |
15493 | && bytemode != xmm_mb_mode | |
15494 | && bytemode != xmm_mw_mode | |
15495 | && bytemode != xmm_md_mode | |
15496 | && bytemode != xmm_mq_mode | |
43234a1e | 15497 | && bytemode != xmm_mdq_mode |
539f890d | 15498 | && bytemode != xmmq_mode |
43234a1e L |
15499 | && bytemode != evex_half_bcst_xmmq_mode |
15500 | && bytemode != ymm_mode | |
539f890d | 15501 | && bytemode != d_scalar_mode |
7bb15c6f | 15502 | && bytemode != d_scalar_swap_mode |
539f890d | 15503 | && bytemode != q_scalar_mode |
1c480963 L |
15504 | && bytemode != q_scalar_swap_mode |
15505 | && bytemode != vex_scalar_w_dq_mode) | |
c0f3af97 L |
15506 | { |
15507 | switch (vex.length) | |
15508 | { | |
15509 | case 128: | |
b9733481 | 15510 | names = names_xmm; |
c0f3af97 L |
15511 | break; |
15512 | case 256: | |
b9733481 | 15513 | names = names_ymm; |
c0f3af97 | 15514 | break; |
43234a1e L |
15515 | case 512: |
15516 | names = names_zmm; | |
15517 | break; | |
c0f3af97 L |
15518 | default: |
15519 | abort (); | |
15520 | } | |
15521 | } | |
43234a1e L |
15522 | else if (bytemode == xmmq_mode |
15523 | || bytemode == evex_half_bcst_xmmq_mode) | |
15524 | { | |
15525 | switch (vex.length) | |
15526 | { | |
15527 | case 128: | |
15528 | case 256: | |
15529 | names = names_xmm; | |
15530 | break; | |
15531 | case 512: | |
15532 | names = names_ymm; | |
15533 | break; | |
15534 | default: | |
15535 | abort (); | |
15536 | } | |
15537 | } | |
15538 | else if (bytemode == ymm_mode) | |
15539 | names = names_ymm; | |
c0f3af97 | 15540 | else |
b9733481 L |
15541 | names = names_xmm; |
15542 | oappend (names[reg]); | |
c608c12e AM |
15543 | } |
15544 | ||
252b5132 | 15545 | static void |
26ca5450 | 15546 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 15547 | { |
7967e09e | 15548 | if (modrm.mod == 3) |
2da11e11 AM |
15549 | OP_EM (bytemode, sizeflag); |
15550 | else | |
6608db57 | 15551 | BadOp (); |
252b5132 RH |
15552 | } |
15553 | ||
992aaec9 | 15554 | static void |
26ca5450 | 15555 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 15556 | { |
7967e09e | 15557 | if (modrm.mod == 3) |
992aaec9 AM |
15558 | OP_EX (bytemode, sizeflag); |
15559 | else | |
6608db57 | 15560 | BadOp (); |
992aaec9 AM |
15561 | } |
15562 | ||
cc0ec051 AM |
15563 | static void |
15564 | OP_M (int bytemode, int sizeflag) | |
15565 | { | |
7967e09e | 15566 | if (modrm.mod == 3) |
75413a22 L |
15567 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
15568 | BadOp (); | |
cc0ec051 AM |
15569 | else |
15570 | OP_E (bytemode, sizeflag); | |
15571 | } | |
15572 | ||
15573 | static void | |
15574 | OP_0f07 (int bytemode, int sizeflag) | |
15575 | { | |
7967e09e | 15576 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
15577 | BadOp (); |
15578 | else | |
15579 | OP_E (bytemode, sizeflag); | |
15580 | } | |
15581 | ||
46e883c5 | 15582 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 15583 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 15584 | |
cc0ec051 | 15585 | static void |
46e883c5 | 15586 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 15587 | { |
8b38ad71 L |
15588 | if ((prefixes & PREFIX_DATA) != 0 |
15589 | || (rex != 0 | |
15590 | && rex != 0x48 | |
15591 | && address_mode == mode_64bit)) | |
46e883c5 L |
15592 | OP_REG (bytemode, sizeflag); |
15593 | else | |
15594 | strcpy (obuf, "nop"); | |
15595 | } | |
15596 | ||
15597 | static void | |
15598 | NOP_Fixup2 (int bytemode, int sizeflag) | |
15599 | { | |
8b38ad71 L |
15600 | if ((prefixes & PREFIX_DATA) != 0 |
15601 | || (rex != 0 | |
15602 | && rex != 0x48 | |
15603 | && address_mode == mode_64bit)) | |
46e883c5 | 15604 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
15605 | } |
15606 | ||
84037f8c | 15607 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
15608 | /* 00 */ NULL, NULL, NULL, NULL, |
15609 | /* 04 */ NULL, NULL, NULL, NULL, | |
15610 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 15611 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
15612 | /* 10 */ NULL, NULL, NULL, NULL, |
15613 | /* 14 */ NULL, NULL, NULL, NULL, | |
15614 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 15615 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
15616 | /* 20 */ NULL, NULL, NULL, NULL, |
15617 | /* 24 */ NULL, NULL, NULL, NULL, | |
15618 | /* 28 */ NULL, NULL, NULL, NULL, | |
15619 | /* 2C */ NULL, NULL, NULL, NULL, | |
15620 | /* 30 */ NULL, NULL, NULL, NULL, | |
15621 | /* 34 */ NULL, NULL, NULL, NULL, | |
15622 | /* 38 */ NULL, NULL, NULL, NULL, | |
15623 | /* 3C */ NULL, NULL, NULL, NULL, | |
15624 | /* 40 */ NULL, NULL, NULL, NULL, | |
15625 | /* 44 */ NULL, NULL, NULL, NULL, | |
15626 | /* 48 */ NULL, NULL, NULL, NULL, | |
15627 | /* 4C */ NULL, NULL, NULL, NULL, | |
15628 | /* 50 */ NULL, NULL, NULL, NULL, | |
15629 | /* 54 */ NULL, NULL, NULL, NULL, | |
15630 | /* 58 */ NULL, NULL, NULL, NULL, | |
15631 | /* 5C */ NULL, NULL, NULL, NULL, | |
15632 | /* 60 */ NULL, NULL, NULL, NULL, | |
15633 | /* 64 */ NULL, NULL, NULL, NULL, | |
15634 | /* 68 */ NULL, NULL, NULL, NULL, | |
15635 | /* 6C */ NULL, NULL, NULL, NULL, | |
15636 | /* 70 */ NULL, NULL, NULL, NULL, | |
15637 | /* 74 */ NULL, NULL, NULL, NULL, | |
15638 | /* 78 */ NULL, NULL, NULL, NULL, | |
15639 | /* 7C */ NULL, NULL, NULL, NULL, | |
15640 | /* 80 */ NULL, NULL, NULL, NULL, | |
15641 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
15642 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
15643 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
15644 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
15645 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
15646 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
15647 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
15648 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
15649 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
15650 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
15651 | /* AC */ NULL, NULL, "pfacc", NULL, | |
15652 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 15653 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 15654 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
15655 | /* BC */ NULL, NULL, NULL, "pavgusb", |
15656 | /* C0 */ NULL, NULL, NULL, NULL, | |
15657 | /* C4 */ NULL, NULL, NULL, NULL, | |
15658 | /* C8 */ NULL, NULL, NULL, NULL, | |
15659 | /* CC */ NULL, NULL, NULL, NULL, | |
15660 | /* D0 */ NULL, NULL, NULL, NULL, | |
15661 | /* D4 */ NULL, NULL, NULL, NULL, | |
15662 | /* D8 */ NULL, NULL, NULL, NULL, | |
15663 | /* DC */ NULL, NULL, NULL, NULL, | |
15664 | /* E0 */ NULL, NULL, NULL, NULL, | |
15665 | /* E4 */ NULL, NULL, NULL, NULL, | |
15666 | /* E8 */ NULL, NULL, NULL, NULL, | |
15667 | /* EC */ NULL, NULL, NULL, NULL, | |
15668 | /* F0 */ NULL, NULL, NULL, NULL, | |
15669 | /* F4 */ NULL, NULL, NULL, NULL, | |
15670 | /* F8 */ NULL, NULL, NULL, NULL, | |
15671 | /* FC */ NULL, NULL, NULL, NULL, | |
15672 | }; | |
15673 | ||
15674 | static void | |
26ca5450 | 15675 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
15676 | { |
15677 | const char *mnemonic; | |
15678 | ||
15679 | FETCH_DATA (the_info, codep + 1); | |
15680 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
15681 | place where an 8-bit immediate would normally go. ie. the last | |
15682 | byte of the instruction. */ | |
ea397f5b | 15683 | obufp = mnemonicendp; |
c608c12e | 15684 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 15685 | if (mnemonic) |
2da11e11 | 15686 | oappend (mnemonic); |
252b5132 RH |
15687 | else |
15688 | { | |
15689 | /* Since a variable sized modrm/sib chunk is between the start | |
15690 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
15691 | all the modrm processing first, and don't know until now that | |
15692 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
15693 | op_out[0][0] = '\0'; |
15694 | op_out[1][0] = '\0'; | |
6608db57 | 15695 | BadOp (); |
252b5132 | 15696 | } |
ea397f5b | 15697 | mnemonicendp = obufp; |
252b5132 | 15698 | } |
c608c12e | 15699 | |
ea397f5b L |
15700 | static struct op simd_cmp_op[] = |
15701 | { | |
15702 | { STRING_COMMA_LEN ("eq") }, | |
15703 | { STRING_COMMA_LEN ("lt") }, | |
15704 | { STRING_COMMA_LEN ("le") }, | |
15705 | { STRING_COMMA_LEN ("unord") }, | |
15706 | { STRING_COMMA_LEN ("neq") }, | |
15707 | { STRING_COMMA_LEN ("nlt") }, | |
15708 | { STRING_COMMA_LEN ("nle") }, | |
15709 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
15710 | }; |
15711 | ||
15712 | static void | |
ad19981d | 15713 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
15714 | { |
15715 | unsigned int cmp_type; | |
15716 | ||
15717 | FETCH_DATA (the_info, codep + 1); | |
15718 | cmp_type = *codep++ & 0xff; | |
c0f3af97 | 15719 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 15720 | { |
ad19981d | 15721 | char suffix [3]; |
ea397f5b | 15722 | char *p = mnemonicendp - 2; |
ad19981d L |
15723 | suffix[0] = p[0]; |
15724 | suffix[1] = p[1]; | |
15725 | suffix[2] = '\0'; | |
ea397f5b L |
15726 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
15727 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
c608c12e AM |
15728 | } |
15729 | else | |
15730 | { | |
ad19981d L |
15731 | /* We have a reserved extension byte. Output it directly. */ |
15732 | scratchbuf[0] = '$'; | |
15733 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 15734 | oappend_maybe_intel (scratchbuf); |
ad19981d | 15735 | scratchbuf[0] = '\0'; |
c608c12e AM |
15736 | } |
15737 | } | |
15738 | ||
ca164297 | 15739 | static void |
b844680a L |
15740 | OP_Mwait (int bytemode ATTRIBUTE_UNUSED, |
15741 | int sizeflag ATTRIBUTE_UNUSED) | |
15742 | { | |
15743 | /* mwait %eax,%ecx */ | |
15744 | if (!intel_syntax) | |
15745 | { | |
15746 | const char **names = (address_mode == mode_64bit | |
15747 | ? names64 : names32); | |
15748 | strcpy (op_out[0], names[0]); | |
15749 | strcpy (op_out[1], names[1]); | |
15750 | two_source_ops = 1; | |
15751 | } | |
15752 | /* Skip mod/rm byte. */ | |
15753 | MODRM_CHECK; | |
15754 | codep++; | |
15755 | } | |
15756 | ||
15757 | static void | |
15758 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
15759 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 15760 | { |
b844680a L |
15761 | /* monitor %eax,%ecx,%edx" */ |
15762 | if (!intel_syntax) | |
ca164297 | 15763 | { |
b844680a | 15764 | const char **op1_names; |
cb712a9e L |
15765 | const char **names = (address_mode == mode_64bit |
15766 | ? names64 : names32); | |
1d9f512f | 15767 | |
b844680a L |
15768 | if (!(prefixes & PREFIX_ADDR)) |
15769 | op1_names = (address_mode == mode_16bit | |
15770 | ? names16 : names); | |
ca164297 L |
15771 | else |
15772 | { | |
b844680a | 15773 | /* Remove "addr16/addr32". */ |
f16cd0d5 | 15774 | all_prefixes[last_addr_prefix] = 0; |
b844680a L |
15775 | op1_names = (address_mode != mode_32bit |
15776 | ? names32 : names16); | |
15777 | used_prefixes |= PREFIX_ADDR; | |
ca164297 | 15778 | } |
b844680a L |
15779 | strcpy (op_out[0], op1_names[0]); |
15780 | strcpy (op_out[1], names[1]); | |
15781 | strcpy (op_out[2], names[2]); | |
15782 | two_source_ops = 1; | |
ca164297 | 15783 | } |
b844680a L |
15784 | /* Skip mod/rm byte. */ |
15785 | MODRM_CHECK; | |
15786 | codep++; | |
30123838 JB |
15787 | } |
15788 | ||
6608db57 KH |
15789 | static void |
15790 | BadOp (void) | |
2da11e11 | 15791 | { |
6608db57 KH |
15792 | /* Throw away prefixes and 1st. opcode byte. */ |
15793 | codep = insn_codep + 1; | |
2da11e11 AM |
15794 | oappend ("(bad)"); |
15795 | } | |
4cc91dba | 15796 | |
35c52694 L |
15797 | static void |
15798 | REP_Fixup (int bytemode, int sizeflag) | |
15799 | { | |
15800 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
15801 | lods and stos. */ | |
35c52694 | 15802 | if (prefixes & PREFIX_REPZ) |
f16cd0d5 | 15803 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
35c52694 L |
15804 | |
15805 | switch (bytemode) | |
15806 | { | |
15807 | case al_reg: | |
15808 | case eAX_reg: | |
15809 | case indir_dx_reg: | |
15810 | OP_IMREG (bytemode, sizeflag); | |
15811 | break; | |
15812 | case eDI_reg: | |
15813 | OP_ESreg (bytemode, sizeflag); | |
15814 | break; | |
15815 | case eSI_reg: | |
15816 | OP_DSreg (bytemode, sizeflag); | |
15817 | break; | |
15818 | default: | |
15819 | abort (); | |
15820 | break; | |
15821 | } | |
15822 | } | |
f5804c90 | 15823 | |
7e8b059b L |
15824 | /* For BND-prefixed instructions 0xF2 prefix should be displayed as |
15825 | "bnd". */ | |
15826 | ||
15827 | static void | |
15828 | BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15829 | { | |
15830 | if (prefixes & PREFIX_REPNZ) | |
15831 | all_prefixes[last_repnz_prefix] = BND_PREFIX; | |
15832 | } | |
15833 | ||
42164a71 L |
15834 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
15835 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. | |
15836 | */ | |
15837 | ||
15838 | static void | |
15839 | HLE_Fixup1 (int bytemode, int sizeflag) | |
15840 | { | |
15841 | if (modrm.mod != 3 | |
15842 | && (prefixes & PREFIX_LOCK) != 0) | |
15843 | { | |
15844 | if (prefixes & PREFIX_REPZ) | |
15845 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15846 | if (prefixes & PREFIX_REPNZ) | |
15847 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15848 | } | |
15849 | ||
15850 | OP_E (bytemode, sizeflag); | |
15851 | } | |
15852 | ||
15853 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as | |
15854 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. | |
15855 | */ | |
15856 | ||
15857 | static void | |
15858 | HLE_Fixup2 (int bytemode, int sizeflag) | |
15859 | { | |
15860 | if (modrm.mod != 3) | |
15861 | { | |
15862 | if (prefixes & PREFIX_REPZ) | |
15863 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15864 | if (prefixes & PREFIX_REPNZ) | |
15865 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15866 | } | |
15867 | ||
15868 | OP_E (bytemode, sizeflag); | |
15869 | } | |
15870 | ||
15871 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as | |
15872 | "xrelease" for memory operand. No check for LOCK prefix. */ | |
15873 | ||
15874 | static void | |
15875 | HLE_Fixup3 (int bytemode, int sizeflag) | |
15876 | { | |
15877 | if (modrm.mod != 3 | |
15878 | && last_repz_prefix > last_repnz_prefix | |
15879 | && (prefixes & PREFIX_REPZ) != 0) | |
15880 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15881 | ||
15882 | OP_E (bytemode, sizeflag); | |
15883 | } | |
15884 | ||
f5804c90 L |
15885 | static void |
15886 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
15887 | { | |
161a04f6 L |
15888 | USED_REX (REX_W); |
15889 | if (rex & REX_W) | |
f5804c90 L |
15890 | { |
15891 | /* Change cmpxchg8b to cmpxchg16b. */ | |
ea397f5b L |
15892 | char *p = mnemonicendp - 2; |
15893 | mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 15894 | bytemode = o_mode; |
f5804c90 | 15895 | } |
42164a71 L |
15896 | else if ((prefixes & PREFIX_LOCK) != 0) |
15897 | { | |
15898 | if (prefixes & PREFIX_REPZ) | |
15899 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15900 | if (prefixes & PREFIX_REPNZ) | |
15901 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15902 | } | |
15903 | ||
f5804c90 L |
15904 | OP_M (bytemode, sizeflag); |
15905 | } | |
42903f7f L |
15906 | |
15907 | static void | |
15908 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
15909 | { | |
b9733481 L |
15910 | const char **names; |
15911 | ||
c0f3af97 L |
15912 | if (need_vex) |
15913 | { | |
15914 | switch (vex.length) | |
15915 | { | |
15916 | case 128: | |
b9733481 | 15917 | names = names_xmm; |
c0f3af97 L |
15918 | break; |
15919 | case 256: | |
b9733481 | 15920 | names = names_ymm; |
c0f3af97 L |
15921 | break; |
15922 | default: | |
15923 | abort (); | |
15924 | } | |
15925 | } | |
15926 | else | |
b9733481 L |
15927 | names = names_xmm; |
15928 | oappend (names[reg]); | |
42903f7f | 15929 | } |
381d071f L |
15930 | |
15931 | static void | |
15932 | CRC32_Fixup (int bytemode, int sizeflag) | |
15933 | { | |
15934 | /* Add proper suffix to "crc32". */ | |
ea397f5b | 15935 | char *p = mnemonicendp; |
381d071f L |
15936 | |
15937 | switch (bytemode) | |
15938 | { | |
15939 | case b_mode: | |
20592a94 | 15940 | if (intel_syntax) |
ea397f5b | 15941 | goto skip; |
20592a94 | 15942 | |
381d071f L |
15943 | *p++ = 'b'; |
15944 | break; | |
15945 | case v_mode: | |
20592a94 | 15946 | if (intel_syntax) |
ea397f5b | 15947 | goto skip; |
20592a94 | 15948 | |
381d071f L |
15949 | USED_REX (REX_W); |
15950 | if (rex & REX_W) | |
15951 | *p++ = 'q'; | |
7bb15c6f | 15952 | else |
f16cd0d5 L |
15953 | { |
15954 | if (sizeflag & DFLAG) | |
15955 | *p++ = 'l'; | |
15956 | else | |
15957 | *p++ = 'w'; | |
15958 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15959 | } | |
381d071f L |
15960 | break; |
15961 | default: | |
15962 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15963 | break; | |
15964 | } | |
ea397f5b | 15965 | mnemonicendp = p; |
381d071f L |
15966 | *p = '\0'; |
15967 | ||
ea397f5b | 15968 | skip: |
381d071f L |
15969 | if (modrm.mod == 3) |
15970 | { | |
15971 | int add; | |
15972 | ||
15973 | /* Skip mod/rm byte. */ | |
15974 | MODRM_CHECK; | |
15975 | codep++; | |
15976 | ||
15977 | USED_REX (REX_B); | |
15978 | add = (rex & REX_B) ? 8 : 0; | |
15979 | if (bytemode == b_mode) | |
15980 | { | |
15981 | USED_REX (0); | |
15982 | if (rex) | |
15983 | oappend (names8rex[modrm.rm + add]); | |
15984 | else | |
15985 | oappend (names8[modrm.rm + add]); | |
15986 | } | |
15987 | else | |
15988 | { | |
15989 | USED_REX (REX_W); | |
15990 | if (rex & REX_W) | |
15991 | oappend (names64[modrm.rm + add]); | |
15992 | else if ((prefixes & PREFIX_DATA)) | |
15993 | oappend (names16[modrm.rm + add]); | |
15994 | else | |
15995 | oappend (names32[modrm.rm + add]); | |
15996 | } | |
15997 | } | |
15998 | else | |
9344ff29 | 15999 | OP_E (bytemode, sizeflag); |
381d071f | 16000 | } |
85f10a01 | 16001 | |
eacc9c89 L |
16002 | static void |
16003 | FXSAVE_Fixup (int bytemode, int sizeflag) | |
16004 | { | |
16005 | /* Add proper suffix to "fxsave" and "fxrstor". */ | |
16006 | USED_REX (REX_W); | |
16007 | if (rex & REX_W) | |
16008 | { | |
16009 | char *p = mnemonicendp; | |
16010 | *p++ = '6'; | |
16011 | *p++ = '4'; | |
16012 | *p = '\0'; | |
16013 | mnemonicendp = p; | |
16014 | } | |
16015 | OP_M (bytemode, sizeflag); | |
16016 | } | |
16017 | ||
c0f3af97 L |
16018 | /* Display the destination register operand for instructions with |
16019 | VEX. */ | |
16020 | ||
16021 | static void | |
16022 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16023 | { | |
539f890d | 16024 | int reg; |
b9733481 L |
16025 | const char **names; |
16026 | ||
c0f3af97 L |
16027 | if (!need_vex) |
16028 | abort (); | |
16029 | ||
16030 | if (!need_vex_reg) | |
16031 | return; | |
16032 | ||
539f890d | 16033 | reg = vex.register_specifier; |
43234a1e L |
16034 | if (vex.evex) |
16035 | { | |
16036 | if (!vex.v) | |
16037 | reg += 16; | |
16038 | } | |
16039 | ||
539f890d L |
16040 | if (bytemode == vex_scalar_mode) |
16041 | { | |
16042 | oappend (names_xmm[reg]); | |
16043 | return; | |
16044 | } | |
16045 | ||
c0f3af97 L |
16046 | switch (vex.length) |
16047 | { | |
16048 | case 128: | |
16049 | switch (bytemode) | |
16050 | { | |
16051 | case vex_mode: | |
16052 | case vex128_mode: | |
6c30d220 | 16053 | case vex_vsib_q_w_dq_mode: |
cb21baef L |
16054 | names = names_xmm; |
16055 | break; | |
16056 | case dq_mode: | |
16057 | if (vex.w) | |
16058 | names = names64; | |
16059 | else | |
16060 | names = names32; | |
c0f3af97 | 16061 | break; |
43234a1e L |
16062 | case mask_mode: |
16063 | names = names_mask; | |
16064 | break; | |
c0f3af97 L |
16065 | default: |
16066 | abort (); | |
16067 | return; | |
16068 | } | |
c0f3af97 L |
16069 | break; |
16070 | case 256: | |
16071 | switch (bytemode) | |
16072 | { | |
16073 | case vex_mode: | |
16074 | case vex256_mode: | |
6c30d220 L |
16075 | names = names_ymm; |
16076 | break; | |
16077 | case vex_vsib_q_w_dq_mode: | |
16078 | names = vex.w ? names_ymm : names_xmm; | |
c0f3af97 | 16079 | break; |
43234a1e L |
16080 | case mask_mode: |
16081 | names = names_mask; | |
16082 | break; | |
c0f3af97 L |
16083 | default: |
16084 | abort (); | |
16085 | return; | |
16086 | } | |
c0f3af97 | 16087 | break; |
43234a1e L |
16088 | case 512: |
16089 | names = names_zmm; | |
16090 | break; | |
c0f3af97 L |
16091 | default: |
16092 | abort (); | |
16093 | break; | |
16094 | } | |
539f890d | 16095 | oappend (names[reg]); |
c0f3af97 L |
16096 | } |
16097 | ||
922d8de8 DR |
16098 | /* Get the VEX immediate byte without moving codep. */ |
16099 | ||
16100 | static unsigned char | |
ccc5981b | 16101 | get_vex_imm8 (int sizeflag, int opnum) |
922d8de8 DR |
16102 | { |
16103 | int bytes_before_imm = 0; | |
16104 | ||
922d8de8 DR |
16105 | if (modrm.mod != 3) |
16106 | { | |
16107 | /* There are SIB/displacement bytes. */ | |
16108 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) | |
6c067bbb | 16109 | { |
922d8de8 | 16110 | /* 32/64 bit address mode */ |
6c067bbb | 16111 | int base = modrm.rm; |
922d8de8 DR |
16112 | |
16113 | /* Check SIB byte. */ | |
6c067bbb RM |
16114 | if (base == 4) |
16115 | { | |
16116 | FETCH_DATA (the_info, codep + 1); | |
16117 | base = *codep & 7; | |
16118 | /* When decoding the third source, don't increase | |
16119 | bytes_before_imm as this has already been incremented | |
16120 | by one in OP_E_memory while decoding the second | |
16121 | source operand. */ | |
16122 | if (opnum == 0) | |
16123 | bytes_before_imm++; | |
16124 | } | |
16125 | ||
16126 | /* Don't increase bytes_before_imm when decoding the third source, | |
16127 | it has already been incremented by OP_E_memory while decoding | |
16128 | the second source operand. */ | |
16129 | if (opnum == 0) | |
16130 | { | |
16131 | switch (modrm.mod) | |
16132 | { | |
16133 | case 0: | |
16134 | /* When modrm.rm == 5 or modrm.rm == 4 and base in | |
16135 | SIB == 5, there is a 4 byte displacement. */ | |
16136 | if (base != 5) | |
16137 | /* No displacement. */ | |
16138 | break; | |
16139 | case 2: | |
16140 | /* 4 byte displacement. */ | |
16141 | bytes_before_imm += 4; | |
16142 | break; | |
16143 | case 1: | |
16144 | /* 1 byte displacement. */ | |
16145 | bytes_before_imm++; | |
16146 | break; | |
16147 | } | |
16148 | } | |
16149 | } | |
922d8de8 | 16150 | else |
02e647f9 SP |
16151 | { |
16152 | /* 16 bit address mode */ | |
6c067bbb RM |
16153 | /* Don't increase bytes_before_imm when decoding the third source, |
16154 | it has already been incremented by OP_E_memory while decoding | |
16155 | the second source operand. */ | |
16156 | if (opnum == 0) | |
16157 | { | |
02e647f9 SP |
16158 | switch (modrm.mod) |
16159 | { | |
16160 | case 0: | |
16161 | /* When modrm.rm == 6, there is a 2 byte displacement. */ | |
16162 | if (modrm.rm != 6) | |
16163 | /* No displacement. */ | |
16164 | break; | |
16165 | case 2: | |
16166 | /* 2 byte displacement. */ | |
16167 | bytes_before_imm += 2; | |
16168 | break; | |
16169 | case 1: | |
16170 | /* 1 byte displacement: when decoding the third source, | |
16171 | don't increase bytes_before_imm as this has already | |
16172 | been incremented by one in OP_E_memory while decoding | |
16173 | the second source operand. */ | |
16174 | if (opnum == 0) | |
16175 | bytes_before_imm++; | |
ccc5981b | 16176 | |
02e647f9 SP |
16177 | break; |
16178 | } | |
922d8de8 DR |
16179 | } |
16180 | } | |
16181 | } | |
16182 | ||
16183 | FETCH_DATA (the_info, codep + bytes_before_imm + 1); | |
16184 | return codep [bytes_before_imm]; | |
16185 | } | |
16186 | ||
16187 | static void | |
16188 | OP_EX_VexReg (int bytemode, int sizeflag, int reg) | |
16189 | { | |
b9733481 L |
16190 | const char **names; |
16191 | ||
922d8de8 DR |
16192 | if (reg == -1 && modrm.mod != 3) |
16193 | { | |
16194 | OP_E_memory (bytemode, sizeflag); | |
16195 | return; | |
16196 | } | |
16197 | else | |
16198 | { | |
16199 | if (reg == -1) | |
16200 | { | |
16201 | reg = modrm.rm; | |
16202 | USED_REX (REX_B); | |
16203 | if (rex & REX_B) | |
16204 | reg += 8; | |
16205 | } | |
16206 | else if (reg > 7 && address_mode != mode_64bit) | |
16207 | BadOp (); | |
16208 | } | |
16209 | ||
16210 | switch (vex.length) | |
16211 | { | |
16212 | case 128: | |
b9733481 | 16213 | names = names_xmm; |
922d8de8 DR |
16214 | break; |
16215 | case 256: | |
b9733481 | 16216 | names = names_ymm; |
922d8de8 DR |
16217 | break; |
16218 | default: | |
16219 | abort (); | |
16220 | } | |
b9733481 | 16221 | oappend (names[reg]); |
922d8de8 DR |
16222 | } |
16223 | ||
a683cc34 SP |
16224 | static void |
16225 | OP_EX_VexImmW (int bytemode, int sizeflag) | |
16226 | { | |
16227 | int reg = -1; | |
16228 | static unsigned char vex_imm8; | |
16229 | ||
16230 | if (vex_w_done == 0) | |
16231 | { | |
16232 | vex_w_done = 1; | |
16233 | ||
16234 | /* Skip mod/rm byte. */ | |
16235 | MODRM_CHECK; | |
16236 | codep++; | |
16237 | ||
16238 | vex_imm8 = get_vex_imm8 (sizeflag, 0); | |
16239 | ||
16240 | if (vex.w) | |
16241 | reg = vex_imm8 >> 4; | |
16242 | ||
16243 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
16244 | } | |
16245 | else if (vex_w_done == 1) | |
16246 | { | |
16247 | vex_w_done = 2; | |
16248 | ||
16249 | if (!vex.w) | |
16250 | reg = vex_imm8 >> 4; | |
16251 | ||
16252 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
16253 | } | |
16254 | else | |
16255 | { | |
16256 | /* Output the imm8 directly. */ | |
16257 | scratchbuf[0] = '$'; | |
16258 | print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf); | |
9ce09ba2 | 16259 | oappend_maybe_intel (scratchbuf); |
a683cc34 SP |
16260 | scratchbuf[0] = '\0'; |
16261 | codep++; | |
16262 | } | |
16263 | } | |
16264 | ||
5dd85c99 SP |
16265 | static void |
16266 | OP_Vex_2src (int bytemode, int sizeflag) | |
16267 | { | |
16268 | if (modrm.mod == 3) | |
16269 | { | |
b9733481 | 16270 | int reg = modrm.rm; |
5dd85c99 | 16271 | USED_REX (REX_B); |
b9733481 L |
16272 | if (rex & REX_B) |
16273 | reg += 8; | |
16274 | oappend (names_xmm[reg]); | |
5dd85c99 SP |
16275 | } |
16276 | else | |
16277 | { | |
16278 | if (intel_syntax | |
16279 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
16280 | { | |
16281 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
16282 | used_prefixes |= (prefixes & PREFIX_DATA); | |
16283 | } | |
16284 | OP_E (bytemode, sizeflag); | |
16285 | } | |
16286 | } | |
16287 | ||
16288 | static void | |
16289 | OP_Vex_2src_1 (int bytemode, int sizeflag) | |
16290 | { | |
16291 | if (modrm.mod == 3) | |
16292 | { | |
16293 | /* Skip mod/rm byte. */ | |
16294 | MODRM_CHECK; | |
16295 | codep++; | |
16296 | } | |
16297 | ||
16298 | if (vex.w) | |
b9733481 | 16299 | oappend (names_xmm[vex.register_specifier]); |
5dd85c99 SP |
16300 | else |
16301 | OP_Vex_2src (bytemode, sizeflag); | |
16302 | } | |
16303 | ||
16304 | static void | |
16305 | OP_Vex_2src_2 (int bytemode, int sizeflag) | |
16306 | { | |
16307 | if (vex.w) | |
16308 | OP_Vex_2src (bytemode, sizeflag); | |
16309 | else | |
b9733481 | 16310 | oappend (names_xmm[vex.register_specifier]); |
5dd85c99 SP |
16311 | } |
16312 | ||
922d8de8 DR |
16313 | static void |
16314 | OP_EX_VexW (int bytemode, int sizeflag) | |
16315 | { | |
16316 | int reg = -1; | |
16317 | ||
16318 | if (!vex_w_done) | |
16319 | { | |
16320 | vex_w_done = 1; | |
41effecb SP |
16321 | |
16322 | /* Skip mod/rm byte. */ | |
16323 | MODRM_CHECK; | |
16324 | codep++; | |
16325 | ||
922d8de8 | 16326 | if (vex.w) |
ccc5981b | 16327 | reg = get_vex_imm8 (sizeflag, 0) >> 4; |
922d8de8 DR |
16328 | } |
16329 | else | |
16330 | { | |
16331 | if (!vex.w) | |
ccc5981b | 16332 | reg = get_vex_imm8 (sizeflag, 1) >> 4; |
922d8de8 DR |
16333 | } |
16334 | ||
16335 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
16336 | } | |
16337 | ||
922d8de8 DR |
16338 | static void |
16339 | VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16340 | int sizeflag ATTRIBUTE_UNUSED) | |
16341 | { | |
16342 | /* Skip the immediate byte and check for invalid bits. */ | |
16343 | FETCH_DATA (the_info, codep + 1); | |
16344 | if (*codep++ & 0xf) | |
16345 | BadOp (); | |
16346 | } | |
16347 | ||
c0f3af97 L |
16348 | static void |
16349 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16350 | { | |
16351 | int reg; | |
b9733481 L |
16352 | const char **names; |
16353 | ||
c0f3af97 L |
16354 | FETCH_DATA (the_info, codep + 1); |
16355 | reg = *codep++; | |
16356 | ||
16357 | if (bytemode != x_mode) | |
16358 | abort (); | |
16359 | ||
16360 | if (reg & 0xf) | |
16361 | BadOp (); | |
16362 | ||
16363 | reg >>= 4; | |
dae39acc L |
16364 | if (reg > 7 && address_mode != mode_64bit) |
16365 | BadOp (); | |
16366 | ||
c0f3af97 L |
16367 | switch (vex.length) |
16368 | { | |
16369 | case 128: | |
b9733481 | 16370 | names = names_xmm; |
c0f3af97 L |
16371 | break; |
16372 | case 256: | |
b9733481 | 16373 | names = names_ymm; |
c0f3af97 L |
16374 | break; |
16375 | default: | |
16376 | abort (); | |
16377 | } | |
b9733481 | 16378 | oappend (names[reg]); |
c0f3af97 L |
16379 | } |
16380 | ||
922d8de8 DR |
16381 | static void |
16382 | OP_XMM_VexW (int bytemode, int sizeflag) | |
16383 | { | |
16384 | /* Turn off the REX.W bit since it is used for swapping operands | |
16385 | now. */ | |
16386 | rex &= ~REX_W; | |
16387 | OP_XMM (bytemode, sizeflag); | |
16388 | } | |
16389 | ||
c0f3af97 L |
16390 | static void |
16391 | OP_EX_Vex (int bytemode, int sizeflag) | |
16392 | { | |
16393 | if (modrm.mod != 3) | |
16394 | { | |
16395 | if (vex.register_specifier != 0) | |
16396 | BadOp (); | |
16397 | need_vex_reg = 0; | |
16398 | } | |
16399 | OP_EX (bytemode, sizeflag); | |
16400 | } | |
16401 | ||
16402 | static void | |
16403 | OP_XMM_Vex (int bytemode, int sizeflag) | |
16404 | { | |
16405 | if (modrm.mod != 3) | |
16406 | { | |
16407 | if (vex.register_specifier != 0) | |
16408 | BadOp (); | |
16409 | need_vex_reg = 0; | |
16410 | } | |
16411 | OP_XMM (bytemode, sizeflag); | |
16412 | } | |
16413 | ||
16414 | static void | |
16415 | VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16416 | { | |
16417 | switch (vex.length) | |
16418 | { | |
16419 | case 128: | |
ea397f5b | 16420 | mnemonicendp = stpcpy (obuf, "vzeroupper"); |
c0f3af97 L |
16421 | break; |
16422 | case 256: | |
ea397f5b | 16423 | mnemonicendp = stpcpy (obuf, "vzeroall"); |
c0f3af97 L |
16424 | break; |
16425 | default: | |
16426 | abort (); | |
16427 | } | |
16428 | } | |
16429 | ||
ea397f5b L |
16430 | static struct op vex_cmp_op[] = |
16431 | { | |
16432 | { STRING_COMMA_LEN ("eq") }, | |
16433 | { STRING_COMMA_LEN ("lt") }, | |
16434 | { STRING_COMMA_LEN ("le") }, | |
16435 | { STRING_COMMA_LEN ("unord") }, | |
16436 | { STRING_COMMA_LEN ("neq") }, | |
16437 | { STRING_COMMA_LEN ("nlt") }, | |
16438 | { STRING_COMMA_LEN ("nle") }, | |
16439 | { STRING_COMMA_LEN ("ord") }, | |
16440 | { STRING_COMMA_LEN ("eq_uq") }, | |
16441 | { STRING_COMMA_LEN ("nge") }, | |
16442 | { STRING_COMMA_LEN ("ngt") }, | |
16443 | { STRING_COMMA_LEN ("false") }, | |
16444 | { STRING_COMMA_LEN ("neq_oq") }, | |
16445 | { STRING_COMMA_LEN ("ge") }, | |
16446 | { STRING_COMMA_LEN ("gt") }, | |
16447 | { STRING_COMMA_LEN ("true") }, | |
16448 | { STRING_COMMA_LEN ("eq_os") }, | |
16449 | { STRING_COMMA_LEN ("lt_oq") }, | |
16450 | { STRING_COMMA_LEN ("le_oq") }, | |
16451 | { STRING_COMMA_LEN ("unord_s") }, | |
16452 | { STRING_COMMA_LEN ("neq_us") }, | |
16453 | { STRING_COMMA_LEN ("nlt_uq") }, | |
16454 | { STRING_COMMA_LEN ("nle_uq") }, | |
16455 | { STRING_COMMA_LEN ("ord_s") }, | |
16456 | { STRING_COMMA_LEN ("eq_us") }, | |
16457 | { STRING_COMMA_LEN ("nge_uq") }, | |
16458 | { STRING_COMMA_LEN ("ngt_uq") }, | |
16459 | { STRING_COMMA_LEN ("false_os") }, | |
16460 | { STRING_COMMA_LEN ("neq_os") }, | |
16461 | { STRING_COMMA_LEN ("ge_oq") }, | |
16462 | { STRING_COMMA_LEN ("gt_oq") }, | |
16463 | { STRING_COMMA_LEN ("true_us") }, | |
c0f3af97 L |
16464 | }; |
16465 | ||
16466 | static void | |
16467 | VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16468 | { | |
16469 | unsigned int cmp_type; | |
16470 | ||
16471 | FETCH_DATA (the_info, codep + 1); | |
16472 | cmp_type = *codep++ & 0xff; | |
16473 | if (cmp_type < ARRAY_SIZE (vex_cmp_op)) | |
16474 | { | |
16475 | char suffix [3]; | |
ea397f5b | 16476 | char *p = mnemonicendp - 2; |
c0f3af97 L |
16477 | suffix[0] = p[0]; |
16478 | suffix[1] = p[1]; | |
16479 | suffix[2] = '\0'; | |
ea397f5b L |
16480 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); |
16481 | mnemonicendp += vex_cmp_op[cmp_type].len; | |
c0f3af97 L |
16482 | } |
16483 | else | |
16484 | { | |
16485 | /* We have a reserved extension byte. Output it directly. */ | |
16486 | scratchbuf[0] = '$'; | |
16487 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16488 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
16489 | scratchbuf[0] = '\0'; |
16490 | } | |
16491 | } | |
16492 | ||
43234a1e L |
16493 | static void |
16494 | VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16495 | int sizeflag ATTRIBUTE_UNUSED) | |
16496 | { | |
16497 | unsigned int cmp_type; | |
16498 | ||
16499 | if (!vex.evex) | |
16500 | abort (); | |
16501 | ||
16502 | FETCH_DATA (the_info, codep + 1); | |
16503 | cmp_type = *codep++ & 0xff; | |
16504 | /* There are aliases for immediates 0, 1, 2, 4, 5, 6. | |
16505 | If it's the case, print suffix, otherwise - print the immediate. */ | |
16506 | if (cmp_type < ARRAY_SIZE (simd_cmp_op) | |
16507 | && cmp_type != 3 | |
16508 | && cmp_type != 7) | |
16509 | { | |
16510 | char suffix [3]; | |
16511 | char *p = mnemonicendp - 2; | |
16512 | ||
16513 | /* vpcmp* can have both one- and two-lettered suffix. */ | |
16514 | if (p[0] == 'p') | |
16515 | { | |
16516 | p++; | |
16517 | suffix[0] = p[0]; | |
16518 | suffix[1] = '\0'; | |
16519 | } | |
16520 | else | |
16521 | { | |
16522 | suffix[0] = p[0]; | |
16523 | suffix[1] = p[1]; | |
16524 | suffix[2] = '\0'; | |
16525 | } | |
16526 | ||
16527 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); | |
16528 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
16529 | } | |
16530 | else | |
16531 | { | |
16532 | /* We have a reserved extension byte. Output it directly. */ | |
16533 | scratchbuf[0] = '$'; | |
16534 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16535 | oappend_maybe_intel (scratchbuf); |
43234a1e L |
16536 | scratchbuf[0] = '\0'; |
16537 | } | |
16538 | } | |
16539 | ||
ea397f5b L |
16540 | static const struct op pclmul_op[] = |
16541 | { | |
16542 | { STRING_COMMA_LEN ("lql") }, | |
16543 | { STRING_COMMA_LEN ("hql") }, | |
16544 | { STRING_COMMA_LEN ("lqh") }, | |
16545 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
16546 | }; |
16547 | ||
16548 | static void | |
16549 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16550 | int sizeflag ATTRIBUTE_UNUSED) | |
16551 | { | |
16552 | unsigned int pclmul_type; | |
16553 | ||
16554 | FETCH_DATA (the_info, codep + 1); | |
16555 | pclmul_type = *codep++ & 0xff; | |
16556 | switch (pclmul_type) | |
16557 | { | |
16558 | case 0x10: | |
16559 | pclmul_type = 2; | |
16560 | break; | |
16561 | case 0x11: | |
16562 | pclmul_type = 3; | |
16563 | break; | |
16564 | default: | |
16565 | break; | |
7bb15c6f | 16566 | } |
c0f3af97 L |
16567 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
16568 | { | |
16569 | char suffix [4]; | |
ea397f5b | 16570 | char *p = mnemonicendp - 3; |
c0f3af97 L |
16571 | suffix[0] = p[0]; |
16572 | suffix[1] = p[1]; | |
16573 | suffix[2] = p[2]; | |
16574 | suffix[3] = '\0'; | |
ea397f5b L |
16575 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
16576 | mnemonicendp += pclmul_op[pclmul_type].len; | |
c0f3af97 L |
16577 | } |
16578 | else | |
16579 | { | |
16580 | /* We have a reserved extension byte. Output it directly. */ | |
16581 | scratchbuf[0] = '$'; | |
16582 | print_operand_value (scratchbuf + 1, 1, pclmul_type); | |
9ce09ba2 | 16583 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
16584 | scratchbuf[0] = '\0'; |
16585 | } | |
16586 | } | |
16587 | ||
f1f8f695 L |
16588 | static void |
16589 | MOVBE_Fixup (int bytemode, int sizeflag) | |
16590 | { | |
16591 | /* Add proper suffix to "movbe". */ | |
ea397f5b | 16592 | char *p = mnemonicendp; |
f1f8f695 L |
16593 | |
16594 | switch (bytemode) | |
16595 | { | |
16596 | case v_mode: | |
16597 | if (intel_syntax) | |
ea397f5b | 16598 | goto skip; |
f1f8f695 L |
16599 | |
16600 | USED_REX (REX_W); | |
16601 | if (sizeflag & SUFFIX_ALWAYS) | |
16602 | { | |
16603 | if (rex & REX_W) | |
16604 | *p++ = 'q'; | |
f1f8f695 | 16605 | else |
f16cd0d5 L |
16606 | { |
16607 | if (sizeflag & DFLAG) | |
16608 | *p++ = 'l'; | |
16609 | else | |
16610 | *p++ = 'w'; | |
16611 | used_prefixes |= (prefixes & PREFIX_DATA); | |
16612 | } | |
f1f8f695 | 16613 | } |
f1f8f695 L |
16614 | break; |
16615 | default: | |
16616 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16617 | break; | |
16618 | } | |
ea397f5b | 16619 | mnemonicendp = p; |
f1f8f695 L |
16620 | *p = '\0'; |
16621 | ||
ea397f5b | 16622 | skip: |
f1f8f695 L |
16623 | OP_M (bytemode, sizeflag); |
16624 | } | |
f88c9eb0 SP |
16625 | |
16626 | static void | |
16627 | OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16628 | { | |
16629 | int reg; | |
16630 | const char **names; | |
16631 | ||
16632 | /* Skip mod/rm byte. */ | |
16633 | MODRM_CHECK; | |
16634 | codep++; | |
16635 | ||
16636 | if (vex.w) | |
16637 | names = names64; | |
f88c9eb0 | 16638 | else |
ce7d077e | 16639 | names = names32; |
f88c9eb0 SP |
16640 | |
16641 | reg = modrm.rm; | |
16642 | USED_REX (REX_B); | |
16643 | if (rex & REX_B) | |
16644 | reg += 8; | |
16645 | ||
16646 | oappend (names[reg]); | |
16647 | } | |
16648 | ||
16649 | static void | |
16650 | OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16651 | { | |
16652 | const char **names; | |
16653 | ||
16654 | if (vex.w) | |
16655 | names = names64; | |
f88c9eb0 | 16656 | else |
ce7d077e | 16657 | names = names32; |
f88c9eb0 SP |
16658 | |
16659 | oappend (names[vex.register_specifier]); | |
16660 | } | |
43234a1e L |
16661 | |
16662 | static void | |
16663 | OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16664 | { | |
16665 | if (!vex.evex | |
16666 | || bytemode != mask_mode) | |
16667 | abort (); | |
16668 | ||
16669 | USED_REX (REX_R); | |
16670 | if ((rex & REX_R) != 0 || !vex.r) | |
16671 | { | |
16672 | BadOp (); | |
16673 | return; | |
16674 | } | |
16675 | ||
16676 | oappend (names_mask [modrm.reg]); | |
16677 | } | |
16678 | ||
16679 | static void | |
16680 | OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16681 | { | |
16682 | if (!vex.evex | |
16683 | || (bytemode != evex_rounding_mode | |
16684 | && bytemode != evex_sae_mode)) | |
16685 | abort (); | |
16686 | if (modrm.mod == 3 && vex.b) | |
16687 | switch (bytemode) | |
16688 | { | |
16689 | case evex_rounding_mode: | |
16690 | oappend (names_rounding[vex.ll]); | |
16691 | break; | |
16692 | case evex_sae_mode: | |
16693 | oappend ("{sae}"); | |
16694 | break; | |
16695 | default: | |
16696 | break; | |
16697 | } | |
16698 | } |